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1537
Inc/HwA_adc.h Normal file
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/**
* @file HwA_aontimer.h
* @author Flagchip
* @brief FC7xxx aontimer hardware access layer
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip076 N/A First version for FC7240
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_AONTIMER_H_
#define HWA_INCLUDE_HWA_AONTIMER_H_
#include "device_header.h"
/**
* @addtogroup HwA_AONTIMER
* @{
*
*/
/********* Local typedef ************/
/**
* @brief The clock source of the pulse mode
*
*/
typedef enum
{
AONTIMER_CLK0_PIN = 0, /*!< select the Aontimer_clk0 pin as pulse sourse*/
AONTIMER_CLK1_PIN, /*!< select the Aontimer_clk1 pin as pulse sourse*/
AONTIMER_CLK2_PIN, /*!< select the Aontimer_clk2 pin as pulse sourse*/
AONTIMER_TRGSEL_OUTPUT, /*!< select the tresel as pulse sourse*/
} AONTIMER_PulseClkSrcType;
/**
* @brief Aontimer clock source, please refer to Reference Manual chapter8.Aontimer for details.
*
* */
typedef enum
{
AONTIMER_SIRC_1MHZ = 0U, /*!< AONTIMER SIRC 1mhz clock */
AONTIMER_RTC_CLK = 2U, /*!< AONTIMER RTC clock */
AONTIMER_IRC_CLK = 3U /*!< AONTIMER internal clock, which comes from PCC */
} AONTIMER_ClkSrcType;
/**
* @brief The polarity of pulse mode
*
* */
typedef enum
{
AONTIMER_PulsePolarityType_HIGH = 0, /*!< select the high polarity */
AONTIMER_PulsePolarityType_LOW /*!< select the low polarity */
} AONTIMER_PulsePolarityType;
/********* Local inline function ************/
/**
* @brief Configure AONTIMER module
*
* @param u32RegValue CSR register value
*/
LOCAL_INLINE void AONTIMER_HWA_ConfigModule(uint32_t u32RegValue)
{
AONTIMER->CSR = u32RegValue;
}
/**
* @brief Configure AONTIMER module prescale
*
* @param u32RegValue PSR register value
*/
LOCAL_INLINE void AONTIMER_HWA_ConfigModulePrescale(uint32_t u32RegValue)
{
AONTIMER->PSR = u32RegValue;
}
/**
* @brief Set AONTIMER compare value
*
* @param u32RegValue CMR register value
*/
LOCAL_INLINE void AONTIMER_HWA_SetModuleCompareValue(uint32_t u32RegValue)
{
AONTIMER->CMR = u32RegValue;
}
/**
* @brief Set AONTIMER current counter value
*
* @param u32RegValue CNR register value
*/
LOCAL_INLINE void AONTIMER_HWA_SetModuleCounterValue(uint32_t u32RegValue)
{
AONTIMER->CNR = u32RegValue;
}
/**
* @brief Set AONTIMER module running on debug mode
*
*/
LOCAL_INLINE void AONTIMER_HWA_SetModuleRunOnDebug(void)
{
AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_DBGEN_MASK;
}
/**
* @brief Enable AONTIMER module interrupt
*
*/
LOCAL_INLINE void AONTIMER_HWA_EnableModuleInterrupt(void)
{
AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TIE_MASK;
}
/**
* @brief Select AONTIMER module external clock source when timer configured to pulse mode
*
* @param eClk Input counter clock source
*/
LOCAL_INLINE void AONTIMER_HWA_SelectClkSrcOnPulseMode(AONTIMER_PulseClkSrcType eClk)
{
uint32_t u32RegValue = AONTIMER->CSR;
AONTIMER->CSR |= (u32RegValue & ~(uint32_t)AONTIMER_CSR_TPS_MASK) | AONTIMER_CSR_TPS(eClk);
}
/**
* @brief Clear AONTIMER interrupt flags
*
*/
LOCAL_INLINE void AONTIMER_HWA_ClearInterruptFlag(void)
{
AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TCF_MASK;
}
/**
* @brief Set AONTIMER module polarity. Pulse counter input source is active-low, and the CNR increments on falling-edge.
*
*/
LOCAL_INLINE void AONTIMER_HWA_SetModulePolarity(void)
{
AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TPP_MASK;
}
/**
* @brief Configure AONTIMER module polarity. If ePol is 0:Pulse counter input source is active-high, and the CNR increments on rising-edge.
* If ePol is 1:Pulse counter input source is active-low, and the CNR increments on falling-edge.
*
* @param ePol Polarity enumeration
*/
LOCAL_INLINE void AONTIMER_HWA_ConfigModulePolarity(AONTIMER_PulsePolarityType ePol)
{
AONTIMER->CSR |= AONTIMER_CSR_TPP(ePol);
}
/**
* @brief Enable AONTIMER module pulse mode
*
*/
LOCAL_INLINE void AONTIMER_HWA_EnablePulseMode(void)
{
AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TMS_MASK;
}
/**
* @brief Enable AONTIMER timer
*
*/
LOCAL_INLINE void AONTIMER_HWA_EnableTimer(void)
{
AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TEN_MASK;
}
/**
* @brief Set AONTIMER prescale
*
* @param u8PrescalerValue Prescaler value,the range of the input value is :0~15, and the range of prescaler is :2^1 ~ 2^16.
*/
LOCAL_INLINE void AONTIMER_HWA_SetPrescale(uint8_t u8PrescalerValue)
{
uint32_t u32RegValue = AONTIMER->PSR;
AONTIMER->PSR = ((u32RegValue & ~(uint32_t)AONTIMER_PSR_PRESCALE_MASK) | AONTIMER_PSR_PRESCALE(u8PrescalerValue));
}
/**
* @brief If enable bypass mode, the timer will bypass the prescaler in timer counter mode or glitch filter in pulse mode
*
*/
LOCAL_INLINE void AONTIMER_HWA_EnableBypassMode(void)
{
AONTIMER->PSR |= (uint32_t)AONTIMER_PSR_PBYP_MASK;
}
/**
* @brief Select AONTIMER mdoule clock source
*
* @param eClk Aontimer clock source
*/
LOCAL_INLINE void AONTIMER_HWA_SelectModuleClkSrc(AONTIMER_ClkSrcType eClk)
{
uint32_t u32RegValue = AONTIMER->PSR;
AONTIMER->PSR = ((u32RegValue & ~(uint32_t)AONTIMER_PSR_PCS_MASK) | AONTIMER_PSR_PCS(eClk));
}
/**
* @brief Set AONTIMER module stop on debug mode
*
*/
LOCAL_INLINE void AONTIMER_HWA_SetModuleStopOnDebug(void)
{
AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_DBGEN_MASK;
}
/**
* @brief Disable AONTIMER module interrupt
*
*/
LOCAL_INLINE void AONTIMER_HWA_DisableModuleInterrupt(void)
{
AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TIE_MASK;
}
/**
* @brief Clear AONTIMER module mode
*
*/
LOCAL_INLINE void AONTIMER_HWA_ClearModuleMode(void)
{
AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TPS_MASK;
}
/**
* @brief Clear AONTIMER module polarity. Pulse counter input source is active-high, and the CNR increments on rising-edge.
*
*/
LOCAL_INLINE void AONTIMER_HWA_ClearModulePolarity(void)
{
AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TPP_MASK;
}
/**
* @brief Disable AONTIEMR module pulse mode
*
*/
LOCAL_INLINE void AONTIMER_HWA_DisablePulseMode(void)
{
AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TMS_MASK;
}
/**
* @brief Disable AONTIMER module timer
*
*/
LOCAL_INLINE void AONTIMER_HWA_DisableTimer(void)
{
AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TEN_MASK;
}
/**
* @brief Clear AONTIMER module prescaler
*
*/
LOCAL_INLINE void AONTIMER_HWA_ClearPrescale(void)
{
AONTIMER->PSR &= ~(uint32_t)AONTIMER_PSR_PRESCALE_MASK;
}
/**
* @brief If disable bypass mode, the timer will enable the prescaler in timer counter mode or glitch filter in pulse mode
*
*/
LOCAL_INLINE void AONTIMER_HWA_DisableBypassMode(void)
{
AONTIMER->PSR &= ~(uint32_t)AONTIMER_PSR_PBYP_MASK;
}
/**
* @brief Clear AONTIMER module clock source
*
*/
LOCAL_INLINE void AONTIMER_HWA_ClearModuleClkSrc(void)
{
AONTIMER->PSR &= ~(uint32_t)AONTIMER_PSR_PCS_MASK;
}
/** @}*/ /* HwA_AONTIMER */
#endif /* HWA_INCLUDE_HWA_AONTIMER_H_ */

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/**
* @file HwA_cm7.h
* @author Flagchip
* @brief FC7xxx cortex m4 hardware access layer
* @version 0.1.0
* @date 2022-11-21
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
#ifndef _HWA_CM7_H_
#define _HWA_CM7_H_
#include "device_header.h"
/**
* @brief Enable deepsleep mode
*
*/
LOCAL_INLINE void CM7_HWA_EnableDeepSleep(void)
{
SCB->SCR |= (uint32_t)SCB_SCR_SLEEPDEEP_Msk;
}
/**
* @brief Disable deepsleep mode
*
*/
LOCAL_INLINE void CM7_HWA_DisableDeepSleep(void)
{
SCB->SCR &= ~(uint32_t)SCB_SCR_SLEEPDEEP_Msk;
}
#endif /* #ifndef _HWA_CM7_H_ */

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/**
* @file HwA_cmp.h
* @author Flagchip0126
* @brief FC7xxx CMP driver type definition and API
* @version 0.1.0
* @date 2024-01-15
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_CMP_H_
#define _HWA_CMP_H_
#include "device_header.h"
/********* Local typedef ************/
/**
* @brief The CMP complete DMA callback function prototype
*
*/
/**
* @brief The instance index of the CMP mode
*/
typedef enum
{
CMP_MOD_DISABLE = 0U, /*!< CMP function mode is disable */
CMP_MOD_CONTINUOUS = 1U, /*!< CMP function mode is continuous */
CMP_MOD_SAMPLE_NONFILTER_EXTCLK = 2U, /*!< CMP function mode is sampled,non-filtered mode 1*/
CMP_MOD_SAMPLE_NONFILTER_INTCLK = 3U, /*!< CMP function mode is sampled,non-filtered mode 2*/
CMP_MOD_SAMPLE_FILTER_EXTCLK = 4U, /*!< CMP function mode is sampled,filtered mode 1*/
CMP_MOD_SAMPLE_FILTER_INTCLK = 5U, /*!< CMP function mode is sampled,filtered mode 2*/
CMP_MOD_WINDOW = 6U, /*!< CMP function mode is windowed mode */
CMP_MOD_WINDOW_RESAMPLE = 7U, /*!< CMP function mode is windowed,re-sampled mode */
CMP_MOD_WINDOW_FILTER = 8U, /*!< CMP function mode is windowed,filtered mode */
CMP_MOD_CHANNEL_SCAN = 9U /*!< CMP channel scan mode */
} CMP_ModSelType;
/**
* @brief The instance index of the CMP peripheral
*/
typedef enum
{
CMP_INSTANCE_0 = 0U, /*!< CMP instance 0 is selected */
CMP_INSTANCE_1 = 1U /*!< CMP instance 1 is selected */
} CMP_InstanceType;
/**
* @brief The instance index of the CMP DAC enable select
*/
typedef enum
{
CMP_DACENABLE_DCR = 0U, /*!< CMP Dac is enabled by DCR[DAC_EN] */
CMP_DACENABLE_CCR0 = 1U /*!< CMP Dac is enabled by CCR0[EN] */
} CMP_DacEnableSrcType;
/**
* @brief The instance index of the CMP output invert
*/
typedef enum
{
CMP_NON_INVERT = 0U, /*!< CMP output do not Invert*/
CMP_INVERT = 1U /*!< CMP output Invert */
} CMP_InvertType;
/**
* @brief The instance index of the CMP output select
*/
typedef enum
{
CMP_FILTEROUT = 0U, /*!< CMP filter output */
CMP_UNFILTEROUT = 1U /*!< CMP Unfilter output */
} CMP_OutSelectType;
/**
* @brief The instance index of the CMP window level
*/
typedef enum
{
CMP_HOLD = 0U, /*!< CMP output hold when window close */
CMP_USERDEF = 1U /*!< CMP output userdefine when window close */
} CMP_OutWinLevelType;
/**
* @brief The instance index of the window output under userdefine CMP window level
*/
typedef enum
{
CMP_OUTWIN_0 = 0U, /*!< CMP window output is 0 */
CMP_OUTWIN_1 = 1U /*!< CMP window output is 1 */
} CMP_OutWinLevel_UserDefType;
/**
* @brief The instance index of the CMP Event caused window close
*/
typedef enum
{
CMP_RISINGEDGE = 0U, /*!< CMP output event RisingEdge causes window close */
CMP_FALLINGEDGE = 1U, /*!< CMP output event FallingEdge causes window close */
CMP_BOTHEDGES = 2U, /*!< CMP output event bothEdges causes window close */
} CMP_EventType;
/**
* @brief The instance index of the CMP filter count numbers
*/
typedef enum
{
CMP_FILTERCNT_0 = 0U, /*!< CMP filter is bypassed */
CMP_FILTERCNT_1 = 1U, /*!< CMP filter is 1 consecutive sample */
CMP_FILTERCNT_2 = 2U, /*!< CMP filter is 2 consecutive sample */
CMP_FILTERCNT_3 = 3U, /*!< CMP filter is 3 consecutive sample */
CMP_FILTERCNT_4 = 4U /*!< CMP filter is 4 consecutive sample */
} CMP_FilterCntType;
/**
* @brief The instance index of the CMP hysteresis control
*/
typedef enum
{
CMP_HYSTCTRL_0 = 0U, /*!< CMP 0 hysteresis internal */
CMP_HYSTCTRL_1 = 1U, /*!< CMP 1 hysteresis internal */
CMP_HYSTCTRL_2 = 2U, /*!< CMP 2 hysteresis internal */
CMP_HYSTCTRL_3 = 3U /*!< CMP 3 hysteresis internal */
} CMP_HystCtrlType;
/**
* @brief The fixed CMP port for reference in channel scan mode
*/
typedef enum
{
CMP_PORTSEL_MUX_POSITIVE = 0U,
CMP_PORTSEL_MUX_NEGATIVE = 1U
} CMP_PortSelType;
/**
* @brief The source of the CMP input
*/
typedef enum
{
CMP_INSRCSEL_DAC = 0U, /*!< CMP input source is DAC */
CMP_INSRCSEL_MUX = 1U /*!< CMP input source is analog 1-8 mux */
} CMP_INSrcSelType;
/**
* @brief The instance index of the CMP input mux
*/
typedef enum
{
CMP_INSEL_MUX_IN0 = 0U, /*!< CMP input mux from IN0(CMP0,CMP1) */
CMP_INSEL_MUX_IN1 = 1U, /*!< CMP input mux from IN1(CMP0,CMP1) */
CMP_INSEL_MUX_IN2 = 2U, /*!< CMP input mux from IN2(CMP0,CMP1) */
CMP_INSEL_MUX_IN3 = 3U, /*!< CMP input mux from IN3(CMP0,CMP1) */
CMP_INSEL_MUX_IN4 = 4U, /*!< CMP input mux from IN4(CMP0,CMP1) */
CMP_INSEL_MUX_IN5 = 5U, /*!< CMP input mux from IN5(CMP0,CMP1) */
CMP_INSEL_MUX_IN6 = 6U, /*!< CMP input mux from IN6(CMP0,CMP1) */
CMP_INSEL_MUX_IN7 = 7U /*!< CMP input mux from IN7(CMP0,CMP1) */
} CMP_MuxSelType;
/**
* @brief The instance index of DAC high voltage reference select
*/
typedef enum
{
CMP_DACVINREF_H0 = 0U, /*!< CMP DAC high voltage input reference vrefh0 */
CMP_DACVINREF_H1 = 1U /*!< CMP DAC high voltage input reference vrefh1 */
} CMP_DacVinRefSelType;
/**
* @brief The instance index of high power mode select
*/
typedef enum
{
CMP_LOWSPEEDMOD = 0U, /*!< CMP low speed mode */
CMP_HIGHSPEEDMOD = 1U /*!< CMP high speed mode */
} CMP_SpeedModSelType;
/**
* @brief Defines CMP out status
*/
typedef enum
{
CMP_OUT_FALLING_EDGE = 0U, /*!< CMP out detect falling edge */
CMP_OUT_RISING_EDGE = 1U, /*!< CMP out detect rising edge */
CMP_OUT_NONE = 2U /*!< CMP out detect none */
} CMP_OutStatus;
/********* Local inline function ************/
/**
* @brief set CMP enable
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_Enable(CMP_Type *const pCmp)
{
uint32_t u32RegVal = pCmp->CCR0;
pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_EN_MASK)) | CMP_CCR0_EN(true));
}
/**
* @brief set CMP disable
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_Disable(CMP_Type *const pCmp)
{
uint32_t u32RegVal = pCmp->CCR0;
pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_EN_MASK)) | CMP_CCR0_EN(false));
}
/**
* @brief set CMP DMA enable
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_DmaEnable(CMP_Type *const pCmp)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_DMA_EN_MASK)) | CMP_CCR1_DMA_EN(true));
}
/**
* @brief set CMP DMA disable
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_DmaDisable(CMP_Type *const pCmp)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_DMA_EN_MASK)) | CMP_CCR1_DMA_EN(false));
}
/**
* @brief set CMP mode
*
* @param pCmp the CMP instance to use
* @param eMod the CMP mode to use
* @param u8FilterPrd the CMP filter period
* @param eFilterCnt the CMP filter sample count
*/
LOCAL_INLINE void CMP_HWA_SetComparatorMod(CMP_Type *const pCmp, CMP_ModSelType eMod, uint8_t u8FilterPrd, CMP_FilterCntType eFilterCnt)
{
switch (eMod)
{
case CMP_MOD_DISABLE:
{
/* Nothing deal with */
}
break;
case CMP_MOD_CONTINUOUS:
{
pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) |
CMP_CCR1_SAMPLE_EN(false);
}
break;
case CMP_MOD_SAMPLE_NONFILTER_EXTCLK:
{
pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) |
CMP_CCR1_SAMPLE_EN(true) |
CMP_CCR1_FILT_CNT(0x01);
}
break;
case CMP_MOD_SAMPLE_NONFILTER_INTCLK:
{
pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) |
CMP_CCR1_SAMPLE_EN(false) |
CMP_CCR1_FILT_CNT(0x01) |
CMP_CCR1_FILT_PER(u8FilterPrd);
}
break;
case CMP_MOD_SAMPLE_FILTER_EXTCLK:
{
pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) |
CMP_CCR1_SAMPLE_EN(true) |
CMP_CCR1_FILT_CNT(u8FilterPrd);
}
break;
case CMP_MOD_SAMPLE_FILTER_INTCLK:
{
pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) |
CMP_CCR1_SAMPLE_EN(false) |
CMP_CCR1_FILT_CNT(eFilterCnt) |
CMP_CCR1_FILT_PER(u8FilterPrd);
}
break;
case CMP_MOD_WINDOW:
{
pCmp->CCR1 |= CMP_CCR1_WIN_EN(true) |
CMP_CCR1_SAMPLE_EN(false) |
CMP_CCR1_FILT_CNT(0x00) |
CMP_CCR1_FILT_PER(0x00);
}
break;
case CMP_MOD_WINDOW_RESAMPLE:
{
pCmp->CCR1 |= CMP_CCR1_WIN_EN(true) |
CMP_CCR1_SAMPLE_EN(false) |
CMP_CCR1_FILT_CNT(0x01) |
CMP_CCR1_FILT_PER(u8FilterPrd);
}
break;
case CMP_MOD_WINDOW_FILTER:
{
pCmp->CCR1 |= CMP_CCR1_WIN_EN(true) |
CMP_CCR1_SAMPLE_EN(false) |
CMP_CCR1_FILT_CNT(eFilterCnt) |
CMP_CCR1_FILT_PER(u8FilterPrd);
}
break;
case CMP_MOD_CHANNEL_SCAN:
{
pCmp->CSCR0 |= CMP_CSCR0_CS_EN(true) ;
}
break;
default:
break;
}
}
/**
* @brief STOP mode enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetEnStopMod(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CCR0;
pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_STOP_EN_MASK)) | CMP_CCR0_STOP_EN(bEnable));
}
/**
* @brief set DAC enable selection
*
* @param pCmp the CMP instance to use
* @param eType Dac enable source
*/
LOCAL_INLINE void CMP_HWA_SetDacEnableSrc(CMP_Type *const pCmp, CMP_DacEnableSrcType eType)
{
uint32_t u32RegVal = pCmp->CCR0;
pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_DACEN_SEL_MASK)) | CMP_CCR0_DACEN_SEL(eType));
}
/**
* @brief set CPM output invert
*
* @param pCmp the CMP instance to use
* @param eType CPM output invert type
*/
LOCAL_INLINE void CMP_HWA_SetCmpOutInvert(CMP_Type *const pCmp, CMP_InvertType eType)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_INV_MASK)) | CMP_CCR1_CMPOUT_INV(eType));
}
/**
* @brief set CPM output filter/unfilter selection
*
* @param pCmp the CMP instance to use
* @param eType CPM output filter/unfilter type
*/
LOCAL_INLINE void CMP_HWA_SetCmpOutSel(CMP_Type *const pCmp, CMP_OutSelectType eType)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_SEL_MASK)) | CMP_CCR1_CMPOUT_SEL(eType));
}
/**
* @brief set comparator output pin enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetEnCmpOutPack(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_PEN_MASK)) | CMP_CCR1_CMPOUT_PEN(bEnable));
}
/**
* @brief set CMPOUT_WIN level, when window is closed
*
* @param pCmp the CMP instance to use
* @param eType CMPOUT_WIN level type
*/
LOCAL_INLINE void CMP_HWA_SetCmpOutWinLevel(CMP_Type *const pCmp, CMP_OutWinLevelType eType)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_WIN_OWEN_MASK)) | CMP_CCR1_CMPOUT_WIN_OWEN(eType));
}
/**
* @brief set CMPOUT_WIN level in user-define mode, when window is closed
*
* @param pCmp the CMP instance to use
* @param eType user-define CMPOUT_WIN level type
*/
LOCAL_INLINE void CMP_HWA_SetCmpOutWin(CMP_Type *const pCmp, CMP_OutWinLevel_UserDefType eType)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_WIN_OW_MASK)) | CMP_CCR1_CMPOUT_WIN_OW(eType));
}
/**
* @brief set invert the WINDOW/SAMPLE signal enable or not
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetEnWinSampleInvert(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_WIN_INV_MASK)) | CMP_CCR1_WIN_INV(bEnable));
}
/**
* @brief WINDOW signal can or not be closed by CMPO event when window mode
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetEnEventCloseWin(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_WIN_CLS_MASK)) | CMP_CCR1_WIN_CLS(bEnable));
}
/**
* @brief set which CMPO event causes window close
*
* @param pCmp the CMP instance to use
* @param eType CMPO event type
*/
LOCAL_INLINE void CMP_HWA_SetEventCloseWin(CMP_Type *const pCmp, CMP_EventType eType)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_EVT_SEL_MASK)) | CMP_CCR1_EVT_SEL(eType));
}
/**
* @brief set CMP power mode select
*
* @param pCmp the CMP instance to use
* @param eMod CMP power mode
*/
LOCAL_INLINE void CMP_HWA_SetSpeedMod(CMP_Type *const pCmp, CMP_SpeedModSelType eMod)
{
uint32_t u32RegVal = pCmp->CCR2;
pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_HPMD_MASK)) | CMP_CCR2_HPMD(eMod));
}
/**
* @brief set Comparator hard block hysteresis control
*
* @param pCmp the CMP instance to use
* @param eType CMP hysteresis control type
*/
LOCAL_INLINE void CMP_HWA_SetHystCtrl(CMP_Type *const pCmp, CMP_HystCtrlType eType)
{
uint32_t u32RegVal = pCmp->CCR2;
pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_HYSTCTR_MASK)) | CMP_CCR2_HYSTCTR(eType));
}
/**
* @brief set Comparator analog confifuration transition bypass
*
* @param pCmp the CMP instance to use
* @param Enable The status for Comparator analog confifuration transition bypass
*/
LOCAL_INLINE void CMP_HWA_SetAnalogConfTransByp(CMP_Type *const pCmp, bool Enable)
{
uint32_t u32RegVal = pCmp->CCR3;
pCmp->CCR3 = ((u32RegVal & (~(uint32_t)CMP_CCR3_DAC_TRANS_BYP_MASK)) | CMP_CCR3_DAC_TRANS_BYP(Enable));
}
/**
* @brief set Comparator hard block hysteresis control
*
* @param pCmp the CMP instance to use
* @param Count Comparator analog confifuration transition bypass count
*/
LOCAL_INLINE void CMP_HWA_SetAnalogConfTransBypCnt(CMP_Type *const pCmp, uint16_t Count)
{
uint32_t u32RegVal = pCmp->CCR3;
Count = Count & 0x3ff;
pCmp->CCR3 = ((u32RegVal & (~(uint32_t)CMP_CCR3_DAC_RDY_CNT_MASK)) | CMP_CCR3_DAC_RDY_CNT(Count));
}
/**
* @brief set which input is selected for the positive mux
*
* @param pCmp the CMP instance to use
* @param eType CMP positive mux type
*/
LOCAL_INLINE void CMP_HWA_SetPSelMux(CMP_Type *const pCmp, CMP_MuxSelType eType)
{
uint32_t u32RegVal = pCmp->CCR2;
pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_PSEL_MASK)) | CMP_CCR2_PSEL(eType));
}
/**
* @brief set which input is selected for the negative mux
*
* @param pCmp the CMP instance to use
* @param eType CMP negative mux type
*/
LOCAL_INLINE void CMP_HWA_SetNSelMux(CMP_Type *const pCmp, CMP_MuxSelType eType)
{
uint32_t u32RegVal = pCmp->CCR2;
pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_MSEL_MASK)) | CMP_CCR2_MSEL(eType));
}
/**
* @brief set the input to the positive port of the comparator
*
* @param pCmp the CMP instance to use
* @param eType CMP positive input source type(analog mux,dac)
*/
LOCAL_INLINE void CMP_HWA_SetINPSel(CMP_Type *const pCmp, CMP_INSrcSelType eType)
{
uint32_t u32RegVal = pCmp->CCR2;
pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_INPSEL_MASK)) | CMP_CCR2_INPSEL(eType));
}
/**
* @brief set the input to the negative port of the comparator
*
* @param pCmp the CMP instance to use
* @param eType CMP negative input source type(analog mux,dac)
*/
LOCAL_INLINE void CMP_HWA_SetINNSel(CMP_Type *const pCmp, CMP_INSrcSelType eType)
{
uint32_t u32RegVal = pCmp->CCR2;
pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_INMSEL_MASK)) | CMP_CCR2_INMSEL(eType));
}
/**
* @brief set CMP DAC enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetEnDac(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->DCR;
pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_DAC_EN_MASK)) | CMP_DCR_DAC_EN(bEnable));
}
/**
* @brief set DAC reference voltage source
*
* @param pCmp the CMP instance to use
* @param eType CMP reference voltage source type
*/
LOCAL_INLINE void CMP_HWA_SetVinRefSel(CMP_Type *const pCmp, CMP_DacVinRefSelType eType)
{
uint32_t u32RegVal = pCmp->DCR;
pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_VRSEL_MASK)) | CMP_DCR_VRSEL(eType));
}
/**
* @brief set CMP Dac output
*
* @param pCmp the CMP instance to use
* @param u8Data the Dac data
* @note output = (VinRef / 256) * (u8Data + 1)
*/
LOCAL_INLINE void CMP_HWA_SetDacData(CMP_Type *const pCmp, uint8_t u8Data)
{
uint32_t u32RegVal = pCmp->DCR;
pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_DAC_DATA_MASK)) | CMP_DCR_DAC_DATA(u8Data));
}
/**
* @brief set comparator rising interrupt enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetIntEn_Rising(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->IER;
pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CFR_IE_MASK)) | CMP_IER_CFR_IE(bEnable));
}
/**
* @brief get comparator rising interrupt enable status
*
* @param pCmp the CMP instance to use
* @return comparator rising interrupt status
*/
LOCAL_INLINE bool CMP_HWA_GetIntEn_Rising(CMP_Type *const pCmp)
{
bool RetStatus = false;
uint32_t u32RegVal = pCmp->IER;
RetStatus = (bool)((((u32RegVal & CMP_IER_CFR_IE_MASK) >> CMP_IER_CFR_IE_SHIFT) != 0U) ? true : false);
return RetStatus;
}
/**
* @brief set comparator falling interrupt enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetIntEn_Falling(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->IER;
pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CFF_IE_MASK)) | CMP_IER_CFF_IE(bEnable));
}
/**
* @brief get comparator falling interrupt enable status
*
* @param pCmp the CMP instance to use
* @return comparator falling interrupt status
*/
LOCAL_INLINE bool CMP_HWA_GetIntEn_Falling(CMP_Type *const pCmp)
{
bool bRetStatus = false;
uint32_t u32RegVal = pCmp->IER;
bRetStatus = (bool)((((u32RegVal & CMP_IER_CFF_IE_MASK) >> CMP_IER_CFF_IE_SHIFT) != 0U) ? true : false);
return bRetStatus;
}
/**
* @brief set comparator channel scan interrupt enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetIntEn_ChannelScan(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->IER;
pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CSF_IE_MASK)) | CMP_IER_CSF_IE(bEnable));
}
/**
* @brief get comparator channel scan interrupt enable status
*
* @param pCmp the CMP instance to use
* @return comparator channel scan interrupt status
*/
LOCAL_INLINE bool CMP_HWA_GetIntEn_ChannelScan(CMP_Type *const pCmp)
{
bool bRetStatus = false;
uint32_t u32RegVal = pCmp->IER;
bRetStatus = (bool)((((u32RegVal & CMP_IER_CSF_IE_MASK) >> CMP_IER_CSF_IE_SHIFT) != 0U) ? true : false);
return bRetStatus;
}
/**
* @brief get CMP output rising edge status
*
* @param pCmp the CMP instance to use
* @return CMP rising edge status
*/
LOCAL_INLINE bool CMP_HWA_GetIntFlag_Rising(CMP_Type *const pCmp)
{
bool bRetStatus = false;
uint32_t u32RegVal = pCmp->CSR;
bRetStatus = (bool)((((u32RegVal & CMP_CSR_CFR_MASK) >> CMP_CSR_CFR_SHIFT) != 0U) ? true : false);
return bRetStatus;
}
/**
* @brief get CMP output falling edge status
*
* @param pCmp the CMP instance to use
* @return CMP falling edge status
*/
LOCAL_INLINE bool CMP_HWA_GetIntFlag_Falling(CMP_Type *const pCmp)
{
bool bRetStatus = false;
uint32_t u32RegVal = pCmp->CSR;
bRetStatus = (bool)((((u32RegVal & CMP_CSR_CFF_MASK) >> CMP_CSR_CFF_SHIFT) != 0U) ? true : false);
return bRetStatus;
}
/**
* @brief get CMP output channel scan status
*
* @param pCmp the CMP instance to use
* @return CMP channel scan status
*/
LOCAL_INLINE bool CMP_HWA_GetIntFlag_ChannelScan(CMP_Type *const pCmp)
{
bool bRetStatus = false;
uint32_t u32RegVal = pCmp->CSR;
bRetStatus = (bool)((((u32RegVal & CMP_CSR_CSF_MASK) >> CMP_CSR_CSF_SHIFT) != 0U) ? true : false);
return bRetStatus;
}
/**
* @brief clear rising interrupt flag
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_ClearIntFlag_Rising(CMP_Type *const pCmp)
{
uint32_t u32RegVal = pCmp->CSR;
pCmp->CSR = ((u32RegVal & (~(uint32_t)CMP_CSR_CFR_MASK)) | CMP_CSR_CFR(true));
}
/**
* @brief clear falling interrupt flag
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_ClearIntFlag_Falling(CMP_Type *const pCmp)
{
uint32_t u32RegVal = pCmp->CSR;
pCmp->CSR = ((u32RegVal & (~(uint32_t)CMP_CSR_CFF_MASK)) | CMP_CSR_CFF(true));
}
/**
* @brief clear channel scan interrupt flag
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_ClearIntFlag_ChannelScan(CMP_Type *const pCmp)
{
uint32_t u32RegVal = pCmp->CSR;
pCmp->CSR = ((u32RegVal & (~(uint32_t)CMP_CSR_CSF_MASK)) | CMP_CSR_CSF(true));
}
/**
* @brief get CMP filtered output
*
* @param pCmp the CMP instance to use
* @return CMP filtered output
*/
LOCAL_INLINE bool CMP_HWA_GetCmpOut(CMP_Type *const pCmp)
{
bool CmpOut;
uint32_t u32RegVal = pCmp->CSR;
CmpOut = ((u32RegVal & CMP_CSR_CMPOUT_FILTER_MASK) >> CMP_CSR_CMPOUT_FILTER_SHIFT) ? true : false;
return CmpOut;
}
/**
* @brief set CMP and DAC initialization delay modulus
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_SetCSInitModulus(CMP_Type *const pCmp, uint8_t u8Modulus)
{
uint32_t u32RegVal = pCmp->CSCR0;
pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_INITMOD_MASK)) | CMP_CSCR0_CS_INITMOD(u8Modulus));
}
/**
* @brief set number of clock cycles for sampling
*
* @param pCmp the CMP instance to use
* @param u8Nsam the sampling clocks value
*/
LOCAL_INLINE void CMP_HWA_SetCSNumOfSampleClocks(CMP_Type *const pCmp, uint8_t u8Nsam)
{
uint32_t u32RegVal = pCmp->CSCR0;
pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_NSAM_MASK)) | CMP_CSCR0_CS_NSAM(u8Nsam));
}
/**
* @brief set CMP channel scan enable
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_CSEnable(CMP_Type *const pCmp)
{
uint32_t u32RegVal = pCmp->CSCR0;
pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_EN_MASK)) | CMP_CSCR0_CS_EN(true));
}
/**
* @brief set CMP channel scan disable
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_CSDisable(CMP_Type *const pCmp)
{
uint32_t u32RegVal = pCmp->CSCR0;
pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_EN_MASK)) | CMP_CSCR0_CS_EN(false));
}
/**
* @brief set channel scan fixed channel
*
* @param pCmp the CMP instance to use
* @param eChannel the fixed channel
*/
LOCAL_INLINE void CMP_HWA_SetCSFixedChannel(CMP_Type *const pCmp, CMP_MuxSelType eChannel)
{
uint32_t u32RegVal = pCmp->CSCR1;
pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)CMP_CSCR1_FIXCH_MASK)) | CMP_CSCR1_FIXCH(eChannel));
}
/**
* @brief set channel scan fixed port
*
* @param pCmp the CMP instance to use
* @param ePort the fixed port
*/
LOCAL_INLINE void CMP_HWA_SetCSFixedPort(CMP_Type *const pCmp, CMP_PortSelType ePort)
{
uint32_t u32RegVal = pCmp->CSCR1;
pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)CMP_CSCR1_FIXP_MASK)) | CMP_CSCR1_FIXP(ePort));
}
/**
* @brief set channel scan channel enabled
*
* @param pCmp the CMP instance to use
* @param eChannel the enabled channel
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetCSChannelEn(CMP_Type *const pCmp, CMP_MuxSelType eChannel, bool bEnable)
{
uint32_t u32RegVal = pCmp->CSCR1;
pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)(1 << eChannel))) | (((uint32_t)bEnable) << eChannel));
}
/**
* @brief set channel scan channel enabled
*
* @param pCmp the CMP instance to use
* @param eChannel the enabled channel
* @param bPresetstate preset state for channel
*/
LOCAL_INLINE void CMP_HWA_SetCSChannelPresetstate(CMP_Type *const pCmp, CMP_MuxSelType eChannel, bool bPresetstate)
{
uint32_t u32RegVal = pCmp->CSCSR;
pCmp->CSCSR = ((u32RegVal & (~(uint32_t)(1 << eChannel))) | (((uint32_t)bPresetstate) << eChannel));
}
/**
* @brief get channel scan channel current state
*
* @param pCmp the CMP instance to use
* @param eChannel the channel that want to get state
*/
LOCAL_INLINE bool CMP_HWA_GetCSChannelsOut(CMP_Type *const pCmp, CMP_MuxSelType eChannel)
{
bool OutFlag;
uint32_t u32RegVal = pCmp->CSCSR;
OutFlag = (bool)((u32RegVal & ((uint32_t)(1 << eChannel))) >> eChannel);
return OutFlag;
}
/**
* @brief software clear channel scan comparison results
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_ClearCSComparisonResults(CMP_Type *const pCmp)
{
uint32_t u32RegVal = pCmp->CSCSR;
pCmp->CSCSR = ((u32RegVal & (~(uint32_t)CMP_CSCSR_CS_SWCLR_MASK)) | CMP_CSCSR_CS_SWCLR(true));
}
/**
* @brief software clear channel scan comparison results
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetCSComparisonResultsAutoClearEn(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CSCSR;
pCmp->CSCSR = ((u32RegVal & (~(uint32_t)CMP_CSCSR_CS_ACLR_MASK)) | CMP_CSCSR_CS_ACLR(bEnable));
}
/**
* @brief get channel scan comparison reuslt
*
* @param pCmp the CMP instance to use
* @param eChannel the enabled channel
* @return channel comparison result for a given channel
*/
LOCAL_INLINE uint32_t CMP_HWA_GetCSComparisonResult(CMP_Type *const pCmp, CMP_MuxSelType eChannel)
{
uint32_t u32RegVal = pCmp->CSCSR;
u32RegVal = (u32RegVal & (1 << eChannel)) >> eChannel;
return u32RegVal;
}
/**
* @brief set channel scan active
*
* @param pCmp the CMP instance to use
* @return status cmp channel whether is active
*/
LOCAL_INLINE bool CMP_HWA_GetCSActive(CMP_Type *const pCmp)
{
bool status;
uint32_t u32RegVal = pCmp->CSSR;
status = ((u32RegVal & ((uint32_t)CMP_CSSR_CS_ACTIVE_MASK)) >> CMP_CSSR_CS_ACTIVE_SHIFT) ? true : false;
return status;
}
/**
* @brief get channel scan comparison result changed flag
*
* @param pCmp the CMP instance to use
* @param eChannel the channel to get comparison result changed flag
* @return the comparison result changed flag for a given channel
*/
LOCAL_INLINE bool CMP_HWA_GetCSComparisonResultFlag(CMP_Type *const pCmp, CMP_MuxSelType eChannel)
{
bool flag;
uint32_t u32RegVal = pCmp->CSSR;
flag = ((u32RegVal & (1 << eChannel)) >> eChannel) ? true : false;
return flag;
}
#endif /* #ifndef _HWA_CMP_H_ */

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/**
* @file HwA_cmu.h
* @author Flagchip085
* @brief FC7xxx CMU hardware access layer
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_CMU_H_
#define _HWA_CMU_H_
#include "device_header.h"
/********* Local inline function ************/
/**
* @brief Set Reference Window value.
* @param pCmu CMU Instance.
* @param u32Value Ref Window value.
*/
LOCAL_INLINE void CMU_HWA_SetRefWindow(CMU_Type *const pCmu, uint32_t u32Value)
{
pCmu->REF_WINDOW = CMU_REF_WINDOW_REF_WINDOW(u32Value);
}
/**
* @brief Get Reference Window value.
* @param pCmu CMU Instance.
* @return Reference Window value.
*/
LOCAL_INLINE uint32_t CMU_HWA_GetRefWindow(const CMU_Type *const pCmu)
{
return (pCmu->REF_WINDOW & CMU_REF_WINDOW_REF_WINDOW_MASK) >> CMU_REF_WINDOW_REF_WINDOW_SHIFT;
}
/**
* @brief Set Minimun Counter value
* @param pCmu CMU Instance.
* @param u32Value Min Count value.
*/
LOCAL_INLINE void CMU_HWA_SetMinCnts(CMU_Type *const pCmu, uint32_t u32Value)
{
pCmu->MIN = CMU_MIN_MIN(u32Value);
}
/**
* @brief Get Minimun Counter value.
* @param pCmu CMU Instance.
* @return Min count value.
*/
LOCAL_INLINE uint32_t CMU_HWA_GetMinCnts(const CMU_Type *const pCmu)
{
return (pCmu->MIN & CMU_MIN_MIN_MASK) >> CMU_MIN_MIN_SHIFT;
}
/**
* @brief Set Maximun Counter value.
* @param pCmu CMU Instance.
* @param u32Value Max count value.
*/
LOCAL_INLINE void CMU_HWA_SetMaxCnts(CMU_Type *const pCmu, uint32_t u32Value)
{
pCmu->MAX = CMU_MAX_MAX(u32Value);
}
/**
* @brief Get Maximun Counter value.
* @param pCmu CMU Instance.
* @return Max count value.
*/
LOCAL_INLINE uint32_t CMU_HWA_GetMaxCnts(const CMU_Type *const pCmu)
{
return (pCmu->MAX & CMU_MAX_MAX_MASK) >> CMU_MAX_MAX_SHIFT;
}
/**
* @brief Get Counter value.
* @param pCmu CMU Instance.
* @return Counter value.
*/
LOCAL_INLINE uint32_t CMU_HWA_GetCount(const CMU_Type *const pCmu)
{
return (pCmu->MON_CNT & CMU_MON_CNT_MON_CNT_MASK) >> CMU_MON_CNT_MON_CNT_SHIFT;
}
/**
* @brief Set period window Counter.
* @param pCmu CMU Instance.
* @param u32Value Period value.
*/
LOCAL_INLINE void CMU_HWA_SetPeriodWindow(CMU_Type *const pCmu, uint32_t u32Value)
{
pCmu->PERIOD = (pCmu->PERIOD & ~CMU_PERIOD_WINDOW_MASK) | CMU_PERIOD_WINDOW(u32Value);
}
/**
* @brief Set period enble bit.
*
* @param pCmu CMU Instance.
* @param bEnable Set enable bit.
*/
LOCAL_INLINE void CMU_HWA_SetPeriodEnable(CMU_Type *const pCmu, bool bEnable)
{
pCmu->PERIOD = (pCmu->PERIOD & ~((uint32_t)CMU_PERIOD_EN_MASK)) | CMU_PERIOD_EN(bEnable);
}
/**
* @brief Set control register value.
*
* @param pCmu CMU Instance.
* @param u32Value Control value.
*/
LOCAL_INLINE void CMU_HWA_SETCTRL(CMU_Type *const pCmu, uint32_t u32Value)
{
pCmu->CTRL = u32Value;
}
/**
* @brief return control register value.
*
* @param pCmu CMU Instance.
* @return CMU Control register value
*/
LOCAL_INLINE uint32_t CMU_HWA_GetCTRL(const CMU_Type *const pCmu)
{
return pCmu->CTRL;
}
/**
* @brief return status register value.
* @param pCmu CMU Instance.
* @return Status value.
*/
LOCAL_INLINE uint32_t CMU_HWA_GetST(const CMU_Type *const pCmu)
{
return pCmu->ST;
}
/**
* @brief Clear clock monitor status
* @param pCmu CMU Instance.
*/
LOCAL_INLINE void CMU_HWA_ClearST(CMU_Type *const pCmu)
{
pCmu->ST = (uint32_t)(CMU_ST_MIS_MASK | CMU_ST_LOC_MASK);
}
/**
* @brief Set the Divider for Reference Clock
* @param pCmu CMU Instance.
* @param eDivider The Divider of Reference Clock
*/
LOCAL_INLINE void CMU_HWA_SetRefClockDiv(CMU_Type *const pCmu, uint8_t eDivider)
{
pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_REF_DIV_MASK)) | CMU_CTRL_REF_DIV(eDivider);
}
/**
* @brief Get the Divider for Reference Clock
* @param pCmu CMU Instance.
* @return The Divider of Reference Clock
*/
LOCAL_INLINE uint8_t CMU_HWA_GetRefClockDiv(const CMU_Type *const pCmu)
{
uint32_t u32Temp = (pCmu->CTRL & (uint32_t)CMU_CTRL_REF_DIV_MASK) >> CMU_CTRL_REF_DIV_SHIFT;
return (uint8_t)u32Temp;
}
/**
* @brief Enable interrupt when LOC or MIS asserted
* @param pCmu CMU Instance.
* @param bEnable Enable or disable CMU interrupt
*/
LOCAL_INLINE void CMU_HWA_IrqEnable(CMU_Type *const pCmu, bool bEnable)
{
pCmu->CTRL = (pCmu->CTRL & (~((uint32_t)CMU_CTRL_IRQ_EN_MASK))) | CMU_CTRL_IRQ_EN(bEnable);
}
/**
* @brief Get CMU interrupt enable flag
* @param pCmu CMU Instance.
* @return 1 : CMU interrupt enabled
* 0 : CMU interrupt disabled
*/
LOCAL_INLINE uint8_t CMU_HWA_GetIrqEnableFlag(const CMU_Type *const pCmu)
{
uint32_t u32Temp = (pCmu->CTRL & (uint32_t)CMU_CTRL_IRQ_EN_MASK) >> CMU_CTRL_IRQ_EN_SHIFT;
return (uint8_t)u32Temp;
}
/**
* @brief Enable Standby mode
* @param pCmu CMU Instance.
* @param bEnable Enable mode
*/
LOCAL_INLINE void CMU_HWA_StanbyModeEnable(CMU_Type *const pCmu, bool bEnable)
{
pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_LP_EN_MASK)) | CMU_CTRL_LP_EN(bEnable);
}
/**
* @brief Enable Stop mode
* @param pCmu CMU Instance.
* @param bEnable Enable mode
*/
LOCAL_INLINE void CMU_HWA_StopModeEnable(CMU_Type *const pCmu, bool bEnable)
{
pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_STOP_EN_MASK)) | CMU_CTRL_STOP_EN(bEnable);
}
/**
* @brief Enable hardware restart CMU after exiting from the low-power mode
* @param pCmu CMU Instance.
* @param bEnable Enable mode
*/
LOCAL_INLINE void CMU_HWA_LPRestartEnable(CMU_Type *const pCmu, bool bEnable)
{
pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_RESTART_EN_MASK)) | CMU_CTRL_RESTART_EN(bEnable);
}
/**
* @brief Software Reset the CMU
* @param pCmu CMU Instance.
*/
LOCAL_INLINE void CMU_HWA_SoftwareReset(CMU_Type *const pCmu)
{
pCmu->CTRL |= CMU_CTRL_SW_RST_MASK;
}
/**
* @brief Enable the CMU
* @param pCmu CMU Instance.
*/
LOCAL_INLINE void CMU_HWA_Enable(CMU_Type *const pCmu)
{
pCmu->CTRL |= CMU_CTRL_ENABLE_MASK;
}
/**
* @brief Disable the CMU
* @param pCmu CMU Instance.
*/
LOCAL_INLINE void CMU_HWA_Disable(CMU_Type *const pCmu)
{
pCmu->CTRL &= ~(CMU_CTRL_ENABLE_MASK | CMU_CTRL_IRQ_EN_MASK);
}
/**
* @brief Get the CMU enabled status
* @param pCmu CMU Instance.
* @return 1 : CMU is enabled
* 0 : CMU is disabled
*/
LOCAL_INLINE uint8_t CMU_HWA_GetEnableStatus(const CMU_Type *const pCmu)
{
uint32_t u32Temp = (pCmu->CTRL & (uint32_t)CMU_CTRL_ENABLE_MASK) >> CMU_CTRL_ENABLE_SHIFT;
return (uint8_t)u32Temp;
}
#endif /* #ifndef _HWA_CMU_H_ */

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/**
* @file HwA_cordic.h
* @author Flagchip
* @brief Hardware access layer for Cordic
* @version 0.1.0
* @date 2024-01-11
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_CORDIC_H_
#define _HWA_CORDIC_H_
#include "device_header.h"
typedef enum
{
CORDIC_Iteration_8 = 0,
CORDIC_Iteration_16,
CORDIC_Iteration_24
}CORDIC_IterationType;
typedef enum
{
CORDIC_Trigonometric = 0,
CORDIC_Hyperbolic,
CORDIC_Linear
}CORDIC_SystemType;
typedef enum
{
CORDIC_Rotate = 0,
CORDIC_Vector
}CORDIC_ModeType;
#define CORDIC_CTR_VAL(s,a,b,c,d) (CORDIC_CTRL_SCALE(s) | CORDIC_CTRL_IE(a) | CORDIC_CTRL_ITER(b) | CORDIC_CTRL_OS(c) | CORDIC_CTRL_MODE(d))
/**
* @brief Set Cordic module Ctrl register
*
* @param u32Value Ctrl register value
*/
LOCAL_INLINE void Cordic_HWA_SetCtrl(uint32_t u32Value)
{
CORDIC->CTRL = u32Value;
}
/**
* @brief Read Cordic module Ctrl register
*
* @return Ctrl register value
*/
LOCAL_INLINE uint32_t Cordic_HWA_GetCtrl(void)
{
return (uint32_t)(CORDIC->CTRL);
}
/**
* @brief Set Cordic module XInput register
*
* @param u32Value XInput register value
*/
LOCAL_INLINE void Cordic_HWA_Set_XInput(int32_t u32Value)
{
CORDIC->X_INPUT = (uint32_t)u32Value;
}
/**
* @brief Set Cordic module YInput register
*
* @param u32Value YInput register value
*/
LOCAL_INLINE void Cordic_HWA_Set_YInput(int32_t u32Value)
{
CORDIC->Y_INPUT = (uint32_t)u32Value;
}
/**
* @brief Set Cordic module ZInput register
*
* @param u32Value ZInput register value
*/
LOCAL_INLINE void Cordic_HWA_Set_ZInput(int32_t u32Value)
{
CORDIC->Z_INPUT = (uint32_t)u32Value;
}
/**
* @brief Read Cordic module XOutput register
*
* @return XOutput register value
*/
LOCAL_INLINE uint32_t Cordic_HWA_Get_XOutput(void)
{
return (uint32_t)(CORDIC->X_OUTPUT);
}
/**
* @brief Read Cordic module YOutput register
*
* @return YOutput register value
*/
LOCAL_INLINE uint32_t Cordic_HWA_Get_YOutput(void)
{
return (uint32_t)(CORDIC->Y_OUTPUT);
}
/**
* @brief Read Cordic module ZOutput register
*
* @return ZOutput register value
*/
LOCAL_INLINE uint32_t Cordic_HWA_Get_ZOutput(void)
{
return (uint32_t)(CORDIC->Z_OUTPUT);
}
/**
* @brief Read Cordic module state
*
* @return Cordic module current state
*/
LOCAL_INLINE bool Cordic_HWA_Get_Stat(void)
{
return (bool)(CORDIC->STAT & CORDIC_STAT_DONE_MASK);
}
#endif

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/**
* @file HwA_cpm.h
* @author Flagchip
* @brief FC7xxx CPM register API
* @version 0.1.0
* @date 2024-1-5
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-1-5 Flagchip120 N/A First version for FC7240
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_CPM_H_
#define HWA_INCLUDE_HWA_CPM_H_
#include "device_header.h"
/* ################################################################################## */
/* ####################################### Macro #################################### */
/** FPSCR Bit Fields */
#define FPSCR_IOC_MASK 0x00000001U
#define FPSCR_DZC_MASK 0x00000002U
#define FPSCR_OFC_MASK 0x00000004U
#define FPSCR_UFC_MASK 0x00000008U
#define FPSCR_IXC_MASK 0x00000010U
#define FPSCR_IDC_MASK 0x00000080U
#define CPM_FPU_INTFLAGMASK 0x0000003FU
/**
* @defgroup HwA_cpm
* @ingroup fc7xxx_driver_cpm
* @{
*/
/**
* @brief FPU INTERRUPT type.
*
* This provides constants for FPU interrupt type for use in the FPU functions.
* Please refer to Reference Manual chapter 14 CPM, it introduce register FISCR for details.
*
*/
typedef enum
{
CPM_FPU_FIO = 1U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FIOCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FIOC Status*/
CPM_FPU_FDZ = 2U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FDZCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FDZC Status*/
CPM_FPU_FUF = 4U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FUFCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FUFC Status*/
CPM_FPU_FOF = 8U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FOFCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FOFC Status*/
CPM_FPU_FID = 16U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FIDCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FIDC Status*/
CPM_FPU_FIX = 32U /*!< in function CPM_FpuIntMode, set CPM_FISCR FIXCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FIXC Status*/
} FPU_IntType;
/** @brief Cpm return type. */
typedef enum
{
CPM_STATUS_SUCCESS = 0U, /*!< CPM status success */
CPM_STATUS_PARAM_INVALID = 1U /*!< CPM status parameter invalid */
} CPM_RetType;
/**
* @brief Get the value of CPM FISCR.
*
* This function returns FISCR value.
*
* @return uint32_t the value of the FISCR register.
*/
LOCAL_INLINE uint32_t CPM_HWA_GetFiscr(void)
{
return CPM->FISCR;
}
/**
* @brief Return CPM_FISCR FIOC value
*
* @return 0: No interrupt; 1: Interrupt occurred
*/
LOCAL_INLINE bool CPM_HWA_GetFpuFiocFlag(void)
{
uint32_t u32TmpVal = CPM->FISCR;
u32TmpVal = (u32TmpVal & CPM_FISCR_FIOC_MASK) >> CPM_FISCR_FIOC_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Return CPM_FISCR FDZC value
*
* @return 0: No interrupt; 1: Interrupt occurred
*/
LOCAL_INLINE bool CPM_HWA_GetFpuFdzcFlag(void)
{
uint32_t u32TmpVal = CPM->FISCR;
u32TmpVal = (u32TmpVal & CPM_FISCR_FDZC_MASK) >> CPM_FISCR_FDZC_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Return CPM_FISCR FOFC value
*
* @return 0: No interrupt; 1: Interrupt occurred
*/
LOCAL_INLINE bool CPM_HWA_GetFpuFofcFlag(void)
{
uint32_t u32TmpVal = CPM->FISCR;
u32TmpVal = (u32TmpVal & CPM_FISCR_FOFC_MASK) >> CPM_FISCR_FOFC_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Return CPM_FISCR FUFC value
*
* @return 0: No interrupt; 1: Interrupt occurred
*/
LOCAL_INLINE bool CPM_HWA_GetFpuFufcFlag(void)
{
uint32_t u32TmpVal = CPM->FISCR;
u32TmpVal = (u32TmpVal & CPM_FISCR_FUFC_MASK) >> CPM_FISCR_FUFC_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Return CPM_FISCR FIXC value
*
* @return 0: No interrupt; 1: Interrupt occurred
*/
LOCAL_INLINE bool CPM_HWA_GetFpuFixcFlag(void)
{
uint32_t u32TmpVal = CPM->FISCR;
u32TmpVal = (u32TmpVal & CPM_FISCR_FIXC_MASK) >> CPM_FISCR_FIXC_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Return CPM_FISCR FIDC value
*
* @return 0: No interrupt; 1: Interrupt occurred
*/
LOCAL_INLINE bool CPM_HWA_GetFpuFidcFlag(void)
{
uint32_t u32TmpVal = CPM->FISCR;
u32TmpVal = (u32TmpVal & CPM_FISCR_FIDC_MASK) >> CPM_FISCR_FIDC_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set FIOCE interrupt
*
* @param bEnable 1: enable interrupt 0: disable interrupt
*/
LOCAL_INLINE void CPM_HWA_SetFioceInt(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FIOCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIOCE_SHIFT));
}
/**
* @brief Set FDZCE interrupt
*
* @param bEnable 1: enable interrupt 0: disable interrupt
*/
LOCAL_INLINE void CPM_HWA_SetFdzceInt(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FDZCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FDZCE_SHIFT));
}
/**
* @brief Set FOFCE interrupt
*
* @param bEnable 1: enable interrupt 0: disable interrupt
*/
LOCAL_INLINE void CPM_HWA_SetFofceInt(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FOFCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FOFCE_SHIFT));
}
/**
* @brief Set FUFCE interrupt
*
* @param bEnable 1: enable interrupt 0: disable interrupt
*/
LOCAL_INLINE void CPM_HWA_SetFufceInt(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FUFCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FUFCE_SHIFT));
}
/**
* @brief Set FIXCE interrupt
*
* @param bEnable 1: enable interrupt 0: disable interrupt
*/
LOCAL_INLINE void CPM_HWA_SetFixceInt(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FIXCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIXCE_SHIFT));
}
/**
* @brief Set FIDCE interrupt
*
* @param bEnable 1: enable interrupt 0: disable interrupt
*/
LOCAL_INLINE void CPM_HWA_SetFidceInt(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FIDCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIDCE_SHIFT));
}
/**
* @brief Set FISCR value
*
* @param u32Val the value want to set the register
*/
LOCAL_INLINE void CPM_HWA_SetFiscr(uint32_t u32Val)
{
CPM->FISCR = u32Val;
}
/**
* @brief Get the value of CPM TCMRCR.
*
* This function returns TCMRCR value.
*
* @return uint32_t the value of the TCMRCR register.
*/
LOCAL_INLINE uint32_t CPM_HWA_GetTcmrcr(void)
{
return CPM->TCMRCR;
}
/**
* @brief Set DTCM1 retry buffer force clear
*
* @param bEnable 1:Force clear DTCM1 retry buffer 0: No operation
*/
LOCAL_INLINE void CPM_HWA_SetDTCM1BufClear(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D1RBCLR_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D1RBCLR_SHIFT));
}
/**
* @brief Set DTCM0 retry buffer force clear
*
* @param bEnable 1:Force clear DTCM0 retry buffer 0: No operation
*/
LOCAL_INLINE void CPM_HWA_SetDTCM0BufClear(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D0RBCLR_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D0RBCLR_SHIFT));
}
/**
* @brief Set ITCM retry buffer force clear
*
* @param bEnable 1:Force clear ITCM retry buffer 0: No operation
*/
LOCAL_INLINE void CPM_HWA_SetITCMBufClear(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_IRBCLR_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_IRBCLR_SHIFT));
}
/**
* @brief Set DTCM1 retry buffer invalid
*/
LOCAL_INLINE void CPM_HWA_SetDTCM1BufInvalid(void)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D1RBVLD_MASK)) | (1U << CPM_TCMRCR_D1RBCLR_SHIFT));
}
/**
* @brief Set DTCM0 retry buffer invalid
*/
LOCAL_INLINE void CPM_HWA_SetDTCM0BufInvalid(void)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D0RBVLD_MASK)) | (1U << CPM_TCMRCR_D0RBCLR_SHIFT));
}
/**
* @brief Set ITCM retry buffer invalid
*/
LOCAL_INLINE void CPM_HWA_SetITCMBufInvalid(void)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_IRBVLD_MASK)) | (1U << CPM_TCMRCR_IRBCLR_SHIFT));
}
/**
* @brief Set DTCM1 retry buffer timeout interrupt enable
*
* @param bEnable 1:Interrupt enable 0: No operation
*/
LOCAL_INLINE void CPM_HWA_SetDTCM1TimeoutInt(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D1RBIE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D1RBIE_SHIFT));
}
/**
* @brief Set DTCM0 retry buffer timeout interrupt enable
*
* @param bEnable 1:Interrupt enable 0: No operation
*/
LOCAL_INLINE void CPM_HWA_SetDTCM0TimeoutInt(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D0RBIE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D0RBIE_SHIFT));
}
/**
* @brief Set ITCM retry buffer timeout interrupt enable
*
* @param bEnable 1:Interrupt enable 0: No operation
*/
LOCAL_INLINE void CPM_HWA_SetITCMTimeoutInt(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_IRBIE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_IRBIE_SHIFT));
}
/**
* @brief Set DTCM1 retry buffer autoclear
*
* @param bEnable 1:Enable autoclear 0: No operation
*/
LOCAL_INLINE void CPM_HWA_SetDTCM1AutoClear(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D1RBAC_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D1RBAC_SHIFT));
}
/**
* @brief Set DTCM0 retry buffer autoclear
*
* @param bEnable 1:Enable autoclear 0: No operation
*/
LOCAL_INLINE void CPM_HWA_SetDTCM0AutoClear(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D0RBAC_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D0RBAC_SHIFT));
}
/**
* @brief Set ITCM retry buffer autoclear
*
* @param bEnable 1:Enable autoclear 0: No operation
*/
LOCAL_INLINE void CPM_HWA_SetITCMAutoClear(bool bEnable)
{
CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_IRBAC_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_IRBAC_SHIFT));
}
/** @}*/
#endif /* HWA_INCLUDE_HWA_CPM_H_ */

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/**
* @file HwA_crc.h
* @author Flagchip
* @brief FC7xxx CRC hardware access layer
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_CRC_H_
#define _HWA_CRC_H_
#include "device_header.h"
/********* Local typedef ************/
/**
* @brief The data swap for write
*/
typedef enum{
WRITE_DATASWAP_NONE = 0U, /*!< none data swap for write */
WRITE_DATASWAP_BIT = 1U, /*!< only bits data swap for write */
WRITE_DATASWAP_BIT_BYTE = 2U, /*!< both bits and bytes data swap for write */
WRITE_DATASWAP_BYTE = 3U /*!< only bytes data swap for write */
} CRC_WriteDataSwapType;
/**
* @brief The data swap for read
*/
typedef enum{
READ_DATASWAP_NONE = 0U, /*!< none data swap for read */
READ_DATASWAP_BIT = 1U, /*!< only bits data swap for read */
READ_DATASWAP_BIT_BYTE = 2U, /*!< both bits and bytes data swap for read */
READ_DATASWAP_BYTE = 3U /*!< only bytes data swap for read */
} CRC_ReadDataSwapType;
/**
* @brief The complement of reading crc data
*/
typedef enum{
READ_DATA_NORMAL = 0U, /*!< none complement of reading crc data */
READ_DATA_FXOR = 1U /*!< Invert or complement with 0xFFFFFFFF or 0xFFFF of crc data */
} CRC_ReadDataFXORType;
/**
* @brief The command type of write crc data or seed value
*/
typedef enum{
WRITE_COMMAND_DATA = 0U, /*!< write crc data */
WRITE_COMMAND_SEED = 1U /*!< write seed value(used to initialization crc calculation) */
} CRC_WriteCommondType;
/**
* @brief The crc mode select
*/
typedef enum{
CRC_BIT_16 = 0U, /*!< crc 16 bit is selected */
CRC_BIT_32 = 1U, /*!< crc 32 bit is selected */
CRC_BIT_8 = 2U,
CRC_BIT_INVALID = 3U
} CRC_BitWidthType;
/********* Local inline function ************/
/**
* @brief set CRC CR register for writing data or seed
*
* @param pCrc CRC instance
* @param u32Mod WAS mode
*/
LOCAL_INLINE void CRC_HWA_SetDataOrSeed(CRC_Type *const pCrc, CRC_WriteCommondType u32Mod)
{
uint32_t u32RegVal = pCrc->CR;
pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_WAS_MASK)) | CRC_CR_WAS(u32Mod));
}
/**
* @brief set polynomial value
*
* @param pCrc CRC instance
* @param u32Poly the polynomial value
*/
LOCAL_INLINE void CRC_HWA_SetPolyVal(CRC_Type *const pCrc, uint32_t u32Poly)
{
pCrc->POLY = u32Poly;
}
/**
* @brief set data register(32 bits)
*
* @param pCrc CRC instance
* @param u32Data data to be set
*/
LOCAL_INLINE void CRC_HWA_SetData_U32(CRC_Type *const pCrc, uint32_t u32Data)
{
pCrc->DATA.uDATA = u32Data;
}
/**
* @brief set data register(16 bits)
*
* @param pCrc CRC instance
* @param u16Data data to be set
*/
LOCAL_INLINE void CRC_HWA_SetData_U16(CRC_Type *const pCrc, uint16_t u16Data)
{
pCrc->DATA.tDATA_16.L = u16Data;
}
/**
* @brief set data register(low 8 bits)
*
* @param pCrc CRC instance
* @param u8Data data to be set
*/
LOCAL_INLINE void CRC_HWA_SetData_U8(CRC_Type *const pCrc, uint8_t u8Data)
{
pCrc->DATA.tDATA_8.LL = u8Data;
}
/**
* @brief get data register(32 bits)
*
* @param pCrc CRC instance
*
* @return 32-bit value
*/
LOCAL_INLINE uint32_t CRC_HWA_GetData_U32(CRC_Type *const pCrc)
{
return (pCrc->DATA.uDATA);
}
/**
* @brief get data register(high 8 bits)
*
* @param pCrc CRC instance
*
* @return high 8-bit value
*/
LOCAL_INLINE uint8 CRC_HWA_GetData_U8_H(CRC_Type *const pCrc)
{
return (pCrc->DATA.tDATA_8.HL);
}
/**
* @brief get data register(low 8 bits)
*
* @param pCrc CRC instance
*
* @return low 8-bit value
*/
LOCAL_INLINE uint8 CRC_HWA_GetData_U8_L(CRC_Type *const pCrc)
{
return (pCrc->DATA.tDATA_8.LL);
}
/**
* @brief get data register(high 16 bits)
*
* @param pCrc CRC instance
*
* @return high 16-bit value
*/
LOCAL_INLINE uint16_t CRC_HWA_GetData_U16_H(CRC_Type *const pCrc)
{
return (pCrc->DATA.tDATA_16.H);
}
/**
* @brief get data register(low 16 bits)
*
* @param pCrc CRC instance
*
* @return low 16-bit value
*/
LOCAL_INLINE uint16_t CRC_HWA_GetData_U16_L(CRC_Type *const pCrc)
{
return (pCrc->DATA.tDATA_16.L);
}
/**
* @brief set data swap for writes
*
* @param pCrc CRC instance
* @param eWrDataSwap the CRC_WriteDataSwapType type
*/
LOCAL_INLINE void CRC_HWA_SetWriteDataSwap(CRC_Type *const pCrc, CRC_WriteDataSwapType eWrDataSwap)
{
uint32_t u32RegVal = pCrc->CR;
pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_DSW_MASK)) | CRC_CR_DSW(eWrDataSwap));
}
/**
* @brief set data swap for read
*
* @param pCrc CRC instance
* @param eRdDataSwap the eRdDataSwap type
*/
LOCAL_INLINE void CRC_HWA_SetReadDataSwap(CRC_Type *const pCrc, CRC_ReadDataSwapType eRdDataSwap)
{
uint32_t u32RegVal = pCrc->CR;
pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_DSR_MASK)) | CRC_CR_DSR(eRdDataSwap));
}
/**
* @brief set complement read Of CRC data
*
* @param pCrc CRC instance
* @param eRdDataFXOR the CRC_ReadDataFXORType type
*/
LOCAL_INLINE void CRC_HWA_SetReadDataFXOR(CRC_Type *const pCrc, CRC_ReadDataFXORType eRdDataFXOR)
{
uint32_t u32RegVal = pCrc->CR;
pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_FXOR_MASK)) | CRC_CR_FXOR(eRdDataFXOR));
}
/**
* @brief set width of CRC protocol
*
* @param pCrc CRC instance
* @param eWidth the CRC_BitWidthType type
*/
LOCAL_INLINE void CRC_HWA_SetBitWidth(CRC_Type *const pCrc, CRC_BitWidthType eWidth)
{
uint32_t u32RegVal = pCrc->CR;
pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_TCRC_MASK)) | CRC_CR_TCRC(eWidth));
}
/**
* @brief set width of CRC protocol
*
* @param pCrc CRC instance
* @param eWidth the CRC_BitWidthType type
*/
LOCAL_INLINE void CRC_HWA_Set_8Bit_Width(CRC_Type *const pCrc, CRC_BitWidthType eWidth)
{
uint32_t u32RegVal = pCrc->CR;
pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_TCRC8_MASK)) | CRC_CR_TCRC8(eWidth));
}
/**
* @brief get width of CRC protocol
*
* @param pCrc CRC instance
*/
LOCAL_INLINE CRC_BitWidthType CRC_HWA_GetBitWidth(CRC_Type *const pCrc)
{
uint32_t u32TempVal = (pCrc->CR & ((uint32_t)CRC_CR_TCRC_MASK)) >> CRC_CR_TCRC_SHIFT;
return ((u32TempVal == 0U)?CRC_BIT_16:CRC_BIT_32);
}
/**
* @brief get 8-bit width of CRC protocol
*
* @param pCrc CRC instance
*/
LOCAL_INLINE CRC_BitWidthType CRC_HWA_Get8BitWidth(CRC_Type *const pCrc)
{
uint32 u32TempVal = (pCrc->CR & ((uint32)CRC_CR_TCRC8_MASK)) >> CRC_CR_TCRC8_SHIFT;
return ((u32TempVal == 1U)?CRC_BIT_8:CRC_BIT_INVALID);
}
/**
* @brief get data swap type for read
*
* @param pCrc CRC instance
*/
LOCAL_INLINE CRC_ReadDataSwapType CRC_HWA_GetReadDataSwap(CRC_Type *const pCrc)
{
CRC_ReadDataSwapType eRet = READ_DATASWAP_NONE;
uint32_t u32TempVal;
u32TempVal = (pCrc->CR & ((uint32_t)CRC_CR_DSR_MASK))>>CRC_CR_DSR_SHIFT;
if (u32TempVal == 0U)
{
eRet = READ_DATASWAP_NONE;
}
else if (u32TempVal == 1U)
{
eRet = READ_DATASWAP_BIT;
}
else if (u32TempVal == 2U)
{
eRet = READ_DATASWAP_BIT_BYTE;
}
else if (u32TempVal == 3U)
{
eRet = READ_DATASWAP_BYTE;
}
else
{
/*Noting to do*/
}
return eRet;
}
#endif /* #ifndef _HWA_CRC_H_ */

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/**
* @file HwA_dmamux.h
* @author Flagchip0126
* @brief Hardware access layer for DMAMUX
* @version 0.1.0
* @date 2024-01-15
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_DMAMUX_H_
#define _HWA_DMAMUX_H_
#include "device_header.h"
/**
* @defgroup HwA_dmamux
* @ingroup fc7xxx_driver_dma
* @{
*/
/**
* @brief Structure for the DMA hardware request
*
* Defines the structure for the DMA hardware request collections. The user can configure the
* hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
* of the hardware request varies according to the to SoC.
*/
typedef enum
{
DMA_REQ_DISABLED = 0U,
DMA_REQ_FCIIC0_RX = 1U,
DMA_REQ_FCIIC0_TX = 2U,
DMA_REQ_FCIIC1_RX = 3U,
DMA_REQ_FCIIC1_TX = 4U,
DMA_REQ_FCSPI0_RX = 5U,
DMA_REQ_FCSPI0_TX = 6U,
DMA_REQ_FCSPI1_RX = 7U,
DMA_REQ_FCSPI1_TX = 8U,
DMA_REQ_FCSPI2_RX = 9U,
DMA_REQ_FCSPI2_TX = 10U,
DMA_REQ_FCSPI3_RX = 11U,
DMA_REQ_FCSPI3_TX = 12U,
DMA_REQ_FCSPI4_RX = 13U,
DMA_REQ_FCSPI4_TX = 14U,
DMA_REQ_FCSPI5_RX = 15U,
DMA_REQ_FCSPI5_TX = 16U,
/* 17 ~ 22 reserved */
DMA_REQ_FLEXCAN0 = 23U,
DMA_REQ_FLEXCAN1 = 24U,
DMA_REQ_FLEXCAN2 = 25U,
DMA_REQ_FLEXCAN3 = 26U,
/* 27 ~ 32 reserved */
DMA_REQ_ADC0 = 33U,
DMA_REQ_ADC1 = 34U,
/* 35 ~ 40 reserved */
DMA_REQ_FCUART0_RX = 41U,
DMA_REQ_FCUART0_TX = 42U,
DMA_REQ_FCUART1_RX = 43U,
DMA_REQ_FCUART1_TX = 44U,
DMA_REQ_FCUART2_RX = 45U,
DMA_REQ_FCUART2_TX = 46U,
DMA_REQ_FCUART3_RX = 47U,
DMA_REQ_FCUART3_TX = 48U,
DMA_REQ_FCUART4_RX = 49U,
DMA_REQ_FCUART4_TX = 50U,
DMA_REQ_FCUART5_RX = 51U,
DMA_REQ_FCUART5_TX = 52U,
DMA_REQ_FCUART6_RX = 53U,
DMA_REQ_FCUART6_TX = 54U,
DMA_REQ_FCUART7_RX = 55U,
DMA_REQ_FCUART7_TX = 56U,
/* 57 ~ 58 reserved */
DMA_REQ_TPU0 = 59U,
DMA_REQ_TPU1 = 60U,
DMA_REQ_TPU2 = 61U,
DMA_REQ_TPU3 = 62U,
DMA_REQ_TPU4 = 63U,
DMA_REQ_TPU5 = 64U,
DMA_REQ_TPU6 = 65U,
DMA_REQ_TPU7 = 66U,
DMA_REQ_TPU8 = 67U,
DMA_REQ_TPU9 = 68U,
DMA_REQ_TPU10 = 69U,
DMA_REQ_TPU11 = 70U,
DMA_REQ_TPU12 = 71U,
DMA_REQ_TPU13 = 72U,
DMA_REQ_TPU14 = 73U,
DMA_REQ_TPU15 = 74U,
DMA_REQ_TPU16TO23 = 75U,
DMA_REQ_TPU24TO31 = 76U,
DMA_REQ_PORTA = 77U,
DMA_REQ_PORTB = 78U,
DMA_REQ_PORTC = 79U,
DMA_REQ_PORTD = 80U,
DMA_REQ_PORTE = 81U,
/* 82 ~ 85 reserved */
DMA_REQ_AONTIMER0 = 86U,
DMA_REQ_CMP0 = 87U,
DMA_REQ_CMP1 = 88U,
/* 89 reserved */
DMA_REQ_PTIMER0 = 90U,
DMA_REQ_PTIMER1 = 91U,
/* 92 ~ 97 reserved */
DMA_REQ_FTU0_ALL_CH_OR = 98U,
DMA_REQ_FTU1_ALL_CH_OR = 99U,
DMA_REQ_FTU2_ALL_CH_OR = 100U,
DMA_REQ_FTU3_ALL_CH_OR = 101U,
DMA_REQ_FTU4_ALL_CH_OR = 102U,
DMA_REQ_FTU5_ALL_CH_OR = 103U,
DMA_REQ_FTU6_ALL_CH_OR = 104U,
DMA_REQ_FTU7_ALL_CH_OR = 105U,
/* 106 ~ 109 reserved */
DMA_REQ_SENT0_CH0_FAST = 110U,
DMA_REQ_SENT0_CH1_FAST = 111U,
DMA_REQ_SENT0_CH2_FAST = 112U,
DMA_REQ_SENT0_CH3_FAST = 113U,
/* 114 ~ 117 reserved */
DMA_REQ_SENT0_CH0_SLOW = 118U,
DMA_REQ_SENT0_CH1_SLOW = 119U,
DMA_REQ_SENT0_CH2_SLOW = 120U,
DMA_REQ_SENT0_CH3_SLOW = 121U,
/* 122 ~ 125 reserved */
DMA_REQ_ALWAYS_ENABLE_0 = 126U,
DMA_REQ_ALWAYS_ENABLE_1 = 127U
} DMA_RequestSourceType;
/**
* @brief Get whether DMAMUX is enabled for the specified DMA channel
*
* @param pDmamux the base address of the DMAMUX instance
* @param u8Channel the selected DMA channel
* @return true DMAMUX is enabled for the specified DMA channel
* @return false DMAMUX is disabled for the specified DMA channel
*/
LOCAL_INLINE bool DMAMUX_HWA_GetEnableFlag(const DMAMUX_Type *const pDmamux, uint8_t u8Channel)
{
uint8_t u8TmpVal = (pDmamux->CHCFG[u8Channel] & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT;
return (bool)((u8TmpVal != 0U) ? true : false);
}
/**
* @brief Get the request source for the specified DMA channel
*
* @param pDmamux the base address of the DMAMUX instance
* @param u8Channel the selected DMA channel
* @return DMA_RequestSourceType the request source of the specified DMA channel
*/
LOCAL_INLINE DMA_RequestSourceType DMAMUX_HWA_GetRequestSource(const DMAMUX_Type *const pDmamux, uint8_t u8Channel)
{
uint8_t u8TmpVal = (pDmamux->CHCFG[u8Channel] & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT;
return (DMA_RequestSourceType)u8TmpVal;
}
/**
* @brief Set the request source for the specified DMA channel
*
* @param pDmamux the base address of the DMAMUX instance
* @param u8Channel the selected DMA channel
* @param bEnable whether to enable DMAMUX for the specified DMA channel
* @param eReqSrc the request source to set for the specified DMA channel
*/
LOCAL_INLINE void DMAMUX_HWA_SetRequestSource(DMAMUX_Type *const pDmamux, uint8_t u8Channel, bool bEnable,
DMA_RequestSourceType eReqSrc)
{
pDmamux->CHCFG[u8Channel] = (pDmamux->CHCFG[u8Channel] & ~(DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE_MASK)) |
DMAMUX_CHCFG_ENBL(bEnable) | DMAMUX_CHCFG_SOURCE(eReqSrc);
}
/**
* @brief Get whether periodic trig is enabled for the specified DMA channel
*
* @note Only DMA channel 0~3 supports periodic trig
*
* @param pDmamux the base address of the DMAMUX instance
* @param u8Channel the selected DMA channel
* @return true periodic trig is enabled for the specified DMA channel
* @return true periodic trig is disabled for the specified DMA channel
*/
LOCAL_INLINE bool DMAMUX_HWA_GetPeriodicTrigFlag(const DMAMUX_Type *const pDmamux, uint8_t u8Channel)
{
uint8_t u8TmpVal = (pDmamux->CHTRG & (DMAMUX_CHTRG_TRIG_MASK << u8Channel)) >> u8Channel;
return (bool)((u8TmpVal != 0U) ? true : false);
}
/**
* @brief Set whether to enable periodic trig for the specified DMA channel
*
* @note Only DMA channel 0~3 supports periodic trig
*
* @param pDmamux the base address of the DMAMUX instance
* @param u8Channel the selected DMA channel
* @param bEnable whether to enable periodic trig for the specified DMA channel
*/
LOCAL_INLINE void DMAMUX_HWA_SetPeriodicTrigFlag(DMAMUX_Type *const pDmamux, uint8_t u8Channel, bool bEnable)
{
pDmamux->CHTRG = (pDmamux->CHTRG & ~(DMAMUX_CHTRG_TRIG_MASK << u8Channel)) | (DMAMUX_CHTRG_TRIG(bEnable) << u8Channel);
}
/** @}*/
#endif /* _HWA_DMAMUX_H_ */

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/**
* @file HwA_eim.h
* @author Flagchip
* @brief FC7xxx FCEim register API
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 qxw0100 N/A FC7240 Eim first version
*********************************************************************************/
#ifndef HWA_INCLUDE_HWA_EIM_H_
#define HWA_INCLUDE_HWA_EIM_H_
#include "device_header.h"
#define EIM_MAXCHANNEL 76U /*!< EIM max channel support */
/**
* @defgroup HwA_eim
* @ingroup HwA_eim
* @{
*/
/** @brief EIM channel number configuration type */
typedef enum
{
EIM_MAM0_S0 = 0U, /*!< Channel 0 SCM Matrix Access Monitor Error Inection0(MAM0_S0) */
EIM_MAM0_S1 = 1U, /*!< Channel 1 SCM Matrix Access Monitor Error Inection1(MAM0_S1) */
EIM_MAM0_S2 = 2U, /*!< Channel 2 SCM Matrix Access Monitor Error Inection2(MAM0_S2) */
EIM_MAM0_S3 = 4U, /*!< Channel 4 SCM Matrix Access Monitor Error Inection3(MAM0_S3) */
EIM_MAM0_S4 = 5U, /*!< Channel 5 SCM Matrix Access Monitor Error Inection4(MAM0_S4) */
EIM_MAM0_S5 = 7U, /*!< Channel 7 SCM Matrix Access Monitor Error Inection5(MAM0_S5) */
EIM_MAM0_S6 = 8U, /*!< Channel 8 SCM Matrix Access Monitor Error Inection6(MAM0_S6) */
EIM_MAM0_S7 = 9U, /*!< Channel 9 SCM Matrix Access Monitor Error Inection7(MAM0_S7) */
EIM_MAM0_S8 = 10U, /*!< Channel 10 SCM Matrix Access Monitor Error Inection8(MAM0_S8) */
EIM_CPU0_AHBM = 11U, /*!< Channel 11 SCM Matrix Access Monitor Error Inection9(CPU0_AHBM) */
EIM_CPU0_AHBP = 12U, /*!< Channel 12 SCM Matrix Access Monitor Error Inection10(CPU0_AHBP) */
EIM_HSM = 18U, /*!< Channel 18 SCM Matrix Access Monitor Error Inection12(HSM) */
EIM_DMA0 = 19U, /*!< Channel 19 SCM Matrix Access Monitor Error Inection13(DMA0) */
EIM_CPU0_AHBS = 21U, /*!< Channel 21 SCM Matrix Access Monitor Error Inection11(CPU0_AHBS) */
EIM_CPU0_ITCM = 24U, /*!< Channel 24 CPU0_ITCM */
EIM_CPU0_DTCM0 = 25U, /*!< Channel 25 CPU0_DTCM0 */
EIM_CPU0_DTCM1 = 26U, /*!< Channel 26 CPU0_DTCM1 */
EIM_SRAM0 = 33U, /*!< Channel 33 SRAM0_INJECTION */
EIM_SRAM1 = 34U, /*!< Channel 34 SRAM1_INJECTION */
EIM_CPU0DCACHE_DATA0_01 = 36U, /*!< Channel 36 CPU0_DCACHE_DATA0_01 Injection */
EIM_CPU0DCACHE_DATA0_23 = 37U, /*!< Channel 37 CPU0_DCACHE_DATA0_23 Injection */
EIM_CPU0DCACHE_DATA1_01 = 38U, /*!< Channel 38 CPU0_DCACHE_DATA1_01 Injection */
EIM_CPU0DCACHE_DATA1_23 = 39U, /*!< Channel 39 CPU0_DCACHE_DATA1_23 Injection */
EIM_CPU0DCACHE_TAG_01 = 40U, /*!< Channel 40 CPU0_DCACHE_TAG_01 Injection */
EIM_CPU0DCACHE_TAG_23 = 41U, /*!< Channel 41 CPU0_DCACHE_TAG_23 Injection */
EIM_CPU0ICACHE_DATA0 = 42U, /*!< Channel 42 CPU0_ICACHE_DATA0 Injection */
EIM_CPU0ICACHE_DATA1 = 43U, /*!< Channel 43 CPU0_ICACHE_DATA1 Injection */
EIM_CPU0ICACHE_TAG = 44U, /*!< Channel 44 CPU0_ICACHE_TAG Injection */
EIM_SCM_S5_DOWNSIZE = 63U, /*!< Channel 63 SCM S5 64:32 DownSize Monitor Error Injection */
EIM_DMA0_CFG = 65U, /*!< Channel 65 DMA0_CFG_ECC Injection */
EIM_ROM_ECC = 67U, /*!< Channel 67 ROM_ECC Injection */
EIM_SCM_S5_DOWNSIZE_AHBS = 68U, /*!< Channel 68 SCM S5 DownSize ECC Check with AHBS Error Injection */
EIM_CPU0AHBP_AHBS_MONITOR = 70U, /*!< Channel 70 SCM CPU0 AHBP and AHBS gasket Monitor Error Injection */
EIM_SCM_S8_DOWNSIZE_MONITOR = 75U, /*!< Channel 75 SCM S8 64:32 DownSize Monitor Error Injection */
EIM_RAM_DECODER_MONITOR = 77U, /*!< Channel 77 RAM Decoder Monitor Error Injection */
EIM_AFCB0_MONITOR = 78U, /*!< Channel 78 AFCB0 Monitor Error Injection */
EIM_AFCB1_MONITOR = 79U, /*!< Channel 79 AFCB1 Monitor Error Injection */
EIM_CPU0_OVERLAY_MONITOR = 80U, /*!< Channel 80 CPU0 Overlay Monitor */
EIM_HSM_DRAM = 82U, /*!< Channel 82 HSM DRAM ECC Error Injection */
EIM_HSM_IRAM = 83U, /*!< Channel 83 HSM IRAM ECC Error Injection */
} EIM_ChannelType;
/** @brief EIM Lockstep channel configuration type */
typedef enum
{
EIM_CPU0_LOCKSTEP, /*!< CPU0 LOCKSTEP Injection */
EIM_CHNTYPE_RESVD,
EIM_DMA0_LOCKSTEP, /*!< DMA0 LOCKSTEP Injection */
} EIM_CPU_ChnType;
/** @brief EIM CPU monitor configuration type */
typedef enum
{
EIM_MONITOR0, /*!< CPU0 LOCKSTEP monitor0 Injection */
EIM_MONITOR1, /*!< CPU0 LOCKSTEP monitor1 Injection */
} EIM_MONType;
/** @brief Eim return type. */
typedef enum
{
EIM_STATUS_SUCCESS = 0U, /*!< EIM status success */
EIM_STATUS_PARAM_INVALID = 1U /*!< EIM status parameter invalid */
} EIM_RetType;
/**
* @brief Select the EIM DWP mode
*
*/
typedef enum
{
EIM_CPU0ALLOWED_0 = 0U, /**< cpu0 is allowed */
EIM_CPU0ALLOWED_1 = 1U, /**< cpu0 is allowed */
} EIM_DWPType;
/**
* @brief Select error injection bus sel
*
*/
typedef enum
{
EIM_BUSREG0 = 0U, /**< Sel bus REG0 to injection */
EIM_BUSREG1 = 1U, /**< Sel bus REG1 to injection */
EIM_BUSREG2 = 2U, /**< Sel bus REG2 to injection */
EIM_BUSREG3 = 3U /**< Sel bus REG3 to injection */
} EIM_BUSChnType;
/**
* @brief Select the EIM InitType
*
*/
typedef struct
{
uint8_t u8EimChn;
uint8_t u8BusSelIdx;
uint8_t u8Attreenable;
uint8_t u8AttrPosition;
uint8_t u8Addreenable;
uint8_t u8AddrePosition;
uint8_t u8Data0enable;
uint8_t u8Data0Val;
uint8_t u8Data1enable;
uint8_t u8Data1Val;
} EIM_InitType;
/**
* @brief Select the CPU Lockstep InitType
*
*/
typedef struct
{
uint8_t u8CpuChn;
uint8_t u8Monitor0Set;
uint8_t u8Monitor0Clr;
uint8_t u8Monitor1Set;
uint8_t u8Monitor1Clr;
} EIM_CpuLockType;
/**
* @brief Enable EIM Global Error Injection
*
*/
LOCAL_INLINE void EIM_HWA_EnableGlobalErrorInjection(void)
{
EIM->CR = 1U;
}
/**
* @brief Disable EIM Global Error Injection
*
*/
LOCAL_INLINE void EIM_HWA_DisableGlobalErrorInjection(void)
{
EIM->CR &= ~(uint32_t) EIM_CR_GEIEN_MASK;
}
/**
* @brief get EIM channel N control register, N:0~82
*
* @return EIM channel N control register value
*/
LOCAL_INLINE uint32_t EIM_HWA_Get_CtrlRegn(uint8_t idx)
{
uint32_t u32RegValue;
u32RegValue = EIM->CTRL_REG[idx];
return u32RegValue;
}
/**
* @brief get EIM bus register, idx:0~3
*
* @return EIM bus register value
*/
LOCAL_INLINE uint32_t EIM_HWA_Get_BUSRegn(uint8_t idx)
{
uint32_t u32RegValue;
u32RegValue = EIM->BUS_REG[idx];
return u32RegValue;
}
/**
* @brief Get EIM_CTRL_GEGn register DWP lock status
* @param u8idx index (0~82)
* @return Lock status
*/
LOCAL_INLINE uint8_t EIM_HWA_GetCtrlDWPLockStatus(uint8_t u8idx)
{
uint32_t u32RegValue;
u32RegValue = EIM->CTRL_REG[u8idx];
u32RegValue = (u32RegValue & EIM_CTRL_REG_DWP_LOCK_MASK) >> EIM_CTRL_REG_DWP_LOCK_SHIFT;
return (uint8_t)((u32RegValue != 0U) ? true : false);
}
/**
* @brief set EIM_CTRL_GEGn register DWP lock mode, idx:0~76
*
* @param u8idx index (0~82)
* @param u8DwpMode DWP mode
*/
LOCAL_INLINE void EIM_HWA_Set_CtrlLockMode(uint8_t u8idx, uint8_t u8DwpMode)
{
uint32_t u32Value = EIM->CTRL_REG[u8idx];
EIM->CTRL_REG[u8idx] = ((u32Value & (~(uint32_t)EIM_CTRL_REG_DWP_MASK)) | EIM_CTRL_REG_DWP(u8DwpMode));
}
/**
* @brief set EIM_CTRL_GEGn register DWP lock status, idx:0~76
*
* @param u8idx index (0~82)
* @param u8Enable enable or disable
*/
LOCAL_INLINE void EIM_HWA_CtrlRegnWritePermit(uint8_t u8idx)
{
uint32_t u32Value = EIM->CTRL_REG[u8idx];
EIM->CTRL_REG[u8idx] = (u32Value | EIM_CTRL_REG_DWP_LOCK_MASK);
}
/**
* @brief set eim channel N control register
*
* @param idx index (0~82)
* @param u32RegValue access control value
*/
LOCAL_INLINE void EIM_HWA_Set_CtrlRegn(uint8_t idx, uint32_t u32RegValue)
{
EIM->CTRL_REG[idx] = u32RegValue;
}
/**
* @brief set EIM CPU LOCKSTEP error injection register, idx:0~2
*
* @param idx index (0~2)
* @param u32RegValue access control value
*/
LOCAL_INLINE void EIM_HWA_Set_CPULockstep(uint8_t idx, uint32_t u32RegValue)
{
*((volatile uint32_t *)(&(EIM->CPU0_LOCKSTEP) + (int32_t)idx)) = u32RegValue;
}
/**
* @brief set EIM CPU LOCKSTEP error injection register, idx:0~2
*
* @param idx index (0~2)
* @return access control value
*/
LOCAL_INLINE uint32_t EIM_HWA_Get_CPULockstep(uint8_t idx)
{
return *((volatile uint32_t *)(&(EIM->CPU0_LOCKSTEP) + (int32_t)idx));
}
/**
* @brief set EIM bus register, idx:0~3
*
* @param idx index (0~3)
* @param u32RegValue access control value
*/
LOCAL_INLINE void EIM_HWA_Set_BUSRegn(uint8_t idx, uint32_t u32RegValue)
{
EIM->BUS_REG[idx] |= u32RegValue;
}
/** @}*/
#endif /* HWA_INCLUDE_HWA_EIM_H_ */

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/**
* @file HwA_erm.h
* @author Flagchip
* @brief FC7xxx erm driver type definition and API
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 qxw0100 N/A FC7240 Erm first version
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_ERM_H_
#define HWA_INCLUDE_HWA_ERM_H_
#include "device_header.h"
#define ERM_SR_MASK 0xCCCCCCCCu
/**
* @defgroup HwA_erm
* @ingroup HwA_erm
* @{
*/
/** @brief ERM configuration type */
typedef enum
{
ERM_NONE_CORRECTABLE = 1U, /*!< select Non-correctable interrupt report */
ERM_SINGLE_BIT = 2U /*!< select single correction interrupt report */
} ERM_InterruptType;
/** @brief ERM configuration type */
typedef enum
{
ERM_PFLASH0_ECC = 1U, /*!< PFlash0 ECC Error */
ERM_PFLASH1_ECC = 2U, /*!< PFlash1 ECC Error */
ERM_DFLASH_ECC = 3U, /*!< DFlash ECC error */
ERM_DMACFG0_ECC = 4U, /*!< DMACFG0 ECC Error */
ERM_ROM_ECC = 6U, /*!< ROM ECC Error */
ERM_SYSRAM0_ECC = 8U, /*!< SysRAM0 ECC ERROR */
ERM_SYSRAM1_ECC = 9U, /*!< SysRAM1 ECC ERROR */
ERM_CPU0ITCM_ECC = 11U, /*!< CPU0 ITCM ECC Error */
ERM_CPU0DTCM0_ECC = 12U, /*!< CPU0 DTCM0 ECC Error */
ERM_CPU0DTCM1_ECC = 13U, /*!< CPU0 DTCM1 ECC Error */
ERM_CPU0ICACHE_ECC = 14U, /*!< CPU0 ICACHE ECC Error */
ERM_CPU0DCACHE_ECC = 15U, /*!< CPU0 DCACHE ECC Error */
ERM_HSMDRAM_ECC = 26U, /*!< HSM DRAM ECC Error */
ERM_HSMIRAM_ECC = 27U, /*!< HSM IRAM ECC Error */
} ERM_ChannelType;
/**
* @brief get ERM configuration register 0~3
*
* @return ERM CRn value
*/
LOCAL_INLINE uint32_t ERM_HWA_Get_CRn(uint8_t idx)
{
uint32_t u32RegValue;
u32RegValue = *((volatile uint32_t *)(&(ERM->CR0) + (uint32_t)idx));
return u32RegValue;
}
/**
* @brief get ERM status register 0~3
*
* @return ERM SRn value
*/
LOCAL_INLINE uint32_t ERM_HWA_Get_SRn(uint8_t idx)
{
uint32_t u32RegValue;
u32RegValue = *((volatile uint32_t *)(&(ERM->SR0) + (uint32_t)idx));
return u32RegValue;
}
/**
* @brief get ERM error address register 0~25
*
* @return ERM error address register value
*/
LOCAL_INLINE uint32_t ERM_HWA_Get_EARn(uint8_t idx)
{
uint32_t u32RegValue;
u32RegValue = *((const volatile uint32_t *)(&(ERM->EAR0) + (uint32_t)idx * 0x10UL/4UL));
return u32RegValue;
}
/**
* @brief set erm configuration register
*
* @param idx index (0~3)
* @param u32RegValue access control value
*/
LOCAL_INLINE void ERM_HWA_Set_CRn(uint8_t idx, uint32_t u32RegValue)
{
*((volatile uint32_t *)(&(ERM->CR0) + (int32_t)idx)) = u32RegValue;
}
/**
* @brief set erm error address register
*
* @param idx index (0~3)
* @param u32RegValue access control value
*/
LOCAL_INLINE void ERM_HWA_Set_SRn(uint8_t idx, uint32_t u32RegValue)
{
*((volatile uint32_t *)(&(ERM->SR0) + (int32_t)idx)) = u32RegValue;
}
/** @}*/
#endif /* HWA_INCLUDE_HWA_ERM_H_ */

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/**
* @file HwA_fciic.h
* @author Flagchip
* @brief FC7xxx FCIIC hardware access layer
* @version 0.2.0
* @date 2023-2-14
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022/12/31 qxw0052 N/A First version for FC7300
* 0.2.0 2023/02/14 qxw0052 N/A Fix MISRA issues
******************************************************************************** */
#ifndef _HWA_FCIIC_H_
#define _HWA_FCIIC_H_
#include "device_header.h"
/**
* @addtogroup HwA_fciic
* @{
*/
/* ################################################################################## */
/* ################################### type define ################################## */
/**
* \brief IIC Command Type Enumeration
*
*/
typedef enum
{
FCIIC_TX_CMD_TRANSMIT = 0, /**< FCIIC_TX_CMD_TRANSMIT transmit command */
FCIIC_TX_CMD_RECEIVE, /**< FCIIC_TX_CMD_RECEIVE receive command*/
FCIIC_TX_CMD_STOP, /**< FCIIC_TX_CMD_STOP stop command */
FCIIC_TX_CMD_RECANDDISCARD, /**< FCIIC_TX_CMD_RECANDDISCARD receive and discard data command*/
FCIIC_TX_CMD_STARTANDTRANSMIT, /**< FCIIC_TX_CMD_STARTANDTRANSMIT start and then transmit data */
FCIIC_TX_CMD_STARTANDTRANSMIT_WITHNAK/**< FCIIC_TX_CMD_STARTANDTRANSMIT_WITHNAK start and then transmit and don't care ACK */
} FCIIC_TX_CMDType;
/**
* \brief IIC Master status type enumeration
*
*/
typedef enum
{
FCIIC_MSR_BBF_STATUS = 25U, /**< FCIIC_MSR_BBF_STATUS Bus Busy Flag */
FCIIC_MSR_MBF_STATUS = 24U, /**< FCIIC_MSR_MBF_STATUS Master Busy Flag */
FCIIC_MSR_DMF_STATUS = 14U, /**< FCIIC_MSR_DMF_STATUS Data Match Flag */
FCIIC_MSR_PLTF_STATUS = 13U, /**< FCIIC_MSR_PLTF_STATUS Pin Low Timeout Flag */
FCIIC_MSR_FEF_STATUS = 12U, /**< FCIIC_MSR_FEF_STATUS FIFO Error Flag */
FCIIC_MSR_ALF_STATUS = 11U, /**< FCIIC_MSR_ALF_STATUS Arbitration Lost Flag */
FCIIC_MSR_NDF_STATUS = 10U, /**< FCIIC_MSR_NDF_STATUS NACK Detect Flag */
FCIIC_MSR_SDF_STATUS = 9U, /**< FCIIC_MSR_SDF_STATUS STOP Detect Flag */
FCIIC_MSR_EPF_STATUS = 8U, /**< FCIIC_MSR_EPF_STATUS End Packet Flag */
FCIIC_MSR_RXFPEF_STATUS = 3U, /**< FCIIC_MSR_EPF_STATUS RX FIFO Parity Error Flag */
FCIIC_MSR_TXFPEF_STATUS = 2U, /**< FCIIC_MSR_EPF_STATUS TX FIFO Parity Error Flag */
FCIIC_MSR_RDF_STATUS = 1U, /**< FCIIC_MSR_RDF_STATUS Receive Data Flag */
FCIIC_MSR_TDF_STATUS = 0U /**< FCIIC_MSR_TDF_STATUS Transmit Data Flag */
} FCIIC_MasterStatusType;
/**
* \brief IIC Slave status type enumeration
*
*/
typedef enum
{
FCIIC_SSR_BBF_STATUS = 25U, /**< FCIIC_SSR_BBF_STATUS Bus Busy Flag */
FCIIC_SSR_SBF_STATUS = 24U, /**< FCIIC_SSR_SBF_STATUS Slave Busy Flag */
FCIIC_SSR_SARF_STATUS = 15U, /**< FCIIC_SSR_SARF_STATUS SMBus Alert Response Flag */
FCIIC_SSR_GCF_STATUS = 14U, /**< FCIIC_SSR_GCF_STATUS General Call Flag */
FCIIC_SSR_AM1F_STATUS = 13U, /**< FCIIC_SSR_AM1F_STATUS Address Match 1 Flag */
FCIIC_SSR_AM0F_STATUS = 12U, /**< FCIIC_SSR_AM0F_STATUS Address Match 0 Flag */
FCIIC_SSR_TREF_STATUS = 11U, /**< FCIIC_SSR_TREF_STATUS FIFO Error Flag */
FCIIC_SSR_BEF_STATUS = 10U, /**< FCIIC_SSR_BEF_STATUS Bit Error Flag */
FCIIC_SSR_SDF_STATUS = 9U, /**< FCIIC_SSR_SDF_STATUS STOP Detect Flag */
FCIIC_SSR_RSF_STATUS = 8U, /**< FCIIC_SSR_RSF_STATUS Repeated Start Flag */
FCIIC_SSR_TAF_STATUS = 3U, /**< FCIIC_SSR_TAF_STATUS Transmit ACK Flag */
FCIIC_SSR_AVF_STATUS = 2U, /**< FCIIC_SSR_AVF_STATUS Address Valid Flag */
FCIIC_SSR_RDF_STATUS = 1U, /**< FCIIC_SSR_RDF_STATUS Receive Data Flag */
FCIIC_SSR_TDF_STATUS = 0U, /**< FCIIC_SSR_TDF_STATUS Transmit Data Flag */
} FCIIC_SlaveStatusType;
/**
* \brief Master Transmit Data
*
* \param pFciic IIC instance value
* \param tCmdType is command type
* \param u8Data to transmit
*/
LOCAL_INLINE void FCIIC_Master_HWA_Transmit(FCIIC_Type *pFciic, FCIIC_TX_CMDType tCmdType, uint8_t u8Data)
{
pFciic->MTDR = FCIIC_MTDR_CMD(tCmdType) | FCIIC_MTDR_DATA(u8Data);
}
/**
* \brief Master Receive Data
*
* \param pFciic IIC instance value
* \return the data received
*/
LOCAL_INLINE uint8_t FCIIC_Master_HWA_Receive(FCIIC_Type *pFciic)
{
/* copy data */
return (uint8_t)((uint8_t)(pFciic->MRDR) & 0xFFU);
}
/**
* \brief Get and clear IIC master status
*
* \param pFciic is IIC instance value
* \param eStatus is status type
*/
LOCAL_INLINE void FCIIC_Master_HwA_CheckClearStatus(FCIIC_Type *pFciic, FCIIC_MasterStatusType eStatus)
{
uint32_t u32RetVal;
u32RetVal = (pFciic->MSR >> eStatus) & 0x01U;
if (u32RetVal != 0U)
{
pFciic->MSR |= (1UL << eStatus); /* w1c */
}
}
/**
* \brief This Function is used to get master status
*
* \param pFciic is IIC instance value
* \param eStatus is status type enumeration
* \return Status value 0 or 1 and 1 is OK
*/
LOCAL_INLINE uint8_t FCIIC_Master_HWA_GetStatus(FCIIC_Type *pFciic, FCIIC_MasterStatusType eStatus)
{
uint32_t u32RetVal;
u32RetVal = (pFciic->MSR >> (uint32_t)eStatus) & 0x01U;
return (uint8_t)(u32RetVal == 1U ? 1U : 0U);
}
/**
* \brief This Function is used to clear master status
*
* \param pFciic is IIC instance value
* \param u32Value is the clear bits
*/
LOCAL_INLINE void FCIIC_Master_HWA_ClrStatus(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->MSR |= u32Value;
}
/**
* \brief This Function is used to get slave status
*
* \param pFciic is IIC instance value
* \param eStatus is status type enumeration
* \return Status value 0 or 1 and 1 is OK
*/
LOCAL_INLINE uint8_t FCIIC_Slave_HWA_GetStatus(FCIIC_Type *pFciic, FCIIC_SlaveStatusType eStatus)
{
uint32_t u32RetVal;
u32RetVal = (pFciic->SSR >> (uint32_t)eStatus) & 0x01U;
return (uint8_t)(u32RetVal == 1U ? 1U : 0U);
}
/**
* \brief This Function is used to clear slave status
*
* \param pFciic is IIC instance value
* \param u32Value is the clear bits value
*/
LOCAL_INLINE void FCIIC_Slave_HWA_ClrStatus(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->SSR |= u32Value;
}
/**
* \brief Slave Transmit Data
*
* \param pFciic IIC instance value
* \param u8Data to transmit
*/
LOCAL_INLINE void FCIIC_Slave_HWA_Transmit(FCIIC_Type *pFciic, uint8_t u8Data)
{
pFciic->STDR = FCIIC_STDR_DATA(u8Data);
}
/**
* \brief Slave Get Data
*
* \param pFciic IIC instance value
* \return the data value
*/
LOCAL_INLINE uint8_t FCIIC_Slave_HWA_Receive(FCIIC_Type *pFciic)
{
/* copy data */
return (uint8_t)((uint8_t)(pFciic->SRDR) & 0xFFU);
}
/**
* \brief Enable Receive Interrupt
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Master_HWA_EnableReceiveInterrupt(FCIIC_Type *pFciic)
{
pFciic->MIER |= FCIIC_MIER_RDIE_MASK;
}
/**
* \brief Disable Receive Interrupt
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Master_HWA_DisableReceiveInterrupt(FCIIC_Type *pFciic)
{
pFciic->MIER &= ~FCIIC_MIER_RDIE_MASK;
}
/**
* \brief Enable Error Interrupt
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Master_HWA_EnableErrorInterrupt(FCIIC_Type *pFciic)
{
pFciic->MIER |= FCIIC_MIER_FEIE_MASK;
}
/**
* \brief Disable Error Interrupt
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Master_HWA_DisableErrorInterrupt(FCIIC_Type *pFciic)
{
pFciic->MIER &= FCIIC_MIER_FEIE_MASK;
}
/**
* \brief Get Error Flag
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE uint32_t FCIIC_Master_HWA_GetErrorFlag(FCIIC_Type *pFciic)
{
return pFciic->MSR & FCIIC_MSR_FEF_MASK;
}
/**
* \brief Clr Error Flag
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Master_HWA_ClrErrorFlag(FCIIC_Type *pFciic)
{
pFciic->MSR |= FCIIC_MSR_FEF_MASK;
}
/**
* \brief Enable Transmit Interrupt
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Master_HWA_EnableTransmitInterrupt(FCIIC_Type *pFciic)
{
pFciic->MIER |= FCIIC_MIER_TDIE_MASK;
}
/**
* \brief Disable Transmit Interrupt
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Master_HWA_DisableTransmitInterrupt(FCIIC_Type *pFciic)
{
pFciic->MIER &= ~FCIIC_MIER_TDIE_MASK;
}
/**
* \brief Enable Receive Interrupt
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Slave_HWA_EnableReceiveInterrupt(FCIIC_Type *pFciic)
{
pFciic->SIER |= FCIIC_SIER_RDIE_MASK;
}
/**
* \brief Disable Receive Interrupt
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Slave_HWA_DisableReceiveInterrupt(FCIIC_Type *pFciic)
{
pFciic->SIER &= ~FCIIC_SIER_RDIE_MASK;
}
/**
* \brief Enable Error Interrupt
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Slave_HWA_EnableErrorInterrupt(FCIIC_Type *pFciic)
{
pFciic->SIER |= FCIIC_SIER_TREIE_MASK | FCIIC_SIER_BEIE_MASK ;
}
/**
* \brief Disable Error Interrupt
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Slave_HWA_DisableErrorInterrupt(FCIIC_Type *pFciic)
{
pFciic->SIER &= ~(FCIIC_SIER_TREIE_MASK | FCIIC_SIER_BEIE_MASK);
}
/**
* \brief Get Error Flag
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE uint32_t FCIIC_Slave_HWA_GetErrorFlag(FCIIC_Type *pFciic)
{
return pFciic->SSR & (FCIIC_SSR_TREF_MASK | FCIIC_SSR_BEF_MASK);
}
/**
* \brief Clear Error Flag
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Slave_HWA_ClrErrorFlag(FCIIC_Type *pFciic)
{
pFciic->SSR |= (FCIIC_SSR_TREF_MASK | FCIIC_SSR_BEF_MASK);
}
/**
* \brief Enable Transmit Interrupt
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Slave_HWA_EnableTransmitInterrupt(FCIIC_Type *pFciic)
{
pFciic->SIER |= FCIIC_SIER_TDIE_MASK;
}
/**
* \brief FCIIC Disable Transmit Interrupt
*
* \param pFciic IIC instance value
*/
LOCAL_INLINE void FCIIC_Slave_HWA_DisableTransmitInterrupt(FCIIC_Type *pFciic)
{
pFciic->SIER &= ~FCIIC_SIER_TDIE_MASK; /* Receive Interrupt Enable */
}
/**
* \brief Set FCIIC MCR register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetMcr(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->MCR = u32Value;
}
/**
* \brief Attach FCIIC MCR register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_AttachMcr(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->MCR |= u32Value;
}
/**
* \brief Set FCIIC MDER register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetMder(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->MDER = u32Value;
}
/**
* \brief Set FCIIC MCFGR0 register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetMCFGR0(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->MCFGR0 = u32Value;
}
/**
* \brief Set FCIIC MCFGR1 register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetMCFGR1(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->MCFGR1 = u32Value;
}
/**
* \brief Set FCIIC MCFGR2 register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetMCFGR2(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->MCFGR2 = u32Value;
}
/**
* \brief Set FCIIC MCFGR3 register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetMCFGR3(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->MCFGR3 = u32Value;
}
/**
* \brief Set FCIIC MFCR register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetMFCR(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->MFCR = u32Value;
}
/**
* \brief Set FCIIC MCCR register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetMCCR(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->MCCR = u32Value;
}
/**
* \brief Set FCIIC SDER register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetSDER(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->SDER = u32Value;
}
/**
* \brief Set FCIIC SCFGR1 register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetSCFGR1(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->SCFGR1 = u32Value;
}
/**
* \brief Set FCIIC MCCR register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetSCFGR2(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->SCFGR2 = u32Value;
}
/**
* \brief Set FCIIC MCCR register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetSAMR(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->SAMR = u32Value;
}
/**
* \brief Set FCIIC MCCR register
*
* \param pFciic FCIIC instance value
* \param u32Value written value
*/
LOCAL_INLINE void FCIIC_HWA_SetSCR(FCIIC_Type *pFciic, uint32_t u32Value)
{
pFciic->SCR = u32Value;
}
/** @}*/
#endif /* end for #ifndef _HWA_FCIIC_H_ */

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/**
* @file HwA_fcpit.h
* @author Flagchip
* @brief FC7xxx FCPIT hardware access layer
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip076 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_FCPIT_H_
#define _HWA_FCPIT_H_
#include "device_header.h"
/********* Local typedef ************/
/** @brief Fcpit counter mode, the default mode is 32bit periodic count mode */
typedef enum
{
FCPIT_32PERIODIC_COUNTER = 0,
FCPIT_DUAL_16PERIODIC_COUNTER,
FCPIT_ACCUMULATOR,
FCPIT_32InputCaptue,
} FCPIT_TimerModeType;
/** @brief Fcpit channel number */
typedef enum
{
FCPIT_CHANNEL_0 = 0U,
FCPIT_CHANNEL_1,
FCPIT_CHANNEL_2,
FCPIT_CHANNEL_3
} FCPIT_ChannelType;
/********* Local inline function ************/
/**
* @brief Set FCPIT channel value
*
* @param eChannel FCPIT channel number
* @param u32RegValue Timer value
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelValue(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint32_t u32RegValue)
{
pFcpit->CONTROLS[eChannel].TVAL = u32RegValue;
}
/**
* @brief read FCPIT channel value
*
* @param eChannel FCPIT channel number
* @return Timer value
*/
LOCAL_INLINE uint32_t FCPIT_HWA_ReadChannelValue(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
return (uint32_t)(pFcpit->CONTROLS[eChannel].TVAL );
}
/**
* @brief Configure FCPIT channel
*
* @param eChannel FCPIT channel number
* @param u32RegValue TCTRL register value
*/
LOCAL_INLINE void FCPIT_HWA_ConfigChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint32_t u32RegValue)
{
pFcpit->CONTROLS[eChannel].TCTRL = u32RegValue;
}
/**
* @brief Configure FCPIT module
*
* @param u32RegValue MCR register value
*/
LOCAL_INLINE void FCPIT_HWA_ConfigModule(FCPIT_Type *pFcpit, uint32_t u32RegValue)
{
pFcpit->MCR = u32RegValue;
}
/**
* @brief Read FCPIT module enable
*
* @return MCR register with FCPIT_MCR_M_CEN_MASK
*/
LOCAL_INLINE uint32_t FCPIT_HWA_ReadModuleEnable(FCPIT_Type *pFcpit)
{
return (uint32_t)(pFcpit->MCR & FCPIT_MCR_M_CEN_MASK);
}
/**
* @brief Read FCPIT channel
*
* @param eChannel Channel number
* @return TCTRL register with FCPIT_TCTRL_T_EN_MASK
*/
LOCAL_INLINE uint32_t FCPIT_HWA_ReadChannelEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
return (uint32_t)(pFcpit->CONTROLS[eChannel].TCTRL & FCPIT_TCTRL_T_EN_MASK);
}
/**
* @brief Read FCPIT active interrupt flag
*
* @return FCPIT active interrupt flag
*/
LOCAL_INLINE uint32_t FCPIT_HWA_ReadInterruptFlag(FCPIT_Type *pFcpit)
{
return (pFcpit->MSR);
}
/**
* @brief Read FCPIT enable interrupt flag
*
* @return FCPIT enable interrupt flag
*/
LOCAL_INLINE uint32_t FCPIT_HWA_ReadEnableInterruptFlag(FCPIT_Type *pFcpit)
{
return (pFcpit->MIER);
}
/**
* @brief Set FCPIT channel running on debug mode
*
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelRunOnDebug(FCPIT_Type *pFcpit)
{
pFcpit->MCR |= FCPIT_MCR_DBG_EN_MASK;
}
/**
* @brief Set FCPIT channel running on low power mode
*
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelRunOnLpm(FCPIT_Type *pFcpit)
{
pFcpit->MCR |= FCPIT_MCR_LPM_EN_MASK;
}
/**
* @brief Enable FCPIT module
*
*/
LOCAL_INLINE void FCPIT_HWA_EnableModule(FCPIT_Type *pFcpit)
{
pFcpit->MCR |= FCPIT_MCR_M_CEN_MASK;
}
/**
* @brief Enable FCPIT channel(n) interrupt
*
* @param u32RegValue u32RegValue 0-3 bit indicate TIE0-TIE3
*/
LOCAL_INLINE void FCPIT_HWA_EnableChannelsInterrupt(FCPIT_Type *pFcpit, uint32_t u32RegValue)
{
pFcpit->MIER |= u32RegValue;
}
/**
* @brief Enable FCPIT channel
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_EnableChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_T_EN_MASK;
}
/**
* @brief Enable FCPIT channel
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_SetTimerEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->SETTEN |= (FCPIT_SETTEN_SET_T_EN_0_MASK << (uint32_t)eChannel);
}
/**
* @brief Disable FCPIT channel
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearTimerEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CLRTEN |= (FCPIT_CLRTEN_CLR_T_EN_0_MASK << (uint32_t)eChannel);
}
/**
* @brief Enable FCPIT channel(n) chain mode
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_EnableChannelChainMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_CHAIN_MASK;
}
/**
* @brief Configure FCPIT channel operation mode
*
* @param eChannel FCPIT channel number
* @param eMode FCPIT operation mode
*/
LOCAL_INLINE void FCPIT_HWA_ConfigChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, FCPIT_TimerModeType eMode)
{
uint32_t u32RegValue = pFcpit->CONTROLS[eChannel].TCTRL;
pFcpit->CONTROLS[eChannel].TCTRL = (u32RegValue & ~(uint32_t)FCPIT_TCTRL_MODE_MASK) | FCPIT_TCTRL_MODE(eMode);
}
/**
* @brief Set FCPIT channel start on trigger
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelStartOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TSOT_MASK;
}
/**
* @brief Set FCPIT channel stop on interrupt
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnInterrupt(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TSOI_MASK;
}
/**
* @brief Set FCPIT channel reload on trigger
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelReloadOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TROT_MASK;
}
/**
* @brief Set FCPIT channel trigger source
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelTriggerSrc(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TRG_SRC_MASK;
}
/**
* @brief Select FCPIT channel trigger
*
* @param eChannel FCPIT channel number
* @param u8SelChannel Select channel, range is 0-3
*/
LOCAL_INLINE void FCPIT_HWA_SelectChannelTrigger(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint8_t u8SelChannel)
{
uint32_t u32RegValue = pFcpit->CONTROLS[eChannel].TCTRL;
pFcpit->CONTROLS[eChannel].TCTRL = (u32RegValue & ~(uint32_t)FCPIT_TCTRL_TRG_SEL_MASK) |
FCPIT_TCTRL_TRG_SEL(u8SelChannel);
}
/**
* @brief Set FCPIT channel stop on debug mode
*
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnDebug(FCPIT_Type *pFcpit)
{
pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_DBG_EN_MASK;
}
/**
* @brief Set FCPIT channel stop on low power mode
*
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnLpm(FCPIT_Type *pFcpit)
{
pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_LPM_EN_MASK;
}
/**
* @brief Disable FCPIT module
*
*/
LOCAL_INLINE void FCPIT_HWA_DisableModule(FCPIT_Type *pFcpit)
{
pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_M_CEN_MASK;
}
/**
* @brief Clear FCPIT channel(n) interrupt flag
*
* @param u32RegValue 0-3 bit indicate TIF0-TIF3
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT_Type *pFcpit, uint32_t u32RegValue)
{
pFcpit->MSR |= u32RegValue;
}
/**
* @brief Disable FCPIT channel(n) interrupt
*
* @param u32RegValue u32RegValue 0-3 bit indicate TIE0-TIE3
*/
LOCAL_INLINE void FCPIT_HWA_DisableChannelsInterrupt(FCPIT_Type *pFcpit, uint32_t u32RegValue)
{
pFcpit->MIER &= ~u32RegValue;
}
/**
* @brief Disable FCPIT channel
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_DisableChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_T_EN_MASK;
}
/**
* @brief Disable FCPIT channel chain mode
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_DisableChannelChainMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_CHAIN_MASK;
}
/**
* @brief Clear FCPIT channel operation mode
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_MODE_MASK;
}
/**
* @brief read FCPIT channel operation mode
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE uint32 FCPIT_HWA_ReadChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
return (uint32) ((pFcpit->CONTROLS[eChannel].TCTRL & (uint32_t)FCPIT_TCTRL_MODE_MASK) >>FCPIT_TCTRL_MODE_SHIFT);
}
/**
* @brief Clear FCPIT channel start on trigger
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelStartOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TSOT_MASK;
}
/**
* @brief Clear FCPIT channel stop on interrupt
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelStopOnInterrupt(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TSOI_MASK;
}
/**
* @brief Clear FCPIT channel reload on trigger
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelReloadOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TROT_MASK;
}
/**
* @brief Clear FCPIT channel trigger source
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelTriggerSrc(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TRG_SRC_MASK;
}
/**
* @brief Clear FCPIT channel trigger select
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelTriggerSelect(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TRG_SEL_MASK;
}
#endif /* #ifndef _HWA_FCPIT_H_ */

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@ -0,0 +1,671 @@
/**
* @file HwA_fcsmu.h
* @author Flagchip
* @brief FC7xxx FCSMU hardware access layer
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_FCSMU_H_
#define _HWA_FCSMU_H_
#include "device_header.h"
/**
* @addtogroup HwA_fcsmu
* @{
*
*/
/********* macros ************/
typedef enum
{
FCSMU_OPC_NONE = 0U, /*!< FCSMU operation code none */
FCSMU_OPC_MOVE_TO_CONFIG = 1U, /*!< FCSMU operation code move to configuration state */
FCSMU_OPC_MOVE_TO_NORMAL = 2U, /*!< FCSMU operation code move to normal state */
FCSMU_OPC_CLEAR_FAULT_IMFO = 13U, /*!< FCSMU operation code clear fault channel information register */
FCSMU_OPC_CLEAR_OPS_TO_IDLE = 15U, /*!< FCSMU operation code clear ops to idle */
FCSMU_OPC_LOAD_NVR_CONFIG = 31U /*!< FCSMU operation code load configuration from nvr */
} FCSMU_OperationCodeType;
typedef enum
{
FCSMU_Crc_STATE_IDLE = 0U, /*!< FCSMU crc status idle */
FCSMU_Crc_STATE_BUSY = 1U /*!< FCSMU crc status busy */
} FCSMU_CrcStatusType;
/********* Local typedef ************/
/********* Local inline function ************/
/********* FCSMU Register interface ************/
/**
* @brief Set the fcsmu CTRL register
*
* @param pFcsmu FCSMU Instance
* @param u32Value The register value
*/
LOCAL_INLINE void FCSMU_HWA_SetCrtl(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->CTRL = u32Value;
}
/**
* @brief Get the fcsmu CTRL register
*
* @param pFcsmu FCSMU Instance
* @return CTRL register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetCtrl(FCSMU_Type *const pFcsmu)
{
return pFcsmu->CTRL;
}
/**
* @brief Get the fcsmu CTRL register OPS
*
* @param pFcsmu FCSMU Instance
* @return CTRL register OPS value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetCtrlOps(FCSMU_Type *const pFcsmu)
{
return ((pFcsmu->CTRL & FCSMU_CTRL_OPS_MASK) >> FCSMU_CTRL_OPS_SHIFT);
}
/**
* @brief Set the fcsmu OPRK register
*
* @param pFcsmu FCSMU Instance
* @param u32Value The register value
*/
LOCAL_INLINE void FCSMU_HWA_SetOprk(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->OPRK = u32Value;
}
/**
* @brief Set the fcsmu SOCTRL register
*
* @param pFcsmu FCSMU Instance
* @param u32Value The register value
*/
LOCAL_INLINE void FCSMU_HWA_SetSoctrl(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->SOCTRL = u32Value;
}
/**
* @brief Get the fcsmu SOCTRL register
*
* @param pFcsmu FCSMU Instance
* @return SOCTRL register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetSoctrl(FCSMU_Type *const pFcsmu)
{
return pFcsmu->SOCTRL;
}
/**
* @brief Set the fcsmu FCCR0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value FCCR0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetFccr0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->FCCR0 = u32Value;
}
/**
* @brief Get the fcsmu FCCR0 register
*
* @param pFcsmu FCSMU Instance
* @return FCCR0 register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetFccr0(FCSMU_Type *const pFcsmu)
{
return pFcsmu->FCCR0;
}
/**
* @brief Set the fcsmu FRST0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value FRST0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetFRST0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->FRST0 = u32Value;
}
/**
* @brief Get the fcsmu FRST0 register
*
* @param pFcsmu FCSMU Instance
* @return FRST0 register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetFRST0(FCSMU_Type *const pFcsmu)
{
return pFcsmu->FRST0;
}
/**
* @brief Set the fcsmu FST0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value FST0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetFst0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->FST0 = u32Value;
}
/**
* @brief Get the fcsmu FST0 register
*
* @param pFcsmu FCSMU Instance
* @return FST0 register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetFst0(FCSMU_Type *const pFcsmu)
{
return pFcsmu->FST0;
}
/**
* @brief Set the fcsmu FST_UNLK register
*
* @param pFcsmu FCSMU Instance
* @param u32Value FST_UNLK register value
*/
LOCAL_INLINE void FCSMU_HWA_SetFunlk(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->FST_UNLK = u32Value;
}
/**
* @brief Set the fcsmu FE0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value FE0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetFe0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->FE0 = u32Value;
}
/**
* @brief Get the fcsmu FE0 register
*
* @param pFcsmu FCSMU Instance
* @return FE0 register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetFE0(FCSMU_Type *const pFcsmu)
{
return pFcsmu->FE0;
}
/**
* @brief Set the fcsmu WARNING_EN0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value WARNING_EN0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetWarningEn0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->WARNING_EN0 = u32Value;
}
/**
* @brief Get the fcsmu WARNING_EN0 register
*
* @param pFcsmu FCSMU Instance
* @return WARNING_EN0 register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetWarningEn0(FCSMU_Type *const pFcsmu)
{
return pFcsmu->WARNING_EN0;
}
/**
* @brief Set the fcsmu WARNING_TO register
*
* @param pFcsmu FCSMU Instance
* @param u32Value WARNING_TO register value
*/
LOCAL_INLINE void FCSMU_HWA_SetWaringTo(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->WARNING_TO = u32Value;
}
/**
* @brief Get the fcsmu WARNING_TO register
*
* @param pFcsmu FCSMU Instance
* @return WARNING_TO register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetWaringTo(FCSMU_Type *const pFcsmu)
{
return pFcsmu->WARNING_TO;
}
/**
* @brief Set the fcsmu CFG_TO register
*
* @param pFcsmu FCSMU Instance
* @param u32Value CFG_TO register value
*/
LOCAL_INLINE void FCSMU_HWA_SetCfgTo(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->CFG_TO = u32Value;
}
/**
* @brief Get the fcsmu CFG_TO register
*
* @param pFcsmu FCSMU Instance
* @return CFG_TO register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetCfgTo(FCSMU_Type *const pFcsmu)
{
return pFcsmu->CFG_TO;
}
/**
* @brief Set the fcsmu SOUT_DIAG register
*
* @param pFcsmu FCSMU Instance
* @param u32Value SOUT_DIAG register value
*/
LOCAL_INLINE void FCSMU_HWA_SetSoutDiag(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->SOUT_DIAG = u32Value;
}
/**
* @brief Get the fcsmu SOUT_DIAG register
*
* @param pFcsmu FCSMU Instance
* @return SOUT_DIAG register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetSoutDiag(FCSMU_Type *const pFcsmu)
{
return pFcsmu->SOUT_DIAG;
}
/**
* @brief Get the fcsmu STATUS register
*
* @param pFcsmu FCSMU Instance
* @return STATUS register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetStatus(FCSMU_Type *const pFcsmu)
{
return pFcsmu->STATUS;
}
/**
* @brief Get the fcsmu STATUS register FIF value
*
* @param pFcsmu FCSMU Instance
* @return STATUS register FIF value
*/
LOCAL_INLINE bool FCSMU_HWA_GetFaultState(FCSMU_Type *const pFcsmu)
{
return (pFcsmu->STATUS & FCSMU_STATUS_FIF_MASK) == FCSMU_STATUS_FIF_MASK ? true : false;
}
/**
* @brief Get the fcsmu STATUS register STAT value
*
* @param pFcsmu FCSMU Instance
* @return STATUS register STAT value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetState(FCSMU_Type *const pFcsmu)
{
return (pFcsmu->STATUS & FCSMU_STATUS_STAT_MASK) >> FCSMU_STATUS_STAT_SHIFT;
}
/**
* @brief Get the fcsmu NTW register
*
* @param pFcsmu FCSMU Instance
* @return NTW register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetNtw(FCSMU_Type *const pFcsmu)
{
return pFcsmu->NTW;
}
/**
* @brief Get the fcsmu WTF register
*
* @param pFcsmu FCSMU Instance
* @return WTF register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetWtf(FCSMU_Type *const pFcsmu)
{
return pFcsmu->WTF;
}
/**
* @brief Get the fcsmu NTF register
*
* @param pFcsmu FCSMU Instance
* @return NTF register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetNtf(FCSMU_Type *const pFcsmu)
{
return pFcsmu->NTF;
}
/**
* @brief Get the fcsmu FTW register
*
* @param pFcsmu FCSMU Instance
* @return FTW register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetFtw(FCSMU_Type *const pFcsmu)
{
return pFcsmu->FTW;
}
/**
* @brief Set the fcsmu INJECT register
*
* @param pFcsmu FCSMU Instance
* @param u32Value INJECT register value
*/
LOCAL_INLINE void FCSMU_HWA_SetInject(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->INJECT = u32Value;
}
/**
* @brief Get the fcsmu IRQ_STAT register
*
* @param pFcsmu FCSMU Instance
* @return IRQ_STAT register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetIrqStat(FCSMU_Type *const pFcsmu)
{
return pFcsmu->IRQ_STAT;
}
/**
* @brief Set the fcsmu IRQ_STAT register
*
* @param pFcsmu FCSMU Instance
* @param u32Value IRQ_STAT register value
*/
LOCAL_INLINE void FCSMU_HWA_ClearCfgToIrq(FCSMU_Type *const pFcsmu)
{
pFcsmu->IRQ_STAT |= FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK;
}
/**
* @brief Set the fcsmu IRQ_EN register
*
* @param pFcsmu FCSMU Instance
* @param bEnable IRQ_EN register value
*/
LOCAL_INLINE void FCSMU_HWA_EnableCfgToIrq(FCSMU_Type *const pFcsmu, bool bEnable)
{
pFcsmu->IRQ_EN = (pFcsmu->IRQ_EN & ~FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK) | FCSMU_IRQ_EN_CFG_TO_IEN(bEnable);
}
/**
* @brief Set the fcsmu TEMP_UNLK register
*
* @param pFcsmu FCSMU Instance
* @param u32Value TEMP_UNLK register value
*/
LOCAL_INLINE void FCSMU_HWA_SetTempUnlk(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->TEMP_UNLK = u32Value;
}
/**
* @brief Set the fcsmu PERMNT_LOCK register
*
* @param pFcsmu FCSMU Instance
* @param u32Value PERMNT_LOCK register value
*/
LOCAL_INLINE void FCSMU_HWA_SetPermntLock(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->PERMNT_LOCK = u32Value;
}
/**
* @brief Set the fcsmu STMR register
*
* @param pFcsmu FCSMU Instance
* @param u32Value STMR register value
*/
LOCAL_INLINE void FCSMU_HWA_SetStmr(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->STMR = u32Value;
}
/**
* @brief Set the fcsmu WARNING_IEN0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value WARNING_IEN0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetWarningIen(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->WARNING_IEN0 = u32Value;
}
/**
* @brief Set the fcsmu FAULT_IEN0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value FAULT_IEN0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetFaultIen(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->FAULT_IEN0 = u32Value;
}
/**
* @brief Set the fcsmu SOUT_EN0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value SOUT_EN0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetSoutEn(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->SOUT_EN0 = u32Value;
}
/**
* @brief Get the fcsmu WARNING_TMR register
*
* @param pFcsmu FCSMU Instance
* @return WARNING_TMR register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetWarningTmr(FCSMU_Type *const pFcsmu)
{
return pFcsmu->WARNING_TMR;
}
/**
* @brief Get the fcsmu SM_TMR register
*
* @param pFcsmu FCSMU Instance
* @return SM_TMR register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetSafeModeTmr(FCSMU_Type *const pFcsmu)
{
return pFcsmu->SM_TMR;
}
/**
* @brief Get the fcsmu CFG_TMR register
*
* @param pFcsmu FCSMU Instance
* @return CFG_TMR register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetConfigTmr(FCSMU_Type *const pFcsmu)
{
return pFcsmu->CFG_TMR;
}
/**
* @brief Get the fcsmu SOUT_TMR register
*
* @param pFcsmu FCSMU Instance
* @return SOUT_TMR register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetSoutTmr(FCSMU_Type *const pFcsmu)
{
return pFcsmu->SOUT_TMR;
}
/**
* @brief Set the fcsmu CRC_CTRL register
*
* @param pFcsmu FCSMU Instance
* @param u32Value CRC_CTRL register value
*/
LOCAL_INLINE void FCSMU_HWA_SetCrcCtrl(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->CRC_CTRL = u32Value;
}
/**
* @brief Get the fcsmu CRC_CTRL register BUSY value
*
* @param pFcsmu FCSMU Instance
* @return BUSY value
*/
LOCAL_INLINE bool FCSMU_HWA_GetCrcBusy(FCSMU_Type *const pFcsmu)
{
return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_BUSY_MASK) == FCSMU_CRC_CTRL_BUSY_MASK ? true : false;
}
/**
* @brief Get the fcsmu CRC_CTRL register EF value
*
* @param pFcsmu FCSMU Instance
* @return EF value
*/
LOCAL_INLINE bool FCSMU_HWA_GetCrcErrorFlag(FCSMU_Type *const pFcsmu)
{
return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_EF_MASK) == FCSMU_CRC_CTRL_EF_MASK ? true : false;
}
/**
* @brief Clear the fcsmu CRC_CTRL register EF
*
* @param pFcsmu FCSMU Instance
* @param u32Value CRC_CTRL register value
*/
LOCAL_INLINE void FCSMU_HWA_ClearCrcErrorFlag(FCSMU_Type *const pFcsmu)
{
pFcsmu->CRC_CTRL |= FCSMU_CRC_CTRL_EF_MASK;
}
/**
* @brief Set the fcsmu CRC_CTRL register
*
* @param pFcsmu FCSMU Instance
* @param u32Value CRC_CTRL register value
*/
LOCAL_INLINE void FCSMU_HWA_EnableErrorOutput(FCSMU_Type *const pFcsmu, bool bEnable)
{
pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_EOEN_MASK) | FCSMU_CRC_CTRL_EOEN(bEnable);
}
/**
* @brief Get the fcsmu CRC_CTRL register EOEN value
*
* @param pFcsmu FCSMU Instance
* @return EOEN value
*/
LOCAL_INLINE bool FCSMU_HWA_GetCrcErrorOutputEnable(FCSMU_Type *const pFcsmu)
{
return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_EOEN_MASK) == FCSMU_CRC_CTRL_EOEN_MASK ? true : false;
}
/**
* @brief Set the fcsmu CRC_CTRL register
*
* @param pFcsmu FCSMU Instance
* @param bEnable CRC_CTRL register value
*/
LOCAL_INLINE void FCSMU_HWA_EnableCrcChecker(FCSMU_Type *const pFcsmu, bool bEnable)
{
pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_CHKEN_MASK) | FCSMU_CRC_CTRL_CHKEN(bEnable);
}
/**
* @brief Get the fcsmu CRC_CTRL register CHKEN value
*
* @param pFcsmu FCSMU Instance
* @return CHKEN value
*/
LOCAL_INLINE bool FCSMU_HWA_GetCrcCheckerEnable(FCSMU_Type *const pFcsmu)
{
return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_CHKEN_MASK) == FCSMU_CRC_CTRL_CHKEN_MASK ? true : false;
}
/**
* @brief Set the fcsmu CRC_CTRL register
*
* @param pFcsmu FCSMU Instance
* @param bEnable CRC_CTRL register value
*/
LOCAL_INLINE void FCSMU_HWA_EnableTrigger(FCSMU_Type *const pFcsmu, bool bEnable)
{
pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_TRGEN_MASK) | FCSMU_CRC_CTRL_TRGEN(bEnable);
}
/**
* @brief Get the fcsmu CRC_CTRL register TRGEN value
*
* @param pFcsmu FCSMU Instance
* @return TRGEN value
*/
LOCAL_INLINE bool FCSMU_HWA_GetTriggerEnable(FCSMU_Type *const pFcsmu)
{
return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_TRGEN_MASK) == FCSMU_CRC_CTRL_TRGEN_MASK ? true : false;
}
/**
* @brief Set the fcsmu CRC_CTRL register
*
* @param pFcsmu FCSMU Instance
*/
LOCAL_INLINE void FCSMU_HWA_GenerateCrc(FCSMU_Type *const pFcsmu)
{
pFcsmu->CRC_CTRL |= FCSMU_CRC_CTRL_GEN(true);
}
/**
* @brief Get the fcsmu CRC_RES register
*
* @param pFcsmu FCSMU Instance
* @return CRC_RES register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetCrcResult(FCSMU_Type *const pFcsmu)
{
return pFcsmu->CRC_RES;
}
/** @}*/ /* HwA_fcsmu */
#endif /* #ifndef _HWA_FCSMU_H_ */

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/**
* @file HwA_fcspi.h
* @author Flagchip
* @brief FC7xxx FCSPI hardware access layer
* @version 0.1.0
* @date 2024-01-13
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip071 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_FCSPI_H_
#define _HWA_FCSPI_H_
#include "device_header.h"
/**
* @addtogroup HwA_fcspi
* @{
*/
/**
* @brief Boolean false value definition for type FCSPI_AtomicBoolType used by FCSPI to ensure read/write atomic
*
*/
#define FCSPI_FALSE ((uint8_t)0)
/**
* @brief Boolean true value definition for type FCSPI_AtomicBoolType used by FCSPI to ensure read/write atomic
*
*/
#define FCSPI_TRUE ((uint8_t)1)
/********* Local typedef ************/
/**
* @brief FCSPI Mode type, master or slave.
*/
typedef enum {
FCSPI_MODE_SLAVE = 0,
FCSPI_MODE_MASTER = 1
} FCSPI_MasterSlaveModeType;
/**
* @brief Boolean type for FCSpi
*/
typedef uint8_t FCSPI_AtomicBoolType;
/********* Local inline function ************/
/**
* @brief Read the FCSPI CTRL register value for all.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return FCSPI CTRL regsiter value.
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetCtrlValue(FCSPI_Type *pFCSPI)
{
return pFCSPI->CTRL;
}
/**
* @brief Set FCSPI CTRL value, users should write the whole value to this register.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value which will be written to the CTRL register.
*/
LOCAL_INLINE void FCSPI_HWA_SetCtrlValue(FCSPI_Type *pFCSPI, uint32_t u32Value)
{
pFCSPI->CTRL = u32Value;
}
/**
* @brief Enable the feature of FCSPI hardware, only for starting the feature of SPI module.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
*/
LOCAL_INLINE void FCSPI_HWA_ModuleEnable(FCSPI_Type *pFCSPI)
{
pFCSPI->CTRL |= FCSPI_CTRL_M_EN(1);
}
/**
* @brief Disable the feature of FCSPI, and shutdown the FCSPI module.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
*/
LOCAL_INLINE void FCSPI_HWA_ModuleDisable(FCSPI_Type *pFCSPI)
{
pFCSPI->CTRL &= (~(FCSPI_CTRL_M_EN_MASK));
}
/**
* @brief Getting the FCSPI transfer status by reading the STATUS register.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return the whole status of FCSPI transfer, which can be read in STATUS register.
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetStatus(FCSPI_Type *pFCSPI)
{
return pFCSPI->STATUS;
}
/**
* @brief Clear FCSPI STATUS register for certain function.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void FCSPI_HWA_ClearStatus(FCSPI_Type *pFCSPI, uint32_t u32Value)
{
pFCSPI->STATUS = u32Value;
}
/**
* @brief Get FCSPI INT_EN register value for checking which interrupt is enabled.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return FCSPI INT_EN regsiter value will be returned.
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetIntrruptEnableReg(FCSPI_Type *pFCSPI)
{
return pFCSPI->INT_EN;
}
/**
* @brief Set the FCSPI INT_EN register value for enable or disable some interrupts.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void FCSPI_HWA_SetInterruptEnableReg(FCSPI_Type *pFCSPI, uint32_t u32Value)
{
pFCSPI->INT_EN = u32Value;
}
/**
* @brief Getting the DMA enabled status through the regsiter FCSPI DMA_EN value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return FCSPI DMA_EN regsiter value
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetDMAEnableReg(FCSPI_Type *pFCSPI)
{
return pFCSPI->DMA_EN;
}
/**
* @brief Enable or disable the DMA feature by setting the FCSPI DMA_EN register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void FCSPI_HWA_SetDMAEnableReg(FCSPI_Type *pFCSPI, uint32_t u32Value)
{
pFCSPI->DMA_EN = u32Value;
}
/**
* @brief Get FCSPI CFG0 register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return FCSPI CFG0 regsiter value
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetCFG0Reg(FCSPI_Type *pFCSPI)
{
return pFCSPI->CFG0;
}
/**
* @brief Set FCSPI CFG0 register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void FCSPI_HWA_SetCFG0Reg(FCSPI_Type *pFCSPI, uint32_t u32Value)
{
pFCSPI->CFG0 = u32Value;
}
/**
* @brief Get FCSPI CFG1 register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return FCSPI CFG1 regsiter value
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetCFG1Reg(FCSPI_Type *pFCSPI)
{
return pFCSPI->CFG1;
}
/**
* @brief Set FCSPI CFG1 register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void FCSPI_HWA_SetCFG1Reg(FCSPI_Type *pFCSPI, uint32_t u32Value)
{
pFCSPI->CFG1 = u32Value;
}
/**
* @brief Set the FCSPI to master mode.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
*/
LOCAL_INLINE void FCSPI_HWA_SetMasterMode(FCSPI_Type *pFCSPI)
{
pFCSPI->CFG1 |= FCSPI_CFG1_MASTER(1);
}
/**
* @brief Set FCSPI to slave mode.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
*/
LOCAL_INLINE void FCSPI_HWA_SetSlaveMode(FCSPI_Type *pFCSPI)
{
pFCSPI->CFG1 &= (~(FCSPI_CFG1_MASTER_MASK));
}
/**
* @brief Check the current mode status, master or slave.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return the mode type of FCSPI, FCSPI_MODE_MASTER or FCSPI_MODE_SLAVE
*/
LOCAL_INLINE FCSPI_MasterSlaveModeType FCSPI_HWA_CheckMode(FCSPI_Type *pFCSPI)
{
FCSPI_MasterSlaveModeType eRet = FCSPI_MODE_SLAVE;
if ((pFCSPI->CFG1 & FCSPI_CFG1_MASTER_MASK) == FCSPI_CFG1_MASTER(1))
{
eRet = FCSPI_MODE_MASTER;
}
return eRet;
}
/**
* @brief Get FCSPI MATCH0 register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return FCSPI MATCH0 regsiter value
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetMatch0Value(FCSPI_Type *pFCSPI)
{
return pFCSPI->DATA_MATCH0;
}
/**
* @brief Set FCSPI MATCH0 register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void FCSPI_HWA_SetMatch0Value(FCSPI_Type *pFCSPI, uint32_t u32Value)
{
pFCSPI->DATA_MATCH0 = u32Value;
}
/**
* @brief Get FCSPI MATCH1 register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return FCSPI MATCH1 regsiter value
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetMatch1Value(FCSPI_Type *pFCSPI)
{
return pFCSPI->DATA_MATCH1;
}
/**
* @brief Set FCSPI MATCH1 register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void FCSPI_HWA_SetMatch1Value(FCSPI_Type *pFCSPI, uint32_t u32Value)
{
pFCSPI->DATA_MATCH1 = u32Value;
}
/**
* @brief Get FCSPI CLK_CFG register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return FCSPI CLK_CFG regsiter value
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetClockConfig(FCSPI_Type *pFCSPI)
{
return pFCSPI->CLK_CFG;
}
/**
* @brief Set FCSPI CLK_CFG register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void FCSPI_HWA_SetClockConfig(FCSPI_Type *pFCSPI, uint32_t u32Value)
{
pFCSPI->CLK_CFG = u32Value;
}
/**
* @brief Get FCSPI FIFO_WTM register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return FCSPI FIFO_WTM regsiter value
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetFIFOWaterMark(FCSPI_Type *pFCSPI)
{
return pFCSPI->FIFO_WTM;
}
/**
* @brief Set FCSPI FIFO_WTM register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u8RxWatermark the rx water mark value.
* @param u8TxWatermark the tx water mark value.
*/
LOCAL_INLINE void FCSPI_HWA_SetWatermark(FCSPI_Type *pFCSPI, uint8_t u8RxWatermark, uint8_t u8TxWatermark)
{
uint32_t u32Flag = 0U;
u32Flag |= ((uint32_t)u8RxWatermark << FCSPI_FIFO_WTM_RXWATER_SHIFT);
u32Flag |= ((uint32_t)u8TxWatermark << FCSPI_FIFO_WTM_TXWATER_SHIFT);
pFCSPI->FIFO_WTM = u32Flag;
}
/**
* @brief Get FCSPI RX FIFO count.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return the real count value of rx fifo.
*/
LOCAL_INLINE uint8_t FCSPI_HWA_GetRxFifoStoredCount(FCSPI_Type *pFCSPI)
{
return (uint8_t)(((pFCSPI->FIFO_STATUS) & FCSPI_FIFO_STATUS_RXCNT_MASK) >> FCSPI_FIFO_STATUS_RXCNT_SHIFT);
}
/**
* @brief Get FCSPI TX FIFO count value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return the real count of tx fifo.
*/
LOCAL_INLINE uint8_t FCSPI_HWA_GetTxFifoStoredCount(FCSPI_Type *pFCSPI)
{
return (uint8_t)(((pFCSPI->FIFO_STATUS) & FCSPI_FIFO_STATUS_TXCNT_MASK) >> FCSPI_FIFO_STATUS_TXCNT_SHIFT);
}
/**
* @brief Get FCSPI TR_CTRL register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return FCSPI TR_CTRL regsiter value
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetTxRxControl(FCSPI_Type *pFCSPI)
{
return pFCSPI->TR_CTRL;
}
/**
* @brief Set FCSPI TR_CTRL register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void FCSPI_HWA_SetTxRxControl(FCSPI_Type *pFCSPI, uint32_t u32Value)
{
pFCSPI->TR_CTRL = u32Value;
}
/**
* @brief Set RX enable status in register FCSPI TR_CTRL.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param eEnable FCSPI_TRUE for enabled, FCSPI_FALSE for disable.
*/
LOCAL_INLINE void FCSPI_HWA_EnableRxDataMask(FCSPI_Type *pFCSPI, FCSPI_AtomicBoolType eEnable)
{
if (FCSPI_FALSE == eEnable)
{
pFCSPI->TR_CTRL |= FCSPI_TR_CTRL_RX_MSK_MASK;
}
else
{
pFCSPI->TR_CTRL &= (~(FCSPI_TR_CTRL_RX_MSK_MASK));
}
}
/**
* @brief Set TX enable status in register FCSPI TR_CTRL.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param eEnable FCSPI_TRUE for enabled, FCSPI_FALSE for disable.
*/
LOCAL_INLINE void FCSPI_HWA_EnableTxDataMask(FCSPI_Type *pFCSPI, FCSPI_AtomicBoolType eEnable)
{
if (FCSPI_FALSE == eEnable)
{
pFCSPI->TR_CTRL |= FCSPI_TR_CTRL_TX_MSK_MASK;
}
else
{
pFCSPI->TR_CTRL &= (~(FCSPI_TR_CTRL_TX_MSK_MASK));
}
}
/**
* @brief Set FCSPI TX_DATA register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void FCSPI_HWA_WriteData(FCSPI_Type *pFCSPI, uint32_t u32Value)
{
pFCSPI->TX_DATA = u32Value;
}
/**
* @brief Get the address of FCSPI TX_DATA register,return value is the pointer address of TX_DATA.
*
* @param pFCSPI FCSPI instance，e.g. FCSPI0, FCSPI1.
* @return FCSPI TX_DATA address.
*/
LOCAL_INLINE uint32_t volatile *FCSPI_HWA_GetTxDataAddr(FCSPI_Type *pFCSPI)
{
return (uint32_t volatile *)&(pFCSPI->TX_DATA);
}
/**
* @brief Read FCSPI RX_STATUS register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return FCSPI RX_STATUS regsiter value
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetRxStatus(FCSPI_Type *pFCSPI)
{
return pFCSPI->RX_STATUS;
}
/**
* @brief Read FCSPI RX_DATA register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return FCSPI RX_DATA regsiter value
*/
LOCAL_INLINE uint32_t FCSPI_HWA_ReadData(FCSPI_Type *pFCSPI)
{
return pFCSPI->RX_DATA;
}
/**
* @brief Get the address of FCSPI RX_DATA register,return value is the pointer address of RX_DATA.
*
* @param pFCSPI FCSPI instance，e.g. FCSPI0, FCSPI1.
* @return FCSPI RX_DATA address.
*/
LOCAL_INLINE uint32_t volatile const *FCSPI_HWA_GetRxDataAddr(FCSPI_Type *pFCSPI)
{
return &(pFCSPI->RX_DATA);
}
#endif /* #ifndef _HWA_FCPIT_H_ */

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/**
* @file HwA_fcuart.h
* @author Flagchip
* @brief FC7xxx FCUart register API
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 Flagchip0122 N/A FC7xxx internal release version
********************************************************************************/
#ifndef _HWA_FCUART_H_
#define _HWA_FCUART_H_
#include "device_header.h"
/**
* @addtogroup HwA_fcuart
* @{
*/
/********* Local typedef ************/
/**
* @brief UART STAT register flag
*
*/
typedef enum
{
FCUART_STAT_LBKDIF = (int32_t)FCUART_STAT_LBKDIF_MASK, /**< FCUART_STAT_LBKDIF LIN Break Detect Interrupt Flag, w1c */
FCUART_STAT_RPAEIF = (int32_t)FCUART_STAT_RPAEIF_MASK, /**< FCUART_STAT_RPAEIF RXD Pin Active Edge Interrupt Flag, w1c */
FCUART_STAT_MSBF = (int32_t)FCUART_STAT_MSBF_MASK, /**< FCUART_STAT_MSBF MSB First, RW */
FCUART_STAT_RXINV = (int32_t)FCUART_STAT_RXINV_MASK, /**< FCUART_STAT_RXINV Receive Data Inversion, RW */
FCUART_STAT_RWUID = (int32_t)FCUART_STAT_RWUID_MASK, /**< FCUART_STAT_RWUID Receive Wake Up Idle Detect, RW */
FCUART_STAT_BCGL = (int32_t)FCUART_STAT_BCGL_MASK, /**< FCUART_STAT_BCGL Break Character Generation Length, RW */
FCUART_STAT_LBKDE = (int32_t)FCUART_STAT_LBKDE_MASK, /**< FCUART_STAT_LBKDE LIN Break Detection Enable, RW */
FCUART_STAT_RAF = (int32_t)FCUART_STAT_RAF_MASK, /**< FCUART_STAT_RAF Receiver Active Flag, RO */
FCUART_STAT_TDREF = (int32_t)FCUART_STAT_TDREF_MASK, /**< FCUART_STAT_TDREF Transmit Data Register Empty Flag, RO */
FCUART_STAT_TCF = (int32_t)FCUART_STAT_TCF_MASK, /**< FCUART_STAT_TCF Transmission Complete Flag, RO */
FCUART_STAT_RDRFF = (int32_t)FCUART_STAT_RDRFF_MASK, /**< FCUART_STAT_RDRFF Receive Data Register Full Flag, RO */
FCUART_STAT_IDLEF = (int32_t)FCUART_STAT_IDLEF_MASK, /**< FCUART_STAT_IDLEF Idle Line Flag, w1c */
FCUART_STAT_RORF = (int32_t)FCUART_STAT_RORF_MASK, /**< FCUART_STAT_RORF Receiver Overrun Flag, w1c */
FCUART_STAT_NF = (int32_t)FCUART_STAT_NF_MASK, /**< FCUART_STAT_NF Noise Flag, w1c */
FCUART_STAT_FEF = (int32_t)FCUART_STAT_FEF_MASK, /**< FCUART_STAT_FEF Frame Error Flag, w1c */
FCUART_STAT_PEF = (int32_t)FCUART_STAT_PEF_MASK, /**< FCUART_STAT_PEF Parity Error Flag, w1c */
FCUART_STAT_M0F = (int32_t)FCUART_STAT_M0F_MASK, /**< FCUART_STAT_M0F Match address 0 Flag, w1c */
FCUART_STAT_M1F = (int32_t)FCUART_STAT_M1F_MASK, /**< FCUART_STAT_M1F Match address 1 Flag, w1c */
FCUART_STAT_RPEF = (int32_t)FCUART_STAT_RPEF_MASK, /**< FCUART_STAT_RPEF Receive Data Parity Error Flag, w1c */
FCUART_STAT_TPEF = (int32_t)FCUART_STAT_TPEF_MASK /**< FCUART_STAT_TPEF Transmit Data Parity Error Flag, w1c */
} FCUART_StatType;
/**
* @brief UART data bit length mode
*
*/
typedef enum
{
UART_BITMODE_8 = 0, /**< UART_BITMODE_8 */
UART_BITMODE_9 /**< UART_BITMODE_9 */
} FCUART_BitModeType;
/**
* @brief UART stop bits number
*
*/
typedef enum
{
UART_STOPBIT_NUM_1 = 0, /**< UART_STOPBIT_NUM_1 */
UART_STOPBIT_NUM_2 /**< UART_STOPBIT_NUM_2 */
} FCUART_StopBitNumType;
/**
* @brief UART parity check type
*
*/
typedef enum
{
UART_PARITY_EVEN = 0, /**< UART_PARITY_EVEN */
UART_PARITY_ODD /**< UART_PARITY_ODD */
} FCUART_ParityType;
/********* Local inline function ************/
/**
* @brief Get Stat Flag
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_SetSoftWareReset(FCUART_Type *pUart)
{
pUart->RST |= FCUART_RST_RST_MASK;
pUart->RST &= ~FCUART_RST_RST_MASK;
}
/**
* @brief Get Stat Flag
*
* @param pUart UART instance value
* @param eStatusType stat type
* @return FCUART STAT status flag
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetStatus(FCUART_Type *pUart, FCUART_StatType eStatusType)
{
return (pUart->STAT & (uint32_t)eStatusType);
}
/**
* @brief Clear Stat Flag
*
* @param pUart UART instance value
* @param u32StatusType stat type
*/
LOCAL_INLINE void FCUART_HWA_ClearStatus(FCUART_Type *pUart, uint32_t u32StatusType)
{
pUart->STAT |= u32StatusType;
}
/**
* @brief Enable Interrupt
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_EnableInterrupt(FCUART_Type *pUart, uint32 u32Value)
{
pUart->CTRL |= u32Value; /* Interrupt Enable */
}
/**
* @brief Disable Interrupt
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_DisableInterrupt(FCUART_Type *pUart, uint32 u32Value)
{
pUart->CTRL &= ~u32Value; /* Interrupt Disable */
}
/**
* @brief Enable Receive Interrupt
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_EnableReceiveInterrupt(FCUART_Type *pUart)
{
pUart->CTRL |= FCUART_CTRL_RIE_MASK; /* Receive Interrupt Enable */
}
/**
* @brief Disable Receive Interrupt
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_DisableReceiveInterrupt(FCUART_Type *pUart)
{
pUart->CTRL &= ~FCUART_CTRL_RIE_MASK; /* Receive Interrupt Enable */
}
/**
* @brief Enable Error Interrupt
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_EnableErrorInterrupt(FCUART_Type *pUart)
{
pUart->CTRL |= FCUART_CTRL_ORIE_MASK | /* Overrun Interrupt Enable */
FCUART_CTRL_NEIE_MASK | /* Noise Error Interrupt Enable */
FCUART_CTRL_FEIE_MASK | /* Frame Error Interrupt Enable */
FCUART_CTRL_PEIE_MASK; /* Parity Error Interrupt Enable */
}
/**
* @brief Disable Error Interrupt
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_DisableErrorInterrupt(FCUART_Type *pUart)
{
pUart->CTRL &= ~(FCUART_CTRL_ORIE_MASK | /* Overrun Interrupt Enable */
FCUART_CTRL_NEIE_MASK | /* Noise Error Interrupt Enable */
FCUART_CTRL_FEIE_MASK | /* Frame Error Interrupt Enable */
FCUART_CTRL_PEIE_MASK); /* Parity Error Interrupt Enable */
}
/**
* @brief Set FCUART Ctrl register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_SetCtrl(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->CTRL = u32Value;
}
/**
* @brief Get FCUART Ctrl register
*
* @param pUart UART instance value
* @return Register value
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetCtrl(FCUART_Type *pUart)
{
return pUart->CTRL;
}
/**
* @brief Attach FCUART Ctrl register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_AttachCtrl(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->CTRL |= u32Value;
}
/**
* @brief Set FCUART Baud register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_SetBaud(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->BAUD = u32Value;
}
/**
* @brief Get FCUART baud register
*
* @param pUart UART instance value
* @return Register value
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetBaud(FCUART_Type *pUart)
{
return pUart->BAUD;
}
/**
* @brief Attach FCUART Baud register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_AttachBaud(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->BAUD |= u32Value;
}
/**
* @brief Set FCUART Fifo register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_SetFifo(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->FIFO = u32Value;
}
/**
* @brief Get FCUART fifo register
*
* @param pUart UART instance value
* @return Register value
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetFifo(FCUART_Type *pUart)
{
return pUart->FIFO;
}
/**
* @brief Get FCUART fifo register
*
* @param pUart UART instance value
* @return Register value
*/
LOCAL_INLINE bool FCUART_HWA_GetEnStatusRxFifo(FCUART_Type *pUart)
{
return ((((pUart->FIFO & FCUART_FIFO_RXFEN_MASK) >> FCUART_FIFO_RXFEN_SHIFT) == 1U) ? true: false);
}
/**
* @brief Get FCUART fifo register
*
* @param pUart UART instance value
* @return Register value
*/
LOCAL_INLINE bool FCUART_HWA_GetEnStatusTxFifo(FCUART_Type *pUart)
{
return ((((pUart->FIFO & FCUART_FIFO_TXFEN_MASK) >> FCUART_FIFO_TXFEN_SHIFT) == 1U) ? true: false);
}
/**
* @brief Attach FCUART Fifo register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_AttachFifo(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->FIFO |= u32Value;
}
/**
* @brief Set FCUART WaterMark register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_SetWaterMark(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->WATERMARK = u32Value;
}
/**
* @brief Get FCUART Rx WaterMark
*
* @param pUart UART instance value
* @return Rxcount value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetRxWaterMark(FCUART_Type *pUart)
{
return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_RXWATER_MASK) >> FCUART_WATERMARK_RXWATER_SHIFT));
}
/**
* @brief Get FCUART Tx WaterMark
*
* @param pUart UART instance value
* @return Rxcount value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetTxWaterMark(FCUART_Type *pUart)
{
return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_TXWATER_MASK) >> FCUART_WATERMARK_TXWATER_SHIFT));
}
/**
* @brief Get FCUART WaterMark Rxcount
*
* @param pUart UART instance value
* @return Rxcount value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetFifoRxCount(FCUART_Type *pUart)
{
return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_RXCOUNT_MASK) >> FCUART_WATERMARK_RXCOUNT_SHIFT));
}
/**
* @brief Get FCUART WaterMark Txcount
*
* @param pUart UART instance value
* @return Rxcount value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetFifoTxCount(FCUART_Type *pUart)
{
return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_TXCOUNT_MASK) >> FCUART_WATERMARK_TXCOUNT_SHIFT));
}
/**
* @brief Attach FCUART WaterMark register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_AttachWaterMark(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->WATERMARK |= u32Value;
}
/**
* @brief Set FCUART Match register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_SetMatch(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->MATCH = u32Value;
}
/**
* @brief Attach FCUART Match register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_AttachMatch(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->MATCH |= u32Value;
}
/**
* @brief Get FCUART Match register
*
* @param pUart UART instance value
* @return Register value
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetMatch(FCUART_Type *pUart)
{
return pUart->MATCH;
}
/**
* @brief Read FCUART STAT register
*
* @param pUart UART instance value
* @return STAT read value
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetSTAT(FCUART_Type *pUart)
{
return pUart->STAT;
}
/**
* @brief Write 1 Clear FCUART STAT register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_WriteClearSTAT(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->STAT |= u32Value;
}
/**
* @brief Set Bit Mode and Parity
*
* @param pUart UART instance value
* @param eBitMode is bit mode, 8 or 9 bits
*/
LOCAL_INLINE void FCUART_HWA_SetBitMode(FCUART_Type *pUart, FCUART_BitModeType eBitMode)
{
uint32_t u32RegVal = pUart->CTRL;
pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_BMSEL_MASK)) | FCUART_CTRL_BMSEL(eBitMode));
}
/**
* @brief Set Bit Mode and Parity
*
* @param pUart UART instance value
* @param bParityEnable If enable Parity, set 1U, or set 0U
* @param eParityType Parity type, odd-even
*/
LOCAL_INLINE void FCUART_HWA_SetParity(FCUART_Type *pUart, FCUART_ParityType eParityType, bool bParityEnable)
{
uint32_t u32RegVal = pUart->CTRL;
pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_PE_MASK | FCUART_CTRL_PT_MASK)) |
FCUART_CTRL_PE(bParityEnable) |
FCUART_CTRL_PT(eParityType) );
}
/**
* @brief Set Bit Mode and Parity
*
* @param pUart UART instance value
* @param eStopBit stop bits number 1 or 2 bits
*/
LOCAL_INLINE void FCUART_HWA_SetStopBit(FCUART_Type *pUart, FCUART_StopBitNumType eStopBit)
{
uint32_t u32RegVal = pUart->BAUD;
pUart->BAUD = ((u32RegVal & (~ FCUART_BAUD_SBNS_MASK)) | FCUART_BAUD_SBNS(eStopBit));
}
/**
* @brief Enable Receive DMA
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_EnableReceiveDMA(FCUART_Type *pUart)
{
pUart->BAUD |= FCUART_BAUD_RDMAEN_MASK;
}
/**
* @brief Disable Receive DMA
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_DisableReceiveDMA(FCUART_Type *pUart)
{
pUart->BAUD &= ~FCUART_BAUD_RDMAEN_MASK;
}
/**
* @brief Enable Receive FIFO
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_EnableReceiveFIFO(FCUART_Type *pUart)
{
pUart->FIFO |= FCUART_FIFO_RXFEN_MASK;
}
/**
* @brief Disable Receive FIFO
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_DisableReceiveFIFO(FCUART_Type *pUart)
{
pUart->FIFO &= ~FCUART_FIFO_RXFEN_MASK;
}
/**
* @brief Clear Fifo Overflow/Underflow flag
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_ClearFIFOErrorFlag(FCUART_Type *pUart)
{
pUart->FIFO |= FCUART_FIFO_TXOF_MASK | FCUART_FIFO_RXUF_MASK;
}
/**
* @brief Set Data Value
*
* @param pUart UART instance value
* @param u32Data Set data
*/
LOCAL_INLINE void FCUART_HWA_SetData(FCUART_Type *pUart, uint32_t u32Data)
{
pUart->DATA = u32Data; /* data 32 bit */
}
/**
* @brief Get Data Value
*
* @param pUart UART instance value
* @return the data value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetData(FCUART_Type *pUart)
{
uint8_t u8Data;
u8Data = *((volatile uint8_t *)&pUart->DATA); /* data 32 bit */
return u8Data;
}
/**
* @brief Set R8T9 bit
*
* @param pUart UART instance value
* @return the data value
*/
LOCAL_INLINE void FCUART_HWA_SetR8T9(FCUART_Type *pUart, uint8_t u8Data)
{
uint32_t u32RegVal = pUart->CTRL;
pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_R8T9_MASK)) | FCUART_CTRL_R8T9(u8Data));
}
/**
* @brief Get R8T9 bit
*
* @param pUart UART instance value
* @return the data value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetR8T9(FCUART_Type *pUart)
{
return (uint8_t)((pUart->CTRL & FCUART_CTRL_R8T9_MASK) >> FCUART_CTRL_R8T9_SHIFT);
}
/**
* @brief Set R9T8 bit
*
* @param pUart UART instance value
* @return the data value
*/
LOCAL_INLINE void FCUART_HWA_SetR9T8(FCUART_Type *pUart, uint8_t u8Data)
{
uint32_t u32RegVal = pUart->CTRL;
pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_R9T8_MASK)) | FCUART_CTRL_R9T8(u8Data));
}
/**
* @brief Get R9T8 bit
*
* @param pUart UART instance value
* @return the data value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetR9T8(FCUART_Type *pUart)
{
return (uint8_t)((pUart->CTRL & FCUART_CTRL_R9T8_MASK) >> FCUART_CTRL_R9T8_SHIFT);
}
/**
* @brief Reset the instance by software.
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_SoftwareReset(FCUART_Type *pUart)
{
pUart->RST |= FCUART_RST_RST_MASK;
pUart->RST &= ~FCUART_RST_RST_MASK;
}
/**
* @brief Set fcuart TX Transfer enable or disable.
*
* @param pUart UART instance value
* @param bEnable Enable cmd, false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetTxTransfer(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->CTRL |= FCUART_CTRL_TE_MASK;
}
else
{
pUart->CTRL &= ~FCUART_CTRL_TE_MASK;
}
}
/**
* @brief Set fcuart RX Transfer enable or disable.
*
* @param pUart UART instance value
* @param bEnable Enable cmd, false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetRxTransfer(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->CTRL |= FCUART_CTRL_RE_MASK;
}
else
{
pUart->CTRL &= ~FCUART_CTRL_RE_MASK;
}
}
/**
* @brief Set lin break detect interrupt.
*
* @param pUart UART instance value
* @param bEnable Enable cmd, false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetLinBreakDetectInterrupt(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->BAUD |= FCUART_BAUD_LBKDIE_MASK;
}
else
{
pUart->BAUD &= ~FCUART_BAUD_LBKDIE_MASK;
}
}
/**
* @brief Set lin break detect feature enable.
*
* @param pUart UART instance value
* @param bEnable Enable cmd, false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetLinBreakDetectEnable(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->STAT |= (FCUART_STAT_LBKDE_MASK | FCUART_STAT_BCGL_MASK);
}
else
{
pUart->STAT &= ~(FCUART_STAT_LBKDE_MASK | FCUART_STAT_BCGL_MASK);
}
}
/**
* @brief Send a lin break field.
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_SendBreakField(FCUART_Type *pUart)
{
pUart->DATA |= FCUART_DATA_FETSC_MASK;
}
/**
* @brief Set uart receive active interrupt.
*
* @param pUart UART instance value
* @param bEnable Enable cmd, false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetReceiveActiveInterrupt(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->BAUD |= FCUART_BAUD_RIAEIE_MASK;
}
else
{
pUart->BAUD &= ~FCUART_BAUD_RIAEIE_MASK;
}
}
/**
* @brief Set uart receive active interrupt.
*
* @param pUart UART instance value
* @param return false for disable, true for enable.
*/
LOCAL_INLINE bool FCUART_HWA_GetReceiveActiveInterrupt(FCUART_Type *pUart)
{
bool bRetVal = false;
if (0U != (pUart->BAUD & FCUART_BAUD_RIAEIE_MASK))
{
bRetVal = true;
}
return bRetVal;
}
/**
* @brief Set FCUART inverse feature.
*
* @param pUart UART instance value
* @param bEnable false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetReceiveDataInverse(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->STAT |= FCUART_STAT_RXINV_MASK;
}
else
{
pUart->STAT &= ~FCUART_STAT_RXINV_MASK;
}
}
/**
* @brief Get the FCUART inverse bit value.
*
* @param pUart UART instance value
* @param return false for disable, true for enable.
*/
LOCAL_INLINE bool FCUART_HWA_GetReceiveDataInverse(FCUART_Type *pUart)
{
bool bRetVal = false;
if (0U != (pUart->STAT & FCUART_STAT_RXINV_MASK))
{
bRetVal = true;
}
return bRetVal;
}
/**
* @brief Set the FCUART frame error interrupt.
*
* @param pUart UART instance value
* @param bEnable false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetFrameErrorInterrupt(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->CTRL |= FCUART_CTRL_FEIE_MASK;
}
else
{
pUart->CTRL &= ~FCUART_CTRL_FEIE_MASK;
}
}
/**
* @brief Enable the FCUART loop mode.
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_EnableLoopMode(FCUART_Type *pUart)
{
pUart->CTRL |= FCUART_CTRL_LOOPMS_MASK;
}
/**
* @brief Disable the FCUART loop mode.
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_DisableLoopMode(FCUART_Type *pUart)
{
pUart->CTRL &= ~FCUART_CTRL_LOOPMS_MASK;
}
/**
* \brief Set FCUART MODIR value
*
* \param pUart UART instance value
* \param u32Data Set data
*/
LOCAL_INLINE void FCUART_HWA_SetModir(FCUART_Type *pUart, uint32_t u32Data)
{
pUart->MODIR = u32Data; /* data 32 bit */
}
/**
* \brief Get FCUART MODIR value
*
* \param pUart UART instance value
* \param u32Data Get data
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetModir(FCUART_Type *pUart)
{
return pUart->MODIR ;
}
/** @}*/
#endif /* end for #ifndef _HWA_FCUART_H_ */

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Inc/HwA_flexcan.h Normal file
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Inc/HwA_fmc.h Normal file
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/**
* @file HwA_cpm.h
* @author Flagchip
* @brief FC7xxx FMC register API
* @version 0.1.0
* @date 2024-1-5
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-1-5 Flagchip120 N/A First version for FC7240
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_FMC_H_
#define HWA_INCLUDE_HWA_FMC_H_
#include "device_header.h"
/* ################################################################################## */
/* ####################################### Macro #################################### */
/**
* @brief Read the FMC FAPC0 register value for all.
*
* @param pFMC FMC instance.
* @return FMC FAPC0 regsiter value.
*/
LOCAL_INLINE uint32_t FMC_HWA_GetFAPC0Value(FMC_Type *pFMC)
{
return pFMC->FAPC0;
}
/**
* @brief Set FMC FAPC0 value, users should write the whole value to this register.
*
* @param pFMC FMC instance.
* @param u32Value the value which will be written to the FAPC0 register.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC0Value(FMC_Type *pFMC, uint32_t u32Value)
{
pFMC->FAPC0 = u32Value;
}
/**
* @brief Set FAPC0 data bus prefetch enable
*
* @param bEnable 0:Data prefetching is disabled. 1:Data prefetching is enabled.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC0DataPrefechEnable(FMC_Type *pFMC, bool bEnable)
{
pFMC->FAPC0 = ((pFMC->FAPC0 & (~FMC_FAPC0_DBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC0_DBPEN_SHIFT));
}
/**
* @brief Set FAPC0 code bus prefetch enable
*
* @param bEnable 0:Code prefetching is disabled. 1:Code prefetching is disabled.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC0CodePrefechEnable(FMC_Type *pFMC, bool bEnable)
{
pFMC->FAPC0 = ((pFMC->FAPC0 & (~FMC_FAPC0_CBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC0_CBPEN_SHIFT));
}
/**
* @brief Set FAPC0 data bus read buffers enable
*
* @param bEnable 0:Read data buffers are disabled. 1:Read data buffers are enabled.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC0DataBuffersEnable(FMC_Type *pFMC, bool bEnable)
{
pFMC->FAPC0 = ((pFMC->FAPC0 & (~FMC_FAPC0_DBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC0_DBBEN_SHIFT));
}
/**
* @brief Set FAPC0 code bus read buffers enable
*
* @param bEnable 0:Read code buffers are disabled. 1:Read code buffers are enabled.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC0CodeBuffersEnable(FMC_Type *pFMC, bool bEnable)
{
pFMC->FAPC0 = ((pFMC->FAPC0 & (~FMC_FAPC0_CBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC0_CBBEN_SHIFT));
}
/**
* @brief Set FAPC1 data bus prefetch enable
*
* @param bEnable 0:Data prefetching is disabled. 1:Data prefetching is enabled.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC1DataPrefechEnable(FMC_Type *pFMC, bool bEnable)
{
pFMC->FAPC1 = ((pFMC->FAPC1 & (~FMC_FAPC1_DBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC1_DBPEN_SHIFT));
}
/**
* @brief Set FAPC1 code bus prefetch enable
*
* @param bEnable 0:Code prefetching is disabled. 1:Code prefetching is disabled.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC1CodePrefechEnable(FMC_Type *pFMC, bool bEnable)
{
pFMC->FAPC1 = ((pFMC->FAPC1 & (~FMC_FAPC1_CBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC1_CBPEN_SHIFT));
}
/**
* @brief Set FAPC1 data bus read buffers enable
*
* @param bEnable 0:Read data buffers are disabled. 1:Read data buffers are enabled.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC1DataBuffersEnable(FMC_Type *pFMC, bool bEnable)
{
pFMC->FAPC1 = ((pFMC->FAPC1 & (~FMC_FAPC1_DBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC1_DBBEN_SHIFT));
}
/**
* @brief Set FAPC1 code bus read buffers enable
*
* @param bEnable 0:Read code buffers are disabled. 1:Read code buffers are enabled.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC1CodeBuffersEnable(FMC_Type *pFMC, bool bEnable)
{
pFMC->FAPC1 = ((pFMC->FAPC1 & (~FMC_FAPC1_CBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC1_CBBEN_SHIFT));
}
/**
* @brief Set FAPC2 data bus prefetch enable
*
* @param bEnable 0:Data prefetching is disabled. 1:Data prefetching is enabled.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC2DataPrefechEnable(FMC_Type *pFMC, bool bEnable)
{
pFMC->FAPC2 = ((pFMC->FAPC2 & (~FMC_FAPC2_DBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC2_DBPEN_SHIFT));
}
/**
* @brief Set FAPC2 code bus prefetch enable
*
* @param bEnable 0:Code prefetching is disabled. 1:Code prefetching is disabled.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC2CodePrefechEnable(FMC_Type *pFMC, bool bEnable)
{
pFMC->FAPC2 = ((pFMC->FAPC2 & (~FMC_FAPC2_CBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC2_CBPEN_SHIFT));
}
/**
* @brief Set FAPC2 data bus read buffers enable
*
* @param bEnable 0:Read data buffers are disabled. 1:Read data buffers are enabled.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC2DataBuffersEnable(FMC_Type *pFMC, bool bEnable)
{
pFMC->FAPC2 = ((pFMC->FAPC2 & (~FMC_FAPC2_DBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC2_DBBEN_SHIFT));
}
/**
* @brief Set FAPC2 code bus read buffers enable
*
* @param bEnable 0:Read code buffers are disabled. 1:Read code buffers are enabled.
*/
LOCAL_INLINE void FMC_HWA_SetFAPC2CodeBuffersEnable(FMC_Type *pFMC, bool bEnable)
{
pFMC->FAPC2 = ((pFMC->FAPC2 & (~FMC_FAPC2_CBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC2_CBBEN_SHIFT));
}
/**
* @brief Read the FMC FEEC register value for all.
*
* @param pFMC FMC instance.
* @return FMC FEEC regsiter value.
*/
LOCAL_INLINE uint32_t FMC_HWA_GetFEECValue(FMC_Type *pFMC)
{
return pFMC->FEEC;
}
/**
* @brief Set FMC FEEC value, users should write the whole value to this register.
*
* @param pFMC FMC instance.
* @param u32Value the value which will be written to the FEEC register.
*/
LOCAL_INLINE void FMC_HWA_SetFEECValue(FMC_Type *pFMC, uint32_t u32Value)
{
pFMC->FEEC = u32Value;
}
/**
* @brief Read the FMC FEIPC register value for all.
*
* @param pFMC FMC instance.
* @return FMC FEIPC regsiter value.
*/
LOCAL_INLINE uint32_t FMC_HWA_GetFEIPCValue(FMC_Type *pFMC)
{
return pFMC->FEIPC;
}
/**
* @brief Set the date error position 1 & position 2
*
* @param pFMC FMC instance.
* @param u32Position1 Data error position 1
* @param u32Position2 Data error position 2
*/
LOCAL_INLINE void FMC_HWA_SetInjectPositon(FMC_Type *pFMC, uint32_t u32Position1, uint32_t u32Position2)
{
pFMC->FEIPC = (pFMC->FEIPC & ~FMC_FEIPC_EDATA_POS1_MASK) | FMC_FEIPC_EDATA_POS1(u32Position1);
pFMC->FEIPC = (pFMC->FEIPC & ~FMC_FEIPC_EDATA_POS2_MASK) | FMC_FEIPC_EDATA_POS2(u32Position2);
}
/**
* @brief Read the FMC FPESA_L register value for all.
*
* @param pFMC FMC instance.
* @return FMC FPESA_L regsiter value.
*/
LOCAL_INLINE uint32_t FMC_HWA_GetFPESALValue(FMC_Type *pFMC)
{
return pFMC->FPESA_L;
}
/**
* @brief Set FMC FPESA_L value.
*
* @param pFMC FMC instance.
* @param u32Value the value which will be written to the FPESA_L register.
*/
LOCAL_INLINE void FMC_HWA_SetFPESALValue(FMC_Type *pFMC, uint32_t u32Value)
{
pFMC->FPESA_L = u32Value;
}
/**
* @brief Read the FMC FPESA_P register value for all.
*
* @param pFMC FMC instance.
* @return FMC FPESA_P regsiter value.
*/
LOCAL_INLINE uint32_t FMC_HWA_GetFPESAPValue(FMC_Type *pFMC)
{
return pFMC->FPESA_P;
}
/**
* @brief Read the FMC FB_FPELCK register value for all.
*
* @param pFMC FMC instance.
* @param u8SeqGroupIndex the index of the sequence group
* @return FMC FB_FPELCK regsiter value.
*/
LOCAL_INLINE uint32_t FMC_HWA_GetFBFPELCKValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex)
{
return pFMC->FB_FPELCK[u8SeqGroupIndex];
}
/**
* @brief Set FMC FB_FPELCK value.
*
* @param pFMC FMC instance.
* @param u8SeqGroupIndex the index of the sequence group
* @param u32Value the value which will be written to the FB_FPELCK register.
*/
LOCAL_INLINE void FMC_HWA_SetFBFPELCKValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex, uint32_t u32Value)
{
pFMC->FB_FPELCK[u8SeqGroupIndex] = u32Value;
}
/**
* @brief NVI program erase Lock
*
* @param bEnable 0:unlock. 1:locked.
*/
LOCAL_INLINE void FMC_HWA_SetNVRLocked(FMC_Type *pFMC, bool bEnable)
{
pFMC->FN_FPELCK = ((pFMC->FN_FPELCK & (~FMC_FN_FPELCK_FPELCK_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FN_FPELCK_FPELCK_SHIFT));
}
/**
* @brief Get NVR lock status.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return the NVR status(1:locked 0:unlocked).
*/
LOCAL_INLINE uint8_t FCSPI_HWA_GetNVRLockedStatus(FMC_Type *pFMC)
{
return (uint8_t)(((pFMC->FN_FPELCK) & FMC_FN_FPELCK_FPELCK_MASK) >> FMC_FN_FPELCK_FPELCK_SHIFT);
}
/**
* @brief Read the FMC FB_CPELCK register value for all.
*
* @param pFMC FMC instance.
* @param u8SeqGroupIndex the index of the sequence group
* @return FMC FB_CPELCK regsiter value.
*/
LOCAL_INLINE uint32_t FMC_HWA_GetFBCPELCKValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex)
{
return pFMC->FB_CPELCK[u8SeqGroupIndex];
}
/**
* @brief Set FMC FB_CPELCK value.
*
* @param pFMC FMC instance.
* @param u8SeqGroupIndex the index of the sequence group
* @param u32Value the value which will be written to the FB_CPELCK register.
*/
LOCAL_INLINE void FMC_HWA_SetFBCPELCKValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex, uint32_t u32Value)
{
pFMC->FB_CPELCK[u8SeqGroupIndex] = u32Value;
}
/**
* @brief Set OTA register lock
*
* @param pFMC FMC instance.
* @param u8SeqGroupIndex the index of the sequence group
* @param bEnable 0:OTA_CTRL can be written. 1:OTA_CTRL is locked.
*/
LOCAL_INLINE void FMC_HWA_SetOTALock(FMC_Type *pFMC, uint8_t u8SeqGroupIndex, bool bEnable)
{
pFMC->OTA_CTRL[u8SeqGroupIndex] = ((pFMC->OTA_CTRL[u8SeqGroupIndex] & (~FMC_OTA_CTRL_OTA_LOCK_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_OTA_CTRL_OTA_LOCK_SHIFT));
}
/**
* @brief Set OTA active block
*
* @param pFMC FMC instance.
* @param u8SeqGroupIndex the index of the sequence group
* @param bEnable 0: block0 is the currently active OTA region. 1: block1 is the currently active OTA region.
*/
LOCAL_INLINE void FMC_HWA_SetOTAActive(FMC_Type *pFMC, uint8_t u8SeqGroupIndex, bool bEnable)
{
pFMC->OTA_CTRL[u8SeqGroupIndex] = ((pFMC->OTA_CTRL[u8SeqGroupIndex] & (~FMC_OTA_CTRL_OTA_ACTIVE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_OTA_CTRL_OTA_ACTIVE_SHIFT));
}
/**
* @brief Enable OTA
*
* @param pFMC FMC instance.
* @param u8SeqGroupIndex the index of the sequence group
*/
LOCAL_INLINE void FMC_HWA_SetOTAEnable(FMC_Type *pFMC, uint8_t u8SeqGroupIndex)
{
pFMC->OTA_CTRL[u8SeqGroupIndex] = ((pFMC->OTA_CTRL[u8SeqGroupIndex] & (~FMC_OTA_CTRL_OTA_EN_MASK)) | FMC_OTA_CTRL_OTA_EN(0xA));
}
/**
* @brief Disable OTA
*
* @param pFMC FMC instance.
* @param u8SeqGroupIndex the index of the sequence group
*/
LOCAL_INLINE void FMC_HWA_SetOTADisable(FMC_Type *pFMC, uint8_t u8SeqGroupIndex)
{
pFMC->OTA_CTRL[u8SeqGroupIndex] = ((pFMC->OTA_CTRL[u8SeqGroupIndex] & (~FMC_OTA_CTRL_OTA_EN_MASK)) | FMC_OTA_CTRL_OTA_EN(0x15));
}
/**
* @brief Read the FMC OTA_CTRL register value for all.
*
* @param pFMC FMC instance.
* @param u8SeqGroupIndex the index of the sequence group
* @return FMC OTA_CTRL regsiter value.
*/
LOCAL_INLINE uint32_t FMC_HWA_GetOTACtrlValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex)
{
return pFMC->OTA_CTRL[u8SeqGroupIndex];
}
/**
* @brief Read the FMC OTA_VER_LOC register value for all.
*
* @param pFMC FMC instance.
* @param u8SeqGroupIndex the index of the sequence group
* @return FMC OTA_VER_LOC regsiter value.
*/
LOCAL_INLINE uint32_t FMC_HWA_GetOTAVerLocValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex)
{
return pFMC->OTA_VER_LOC[u8SeqGroupIndex];
}
/**
* @brief Read the FMC OTA_ACT_VER register value for all.
*
* @param pFMC FMC instance.
* @param u8SeqGroupIndex the index of the sequence group
* @return FMC OTA_ACT_VER regsiter value.
*/
LOCAL_INLINE uint32_t FMC_HWA_GetOTAActVerValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex)
{
return pFMC->OTA_ACT_VER[u8SeqGroupIndex];
}
/** @}*/
#endif /* HWA_INCLUDE_HWA_FMC_H_ */

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/**
* @file HwA_fpu.h
* @author Flagchip051
* @brief FC4xxx FPU hardware access layer
* @version 0.1.0
* @date 2024-01-11
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_FPU_H_
#define _HWA_FPU_H_
#include "device_header.h"
/* CPACR Bit Fields */
#define FC7240_SCB_CPACR_CP10_MASK 0x300000u
#define FC7240_SCB_CPACR_CP10_SHIFT 20u
#define FC7240_SCB_CPACR_CP10_WIDTH 2u
#define FC7240_SCB_CPACR_CP10(x) (((uint32_t)(((uint32_t)(x))<<FC7240_SCB_CPACR_CP10_SHIFT))&FC7240_SCB_CPACR_CP10_MASK)
#define FC7240_SCB_CPACR_CP11_MASK 0xC00000u
#define FC7240_SCB_CPACR_CP11_SHIFT 22u
#define FC7240_SCB_CPACR_CP11_WIDTH 2u
#define FC7240_SCB_CPACR_CP11(x) (((uint32_t)(((uint32_t)(x))<<FC7240_SCB_CPACR_CP11_SHIFT))&FC7240_SCB_CPACR_CP11_MASK)
/**
* @brief enable fpu
*
*/
LOCAL_INLINE void FPU_HWA_Enable(void)
{
SCB->CPACR |= (FC7240_SCB_CPACR_CP10(3) | FC7240_SCB_CPACR_CP11(3)); /* set CP10 and CP11 Full Access */
}
/**
* @brief disable fpu
*
*/
LOCAL_INLINE void FPU_HWA_Disable(void)
{
SCB->CPACR &= ~((FC7240_SCB_CPACR_CP10(3) | FC7240_SCB_CPACR_CP11(3))); /* Access denied. Any attempted access generates a NOCP UsageFault */
}
#endif /* HWA_INCLUDE_HWA_FPU_H_ */

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/**
* @file HwA_freqm.h
* @author Flagchip
* @brief FC7xxx freqm hardware access layer
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_FREQM_H_
#define _HWA_FREQM_H_
#include "device_header.h"
/**
* @brief Select the measured clock
*
*/
typedef enum
{
MES_RSVD00 = 0U,
MES_SLOW_CLK = 1U,
MES_PLL1_FEEDBACK = 2U,
MES_PLL0_FEEDBACK = 3U,
MES_SCG_CLKOUT = 4U,
MES_RTC_CLK = 5U,
MES_AON_CLK = 6U,
MES_SIRC128K_CLK = 7U,
MES_RSVD01 = 8U,
MES_RSVD02 = 9U,
MES_FCPIT0_FUN_CLK = 10U,
MES_RSVD03 = 11U,
MES_RSVD04 = 12U,
MES_FCSPI0_FUN_CLK = 13U,
MES_FCSPI1_FUN_CLK = 14U,
MES_FCSPI2_FUN_CLK = 15U,
MES_RSVD05 = 16U,
MES_FCUART0_FUN_CLK = 17U,
MES_FCUART1_FUN_CLK = 18U,
MES_FCUART2_FUN_CLK = 19U,
MES_RSVD06 = 20U,
MES_TRGSEL1_OUT4 = 21U,
MES_FTU0_FUN_CLK = 22U,
MES_FTU1_FUN_CLK = 23U,
MES_RSVD07 = 24U,
MES_FTU2_FUN_CLK = 25U,
MES_FTU3_FUN_CLK = 26U,
MES_ADC0_FUN_CLK = 27U,
MES_RSVD08 = 28U,
MES_ADC1_FUN_CLK = 29U,
MES_RSVD09 = 30U,
MES_RSVD10 = 31U,
MES_RSVD11 = 32U,
MES_FOSC_DIVL = 33U,
MES_SIRC_DIVL = 34U,
MES_FIRC_DIVL = 35U,
MES_RSVD12 = 36U,
MES_PLL1_DIVL = 37U,
MES_PLL0_DIVL = 38U,
MES_RSVD13 = 39U,
MES_RSVD14 = 40U,
MES_FOSC_DIVM = 41U,
MES_SIRC_DIVM = 42U,
MES_FIRC_DIVM = 43U,
MES_RSVD15 = 44U,
MES_PLL1_DIVM = 45U,
MES_PLL0_DIVM = 46U,
MES_RSVD16 = 47U,
MES_RSVD17 = 48U,
MES_FOSC_DIVH = 49U,
MES_SIRC_DIVH = 50U,
MES_FIRC_DIVH = 51U,
MES_RSVD18 = 52U,
MES_PLL1_DIVH = 53U,
MES_PLL0_DIVH = 54U,
MES_RSVD19 = 55U,
MES_RSVD20 = 56U,
MES_SENT0_FUN_CLK = 57U,
MES_FLEXCAN0_FUN_CLK = 58U,
MES_FLEXCAN1_FUN_CLK = 59U,
MES_RSVD21 = 60U,
MES_MSC0_FUN_CLK = 61U,
MES_TPU_FUN_CLK = 62U,
MES_RSVD22 = 63U,
} FREQM_MesClkSelType;
/**
* @brief Set the clock selection
*
* @param pFreqm the base address of the FREQM
* @param eClkSel the clock selection index
*/
LOCAL_INLINE void FREQM_HWA_MesClkSel(FREQM_Type *pFreqm,FREQM_MesClkSelType eClkSel)
{
pFreqm->CTRL &= ~FREQM_CTRL_MES_CLK_SEL_MASK;
pFreqm->CTRL |= FREQM_CTRL_MES_CLK_SEL((uint32_t)eClkSel);
}
/**
* @brief Set the clock selection
*
* @param pFreqm the base address of the FREQM
* @param u8PredivVal the measure clock prediv value
*/
LOCAL_INLINE void FREQM_HWA_MesClk_PreDiv(FREQM_Type *pFreqm,uint8_t u8PredivVal)
{
pFreqm->CTRL &= ~FREQM_CTRL_MES_CLK_PREDIV_MASK;
pFreqm->CTRL |= FREQM_CTRL_MES_CLK_PREDIV(u8PredivVal);
}
/**
* @brief Enable count event interrupt
*
* @param pFreqm the base address of the FREQM
*/
LOCAL_INLINE void FREQM_HWA_EnableCntEventInterrupt(FREQM_Type *pFreqm)
{
pFreqm->CTRL |= FREQM_CTRL_CNT_EVENT_IE_MASK;
}
/**
* @brief Disable count event interrupt
*
* @param pFreqm the base address of the FREQM
*/
LOCAL_INLINE void FREQM_HWA_DisableCntEventInterrupt(FREQM_Type *pFreqm)
{
pFreqm->CTRL &= ~((uint32_t)FREQM_CTRL_CNT_EVENT_IE_MASK);
}
/**
* @brief Set counting length of measure counter
*
* @param pFreqm the base address of the FREQM
* @param u32MesLen counting length of measure counter
*/
LOCAL_INLINE void FREQM_HWA_SetMesLength(FREQM_Type *pFreqm,uint32_t u32MesLen)
{
pFreqm->MES_LENGTH = u32MesLen;
}
/**
* @brief Set timeout value of reference counter
*
* @param pFreqm the base address of the FREQM
* @param u32RefTo timeout value of reference counter
*/
LOCAL_INLINE void FREQM_HWA_SetRefTimeout(FREQM_Type *pFreqm,uint32_t u32RefTo)
{
pFreqm->REF_TIMEOUT = u32RefTo;
}
/**
* @brief Set value of reference counter
*
* @param pFreqm the base address of the FREQM
* @param u32RefCnt value of reference counter
*/
LOCAL_INLINE void FREQM_HWA_SetRefCnt(FREQM_Type *pFreqm,uint32_t u32RefCnt)
{
pFreqm->REF_CNT = u32RefCnt;
}
/**
* @brief Clear counter event interrupt flag
*
* @param pFreqm the base address of the FREQM
*/
LOCAL_INLINE void FREQM_HWA_ClearInterruptFlag(FREQM_Type *pFreqm)
{
pFreqm->CNT_STATUS |= FREQM_CNT_STATUS_CNT_EVENT_MASK;
}
/**
* @brief Get counter event interrupt flag
*
* @param pFreqm the base address of the FREQM
* @param return false for disable, true for enable.
*/
LOCAL_INLINE bool FREQM_HWA_GetInterruptFlag(FREQM_Type *pFreqm)
{
return ((pFreqm->CNT_STATUS & FREQM_CNT_STATUS_CNT_EVENT_MASK) == FREQM_CNT_STATUS_CNT_EVENT_MASK) ? true : false;
}
/**
* @brief Get counter status
*
* @param pFreqm the base address of the FREQM
* @param return Counter status.
*/
LOCAL_INLINE uint32_t FREQM_HWA_GetCntStatus(FREQM_Type *pFreqm)
{
uint32_t u32Mask = (FREQM_CNT_STATUS_MES_CNT_START_MASK|FREQM_CNT_STATUS_MES_CNT_STOP_MASK|FREQM_CNT_STATUS_REF_CNT_STOP_MASK);
return (pFreqm->CNT_STATUS & u32Mask);
}
/**
* @brief Set value of measure counter
*
* @param pFreqm the base address of the FREQM
* @param u32MesCnt value of measure counter
*/
LOCAL_INLINE void FREQM_HWA_SetMesCnt(FREQM_Type *pFreqm,uint32_t u32MesCnt)
{
pFreqm->MES_CNT = u32MesCnt;
}
/**
* @brief Get saved reference counter value
*
* @param pFreqm the base address of the FREQM
* @param return saved reference counter value.
*/
LOCAL_INLINE uint32_t FREQM_HWA_GetRefCntSave(FREQM_Type *pFreqm)
{
return pFreqm->REF_CNT_SAVE;
}
#endif /* #ifndef _HWA_FREQM_H_ */

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/**
* @file HwA_gpio.h
* @author Flagchip
* @brief FC7xxx GPIO hardware access layer
* @version 0.1.0
* @date 2023-02-13
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022-11-18 Flagchip071 N/A First version for FC7xxx
******************************************************************************** */
#ifndef _HWA_GPIO_H_
#define _HWA_GPIO_H_
#include "device_header.h"
/** @brief GPIO initialization level */
typedef enum
{
GPIO_LOW = 0U,
GPIO_HIGH = 1U
} GPIO_PinLevelType;
/**
* @brief Set port data output, port output can set 1 or 0
*
* @param pGpio Gpio instance
* @param u32Value Written value
*/
LOCAL_INLINE void GPIO_HWA_ConfigPortDataOutput(GPIO_Type *pGpio, uint32_t u32Value)
{
pGpio->PDOR = u32Value;
}
/**
* @brief Set pin data output, pin output can set 1 or 0
*
* @param pGpio Gpio instance
* @param u32Pin Pin mask
* @param ePinLevel Pin level
*/
LOCAL_INLINE void GPIO_HWA_ConfigPinDataOutput(GPIO_Type *pGpio, uint32_t u32Pin, GPIO_PinLevelType ePinLevel)
{
if (GPIO_HIGH == ePinLevel)
{
pGpio->PDOR |= GPIO_PDOR_PDO(u32Pin);
}
else
{
pGpio->PDOR &= ~GPIO_PDOR_PDO(u32Pin);
}
}
/**
* @brief Set port output to 1
*
* @param pGpio Gpio instance
* @param u32Value Written value
*/
LOCAL_INLINE void GPIO_HWA_SetPortOutput(GPIO_Type *pGpio, uint32_t u32Value)
{
pGpio->PSOR |= u32Value;
}
/**
* @brief Set port output to 0
*
* @param pGpio Gpio instance
* @param u32Value Written value
*/
LOCAL_INLINE void GPIO_HWA_ClearPortOutput(GPIO_Type *pGpio, uint32_t u32Value)
{
pGpio->PCOR |= u32Value;
}
/**
* @brief Toggle port output
*
* @param pGpio Gpio instance
* @param u32Value Written value
*/
LOCAL_INLINE void GPIO_HWA_TogglePort(GPIO_Type *pGpio, uint32_t u32Value)
{
pGpio->PTOR = u32Value;
}
/**
* @brief Set port direction
*
* @param pGpio Gpio instance
* @param u32Value Written value
*/
LOCAL_INLINE void GPIO_HWA_SetPortDirection(GPIO_Type *pGpio, uint32_t u32Value)
{
pGpio->PDDR = u32Value;
}
/**
* @brief Set port input disable
*
* @param pGpio Gpio instance
* @param u32Value Written value
*/
LOCAL_INLINE void GPIO_HWA_SetPortInputDisable(GPIO_Type *pGpio, uint32_t u32Value)
{
pGpio->PIDR = u32Value;
}
/**
* @brief Read port data output
*
* @param pGpio Gpio instance
* @return PDOR register value
*/
LOCAL_INLINE uint32_t GPIO_HWA_ReadPortDataOutput(GPIO_Type *pGpio)
{
return pGpio->PDOR;
}
/**
* @brief Read port data input, this register indicate data on pad.
*
* @param pGpio Gpio instance
* @return PDIR register value
*/
LOCAL_INLINE uint32_t GPIO_HWA_ReadPortDataInput(GPIO_Type *pGpio)
{
return pGpio->PDIR;
}
/**
* @brief Set pin data output, pin output can set 1 or 0
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_SetPinDataOutput(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PDOR |= (uint32_t)1 << u8Pin;
}
/**
* @brief Set pin output to 1
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_SetPinOutput(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PSOR |= (uint32_t)1 << u8Pin;
}
/**
* @brief Set pin output to 0
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_ClearPinOutput(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PCOR |= (uint32_t)1 << u8Pin;
}
/**
* @brief Toggle pin
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_TogglePin(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PTOR |= (uint32_t)1 << u8Pin;
}
/**
* @brief Set pin direction
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_SetPinDirection(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PDDR |= (uint32_t)1 << u8Pin;
}
/**
* @brief Set pin input disable
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_SetPinInputDisable(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PIDR |= (uint32_t)1 << u8Pin;
}
/**
* @brief Clear pin data output
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_ClearPinDataOutput(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PDOR &= ~((uint32_t)1 << u8Pin);
}
/**
* @brief Clear pin direction
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_ClearPinDirection(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PDDR &= ~((uint32_t)1 << u8Pin);
}
/**
* @brief Clear pin input disable
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_ClearPinInputDisable(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PIDR &= ~((uint32_t)1 << u8Pin);
}
#endif /* #ifndef _HWA_GPIO_H_ */

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/**
* @file HwA_intm.h
* @author Flagchip
* @brief FC7240 INTM HWA driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version
******************************************************************************** */
#ifndef _HWA_INTM_H_
#define _HWA_INTM_H_
#include "device_header.h"
typedef struct
{
__IO uint32_t IRQSELR; /* INTM Interrupt Request Select Register*/
__IO uint32_t LATR; /* INTM Latency Register */
__IO uint32_t TMR; /* INTM Timer Register */
__I uint32_t SR; /* INTM Status Register */
} INTM_MonitorType, *INTM_MonitorMemMapPtr;
/**
* @brief Enable the INTM.
* @param pIntm INTM instance. INTM instance.
* @param bEnable Enable the ITNM.
*/
LOCAL_INLINE void INTM_HWA_Enable(INTM_Type *const pIntm, bool bEnable)
{
if (bEnable)
{
pIntm->ER = INTM_ER_EN_MASK;
}
else
{
pIntm->ER = 0U;
}
}
/**
* @brief Get the instance of interrupt monitor.
* @param pIntm INTM instance.
* @param u8IrqMonitorIndex Interrupt monitor index.
* @return Monitor Instance.
*/
LOCAL_INLINE INTM_MonitorType *INTM_HWA_GetIrqMonitor(INTM_Type *const pIntm, uint8_t u8IrqMonitorIndex)
{
return (INTM_MonitorType *)((uint32_t) & (pIntm->IRQSELR0) + (uint32_t)u8IrqMonitorIndex * 0x10U);
}
/**
* @brief Set the interrupt acknowledge.
* @param pIntm INTM instance.
* @param u16IrqNum Interrupt number to be monitored.
*/
LOCAL_INLINE void INTM_HWA_SetIACKR(INTM_Type *const pIntm, uint16_t u16IrqNum)
{
pIntm->IACKR = u16IrqNum;
}
/**
* @brief Set which interrupt to be monoterd.
* @param pIntm INTM instance.
* @param u16IrqNum Interrupt number to be monitored.
*/
LOCAL_INLINE void INTM_HWA_SetIRQReqNum(INTM_MonitorType *const pIrqMon, uint16_t u16IrqNum)
{
pIrqMon->IRQSELR = u16IrqNum;
}
/**
* @brief Enable reset when interrupt delays overtime.
* @param pIrqMon Interrupt monitor instance.
* @param bEnable Enable reset.
*/
LOCAL_INLINE void INTM_HWA_EnableReset(INTM_MonitorType *const pIrqMon, bool bEnable)
{
pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_RSTE_MASK) | INTM_IRQSELR_RSTE(bEnable);
}
/**
* @brief Enable interrupt when monitored interrupt delays overtime.
* @param pIrqMon Interrupt monitor instance.
* @param bEnable Enabel the interrupt.
*/
LOCAL_INLINE void INTM_HWA_EnableInterrupt(INTM_MonitorType *const pIrqMon, bool bEnable)
{
pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_INTE_MASK) | INTM_IRQSELR_INTE(bEnable);
}
/**
* @brief Enable inactive mode.
* @param pIrqMon Interrupt monitor instance.
* @param bEnable Enable inactive mode.
*/
LOCAL_INLINE void INTM_HWA_EnableInactiveMode(INTM_MonitorType *const pIrqMon, bool bEnable)
{
pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_IACTE_MASK) | INTM_IRQSELR_IACTE(bEnable);
__asm volatile(
"dmb \n"
"ldr r8, [%[IRQSELR]] \n"/* Must Read IRQSELR after set. */
: : [IRQSELR] "r"(&pIrqMon->IRQSELR) : "r8", "memory"
);
}
/**
* @brief Start the inactive mode.
* @param pIrqMon Interrupt monitor instance.
*/
LOCAL_INLINE void INTM_HWA_StartInactiveMode(INTM_MonitorType *const pIrqMon)
{
pIrqMon->IRQSELR |= INTM_IRQSELR_IACTST_MASK;
__asm volatile(
"dmb \n"
"ldr r8, [%[IRQSELR]] \n"/* Must Read IRQSELR after set. */
: : [IRQSELR] "r"(&pIrqMon->IRQSELR) : "r8", "memory"
);
}
/**
* @brief Stop the inactive mode.
* @param pIrqMon Interrupt monitor instance.
* @param bEnable
*/
LOCAL_INLINE void INTM_HWA_StopInactiveMode(INTM_MonitorType *const pIrqMon)
{
pIrqMon->IRQSELR &= ~INTM_IRQSELR_IACTST_MASK;
}
/**
* @brief Set the timeout value of interrupt.
* @param pIrqMon Interrupt monitor instance.
* @param u32Latency the timeout value of interrupt monitor.
*/
LOCAL_INLINE void INTM_HWA_SetLatency(INTM_MonitorType *const pIrqMon, uint32_t u32Latency)
{
pIrqMon->LATR = u32Latency;
}
/**
* @brief Get the value of timer.
* @param pIrqMon Interrupt monitor instance.
* @return Timer value
*/
LOCAL_INLINE uint32_t INTM_HWA_GetTimerCounter(INTM_MonitorType *const pIrqMon)
{
return pIrqMon->TMR;
}
/**
* @brief Set the value of timer.
* @param pIrqMon Interrupt monitor instance.
* @param u32Value The value to be set.
*/
LOCAL_INLINE void INTM_HWA_SetTimerCounter(INTM_MonitorType *const pIrqMon, uint32_t u32Value)
{
pIrqMon->TMR = u32Value;
}
/**
* @brief Read interrupt status.
* @param pIrqMon Interrupt monitor instance.
* @return Interrupt status.
*/
LOCAL_INLINE bool INTM_HWA_ReadStatus(INTM_MonitorType *const pIrqMon)
{
return (pIrqMon->SR & INTM_SR_MASK) == INTM_SR_MASK ? true : false;
}
#endif /*#ifndef _HWA_INTM_H_*/

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/**
* @file HwA_ism.h
* @author Flagchip084
* @brief FC7xxx ISM hardware access layer
* @version 0.2.0
* @date 2023-02-13
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022-11-18 Flagchip084 N/A First version for FC7xxx
* 0.2.0 2023-02-13 Flagchip084 N/A FC7xxx release version
******************************************************************************** */
#ifndef _HWA_ISM_H_
#define _HWA_ISM_H_
#include "device_header.h"
/**
* @addtogroup HwA_ism
* @{
*
*/
/********* macros ************/
/********* Local typedef ************/
typedef struct
{
__IO uint32_t FPC_STATUS;
__IO uint32_t FPC_CTRL;
__IO uint32_t FPC_CONFIG;
__IO uint32_t FPC_TIMER;
} FPC_Type, *FPC_MemMapPtr;
typedef struct
{
__IO uint32_t LAM_STATUS;
__IO uint32_t LAM_CTRL;
__IO uint32_t LAM_CONFIG;
__IO uint32_t LAM_CONTER;
} LAM_Type, *LAM_MemMapPtr;
typedef enum
{
ISM_FPC_DETECT_NO_FILTER = 0U, /*No filter mode. Copy input to SOUT directly, which is LAM input.*/
ISM_FPC_DETECT_IMMI_FILTER = 1U, /*Immediate filter mode.*/
ISM_FPC_DETECT_DELAY_MODE = 2U, /*Delay mode.*/
ISM_FPC_DETECT_PRESCALER_MODE = 3U /*Prescaler mode.*/
} ISM_FPC_EdgeDetectModeType;
typedef enum
{
ISM_FPC_DELAY_FIXED0 = 0U, /*Fixed delay mode.*/
ISM_FPC_DELAY_FIXED1 = 1U, /*Fixed delay mode.*/
ISM_FPC_DELAY_SMART_DELAY0 = 2U, /*Smart delay mode. The counter is decremented when a glitch happens.*/
ISM_FPC_DELAY_SMART_DELAY1 = 3U /*Smart delay mode. The counter is reset when a glitch happens.*/
} ISM_FPC_EdgeDelayModeType;
typedef enum
{
ISM_LAM_EVT_WIN_NON_INVERT = 0U, /*Event window non-inverted.*/
ISM_LAM_EVT_WIN_INVERT = 1U /*Event window inverted.*/
} ISM_LAM_InvertEventWindowType;
typedef enum
{
ISM_LAM_NTR_CLEAR_NTR_GATE = 0U, /*Neither edge used to clear the event window counter. Neither edge used to gate event generation.*/
ISM_LAM_POS_CLEAR_NTR_GATE = 1U, /*Positive edge used to clear the event window counter. Neither edge used to gate event generation.*/
ISM_LAM_NEG_CLEAR_NTR_GATE = 2U, /*Negative edge used to clear the event window counter. Neither edge used to gate event generation.*/
ISM_LAM_ETR_CLEAR_NTR_GATE = 3U, /*Either edge used to clear the event window counter. Neither edge used to gate event generation.*/
ISM_LAM_NTR_CLEAR_POS_GATE = 4U, /*Neither edge used to clear the event window counter. Positive edge used to gate event generation.*/
ISM_LAM_POS_CLEAR_POS_GATE = 5U, /*Positive edge used to clear the event window counter. Positive edge used to gate event generation.*/
ISM_LAM_NEG_CLEAR_POS_GATE = 6U, /*Negative edge used to clear the event window counter. Positive edge used to gate event generation.*/
ISM_LAM_ETR_CLEAR_POS_GATE = 7U, /*Either edge used to clear the event window counter. Positive edge used to gate event generation.*/
ISM_LAM_NTR_CLEAR_NEG_GATE = 8U, /*Neither edge used to clear the event window counter. Negative edge used to gate event generation.*/
ISM_LAM_POS_CLEAR_NEG_GATE = 9U, /*Positive edge used to clear the event window counter. Negative edge used to gate event generation.*/
ISM_LAM_NEG_CLEAR_NEG_GATE = 10U, /*Negative edge used to clear the event window counter. Negative edge used to gate event generation.*/
ISM_LAM_ETR_CLEAR_NEG_GATE = 11U, /*Either edge used to clear the event window counter. Negative edge used to gate event generation.*/
ISM_LAM_NTR_CLEAR_ETR_GATE = 12U, /*Neither edge used to clear the event window counter. Either edge used to gate event generation.*/
ISM_LAM_POS_CLEAR_ETR_GATE = 13U, /*Positive edge used to clear the event window counter. Either edge used to gate event generation.*/
ISM_LAM_NEG_CLEAR_ETR_GATE = 14U, /*Negative edge used to clear the event window counter. Either edge used to gate event generation.*/
ISM_LAM_ETR_CLEAR_ETR_GATE = 15U /*Either edge used to clear the event window counter. Either edge used to gate event generation.*/
} ISM_LAM_EventWindowEdgeType;
typedef enum
{
ISM_LAM_EVT_WIN_SEL_REF = 0U, /*Event window generation is determined from the reference signal.*/
ISM_LAM_EVT_WIN_SEL_MON = 1U /*Event window generation is determined from the monitor signal.*/
} ISM_LAM_EventWindowSelectType;
typedef enum
{
ISM_LAM_RUN_FREE = 0U, /*Event window generation is free-running.*/
ISM_LAM_RUN_GATED = 1U /*Event window generation is gated with the monitor or reference signal.*/
} ISM_LAM_RunModeSelectType;
typedef enum
{
ISM_LAM_SRC_FPC_MON = 0U, /* Monitor signal is sourced directly from FPC monitor channel.*/
ISM_LAM_SRC_EXORD_FPC_REF = 1U /* Monitor signal is EXOR'd with FPC reference channel.*/
} ISM_LAM_MonitorSourceType;
typedef enum
{
ISM_LAM_FPC_MON_NON_INVERT = 0U, /* Do not invert the monitor signal from FPC.*/
ISM_LAM_FPC_MON_INVERT = 1U /* Invert the monitor signal from FPC.*/
} ISM_LAM_InvertMonitorType;
typedef enum
{
ISM_LAM_FPC_REF_NON_INVERT = 0U, /* Do not invert the reference signal from FPC.*/
ISM_LAM_FPC_REF_INVERT = 1U /* Invert the reference signal from FPC.*/
} ISM_LAM_InvertReferenceType;
/********* Local inline function ************/
/********* ISM Register interface ************/
/**
* @brief Get ISM ECM count
*
* @param pIsm ISM Instance
* @return ECM count
*/
LOCAL_INLINE uint8_t ISM_HWA_PARAM_ECMC(ISM_Type *const pIsm)
{
return (uint8_t)((pIsm->PARAM & ISM_PARAM_ECMC_MASK) >> ISM_PARAM_ECMC_SHIFT);
}
/**
* @brief Get ISM FPC count
*
* @param pIsm ISM Instance
* @return FPC count
*/
LOCAL_INLINE uint8_t ISM_HWA_PARAM_FPC(ISM_Type *const pIsm)
{
return (uint8_t)((pIsm->PARAM & ISM_PARAM_FPC_MASK) >> ISM_PARAM_FPC_SHIFT);
}
/**
* @brief Get ISM LAM count
*
* @param pIsm ISM Instance
* @return LAM count
*/
LOCAL_INLINE uint8_t ISM_HWA_PARAM_LAM(ISM_Type *const pIsm)
{
return (uint8_t)((pIsm->PARAM & ISM_PARAM_LAM_MASK) >> ISM_PARAM_LAM_SHIFT);
}
/**
* @brief Enable ISM
*
* @param pIsm ISM Instance
* @param bEnable EN value
*/
LOCAL_INLINE void ISM_HWA_Enable(ISM_Type *const pIsm, bool bEnable)
{
pIsm->CTRL = (pIsm->CTRL & ~ISM_CTRL_EN_MASK) | ISM_CTRL_EN(bEnable);
}
/**
* @brief Enable ISM Interrupt
*
* @param pIsm ISM Instance
* @param bEnable IEN value
*/
LOCAL_INLINE void ISM_HWA_InterruptEnable(ISM_Type *const pIsm, bool bEnable)
{
pIsm->CTRL = (pIsm->CTRL & ~ISM_CTRL_IEN_MASK) | ISM_CTRL_IEN(bEnable);
}
/**
* @brief Get ECS of ISM_E_STATUS register
*
* @param pIsm ISM Instance
* @return ECS value
*/
LOCAL_INLINE uint8_t ISM_HWA_GetEcs(ISM_Type *const pIsm)
{
return (uint8_t)((pIsm->E_STATUS & ISM_E_STATUS_ECS_MASK) >> ISM_E_STATUS_ECS_SHIFT);
}
/**
* @brief Clear ECS of ISM_E_STATUS register
*
* @param pIsm ISM Instance
* @param u32Channels ECM channels
*/
LOCAL_INLINE void ISM_HWA_ClearEcs(ISM_Type *const pIsm, uint32_t u32Channels)
{
pIsm->E_STATUS = (u32Channels << ISM_E_STATUS_ECS_SHIFT) & ISM_E_STATUS_ECS_MASK;
}
/**
* @brief Get ES of ISM_E_STATUS register
*
* @param pIsm ISM Instance
* @return ES value
*/
LOCAL_INLINE uint16_t ISM_HWA_GetEs(ISM_Type *const pIsm)
{
return (uint16_t)((pIsm->E_STATUS & ISM_E_STATUS_ES_MASK) >> ISM_E_STATUS_ES_SHIFT);
}
/**
* @brief Clear ES of ISM_E_STATUS register
*
* @param pIsm ISM Instance
* @param u32Channels ECM channels
*/
LOCAL_INLINE void ISM_HWA_ClearEs(ISM_Type *const pIsm, uint32_t u32Channels)
{
pIsm->E_STATUS = (u32Channels << ISM_E_STATUS_ES_SHIFT) & ISM_E_STATUS_ES_MASK;
}
/**
* @brief Enable ISM ECM channels system event
*
* @param pIsm ISM Instance
* @param u32Channels ECM Channels
* @param bEnable enable value
*/
LOCAL_INLINE void ISM_HWA_EnableEcmSystemEvent(ISM_Type *const pIsm, uint32_t u32Channels, bool bEnable)
{
if (bEnable)
{
pIsm->E_CTRL = pIsm->E_CTRL | (u32Channels << ISM_E_CTRL_ECE_SHIFT);
}
else
{
pIsm->E_CTRL = pIsm->E_CTRL & ~(u32Channels << ISM_E_CTRL_ECE_SHIFT);
}
}
/**
* @brief Get Enabled ISM ECM channels system event
*
* @param pIsm ISM Instance
* @return Enabled ECM event
*/
LOCAL_INLINE uint8_t ISM_HWA_GetEnabledEcmSystemEvent(ISM_Type *const pIsm)
{
return (uint8_t)((pIsm->E_CTRL & ISM_E_CTRL_ECE_MASK) >> ISM_E_CTRL_ECE_SHIFT);
}
/**
* @brief Enable ISM LAM channels system event
*
* @param pIsm ISM Instance
* @param u32Channels LAM Channels
* @param bEnable enable value
*/
LOCAL_INLINE void ISM_HWA_EnableLamSystemEvent(ISM_Type *const pIsm, uint32_t u32Channels, bool bEnable)
{
if (bEnable)
{
pIsm->E_CTRL = pIsm->E_CTRL | (u32Channels << ISM_E_CTRL_EE_SHIFT);
}
else
{
pIsm->E_CTRL = pIsm->E_CTRL & ~(u32Channels << ISM_E_CTRL_EE_SHIFT);
}
}
/**
* @brief Get Enabled ISM LAM channels system event
*
* @param pIsm ISM Instance
* @return Enabled LAM event
*/
LOCAL_INLINE uint16_t ISM_HWA_GetEnabledLamSystemEvent(ISM_Type *const pIsm)
{
return (uint16_t)((pIsm->E_CTRL & ISM_E_CTRL_EE_MASK) >> ISM_E_CTRL_EE_SHIFT);
}
/**
* @brief Set the EC_CTRL register
*
* @param pIsm ISM Instance
* @param u32Value register Value
*/
LOCAL_INLINE void ISM_HWA_SetEcCtrl(ISM_Type *const pIsm, uint32_t u32Value)
{
pIsm->EC_CTRL = u32Value;
}
/**
* @brief Set THRL and LAM channel of ECM0
*
* @param pIsm ISM Instance
* @param u32Value THRL value
* @param u32LamChannel Lam channel
*/
LOCAL_INLINE void ISM_HWA_SetEcm0EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel)
{
uint32_t u32TempValue = pIsm->EC_CTRL;
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_0_MASK) | ISM_EC_CTRL_SEL_0(u32LamChannel);
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_0_MASK) | ISM_EC_CTRL_THRL_0(u32Value);
pIsm->EC_CTRL = u32TempValue;
}
/**
* @brief Set THRL and LAM channel of ECM1
*
* @param pIsm ISM Instance
* @param u32Value THRL value
* @param u32LamChannel Lam channel
*/
LOCAL_INLINE void ISM_HWA_SetEcm1EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel)
{
uint32_t u32TempValue = pIsm->EC_CTRL;
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_1_MASK) | ISM_EC_CTRL_SEL_1(u32LamChannel);
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_1_MASK) | ISM_EC_CTRL_THRL_1(u32Value);
pIsm->EC_CTRL = u32TempValue;
}
/**
* @brief Set THRL and LAM channel of ECM2
*
* @param pIsm ISM Instance
* @param u32Value THRL value
* @param u32LamChannel Lam channel
*/
LOCAL_INLINE void ISM_HWA_SetEcm2EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel)
{
uint32_t u32TempValue = pIsm->EC_CTRL;
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_2_MASK) | ISM_EC_CTRL_SEL_2(u32LamChannel);
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_2_MASK) | ISM_EC_CTRL_THRL_2(u32Value);
pIsm->EC_CTRL = u32TempValue;
}
/**
* @brief Set THRL and LAM channel of ECM3
*
* @param pIsm ISM Instance
* @param u32Value THRL value
* @param u32LamChannel Lam channel
*/
LOCAL_INLINE void ISM_HWA_SetEcm3EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel)
{
uint32_t u32TempValue = pIsm->EC_CTRL;
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_3_MASK) | ISM_EC_CTRL_SEL_3(u32LamChannel);
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_3_MASK) | ISM_EC_CTRL_THRL_3(u32Value);
pIsm->EC_CTRL = u32TempValue;
}
/**
* @brief Get the RGD value of FPC_STATUS
*
* @param pFpc FPC Instance
* @return RGD value
*/
LOCAL_INLINE bool ISM_HWA_GetFpcRgd(FPC_Type *const pFpc)
{
return (pFpc->FPC_STATUS & ISM_FPC_STATUS_RGD_MASK) == ISM_FPC_STATUS_RGD_MASK ? true : false;
}
/**
* @brief Clear the RGD value of FPC_STATUS
*
* @param pFpc FPC Instance
*/
LOCAL_INLINE void ISM_HWA_ClearFpcRgd(FPC_Type *const pFpc)
{
pFpc->FPC_STATUS = ISM_FPC_STATUS_RGD_MASK;
}
/**
* @brief Get the FGD value of FPC_STATUS
*
* @param pFpc FPC Instance
* @return FGD value
*/
LOCAL_INLINE bool ISM_HWA_GetFpcFgd(FPC_Type *const pFpc)
{
return (pFpc->FPC_STATUS & ISM_FPC_STATUS_FGD_MASK) == ISM_FPC_STATUS_FGD_MASK ? true : false;
}
/**
* @brief Clear the FGD value of FPC_STATUS
*
* @param pFpc FPC Instance
*/
LOCAL_INLINE void ISM_HWA_ClearFpcFgd(FPC_Type *const pFpc)
{
pFpc->FPC_STATUS = ISM_FPC_STATUS_FGD_MASK;
}
/**
* @brief Set the EN of FPC_CTRL
*
* @param pFpc FPC Instance
* @param bEnable EN value
*/
LOCAL_INLINE void ISM_HWA_SetFpcCtrlEn(FPC_Type *const pFpc, bool bEnable)
{
pFpc->FPC_CTRL = (pFpc->FPC_CTRL & ~ISM_FPC_CTRL_EN_MASK) | ISM_FPC_CTRL_EN(bEnable);
}
/**
* @brief Set the IEN of FPC_CTRL
*
* @param pFpc FPC Instance
* @param bEnable IEN value
*/
LOCAL_INLINE void ISM_HWA_SetFpcCtrlIen(FPC_Type *const pFpc, bool bEnable)
{
pFpc->FPC_CTRL = (pFpc->FPC_CTRL & ~ISM_FPC_CTRL_IEN_MASK) | ISM_FPC_CTRL_IEN(bEnable);
}
/**
* @brief Get the IEN of FPC_CTRL
*
* @param pFpc FPC Instance
* @return Interrupt enable bit
*/
LOCAL_INLINE bool ISM_HWA_GetFpcCtrlIen(FPC_Type *const pFpc)
{
return (pFpc->FPC_CTRL & ISM_FPC_CTRL_IEN_MASK) == ISM_FPC_CTRL_IEN_MASK ? true : false;
}
/**
* @brief Set the FEG of FPC_CONFIG
*
* @param pFpc FPC Instance
* @param eMode FEG mode
*/
LOCAL_INLINE void ISM_HWA_SetFpcFallingDetectMode(FPC_Type *const pFpc, ISM_FPC_EdgeDetectModeType eMode)
{
pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_FEG_MASK) | ISM_FPC_CONFIG_FEG(eMode);
}
/**
* @brief Set the FED of FPC_CONFIG
*
* @param pFpc FPC Instance
* @param eMode FED mode
*/
LOCAL_INLINE void ISM_HWA_SetFpcFallingDelayMode(FPC_Type *const pFpc, ISM_FPC_EdgeDelayModeType eMode)
{
pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_FED_MASK) | ISM_FPC_CONFIG_FED(eMode);
}
/**
* @brief Set the REG of FPC_CONFIG
*
* @param pFpc FPC Instance
* @param eMode REG mode
*/
LOCAL_INLINE void ISM_HWA_SetFpcRisingDetectMode(FPC_Type *const pFpc, ISM_FPC_EdgeDetectModeType eMode)
{
pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_REG_MASK) | ISM_FPC_CONFIG_REG(eMode);
}
/**
* @brief Set the RED of FPC_CONFIG
*
* @param pFpc FPC Instance
* @param eMode RED mode
*/
LOCAL_INLINE void ISM_HWA_SetFpcRisingDelayMode(FPC_Type *const pFpc, ISM_FPC_EdgeDelayModeType eMode)
{
pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_RED_MASK) | ISM_FPC_CONFIG_RED(eMode);
}
/**
* @brief Set the CMP of FPC_CONFIG
*
* @param pFpc FPC Instance
* @param u32Value FPC threshold value that is compared with the 16-bit timer.
*/
LOCAL_INLINE void ISM_HWA_SetFpcConfigCmp(FPC_Type *const pFpc, uint32_t u32Value)
{
pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_CMP_MASK) | ISM_FPC_CONFIG_CMP(u32Value);
}
/**
* @brief Set the value of FPC_CONFIG
*
* @param pFpc FPC Instance
* @param u32Value Register value
*/
LOCAL_INLINE void ISM_HWA_SetFpcConfig(FPC_Type *const pFpc, uint32_t u32Value)
{
pFpc->FPC_CONFIG = u32Value;
}
/**
* @brief Get the TIM of FPC_TIMER
*
* @param pFpc FPC Instance
* @return TIM value
*/
LOCAL_INLINE uint16_t ISM_HWA_GetFpcTimer(FPC_Type *const pFpc)
{
return (uint16_t)((pFpc->FPC_TIMER & ISM_FPC_TIMER_TIM_MASK) >> ISM_FPC_TIMER_TIM_SHIFT);
}
/**
* @brief Clear the TIM of FPC_TIMER
*
* @param pFpc FPC Instance
*/
LOCAL_INLINE void ISM_HWA_ClearFpcTimer(FPC_Type *const pFpc)
{
pFpc->FPC_TIMER = ISM_FPC_TIMER_TIM_MASK;
}
/**
* @brief Get the COUNT of LAM_STATUS
*
* @param pLam LAM Instance
* @return COUNT value
*/
LOCAL_INLINE uint32_t ISM_HWA_GetLamStatusCounter(LAM_Type *const pLam)
{
return (pLam->LAM_STATUS & ISM_LAM_STATUS_COUNT_MASK) >> ISM_LAM_STATUS_COUNT_SHIFT;
}
/**
* @brief Clear the COUNT of LAM_STATUS
*
* @param pLam LAM Instance
*/
LOCAL_INLINE void ISM_HWA_ClearLamStatusCounter(LAM_Type *const pLam)
{
pLam->LAM_STATUS = ISM_LAM_STATUS_COUNT_MASK;
}
/**
* @brief Get the OVFL of LAM_STATUS
*
* @param pLam LAM Instance
* @return OVFL value
*/
LOCAL_INLINE bool ISM_HWA_GetLamStatusOvfl(LAM_Type *const pLam)
{
return (pLam->LAM_STATUS & ISM_LAM_STATUS_OVFL_MASK) == ISM_LAM_STATUS_OVFL_MASK ? true : false;
}
/**
* @brief Clear the OVFL of LAM_STATUS
*
* @param pLam LAM Instance
*/
LOCAL_INLINE void ISM_HWA_ClearLamStatusOvfl(LAM_Type *const pLam)
{
pLam->LAM_STATUS = ISM_LAM_STATUS_OVFL_MASK;
}
/**
* @brief Set the IEN of LAM_CTRL
*
* @param pLam LAM Instance
* @param bEnable IEN value, LAM Channel Overflow Interrupt Enable
*/
LOCAL_INLINE void ISM_HWA_SetLamCtrIen(LAM_Type *const pLam, bool bEnable)
{
pLam->LAM_CTRL = (pLam->LAM_CTRL & ~ISM_LAM_CTRL_IEN_MASK) | ISM_LAM_CTRL_IEN(bEnable);
}
/**
* @brief Get the IEN of LAM_CTRL
*
* @param pLam LAM Instance
* @return LAM Channel Overflow Interrupt Enable bit
*/
LOCAL_INLINE bool ISM_HWA_GetLamCtrIen(LAM_Type *const pLam)
{
return (pLam->LAM_CTRL & ISM_LAM_CTRL_IEN_MASK) == ISM_LAM_CTRL_IEN_MASK ? true : false;
}
/**
* @brief Set the EN of LAM_CTRL
*
* @param pLam LAM Instance
* @param bEnable EN value, LAM Channel Enable
*/
LOCAL_INLINE void ISM_HWA_SetLamCtrEn(LAM_Type *const pLam, bool bEnable)
{
pLam->LAM_CTRL = (pLam->LAM_CTRL & ~ISM_LAM_CTRL_EN_MASK) | ISM_LAM_CTRL_EN(bEnable);
}
/**
* @brief Set the value of LAM_CONFIG
*
* @param pLam LAM Instance
* @param u32Value Reigster value
*/
LOCAL_INLINE void ISM_HWA_SetLamConfig(LAM_Type *const pLam, uint32_t u32Value)
{
pLam->LAM_CONFIG = u32Value;
}
/**
* @brief Set the value of LAM_COUNTER
*
* @param pLam LAM Instance
* @param u32Value Reigster value
*/
LOCAL_INLINE void ISM_HWA_SetLamCounter(LAM_Type *const pLam, uint32_t u32Value)
{
pLam->LAM_CONTER = u32Value;
}
/**
* @brief Get the FPC instance.
* @param pIsm ISM Instance
* @param u8FpcIndex FPC index
* @return FPC Instance
*/
LOCAL_INLINE FPC_Type *ISM_HWA_GetFpc(ISM_Type *const pIsm, uint8_t u8FpcIndex)
{
return (FPC_Type *)((uint32_t) & (pIsm->FPC_STATUS0) + (uint32_t)u8FpcIndex * 0x10U);
}
/**
* @brief Get the LAM instance.
* @param pIsm ISM Instance
* @param u8FpcIndex LAM index
* @return LAM Instance
*/
LOCAL_INLINE LAM_Type *ISM_HWA_GetLam(ISM_Type *const pIsm, uint8_t u8LamIndex)
{
return (LAM_Type *)((uint32_t) & (pIsm->LAM_STATUS0) + (uint32_t)u8LamIndex * 0x10U);
}
/** @}*/ /* HwA_ism */
#endif /* #ifndef _HWA_ISM_H_ */

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/**
* @file HwA_lu.h
* @author Flagchip0103
* @brief FC7xxx LU hardware access layer
* @version 0.1.0
* @date 2023-12-19
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-19 Flagchip0103 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_LU_H_
#define _HWA_LU_H_
#include "device_header.h"
/********* Local typedef ************/
/** @brief LU LG instance */
typedef enum
{
LU_LG_0 = 0U,
LU_LG_1,
LU_LG_2,
LU_LG_3
} LU_LgType;
/** @brief LU AOI mode */
typedef enum
{
LU_NO_BYPASS = 0U,
LU_AOI0_BYPASS,
LU_AOI1_BYPASS,
LU_AOI0_AOI1_BYPASS
} LU_BypassModeType;
/** @brief LU FF mode */
typedef enum
{
LU_BYPASS_MODE0 = 0U,
LU_RS_MODE,
LU_TFF_MODE,
LU_DFF_MODE,
LU_JKFF_MODE,
LU_LATCH_MODE
} LU_ConfigModeType;
/** @brief LU Input(n) type */
typedef enum
{
LU_INPUT_N_A = 0U,
LU_INPUT_N_B,
LU_INPUT_N_C,
LU_INPUT_N_D
} LU_InputNType;
/********* Local inline function ************/
/**
* @brief Configure LU LG(n) AOI0 configuration
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32RegValue AOI0 register value
*/
LOCAL_INLINE void LU_HWA_ConfigAOI0(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue)
{
pLu->LG[eLg].AOI_0 = u32RegValue;
}
/**
* @brief Configure LU LG(n) AOI1 configuration
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32RegValue AOI1 register value
*/
LOCAL_INLINE void LU_HWA_ConfigAOI1(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue)
{
pLu->LG[eLg].AOI_1 = u32RegValue;
}
/**
* @brief Configure LU LG(n) contrl configuration
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32RegValue CTRL register value
*/
LOCAL_INLINE void LU_HWA_ConfigCtrl(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue)
{
pLu->LG[eLg].CTRL = u32RegValue;
}
/**
* @brief Configure LU LG(n) filter configuration
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32RegValue FILT register value
*/
LOCAL_INLINE void LU_HWA_ConfigFilter(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue)
{
pLu->LG[eLg].FILT = u32RegValue;
}
/**
* @brief Set LG bypass control
*
* @param pLu LU instance
* @param eLg LG instance
* @param eMode LG bypass control mode
*/
LOCAL_INLINE void LU_HWA_SetLgBypassControl(LU_Type* pLu, LU_LgType eLg, LU_BypassModeType eMode)
{
uint32_t u32TempRegValue = pLu->LG[eLg].CTRL;
pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_BYPASS_MASK) | LU_CTRL_BYPASS(eMode));
}
/**
* @brief Set LG Flip-Flop mode
*
* @param pLu LU instance
* @param eLg LG instance
* @param eMode Flip-Flop mode
*/
LOCAL_INLINE void LU_HWA_SetLgFlipFlopMode(LU_Type* pLu, LU_LgType eLg, LU_ConfigModeType eMode)
{
uint32_t u32TempRegValue = pLu->LG[eLg].CTRL;
pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_MOD_MASK) | LU_CTRL_MOD(eMode));
}
/**
* @brief Set LG inputs synchronous control
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32Value LG input bit,0-3 bit indicate INPUT(n)A/INPUT(n)B/INPUT(n)C/INPUT(n)D
*/
LOCAL_INLINE void LU_HWA_SetLgInputsSyncCtrl(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value)
{
uint32_t u32TempRegValue = pLu->LG[eLg].CTRL;
pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_SYNC_MASK) | LU_CTRL_SYNC(u32Value));
}
/**
* @brief Set LG output feedback override control
*
* @param pLu LU instance
* @param eLg LG instance
* @param eInput Feedback to LG input
*/
LOCAL_INLINE void LU_HWA_SetLgFeedbackOverrideCtrl(LU_Type* pLu, LU_LgType eLg, LU_InputNType eInput)
{
uint32_t u32TempRegValue = pLu->LG[eLg].CTRL;
pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_FB_OVRD_MASK) | LU_CTRL_FB_OVRD(eInput));
}
/**
* @brief Configure the output of flip-flop as "1"
*
* @param pLu LU instance
* @param eLg LG instance
*/
LOCAL_INLINE void LU_HWA_ConfigFlipFlopTo1(LU_Type* pLu, LU_LgType eLg)
{
pLu->LG[eLg].CTRL |= (uint32_t)LU_CTRL_FF_INIT_MASK;
}
/**
* @brief Generate enable pulse
*
* @param pLu LU instance
* @param eLg LG instance
*/
LOCAL_INLINE void LU_HWA_EnableControlFlipFlopInitOutput(LU_Type* pLu, LU_LgType eLg)
{
pLu->LG[eLg].CTRL |= (uint32_t)LU_CTRL_INIT_EN_MASK;
}
/**
* @brief Input filter sample count for AOI0
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32Value Sample count value
*/
LOCAL_INLINE void LU_HWA_SetAOI0InputFilterSampleCount(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value)
{
uint32_t u32TempRegValue = pLu->LG[eLg].FILT;
pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_CNT0_MASK) | LU_FILT_CNT0(u32Value));
}
/**
* @brief Input filter sample period for AOI0
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32Value Sample period value
*/
LOCAL_INLINE void LU_HWA_SetAOI0InputFilterSamplePeriod(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value)
{
uint32_t u32TempRegValue = pLu->LG[eLg].FILT;
pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_PRE0_MASK) | LU_FILT_PRE0(u32Value));
}
/**
* @brief Input filter sample count for AOI1
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32Value Sample count value
*/
LOCAL_INLINE void LU_HWA_SetAOI1InputFilterSampleCount(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value)
{
uint32_t u32TempRegValue = pLu->LG[eLg].FILT;
pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_CNT1_MASK) | LU_FILT_CNT1(u32Value));
}
/**
* @brief Input filter sample period for AOI1
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32Value Sample period value
*/
LOCAL_INLINE void LU_HWA_SetAOI1InputFilterSamplePeriod(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value)
{
uint32_t u32TempRegValue = pLu->LG[eLg].FILT;
pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_PRE1_MASK) | LU_FILT_PRE1(u32Value));
}
/**
* @brief Configure the output of flip-flop as "0"
*
* @param pLu LU instance
* @param eLg LG instance
*/
LOCAL_INLINE void LU_HWA_ConfigFlipFlopTo0(LU_Type* pLu, LU_LgType eLg)
{
pLu->LG[eLg].CTRL &= ~(uint32_t)LU_CTRL_FF_INIT_MASK;
}
#endif /* #ifndef _HWA_LU_H_ */

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/**
* @file HwA_mam.h
* @author Flagchip
* @brief Hardware access layer for MAM
* @version 0.2.0
* @date 2023-02-08
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-02-08 Flagchip054 N/A First version for FC7300
******************************************************************************** */
#ifndef _HWA_MAM_H_
#define _HWA_MAM_H_
#include "device_header.h"
/**
* @brief Set Mam module Matrix Configure register
*
* @param1 MAM base pointer
*
* @param2 u32Value Matrix Configure register value
*/
LOCAL_INLINE void Mam_HWA_SetMatrixCfg(MAM_Type *MAMInstance, uint32_t u32Value)
{
MAMInstance->MAXCFG = u32Value;
}
/**
* @brief Read Mam module Ctrl register
*
* @param MAM base pointer
*
* @return Matrix Configure register value
*/
LOCAL_INLINE uint32_t Mam_HWA_GetMatrixCfg(MAM_Type *MAMInstance)
{
return (uint32_t)(MAMInstance->MAXCFG);
}
/**
* @brief Set Mam module Wdgctr register
*
* @param1 MAM base pointer
*
* @param2 u32Value Wdgctr register value
*/
LOCAL_INLINE void Mam_HWA_Set_Wdgctr(MAM_Type *MAMInstance, uint32_t u32Value)
{
MAMInstance->WDGCR = u32Value;
}
/**
* @brief Read Mam module Wdgctr register
*
* @param MAM base pointer
*
* @return Wdgctr register value
*/
LOCAL_INLINE uint32 Mam_HWA_Get_Wdgctr(MAM_Type *MAMInstance)
{
return MAMInstance->WDGCR;
}
/**
* @brief Set Mam module ACR register
*
* @param1 MAM base pointer
*
* @param2 idx ACR register index
*
* @param3 u32Value ACR register value
*/
LOCAL_INLINE void Mam_HWA_Set_ACR(MAM_Type *MAMInstance, uint32_t idx, uint32_t u32Value)
{
MAMInstance->ACR[idx] = u32Value;
}
/**
* @brief Read Mam module ACR register
*
* @param1 MAM base pointer
*
* @param2 idx ACR register index
*
* @return ACR register value
*/
LOCAL_INLINE uint32_t Mam_HWA_Get_ACR(MAM_Type *MAMInstance, uint32_t idx)
{
return MAMInstance->ACR[idx];
}
/**
* @brief Set Mam module ACLR register
*
* @param1 MAM base pointer
*
* @param2 idx ACLR register index
*
* @param3 u32Value ACLR register value
*/
LOCAL_INLINE void Mam_HWA_Set_ACLR(MAM_Type *MAMInstance, uint32_t idx, uint32_t u32Value)
{
MAMInstance->ACLR[idx] = u32Value;
}
/**
* @brief Read Mam module ACLR register
*
* @param1 MAM base pointer
*
* @param2 idx ACLR register index
*
* @return ACLR register value
*/
LOCAL_INLINE uint32_t Mam_HWA_Get_ACLR(MAM_Type *MAMInstance, uint32_t idx)
{
return MAMInstance->ACLR[idx];
}
#endif

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/**
* @file HwA_mb.h
* @author Flagchip070
* @brief FC7xxx Mailbox hardware access layer
* @version 0.1.0
* @date 2022-11-15
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022-11-15 Flagchip070 N/A First version for FC7300
******************************************************************************** */
#ifndef _HWA_MAILBOX_H_
#define _HWA_MAILBOX_H_
#include "device_header.h"
/**
* @brief The definition of mask all events
*
*/
#define MB_EVENT_NONE 0u
/**
* @brief The definition of receiving all events
*
*/
#define MB_EVENT_ALL 0xFFFFFFFFu
/**
* @brief The definition of receiving all request events
*
*/
#define MB_EVENT_ALL_REQ 0x0000FFFFu
/**
* @brief The definition of receiving all done events
*
*/
#define MB_EVENT_ALL_DONE 0xFFFF0000u
/**
* @brief The definition of request events on ch
*
*/
#define MB_EVENT_REQ(ch) (uint32_t)((uint32_t)1u << (ch))
/**
* @brief The definition of done events on ch
*
*/
#define MB_EVENT_DONE(ch) (uint32_t)((uint32_t)1u << ((ch) + 16u))
/**
* @brief The definition of issue to no core
*
*/
#define MB_CORE_MASK_CORE_NONE 0u
/**
* @brief The definition of issue to core 0
*
*/
#define MB_CORE_MASK_CORE_0 1u
/**
* @brief The definition of issue to HSM
*
*/
#define MB_CORE_MASK_HSM 2u
/**
* @brief The definition of issue to all cores
*
*/
#define MB_CORE_MASK_ALL 0x3u
/**
* @brief The definition of issue to core
*
*/
#define MB_CORE_MASK(core) (uint32_t)(1ul << (core))
enum
{
MB_CORE_INDEX_CORE_0 = 0, /*!< Core index of core 0 */
MB_CORE_INDEX_HSM, /*!< Core index of HSM */
};
/**
* @brief Configure receive events of mailbox interrupt channel
*
* @param u32CoreIndex the index of the core
* @param u32Mask configuration for receiving events
*/
LOCAL_INLINE void MB_HWA_ConfigFlagMask(uint32_t u32CoreIndex, uint32_t u32Mask)
{
MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_FLG_MASK_LOCK_MASK;
MB->INTR[u32CoreIndex].MB_INTn_FLG_MASK = u32Mask;
MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_FLG_MASK_LOCK_MASK;
}
/**
* @brief Enable receive events of mailbox interrupt channel
*
* @param u32CoreIndex the index of the core
* @param u32Mask indicates the events to be enabled
*/
LOCAL_INLINE void MB_HWA_EnableEvent(uint32_t u32CoreIndex, uint32_t u32Mask)
{
MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_FLG_MASK_LOCK_MASK;
MB->INTR[u32CoreIndex].MB_INTn_FLG_MASK |= u32Mask;
MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_FLG_MASK_LOCK_MASK;
}
/**
* @brief Disable receive events of mailbox interrupt channel
*
* @param u32CoreIndex the index of the core
* @param u32Mask indicates the events to be enabled
*/
LOCAL_INLINE void MB_HWA_DisableEvent(uint32_t u32CoreIndex, uint32_t u32Mask)
{
MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_FLG_MASK_LOCK_MASK;
MB->INTR[u32CoreIndex].MB_INTn_FLG_MASK &= ~u32Mask;
MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_FLG_MASK_LOCK_MASK;
}
/**
* @brief Configure the interrupt of mailbox interrupt channel
*
* @param u32CoreIndex the index of the core
* @param u32Mask configuration for interrupts
*/
LOCAL_INLINE void MB_HWA_ConfigIntrEnable(uint32_t u32CoreIndex, uint32_t u32Mask)
{
MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_INTEN_LOCK_MASK;
MB->INTR[u32CoreIndex].MB_INTn_INTEN = u32Mask;
MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_INTEN_LOCK_MASK;
}
/**
* @brief Enable the interrupt of mailbox interrupt channel
*
* @param u32CoreIndex the index of the core
* @param u32Mask indicates the interrupts to be enabled
*/
LOCAL_INLINE void MB_HWA_EnableIntr(uint32_t u32CoreIndex, uint32_t u32Mask)
{
MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_INTEN_LOCK_MASK;
MB->INTR[u32CoreIndex].MB_INTn_INTEN |= u32Mask;
MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_INTEN_LOCK_MASK;
}
/**
* @brief Disable the interrupt of mailbox interrupt channel
*
* @param u32CoreIndex the index of the core
* @param u32Mask indicates the interrupts to be disabled
*/
LOCAL_INLINE void MB_HWA_DisableIntr(uint32_t u32CoreIndex, uint32_t u32Mask)
{
MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_INTEN_LOCK_MASK;
MB->INTR[u32CoreIndex].MB_INTn_INTEN &= ~u32Mask;
MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_INTEN_LOCK_MASK;
}
/**
* @brief Clear the flag of mailbox interrupt channel
*
* @param u32CoreIndex the index of the core
* @param u32Mask indicates the flags to be cleared
*/
LOCAL_INLINE void MB_HWA_ClearFlag(uint32_t u32CoreIndex, uint32_t u32Mask)
{
MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_FLG_LOCK_MASK;
MB->INTR[u32CoreIndex].MB_INTn_FLG |= u32Mask;
MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_FLG_LOCK_MASK;
}
/**
* @brief Get the flag masks of mailbox interrupt channel
*
* @param u32CoreIndex the index of the core
* @param u32Mask the mask to get
* @return the flag masks of the mailbox interrupt channel
*/
LOCAL_INLINE uint32_t MB_HWA_GetFlagMask(uint32_t u32CoreIndex, uint32_t u32Mask)
{
uint32_t u32RegValue = MB->INTR[u32CoreIndex].MB_INTn_FLG_MASK & u32Mask;
return u32RegValue;
}
/**
* @brief Get the flags of mailbox interrupt channel
*
* @param u32CoreIndex the index of the core
* @param u32Mask the mask to get
* @return the flags of the mailbox interrupt channel
*/
LOCAL_INLINE uint32_t MB_HWA_GetFlag(uint32_t u32CoreIndex, uint32_t u32Mask)
{
uint32_t u32RegValue = MB->INTR[u32CoreIndex].MB_INTn_FLG & u32Mask;
return u32RegValue;
}
/**
* @brief Get the result of flag & inten of mailbox interrupt channel
*
* @param u32CoreIndex the index of the core
* @param u32Mask the mask to get
* @return the result of flag & inten of the mailbox interrupt channel
*/
LOCAL_INLINE uint32_t MB_HWA_GetFlagStat(uint32_t u32CoreIndex, uint32_t u32Mask)
{
uint32_t u32RegValue = MB->INTR[u32CoreIndex].MB_INTn_FLG_STAT & u32Mask;
return u32RegValue;
}
/**
* @brief Get the master ID of the currently obtained channel
*
* @param u32Channel the index of the channel
* @return the master ID
*/
LOCAL_INLINE uint32_t MB_HWA_GetMasterID(uint32_t u32Channel)
{
uint32_t u32MasterId = MB->CHANNEL[u32Channel].MB_CCn_STAT;
u32MasterId = (u32MasterId & MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_MASK) >> MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_SHIFT;
return u32MasterId;
}
/**
* @brief Get the security information of the currently obtained channel
*
* @param u32Channel the index of the channel
* @return the security information
*/
LOCAL_INLINE uint32_t MB_HWA_GetSecure(uint32_t u32Channel)
{
uint32_t u32Secure = MB->CHANNEL[u32Channel].MB_CCn_STAT & MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_MASK;
return u32Secure;
}
/**
* @brief Get the processing mode of the currently obtained channel
*
* @param u32Channel the index of the channel
* @return the processing mode
*/
LOCAL_INLINE uint32_t MB_HWA_GetSupervisor(uint32_t u32Channel)
{
uint32_t u32Supervisor = MB->CHANNEL[u32Channel].MB_CCn_STAT & MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_MASK;
return u32Supervisor;
}
/**
* @brief Send data to the mailbox channel
*
* @param u32Channel the index of the channel
* @param pData the buffer to be written
*/
LOCAL_INLINE void MB_HWA_WriteData(uint32_t u32Channel, uint32_t *pData)
{
MB->CHANNEL[u32Channel].MB_CCn_DATA0 = pData[0];
MB->CHANNEL[u32Channel].MB_CCn_DATA1 = pData[1];
}
/**
* @brief Receive data from the mailbox channel
*
* @param u32Channel the index of the channel
* @param pData the buffer to receive data
*/
LOCAL_INLINE void MB_HWA_GetData(uint32_t u32Channel, uint32_t *pData)
{
pData[0] = MB->CHANNEL[u32Channel].MB_CCn_DATA0;
pData[1] = MB->CHANNEL[u32Channel].MB_CCn_DATA1;
}
/**
* @brief Get the automatically clear status of the mailbox channel
*
* @param u32Channel the index of the channel
* @param u32CoreIndex the index of the core
* @return automatically clear the channel lock enable bit
*/
LOCAL_INLINE uint32_t MB_HWA_GetAutoClear(uint32_t u32Channel, uint32_t u32CoreIndex)
{
uint32_t u32SemaUnlock = MB->CHANNEL[u32Channel].MB_CCn_SEMA_UNLK;
u32SemaUnlock &= (uint32_t)1u << (u32CoreIndex + MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_SHIFT);
return u32SemaUnlock;
}
/**
* @brief Release the mailbox channel
*
* @param u32Channel the index of the channel
*/
LOCAL_INLINE void MB_HWA_ReleaseChannel(uint32_t u32Channel)
{
MB->CHANNEL[u32Channel].MB_CCn_DONE = MB_MASTER_DONE_CODE;
}
/**
* @brief Software clears channel lock
*
* @param u32Channel the index of the channel
*/
LOCAL_INLINE void MB_HWA_UnlockChanne(uint32_t u32Channel)
{
MB->CHANNEL[u32Channel].MB_CCn_CLR = MB_FORCE_UNLOCK_CODE;
}
/**
* @brief Issue a done event
*
* @param u32Channel the index of the channel
* @param u32DoneMask the cores to issue
*/
LOCAL_INLINE void MB_HWA_SetDone(uint32_t u32Channel, uint32_t u32DoneMask)
{
MB->CHANNEL[u32Channel].MB_CCn_DONE |= (u32DoneMask & MB_CCn_DONE_DONE_MASK);
}
/**
* @brief Try to lock a channel
*
* @param u32Channel the index of the channel
* @return Channel Lock Acquisition
*/
LOCAL_INLINE uint32_t MB_HWA_LockChannel(uint32_t u32Channel)
{
uint32_t u32RegValue = MB->CHANNEL[u32Channel].MB_CCn_SEMA;
return u32RegValue & MB_CCn_SEMA_LOCK_MASK;
}
/**
* @brief Configure the master ID of the core that generates a done event
*
* @param u32Channel the index of the channel
* @param u32MasterId master ID
*/
LOCAL_INLINE void MB_HWA_ConfigDoneMasterId(uint32_t u32Channel, uint32_t u32MasterId)
{
MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK &= ~MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK;
MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK |= MB_CCn_DONE_MASK_DONE_MASTER_ID(u32MasterId);
}
/**
* @brief Get the master ID of the core that generates a done event
*
* @param u32Channel the index of the channel
* @return the master ID
*/
LOCAL_INLINE uint32_t MB_HWA_GetDoneMasterId(uint32_t u32Channel)
{
uint32_t u32MasterId =
(MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK & MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK)
>> MB_CCn_DONE_MASK_DONE_MASTER_ID_SHIFT;
return u32MasterId;
}
/**
* @brief Configure the mask of the done events
*
* @param u32Channel the index of the channel
* @param u32DoneMask the cores to issue
*/
LOCAL_INLINE void MB_HWA_ConfigDoneMask(uint32_t u32Channel, uint32_t u32DoneMask)
{
MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK &= ~MB_CCn_DONE_DONE_MASK;
MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK |= (u32DoneMask << MB_CCn_DONE_DONE_SHIFT) & MB_CCn_DONE_DONE_MASK;
}
/**
* @brief Get the mask of the done events
*
* @param u32Channel the index of the channel
* @return the mask of the done events
*/
LOCAL_INLINE uint32_t MB_HWA_GetDoneMask(uint32_t u32Channel)
{
uint32_t u32Mask = MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK & MB_CCn_DONE_DONE_MASK;
return u32Mask;
}
/**
* @brief Configure the automatically clear of the lock enable bit
*
* @param u32Channel the index of the channel
* @param u32AutoUnlockMask the automatically clear of the lock enable bit
*/
LOCAL_INLINE void MB_HWA_ConfigAutoUnlock(uint32_t u32Channel, uint32_t u32AutoUnlockMask)
{
MB->CHANNEL[u32Channel].MB_CCn_SEMA_UNLK = MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN(u32AutoUnlockMask);
}
/**
* @brief Issue request events
*
* @param u32Channel the index of the channel
* @param u32RequestMask the cores to issue
*/
LOCAL_INLINE void MB_HWA_ConfigRequest(uint32_t u32Channel, uint32_t u32RequestMask)
{
MB->CHANNEL[u32Channel].MB_CCn_REQUEST = MB_CCn_REQUEST_REQ(u32RequestMask);
}
#endif

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/**
* @file HwA_mpu.h
* @author Flagchip085
* @brief FC7xxx MPU hardware access layer
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_MPU_H_
#define _HWA_MPU_H_
#include "device_header.h"
/**
* @brief The MPU registers struct
*
*/
typedef struct {
__I uint32_t MPU_TYPE; /* TYPE, offset: 0x0 */
__IO uint32_t MPU_CTRL; /* CTRL, offset: 0x4 */
__IO uint32_t MPU_RNR; /* RNR, offset: 0x8 */
__IO uint32_t MPU_RBAR; /* RBAR, offset: 0xC */
__IO uint32_t MPU_RASR; /* RASR, offset: 0x10 */
} CORTEX_MPU_Type, *PCORTEX_MPU_Type;
/** mpu base Address */
#define CORTEX_MPU_BASE (0xE000ED90U)
#define CORTEX_MPU ((CORTEX_MPU_Type *)CORTEX_MPU_BASE)
/** TYPE Bit Fields **/
#define CORTEX_MPU_TYPE_IREGION_MASK 0xFF0000U
#define CORTEX_MPU_TYPE_IREGION_SHIFT 16U
#define CORTEX_MPU_TYPE_IREGION_WIDTH 8U
#define CORTEX_MPU_TYPE_IREGION(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_TYPE_IREGION_SHIFT))&CORTEX_MPU_TYPE_IREGION_MASK)
#define CORTEX_MPU_TYPE_DREGION_MASK 0xFF00U
#define CORTEX_MPU_TYPE_DREGION_SHIFT 8U
#define CORTEX_MPU_TYPE_DREGION_WIDTH 8U
#define CORTEX_MPU_TYPE_DREGION(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_TYPE_DREGION_SHIFT))&CORTEX_MPU_TYPE_DREGION_MASK)
#define CORTEX_MPU_TYPE_SEPARATE_MASK 0x1U
#define CORTEX_MPU_TYPE_SEPARATE_SHIFT 0U
#define CORTEX_MPU_TYPE_SEPARATE_WIDTH 1U
#define CORTEX_MPU_TYPE_SEPARATE(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_TYPE_SEPARATE_SHIFT))&CORTEX_MPU_TYPE_SEPARATE_MASK)
/** TYPE Reg Mask **/
#define CORTEX_MPU_TYPE 0x00FFFF01U
/** CTRL Bit Fields **/
#define CORTEX_MPU_CTRL_RPRIVDEFENA_MASK 0x4U
#define CORTEX_MPU_CTRL_RPRIVDEFENA_SHIFT 2U
#define CORTEX_MPU_CTRL_RPRIVDEFENA_WIDTH 1U
#define CORTEX_MPU_CTRL_RPRIVDEFENA(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_CTRL_RPRIVDEFENA_SHIFT))&CORTEX_MPU_CTRL_RPRIVDEFENA_MASK)
#define CORTEX_MPU_CTRL_HFNMIENA_MASK 0x2U
#define CORTEX_MPU_CTRL_HFNMIENA_SHIFT 1U
#define CORTEX_MPU_CTRL_HFNMIENA_WIDTH 1U
#define CORTEX_MPU_CTRL_HFNMIENA(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_CTRL_HFNMIENA_SHIFT))&CORTEX_MPU_CTRL_HFNMIENA_MASK)
#define CORTEX_MPU_CTRL_ENABLE_MASK 0x1U
#define CORTEX_MPU_CTRL_ENABLE_SHIFT 0U
#define CORTEX_MPU_CTRL_ENABLE_WIDTH 1U
#define CORTEX_MPU_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_CTRL_ENABLE_SHIFT))&CORTEX_MPU_CTRL_ENABLE_MASK)
/** CTRL Reg Mask **/
#define CORTEX_MPU_CTRL 0x00000007U
/** RNR Bit Fields **/
#define CORTEX_MPU_RNR_REGION_MASK 0xFFu
#define CORTEX_MPU_RNR_REGION_SHIFT 0U
#define CORTEX_MPU_RNR_REGION_WIDTH 8U
#define CORTEX_MPU_RNR_REGION(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RNR_REGION_SHIFT))&CORTEX_MPU_RNR_REGION_MASK)
/** MPU_RNR Reg Mask **/
#define CORTEX_MPU_RNR 0x000000FFu
/** RBAR Bit Fields **/
#define CORTEX_MPU_RBAR_ADDR_MASK 0xFFFFFFE0U
#define CORTEX_MPU_RBAR_ADDR_SHIFT 5U
#define CORTEX_MPU_RBAR_ADDR_WIDTH 27U
#define CORTEX_MPU_RBAR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RBAR_ADDR_SHIFT))&CORTEX_MPU_RBAR_ADDR_MASK)
#define CORTEX_MPU_RBAR_VALID_MASK 0x10U
#define CORTEX_MPU_RBAR_VALID_SHIFT 4U
#define CORTEX_MPU_RBAR_VALID_WIDTH 1U
#define CORTEX_MPU_RBAR_VALID(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RBAR_VALID_SHIFT))&CORTEX_MPU_RBAR_VALID_MASK)
#define CORTEX_MPU_RBAR_REGION_MASK 0xFu
#define CORTEX_MPU_RBAR_REGION_SHIFT 0U
#define CORTEX_MPU_RBAR_REGION_WIDTH 4U
#define CORTEX_MPU_RBAR_REGION(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RBAR_REGION_SHIFT))&CORTEX_MPU_RBAR_REGION_MASK)
/** RBAR Reg Mask **/
#define CORTEX_MPU_RBAR 0xFFFFFFFFu
/** RASR Bit Fields **/
#define CORTEX_MPU_RASR_ATTRS_MASK 0xFFFF0000U
#define CORTEX_MPU_RASR_ATTRS_SHIFT 16U
#define CORTEX_MPU_RASR_ATTRS_WIDTH 16U
#define CORTEX_MPU_RASR_ATTRS(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_ATTRS_SHIFT))&CORTEX_MPU_RASR_ATTRS_MASK)
#define CORTEX_MPU_RASR_XN_MASK 0x10000000U
#define CORTEX_MPU_RASR_XN_SHIFT 28U
#define CORTEX_MPU_RASR_XN_WIDTH 1U
#define CORTEX_MPU_RASR_XN(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_XN_SHIFT))&CORTEX_MPU_RASR_XN_MASK)
#define CORTEX_MPU_RASR_AP_MASK 0x7000000U
#define CORTEX_MPU_RASR_AP_SHIFT 24U
#define CORTEX_MPU_RASR_AP_WIDTH 3U
#define CORTEX_MPU_RASR_AP(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_AP_SHIFT))&CORTEX_MPU_RASR_AP_MASK)
#define CORTEX_MPU_RASR_TEX_MASK 0x380000U
#define CORTEX_MPU_RASR_TEX_SHIFT 19U
#define CORTEX_MPU_RASR_TEX_WIDTH 3U
#define CORTEX_MPU_RASR_TEX(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_TEX_SHIFT))&CORTEX_MPU_RASR_TEX_MASK)
#define CORTEX_MPU_RASR_S_MASK 0x40000U
#define CORTEX_MPU_RASR_S_SHIFT 18U
#define CORTEX_MPU_RASR_S_WIDTH 1U
#define CORTEX_MPU_RASR_S(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_S_SHIFT))&CORTEX_MPU_RASR_S_MASK)
#define CORTEX_MPU_RASR_C_MASK 0x20000U
#define CORTEX_MPU_RASR_C_SHIFT 17U
#define CORTEX_MPU_RASR_C_WIDTH 1U
#define CORTEX_MPU_RASR_C(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_C_SHIFT))&CORTEX_MPU_RASR_C_MASK)
#define CORTEX_MPU_RASR_B_MASK 0x10000U
#define CORTEX_MPU_RASR_B_SHIFT 16U
#define CORTEX_MPU_RASR_B_WIDTH 1U
#define CORTEX_MPU_RASR_B(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_B_SHIFT))&CORTEX_MPU_RASR_B_MASK)
#define CORTEX_MPU_RASR_SRD_MASK 0xFF00U
#define CORTEX_MPU_RASR_SRD_SHIFT 8U
#define CORTEX_MPU_RASR_SRD_WIDTH 8U
#define CORTEX_MPU_RASR_SRD(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_SRD_SHIFT))&CORTEX_MPU_RASR_SRD_MASK)
#define CORTEX_MPU_RASR_SIZE_MASK 0x3Eu
#define CORTEX_MPU_RASR_SIZE_SHIFT 1U
#define CORTEX_MPU_RASR_SIZE_WIDTH 5U
#define CORTEX_MPU_RASR_SIZE(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_SIZE_SHIFT))&CORTEX_MPU_RASR_SIZE_MASK)
#define CORTEX_MPU_RASR_ENABLE_MASK 0x1U
#define CORTEX_MPU_RASR_ENABLE_SHIFT 0U
#define CORTEX_MPU_RASR_ENABLE_WIDTH 1U
#define CORTEX_MPU_RASR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_ENABLE_SHIFT))&CORTEX_MPU_RASR_ENABLE_MASK)
/** RASR Reg Mask **/
#define CORTEX_MPU_RASR 0xFFFFFF3Fu
#define MPU_RBAR_BASEADDR_MASK_U32 (0xFFFFFFE0u)
#define MPU_RBAR_VALID_REGION_MASK_U32 (0x1Fu)
#define MPU_EN_MASK_U32 ((uint32_t)(CORTEX_MPU_CTRL_HFNMIENA_MASK | CORTEX_MPU_CTRL_RPRIVDEFENA_MASK))
#define MPU_REGION_MASK_U32 ((uint32_t)0xFF)
/**
* @brief get mpu type register
*
* @return type value
*/
LOCAL_INLINE uint32_t MPU_HWA_Get_Type(void)
{
return CORTEX_MPU->MPU_TYPE;
}
/**
* @brief disable fault exceptions
*
*
*/
LOCAL_INLINE void MPU_HWA_Fault_Disable(void)
{
SCB->SHCSR &= ~((uint32_t)SCB_SHCSR_MEMFAULTENA_Msk);
}
/**
* @brief enable fault exceptions
*
*
*/
LOCAL_INLINE void MPU_HWA_Fault_Enable(void)
{
SCB->SHCSR |= (uint32_t)SCB_SHCSR_MEMFAULTENA_Msk;
}
/**
* @brief set mpu control register
*
* @param u32RegValue the value write to register
* @return LOCAL_INLINE
*/
LOCAL_INLINE void MPU_HWA_Set_CR(uint32_t u32RegValue)
{
CORTEX_MPU->MPU_CTRL = u32RegValue;
}
/**
* @brief set mpu number register
*
* @param u32RegValue the value write to register
* @return LOCAL_INLINE
*/
LOCAL_INLINE void MPU_HWA_Set_NR(uint8_t u32RegValue)
{
CORTEX_MPU->MPU_RNR = (MPU_REGION_MASK_U32 & u32RegValue);
}
/**
* @brief set mpu base address register
*
* @param u32RegValue the value write to register
* @return LOCAL_INLINE
*/
LOCAL_INLINE void MPU_HWA_Set_BAR(uint32_t u32RegValue)
{
CORTEX_MPU->MPU_RBAR = u32RegValue;
}
/**
* @brief set mpu attribute and size register
*
* @param u32RegValue the value write to registe
* @return LOCAL_INLINE
*/
LOCAL_INLINE void MPU_HWA_Set_ASR(uint32_t u32RegValue)
{
CORTEX_MPU->MPU_RASR = u32RegValue;
}
#endif /* _HWA_MPU_H_ */

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/**
* @file HwA_msc.h
* @author Flagchip
* @brief FC7240 MSC HWA driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version
******************************************************************************** */
#ifndef _HWA_MSC_H_
#define _HWA_MSC_H_
#include "device_header.h"
/**
* @addtogroup HwA_msc
* @{
*
*/
/********* macros ************/
typedef enum
{
MSC_RSV_SUCCESS = 0x0U, /*!< MSC receive status is successful. */
MSC_RSV_PARITY_ERROR = 0x1U, /*!< MSC receive has parity error. */
MSC_RSV_STOP_ERROR = 0x2U /*!< MSC receive has stop error. */
} MSC_ReceiveStatusType;
/********* Local typedef ************/
/********* Local inline function ************/
/********* xxx Register interface ************/
/**
* @brief Get the msc TCCTR register
*
* @param pMsc MSCInstance
* @param u32Value TCCTR register value
*/
LOCAL_INLINE void MSC_HWA_SetTcctr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCCTR = u32Value;
}
/**
* @brief Get the msc TCCTR register DTS bit
*
* @param pMsc MSCInstance
* @return DTS value
*/
LOCAL_INLINE bool MSC_HWA_GetDataNeedSend(MSC_Type *const pMsc)
{
return (pMsc->TCCTR & MSC_TCCTR_DTS_MASK) == MSC_TCCTR_DTS_MASK ? true : false;
}
/**
* @brief Set the msc TCCTR register DTS bit
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_SetDataNeedSend(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_SDTS_MASK;
}
/**
* @brief Get the msc TCCTR register CTS bit
*
* @param pMsc MSCInstance
* @return CTS value
*/
LOCAL_INLINE bool MSC_HWA_GetCmdNeedSend(MSC_Type *const pMsc)
{
return (pMsc->TCCTR & MSC_TCCTR_CTS_MASK) == MSC_TCCTR_CTS_MASK ? true : false;
}
/**
* @brief Get the CFB value of TCSTR register
*
* @param pMsc MSCInstance
* @return CFB value
*/
LOCAL_INLINE bool MSC_HWA_GetCfb(MSC_Type *const pMsc)
{
return (bool)(((pMsc->TCSTR & (uint32_t)MSC_TCSTR_CFB_MASK) != 0U) ? true : false);
}
/**
* @brief Get the DFB value of TCSTR register
*
* @param pMsc MSCInstance
* @return DFB value
*/
LOCAL_INLINE bool MSC_HWA_GetDfb(MSC_Type *const pMsc)
{
return ((pMsc->TCSTR & (uint32_t)MSC_TCSTR_DFB_MASK) != 0U) ? true : false;
}
/**
* @brief Set the NP value of TCSTR register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_SetNp(MSC_Type *const pMsc, uint8_t u8Np)
{
pMsc->TCSTR = (pMsc->TCSTR & ~MSC_TCSTR_NP_MASK) | MSC_TCSTR_NP(u8Np);
}
/**
* @brief Get the NP value of TCSTR register
*
* @param pMsc MSCInstance
* @return NP value
*/
LOCAL_INLINE uint32_t MSC_HWA_GetNp(MSC_Type *const pMsc)
{
return ((pMsc->TCSTR & (uint32_t)MSC_TCSTR_NP_MASK)) >> MSC_TCSTR_NP_SHIFT;
}
/**
* @brief Set the msc TCDAR register
*
* @param pMsc MSCInstance
* @param u32Value TCDAR value
*/
LOCAL_INLINE void MSC_HWA_SetTcdar(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCDAR = u32Value;
}
/**
* @brief Set the TDH of TCDAR register
*
* @param pMsc MSCInstance
* @param u16Value TDH value
*/
LOCAL_INLINE void MSC_HWA_SetTcdarTdh(MSC_Type *const pMsc, uint16_t u16Value)
{
pMsc->TCDAR = (pMsc->TCDAR & ~MSC_TCDAR_TDH_MASK) | MSC_TCDAR_TDH(u16Value);
}
/**
* @brief Set the TDL of TCDAR register
*
* @param pMsc MSCInstance
* @param u16Value TDL value
*/
LOCAL_INLINE void MSC_HWA_SetTcdarTdl(MSC_Type *const pMsc, uint16_t u16Value)
{
pMsc->TCDAR = (pMsc->TCDAR & ~MSC_TCDAR_TDL_MASK) | MSC_TCDAR_TDL(u16Value);
}
/**
* @brief Set the TCCOR register
*
* @param pMsc MSCInstance
* @param u32Value TCCOR value
*/
LOCAL_INLINE void MSC_HWA_SetTccor(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCCOR = u32Value;
}
/**
* @brief Set the TCH of TCCOR register
*
* @param pMsc MSCInstance
* @param u16Value TCH value
*/
LOCAL_INLINE void MSC_HWA_SetTccorTch(MSC_Type *const pMsc, uint16_t u16Value)
{
pMsc->TCCOR = (pMsc->TCCOR & ~MSC_TCCOR_TCH_MASK) | MSC_TCCOR_TCH(u16Value);
}
/**
* @brief Set the TCL of TCCOR register
*
* @param pMsc MSCInstance
* @param u16Value TCL value
*/
LOCAL_INLINE void MSC_HWA_SetTccorTcl(MSC_Type *const pMsc, uint16_t u16Value)
{
pMsc->TCCOR = (pMsc->TCCOR & ~MSC_TCCOR_TCL_MASK) | MSC_TCCOR_TCL(u16Value);
}
/**
* @brief Set the TCSLR register
*
* @param pMsc MSCInstance
* @param u32Value TCSLR value
*/
LOCAL_INLINE void MSC_HWA_SetTcslr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCSLR = u32Value;
}
/**
* @brief Set the TCSHR register
*
* @param pMsc MSCInstance
* @param u32Value TCSHR value
*/
LOCAL_INLINE void MSC_HWA_SetTcshr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCSHR = u32Value;
}
/**
* @brief Set the TCELR register
*
* @param pMsc MSCInstance
* @param u32Value TCELR value
*/
LOCAL_INLINE void MSC_HWA_SetTcelr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCELR = u32Value;
}
/**
* @brief Get the IOCR register value
*
* @param pMsc MSCInstance
* @return IOCR value
*/
LOCAL_INLINE uint32_t MSC_HWA_GetIocr(MSC_Type *const pMsc)
{
return pMsc->IOCR;
}
/**
* @brief Set the IOCR register
*
* @param pMsc MSCInstance
* @param u32Value IOCR value
*/
LOCAL_INLINE void MSC_HWA_SetIocr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->IOCR = u32Value;
}
/**
* @brief Set the ISCR register
*
* @param pMsc MSCInstance
* @param u32Value ISCR value
*/
LOCAL_INLINE void MSC_HWA_SetIscr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->ISCR = u32Value;
}
/**
* @brief Set the msc TCDIS
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_SetTcdis(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_SDIS_MASK;
}
/**
* @brief Clear the msc TCDIS
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearTcdis(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_CDIS_MASK;
}
/**
* @brief Clear the msc CRFI
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearCrfi(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_CRFI_MASK;
}
/**
* @brief Clear the msc CTFI
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearCtfi(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_CTFI_MASK;
}
/**
* @brief Clear the msc CCFI
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearCcfi(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_CCFI_MASK;
}
/**
* @brief Clear the msc CDFI
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearCdfi(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_CDFI_MASK;
}
/**
* @brief Get the msc INSR register
*
* @param pMsc MSCInstance
* @return INSR register value
*/
LOCAL_INLINE uint32_t MSC_HWA_GetInsr(MSC_Type *const pMsc)
{
return pMsc->INSR & (uint32_t)MSC_INSR_MASK;
}
/**
* @brief Set the INCR register
*
* @param pMsc MSCInstance
* @param u32Value INCR value
*/
LOCAL_INLINE void MSC_HWA_SetIncr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->INCR = u32Value;
}
/**
* @brief Check the RFIE of INCR register
*
* @param pMsc MSCInstance
* @return RFIE enable
*/
LOCAL_INLINE bool MSC_HWA_GetRfieEnable(MSC_Type *const pMsc)
{
return (pMsc->INCR & MSC_INCR_RFIE_MASK) != 0U ? true : false;
}
/**
* @brief Set the RFIE of INCR register
*
* @param pMsc MSCInstance
* @param bEnable enable RFIE
*/
LOCAL_INLINE void MSC_HWA_SetRfieEnable(MSC_Type *const pMsc, bool bEnable)
{
pMsc->INCR = (pMsc->INCR & ~MSC_INCR_RFIE_MASK) | MSC_INCR_RFIE(bEnable);
}
/**
* @brief Check the TFIE of INCR register
*
* @param pMsc MSCInstance
* @return TFIE enable
*/
LOCAL_INLINE bool MSC_HWA_GetTfieEnable(MSC_Type *const pMsc)
{
return (pMsc->INCR & MSC_INCR_TFIE_MASK) == MSC_INCR_TFIE_MASK ? true : false;
}
/**
* @brief Set the TFIE of INCR register
*
* @param pMsc MSCInstance
* @param bEnable enable TFIE
*/
LOCAL_INLINE void MSC_HWA_SetTfieEnable(MSC_Type *const pMsc, bool bEnable)
{
pMsc->INCR = (pMsc->INCR & ~MSC_INCR_TFIE_MASK) | MSC_INCR_TFIE(bEnable);
}
/**
* @brief Check the CFIE of INCR register
*
* @param pMsc MSCInstance
* @return CFIE enable
*/
LOCAL_INLINE bool MSC_HWA_GetCfieEnable(MSC_Type *const pMsc)
{
return (pMsc->INCR & MSC_INCR_CFIE_MASK) == MSC_INCR_CFIE_MASK ? true : false;
}
/**
* @brief Set the CFIE of INCR register
*
* @param pMsc MSCInstance
* @param bEnable enable CFIE
*/
LOCAL_INLINE void MSC_HWA_SetCfieEnable(MSC_Type *const pMsc, bool bEnable)
{
pMsc->INCR = (pMsc->INCR & ~MSC_INCR_CFIE_MASK) | MSC_INCR_CFIE(bEnable);
}
/**
* @brief Check the DFIE of INCR register
*
* @param pMsc MSCInstance
* @return DFIE enable
*/
LOCAL_INLINE bool MSC_HWA_GetDfieEnable(MSC_Type *const pMsc)
{
return (pMsc->INCR & MSC_INCR_DFIE_MASK) == MSC_INCR_DFIE_MASK ? true : false;
}
/**
* @brief Set the DFIE of INCR register
*
* @param pMsc MSCInstance
* @param bEnable enable DFIE
*/
LOCAL_INLINE void MSC_HWA_SetDfieEnable(MSC_Type *const pMsc, bool bEnable)
{
pMsc->INCR = (pMsc->INCR & ~MSC_INCR_DFIE_MASK) | MSC_INCR_DFIE(bEnable);
}
/**
* @brief Check the TOIE of RTOR register
*
* @param pMsc MSCInstance
* @return TOIE enable
*/
LOCAL_INLINE bool MSC_HWA_GetToieEnable(MSC_Type *const pMsc)
{
return (pMsc->RTOR & MSC_RTOR_TOIE_MASK) == MSC_RTOR_TOIE_MASK ? true : false;
}
/**
* @brief Set the TOIE of RTOR register
*
* @param pMsc MSCInstance
* @param bEnable enable TOIE
*/
LOCAL_INLINE void MSC_HWA_SetToieEnable(MSC_Type *const pMsc, bool bEnable)
{
pMsc->RTOR = (pMsc->RTOR & ~MSC_RTOR_TOIE_MASK) | MSC_RTOR_TOIE(bEnable);
}
/**
* @brief Check the TOF of RTOR register
*
* @param pMsc MSCInstance
* @return TOIE enable
*/
LOCAL_INLINE bool MSC_HWA_GetTofEnable(MSC_Type *const pMsc)
{
return (pMsc->RTOR & MSC_RTOR_TOF_MASK) == MSC_RTOR_TOF_MASK ? true : false;
}
/**
* @brief Check the TOF of RTOR register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearTofEnable(MSC_Type *const pMsc)
{
pMsc->RTOR = (pMsc->RTOR & (~(MSC_RTOR_TOFC_MASK | MSC_RTOR_TOFS_MASK))) | MSC_RTOR_TOFC_MASK;
}
/**
* @brief Check the RX busy status of RCCSR register
*
* @param pMsc MSCInstance
* @return rx busy status
*/
LOCAL_INLINE bool MSC_HWA_GetRxBusy(MSC_Type *const pMsc)
{
return (pMsc->RCCSR & MSC_RCCSR_RX_BUSY_MASK) == MSC_RCCSR_RX_BUSY_MASK ? true : false;
}
/**
* @brief Get the msc RCCSR register
*
* @param pMsc MSCInstance
* @return RCCSR register value
*/
LOCAL_INLINE uint32_t MSC_HWA_GetRccsr(MSC_Type *const pMsc)
{
return pMsc->RCCSR;
}
/**
* @brief Set the RCCSR register
*
* @param pMsc MSCInstance
* @param u32Value RCCSR value
*/
LOCAL_INLINE void MSC_HWA_SetRccsr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->RCCSR = u32Value;
}
/**
* @brief Get the DATA of RDR0 register
*
* @param pMsc MSCInstance
* @return RDATA value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr0Data(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR0 & MSC_RDR0_RDATA_MASK) >> MSC_RDR0_RDATA_SHIFT);
}
/**
* @brief Get the LAF of RDR0 register
*
* @param pMsc MSCInstance
* @return LAF value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr0Addr(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR0 & MSC_RDR0_LAF_MASK) >> MSC_RDR0_LAF_SHIFT);
}
/**
* @brief Get the VLD of RDR0 register
*
* @param pMsc MSCInstance
* @return VLD value
*/
LOCAL_INLINE bool MSC_HWA_GetRdr0Vld(MSC_Type *const pMsc)
{
return (pMsc->RDR0 & MSC_RDR0_VLD_MASK) == MSC_RDR0_VLD_MASK ? true : false;
}
/**
* @brief Get the RERR of RDR0 register
*
* @param pMsc MSCInstance
* @return RERR value
*/
LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr0Rerr(MSC_Type *const pMsc)
{
uint32_t u32Tempvalue = (pMsc->RDR0 & MSC_RDR0_RERR_MASK) >> MSC_RDR0_RERR_SHIFT;
return (MSC_ReceiveStatusType)u32Tempvalue;
}
/**
* @brief Clear the VLD of register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearRdr0Vld(MSC_Type *const pMsc)
{
pMsc->RDR0 |= MSC_RDR0_CLR_MASK;
}
/**
* @brief Get the DATA of RDR1 register
*
* @param pMsc MSCInstance
* @return RDATA value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr1Data(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR1 & MSC_RDR1_RDATA_MASK) >> MSC_RDR1_RDATA_SHIFT);
}
/**
* @brief Get the LAF of RDR1 register
*
* @param pMsc MSCInstance
* @return LAF value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr1Addr(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR1 & MSC_RDR1_LAF_MASK) >> MSC_RDR1_LAF_SHIFT);
}
/**
* @brief Get the VLD of RDR1 register
*
* @param pMsc MSCInstance
* @return VLD value
*/
LOCAL_INLINE bool MSC_HWA_GetRdr1Vld(MSC_Type *const pMsc)
{
return (pMsc->RDR1 & MSC_RDR1_VLD_MASK) == MSC_RDR1_VLD_MASK ? true : false;
}
/**
* @brief Get the RERR of RDR1 register
*
* @param pMsc MSCInstance
* @return RERR value
*/
LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr1Rerr(MSC_Type *const pMsc)
{
uint32_t u32Tempvalue = (pMsc->RDR1 & MSC_RDR1_RERR_MASK) >> MSC_RDR1_RERR_SHIFT;
return (MSC_ReceiveStatusType)u32Tempvalue ;
}
/**
* @brief Clear the VLD of register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearRdr1Vld(MSC_Type *const pMsc)
{
pMsc->RDR1 |= MSC_RDR1_CLR_MASK;
}
/**
* @brief Get the DATA of RDR2 register
*
* @param pMsc MSCInstance
* @return RDATA value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr2Data(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR2 & MSC_RDR2_RDATA_MASK) >> MSC_RDR2_RDATA_SHIFT);
}
/**
* @brief Get the LAF of RDR2 register
*
* @param pMsc MSCInstance
* @return LAF value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr2Addr(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR2 & MSC_RDR2_LAF_MASK) >> MSC_RDR2_LAF_SHIFT);
}
/**
* @brief Get the VLD of RDR2 register
*
* @param pMsc MSCInstance
* @return VLD value
*/
LOCAL_INLINE bool MSC_HWA_GetRdr2Vld(MSC_Type *const pMsc)
{
return (pMsc->RDR2 & MSC_RDR2_VLD_MASK) == MSC_RDR2_VLD_MASK ? true : false;
}
/**
* @brief Get the RERR of RDR2 register
*
* @param pMsc MSCInstance
* @return RERR value
*/
LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr2Rerr(MSC_Type *const pMsc)
{
uint32_t u32Tempvalue = (pMsc->RDR2 & MSC_RDR2_RERR_MASK) >> MSC_RDR2_RERR_SHIFT;
return (MSC_ReceiveStatusType)u32Tempvalue;
}
/**
* @brief Clear the VLD of register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearRdr2Vld(MSC_Type *const pMsc)
{
pMsc->RDR2 |= MSC_RDR2_CLR_MASK;
}
/**
* @brief Get the DATA of RDR3 register
*
* @param pMsc MSCInstance
* @return RDATA value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr3Data(MSC_Type *const pMsc)
{
return (uint8_t)(pMsc->RDR3 & MSC_RDR3_RDATA_MASK) >> MSC_RDR3_RDATA_SHIFT;
}
/**
* @brief Get the LAF of RDR3 register
*
* @param pMsc MSCInstance
* @return LAF value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr3Addr(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR3 & MSC_RDR3_LAF_MASK) >> MSC_RDR3_LAF_SHIFT);
}
/**
* @brief Get the VLD of RDR3 register
*
* @param pMsc MSCInstance
* @return VLD value
*/
LOCAL_INLINE bool MSC_HWA_GetRdr3Vld(MSC_Type *const pMsc)
{
return (pMsc->RDR3 & MSC_RDR3_VLD_MASK) == MSC_RDR3_VLD_MASK ? true : false;
}
/**
* @brief Get the RERR of RDR3 register
*
* @param pMsc MSCInstance
* @return RERR value
*/
LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr3Rerr(MSC_Type *const pMsc)
{
uint32_t u32Tempvalue = (pMsc->RDR3 & MSC_RDR3_RERR_MASK) >> MSC_RDR3_RERR_SHIFT;
return (MSC_ReceiveStatusType)u32Tempvalue;
}
/**
* @brief Clear the VLD of register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearRdr3Vld(MSC_Type *const pMsc)
{
pMsc->RDR3 |= MSC_RDR3_CLR_MASK;
}
/**
* @brief Reset the msc
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_SetMsrRst(MSC_Type *const pMsc)
{
pMsc->MSR |= MSC_MSR_RST_MASK;
}
/**
* @brief Get the reset status
*
* @param pMsc MSCInstance
* @return reset status
*/
LOCAL_INLINE bool MSC_HWA_GetMsrRdone(MSC_Type *const pMsc)
{
return (bool)(((pMsc->MSR & MSC_MSR_RDONE_MASK) != 0U) ? true : false);
}
/**
* @brief clear reset status
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearMsrDone(MSC_Type *const pMsc)
{
pMsc->SRCR = MSC_SRCR_RCLR_MASK;
}
/**
* @brief Get the msc RTOR register
*
* @param pMsc MSCInstance
* @return RTOR register value
*/
LOCAL_INLINE uint32_t MSC_HWA_GetRtor(MSC_Type *const pMsc)
{
return pMsc->RTOR;
}
/**
* @brief Set the msc RTOR register
*
* @param pMsc MSCInstance
* @param u32Value RTOR value
*/
LOCAL_INLINE void MSC_HWA_SetRtor(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->RTOR = u32Value;
}
/**
* @brief Get the msc TCCTR1 register
*
* @param pMsc MSCInstance
* @return TCCTR1 register value
*/
LOCAL_INLINE uint32_t MSC_HWA_GetTcctr1(MSC_Type *const pMsc)
{
return pMsc->TCCTR1;
}
/**
* @brief Set the msc TCCTR1 register
*
* @param pMsc MSCInstance
* @param u32Value TCCTR1 value
*/
LOCAL_INLINE void MSC_HWA_SetTcctr1(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCCTR1 = u32Value;
}
/**
* @brief Set the EN msc GCR register
*
* @param pMsc MSCInstance
* @param bEnable EN value
*/
LOCAL_INLINE void MSC_HWA_SetMscEnable(MSC_Type *const pMsc, bool bEnable)
{
pMsc->GCR = (pMsc->GCR & ~MSC_GCR_EN_MASK) | MSC_GCR_EN(bEnable);
}
/**
* @brief Set the WP_EN of msc GCR register
*
* @param pMsc MSCInstance
* @param bEnable WP_EN value
*/
LOCAL_INLINE void MSC_HWA_SetMscWriteProtection(MSC_Type *const pMsc, bool bEnable)
{
pMsc->GCR = (pMsc->GCR & ~MSC_GCR_WP_EN_MASK) | MSC_GCR_WP_EN(bEnable);
}
/**
* @brief Unlock the msc CCULR register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_Unlock(MSC_Type *const pMsc)
{
pMsc->CCULR = 0x10248888U;
}
/** @}*/ /* HwA_msc */
#endif /* #ifndef _HWA_MSC_H_ */

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/**
* @file HwA_overlay.h
* @author Flagchip
* @brief FC4xxx Overlay hardware access layer
* @version 0.1.0
* @date 2023-12-25
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-29 Flagchip0038 N/A First version for FC7240
********************************************************************************/
#ifndef _HWA_OVERLAY_H_
#define _HWA_OVERLAY_H_
#include "device_header.h"
/**
* @defgroup HwA_overlay
* @ingroup fc7xxx_hwa_overlay
* @{
*/
/** Overlay Region Count */
#define OVERLYA_REGION_CNT 3U
/** FAR source address */
#define OVERLAY_FAR_SRC 0x08000000U
/** FAR max size */
#define OVERLAY_FAR_SIZE_MAX 0x2000000U
/** FAR size align */
#define OVERLAY_FAR_SIZE_ALIGN 0x10000U
/** FAR size max mask **/
#define OVERLAY_FAR_SIZE_MASK 0xFFFFU
/**
* @brief OVERlay Region size
*
*/
typedef enum
{
OVERLAY_OVERLAYSIZE_1KB = 0x1, /**< OVERLAY_OVERLAYSIZE_1KB, remapping overlay region size to 1KB */
OVERLAY_OVERLAYSIZE_2KB = 0x2, /**< OVERLAY_OVERLAYSIZE_2KB, remapping overlay region size to 2KB */
OVERLAY_OVERLAYSIZE_4KB = 0x4, /**< OVERLAY_OVERLAYSIZE_4KB, remapping overlay region size to 4KB */
OVERLAY_OVERLAYSIZE_8KB = 0x8, /**< OVERLAY_OVERLAYSIZE_8KB, remapping overlay region size to 8KB */
OVERLAY_OVERLAYSIZE_16KB = 0x10, /**< OVERLAY_OVERLAYSIZE_16KB, remapping overlay region size to 16KB */
OVERLAY_OVERLAYSIZE_32KB = 0x20, /**< OVERLAY_OVERLAYSIZE_32KB, remapping overlay region size to 32KB */
OVERLAY_OVERLAYSIZE_64KB = 0x40 /**< OVERLAY_OVERLAYSIZE_64KB, remapping overlay region size to 64KB */
}OVERLAY_OverlaySizeType;
/**
* @brief FAR Size
*
*/
typedef enum
{
OVERLAY_FARUINTSIZE_64KB = 0x10000, /**< OVERLAY_FARUINTSIZE_64KB, remapping far uint size to 64KB */
}OVERLAY_FARSizeType;
/**
* @brief enable overlay global switch
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayEnable(void)
{
AHB_OVERLAY->GLOBAL_EN |= AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK;
}
/**
* @brief disable overlay global switch
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayDisable(void)
{
AHB_OVERLAY->GLOBAL_EN &= ~((uint32_t)AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK);
}
/**
* @brief enable far global switch
*
*/
LOCAL_INLINE void OVERLAY_HWA_FAREnable(void)
{
AHB_OVERLAY->GLOBAL_EN |= AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK;
}
/**
* @brief disable far global switch
*
*/
LOCAL_INLINE void OVERLAY_HWA_FARDisable(void)
{
AHB_OVERLAY->GLOBAL_EN &= ~((uint32_t)AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK);
}
/**
* @brief enable overlay region 0
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayRegion0Enable(void)
{
AHB_OVERLAY->REGION_0_EN |= AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK;
}
/**
* @brief disable overlay region 0
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayRegion0Disable(void)
{
AHB_OVERLAY->REGION_0_EN &= ~((uint32_t)AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK);
}
/**
* @brief Set Overlay Region 0 Source
*
* @param u32Src Source address
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Src(uint32_t u32Src)
{
AHB_OVERLAY->REGION_0_SRC = AHB_OVERLAY_REGION_0_SRC_REGION0_SRC(u32Src);
}
/**
* @brief Set Overlay Region 0 Destination
*
* @param u32Dst Destination address
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Dst(uint32_t u32Dst)
{
AHB_OVERLAY->REGION_0_DST = AHB_OVERLAY_REGION_0_DST_REGION0_DST(u32Dst);
}
/**
* @brief Set Overlay Region 0 Size
*
* @param eSize size
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Size(OVERLAY_OverlaySizeType eSize)
{
AHB_OVERLAY->REGION_0_SIZE = AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE((uint32_t)eSize);
}
/**
* @brief enable overlay region 1
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayRegion1Enable(void)
{
AHB_OVERLAY->REGION_1_EN |= AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK;
}
/**
* @brief disable overlay region 1
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayRegion1Disable(void)
{
AHB_OVERLAY->REGION_1_EN &= ~((uint32_t)AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK);
}
/**
* @brief Set Overlay Region 1 Source
*
* @param u32Src Source address
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Src(uint32_t u32Src)
{
AHB_OVERLAY->REGION_1_SRC = AHB_OVERLAY_REGION_1_SRC_REGION1_SRC(u32Src);
}
/**
* @brief Set Overlay Region 1 Destination
*
* @param u32Dst Destination address
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Dst(uint32_t u32Dst)
{
AHB_OVERLAY->REGION_1_DST = AHB_OVERLAY_REGION_1_DST_REGION1_DST(u32Dst);
}
/**
* @brief Set Overlay Region 1 Size
*
* @param eSize size
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Size(OVERLAY_OverlaySizeType eSize)
{
AHB_OVERLAY->REGION_1_SIZE = AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE((uint32_t)eSize);
}
/**
* @brief enable overlay region 2
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayRegion2Enable(void)
{
AHB_OVERLAY->REGION_2_EN |= AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK;
}
/**
* @brief disable overlay region 2
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayRegion2Disable(void)
{
AHB_OVERLAY->REGION_2_EN &= ~((uint32_t)AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK);
}
/**
* @brief Set Overlay Region 2 Source
*
* @param u32Src Source address
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Src(uint32_t u32Src)
{
AHB_OVERLAY->REGION_2_SRC = AHB_OVERLAY_REGION_2_SRC_REGION2_SRC(u32Src);
}
/**
* @brief Set Overlay Region 2 Destination
*
* @param u32Dst Destination address
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Dst(uint32_t u32Dst)
{
AHB_OVERLAY->REGION_2_DST = AHB_OVERLAY_REGION_2_DST_REGION2_DST(u32Dst);
}
/**
* @brief Set Overlay Region 2 Size
*
* @param eSize size
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Size(OVERLAY_OverlaySizeType eSize)
{
AHB_OVERLAY->REGION_2_SIZE = AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE((uint32_t)eSize);
}
/**
* @brief Set Far Destination
*
* @param u32Dst Destination address, must pflash
*/
LOCAL_INLINE void OVERLAY_HWA_SetFarDst(uint32_t u32Dst)
{
AHB_OVERLAY->FAR_DST = AHB_OVERLAY_FAR_DST_FAR_DST_ADDR(u32Dst);
}
/**
* @brief Set Far Size
*
* @param u32Size size=(u32Size+1)*64KB
*/
LOCAL_INLINE void OVERLAY_HWA_SetFarSize(uint32_t u32Size)
{
AHB_OVERLAY->FAR_SIZE = AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL(u32Size);
}
/**
* @brief enable error interrupt
*
*/
LOCAL_INLINE void OVERLAY_HWA_ErrorInterruptEnable(void)
{
AHB_OVERLAY->INTR_EN |= AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK;
}
/**
* @brief disable error interrupt
*
*/
LOCAL_INLINE void OVERLAY_HWA_ErrorInterruptDisable(void)
{
AHB_OVERLAY->INTR_EN &= ~((uint32_t)AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK);
}
/**
* @brief get error flag
*
*/
LOCAL_INLINE uint32 OVERLAY_HWA_GetErrorFlag(void)
{
return (AHB_OVERLAY->INTR_FLAG & AHB_OVERLAY_INTR_FLAG_MASK);
}
/**
* @brief clear error flag
*
*/
LOCAL_INLINE uint32 OVERLAY_HWA_ClrErrorFlag(uint32_t u32ClrBits)
{
return AHB_OVERLAY->INTR_CLR |= AHB_OVERLAY_INTR_FLAG_MASK & u32ClrBits;
}
/** @}*/
#endif /* _HWA_OVERLAY_H_ */

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/**
* @file HwA_pcc.h
* @author Flagchip085
* @brief FC7xxx PCC register API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_PCC_H_
#define HWA_INCLUDE_HWA_PCC_H_
#include "device_header.h"
/**
* @defgroup HwA_pcc
* @ingroup HwA_pcc
* @{
*/
/** @brief Marco for PCCn Bit Field definition */
#define PCC_CGC_MASK 0x800000U
#define PCC_CGC_SHIFT 23U
#define PCC_CGC_WIDTH 1U
#define PCC_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_CGC_SHIFT))&PCC_CGC_MASK)
#define PCC_GetCGC(x) ((((uint32_t)(x))&PCC_CGC_MASK)>>PCC_CGC_SHIFT)
#define PCC_SEL_MASK 0x700000U
#define PCC_SEL_SHIFT 20U
#define PCC_SEL_WIDTH 3U
#define PCC_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_SEL_SHIFT))&PCC_SEL_MASK)
#define PCC_GetSEL(x) ((((uint32_t)(x))&PCC_SEL_MASK)>>PCC_SEL_SHIFT)
#define PCC_DIV_MASK 0x7U
#define PCC_DIV_SHIFT 0U
#define PCC_DIV_WIDTH 3U
#define PCC_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCC_DIV_SHIFT))&PCC_DIV_MASK)
#define PCC_GetDIV(x) ((((uint32_t)(x))&PCC_DIV_MASK)>>PCC_DIV_SHIFT)
#define PCC_SWR_MASK 0x10000u
/**
* @brief defined the clock source for function clock,match with PCC_XXX[SEL] bit filed.
*/
typedef enum
{
PCC_CLKGATE_SRC_OFF_OR_TCLK = 0U,
PCC_CLKGATE_SRC_FOSCDIV = 1U,
PCC_CLKGATE_SRC_SIRCDIV = 2U,
PCC_CLKGATE_SRC_FIRCDIV = 3U,
PCC_CLKGATE_SRC_RESERVE0 = 4U,
PCC_CLKGATE_SRC_PLL1DIV = 5U,
PCC_CLKGATE_SRC_PLL0DIV = 6U,
PCC_CLKGATE_SRC_RESERVE1 = 7U,
PCC_CLKGATE_UNINVOLVED = 8U
} PCC_ClkGateSrcType;
/**
* @brief define the clock divider,match with PCC_XXX[DIV] bit filed.
*/
typedef enum
{
PCC_CLK_DIV_BY1 = 0U, /*!< Divide by 1 (pass-through, no clock divide) */
PCC_CLK_DIV_BY2 = 1U, /*!< Divide by 2 */
PCC_CLK_DIV_BY3 = 2U, /*!< Divide by 3 */
PCC_CLK_DIV_BY4 = 3U, /*!< Divide by 4 */
PCC_CLK_DIV_BY5 = 4U, /*!< Divide by 5 */
PCC_CLK_DIV_BY6 = 5U, /*!< Divide by 6 */
PCC_CLK_DIV_BY7 = 6U, /*!< Divide by 7 */
PCC_CLK_DIV_BY8 = 7U, /*!< Divide by 8 */
PCC_CLK_UNINVOLVED = 8U /*!< Current peripheral dose not contain DIV configuration */
} PCC_ClkDivType;
/**
* @brief Get PCC register value
*
* @param u32Offset the PCC register offset
* @return uint32_t PCC register value
*/
LOCAL_INLINE uint32_t PCC_HWA_GetRegister(uint32_t u32Offset)
{
return *((uint32_t *)((uint32_t)PCC_BASE + u32Offset));
}
/**
* @brief Set PCC register value
*
* @param u32Offset the PCC register offset
* @param eValue value to set
*/
LOCAL_INLINE void PCC_HWA_SetRegister(uint32_t u32Offset,uint32_t eValue)
{
*((uint32_t *)((uint32_t)PCC_BASE + u32Offset)) = eValue;
}
/**
* @brief Get PCC clock gate control
*
* @param u32Offset the PCC register offset
* @return bool PCC clock enabled or disabled
*/
LOCAL_INLINE bool PCC_HWA_GetClockGateControl(uint32_t u32Offset)
{
uint32_t u32Value = *((uint32_t *)((uint32_t)PCC_BASE + u32Offset));
return (bool)PCC_GetCGC(u32Value);
}
/**
* @brief Set PCC clock gate control
*
* @param u32Offset the PCC register offset
* @param eSrc PCC clock source
*/
LOCAL_INLINE void PCC_HWA_SetClockGateControl(uint32_t u32Offset,bool bEnable)
{
uint32_t *pRegister = (uint32_t *)((uint32_t)PCC_BASE + u32Offset);
*pRegister = ((*pRegister) & (~PCC_CGC_MASK)) | PCC_CGC(bEnable);
}
/**
* @brief Get PCC clock source
*
* @param u32Offset the PCC register offset
* @return PCC_ClkGateSrcType PCC clock source
*/
LOCAL_INLINE PCC_ClkGateSrcType PCC_HWA_GetClockSource(uint32_t u32Offset)
{
uint32_t u32Value = *((uint32_t *)((uint32_t)PCC_BASE + u32Offset));
return (PCC_ClkGateSrcType)PCC_GetSEL(u32Value);
}
/**
* @brief Set PCC clock source
*
* @param u32Offset the PCC register offset
* @param eSrc PCC clock source
*/
LOCAL_INLINE void PCC_HWA_SetClockSource(uint32_t u32Offset,PCC_ClkGateSrcType eSrc)
{
uint32_t *pRegister = (uint32_t *)((uint32_t)PCC_BASE + u32Offset);
*pRegister = ((*pRegister) & (~PCC_SEL_MASK)) | PCC_SEL(eSrc);
}
/**
* @brief PCC peripheral software reset
*
* @param u32Offset the PCC register offset
*/
LOCAL_INLINE void PCC_HWA_SoftwareReset(uint32_t u32Offset)
{
*((uint32_t *)((uint32_t)PCC_BASE + u32Offset)) |= (uint32_t)PCC_SWR_MASK;
*((uint32_t *)((uint32_t)PCC_BASE + u32Offset)) &= ~(uint32_t)PCC_SWR_MASK;
}
/**
* @brief Get PCC divider
*
* @param u32Offset the PCC register offset
* @return PCC_ClkDivType PCC clock divider
*/
LOCAL_INLINE PCC_ClkDivType PCC_HWA_GetDivider(uint32_t u32Offset)
{
uint32_t u32Value = *((uint32_t *)((uint32_t)PCC_BASE + u32Offset));
return (PCC_ClkDivType)PCC_GetDIV(u32Value);
}
/**
* @brief Set PCC register value
*
* @param u32Offset the PCC register offset
* @param eDivider PCC clock divider
*/
LOCAL_INLINE void PCC_HWA_SetDivider(uint32_t u32Offset,PCC_ClkDivType eDivider)
{
uint32_t *pRegister = (uint32_t *)((uint32_t)PCC_BASE + u32Offset);
*pRegister = ((*pRegister) & (~PCC_DIV_MASK)) | PCC_DIV(eDivider);
}
/** @}*/
#endif /* HWA_INCLUDE_HWA_PCC_H_ */

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/**
* @file HwA_pmc.h
* @author Flagchip0105
* @brief FC7xxx PMC register API
* @version 0.1.0
* @date 2024-01-08
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-08 Flagchip0105 N/A First version for FC7240
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_PMC_H_
#define HWA_INCLUDE_HWA_PMC_H_
#include "device_header.h"
/**
* @defgroup HwA_pmc
* @ingroup fc7xxx_driver_pmc
* @{
*/
/**
* @brief get PMC LVCSR register
*
* @return uint32_t LVCSR register value
*/
LOCAL_INLINE uint32_t PMC_HWA_GetLVCSRRegister(void)
{
return (uint32)(PMC->LVSCR);
}
/**
* @brief set PMC LVCSR register.
*
* This function configures the PMC LVCSR registe.
*
* @param u32LvcsrValue Set PMC LVCSR register value.
*/
LOCAL_INLINE void PMC_HWA_SetLVCSRRegister(uint32_t u32LvcsrValue)
{
PMC->LVSCR = u32LvcsrValue;
}
/**
* @brief get PMC CONFIG register
*
* @return uint32_t CONFIG register value
*/
LOCAL_INLINE uint32_t PMC_HWA_GetConfigRegister(void)
{
return (uint32)(PMC -> CONFIG);
}
/**
* @brief set PMC CONFIG register.
*
* This function configures the PMC CONFIG registe.
*
* @param u32LVSCRValue Set PMC CONFIG register value.
*/
LOCAL_INLINE void PMC_HWA_SetConfigRegister(uint32_t u32LVSCRValue)
{
PMC -> CONFIG = u32LVSCRValue;
}
/**
* @brief Unlock control for V15_EXT_EN and V15_AUTOSW
*
*/
LOCAL_INLINE void PMC_HWA_UnlockConfigRegister(void)
{
PMC->CONFIG &= ~(uint32_t)PMC_CONFIG_V15_LOCK_MASK;
}
/**
* @brief lock control for V15_EXT_EN and V15_AUTOSW
*
*/
LOCAL_INLINE void PMC_HWA_LockConfigRegister(void)
{
PMC->CONFIG |= (uint32_t)PMC_CONFIG_V15_LOCK_MASK;
}
/** @}*/
#endif /* HWA_INCLUDE_HWA_PMC_H_ */

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/**
* @file HwA_ptimer.h
* @author Flagchip0126
* @brief Hardware access layer for PTIMER
* @version 0.1.0
* @date 2024-01-15
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_PTIMER_H_
#define _HWA_PTIMER_H_
#include "device_header.h"
/**
* @defgroup HwA_ptimer
* @ingroup fc4xxx_driver_ptimer
* @{
*/
/**
* @brief Ptimer value load mode
*
* Some Ptimer registers are buffered and will only take effect after called
* PTIMER_LoadValue() function, and this option selects when the buffered configurations
* will tack effect after PTIMER_LoadValue() is called.
*
*/
typedef enum
{
PTIMER_LOAD_VAL_IMMEDIATELY = 0U,
/*!< Loaded immediately after load operation. */
PTIMER_LOAD_VAL_AT_MODULO_COUNTER = 1U,
/*!< Loaded when counter hits the max count after load operation. */
PTIMER_LOAD_VAL_AT_NEXT_TRIGGER = 2U,
/*!< Loaded when detecting an input trigger after load operation. */
PTIMER_LOAD_VAL_AT_MODULO_COUNTER_OR_NEXT_TRIGGER = 3U
/*!< Loaded when counter hits the max count or detecting an input trigger after load operation. */
} PTIMER_LoadValueModeType;
/**
* @brief Ptimer clock pre-divider factor
*
* The Ptimer clock source is from core clock and the divider is a multiplication of
* PTIMER_ClockPreDividerType and PTIMER_ClockPreDivMultiplyFactorType, and thus:
* Freq = Core_Freq / (PTIMER_ClockPreDividerType * PTIMER_ClockPreDivMultiplyFactorType)
*
*/
typedef enum
{
PTIMER_PRE_DIVIDE_BY_1 = 0U,
PTIMER_PRE_DIVIDE_BY_2 = 1U,
PTIMER_PRE_DIVIDE_BY_4 = 2U,
PTIMER_PRE_DIVIDE_BY_8 = 3U,
PTIMER_PRE_DIVIDE_BY_16 = 4U,
PTIMER_PRE_DIVIDE_BY_32 = 5U,
PTIMER_PRE_DIVIDE_BY_64 = 6U,
PTIMER_PRE_DIVIDE_BY_128 = 7U
} PTIMER_ClockPreDividerType;
/**
* @brief Ptimer clock divider multiplication factor
*
* The Ptimer clock source is from core clock and the divider is a multiplication of
* PTIMER_ClockPreDividerType and PTIMER_ClockPreDivMultiplyFactorType, and thus:
* Freq = Core_Freq / (PTIMER_ClockPreDividerType * PTIMER_ClockPreDivMultiplyFactorType)
*
*/
typedef enum
{
PTIMER_PRE_DIVIDER_MULTIPLY_BY_1 = 0U,
PTIMER_PRE_DIVIDER_MULTIPLY_BY_10 = 1U,
PTIMER_PRE_DIVIDER_MULTIPLY_BY_20 = 2U,
PTIMER_PRE_DIVIDER_MULTIPLY_BY_40 = 3U
} PTIMER_ClockPreDivMultiplyFactorType;
/**
* @brief Ptimer trigger source
*
*/
typedef enum
{
PTIMER_TRGSRC_TRGSEL = 0x00U, /*!< Ptimer trigger source from TrgSel */
PTIMER_TRGSRC_SW = 0x0FU /*!< Ptimer trigger source from software trigger*/
} PTIMER_TrgSrcType;
/**
* @brief Get the STATUS_CTRL register value
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE uint32_t PTIMER_HWA_GetStatusCtrl(const PTIMER_Type *const pPtimer)
{
return pPtimer->STATUS_CTRL;
}
/**
* @brief Set the STATUS_CTRL register value
*
* @param pPtimer the base address of the Ptimer instance
* @param u32CfgValue the register value to set
*/
LOCAL_INLINE void PTIMER_HWA_SetStatusCtrl(PTIMER_Type *const pPtimer, uint32_t u32CfgValue)
{
pPtimer->STATUS_CTRL = u32CfgValue;
}
/**
* @brief Get the load mode of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @return PTIMER_LoadValueModeType the load mode of the Ptimer instance
*/
LOCAL_INLINE PTIMER_LoadValueModeType PTIMER_HWA_GetLoadMode(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_LDMODE_MASK) >> PTIMER_STATUS_CTRL_LDMODE_SHIFT;
return (PTIMER_LoadValueModeType)u32TmpVal;
}
/**
* @brief Set the load mode of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param eLoadMode the load mode of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetLoadMode(PTIMER_Type *const pPtimer, PTIMER_LoadValueModeType eLoadMode)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_LDMODE_MASK) | PTIMER_STATUS_CTRL_LDMODE(eLoadMode);
}
/**
* @brief Get whether sequence error interrupt is enabled
*
* @param pPtimer the base address of the Ptimer instance
* @return true sequence error interrupt is enabled
* @return false sequence error interrupt is disabled
*/
LOCAL_INLINE bool PTIMER_HWA_GetSeqErrIntEnableFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_SERR_INTEN_MASK) >> PTIMER_STATUS_CTRL_SERR_INTEN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set whether to enable sequence error interrupt
*
* @param pPtimer the base address of the Ptimer instance
* @param bEnable whether to enable sequence error interrupt
*/
LOCAL_INLINE void PTIMER_HWA_SetSeqErrIntEnableFlag(PTIMER_Type *const pPtimer, bool bEnable)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_SERR_INTEN_MASK) | PTIMER_STATUS_CTRL_SERR_INTEN(
bEnable ? 1U : 0U);
}
/**
* @brief Generate software trigger signal for Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_GenerateSwTrigger(PTIMER_Type *const pPtimer)
{
pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_SWTRG_MASK;
}
/**
* @brief Get whether DMA is enabled for the Ptimer insstance
*
* @param pPtimer the base address of the Ptimer instance
* @return true DMA is enabled
* @return false DMA is disabled
*/
LOCAL_INLINE bool PTIMER_HWA_GetDMAEnableFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_DMAEN_MASK) >> PTIMER_STATUS_CTRL_DMAEN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set whether to enable Ptimer DMA
*
* @param pPtimer the base address of the Ptimer instance
* @param bEnable whether to enable DMA for the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetDMAEnableFlag(PTIMER_Type *const pPtimer, bool bEnable)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_DMAEN_MASK) | PTIMER_STATUS_CTRL_DMAEN(bEnable ? 1U : 0U);
}
/**
* @brief Get the predivider value of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @return PTIMER_ClockPreDividerType the predivider of the Ptimer instance
*/
LOCAL_INLINE PTIMER_ClockPreDividerType PTIMER_HWA_GetDivPrescaler(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_PRESCALER_MASK) >> PTIMER_STATUS_CTRL_PRESCALER_SHIFT;
return (PTIMER_ClockPreDividerType)u32TmpVal;
}
/**
* @brief Set the predivider value of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param eDivPrescaler the predivider of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetDivPrescaler(PTIMER_Type *const pPtimer, PTIMER_ClockPreDividerType eDivPrescaler)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_PRESCALER_MASK) | PTIMER_STATUS_CTRL_PRESCALER(
eDivPrescaler);
}
/**
* @brief Get the trigger source of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @return PTIMER_TRGSRC_TRGSEL the trigger source is from TrgSel
* @return PTIMER_TRGSRC_SW the trigger source is from software
*/
LOCAL_INLINE PTIMER_TrgSrcType PTIMER_HWA_GetTriggerSource(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_TRGSEL_MASK) >> PTIMER_STATUS_CTRL_TRGSEL_SHIFT;
return (PTIMER_TrgSrcType)u32TmpVal;
}
/**
* @brief Set the trigger source of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param eTriggerSource the trigger source of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetTriggerSource(PTIMER_Type *const pPtimer, PTIMER_TrgSrcType eTriggerSource)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_TRGSEL_MASK) | PTIMER_STATUS_CTRL_TRGSEL(
eTriggerSource);
}
/**
* @brief Get whether the Ptimer instance is enabled
*
* @param pPtimer the base address of the Ptimer instance
* @return true the Ptimer instance is enabled
* @return false the Ptimer instance is disabled
*/
LOCAL_INLINE bool PTIMER_HWA_GetEnableFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_ENABLE_MASK) >> PTIMER_STATUS_CTRL_ENABLE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Enable the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_Enable(PTIMER_Type *const pPtimer)
{
pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_ENABLE_MASK;
}
/**
* @brief Disable the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_Disable(PTIMER_Type *const pPtimer)
{
pPtimer->STATUS_CTRL &= ~PTIMER_STATUS_CTRL_ENABLE_MASK;
}
/**
* @brief Get the delay interrupt flag of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @return true the delay interrupt flag of the Ptimer instance is generated
* @return false the delay interrupt flag of the Ptimer instance is not generated
*/
LOCAL_INLINE bool PTIMER_HWA_GetInterruptFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_INTFLAG_MASK) >> PTIMER_STATUS_CTRL_INTFLAG_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the delay interrupt flag of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_ClearInterruptFlag(PTIMER_Type *const pPtimer)
{
pPtimer->STATUS_CTRL &= ~PTIMER_STATUS_CTRL_INTFLAG_MASK;
}
/**
* @brief Get whether delay interrupt is enabled for the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE bool PTIMER_HWA_GetInterruptEnableFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_INTEN_MASK) >> PTIMER_STATUS_CTRL_INTEN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set whether to enable delay interrupt for the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param bEnable whether to enable delay interrupt for the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetInterruptEnableFlag(PTIMER_Type *const pPtimer, bool bEnable)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_INTEN_MASK) | PTIMER_STATUS_CTRL_INTEN(bEnable ? 1U : 0U);
}
/**
* @brief Get the multiply factor of the predivider of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @return PTIMER_ClockPreDivMultiplyFactorType the multiply factor of the Ptimer instance
*/
LOCAL_INLINE PTIMER_ClockPreDivMultiplyFactorType PTIMER_HWA_GetDivMultiply(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_MULT_MASK) >> PTIMER_STATUS_CTRL_MULT_SHIFT;
return (PTIMER_ClockPreDivMultiplyFactorType)u32TmpVal;
}
/**
* @brief Set the multiply factor of the predivider of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param eMultFactor the multiply factor of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetDivMultiply(PTIMER_Type *const pPtimer,
PTIMER_ClockPreDivMultiplyFactorType eMultFactor)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_MULT_MASK) | PTIMER_STATUS_CTRL_MULT(eMultFactor);
}
/**
* @brief Get whether continuous mode is enabled for the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @return true continuous mode is enabled for the Ptimer instance
* @return false continuous mode is disabled for the Ptimer instance
*/
LOCAL_INLINE bool PTIMER_HWA_GetContinuoiusModeFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_CONT_MASK) >> PTIMER_STATUS_CTRL_CONT_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set whether to enable continuous mode for the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param bEnable whether to enable continuous mode for the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetContinuoiusModeFlag(PTIMER_Type *const pPtimer, bool bEnable)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_CONT_MASK) | PTIMER_STATUS_CTRL_CONT(bEnable ? 1U : 0U);
}
/**
* @brief Get the config value loading status
*
* @param pPtimer the base address of the Ptimer instance
* @return true the config values are in loading status
* @return false the config values are loaded
*/
LOCAL_INLINE bool PTIMER_HWA_GetValueLoadStatus(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_LDOK_MASK) >> PTIMER_STATUS_CTRL_LDOK_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Load the buffered values into register
*
* @note Some Ptimer registers are buffered and will only take effect after called
* this function
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_LoadValue(PTIMER_Type *const pPtimer)
{
pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_LDOK_MASK;
}
/**
* @brief Get the Ptimer max counter period
* When the Ptimer counter reaches the period, it will return to zero
*
* @param pPtimer the base address of the Ptimer instance
* @return uint16_t the Ptimer max count
*/
LOCAL_INLINE uint16_t PTIMER_HWA_GetMaxCount(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->MAX_CNT & PTIMER_MAX_CNT_MAX_CNT_MASK) >> PTIMER_MAX_CNT_MAX_CNT_SHIFT;
return (uint16_t)u32TmpVal;
}
/**
* @brief Set the Ptimer max counter period
* When the Ptimer counter reaches the period, it will return to zero
*
* @note the period parameter is buffered and will take effect only after called PTIMER_LoadValue()
* function.
*
* @param pPtimer the base address of the Ptimer instance
* @param u16MaxCnt the Ptimer max count
*/
LOCAL_INLINE void PTIMER_HWA_SetMaxCount(PTIMER_Type *const pPtimer, uint16_t u16MaxCnt)
{
pPtimer->MAX_CNT = PTIMER_MAX_CNT_MAX_CNT(u16MaxCnt);
}
/**
* @brief Get the Ptimer current count value
*
* @param pPtimer the base address of the Ptimer instance
* @return uint16_t the Ptimer current count value
*/
LOCAL_INLINE uint16_t PTIMER_HWA_GetCounterValue(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->CNT & PTIMER_CNT_CNT_MASK) >> PTIMER_CNT_CNT_SHIFT;
return (uint16_t)u32TmpVal;
}
/**
* @brief Get the ptimer interrupt period
*
* @param pPtimer the base address of the Ptimer instance
* @return uint16_t the Ptimer interrupt period
*/
LOCAL_INLINE uint16_t PTIMER_HWA_GetInterruptDelay(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->INT_DLY & PTIMER_INT_DLY_INT_DLY_MASK) >> PTIMER_INT_DLY_INT_DLY_SHIFT;
return (uint16_t)u32TmpVal;
}
/**
* @brief Set the ptimer interrupt period
*
* @param pPtimer the base address of the Ptimer instance
* @param u16InterruptDelay the Ptimer interrupt period
*/
LOCAL_INLINE void PTIMER_HWA_SetInterruptDelay(PTIMER_Type *const pPtimer, uint16_t u16InterruptDelay)
{
pPtimer->INT_DLY = PTIMER_INT_DLY_INT_DLY(u16InterruptDelay);
}
/**
* @brief Get whether back to back trigger is enbaled for the Ptimer channel
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @return true back to back trigger is enbaled for the Ptimer channel
* @return false back to back trigger is disabled for the Ptimer channel
*/
LOCAL_INLINE bool PTIMER_HWA_GetChannelBackToBackFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerCtrlIdx = u8Channel % 8U;
uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_BTB(1UL << u8PtimerCtrlIdx)) >>
(PTIMER_CTRL_CH_BTB_SHIFT + u8PtimerCtrlIdx);
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get whether pre-trigger output is enbaled for the Ptimer channel
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @return true pre-trigger output is enbaled for the Ptimer channel
* @return false pre-trigger output is disabled for the Ptimer channel
*/
LOCAL_INLINE bool PTIMER_HWA_GetChannelPretriggerOutputFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerCtrlIdx = u8Channel % 8U;
uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_PTOS(1UL << u8PtimerCtrlIdx)) >>
(PTIMER_CTRL_CH_PTOS_SHIFT + u8PtimerCtrlIdx);
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get whether pre-trigger is enbaled for the Ptimer channel
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @return true pre-trigger is enbaled for the Ptimer channel
* @return false pre-trigger is disabled for the Ptimer channel
*/
LOCAL_INLINE bool PTIMER_HWA_GetChannelPretriggerEnableFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerCtrlIdx = u8Channel % 8U;
uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_PTEN(1UL << u8PtimerCtrlIdx)) >>
(PTIMER_CTRL_CH_PTEN_SHIFT + u8PtimerCtrlIdx);
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Ptimer channel control flags
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @param bEnablePretrigger whether to enable pre-trigger
* @param bEnablePretriggerOutput whether to enable pre-trigger output
* @param bEnableBackToBack whether to enable back to back trigger
*/
LOCAL_INLINE void PTIMER_HWA_SetChannelControl(PTIMER_Type *const pPtimer, uint8_t u8Channel, bool bEnablePretrigger,
bool bEnablePretriggerOutput, bool bEnableBackToBack)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerCtrlIdx = u8Channel % 8U;
uint32_t u32CtrlMask = PTIMER_CTRL_CH_PTEN(1UL << u8PtimerCtrlIdx) |
PTIMER_CTRL_CH_PTOS(1UL << u8PtimerCtrlIdx) |
PTIMER_CTRL_CH_BTB(1UL << u8PtimerCtrlIdx);
pPtimer->CH[u8PtimerChannelIdx].CTRL = (pPtimer->CH[u8PtimerChannelIdx].CTRL & ~u32CtrlMask) |
PTIMER_CTRL_CH_PTEN((bEnablePretrigger ? 1UL : 0UL) << u8PtimerCtrlIdx) |
PTIMER_CTRL_CH_PTOS((bEnablePretriggerOutput ? 1UL : 0UL) << u8PtimerCtrlIdx) |
PTIMER_CTRL_CH_BTB((bEnableBackToBack ? 1UL : 0UL) << u8PtimerCtrlIdx);
}
/**
* @brief Get whether the Ptimer counter matches the channel counter
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @return true the Ptimer counter matches the channel counter
* @return false the Ptimer counter has not reached the channel counter
*/
LOCAL_INLINE bool PTIMER_HWA_GetChannelCounterFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerStatusIdx = u8Channel % 8U;
uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].STATUS & PTIMER_STATUS_CH_CHN_FLAG(1UL << u8PtimerStatusIdx)) >>
(PTIMER_STATUS_CH_CHN_FLAG_SHIFT + u8PtimerStatusIdx);
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the Ptimer channel counter match flag
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
*/
LOCAL_INLINE void PTIMER_HWA_ClearChannelCounterFlag(PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerStatusIdx = u8Channel % 8U;
pPtimer->CH[u8PtimerChannelIdx].STATUS &= ~PTIMER_STATUS_CH_CHN_FLAG(1UL << u8PtimerStatusIdx);
}
/**
* @brief Get the sequence error status of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the channel related to the sequence error
* @return true the selected channel has sequence error
* @return false the selected channel does not have sequence error
*/
LOCAL_INLINE bool PTIMER_HWA_GetChannelSequenceErrorFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerStatusIdx = u8Channel % 8U;
uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].STATUS & PTIMER_STATUS_CH_SERR_FLAG(1UL << u8PtimerStatusIdx)) >>
(PTIMER_STATUS_CH_SERR_FLAG_SHIFT + u8PtimerStatusIdx);
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the sequence error flag of the selected Ptimer channel
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel to clear the sequence error flag
*/
LOCAL_INLINE void PTIMER_HWA_ClearChannelSequenceErrorFlag(PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerStatusIdx = u8Channel % 8U;
pPtimer->CH[u8PtimerChannelIdx].STATUS &= ~PTIMER_STATUS_CH_SERR_FLAG(1UL << u8PtimerStatusIdx);
}
/**
* @brief Get the channel delay value
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @return uint16_t the channel delay value
*/
LOCAL_INLINE uint16_t PTIMER_HWA_GetChannelDelay(const PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / PTIMER_CH_DLY_CNT;
uint8_t u8PtimerDelayIdx = u8Channel % PTIMER_CH_DLY_CNT;
uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].DLY[u8PtimerDelayIdx] & PTIMER_DLY_CH_CHNDLY_MASK) >>
PTIMER_DLY_CH_CHNDLY_SHIFT;
return (uint16_t)u32TmpVal;
}
/**
* @brief Set the channel delay value
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @param u16Delay the channel delay value
*/
LOCAL_INLINE void PTIMER_HWA_SetChannelDelay(PTIMER_Type *const pPtimer, uint8_t u8Channel, uint16_t u16Delay)
{
uint8_t u8PtimerChannelIdx = u8Channel / PTIMER_CH_DLY_CNT;
uint8_t u8PtimerDelayIdx = u8Channel % PTIMER_CH_DLY_CNT;
pPtimer->CH[u8PtimerChannelIdx].DLY[u8PtimerDelayIdx] = PTIMER_DLY_CH_CHNDLY(u16Delay);
}
/**
* @brief Get whether pulse-out is enabled
*
* @param pPtimer the base address of the Ptimer instance
* @return true pulse-out is enabled
* @return false pulse-out is disabled
*/
LOCAL_INLINE bool PTIMER_HWA_GetPulseOutEnableFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->POEN & PTIMER_POEN_POEN_MASK) >> PTIMER_POEN_POEN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Enable pulse-out for the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_EnablePulseOut(PTIMER_Type *const pPtimer)
{
pPtimer->POEN |= PTIMER_POEN_POEN_MASK;
}
/**
* @brief Disable pulse-out for the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_DisablePulseOut(PTIMER_Type *const pPtimer)
{
pPtimer->POEN &= ~PTIMER_POEN_POEN_MASK;
}
/**
* @brief Get the delay high value for the pulse-out function
* When the Ptimer counter reach the delay high value, the pulse output goes high
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE uint16_t PTIMER_HWA_GetPulseOutDelayHigh(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->PODLY & PTIMER_PODLY_DLY1_MASK) >> PTIMER_PODLY_DLY1_SHIFT;
return (uint16_t)u32TmpVal;
}
/**
* @brief Get the delay low value for the pulse-out function
* When the Ptimer counter reach the delay low value, the pulse output goes low
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE uint16_t PTIMER_HWA_GetPulseOutDelayLow(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->PODLY & PTIMER_PODLY_DLY2_MASK) >> PTIMER_PODLY_DLY2_SHIFT;
return (uint16_t)u32TmpVal;
}
/**
* @brief Set the pulse out delay value
* When the Ptimer counter reach the delay high value, the pulse output goes high
* When the Ptimer counter reach the delay low value, the pulse output goes low
* The delay high value can be either greater or less than the delay low value
*
* @param pPtimer the base address of the Ptimer instance
* @param u16DelayHigh the delay high value
* @param u16DelayLow the delay low value
*/
LOCAL_INLINE void PTIMER_HWA_SetPulseOutDelay(PTIMER_Type *const pPtimer, uint16_t u16DelayHigh, uint16_t u16DelayLow)
{
pPtimer->PODLY = PTIMER_PODLY_DLY1(u16DelayHigh) | PTIMER_PODLY_DLY2(u16DelayLow);
}
/** @}*/
#endif /* _HWA_PTIMER_H_ */

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/**
* @file HwA_rgm.h
* @author Flagchip
* @brief FC7xxx RGM hardware access layer
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_RGM_H_
#define _HWA_RGM_H_
#include "device_header.h"
/********* Local typedef ************/
/** @brief Rgm reset event */
typedef enum
{
RGM_WAKEUP = 0x00000001U,
RGM_LVD = 0x00000002U,
RGM_CLKERR1 = 0x00000004U,
RGM_CLKERR0 = 0x00000008U,
RGM_FSCMU = 0x00000010U,
RGM_HSMWDOG = 0x00000020U,
RGM_PIN = 0x00000040U,
RGM_POR = 0x00000080U,
RGM_JTAG = 0x00000100U,
RGM_SYSAP = 0x00000800U,
RGM_WDOG1 = 0x00001000U,
RGM_SACKERR = 0x00002000U,
RGM_CMU = 0x00004000U,
RGM_LBIST = 0x00008000U,
RGM_FSMERR = 0x20000000U,
RGM_PINRSTTOUT = 0x40000000U,
RGM_SYSRSTTOUT = 0x80000000U
} RGM_ResetEventType;
/** @brief Rgm reset interrupt delay cycles type. */
typedef enum
{
RGM_8_CLOCK_CYCLES = 0x00U,
RGM_32_CLOCK_CYCLES = 0x01U,
RGM_128_CLOCK_CYCLES = 0x02U,
RGM_512_CLOCK_CYCLES = 0x03U
} RGM_ResetDelayType;
/** @brief Rgm reset interrupt event manger */
typedef enum
{
RGM_INT_CLKERR0 = 0x0008U,
RGM_INT_FCSMU = 0x0010U,
RGM_INT_WDG = 0x0020U,
RGM_INT_PIN = 0x0040U,
RGM_INT_JTAG = 0x0100U,
RGM_INT_CPULOC = 0x0200U,
RGM_INT_SW = 0x0400U,
RGM_INT_SYSAP = 0x0800U,
RGM_INT_WDOG1 = 0x1000U,
RGM_INT_SACKERR = 0x2000U,
RGM_INT_CMU = 0x4000U
} RGM_ResetIntMangerType;
/** @brief Select the Rgm CORE Write protection */
typedef enum
{
RGM_WPB_ALL = 0x00U,
RGM_WPB_CPU0 = 0x01U,
RGM_WPB_NOCORE = 0x04U
} RGM_WriteprotectionBitType;
/** @brief Rgm CPU0,1,2 related interrupt event manger */
typedef enum
{
RGM_CPU_INT_LOCKUP = 0x01U,
RGM_CPU_INT_SYSRST = 0x02U,
RGM_CPU_INT_WDOG = 0x04U,
RGM_CPU_INT_INTM = 0x08U,
RGM_CPU_INT_SWRST = 0x10U
} RGM_CPUIntMangerType;
/** @brief Rgm CPU0,1,2 software reset status */
typedef enum
{
RGM_CPU_OUT_RST_UNDER = 0x00U,
RGM_CPU_OUT_RST_OUT = 0x01U
} RGM_CPUOutResetType;
/** @brief Rgm CPU0,1,2 reset event */
typedef enum
{
RGM_CPU_WAKEUP = 0x00000001U,
RGM_CPU_LVD = 0x00000002U,
RGM_CPU_CLKERR1 = 0x00000004U,
RGM_CPU_CLKERR0 = 0x00000008U,
RGM_CPU_FSCMU = 0x00000010U,
RGM_CPU_HSMWDOG = 0x00000020U,
RGM_CPU_PIN = 0x00000040U,
RGM_CPU_POR = 0x00000080U,
RGM_CPU_JTAG = 0x00000100U,
RGM_CPU_SYSAP = 0x00000800U,
RGM_CPU_WDOG1 = 0x00001000U,
RGM_CPU_SACKERR = 0x00002000U,
RGM_CPU_CMU = 0x00004000U,
RGM_CPU_LBIST = 0x00008000U,
RGM_CPU_LOCKUP = 0x00010000U,
RGM_CPU_SYSRST = 0x00020000U,
RGM_CPU_WDOG = 0x00040000U,
RGM_CPU_INTM = 0x00080000U,
RGM_CPU_SWRST = 0x00100000U,
RGM_CPU_FSMERR = 0x20000000U,
RGM_CPU_PINRSTTOUT = 0x40000000U,
RGM_CPU_SYSRSTTOUT = 0x80000000U
} RGM_CPUResetEventType;
/** @brief Rgm CPU1,2 system reset enable flag */
typedef enum
{
RGM_CPU_EN_LOCKUP = 0x00010000U,
RGM_CPU_EN_SYSRST = 0x00020000U,
RGM_CPU_EN_WDOG = 0x00040000U,
RGM_CPU_EN_INTM = 0x00080000U,
RGM_CPU_EN_SWRST = 0x00100000U,
} RGM_CPUSystemRstMangerType;
/********* Local inline function ************/
/**
* @brief Read last reset flag
*
* @return Last reset flag
*/
LOCAL_INLINE uint32_t RGM_HWA_ReadLastResetFlag(void)
{
return (uint32_t)RGM->SRS;
}
/**
* @brief Read all reset flag before POR,SSRS register is reset on POR only
*
* @return All reset flag before POR
*/
LOCAL_INLINE uint32_t RGM_HWA_ReadAllResetFlagBeforePOR(void)
{
return (uint32_t)RGM->SSRS;
}
/**
* @brief Read reset pin filter register
*
* @return Reset pin filter register
*/
LOCAL_INLINE uint32_t RGM_HWA_ReadResetPinFilterEnable(void)
{
return (uint32_t)RGM->RSTFLT;
}
/**
* @brief This api can clear reset flag of SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
*
* @param eReset Reset flag
*/
LOCAL_INLINE void RGM_HWA_ClearResetFlagAfterPOR(RGM_ResetEventType eReset)
{
RGM->SSRS = (uint32_t)(eReset);
}
/**
* @brief This api can clear all reset flag of SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
*
*/
LOCAL_INLINE void RGM_HWA_ClearAllResetFlagAfterPOR(void)
{
RGM->SSRS = (uint32_t)0xE000F9FFU;
}
/**
* @brief Set reset pin filter bus clock filter width
*
* @param u8Value Bus clock filter width value
*/
LOCAL_INLINE void RGM_HWA_SetBusClockFilterWidth(uint8_t u8Value)
{
uint32_t u32RegValue = RGM->RSTFLT;
RGM->RSTFLT = (u32RegValue & ~(uint32_t)RGM_RSTFLT_RSTFLT_BUSW_MASK) | RGM_RSTFLT_RSTFLT_BUSW(u8Value);
}
/**
* @brief Enable reset pin filter bus clock
*
*/
LOCAL_INLINE void RGM_HWA_EnableBusClockFilter(void)
{
RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_BUS_MASK;
}
/**
* @brief Enable reset pin filter AON32K clock
*
*/
LOCAL_INLINE void RGM_HWA_EnableAon32kClockFilter(void)
{
RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_AON_MASK;
}
/**
* @brief Enable reset pin filter AON32K low power clock
*
*/
LOCAL_INLINE void RGM_HWA_EnableAon32kLPClockFilter(void)
{
RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_AON_LP_MASK;
}
/**
* @brief Clear reset pin filter bus clock filter width
*
*/
LOCAL_INLINE void RGM_HWA_ClearBusClockFilterWidth(void)
{
RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_BUSW_MASK;
}
/**
* @brief Disable reset pin filter bus clock
*
*/
LOCAL_INLINE void RGM_HWA_DisableBusClockFilter(void)
{
RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_BUS_MASK;
}
/**
* @brief Disable reset pin filter AON32K clock
*
*/
LOCAL_INLINE void RGM_HWA_DisableAon32kClockFilter(void)
{
RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_AON_MASK;
}
/**
* @brief Disable reset pin filter AON32K low power clock
*
*/
LOCAL_INLINE void RGM_HWA_DisableAon32kLPClockFilter(void)
{
RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_AON_LP_MASK;
}
/**
* @brief Set Reset delay
*
* @param eDelay Reset delay type
*/
LOCAL_INLINE void RGM_HWA_SetResetDelay(RGM_ResetDelayType eDelay)
{
uint32_t u32RegValue = RGM->SRIE;
RGM->SRIE = (u32RegValue & ~(uint32_t)RGM_SRIE_DELAY_MASK) | RGM_SRIE_DELAY(eDelay);
}
/**
* @brief Clear Reset delay
*/
LOCAL_INLINE void RGM_HWA_ClearResetDelay(void)
{
RGM->SRIE &= ~(uint32_t)RGM_SRIE_DELAY_MASK;
}
/**
* @brief Enable global reset interrupt
*
*/
LOCAL_INLINE void RGM_HWA_EnableGlobalResetInterrupt(void)
{
RGM->SRIE |= (uint32_t)RGM_SRIE_GLOBAL_RIE_MASK;
}
/**
* @brief Enable reset interrupt
*
* @param eResetInterrupt Reset interrupt type
*/
LOCAL_INLINE void RGM_HWA_EnableResetInterrupt(RGM_ResetIntMangerType eResetInterrupt)
{
RGM->SRIE |= (uint32_t)((uint32_t)eResetInterrupt & (RGM_SRIE_CLKERR0_RIE_MASK | RGM_SRIE_WDG_RIE_MASK |
RGM_SRIE_PIN_RIE_MASK | RGM_SRIE_JTAG_RIE_MASK | RGM_SRIE_CPULOC_RIE_MASK | RGM_SRIE_SW_RIE_MASK |
RGM_SRIE_SYSAP_RIE_MASK | RGM_SRIE_WDOG1_RIE_MASK | RGM_SRIE_SACKERR_RIE_MASK));
}
/**
* @brief Disable reset interrupt
*
* @param eResetInterrupt Reset interrupt type
*/
LOCAL_INLINE void RGM_HWA_DisableResetInterrupt(RGM_ResetIntMangerType eResetInterrupt)
{
RGM->SRIE &= ~(uint32_t)((uint32_t)eResetInterrupt & (RGM_SRIE_CLKERR0_RIE_MASK | RGM_SRIE_WDG_RIE_MASK |
RGM_SRIE_PIN_RIE_MASK | RGM_SRIE_JTAG_RIE_MASK | RGM_SRIE_CPULOC_RIE_MASK | RGM_SRIE_SW_RIE_MASK |
RGM_SRIE_SYSAP_RIE_MASK | RGM_SRIE_WDOG1_RIE_MASK | RGM_SRIE_SACKERR_RIE_MASK));
}
/**
* @brief Get enabling status of system reset
*
* @return Interrupt enabling status of system reset
*/
LOCAL_INLINE uint32_t RGM_HWA_GetResetInterrupt(void)
{
return (uint32_t)(RGM->SRIE & (RGM_SRIE_CLKERR0_RIE_MASK | RGM_SRIE_WDG_RIE_MASK |
RGM_SRIE_PIN_RIE_MASK | RGM_SRIE_GLOBAL_RIE_MASK | RGM_SRIE_JTAG_RIE_MASK | RGM_SRIE_CPULOC_RIE_MASK |
RGM_SRIE_SW_RIE_MASK | RGM_SRIE_SYSAP_RIE_MASK | RGM_SRIE_WDOG1_RIE_MASK | RGM_SRIE_SACKERR_RIE_MASK));
}
/**
* @brief Perform system reset.
*
*/
LOCAL_INLINE void CM7_HWA_SystemReset(void)
{
uint32 u32Temp;
u32Temp = SCB->AIRCR;
u32Temp &= ~(uint32)(SCB_AIRCR_VECTKEY_Msk);
u32Temp |= (uint32)((((uint32_t)(((uint32_t)(0x5FAU))<<SCB_AIRCR_VECTKEY_Pos))&SCB_AIRCR_VECTKEY_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk | SCB_AIRCR_PRIGROUP_Msk);
SCB->AIRCR = u32Temp;
}
/**
* @brief Enable CPU0 interrupt
*
* @param eCPU0ResetInterrupt CPU0 related interrupt type
*/
LOCAL_INLINE void RGM_HWA_EnableCPU0InterruptFlag(RGM_CPUIntMangerType eCPU0ResetInterrupt)
{
RGM->C0_CFG |= (uint32_t)((uint32_t)eCPU0ResetInterrupt & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK |
RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK));
}
/**
* @brief Disable CPU0 interrupt
*
* @param eCPU0ResetInterrupt CPU0 related interrupt type
*/
LOCAL_INLINE void RGM_HWA_DisableCPU0InterruptFlag(RGM_CPUIntMangerType eCPU0ResetInterrupt)
{
RGM->C0_CFG &= ~(uint32_t)((uint32_t)eCPU0ResetInterrupt & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK |
RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK));
}
/**
* @brief Get enabling status of CPU0 core related reset
*
* @return Interrupt enabling status of CPU0 core related reset
*/
LOCAL_INLINE uint32_t RGM_HWA_GetCPU0ResetInterrupt(void)
{
return (uint32_t)(RGM->C0_CFG & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK |
RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK));
}
/**
* @brief Get the CPU0 exit reset flag
*
* @return RGM_CPU_OUT_RST_UNDER CPU0 is under reset
* @return RGM_CPU_OUT_RST_OUT CPU0 is out of reset
*/
LOCAL_INLINE RGM_CPUOutResetType RGM_HWA_GetCPU0OutResetFlag(void)
{
uint8_t u8TmpVal = (uint8_t)(RGM->C0_RST & RGM_C0_RST_C0_OUT_OF_RST_MASK) >> RGM_C0_RST_C0_OUT_OF_RST_SHIFT;
return (RGM_CPUOutResetType)u8TmpVal;
}
/**
* @brief Issue a CPU0 software reset.
*
*/
LOCAL_INLINE void RGM_HWA_CPU0SWReset(void)
{
RGM->C0_RST |= (uint32_t)RGM_C0_RST_C0_SWRST_MASK;
}
/**
* @brief Read CPU0 last reset flag
*
* @return CPU0 last reset flag
*/
LOCAL_INLINE uint32_t RGM_HWA_ReadCPU0LastResetFlag(void)
{
return (uint32_t)RGM->C0_SRS;
}
/**
* @brief Read CPU0 all reset flag before POR,SSRS register is reset on POR only
*
* @return CPU0 all reset flag before POR
*/
LOCAL_INLINE uint32_t RGM_HWA_ReadCPU0AllResetFlagBeforePOR(void)
{
return (uint32_t)RGM->C0_SSRS;
}
/**
* @brief This api can clear reset flag of RGM_C0_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
*
* @param eReset Reset flag
*/
LOCAL_INLINE void RGM_HWA_ClearC0ResetFlagAfterPOR(RGM_CPUResetEventType eReset)
{
RGM->C0_SSRS = (uint32_t)(eReset);
}
/**
* @brief This api can clear all reset flag of SSRGM_C0_SSRSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
*
*/
LOCAL_INLINE void RGM_HWA_ClearC0AllResetFlagAfterPOR(void)
{
RGM->C0_SSRS = (uint32_t)0xE01FF9FFU;
}
#endif /* #ifndef _HWA_RGM_H_ */

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/**
* @file HwA_rtc.h
* @author Flagchip
* @brief FC7xxx rtc hardware access layer
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_RTC_H_
#define HWA_INCLUDE_HWA_RTC_H_
#include "device_header.h"
/**
* @addtogroup HwA_RTC
* @{
*
*/
/********* Local typedef ************/
/**
* @brief in the second interrupt mode, this type indicates the interrupt frequency.
* in the clkout mode , this type indicates the clkout frequency .
*
* */
typedef enum
{
RTC_FREQ_1HZ = 0, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 1Hz */
RTC_FREQ_2HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 2Hz */
RTC_FREQ_4HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 4Hz */
RTC_FREQ_8HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 8Hz */
RTC_FREQ_16HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 16Hz */
RTC_FREQ_32hZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 32Hz */
RTC_FREQ_64HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 64Hz */
RTC_FREQ_128HZ /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 128Hz */
} RTC_ClkoutSecIntFreqType;
/********* Local inline function ************/
/**
* @brief Read second value
*
* @return Second value
*/
LOCAL_INLINE uint32_t RTC_HWA_ReadSecondValue(void)
{
return (uint32_t)RTC->SR;
}
/**
* @brief Read RTC SR overflow flag
*
* @return true means Overflow flag is 1 ;false means Overflow flag is 0.
*/
LOCAL_INLINE bool RTC_HWA_GetOverflowFlag(void)
{
return (bool)(((RTC->STR & (uint32_t)RTC_STR_TOF_MASK)!=0u)? true:false);
}
/**
* @brief Read RTC IER overflow enable bit
*
* @return true means enable Overflow Interrupt ;false means disable Overflow Interrupt
*/
LOCAL_INLINE bool RTC_HWA_GetOverflowEnable(void)
{
return (bool)(((RTC->IER & (uint32_t)RTC_IER_TOIE_MASK)!=0u) ? true:false);
}
/**
* @brief Read RTC alarm flag
*
* @return true means alarm flag is 1 ;false means alarm flag is 0.
*/
LOCAL_INLINE bool RTC_HWA_GetAlarmFlag(void)
{
return (bool)(((RTC->STR & (uint32_t)RTC_STR_TAF_MASK)!=0u)?true:false);
}
/**
* @brief Read RTC alarm Enable
*
* @return true means enable alarm Interrupt ;false means disable alarm Interrupt
*/
LOCAL_INLINE bool RTC_HWA_GetAlarmEnable(void)
{
return (bool)(((RTC->IER & (uint32_t)RTC_IER_TAIE_MASK)!=0u)?true:false);
}
/**
* @brief Read RTC second interrupt Enable
*
* @return true means enable second Interrupt ;false means disable second Interrupt
*/
LOCAL_INLINE bool RTC_HWA_GetSecondEnable(void)
{
return (bool)(((RTC->IER & (uint32_t)RTC_IER_TSIE_MASK)!=0u)?true:false);
}
/**
* @brief Set RTC prescaler register
*
* @param u16Value PR register value
*/
LOCAL_INLINE void RTC_HWA_SetPrescalerCounterValue(uint16_t u16Value)
{
RTC->PR = (uint32_t)u16Value;
}
/**
* @brief Set RTC seconds register
*
* @param u32Value SR register value
*/
LOCAL_INLINE void RTC_HWA_SetSecondCounterValue(uint32_t u32Value)
{
RTC->SR = u32Value;
}
/**
* @brief Set RTC alarm value
*
* @param u32Value TAR register value
*/
LOCAL_INLINE void RTC_HWA_SetAlarmCounterValue(uint32_t u32Value)
{
RTC->AR = u32Value;
}
/**
* @brief Set RTC interrupt value
*
* @param u32Value IER register value
*/
LOCAL_INLINE void RTC_HWA_SetInterruptValue(uint32_t u32Value)
{
RTC->IER = u32Value;
}
/**
* @brief Configure control register
*
* @param u32Value Control value
*/
LOCAL_INLINE void RTC_HWA_ConfigControl(uint32_t u32Value)
{
RTC->CR = u32Value;
}
/**
* @brief Enable RTC time counter
*
*/
LOCAL_INLINE void RTC_HWA_EnableRtcCounter(void)
{
RTC->STR |= (uint32_t)RTC_STR_TCE_MASK;
}
/**
* @brief Set RTC_CLKOUT is from the 32.768 khz clock
*
*/
LOCAL_INLINE void RTC_HWA_SetClkoutFreqStable(void)
{
RTC->CR |= (uint32_t)RTC_CR_CKPS_MASK;
}
/**
* @brief Enable alarm interrupt
*
*/
LOCAL_INLINE void RTC_HWA_EnableAlarmInterrupt(void)
{
RTC->IER |= (uint32_t)RTC_IER_TAIE_MASK;
}
/**
* @brief Enable second interrupt
*
*/
LOCAL_INLINE void RTC_HWA_EnableSecondInterrupt(void)
{
RTC->IER |= (uint32_t)RTC_IER_TSIE_MASK;
}
/**
* @brief Enable overflow interrupt
*
*/
LOCAL_INLINE void RTC_HWA_EnableOverflowInterrupt(void)
{
RTC->IER |= (uint32_t)RTC_IER_TOIE_MASK;
}
/**
* @brief Unlock lock/status/control/compensation register
*
*/
LOCAL_INLINE void RTC_HWA_UnlockStatusControlCompensationReg(void)
{
RTC->LR |= (uint32_t)(RTC_LR_LRL_MASK | RTC_LR_STRL_MASK | RTC_LR_CRL_MASK | RTC_LR_CPL_MASK);
}
/**
* @brief Set second interrupt and RTC_CLKOUT frequency
*
* @param eFreq Frequency value
*/
LOCAL_INLINE void RTC_HWA_SetSecondAndClkoutFreq(RTC_ClkoutSecIntFreqType eFreq)
{
uint32_t u32RegValue = RTC->IER;
RTC->IER &= ~(uint32_t)RTC_IER_TSIE_MASK;
RTC->IER = (u32RegValue & ~(uint32_t)RTC_IER_TSIC_MASK) | RTC_IER_TSIC(eFreq);
}
/**
* @brief Disable RTC time counter
*
*/
LOCAL_INLINE void RTC_HWA_DisableRtcCounter(void)
{
RTC->STR &= ~(uint32_t)RTC_STR_TCE_MASK;
}
/**
* @brief Set RTC_CLKOUT is from the prescaler output clock selected by IER[TSIC]
*
*/
LOCAL_INLINE void RTC_HWA_SetClkoutFromSelectFreq(void)
{
RTC->CR &= ~(uint32_t)RTC_CR_CKPS_MASK;
}
/**
* @brief Disable alarm interrupt
*
*/
LOCAL_INLINE void RTC_HWA_DisableAlarmInterrupt(void)
{
RTC->IER &= ~(uint32_t)RTC_IER_TAIE_MASK;
}
/**
* @brief Disable second interrupt
*
*/
LOCAL_INLINE void RTC_HWA_DisableSecondInterrupt(void)
{
RTC->IER &= ~(uint32_t)RTC_IER_TSIE_MASK;
}
/**
* @brief Disable overflow interrupt
*
*/
LOCAL_INLINE void RTC_HWA_DisableOverflowInterrupt(void)
{
RTC->IER &= ~(uint32_t)RTC_IER_TOIE_MASK;
}
/** @}*/ /* HwA_RTC */
#endif /* HWA_INCLUDE_HWA_RTC_H_ */

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/**
* @file HwA_SCG.h
* @author Flagchip
* @brief FC7xxx SCG hardware access layer
* @version 0.1.0
* @date 2023-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_SCG_H_
#define _HWA_SCG_H_
#include "device_header.h"
/**
* @addtogroup HwA_SCG
* @{
*
*/
/********* macros ************/
#define UNKNOWN_CLOCK 0xFFFFFFFFU
#define SCG_CORE_CLOCK_SYMBOL CORE
#define SCG_BUS_CLOCK_SYMBOL BUS
#define SCG_SLOW_CLOCK_SYMBOL SLOW
#define SCG_SIRC_CLOCK_SYMBOL SIRC
#define SCG_SIRC32K_CLOCK_SYMBOL SIRC32K
#define SCG_FIRC_CLOCK_SYMBOL FIRC
#define SCG_FOSC_CLOCK_SYMBOL FOSC
#define SCG_SOSC_CLOCK_SYMBOL SOSC
#define SCG_PLL0_CLOCK_SYMBOL PLL0
#define SCG_PLL1_CLOCK_SYMBOL PLL1
/* PLL related */
#define SCG_PLLCSR_LK_MASK 0x800000u
#define SCG_PLLCSR_EN_MASK 0x1u
#define SCG_PLLCSR_CMRE_MASK 0x20000u
#define SCG_PLLCSR_CMRE_SHIFT 17u
#define SCG_PLLCSR_CMRE(x) (((uint32_t)(((uint32_t)(x))<<SCG_PLLCSR_CMRE_SHIFT))&SCG_PLLCSR_CMRE_MASK)
#define SCG_PLLCSR_CM_MASK 0x10000u
#define SCG_PLLCSR_CM_SHIFT 16u
#define SCG_PLLCSR_CM(x) (((uint32_t)(((uint32_t)(x))<<SCG_PLLCSR_CM_SHIFT))&SCG_PLLCSR_CM_MASK)
#define SCG_PLLCSR_STEN_MASK 0x2u
#define SCG_PLLCSR_STEN_SHIFT 1u
#define SCG_PLLCSR_STEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_PLLCSR_STEN_SHIFT))&SCG_PLLCSR_STEN_MASK)
#define SCG_PLLDIV_DIVL_EN_MASK 0x4000000u
#define SCG_PLLDIV_DIVL_MASK 0x70000u
#define SCG_PLLDIV_DIVL_SHIFT 16u
#define SCG_PLLDIV_DIVL(x) (((uint32_t)(((uint32_t)(x))<<SCG_PLLDIV_DIVL_SHIFT))&SCG_PLLDIV_DIVL_MASK)
#define SCG_PLLDIV_DIVM_EN_MASK 0x2000000u
#define SCG_PLLDIV_DIVM_MASK 0x700u
#define SCG_PLLDIV_DIVM_SHIFT 8u
#define SCG_PLLDIV_DIVM(x) (((uint32_t)(((uint32_t)(x))<<SCG_PLLDIV_DIVM_SHIFT))&SCG_PLLDIV_DIVM_MASK)
#define SCG_PLLDIV_DIVH_EN_MASK 0x1000000u
#define SCG_PLLDIV_DIVH_MASK 0x7u
#define SCG_PLLDIV_DIVH_SHIFT 0u
#define SCG_PLLDIV_DIVH(x) (((uint32_t)(((uint32_t)(x))<<SCG_PLLDIV_DIVH_SHIFT))&SCG_PLLDIV_DIVH_MASK)
#define SCG_PLLCFG_MULT_MASK 0x1FF0000u
#define SCG_PLLCFG_MULT_SHIFT 16u
#define SCG_PLLCFG_MULT(x) (((uint32_t)(((uint32_t)(x))<<SCG_PLLCFG_MULT_SHIFT))&SCG_PLLCFG_MULT_MASK)
#define SCG_PLLCFG_PREDIV_MASK 0x1F00u
#define SCG_PLLCFG_PREDIV_SHIFT 8u
#define SCG_PLLCFG_PREDIV(x) (((uint32_t)(((uint32_t)(x))<<SCG_PLLCFG_PREDIV_SHIFT))&SCG_PLLCFG_PREDIV_MASK)
#define SCG_PLLCFG_PSTDIV_MASK 0x30u
#define SCG_PLLCFG_PSTDIV_SHIFT 4u
#define SCG_PLLCFG_PSTDIV(x) (((uint32_t)(((uint32_t)(x))<<SCG_PLLCFG_PSTDIV_SHIFT))&SCG_PLLCFG_PSTDIV_MASK)
#define SCG_PLLCFG_SOURCE_MASK 0x1u
#define SCG_PLLCFG_SOURCE_SHIFT 0u
#define SCG_PLLCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x))<<SCG_PLLCFG_SOURCE_SHIFT))&SCG_PLLCFG_SOURCE_MASK)
#define _SCG_HWA_SetPllCsr(_pll_, val) SCG->_pll_##CSR = val
#define SCG_HWA_SetPllCsr(pll, val) _SCG_HWA_SetPllCsr(pll, val)
#define _SCG_HWA_UnlockPllCsr(_pll_) SCG->_pll_##CSR &= ~(uint32_t)SCG_PLLCSR_LK_MASK
#define SCG_HWA_UnlockPllCsr(pll) _SCG_HWA_UnlockPllCsr(pll)
#define _SCG_HWA_LockPllCsr(_pll_) SCG->_pll_##CSR |= (uint32_t)SCG_PLLCSR_LK_MASK
#define SCG_HWA_LockPllCsr(pll) _SCG_HWA_LockPllCsr(pll)
#define _SCG_HWA_EnablePllClockMonitor(_pll_) SCG->_pll_##CSR |= (uint32_t)SCG_PLLCSR_CM_MASK
#define SCG_HWA_EnablePllClockMonitor(pll) _SCG_HWA_EnablePllClockMonitor(pll)
#define _SCG_HWA_EnablePllClockMonitorReset(_pll_) SCG->_pll_##CSR |= (uint32_t)SCG_PLLCSR_CMRE_MASK
#define SCG_HWA_EnablePllClockMonitorReset(pll) _SCG_HWA_EnablePllClockMonitorReset(pll)
#define _SCG_HWA_SetPllCfg(_pll_, val) SCG->_pll_##CFG = val
#define SCG_HWA_SetPllCfg(pll, val) _SCG_HWA_SetPllCfg(pll, val)
#define _SCG_HWA_SetPllDiv(_pll_, val) SCG->_pll_##DIV = val
#define SCG_HWA_SetPllDiv(pll, val) _SCG_HWA_SetPllDiv(pll, val)
#define _SCG_HWA_EnablePll(_pll_) SCG->_pll_##CSR |= (uint32_t)(SCG_PLLCSR_EN_MASK)
#define SCG_HWA_EnablePll(pll) _SCG_HWA_EnablePll(pll)
#define _SCG_HWA_GetPllMult(_pll_) (uint32_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_MULT_MASK) >> SCG_PLLCFG_MULT_SHIFT)
#define SCG_HWA_GetPllMult(pll) _SCG_HWA_GetPllMult(pll)
#define _SCG_HWA_GetPllPrediv(_pll_) (uint32_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_PREDIV_MASK) >> SCG_PLLCFG_PREDIV_SHIFT)
#define SCG_HWA_GetPllPrediv(pll) _SCG_HWA_GetPllPrediv(pll)
#define _SCG_HWA_GetPllPstdiv(_pll_) (uint32_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_PSTDIV_MASK) >> SCG_PLLCFG_PSTDIV_SHIFT)
#define SCG_HWA_GetPllPstdiv(pll) _SCG_HWA_GetPllPstdiv(pll)
#define _SCG_HWA_GetPllSrc(_pll_) (uint32_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_SOURCE_MASK) >> SCG_PLLCFG_SOURCE_SHIFT)
#define SCG_HWA_GetPllSrc(pll) _SCG_HWA_GetPllSrc(pll)
/* Clock valid and div related */
#define _SCG_HWA_GetClockVliad(_clock_) (bool)((((uint32_t)SCG->_clock_##CSR & (uint32_t)SCG_##_clock_##CSR_VLD_MASK) != 0U) ? true : false)
#define SCG_HWA_GetClockVliad(_clock_) _SCG_HWA_GetClockVliad(_clock_)
#define _SCG_HWA_GetClockDiv(_clock_) (uint32_t)SCG->_clock_##DIV
#define SCG_HWA_GetClockDiv(_clock_) _SCG_HWA_GetClockDiv(_clock_)
#define SCG_CLOCKDIV_DIVL_ACK_MASK 0x40000000u
#define SCG_CLOCKDIV_DIVM_ACK_MASK 0x20000000u
#define SCG_CLOCKDIV_DIVH_ACK_MASK 0x10000000u
#define SCG_CLOCKDIV_DIVL_ACK_SHIFT 30u
#define SCG_CLOCKDIV_DIVM_ACK_SHIFT 29u
#define SCG_CLOCKDIV_DIVH_ACK_SHIFT 28u
#define SCG_CLOCKDIV_DIVL_EN_MASK 0x4000000u
#define SCG_CLOCKDIV_DIVM_EN_MASK 0x2000000u
#define SCG_CLOCKDIV_DIVH_EN_MASK 0x1000000u
#define SCG_CLOCKDIV_DIVL_EN_SHIFT 26u
#define SCG_CLOCKDIV_DIVM_EN_SHIFT 25u
#define SCG_CLOCKDIV_DIVH_EN_SHIFT 24u
#define SCG_CLOCKDIV_EN2ACK_SHIFT 4u
#define SCG_CLOCKDIV_DIVL_VAL_MASK 0x70000u
#define SCG_CLOCKDIV_DIVM_VAL_MASK 0x700u
#define SCG_CLOCKDIV_DIVH_VAL_MASK 0x7u
#define SCG_CLOCKDIV_DIVL_VAL_SHIFT 16u
#define SCG_CLOCKDIV_DIVM_VAL_SHIFT 8u
#define SCG_CLOCKDIV_DIVH_VAL_SHIFT 0u
#define SCG_CHECK_DIVL_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIVL_ACK_MASK) >> SCG_CLOCKDIV_DIVL_ACK_SHIFT)
#define SCG_CHECK_DIVM_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIVM_ACK_MASK) >> SCG_CLOCKDIV_DIVM_ACK_SHIFT)
#define SCG_CHECK_DIVH_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIVH_ACK_MASK) >> SCG_CLOCKDIV_DIVH_ACK_SHIFT)
#define SCG_CHECK_DIVL_EN(reg_val) ((reg_val & SCG_CLOCKDIV_DIVL_EN_MASK) >> SCG_CLOCKDIV_DIVL_EN_SHIFT)
#define SCG_CHECK_DIVM_EN(reg_val) ((reg_val & SCG_CLOCKDIV_DIVM_EN_MASK) >> SCG_CLOCKDIV_DIVM_EN_SHIFT)
#define SCG_CHECK_DIVH_EN(reg_val) ((reg_val & SCG_CLOCKDIV_DIVH_EN_MASK) >> SCG_CLOCKDIV_DIVH_EN_SHIFT)
#define SCG_GET_DIVL_VAL(reg_val) ((0U == ((reg_val & SCG_CLOCKDIV_DIVL_VAL_MASK) >> SCG_CLOCKDIV_DIVL_VAL_SHIFT)) ? 1U : ((reg_val & SCG_CLOCKDIV_DIVL_VAL_MASK) >> SCG_CLOCKDIV_DIVL_VAL_SHIFT))
#define SCG_GET_DIVM_VAL(reg_val) ((0U == ((reg_val & SCG_CLOCKDIV_DIVM_VAL_MASK) >> SCG_CLOCKDIV_DIVM_VAL_SHIFT)) ? 1U : ((reg_val & SCG_CLOCKDIV_DIVM_VAL_MASK) >> SCG_CLOCKDIV_DIVM_VAL_SHIFT))
#define SCG_GET_DIVH_VAL(reg_val) ((0U == ((reg_val & SCG_CLOCKDIV_DIVH_VAL_MASK) >> SCG_CLOCKDIV_DIVH_VAL_SHIFT)) ? 1U : ((reg_val & SCG_CLOCKDIV_DIVH_VAL_MASK) >> SCG_CLOCKDIV_DIVH_VAL_SHIFT))
#define SCG_CALCULATE_DIVL_FREQ(clk_freq, reg_val) (((1U == SCG_CHECK_DIVL_EN(reg_val)) && (clk_freq != UNKNOWN_CLOCK)) ? (uint32_t)clk_freq >> (uint8_t)(SCG_GET_DIVL_VAL(reg_val) - 1U) : (uint32_t)UNKNOWN_CLOCK)
#define SCG_CALCULATE_DIVM_FREQ(clk_freq, reg_val) (((1U == SCG_CHECK_DIVM_EN(reg_val)) && (clk_freq != UNKNOWN_CLOCK)) ? (uint32_t)clk_freq >> (uint8_t)(SCG_GET_DIVM_VAL(reg_val) - 1U) : (uint32_t)UNKNOWN_CLOCK)
#define SCG_CALCULATE_DIVH_FREQ(clk_freq, reg_val) (((1U == SCG_CHECK_DIVH_EN(reg_val)) && (clk_freq != UNKNOWN_CLOCK)) ? (uint32_t)clk_freq >> (uint8_t)(SCG_GET_DIVH_VAL(reg_val) - 1U) : (uint32_t)UNKNOWN_CLOCK)
typedef enum
{
SCG_CLOCK_DIV_H = 0x01000000U, /* DIVH clock enable bit [24] */
SCG_CLOCK_DIV_M = 0x02000000U, /* DIVM clock enable bit [25] */
SCG_CLOCK_DIV_L = 0x04000000U, /* DIVL clock enable bit [26] */
SCG_CLOCK_DIV_ALL = 0x07000000U, /* DIVH DIVM DIVL clock enable bit [26:24] */
}SCG_DivEnableType;
/********* Local inline function ************/
/**
* @brief Get clock out configure register CLKOUTSEL value
*/
LOCAL_INLINE uint8_t SCG_HWA_GetClkOutSel(void)
{
return (uint8_t)(((uint32_t)SCG->CLKOUTCFG & SCG_CLKOUTCFG_CLKOUTSEL_MASK) >> SCG_CLKOUTCFG_CLKOUTSEL_SHIFT);
}
/**
* @brief Get clock out configure register value
*/
LOCAL_INLINE uint32_t SCG_HWA_GetClkOutCfg(void)
{
return SCG->CLKOUTCFG;
}
/**
* @brief Unlock SOSC CSR register
*
*/
LOCAL_INLINE void SCG_HWA_UnlockSoscCsrReg(void)
{
SCG->SOSCCSR &= ~(uint32_t)(SCG_SOSCCSR_LK_MASK);
}
/**
* @brief Lock SOSC CSR register
*
*/
LOCAL_INLINE void SCG_HWA_LockSoscCsrReg(void)
{
SCG->SOSCCSR |= (uint32_t)(SCG_SOSCCSR_LK_MASK);
}
/**
* @brief Enable SOSC clock monitor
*
*/
LOCAL_INLINE void SCG_HWA_EnableSoscClockMonitor(void)
{
SCG->SOSCCSR |= (uint32_t)(SCG_SOSCCSR_CM_MASK);
}
/**
* @brief Enable SOSC clock monitor Reset
*
*/
LOCAL_INLINE void SCG_HWA_EnableSoscClockMonitorReset(void)
{
SCG->SOSCCSR |= (uint32_t)(SCG_SOSCCSR_CMRE_MASK);
}
/**
* @brief Set SOSC enable
*/
LOCAL_INLINE void SCG_HWA_EnableSosc(void)
{
SCG->SOSCCSR |= (uint32_t)SCG_SOSCCSR_EN_MASK;
}
/**
* @brief Diable SOSC
*/
LOCAL_INLINE void SCG_HWA_DisableSosc(void)
{
SCG->SOSCCSR &= ~(uint32_t)SCG_SOSCCSR_EN_MASK;
}
/**
* @brief Set recommend value to SOSCCFG register
*
*/
LOCAL_INLINE void SCG_HWA_SetSoscRecommendCfg(void)
{
SCG->SOSCCFG = (uint32_t)(SCG_SOSCCFG_EOCV(64U) | SCG_SOSCCFG_GM_SEL(3U) | SCG_SOSCCFG_CURPRG_SF(3U) | SCG_SOSCCFG_CURPRG_COMP(3U));
}
/**
* @brief Set SOSC CSR register value
*
* @param u32CsrValue configured register value
*/
LOCAL_INLINE void SCG_HWA_SetSoscCsr(uint32_t u32CsrValue)
{
SCG->SOSCCSR = u32CsrValue;
}
/**
* @brief Get SOSC CSR register value
*
*/
LOCAL_INLINE uint32_t SCG_HWA_GetSoscCsr(void)
{
return (uint32_t)SCG->SOSCCSR;
}
/********* Fosc Register interface ************/
/**
* @brief Enable FOSC
*/
LOCAL_INLINE void SCG_HWA_EnableFosc(void)
{
SCG->FOSCCSR |= (uint32_t)SCG_FOSCCSR_EN_MASK;
}
/**
* @brief Disable FOSC
*/
LOCAL_INLINE void SCG_HWA_DisableFosc(void)
{
SCG->FOSCCSR &= ~SCG_FOSCCSR_EN_MASK;
}
/**
* @brief Set FOSCCFG register value
*
* @param u32CfgValue configured register value
*/
LOCAL_INLINE void SCG_HWA_SetFoscCfg(uint32_t u32CfgValue)
{
SCG->FOSCCFG = u32CfgValue;
}
/**
* @brief Set FOSCCSR register value
*
* @param u32CsrValue configured register value
*/
LOCAL_INLINE void SCG_HWA_SetFoscCsr(uint32_t u32CsrValue)
{
SCG->FOSCCSR = u32CsrValue;
}
/**
* @brief Get FOSCCSR register value
*
*/
LOCAL_INLINE uint32_t SCG_HWA_GetFoscCsr(void)
{
return (uint32_t)SCG->FOSCCSR;
}
/**
* @brief Unlock FOSC CSR register
*
*/
LOCAL_INLINE void SCG_HWA_UnlockFoscCsrReg(void)
{
SCG->FOSCCSR &= ~(uint32_t)(SCG_FOSCCSR_LK_MASK);
}
/**
* @brief lock FOSC CSR register
*
*/
LOCAL_INLINE void SCG_HWA_LockFoscCsrReg(void)
{
SCG->FOSCCSR |= (uint32_t)(SCG_FOSCCSR_LK_MASK);
}
/**
* @brief Enable FOSC clock monitor
*
*/
LOCAL_INLINE void SCG_HWA_EnableFoscClockMonitor(void)
{
SCG->FOSCCSR |= (uint32_t)(SCG_FOSCCSR_CM_MASK);
}
/**
* @brief Enable FOSC clock monitor Reset
*
*/
LOCAL_INLINE void SCG_HWA_EnableFoscClockMonitorReset(void)
{
SCG->FOSCCSR |= (uint32_t)(SCG_FOSCCSR_CMRE_MASK);
}
/**
* @brief enable FOSCDIV as user manual request sequence
* @param DivEn the or value of SCG_DivEnableType
*/
LOCAL_INLINE void SCG_HWA_EnableFoscDiv(SCG_DivEnableType DivEn)
{
SCG->FOSCDIV |= (uint32_t)DivEn;
}
/**
* @brief Disable FOSCDIV as user manual request sequence
* @param DivEn the or value of SCG_DivEnableType
*/
LOCAL_INLINE void SCG_HWA_DiableFoscDiv(SCG_DivEnableType DivEn)
{
SCG->FOSCDIV &= ~(uint32_t)DivEn;
}
/**
* @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnableFoscDiv
* @param DivEn the or value of SCG_DivEnableType
* @return bool true : The enabled DIV clocks are acknowledged
* false : The enabled DIV clocks are not acknowledged
*/
LOCAL_INLINE bool SCG_HWA_GetFoscDivAck(SCG_DivEnableType DivEn)
{
return (bool)((SCG->FOSCDIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT));
}
/**
* @brief Set FOSCDIV register value
*
* @param u32DivValue configured register value
*/
LOCAL_INLINE void SCG_HWA_SetFoscDiv(uint32_t u32DivValue)
{
SCG->FOSCDIV = u32DivValue;
}
/**
* @brief Set Low Power Wakeup WDOG Register
*
* @param u8MSBVal Most Significant value, if OSC is 40M
* and FOSC not valid after 1.8ms wakeup,
* the chip will reset and RGM register will
* report clock error reset reason.
*/
LOCAL_INLINE void SCG_HWA_SetWKPWDG(uint8_t u8MSBVal)
{
SCG->WKPWDG = SCG_WKPWDG_MSB(u8MSBVal) | SCG_WKPWDG_EN_MASK;
}
/********* Sirc Register interface ************/
/**
* @brief Set SIRCCSR register value
*
* @param u32CsrValue configured register value
*/
LOCAL_INLINE void SCG_HWA_SetSircCsr(uint32_t u32CsrValue)
{
SCG->SIRCCSR = u32CsrValue;
}
/**
* @brief Get SIRCCSR register value
*
*/
LOCAL_INLINE uint32_t SCG_HWA_GetSircCsr(void)
{
return (uint32_t)SCG->SIRCCSR;
}
/**
* @brief Unlock SIRC CSR register
*
*/
LOCAL_INLINE void SCG_HWA_UnlockSircCsrReg(void)
{
SCG->SIRCCSR &= ~(uint32_t)SCG_SIRCCSR_LK_MASK;
}
/**
* @brief Lock SIRC CSR register
*
*/
LOCAL_INLINE void SCG_HWA_LockSircCsrReg(void)
{
SCG->SIRCCSR |= (uint32_t)SCG_SIRCCSR_LK_MASK;
}
/**
* @brief Enable SIRC clock monitor
*
*/
LOCAL_INLINE void SCG_HWA_EnableSircClockMonitor(void)
{
SCG->SIRCCSR |= (uint32_t)(SCG_SIRCCSR_CM_MASK);
}
/**
* @brief Set SIRCDIV register value
*
* @param u32DivValue configured register value
*/
LOCAL_INLINE void SCG_HWA_SetSircDiv(uint32_t u32DivValue)
{
SCG->SIRCDIV = u32DivValue;
}
/**
* @brief enable SIRCDIV as user manual request sequence
* @param DivEn the or value of SCG_DivEnableType
*/
LOCAL_INLINE void SCG_HWA_EnableSircDiv(SCG_DivEnableType DivEn)
{
SCG->SIRCDIV |= (uint32_t)DivEn;
}
/**
* @brief Disable SIRCDIV as user manual request sequence
* @param DivEn the or value of SCG_DivEnableType
*/
LOCAL_INLINE void SCG_HWA_DiableSircDiv(SCG_DivEnableType DivEn)
{
SCG->SIRCDIV &= ~(uint32_t)DivEn;
}
/**
* @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnableSircDiv
* @param DivEn the or value of SCG_DivEnableType
* @return bool true : The enabled DIV clocks are acknowledged
* false : The enabled DIV clocks are not acknowledged
*/
LOCAL_INLINE bool SCG_HWA_GetSircDivAck(SCG_DivEnableType DivEn)
{
return (bool)((SCG->SIRCDIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT));
}
/**
* @brief Set SIRCTCFG register value for SIRC Trim configure.
*
* @param u32TcfgValue configured register value
*/
LOCAL_INLINE void SCG_HWA_SetSircTcfg(uint32_t u32TcfgValue)
{
SCG->SIRCTCFG = u32TcfgValue;
}
/********* Sirc32k Register interface ************/
/**
* @brief Enable SIRC32KCSR register
*
*/
LOCAL_INLINE void SCG_HWA_EnableSirc32kCsr(void)
{
SCG->SIRC32KCSR |= (uint32_t)SCG_SIRC32KCSR_EN_MASK;
}
/**
* @brief Disable SIRC32KCSR register
*
*/
LOCAL_INLINE void SCG_HWA_DisableSirc32kCsr(void)
{
SCG->SIRC32KCSR &= ~(uint32_t)SCG_SIRC32KCSR_EN_MASK;
}
/**
* @brief Unlock SIRC32K CSR register
*/
LOCAL_INLINE void SCG_HWA_UnlockSirc32kCsrReg(void)
{
SCG->SIRC32KCSR &= ~(uint32_t)(SCG_SIRC32KCSR_LK_MASK);
}
/**
* @brief Lock SIRC32K CSR register
*/
LOCAL_INLINE void SCG_HWA_LockSirc32kCsrReg(void)
{
SCG->SIRC32KCSR |= (uint32_t)(SCG_SIRC32KCSR_LK_MASK);
}
/********* Firc Register interface ************/
/**
* @brief Get FIRC CSR register value.
*/
LOCAL_INLINE uint32_t SCG_HWA_GetFircCsr(void)
{
return (uint32_t)SCG->FIRCCSR;
}
/**
* @brief Enable FIRC.
*/
LOCAL_INLINE void SCG_HWA_EnableFirc(void)
{
SCG->FIRCCSR |= (uint32_t)SCG_FIRCCSR_EN_MASK;
}
/**
* @brief Unlock FIRC CSR register
*/
LOCAL_INLINE void SCG_HWA_UnlockFircCsrReg(void)
{
SCG->FIRCCSR &= ~(uint32_t)(SCG_FIRCCSR_LK_MASK);
}
/**
* @brief Lock FIRC CSR register
*/
LOCAL_INLINE void SCG_HWA_LockFircCsrReg(void)
{
SCG->FIRCCSR |= (uint32_t)(SCG_FIRCCSR_LK_MASK);
}
/**
* @brief Enable FIRC clock monitor
*
*/
LOCAL_INLINE void SCG_HWA_EnableFircClockMonitor(void)
{
SCG->FIRCCSR |= (uint32_t)(SCG_FIRCCSR_CM_MASK);
}
/**
* @brief Disable FIRC.
*/
LOCAL_INLINE void SCG_HWA_DisableFirc(void)
{
SCG->FIRCCSR &= ~(uint32_t)SCG_FIRCCSR_EN_MASK;
}
/**
* @brief Set FIRCCSR register value
*
* @param u32CsrValue configured register value
*/
LOCAL_INLINE void SCG_HWA_SetFircCsr(uint32_t u32CsrValue)
{
SCG->FIRCCSR = u32CsrValue;
}
/**
* @brief Set FIRCCFG register value
*
* @param u32CfgValue configured register value
*/
LOCAL_INLINE void SCG_HWA_SetFircCfg(uint32_t u32CfgValue)
{
SCG->FIRCCFG = u32CfgValue;
}
/**
* @brief Set FOSCDIV register value
*
* @param u32DivValue configured register value
*/
LOCAL_INLINE void SCG_HWA_SetFircDiv(uint32_t u32DivValue)
{
SCG->FIRCDIV = u32DivValue;
}
/**
* @brief enable FIRCDIV as user manual request sequence
* @param DivEn the or value of SCG_DivEnableType
*/
LOCAL_INLINE void SCG_HWA_EnableFircDiv(SCG_DivEnableType DivEn)
{
SCG->FIRCDIV |= (uint32_t)DivEn;
}
/**
* @brief Disable FIRCDIV as user manual request sequence
* @param DivEn the or value of SCG_DivEnableType
*/
LOCAL_INLINE void SCG_HWA_DiableFircDiv(SCG_DivEnableType DivEn)
{
SCG->FIRCDIV &= ~(uint32_t)DivEn;
}
/**
* @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnableFircDiv
* @param DivEn the or value of SCG_DivEnableType
* @return bool true : The enabled DIV clocks are acknowledged
* false : The enabled DIV clocks are not acknowledged
*/
LOCAL_INLINE bool SCG_HWA_GetFircDivAck(SCG_DivEnableType DivEn)
{
return (bool)((SCG->FIRCDIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT));
}
/**
* @brief Set FIRCTCFG register value for FIRC clock trim configure.
*
* @param u32TcfgValue configured register value.
*/
LOCAL_INLINE void SCG_HWA_SetFircTcfg(uint32_t u32TcfgValue)
{
SCG->FIRCTCFG = u32TcfgValue;
}
/********* PLL0 clock Register interface ************/
/**
* @brief enable PLL0DIV as user manual request sequence
* @param DivEn the or value of SCG_DivEnableType
*/
LOCAL_INLINE void SCG_HWA_EnablePll0Div(SCG_DivEnableType DivEn)
{
SCG->PLL0DIV |= (uint32_t)DivEn;
}
/**
* @brief Disable FOSCDIV as user manual request sequence
* @param DivEn the or value of SCG_DivEnableType
*/
LOCAL_INLINE void SCG_HWA_DiablePll0Div(SCG_DivEnableType DivEn)
{
SCG->PLL0DIV &= ~(uint32_t)DivEn;
}
/**
* @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnablePll0Div
* @param DivEn the or value of SCG_DivEnableType
* @return bool true : The enabled DIV clocks are acknowledged
* false : The enabled DIV clocks are not acknowledged
*/
LOCAL_INLINE bool SCG_HWA_GetPll0DivAck(SCG_DivEnableType DivEn)
{
return (bool)((SCG->PLL0DIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT));
}
/********* PLL1 clock Register interface ************/
/**
* @brief enable PLL0DIV as user manual request sequence
* @param DivEn the or value of SCG_DivEnableType
*/
LOCAL_INLINE void SCG_HWA_EnablePll1Div(SCG_DivEnableType DivEn)
{
SCG->PLL1DIV |= (uint32_t)DivEn;
}
/**
* @brief Disable FOSCDIV as user manual request sequence
* @param DivEn the or value of SCG_DivEnableType
*/
LOCAL_INLINE void SCG_HWA_DiablePll1Div(SCG_DivEnableType DivEn)
{
SCG->PLL1DIV &= ~(uint32_t)DivEn;
}
/**
* @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnablePll1Div
* @param DivEn the or value of SCG_DivEnableType
* @return bool true : The enabled DIV clocks are acknowledged
* false : The enabled DIV clocks are not acknowledged
*/
LOCAL_INLINE bool SCG_HWA_GetPll1DivAck(SCG_DivEnableType DivEn)
{
return (bool)((SCG->PLL1DIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT));
}
/********* System clock Register interface ************/
/**
* @brief Get system clock CCR register value
*
* @return system clock CCR register value
*/
LOCAL_INLINE uint32_t SCG_HWA_GetCCR(void)
{
return SCG->CCR;
}
/**
* @brief Set system clock CCR register value
*
* @param u32CcrValue configured register value
*/
LOCAL_INLINE void SCG_HWA_SetCCR(uint32_t u32CcrValue)
{
SCG->CCR = u32CcrValue;
}
/**
* @brief Set system clock
*
* @param u8SystemCLock System clock value
*/
LOCAL_INLINE void SCG_HWA_SetSystemClock(uint8_t u8SystemCLock)
{
SCG->CCR = ((SCG->CCR & ~(uint32_t)SCG_CCR_SCS_MASK) | SCG_CCR_SCS(u8SystemCLock));
}
/**
* @brief Get system clock source. used to calculate system clock frequency at startup.
* used to check if the target clock soure successfully switched.
* @return uint8_t. system clock source.
*/
LOCAL_INLINE uint8_t SCG_HWA_GetSysClkSrc(void)
{
return (uint8_t)(((uint32_t)(SCG->CSR) & (uint32_t)SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT);
}
/**
* @brief Get system clock valid status, use this status to check system clock update finished or not.
* @return bool. true as updated; false as not updated.
*/
LOCAL_INLINE bool SCG_HWA_GetSysClkUPRD(void)
{
return (bool)((((uint32_t)SCG->CSR & (uint32_t)SCG_CSR_CCR_UPRD_MASK) != 0U) ? true : false);
}
/**
* @brief Get system clock Divcore. used to calculate core clock frequency at startup.
* @return uint8_t. system clock Divcore.
*/
LOCAL_INLINE uint8_t SCG_HWA_GetSysClkDivCore(void)
{
return (uint8_t)(((uint32_t)(SCG->CSR) & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT);
}
/**
* @brief Get system clock Divbus. used to calculate bus clock frequency at startup.
* @return uint8_t. system clock Divbus.
*/
LOCAL_INLINE uint8_t SCG_HWA_GetSysClkDivBus(void)
{
return (uint8_t)(((uint32_t)(SCG->CSR) & SCG_CSR_DIVBUS_MASK) >> SCG_CSR_DIVBUS_SHIFT);
}
/**
* @brief Get system clock Divslow. used to calculate slow clock frequency at startup.
* @return uint8_t. system clock Divslow.
*/
LOCAL_INLINE uint8_t SCG_HWA_GetSysClkDivSlow(void)
{
return (uint8_t)(((uint32_t)(SCG->CSR) & SCG_CSR_DIVSLOW_MASK) >> SCG_CSR_DIVSLOW_SHIFT);
}
/********* Clkout Register interface ************/
/**
* @brief Select clock out source
*
* @param u8ClkOutSel Clock out select
*/
LOCAL_INLINE void SCG_HWA_SetClkOutSel(uint8_t u8ClkOutSel)
{
SCG->CLKOUTCFG = ((SCG->CLKOUTCFG & ~(uint32_t)SCG_CLKOUTCFG_CLKOUTSEL_MASK) | SCG_CLKOUTCFG_CLKOUTSEL(u8ClkOutSel));
}
/**
* @brief Set Nvm clock source
*
* @param u32NvmClkMask Nvm clock source mask
*/
LOCAL_INLINE void SCG_HWA_SetNvmClk(uint32_t u32NvmClkMask)
{
SCG->CLKOUTCFG &= ~(uint32_t)(SCG_CLKOUTCFG_NVMCLK_FIRC_MASK | SCG_CLKOUTCFG_NVMCLK_SIRC_MASK);
SCG->CLKOUTCFG |= u32NvmClkMask;
}
/**
* @brief Set CMU4 clock source
*
* @param u32Cmu4ClkMask CMU4 clock source mask
*/
LOCAL_INLINE void SCG_HWA_SetCmu4Clk(uint32_t u32Cmu4ClkMask)
{
SCG->CLKOUTCFG &= ~(uint32_t)(SCG_CLKOUTCFG_CMU4CLK_FOSC_MASK | SCG_CLKOUTCFG_CMU4CLK_SIRC_MASK);
SCG->CLKOUTCFG |= u32Cmu4ClkMask;
}
/********* CRC Register interface ************/
/**
* @brief Generate SCG register CRC value
*/
LOCAL_INLINE void SCG_HWA_GenCrcVal(void)
{
SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_GEN_MASK;
}
/**
* @brief Enable SCG register CRC check
*/
LOCAL_INLINE void SCG_HWA_EnableCrcCheck(void)
{
SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_CHKEN_MASK;
}
/**
* @brief Disable SCG register CRC check
*/
LOCAL_INLINE void SCG_HWA_DisableCrcCheck(void)
{
SCG->CRCCSR &= ~(uint32_t)SCG_CRCCSR_CHKEN_MASK;
}
/**
* @brief Enable SCG register CRC error output
*/
LOCAL_INLINE void SCG_HWA_EnableCrcErrorOutput(void)
{
SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_EOEN_MASK;
}
/**
* @brief Disable SCG register CRC error output
*/
LOCAL_INLINE void SCG_HWA_DisableCrcErrorOutput(void)
{
SCG->CRCCSR &= ~(uint32_t)SCG_CRCCSR_EOEN_MASK;
}
/**
* @brief Get CRC busy status
*/
LOCAL_INLINE bool SCG_HWA_GetCrcBusyStatus(void)
{
return (0U != (SCG->CRCCSR & (uint32_t)SCG_CRCCSR_BUSY_MASK));
}
/**
* @brief Get CRC error status
*/
LOCAL_INLINE bool SCG_HWA_GetCrcErrorStatus(void)
{
return (0U != (SCG->CRCCSR & (uint32_t)SCG_CRCCSR_ERR_MASK));
}
/**
* @brief Clear CRC error flag
*/
LOCAL_INLINE void SCG_HWA_ClearCrcErrorFlag(void)
{
SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_ERR_MASK;
}
/**
* @brief Get CRC result
*/
LOCAL_INLINE uint32_t SCG_HWA_GetCrcResult(void)
{
return SCG->CRCRES;
}
/**
* @brief Enable SCG register CRC trigger mode
*/
LOCAL_INLINE void SCG_HWA_EnableCrcTriggerMode(void)
{
SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_TRGEN_MASK;
}
/**
* @brief Disable SCG register CRC trigger mode
*/
LOCAL_INLINE void SCG_HWA_DisableCrcTriggerMode(void)
{
SCG->CRCCSR &= ~(uint32_t)SCG_CRCCSR_TRGEN_MASK;
}
/** @}*/ /* HwA_SCG */
#endif /* #ifndef _HWA_SCG_H_ */

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/**
* @file HwA_sec.h
* @author Flagchip
* @brief FC7xxx sec hardware access layer
* @version 0.2.0
* @date 2023-2-7
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.2.0 2023-2-7 Flagchip076 N/A First version for FC7300
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_SEC_H_
#define HWA_INCLUDE_HWA_SEC_H_
#include "device_header.h"
/**
* @addtogroup HwA_SEC
* @{
*
*/
/* DEN Bit Fields */
/**
*@brief Enable the debug module
* */
LOCAL_INLINE void SEC_HWA_EnDebug(void)
{
SEC->DEN = SEC_DEN_DEN(0X5) ;
}
/* FSEC0 Bit Fields */
/**
* @brief Get the system security KEY0
* */
LOCAL_INLINE uint16_t SEC_HWA_GetSScontrol0(void)
{
return (uint16_t)((SEC->FSEC0) & (SEC_FSEC0_SSC0_MASK));
}
/* FSEC1 Bit Fields */
/**
* @brief Get the system security KEY1
* */
LOCAL_INLINE uint16_t SEC_HWA_GetSScontrol1(void)
{
return (uint16_t)((SEC->FSEC1) & (SEC_FSEC1_SSC1_MASK));
}
/* DCWOR Bit Fields */
/**
* @brief Re-enable the Debug mode.
* @note This register can only be write once. startup_fc4150.s has lock the register.
* */
LOCAL_INLINE void SEC_HWA_ReEnDebug(void)
{
SEC->DCWOR = ((SEC->DCWOR & (~SEC_DCWOR_DEA_MASK)) | SEC_DCWOR_DEA(0X5));
}
/**
* @brief Get the Re-enable Debug permission.
* */
LOCAL_INLINE bool SEC_HWA_GetReEnDebug(void)
{
bool ret = false;
uint8_t dea = (uint8_t)((SEC->DCWOR & (SEC_DCWOR_DEA_MASK)) >> SEC_DCWOR_DEA_SHIFT);
if (dea == 0x5U)
{
ret = true;
}
return ret;
}
/**
* @brief Enable the write operation for SEC register.
* @note This register can only be write once. startup_fc4150.s has lock the register.
* */
LOCAL_INLINE void SEC_HWA_WriteUnlock(void)
{
SEC->DCWOR = ((SEC->DCWOR & (~SEC_DCWOR_RWL_MASK)) | SEC_DCWOR_RWL(0X5));
}
/**
* @brief Get the sec write permission
* @return true means allow write. false means forbid write.
*/
LOCAL_INLINE bool SEC_HWA_GetWritePer(void)
{
bool ret = false;
uint8_t rwl = (uint8_t)((SEC->DCWOR & (SEC_DCWOR_RWL_MASK)) >> SEC_DCWOR_RWL_SHIFT);
if ((rwl == 0x5U) || (rwl == 0xFU))
{
ret = true;
}
return ret;
}
/* DEK Bit Fields */
/**
* @brief Enable the write operation for SEC register.
* */
LOCAL_INLINE void SEC_HWA_ChangeDBK(uint8_t count, uint32_t key)
{
SEC->DEK[count] = SEC_DEK_DEK(key) ;
}
/* TME Bit Fields */
/**
*@brief Enable the Test module
* */
LOCAL_INLINE void SEC_HWA_EnTest(void)
{
SEC->TME = SEC_TME_TME(0X5) ;
}
/* TMEA Bit Fields */
/**
* @brief Re-Enable Test mode
* */
LOCAL_INLINE void SEC_HWA_ReEnTest(void)
{
SEC->TMEA = SEC_TMEA_TMEA(0X5) ;
}
/**
* @brief Get the Re-enable Test permission.
* */
LOCAL_INLINE bool SEC_HWA_GetReEnTest(void)
{
bool ret = false;
uint8_t tmea = (uint8_t)((SEC->TMEA & (SEC_TMEA_TMEA_MASK)) >> SEC_TMEA_TMEA_SHIFT);
if ((tmea == 0x5U) || (tmea == 0xFU))
{
ret = true;
}
return ret;
}
/* TMEK Bit Fields */
/**
*@brief write Test re-enable mode key
*
*/
LOCAL_INLINE void SEC_HWA_ReEnTestKey(uint32_t testkey)
{
SEC->TMEK = SEC_TMEK_TMEK(testkey) ;
}
/* FCR0 Bit Fields */
/**
* @brief Enable the Mass Erase
*/
LOCAL_INLINE void SEC_HWA_EnME(void)
{
SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_MED_MASK)) | SEC_FCR0_MED(0x5));
}
/**
* @brief Enable the Block 0 NVR write .
*/
LOCAL_INLINE void SEC_HWA_EnWriteB0NVR(void)
{
SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_NWP_MASK)) | SEC_FCR0_NWP(0x5)) ;
}
/**
* @brief Disable the Block 0 NVR write .
*/
LOCAL_INLINE void SEC_HWA_DisWriteB0NVR(void)
{
SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_NWP_MASK)) | SEC_FCR0_NWP(0xA)) ;
}
/**
* @brief Enable the Block 0 NVR erase .
*/
LOCAL_INLINE void SEC_HWA_EnEraseB0NVR(void)
{
SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_NEP_MASK)) | SEC_FCR0_NEP(0x5)) ;
}
/**
* @brief Disable the Block 0 NVR erase .
*/
LOCAL_INLINE void SEC_HWA_DisEraseB0NVR(void)
{
SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_NEP_MASK)) | SEC_FCR0_NEP(0xA)) ;
}
/* NKRP Bit Fields */
/**
* @brief NVR Key Read Protection.
* @brief Enable the Block 0 NVR read.
*/
LOCAL_INLINE void SEC_HWA_EnReadB0NVR(void)
{
SEC->FCR0 = ((SEC->NKRP & (~SEC_NKRP_NKRP_MASK)) | SEC_NKRP_NKRP(0x5)) ;
}
/**
* @brief Disable the Block 0 NVR read .
*/
LOCAL_INLINE void SEC_HWA_DisReadB0NVR(void)
{
SEC->FCR0 = ((SEC->FCR0 & (~SEC_NKRP_NKRP_MASK)) | SEC_NKRP_NKRP(0xA)) ;
}
/* BCS Bit Fields */
/**
* @brief Get the Fast Boot Select.
* @return 0b - Select PLL0 as the core clock source; the core clock is 300MHz
* 1b - Select FIRC as the core clock source; the core clock is 96MHz.
* */
LOCAL_INLINE uint8_t SEC_HWA_GetFastBootClock(void)
{
return (uint8_t)((SEC->BCS & SEC_BCS_FBS_MASK) >> SEC_BCS_FBS_SHIFT);
}
/**
* @brief NMI Function Enable/Disable
* @return false - NMI pin function is disabled after reset.
* true - NMI pin function is enabled
* */
LOCAL_INLINE bool SEC_HWA_GetNmiPin(void)
{
return (bool)((SEC->BCS & SEC_BCS_NMIDIS_MASK) >> SEC_BCS_NMIDIS_SHIFT);
}
/**
* @brief ISP Function Enable/Disable ISP Mode Status
* @return false - ISP mode is inactive.
* true - ISP mode is active.
* */
LOCAL_INLINE bool SEC_HWA_GetIspStatus(void)
{
return (bool)((SEC->BCS & SEC_BCS_ISPMODE_MASK) >> SEC_BCS_ISPMODE_SHIFT);
}
/**
* @brief Boot Rom Configuration
* @return false - Boot from GPR defined address (except ROM).
* true - Boot from ROM.
* */
LOCAL_INLINE bool SEC_HWA_GetBootRom(void)
{
return (bool)((SEC->BCS & SEC_BCS_BOOTROM_MASK) >> SEC_BCS_BOOTROM_SHIFT);
}
/**
* @brief Get Chip Part Mode
* @return false - Chip is in FlexCore part mode.
* true - Chip is in HSM part mode.
* */
LOCAL_INLINE bool SEC_HWA_GetPartMode(void)
{
return (bool)((SEC->BCS & SEC_BCS_PART_MODE_MASK) >> SEC_BCS_PART_MODE_SHIFT);
}
/**
* @brief Get PF_128BIT_MODE
* @return false - Chip is in FlexCore part mode.
* true - Chip is in HSM part mode.
* */
LOCAL_INLINE bool SEC_HWA_GetPF128BitMode(void)
{
return (bool)((SEC->BCS & SEC_BCS_PF_128BIT_MODE_MASK) >> SEC_BCS_PF_128BIT_MODE_SHIFT);
}
/* UKAC Bit Fields */
/**
* @brief User Key Access Enable. Only valid under non-secure boot
* @return true means User key can be read/programmed/erased by host CPU ,false means User key is not available for host cpu
* */
LOCAL_INLINE bool SEC_HWA_GetUKAS(void)
{
bool ret = false;
uint8_t uake =(uint8_t)((SEC->UKAC & SEC_UKAC_UKAE_MASK) >> SEC_UKAC_UKAE_SHIFT);
if ((uake == 0x5U) || (uake == 0xFU))
{
ret = true;
}
return ret;
}
/* BRC0 Bit Fields */
/**
* @brief Secure Boot Disable (Value loaded from NVR sector)
* @return true means Secure boot mode , false means Non secure boot mode.
*/
LOCAL_INLINE bool SEC_HWA_GetSB(void)
{
bool ret = false;
uint8_t sbdis = (uint8_t)((SEC->BRC0 & SEC_BRC0_SECURE_BOOT_DIS_MASK) >> SEC_BRC0_SECURE_BOOT_DIS_SHIFT);
if (sbdis == 0x0u)
{
ret = true;
}
return ret;
}
/**
* @brief Host Debug Auth Enable. Only valid in secure boot. (Value loaded from NVR sector)
* @return true means Host debug authentication enable. false means Host debug authentication disable.
*/
LOCAL_INLINE bool SEC_HWA_GetDEAUEn(void)
{
bool ret = false;
uint8_t dean = (uint8_t)((SEC->BRC0 & SEC_BRC0_DEBUG_AUTH_EN_MASK) >> SEC_BRC0_DEBUG_AUTH_EN_SHIFT);
if ((dean == 0x5u) || (dean == 0xFu))
{
ret = true;
}
return ret;
}
/**
* @brief ISP Auth Enable. Only valid in secure boot. (Value loaded from NVR sector)
* @return true means ISP authentication enable, false means ISP authentication disable.
*/
LOCAL_INLINE bool SEC_HWA_GetISPAU(void)
{
bool ret = false;
uint8_t isp = (uint8_t)((SEC->BRC0 & SEC_BRC0_ISP_AUTH_EN_MASK) >> SEC_BRC0_ISP_AUTH_EN_SHIFT);
if ((isp == 0x5u) || (isp == 0xFu))
{
ret = true;
}
return ret;
}
/* BRC1 Bit Fields */
/**
* @brief Get the FCUART Baud Rate for ISP
* @return FCUART Baud Rate for ISP
* */
LOCAL_INLINE uint8_t SEC_HWA_GetUartBR(void)
{
return (uint8_t)((SEC->BRC1 & SEC_BRC1_UARTBR_MASK) >> SEC_BRC1_UARTBR_SHIFT);
}
/**
* @brief Get CAN Baud Rate for ISP
* @return CAN Baud Rate for ISP
* */
LOCAL_INLINE uint8_t SEC_HWA_GetCanBR(void)
{
return (uint8_t)((SEC->BRC1 & SEC_BRC1_CANBR_MASK) >> SEC_BRC1_CANBR_SHIFT);
}
/**
* @brief Get OSC Frequency
* @return OSC Frequency
* */
LOCAL_INLINE uint8_t SEC_HWA_GetOSCFre(void)
{
return (uint8_t)((SEC->BRC1 & SEC_BRC1_OSCFREQ_MASK) >> SEC_BRC1_OSCFREQ_SHIFT);
}
/**
* @brief Get whether OSC Available.
* @return true means OSC is available. false means -OSC is not available
* */
LOCAL_INLINE bool SEC_HWA_GetOSCAvail(void)
{
bool ret = false;
uint8_t osc = (uint8_t)((SEC->BRC1 & SEC_BRC1_OSCA_MASK) >> SEC_BRC1_OSCA_SHIFT);
if (osc == 0x0U)
{
ret = true;
}
return ret;
}
/**
* @brief Get Debug Backdoor Key Input Enable.
* @return
* 0011b - User can input DBK through debug mailbox, ISP is not valid
* 1100b - User can input DBK through ISP, debug mailbox is not valid.
* 1111b - User can input DBK through both debug mailbox and ISP.
* Other Values - User cannot input DBK through both debug mailbox andISP
* */
LOCAL_INLINE uint32_t SEC_HWA_GetMBBKEN(void)
{
return (uint32_t)((SEC->BRC1 & SEC_BRC1_DBK_IN_EN_MASK) >> SEC_BRC1_DBK_IN_EN_SHIFT);
}
/**
* @brief Get Debug Backdoor Key Encryption Algorithm
* @return false-User code verification enable in non-secure boot mode
true- User code verification disable in non-secure boot mode.
* */
LOCAL_INLINE bool SEC_HWA_GetNonSecVerifEN(void)
{
bool ret = false;
uint8_t dean = (uint8_t)((SEC->BRC0 & SEC_BRC1_NON_SEC_VERIF_EN_MASK) >> SEC_BRC1_NON_SEC_VERIF_EN_SHIFT);
if (dean == 1u)
{
ret = true;
}
return ret;
}
/**
* @brief Get User Code Verification Enable under Non-secure Boot Mode
* @return Bootloader Verification Algorithm
* 000b - AES256-CBC
* 111b - SM4-CBC.
* */
LOCAL_INLINE uint8_t SEC_HWA_GetDBDkeyEncrypAlg(void)
{
return (uint8_t)((SEC->BRC1 & SEC_BRC1_DBKEA_MASK) >> SEC_BRC1_DBKEA_SHIFT);
}
/**
* @brief ISP Function Enable/Disable，Only valid in non-secure mode
* @return false - ISP pin function is disabled after reset.
* true - ISP pin function is enabled.
* */
LOCAL_INLINE bool SEC_HWA_GetIspEn(void)
{
return (bool)((SEC->BRC1 & SEC_BRC1_ISP_PIN_EN_MASK) >> SEC_BRC1_ISP_PIN_EN_SHIFT);
}
/**
* @brief GET ISP Mode whether Allowed in Recovery Mode
* @return false - ISP mode is not allowed in recovery mode
* true - ISP mode is allowed in recovery mode.
* */
LOCAL_INLINE bool SEC_HWA_GetIspIsAllowedInRec(void)
{
return (bool)((SEC->BRC1 & SEC_BRC1_ISPAIRM_MASK) >> SEC_BRC1_ISPAIRM_SHIFT);
}
/**
* @brief GET Enable the Output of Plaintext Decrypted ROOT Key
* @return false - The output of plaintext decrypted ROOT key is enabled
* true - The output of plaintext decrypted ROOT key is disabled.
* */
LOCAL_INLINE bool SEC_HWA_GetKeyPlaRoot(void)
{
return (bool)((SEC->BRC1 & SEC_BRC1_KEY_PROT_MASK) >> SEC_BRC1_KEY_PROT_SHIFT);
}
/**
* @brief Get ROM Loop Control Flag
* @return false - ROM executes normal run under VIRGIN and FT state.
* true - ROM enters debug loop under VIRGIN and FT state.
* */
LOCAL_INLINE bool SEC_HWA_GetLoopCtrFlag(void)
{
return (bool)((SEC->BRC1 & SEC_BRC1_ROM_LOOP_CTRL_MASK) >> SEC_BRC1_ROM_LOOP_CTRL_SHIFT);
}
/**
* @brief Get Enable Software Configuration to Enter ISP
* @return false - Software configuration to enter ISP is enabled.
* true - Software configuration to enter ISP is disabled.
* */
LOCAL_INLINE bool SEC_HWA_GetIspSoftConfig(void)
{
return (bool)((SEC->BRC1 & SEC_BRC1_SW_CFG_ISP_EN_MASK) >> SEC_BRC1_SW_CFG_ISP_EN_SHIFT);
}
/* SW_CFG_ISP_FLG Bit Fields */
/**
* @brief Software Configuration to Enter ISP Flag
* @return ISP Flag.
* */
LOCAL_INLINE uint8_t SEC_HWA_GetSwCfgIspFlg(void)
{
return (uint8_t)((SEC->SW_CFG_ISP_FLG & SEC_SW_CFG_ISP_FLG_SW_CFG_ISP_FLG_MASK) >> SEC_SW_CFG_ISP_FLG_SW_CFG_ISP_FLG_SHIFT);
}
/* BRC2 Bit Fields */
/**
* @brief Get USERCODE_VERIFY_MASK_MASK
* @return USERCODE_VERIFY_MASK_MASK.
* */
LOCAL_INLINE uint32_t SEC_HWA_GetBLMask(void)
{
return (uint32_t)((SEC->BRC2 & SEC_BRC2_USERCODE_VERIFY_MASK_MASK) >> SEC_BRC2_USERCODE_VERIFY_MASK_SHIFT);
}
/**
* @brief Get the ISP Instance Select.
* @return ISP Instance Select
* */
LOCAL_INLINE uint8_t SEC_HWA_GetIspIns(void)
{
return (uint8_t)((SEC->BRC2 & SEC_BRC2_ISP_INST_SEL_MASK) >> SEC_BRC2_ISP_INST_SEL_SHIFT);
}
/**
* @brief Get Bootloader Verification Algorithm
* @return Bootloader Verification Algorithm
* */
LOCAL_INLINE uint8_t SEC_HWA_GetBLVer(void)
{
return (uint8_t)((SEC->BRC2 & SEC_BRC2_USERCODE_VERIFICATION_ALG_MASK) >> SEC_BRC2_USERCODE_VERIFICATION_ALG_SHIFT);
}
/**
* @brief Get Debug/ISP/PREFA Authentication and USRK decryption algorithm
* @return 1b - SM2, 0b - ECC256
* */
LOCAL_INLINE uint8_t SEC_HWA_GetDecrypt(void)
{
return (uint8_t)((SEC->BRC2 & SEC_BRC2_DECRP_ALG_MASK) >> SEC_BRC2_DECRP_ALG_SHIFT);
}
/* IMAGEA Bit Fields */
/**
* @brief Get the bootloader address.
* @return Bootloader Address.
* */
LOCAL_INLINE uint32_t SEC_HWA_GetBLAddr(void)
{
return (uint32_t)((SEC->IMGEA & SEC_IMGEA_IMAGE_ADDR_MASK) >> SEC_IMGEA_IMAGE_ADDR_SHIFT);
}
/* NVR VER Bit Fields */
/**
* @brief Get C version.
* @return C version.
* */
LOCAL_INLINE uint32_t SEC_HWA_GetCVer(void)
{
return (uint32_t)((SEC->NVR_VER & SEC_NVR_VER_C_VER_MASK) >> SEC_NVR_VER_C_VER_SHIFT);
}
/**
* @brief Set C version.
* @return C version.
* */
LOCAL_INLINE void SEC_HWA_SetCVer(uint32_t C_Ver)
{
SEC->NVR_VER=((SEC->NVR_VER & (~SEC_NVR_VER_C_VER_MASK)) | SEC_NVR_VER_C_VER(C_Ver));
}
/**
* @brief Get R version.
* @return R version.
* */
LOCAL_INLINE uint32_t SEC_HWA_GetRVer(void)
{
return (uint32_t)((SEC->NVR_VER & SEC_NVR_VER_R_VER_MASK) >> SEC_NVR_VER_R_VER_SHIFT);
}
/**
* @brief Set R version.
* */
LOCAL_INLINE void SEC_HWA_SetRVer(uint32_t R_Ver)
{
SEC->NVR_VER=((SEC->NVR_VER & (~SEC_NVR_VER_R_VER_MASK)) | SEC_NVR_VER_R_VER(R_Ver));
}
/**
* @brief Get V version.
* @return V version.
* */
LOCAL_INLINE uint32_t SEC_HWA_GetVVer(void)
{
return (uint32_t)((SEC->NVR_VER & SEC_NVR_VER_V_VER_MASK) >> SEC_NVR_VER_V_VER_SHIFT);
}
/**
* @brief Set V version.
* */
LOCAL_INLINE void SEC_HWA_SetVVer(uint32_t V_Ver)
{
SEC->NVR_VER=((SEC->NVR_VER & (~SEC_NVR_VER_V_VER_MASK)) | SEC_NVR_VER_V_VER(V_Ver));
}
/**
* @brief Get CHIP version.
* @return CHIP version.
* */
LOCAL_INLINE uint32_t SEC_HWA_GetChipVer(void)
{
return (uint32_t)((SEC->NVR_VER & SEC_NVR_VER_CHIP_VER_MASK) >> SEC_NVR_VER_CHIP_VER_SHIFT);
}
/**
* @brief Set CHIP version.
* */
LOCAL_INLINE void SEC_HWA_SetChipVer(uint32_t CHIP_Ver)
{
SEC->NVR_VER=((SEC->NVR_VER & (~SEC_NVR_VER_CHIP_VER_MASK)) | SEC_NVR_VER_V_VER(CHIP_Ver));
}
/* LCSTAT Bit Fields */
/**
* @brief Get the life cycle status of the chip.
* @return The lifecycle status
* */
LOCAL_INLINE uint8_t SEC_HWA_GetLCStaus(void)
{
return (uint8_t)(SEC->LCSTAT & 0XFFU);
}
/**
* @brief Get Lifecycle OEM Development
* @return 0b - Chip is not in this lifecycle
* 1b - Chip is in this lifecycle
* */
LOCAL_INLINE bool SEC_HWA_GetLCOemDev(void)
{
return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_OEM_DEV_MASK) >> SEC_LCSTAT_LIFECYCLE_OEM_DEV_SHIFT);
}
/**
* @brief Get Lifecycle OEM Production
* @return false - Chip is not in this lifecycle
* true - Chip is in this lifecycle
* */
LOCAL_INLINE bool SEC_HWA_GetLCOemPdt(void)
{
return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_OEM_PDT_MASK) >> SEC_LCSTAT_LIFECYCLE_OEM_PDT_SHIFT);
}
/**
* @brief Get Lifecycle In Field
* @return false - Chip is not in this lifecycle
* true - Chip is in this lifecycle
* */
LOCAL_INLINE bool SEC_HWA_GetLCInField(void)
{
return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_IN_FIELD_MASK) >> SEC_LCSTAT_LIFECYCLE_IN_FIELD_SHIFT);
}
/**
* @brief Get Lifecycle Software Fault Analysis
* @return false - Chip is not in this lifecycle
* true - Chip is in this lifecycle
* */
LOCAL_INLINE bool SEC_HWA_GetLCSwFa(void)
{
return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_SWFA_MASK) >> SEC_LCSTAT_LIFECYCLE_SWFA_SHIFT);
}
/**
* @brief Get Lifecycle Hardware Fault Analysis
* @return false - Chip is not in this lifecycle
* true - Chip is in this lifecycle
* */
LOCAL_INLINE bool SEC_HWA_GetLCHwFa(void)
{
return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_HWFA_MASK) >> SEC_LCSTAT_LIFECYCLE_HWFA_SHIFT);
}
/* FAC Bit Fields */
/**
* @brief Get the Host User Key Read Protection
* @return true - Host read access to User Key region is enabled
* false - Host read access to User Key region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHUKRead(void)
{
return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_UKEY_RPROT_MASK) >> SEC_FAC_HOST_UKEY_RPROT_SHIFT));
}
/**
* @brief Get the Host User Key write Protection
* @return true - Host write access to User Key region is enabled
* false - Host write access to User Key region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHUKWrite(void)
{
return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_UKEY_WPROT_MASK) >> SEC_FAC_HOST_UKEY_WPROT_SHIFT));
}
/**
* @brief Get the Host User Key erase Protection
* @return true - Host erase access to User Key region is enabled
* false - Host erase access to User Key region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHUKErase(void)
{
return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_UKEY_EPROT_MASK) >> SEC_FAC_HOST_UKEY_EPROT_SHIFT));
}
/**
* @brief Get the Host NVR Read Protection
* @return true - Host read access to NVR region is enabled
* false - Host read access to NVR region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHostNvrRead(void)
{
return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_NVR_RPROT_MASK) >> SEC_FAC_HOST_NVR_RPROT_SHIFT));
}
/**
* @brief Get the Host NVR write Protection
* @return true - Host write access to NVR region is enabled
* false - Host write access to NVR region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHostNvrWrite(void)
{
return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_NVR_WPROT_MASK) >> SEC_FAC_HOST_NVR_WPROT_SHIFT));
}
/**
* @brief Get the Host NVR erase Protection
* @return true - Host erase access to NVR region is enabled
* false - Host erase access to NVR region is disabled-
* */
LOCAL_INLINE bool SEC_HWA_GetHostNvrErase(void)
{
return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_NVR_EPROT_MASK) >> SEC_FAC_HOST_NVR_EPROT_SHIFT));
}
/**
* @brief Get HSM User Key Read Protection
* @return true - HSM Read access to User Key region is disabled
* false - HSM Read access to User Key region is enabled
* */
LOCAL_INLINE bool SEC_HWA_GetHsmUKRead(void)
{
return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_UKEY_RPROT_MASK) >> SEC_FAC_HSM_UKEY_RPROT_SHIFT));
}
/**
* @brief Get HSM User Key Program Protection
* @return true - HSM Program access to User Key region is disabled
* false - HSM Program access to User Key region is enabled
* */
LOCAL_INLINE bool SEC_HWA_GetHsmUKProg(void)
{
return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_UKEY_WPROT_MASK) >> SEC_FAC_HSM_UKEY_WPROT_SHIFT));
}
/**
* @brief Get the HSM User Key Erase Protection
* @return true - HSM erase access to User Key region is enabled
* false -HSM erase access to User Key region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHsmUKErase(void)
{
return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_UKEY_EPROT_MASK) >> SEC_FAC_HSM_UKEY_EPROT_SHIFT));
}
/**
* @brief Get HSM NVR Key Read Protection
* @return true - HSM Read access to NVR key region is disabled
* false - HSM Read access to NVR key region is enabled
* */
LOCAL_INLINE bool SEC_HWA_GetHsmNvrKRead(void)
{
return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_NVR_RPROT_MASK) >> SEC_FAC_HSM_NVR_RPROT_SHIFT));
}
/**
* @brief Get HSM NVR Program Protection
* @return true - HSM Program access to NVR region is disabled
* false - HSM Program access to NVR region is enabled
* */
LOCAL_INLINE bool SEC_HWA_GetHsmNvrProg(void)
{
return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_NVR_WPROT_MASK) >> SEC_FAC_HSM_NVR_WPROT_SHIFT));
}
/**
* @brief Get the HSM NVR Erase Protection
* @return true - HSM erase access to NVR region is enabled
* false -HSM erase access to NVR region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHsmNvrErase(void)
{
return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_NVR_EPROT_MASK) >> SEC_FAC_HSM_NVR_EPROT_SHIFT));
}
/* FLEXCORE_EN Bit Fields */
/**
* @brief Get the FlexCore Enable.
* @return true means enable ,false means disable.
* */
LOCAL_INLINE bool SEC_HWA_GetFlexCoreEn(void)//?
{
bool ret = false;
uint8_t srk = (uint8_t)((SEC->FLEXCORE_EN & SEC_FLEXCORE_EN_FLEXCORE_EN_MASK) >> SEC_FLEXCORE_EN_FLEXCORE_EN_SHIFT);
if (srk == 0xFU||srk == 0x5U)
{
ret = true;
}
return ret;
}
/**
* @brief Set the FlexCore Enable.
* @return true means set sucess ,false means set fail,0x5 and 0xf is enable,others is disable.
* */
LOCAL_INLINE bool SEC_HWA_SetFlexCoreEn(uint8_t CoreEn)
{
if(CoreEn>0xF)
return false;
SEC->FLEXCORE_EN = ((SEC->FLEXCORE_EN & (~SEC_FLEXCORE_EN_FLEXCORE_EN_MASK)) | SEC_FLEXCORE_EN_FLEXCORE_EN(CoreEn));
return true;
}
/**
* @brief Get SEC_FLEXCORE_EN FLEXCORE_DBG.
* @return true means enable ,false means disable.
* */
LOCAL_INLINE bool SEC_HWA_GetFlexCoreDbgEn(void)
{
return (bool)((SEC->FLEXCORE_EN & SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_MASK) >> SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_SHIFT);
}
/**
* @brief Set SEC_FLEXCORE_EN FLEXCORE_DBG.
* */
LOCAL_INLINE void SEC_HWA_SetFlexCoreDbgEn(uint8_t DbgEn)
{
SEC->FLEXCORE_EN=((SEC->FLEXCORE_EN & (~SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_MASK)) | SEC_FLEXCORE_EN_FLEXCORE_DBG_EN(DbgEn));
}
/* FLEX_CODE_ADDR Bit Fields */
/**
* @brief Get Code Header Address for FlexCore Always 4-byte aligned
* @return FLEX Code Header Address.
* */
LOCAL_INLINE uint32_t SEC_HWA_GetFlexCodeHeadAddr(void)
{
return (uint32_t)((SEC->FLEX_CODE_ADDR & SEC_FLEX_CODE_ADDR_FLEX_CODE_ADDR_MASK) >> SEC_FLEX_CODE_ADDR_FLEX_CODE_ADDR_SHIFT);
}
/* PFLASH_PRLLL_EN Bit Fields */
/**
* @brief Get PFLASH Parallel Enable
* @return
* 0101b - Disable
* Others - Enable
* */
LOCAL_INLINE bool SEC_HWA_GetPflashPrlllEn(void)
{
bool ret = false;
uint32_t srk=(uint32_t)((SEC->PFLASH_PRLLL_EN & SEC_PFLASH_PRLLL_EN_PFLASH_PRLLL_EN_MASK) >> SEC_PFLASH_PRLLL_EN_PFLASH_PRLLL_EN_SHIFT);
if (srk !=0x5U)
{
ret =true ;
}
return ret;
}
/** @}*/ /* HwA_SEC */
#endif /* HWA_INCLUDE_HWA_SEC_H_ */

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/**
* @file HwA_smc.h
* @author Flagchip
* @brief FC7xxx SMC hardware access layer
* @version 0.1.0
* @date 2022-11-21
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
#ifndef _HWA_SMC_H_
#define _HWA_SMC_H_
#include "device_header.h"
/********* Local typedef ************/
/** @brief SMC stop mode control */
typedef enum
{
SMC_STOP_MODE = 0U,
SMC_STANDBY_MODE = 4U
} SMC_LpwModeCtrlType;
/** @brief SMC standby mode */
typedef enum
{
SMC_CFG_STANDBY_0 = 0U,
SMC_CFG_STANDBY_1 = 1U,
SMC_CFG_STANDBY_2 = 2U,
SMC_CFG_STANDBY_3 = 3U
} SMC_StandbyModeType;
/********* Local inline function ************/
/**
* @brief Clear stop mode control value
*
*/
LOCAL_INLINE void SMC_HWA_ClearStopModeCtrl(void)
{
SMC->PMCTRL &= ~(uint32_t)SMC_PMCTRL_STOP_MODE_MASK;
}
/**
* @brief Set stop mode control
*
* @param eMode Stop mode control type
*/
LOCAL_INLINE void SMC_HWA_SetStopModeCtrl(SMC_LpwModeCtrlType eMode)
{
SMC->PMCTRL = (uint32_t)eMode;
}
/**
* @brief Clear standby mode
*
*/
LOCAL_INLINE void SMC_HWA_ClearStandbyMode(void)
{
SMC->STANDBY_CFG &= ~(uint32_t)SMC_STANDBY_CFG_OPTION_MASK;
}
/**
* @brief Set standby mode
*
* @param eMode Standby mode type
*/
LOCAL_INLINE void SMC_HWA_SetStandbyMode(SMC_StandbyModeType eMode)
{
SMC->STANDBY_CFG = (uint32_t)eMode;
}
#endif /* #ifndef _HWA_SMC_H_ */

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/**
* @file HwA_stcu.h
* @author Flagchip
* @brief Safety Test and Control Unit
* @version 0.1.0
* @date 2022-11-30
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 03/08/2022 Flagchip038 N/A First version for FC7xxx
******************************************************************************** */
#ifndef _HWA_STCU_H_
#define _HWA_STCU_H_
#include "device_header.h"
#include "fc7xxx_driver_stcu.h"
/**
* \brief Get Self Test Status
*
* \return Status, maybe more than one status, refer to "STCU_SelfTestStatusType"
*/
LOCAL_INLINE uint32_t STCU_HWA_GetSelfTestStatus(void)
{
return STCU->SELF_TEST_STATUS;
}
/**
* \brief Clear all Self Test Status
*/
LOCAL_INLINE void STCU_HWA_ClearSelfTestStatus(void)
{
STCU->SELF_TEST_STATUS = 0x0UL;
}
/**
* \brief Mbist select for self-test
*
* \param u32MbistSel maybe more than one
*/
LOCAL_INLINE void STCU_HWA_MbistSelect(uint32_t u32MbistSel)
{
STCU->MBIST_SEL = u32MbistSel;
}
/**
* \brief Get Mbist Done Flag
*
* \return All Mbist Done flags, refer to "STCU_MbistDoneType"
*/
LOCAL_INLINE uint32_t STCU_GetMbistDone(void)
{
return STCU->MBIST_DONE_STATUS;
}
/**
* \brief Get Mbist Fail Flag
*
* \return All Mbist Fail flags "STCU_MbistFailedType"
*/
LOCAL_INLINE uint32_t STCU_GetMbistFail(void)
{
return STCU->MBIST_FAIL_STATUS;
}
/**
* \brief Check Lbist execution failed status
*
* \return LBIST status, refer to "STCU_LbistStatusType"
*/
LOCAL_INLINE uint32_t STCU_HWA_CheckLbistStatus(void)
{
return STCU->LBIST_STATUS;
}
/**
* \brief Get STCU Hardware Ram Initial Status
*
* \return Initial Status, refer to "STCU_HardwareInitRamStatusType"
*/
LOCAL_INLINE uint32_t STCU_HWA_GetHardwareRamInitStatus(void)
{
return STCU->SRAM_INI_STATUS;
}
/**
* \brief STCU RAM Init Mode set, can select more than one, for example: STCU_INIT_RAM_TYPE_SRAM0 | STCU_INIT_RAM_TYPE_SRAM1
*
* \param u32InitRamType Init Mode
*/
LOCAL_INLINE void STCU_HWA_SetRamInitType(uint32_t u32InitRamType)
{
STCU->SRAM_INI_SEL = u32InitRamType;
}
/**
* \brief Set STCU Interrupt
*
* \param bIntEn Normal interrupt enable
* \param bSequenceErrorIntEn Sequence error interrupt enable
* \param bSizeErrorIntEn Size error interrupt enable
*/
LOCAL_INLINE void STCU_HWA_SetInterrupt(uint8_t bIntEn, uint8_t bSequenceErrorIntEn, uint8_t bSizeErrorIntEn)
{
STCU->IRQ = STCU_IRQ_EN(bIntEn) | STCU_IRQ_SEQ_ERR(bSequenceErrorIntEn) | STCU_IRQ_SIZE_ERR(bSizeErrorIntEn);
}
/**
* \brief STCU Ram Initial Start
*
* \param eInitRamMode Initial mode
* \param bEnable Enable Initial
* \param bLock Lock after initial
*/
LOCAL_INLINE void STCU_HWA_StartRamInit(STCU_InitRamModeType eInitRamMode, uint8_t bLock)
{
STCU->SRAM_INI_CTRL = STCU_SRAM_INI_CTRL_MODE(eInitRamMode) | STCU_SRAM_INI_CTRL_EN_MASK | STCU_SRAM_INI_CTRL_LOCK(bLock) ;
}
/**
* \brief Get Ram Initial Done flag
*
* \return All Done flag, maybe more than one flag, refer to "STCU_InitRamDoneType"
*/
LOCAL_INLINE uint32_t STCU_HWA_GetRamInitDone(void)
{
return STCU->SRAM_INI_DONE_STATUS;
}
/**
* \brief Get Ram Initial status
*
* \return All Done flag, maybe more than one flag, refer to "STCU_HardwareInitRamStatusType"
*/
LOCAL_INLINE uint32_t STCU_HWA_GetRamInitStatus(void)
{
return STCU->SRAM_INI_STATUS;
}
/**
* \brief Set the LBIST pattern amount control value N.
*
* \param u32Amount LBIST pattern amount control value N. (pattern amount = N * 256)
*/
LOCAL_INLINE void STCU_HWA_SetLBISTPatternAmount(uint32_t u32Amount)
{
STCU->LBIST_PAT_CTRL = u32Amount;
}
/**
* \brief Set the MBIST algorithm for SW trigger self-test
*
* \param bFullTest Enable Full test for MBIST.
* \param bSRAMInit Enable SRAM initialization at the end of software trigger self-test.
*/
LOCAL_INLINE void STCU_HWA_SetMBISTSWAlg(bool bFullTest, bool bSRAMInit)
{
STCU->MBIST_ALG = (STCU->MBIST_ALG & ~(STCU_MBIST_ALG_TRIG_ALG_SEL_MASK | STCU_MBIST_ALG_TRIG_INI_EN_MASK)) | \
(STCU_MBIST_ALG_TRIG_ALG_SEL(bFullTest?0X1FU:0x19U) | STCU_MBIST_ALG_TRIG_INI_EN(bSRAMInit?0x1U:0x0U));
}
/**
* \brief Set safety key
*
* \param u32Key Safety Key.
*/
LOCAL_INLINE void STCU_HWA_SetSafetyKey(uint32_t u32Key)
{
STCU->SELF_TEST_KEY = u32Key;
}
/**
* \brief Enable A self-test software trigger.
*/
LOCAL_INLINE void STCU_HWA_SwTriggerA(void)
{
STCU->SELF_TEST_TRIG_A = STCU_SELF_TEST_TRIG_A_MASK;
}
/**
* \brief Enable B self-test software trigger.
*/
LOCAL_INLINE void STCU_HWA_SwTriggerB(void)
{
STCU->SELF_TEST_TRIG_B = STCU_SELF_TEST_TRIG_B_MASK;
}
/**
* \brief Set self test ctrl register
*
* \param u32Reg Register value.
*/
LOCAL_INLINE void STCU_HWA_SetSelfTestCTRL(uint32_t u32Reg)
{
STCU->SELF_TEST_CTRL = u32Reg;
}
/**
* \brief Enable interrupt
*/
LOCAL_INLINE void STCU_HWA_EnableInterrupt(void)
{
STCU->IRQ |= STCU_IRQ_EN_MASK;
}
/**
* \brief Disable interrupt
*/
LOCAL_INLINE void STCU_HWA_DisableInterrupt(void)
{
STCU->IRQ &= ~STCU_IRQ_EN_MASK;
}
/**
* \brief Get STCU interrupt flags
*
* \return Status, maybe more than one status, refer to "STCU_InterruptFlagType"
*/
LOCAL_INLINE uint32_t STCU_HWA_GetInterruptFlag(void)
{
return ((STCU->IRQ) & (STCU_IRQ_SEQ_ERR_MASK | STCU_IRQ_SIZE_ERR_MASK));
}
/**
* \brief Clear STCU interrupt flags
*/
LOCAL_INLINE void STCU_HWA_ClearInterruptFlag(void)
{
STCU->IRQ &= ~(STCU_IRQ_SEQ_ERR_MASK | STCU_IRQ_SIZE_ERR_MASK);
}
/**
* \brief Set STCU LBIST expected misr value
*/
LOCAL_INLINE void STCU_HWA_SetExpectedMisr(uint32_t u32Misr)
{
STCU->LBIST_EXP_MISR = STCU_LBIST_EXP_MISR_MISR(u32Misr);
}
/**
* \brief Get STCU LBIST expected misr value
*/
LOCAL_INLINE uint32_t STCU_HWA_GetExpectedMisr(void)
{
return STCU->LBIST_EXP_MISR;
}
/**
* \brief Get STCU LBIST actual misr value
*/
LOCAL_INLINE uint32_t STCU_HWA_GetActualMisr(void)
{
return STCU->LBIST_ACT_MISR;
}
#endif /*#ifndef _HWA_STCU_H_*/

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/**
* @file HwA_tmu.h
* @author Flagchip
* @brief Hardware access layer for TMU
* @version 0.1.0
* @date 2023-12-29
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/*********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-29 qxw074 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_TMU_H
#define _HWA_TMU_H
#include "device_header.h"
#include "HwA_csc.h"
/**
* @defgroup HwA_tmu
* @ingroup fc7xxx_driver_tmu
* @{
*/
/**
* @brief Select the TF_CTRL and TV_CTRL register is lock or not
*
*/
typedef enum
{
TMU_TF_TV_LOCK = 0U, /*!< TF_CTRL and TV_CTRL register is lock*/
TMU_TF_TV_UNLOCK = 1U /*!< TF_CTRL and TV_CTRL register is unlock*/
}TMU_LockType;
/**
* @brief Select the Flag-based temperature sensor hysteresis control
*
*/
typedef enum
{
TMU_TF_HYSOFF_ON = 0U, /*!< Flag-based temperature sensor hysteresis is on*/
TMU_TF_HYSOFF_OFF = 1U /*!< Flag-based temperature sensor hysteresis is off*/
}TMU_HysteresisType;
/**
* @brief Select the Flag-based temperature sensor filter control
*
*/
typedef enum
{
TMU_TF_FILT_BYP_BYPASSED = 0U, /*!< Flag-based temperature sensor filter is bypassed*/
TMU_TF_FILT_BYP_ENABLED = 1U /*!< Flag-based temperature sensor filter is enabled*/
}TMU_bypassType;
/**
* @brief Get the status of whether the temperature sensor register is locked
*
* @param pTmu the base address of the TMU instance
* @return true Temperature register is locked(CTRL)
* @return false Temperature register is unlocked(CTRL)
*/
LOCAL_INLINE TMU_LockType TMU_HWA_GetTemperatureLockStatus(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->UNLOCK & TMU_UNLOCK_UNLOCK_MASK) >> TMU_UNLOCK_UNLOCK_SHIFT;
return (TMU_LockType)u32TmpVal;
}
/**
* @brief Set the status of whether the temperature sensor register is locked or not
*
* @param pTmu the base address of the TMU instance
* @param eLockStatus Select the TF_CTRL and TV_CTRL register is lock or not
*/
LOCAL_INLINE void TMU_HWA_SetTemperatureLockStatus(TMU_Type *const pTmu,TMU_LockType eLockStatus)
{
if((bool)eLockStatus)
{
pTmu->UNLOCK = 0xA5A50000U | TMU_UNLOCK_UNLOCK(eLockStatus);
}else
{
pTmu->UNLOCK = TMU_UNLOCK_UNLOCK(eLockStatus);
}
}
/**
* @brief Get the Flag-based temperature sensor over 150 Celsius interrupt flag
*
* @param pTmu the base address of the TMU instance
* @return true Temperature over 150 Celsius interrupt is enabled
* @return false Temperature over 150 Celsius interrupt is disabled
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperature150InterruptFlag(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_150F_IE_MASK) >> TMU_TF_CTRL_TF_150F_IE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Flag-based temperature sensor over 150 Celsius interrupt flag
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether to enable the temperature over 150 Celsius interrupt
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperature150InterruptFlag(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_150F_IE_MASK) | TMU_TF_CTRL_TF_150F_IE(bEnable);
}
/**
* @brief Get the Flag-based temperature sensor over 125 Celsius interrupt flag
*
* @param pTmu the base address of the TMU instance
* @return true Temperature over 125 Celsius interrupt is enabled
* @return false Temperature over 125 Celsius interrupt is disabled
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperature125InterruptFlag(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_125F_IE_MASK) >> TMU_TF_CTRL_TF_125F_IE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Flag-based temperature sensor over 125 Celsius interrupt flag
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether to enable the temperature over 125 Celsius interrupt
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperature125InterruptFlag(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_125F_IE_MASK) | TMU_TF_CTRL_TF_125F_IE(bEnable);
}
/**
* @brief Get the Flag-based temperature sensor ready interrupt flag
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor ready interrupt is enabled
* @return false Temperature sensor ready interrupt is disabled
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureReadyInterruptFlag(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_RDYF_IE_MASK) >> TMU_TF_CTRL_TF_RDYF_IE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Flag-based temperature sensor over ready interrupt flag
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether to enable the temperature sensor ready interrupt
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperatureReadyInterruptFlag(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_RDYF_IE_MASK) | TMU_TF_CTRL_TF_RDYF_IE(bEnable);
}
/**
* @brief Get the Flag-based temperature sensor hysteresis control status
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor Hysteresis is off
* @return false Temperature sensor Hysteresis is on
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureHysteresisStatus(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_HYSOFF_MASK) >> TMU_TF_CTRL_TF_HYSOFF_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Flag-based temperature sensor hysteresis control status
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether to off(1)/on(0) the temperature sensor hysteresis
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperatureHysteresisStatus(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_HYSOFF_MASK) | TMU_TF_CTRL_TF_HYSOFF(bEnable);
}
/**
* @brief Get the Flag-based temperature sensor startup counter
*
* @param pTmu the base address of the TMU instance
* @return u32TmpVal count of the startup
*/
LOCAL_INLINE uint8_t TMU_HWA_GetFlagTemperatureCounter(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_START_CNT_MASK) >> TMU_TF_CTRL_TF_START_CNT_SHIFT;
return (uint8_t)u32TmpVal;
}
/**
* @brief Set the Flag-based temperature sensor startup counter
*
* @param pTmu the base address of the TMU instance
* @param u8Counter the startup counter
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperatureCounter(TMU_Type *const pTmu,uint8_t u8Counter)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_START_CNT_MASK) | TMU_TF_CTRL_TF_START_CNT(u8Counter);
}
/**
* @brief Get the Flag-based temperature sensor filter bypass control status
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor Filter is enabled
* @return false Temperature sensor Filter is bypassed
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureFilterBypassStatus(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_FILT_BYP_MASK) >> TMU_TF_CTRL_TF_FILT_BYP_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Flag-based temperature sensor filter bypass control status
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether the temperature sensor filter is enabled(1) or bypassed(0)
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperatureFilterBypassStatus(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_FILT_BYP_MASK) | TMU_TF_CTRL_TF_FILT_BYP(bEnable);
}
/**
* @brief Get the Flag-based temperature sensor enable status
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor is on
* @return false Temperature sensor is off
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureEnableStatus(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_EN_MASK) >> TMU_TF_CTRL_TF_EN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Flag-based temperature sensor enable status
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether the temperature sensor is on(1) or off(0)
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperatureEnableStatus(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_EN_MASK) | TMU_TF_CTRL_TF_EN(bEnable);
}
/**
* @brief Check whether the temperature is over 150 Celsius
*
* @param pTmu the base address of the TMU instance
* @return true the temperature is over 150 Celsius
* @return false the temperature is not over 150 Celsius
*/
LOCAL_INLINE bool TMU_HWA_Get150Status(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TF_STATUS;
u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_150_MASK) >> TMU_TF_STATUS_TF_150_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Check whether the temperature is over 125 Celsius
*
* @param pTmu the base address of the TMU instance
* @return true the temperature is over 125 Celsius
* @return false the temperature is not over 125 Celsius
*/
LOCAL_INLINE bool TMU_HWA_Get125Status(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TF_STATUS;
u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_125_MASK) >> TMU_TF_STATUS_TF_125_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Check whether the flag for temperature over 150 Celsius is set
*
* @param pTmu the base address of the TMU instance
* @return true the temperature has exceeded 150 Celsius since last time W1C
* @return false the temperature has not exceeded 150 Celsius since TF is ready
*/
LOCAL_INLINE bool TMU_HWA_Get150Flag(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TF_STATUS;
u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_150F_MASK) >> TMU_TF_STATUS_TF_150F_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the temperature over 150 Celsius flag
*
* @param pTmu the base address of the TMU instance
*/
LOCAL_INLINE void TMU_HWA_Clear150Flag(TMU_Type *const pTmu)
{
pTmu->TF_STATUS |= TMU_TF_STATUS_TF_150F(1U);
}
/**
* @brief Check whether the flag for temperature over 125 Celsius is set
*
* @param pTmu the base address of the TMU instance
* @return true the temperature has exceeded 125 Celsius since last time W1C
* @return false the temperature has not exceeded 125 Celsius since TF is ready
*/
LOCAL_INLINE bool TMU_HWA_Get125Flag(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TF_STATUS;
u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_125F_MASK) >> TMU_TF_STATUS_TF_125F_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the temperature over 125 Celsius flag
*
* @param pTmu the base address of the TMU instance
*/
LOCAL_INLINE void TMU_HWA_Clear125Flag(TMU_Type *const pTmu)
{
pTmu->TF_STATUS |= TMU_TF_STATUS_TF_125F(1U);
}
/**
* @brief Check whether the Flag-based temperature sensor is ready
*
* @param pTmu the base address of the TMU instance
* @return true the Flag-based temperature sensor is ready
* @return false the Flag-based temperature sensor is not ready
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureReady(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TF_STATUS;
u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_RDYF_MASK) >> TMU_TF_STATUS_TF_RDYF_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the Flag-based temperature sensor ready flag
*
* @param pTmu the base address of the TMU instance
*/
LOCAL_INLINE void TMU_HWA_ClearFlagTemperatureReady(TMU_Type *const pTmu)
{
pTmu->TF_STATUS |= TMU_TF_STATUS_TF_RDYF(1U);
}
/**
* @brief Get the Vlotage-based temperature sensor ready interrupt flag
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor ready interrupt is enabled
* @return false Temperature sensor ready interrupt is disabled
*/
LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureReadyInterruptFlag(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_RDYF_IE_MASK) >> TMU_TV_CTRL_TV_RDYF_IE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Voltage-based temperature sensor over ready interrupt flag
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether to enable the temperature sensor ready interrupt
*/
LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureReadyInterruptFlag(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_RDYF_IE_MASK) | TMU_TV_CTRL_TV_RDYF_IE(bEnable);
}
/**
* @brief Get the Voltage-based temperature sensor startup counter
*
* @param pTmu the base address of the TMU instance
* @return u32TmpVal count of the startup
*/
LOCAL_INLINE uint8_t TMU_HWA_GetVoltageTemperatureCounter(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_START_CNT_MASK) >> TMU_TV_CTRL_TV_START_CNT_SHIFT;
return (uint8_t)u32TmpVal;
}
/**
* @brief Set the Voltage-based temperature sensor startup counter
*
* @param pTmu the base address of the TMU instance
* @param u8Counter the startup counter
*/
LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureCounter(TMU_Type *const pTmu,uint8_t u8Counter)
{
pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_START_CNT_MASK) | TMU_TV_CTRL_TV_START_CNT(u8Counter);
}
/**
* @brief Get the Voltage-based temperature sensor enable status
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor is on
* @return false Temperature sensor is off
*/
LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureEnableStatus(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_EN_MASK) >> TMU_TV_CTRL_TV_EN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Voltage-based temperature sensor enable status
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether the temperature sensor is on(1) or off(0)
*/
LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureEnableStatus(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_EN_MASK) | TMU_TV_CTRL_TV_EN(bEnable);
}
/**
* @brief Check whether the Voltage-based temperature sensor is ready
*
* @param pTmu the base address of the TMU instance
* @return true the Voltage-based temperature sensor is ready
* @return false the Voltage-based temperature sensor is not ready
*/
LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureReady(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TV_STATUS;
u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_RDYF_MASK) >> TMU_TV_STATUS_TV_RDYF_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the Voltage-based temperature sensor ready flag
*
* @param pTmu the base address of the TMU instance
*/
LOCAL_INLINE void TMU_HWA_ClearVoltageTemperatureReady(TMU_Type *const pTmu)
{
pTmu->TV_STATUS |= TMU_TV_STATUS_TV_RDYF(1U);
}
/**
* @brief Get the TMU_TF_CTRL config
*
* @param pTmu the base address of the TMU instance
* @return uint32_t the TMU_TF_CTRL config
*/
LOCAL_INLINE uint32_t TMU_HWA_GetFlagTempCtrl(const TMU_Type *const pTmu)
{
return pTmu->TF_CTRL;
}
/**
* @brief Set the TMU_TF_CTRL config
*
* @param pTmu the base address of the TMU instance
* @param u32Config the TMU_TF_CTRL config
*/
LOCAL_INLINE void TMU_HWA_SetFlagTempCtrl(TMU_Type *const pTmu, uint32_t u32Config)
{
pTmu->TF_CTRL = u32Config;
}
/**
* @brief Get the TMU_TV_CTRL config
*
* @param pTmu the base address of the TMU instance
* @return uint32_t the TMU_TV_CTRL config
*/
LOCAL_INLINE uint32_t TMU_HWA_GetVoltageTempCtrl(const TMU_Type *const pTmu)
{
return pTmu->TV_CTRL;
}
/**
* @brief Set the TMU_TV_CTRL config
*
* @param pTmu the base address of the TMU instance
* @param u32Config the TMU_TV_CTRL config
*/
LOCAL_INLINE void TMU_HWA_SetVoltageTempCtrl(TMU_Type *const pTmu, uint32_t u32Config)
{
pTmu->TV_CTRL = u32Config;
}
/**
* @brief Controls the stop ack function enable or not to the TMU0
*
* @param bEnable set the ACK enable or not
*/
LOCAL_INLINE void TMU_HWA_SetStopAck(bool bEnable)
{
if(bEnable)
{
CSC0_HWA_MODER0_EnableStopAck(CSC_STOPMODE_TMU);
}
else
{
CSC0_HWA_MODER0_DisableStopAck(CSC_STOPMODE_TMU);
}
}
/**
* @brief Get the TV_TRIM_TV_TCODE value
*
* @param pTmu the base address of the TMU instance
* @return uint32_t the TV_TRIM_TV_TCODE value
*/
LOCAL_INLINE uint32_t TMU_HWA_GetTemperatureCode(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TV_TRIM;
u32TmpVal = (u32TmpVal & TMU_TV_TRIM_TV_TCODE_MASK) >> TMU_TV_TRIM_TV_TCODE_SHIFT;
return u32TmpVal;
}
/**
* @brief Get the TV_TRIM_TV_SLOPE value
*
* @param pTmu the base address of the TMU instance
* @return uint32_t the TV_TRIM_TV_SLOPE value
*/
LOCAL_INLINE uint32_t TMU_HWA_GetSlopeFactor(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TV_TRIM;
u32TmpVal = (u32TmpVal & TMU_TV_TRIM_TV_SLOPE_MASK) >> TMU_TV_TRIM_TV_SLOPE_SHIFT;
return u32TmpVal;
}
/** @}*/
#endif /* _HWA_TMU_H_ */

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/**
* @file HwA_tpuh.h
* @author Flagchip
* @brief FC7xxx TPUH hardware access layer
* @version 0.1.0
* @date 2024-1-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
#ifndef _HWA_TPUH_H_
#define _HWA_TPUH_H_
#include "device_header.h"
#if 1
/********* Local typedef ************/
/** @brief TPU TCR1 clock control mode type */
typedef enum
{
TPUH_CLK_SRC_TCRCLK = 0U,
UTPUH_PDOWN_CNT_MODE = 3U,
TPUH_CLK_SRC_TPUCLKDIV2 = 4U,
TPUH_CLK_SRC_TPUCLK = 5U
} TPUH_TCR1ClkCtrlModeType;
/** @brief TPU angle tick gen clk type */
typedef enum
{
TPUH_TCR1_PRESCAL_OUTPUT = 0U,
TPUH_TCR2_PRESCAL_OUTPUT = 1U
} TPUH_AngleTickGenClkType;
/** @brief TPU Angle Mode Selection type */
typedef enum
{
TPUH_TCR2_TIMEBASE_EAC_DISABLE = 0U,
TPUH_TOOTHSIGNAL_AS_TCRCLK_TOOTH_CH_0 = 1U,
TPUH_TOOTHSIGNAL_AS_CH1INPUT_TOOTH_CH_1 = 2U,
TPUH_TOOTHSIGNAL_AS_CH2INPUT_TOOTH_CH_2 = 3U
} TPUH_AngleModeSel;
/** @brief TPU Angle Mode Selection type */
typedef enum
{
TPUH_TWO_SAMPLE_MODE_TPU_CLK_DIV2 = 0U,
TPUH_TWO_SAMPLE_MODE_CH_CLK = 1U,
TPUH_INTEGRATOR_MODE_TPU_CLK_DIV2 = 2U,
TPUH_INTEGRATOR_MODE_CH_CLK = 3U
} TPUH_TCRClkFilterType;
/** @brief TPU TCR2 clock control mode0 type */
typedef enum
{
TPUH_GATED_DIV8_CLK = 0U,
TPUH_RISE_TRANSITION_INCREMENT_TCR2_PRESCALER = 1U,
TPUH_FALL_TRANSITION_INCREMENT_TCR2_PRESCALER = 2U,
TPUH_DIV8_CLK = 4U,
TPUH_UPDOWN_CNT_MODE = 5U,
TPUH_FROZEN = 7U
} TPUH_TCR1ClkCtrlMode0Type;
typedef enum
{
TPUH_RSING_EDGE = 1U,
TPUH_FALLING_EDGE = 2U,
TPUH_BOTH_EDGES = 3U,
TPUH_NO_EDGE = 6U,
} TPUH_TCR1ClkCtrlMode1Type;
/** @brief Missing Tooth Counter */
typedef enum
{
TPUH_NOT_A_MISSING_TOOTH = 0U,
TPUH_ONE_MISSING_TOOTH = 1U,
TPUH_TWO_MISSING_TOOTH = 2U,
TPUH_THREE_MISSING_TOOTH = 3U,
} TPUH_MissToothCntType;
/** @brief Channel Trigger Configuration */
typedef enum
{
TPUH_DISABLED = 0U,
TPUH_ANY_EVENT_GATED_BY_MSRTSR = 2U,
TPUH_HSA_EVENT_ON_FLEXCORE_MODE = 3U,
TPUH_MRL1_EVENT_NOT_GATED_BY_MSR = 4U,
TPUH_MRL2_EVENT_NOT_GATED_BY_MSR = 5U,
TPUH_MRL1_OR_MRL2_EVENT_NOT_GATED_BY_MSR = 6U,
TPUH_MRL1_AND_MRL2_EVENT_NOT_GATED_BY_MSR = 7U,
TPUH_TDL1_OR_TDL2_EVENT_NOT_GATED_BY_TSR = 8U,
TPUH_TDL1_AND_TDL2_EVENT_NOT_GATED_BY_TSR = 9U,
TPUH_EVENT_EQUAL_TO_CH_DO_LEVEL = 10U,
TPUH_EVENT_NEGATIVE_TO_CH_DO_LEVEL = 11U,
TPUH_EVENT_EQUAL_TO_CH_DO_PART1_LEVEL = 12U,
TPUH_EVENT_EQUAL_TO_CH_DO_PART2_LEVEL = 13U,
TPUH_EVENT_EQUAL_TO_CH_IND_LEVEL = 14U,
TPUH_EVENT_EQUAL_TO_CH_IND_LATCH_LEVEL = 15U,
} TPUH_ChTrigCFGType;
#endif
/********* Local inline function ************/
/**
* @brief Get service request status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetSRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VSR & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get pin input status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetInputStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VIR & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get pin output status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetoutputStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VOR & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get pin output enable status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetoutputEnStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VOBR & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get MRL1 status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetMRL1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VM1R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get MRL2 status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetMRL2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VM2R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TDL1 status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetTDL1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VT1R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TDL2 status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetTDL2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VT2R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get MRL1 event status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetMRL1EventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_EM1R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get MRL2 event status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetMRL2EventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_EM2R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TDL1 event status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetTDL1eventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_ET1R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TDL2 event status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetTDL2eventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_ET2R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get HAS status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetHASStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VHSR & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TCR1 prescaler.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1Prescaler(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR1P_MASK) >> TPU_H_TBR_CR_TCR1P_SHIFT;
return u32TmpVal;
}
/**
* @brief Get TCR1 clock control.
*
*/
LOCAL_INLINE TPUH_TCR1ClkCtrlModeType TPU_H_HWA_GetTCR1ClkControl(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR1CTL_MASK) >> TPU_H_TBR_CR_TCR1CTL_SHIFT;
return (TPUH_TCR1ClkCtrlModeType)u32TmpVal;
}
/**
* @brief Get TCR2 prescaler.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2Prescaler(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2P_MASK) >> TPU_H_TBR_CR_TCR2P_SHIFT;
return u32TmpVal;
}
/**
* @brief Get Angle tick generator clock.
*
*/
LOCAL_INLINE TPUH_AngleTickGenClkType TPU_H_HWA_GetATGC(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_ATGC_MASK) >> TPU_H_TBR_CR_ATGC_SHIFT;
return (TPUH_AngleTickGenClkType)u32TmpVal;
}
/**
* @brief Get Angle Mode Selection.
*
*/
LOCAL_INLINE TPUH_AngleModeSel TPU_H_HWA_GetAM(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_AM_MASK) >> TPU_H_TBR_CR_AM_SHIFT;
return (TPUH_AngleModeSel)u32TmpVal;
}
/**
* @brief Get TCRCLK signal Filter Control.
*
*/
LOCAL_INLINE TPUH_TCRClkFilterType TPU_H_HWA_GetTCRClkFilter(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCRCF_MASK) >> TPU_H_TBR_CR_TCRCF_SHIFT;
return (TPUH_TCRClkFilterType)u32TmpVal;
}
/**
* @brief Get TCR2 clock control.
*
*/
LOCAL_INLINE TPUH_TCR1ClkCtrlMode0Type TPU_H_HWA_GetTCR2ClkControlAM0(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2CTL_MASK) >> TPU_H_TBR_CR_TCR2CTL_SHIFT;
return (TPUH_TCR1ClkCtrlMode0Type)u32TmpVal;
}
/**
* @brief Get TCR2 clock control.
*
*/
LOCAL_INLINE TPUH_TCR1ClkCtrlMode1Type TPU_H_HWA_GetTCR2ClkControlAM1(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2CTL_MASK) >> TPU_H_TBR_CR_TCR2CTL_SHIFT;
return (TPUH_TCR1ClkCtrlMode1Type)u32TmpVal;
}
/**
* @brief Get TCR1 cnt value.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1CntVal(const TPU_H_Type *const pTPUH)
{
return pTPUH->TBR_T1R;
}
/**
* @brief Get TCR2 cnt value.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2CntVal(const TPU_H_Type *const pTPUH)
{
return pTPUH->TBR_T2R;
}
/**
* @brief Get last tooth indication.
*
*/
LOCAL_INLINE bool TPU_H_HWA_NotLastTooth(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_LAST_MASK) >> TPU_H_TBR_TPR_LAST_SHIFT;
return (bool)((u32TmpVal == 0U) ? true : false);
}
/**
* @brief Get missing tooth counter.
*
*/
LOCAL_INLINE TPUH_MissToothCntType TPU_H_HWA_GetMissingTooth(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_MISSCNT_MASK) >> TPU_H_TBR_TPR_MISSCNT_SHIFT;
return (TPUH_MissToothCntType)u32TmpVal;
}
/**
* @brief Get last tooth indication.
*
*/
LOCAL_INLINE bool TPU_H_HWA_NoInsertTooth(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_IPH_MASK) >> TPU_H_TBR_TPR_IPH_SHIFT;
return (bool)((u32TmpVal == 0U) ? true : false);
}
/**
* @brief Get last tooth indication.
*
*/
LOCAL_INLINE bool TPU_H_HWA_NoForceEACHalt(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_HOLD_MASK) >> TPU_H_TBR_TPR_HOLD_SHIFT;
return (bool)((u32TmpVal == 0U) ? true : false);
}
/**
* @brief Get angle ticks number.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetAngleTicksVal(const TPU_H_Type *const pTPUH)
{
return (pTPUH->TBR_TPR & TPU_H_TBR_TPR_TICKS_MASK) >> TPU_H_TBR_TPR_TICKS_SHIFT;
}
/**
* @brief Get the integer part of TCR1 clocks in one Angle tick.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetIntergerPerAngleTick(const TPU_H_Type *const pTPUH)
{
return (pTPUH->TBR_TRR & TPU_H_TBR_TRR_INTEGER_MASK) >> TPU_H_TBR_TRR_INTEGER_SHIFT;
}
/**
* @brief Get the fraction part of TCR1 clocks in one Angle tick.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetFractionPerAngleTick(const TPU_H_Type *const pTPUH)
{
return (pTPUH->TBR_TRR & TPU_H_TBR_TRR_FRACTION_MASK) >> TPU_H_TBR_TRR_FRACTION_SHIFT;
}
/**
* @brief Get TCR1 overflow flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetTCR1Overflow(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_OVF_MASK) >> TPU_H_TBR_T1MR_OVF_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TCR1 IRQ enable flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_TCR1IRQEnable(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_IRQ_EN_MASK) >> TPU_H_TBR_T1MR_IRQ_EN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get the maximum value of TCR1 counter in TCR1 updown mode.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1MaxCnt(const TPU_H_Type *const pTPUH)
{
return (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_MAX_MASK) >> TPU_H_TBR_T1MR_MAX_SHIFT;
}
/**
* @brief Get TCR2 overflow flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_TCR2Overflow(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_OVF_MASK) >> TPU_H_TBR_T2MR_OVF_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TCR2 IRQ enable flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_TCR2IRQEnable(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_IRQ_EN_MASK) >> TPU_H_TBR_T2MR_IRQ_EN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get the maximum value of TCR2 counter in TCR1 updown mode.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2MaxCnt(const TPU_H_Type *const pTPUH)
{
return (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_MAX_MASK) >> TPU_H_TBR_T2MR_MAX_SHIFT;
}
/**
* @brief Get channel HSA enable flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChHSAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHAE_MASK) >> TPU_H_CHn_CR_CHAE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set channel HSA enable or disable.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChHSA(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHAE_MASK) | TPU_H_CHn_CR_CHAE(benable));
}
/**
* @brief Set channel event trigger dma enable or disable.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChEventDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CDFD_MASK) | TPU_H_CHn_CR_CDFD(benable));
}
/**
* @brief Set channel request Dma enable or disable.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChReqDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHDE_MASK) | TPU_H_CHn_CR_CHDE(benable));
}
/**
* @brief Get channel HSR Dma request enable flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChDMAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHDE_MASK) >> TPU_H_CHn_CR_CHDE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set channel Sync isr from flexcore enable or disable.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChSyncISR(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHEE_MASK) | TPU_H_CHn_CR_CHEE(benable));
}
/**
* @brief Get channel HSR event as interrupt enable flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChHSRISREnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHEE_MASK) >> TPU_H_CHn_CR_CHEE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set channel channel HSR event as interrupt enable or disable.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChHSRISR(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHEE_MASK) | TPU_H_CHn_CR_CHEE(benable));
}
/**
* @brief Get channel trigger configuration.
*
*/
LOCAL_INLINE TPUH_ChTrigCFGType TPU_H_HWA_GetChTrigCondition(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CTC_MASK) >> TPU_H_CHn_CR_CTC_SHIFT;
return (TPUH_ChTrigCFGType)u32TmpVal;
}
/**
* @brief Set channel trigger configuration.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChTrig(TPU_H_Type *const pTPUH, uint8_t u8Channel, TPUH_ChTrigCFGType etrgcfg)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CTC_MASK) | TPU_H_CHn_CR_CTC(etrgcfg));
}
/**
* @brief Get channel trigger DMA enable.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChTrigDMAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CDFD_MASK) >> TPU_H_CHn_CR_CDFD_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set channel trigger DMA enable.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChTrigDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CDFD_MASK) | TPU_H_CHn_CR_CDFD(benable));
}
/**
* @brief Get channel HSR index.
*
*/
LOCAL_INLINE uint8 TPU_H_HWA_GetChHSRIdx(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHSR_MASK) >> TPU_H_CHn_CR_CHSR_SHIFT;
return (uint8)u32TmpVal;
}
/**
* @brief Get channel HSR index.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChHSRIdx(TPU_H_Type *const pTPUH, uint8_t u8Channel, uint8_t u8HSRIdx)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHSR_MASK) | TPU_H_CHn_CR_CHSR(u8HSRIdx));
}
/**
* @brief Get channel event trigger interrupt status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChEventTrigISRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CIS_MASK) >> TPU_H_CHn_SR_CIS_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get channel host service request (HSR) status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChHSRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (uint8_t)(pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHRS_MASK) >> TPU_H_CHn_SR_CHRS_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get HSA.
*
*/
LOCAL_INLINE uint8 TPU_H_HWA_GetChHSAIdx(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHRI_MASK) >> TPU_H_CHn_SR_CHRI_SHIFT;
return (uint8_t)u32TmpVal;
}
/**
* @brief Get channel event as interrupt status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChDMAReq(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHDS_MASK) >> TPU_H_CHn_SR_CHDS_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get channel trigger status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChTrigStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CTS_MASK) >> TPU_H_CHn_SR_CTS_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get channel host service acknowledge (HSA) interrupt status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChHSAReqStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHAS_MASK) >> TPU_H_CHn_SR_CHAS_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear channel interrupt by event.
*
*/
LOCAL_INLINE void TPU_H_HWA_ClearChEventISRFlg(TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CEIC_MASK;
}
/**
* @brief Clear channel HSA.
*
*/
LOCAL_INLINE void TPU_H_HWA_ClearChHSA(TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CHAC_MASK;
}
/**
* @brief Clear channel HSR.
*
*/
LOCAL_INLINE void TPU_H_HWA_ClearChHSR(TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CHRT_MASK;
}
/**
* @brief Get channel service request.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChServiceReq(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_CSR_MASK) >> TPU_H_CHn_EFR_CSR_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get channel service request to HOST.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChServiceReqToHost(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_CHSR_MASK) >> TPU_H_CHn_EFR_CHSR_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get match recognition latch 1 event status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_EMRL1_MASK) >> TPU_H_CHn_EFR_EMRL1_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get match recognition latch 2 event status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_EMRL2_MASK) >> TPU_H_CHn_EFR_EMRL2_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get transition detect latch 1 event status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch1Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_ETDL1_MASK) >> TPU_H_CHn_EFR_ETDL1_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get transition detect latch 2 event status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch2Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_ETDL2_MASK) >> TPU_H_CHn_EFR_ETDL2_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get match recognition latch 1 enable status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1En(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRLE1_MASK) >> TPU_H_CHn_EFR_MRLE1_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get match recognition latch 2 enable status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2En(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRLE2_MASK) >> TPU_H_CHn_EFR_MRLE2_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get match recognition latch 1 enable status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRL1_MASK) >> TPU_H_CHn_EFR_MRL1_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get match recognition latch 2 enable status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRL2_MASK) >> TPU_H_CHn_EFR_MRL2_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get Transition Detect latch 1 enable status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_TDL1_MASK) >> TPU_H_CHn_EFR_TDL1_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get Transition Detect latch 2 enable status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_TDL2_MASK) >> TPU_H_CHn_EFR_TDL2_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
#endif /* #ifndef _HWA_TPUH_H_ */

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@ -0,0 +1,150 @@
/**
* @file HwA_trgsel.h
* @author Flagchip0103
* @brief Hardware access layer for TrgSel
* @version 0.1.0
* @date 2023-12-19
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-19 Flagchip0103 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_TRGSEL_H_
#define _HWA_TRGSEL_H_
#include "device_header.h"
#define TRGSEL_REGSIZE 4U
/**
* @brief Get the trigger source of the selected trigger target
*
* @param pTrgsel the base address of the TrgSel instance
* @param u32TargetIndex the trigger target to get the trigger source
* @return uint32_t the trigger source of the selected trigger target
*/
LOCAL_INLINE uint32_t TRGSEL_HWA_GetTargetTriggerSource(const TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex)
{
uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE;
uint32_t u32SelIdx = u32TargetIndex % TRGSEL_REGSIZE;
uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx];
switch (u32SelIdx)
{
case 0U:
{
u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_0_MASK) >> TRGSEL_OUT_SEL_SEL_0_SHIFT;
break;
}
case 1U:
{
u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_1_MASK) >> TRGSEL_OUT_SEL_SEL_1_SHIFT;
break;
}
case 2U:
{
u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_2_MASK) >> TRGSEL_OUT_SEL_SEL_2_SHIFT;
break;
}
case 3U:
{
u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_3_MASK) >> TRGSEL_OUT_SEL_SEL_3_SHIFT;
break;
}
default:
break;
}
return (uint32_t)u32Tmp;
}
/**
* @brief Set the trigger source of the selected trigger target
*
* @param pTrgsel the base address of the TrgSel instance
* @param u32TargetIndex the trigger target to set the trigger source
* @param u32SourceIndex the selected trigger source to trig the target
*/
LOCAL_INLINE void TRGSEL_HWA_SetTargetTriggerSource(TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex,
uint32_t u32SourceIndex)
{
uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE;
uint32_t u32SelIdx = u32TargetIndex % TRGSEL_REGSIZE;
uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx];
switch (u32SelIdx)
{
case 0U:
{
u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_0_MASK) | TRGSEL_OUT_SEL_SEL_0(u32SourceIndex);
break;
}
case 1U:
{
u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_1_MASK) | TRGSEL_OUT_SEL_SEL_1(u32SourceIndex);
break;
}
case 2U:
{
u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_2_MASK) | TRGSEL_OUT_SEL_SEL_2(u32SourceIndex);
break;
}
case 3U:
{
u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_3_MASK) | TRGSEL_OUT_SEL_SEL_3(u32SourceIndex);
break;
}
default:
break;
}
pTrgsel->OUT_SEL[u32RegIdx] = u32Tmp;
}
/**
* @brief Get wether the trigger source of the selected target is locked
*
* @param pTrgsel the base address of the TrgSel instance
* @param u32TargetIndex the trigger target to get the lock status
* @return true the trigger source of the selected target cannot be modified
* @return false the trigger source of the selected target can be modified
*/
LOCAL_INLINE bool TRGSEL_HWA_GetTargetLockStatus(const TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex)
{
uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE;
uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx];
u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_LOCK_MASK) >> TRGSEL_OUT_SEL_LOCK_SHIFT;
return (bool)((u32Tmp != 0U) ? true : false);
}
/**
* @brief Lock the trigger source of the selected target
*
* @note The trigger target is grouped by four, so if you lock the trigger source of one target, the
* adjacent three trigger targets in the same register group are also be locked. So please ensure the
* trigger sources are not to be modified before lock the trigger target.
*
* @param pTrgsel the base address of the TrgSel instance
* @param u32TargetIndex the trigger target to lock the trigger source
*/
LOCAL_INLINE void TRGSEL_HWA_LockTargetTriggerSource(TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex)
{
uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE;
pTrgsel->OUT_SEL[u32RegIdx] |= TRGSEL_OUT_SEL_LOCK_MASK;
}
/** @}*/
#endif /* _HWA_TRGSEL_H_ */

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/**
* @file HwA_tstmp.h
* @author Flagchip
* @brief FC7xxx TSTMP hardware access layer
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 Flagchip0122 N/A FC7xxx internal release version
********************************************************************************/
#ifndef _HWA_TSTMP_H_
#define _HWA_TSTMP_H_
#include "device_header.h"
/********* Local typedef ************/
/** @brief Tstmp modulate number */
typedef enum
{
TSTMP_MOD0 = 0U,
TSTMP_MOD1,
TSTMP_MOD2,
TSTMP_MOD3,
} TSTMP_ModulateType;
/** @brief Tstmp running mode */
typedef enum
{
TSTMP_MODE_ALWAYS_RUNNING = 0U,
TSTMP_MODE_PERIOD_RUNNING = 1U
} TSTMP_ModeCounterRunningMode;
typedef enum
{
TSTMP_SIRC1M_CLK = 0U,
TSTMP_AON_CLK = 1U
} TSTMP_ClockSourceType;
/********* Local inline function ************/
/**
* @brief Read TSTMP value
*
* @param pTstmp TSTMP instance
* @return TSTMP value
*/
LOCAL_INLINE uint64_t TSTMP_HWA_ReadTstmpValue(TSTMP_Type *pTstmp)
{
uint32_t u32TstmpL, u32TstmpH;
uint64_t u64TempValue;
u32TstmpL = pTstmp->VALL;
u32TstmpH = pTstmp->VALH;
u64TempValue = u32TstmpH;
u64TempValue = (u64TempValue << 32U) + u32TstmpL;
return u64TempValue;
}
/**
* @brief Read TSTMP interrupt enable bits
*
* @param pTstmp TSTMP instance
* @return TSTMP interrupt enable bits
*/
LOCAL_INLINE uint32_t TSTMP_HWA_ReadTstmpInterruptEnable(TSTMP_Type *pTstmp)
{
return (uint32_t)pTstmp->MOD_INTEN;
}
/**
* @brief Enable TSTMP MOD(n) match interrupt
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
*/
LOCAL_INLINE void TSTMP_HWA_EnableModMatchInterrupt(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod)
{
pTstmp->MOD_INTEN |= ((uint32_t)1U << (uint32_t)eMod);
}
/**
* @brief Disable TSTMP MOD(n) match interrupt
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
*/
LOCAL_INLINE void TSTMP_HWA_DisableModMatchInterrupt(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod)
{
pTstmp->MOD_INTEN &= ~((uint32_t)1U << (uint32_t)eMod);
}
/**
* @brief Set the counting modes of TSTMP MOD(n)
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
* @param eCounterMode Counting mode set
*/
LOCAL_INLINE void TSTMP_HWA_SetModCounterMode(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod, TSTMP_ModeCounterRunningMode eCounterMode)
{
pTstmp->MOD_INTEN = (pTstmp->MOD_INTEN & ~((uint32_t)0x100U << (uint32_t)eMod)) |
(((uint32_t)eCounterMode << TSTMP_MOD_INTEN_MOD0_MODE_SHIFT) << (uint32_t)eMod);
}
/**
* @brief Enable TSTMP MOD(n) counter
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
*/
LOCAL_INLINE void TSTMP_HWA_EnableModCounter(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod)
{
pTstmp->MOD_INTEN |= (TSTMP_MOD_INTEN_MOD0_ENABLE_MASK << (uint32_t)eMod);
}
/**
* @brief Disable TSTMP MOD(n) counter
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
*/
LOCAL_INLINE void TSTMP_HWA_DisableModCounter(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod)
{
pTstmp->MOD_INTEN &= ~(TSTMP_MOD_INTEN_MOD0_ENABLE_MASK << (uint32_t)eMod);
}
/**
* @brief Select TSTMP MOD(n) clock source
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
*/
LOCAL_INLINE void TSTMP_HWA_SelectClkSource(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod, TSTMP_ClockSourceType eClk)
{
pTstmp->MOD_INTEN |= (((uint32_t)eClk) << (TSTMP_MOD_INTEN_MOD0_CLK_SHIFT + (uint32_t)eMod));
}
/**
* @brief Read TSTMP all MOD match flag
*
* @param pTstmp TSTMP instance
* @return TSTMP all MOD match flag
*/
LOCAL_INLINE uint32_t TSTMP_HWA_ReadModMatchFlag(TSTMP_Type *pTstmp)
{
return ((uint32_t)(pTstmp->MOD_STATUS) & (uint32_t)(TSTMP_MOD_STATUS_MOD0_MATCH_MASK | TSTMP_MOD_STATUS_MOD1_MATCH_MASK
| TSTMP_MOD_STATUS_MOD2_MATCH_MASK | TSTMP_MOD_STATUS_MOD3_MATCH_MASK));
}
/**
* @brief Clear TSTMP all MOD(0) match flag
*
* @param pTstmp TSTMP instance
*/
LOCAL_INLINE void TSTMP_HWA_ClearMod0MatchFlag(TSTMP_Type *pTstmp)
{
pTstmp->MOD_STATUS = (uint32_t)(TSTMP_MOD_STATUS_MOD0_MATCH_MASK);
}
/**
* @brief Clear TSTMP all MOD(1,2,3) match flag
*
* @param pTstmp TSTMP instance
*/
LOCAL_INLINE void TSTMP_HWA_ClearAllMod123MatchFlag(TSTMP_Type *pTstmp)
{
pTstmp->MOD_STATUS = (uint32_t)(TSTMP_MOD_STATUS_MOD1_MATCH_MASK | TSTMP_MOD_STATUS_MOD2_MATCH_MASK |
TSTMP_MOD_STATUS_MOD3_MATCH_MASK);
}
/**
* @brief Clear TSTMP single MOD(1,2,3) match flag
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
*/
LOCAL_INLINE void TSTMP_HWA_ClearSingleMod123MatchFlag(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod)
{
pTstmp->MOD_STATUS = ((uint32_t)1U << (uint32_t)eMod);
}
/**
* @brief Set MOD match value
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
* @param u32ModValue MOD value
*/
LOCAL_INLINE void TSTMP_HWA_SetModMatchValue(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod, uint32_t u32ModValue)
{
switch(eMod)
{
case TSTMP_MOD0:
pTstmp->MOD0_SETVAL = u32ModValue;
break;
case TSTMP_MOD1:
pTstmp->MOD1_SETVAL = u32ModValue;
break;
case TSTMP_MOD2:
pTstmp->MOD2_SETVAL = u32ModValue;
break;
case TSTMP_MOD3:
pTstmp->MOD3_SETVAL = u32ModValue;
break;
default:
break;
}
}
#endif /* #ifndef _HWA_TSTMP_H_ */

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/**
* @file HwA_WDOG.h
* @author Flagchip
* @brief FC7xxx Wdog hardware access layer
* @version 0.1.0
* @date 2022-04-16
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/*********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-29 qxw0074 N/A First version for FC7240
******************************************************************************** */
#ifndef _HWA_WDOG_H_
#define _HWA_WDOG_H_
#include "device_header.h"
/**
* @addtogroup HwA_WDOG
* @{
*/
/********* Local typedef ************/
/********* Local inline function ************/
/********* Wdog Register interface ************/
/**
* @brief Set CS register value, for Wdog working mode configuration.
*
* @param WDOG_Type *pWdog. point to wdog instance base register address.
*
* @param uint32_t u32Cs. configured register value
*/
LOCAL_INLINE void WDOG_HWA_SetCs(WDOG_Type *pWdog, uint32_t u32Cs)
{
pWdog->CS = u32Cs;
}
/**
* @brief Get CS register value, for WDOG working mode configuration.
* @return uint32_t CS register value.
*/
LOCAL_INLINE uint32_t WDOG_HWA_GetCs(WDOG_Type *pWdog)
{
uint32_t u32Temp = 0U;
u32Temp = pWdog->CS;
return u32Temp;
}
/**
* @brief Clear Wdog interrupt flag.
*
* @param WDOG_Type *pWdog. point to wdog instance base register address.
*/
LOCAL_INLINE void WDOG_HWA_ClearInterruptFlag(WDOG_Type *pWdog)
{
pWdog->CS |= WDOG_CS_FLAG_MASK;
}
/**
* @brief Get WDOG unlock status, if locked, register can't be written.
* @return bool. true as unlocked. false as locked.
*/
LOCAL_INLINE bool WDOG_HWA_GetUnlockStatus(WDOG_Type *pWdog)
{
return (bool)((((uint32_t)pWdog->CS & (uint32_t)WDOG_CS_ULK_STAT_MASK) != 0U) ? true : false);
}
/**
* @brief Set COUNTER register value. for Wdog unlock and refresh usage.
*
* @param pWdog. point to wdog instance base register address.
*
* @param u32Counter. configured register value
*/
LOCAL_INLINE void WDOG_HWA_SetCounter(WDOG_Type *pWdog, uint32_t u32Counter)
{
pWdog->COUNTER = u32Counter;
}
/**
* @brief Set TIMEOUT register value. for WDOG timeout value
*
* @param WDOG_Type *pWdog. point to wdog instance base register address.
*
* @param uint16_t u16Timeout configured register value
*/
LOCAL_INLINE void WDOG_HWA_SetTimeout(WDOG_Type *pWdog, uint16_t u16Timeout)
{
pWdog->TIMEOUT = u16Timeout;
}
/**
* @brief Set WINDOW register value. for windowed WDOG low threshold value.
*
* @param WDOG_Type *pWdog. point to wdog instance base register address.
*
* @param uint16_t u16Window. configured register value
*/
LOCAL_INLINE void WDOG_HWA_SetWindow(WDOG_Type *pWdog, uint16_t u16Window)
{
pWdog->WINDOW = u16Window;
}
/** @}*/ /* HwA_WODG */
#endif /* #ifndef _HWA_WDOG_H_ */

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/**
* @file HwA_wku.h
* @author Flagchip
* @brief FC7xxx WKU hardware access layer
* @version 0.1.0
* @date 2024-01-05
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
#ifndef _HWA_WKU_H_
#define _HWA_WKU_H_
#include "device_header.h"
/********* Local typedef ************/
/** @brief Wku input */
typedef enum
{
WKU_INPUT_FCSPI0 = 0x000040U,
WKU_INPUT_FCUART = 0x000080U,
WKU_INPUT_CMP0 = 0x000400U,
WKU_INPUT_CMP1 = 0x000800U,
WKU_INPUT_TSTMP0 = 0x002000U,
WKU_INPUT_RTC_ALARM = 0x004000U,
WKU_INPUT_RTC_SECONDS = 0x008000U,
WKU_INPUT_FCPIT0 = 0x010000U,
WKU_INPUT_CMU0 = 0x020000U,
WKU_INPUT_AONTIMER = 0x040000U,
WKU_INPUT_GPIOA = 0x080000U,
WKU_INPUT_GPIOC = 0x100000U,
WKU_INPUT_GPIOE = 0x200000U,
WKU_INPUT_GPIOF = 0x400000U,
WKU_INPUT_GPIOG = 0x800000U,
WKU_INPUT_MAX = 0xFFFFFFU
} WKU_WakeupInputType;
/********* mcaro ************/
#define WKU_INPUT_ALL_MASK (WKU_INPUT_FCSPI0 |\
WKU_INPUT_FCUART |\
WKU_INPUT_CMP0 |\
WKU_INPUT_CMP1 |\
WKU_INPUT_TSTMP0 |\
WKU_INPUT_RTC_ALARM |\
WKU_INPUT_RTC_SECONDS |\
WKU_INPUT_FCPIT0 |\
WKU_INPUT_CMU0 |\
WKU_INPUT_AONTIMER |\
WKU_INPUT_GPIOA |\
WKU_INPUT_GPIOC |\
WKU_INPUT_GPIOE |\
WKU_INPUT_GPIOF |\
WKU_INPUT_GPIOG |\
WKU_INPUT_MAX)
/********* Local inline function ************/
/**
* @brief Enable wakeup delay counter
*
*/
LOCAL_INLINE void WKU_HWA_EnableDelayCounter(void)
{
WKU->MDC |= (uint32_t)WKU_MDC_DLYEN_MASK;
}
/**
* @brief Disable wakeup delay counter
*
*/
LOCAL_INLINE void WKU_HWA_DisableDelayCounter(void)
{
WKU->MDC &= ~((uint32_t)WKU_MDC_DLYEN_MASK);
}
/**
* @brief Set wakeup delay time
*
* @param u8DelayTime delay time
*/
LOCAL_INLINE void WKU_HWA_SetDelayTime(uint8_t u8DelayTime)
{
uint32_t u32RegVal = WKU->MDC;
WKU->MDC = ((u32RegVal & (~WKU_MDC_DELAYTIME_MASK)) | WKU_MDC_DELAYTIME(u8DelayTime));
}
/**
* @brief Enable wakeup source
*
* @param eWakeup Wakeup source type
*/
LOCAL_INLINE void WKU_HWA_EnableWakeupSource(const WKU_WakeupInputType eWakeup)
{
if (eWakeup < WKU_INPUT_CMP0)
{
WKU->MWER0 |= (uint32_t)eWakeup;
}
else if ((eWakeup < WKU_INPUT_FCPIT0) && (eWakeup > WKU_INPUT_FCUART))
{
WKU->MWER1 |= ((uint32_t)eWakeup >> 8U);
}
else
{
WKU->MWER2 |= ((uint32_t)eWakeup >> 16U);
}
}
/**
* @brief Disable wakeup source
*
* @param eWakeup Wakeup source type
*/
LOCAL_INLINE void WKU_HWA_DisableWakeupSource(const WKU_WakeupInputType eWakeup)
{
if (eWakeup < WKU_INPUT_CMP0)
{
WKU->MWER0 &= ((~((uint32_t)eWakeup)) & (uint32_t)0xFF);
}
else if ((eWakeup < WKU_INPUT_FCPIT0) && (eWakeup > WKU_INPUT_FCUART))
{
WKU->MWER1 &= ((~(uint32_t)((uint32_t)eWakeup >> 8U)) & (uint32_t)0xFF);
}
else
{
WKU->MWER2 &= ((~(uint32_t)((uint32_t)eWakeup >> 16U)) & (uint32_t)0xFF);
}
}
/**
* @brief Read WKU wakeup source
*
* @return WKU wakeup source value
*/
LOCAL_INLINE uint32_t WKU_HWA_ReadWakeupSource(void)
{
uint32_t u32WakeupSource = 0U;
u32WakeupSource = (uint32_t)(WKU->MWER0);
u32WakeupSource |= (uint32_t)((uint32_t)(WKU->MWER1) << 8U);
u32WakeupSource |= (uint32_t)((uint32_t)(WKU->MWER2) << 16U);
return u32WakeupSource;
}
#endif /* #ifndef _HWA_WKU_H_ */

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modular.json Normal file
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{
"cmake": {
"inc_dirs": [
"Inc"
]
}
}