479 lines
12 KiB
C
479 lines
12 KiB
C
/**
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* @file HwA_fcspi.h
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* @author Flagchip
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* @brief FC7xxx FCSPI hardware access layer
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* @version 0.1.0
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* @date 2024-01-13
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*
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* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
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*
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* @details
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2024-01-12 Flagchip071 N/A First version for FC7240
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******************************************************************************** */
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#ifndef _HWA_FCSPI_H_
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#define _HWA_FCSPI_H_
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#include "device_header.h"
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/**
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* @addtogroup HwA_fcspi
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* @{
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*/
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/**
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* @brief Boolean false value definition for type FCSPI_AtomicBoolType used by FCSPI to ensure read/write atomic
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*
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*/
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#define FCSPI_FALSE ((uint8_t)0)
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/**
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* @brief Boolean true value definition for type FCSPI_AtomicBoolType used by FCSPI to ensure read/write atomic
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*
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*/
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#define FCSPI_TRUE ((uint8_t)1)
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/********* Local typedef ************/
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/**
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* @brief FCSPI Mode type, master or slave.
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*/
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typedef enum {
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FCSPI_MODE_SLAVE = 0,
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FCSPI_MODE_MASTER = 1
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} FCSPI_MasterSlaveModeType;
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/**
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* @brief Boolean type for FCSpi
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*/
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typedef uint8_t FCSPI_AtomicBoolType;
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/********* Local inline function ************/
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/**
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* @brief Read the FCSPI CTRL register value for all.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return FCSPI CTRL regsiter value.
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_GetCtrlValue(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->CTRL;
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}
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/**
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* @brief Set FCSPI CTRL value, users should write the whole value to this register.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param u32Value the value which will be written to the CTRL register.
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*/
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LOCAL_INLINE void FCSPI_HWA_SetCtrlValue(FCSPI_Type *pFCSPI, uint32_t u32Value)
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{
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pFCSPI->CTRL = u32Value;
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}
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/**
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* @brief Enable the feature of FCSPI hardware, only for starting the feature of SPI module.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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*/
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LOCAL_INLINE void FCSPI_HWA_ModuleEnable(FCSPI_Type *pFCSPI)
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{
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pFCSPI->CTRL |= FCSPI_CTRL_M_EN(1);
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}
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/**
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* @brief Disable the feature of FCSPI, and shutdown the FCSPI module.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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*/
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LOCAL_INLINE void FCSPI_HWA_ModuleDisable(FCSPI_Type *pFCSPI)
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{
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pFCSPI->CTRL &= (~(FCSPI_CTRL_M_EN_MASK));
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}
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/**
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* @brief Getting the FCSPI transfer status by reading the STATUS register.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return the whole status of FCSPI transfer, which can be read in STATUS register.
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_GetStatus(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->STATUS;
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}
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/**
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* @brief Clear FCSPI STATUS register for certain function.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param u32Value the value write to the register.
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*/
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LOCAL_INLINE void FCSPI_HWA_ClearStatus(FCSPI_Type *pFCSPI, uint32_t u32Value)
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{
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pFCSPI->STATUS = u32Value;
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}
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/**
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* @brief Get FCSPI INT_EN register value for checking which interrupt is enabled.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return FCSPI INT_EN regsiter value will be returned.
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_GetIntrruptEnableReg(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->INT_EN;
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}
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/**
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* @brief Set the FCSPI INT_EN register value for enable or disable some interrupts.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param u32Value the value write to the register.
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*/
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LOCAL_INLINE void FCSPI_HWA_SetInterruptEnableReg(FCSPI_Type *pFCSPI, uint32_t u32Value)
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{
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pFCSPI->INT_EN = u32Value;
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}
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/**
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* @brief Getting the DMA enabled status through the regsiter FCSPI DMA_EN value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return FCSPI DMA_EN regsiter value
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_GetDMAEnableReg(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->DMA_EN;
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}
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/**
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* @brief Enable or disable the DMA feature by setting the FCSPI DMA_EN register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param u32Value the value write to the register.
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*/
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LOCAL_INLINE void FCSPI_HWA_SetDMAEnableReg(FCSPI_Type *pFCSPI, uint32_t u32Value)
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{
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pFCSPI->DMA_EN = u32Value;
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}
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/**
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* @brief Get FCSPI CFG0 register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return FCSPI CFG0 regsiter value
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_GetCFG0Reg(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->CFG0;
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}
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/**
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* @brief Set FCSPI CFG0 register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param u32Value the value write to the register.
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*/
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LOCAL_INLINE void FCSPI_HWA_SetCFG0Reg(FCSPI_Type *pFCSPI, uint32_t u32Value)
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{
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pFCSPI->CFG0 = u32Value;
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}
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/**
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* @brief Get FCSPI CFG1 register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return FCSPI CFG1 regsiter value
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_GetCFG1Reg(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->CFG1;
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}
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/**
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* @brief Set FCSPI CFG1 register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param u32Value the value write to the register.
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*/
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LOCAL_INLINE void FCSPI_HWA_SetCFG1Reg(FCSPI_Type *pFCSPI, uint32_t u32Value)
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{
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pFCSPI->CFG1 = u32Value;
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}
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/**
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* @brief Set the FCSPI to master mode.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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*/
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LOCAL_INLINE void FCSPI_HWA_SetMasterMode(FCSPI_Type *pFCSPI)
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{
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pFCSPI->CFG1 |= FCSPI_CFG1_MASTER(1);
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}
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/**
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* @brief Set FCSPI to slave mode.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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*/
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LOCAL_INLINE void FCSPI_HWA_SetSlaveMode(FCSPI_Type *pFCSPI)
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{
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pFCSPI->CFG1 &= (~(FCSPI_CFG1_MASTER_MASK));
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}
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/**
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* @brief Check the current mode status, master or slave.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return the mode type of FCSPI, FCSPI_MODE_MASTER or FCSPI_MODE_SLAVE
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*/
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LOCAL_INLINE FCSPI_MasterSlaveModeType FCSPI_HWA_CheckMode(FCSPI_Type *pFCSPI)
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{
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FCSPI_MasterSlaveModeType eRet = FCSPI_MODE_SLAVE;
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if ((pFCSPI->CFG1 & FCSPI_CFG1_MASTER_MASK) == FCSPI_CFG1_MASTER(1))
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{
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eRet = FCSPI_MODE_MASTER;
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}
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return eRet;
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}
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/**
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* @brief Get FCSPI MATCH0 register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return FCSPI MATCH0 regsiter value
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_GetMatch0Value(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->DATA_MATCH0;
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}
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/**
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* @brief Set FCSPI MATCH0 register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param u32Value the value write to the register.
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*/
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LOCAL_INLINE void FCSPI_HWA_SetMatch0Value(FCSPI_Type *pFCSPI, uint32_t u32Value)
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{
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pFCSPI->DATA_MATCH0 = u32Value;
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}
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/**
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* @brief Get FCSPI MATCH1 register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return FCSPI MATCH1 regsiter value
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_GetMatch1Value(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->DATA_MATCH1;
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}
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/**
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* @brief Set FCSPI MATCH1 register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param u32Value the value write to the register.
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*/
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LOCAL_INLINE void FCSPI_HWA_SetMatch1Value(FCSPI_Type *pFCSPI, uint32_t u32Value)
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{
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pFCSPI->DATA_MATCH1 = u32Value;
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}
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/**
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* @brief Get FCSPI CLK_CFG register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return FCSPI CLK_CFG regsiter value
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_GetClockConfig(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->CLK_CFG;
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}
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/**
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* @brief Set FCSPI CLK_CFG register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param u32Value the value write to the register.
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*/
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LOCAL_INLINE void FCSPI_HWA_SetClockConfig(FCSPI_Type *pFCSPI, uint32_t u32Value)
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{
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pFCSPI->CLK_CFG = u32Value;
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}
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/**
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* @brief Get FCSPI FIFO_WTM register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return FCSPI FIFO_WTM regsiter value
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_GetFIFOWaterMark(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->FIFO_WTM;
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}
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/**
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* @brief Set FCSPI FIFO_WTM register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param u8RxWatermark the rx water mark value.
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* @param u8TxWatermark the tx water mark value.
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*/
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LOCAL_INLINE void FCSPI_HWA_SetWatermark(FCSPI_Type *pFCSPI, uint8_t u8RxWatermark, uint8_t u8TxWatermark)
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{
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uint32_t u32Flag = 0U;
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u32Flag |= ((uint32_t)u8RxWatermark << FCSPI_FIFO_WTM_RXWATER_SHIFT);
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u32Flag |= ((uint32_t)u8TxWatermark << FCSPI_FIFO_WTM_TXWATER_SHIFT);
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pFCSPI->FIFO_WTM = u32Flag;
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}
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/**
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* @brief Get FCSPI RX FIFO count.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return the real count value of rx fifo.
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*/
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LOCAL_INLINE uint8_t FCSPI_HWA_GetRxFifoStoredCount(FCSPI_Type *pFCSPI)
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{
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return (uint8_t)(((pFCSPI->FIFO_STATUS) & FCSPI_FIFO_STATUS_RXCNT_MASK) >> FCSPI_FIFO_STATUS_RXCNT_SHIFT);
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}
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/**
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* @brief Get FCSPI TX FIFO count value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return the real count of tx fifo.
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*/
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LOCAL_INLINE uint8_t FCSPI_HWA_GetTxFifoStoredCount(FCSPI_Type *pFCSPI)
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{
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return (uint8_t)(((pFCSPI->FIFO_STATUS) & FCSPI_FIFO_STATUS_TXCNT_MASK) >> FCSPI_FIFO_STATUS_TXCNT_SHIFT);
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}
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/**
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* @brief Get FCSPI TR_CTRL register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return FCSPI TR_CTRL regsiter value
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_GetTxRxControl(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->TR_CTRL;
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}
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/**
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* @brief Set FCSPI TR_CTRL register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param u32Value the value write to the register.
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*/
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LOCAL_INLINE void FCSPI_HWA_SetTxRxControl(FCSPI_Type *pFCSPI, uint32_t u32Value)
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{
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pFCSPI->TR_CTRL = u32Value;
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}
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/**
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* @brief Set RX enable status in register FCSPI TR_CTRL.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param eEnable FCSPI_TRUE for enabled, FCSPI_FALSE for disable.
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*/
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LOCAL_INLINE void FCSPI_HWA_EnableRxDataMask(FCSPI_Type *pFCSPI, FCSPI_AtomicBoolType eEnable)
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{
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if (FCSPI_FALSE == eEnable)
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{
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pFCSPI->TR_CTRL |= FCSPI_TR_CTRL_RX_MSK_MASK;
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}
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else
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{
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pFCSPI->TR_CTRL &= (~(FCSPI_TR_CTRL_RX_MSK_MASK));
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}
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}
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/**
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* @brief Set TX enable status in register FCSPI TR_CTRL.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param eEnable FCSPI_TRUE for enabled, FCSPI_FALSE for disable.
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*/
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LOCAL_INLINE void FCSPI_HWA_EnableTxDataMask(FCSPI_Type *pFCSPI, FCSPI_AtomicBoolType eEnable)
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{
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if (FCSPI_FALSE == eEnable)
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{
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pFCSPI->TR_CTRL |= FCSPI_TR_CTRL_TX_MSK_MASK;
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}
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else
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{
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pFCSPI->TR_CTRL &= (~(FCSPI_TR_CTRL_TX_MSK_MASK));
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}
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}
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/**
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* @brief Set FCSPI TX_DATA register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @param u32Value the value write to the register.
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*/
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LOCAL_INLINE void FCSPI_HWA_WriteData(FCSPI_Type *pFCSPI, uint32_t u32Value)
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{
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pFCSPI->TX_DATA = u32Value;
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}
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/**
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* @brief Get the address of FCSPI TX_DATA register,return value is the pointer address of TX_DATA.
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*
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* @param pFCSPI FCSPI instance，e.g. FCSPI0, FCSPI1.
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* @return FCSPI TX_DATA address.
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*/
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LOCAL_INLINE uint32_t volatile *FCSPI_HWA_GetTxDataAddr(FCSPI_Type *pFCSPI)
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{
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return (uint32_t volatile *)&(pFCSPI->TX_DATA);
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}
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/**
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* @brief Read FCSPI RX_STATUS register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return FCSPI RX_STATUS regsiter value
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_GetRxStatus(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->RX_STATUS;
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}
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/**
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* @brief Read FCSPI RX_DATA register value.
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*
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* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
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* @return FCSPI RX_DATA regsiter value
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*/
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LOCAL_INLINE uint32_t FCSPI_HWA_ReadData(FCSPI_Type *pFCSPI)
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{
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return pFCSPI->RX_DATA;
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}
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/**
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* @brief Get the address of FCSPI RX_DATA register,return value is the pointer address of RX_DATA.
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*
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* @param pFCSPI FCSPI instance，e.g. FCSPI0, FCSPI1.
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* @return FCSPI RX_DATA address.
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*/
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LOCAL_INLINE uint32_t volatile const *FCSPI_HWA_GetRxDataAddr(FCSPI_Type *pFCSPI)
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{
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return &(pFCSPI->RX_DATA);
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}
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#endif /* #ifndef _HWA_FCPIT_H_ */
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