120 lines
3.5 KiB
C
120 lines
3.5 KiB
C
/**
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* @file HwA_erm.h
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* @author Flagchip
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* @brief FC7xxx erm driver type definition and API
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* @version 0.1.0
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* @date 2024-01-14
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*
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* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2024-01-14 qxw0100 N/A FC7240 Erm first version
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******************************************************************************** */
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#ifndef HWA_INCLUDE_HWA_ERM_H_
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#define HWA_INCLUDE_HWA_ERM_H_
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#include "device_header.h"
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#define ERM_SR_MASK 0xCCCCCCCCu
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/**
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* @defgroup HwA_erm
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* @ingroup HwA_erm
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* @{
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*/
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/** @brief ERM configuration type */
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typedef enum
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{
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ERM_NONE_CORRECTABLE = 1U, /*!< select Non-correctable interrupt report */
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ERM_SINGLE_BIT = 2U /*!< select single correction interrupt report */
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} ERM_InterruptType;
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/** @brief ERM configuration type */
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typedef enum
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{
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ERM_PFLASH0_ECC = 1U, /*!< PFlash0 ECC Error */
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ERM_PFLASH1_ECC = 2U, /*!< PFlash1 ECC Error */
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ERM_DFLASH_ECC = 3U, /*!< DFlash ECC error */
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ERM_DMACFG0_ECC = 4U, /*!< DMACFG0 ECC Error */
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ERM_ROM_ECC = 6U, /*!< ROM ECC Error */
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ERM_SYSRAM0_ECC = 8U, /*!< SysRAM0 ECC ERROR */
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ERM_SYSRAM1_ECC = 9U, /*!< SysRAM1 ECC ERROR */
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ERM_CPU0ITCM_ECC = 11U, /*!< CPU0 ITCM ECC Error */
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ERM_CPU0DTCM0_ECC = 12U, /*!< CPU0 DTCM0 ECC Error */
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ERM_CPU0DTCM1_ECC = 13U, /*!< CPU0 DTCM1 ECC Error */
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ERM_CPU0ICACHE_ECC = 14U, /*!< CPU0 ICACHE ECC Error */
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ERM_CPU0DCACHE_ECC = 15U, /*!< CPU0 DCACHE ECC Error */
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ERM_HSMDRAM_ECC = 26U, /*!< HSM DRAM ECC Error */
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ERM_HSMIRAM_ECC = 27U, /*!< HSM IRAM ECC Error */
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} ERM_ChannelType;
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/**
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* @brief get ERM configuration register 0~3
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*
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* @return ERM CRn value
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*/
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LOCAL_INLINE uint32_t ERM_HWA_Get_CRn(uint8_t idx)
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{
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uint32_t u32RegValue;
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u32RegValue = *((volatile uint32_t *)(&(ERM->CR0) + (uint32_t)idx));
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return u32RegValue;
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}
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/**
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* @brief get ERM status register 0~3
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*
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* @return ERM SRn value
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*/
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LOCAL_INLINE uint32_t ERM_HWA_Get_SRn(uint8_t idx)
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{
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uint32_t u32RegValue;
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u32RegValue = *((volatile uint32_t *)(&(ERM->SR0) + (uint32_t)idx));
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return u32RegValue;
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}
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/**
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* @brief get ERM error address register 0~25
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*
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* @return ERM error address register value
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*/
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LOCAL_INLINE uint32_t ERM_HWA_Get_EARn(uint8_t idx)
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{
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uint32_t u32RegValue;
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u32RegValue = *((const volatile uint32_t *)(&(ERM->EAR0) + (uint32_t)idx * 0x10UL/4UL));
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return u32RegValue;
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}
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/**
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* @brief set erm configuration register
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*
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* @param idx index (0~3)
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* @param u32RegValue access control value
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*/
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LOCAL_INLINE void ERM_HWA_Set_CRn(uint8_t idx, uint32_t u32RegValue)
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{
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*((volatile uint32_t *)(&(ERM->CR0) + (int32_t)idx)) = u32RegValue;
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}
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/**
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* @brief set erm error address register
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*
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* @param idx index (0~3)
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* @param u32RegValue access control value
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*/
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LOCAL_INLINE void ERM_HWA_Set_SRn(uint8_t idx, uint32_t u32RegValue)
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{
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*((volatile uint32_t *)(&(ERM->SR0) + (int32_t)idx)) = u32RegValue;
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}
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/** @}*/
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#endif /* HWA_INCLUDE_HWA_ERM_H_ */
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