321 lines
8.5 KiB
C
321 lines
8.5 KiB
C
/**
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* @file HwA_mpu.h
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* @author Flagchip085
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* @brief FC7xxx MPU hardware access layer
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* @version 0.1.0
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* @date 2024-01-12
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*
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* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
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******************************************************************************** */
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#ifndef _HWA_MPU_H_
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#define _HWA_MPU_H_
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#include "device_header.h"
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/**
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* @brief The MPU registers struct
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*
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*/
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typedef struct {
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__I uint32_t MPU_TYPE; /* TYPE, offset: 0x0 */
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__IO uint32_t MPU_CTRL; /* CTRL, offset: 0x4 */
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__IO uint32_t MPU_RNR; /* RNR, offset: 0x8 */
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__IO uint32_t MPU_RBAR; /* RBAR, offset: 0xC */
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__IO uint32_t MPU_RASR; /* RASR, offset: 0x10 */
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} CORTEX_MPU_Type, *PCORTEX_MPU_Type;
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/** mpu base Address */
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#define CORTEX_MPU_BASE (0xE000ED90U)
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#define CORTEX_MPU ((CORTEX_MPU_Type *)CORTEX_MPU_BASE)
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/** TYPE Bit Fields **/
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#define CORTEX_MPU_TYPE_IREGION_MASK 0xFF0000U
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#define CORTEX_MPU_TYPE_IREGION_SHIFT 16U
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#define CORTEX_MPU_TYPE_IREGION_WIDTH 8U
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#define CORTEX_MPU_TYPE_IREGION(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_TYPE_IREGION_SHIFT))&CORTEX_MPU_TYPE_IREGION_MASK)
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#define CORTEX_MPU_TYPE_DREGION_MASK 0xFF00U
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#define CORTEX_MPU_TYPE_DREGION_SHIFT 8U
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#define CORTEX_MPU_TYPE_DREGION_WIDTH 8U
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#define CORTEX_MPU_TYPE_DREGION(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_TYPE_DREGION_SHIFT))&CORTEX_MPU_TYPE_DREGION_MASK)
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#define CORTEX_MPU_TYPE_SEPARATE_MASK 0x1U
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#define CORTEX_MPU_TYPE_SEPARATE_SHIFT 0U
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#define CORTEX_MPU_TYPE_SEPARATE_WIDTH 1U
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#define CORTEX_MPU_TYPE_SEPARATE(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_TYPE_SEPARATE_SHIFT))&CORTEX_MPU_TYPE_SEPARATE_MASK)
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/** TYPE Reg Mask **/
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#define CORTEX_MPU_TYPE 0x00FFFF01U
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/** CTRL Bit Fields **/
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#define CORTEX_MPU_CTRL_RPRIVDEFENA_MASK 0x4U
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#define CORTEX_MPU_CTRL_RPRIVDEFENA_SHIFT 2U
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#define CORTEX_MPU_CTRL_RPRIVDEFENA_WIDTH 1U
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#define CORTEX_MPU_CTRL_RPRIVDEFENA(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_CTRL_RPRIVDEFENA_SHIFT))&CORTEX_MPU_CTRL_RPRIVDEFENA_MASK)
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#define CORTEX_MPU_CTRL_HFNMIENA_MASK 0x2U
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#define CORTEX_MPU_CTRL_HFNMIENA_SHIFT 1U
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#define CORTEX_MPU_CTRL_HFNMIENA_WIDTH 1U
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#define CORTEX_MPU_CTRL_HFNMIENA(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_CTRL_HFNMIENA_SHIFT))&CORTEX_MPU_CTRL_HFNMIENA_MASK)
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#define CORTEX_MPU_CTRL_ENABLE_MASK 0x1U
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#define CORTEX_MPU_CTRL_ENABLE_SHIFT 0U
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#define CORTEX_MPU_CTRL_ENABLE_WIDTH 1U
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#define CORTEX_MPU_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_CTRL_ENABLE_SHIFT))&CORTEX_MPU_CTRL_ENABLE_MASK)
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/** CTRL Reg Mask **/
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#define CORTEX_MPU_CTRL 0x00000007U
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/** RNR Bit Fields **/
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#define CORTEX_MPU_RNR_REGION_MASK 0xFFu
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#define CORTEX_MPU_RNR_REGION_SHIFT 0U
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#define CORTEX_MPU_RNR_REGION_WIDTH 8U
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#define CORTEX_MPU_RNR_REGION(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RNR_REGION_SHIFT))&CORTEX_MPU_RNR_REGION_MASK)
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/** MPU_RNR Reg Mask **/
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#define CORTEX_MPU_RNR 0x000000FFu
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/** RBAR Bit Fields **/
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#define CORTEX_MPU_RBAR_ADDR_MASK 0xFFFFFFE0U
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#define CORTEX_MPU_RBAR_ADDR_SHIFT 5U
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#define CORTEX_MPU_RBAR_ADDR_WIDTH 27U
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#define CORTEX_MPU_RBAR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RBAR_ADDR_SHIFT))&CORTEX_MPU_RBAR_ADDR_MASK)
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#define CORTEX_MPU_RBAR_VALID_MASK 0x10U
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#define CORTEX_MPU_RBAR_VALID_SHIFT 4U
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#define CORTEX_MPU_RBAR_VALID_WIDTH 1U
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#define CORTEX_MPU_RBAR_VALID(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RBAR_VALID_SHIFT))&CORTEX_MPU_RBAR_VALID_MASK)
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#define CORTEX_MPU_RBAR_REGION_MASK 0xFu
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#define CORTEX_MPU_RBAR_REGION_SHIFT 0U
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#define CORTEX_MPU_RBAR_REGION_WIDTH 4U
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#define CORTEX_MPU_RBAR_REGION(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RBAR_REGION_SHIFT))&CORTEX_MPU_RBAR_REGION_MASK)
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/** RBAR Reg Mask **/
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#define CORTEX_MPU_RBAR 0xFFFFFFFFu
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/** RASR Bit Fields **/
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#define CORTEX_MPU_RASR_ATTRS_MASK 0xFFFF0000U
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#define CORTEX_MPU_RASR_ATTRS_SHIFT 16U
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#define CORTEX_MPU_RASR_ATTRS_WIDTH 16U
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#define CORTEX_MPU_RASR_ATTRS(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_ATTRS_SHIFT))&CORTEX_MPU_RASR_ATTRS_MASK)
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#define CORTEX_MPU_RASR_XN_MASK 0x10000000U
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#define CORTEX_MPU_RASR_XN_SHIFT 28U
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#define CORTEX_MPU_RASR_XN_WIDTH 1U
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#define CORTEX_MPU_RASR_XN(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_XN_SHIFT))&CORTEX_MPU_RASR_XN_MASK)
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#define CORTEX_MPU_RASR_AP_MASK 0x7000000U
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#define CORTEX_MPU_RASR_AP_SHIFT 24U
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#define CORTEX_MPU_RASR_AP_WIDTH 3U
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#define CORTEX_MPU_RASR_AP(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_AP_SHIFT))&CORTEX_MPU_RASR_AP_MASK)
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#define CORTEX_MPU_RASR_TEX_MASK 0x380000U
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#define CORTEX_MPU_RASR_TEX_SHIFT 19U
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#define CORTEX_MPU_RASR_TEX_WIDTH 3U
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#define CORTEX_MPU_RASR_TEX(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_TEX_SHIFT))&CORTEX_MPU_RASR_TEX_MASK)
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#define CORTEX_MPU_RASR_S_MASK 0x40000U
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#define CORTEX_MPU_RASR_S_SHIFT 18U
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#define CORTEX_MPU_RASR_S_WIDTH 1U
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#define CORTEX_MPU_RASR_S(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_S_SHIFT))&CORTEX_MPU_RASR_S_MASK)
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#define CORTEX_MPU_RASR_C_MASK 0x20000U
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#define CORTEX_MPU_RASR_C_SHIFT 17U
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#define CORTEX_MPU_RASR_C_WIDTH 1U
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#define CORTEX_MPU_RASR_C(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_C_SHIFT))&CORTEX_MPU_RASR_C_MASK)
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#define CORTEX_MPU_RASR_B_MASK 0x10000U
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#define CORTEX_MPU_RASR_B_SHIFT 16U
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#define CORTEX_MPU_RASR_B_WIDTH 1U
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#define CORTEX_MPU_RASR_B(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_B_SHIFT))&CORTEX_MPU_RASR_B_MASK)
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#define CORTEX_MPU_RASR_SRD_MASK 0xFF00U
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#define CORTEX_MPU_RASR_SRD_SHIFT 8U
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#define CORTEX_MPU_RASR_SRD_WIDTH 8U
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#define CORTEX_MPU_RASR_SRD(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_SRD_SHIFT))&CORTEX_MPU_RASR_SRD_MASK)
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#define CORTEX_MPU_RASR_SIZE_MASK 0x3Eu
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#define CORTEX_MPU_RASR_SIZE_SHIFT 1U
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#define CORTEX_MPU_RASR_SIZE_WIDTH 5U
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#define CORTEX_MPU_RASR_SIZE(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_SIZE_SHIFT))&CORTEX_MPU_RASR_SIZE_MASK)
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#define CORTEX_MPU_RASR_ENABLE_MASK 0x1U
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#define CORTEX_MPU_RASR_ENABLE_SHIFT 0U
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#define CORTEX_MPU_RASR_ENABLE_WIDTH 1U
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#define CORTEX_MPU_RASR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<CORTEX_MPU_RASR_ENABLE_SHIFT))&CORTEX_MPU_RASR_ENABLE_MASK)
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/** RASR Reg Mask **/
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#define CORTEX_MPU_RASR 0xFFFFFF3Fu
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#define MPU_RBAR_BASEADDR_MASK_U32 (0xFFFFFFE0u)
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#define MPU_RBAR_VALID_REGION_MASK_U32 (0x1Fu)
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#define MPU_EN_MASK_U32 ((uint32_t)(CORTEX_MPU_CTRL_HFNMIENA_MASK | CORTEX_MPU_CTRL_RPRIVDEFENA_MASK))
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#define MPU_REGION_MASK_U32 ((uint32_t)0xFF)
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/**
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* @brief get mpu type register
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*
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* @return type value
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*/
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LOCAL_INLINE uint32_t MPU_HWA_Get_Type(void)
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{
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return CORTEX_MPU->MPU_TYPE;
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}
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/**
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* @brief disable fault exceptions
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*
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*
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*/
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LOCAL_INLINE void MPU_HWA_Fault_Disable(void)
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{
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SCB->SHCSR &= ~((uint32_t)SCB_SHCSR_MEMFAULTENA_Msk);
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}
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/**
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* @brief enable fault exceptions
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*
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*
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*/
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LOCAL_INLINE void MPU_HWA_Fault_Enable(void)
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{
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SCB->SHCSR |= (uint32_t)SCB_SHCSR_MEMFAULTENA_Msk;
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}
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/**
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* @brief set mpu control register
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*
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* @param u32RegValue the value write to register
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* @return LOCAL_INLINE
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*/
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LOCAL_INLINE void MPU_HWA_Set_CR(uint32_t u32RegValue)
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{
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CORTEX_MPU->MPU_CTRL = u32RegValue;
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}
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/**
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* @brief set mpu number register
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*
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* @param u32RegValue the value write to register
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* @return LOCAL_INLINE
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*/
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LOCAL_INLINE void MPU_HWA_Set_NR(uint8_t u32RegValue)
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{
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CORTEX_MPU->MPU_RNR = (MPU_REGION_MASK_U32 & u32RegValue);
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}
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/**
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* @brief set mpu base address register
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*
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* @param u32RegValue the value write to register
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* @return LOCAL_INLINE
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*/
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LOCAL_INLINE void MPU_HWA_Set_BAR(uint32_t u32RegValue)
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{
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CORTEX_MPU->MPU_RBAR = u32RegValue;
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}
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/**
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* @brief set mpu attribute and size register
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*
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* @param u32RegValue the value write to registe
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* @return LOCAL_INLINE
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*/
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LOCAL_INLINE void MPU_HWA_Set_ASR(uint32_t u32RegValue)
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{
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CORTEX_MPU->MPU_RASR = u32RegValue;
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}
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#endif /* _HWA_MPU_H_ */
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