From c3279e5bc97bd73239bd97a62335632c7cea8d89 Mon Sep 17 00:00:00 2001 From: cfif Date: Tue, 23 Sep 2025 13:35:15 +0300 Subject: [PATCH] =?UTF-8?q?=D0=9D=D0=B0=D1=87=D0=B0=D0=BB=D0=BE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Inc/HwA_adc.h | 1537 ++++++++++++++++++++++++++++ Inc/HwA_aontimer.h | 299 ++++++ Inc/HwA_cm7.h | 39 + Inc/HwA_cmp.h | 947 ++++++++++++++++++ Inc/HwA_cmu.h | 271 +++++ Inc/HwA_cordic.h | 134 +++ Inc/HwA_cpm.h | 350 +++++++ Inc/HwA_crc.h | 313 ++++++ Inc/HwA_csc.h | 1705 +++++++++++++++++++++++++++++++ Inc/HwA_dma.h | 1514 ++++++++++++++++++++++++++++ Inc/HwA_dmamux.h | 210 ++++ Inc/HwA_eim.h | 276 +++++ Inc/HwA_erm.h | 119 +++ Inc/HwA_fciic.h | 542 ++++++++++ Inc/HwA_fcpit.h | 412 ++++++++ Inc/HwA_fcsmu.h | 671 +++++++++++++ Inc/HwA_fcspi.h | 478 +++++++++ Inc/HwA_fcuart.h | 830 +++++++++++++++ Inc/HwA_flexcan.h | 1001 +++++++++++++++++++ Inc/HwA_fmc.h | 402 ++++++++ Inc/HwA_fpu.h | 52 + Inc/HwA_freqm.h | 229 +++++ Inc/HwA_ftu.h | 1924 +++++++++++++++++++++++++++++++++++ Inc/HwA_gpio.h | 245 +++++ Inc/HwA_intm.h | 179 ++++ Inc/HwA_ism.h | 645 ++++++++++++ Inc/HwA_lu.h | 248 +++++ Inc/HwA_mam.h | 126 +++ Inc/HwA_mb.h | 408 ++++++++ Inc/HwA_mpu.h | 320 ++++++ Inc/HwA_msc.h | 841 ++++++++++++++++ Inc/HwA_overlay.h | 315 ++++++ Inc/HwA_pcc.h | 191 ++++ Inc/HwA_pmc.h | 92 ++ Inc/HwA_port.h | 2348 +++++++++++++++++++++++++++++++++++++++++++ Inc/HwA_ptimer.h | 701 +++++++++++++ Inc/HwA_rgm.h | 427 ++++++++ Inc/HwA_rtc.h | 276 +++++ Inc/HwA_scg.h | 917 +++++++++++++++++ Inc/HwA_scm.h | 2388 ++++++++++++++++++++++++++++++++++++++++++++ Inc/HwA_sec.h | 859 ++++++++++++++++ Inc/HwA_sent.h | 1454 +++++++++++++++++++++++++++ Inc/HwA_smc.h | 74 ++ Inc/HwA_stcu.h | 265 +++++ Inc/HwA_tmu.h | 548 ++++++++++ Inc/HwA_tpue.h | 2062 ++++++++++++++++++++++++++++++++++++++ Inc/HwA_tpuh.h | 902 +++++++++++++++++ Inc/HwA_trgsel.h | 150 +++ Inc/HwA_tstmp.h | 222 ++++ Inc/HwA_wdog.h | 115 +++ Inc/HwA_wku.h | 147 +++ modular.json | 7 + 52 files changed, 31727 insertions(+) create mode 100644 Inc/HwA_adc.h create mode 100644 Inc/HwA_aontimer.h create mode 100644 Inc/HwA_cm7.h create mode 100644 Inc/HwA_cmp.h create mode 100644 Inc/HwA_cmu.h create mode 100644 Inc/HwA_cordic.h create mode 100644 Inc/HwA_cpm.h create mode 100644 Inc/HwA_crc.h create mode 100644 Inc/HwA_csc.h create mode 100644 Inc/HwA_dma.h create mode 100644 Inc/HwA_dmamux.h create mode 100644 Inc/HwA_eim.h create mode 100644 Inc/HwA_erm.h create mode 100644 Inc/HwA_fciic.h create mode 100644 Inc/HwA_fcpit.h create mode 100644 Inc/HwA_fcsmu.h create mode 100644 Inc/HwA_fcspi.h create mode 100644 Inc/HwA_fcuart.h create mode 100644 Inc/HwA_flexcan.h create mode 100644 Inc/HwA_fmc.h create mode 100644 Inc/HwA_fpu.h create mode 100644 Inc/HwA_freqm.h create mode 100644 Inc/HwA_ftu.h create mode 100644 Inc/HwA_gpio.h create mode 100644 Inc/HwA_intm.h create mode 100644 Inc/HwA_ism.h create mode 100644 Inc/HwA_lu.h create mode 100644 Inc/HwA_mam.h create mode 100644 Inc/HwA_mb.h create mode 100644 Inc/HwA_mpu.h create mode 100644 Inc/HwA_msc.h create mode 100644 Inc/HwA_overlay.h create mode 100644 Inc/HwA_pcc.h create mode 100644 Inc/HwA_pmc.h create mode 100644 Inc/HwA_port.h create mode 100644 Inc/HwA_ptimer.h create mode 100644 Inc/HwA_rgm.h create mode 100644 Inc/HwA_rtc.h create mode 100644 Inc/HwA_scg.h create mode 100644 Inc/HwA_scm.h create mode 100644 Inc/HwA_sec.h create mode 100644 Inc/HwA_sent.h create mode 100644 Inc/HwA_smc.h create mode 100644 Inc/HwA_stcu.h create mode 100644 Inc/HwA_tmu.h create mode 100644 Inc/HwA_tpue.h create mode 100644 Inc/HwA_tpuh.h create mode 100644 Inc/HwA_trgsel.h create mode 100644 Inc/HwA_tstmp.h create mode 100644 Inc/HwA_wdog.h create mode 100644 Inc/HwA_wku.h create mode 100644 modular.json diff --git a/Inc/HwA_adc.h b/Inc/HwA_adc.h new file mode 100644 index 0000000..328e643 --- /dev/null +++ b/Inc/HwA_adc.h @@ -0,0 +1,1537 @@ +/** + * @file HwA_adc.h + * @author Flagchip0126 + * @brief Hardware access layer for ADC + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_ADC_H_ +#define _HWA_ADC_H_ + +#include "device_header.h" + +/** + * @defgroup HwA_adc + * @ingroup fc7xxx_driver_adc + * @{ + */ + +/** + * @brief Select the ADC Resolution + * + */ +typedef enum +{ + ADC_RESOLUTION_12_BIT = 0U, /*!< 12 bit resolution */ + ADC_RESOLUTION_10_BIT = 1U, /*!< 10 bit resolution */ + ADC_RESOLUTION_8_BIT = 2U /*!< 8 bit resolution */ +} ADC_ResolutionType; + +/** + * @brief Select the ADC result alignment + * + */ +typedef enum +{ + ADC_ALIGN_RIGHT = 0U, /*!< ADC result is aligned in right */ + ADC_ALIGN_LEFT = 1U /*!< ADC result is aligned in left */ +} ADC_AlignType; + +/** + * @brief Select the ADC trigger mode + * + * @note This option is only valid in ADC single sequence mode and ADC continuous mode. + * In ADC discontinuous mode, the ADC trigger mode is fixed as ADC_TRIGMODE_RISING_EDGE + * + */ +typedef enum +{ + ADC_TRIGMODE_SW = 0U, /*!< ADC is triggered by software */ + ADC_TRIGMODE_RISING_EDGE = 1U, /*!< ADC is triggered by hardware trigger on rising edge */ + ADC_TRIGMODE_FALLING_EDGE = 2U, /*!< ADC is triggered by hardware trigger on falling edge */ + ADC_TRIGMODE_BOTH_EDGE = 3U, /*!< ADC is triggered by hardware trigger on both edges */ + ADC_TRIGMODE_HIGH_VOLTAGE = 4U, /*!< ADC is triggered when hardware trigger is high voltage */ + ADC_TRIGMODE_LOW_VOLTAGE = 5U /*!< ADC is triggered when hardware trigger is low voltage */ +} ADC_TrigModeType; + +/** + * @brief Select the ADC sequence mode + * + */ +typedef enum +{ + ADC_SEQMODE_SINGLE = 0U, /*!< ADC single sequence mode */ + ADC_SEQMODE_CONTINUOUS = 1U, /*!< ADC continuous mode */ + ADC_SEQMODE_DISCONTINUOUS_0 = 2U, /*!< ADC discontinuous 0 mode */ + ADC_SEQMODE_DISCONTINUOUS_1 = 3U /*!< ADC discontinuous 1 mode */ +} ADC_SeqModeType; + +/** + * @brief Select the ADC overrun management mode + * + * To select whether the old data are preserved or overwritten by the new data when ADC + * is overrun (The FIFO is full when new convertion result comes) + * + */ +typedef enum +{ + ADC_OVERRUN_MODE_PRESERVE = 0U, /*!< old data are preserved when ADC is overrun */ + ADC_OVERRUN_MODE_OVERWRITE = 1U /*!< old data are overwritten when ADC is overrun */ +} ADC_OvrModeType; + +/** + * @brief Select the ADC voltage reference source + * + */ +typedef enum +{ + ADC_REF_INTERNAL = 0U, /*!< select the internal voltage reference */ + ADC_REF_EXTERNAL = 1U /*!< select the external voltage reference */ +} ADC_RefType; + +/** + * @brief Select the priority of Trigger Latch Unit + * + */ +typedef enum +{ + TRG_LATCH_UNIT_PRI_ROUND_ROBIN = 0U, /*!< select the round robin scheduling priority */ + TRG_LATCH_UNIT_PRI_FIX = 1U /*!< select the fixed priority(0>1>2>3) */ +} ADC_TrgLatchUnitPri; + +/** + * @brief Select the ADC hardware average samples + * + */ +typedef enum +{ + ADC_AVERAGE_4 = 0U, /*!< result average by 4 samples */ + ADC_AVERAGE_8 = 1U, /*!< result average by 8 samples */ + ADC_AVERAGE_16 = 2U, /*!< result average by 16 samples */ + ADC_AVERAGE_32 = 3U /*!< result average by 32 samples */ +} ADC_AverageType; + +/** + * @brief Set the ADC clock divider + * + * @note ADC clock divider is not available in FC4150F512K + * + */ +typedef enum +{ + ADC_CLOCK_DIV_1 = 0U, + ADC_CLOCK_DIV_2 = 1U, + ADC_CLOCK_DIV_4 = 2U, + ADC_CLOCK_DIV_8 = 3U +} ADC_ClockDivideType; + +/** + * @brief The trigger source of the ADC instance + * + * @note In ADC discontinuous 1 mode, the trigger source is from Ptimer + * In ADC single and continuous mode, if hardware trigger is enabled, the trigger + * source is from TRGSEL + * + */ +typedef enum +{ + ADC_TRIGSRC_PTIMER = 0U, /* Trigger source from PTIMER/TRGSEL with Ptimer */ + ADC_TRIGSRC_TRGSEL = 2U, /* Trigger source from TRGSEL */ + ADC_TRIGSRC_TRIG_LATCH_UNIT = 3U /* Trigger source from LATCH UNIT */ +} ADC_TrigSrcType; + +/** + * @brief Select the channel compare mode + * + * Select whether the channel compare is enabled on all channels or on the single + * selected channel + * + */ +typedef enum +{ + ADC_CMP_CHANNEL_ALL = 0U, /*!< Compare enabled in all channels */ + ADC_CMP_CHANNEL_SINGLE = 1U /*!< Compare enabled in the specified channel */ +} ADC_CmpChannelType; + +/** + * @brief Check whether the conversion result is in the comparing range + * + * @param pAdc the base address of the ADC instance + * @return true the conversion result is in the comparing range + * @return false the conversion result is not in the comparing range + */ +LOCAL_INLINE bool ADC_HWA_GetCompareFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_ACMP_MASK) >> ADC_INT_STATUS_ACMP_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the compare flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearCompareFlag(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_ACMP(1U); +} + +/** + * @brief Get the overrrun status of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return true the ADC is in overrun status + * @return false the ADC is not overrun + */ +LOCAL_INLINE bool ADC_HWA_GetOverRun(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_OVR_MASK) >> ADC_INT_STATUS_OVR_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the overrun flag of the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearOverRun(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_OVR(1U); +} + +/** + * @brief Check whether the ADC conversion sequence is finished + * + * @param pAdc the base address of the ADC instance + * @return true the ADC conversion sequence is finished + * @return false the ADC conversion sequence is unfinished + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSequence(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_EOSEQ_MASK) >> ADC_INT_STATUS_EOSEQ_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ADC conversion sequence complete flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearEndOfSequence(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_EOSEQ(1U); +} + +/** + * @brief Check whether the current ADC conversion is finished + * + * @param pAdc the base address of the ADC instance + * @return true the current ADC conversion is finished + * @return false the current ADC conversion is unfinished + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfConversion(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_EOC_MASK) >> ADC_INT_STATUS_EOC_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ADC single conversion complete flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearEndOfConversion(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_EOC(1U); +} + +/** + * @brief Check whether the sampling phase of the current ADC conversion is finished + * + * @param pAdc the base address of the ADC instance + * @return true the sampling phase of the ADC conversion is finished + * @return false the sampling phase of the ADC conversion is unfinished + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSample(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_EOSMP_MASK) >> ADC_INT_STATUS_EOSMP_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ADC sampling complete flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearEndOfSample(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_EOSMP(1U); +} + +/** + * @brief Check whether the data quantity in the FIFO is greater than watermark + * + * @param pAdc the base address of the ADC instance + * @return true the ADC FIFO is ready + * @return false the ADC FIFO is unready + */ +LOCAL_INLINE bool ADC_HWA_GetFIFOReady(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_FIFO_RDY_MASK) >> ADC_INT_STATUS_FIFO_RDY_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the FIFO ready flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearFIFOReady(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_FIFO_RDY(1U); +} + +/** + * @brief Check whether the ADC FIFO is full + * + * @param pAdc the base address of the ADC instance + * @return true the ADC FIFO is full + * @return false the ADC FIFO is not full + */ +LOCAL_INLINE bool ADC_HWA_GetFull(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_FULL_MASK) >> ADC_INT_STATUS_FULL_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the ADC FIFO is empty + * + * @param pAdc the base address of the ADC instance + * @return true the ADC FIFO is empty + * @return false the ADC FIFO is not empty + */ +LOCAL_INLINE bool ADC_HWA_GetEmpty(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_EMPTY_MASK) >> ADC_INT_STATUS_EMPTY_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the ADC instance is ready to operate + * + * @param pAdc the base address of the ADC instance + * @return true the ADC instance is ready for a new conversion + * @return false the ADC instance is unready + */ +LOCAL_INLINE bool ADC_HWA_GetReady(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_ADRDY_MASK) >> ADC_INT_STATUS_ADRDY_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ready flag of the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearReady(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_ADRDY(1U); +} + +/** + * @brief Get the FIFO Ready interrupt flag + * If enabled, ADC interrupt is generated when the FIFO water mark is greater than FWMARK + * @param pAdc the base address of the ADC instance + * @return true ADC FIFO Ready interrupt is enabled + * @return false ADC FIFO Ready interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetFIFOReadyInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_FIFO_RDY_IE_MASK) >> ADC_INT_ENABLE_FIFO_RDY_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the FIFO Ready interrupt flag + * If enabled, ADC interrupt is generated when the FIFO water mark is greater than FWMARK + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC FIFO Ready interrupt + */ +LOCAL_INLINE void ADC_HWA_SetFIFOReadyInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_FIFO_RDY_IE_MASK) | ADC_INT_ENABLE_FIFO_RDY_IE(bEnable); +} + +/** + * @brief Get the Compare interrupt flag + * If enabled, ADC interrupt is generated when the ADC conversion result is not within the compare threshold + * @param pAdc the base address of the ADC instance + * @return true ADC Compare interrupt is enabled + * @return false ADC Compare interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetCompareInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_ACMP_IE_MASK) >> ADC_INT_ENABLE_ACMP_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Compare interrupt flag + * If enabled, ADC interrupt is generated when the ADC conversion result is not within the compare threshold + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC Compare interrupt + */ +LOCAL_INLINE void ADC_HWA_SetCompareInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_ACMP_IE_MASK) | ADC_INT_ENABLE_ACMP_IE(bEnable); +} + +/** + * @brief Get the Overrun interrupt flag + * If enabled, ADC interrupt is generated when the ADC instance is overrun + * @param pAdc the base address of the ADC instance + * @return true ADC Overrun interrupt is enabled + * @return false ADC Overrun interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetOverrunInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_OVRIE_MASK) >> ADC_INT_ENABLE_OVRIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Overrun interrupt flag + * If enabled, ADC interrupt is generated when the ADC instance is overrun + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC Overrun interrupt + */ +LOCAL_INLINE void ADC_HWA_SetOverrunInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_OVRIE_MASK) | ADC_INT_ENABLE_OVRIE(bEnable); +} + +/** + * @brief Get the End of Sequence interrupt enable flag + * If enabled, ADC interrupt is generated when the ADC sequence conversion is completed + * @param pAdc the base address of the ADC instance + * @return true ADC End of Sequence interrupt is enabled + * @return false ADC End of Sequence interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSequenceInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_EOSEQIE_MASK) >> ADC_INT_ENABLE_EOSEQIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the End of Sequence interrupt enable flag + * If enabled, ADC interrupt is generated when the ADC sequence conversion is completed + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC End of Sequence interrupt + */ +LOCAL_INLINE void ADC_HWA_SetEndOfSequenceInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_EOSEQIE_MASK) | ADC_INT_ENABLE_EOSEQIE(bEnable); +} + +/** + * @brief Get the conversion complete interrupt enable flag + * If enabled, ADC interrupt is generated when each ADC conversion is completed + * @param pAdc the base address of the ADC instance + * @return true the ADC End of Conversion interrupt is enabled + * @return false the ADC End of Conversion interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWAGetEndOfConversionInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_EOCIE_MASK) >> ADC_INT_ENABLE_EOCIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the conversion complete interrupt enable flag + * If enabled, ADC interrupt is generated when each ADC conversion is completed + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the conversion complete interrupt + */ +LOCAL_INLINE void ADC_HWA_SetEndOfConversionInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_EOCIE_MASK) | ADC_INT_ENABLE_EOCIE(bEnable); +} + +/** + * @brief Get the sample complete interrupt enable flag + * If enabled, ADC interrupt is generated when each ADC conversion finished the sampling phase + * @param pAdc the base address of the ADC instance + * @return true the sample complete interrupt is enabled + * @return false the sample complete interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSampleInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_EOSMPIE_MASK) >> ADC_INT_ENABLE_EOSMPIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the sample complete interrupt enable flag + * If enabled, ADC interrupt is generated when each ADC conversion finished the sampling phase + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the sample complete interrupt + */ +LOCAL_INLINE void ADC_HWA_SetEndOfSampleInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_EOSMPIE_MASK) | ADC_INT_ENABLE_EOSMPIE(bEnable); +} + +/** + * @brief Get the ADC ready interrupt enable flag + * If enabled, ADC interrupt is generated when the ADC module is ready for conversion + * @param pAdc the base address of the ADC instance + * @return true the ADC ready interrupt is enabled + * @return false the ADC ready interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetADCReadyInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_ADRDYIE_MASK) >> ADC_INT_ENABLE_ADRDYIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the ADC ready interrupt enable flag + * If enabled, ADC interrupt is generated when the ADC module is ready for conversion + * @param pAdc the base address of the ADC instance + * @param bEnable Whether to enable the ADC ready interrupt + */ +LOCAL_INLINE void ADC_HWA_SetADCReadyInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_ADRDYIE_MASK) | ADC_INT_ENABLE_ADRDYIE(bEnable); +} + +/** + * @brief Get the interrupt enable config + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the interrupt enable config + */ +LOCAL_INLINE uint32_t ADC_HWA_GetInterruptEnable(const ADC_Type *const pAdc) +{ + return pAdc->INT_ENABLE; +} + +/** + * @brief Set the interrupt enable + * + * @param u32InterruptCfg the interrupt enable config + */ +LOCAL_INLINE void ADC_HWA_SetInterruptEnable(ADC_Type *const pAdc, uint32_t u32InterruptCfg) +{ + pAdc->INT_ENABLE = u32InterruptCfg; +} + +/** + * @brief Reset the ADC hardware + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Reset(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADRST(1U); + pAdc->CONTROL = 0U; +} + +/** + * @brief Get the enable status of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return true the ADC instance is enabled + * @return false the ADC instance has not been enabled + */ +LOCAL_INLINE bool ADC_HWA_GetEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CONTROL; + u32TmpVal = (u32TmpVal & ADC_CONTROL_ADEN_MASK) >> ADC_CONTROL_ADEN_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Enable(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADEN(1U); +} + +/** + * @brief Get whether the ADC instance is in disable status + * + * @param pAdc the base address of the ADC instance + * @return true the ADC instance is in disable status + * @return false the ADC instance is not in disable status + */ +LOCAL_INLINE bool ADC_HWA_GetDisable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CONTROL; + u32TmpVal = (u32TmpVal & ADC_CONTROL_ADDIS_MASK) >> ADC_CONTROL_ADDIS_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Disable the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Disable(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADDIS(1U); +} + +/** + * @brief Get the conversion start status of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return true the conversion of the ADC instance is started + * @return false the conversion of the ADC instance has not been started + */ +LOCAL_INLINE bool ADC_HWA_GetStart(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CONTROL; + u32TmpVal = (u32TmpVal & ADC_CONTROL_ADSTART_MASK) >> ADC_CONTROL_ADSTART_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Start the ADC conversion + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Start(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADSTART(1U); +} + +/** + * @brief Get whether ADC is in stopping status + * + * @param pAdc the base address of the ADC instance + * @return true the ADC instance is stopping + * @return false the ADC instance is not in stopping status + */ +LOCAL_INLINE bool ADC_HWA_GetStop(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CONTROL; + u32TmpVal = (u32TmpVal & ADC_CONTROL_ADSTP_MASK) >> ADC_CONTROL_ADSTP_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Stop the ADC conversion + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Stop(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADSTP(1U); +} + +/** + * @brief Get the overrun management mode + * + * @param pAdc the base address of the ADC instance + * @return ADC_OVERRUN_MODE_PRESERVE the conversion data is preserved when ADC is overrun + * @return ADC_OVERRUN_MODE_OVERWRITE the conversion data is overwritten when ADC is overrun + */ +LOCAL_INLINE ADC_OvrModeType ADC_HWA_GetOverrunManagementMode(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_OVRMOD_MASK) >> ADC_CFG1_OVRMOD_SHIFT; + return (ADC_OvrModeType)u32TmpVal; +} + +/** + * @brief Set the overrun management mode + * + * @param pAdc the base address of the ADC instance + * @param eOvrMode the overrun management for the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetOverrunManagementMode(ADC_Type *const pAdc, ADC_OvrModeType eOvrMode) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_OVRMOD_MASK) | ADC_CFG1_OVRMOD(eOvrMode); +} + +/** + * @brief Get the sequence group mode state + * + * @param pAdc the base address of the ADC instance + * @return the sequence group mode state + */ +LOCAL_INLINE bool ADC_HWA_GetSeqGpEn(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_SEQGP_EN_MASK) >> ADC_CFG1_SEQ_LEN_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the sequence group mode state + * + * @param pAdc the base address of the ADC instance + * @param the sequence group mode state + */ +LOCAL_INLINE void ADC_HWA_SetSeqGpEn(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_SEQGP_EN_MASK) | ADC_CFG1_SEQGP_EN(bEnable); +} + +/** + * @brief Get the sequence length of the ADC conversion sequence + * + * @param pAdc the base address of the ADC instance + * @return uint8_t the sequence length of the ADC conversion sequence + */ +LOCAL_INLINE uint8_t ADC_HWA_GetSequenceLength(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_SEQ_LEN_MASK) >> ADC_CFG1_SEQ_LEN_SHIFT; + + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the sequence length of the ADC conversion sequence + * + * @param pAdc the base address of the ADC instance + * @param u8SequenceLength the sequence length of the ADC conversion sequence + */ +LOCAL_INLINE void ADC_HWA_SetSequenceLength(ADC_Type *const pAdc, uint8_t u8SequenceLength) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_SEQ_LEN_MASK) | ADC_CFG1_SEQ_LEN(u8SequenceLength); +} + +/** + * @brief Get the ADC sequence mode + * + * @param pAdc the base address of the ADC instance + * @return ADC_SeqModeType the sequence mode the the ADC instance + */ +LOCAL_INLINE ADC_SeqModeType ADC_HWA_GetSequenceMode(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_SEQ_MOD_MASK) >> ADC_CFG1_SEQ_MOD_SHIFT; + + return (ADC_SeqModeType)u32TmpVal; +} + +/** + * @brief Set the ADC sequence mode + * + * @param pAdc the base address of the ADC instance + * @param eSequenceMode the sequence mode the the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetSequenceMode(ADC_Type *const pAdc, ADC_SeqModeType eSequenceMode) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_SEQ_MOD_MASK) | ADC_CFG1_SEQ_MOD(eSequenceMode); +} + +/** + * @brief Get whether auto disable is enabled + * + * @note Auto disable mode is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @return true auto disable mode is enabled + * @return false auto disable mode is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetAutoDisableModeEnableFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_AUTO_DIS_MASK) >> ADC_CFG1_AUTO_DIS_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable auto disable mode + * + * @note Auto disable mode is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable auto disable mode + */ +LOCAL_INLINE void ADC_HWA_SetAutoDisableModeEnableFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_AUTO_DIS_MASK) | ADC_CFG1_AUTO_DIS(bEnable); +} + +/** + * @brief Get whether the wait conversion mode is enabled + * + * @param pAdc the base address of the ADC instance + * @return true the wait conversion mode is enabled + * @return false the wait conversion mode is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetWaitConversionModeFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_WAIT_MASK) >> ADC_CFG1_WAIT_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the wait conversion mode + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the wait conversion mode + */ +LOCAL_INLINE void ADC_HWA_SetWaitConversionModeFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_WAIT_MASK) | ADC_CFG1_WAIT(bEnable); +} + +/** + * @brief Get the trigger source the the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return ADC_TrigSrcType the trigger source of the ADC instance + */ +LOCAL_INLINE ADC_TrigSrcType ADC_HWA_GetTriggerSource(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_TRIGSRC_MASK) >> ADC_CFG1_TRIGSRC_SHIFT; + + return (ADC_TrigSrcType)u32TmpVal; +} + +/** + * @brief Set the trigger source the the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param eTriggerSource the trigger source of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetTriggerSource(ADC_Type *const pAdc, ADC_TrigSrcType eTriggerSource) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_TRIGSRC_MASK) | ADC_CFG1_TRIGSRC(eTriggerSource); +} + +/** + * @brief Get the trigger mode of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return ADC_TrigModeType the trigger mode if the ADC instance + */ +LOCAL_INLINE ADC_TrigModeType ADC_HWA_GetTriggerMode(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_TRIGMODE_MASK) >> ADC_CFG1_TRIGMODE_SHIFT; + + return (ADC_TrigModeType)u32TmpVal; +} + +/** + * @brief Set the trigger mode of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param eTriggerMode the trigger mode if the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetTriggerMode(ADC_Type *const pAdc, ADC_TrigModeType eTriggerMode) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_TRIGMODE_MASK) | ADC_CFG1_TRIGMODE(eTriggerMode); +} + +/** + * @brief Get the data align mode + * + * @param pAdc the base address of the ADC instance + * @return ADC_ALIGN_RIGHT the conversion data is aligned right + * @return ADC_ALIGN_LEFT the conversion is aligned left + */ +LOCAL_INLINE ADC_AlignType ADC_HWA_GetDataAlignment(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_ALIGN_MASK) >> ADC_CFG1_ALIGN_SHIFT; + return (ADC_AlignType)u32TmpVal; +} + +/** + * @brief Set the data align mode + * + * @param pAdc the base address of the ADC instance + * @param eAlign the data align mode + */ +LOCAL_INLINE void ADC_HWA_SetDataAlignment(ADC_Type *const pAdc, ADC_AlignType eAlign) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_ALIGN_MASK) | ADC_CFG1_ALIGN(eAlign); +} + +/** + * @brief Get the ADC resolution of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return ADC_ResolutionType the resolution of the ADC instance + */ +LOCAL_INLINE ADC_ResolutionType ADC_HWA_GetDataResolution(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_RES_MASK) >> ADC_CFG1_RES_SHIFT; + return (ADC_ResolutionType)u32TmpVal; +} + +/** + * @brief Set the resolution of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param eResolution the resolution of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetDataResolution(ADC_Type *const pAdc, ADC_ResolutionType eResolution) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_RES_MASK) | ADC_CFG1_RES(eResolution); +} + +/** + * @brief Get whether DMA for the ADC instance is enabled + * + * @param pAdc the base address of the ADC instance + * @return true DMA is enabled for the ADC instance + * @return false DMA is disabled for the ADC instance + */ +LOCAL_INLINE bool ADC_HWA_GetDMAEnableFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_DMAEN_MASK) >> ADC_CFG1_DMAEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable or disable the DMA for the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the DMA for the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetDMAEnableFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_DMAEN_MASK) | ADC_CFG1_DMAEN(bEnable); +} + +/** + * @brief Get the ADC_CFG1 config + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the ADC_CFG1 config + */ +LOCAL_INLINE uint32_t ADC_HWA_GetConfig1(const ADC_Type *const pAdc) +{ + return pAdc->CFG1; +} + +/** + * @brief Set the ADC_CFG1 config + * + * @param pAdc the base address of the ADC instance + * @param u32Config the ADC_CFG1 config + */ +LOCAL_INLINE void ADC_HWA_SetConfig1(ADC_Type *const pAdc, uint32_t u32Config) +{ + pAdc->CFG1 = u32Config; +} + +/** + * @brief Get the FIFO water mark settings for the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return uint8_t the ADC FIFO water mark setting + */ +LOCAL_INLINE uint8_t ADC_HWA_GetFIFOWaterMark(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_FWMARK_MASK) >> ADC_CFG2_FWMARK_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the FIFO water mark for the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param u8WaterMark the ADC FIFO water mark setting + */ +LOCAL_INLINE void ADC_HWA_SetFIFOWaterMark(ADC_Type *const pAdc, uint8_t u8WaterMark) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_FWMARK_MASK) | ADC_CFG2_FWMARK(u8WaterMark); +} + +/** + * @brief Get the priority of Trigger Latch + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE uint8_t ADC_HWA_GetTriggerLatchUnitPriority(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_TRG_PRI_MASK) >> ADC_CFG2_TRG_PRI_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the priority of Trigger Latch + * + * @param pAdc the base address of the ADC instance + * @param eTrgLatchUnitPri the priority of Trigger Latch Unit setting + */ +LOCAL_INLINE void ADC_HWA_SetTriggerLatchUnitPriority(ADC_Type *const pAdc, ADC_TrgLatchUnitPri eTrgLatchUnitPri) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_TRG_CLR_MASK) | ADC_CFG2_TRG_CLR(eTrgLatchUnitPri); +} + +/** + * @brief Clear Latch Trigger in Trigger Latch Unit + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearLatchTrigger(ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG2; + pAdc->CFG2 = u32TmpVal | ADC_CFG2_TRG_CLR(1); +} + +/** + * @brief Get whether hardware average is enabled + * + * @param pAdc the base address of the ADC instance + * @return true hardware average is enabled + * @return false hardware average is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetAverageEnableFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_AVG_EN_MASK) >> ADC_CFG2_AVG_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable or disable hardware average for the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC hardware average + */ +LOCAL_INLINE void ADC_HWA_SetAverageEnableFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_AVG_EN_MASK) | ADC_CFG2_AVG_EN(bEnable); +} + +/** + * @brief Get the hardware average number + * + * @param pAdc the base address of the ADC instance + * @return ADC_AverageType the hardware average number + */ +LOCAL_INLINE ADC_AverageType ADC_HWA_GetAverageNumber(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_AVG_LEN_MASK) >> ADC_CFG2_AVG_LEN_SHIFT; + return (ADC_AverageType)u32TmpVal; +} + +/** + * @brief Set the hardware average number + * + * @param pAdc the base address of the ADC instance + * @param eAverageNumber the hardware average number to set + */ +LOCAL_INLINE void ADC_HWA_SetAverageNumber(ADC_Type *const pAdc, ADC_AverageType eAverageNumber) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_AVG_LEN_MASK) | ADC_CFG2_AVG_LEN(eAverageNumber); +} +/** + * @brief Whether clock gating is acknowledged + * + * @note This feature is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @return true ADC clock source is off after setting Clock Gating Enable Flag + * @return false ADC clock source is on after clearing Clock Gating Enable Flag + */ +LOCAL_INLINE bool ADC_HWA_GetClockGatingAck(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_CG_ACK_MASK) >> ADC_CFG2_CG_ACK_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether clock gating is enabled + * + * @note This feature is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @return true Clock gating is enabled, ADC clock is off + * @return false Clock gating is disabled, ADC clock is on + */ +LOCAL_INLINE bool ADC_HWA_GetClockGatingEnableFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_CG_MASK) >> ADC_CFG2_CG_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable ADC clock gating + * + * @note This feature is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable ADC clock gating + */ +LOCAL_INLINE void ADC_HWA_SetClockGatingEnableFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_CG_MASK) | ADC_CFG2_CG(bEnable); +} + +/** + * @brief Get the voltage reference of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return ADC_REF_INTERNAL the ADC instance uses internal voltage reference + * @return ADC_REF_EXTERNAL the ADC instance uses external voltage reference + */ +LOCAL_INLINE ADC_RefType ADC_HWA_GetVoltageReference(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_REF_EXT_MASK) >> ADC_CFG2_REF_EXT_SHIFT; + return (ADC_RefType)u32TmpVal; +} + +/** + * @brief Set the voltage reference of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param eRefSel the voltage reference of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetVoltageReference(ADC_Type *const pAdc, ADC_RefType eRefSel) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_REF_EXT_MASK) | ADC_CFG2_REF_EXT(eRefSel); +} + +/** + * @brief Get the ADC clock divider + * + * @note This feature is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @return ADC_ClockDivideType the ADC clock divider + */ +LOCAL_INLINE ADC_ClockDivideType ADC_HWA_GetClockDivider(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_DIV_MASK) >> ADC_CFG2_DIV_SHIFT; + return (ADC_ClockDivideType)u32TmpVal; +} + +/** + * @brief Set the ADC clock divider + * + * @note Before configuring DIV, must set CG and wait for CG_ACK=1. + * After configuring DIV, must clear CG and wait for CG_ACK=0. + * @note This feature is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @param eDivider the ADC clock divider to set + */ +LOCAL_INLINE void ADC_HWA_SetClockDivider(ADC_Type *const pAdc, ADC_ClockDivideType eDivider) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_DIV_MASK) | ADC_CFG2_DIV(eDivider); +} + +/** + * @brief Get the ADC start up count + * + * @param pAdc the base address of the ADC instance + * @return uint8_t the start count of the ADC instance + */ +LOCAL_INLINE uint8_t ADC_HWA_GetStartupCnt(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_STCNT_MASK) >> ADC_CFG2_STCNT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the ADC start up count + * + * @param pAdc the base address of the ADC instance + * @param u8StartupCnt the start count of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetStartupCnt(ADC_Type *const pAdc, uint8_t u8StartupCnt) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_STCNT_MASK) | ADC_CFG2_STCNT(u8StartupCnt); +} + +/** + * @brief Get the ADC_CFG2 config + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the ADC_CFG2 config + */ +LOCAL_INLINE uint32_t ADC_HWA_GetConfig2(const ADC_Type *const pAdc) +{ + return pAdc->CFG2; +} + +/** + * @brief Set the ADC_CFG2 config + * + * @param pAdc the base address of the ADC instance + * @param u32Config the ADC_CFG2 config + */ +LOCAL_INLINE void ADC_HWA_SetConfig2(ADC_Type *const pAdc, uint32_t u32Config) +{ + pAdc->CFG2 = u32Config; +} + +/** + * @brief Set the ADC_CAL config + * + * @param pAdc the base address of the ADC instance + * @param u32Cal the ADC_CAL config + */ +LOCAL_INLINE void ADC_HWA_SetCal(ADC_Type *const pAdc, uint32_t u32Cal) +{ + pAdc->CAL = u32Cal; +} + +/** + * @brief Get the sample time of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param u8Selection the sample time index, range 0~3 + * @return uint8_t the sample time of the selected index + */ +LOCAL_INLINE uint8_t ADC_HWA_GetSampleTime(ADC_Type *const pAdc, uint8_t u8Selection) +{ + uint32_t ret; + ret = (pAdc->SMPR & (ADC_SMPR_SMP_OPT0_MASK << (8U * u8Selection))) >> (8U * u8Selection); + return (uint8_t)ret; +} + +/** + * @brief Set the sample time of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param u8Selection the sample time index, range 0~3 + * @param u8SampleTime the sample time of the selected index + */ +LOCAL_INLINE void ADC_HWA_SetSampleTime(ADC_Type *const pAdc, uint8_t u8Selection, uint8_t u8SampleTime) +{ + DEV_ASSERT(u8Selection < ADC_SAMPLE_TIME_OPTION_CNT); + pAdc->SMPR = (pAdc->SMPR & ~(ADC_SMPR_SMP_OPT0_MASK << (8U * u8Selection))) | + (ADC_SMPR_SMP_OPT0(u8SampleTime) << (8U * u8Selection)); +} + +/** + * @brief Set the ADC hardware compare channel + * + * @param pAdc the base address of the ADC instance + * @param eChannelType whether the hardware compare enabled on single channel or all channels + * @param u8ChannalNum if hardware compare is enabled on single channel, this specifies the channel number + */ +LOCAL_INLINE void ADC_HWA_SetHwCompareChannel(ADC_Type *const pAdc, ADC_CmpChannelType eChannelType, + uint8_t u8ChannalNum) +{ + pAdc->CMP_CTRL = (pAdc->CMP_CTRL & (~ADC_CMP_CTRL_ACMPSGL_MASK) & (~ADC_CMP_CTRL_ACMPCH_MASK)) | + ADC_CMP_CTRL_ACMPSGL(eChannelType) | ADC_CMP_CTRL_ACMPCH(u8ChannalNum); +} + +/** + * @brief Get whether hardware compare is enabled + * + * @param pAdc the base address of the ADC instance + * @return true hardware compare is enabled + * @return false hardware compare is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetHwCompareEnableFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CMP_CTRL & ADC_CMP_CTRL_ACMPEN_MASK) >> ADC_CMP_CTRL_ACMPEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set to enable or disable the hardware compare + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether the ADC hardware compare is enabled + */ +LOCAL_INLINE void ADC_HWA_SetHwCompareEnableFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CMP_CTRL = (pAdc->CMP_CTRL & ~ADC_CMP_CTRL_ACMPEN_MASK) | ADC_CMP_CTRL_ACMPEN(bEnable); +} + +/** + * @brief Set the ADC hardware compare threshold + * + * @param pAdc the base address of the ADC instance + * @param u16LowThres the lower threshold + * @param u16HighThres the higher threshold + */ +LOCAL_INLINE void ADC_HWA_SetHwCompareThreshold(ADC_Type *const pAdc, uint16_t u16LowThres, uint16_t u16HighThres) +{ + pAdc->CMP_TR = ADC_CMP_TR_LT(u16LowThres) | ADC_CMP_TR_HT(u16HighThres); +} + +/** + * @brief Get the end of sequence group flag + * + * @param pAdc the base address of the ADC instance + * @param u8SeqGroupIndex the index of the sequence group + * @param bool the sequence group interrupt flag + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSequenceGroupInterruptFlag(ADC_Type *const pAdc, const uint8_t u8SeqGroupIndex) +{ + uint32_t u32TmpVal = (pAdc->SGCSR[u8SeqGroupIndex] & ADC_SGCSR_EOSG_MASK) >> ADC_SGCSR_EOSG_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Clear the end of sequence group flag + * + * @param pAdc the base address of the ADC instance + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE void ADC_HWA_ClearEndOfSequenceGroupInterruptFlag(ADC_Type *const pAdc, const uint8_t u8SeqGroupIndex) +{ + uint32_t u32TmpVal = pAdc->SGCSR[u8SeqGroupIndex]; + pAdc->SGCSR[u8SeqGroupIndex] = (u32TmpVal & ~ADC_SGCSR_EOSG_MASK) | ADC_SGCSR_EOSG(1U); +} + +/** + * @brief Set the sequence group end of sequence interrupt enable + * + * @param pAdc the base address of the ADC instance + * @param u8SeqGroupIndex the index of the sequence group + * @param bEnable the sequence group interrupt enable or disable + */ +LOCAL_INLINE void ADC_HWA_SetEndOfSequenceGroupInterruptEnable(ADC_Type *const pAdc, const uint8_t u8SeqGroupIndex, const bool bEnable) +{ + uint32_t u32TmpVal = pAdc->SGCSR[u8SeqGroupIndex]; + pAdc->SGCSR[u8SeqGroupIndex] = (u32TmpVal & ~ADC_SGCSR_EOSGIE_MASK) | ADC_SGCSR_EOSGIE(bEnable); +} + +/** + * @brief Get the sequence group start point + * + * @param pAdc the base address of the ADC instance + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE uint32_t ADC_HWA_GetSeqGroupStartPoint(ADC_Type *const pAdc, const uint8_t u8SeqGroupIndex) +{ + return (pAdc->SGCSR[u8SeqGroupIndex] & ~ADC_SGCSR_SG_START_MASK) >> ADC_SGCSR_SG_START_SHIFT; +} + +/** + * @brief Get the sequence group end point + * + * @param pAdc the base address of the ADC instance + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE uint32_t ADC_HWA_GetSeqGroupEndPoint(ADC_Type *const pAdc, const uint8_t u8SeqGroupIndex) +{ + return (pAdc->SGCSR[u8SeqGroupIndex] & ~ADC_SGCSR_SG_END_MASK) >> ADC_SGCSR_SG_END_SHIFT; +} + +/** + * @brief Set the sequence group start point & end point + * + * @param pAdc the base address of the ADC instance + * @param u8SeqGroupIndex the index of the sequence group + * @param u8Start the sequence group start point + * @param u8End the sequence group end point + */ +LOCAL_INLINE void ADC_HWA_SetSeqGroupStartEndPoint(ADC_Type *const pAdc, const uint8_t u8SeqGroupIndex, const uint8_t u8Start, const uint8_t u8End) +{ + uint32_t u32TmpVal = pAdc->SGCSR[u8SeqGroupIndex]; + u32TmpVal = (u32TmpVal & ~ADC_SGCSR_SG_END_MASK) | ADC_SGCSR_SG_END(u8End); + u32TmpVal = (u32TmpVal & ~ADC_SGCSR_SG_START_MASK) | ADC_SGCSR_SG_START(u8Start); + pAdc->SGCSR[u8SeqGroupIndex] = u32TmpVal; +} + +/** + * @brief Get the conversion result FIFO data of the ADC instance + * + * @note only reslut data of ADC single mode and continuous mode will be stored + * in FIFO register. + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the ADC conversion result + */ +LOCAL_INLINE uint32_t ADC_HWA_GetFIFOData(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->FIFO_DATA; + u32TmpVal = (u32TmpVal & ADC_FIFO_DATA_FIFO_DATA_MASK) >> ADC_FIFO_DATA_FIFO_DATA_SHIFT; + return (uint32_t)u32TmpVal; +} + +/** + * @brief Get the differential mode state of the ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return bool the state of diff mode for ADC channel + */ +LOCAL_INLINE bool ADC_HWA_GetChannelDiff(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = (pAdc->SC[u8ChnIdx] & ADC_SC_DIFF_MASK) >> ADC_SC_DIFF_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the differential mode state of the ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @param bEnable the state of diff mode for ADC channel + */ +LOCAL_INLINE void ADC_HWA_SetChannelDiff(ADC_Type *const pAdc, const uint8_t u8ChnIdx, const bool bEnable) +{ + pAdc->SC[u8ChnIdx] = (pAdc->SC[u8ChnIdx] & ~ADC_SC_DIFF_MASK) | ADC_SC_DIFF(bEnable); +} + +/** + * @brief Get the sample time index of the ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return uint8_t the sample time index of the ADC channel + */ +LOCAL_INLINE uint8_t ADC_HWA_GetChannelSampleTimeIndex(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = (pAdc->SC[u8ChnIdx] & ADC_SC_SMPSEL_MASK) >> ADC_SC_SMPSEL_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the sample time index of the ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @param u8SmpSel the sample time index of the ADC channel + */ +LOCAL_INLINE void ADC_HWA_SetChannelSampleTimeIndex(ADC_Type *const pAdc, const uint8_t u8ChnIdx, uint8_t u8SmpSel) +{ + pAdc->SC[u8ChnIdx] = (pAdc->SC[u8ChnIdx] & ~ADC_SC_SMPSEL_MASK) | ADC_SC_SMPSEL(u8SmpSel); +} + +/** + * @brief Get the channel conversion complete status of the ADC instance + * + * @note this function is used only in ADC discontinuous mode to get the channel complete + * status + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return true the ADC conversion on the selected channel is completed + * @return false the ADC conversion on the selected channel is not completed + */ +LOCAL_INLINE bool ADC_HWA_GetChannelConvertComplete(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pAdc->SC[u8ChnIdx]; + u32TmpVal = (u32TmpVal & ADC_SC_COCO_MASK) >> ADC_SC_COCO_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether interrupt is enabled on the selected ADC channel + * + * @note this function is used only in ADC discontinuous mode to get the channel interrupt + * settings + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return true interrupt is enabled on the selected channel + * @return false interrupt is disabled on the selected channel + */ +LOCAL_INLINE bool ADC_HWA_GetChannelInterruptEnable(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pAdc->SC[u8ChnIdx]; + u32TmpVal = (u32TmpVal & ADC_SC_AIEN_MASK) >> ADC_SC_AIEN_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set to enable or disable interrupt on the selected ADC channel + * + * @note this function is used only in ADC discontinuous mode to get the channel interrupt + * settings + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @param bEnable whether to enable interrupt on the selected ADC channel + */ +LOCAL_INLINE void ADC_HWA_SetChannelInterruptEnable(ADC_Type *const pAdc, const uint8_t u8ChnIdx, bool bEnable) +{ + pAdc->SC[u8ChnIdx] = (pAdc->SC[u8ChnIdx] & ~ADC_SC_AIEN_MASK) | ADC_SC_AIEN(bEnable); +} + +/** + * @brief Get the input channel of the selected ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return uint8_t the hardware input channel + */ +LOCAL_INLINE uint8_t ADC_HWA_GetChannelInput(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = (pAdc->SC[u8ChnIdx] & ADC_SC_CHS_MASK) >> ADC_SC_CHS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the input channel to the selected ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @param u8InputChann the hardware input channel + */ +LOCAL_INLINE void ADC_HWA_SetChannelInput(ADC_Type *const pAdc, const uint8_t u8ChnIdx, uint8_t u8InputChann) +{ + pAdc->SC[u8ChnIdx] = (pAdc->SC[u8ChnIdx] & ~ADC_SC_CHS_MASK) | ADC_SC_CHS(u8InputChann); +} + +/** + * @brief Get the conversion result data of the ADC instance + * + * @note only result data of ADC discontinuous mode will be stored in RESULTn register. + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the ADC channel + * @return uint32_t the ADC conversion result + */ +LOCAL_INLINE uint32_t ADC_HWA_GetChannelData(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pAdc->RESULT[u8ChnIdx]; + u32TmpVal = (u32TmpVal & ADC_RESULT_RESULT_MASK) >> ADC_RESULT_RESULT_SHIFT; + + return (uint32_t)u32TmpVal; +} + +/** @}*/ + +#endif /* _HWA_ADC_H_ */ diff --git a/Inc/HwA_aontimer.h b/Inc/HwA_aontimer.h new file mode 100644 index 0000000..c9fd40d --- /dev/null +++ b/Inc/HwA_aontimer.h @@ -0,0 +1,299 @@ +/** + * @file HwA_aontimer.h + * @author Flagchip + * @brief FC7xxx aontimer hardware access layer + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip076 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_AONTIMER_H_ +#define HWA_INCLUDE_HWA_AONTIMER_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_AONTIMER + * @{ + * + */ + +/********* Local typedef ************/ +/** + * @brief The clock source of the pulse mode + * + */ +typedef enum +{ + + AONTIMER_CLK0_PIN = 0, /*!< select the Aontimer_clk0 pin as pulse sourse*/ + AONTIMER_CLK1_PIN, /*!< select the Aontimer_clk1 pin as pulse sourse*/ + AONTIMER_CLK2_PIN, /*!< select the Aontimer_clk2 pin as pulse sourse*/ + AONTIMER_TRGSEL_OUTPUT, /*!< select the tresel as pulse sourse*/ + +} AONTIMER_PulseClkSrcType; + +/** + * @brief Aontimer clock source, please refer to Reference Manual chapter8.Aontimer for details. + * + * */ +typedef enum +{ + AONTIMER_SIRC_1MHZ = 0U, /*!< AONTIMER SIRC 1mhz clock */ + AONTIMER_RTC_CLK = 2U, /*!< AONTIMER RTC clock */ + AONTIMER_IRC_CLK = 3U /*!< AONTIMER internal clock, which comes from PCC */ +} AONTIMER_ClkSrcType; + +/** + * @brief The polarity of pulse mode + * + * */ +typedef enum +{ + AONTIMER_PulsePolarityType_HIGH = 0, /*!< select the high polarity */ + AONTIMER_PulsePolarityType_LOW /*!< select the low polarity */ +} AONTIMER_PulsePolarityType; + +/********* Local inline function ************/ +/** + * @brief Configure AONTIMER module + * + * @param u32RegValue CSR register value + */ +LOCAL_INLINE void AONTIMER_HWA_ConfigModule(uint32_t u32RegValue) +{ + AONTIMER->CSR = u32RegValue; +} + +/** + * @brief Configure AONTIMER module prescale + * + * @param u32RegValue PSR register value + */ +LOCAL_INLINE void AONTIMER_HWA_ConfigModulePrescale(uint32_t u32RegValue) +{ + AONTIMER->PSR = u32RegValue; +} + +/** + * @brief Set AONTIMER compare value + * + * @param u32RegValue CMR register value + */ +LOCAL_INLINE void AONTIMER_HWA_SetModuleCompareValue(uint32_t u32RegValue) +{ + AONTIMER->CMR = u32RegValue; +} + +/** + * @brief Set AONTIMER current counter value + * + * @param u32RegValue CNR register value + */ +LOCAL_INLINE void AONTIMER_HWA_SetModuleCounterValue(uint32_t u32RegValue) +{ + AONTIMER->CNR = u32RegValue; +} + +/** + * @brief Set AONTIMER module running on debug mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_SetModuleRunOnDebug(void) +{ + AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_DBGEN_MASK; +} + +/** + * @brief Enable AONTIMER module interrupt + * + */ +LOCAL_INLINE void AONTIMER_HWA_EnableModuleInterrupt(void) +{ + AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TIE_MASK; +} + +/** + * @brief Select AONTIMER module external clock source when timer configured to pulse mode + * + * @param eClk Input counter clock source + */ +LOCAL_INLINE void AONTIMER_HWA_SelectClkSrcOnPulseMode(AONTIMER_PulseClkSrcType eClk) +{ + uint32_t u32RegValue = AONTIMER->CSR; + AONTIMER->CSR |= (u32RegValue & ~(uint32_t)AONTIMER_CSR_TPS_MASK) | AONTIMER_CSR_TPS(eClk); +} + +/** + * @brief Clear AONTIMER interrupt flags + * + */ +LOCAL_INLINE void AONTIMER_HWA_ClearInterruptFlag(void) +{ + AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TCF_MASK; +} + +/** + * @brief Set AONTIMER module polarity. Pulse counter input source is active-low, and the CNR increments on falling-edge. + * + */ +LOCAL_INLINE void AONTIMER_HWA_SetModulePolarity(void) +{ + AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TPP_MASK; +} + +/** + * @brief Configure AONTIMER module polarity. If ePol is 0:Pulse counter input source is active-high, and the CNR increments on rising-edge. + * If ePol is 1:Pulse counter input source is active-low, and the CNR increments on falling-edge. + * + * @param ePol Polarity enumeration + */ +LOCAL_INLINE void AONTIMER_HWA_ConfigModulePolarity(AONTIMER_PulsePolarityType ePol) +{ + AONTIMER->CSR |= AONTIMER_CSR_TPP(ePol); +} + +/** + * @brief Enable AONTIMER module pulse mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_EnablePulseMode(void) +{ + AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TMS_MASK; +} + +/** + * @brief Enable AONTIMER timer + * + */ +LOCAL_INLINE void AONTIMER_HWA_EnableTimer(void) +{ + AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TEN_MASK; +} + +/** + * @brief Set AONTIMER prescale + * + * @param u8PrescalerValue Prescaler value,the range of the input value is :0~15, and the range of prescaler is :2^1 ~ 2^16. + */ +LOCAL_INLINE void AONTIMER_HWA_SetPrescale(uint8_t u8PrescalerValue) +{ + uint32_t u32RegValue = AONTIMER->PSR; + AONTIMER->PSR = ((u32RegValue & ~(uint32_t)AONTIMER_PSR_PRESCALE_MASK) | AONTIMER_PSR_PRESCALE(u8PrescalerValue)); +} + +/** + * @brief If enable bypass mode, the timer will bypass the prescaler in timer counter mode or glitch filter in pulse mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_EnableBypassMode(void) +{ + AONTIMER->PSR |= (uint32_t)AONTIMER_PSR_PBYP_MASK; +} + +/** + * @brief Select AONTIMER mdoule clock source + * + * @param eClk Aontimer clock source + */ +LOCAL_INLINE void AONTIMER_HWA_SelectModuleClkSrc(AONTIMER_ClkSrcType eClk) +{ + uint32_t u32RegValue = AONTIMER->PSR; + AONTIMER->PSR = ((u32RegValue & ~(uint32_t)AONTIMER_PSR_PCS_MASK) | AONTIMER_PSR_PCS(eClk)); +} + +/** + * @brief Set AONTIMER module stop on debug mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_SetModuleStopOnDebug(void) +{ + AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_DBGEN_MASK; +} + + +/** + * @brief Disable AONTIMER module interrupt + * + */ +LOCAL_INLINE void AONTIMER_HWA_DisableModuleInterrupt(void) +{ + AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TIE_MASK; +} + +/** + * @brief Clear AONTIMER module mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_ClearModuleMode(void) +{ + AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TPS_MASK; +} + +/** + * @brief Clear AONTIMER module polarity. Pulse counter input source is active-high, and the CNR increments on rising-edge. + * + */ +LOCAL_INLINE void AONTIMER_HWA_ClearModulePolarity(void) +{ + AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TPP_MASK; +} + +/** + * @brief Disable AONTIEMR module pulse mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_DisablePulseMode(void) +{ + AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TMS_MASK; +} + +/** + * @brief Disable AONTIMER module timer + * + */ +LOCAL_INLINE void AONTIMER_HWA_DisableTimer(void) +{ + AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TEN_MASK; +} + +/** + * @brief Clear AONTIMER module prescaler + * + */ +LOCAL_INLINE void AONTIMER_HWA_ClearPrescale(void) +{ + AONTIMER->PSR &= ~(uint32_t)AONTIMER_PSR_PRESCALE_MASK; +} + +/** + * @brief If disable bypass mode, the timer will enable the prescaler in timer counter mode or glitch filter in pulse mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_DisableBypassMode(void) +{ + AONTIMER->PSR &= ~(uint32_t)AONTIMER_PSR_PBYP_MASK; +} + +/** + * @brief Clear AONTIMER module clock source + * + */ +LOCAL_INLINE void AONTIMER_HWA_ClearModuleClkSrc(void) +{ + AONTIMER->PSR &= ~(uint32_t)AONTIMER_PSR_PCS_MASK; +} + +/** @}*/ /* HwA_AONTIMER */ + +#endif /* HWA_INCLUDE_HWA_AONTIMER_H_ */ diff --git a/Inc/HwA_cm7.h b/Inc/HwA_cm7.h new file mode 100644 index 0000000..694fbcc --- /dev/null +++ b/Inc/HwA_cm7.h @@ -0,0 +1,39 @@ +/** + * @file HwA_cm7.h + * @author Flagchip + * @brief FC7xxx cortex m4 hardware access layer + * @version 0.1.0 + * @date 2022-11-21 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +#ifndef _HWA_CM7_H_ +#define _HWA_CM7_H_ + +#include "device_header.h" + +/** + * @brief Enable deepsleep mode + * + */ +LOCAL_INLINE void CM7_HWA_EnableDeepSleep(void) +{ + SCB->SCR |= (uint32_t)SCB_SCR_SLEEPDEEP_Msk; +} + +/** + * @brief Disable deepsleep mode + * + */ +LOCAL_INLINE void CM7_HWA_DisableDeepSleep(void) +{ + SCB->SCR &= ~(uint32_t)SCB_SCR_SLEEPDEEP_Msk; +} + + + + +#endif /* #ifndef _HWA_CM7_H_ */ diff --git a/Inc/HwA_cmp.h b/Inc/HwA_cmp.h new file mode 100644 index 0000000..ebdd75b --- /dev/null +++ b/Inc/HwA_cmp.h @@ -0,0 +1,947 @@ +/** + * @file HwA_cmp.h + * @author Flagchip0126 + * @brief FC7xxx CMP driver type definition and API + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + + +#ifndef _HWA_CMP_H_ +#define _HWA_CMP_H_ + +#include "device_header.h" + +/********* Local typedef ************/ + +/** + * @brief The CMP complete DMA callback function prototype + * + */ + +/** + * @brief The instance index of the CMP mode + */ +typedef enum +{ + CMP_MOD_DISABLE = 0U, /*!< CMP function mode is disable */ + CMP_MOD_CONTINUOUS = 1U, /*!< CMP function mode is continuous */ + CMP_MOD_SAMPLE_NONFILTER_EXTCLK = 2U, /*!< CMP function mode is sampled,non-filtered mode 1*/ + CMP_MOD_SAMPLE_NONFILTER_INTCLK = 3U, /*!< CMP function mode is sampled,non-filtered mode 2*/ + CMP_MOD_SAMPLE_FILTER_EXTCLK = 4U, /*!< CMP function mode is sampled,filtered mode 1*/ + CMP_MOD_SAMPLE_FILTER_INTCLK = 5U, /*!< CMP function mode is sampled,filtered mode 2*/ + CMP_MOD_WINDOW = 6U, /*!< CMP function mode is windowed mode */ + CMP_MOD_WINDOW_RESAMPLE = 7U, /*!< CMP function mode is windowed,re-sampled mode */ + CMP_MOD_WINDOW_FILTER = 8U, /*!< CMP function mode is windowed,filtered mode */ + CMP_MOD_CHANNEL_SCAN = 9U /*!< CMP channel scan mode */ +} CMP_ModSelType; + +/** + * @brief The instance index of the CMP peripheral + */ +typedef enum +{ + CMP_INSTANCE_0 = 0U, /*!< CMP instance 0 is selected */ + CMP_INSTANCE_1 = 1U /*!< CMP instance 1 is selected */ +} CMP_InstanceType; + +/** + * @brief The instance index of the CMP DAC enable select + */ +typedef enum +{ + CMP_DACENABLE_DCR = 0U, /*!< CMP Dac is enabled by DCR[DAC_EN] */ + CMP_DACENABLE_CCR0 = 1U /*!< CMP Dac is enabled by CCR0[EN] */ +} CMP_DacEnableSrcType; + +/** + * @brief The instance index of the CMP output invert + */ +typedef enum +{ + CMP_NON_INVERT = 0U, /*!< CMP output do not Invert*/ + CMP_INVERT = 1U /*!< CMP output Invert */ +} CMP_InvertType; + +/** + * @brief The instance index of the CMP output select + */ +typedef enum +{ + CMP_FILTEROUT = 0U, /*!< CMP filter output */ + CMP_UNFILTEROUT = 1U /*!< CMP Unfilter output */ +} CMP_OutSelectType; + +/** + * @brief The instance index of the CMP window level + */ +typedef enum +{ + CMP_HOLD = 0U, /*!< CMP output hold when window close */ + CMP_USERDEF = 1U /*!< CMP output userdefine when window close */ +} CMP_OutWinLevelType; + +/** + * @brief The instance index of the window output under userdefine CMP window level + */ +typedef enum +{ + CMP_OUTWIN_0 = 0U, /*!< CMP window output is 0 */ + CMP_OUTWIN_1 = 1U /*!< CMP window output is 1 */ +} CMP_OutWinLevel_UserDefType; + + +/** + * @brief The instance index of the CMP Event caused window close + */ +typedef enum +{ + CMP_RISINGEDGE = 0U, /*!< CMP output event RisingEdge causes window close */ + CMP_FALLINGEDGE = 1U, /*!< CMP output event FallingEdge causes window close */ + CMP_BOTHEDGES = 2U, /*!< CMP output event bothEdges causes window close */ +} CMP_EventType; + +/** + * @brief The instance index of the CMP filter count numbers + */ +typedef enum +{ + CMP_FILTERCNT_0 = 0U, /*!< CMP filter is bypassed */ + CMP_FILTERCNT_1 = 1U, /*!< CMP filter is 1 consecutive sample */ + CMP_FILTERCNT_2 = 2U, /*!< CMP filter is 2 consecutive sample */ + CMP_FILTERCNT_3 = 3U, /*!< CMP filter is 3 consecutive sample */ + CMP_FILTERCNT_4 = 4U /*!< CMP filter is 4 consecutive sample */ +} CMP_FilterCntType; + +/** + * @brief The instance index of the CMP hysteresis control + */ +typedef enum +{ + CMP_HYSTCTRL_0 = 0U, /*!< CMP 0 hysteresis internal */ + CMP_HYSTCTRL_1 = 1U, /*!< CMP 1 hysteresis internal */ + CMP_HYSTCTRL_2 = 2U, /*!< CMP 2 hysteresis internal */ + CMP_HYSTCTRL_3 = 3U /*!< CMP 3 hysteresis internal */ +} CMP_HystCtrlType; + +/** + * @brief The fixed CMP port for reference in channel scan mode + */ +typedef enum +{ + CMP_PORTSEL_MUX_POSITIVE = 0U, + CMP_PORTSEL_MUX_NEGATIVE = 1U +} CMP_PortSelType; + +/** + * @brief The source of the CMP input + */ +typedef enum +{ + CMP_INSRCSEL_DAC = 0U, /*!< CMP input source is DAC */ + CMP_INSRCSEL_MUX = 1U /*!< CMP input source is analog 1-8 mux */ +} CMP_INSrcSelType; + +/** + * @brief The instance index of the CMP input mux + */ +typedef enum +{ + CMP_INSEL_MUX_IN0 = 0U, /*!< CMP input mux from IN0(CMP0,CMP1) */ + CMP_INSEL_MUX_IN1 = 1U, /*!< CMP input mux from IN1(CMP0,CMP1) */ + CMP_INSEL_MUX_IN2 = 2U, /*!< CMP input mux from IN2(CMP0,CMP1) */ + CMP_INSEL_MUX_IN3 = 3U, /*!< CMP input mux from IN3(CMP0,CMP1) */ + CMP_INSEL_MUX_IN4 = 4U, /*!< CMP input mux from IN4(CMP0,CMP1) */ + CMP_INSEL_MUX_IN5 = 5U, /*!< CMP input mux from IN5(CMP0,CMP1) */ + CMP_INSEL_MUX_IN6 = 6U, /*!< CMP input mux from IN6(CMP0,CMP1) */ + CMP_INSEL_MUX_IN7 = 7U /*!< CMP input mux from IN7(CMP0,CMP1) */ +} CMP_MuxSelType; + +/** + * @brief The instance index of DAC high voltage reference select + */ +typedef enum +{ + CMP_DACVINREF_H0 = 0U, /*!< CMP DAC high voltage input reference vrefh0 */ + CMP_DACVINREF_H1 = 1U /*!< CMP DAC high voltage input reference vrefh1 */ +} CMP_DacVinRefSelType; + +/** + * @brief The instance index of high power mode select + */ +typedef enum +{ + CMP_LOWSPEEDMOD = 0U, /*!< CMP low speed mode */ + CMP_HIGHSPEEDMOD = 1U /*!< CMP high speed mode */ +} CMP_SpeedModSelType; + +/** + * @brief Defines CMP out status + */ +typedef enum +{ + CMP_OUT_FALLING_EDGE = 0U, /*!< CMP out detect falling edge */ + CMP_OUT_RISING_EDGE = 1U, /*!< CMP out detect rising edge */ + CMP_OUT_NONE = 2U /*!< CMP out detect none */ +} CMP_OutStatus; + +/********* Local inline function ************/ + +/** + * @brief set CMP enable + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_Enable(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CCR0; + pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_EN_MASK)) | CMP_CCR0_EN(true)); +} + +/** + * @brief set CMP disable + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_Disable(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CCR0; + pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_EN_MASK)) | CMP_CCR0_EN(false)); +} + +/** + * @brief set CMP DMA enable + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_DmaEnable(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_DMA_EN_MASK)) | CMP_CCR1_DMA_EN(true)); +} + +/** + * @brief set CMP DMA disable + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_DmaDisable(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_DMA_EN_MASK)) | CMP_CCR1_DMA_EN(false)); +} + +/** + * @brief set CMP mode + * + * @param pCmp the CMP instance to use + * @param eMod the CMP mode to use + * @param u8FilterPrd the CMP filter period + * @param eFilterCnt the CMP filter sample count + */ +LOCAL_INLINE void CMP_HWA_SetComparatorMod(CMP_Type *const pCmp, CMP_ModSelType eMod, uint8_t u8FilterPrd, CMP_FilterCntType eFilterCnt) +{ + switch (eMod) + { + case CMP_MOD_DISABLE: + { + /* Nothing deal with */ + } + break; + + case CMP_MOD_CONTINUOUS: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) | + CMP_CCR1_SAMPLE_EN(false); + } + break; + + case CMP_MOD_SAMPLE_NONFILTER_EXTCLK: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) | + CMP_CCR1_SAMPLE_EN(true) | + CMP_CCR1_FILT_CNT(0x01); + } + break; + + case CMP_MOD_SAMPLE_NONFILTER_INTCLK: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) | + CMP_CCR1_SAMPLE_EN(false) | + CMP_CCR1_FILT_CNT(0x01) | + CMP_CCR1_FILT_PER(u8FilterPrd); + } + break; + + case CMP_MOD_SAMPLE_FILTER_EXTCLK: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) | + CMP_CCR1_SAMPLE_EN(true) | + CMP_CCR1_FILT_CNT(u8FilterPrd); + } + break; + + case CMP_MOD_SAMPLE_FILTER_INTCLK: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) | + CMP_CCR1_SAMPLE_EN(false) | + CMP_CCR1_FILT_CNT(eFilterCnt) | + CMP_CCR1_FILT_PER(u8FilterPrd); + } + break; + + case CMP_MOD_WINDOW: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(true) | + CMP_CCR1_SAMPLE_EN(false) | + CMP_CCR1_FILT_CNT(0x00) | + CMP_CCR1_FILT_PER(0x00); + } + break; + + case CMP_MOD_WINDOW_RESAMPLE: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(true) | + CMP_CCR1_SAMPLE_EN(false) | + CMP_CCR1_FILT_CNT(0x01) | + CMP_CCR1_FILT_PER(u8FilterPrd); + } + break; + + case CMP_MOD_WINDOW_FILTER: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(true) | + CMP_CCR1_SAMPLE_EN(false) | + CMP_CCR1_FILT_CNT(eFilterCnt) | + CMP_CCR1_FILT_PER(u8FilterPrd); + } + break; + + case CMP_MOD_CHANNEL_SCAN: + { + pCmp->CSCR0 |= CMP_CSCR0_CS_EN(true) ; + } + + break; + default: + break; + } +} + +/** + * @brief STOP mode enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnStopMod(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR0; + pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_STOP_EN_MASK)) | CMP_CCR0_STOP_EN(bEnable)); +} + +/** + * @brief set DAC enable selection + * + * @param pCmp the CMP instance to use + * @param eType Dac enable source + */ +LOCAL_INLINE void CMP_HWA_SetDacEnableSrc(CMP_Type *const pCmp, CMP_DacEnableSrcType eType) +{ + uint32_t u32RegVal = pCmp->CCR0; + pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_DACEN_SEL_MASK)) | CMP_CCR0_DACEN_SEL(eType)); +} + +/** + * @brief set CPM output invert + * + * @param pCmp the CMP instance to use + * @param eType CPM output invert type + */ +LOCAL_INLINE void CMP_HWA_SetCmpOutInvert(CMP_Type *const pCmp, CMP_InvertType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_INV_MASK)) | CMP_CCR1_CMPOUT_INV(eType)); +} + +/** + * @brief set CPM output filter/unfilter selection + * + * @param pCmp the CMP instance to use + * @param eType CPM output filter/unfilter type + */ +LOCAL_INLINE void CMP_HWA_SetCmpOutSel(CMP_Type *const pCmp, CMP_OutSelectType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_SEL_MASK)) | CMP_CCR1_CMPOUT_SEL(eType)); +} + +/** + * @brief set comparator output pin enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnCmpOutPack(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_PEN_MASK)) | CMP_CCR1_CMPOUT_PEN(bEnable)); +} + +/** + * @brief set CMPOUT_WIN level, when window is closed + * + * @param pCmp the CMP instance to use + * @param eType CMPOUT_WIN level type + */ +LOCAL_INLINE void CMP_HWA_SetCmpOutWinLevel(CMP_Type *const pCmp, CMP_OutWinLevelType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_WIN_OWEN_MASK)) | CMP_CCR1_CMPOUT_WIN_OWEN(eType)); +} + +/** + * @brief set CMPOUT_WIN level in user-define mode, when window is closed + * + * @param pCmp the CMP instance to use + * @param eType user-define CMPOUT_WIN level type + */ +LOCAL_INLINE void CMP_HWA_SetCmpOutWin(CMP_Type *const pCmp, CMP_OutWinLevel_UserDefType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_WIN_OW_MASK)) | CMP_CCR1_CMPOUT_WIN_OW(eType)); +} + +/** + * @brief set invert the WINDOW/SAMPLE signal enable or not + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnWinSampleInvert(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_WIN_INV_MASK)) | CMP_CCR1_WIN_INV(bEnable)); +} + +/** + * @brief WINDOW signal can or not be closed by CMPO event when window mode + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnEventCloseWin(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_WIN_CLS_MASK)) | CMP_CCR1_WIN_CLS(bEnable)); +} + +/** + * @brief set which CMPO event causes window close + * + * @param pCmp the CMP instance to use + * @param eType CMPO event type + */ +LOCAL_INLINE void CMP_HWA_SetEventCloseWin(CMP_Type *const pCmp, CMP_EventType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_EVT_SEL_MASK)) | CMP_CCR1_EVT_SEL(eType)); +} + +/** + * @brief set CMP power mode select + * + * @param pCmp the CMP instance to use + * @param eMod CMP power mode + */ +LOCAL_INLINE void CMP_HWA_SetSpeedMod(CMP_Type *const pCmp, CMP_SpeedModSelType eMod) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_HPMD_MASK)) | CMP_CCR2_HPMD(eMod)); +} + +/** + * @brief set Comparator hard block hysteresis control + * + * @param pCmp the CMP instance to use + * @param eType CMP hysteresis control type + */ +LOCAL_INLINE void CMP_HWA_SetHystCtrl(CMP_Type *const pCmp, CMP_HystCtrlType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_HYSTCTR_MASK)) | CMP_CCR2_HYSTCTR(eType)); +} + +/** + * @brief set Comparator analog confifuration transition bypass + * + * @param pCmp the CMP instance to use + * @param Enable The status for Comparator analog confifuration transition bypass + */ +LOCAL_INLINE void CMP_HWA_SetAnalogConfTransByp(CMP_Type *const pCmp, bool Enable) +{ + uint32_t u32RegVal = pCmp->CCR3; + pCmp->CCR3 = ((u32RegVal & (~(uint32_t)CMP_CCR3_DAC_TRANS_BYP_MASK)) | CMP_CCR3_DAC_TRANS_BYP(Enable)); +} + +/** + * @brief set Comparator hard block hysteresis control + * + * @param pCmp the CMP instance to use + * @param Count Comparator analog confifuration transition bypass count + */ +LOCAL_INLINE void CMP_HWA_SetAnalogConfTransBypCnt(CMP_Type *const pCmp, uint16_t Count) +{ + uint32_t u32RegVal = pCmp->CCR3; + Count = Count & 0x3ff; + pCmp->CCR3 = ((u32RegVal & (~(uint32_t)CMP_CCR3_DAC_RDY_CNT_MASK)) | CMP_CCR3_DAC_RDY_CNT(Count)); +} + +/** + * @brief set which input is selected for the positive mux + * + * @param pCmp the CMP instance to use + * @param eType CMP positive mux type + */ +LOCAL_INLINE void CMP_HWA_SetPSelMux(CMP_Type *const pCmp, CMP_MuxSelType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_PSEL_MASK)) | CMP_CCR2_PSEL(eType)); +} + +/** + * @brief set which input is selected for the negative mux + * + * @param pCmp the CMP instance to use + * @param eType CMP negative mux type + */ +LOCAL_INLINE void CMP_HWA_SetNSelMux(CMP_Type *const pCmp, CMP_MuxSelType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_MSEL_MASK)) | CMP_CCR2_MSEL(eType)); +} + +/** + * @brief set the input to the positive port of the comparator + * + * @param pCmp the CMP instance to use + * @param eType CMP positive input source type(analog mux,dac) + */ +LOCAL_INLINE void CMP_HWA_SetINPSel(CMP_Type *const pCmp, CMP_INSrcSelType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_INPSEL_MASK)) | CMP_CCR2_INPSEL(eType)); +} + +/** + * @brief set the input to the negative port of the comparator + * + * @param pCmp the CMP instance to use + * @param eType CMP negative input source type(analog mux,dac) + */ +LOCAL_INLINE void CMP_HWA_SetINNSel(CMP_Type *const pCmp, CMP_INSrcSelType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_INMSEL_MASK)) | CMP_CCR2_INMSEL(eType)); +} + +/** + * @brief set CMP DAC enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnDac(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->DCR; + pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_DAC_EN_MASK)) | CMP_DCR_DAC_EN(bEnable)); +} + + +/** + * @brief set DAC reference voltage source + * + * @param pCmp the CMP instance to use + * @param eType CMP reference voltage source type + */ +LOCAL_INLINE void CMP_HWA_SetVinRefSel(CMP_Type *const pCmp, CMP_DacVinRefSelType eType) +{ + uint32_t u32RegVal = pCmp->DCR; + pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_VRSEL_MASK)) | CMP_DCR_VRSEL(eType)); +} + +/** + * @brief set CMP Dac output + * + * @param pCmp the CMP instance to use + * @param u8Data the Dac data + * @note output = (VinRef / 256) * (u8Data + 1) + */ +LOCAL_INLINE void CMP_HWA_SetDacData(CMP_Type *const pCmp, uint8_t u8Data) +{ + uint32_t u32RegVal = pCmp->DCR; + pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_DAC_DATA_MASK)) | CMP_DCR_DAC_DATA(u8Data)); +} + +/** + * @brief set comparator rising interrupt enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetIntEn_Rising(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->IER; + pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CFR_IE_MASK)) | CMP_IER_CFR_IE(bEnable)); +} + +/** + * @brief get comparator rising interrupt enable status + * + * @param pCmp the CMP instance to use + * @return comparator rising interrupt status + */ +LOCAL_INLINE bool CMP_HWA_GetIntEn_Rising(CMP_Type *const pCmp) +{ + bool RetStatus = false; + uint32_t u32RegVal = pCmp->IER; + + RetStatus = (bool)((((u32RegVal & CMP_IER_CFR_IE_MASK) >> CMP_IER_CFR_IE_SHIFT) != 0U) ? true : false); + return RetStatus; +} + +/** + * @brief set comparator falling interrupt enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetIntEn_Falling(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->IER; + pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CFF_IE_MASK)) | CMP_IER_CFF_IE(bEnable)); +} + +/** + * @brief get comparator falling interrupt enable status + * + * @param pCmp the CMP instance to use + * @return comparator falling interrupt status + */ +LOCAL_INLINE bool CMP_HWA_GetIntEn_Falling(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->IER; + + bRetStatus = (bool)((((u32RegVal & CMP_IER_CFF_IE_MASK) >> CMP_IER_CFF_IE_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief set comparator channel scan interrupt enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetIntEn_ChannelScan(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->IER; + pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CSF_IE_MASK)) | CMP_IER_CSF_IE(bEnable)); +} + +/** + * @brief get comparator channel scan interrupt enable status + * + * @param pCmp the CMP instance to use + * @return comparator channel scan interrupt status + */ +LOCAL_INLINE bool CMP_HWA_GetIntEn_ChannelScan(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->IER; + + bRetStatus = (bool)((((u32RegVal & CMP_IER_CSF_IE_MASK) >> CMP_IER_CSF_IE_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief get CMP output rising edge status + * + * @param pCmp the CMP instance to use + * @return CMP rising edge status + */ +LOCAL_INLINE bool CMP_HWA_GetIntFlag_Rising(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->CSR; + + bRetStatus = (bool)((((u32RegVal & CMP_CSR_CFR_MASK) >> CMP_CSR_CFR_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief get CMP output falling edge status + * + * @param pCmp the CMP instance to use + * @return CMP falling edge status + */ +LOCAL_INLINE bool CMP_HWA_GetIntFlag_Falling(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->CSR; + + bRetStatus = (bool)((((u32RegVal & CMP_CSR_CFF_MASK) >> CMP_CSR_CFF_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief get CMP output channel scan status + * + * @param pCmp the CMP instance to use + * @return CMP channel scan status + */ +LOCAL_INLINE bool CMP_HWA_GetIntFlag_ChannelScan(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->CSR; + + bRetStatus = (bool)((((u32RegVal & CMP_CSR_CSF_MASK) >> CMP_CSR_CSF_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + + +/** + * @brief clear rising interrupt flag + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_ClearIntFlag_Rising(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSR; + pCmp->CSR = ((u32RegVal & (~(uint32_t)CMP_CSR_CFR_MASK)) | CMP_CSR_CFR(true)); +} + +/** + * @brief clear falling interrupt flag + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_ClearIntFlag_Falling(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSR; + pCmp->CSR = ((u32RegVal & (~(uint32_t)CMP_CSR_CFF_MASK)) | CMP_CSR_CFF(true)); +} + +/** + * @brief clear channel scan interrupt flag + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_ClearIntFlag_ChannelScan(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSR; + pCmp->CSR = ((u32RegVal & (~(uint32_t)CMP_CSR_CSF_MASK)) | CMP_CSR_CSF(true)); +} + +/** + * @brief get CMP filtered output + * + * @param pCmp the CMP instance to use + * @return CMP filtered output + */ +LOCAL_INLINE bool CMP_HWA_GetCmpOut(CMP_Type *const pCmp) +{ + bool CmpOut; + uint32_t u32RegVal = pCmp->CSR; + CmpOut = ((u32RegVal & CMP_CSR_CMPOUT_FILTER_MASK) >> CMP_CSR_CMPOUT_FILTER_SHIFT) ? true : false; + return CmpOut; +} + +/** + * @brief set CMP and DAC initialization delay modulus + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_SetCSInitModulus(CMP_Type *const pCmp, uint8_t u8Modulus) +{ + uint32_t u32RegVal = pCmp->CSCR0; + pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_INITMOD_MASK)) | CMP_CSCR0_CS_INITMOD(u8Modulus)); +} + +/** + * @brief set number of clock cycles for sampling + * + * @param pCmp the CMP instance to use + * @param u8Nsam the sampling clocks value + */ +LOCAL_INLINE void CMP_HWA_SetCSNumOfSampleClocks(CMP_Type *const pCmp, uint8_t u8Nsam) +{ + uint32_t u32RegVal = pCmp->CSCR0; + pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_NSAM_MASK)) | CMP_CSCR0_CS_NSAM(u8Nsam)); +} + +/** + * @brief set CMP channel scan enable + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_CSEnable(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSCR0; + pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_EN_MASK)) | CMP_CSCR0_CS_EN(true)); +} + +/** + * @brief set CMP channel scan disable + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_CSDisable(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSCR0; + pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_EN_MASK)) | CMP_CSCR0_CS_EN(false)); +} + +/** + * @brief set channel scan fixed channel + * + * @param pCmp the CMP instance to use + * @param eChannel the fixed channel + */ +LOCAL_INLINE void CMP_HWA_SetCSFixedChannel(CMP_Type *const pCmp, CMP_MuxSelType eChannel) +{ + uint32_t u32RegVal = pCmp->CSCR1; + pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)CMP_CSCR1_FIXCH_MASK)) | CMP_CSCR1_FIXCH(eChannel)); +} + +/** + * @brief set channel scan fixed port + * + * @param pCmp the CMP instance to use + * @param ePort the fixed port + */ +LOCAL_INLINE void CMP_HWA_SetCSFixedPort(CMP_Type *const pCmp, CMP_PortSelType ePort) +{ + uint32_t u32RegVal = pCmp->CSCR1; + pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)CMP_CSCR1_FIXP_MASK)) | CMP_CSCR1_FIXP(ePort)); +} + +/** + * @brief set channel scan channel enabled + * + * @param pCmp the CMP instance to use + * @param eChannel the enabled channel + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetCSChannelEn(CMP_Type *const pCmp, CMP_MuxSelType eChannel, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CSCR1; + pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)(1 << eChannel))) | (((uint32_t)bEnable) << eChannel)); +} + +/** + * @brief set channel scan channel enabled + * + * @param pCmp the CMP instance to use + * @param eChannel the enabled channel + * @param bPresetstate preset state for channel + */ +LOCAL_INLINE void CMP_HWA_SetCSChannelPresetstate(CMP_Type *const pCmp, CMP_MuxSelType eChannel, bool bPresetstate) +{ + uint32_t u32RegVal = pCmp->CSCSR; + pCmp->CSCSR = ((u32RegVal & (~(uint32_t)(1 << eChannel))) | (((uint32_t)bPresetstate) << eChannel)); +} + +/** + * @brief get channel scan channel current state + * + * @param pCmp the CMP instance to use + * @param eChannel the channel that want to get state + */ +LOCAL_INLINE bool CMP_HWA_GetCSChannelsOut(CMP_Type *const pCmp, CMP_MuxSelType eChannel) +{ + bool OutFlag; + uint32_t u32RegVal = pCmp->CSCSR; + OutFlag = (bool)((u32RegVal & ((uint32_t)(1 << eChannel))) >> eChannel); + + return OutFlag; +} + +/** + * @brief software clear channel scan comparison results + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_ClearCSComparisonResults(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSCSR; + pCmp->CSCSR = ((u32RegVal & (~(uint32_t)CMP_CSCSR_CS_SWCLR_MASK)) | CMP_CSCSR_CS_SWCLR(true)); +} + +/** + * @brief software clear channel scan comparison results + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetCSComparisonResultsAutoClearEn(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CSCSR; + pCmp->CSCSR = ((u32RegVal & (~(uint32_t)CMP_CSCSR_CS_ACLR_MASK)) | CMP_CSCSR_CS_ACLR(bEnable)); +} + +/** + * @brief get channel scan comparison reuslt + * + * @param pCmp the CMP instance to use + * @param eChannel the enabled channel + * @return channel comparison result for a given channel + */ +LOCAL_INLINE uint32_t CMP_HWA_GetCSComparisonResult(CMP_Type *const pCmp, CMP_MuxSelType eChannel) +{ + uint32_t u32RegVal = pCmp->CSCSR; + u32RegVal = (u32RegVal & (1 << eChannel)) >> eChannel; + return u32RegVal; +} + +/** + * @brief set channel scan active + * + * @param pCmp the CMP instance to use + * @return status cmp channel whether is active + */ +LOCAL_INLINE bool CMP_HWA_GetCSActive(CMP_Type *const pCmp) +{ + bool status; + uint32_t u32RegVal = pCmp->CSSR; + status = ((u32RegVal & ((uint32_t)CMP_CSSR_CS_ACTIVE_MASK)) >> CMP_CSSR_CS_ACTIVE_SHIFT) ? true : false; + return status; +} + +/** + * @brief get channel scan comparison result changed flag + * + * @param pCmp the CMP instance to use + * @param eChannel the channel to get comparison result changed flag + * @return the comparison result changed flag for a given channel + */ +LOCAL_INLINE bool CMP_HWA_GetCSComparisonResultFlag(CMP_Type *const pCmp, CMP_MuxSelType eChannel) +{ + bool flag; + uint32_t u32RegVal = pCmp->CSSR; + flag = ((u32RegVal & (1 << eChannel)) >> eChannel) ? true : false; + return flag; +} + +#endif /* #ifndef _HWA_CMP_H_ */ diff --git a/Inc/HwA_cmu.h b/Inc/HwA_cmu.h new file mode 100644 index 0000000..887dc31 --- /dev/null +++ b/Inc/HwA_cmu.h @@ -0,0 +1,271 @@ +/** + * @file HwA_cmu.h + * @author Flagchip085 + * @brief FC7xxx CMU hardware access layer + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 +******************************************************************************** */ + +#ifndef _HWA_CMU_H_ +#define _HWA_CMU_H_ + +#include "device_header.h" + +/********* Local inline function ************/ +/** + * @brief Set Reference Window value. + * @param pCmu CMU Instance. + * @param u32Value Ref Window value. +*/ +LOCAL_INLINE void CMU_HWA_SetRefWindow(CMU_Type *const pCmu, uint32_t u32Value) +{ + pCmu->REF_WINDOW = CMU_REF_WINDOW_REF_WINDOW(u32Value); +} + +/** + * @brief Get Reference Window value. + * @param pCmu CMU Instance. + * @return Reference Window value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetRefWindow(const CMU_Type *const pCmu) +{ + return (pCmu->REF_WINDOW & CMU_REF_WINDOW_REF_WINDOW_MASK) >> CMU_REF_WINDOW_REF_WINDOW_SHIFT; +} + +/** +* @brief Set Minimun Counter value + * @param pCmu CMU Instance. + * @param u32Value Min Count value. +*/ +LOCAL_INLINE void CMU_HWA_SetMinCnts(CMU_Type *const pCmu, uint32_t u32Value) +{ + pCmu->MIN = CMU_MIN_MIN(u32Value); +} + +/** + * @brief Get Minimun Counter value. + * @param pCmu CMU Instance. + * @return Min count value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetMinCnts(const CMU_Type *const pCmu) +{ + return (pCmu->MIN & CMU_MIN_MIN_MASK) >> CMU_MIN_MIN_SHIFT; +} + +/** + * @brief Set Maximun Counter value. + * @param pCmu CMU Instance. + * @param u32Value Max count value. +*/ +LOCAL_INLINE void CMU_HWA_SetMaxCnts(CMU_Type *const pCmu, uint32_t u32Value) +{ + pCmu->MAX = CMU_MAX_MAX(u32Value); +} + +/** + * @brief Get Maximun Counter value. + * @param pCmu CMU Instance. + * @return Max count value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetMaxCnts(const CMU_Type *const pCmu) +{ + return (pCmu->MAX & CMU_MAX_MAX_MASK) >> CMU_MAX_MAX_SHIFT; +} + +/** + * @brief Get Counter value. + * @param pCmu CMU Instance. + * @return Counter value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetCount(const CMU_Type *const pCmu) +{ + return (pCmu->MON_CNT & CMU_MON_CNT_MON_CNT_MASK) >> CMU_MON_CNT_MON_CNT_SHIFT; +} + +/** + * @brief Set period window Counter. + * @param pCmu CMU Instance. + * @param u32Value Period value. +*/ +LOCAL_INLINE void CMU_HWA_SetPeriodWindow(CMU_Type *const pCmu, uint32_t u32Value) +{ + pCmu->PERIOD = (pCmu->PERIOD & ~CMU_PERIOD_WINDOW_MASK) | CMU_PERIOD_WINDOW(u32Value); +} + +/** + * @brief Set period enble bit. +* + * @param pCmu CMU Instance. + * @param bEnable Set enable bit. +*/ +LOCAL_INLINE void CMU_HWA_SetPeriodEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->PERIOD = (pCmu->PERIOD & ~((uint32_t)CMU_PERIOD_EN_MASK)) | CMU_PERIOD_EN(bEnable); +} + +/** +* @brief Set control register value. + * + * @param pCmu CMU Instance. + * @param u32Value Control value. +*/ +LOCAL_INLINE void CMU_HWA_SETCTRL(CMU_Type *const pCmu, uint32_t u32Value) +{ + pCmu->CTRL = u32Value; +} + +/** +* @brief return control register value. + * + * @param pCmu CMU Instance. + * @return CMU Control register value +*/ +LOCAL_INLINE uint32_t CMU_HWA_GetCTRL(const CMU_Type *const pCmu) +{ + return pCmu->CTRL; +} + +/** + * @brief return status register value. + * @param pCmu CMU Instance. + * @return Status value. +*/ +LOCAL_INLINE uint32_t CMU_HWA_GetST(const CMU_Type *const pCmu) +{ + return pCmu->ST; +} + +/** + * @brief Clear clock monitor status + * @param pCmu CMU Instance. +*/ +LOCAL_INLINE void CMU_HWA_ClearST(CMU_Type *const pCmu) +{ + pCmu->ST = (uint32_t)(CMU_ST_MIS_MASK | CMU_ST_LOC_MASK); +} + +/** + * @brief Set the Divider for Reference Clock + * @param pCmu CMU Instance. + * @param eDivider The Divider of Reference Clock +*/ +LOCAL_INLINE void CMU_HWA_SetRefClockDiv(CMU_Type *const pCmu, uint8_t eDivider) +{ + pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_REF_DIV_MASK)) | CMU_CTRL_REF_DIV(eDivider); +} + +/** + * @brief Get the Divider for Reference Clock + * @param pCmu CMU Instance. + * @return The Divider of Reference Clock +*/ +LOCAL_INLINE uint8_t CMU_HWA_GetRefClockDiv(const CMU_Type *const pCmu) +{ + uint32_t u32Temp = (pCmu->CTRL & (uint32_t)CMU_CTRL_REF_DIV_MASK) >> CMU_CTRL_REF_DIV_SHIFT; + return (uint8_t)u32Temp; +} + +/** + * @brief Enable interrupt when LOC or MIS asserted + * @param pCmu CMU Instance. + * @param bEnable Enable or disable CMU interrupt +*/ +LOCAL_INLINE void CMU_HWA_IrqEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->CTRL = (pCmu->CTRL & (~((uint32_t)CMU_CTRL_IRQ_EN_MASK))) | CMU_CTRL_IRQ_EN(bEnable); +} + +/** + * @brief Get CMU interrupt enable flag + * @param pCmu CMU Instance. + * @return 1 : CMU interrupt enabled + * 0 : CMU interrupt disabled +*/ +LOCAL_INLINE uint8_t CMU_HWA_GetIrqEnableFlag(const CMU_Type *const pCmu) +{ + uint32_t u32Temp = (pCmu->CTRL & (uint32_t)CMU_CTRL_IRQ_EN_MASK) >> CMU_CTRL_IRQ_EN_SHIFT; + return (uint8_t)u32Temp; +} + +/** + * @brief Enable Standby mode + * @param pCmu CMU Instance. + * @param bEnable Enable mode +*/ +LOCAL_INLINE void CMU_HWA_StanbyModeEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_LP_EN_MASK)) | CMU_CTRL_LP_EN(bEnable); +} + +/** + * @brief Enable Stop mode + * @param pCmu CMU Instance. + * @param bEnable Enable mode +*/ +LOCAL_INLINE void CMU_HWA_StopModeEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_STOP_EN_MASK)) | CMU_CTRL_STOP_EN(bEnable); +} + +/** + * @brief Enable hardware restart CMU after exiting from the low-power mode + * @param pCmu CMU Instance. + * @param bEnable Enable mode +*/ +LOCAL_INLINE void CMU_HWA_LPRestartEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_RESTART_EN_MASK)) | CMU_CTRL_RESTART_EN(bEnable); +} + +/** + * @brief Software Reset the CMU + * @param pCmu CMU Instance. +*/ +LOCAL_INLINE void CMU_HWA_SoftwareReset(CMU_Type *const pCmu) +{ + pCmu->CTRL |= CMU_CTRL_SW_RST_MASK; +} + +/** + * @brief Enable the CMU + * @param pCmu CMU Instance. +*/ +LOCAL_INLINE void CMU_HWA_Enable(CMU_Type *const pCmu) +{ + pCmu->CTRL |= CMU_CTRL_ENABLE_MASK; +} + +/** + * @brief Disable the CMU + * @param pCmu CMU Instance. +*/ +LOCAL_INLINE void CMU_HWA_Disable(CMU_Type *const pCmu) +{ + pCmu->CTRL &= ~(CMU_CTRL_ENABLE_MASK | CMU_CTRL_IRQ_EN_MASK); + +} + +/** + * @brief Get the CMU enabled status + * @param pCmu CMU Instance. + * @return 1 : CMU is enabled + * 0 : CMU is disabled +*/ +LOCAL_INLINE uint8_t CMU_HWA_GetEnableStatus(const CMU_Type *const pCmu) +{ + uint32_t u32Temp = (pCmu->CTRL & (uint32_t)CMU_CTRL_ENABLE_MASK) >> CMU_CTRL_ENABLE_SHIFT; + return (uint8_t)u32Temp; +} + +#endif /* #ifndef _HWA_CMU_H_ */ diff --git a/Inc/HwA_cordic.h b/Inc/HwA_cordic.h new file mode 100644 index 0000000..276a7b3 --- /dev/null +++ b/Inc/HwA_cordic.h @@ -0,0 +1,134 @@ +/** + * @file HwA_cordic.h + * @author Flagchip + * @brief Hardware access layer for Cordic + * @version 0.1.0 + * @date 2024-01-11 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _HWA_CORDIC_H_ +#define _HWA_CORDIC_H_ +#include "device_header.h" + +typedef enum +{ + CORDIC_Iteration_8 = 0, + CORDIC_Iteration_16, + CORDIC_Iteration_24 +}CORDIC_IterationType; + +typedef enum +{ + CORDIC_Trigonometric = 0, + CORDIC_Hyperbolic, + CORDIC_Linear +}CORDIC_SystemType; + +typedef enum +{ + CORDIC_Rotate = 0, + CORDIC_Vector +}CORDIC_ModeType; + + +#define CORDIC_CTR_VAL(s,a,b,c,d) (CORDIC_CTRL_SCALE(s) | CORDIC_CTRL_IE(a) | CORDIC_CTRL_ITER(b) | CORDIC_CTRL_OS(c) | CORDIC_CTRL_MODE(d)) +/** + * @brief Set Cordic module Ctrl register + * + * @param u32Value Ctrl register value + */ +LOCAL_INLINE void Cordic_HWA_SetCtrl(uint32_t u32Value) +{ + CORDIC->CTRL = u32Value; +} + +/** + * @brief Read Cordic module Ctrl register + * + * @return Ctrl register value + */ +LOCAL_INLINE uint32_t Cordic_HWA_GetCtrl(void) +{ + return (uint32_t)(CORDIC->CTRL); +} + +/** + * @brief Set Cordic module XInput register + * + * @param u32Value XInput register value + */ +LOCAL_INLINE void Cordic_HWA_Set_XInput(int32_t u32Value) +{ + CORDIC->X_INPUT = (uint32_t)u32Value; +} + +/** + * @brief Set Cordic module YInput register + * + * @param u32Value YInput register value + */ +LOCAL_INLINE void Cordic_HWA_Set_YInput(int32_t u32Value) +{ + CORDIC->Y_INPUT = (uint32_t)u32Value; +} + +/** + * @brief Set Cordic module ZInput register + * + * @param u32Value ZInput register value + */ +LOCAL_INLINE void Cordic_HWA_Set_ZInput(int32_t u32Value) +{ + CORDIC->Z_INPUT = (uint32_t)u32Value; +} + +/** + * @brief Read Cordic module XOutput register + * + * @return XOutput register value + */ +LOCAL_INLINE uint32_t Cordic_HWA_Get_XOutput(void) +{ + return (uint32_t)(CORDIC->X_OUTPUT); +} + +/** + * @brief Read Cordic module YOutput register + * + * @return YOutput register value + */ +LOCAL_INLINE uint32_t Cordic_HWA_Get_YOutput(void) +{ + return (uint32_t)(CORDIC->Y_OUTPUT); +} + +/** + * @brief Read Cordic module ZOutput register + * + * @return ZOutput register value + */ +LOCAL_INLINE uint32_t Cordic_HWA_Get_ZOutput(void) +{ + return (uint32_t)(CORDIC->Z_OUTPUT); +} + +/** + * @brief Read Cordic module state + * + * @return Cordic module current state + */ +LOCAL_INLINE bool Cordic_HWA_Get_Stat(void) +{ + return (bool)(CORDIC->STAT & CORDIC_STAT_DONE_MASK); +} + +#endif diff --git a/Inc/HwA_cpm.h b/Inc/HwA_cpm.h new file mode 100644 index 0000000..a9904ed --- /dev/null +++ b/Inc/HwA_cpm.h @@ -0,0 +1,350 @@ +/** + * @file HwA_cpm.h + * @author Flagchip + * @brief FC7xxx CPM register API + * @version 0.1.0 + * @date 2024-1-5 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-1-5 Flagchip120 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_CPM_H_ +#define HWA_INCLUDE_HWA_CPM_H_ +#include "device_header.h" +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + +/** FPSCR Bit Fields */ +#define FPSCR_IOC_MASK 0x00000001U +#define FPSCR_DZC_MASK 0x00000002U +#define FPSCR_OFC_MASK 0x00000004U +#define FPSCR_UFC_MASK 0x00000008U +#define FPSCR_IXC_MASK 0x00000010U +#define FPSCR_IDC_MASK 0x00000080U +#define CPM_FPU_INTFLAGMASK 0x0000003FU + +/** + * @defgroup HwA_cpm + * @ingroup fc7xxx_driver_cpm + * @{ + */ + +/** + * @brief FPU INTERRUPT type. + * + * This provides constants for FPU interrupt type for use in the FPU functions. + * Please refer to Reference Manual chapter 14 CPM, it introduce register FISCR for details. + * + */ + + +typedef enum +{ + CPM_FPU_FIO = 1U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FIOCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FIOC Status*/ + CPM_FPU_FDZ = 2U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FDZCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FDZC Status*/ + CPM_FPU_FUF = 4U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FUFCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FUFC Status*/ + CPM_FPU_FOF = 8U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FOFCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FOFC Status*/ + CPM_FPU_FID = 16U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FIDCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FIDC Status*/ + CPM_FPU_FIX = 32U /*!< in function CPM_FpuIntMode, set CPM_FISCR FIXCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FIXC Status*/ +} FPU_IntType; + + +/** @brief Cpm return type. */ + +typedef enum +{ + CPM_STATUS_SUCCESS = 0U, /*!< CPM status success */ + CPM_STATUS_PARAM_INVALID = 1U /*!< CPM status parameter invalid */ +} CPM_RetType; + +/** + * @brief Get the value of CPM FISCR. + * + * This function returns FISCR value. + * + * @return uint32_t the value of the FISCR register. + */ +LOCAL_INLINE uint32_t CPM_HWA_GetFiscr(void) +{ + return CPM->FISCR; +} + +/** + * @brief Return CPM_FISCR FIOC value + * + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFiocFlag(void) +{ + uint32_t u32TmpVal = CPM->FISCR; + u32TmpVal = (u32TmpVal & CPM_FISCR_FIOC_MASK) >> CPM_FISCR_FIOC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FDZC value + * + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFdzcFlag(void) +{ + uint32_t u32TmpVal = CPM->FISCR; + u32TmpVal = (u32TmpVal & CPM_FISCR_FDZC_MASK) >> CPM_FISCR_FDZC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FOFC value + * + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFofcFlag(void) +{ + uint32_t u32TmpVal = CPM->FISCR; + u32TmpVal = (u32TmpVal & CPM_FISCR_FOFC_MASK) >> CPM_FISCR_FOFC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FUFC value + * + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFufcFlag(void) +{ + uint32_t u32TmpVal = CPM->FISCR; + u32TmpVal = (u32TmpVal & CPM_FISCR_FUFC_MASK) >> CPM_FISCR_FUFC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FIXC value + * + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFixcFlag(void) +{ + uint32_t u32TmpVal = CPM->FISCR; + u32TmpVal = (u32TmpVal & CPM_FISCR_FIXC_MASK) >> CPM_FISCR_FIXC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FIDC value + * + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFidcFlag(void) +{ + uint32_t u32TmpVal = CPM->FISCR; + u32TmpVal = (u32TmpVal & CPM_FISCR_FIDC_MASK) >> CPM_FISCR_FIDC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set FIOCE interrupt + * + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFioceInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FIOCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIOCE_SHIFT)); +} + +/** + * @brief Set FDZCE interrupt + * + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFdzceInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FDZCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FDZCE_SHIFT)); +} + +/** + * @brief Set FOFCE interrupt + * + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFofceInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FOFCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FOFCE_SHIFT)); +} + +/** + * @brief Set FUFCE interrupt + * + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFufceInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FUFCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FUFCE_SHIFT)); +} + +/** + * @brief Set FIXCE interrupt + * + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFixceInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FIXCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIXCE_SHIFT)); +} + +/** + * @brief Set FIDCE interrupt + * + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFidceInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FIDCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIDCE_SHIFT)); +} + +/** + * @brief Set FISCR value + * + * @param u32Val the value want to set the register + */ +LOCAL_INLINE void CPM_HWA_SetFiscr(uint32_t u32Val) +{ + CPM->FISCR = u32Val; +} + +/** + * @brief Get the value of CPM TCMRCR. + * + * This function returns TCMRCR value. + * + * @return uint32_t the value of the TCMRCR register. + */ +LOCAL_INLINE uint32_t CPM_HWA_GetTcmrcr(void) +{ + return CPM->TCMRCR; +} + +/** + * @brief Set DTCM1 retry buffer force clear + * + * @param bEnable 1:Force clear DTCM1 retry buffer 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetDTCM1BufClear(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D1RBCLR_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D1RBCLR_SHIFT)); +} + +/** + * @brief Set DTCM0 retry buffer force clear + * + * @param bEnable 1:Force clear DTCM0 retry buffer 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetDTCM0BufClear(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D0RBCLR_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D0RBCLR_SHIFT)); +} + +/** + * @brief Set ITCM retry buffer force clear + * + * @param bEnable 1:Force clear ITCM retry buffer 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetITCMBufClear(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_IRBCLR_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_IRBCLR_SHIFT)); +} + +/** + * @brief Set DTCM1 retry buffer invalid + */ +LOCAL_INLINE void CPM_HWA_SetDTCM1BufInvalid(void) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D1RBVLD_MASK)) | (1U << CPM_TCMRCR_D1RBCLR_SHIFT)); +} + +/** + * @brief Set DTCM0 retry buffer invalid + */ +LOCAL_INLINE void CPM_HWA_SetDTCM0BufInvalid(void) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D0RBVLD_MASK)) | (1U << CPM_TCMRCR_D0RBCLR_SHIFT)); +} + +/** + * @brief Set ITCM retry buffer invalid + */ +LOCAL_INLINE void CPM_HWA_SetITCMBufInvalid(void) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_IRBVLD_MASK)) | (1U << CPM_TCMRCR_IRBCLR_SHIFT)); +} + +/** + * @brief Set DTCM1 retry buffer timeout interrupt enable + * + * @param bEnable 1:Interrupt enable 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetDTCM1TimeoutInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D1RBIE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D1RBIE_SHIFT)); +} + +/** + * @brief Set DTCM0 retry buffer timeout interrupt enable + * + * @param bEnable 1:Interrupt enable 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetDTCM0TimeoutInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D0RBIE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D0RBIE_SHIFT)); +} + +/** + * @brief Set ITCM retry buffer timeout interrupt enable + * + * @param bEnable 1:Interrupt enable 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetITCMTimeoutInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_IRBIE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_IRBIE_SHIFT)); +} + +/** + * @brief Set DTCM1 retry buffer autoclear + * + * @param bEnable 1:Enable autoclear 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetDTCM1AutoClear(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D1RBAC_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D1RBAC_SHIFT)); +} + +/** + * @brief Set DTCM0 retry buffer autoclear + * + * @param bEnable 1:Enable autoclear 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetDTCM0AutoClear(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D0RBAC_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D0RBAC_SHIFT)); +} + +/** + * @brief Set ITCM retry buffer autoclear + * + * @param bEnable 1:Enable autoclear 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetITCMAutoClear(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_IRBAC_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_IRBAC_SHIFT)); +} + +/** @}*/ + +#endif /* HWA_INCLUDE_HWA_CPM_H_ */ diff --git a/Inc/HwA_crc.h b/Inc/HwA_crc.h new file mode 100644 index 0000000..8877410 --- /dev/null +++ b/Inc/HwA_crc.h @@ -0,0 +1,313 @@ +/** + * @file HwA_crc.h + * @author Flagchip + * @brief FC7xxx CRC hardware access layer + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240 + ******************************************************************************** */ + + +#ifndef _HWA_CRC_H_ +#define _HWA_CRC_H_ + +#include "device_header.h" + + +/********* Local typedef ************/ + +/** + * @brief The data swap for write + */ +typedef enum{ + WRITE_DATASWAP_NONE = 0U, /*!< none data swap for write */ + WRITE_DATASWAP_BIT = 1U, /*!< only bits data swap for write */ + WRITE_DATASWAP_BIT_BYTE = 2U, /*!< both bits and bytes data swap for write */ + WRITE_DATASWAP_BYTE = 3U /*!< only bytes data swap for write */ +} CRC_WriteDataSwapType; + +/** + * @brief The data swap for read + */ +typedef enum{ + READ_DATASWAP_NONE = 0U, /*!< none data swap for read */ + READ_DATASWAP_BIT = 1U, /*!< only bits data swap for read */ + READ_DATASWAP_BIT_BYTE = 2U, /*!< both bits and bytes data swap for read */ + READ_DATASWAP_BYTE = 3U /*!< only bytes data swap for read */ +} CRC_ReadDataSwapType; + +/** + * @brief The complement of reading crc data + */ +typedef enum{ + READ_DATA_NORMAL = 0U, /*!< none complement of reading crc data */ + READ_DATA_FXOR = 1U /*!< Invert or complement with 0xFFFFFFFF or 0xFFFF of crc data */ +} CRC_ReadDataFXORType; + +/** + * @brief The command type of write crc data or seed value + */ +typedef enum{ + WRITE_COMMAND_DATA = 0U, /*!< write crc data */ + WRITE_COMMAND_SEED = 1U /*!< write seed value(used to initialization crc calculation) */ +} CRC_WriteCommondType; + +/** + * @brief The crc mode select + */ +typedef enum{ + CRC_BIT_16 = 0U, /*!< crc 16 bit is selected */ + CRC_BIT_32 = 1U, /*!< crc 32 bit is selected */ + CRC_BIT_8 = 2U, + CRC_BIT_INVALID = 3U +} CRC_BitWidthType; + + +/********* Local inline function ************/ + +/** + * @brief set CRC CR register for writing data or seed + * + * @param pCrc CRC instance + * @param u32Mod WAS mode + */ +LOCAL_INLINE void CRC_HWA_SetDataOrSeed(CRC_Type *const pCrc, CRC_WriteCommondType u32Mod) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_WAS_MASK)) | CRC_CR_WAS(u32Mod)); +} + +/** + * @brief set polynomial value + * + * @param pCrc CRC instance + * @param u32Poly the polynomial value + */ +LOCAL_INLINE void CRC_HWA_SetPolyVal(CRC_Type *const pCrc, uint32_t u32Poly) +{ + pCrc->POLY = u32Poly; +} + +/** + * @brief set data register(32 bits) + * + * @param pCrc CRC instance + * @param u32Data data to be set + */ +LOCAL_INLINE void CRC_HWA_SetData_U32(CRC_Type *const pCrc, uint32_t u32Data) +{ + pCrc->DATA.uDATA = u32Data; +} + +/** + * @brief set data register(16 bits) + * + * @param pCrc CRC instance + * @param u16Data data to be set + */ +LOCAL_INLINE void CRC_HWA_SetData_U16(CRC_Type *const pCrc, uint16_t u16Data) +{ + pCrc->DATA.tDATA_16.L = u16Data; +} + +/** + * @brief set data register(low 8 bits) + * + * @param pCrc CRC instance + * @param u8Data data to be set + */ +LOCAL_INLINE void CRC_HWA_SetData_U8(CRC_Type *const pCrc, uint8_t u8Data) +{ + pCrc->DATA.tDATA_8.LL = u8Data; +} + +/** + * @brief get data register(32 bits) + * + * @param pCrc CRC instance + * + * @return 32-bit value + */ +LOCAL_INLINE uint32_t CRC_HWA_GetData_U32(CRC_Type *const pCrc) +{ + return (pCrc->DATA.uDATA); +} + +/** + * @brief get data register(high 8 bits) + * + * @param pCrc CRC instance + * + * @return high 8-bit value + */ +LOCAL_INLINE uint8 CRC_HWA_GetData_U8_H(CRC_Type *const pCrc) +{ + return (pCrc->DATA.tDATA_8.HL); +} + +/** + * @brief get data register(low 8 bits) + * + * @param pCrc CRC instance + * + * @return low 8-bit value + */ +LOCAL_INLINE uint8 CRC_HWA_GetData_U8_L(CRC_Type *const pCrc) +{ + return (pCrc->DATA.tDATA_8.LL); +} + +/** + * @brief get data register(high 16 bits) + * + * @param pCrc CRC instance + * + * @return high 16-bit value + */ +LOCAL_INLINE uint16_t CRC_HWA_GetData_U16_H(CRC_Type *const pCrc) +{ + return (pCrc->DATA.tDATA_16.H); +} + +/** + * @brief get data register(low 16 bits) + * + * @param pCrc CRC instance + * + * @return low 16-bit value + */ +LOCAL_INLINE uint16_t CRC_HWA_GetData_U16_L(CRC_Type *const pCrc) +{ + return (pCrc->DATA.tDATA_16.L); +} + +/** + * @brief set data swap for writes + * + * @param pCrc CRC instance + * @param eWrDataSwap the CRC_WriteDataSwapType type + */ +LOCAL_INLINE void CRC_HWA_SetWriteDataSwap(CRC_Type *const pCrc, CRC_WriteDataSwapType eWrDataSwap) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_DSW_MASK)) | CRC_CR_DSW(eWrDataSwap)); +} + +/** + * @brief set data swap for read + * + * @param pCrc CRC instance + * @param eRdDataSwap the eRdDataSwap type + */ +LOCAL_INLINE void CRC_HWA_SetReadDataSwap(CRC_Type *const pCrc, CRC_ReadDataSwapType eRdDataSwap) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_DSR_MASK)) | CRC_CR_DSR(eRdDataSwap)); +} + +/** + * @brief set complement read Of CRC data + * + * @param pCrc CRC instance + * @param eRdDataFXOR the CRC_ReadDataFXORType type + */ +LOCAL_INLINE void CRC_HWA_SetReadDataFXOR(CRC_Type *const pCrc, CRC_ReadDataFXORType eRdDataFXOR) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_FXOR_MASK)) | CRC_CR_FXOR(eRdDataFXOR)); +} + +/** + * @brief set width of CRC protocol + * + * @param pCrc CRC instance + * @param eWidth the CRC_BitWidthType type + */ +LOCAL_INLINE void CRC_HWA_SetBitWidth(CRC_Type *const pCrc, CRC_BitWidthType eWidth) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_TCRC_MASK)) | CRC_CR_TCRC(eWidth)); +} + +/** + * @brief set width of CRC protocol + * + * @param pCrc CRC instance + * @param eWidth the CRC_BitWidthType type + */ +LOCAL_INLINE void CRC_HWA_Set_8Bit_Width(CRC_Type *const pCrc, CRC_BitWidthType eWidth) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_TCRC8_MASK)) | CRC_CR_TCRC8(eWidth)); +} + +/** + * @brief get width of CRC protocol + * + * @param pCrc CRC instance + */ +LOCAL_INLINE CRC_BitWidthType CRC_HWA_GetBitWidth(CRC_Type *const pCrc) +{ + uint32_t u32TempVal = (pCrc->CR & ((uint32_t)CRC_CR_TCRC_MASK)) >> CRC_CR_TCRC_SHIFT; + return ((u32TempVal == 0U)?CRC_BIT_16:CRC_BIT_32); +} + +/** + * @brief get 8-bit width of CRC protocol + * + * @param pCrc CRC instance + */ +LOCAL_INLINE CRC_BitWidthType CRC_HWA_Get8BitWidth(CRC_Type *const pCrc) +{ + uint32 u32TempVal = (pCrc->CR & ((uint32)CRC_CR_TCRC8_MASK)) >> CRC_CR_TCRC8_SHIFT; + return ((u32TempVal == 1U)?CRC_BIT_8:CRC_BIT_INVALID); +} + +/** + * @brief get data swap type for read + * + * @param pCrc CRC instance + */ +LOCAL_INLINE CRC_ReadDataSwapType CRC_HWA_GetReadDataSwap(CRC_Type *const pCrc) +{ + CRC_ReadDataSwapType eRet = READ_DATASWAP_NONE; + uint32_t u32TempVal; + + u32TempVal = (pCrc->CR & ((uint32_t)CRC_CR_DSR_MASK))>>CRC_CR_DSR_SHIFT; + if (u32TempVal == 0U) + { + eRet = READ_DATASWAP_NONE; + } + else if (u32TempVal == 1U) + { + eRet = READ_DATASWAP_BIT; + } + else if (u32TempVal == 2U) + { + eRet = READ_DATASWAP_BIT_BYTE; + } + else if (u32TempVal == 3U) + { + eRet = READ_DATASWAP_BYTE; + } + else + { + /*Noting to do*/ + } + return eRet; +} + + + + +#endif /* #ifndef _HWA_CRC_H_ */ diff --git a/Inc/HwA_csc.h b/Inc/HwA_csc.h new file mode 100644 index 0000000..c346294 --- /dev/null +++ b/Inc/HwA_csc.h @@ -0,0 +1,1705 @@ +/** + * @file HwA_csc.h + * @author Flagchip085 + * @brief Hardware access layer for CSC + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_CSC_H_ +#define _HWA_CSC_H_ + +#include "device_header.h" + +#define CSC_STOP_PERIPH_GROUP_MAX 3U + +#define CSC_STOP_PERIPH_GROUP0_MASK (CSC0_STOP_MODER0_MASK & 0x00FFFFFFU) + +#define CSC_STOP_PERIPH_GROUP1_MASK (CSC0_STOP_MODER1_MASK & 0x00FFFFFFU) + +#define CSC_STOP_PERIPH_GROUP2_MASK (CSC0_STOP_MODER2_MASK & 0x00FFFFFFU) + +#define CSC_SMU_CTRL_GROUP0_MASK (CSC0_SMU_CTRL0_MASK & 0xFFFFFFFEU) + +#define CSC_SMU_CTRL_GROUP1_MASK (CSC0_SMU_CTRL1_MASK & 0xFFFFFFFEU) + +#define CSC_SMU_CTRL_GROUP4_MASK (CSC0_SMU_CTRL4_MASK & 0xFFFFFFFEU) + +#define CSC_SMU_CTRL_GROUP5_MASK (CSC0_SMU_CTRL5_MASK & 0xFFFFFFFEU) + + +/********* Local typedef ************/ + +/** + * @brief Control cpu type + * + */ +typedef enum +{ + CSC_WP_CPU_ALL = 0U, /*!< All CPUs are allowed to write this peripheral */ + CSC_WP_CPU_0 = 1U, /*!< Only CPU0 is allowed to control this peripheral */ + CSC_WP_CPU_NONE = 2U /*!< No CPU is allowed to control this peripheral */ +} CSC_WPB_CpuType; + +/** + * @brief Hand shake mode type + * + */ +typedef enum +{ + CSC_WAIT_ALL_ACK = 0U, /*!< follow other master stop acknowledge state */ + CSC_WAIT_REQ_ACK = 3U /*!< follow cpu stop acknowledge state */ +} CSC_HandShakeModeType; + +/** + * @brief CSC0 clock out divide ratio type + * + */ +typedef enum +{ + CSC0_CLKOUT_DIV_BY1 = 0U, /*!< Divided by 1 */ + CSC0_CLKOUT_DIV_BY2 = 1U, /*!< Divided by 2 */ + CSC0_CLKOUT_DIV_BY3 = 2U, /*!< Divided by 3 */ + CSC0_CLKOUT_DIV_BY4 = 3U, /*!< Divided by 4 */ + CSC0_CLKOUT_DIV_BY5 = 4U, /*!< Divided by 5 */ + CSC0_CLKOUT_DIV_BY6 = 5U, /*!< Divided by 6 */ + CSC0_CLKOUT_DIV_BY7 = 6U, /*!< Divided by 7 */ + CSC0_CLKOUT_DIV_BY8 = 7U /*!< Divided by 8 */ +} CSC0_ClockOutDivType; + +/** + * @brief CSC0 clock out source type + * + */ +typedef enum +{ + CSC0_CLKOUT_SCG_CLKOUT = 0U, /*!< SCG CLKOUT */ + CSC0_CLKOUT_FOSC_DIVM_CLK = 2U, /*!< FOSC DIVM CLK */ + CSC0_CLKOUT_SLOW_CLK = 3U, /*!< SLOW CLK */ + CSC0_CLKOUT_SIRC_DIVM_CLK = 4U, /*!< SIRC DIVM CLK */ + CSC0_CLKOUT_PLL1_DIVM_CLK = 5U, /*!< PLL1 DIVM CLK */ + CSC0_CLKOUT_FIRC_DIVM_CLK = 6U, /*!< FIRC DIVM CLK */ + CSC0_CLKOUT_CORE_CLK = 7U, /*!< CORE CLK */ + CSC0_CLKOUT_PLL0_DIVM_CLK = 8U, /*!< PLL0 DIVM CLK */ + CSC0_CLKOUT_BUS_CLK = 9U, /*!< BUS CLK */ + CSC0_CLKOUT_SIRC_128K_CLK = 10U, /*!< SIRC 128K CLK */ + CSC0_CLKOUT_AON_CLK = 12U, /*!< AON CLK */ + CSC0_CLKOUT_RTC_CLK = 14U /*!< RTC CLK */ +} CSC0_ClockOutSrcType; + +/** + * @brief Data type for CSC0_AONCLKSR[32KAONCLKSEL], set AON32KCLK source clock + * + */ +typedef enum +{ + CSC0_AON32K_SIRCDIV_32K_CLK = 1U, /*!< CSC0_AONCLKSR[32KAONCLKSEL], SIRCDIV_32K */ + CSC0_AON32K_SOSC32K_CLK = 2U, /*!< CSC0_AONCLKSR[32KAONCLKSEL], SOSC32K */ + CSC0_AON32K_SIRC32K_CLK = 3U /*!< CSC0_AONCLKSR[32KAONCLKSEL], SIRC32K */ +} CSC0_AON32KClkSrcType; + +/** + * @brief Data type for CSC0_RTCCLKSEL[RTCCLKSEL], set RTCCLK source clock + * + */ +typedef enum +{ + CSC0_RTC_FOSCDIVL_CLK = 0U, /*!< CSC0_RTCCLKSEL[RTCCLKSEL], FOSC_DIVL */ + CSC0_RTC_SIRCDIV_32K_CLK = 1U, /*!< CSC0_RTCCLKSEL[RTCCLKSEL], SIRC_DIV */ + CSC0_RTC_SOSC_CLK = 2U, /*!< CSC0_RTCCLKSEL[RTCCLKSEL], SOSC */ + CSC0_RTC_SIRC32K_CLK = 3U /*!< CSC0_RTCCLKSEL[RTCCLKSEL], SIRC_32K */ +} CSC0_RTCClkSrcType; + +/** + * @brief Data type for CSC0_AONCLKSEL[AONCLKSEL], set AONCLK source clock + * + */ +typedef enum +{ + CSC0_AON_SIRCDIV_128K_CLK = 0U, /*!< CSC0_AONCLKSEL[AONCLKSEL], SIRCDIV_128K */ + CSC0_AON_SIRC32K_CLK = 1U, /*!< CSC0_AONCLKSEL[AONCLKSEL], SIRC32K */ + CSC0_AON_SIRCDIV_32K_CLK = 2U, /*!< CSC0_AONCLKSEL[AONCLKSEL], SIRCDIV_32K */ + CSC0_AON_SIRC32_1K_CLK = 3U /*!< CSC0_AONCLKSEL[AONCLKSEL], SIRC32_1K */ +} CSC0_AONClkSrcType; + + +/** + * @brief Register 0 related peripheral(CSC0,CSC1,CSC2) + */ +typedef enum +{ + CSC_STOPMODE_FLEXCAN1 = (int)CSC0_STOP_MODER0_FLEXCAN1_MASK, /*!< Stop acknowledge function FLEXCAN1 */ + CSC_STOPMODE_FLEXCAN0 = (int)CSC0_STOP_MODER0_FLEXCAN0_MASK, /*!< Stop acknowledge function FLEXCAN0 */ + CSC_STOPMODE_FREQM = (int)CSC0_STOP_MODER0_FREQM_MASK, /*!< Stop acknowledge function FREQM */ + CSC_STOPMODE_FCUART3 = (int)CSC0_STOP_MODER0_FCUART3_MASK, /*!< Stop acknowledge function FCUART3 */ + CSC_STOPMODE_FCUART2 = (int)CSC0_STOP_MODER0_FCUART2_MASK, /*!< Stop acknowledge function FCUART2 */ + CSC_STOPMODE_FCUART1 = (int)CSC0_STOP_MODER0_FCUART1_MASK, /*!< Stop acknowledge function FCUART1 */ + CSC_STOPMODE_FCSPI2 = (int)CSC0_STOP_MODER0_FCSPI2_MASK, /*!< Stop acknowledge function FCSPI2 */ + CSC_STOPMODE_FCSPI1 = (int)CSC0_STOP_MODER0_FCSPI1_MASK, /*!< Stop acknowledge function FCSPI1 */ + CSC_STOPMODE_SENT0 = (int)CSC0_STOP_MODER0_SENT0_MASK, /*!< Stop acknowledge function SENT0 */ + CSC_STOPMODE_TMU = (int)CSC0_STOP_MODER0_TMU_MASK, /*!< Stop acknowledge function TMU */ + CSC_STOPMODE_ADC1 = (int)CSC0_STOP_MODER0_ADC1_MASK, /*!< Stop acknowledge function ADC1 */ + CSC_STOPMODE_ADC0 = (int)CSC0_STOP_MODER0_ADC0_MASK, /*!< Stop acknowledge function ADC0 */ + CSC_STOPMODE_CMU4 = (int)CSC0_STOP_MODER0_CMU4_MASK, /*!< Stop acknowledge function CMU4 */ + CSC_STOPMODE_WDOG0 = (int)CSC0_STOP_MODER0_WDOG0_MASK, /*!< Stop acknowledge function WDG0 */ + CSC_STOPMODE_ISM0 = (int)CSC0_STOP_MODER0_ISM0_MASK, /*!< Stop acknowledge function ISM0 */ + CSC_STOPMODE_DMA0 = (int)CSC0_STOP_MODER0_DMA0_MASK /*!< Stop acknowledge function DMA0 */ +} CSCx_Reg0_PeriphType; + +/** + * @brief Register 1 related peripheral(CSC0,CSC1,CSC2) + */ +typedef enum +{ + CSC_STOPMODE_FLEXCAN3 = (int)CSC0_STOP_MODER1_FLEXCAN3_MASK, /*!< Stop acknowledge function FLEXCAN3 */ + CSC_STOPMODE_FLEXCAN2 = (int)CSC0_STOP_MODER1_FLEXCAN2_MASK, /*!< Stop acknowledge function FLEXCAN2 */ + CSC_STOPMODE_MSC0 = (int)CSC0_STOP_MODER1_MSC0_MASK, /*!< Stop acknowledge function MSC0 */ + CSC_STOPMODE_FCUART7 = (int)CSC0_STOP_MODER1_FCUART7_MASK, /*!< Stop acknowledge function FCUART7 */ + CSC_STOPMODE_FCUART6 = (int)CSC0_STOP_MODER1_FCUART6_MASK, /*!< Stop acknowledge function FCUART6 */ + CSC_STOPMODE_FCUART5 = (int)CSC0_STOP_MODER1_FCUART5_MASK, /*!< Stop acknowledge function FCUART5 */ + CSC_STOPMODE_FCUART4 = (int)CSC0_STOP_MODER1_FCUART4_MASK, /*!< Stop acknowledge function FCUART4 */ + CSC_STOPMODE_FCIIC1 = (int)CSC0_STOP_MODER1_FCIIC1_MASK, /*!< Stop acknowledge function FCIIC1 */ + CSC_STOPMODE_FCSPI5 = (int)CSC0_STOP_MODER1_FCSPI5_MASK, /*!< Stop acknowledge function FCSPI5 */ + CSC_STOPMODE_FCSPI4 = (int)CSC0_STOP_MODER1_FCSPI4_MASK, /*!< Stop acknowledge function FCSPI4 */ + CSC_STOPMODE_FCSPI3 = (int)CSC0_STOP_MODER1_FCSPI3_MASK, /*!< Stop acknowledge function FCSPI3 */ + CSC_STOPMODE_WDOG1 = (int)CSC0_STOP_MODER1_WDOG1_MASK, /*!< Stop acknowledge function WDOG1 */ +} CSCx_Reg1_PeriphType; + +/** + * @brief Regsister 2 related peripheral(CSC0,CSC1,CSC2) + */ +typedef enum +{ + CSC_STOPMODE_FCUART0 = (int)CSC0_STOP_MODER2_FCUART0_MASK, /*!< Stop acknowledge function FCUART0 */ + CSC_STOPMODE_FCIIC0 = (int)CSC0_STOP_MODER2_FCIIC0_MASK, /*!< Stop acknowledge function FCIIC0 */ + CSC_STOPMODE_FCSPI0 = (int)CSC0_STOP_MODER2_FCSPI0_MASK, /*!< Stop acknowledge function FCSPI0 */ + CSC_STOPMODE_CMP1 = (int)CSC0_STOP_MODER2_CMP1_MASK, /*!< Stop acknowledge function CMP1 */ + CSC_STOPMODE_CMP0 = (int)CSC0_STOP_MODER2_CMP0_MASK, /*!< Stop acknowledge function CMP0 */ + CSC_STOPMODE_CMU3 = (int)CSC0_STOP_MODER2_CMU3_MASK, /*!< Stop acknowledge function CMU3 */ + CSC_STOPMODE_CMU2 = (int)CSC0_STOP_MODER2_CMU2_MASK, /*!< Stop acknowledge function CMU2 */ + CSC_STOPMODE_CMU1 = (int)CSC0_STOP_MODER2_CMU1_MASK, /*!< Stop acknowledge function CMU1 */ + CSC_STOPMODE_CMU0 = (int)CSC0_STOP_MODER2_CMU0_MASK /*!< Stop acknowledge function CMU0 */ +} CSCx_Reg2_PeriphType; + +/** + * @brief CCM stop clock type(CSC0,CSC1,CSC2) + */ +typedef enum +{ + CSC_CCM_STOPCLOCK_STATUS_SYS_SLAVE = (int)CSC0_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_MASK, /*!< System Slave Clock */ + CSC_CCM_STOPCLOCK_STATUS_MASTER = (int)CSC0_CCM0_STATUS_CPU0_STOP_MASTER_MASK, /*!< Master Clock */ + CSC_CCM_STOPCLOCK_STATUS_SLOW_SLAVE = (int)CSC0_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_MASK, /*!< Slave Clock */ + CSC_CCM_STOPCLOCK_STATUS_BUS_SLAVE = (int)CSC0_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_MASK /*!< Bus Slave Clock */ +} CSCx_CCM_StopClockType; + +/** + * @brief CSC0 SMU control group 0 + */ +typedef enum +{ + CSC_SMU_CMU4 = (int)CSC0_SMU_CTRL0_CMU4_MASK, /*!< CMU4 to FCSMU */ + CSC_SMU_PMC_MON = (int)CSC0_SMU_CTRL0_PMC_MON_MASK, /*!< PMC Monitor to FCSMU */ + CSC_SMU_CMU2 = (int)CSC0_SMU_CTRL0_CMU2_MASK, /*!< CMU2 to FCSMU */ + CSC_SMU_CMU1 = (int)CSC0_SMU_CTRL0_CMU1_MASK, /*!< CMU1 to FCSMU */ + CSC_SMU_PMC_LVD_HVD = (int)CSC0_SMU_CTRL0_PMC_LVD_HVD_MASK, /*!< PMC HVD/LVD to FCSMU */ + CSC_SMU_SRAM1_MON = (int)CSC0_SMU_CTRL0_SRAM1_MON_MASK, /*!< SRAM1 Decoder Monitor to FCSMU */ + CSC_SMU_SRAM0_MON = (int)CSC0_SMU_CTRL0_SRAM0_MON_MASK, /*!< SRAM0 Decoder Monitor to FCSMU */ + CSC_SMU_MCM = (int)CSC0_SMU_CTRL0_CPM_MON_MASK, /*!< CPU Private Module Monitor to FCSMU */ + CSC_SMU_MAM0_S5_DS_ECC = (int)CSC0_SMU_CTRL0_MAM0_S5_DS_ECC_MASK, /*!< MAM0 S5 Downsize ECC to FCSMU */ + CSC_SMU_MAM0_S8_DS = (int)CSC0_SMU_CTRL0_MAM0_S8_DS_MASK, /*!< MAM0 S8 Downsize Monitor to FCSMU */ + CSC_SMU_MAM0_S5_DS = (int)CSC0_SMU_CTRL0_MAM0_S5_DS_MASK, /*!< MAM0 S5 Downsize Monitor to FCSMU */ + CSC_SMU_DMA0 = (int)CSC0_SMU_CTRL0_DMA0_MASK, /*!< DMA0 ECC to FCSMU */ + CSC_SMU_HSM = (int)CSC0_SMU_CTRL0_HSM_MASK, /*!< HSM ECC to FCSMU */ + CSC_SMU_MAM0_S2F_MON = (int)CSC0_SMU_CTRL0_MAM0_S2F_MON_MASK, /*!< MAM0 S5 Slow to Fast AHBS Monitor to FCSMU */ + CSC_SMU_CPU0_AHBS = (int)CSC0_SMU_CTRL0_CPU0_AHBS_MASK, /*!< CPU0_AHBS ECC to FCSMU */ + CSC_SMU_MAM0_S8 = (int)CSC0_SMU_CTRL0_MAM0_S8_MASK, /*!< MAM0 S8 ECC to FCSMU */ + CSC_SMU_MAM0_S7 = (int)CSC0_SMU_CTRL0_MAM0_S7_MASK, /*!< MAM0 S7 ECC to FCSMU */ + CSC_SMU_MAM0_S6 = (int)CSC0_SMU_CTRL0_MAM0_S6_MASK, /*!< MAM0 S6 ECC to FCSMU */ + CSC_SMU_MAM0_S5 = (int)CSC0_SMU_CTRL0_MAM0_S5_MASK, /*!< MAM0 S5 ECC to FCSMU */ + CSC_SMU_MAM0_S4 = (int)CSC0_SMU_CTRL0_MAM0_S4_MASK, /*!< MAM0 S4 ECC to FCSMU */ + CSC_SMU_MAM0_S3 = (int)CSC0_SMU_CTRL0_MAM0_S3_MASK, /*!< MAM0 S3 ECC to FCSMU */ + CSC_SMU_MAM0_S2 = (int)CSC0_SMU_CTRL0_MAM0_S2_MASK, /*!< MAM0 S2 ECC to FCSMU */ + CSC_SMU_MAM0_S1 = (int)CSC0_SMU_CTRL0_MAM0_S1_MASK, /*!< MAM0 S1 ECC to FCSMU */ + CSC_SMU_MAM0_S0 = (int)CSC0_SMU_CTRL0_MAM0_S0_MASK /*!< MAM0 S0 ECC to FCSMU */ +} CSC_SMU_CtrlGrp0Type; + +/** + * @brief CSC0 SMU control group of CPUx(group1~3) + */ +typedef enum +{ + CSC_SMU_DTCM1_S_EN = (int)CSC0_SMU_CTRL1_CPU0_DTCM1_S_EN_MASK, /*!< CPU0 DTCM1 Single Bit Data to FCSMU */ + CSC_SMU_DTCM0_S_EN = (int)CSC0_SMU_CTRL1_CPU0_DTCM0_S_EN_MASK, /*!< CPU0 DTCM0 Single Bit Data to FCSMU */ + CSC_SMU_ITCM_S_EN = (int)CSC0_SMU_CTRL1_CPU0_ITCM_S_EN_MASK, /*!< CPU0 ITCM Single Bit Data to FCSMU */ + CSC_SMU_OVERLAY = (int)CSC0_SMU_CTRL1_CPU0_OVERLAY_MASK, /*!< CPU0 Overlay to FCSMU */ + CSC_SMU_DTCM1_MON = (int)CSC0_SMU_CTRL1_CPU0_DTCM1_MON_MASK, /*!< CPU0_DTCM1_MON to FCSMU */ + CSC_SMU_DTCM0_MON = (int)CSC0_SMU_CTRL1_CPU0_DTCM0_MON_MASK, /*!< CPU0_DTCM0_MON to FCSMU */ + CSC_SMU_ITCM_MON = (int)CSC0_SMU_CTRL1_CPU0_ITCM_MON_MASK, /*!< CPU0 ITCM Decoder Monitor to FCSMU */ + CSC_SMU_AHBM1_F2S = (int)CSC0_SMU_CTRL1_CPU0_AHBM1_F2S_MASK, /*!< CPU0 AHBM1 Fast to Slow Monitor to FCSMU */ + CSC_SMU_AHBM0_F2S = (int)CSC0_SMU_CTRL1_CPU0_AHBM0_F2S_MASK, /*!< CPU0 AHBM0 Fast to Slow Monitor to FCSMU */ + CSC_SMU_AHBP_F2S = (int)CSC0_SMU_CTRL1_CPU0_AHBP_F2S_MASK, /*!< CPU0 AHBP Fast to Slow Monito to FCSMU */ + CSC_SMU_DTCM1 = (int)CSC0_SMU_CTRL1_CPU0_DTCM1_MASK, /*!< CPU0 DTCM1 ECC to FCSMU */ + CSC_SMU_DTCM0 = (int)CSC0_SMU_CTRL1_CPU0_DTCM0_MASK, /*!< CPU0 DTCM0 ECC to FCSMU */ + CSC_SMU_ITCM = (int)CSC0_SMU_CTRL1_CPU0_ITCM_MASK, /*!< CPU0 ITCM ECC to FCSMU */ + CSC_SMU_DCACHE = (int)CSC0_SMU_CTRL1_CPU0_DCACHE_MASK, /*!< CPU0 Data CACHE to FCSMU */ + CSC_SMU_ICACHE = (int)CSC0_SMU_CTRL1_CPU0_ICACHE_MASK, /*!< CPU0 Code CACHE to FCSMU */ + CSC_SMU_AHBP = (int)CSC0_SMU_CTRL1_CPU0_AHBP_MASK, /*!< CPU0 AHBP ECC to FCSMU */ + CSC_SMU_AHBM = (int)CSC0_SMU_CTRL1_CPU0_AHBM_MASK /*!< CPU0 AHBM ECC to FCSMU */ +} CSC_SMU_Cpux_CtrlGrpType; + +/** + * @brief CSC0 SMU control group 4 + */ +typedef enum +{ + CSC_SMU_HSM_WDOG = (int)CSC0_SMU_CTRL4_HSM_WDOG_MASK, /*!< HSM WDOG Request Enable to FCSMU */ + CSC_SMU_FMC_ERR = (int)CSC0_SMU_CTRL4_FMC_ERR_MASK, /*!< FMC ECC Error Enable to FCSMU */ + CSC_SMU_ROM_S_EN = (int)CSC0_SMU_CTRL4_ROM_S_EN_MASK, /*!< ROM Single Bit Data Error Enable to FCSMU */ + CSC_SMU_SRAM1_EDC_MON_EN = (int)CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN_MASK, /*!< SRAM1_EDC Monitor Error Enable to FCSMU */ + CSC_SMU_SRAM0_EDC_MON_EN = (int)CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN_MASK, /*!< SRAM0_EDC Monitor Error Enable to FCSMU */ + CSC_SMU_SRAM1_S_EN = (int)CSC0_SMU_CTRL4_SRAM1_S_EN_MASK, /*!< SRAM1 Single Bit Data Error Enable to FCSMU */ + CSC_SMU_SRAM0_S_EN = (int)CSC0_SMU_CTRL4_SRAM0_S_EN_MASK, /*!< SRAM0 Single Bit Data Error Enable to FCSMU */ + CSC_SMU_FLASH_ECC_EN_S = (int)CSC0_SMU_CTRL4_FLASH_ECC_EN_S_MASK, /*!< FLASH Single Bit Error Enable to FCSMU */ + CSC_SMU_FLASH_ECC_EN = (int)CSC0_SMU_CTRL4_FLASH_ECC_EN_MASK, /*!< FLASH ECC Error Enable to FCSMU */ + CSC_SMU_AFCB1_MON = (int)CSC0_SMU_CTRL4_AFCB1_MON_MASK, /*!< AFCB1 Monitor Error Enable to FCSMU */ + CSC_SMU_AFCB0_MON = (int)CSC0_SMU_CTRL4_AFCB0_MON_MASK, /*!< AFCB0 Monitor Error Enable to FCSMU */ + CSC_SMU_SCF_RST = (int)CSC0_SMU_CTRL4_SCF_RST_EN_MASK, /*!< Self Check Feature Enable */ + CSC_SMU_SCF_IRQ = (int)CSC0_SMU_CTRL4_SCF_IRQ_EN_MASK, /*!< Self Check Feature Interrupt Request Enable */ + CSC_SMU_TMU = (int)CSC0_SMU_CTRL4_TMU_MASK, /*!< TMU Error Enable to FCSMU */ + CSC_SMU_SCM_CRC = (int)CSC0_SMU_CTRL4_SCM_CRC_MASK, /*!< SCM CRC Error Enable to FCSMU */ + CSC_SMU_SCG_CRC = (int)CSC0_SMU_CTRL4_SCG_CRC_MASK, /*!< SCG CRC Error Enable to FCSMU */ + CSC_SMU_SRAM1_ECC = (int)CSC0_SMU_CTRL4_SRAM1_ECC_MASK, /*!< SRAM1 ECC Error Enable to FCSMU */ + CSC_SMU_SRAM0_ECC = (int)CSC0_SMU_CTRL4_SRAM0_ECC_MASK, /*!< SRAM0 ECC Error Enable to FCSMU */ + CSC_SMU_MAM0_ERR = (int)CSC0_SMU_CTRL4_MAM0_ERR_MASK /*!< Matrix Access Monitor 0 Timeout Error Enable to FCSMU */ +} CSC_SMU_CtrlGrp4Type; + +/** + * @brief CSC0 SMU control group 5 + */ +typedef enum +{ + CSC_SMU_SRAM1_EDC = (int)CSC0_SMU_CTRL5_SRAM1_EDC_MASK, /*!< SRAM1 EDC Error Enable to FCSMU */ + CSC_SMU_SRAM0_EDC = (int)CSC0_SMU_CTRL5_SRAM0_EDC_MASK, /*!< SRAM0 EDC Error Enable to FCSMU */ + CSC_SMU_FLASH_EDC_P1_EN = (int)CSC0_SMU_CTRL5_FLASH_EDC_P1_EN_MASK,/*!< FLASH P1 EDC Error Enable to FCSMU */ + CSC_SMU_FLASH_EDC_P0_EN = (int)CSC0_SMU_CTRL5_FLASH_EDC_P0_EN_MASK,/*!< FLASH P0 EDC Error Enable to FCSMU */ + CSC_SMU_HSM_IRAM_S = (int)CSC0_SMU_CTRL5_HSM_IRAM_S_MASK, /*!< HSM IRAM Single Bit Data Error Enable to FCSMU */ + CSC_SMU_HSM_DRAM_S = (int)CSC0_SMU_CTRL5_HSM_DRAM_S_MASK, /*!< HSM DRAM Single Bit Data Error Enable to FCSMU */ + CSC_SMU_HSM_IRAM = (int)CSC0_SMU_CTRL5_HSM_IRAM_MASK, /*!< HSM IRAM ECC Error Enable to FCSMU */ + CSC_SMU_HSM_DRAM = (int)CSC0_SMU_CTRL5_HSM_DRAM_MASK, /*!< HSM DRAM ECC Error Enable to FCSMU */ + CSC_SMU_DMA0_ECC_S = (int)CSC0_SMU_CTRL5_DMA0_ECC_S_MASK, /*!< DMA0_CFG_ECC Single Bit Data Error Enable to FCSMU */ + CSC_SMU_DMA0_ECC = (int)CSC0_SMU_CTRL5_DMA0_ECC_MASK, /*!< DMA0 CFG ECC Error Enable to FCSMU */ + CSC_SMU_DMA0_LOCKSTEP = (int)CSC0_SMU_CTRL5_DMA0_LOCKSTEP_MASK, /*!< DMA0 lockstep Error Enable to FCSMU */ + CSC_SMU_FOSC_ERR = (int)CSC0_SMU_CTRL5_FOSC_ERR_MASK, /*!< FOSC Loss of Clock Error Enable to FCSMU */ + CSC_SMU_PLL1_ERR = (int)CSC0_SMU_CTRL5_PLL1_ERR_MASK, /*!< PLL1 Loss of Clock Error Enable to FCSMU */ + CSC_SMU_PLL0_ERR = (int)CSC0_SMU_CTRL5_PLL0_ERR_MASK, /*!< PLL0 Loss of Clock Error Enable to FCSMU */ + CSC_SMU_STCU_ERR = (int)CSC0_SMU_CTRL5_STCU_ERR_MASK, /*!< STCU Self Test Error Enable to FCSMU */ + CSC_SMU_NONUSER_ERR = (int)CSC0_SMU_CTRL5_NONUSER_ERR_MASK, /*!< STCU Non User Error Enable to FCSMU */ + CSC_SMU_NVR_ERR = (int)CSC0_SMU_CTRL5_NVR_ERR_MASK, /*!< NVR Error Enable to FCSMU */ +} CSC_SMU_CtrlGrp5Type; + +/** + * @brief CSC0 CMU control group + */ +typedef enum +{ + CSC_CMU_DMA0_CFG_S_EN_ADDR = (int)CSC0_CMU_CTRL_DMA0_CFG_S_EN_ADDR_MASK,/*!< Enable to Report Single Error When One Bit Address_ECC Error Inject */ + CSC_CMU_CMU3_FCSMU_RST = (int)CSC0_CMU_CTRL_CMU3_FCSMU_RST_MASK, /*!< CMU3 clcok error to assert reset request to RGM to reset System and FCSMU */ + CSC_CMU_CMU3_RST = (int)CSC0_CMU_CTRL_CMU3_RST_EN_MASK, /*!< CMU3 clock error to assert reset request to RGM to reset System */ + CSC_CMU_CMU4_LOC = (int)CSC0_CMU_CTRL_CMU4_LOC_EN_MASK /*!< Enable CMU4 Loss of clock error request to SCG */ +} CSC0_CMU_CtrlGrpType; + +/** + * @brief CSC0 Low Power Wakeup configuration group type + */ +typedef enum +{ + CSC_LP_WAKEUP_GROUP_0 = 0U, /*!< CSC0 Low Power Wakeup configuration group0 */ + CSC_LP_WAKEUP_GROUP_1 = 1U, /*!< CSC0 Low Power Wakeup configuration group1 */ + CSC_LP_WAKEUP_GROUP_2 = 2U, /*!< CSC0 Low Power Wakeup configuration group2 */ + CSC_LP_WAKEUP_GROUP_3 = 3U, /*!< CSC0 Low Power Wakeup configuration group3 */ + CSC_LP_WAKEUP_GROUP_4 = 4U /*!< CSC0 Low Power Wakeup configuration group4 */ +} CSC0_LPWakeupGrpType; + +/** + * @brief CSC0 Low Power Wakeup configuration source type + */ +typedef enum +{ + CSC_LP_WAKEUP_DISABLE = 0U, /*!< Disable */ + CSC_LP_WAKEUP_AONTIMER_TRIGGER = 1U, /*!< AONTIMER Trigger */ + CSC_LP_WAKEUP_RTC_TIME_ALARM = 2U, /*!< RTC Time Alarm */ + CSC_LP_WAKEUP_CPM0_OUTPUT = 3U, /*!< CPM0 output */ + CSC_LP_WAKEUP_CPM1_OUTPUT = 4U, /*!< CPM1 output */ + CSC_LP_WAKEUP_RESERVED = 5U, /*!< Reserved */ + CSC_LP_WAKEUP_PMC_RPM_ENTRY = 6U, /*!< PMC RPM Entry */ + CSC_LP_WAKEUP_WKU_INTERRUPT = 7U, /*!< WKU Interrupt */ + CSC_LP_WAKEUP_TSTMP0_PWM_TRIGGER0 = 8U, /*!< TSTMP0 PWM TRIGGER0 */ + CSC_LP_WAKEUP_TSTMP0_PWM_TRIGGER1 = 9U, /*!< TSTMP0 PWM TRIGGER1 */ + CSC_LP_WAKEUP_FCPIT0_PWM_TRIGGER0 = 10U, /*!< FCPT0 PWM TRIGGER0 */ + CSC_LP_WAKEUP_FCPIT0_PWM_TRIGGER1 = 11U, /*!< FCPT0 PWM TRIGGER1 */ + CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT0 = 12U, /*!< FCPIT0 Trigger out[0] */ + CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT1 = 13U, /*!< FCPIT0 Trigger out[1] */ + CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT2 = 14U, /*!< FCPIT0 Trigger out[2] */ + CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT3 = 15U /*!< FCPIT0 Trigger out[3] */ +} CSC0_LPWakeupSrcType; + +/** + * @brief CSC0 Low Power Wakeup polarity type + */ +typedef enum +{ + CSC_LP_WAKEUP_POL_KEEP = 0U, /*!< Keep the LP_WAKEUP CFGx */ + CSC_LP_WAKEUP_POL_INVERT = 1U, /*!< Invert the LP_WAKEUP CFGx */ +} CSC0_LPWakeupPolType; + + +/********* Local inline function ************/ +/****** Operation on CSC0_xxxRegister0 ******/ +/** + * @brief Lock the cpu to control stop mode register 0 + * + */ +LOCAL_INLINE void CSC0_HWA_MODER0_LockWritePermit(void) +{ + CSC0->STOP_MODER0 |= (uint32_t)CSC0_STOP_MODER0_WPB_LOCK_MASK; +} + +/** + * @brief Get the stop mode register 0 lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_MODER0_GetWPBLockStatus(void) +{ + return (CSC0->STOP_MODER0 & (uint32_t)CSC0_STOP_MODER0_WPB_LOCK_MASK); +} + +/** + * @brief Get the CPU type of writing permission + * + * @return CSC_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_MODER0_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((CSC0->STOP_MODER0 & (uint32_t)CSC0_STOP_MODER0_WPB_MASK)>>CSC0_STOP_MODER0_WPB_SHIFT); + return (CSC_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set cpu to control this stop mode register 0 + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_MODER0_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->STOP_MODER0; + CSC0->STOP_MODER0 = ((u32RegVal & (~(uint32_t)CSC0_STOP_MODER0_WPB_MASK)) | CSC0_STOP_MODER0_WPB(eCpuType)); +} + +/** + * @brief Enable the stop acknowledge function of register 0 group + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER0_EnableStopAck(CSCx_Reg0_PeriphType ePeriphType) +{ + CSC0->STOP_MODER0 |= (uint32_t)ePeriphType; +} + +/** + * @brief Disable the stop acknowledge function of register 0 group + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER0_DisableStopAck(CSCx_Reg0_PeriphType ePeriphType) +{ + CSC0->STOP_MODER0 &= ~(uint32_t)ePeriphType; +} + +/** + * @brief Set multiple stop ack enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg0_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_MODER0_SetMultiStopAck(uint32_t u32Value) +{ + CSC0->STOP_MODER0 = u32Value; +} + +/** + * @brief Clear multiple stop ack enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg0_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_MODER0_ClearMultiStopAck(uint32_t u32Value) +{ + CSC0->STOP_MODER0 = (CSC0->STOP_MODER0 & (~u32Value)); +} + +/** + * @brief Lock the cpu to control this stop request register 0 + * + * @param eLockType Cpu lock type + */ +LOCAL_INLINE void CSC0_HWA_REQR0_LockWritePermit(void) +{ + CSC0->STOP_REQR0 |= (uint32_t)CSC0_STOP_REQR0_WPB_LOCK_MASK; +} + +/** + * @brief Get the stop request register 0 lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_REQR0_GetWPBLockStatus(void) +{ + return (CSC0->STOP_REQR0 & (uint32_t)CSC0_STOP_REQR0_WPB_LOCK_MASK); +} + +/** + * @brief Get the CPU type of writing permission + * + * @return CSC_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_REQR0_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((CSC0->STOP_REQR0 & (uint32_t)CSC0_STOP_REQR0_WPB_MASK)>>CSC0_STOP_REQR0_WPB_SHIFT); + return (CSC_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set cpu to control stop request register 0 + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_REQR0_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->STOP_REQR0; + CSC0->STOP_REQR0 = ((u32RegVal & (~(uint32_t)CSC0_STOP_REQR0_WPB_MASK)) | CSC0_STOP_REQR0_WPB(eCpuType)); +} + +/** + * @brief Set stop request in register 0 + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_REQR0_SetStopRequest(CSCx_Reg0_PeriphType ePeriphType) +{ + CSC0->STOP_REQR0 |= (uint32_t)ePeriphType; +} + +/** + * @brief Clear stop request in register 0 + * + * @param ePeriphType Peripheral to be cleared + */ +LOCAL_INLINE void CSC0_HWA_REQR0_ClearStopRequest(CSCx_Reg0_PeriphType ePeriphType) +{ + CSC0->STOP_REQR0 &= ~(uint32_t)ePeriphType; +} + +/** + * @brief Set multiple stop request enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg0_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_REQR0_SetMultiStopRequest(uint32_t u32Value) +{ + CSC0->STOP_REQR0 = u32Value; +} + +/** + * @brief Clear stop request in register 0 + * + * @param u32Value the OR value of type CSCx_Reg0_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_REQR0_ClearMultiStopRequest(uint32_t u32Value) +{ + CSC0->STOP_REQR0 = (CSC0->STOP_REQR0 & (~u32Value)); +} + +/** + * @brief Get stop ack status in register 0 + * + * @param u32Value value to be set + * @return Stop ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_ACKR0_GetStopAckStatus(CSCx_Reg0_PeriphType ePeriphType) +{ + return (CSC0->STOP_ACKR0 & ((uint32_t)ePeriphType)); +} + +/** + * @brief Get multiple stop ack status in register 0 + * + * @param u32Value the OR value of type CSCx_Reg0_PeriphType + * @return Stop ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_ACKR0_GetMultiStopAckStatus(uint32_t u32Value) +{ + return (CSC0->STOP_ACKR0 & u32Value); +} + + + +/****** Operation on CSC0_xxxRegister1 ******/ +/** + * @brief Lock the cpu to control stop mode register 1 + * + */ +LOCAL_INLINE void CSC0_HWA_MODER1_LockWritePermit(void) +{ + CSC0->STOP_MODER1 |= (uint32_t)CSC0_STOP_MODER1_WPB_LOCK_MASK; +} + +/** + * @brief Get the stop mode register 1 lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_MODER1_GetWPBLockStatus(void) +{ + return (CSC0->STOP_MODER1 & (uint32_t)CSC0_STOP_MODER1_WPB_LOCK_MASK); +} + +/** + * @brief Set cpu to control this stop mode register 1 + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_MODER1_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->STOP_MODER1; + CSC0->STOP_MODER1 = ((u32RegVal & (~(uint32_t)CSC0_STOP_MODER1_WPB_MASK)) | CSC0_STOP_MODER1_WPB(eCpuType)); +} + +/** + * @brief Get the CPU type of writing permission + * + * @return CSC_WPB_CpuType The Cpu which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_MODER1_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((CSC0->STOP_MODER1 & (uint32_t)CSC0_STOP_MODER1_WPB_MASK)>>CSC0_STOP_MODER1_WPB_SHIFT); + return (CSC_WPB_CpuType)u32RegVal; +} + +/** + * @brief Enable the stop acknowledge function of register 1 group + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER1_EnableStopAck(CSCx_Reg1_PeriphType ePeriphType) +{ + CSC0->STOP_MODER1 |= (uint32_t)ePeriphType; +} + +/** + * @brief Disable the stop acknowledge function of register 1 group + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER1_DisableStopAck(CSCx_Reg1_PeriphType ePeriphType) +{ + CSC0->STOP_MODER1 &= ~(uint32_t)ePeriphType; +} + +/** + * @brief Set multiple stop ack enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg1_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_MODER1_SetMultiStopAck(uint32_t u32Value) +{ + CSC0->STOP_MODER1 = u32Value; +} + +/** + * @brief Clear multiple stop ack enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg1_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_MODER1_ClearMultiStopAck(uint32_t u32Value) +{ + CSC0->STOP_MODER1 = (CSC0->STOP_MODER1 & (~u32Value)); +} + +/** + * @brief Lock the cpu to control this stop request register 1 + * + */ +LOCAL_INLINE void CSC0_HWA_REQR1_LockWritePermit(void) +{ + CSC0->STOP_REQR1 |= (uint32_t)CSC0_STOP_REQR1_WPB_LOCK_MASK; +} + +/** + * @brief Get the stop request register 1 lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_REQR1_GetWPBLockStatus(void) +{ + return (CSC0->STOP_REQR1 & (uint32_t)CSC0_STOP_REQR1_WPB_LOCK_MASK); +} + +/** + * @brief Get the CPU type of writing permission + * + * @return CSC_WPB_CpuType CPU type which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_REQR1_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((CSC0->STOP_REQR1 & (uint32_t)CSC0_STOP_REQR1_WPB_MASK)>>CSC0_STOP_REQR1_WPB_SHIFT); + return (CSC_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set cpu to control stop request register 1 + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_REQR1_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->STOP_REQR1; + CSC0->STOP_REQR1 |= ((u32RegVal & (~(uint32_t)CSC0_STOP_REQR1_WPB_MASK)) | CSC0_STOP_REQR1_WPB(eCpuType)); +} + +/** + * @brief Set stop request in register 1 + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_REQR1_SetStopRequest(CSCx_Reg1_PeriphType ePeriphType) +{ + CSC0->STOP_REQR1 |= (uint32_t)ePeriphType; +} + +/** + * @brief Clear stop request in register 1 + * + * @param ePeriphType Peripheral to be cleared + */ +LOCAL_INLINE void CSC0_HWA_REQR1_ClearStopRequest(CSCx_Reg1_PeriphType ePeriphType) +{ + CSC0->STOP_REQR1 &= ~(uint32_t)ePeriphType; +} + +/** + * @brief Set multiple stop request enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg1_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_REQR1_SetMultiStopRequest(uint32_t u32Value) +{ + CSC0->STOP_REQR1 = u32Value; +} + +/** + * @brief Clear multiple stop request in register 0 + * + * @param u32Value the OR value of type CSCx_Reg1_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_REQR1_ClearMultiStopRequest(uint32_t u32Value) +{ + CSC0->STOP_REQR1 = (CSC0->STOP_REQR1 & (~u32Value)); +} + +/** + * @brief Get stop ack status in register 1 + * + * @param u32Value value to be set + * @return Stop ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_ACKR1_GetStopAckStatus(CSCx_Reg1_PeriphType ePeriphType) +{ + return (CSC0->STOP_ACKR1 & (uint32_t)ePeriphType); +} + +/** + * @brief Get multiple stop ack status in register 1 + * + * @param u32Value the OR value of type CSCx_Reg1_PeriphType + * @return Stop ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_ACKR1_GetMultiStopAckStatus(uint32_t u32Value) +{ + return (CSC0->STOP_ACKR1 & u32Value); +} + +/****** Operation on CSC0_xxxRegister2 ******/ +/** + * @brief Lock the cpu to control stop mode register 2 + * + */ +LOCAL_INLINE void CSC0_HWA_MODER2_LockWritePermit(void) +{ + CSC0->STOP_MODER2 |= (uint32_t)CSC0_STOP_MODER2_WPB_LOCK_MASK; +} + +/** + * @brief Get the stop mode register 2 lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_MODER2_GetWPBLockStatus(void) +{ + return (CSC0->STOP_MODER2 & (uint32_t)CSC0_STOP_MODER2_WPB_LOCK_MASK); +} + +/** + * @brief Set cpu to control this stop mode register 2 + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_MODER2_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->STOP_MODER2; + CSC0->STOP_MODER2 = ((u32RegVal & (~(uint32_t)CSC0_STOP_MODER2_WPB_MASK)) | CSC0_STOP_MODER2_WPB(eCpuType)); +} + +/** + * @brief Get the CPU type of writing permission + * + * @return CSC_WPB_CpuType The Cpu which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_MODER2_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((CSC0->STOP_MODER2 & (uint32_t)CSC0_STOP_MODER2_WPB_MASK)>>CSC0_STOP_MODER2_WPB_SHIFT); + return (CSC_WPB_CpuType)u32RegVal; +} + + +/** + * @brief Enable the stop acknowledge function of register 2 group + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER2_EnableStopAck(CSCx_Reg2_PeriphType ePeriphType) +{ + CSC0->STOP_MODER2 |= (uint32_t)ePeriphType; +} + +/** + * @brief Disable the stop acknowledge function of register 1 group + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER2_DisableStopAck(CSCx_Reg2_PeriphType ePeriphType) +{ + CSC0->STOP_MODER2 &= ~(uint32_t)ePeriphType; +} + +/** + * @brief Set multiple stop ack enable/disable value + * + * @param u32Value value to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER2_SetMultiStopAck(uint32_t u32Value) +{ + CSC0->STOP_MODER2 = u32Value; +} + +/** + * @brief Clear multiple stop ack enable/disable value + * + * @param u32Value value to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER2_ClearMultiStopAck(uint32_t u32Value) +{ + CSC0->STOP_MODER2 = (CSC0->STOP_MODER2 & (~u32Value)); +} + +/** + * @brief Lock the cpu to control this stop request register 2 + * + */ +LOCAL_INLINE void CSC0_HWA_REQR2_LockWritePermit(void) +{ + CSC0->STOP_REQR2 |= (uint32_t)CSC0_STOP_REQR2_WPB_LOCK_MASK; +} + +/** + * @brief Get the stop request register 2 lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_REQR2_GetWPBLockStatus(void) +{ + return (CSC0->STOP_REQR2 & (uint32_t)CSC0_STOP_REQR2_WPB_LOCK_MASK); +} + +/** + * @brief Set cpu to control stop request register 2 + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_REQR2_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->STOP_REQR2; + CSC0->STOP_REQR2 = ((u32RegVal & (~(uint32_t)CSC0_STOP_REQR2_WPB_MASK)) | CSC0_STOP_REQR2_WPB(eCpuType)); +} + +/** + * @brief Get the CPU type of writing permission + * + * @return CSC_WPB_CpuType The Cpu which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_REQR2_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((CSC0->STOP_REQR2 & (uint32_t)CSC0_STOP_REQR2_WPB_MASK)>>CSC0_STOP_REQR2_WPB_SHIFT); + return (CSC_WPB_CpuType)u32RegVal; +} + + +/** + * @brief Set stop request in register 2 + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_REQR2_SetStopRequest(CSCx_Reg2_PeriphType ePeriphType) +{ + CSC0->STOP_REQR2 |= (uint32_t)ePeriphType; +} + +/** + * @brief Clear stop request in register 2 + * + * @param ePeriphType Peripheral to be cleared + */ +LOCAL_INLINE void CSC0_HWA_REQR2_ClearStopRequest(CSCx_Reg2_PeriphType ePeriphType) +{ + CSC0->STOP_REQR2 &= ~(uint32_t)ePeriphType; +} + +/** + * @brief Set multiple stop request enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg2_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_REQR2_SetMultiStopRequest(uint32_t u32Value) +{ + CSC0->STOP_REQR2 = u32Value; +} + +/** + * @brief Clear multiple stop request in register 0 + * + * @param u32Value the OR value of type CSCx_Reg2_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_REQR2_ClearMultiStopRequest(uint32_t u32Value) +{ + CSC0->STOP_REQR2 = (CSC0->STOP_REQR2 & (~u32Value)); +} + +/** + * @brief Get stop ack status in register 2 + * + * @param u32Value value to be set + * @return Stop ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_ACKR2_GetStopAckStatus(CSCx_Reg2_PeriphType ePeriphType) +{ + return (CSC0->STOP_ACKR2 & (uint32_t)ePeriphType); +} + +/** + * @brief Get multiple stop ack status in register 2 + * + * @param u32Value the OR value of type CSCx_Reg2_PeriphType + * @return Stop ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_ACKR2_GetMultiStopAckStatus(uint32_t u32Value) +{ + return (CSC0->STOP_ACKR2 & u32Value); +} + +/** + * @brief Lock the cpu to control CCM0 register + * + */ +LOCAL_INLINE void CSC0_HWA_CCM0_LockWritePermit(void) +{ + CSC0->CCM0_CFG |= (uint32_t)CSC0_CCM0_CFG_WPB_LOCK_MASK; +} + +/** + * @brief Unlock the cpu to control CCM0 register + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_CCM0_GetWPBLockStatus(void) +{ + return (CSC0->CCM0_CFG & (uint32_t)CSC0_CCM0_CFG_WPB_LOCK_MASK); +} + +/** + * @brief Get the CPU type of writing permission + * + * @param CSC_WPB_CpuType The Cpu which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_CCM0_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = (CSC0->CCM0_CFG & CSC0_CCM0_CFG_WPB_MASK) >> CSC0_CCM0_CFG_WPB_SHIFT; + return (CSC_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set cpu to control this CCM0 register + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_CCM0_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->CCM0_CFG; + CSC0->CCM0_CFG = ((u32RegVal & (~(uint32_t)CSC0_CCM0_CFG_WPB_MASK)) | CSC0_CCM0_CFG_WPB(eCpuType)); +} + +/** + * @brief Force enable HClock of cpu 0 + * + */ +LOCAL_INLINE bool CSC0_HWA_GetHClockEnFlag(void) +{ + return (bool)((CSC0->CCM0_CFG & CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_MASK) != 0U); +} + +/** + * @brief Force enable HClock of cpu 0 + * + */ +LOCAL_INLINE void CSC0_HWA_HClockEnable(bool bEnable) +{ + CSC0->CCM0_CFG = (CSC0->CCM0_CFG & (~(uint32_t)CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_MASK)) | + CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN(bEnable); +} + +/** + * @brief Get CCM0 hand shake mode + * + * @param eHandShakeType CCM0 hand shake mode + */ +LOCAL_INLINE CSC_HandShakeModeType CSC0_HWA_GetHandShakeMode(void) +{ + uint32_t u32RegVal = (CSC0->CCM0_CFG & CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_MASK) >> CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_SHIFT; + return (CSC_HandShakeModeType)u32RegVal; +} + +/** + * @brief Set CCM0 hand shake mode + * + * @param eHandShakeType CCM0 hand shake mode + */ +LOCAL_INLINE void CSC0_HWA_SetHandShakeMode(CSC_HandShakeModeType eHandShakeType) +{ + uint32_t u32RegVal = CSC0->CCM0_CFG; + CSC0->CCM0_CFG = ((u32RegVal & (~(uint32_t)CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_MASK)) | CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE(eHandShakeType)); +} + +/** + * @brief Get CCM0 clock status + * + * @param eStopClockType CCM0 stop clock type + * @return CCM0 clock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_CCM0_GetClockStatus(CSCx_CCM_StopClockType eStopClockType) +{ + return (CSC0->CCM0_STATUS & (uint32_t)eStopClockType); +} + +/** + * @brief Enable SCG MAM stall + * + */ +LOCAL_INLINE void CSC0_HWA_EnalbeSCGStall(void) +{ + CSC0->SCG_MAM_STALL |= (uint32_t)CSC0_SCG_MAM_STALL_SCG_STALL_MASK; +} + +/** + * @brief Disable SCG MAM stall + * + */ +LOCAL_INLINE void CSC0_HWA_DisableSCGStall(void) +{ + CSC0->SCG_MAM_STALL &= ~(uint32_t)CSC0_SCG_MAM_STALL_SCG_STALL_MASK; +} + +/** + * @brief Lock SCG_MAM_STALL register status + * + */ +LOCAL_INLINE void CSC0_HWA_LockSCG_MAM_STALL(void) +{ + CSC0->SCG_MAM_STALL |= (uint32_t)CSC0_SCG_MAM_STALL_LOCK_MASK; +} + +/** + * @brief Get SCG_MAM_STALL register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_SCG_MAM_STALL_GetLockStatus(void) +{ + return (CSC0->SCG_MAM_STALL & (uint32_t)CSC0_SCG_MAM_STALL_LOCK_MASK); +} + +/** + * @brief Lock the cpu to control CPU0_INT register + * + */ +LOCAL_INLINE void CSC0_HWA_CPU0INT_LockWritePermit(void) +{ + CSC0->CPU0_INT |= (uint32_t)CSC0_CPU0_INT_WPB_LOCK_MASK; +} + +/** + * @brief Get CPU0_INT register WPB lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_CPU0INT_GetWPBLockStatus(void) +{ + return (CSC0->CPU0_INT & (uint32_t)CSC0_CPU0_INT_WPB_LOCK_MASK); +} + +/** + * @brief Get the CPU type of writing permission + * + * @param CSC_WPB_CpuType The Cpu which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_CPU0INT_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = (CSC0->CPU0_INT & CSC0_CPU0_INT_WPB_MASK) >> CSC0_CPU0_INT_WPB_SHIFT; + return (CSC_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set cpu to control this CPU0_INT register + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_CPU0INT_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->CPU0_INT; + CSC0->CPU0_INT = ((u32RegVal & (~(uint32_t)CSC0_CPU0_INT_WPB_MASK)) | CSC0_CPU0_INT_WPB(eCpuType)); +} + +/** + * @brief Enable cpu0 software interrupt + * + */ +LOCAL_INLINE void CSC0_HWA_CPU0INT_EnableSWInterrupt(void) +{ + CSC0->CPU0_INT |= (uint32_t)CSC0_CPU0_INT_SW_INT_MASK; +} + +/** + * @brief Disable cpu0 software interrupt + * + */ +LOCAL_INLINE void CSC0_HWA_CPU0INT_DisableSWInterrupt(void) +{ + CSC0->CPU0_INT &= ~(uint32_t)CSC0_CPU0_INT_SW_INT_MASK; +} + +/** + * @brief Enable CSC0 clock out + * + */ +LOCAL_INLINE void CSC0_HWA_EnableClockOut(void) +{ + CSC0->CLKOUT_CTRL |= (uint32_t)CSC0_CLKOUT_CTRL_CLKOUT_EN_MASK; +} + +/** + * @brief Disable CSC0 clock out + * + */ +LOCAL_INLINE void CSC0_HWA_DisableClockOut(void) +{ + CSC0->CLKOUT_CTRL &= ~(uint32_t)CSC0_CLKOUT_CTRL_CLKOUT_EN_MASK; +} + +/** + * @brief Get CLKOUT CSC0 clock out divider + * + * @return CSC0_ClockOutDivType CSC0 clock out divider + */ +LOCAL_INLINE CSC0_ClockOutDivType CSC0_HWA_GetClkOutDiv(void) +{ + uint32_t u32RegVal = (CSC0->CLKOUT_CTRL & CSC0_CLKOUT_CTRL_CLKOUT_DIV_MASK) >> CSC0_CLKOUT_CTRL_CLKOUT_DIV_SHIFT; + return (CSC0_ClockOutDivType)u32RegVal; +} + +/** + * @brief Set CLKOUTDIV + * + * @param eDivType CSC0 clock out divider + */ +LOCAL_INLINE void CSC0_HWA_SetClkOutDiv(CSC0_ClockOutDivType eDivType) +{ + uint32_t u32RegVal = CSC0->CLKOUT_CTRL; + CSC0->CLKOUT_CTRL = ((u32RegVal & (~(uint32_t)CSC0_CLKOUT_CTRL_CLKOUT_DIV_MASK)) | CSC0_CLKOUT_CTRL_CLKOUT_DIV(eDivType)); +} + +/** + * @brief Get CLKOUT source Select + * + * @return CSC0_ClockOutSrcType CSC0 clock out source + */ +LOCAL_INLINE CSC0_ClockOutSrcType CSC0_HWA_GetClkOutSel(void) +{ + uint32_t u32RegVal = (CSC0->CLKOUT_CTRL & CSC0_CLKOUT_CTRL_CLKOUT_SEL_MASK) >> CSC0_CLKOUT_CTRL_CLKOUT_SEL_SHIFT; + return (CSC0_ClockOutSrcType)u32RegVal; +} + +/** + * @brief Set CLKOUT source Select + * + * @param eClkSrcType CSC0 clock out source + */ +LOCAL_INLINE void CSC0_HWA_SetClkOutSel(CSC0_ClockOutSrcType eClkSrcType) +{ + uint32_t u32RegVal = CSC0->CLKOUT_CTRL; + CSC0->CLKOUT_CTRL = ((u32RegVal & (~(uint32_t)CSC0_CLKOUT_CTRL_CLKOUT_SEL_MASK)) | CSC0_CLKOUT_CTRL_CLKOUT_SEL(eClkSrcType)); +} + +/** + * @brief Lock CSC0_CLKOUT_CTRL register + * + */ +LOCAL_INLINE void CSC0_HWA_LockCLKOUT_CTRL(void) +{ + CSC0->CLKOUT_CTRL |= (uint32_t)CSC0_CLKOUT_CTRL_LOCK_MASK; +} + +/** + * @brief Get CSC0_CLKOUT_CTRL register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_CLKOUT_CTRL_GetLockStatus(void) +{ + return (CSC0->CLKOUT_CTRL & (uint32_t)CSC0_CLKOUT_CTRL_LOCK_MASK); +} + +/** + * @brief Get AONCLKSR register status + * + * @return AONCLKSR register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_GetStatus_AONCLKSR(void) +{ + return CSC0->AONCLKSR; +} + +/** + * @brief Get CSC0_AON32KCLK source clock + * + * @return CSC0_AON32KClkSrcType CSC0_AON32KCLK source type + */ +LOCAL_INLINE CSC0_AON32KClkSrcType CSC0_HWA_GetAON32kClkSrc(void) +{ + uint32_t u32RegVal = (CSC0->AONCLKSR & CSC0_AONCLKSR_AON32KCLKSEL_MASK) >> CSC0_AONCLKSR_AON32KCLKSEL_SHIFT; + return (CSC0_AON32KClkSrcType)u32RegVal; +} + +/** + * @brief Set CSC0_AON32KCLK source clock + * + * @param CSC0_AON32KClkSrcType CSC0_AON32KCLK source type + */ +LOCAL_INLINE void CSC0_HWA_SetAON32kClkSrc(CSC0_AON32KClkSrcType eClkSrcType) +{ + uint32_t u32RegVal = CSC0->AONCLKSR; + CSC0->AONCLKSR = ((u32RegVal & (~(uint32_t)CSC0_AONCLKSR_AON32KCLKSEL_MASK)) | CSC0_AONCLKSR_AON32KCLKSEL(eClkSrcType)); +} + +/** + * @brief Get CSC0_RTCCLK source clock + * + * @return CSC0_RTCClkSrcType CSC0_RTCCLK source type + */ +LOCAL_INLINE CSC0_RTCClkSrcType CSC0_HWA_GetRTCClkSrc(void) +{ + uint32_t u32RegVal = (CSC0->AONCLKSR & CSC0_AONCLKSR_RTCCLKSEL_MASK) >> CSC0_AONCLKSR_RTCCLKSEL_SHIFT; + return (CSC0_RTCClkSrcType)u32RegVal; +} + +/** + * @brief Set CSC0_RTCCLK source clock + * + * @param CSC0_RTCClkSrcType CSC0_RTCCLK source type + */ +LOCAL_INLINE void CSC0_HWA_SetRTCClkSrc(CSC0_RTCClkSrcType eClkSrcType) +{ + uint32_t u32RegVal = CSC0->AONCLKSR; + CSC0->AONCLKSR = ((u32RegVal & (~(uint32_t)CSC0_AONCLKSR_RTCCLKSEL_MASK)) | CSC0_AONCLKSR_RTCCLKSEL(eClkSrcType)); +} + +/** + * @brief Get CSC0_AONCLK source clock + * + * @return CSC0_AONClkSrcType CSC0_AONCLK source type + */ +LOCAL_INLINE CSC0_AONClkSrcType CSC0_HWA_GetAONClkSrc(void) +{ + uint32_t u32RegVal = (CSC0->AONCLKSR & CSC0_AONCLKSR_AONCLKSEL_MASK) >> CSC0_AONCLKSR_AONCLKSEL_SHIFT; + return (CSC0_AONClkSrcType)u32RegVal; +} + +/** + * @brief Set CSC0_AONCLK source clock + * + * @param CSC0_AONClkSrcType CSC0_AONCLK source type + */ +LOCAL_INLINE void CSC0_HWA_SetAONClkSrc(CSC0_AONClkSrcType eClkSrcType) +{ + uint32_t u32RegVal = CSC0->AONCLKSR; + CSC0->AONCLKSR = ((u32RegVal & (~(uint32_t)CSC0_AONCLKSR_AONCLKSEL_MASK)) | CSC0_AONCLKSR_AONCLKSEL(eClkSrcType)); +} + +/** + * @brief Enable CSC0_SIRCDIV32K clock out + * + */ +LOCAL_INLINE void CSC0_HWA_EnableSIRCDIV_32KClkOut(void) +{ + CSC0->AONCLKSR |= (uint32_t)CSC0_AONCLKSR_SIRCDIV32KEN_MASK; +} + +/** + * @brief Disable CSC0_SIRCDIV32K clock out + * + */ +LOCAL_INLINE void CSC0_HWA_DisableSIRCDIV_32KClkOut(void) +{ + CSC0->AONCLKSR &= ~(uint32_t)CSC0_AONCLKSR_SIRCDIV32KEN_MASK; +} + +/** + * @brief Enable CSC0_SIRC32_1K clock out + * + */ +LOCAL_INLINE void CSC0_HWA_EnableSIRC32_1KClkOut(void) +{ + CSC0->AONCLKSR |= (uint32_t)CSC0_AONCLKSR_AON1KCLKEN_MASK; +} + +/** + * @brief Disable CSC0_SIRC32_1K clock out + * + */ +LOCAL_INLINE void CSC0_HWA_DisableSIRC32_1KClkOut(void) +{ + CSC0->AONCLKSR &= ~(uint32_t)CSC0_AONCLKSR_AON1KCLKEN_MASK; +} + +/** + * @brief Lock CSC0_AONCLKSR register + * + */ +LOCAL_INLINE void CSC0_HWA_LockAONCLKSR(void) +{ + CSC0->AONCLKSR |= (uint32_t)CSC0_AONCLKSR_LOCK_MASK; +} + +/** + * @brief Get CSC0_AONCLKSR register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_AONCLKSR_GetLockStaus(void) +{ + return (CSC0->AONCLKSR & (uint32_t)CSC0_AONCLKSR_LOCK_MASK); +} + +/** + * @brief Set count for reduce power mode exit + * + * @param u8Conut count to be set + */ +LOCAL_INLINE void CSC0_HWA_SetRpmExitCount(uint8_t u8Conut) +{ + uint32_t u32RegVal = CSC0->PCU_CTRL; + CSC0->PCU_CTRL = ((u32RegVal & (~(uint32_t)CSC0_PCU_CTRL_RPM_EXIT_CNT_MASK)) | CSC0_PCU_CTRL_RPM_EXIT_CNT(u8Conut)); +} + +/** + * @brief Get count of reduce power mode exit + * + * @return count be got + */ +LOCAL_INLINE uint8_t CSC0_HWA_GetRpmExitCount(void) +{ + return (uint8_t)((CSC0->PCU_CTRL & (uint32_t)CSC0_PCU_CTRL_RPM_EXIT_CNT_MASK)>>CSC0_PCU_CTRL_RPM_EXIT_CNT_SHIFT); +} + +/** + * @brief Set power domain 1 isolation enable hold + * + */ +LOCAL_INLINE void CSC0_HWA_SetPadIsoHold(void) +{ + CSC0->PCU_CTRL |= CSC0_PCU_CTRL_PAD_ISO_HOLD_MASK; +} + +/** + * @brief Power domain 1 isolation enable hold clear + * + */ +LOCAL_INLINE void CSC0_HWA_CLearPadIsoHold(void) +{ + CSC0->PCU_CTRL |= CSC0_PCU_CTRL_PAD_ISO_HOLD_CLR_MASK; +} + +/** + * @brief Lock CSC0_PCU_CTRL register + * + */ +LOCAL_INLINE void CSC0_HWA_LockPCU_CTRL(void) +{ + CSC0->PCU_CTRL |= (uint32_t)CSC0_PCU_CTRL_LOCK_MASK; +} + +/** + * @brief Unlock CSC0_PCU_CTRL register + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_PCU_CTRL_GetLockStatus(void) +{ + return (CSC0->PCU_CTRL & (uint32_t)CSC0_PCU_CTRL_LOCK_MASK); +} + +/** + * @brief Enable CSC_SMU control group 0 + * + * @param eType CSC_SMU control group 0 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL0_EnableReqToSMU(CSC_SMU_CtrlGrp0Type eType) +{ + CSC0->SMU_CTRL0 |= (uint32_t)eType; +} + +/** + * @brief Disable CSC_SMU control group 0 + * + * @param eType CSC_SMU control group 0 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL0_DisableReqToSMU(CSC_SMU_CtrlGrp0Type eType) +{ + CSC0->SMU_CTRL0 &= ~(uint32_t)eType; +} + +/** + * @brief Set multiple CSC_SMU control group 0 + * + * @param u32Value The or value of CSC_SMU_CtrlGrp0Type + */ +LOCAL_INLINE void CSC0_HWA_CTRL0_SetMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL0 = u32Value; +} + +/** + * @brief Clear multiple CSC_SMU control group 0 + * + * @param u32Value The or value of CSC_SMU_CtrlGrp0Type + */ +LOCAL_INLINE void CSC0_HWA_CTRL0_ClearMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL0 &= ~u32Value; +} + +/** + * @brief Lock CSC0_SMU_CTRL0 register + * + */ +LOCAL_INLINE void CSC0_HWA_LockSMU_CTRL0(void) +{ + CSC0->SMU_CTRL0 |= (uint32_t)CSC0_SMU_CTRL0_LOCK_MASK; +} + +/** + * @brief Get CSC0_SMU_CTRL0 register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_SMU_CTRL0_GetLockStatus(void) +{ + return (CSC0->SMU_CTRL0 & (uint32_t)CSC0_SMU_CTRL0_LOCK_MASK); +} + +/** + * @brief Enable CSC_SMU control group 1 + * + * @param eType CSC_SMU control group 1 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL1_EnableReqToSMU(CSC_SMU_Cpux_CtrlGrpType eType) +{ + CSC0->SMU_CTRL1 |= (uint32_t)eType; +} + +/** + * @brief Disable CSC_SMU control group 1 + * + * @param eType CSC_SMU control group 1 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL1_DisableReqToSMU(CSC_SMU_Cpux_CtrlGrpType eType) +{ + CSC0->SMU_CTRL1 &= ~(uint32_t)eType; +} + +/** + * @brief Set multiple CSC_SMU control group 1 + * + * @param u32Value The or value of CSC_SMU_Cpux_CtrlGrpType + */ +LOCAL_INLINE void CSC0_HWA_CTRL1_SetMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL1 = u32Value; +} + +/** + * @brief Clear multiple CSC_SMU control group 1 + * + * @param u32Value The or value of CSC_SMU_Cpux_CtrlGrpType + */ +LOCAL_INLINE void CSC0_HWA_CTRL1_ClearMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL1 &= ~u32Value; +} + +/** + * @brief Lock CSC0_SMU_CTRL1 register + * + */ +LOCAL_INLINE void CSC0_HWA_LockSMU_CTRL1(void) +{ + CSC0->SMU_CTRL1 |= (uint32_t)CSC0_SMU_CTRL1_LOCK_MASK; +} + +/** + * @brief Get CSC0_SMU_CTRL1 register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_SMU_CTRL1_GetLockStatus(void) +{ + return (CSC0->SMU_CTRL1 & (uint32_t)CSC0_SMU_CTRL1_LOCK_MASK); +} + +/** + * @brief Enable CSC_SMU control group 4 + * + * @param eType CSC_SMU control group 4 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL4_EnableReqToSMU(CSC_SMU_CtrlGrp4Type eType) +{ + CSC0->SMU_CTRL4 |= (uint32_t)eType; +} + +/** + * @brief Disable CSC_SMU control group 4 + * + * @param eType CSC_SMU control group 4 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL4_DisableReqToSMU(CSC_SMU_CtrlGrp4Type eType) +{ + CSC0->SMU_CTRL4 &= ~(uint32_t)eType; +} + +/** + * @brief Set multiple CSC_SMU control group 4 + * + * @param u32Value The or value of CSC_SMU_CtrlGrp4Type + */ +LOCAL_INLINE void CSC0_HWA_CTRL4_SetMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL4 = u32Value; +} + +/** + * @brief Clear multiple CSC_SMU control group 4 + * + * @param u32Value The or value of CSC_SMU_CtrlGrp4Type + */ +LOCAL_INLINE void CSC0_HWA_CTRL4_ClearMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL4 &= ~u32Value; +} + +/** + * @brief Lock CSC0_SMU_CTRL4 register + * + */ +LOCAL_INLINE void CSC0_HWA_LockSMU_CTRL4(void) +{ + CSC0->SMU_CTRL4 |= (uint32_t)CSC0_SMU_CTRL4_LOCK_MASK; +} + +/** + * @brief Get CSC0_SMU_CTRL4 register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_SMU_CTRL4_GetLockStatus(void) +{ + return (CSC0->SMU_CTRL4 & (uint32_t)CSC0_SMU_CTRL4_LOCK_MASK); +} + +/** + * @brief Enable CSC_SMU control group 5 + * + * @param eType CSC_SMU control group 5 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL5_EnableReqToSMU(CSC_SMU_CtrlGrp5Type eType) +{ + CSC0->SMU_CTRL5 |= (uint32_t)eType; +} + +/** + * @brief Disable CSC_SMU control group 5 + * + * @param eType CSC_SMU control group 5 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL5_DisableReqToSMU(CSC_SMU_CtrlGrp5Type eType) +{ + CSC0->SMU_CTRL5 &= ~(uint32_t)eType; +} + +/** + * @brief Set multiple CSC_SMU control group 5 + * + * @param u32Value The or value of CSC_SMU_CtrlGrp5Type + */ +LOCAL_INLINE void CSC0_HWA_CTRL5_SetMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL5 = u32Value; +} + +/** + * @brief Clear multiple CSC_SMU control group 5 + * + * @param u32Value The or value of CSC_SMU_CtrlGrp4Type + */ +LOCAL_INLINE void CSC0_HWA_CTRL5_ClearMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL5 &= ~u32Value; +} + +/** + * @brief Lock CSC0_SMU_CTRL5 register + * + */ +LOCAL_INLINE void CSC0_HWA_LockSMU_CTRL5(void) +{ + CSC0->SMU_CTRL5 |= (uint32_t)CSC0_SMU_CTRL5_LOCK_MASK; +} + +/** + * @brief Get CSC0_SMU_CTRL5 register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_SMU_CTRL5_GetLockStatus(void) +{ + return (CSC0->SMU_CTRL5 & (uint32_t)CSC0_SMU_CTRL5_LOCK_MASK); +} + +/** + * @brief Enable CSC_CMU control group + * + * @param eType CSC_CMU control group type + */ +LOCAL_INLINE void CSC0_HWA_EnableReqToCMU(CSC0_CMU_CtrlGrpType eType) +{ + CSC0->CMU_CTRL |= (uint32_t)eType; +} + +/** + * @brief Disable CSC_CMU control group + * + * @param eType CSC_CMU control group type + */ +LOCAL_INLINE void CSC0_HWA_DisableReqToCMU(CSC0_CMU_CtrlGrpType eType) +{ + CSC0->CMU_CTRL &= ~(uint32_t)eType; +} + +/** + * @brief Lock CSC0_SMU_CTRL4 register + * + */ +LOCAL_INLINE void CSC0_HWA_LockCMU_CTRL(void) +{ + CSC0->CMU_CTRL |= (uint32_t)CSC0_CMU_CTRL_LOCK_MASK; +} + +/** + * @brief Get CSC0_SMU_CTRL4 register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_CMU_CTRL_GetLockStatus(void) +{ + return (CSC0->CMU_CTRL & (uint32_t)CSC0_CMU_CTRL_LOCK_MASK); +} + +/** + * @brief Set low power wakeup PADx configure source + * + * @param eGroup Low power PADx group type + * @eSrc eSrc Low power wakeup PADx configure source + */ +LOCAL_INLINE void CSC0_HWA_SetLP_WAKEUPCfgSrc(CSC0_LPWakeupGrpType eGroup, CSC0_LPWakeupSrcType eSrc) +{ + CSC0->LP_WAKEUP = (CSC0->LP_WAKEUP & (~(CSC0_LP_WAKEUP_LP_WAKEUP_CFG0_MASK >> (4U * (uint32_t)eGroup)))) | + (CSC0_LP_WAKEUP_LP_WAKEUP_CFG0(eSrc) >> (4U * (uint32_t)eGroup)); +} + + +/** + * @brief Set low power wakeup PADx configure source polarity + * + * @param eGroup Low power PADx group type + * @eSrc eSrc Low power wakeup PADx configure source polarity + */ +LOCAL_INLINE void CSC0_HWA_SetLP_WAKEUPCfgPol(CSC0_LPWakeupGrpType eGroup, CSC0_LPWakeupPolType ePolarity) +{ + CSC0->LP_WAKEUP = (CSC0->LP_WAKEUP & (~(CSC0_LP_WAKEUP_LP0_POL_MASK >> (uint32_t)eGroup))) | + (CSC0_LP_WAKEUP_LP0_POL(ePolarity) >> (uint32_t)eGroup); +} + +/** + * @brief Lock low power wakeup register + * + */ +LOCAL_INLINE void CSC0_HWA_LockLP_WAKEUP(void) +{ + CSC0->LP_WAKEUP |= (uint32_t)CSC0_LP_WAKEUP_LOCK_MASK; +} + +/** + * @brief Get low power wakeup register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_LP_WAKEUP_GetLockStatus(void) +{ + return (CSC0->LP_WAKEUP & (uint32_t)CSC0_LP_WAKEUP_LOCK_MASK); +} + +#endif /*#ifndef _HWA_CSC_H_*/ diff --git a/Inc/HwA_dma.h b/Inc/HwA_dma.h new file mode 100644 index 0000000..03f7632 --- /dev/null +++ b/Inc/HwA_dma.h @@ -0,0 +1,1514 @@ +/** + * @file HwA_dma.h + * @author Flagchip0126 + * @brief Hardware access layer for DMA + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_DMA_H_ +#define _HWA_DMA_H_ + +#include "device_header.h" + +#define DMA_CH_TO_DCHPRI(x) ((x) ^ 3U) + +/** + * @defgroup HwA_dma + * @ingroup fc7xxx_driver_dma + * @{ + */ + +/** + * @brief DMA running status + * + */ +typedef enum +{ + DMA_RUNNING_STATUS_IDLE = 0x0U, /*!< The DMA engine is idle */ + DMA_RUNNING_STATUS_ACTIVE = 0x1U /*!< The DMA engine is transferring data */ +} DMA_RunningStatusType; + +/** + * @brief DMA channel arbitration algorithm used in the channel arbitration phase + * + */ +typedef enum +{ + DMA_ARBITRATION_ALGORITHM_FIXED_PRIORITY = 0U, /*!< Use the fixed priority for arbitration */ + DMA_ARBITRATION_ALGORITHM_ROUND_ROBIN = 1U /*!< Use the channel number for arbitration, + higher channel number has higher priority */ +} DMA_ArbitrationAlgorithmType; + +/** + * @brief Defines the size of data in one transfer + * + * One transfer can contain multiple block, and one block may contain multiple + * data, this parameter specifies the size of data which the DMA engine will + * access one time in the memory. + * + */ +typedef enum +{ + + DMA_TRANSFER_SIZE_1B = 0x0U, + DMA_TRANSFER_SIZE_2B = 0x1U, + DMA_TRANSFER_SIZE_4B = 0x2U, + DMA_TRANSFER_SIZE_8B = 0x3U, + DMA_TRANSFER_SIZE_32B = 0x5U +} DMA_TransferSizeType; + +/** + * @brief Get active status of the DMA instance + * + * @param pDma the base address of the DMA instance + * @return DMA_RUNNING_STATUS_ACTIVE DMA is executing a channel + * @return DMA_RUNNING_STATUS_IDLE DMA is idle + */ +LOCAL_INLINE DMA_RunningStatusType DMA_HWA_GetStatus(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_ACTIVE_MASK) >> DMA_CR_ACTIVE_SHIFT; + return (DMA_RunningStatusType)u32TmpVal; +} + +/** + * @brief Get whether the DMA instance is cancelling + * + * @param pDma the base address of the DMA instance + * @return true cancel operation is requested and has not been finished + * @return false DMA is under normal operation + */ +LOCAL_INLINE bool DMA_HWA_GetCancelTransferStatus(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_CX_MASK) >> DMA_CR_CX_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Cancel the remaining transfer of the DMA + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_CancelTransfer(DMA_Type *const pDma) +{ + pDma->CR |= DMA_CR_CX_MASK; +} + +/** + * @brief Get whether the DMA instance is cancelling with error + * + * @param pDma the base address of the DMA instance + * @return true cancel operation is requested and has not been finished + * @return false DMA is under normal operation + */ +LOCAL_INLINE bool DMA_HWA_GetErrorCancelTransferStatus(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_ECX_MASK) >> DMA_CR_ECX_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set Channel Group 0 Priority + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_SetGPR0PRI(DMA_Type *const pDma) +{ + pDma->CR = (pDma->CR & ~DMA_CR_GPR0PRI_MASK) | DMA_CR_GPR0PRI(1U); +} + +/** + * @brief Cancel the remaining transfer of the DMA and generate an error after finished cancelling + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ErrorCancelTransfer(DMA_Type *const pDma) +{ + pDma->CR |= DMA_CR_ECX_MASK; +} + +/** + * @brief Get whether inner loop mapping is enabled + * + * @param pDma the base address of the DMA instance + * @return true inner loop mapping is enabled + * @return false inner loop mapping is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetInnerLoopMappingEnableFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_EILM_MASK) >> DMA_CR_EILM_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable inner loop mapping + * + * @note Only after enabling inner loop mapping, you can apply an offset to the source + * and/or destination address after the inner loop finishes. + * + * @param pDma the base address of the DMA instance + * @param bEnable whether to enable the inner loop mapping + */ +LOCAL_INLINE void DMA_HWA_SetInnerLoopMappingEnableFlag(DMA_Type *const pDma, bool bEnable) +{ + pDma->CR = (pDma->CR & ~DMA_CR_EILM_MASK) | DMA_CR_EILM(bEnable); +} + +/** + * @brief Get whether the continuous trig mode is enabled + * When continuous trig mode is enabled, channel arbitration is not used for a inner loop + * channel trig before being activated again. Upon inner loop completion, the channel + * activates again if that channel has a inner loop channel trig enabled and the trig + * channel is itself. This effectively applies the inner loop offsets and restarts the next + * inner loop. + * + * @param pDma the base address of the DMA instance + * @return true continuous trig mode is enabled + * @return false continuous trig mode is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetContinuousTrigModeEnableFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_CTM_MASK) >> DMA_CR_CTM_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable the continuous trig mode + * + * @param pDma the base address of the DMA instance + * @param bEnable whether to enable the continuous trig mode + */ +LOCAL_INLINE void DMA_HWA_SetContinuousTrigModeEnableFlag(DMA_Type *const pDma, bool bEnable) +{ + pDma->CR = (pDma->CR & ~DMA_CR_CTM_MASK) | DMA_CR_CTM(bEnable); +} + +/** + * @brief Get whether the DMA is halted + * When the DMA is halted, it will ignore all service requests + * @param pDma the base address of the DMA instance + * @return true the DMA is halted + * @return true the DMA is not halted + */ +LOCAL_INLINE bool DMA_HWA_GetHatlStatus(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_HALT_MASK) >> DMA_CR_HALT_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Halt the DMA operations + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_HaltOperations(DMA_Type *const pDma) +{ + pDma->CR |= DMA_CR_HALT_MASK; +} + +/** + * @brief Clear the halt flag of the DMA instance + * After HALT is cleared, the DMA could continue to operate + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearHaltFlag(DMA_Type *const pDma) +{ + pDma->CR &= ~DMA_CR_HALT_MASK; +} + +/** + * @brief Get whether halt on error is enabled on the DMA instance + * + * @param pDma the base address of the DMA instance + * @return true halt on error is enabled, any error will cause HALT flag to be set + * @return false halt on error is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetHaltOnErrorFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_HOE_MASK) >> DMA_CR_HOE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable halt on error on the DMA instance + * + * @note Ff halt on error is enabled, any error will cause HALT flag to be set + * + * @param pDma the base address of the DMA instance + * @param bEnable whether to enable halt on error + */ +LOCAL_INLINE void DMA_HWA_SetHaltOnErrorFlag(DMA_Type *const pDma, bool bEnable) +{ + pDma->CR = (pDma->CR & ~DMA_CR_HOE_MASK) | DMA_CR_HOE(bEnable); +} + +/** + * @brief Get the DMA arbitration algorithm + * + * @param pDma the base address of the DMA instance + * @return DMA_ArbitrationAlgorithmType the DMA arbitration algorithm + */ +LOCAL_INLINE DMA_ArbitrationAlgorithmType DMA_HWA_GetArbitrationAlgorithm(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_ERCA_MASK) >> DMA_CR_ERCA_SHIFT; + return (DMA_ArbitrationAlgorithmType)u32TmpVal; +} + +/** + * @brief Set the DMA arbitration algorithm + * + * @param pDma the base address of the DMA instance + * @param eAlgorithm the DMA arbitration algorithm + */ +LOCAL_INLINE void DMA_HWA_SetArbitrationAlgorithm(DMA_Type *const pDma, DMA_ArbitrationAlgorithmType eAlgorithm) +{ + pDma->CR = (pDma->CR & ~DMA_CR_ERCA_MASK) | DMA_CR_ERCA(eAlgorithm); +} + +/** + * @brief Get whether the DMA is configured to stop under debug mode + * + * @param pDma the base address of the DMA instance + * @return true the DMA is will stop under debug mode + * @return true the DMA is will continue to operate under debug mode + */ +LOCAL_INLINE bool DMA_HWA_GetDebugModeStopFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_DBGS_MASK) >> DMA_CR_DBGS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the control register of the DMA instance + * + * @param pDma the base address of the DMA instance + * @return uint32_t the control register settings + */ +LOCAL_INLINE uint32_t DMA_HWA_GetControlRegister(const DMA_Type *const pDma) +{ + return pDma->CR; +} + +/** + * @brief Set the control register of the DMA instance + * + * @param pDma the base address of the DMA instance + * @param u32Settings the settings of the DMA control register + */ +LOCAL_INLINE void DMA_HWA_SetControlRegister(DMA_Type *const pDma, uint32_t u32Settings) +{ + pDma->CR = u32Settings; +} + +/** + * @brief Set whether to stop DMA under debug mode + * + * @param pDma the base address of the DMA instance + * @param bEnable whether to stop DMA under debug mode + */ +LOCAL_INLINE void DMA_HWA_SetDebugModeStopFlag(DMA_Type *const pDma, bool bEnable) +{ + pDma->CR = (pDma->CR & ~DMA_CR_DBGS_MASK) | DMA_CR_DBGS(bEnable); +} + +/** + * @brief Get the DMA error status + * + * @param pDma the base address of the DMA instance + * @return uint32_t the DMA error status + */ +LOCAL_INLINE uint32_t DMA_HWA_GetErrorStatus(const DMA_Type *const pDma) +{ + return pDma->ES; +} + +/** + * @brief Get whether there is error occured on the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true there is error on the specified channel + * @return false there is no error on the specified channel + */ +LOCAL_INLINE bool DMA_HWA_GetChannelErrorFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pDma->ERR & (1UL << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the channel error status, each bit represents a channel + * + * @param pDma the base address of the DMA instance + * @return uint16_t the channel error status + */ +LOCAL_INLINE uint16_t DMA_HWA_GetAllChannelErrorFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = pDma->ERR; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get whether error interrupt is enabled on the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true error interrupt is enabled on the specified channel + * @return false error interrupt is disabled on the specified channel + */ +LOCAL_INLINE bool DMA_HWA_GetChannelErrorInterruptEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pDma->EEI & (1UL << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel error interrupt enable status + * + * @param pDma the base address of the DMA instance + * @return uint16_t the channel error interrupt enable status + */ +LOCAL_INLINE uint16_t DMA_HWA_GetAllChannelErrorInterruptEnableFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = pDma->EEI; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Enable error interrupt for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_EnableChannelErrorInterrupt(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->SEEI = DMA_SEEI_SEEI(u8Channel); +} + +/** + * @brief Enable error interrupt for all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_EnableAllChannelErrorInterrupt(DMA_Type *const pDma) +{ + pDma->SEEI = DMA_SEEI_SAEE_MASK; +} + +/** + * @brief Disable error interrupt for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_DisableChannelErrorInterrupt(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CEEI = DMA_CEEI_CEEI(u8Channel); +} + +/** + * @brief Disable error interrupt for all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_DisableAllChannelErrorInterrupt(DMA_Type *const pDma) +{ + pDma->CEEI = DMA_CEEI_CAEE_MASK; +} + +/** + * @brief Enable channel request for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_EnableChannelRequest(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->SERQ = DMA_SERQ_SERQ(u8Channel); +} + +/** + * @brief Enable channel request for all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_EnableAllChannelRequest(DMA_Type *const pDma) +{ + pDma->SERQ = DMA_SERQ_SAER_MASK; +} + +/** + * @brief Disable channel request for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_DisableChannelRequest(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CERQ = DMA_CERQ_CERQ(u8Channel); +} + +/** + * @brief Disable channel request for all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_DisableAllChannelRequest(DMA_Type *const pDma) +{ + pDma->CERQ = DMA_CERQ_CAER_MASK; +} + +/** + * @brief Clear DONE bit for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_ClearChannelDoneStatus(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CDNE = DMA_CDNE_CDNE(u8Channel); +} + +/** + * @brief Clear DONE bit for the all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearAllChannelDoneStatus(DMA_Type *const pDma) +{ + pDma->CDNE = DMA_CDNE_CADN_MASK; +} + +/** + * @brief Clear ERR bit for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_ClearChannelErrorFlag(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CERR = DMA_CERR_CERR(u8Channel); +} + +/** + * @brief Clear ERR bit for the all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearAllChannelErrorFlag(DMA_Type *const pDma) +{ + pDma->CERR = DMA_CERR_CAEI_MASK; +} + +/** + * @brief Clear interrupt flag for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_ClearChannelInterruptFlag(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CINT = DMA_CINT_CINT(u8Channel); +} + +/** + * @brief Clear interrupt flag for the all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearAllChannelInterruptFlag(DMA_Type *const pDma) +{ + pDma->CINT = DMA_CINT_CAIR_MASK; +} + +/** + * @brief Set start for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_SetChannelStart(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->SSRT = DMA_SSRT_SSRT(u8Channel); +} + +/** + * @brief Set start for the all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_SetAllChannelStart(DMA_Type *const pDma) +{ + pDma->SSRT = DMA_SSRT_SAST_MASK; +} + +/** + * @brief Get whether source unalign modulo is enabled for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE bool DMA_HWA_GetSrcUnalignModuloEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pDma->DUME[u8Channel/16U] & ((uint32_t)DMA_DUME_SUME0_MASK << (2U * (u8Channel % 16U)))) >> + (DMA_DUME_SUME0_SHIFT + 2U * (u8Channel % 16U)); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether destination unalign modulo is enabled for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE bool DMA_HWA_GetDestUnalignModuloEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pDma->DUME[u8Channel/16U] & ((uint32_t)DMA_DUME_DUME0_MASK << (2U * (u8Channel % 16U)))) >> + (DMA_DUME_DUME0_SHIFT + 2U * (u8Channel % 16U)); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether to enable unalign modulo for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnableSrcModulo whether source unalign modulo is to be enabled + * @param bEnableDestModulo whether destination unalign modulo is to be enabled + */ +LOCAL_INLINE void DMA_HWA_SetUnalignModuloEnableFlag(DMA_Type *const pDma, uint8_t u8Channel, + bool bEnableSrcModulo, bool bEnableDestModulo) +{ + pDma->DUME[u8Channel/16U] = (pDma->DUME[u8Channel/16U] & ~((DMA_DUME_DUME0_MASK | DMA_DUME_SUME0_MASK) << (2U * (u8Channel % 16U)))) | + ((DMA_DUME_DUME0(bEnableDestModulo) | DMA_DUME_SUME0(bEnableSrcModulo)) << (2U * (u8Channel % 16U))); +} + +/** + * @brief Get the source unalign modulo of the index + * + * @param pDma the base address of the DMA instance + * @param u8Selection the index of the unalign modulo + * @return uint16_t the source unalign modulo + */ +LOCAL_INLINE uint16_t DMA_HWA_GetSrcUnalignModulo(const DMA_Type *const pDma, uint8_t u8Selection) +{ + uint32_t u32TmpVal = (pDma->DUMO[u8Selection] & DMA_DUMO_SUMO_MASK) >> DMA_DUMO_SUMO_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get the destination unalign modulo of the index + * + * @param pDma the base address of the DMA instance + * @param u8Selection the index of the unalign modulo + * @return uint16_t the destination unalign modulo + */ +LOCAL_INLINE uint16_t DMA_HWA_GetDestUnalignModulo(const DMA_Type *const pDma, uint8_t u8Selection) +{ + uint32_t u32TmpVal = (pDma->DUMO[u8Selection] & DMA_DUMO_DUMO_MASK) >> DMA_DUMO_DUMO_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set unalign modulo of the index + * + * @param pDma the base address of the DMA instance + * @param u8Selection the index of the unalign modulo + * @param u16SrcModulo the source unalign modulo + * @param u16DestModulo the destination unalign modulo + */ +LOCAL_INLINE void DMA_HWA_SetUnalignModulo(DMA_Type *const pDma, uint8_t u8Selection, + uint16_t u16SrcModulo, uint16_t u16DestModulo) +{ + pDma->DUMO[u8Selection] = DMA_DUMO_SUMO(u16SrcModulo) | DMA_DUMO_DUMO(u16DestModulo); +} + +/** + * @brief Get priority of the channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the priority of the channel + */ +LOCAL_INLINE uint8_t DMA_HWA_GetPriority(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint8_t u8TmpVal = pDma->DCHPRI[DMA_CH_TO_DCHPRI(u8Channel)]; + return u8TmpVal; +} + +/** + * @brief Set priority of the channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8Priority the priority of the channel + */ +LOCAL_INLINE void DMA_HWA_SetPriority(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8Priority) +{ + pDma->DCHPRI[DMA_CH_TO_DCHPRI(u8Channel)] = u8Priority; +} + +/** + * @brief Get the source address of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint32_t the source address of the DMA channel + */ +LOCAL_INLINE uint32_t DMA_HWA_GetSrcAddr(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return pDma->CFG[u8Channel].SADDR; +} + +/** + * @brief Set the source address of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u32SrcAddr the source address of the DMA channel + */ +LOCAL_INLINE void DMA_HWA_SetSrcAddr(DMA_Type *const pDma, uint8_t u8Channel, uint32_t u32SrcAddr) +{ + pDma->CFG[u8Channel].SADDR = u32SrcAddr; +} + +/** + * @brief Get the destination address of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint32_t the destination address of the DMA channel + */ +LOCAL_INLINE uint32_t DMA_HWA_GetDestAddr(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return pDma->CFG[u8Channel].DADDR; +} + +/** + * @brief Set the destination address of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u32DestAddr the destination address of the DMA channel + */ +LOCAL_INLINE void DMA_HWA_SetDestAddr(DMA_Type *const pDma, uint8_t u8Channel, uint32_t u32DestAddr) +{ + pDma->CFG[u8Channel].DADDR = u32DestAddr; +} + +/** + * @brief Get source data offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int16_t the source data offset + */ +LOCAL_INLINE int16_t DMA_HWA_GetSrcOffset(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return (int16_t)pDma->CFG[u8Channel].SOFF; +} + +/** + * @brief Set source data offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param s16Offset the source data offset + */ +LOCAL_INLINE void DMA_HWA_SetSrcOffset(DMA_Type *const pDma, uint8_t u8Channel, int16_t s16Offset) +{ + pDma->CFG[u8Channel].SOFF = (uint16_t)s16Offset; +} + +/** + * @brief Get destination data offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int16_t the destination data offset + */ +LOCAL_INLINE int16_t DMA_HWA_GetDestOffset(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return (int16_t)pDma->CFG[u8Channel].DOFF; +} + +/** + * @brief Set destination data offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param s16Offset the destination data offset + */ +LOCAL_INLINE void DMA_HWA_SetDestOffset(DMA_Type *const pDma, uint8_t u8Channel, int16_t s16Offset) +{ + pDma->CFG[u8Channel].DOFF = (uint16_t)s16Offset; +} + +/** + * @brief Get the source data size of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return DMA_TransferSizeType the source data size of the DMA channel + */ +LOCAL_INLINE DMA_TransferSizeType DMA_HWA_GetSrcDataSize(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].ATTR & DMA_CFG_ATTR_SSIZE_MASK) >> DMA_CFG_ATTR_SSIZE_SHIFT; + return (DMA_TransferSizeType)u16TmpVal; +} + +/** + * @brief Set the source data size of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param eDataSize the source data size of the DMA channel + */ +LOCAL_INLINE void DMA_HWA_SetSrcDataSize(DMA_Type *const pDma, uint8_t u8Channel, DMA_TransferSizeType eDataSize) +{ + pDma->CFG[u8Channel].ATTR = (pDma->CFG[u8Channel].ATTR & ~DMA_CFG_ATTR_SSIZE_MASK) | DMA_CFG_ATTR_SSIZE(eDataSize); +} + +/** + * @brief Get the destination data size of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return DMA_TransferSizeType the destination data size of the DMA channel + */ +LOCAL_INLINE DMA_TransferSizeType DMA_HWA_GetDestDataSize(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].ATTR & DMA_CFG_ATTR_DSIZE_MASK) >> DMA_CFG_ATTR_DSIZE_SHIFT; + return (DMA_TransferSizeType)u16TmpVal; +} + +/** + * @brief Set the destination data size of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param eDataSize the destination data size of the DMA channel + */ +LOCAL_INLINE void DMA_HWA_SetDestDataSize(DMA_Type *const pDma, uint8_t u8Channel, DMA_TransferSizeType eDataSize) +{ + pDma->CFG[u8Channel].ATTR = (pDma->CFG[u8Channel].ATTR & ~DMA_CFG_ATTR_DSIZE_MASK) | DMA_CFG_ATTR_DSIZE(eDataSize); +} + +/** + * @brief Get the source address aligned modulo of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the source address aligned modulo + */ +LOCAL_INLINE uint8_t DMA_HWA_GetSrcModulo(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].ATTR & DMA_CFG_ATTR_SMOD_MASK) >> DMA_CFG_ATTR_SMOD_SHIFT; + return (uint8_t)u16TmpVal; +} + +/** + * @brief Set the source address aligned modulo of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8SrcModulo the source address aligned modulo + */ +LOCAL_INLINE void DMA_HWA_SetSrcModulo(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8SrcModulo) +{ + pDma->CFG[u8Channel].ATTR = (pDma->CFG[u8Channel].ATTR & ~DMA_CFG_ATTR_SMOD_MASK) | DMA_CFG_ATTR_SMOD(u8SrcModulo); +} + +/** + * @brief Get the destination address aligned modulo of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the destination address aligned modulo + */ +LOCAL_INLINE uint8_t DMA_HWA_GetDestModulo(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].ATTR & DMA_CFG_ATTR_DMOD_MASK) >> DMA_CFG_ATTR_DMOD_SHIFT; + return (uint8_t)u16TmpVal; +} + +/** + * @brief Set the destination address aligned modulo of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8DestModulo the destination address aligned modulo + */ +LOCAL_INLINE void DMA_HWA_SetDestModulo(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8DestModulo) +{ + pDma->CFG[u8Channel].ATTR = (pDma->CFG[u8Channel].ATTR & ~DMA_CFG_ATTR_DMOD_MASK) | DMA_CFG_ATTR_DMOD(u8DestModulo); +} + +/** + * @brief Get the address adjustment applied to the source address after major loop finished + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int32_t the address adjustment applied to the source address after major loop finished + */ +LOCAL_INLINE int32_t DMA_HWA_GetSrcLastAddrAdjustment(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return (int32_t)pDma->CFG[u8Channel].SLAST; +} + +/** + * @brief Set the address adjustment applied to the source address after major loop finished + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param s32LastAdj the address adjustment applied to the source address after major loop finished + */ +LOCAL_INLINE void DMA_HWA_SetSrcLastAddrAdjustment(DMA_Type *const pDma, uint8_t u8Channel, int32_t s32LastAdj) +{ + pDma->CFG[u8Channel].SLAST = (uint32_t)s32LastAdj; +} + +/** + * @brief Get the address adjustment applied to the destination address after major loop finished + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int32_t the address adjustment applied to the destination address after major loop finished + */ +LOCAL_INLINE int32_t DMA_HWA_GetDestLastAddrAdjustment(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return (int32_t)pDma->CFG[u8Channel].DLAST; +} + +/** + * @brief Set the address adjustment applied to the destination address after major loop finished + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param s32LastAdj the address adjustment applied to the destination address after major loop finished + */ +LOCAL_INLINE void DMA_HWA_SetDestLastAddrAdjustment(DMA_Type *const pDma, uint8_t u8Channel, int32_t s32LastAdj) +{ + pDma->CFG[u8Channel].DLAST = (uint32_t)s32LastAdj; +} + +/** + * @brief Get whether source address inner loop offset is enabled + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true source address inner loop offset is enabled + * @return false source address inner loop offset is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + u32TmpVal = 0U; + } + else + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFNO & DMA_CFG_NBYTES_ILOFFNO_SILOE_MASK) >> + DMA_CFG_NBYTES_ILOFFNO_SILOE_SHIFT; + } + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether destination address inner loop offset is enabled + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true destination address inner loop offset is enabled + * @return false destination address inner loop offset is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetInnerLoopDestOffsetEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + u32TmpVal = 0U; + } + else + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFNO & DMA_CFG_NBYTES_ILOFFNO_DILOE_MASK) >> + DMA_CFG_NBYTES_ILOFFNO_DILOE_SHIFT; + } + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the inner loop offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int32_t the signed inner loop offset + */ +LOCAL_INLINE int32_t DMA_HWA_GetInnerLoopOffset(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + u32TmpVal = 0U; + } + else + { + bool bDmaInnerLoopSrcOffsetEnable = DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(pDma, u8Channel); + bool bDmaInnerLoopDestOffsetEnable = DMA_HWA_GetInnerLoopDestOffsetEnableFlag(pDma, u8Channel); + if ((bDmaInnerLoopSrcOffsetEnable == false) && (bDmaInnerLoopDestOffsetEnable == false)) + { + u32TmpVal = 0U; + } + else + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFYES & DMA_CFG_NBYTES_ILOFFYES_ILOFF_MASK) >> + DMA_CFG_NBYTES_ILOFFYES_ILOFF_SHIFT; + } + } + /* Convert sign-extended 20bit value to signed 32bit value */ + if ((u32TmpVal & (1U << 19U)) != 0U) + { + u32TmpVal |= 0xFFF00000U; + } + return (int32_t)u32TmpVal; +} + +/** + * @brief Get the transfer data size of the inner loop + * @note if inner loop mapping is disabled, the range is 0~2^31-1 + * if inner loop mapping is enabled and inner loop offset is disabled, the range is 0~2^30-1 + * if inner loop mapping is enabled and inner loop offset is enabled, the range is 0~2^10-1 + * 0 means 2^32 + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint32_t the transfer data size of the inner loop + */ +LOCAL_INLINE uint32_t DMA_HWA_GetInnerLoopSize(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + u32TmpVal = pDma->CFG[u8Channel].NBYTES.ILNO; + } + else + { + bool bDmaInnerLoopSrcOffsetEnable = DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(pDma, u8Channel); + bool bDmaInnerLoopDestOffsetEnable = DMA_HWA_GetInnerLoopDestOffsetEnableFlag(pDma, u8Channel); + if ((bDmaInnerLoopSrcOffsetEnable == false) && (bDmaInnerLoopDestOffsetEnable == false)) + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFNO & DMA_CFG_NBYTES_ILOFFNO_NBYTES_MASK) >> + DMA_CFG_NBYTES_ILOFFNO_NBYTES_SHIFT; + } + else + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFYES & DMA_CFG_NBYTES_ILOFFYES_NBYTES_MASK) >> + DMA_CFG_NBYTES_ILOFFYES_NBYTES_SHIFT; + } + } + return u32TmpVal; +} + +/** + * @brief Set the inner loop offset of the DMA channel + * + * @note the inner loop offset can only be enabled when inner loop mapping is enabled + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnableSrcOffset whether to enable source address inner loop offset + * @param bEnableDestOffset whether to enable destination address inner loop offset + * @param s32Offset the inner loop offset + */ +LOCAL_INLINE void DMA_HWA_SetInnerLoopOffset(DMA_Type *const pDma, uint8_t u8Channel, bool bEnableSrcOffset, + bool bEnableDestOffset, int32_t s32Offset) +{ + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + //ignore the action + } + else + { + if ((bEnableSrcOffset == false) && (bEnableDestOffset == false)) + { + bool bDmaInnerLoopSrcOffsetEnable = DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(pDma, u8Channel); + bool bDmaInnerLoopDestOffsetEnable = DMA_HWA_GetInnerLoopDestOffsetEnableFlag(pDma, u8Channel); + /* If inner loop offset is enabled, to disable inner loop offset, we should clear the inner + loop offset enable bit and meanwhile the inner loop offset bits */ + if ((bDmaInnerLoopSrcOffsetEnable == true) || (bDmaInnerLoopDestOffsetEnable == true)) + { + pDma->CFG[u8Channel].NBYTES.ILOFFNO &= ~(DMA_CFG_NBYTES_ILOFFNO_SILOE_MASK | DMA_CFG_NBYTES_ILOFFNO_DILOE_MASK | + DMA_CFG_NBYTES_ILOFFYES_ILOFF_MASK); + } + } + else + { + pDma->CFG[u8Channel].NBYTES.ILOFFYES = (pDma->CFG[u8Channel].NBYTES.ILOFFYES & ~(DMA_CFG_NBYTES_ILOFFYES_SILOE_MASK | + DMA_CFG_NBYTES_ILOFFYES_DILOE_MASK | DMA_CFG_NBYTES_ILOFFYES_ILOFF_MASK)) | + DMA_CFG_NBYTES_ILOFFYES_SILOE(bEnableSrcOffset) | + DMA_CFG_NBYTES_ILOFFYES_DILOE(bEnableDestOffset) | + DMA_CFG_NBYTES_ILOFFYES_ILOFF(s32Offset); + } + } +} + +/** + * @brief Set the transfer data size of the inner loop + * @note if inner loop mapping is disabled, the range is 0~2^31-1 + * if inner loop mapping is enabled and inner loop offset is disabled, the range is 0~2^30-1 + * if inner loop mapping is enabled and inner loop offset is enabled, the range is 0~2^10-1 + * 0 means 2^32 + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u32Size the transfer data size of the inner loop + */ +LOCAL_INLINE void DMA_HWA_SetInnerLoopSize(DMA_Type *const pDma, uint8_t u8Channel, uint32_t u32Size) +{ + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + pDma->CFG[u8Channel].NBYTES.ILNO = DMA_CFG_NBYTES_ILNO_NBYTES(u32Size); + } + else + { + bool bDmaInnerLoopSrcOffsetEnable = DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(pDma, u8Channel); + bool bDmaInnerLoopDestOffsetEnable = DMA_HWA_GetInnerLoopDestOffsetEnableFlag(pDma, u8Channel); + if ((bDmaInnerLoopSrcOffsetEnable == false) && (bDmaInnerLoopDestOffsetEnable == false)) + { + pDma->CFG[u8Channel].NBYTES.ILOFFNO = (pDma->CFG[u8Channel].NBYTES.ILOFFNO & ~DMA_CFG_NBYTES_ILOFFNO_NBYTES_MASK) | + DMA_CFG_NBYTES_ILOFFNO_NBYTES(u32Size); + } + else + { + pDma->CFG[u8Channel].NBYTES.ILOFFYES = (pDma->CFG[u8Channel].NBYTES.ILOFFYES & ~DMA_CFG_NBYTES_ILOFFYES_NBYTES_MASK) | + DMA_CFG_NBYTES_ILOFFYES_NBYTES(u32Size); + } + } +} + +/** + * @brief Get whether current channel to channel trig is enabled when inner loop complete + * @note this field shall always be same with the beginning channel to channel trig enable flag + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true channel to channel trig is enabled when inner loop complete + * @return false channel to channel trig is disabled when inner loop complete + */ +LOCAL_INLINE bool DMA_HWA_GetCurrentChannelToChannelTrigEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CLC.CHTRGENNO & DMA_CFG_CLC_CHTRGENNO_CHTRGEN_MASK) >> + DMA_CFG_CLC_CHTRGENNO_CHTRGEN_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the target channel when current channel to channel trig is enabled + * @note this field shall always be same with the beginning traget channel trig field + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the target channel + */ +LOCAL_INLINE uint8_t DMA_HWA_GetCurrentChannelToChannelTrigChannel(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal; + if (DMA_HWA_GetCurrentChannelToChannelTrigEnableFlag(pDma, u8Channel) == true) + { + u16TmpVal = (pDma->CFG[u8Channel].CLC.CHTRGENYES & DMA_CFG_CLC_CHTRGENYES_TRGCH_MASK) >> + DMA_CFG_CLC_CHTRGENYES_TRGCH_SHIFT; + } + else + { + u16TmpVal = 0U; + } + return (uint8_t)u16TmpVal; +} + +/** + * @brief Get the current loop count + * The current loop count is the same as the beginning loop count initially, and it will decrement + * each time a inner loop finishes + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint16_t the current loop count + */ +LOCAL_INLINE uint16_t DMA_HWA_GetCurrentLoopCount(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal; + if (DMA_HWA_GetCurrentChannelToChannelTrigEnableFlag(pDma, u8Channel) == false) + { + u16TmpVal = (pDma->CFG[u8Channel].CLC.CHTRGENNO & DMA_CFG_CLC_CHTRGENNO_CLC_MASK) >> DMA_CFG_CLC_CHTRGENNO_CLC_SHIFT; + } + else + { + u16TmpVal = (pDma->CFG[u8Channel].CLC.CHTRGENYES & DMA_CFG_CLC_CHTRGENYES_CLC_MASK) >> DMA_CFG_CLC_CHTRGENYES_CLC_SHIFT; + } + return u16TmpVal; +} + +/** + * @brief Get whether beginning channel to channel trig is enabled when inner loop complete + * @note this field shall always be same with the current channel to channel trig enable flag + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true channel to channel trig is enabled when inner loop complete + * @return false channel to channel trig is disabled when inner loop complete + */ +LOCAL_INLINE bool DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].BLC.CHTRGENNO & DMA_CFG_BLC_CHTRGENNO_CHTRGEN_MASK) >> + DMA_CFG_BLC_CHTRGENNO_CHTRGEN_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the target channel when beginning channel to channel trig is enabled + * @note this field shall always be same with the current traget channel trig field + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the target channel + */ +LOCAL_INLINE uint8_t DMA_HWA_GetBeginningChannelToChannelTrigChannel(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal; + if (DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(pDma, u8Channel) == true) + { + u16TmpVal = (pDma->CFG[u8Channel].BLC.CHTRGENYES & DMA_CFG_BLC_CHTRGENYES_TRGCH_MASK) >> + DMA_CFG_BLC_CHTRGENYES_TRGCH_SHIFT; + } + else + { + u16TmpVal = 0U; + } + return (uint8_t)u16TmpVal; +} + +/** + * @brief Get the beginning loop count + * This field specifies how many inner loops will be executed in a DMA transfer + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint16_t the beginning loop count + */ +LOCAL_INLINE uint16_t DMA_HWA_GetBeginningLoopCount(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal; + if (DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(pDma, u8Channel) == false) + { + u16TmpVal = (pDma->CFG[u8Channel].BLC.CHTRGENNO & DMA_CFG_BLC_CHTRGENNO_BLC_MASK) >> DMA_CFG_BLC_CHTRGENNO_BLC_SHIFT; + } + else + { + u16TmpVal = (pDma->CFG[u8Channel].BLC.CHTRGENYES & DMA_CFG_BLC_CHTRGENYES_BLC_MASK) >> DMA_CFG_BLC_CHTRGENYES_BLC_SHIFT; + } + return u16TmpVal; +} + +/** + * @brief Set channel to channel trig when inner loop complete + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnable whether to enbable channel to channel trig when inner loop complete + * @param u8TrigChannel the target channel + */ +LOCAL_INLINE void DMA_HWA_SetChannelToChannelTrig(DMA_Type *const pDma, uint8_t u8Channel, bool bEnable, + uint8_t u8TrigChannel) +{ + if (bEnable == false) + { + if (DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(pDma, u8Channel) == true) + { + pDma->CFG[u8Channel].BLC.CHTRGENNO &= ~(DMA_CFG_BLC_CHTRGENNO_CHTRGEN_MASK); + pDma->CFG[u8Channel].CLC.CHTRGENNO &= ~(DMA_CFG_CLC_CHTRGENNO_CHTRGEN_MASK); + } + } + else + { + pDma->CFG[u8Channel].BLC.CHTRGENYES = (pDma->CFG[u8Channel].BLC.CHTRGENYES & + ~(DMA_CFG_BLC_CHTRGENYES_CHTRGEN_MASK | DMA_CFG_BLC_CHTRGENYES_TRGCH_MASK)) | + DMA_CFG_BLC_CHTRGENYES_CHTRGEN(bEnable) | DMA_CFG_BLC_CHTRGENYES_TRGCH(u8TrigChannel); + pDma->CFG[u8Channel].CLC.CHTRGENYES = (pDma->CFG[u8Channel].CLC.CHTRGENYES & + ~(DMA_CFG_CLC_CHTRGENYES_CHTRGEN_MASK | DMA_CFG_CLC_CHTRGENYES_TRGCH_MASK)) | + DMA_CFG_CLC_CHTRGENYES_CHTRGEN(bEnable) | DMA_CFG_CLC_CHTRGENYES_TRGCH(u8TrigChannel); + } +} + +/** + * @brief Set the loop count of the DMA transfer + * This field specifies how many inner loops will be executed in a DMA transfer + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u16LoopCnt the inner loop count in a DMA transfer + */ +LOCAL_INLINE void DMA_HWA_SetLoopCount(DMA_Type *const pDma, uint8_t u8Channel, uint16_t u16LoopCnt) +{ + if (DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(pDma, u8Channel) == false) + { + pDma->CFG[u8Channel].BLC.CHTRGENNO = (pDma->CFG[u8Channel].BLC.CHTRGENNO & ~DMA_CFG_BLC_CHTRGENNO_BLC_MASK) | + DMA_CFG_BLC_CHTRGENNO_BLC(u16LoopCnt); + pDma->CFG[u8Channel].CLC.CHTRGENNO = (pDma->CFG[u8Channel].CLC.CHTRGENNO & ~DMA_CFG_CLC_CHTRGENNO_CLC_MASK) | + DMA_CFG_CLC_CHTRGENNO_CLC(u16LoopCnt); + } + else + { + pDma->CFG[u8Channel].BLC.CHTRGENYES = (pDma->CFG[u8Channel].BLC.CHTRGENYES & ~DMA_CFG_BLC_CHTRGENYES_BLC_MASK) | + DMA_CFG_BLC_CHTRGENYES_BLC(u16LoopCnt); + pDma->CFG[u8Channel].CLC.CHTRGENYES = (pDma->CFG[u8Channel].CLC.CHTRGENYES & ~DMA_CFG_CLC_CHTRGENYES_CLC_MASK) | + DMA_CFG_CLC_CHTRGENYES_CLC(u16LoopCnt); + } +} + +/** + * @brief Get the unalign modulo index selection + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the unalign modulo index selection + */ +LOCAL_INLINE uint8_t DMA_HWA_GetUnalignModuloSel(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_UMS_MASK) >> DMA_CFG_CSR_UMS_SHIFT; + return (uint8_t)u16TmpVal; +} + +/** + * @brief Set the unalign modulo index selection + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8UnalignModuloSel the unalign modulo index selection + */ +LOCAL_INLINE void DMA_HWA_SetUnalignModuloSel(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8UnalignModuloSel) +{ + pDma->CFG[u8Channel].CSR = (pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_UMS_MASK) | DMA_CFG_CSR_UMS(u8UnalignModuloSel); +} + +/** + * @brief Get the target channel to trig when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the target channel + */ +LOCAL_INLINE uint8_t DMA_HWA_GetOuterLoopTrigChannel(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_OTRGCH_MASK) >> DMA_CFG_CSR_OTRGCH_SHIFT; + return (uint8_t)u16TmpVal; +} + +/** + * @brief Set the target channel to trig when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8TrigChannel the target channel + */ +LOCAL_INLINE void DMA_HWA_SetOuterLoopTrigChannel(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8TrigChannel) +{ + pDma->CFG[u8Channel].CSR = (pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_OTRGCH_MASK) | DMA_CFG_CSR_OTRGCH(u8TrigChannel); +} + +/** + * @brief Get whether the transfer is done on the selected channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true the transfer is done + * @return false the transfer has not done + */ +LOCAL_INLINE bool DMA_HWA_GetChannelDoneStatus(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_DONE_MASK) >> DMA_CFG_CSR_DONE_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the active status of the DMA channel + * This flag signals the channel is currently in execution. It is set when channel service begins, + * and is cleared by the DMA as the inner loop completes or when any error condition is detected + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true the channel is in execution + * @return false the channel is idle + */ +LOCAL_INLINE DMA_RunningStatusType DMA_HWA_GetChannelActiveStatus(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_ACTIVE_MASK) >> DMA_CFG_CSR_ACTIVE_SHIFT; + return (DMA_RunningStatusType)u16TmpVal; +} + +/** + * @brief Get channel to channel trig is enabled when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true the target channel will be trigged when outer loop is completed + * @return false the channel to channel trig when outer loop is completed is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetOuterLoopTrigEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_OCHTRGEN_MASK) >> DMA_CFG_CSR_OCHTRGEN_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable channel to channel trig when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnable whether to enable channel to channel trig when outer loop is completed + */ +LOCAL_INLINE void DMA_HWA_SetOuterLoopTrigEnableFlag(DMA_Type *const pDma, uint8_t u8Channel, bool bEnable) +{ + pDma->CFG[u8Channel].CSR = (pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_OCHTRGEN_MASK) | DMA_CFG_CSR_OCHTRGEN(bEnable); +} + +/** + * @brief Get whether DMA request will be disabled automatically when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true DMA request will be disabled automatically when outer loop is completed + * @return false DMA request will not be cleared when outer loop is completed + */ +LOCAL_INLINE bool DMA_HWA_GetAutoDisableReuqestEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_DREQ_MASK) >> DMA_CFG_CSR_DREQ_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to disable DMA request automatically when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnable whether to disable DMA request automatically when outer loop is completed + */ +LOCAL_INLINE void DMA_HWA_SetAutoDisableReuqestEnableFlag(DMA_Type *const pDma, uint8_t u8Channel, bool bEnable) +{ + pDma->CFG[u8Channel].CSR = (pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_DREQ_MASK) | DMA_CFG_CSR_DREQ(bEnable); +} + +/** + * @brief Get whether DMA interrupt wiil be generated when the outer loop is half done + * @note When outer loop count is 1, do not enable half complete interrupt + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true DMA will generate interrupt when outer loop is half done + * @return true DMA will not generate interrupt when outer loop is half done + */ +LOCAL_INLINE bool DMA_HWA_GetHalfCompleteInterruptEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_INTHALF_MASK) >> DMA_CFG_CSR_INTHALF_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable DMA interrupt when the outer loop is half done + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnable whether to enable DMA interrupt when the outer loop is half done + */ +LOCAL_INLINE void DMA_HWA_SetHalfCompleteInterruptEnableFlag(DMA_Type *const pDma, uint8_t u8Channel, bool bEnable) +{ + pDma->CFG[u8Channel].CSR = (pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_INTHALF_MASK) | DMA_CFG_CSR_INTHALF(bEnable); +} + +/** + * @brief Get whether DMA interrupt is enabled when DMA transfer is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true DMA will generate interrupt when outer loop is completed + * @return false DMA will not generate interrupt when outer loop is completed + */ +LOCAL_INLINE bool DMA_HWA_GetTransferCompleteInterruptEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_INTOUTER_MASK) >> DMA_CFG_CSR_INTOUTER_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable DMA transfer complete interrupt + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_EnableTransferCompleteInterrupt(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CFG[u8Channel].CSR |= DMA_CFG_CSR_INTOUTER_MASK; +} + +/** + * @brief Disable DMA transfer complete interrupt + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_DisableTransferCompleteInterrupt(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CFG[u8Channel].CSR &= ~DMA_CFG_CSR_INTOUTER_MASK; +} + +/** + * @brief Get whether the DMA start is requested but has not been executed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true the DMA start is requested but has not been executed + * @return false the DMA start is not requested or it has started execution + */ +LOCAL_INLINE bool DMA_HWA_GetWaitStartFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_START_MASK) >> DMA_CFG_CSR_START_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Get DMA channel control and status + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint16_t control and status of the selected channel + */ +LOCAL_INLINE uint16_t DMA_HWA_GetChannelControlStatus(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return pDma->CFG[u8Channel].CSR; +} + +/** + * @brief Set DMA channel control and status + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u16Setting control settings of the selected channel + */ +LOCAL_INLINE void DMA_HWA_SetChannelControlStatus(DMA_Type *const pDma, uint8_t u8Channel, uint16_t u16Setting) +{ + pDma->CFG[u8Channel].CSR = u16Setting; +} + +/** @}*/ + +#endif /* _HWA_DMA_H_ */ diff --git a/Inc/HwA_dmamux.h b/Inc/HwA_dmamux.h new file mode 100644 index 0000000..8c31777 --- /dev/null +++ b/Inc/HwA_dmamux.h @@ -0,0 +1,210 @@ +/** + * @file HwA_dmamux.h + * @author Flagchip0126 + * @brief Hardware access layer for DMAMUX + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_DMAMUX_H_ +#define _HWA_DMAMUX_H_ + +#include "device_header.h" + +/** + * @defgroup HwA_dmamux + * @ingroup fc7xxx_driver_dma + * @{ + */ + +/** + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum +{ + DMA_REQ_DISABLED = 0U, + DMA_REQ_FCIIC0_RX = 1U, + DMA_REQ_FCIIC0_TX = 2U, + DMA_REQ_FCIIC1_RX = 3U, + DMA_REQ_FCIIC1_TX = 4U, + DMA_REQ_FCSPI0_RX = 5U, + DMA_REQ_FCSPI0_TX = 6U, + DMA_REQ_FCSPI1_RX = 7U, + DMA_REQ_FCSPI1_TX = 8U, + DMA_REQ_FCSPI2_RX = 9U, + DMA_REQ_FCSPI2_TX = 10U, + DMA_REQ_FCSPI3_RX = 11U, + DMA_REQ_FCSPI3_TX = 12U, + DMA_REQ_FCSPI4_RX = 13U, + DMA_REQ_FCSPI4_TX = 14U, + DMA_REQ_FCSPI5_RX = 15U, + DMA_REQ_FCSPI5_TX = 16U, + /* 17 ~ 22 reserved */ + DMA_REQ_FLEXCAN0 = 23U, + DMA_REQ_FLEXCAN1 = 24U, + DMA_REQ_FLEXCAN2 = 25U, + DMA_REQ_FLEXCAN3 = 26U, + /* 27 ~ 32 reserved */ + DMA_REQ_ADC0 = 33U, + DMA_REQ_ADC1 = 34U, + /* 35 ~ 40 reserved */ + DMA_REQ_FCUART0_RX = 41U, + DMA_REQ_FCUART0_TX = 42U, + DMA_REQ_FCUART1_RX = 43U, + DMA_REQ_FCUART1_TX = 44U, + DMA_REQ_FCUART2_RX = 45U, + DMA_REQ_FCUART2_TX = 46U, + DMA_REQ_FCUART3_RX = 47U, + DMA_REQ_FCUART3_TX = 48U, + DMA_REQ_FCUART4_RX = 49U, + DMA_REQ_FCUART4_TX = 50U, + DMA_REQ_FCUART5_RX = 51U, + DMA_REQ_FCUART5_TX = 52U, + DMA_REQ_FCUART6_RX = 53U, + DMA_REQ_FCUART6_TX = 54U, + DMA_REQ_FCUART7_RX = 55U, + DMA_REQ_FCUART7_TX = 56U, + /* 57 ~ 58 reserved */ + DMA_REQ_TPU0 = 59U, + DMA_REQ_TPU1 = 60U, + DMA_REQ_TPU2 = 61U, + DMA_REQ_TPU3 = 62U, + DMA_REQ_TPU4 = 63U, + DMA_REQ_TPU5 = 64U, + DMA_REQ_TPU6 = 65U, + DMA_REQ_TPU7 = 66U, + DMA_REQ_TPU8 = 67U, + DMA_REQ_TPU9 = 68U, + DMA_REQ_TPU10 = 69U, + DMA_REQ_TPU11 = 70U, + DMA_REQ_TPU12 = 71U, + DMA_REQ_TPU13 = 72U, + DMA_REQ_TPU14 = 73U, + DMA_REQ_TPU15 = 74U, + DMA_REQ_TPU16TO23 = 75U, + DMA_REQ_TPU24TO31 = 76U, + DMA_REQ_PORTA = 77U, + DMA_REQ_PORTB = 78U, + DMA_REQ_PORTC = 79U, + DMA_REQ_PORTD = 80U, + DMA_REQ_PORTE = 81U, + /* 82 ~ 85 reserved */ + DMA_REQ_AONTIMER0 = 86U, + DMA_REQ_CMP0 = 87U, + DMA_REQ_CMP1 = 88U, + /* 89 reserved */ + DMA_REQ_PTIMER0 = 90U, + DMA_REQ_PTIMER1 = 91U, + /* 92 ~ 97 reserved */ + DMA_REQ_FTU0_ALL_CH_OR = 98U, + DMA_REQ_FTU1_ALL_CH_OR = 99U, + DMA_REQ_FTU2_ALL_CH_OR = 100U, + DMA_REQ_FTU3_ALL_CH_OR = 101U, + DMA_REQ_FTU4_ALL_CH_OR = 102U, + DMA_REQ_FTU5_ALL_CH_OR = 103U, + DMA_REQ_FTU6_ALL_CH_OR = 104U, + DMA_REQ_FTU7_ALL_CH_OR = 105U, + /* 106 ~ 109 reserved */ + DMA_REQ_SENT0_CH0_FAST = 110U, + DMA_REQ_SENT0_CH1_FAST = 111U, + DMA_REQ_SENT0_CH2_FAST = 112U, + DMA_REQ_SENT0_CH3_FAST = 113U, + /* 114 ~ 117 reserved */ + DMA_REQ_SENT0_CH0_SLOW = 118U, + DMA_REQ_SENT0_CH1_SLOW = 119U, + DMA_REQ_SENT0_CH2_SLOW = 120U, + DMA_REQ_SENT0_CH3_SLOW = 121U, + /* 122 ~ 125 reserved */ + DMA_REQ_ALWAYS_ENABLE_0 = 126U, + DMA_REQ_ALWAYS_ENABLE_1 = 127U +} DMA_RequestSourceType; + +/** + * @brief Get whether DMAMUX is enabled for the specified DMA channel + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @return true DMAMUX is enabled for the specified DMA channel + * @return false DMAMUX is disabled for the specified DMA channel + */ +LOCAL_INLINE bool DMAMUX_HWA_GetEnableFlag(const DMAMUX_Type *const pDmamux, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pDmamux->CHCFG[u8Channel] & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT; + return (bool)((u8TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the request source for the specified DMA channel + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @return DMA_RequestSourceType the request source of the specified DMA channel + */ +LOCAL_INLINE DMA_RequestSourceType DMAMUX_HWA_GetRequestSource(const DMAMUX_Type *const pDmamux, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pDmamux->CHCFG[u8Channel] & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT; + return (DMA_RequestSourceType)u8TmpVal; +} + +/** + * @brief Set the request source for the specified DMA channel + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @param bEnable whether to enable DMAMUX for the specified DMA channel + * @param eReqSrc the request source to set for the specified DMA channel + */ +LOCAL_INLINE void DMAMUX_HWA_SetRequestSource(DMAMUX_Type *const pDmamux, uint8_t u8Channel, bool bEnable, + DMA_RequestSourceType eReqSrc) +{ + pDmamux->CHCFG[u8Channel] = (pDmamux->CHCFG[u8Channel] & ~(DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE_MASK)) | + DMAMUX_CHCFG_ENBL(bEnable) | DMAMUX_CHCFG_SOURCE(eReqSrc); +} + +/** + * @brief Get whether periodic trig is enabled for the specified DMA channel + * + * @note Only DMA channel 0~3 supports periodic trig + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @return true periodic trig is enabled for the specified DMA channel + * @return true periodic trig is disabled for the specified DMA channel + */ +LOCAL_INLINE bool DMAMUX_HWA_GetPeriodicTrigFlag(const DMAMUX_Type *const pDmamux, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pDmamux->CHTRG & (DMAMUX_CHTRG_TRIG_MASK << u8Channel)) >> u8Channel; + return (bool)((u8TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable periodic trig for the specified DMA channel + * + * @note Only DMA channel 0~3 supports periodic trig + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @param bEnable whether to enable periodic trig for the specified DMA channel + */ +LOCAL_INLINE void DMAMUX_HWA_SetPeriodicTrigFlag(DMAMUX_Type *const pDmamux, uint8_t u8Channel, bool bEnable) +{ + pDmamux->CHTRG = (pDmamux->CHTRG & ~(DMAMUX_CHTRG_TRIG_MASK << u8Channel)) | (DMAMUX_CHTRG_TRIG(bEnable) << u8Channel); +} + +/** @}*/ + +#endif /* _HWA_DMAMUX_H_ */ diff --git a/Inc/HwA_eim.h b/Inc/HwA_eim.h new file mode 100644 index 0000000..073a970 --- /dev/null +++ b/Inc/HwA_eim.h @@ -0,0 +1,276 @@ +/** + * @file HwA_eim.h + * @author Flagchip + * @brief FC7xxx FCEim register API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 qxw0100 N/A FC7240 Eim first version + *********************************************************************************/ + +#ifndef HWA_INCLUDE_HWA_EIM_H_ +#define HWA_INCLUDE_HWA_EIM_H_ +#include "device_header.h" +#define EIM_MAXCHANNEL 76U /*!< EIM max channel support */ + +/** + * @defgroup HwA_eim + * @ingroup HwA_eim + * @{ + */ + +/** @brief EIM channel number configuration type */ +typedef enum +{ + EIM_MAM0_S0 = 0U, /*!< Channel 0 SCM Matrix Access Monitor Error Inection0(MAM0_S0) */ + EIM_MAM0_S1 = 1U, /*!< Channel 1 SCM Matrix Access Monitor Error Inection1(MAM0_S1) */ + EIM_MAM0_S2 = 2U, /*!< Channel 2 SCM Matrix Access Monitor Error Inection2(MAM0_S2) */ + EIM_MAM0_S3 = 4U, /*!< Channel 4 SCM Matrix Access Monitor Error Inection3(MAM0_S3) */ + EIM_MAM0_S4 = 5U, /*!< Channel 5 SCM Matrix Access Monitor Error Inection4(MAM0_S4) */ + EIM_MAM0_S5 = 7U, /*!< Channel 7 SCM Matrix Access Monitor Error Inection5(MAM0_S5) */ + EIM_MAM0_S6 = 8U, /*!< Channel 8 SCM Matrix Access Monitor Error Inection6(MAM0_S6) */ + EIM_MAM0_S7 = 9U, /*!< Channel 9 SCM Matrix Access Monitor Error Inection7(MAM0_S7) */ + EIM_MAM0_S8 = 10U, /*!< Channel 10 SCM Matrix Access Monitor Error Inection8(MAM0_S8) */ + EIM_CPU0_AHBM = 11U, /*!< Channel 11 SCM Matrix Access Monitor Error Inection9(CPU0_AHBM) */ + EIM_CPU0_AHBP = 12U, /*!< Channel 12 SCM Matrix Access Monitor Error Inection10(CPU0_AHBP) */ + EIM_HSM = 18U, /*!< Channel 18 SCM Matrix Access Monitor Error Inection12(HSM) */ + EIM_DMA0 = 19U, /*!< Channel 19 SCM Matrix Access Monitor Error Inection13(DMA0) */ + EIM_CPU0_AHBS = 21U, /*!< Channel 21 SCM Matrix Access Monitor Error Inection11(CPU0_AHBS) */ + EIM_CPU0_ITCM = 24U, /*!< Channel 24 CPU0_ITCM */ + EIM_CPU0_DTCM0 = 25U, /*!< Channel 25 CPU0_DTCM0 */ + EIM_CPU0_DTCM1 = 26U, /*!< Channel 26 CPU0_DTCM1 */ + EIM_SRAM0 = 33U, /*!< Channel 33 SRAM0_INJECTION */ + EIM_SRAM1 = 34U, /*!< Channel 34 SRAM1_INJECTION */ + EIM_CPU0DCACHE_DATA0_01 = 36U, /*!< Channel 36 CPU0_DCACHE_DATA0_01 Injection */ + EIM_CPU0DCACHE_DATA0_23 = 37U, /*!< Channel 37 CPU0_DCACHE_DATA0_23 Injection */ + EIM_CPU0DCACHE_DATA1_01 = 38U, /*!< Channel 38 CPU0_DCACHE_DATA1_01 Injection */ + EIM_CPU0DCACHE_DATA1_23 = 39U, /*!< Channel 39 CPU0_DCACHE_DATA1_23 Injection */ + EIM_CPU0DCACHE_TAG_01 = 40U, /*!< Channel 40 CPU0_DCACHE_TAG_01 Injection */ + EIM_CPU0DCACHE_TAG_23 = 41U, /*!< Channel 41 CPU0_DCACHE_TAG_23 Injection */ + EIM_CPU0ICACHE_DATA0 = 42U, /*!< Channel 42 CPU0_ICACHE_DATA0 Injection */ + EIM_CPU0ICACHE_DATA1 = 43U, /*!< Channel 43 CPU0_ICACHE_DATA1 Injection */ + EIM_CPU0ICACHE_TAG = 44U, /*!< Channel 44 CPU0_ICACHE_TAG Injection */ + EIM_SCM_S5_DOWNSIZE = 63U, /*!< Channel 63 SCM S5 64:32 DownSize Monitor Error Injection */ + EIM_DMA0_CFG = 65U, /*!< Channel 65 DMA0_CFG_ECC Injection */ + EIM_ROM_ECC = 67U, /*!< Channel 67 ROM_ECC Injection */ + EIM_SCM_S5_DOWNSIZE_AHBS = 68U, /*!< Channel 68 SCM S5 DownSize ECC Check with AHBS Error Injection */ + EIM_CPU0AHBP_AHBS_MONITOR = 70U, /*!< Channel 70 SCM CPU0 AHBP and AHBS gasket Monitor Error Injection */ + EIM_SCM_S8_DOWNSIZE_MONITOR = 75U, /*!< Channel 75 SCM S8 64:32 DownSize Monitor Error Injection */ + EIM_RAM_DECODER_MONITOR = 77U, /*!< Channel 77 RAM Decoder Monitor Error Injection */ + EIM_AFCB0_MONITOR = 78U, /*!< Channel 78 AFCB0 Monitor Error Injection */ + EIM_AFCB1_MONITOR = 79U, /*!< Channel 79 AFCB1 Monitor Error Injection */ + EIM_CPU0_OVERLAY_MONITOR = 80U, /*!< Channel 80 CPU0 Overlay Monitor */ + EIM_HSM_DRAM = 82U, /*!< Channel 82 HSM DRAM ECC Error Injection */ + EIM_HSM_IRAM = 83U, /*!< Channel 83 HSM IRAM ECC Error Injection */ +} EIM_ChannelType; + +/** @brief EIM Lockstep channel configuration type */ +typedef enum +{ + EIM_CPU0_LOCKSTEP, /*!< CPU0 LOCKSTEP Injection */ + EIM_CHNTYPE_RESVD, + EIM_DMA0_LOCKSTEP, /*!< DMA0 LOCKSTEP Injection */ +} EIM_CPU_ChnType; + +/** @brief EIM CPU monitor configuration type */ +typedef enum +{ + EIM_MONITOR0, /*!< CPU0 LOCKSTEP monitor0 Injection */ + EIM_MONITOR1, /*!< CPU0 LOCKSTEP monitor1 Injection */ +} EIM_MONType; + +/** @brief Eim return type. */ + +typedef enum +{ + EIM_STATUS_SUCCESS = 0U, /*!< EIM status success */ + EIM_STATUS_PARAM_INVALID = 1U /*!< EIM status parameter invalid */ +} EIM_RetType; + +/** + * @brief Select the EIM DWP mode + * + */ +typedef enum +{ + EIM_CPU0ALLOWED_0 = 0U, /**< cpu0 is allowed */ + EIM_CPU0ALLOWED_1 = 1U, /**< cpu0 is allowed */ +} EIM_DWPType; + +/** + * @brief Select error injection bus sel + * + */ +typedef enum +{ + EIM_BUSREG0 = 0U, /**< Sel bus REG0 to injection */ + EIM_BUSREG1 = 1U, /**< Sel bus REG1 to injection */ + EIM_BUSREG2 = 2U, /**< Sel bus REG2 to injection */ + EIM_BUSREG3 = 3U /**< Sel bus REG3 to injection */ +} EIM_BUSChnType; +/** + * @brief Select the EIM InitType + * + */ +typedef struct +{ + uint8_t u8EimChn; + uint8_t u8BusSelIdx; + uint8_t u8Attreenable; + uint8_t u8AttrPosition; + uint8_t u8Addreenable; + uint8_t u8AddrePosition; + uint8_t u8Data0enable; + uint8_t u8Data0Val; + uint8_t u8Data1enable; + uint8_t u8Data1Val; +} EIM_InitType; + +/** + * @brief Select the CPU Lockstep InitType + * + */ +typedef struct +{ + uint8_t u8CpuChn; + uint8_t u8Monitor0Set; + uint8_t u8Monitor0Clr; + uint8_t u8Monitor1Set; + uint8_t u8Monitor1Clr; +} EIM_CpuLockType; + + +/** + * @brief Enable EIM Global Error Injection + * + */ +LOCAL_INLINE void EIM_HWA_EnableGlobalErrorInjection(void) +{ + EIM->CR = 1U; +} + +/** + * @brief Disable EIM Global Error Injection + * + */ +LOCAL_INLINE void EIM_HWA_DisableGlobalErrorInjection(void) +{ + EIM->CR &= ~(uint32_t) EIM_CR_GEIEN_MASK; +} + +/** + * @brief get EIM channel N control register, N:0~82 + * + * @return EIM channel N control register value + */ +LOCAL_INLINE uint32_t EIM_HWA_Get_CtrlRegn(uint8_t idx) +{ + uint32_t u32RegValue; + u32RegValue = EIM->CTRL_REG[idx]; + return u32RegValue; +} + +/** + * @brief get EIM bus register, idx:0~3 + * + * @return EIM bus register value + */ +LOCAL_INLINE uint32_t EIM_HWA_Get_BUSRegn(uint8_t idx) +{ + uint32_t u32RegValue; + u32RegValue = EIM->BUS_REG[idx]; + return u32RegValue; +} + +/** + * @brief Get EIM_CTRL_GEGn register DWP lock status + * @param u8idx index (0~82) + * @return Lock status + */ +LOCAL_INLINE uint8_t EIM_HWA_GetCtrlDWPLockStatus(uint8_t u8idx) +{ + uint32_t u32RegValue; + u32RegValue = EIM->CTRL_REG[u8idx]; + u32RegValue = (u32RegValue & EIM_CTRL_REG_DWP_LOCK_MASK) >> EIM_CTRL_REG_DWP_LOCK_SHIFT; + return (uint8_t)((u32RegValue != 0U) ? true : false); +} + +/** + * @brief set EIM_CTRL_GEGn register DWP lock mode, idx:0~76 + * + * @param u8idx index (0~82) + * @param u8DwpMode DWP mode + */ +LOCAL_INLINE void EIM_HWA_Set_CtrlLockMode(uint8_t u8idx, uint8_t u8DwpMode) +{ + uint32_t u32Value = EIM->CTRL_REG[u8idx]; + EIM->CTRL_REG[u8idx] = ((u32Value & (~(uint32_t)EIM_CTRL_REG_DWP_MASK)) | EIM_CTRL_REG_DWP(u8DwpMode)); +} + +/** + * @brief set EIM_CTRL_GEGn register DWP lock status, idx:0~76 + * + * @param u8idx index (0~82) + * @param u8Enable enable or disable + */ +LOCAL_INLINE void EIM_HWA_CtrlRegnWritePermit(uint8_t u8idx) +{ + uint32_t u32Value = EIM->CTRL_REG[u8idx]; + EIM->CTRL_REG[u8idx] = (u32Value | EIM_CTRL_REG_DWP_LOCK_MASK); +} + +/** + * @brief set eim channel N control register + * + * @param idx index (0~82) + * @param u32RegValue access control value + */ +LOCAL_INLINE void EIM_HWA_Set_CtrlRegn(uint8_t idx, uint32_t u32RegValue) +{ + EIM->CTRL_REG[idx] = u32RegValue; +} + +/** + * @brief set EIM CPU LOCKSTEP error injection register, idx:0~2 + * + * @param idx index (0~2) + * @param u32RegValue access control value + */ +LOCAL_INLINE void EIM_HWA_Set_CPULockstep(uint8_t idx, uint32_t u32RegValue) +{ + *((volatile uint32_t *)(&(EIM->CPU0_LOCKSTEP) + (int32_t)idx)) = u32RegValue; +} + +/** + * @brief set EIM CPU LOCKSTEP error injection register, idx:0~2 + * + * @param idx index (0~2) + * @return access control value + */ +LOCAL_INLINE uint32_t EIM_HWA_Get_CPULockstep(uint8_t idx) +{ + return *((volatile uint32_t *)(&(EIM->CPU0_LOCKSTEP) + (int32_t)idx)); +} + +/** + * @brief set EIM bus register, idx:0~3 + * + * @param idx index (0~3) + * @param u32RegValue access control value + */ +LOCAL_INLINE void EIM_HWA_Set_BUSRegn(uint8_t idx, uint32_t u32RegValue) +{ + EIM->BUS_REG[idx] |= u32RegValue; +} + + +/** @}*/ +#endif /* HWA_INCLUDE_HWA_EIM_H_ */ diff --git a/Inc/HwA_erm.h b/Inc/HwA_erm.h new file mode 100644 index 0000000..b114c70 --- /dev/null +++ b/Inc/HwA_erm.h @@ -0,0 +1,119 @@ +/** + * @file HwA_erm.h + * @author Flagchip + * @brief FC7xxx erm driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 qxw0100 N/A FC7240 Erm first version + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_ERM_H_ +#define HWA_INCLUDE_HWA_ERM_H_ +#include "device_header.h" + +#define ERM_SR_MASK 0xCCCCCCCCu + + +/** + * @defgroup HwA_erm + * @ingroup HwA_erm + * @{ + */ + +/** @brief ERM configuration type */ +typedef enum +{ + ERM_NONE_CORRECTABLE = 1U, /*!< select Non-correctable interrupt report */ + ERM_SINGLE_BIT = 2U /*!< select single correction interrupt report */ +} ERM_InterruptType; + + +/** @brief ERM configuration type */ +typedef enum +{ + ERM_PFLASH0_ECC = 1U, /*!< PFlash0 ECC Error */ + ERM_PFLASH1_ECC = 2U, /*!< PFlash1 ECC Error */ + ERM_DFLASH_ECC = 3U, /*!< DFlash ECC error */ + ERM_DMACFG0_ECC = 4U, /*!< DMACFG0 ECC Error */ + ERM_ROM_ECC = 6U, /*!< ROM ECC Error */ + ERM_SYSRAM0_ECC = 8U, /*!< SysRAM0 ECC ERROR */ + ERM_SYSRAM1_ECC = 9U, /*!< SysRAM1 ECC ERROR */ + ERM_CPU0ITCM_ECC = 11U, /*!< CPU0 ITCM ECC Error */ + ERM_CPU0DTCM0_ECC = 12U, /*!< CPU0 DTCM0 ECC Error */ + ERM_CPU0DTCM1_ECC = 13U, /*!< CPU0 DTCM1 ECC Error */ + ERM_CPU0ICACHE_ECC = 14U, /*!< CPU0 ICACHE ECC Error */ + ERM_CPU0DCACHE_ECC = 15U, /*!< CPU0 DCACHE ECC Error */ + ERM_HSMDRAM_ECC = 26U, /*!< HSM DRAM ECC Error */ + ERM_HSMIRAM_ECC = 27U, /*!< HSM IRAM ECC Error */ +} ERM_ChannelType; + + +/** + * @brief get ERM configuration register 0~3 + * + * @return ERM CRn value + */ +LOCAL_INLINE uint32_t ERM_HWA_Get_CRn(uint8_t idx) +{ + uint32_t u32RegValue; + u32RegValue = *((volatile uint32_t *)(&(ERM->CR0) + (uint32_t)idx)); + return u32RegValue; +} + +/** + * @brief get ERM status register 0~3 + * + * @return ERM SRn value + */ +LOCAL_INLINE uint32_t ERM_HWA_Get_SRn(uint8_t idx) +{ + uint32_t u32RegValue; + u32RegValue = *((volatile uint32_t *)(&(ERM->SR0) + (uint32_t)idx)); + return u32RegValue; +} + +/** + * @brief get ERM error address register 0~25 + * + * @return ERM error address register value + */ +LOCAL_INLINE uint32_t ERM_HWA_Get_EARn(uint8_t idx) +{ + uint32_t u32RegValue; + u32RegValue = *((const volatile uint32_t *)(&(ERM->EAR0) + (uint32_t)idx * 0x10UL/4UL)); + + return u32RegValue; +} + +/** + * @brief set erm configuration register + * + * @param idx index (0~3) + * @param u32RegValue access control value + */ +LOCAL_INLINE void ERM_HWA_Set_CRn(uint8_t idx, uint32_t u32RegValue) +{ + *((volatile uint32_t *)(&(ERM->CR0) + (int32_t)idx)) = u32RegValue; +} +/** + * @brief set erm error address register + * + * @param idx index (0~3) + * @param u32RegValue access control value + */ +LOCAL_INLINE void ERM_HWA_Set_SRn(uint8_t idx, uint32_t u32RegValue) +{ + *((volatile uint32_t *)(&(ERM->SR0) + (int32_t)idx)) = u32RegValue; +} + +/** @}*/ +#endif /* HWA_INCLUDE_HWA_ERM_H_ */ diff --git a/Inc/HwA_fciic.h b/Inc/HwA_fciic.h new file mode 100644 index 0000000..c10014e --- /dev/null +++ b/Inc/HwA_fciic.h @@ -0,0 +1,542 @@ +/** + * @file HwA_fciic.h + * @author Flagchip + * @brief FC7xxx FCIIC hardware access layer + * @version 0.2.0 + * @date 2023-2-14 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022/12/31 qxw0052 N/A First version for FC7300 + * 0.2.0 2023/02/14 qxw0052 N/A Fix MISRA issues + ******************************************************************************** */ + +#ifndef _HWA_FCIIC_H_ +#define _HWA_FCIIC_H_ + +#include "device_header.h" + + +/** + * @addtogroup HwA_fciic + * @{ + */ + + +/* ################################################################################## */ +/* ################################### type define ################################## */ + + +/** + * \brief IIC Command Type Enumeration + * + */ +typedef enum +{ + FCIIC_TX_CMD_TRANSMIT = 0, /**< FCIIC_TX_CMD_TRANSMIT transmit command */ + FCIIC_TX_CMD_RECEIVE, /**< FCIIC_TX_CMD_RECEIVE receive command*/ + FCIIC_TX_CMD_STOP, /**< FCIIC_TX_CMD_STOP stop command */ + FCIIC_TX_CMD_RECANDDISCARD, /**< FCIIC_TX_CMD_RECANDDISCARD receive and discard data command*/ + FCIIC_TX_CMD_STARTANDTRANSMIT, /**< FCIIC_TX_CMD_STARTANDTRANSMIT start and then transmit data */ + FCIIC_TX_CMD_STARTANDTRANSMIT_WITHNAK/**< FCIIC_TX_CMD_STARTANDTRANSMIT_WITHNAK start and then transmit and don't care ACK */ + +} FCIIC_TX_CMDType; + + +/** + * \brief IIC Master status type enumeration + * + */ +typedef enum +{ + FCIIC_MSR_BBF_STATUS = 25U, /**< FCIIC_MSR_BBF_STATUS Bus Busy Flag */ + FCIIC_MSR_MBF_STATUS = 24U, /**< FCIIC_MSR_MBF_STATUS Master Busy Flag */ + FCIIC_MSR_DMF_STATUS = 14U, /**< FCIIC_MSR_DMF_STATUS Data Match Flag */ + FCIIC_MSR_PLTF_STATUS = 13U, /**< FCIIC_MSR_PLTF_STATUS Pin Low Timeout Flag */ + FCIIC_MSR_FEF_STATUS = 12U, /**< FCIIC_MSR_FEF_STATUS FIFO Error Flag */ + FCIIC_MSR_ALF_STATUS = 11U, /**< FCIIC_MSR_ALF_STATUS Arbitration Lost Flag */ + FCIIC_MSR_NDF_STATUS = 10U, /**< FCIIC_MSR_NDF_STATUS NACK Detect Flag */ + FCIIC_MSR_SDF_STATUS = 9U, /**< FCIIC_MSR_SDF_STATUS STOP Detect Flag */ + FCIIC_MSR_EPF_STATUS = 8U, /**< FCIIC_MSR_EPF_STATUS End Packet Flag */ + FCIIC_MSR_RXFPEF_STATUS = 3U, /**< FCIIC_MSR_EPF_STATUS RX FIFO Parity Error Flag */ + FCIIC_MSR_TXFPEF_STATUS = 2U, /**< FCIIC_MSR_EPF_STATUS TX FIFO Parity Error Flag */ + FCIIC_MSR_RDF_STATUS = 1U, /**< FCIIC_MSR_RDF_STATUS Receive Data Flag */ + FCIIC_MSR_TDF_STATUS = 0U /**< FCIIC_MSR_TDF_STATUS Transmit Data Flag */ +} FCIIC_MasterStatusType; + + + +/** + * \brief IIC Slave status type enumeration + * + */ +typedef enum +{ + FCIIC_SSR_BBF_STATUS = 25U, /**< FCIIC_SSR_BBF_STATUS Bus Busy Flag */ + FCIIC_SSR_SBF_STATUS = 24U, /**< FCIIC_SSR_SBF_STATUS Slave Busy Flag */ + FCIIC_SSR_SARF_STATUS = 15U, /**< FCIIC_SSR_SARF_STATUS SMBus Alert Response Flag */ + FCIIC_SSR_GCF_STATUS = 14U, /**< FCIIC_SSR_GCF_STATUS General Call Flag */ + FCIIC_SSR_AM1F_STATUS = 13U, /**< FCIIC_SSR_AM1F_STATUS Address Match 1 Flag */ + FCIIC_SSR_AM0F_STATUS = 12U, /**< FCIIC_SSR_AM0F_STATUS Address Match 0 Flag */ + FCIIC_SSR_TREF_STATUS = 11U, /**< FCIIC_SSR_TREF_STATUS FIFO Error Flag */ + FCIIC_SSR_BEF_STATUS = 10U, /**< FCIIC_SSR_BEF_STATUS Bit Error Flag */ + FCIIC_SSR_SDF_STATUS = 9U, /**< FCIIC_SSR_SDF_STATUS STOP Detect Flag */ + FCIIC_SSR_RSF_STATUS = 8U, /**< FCIIC_SSR_RSF_STATUS Repeated Start Flag */ + FCIIC_SSR_TAF_STATUS = 3U, /**< FCIIC_SSR_TAF_STATUS Transmit ACK Flag */ + FCIIC_SSR_AVF_STATUS = 2U, /**< FCIIC_SSR_AVF_STATUS Address Valid Flag */ + FCIIC_SSR_RDF_STATUS = 1U, /**< FCIIC_SSR_RDF_STATUS Receive Data Flag */ + FCIIC_SSR_TDF_STATUS = 0U, /**< FCIIC_SSR_TDF_STATUS Transmit Data Flag */ +} FCIIC_SlaveStatusType; + + +/** + * \brief Master Transmit Data + * + * \param pFciic IIC instance value + * \param tCmdType is command type + * \param u8Data to transmit + */ +LOCAL_INLINE void FCIIC_Master_HWA_Transmit(FCIIC_Type *pFciic, FCIIC_TX_CMDType tCmdType, uint8_t u8Data) +{ + pFciic->MTDR = FCIIC_MTDR_CMD(tCmdType) | FCIIC_MTDR_DATA(u8Data); +} + +/** + * \brief Master Receive Data + * + * \param pFciic IIC instance value + * \return the data received + */ +LOCAL_INLINE uint8_t FCIIC_Master_HWA_Receive(FCIIC_Type *pFciic) +{ + /* copy data */ + return (uint8_t)((uint8_t)(pFciic->MRDR) & 0xFFU); +} + +/** + * \brief Get and clear IIC master status + * + * \param pFciic is IIC instance value + * \param eStatus is status type + */ +LOCAL_INLINE void FCIIC_Master_HwA_CheckClearStatus(FCIIC_Type *pFciic, FCIIC_MasterStatusType eStatus) +{ + uint32_t u32RetVal; + + u32RetVal = (pFciic->MSR >> eStatus) & 0x01U; + + + if (u32RetVal != 0U) + { + pFciic->MSR |= (1UL << eStatus); /* w1c */ + } +} + +/** + * \brief This Function is used to get master status + * + * \param pFciic is IIC instance value + * \param eStatus is status type enumeration + * \return Status value 0 or 1 and 1 is OK + */ +LOCAL_INLINE uint8_t FCIIC_Master_HWA_GetStatus(FCIIC_Type *pFciic, FCIIC_MasterStatusType eStatus) +{ + uint32_t u32RetVal; + + u32RetVal = (pFciic->MSR >> (uint32_t)eStatus) & 0x01U; + + return (uint8_t)(u32RetVal == 1U ? 1U : 0U); +} + +/** + * \brief This Function is used to clear master status + * + * \param pFciic is IIC instance value + * \param u32Value is the clear bits + */ +LOCAL_INLINE void FCIIC_Master_HWA_ClrStatus(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MSR |= u32Value; +} + +/** + * \brief This Function is used to get slave status + * + * \param pFciic is IIC instance value + * \param eStatus is status type enumeration + * \return Status value 0 or 1 and 1 is OK + */ +LOCAL_INLINE uint8_t FCIIC_Slave_HWA_GetStatus(FCIIC_Type *pFciic, FCIIC_SlaveStatusType eStatus) +{ + uint32_t u32RetVal; + + u32RetVal = (pFciic->SSR >> (uint32_t)eStatus) & 0x01U; + + return (uint8_t)(u32RetVal == 1U ? 1U : 0U); +} + +/** + * \brief This Function is used to clear slave status + * + * \param pFciic is IIC instance value + * \param u32Value is the clear bits value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_ClrStatus(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SSR |= u32Value; +} + +/** + * \brief Slave Transmit Data + * + * \param pFciic IIC instance value + * \param u8Data to transmit + */ +LOCAL_INLINE void FCIIC_Slave_HWA_Transmit(FCIIC_Type *pFciic, uint8_t u8Data) +{ + pFciic->STDR = FCIIC_STDR_DATA(u8Data); +} + + +/** + * \brief Slave Get Data + * + * \param pFciic IIC instance value + * \return the data value + */ +LOCAL_INLINE uint8_t FCIIC_Slave_HWA_Receive(FCIIC_Type *pFciic) +{ + /* copy data */ + return (uint8_t)((uint8_t)(pFciic->SRDR) & 0xFFU); +} + +/** + * \brief Enable Receive Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_EnableReceiveInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER |= FCIIC_MIER_RDIE_MASK; +} + +/** + * \brief Disable Receive Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_DisableReceiveInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER &= ~FCIIC_MIER_RDIE_MASK; +} + +/** + * \brief Enable Error Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_EnableErrorInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER |= FCIIC_MIER_FEIE_MASK; +} + +/** + * \brief Disable Error Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_DisableErrorInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER &= FCIIC_MIER_FEIE_MASK; +} + +/** + * \brief Get Error Flag + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE uint32_t FCIIC_Master_HWA_GetErrorFlag(FCIIC_Type *pFciic) +{ + return pFciic->MSR & FCIIC_MSR_FEF_MASK; +} + +/** + * \brief Clr Error Flag + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_ClrErrorFlag(FCIIC_Type *pFciic) +{ + pFciic->MSR |= FCIIC_MSR_FEF_MASK; +} + +/** + * \brief Enable Transmit Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_EnableTransmitInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER |= FCIIC_MIER_TDIE_MASK; +} + +/** + * \brief Disable Transmit Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_DisableTransmitInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER &= ~FCIIC_MIER_TDIE_MASK; +} + + +/** + * \brief Enable Receive Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_EnableReceiveInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER |= FCIIC_SIER_RDIE_MASK; +} + +/** + * \brief Disable Receive Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_DisableReceiveInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER &= ~FCIIC_SIER_RDIE_MASK; +} + +/** + * \brief Enable Error Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_EnableErrorInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER |= FCIIC_SIER_TREIE_MASK | FCIIC_SIER_BEIE_MASK ; +} + +/** + * \brief Disable Error Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_DisableErrorInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER &= ~(FCIIC_SIER_TREIE_MASK | FCIIC_SIER_BEIE_MASK); +} + +/** + * \brief Get Error Flag + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE uint32_t FCIIC_Slave_HWA_GetErrorFlag(FCIIC_Type *pFciic) +{ + return pFciic->SSR & (FCIIC_SSR_TREF_MASK | FCIIC_SSR_BEF_MASK); +} + +/** + * \brief Clear Error Flag + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_ClrErrorFlag(FCIIC_Type *pFciic) +{ + pFciic->SSR |= (FCIIC_SSR_TREF_MASK | FCIIC_SSR_BEF_MASK); +} + +/** + * \brief Enable Transmit Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_EnableTransmitInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER |= FCIIC_SIER_TDIE_MASK; +} + +/** + * \brief FCIIC Disable Transmit Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_DisableTransmitInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER &= ~FCIIC_SIER_TDIE_MASK; /* Receive Interrupt Enable */ +} + + +/** + * \brief Set FCIIC MCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMcr(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCR = u32Value; +} + +/** + * \brief Attach FCIIC MCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_AttachMcr(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCR |= u32Value; +} + + +/** + * \brief Set FCIIC MDER register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMder(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MDER = u32Value; +} + +/** + * \brief Set FCIIC MCFGR0 register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCFGR0(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCFGR0 = u32Value; +} + +/** + * \brief Set FCIIC MCFGR1 register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCFGR1(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCFGR1 = u32Value; +} + +/** + * \brief Set FCIIC MCFGR2 register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCFGR2(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCFGR2 = u32Value; +} + +/** + * \brief Set FCIIC MCFGR3 register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCFGR3(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCFGR3 = u32Value; +} + +/** + * \brief Set FCIIC MFCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMFCR(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MFCR = u32Value; +} + +/** + * \brief Set FCIIC MCCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCCR(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCCR = u32Value; +} + +/** + * \brief Set FCIIC SDER register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSDER(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SDER = u32Value; +} + + + +/** + * \brief Set FCIIC SCFGR1 register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSCFGR1(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SCFGR1 = u32Value; +} + +/** + * \brief Set FCIIC MCCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSCFGR2(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SCFGR2 = u32Value; +} + +/** + * \brief Set FCIIC MCCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSAMR(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SAMR = u32Value; +} + +/** + * \brief Set FCIIC MCCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSCR(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SCR = u32Value; +} + + + +/** @}*/ + +#endif /* end for #ifndef _HWA_FCIIC_H_ */ diff --git a/Inc/HwA_fcpit.h b/Inc/HwA_fcpit.h new file mode 100644 index 0000000..6991ab2 --- /dev/null +++ b/Inc/HwA_fcpit.h @@ -0,0 +1,412 @@ +/** + * @file HwA_fcpit.h + * @author Flagchip + * @brief FC7xxx FCPIT hardware access layer + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip076 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_FCPIT_H_ +#define _HWA_FCPIT_H_ + +#include "device_header.h" +/********* Local typedef ************/ +/** @brief Fcpit counter mode, the default mode is 32bit periodic count mode */ +typedef enum +{ + FCPIT_32PERIODIC_COUNTER = 0, + FCPIT_DUAL_16PERIODIC_COUNTER, + FCPIT_ACCUMULATOR, + FCPIT_32InputCaptue, +} FCPIT_TimerModeType; + +/** @brief Fcpit channel number */ +typedef enum +{ + FCPIT_CHANNEL_0 = 0U, + FCPIT_CHANNEL_1, + FCPIT_CHANNEL_2, + FCPIT_CHANNEL_3 +} FCPIT_ChannelType; +/********* Local inline function ************/ +/** + * @brief Set FCPIT channel value + * + * @param eChannel FCPIT channel number + * @param u32RegValue Timer value + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelValue(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint32_t u32RegValue) +{ + pFcpit->CONTROLS[eChannel].TVAL = u32RegValue; +} + + +/** + * @brief read FCPIT channel value + * + * @param eChannel FCPIT channel number + * @return Timer value + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadChannelValue(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + return (uint32_t)(pFcpit->CONTROLS[eChannel].TVAL ); +} + +/** + * @brief Configure FCPIT channel + * + * @param eChannel FCPIT channel number + * @param u32RegValue TCTRL register value + */ +LOCAL_INLINE void FCPIT_HWA_ConfigChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint32_t u32RegValue) +{ + pFcpit->CONTROLS[eChannel].TCTRL = u32RegValue; +} + +/** + * @brief Configure FCPIT module + * + * @param u32RegValue MCR register value + */ +LOCAL_INLINE void FCPIT_HWA_ConfigModule(FCPIT_Type *pFcpit, uint32_t u32RegValue) +{ + pFcpit->MCR = u32RegValue; +} + + +/** + * @brief Read FCPIT module enable + * + * @return MCR register with FCPIT_MCR_M_CEN_MASK + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadModuleEnable(FCPIT_Type *pFcpit) +{ + return (uint32_t)(pFcpit->MCR & FCPIT_MCR_M_CEN_MASK); +} + +/** + * @brief Read FCPIT channel + * + * @param eChannel Channel number + * @return TCTRL register with FCPIT_TCTRL_T_EN_MASK + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadChannelEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + return (uint32_t)(pFcpit->CONTROLS[eChannel].TCTRL & FCPIT_TCTRL_T_EN_MASK); +} + +/** + * @brief Read FCPIT active interrupt flag + * + * @return FCPIT active interrupt flag + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadInterruptFlag(FCPIT_Type *pFcpit) +{ + return (pFcpit->MSR); +} + +/** + * @brief Read FCPIT enable interrupt flag + * + * @return FCPIT enable interrupt flag + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadEnableInterruptFlag(FCPIT_Type *pFcpit) +{ + return (pFcpit->MIER); +} + +/** + * @brief Set FCPIT channel running on debug mode + * + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelRunOnDebug(FCPIT_Type *pFcpit) +{ + pFcpit->MCR |= FCPIT_MCR_DBG_EN_MASK; +} + +/** + * @brief Set FCPIT channel running on low power mode + * + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelRunOnLpm(FCPIT_Type *pFcpit) +{ + pFcpit->MCR |= FCPIT_MCR_LPM_EN_MASK; +} + +/** + * @brief Enable FCPIT module + * + */ +LOCAL_INLINE void FCPIT_HWA_EnableModule(FCPIT_Type *pFcpit) +{ + pFcpit->MCR |= FCPIT_MCR_M_CEN_MASK; +} + +/** + * @brief Enable FCPIT channel(n) interrupt + * + * @param u32RegValue u32RegValue 0-3 bit indicate TIE0-TIE3 + */ +LOCAL_INLINE void FCPIT_HWA_EnableChannelsInterrupt(FCPIT_Type *pFcpit, uint32_t u32RegValue) +{ + pFcpit->MIER |= u32RegValue; +} + +/** + * @brief Enable FCPIT channel + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_EnableChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_T_EN_MASK; +} + +/** + * @brief Enable FCPIT channel + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetTimerEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->SETTEN |= (FCPIT_SETTEN_SET_T_EN_0_MASK << (uint32_t)eChannel); +} + + +/** + * @brief Disable FCPIT channel + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearTimerEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CLRTEN |= (FCPIT_CLRTEN_CLR_T_EN_0_MASK << (uint32_t)eChannel); +} + +/** + * @brief Enable FCPIT channel(n) chain mode + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_EnableChannelChainMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_CHAIN_MASK; +} + +/** + * @brief Configure FCPIT channel operation mode + * + * @param eChannel FCPIT channel number + * @param eMode FCPIT operation mode + */ +LOCAL_INLINE void FCPIT_HWA_ConfigChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, FCPIT_TimerModeType eMode) +{ + uint32_t u32RegValue = pFcpit->CONTROLS[eChannel].TCTRL; + pFcpit->CONTROLS[eChannel].TCTRL = (u32RegValue & ~(uint32_t)FCPIT_TCTRL_MODE_MASK) | FCPIT_TCTRL_MODE(eMode); +} + +/** + * @brief Set FCPIT channel start on trigger + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelStartOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TSOT_MASK; +} + +/** + * @brief Set FCPIT channel stop on interrupt + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnInterrupt(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TSOI_MASK; +} + +/** + * @brief Set FCPIT channel reload on trigger + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelReloadOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TROT_MASK; +} + +/** + * @brief Set FCPIT channel trigger source + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelTriggerSrc(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TRG_SRC_MASK; +} + +/** + * @brief Select FCPIT channel trigger + * + * @param eChannel FCPIT channel number + * @param u8SelChannel Select channel, range is 0-3 + */ +LOCAL_INLINE void FCPIT_HWA_SelectChannelTrigger(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint8_t u8SelChannel) +{ + uint32_t u32RegValue = pFcpit->CONTROLS[eChannel].TCTRL; + pFcpit->CONTROLS[eChannel].TCTRL = (u32RegValue & ~(uint32_t)FCPIT_TCTRL_TRG_SEL_MASK) | + FCPIT_TCTRL_TRG_SEL(u8SelChannel); +} + +/** + * @brief Set FCPIT channel stop on debug mode + * + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnDebug(FCPIT_Type *pFcpit) +{ + pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_DBG_EN_MASK; +} + +/** + * @brief Set FCPIT channel stop on low power mode + * + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnLpm(FCPIT_Type *pFcpit) +{ + pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_LPM_EN_MASK; +} + +/** + * @brief Disable FCPIT module + * + */ +LOCAL_INLINE void FCPIT_HWA_DisableModule(FCPIT_Type *pFcpit) +{ + pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_M_CEN_MASK; +} + +/** + * @brief Clear FCPIT channel(n) interrupt flag + * + * @param u32RegValue 0-3 bit indicate TIF0-TIF3 + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT_Type *pFcpit, uint32_t u32RegValue) +{ + pFcpit->MSR |= u32RegValue; +} + +/** + * @brief Disable FCPIT channel(n) interrupt + * + * @param u32RegValue u32RegValue 0-3 bit indicate TIE0-TIE3 + */ +LOCAL_INLINE void FCPIT_HWA_DisableChannelsInterrupt(FCPIT_Type *pFcpit, uint32_t u32RegValue) +{ + pFcpit->MIER &= ~u32RegValue; +} + +/** + * @brief Disable FCPIT channel + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_DisableChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_T_EN_MASK; +} + +/** + * @brief Disable FCPIT channel chain mode + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_DisableChannelChainMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_CHAIN_MASK; +} + +/** + * @brief Clear FCPIT channel operation mode + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_MODE_MASK; +} + +/** + * @brief read FCPIT channel operation mode + * + * @param eChannel FCPIT channel number + */ + +LOCAL_INLINE uint32 FCPIT_HWA_ReadChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + return (uint32) ((pFcpit->CONTROLS[eChannel].TCTRL & (uint32_t)FCPIT_TCTRL_MODE_MASK) >>FCPIT_TCTRL_MODE_SHIFT); +} + + +/** + * @brief Clear FCPIT channel start on trigger + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelStartOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TSOT_MASK; +} + +/** + * @brief Clear FCPIT channel stop on interrupt + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelStopOnInterrupt(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TSOI_MASK; +} + +/** + * @brief Clear FCPIT channel reload on trigger + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelReloadOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TROT_MASK; +} + +/** + * @brief Clear FCPIT channel trigger source + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelTriggerSrc(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TRG_SRC_MASK; +} + +/** + * @brief Clear FCPIT channel trigger select + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelTriggerSelect(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TRG_SEL_MASK; +} + + +#endif /* #ifndef _HWA_FCPIT_H_ */ diff --git a/Inc/HwA_fcsmu.h b/Inc/HwA_fcsmu.h new file mode 100644 index 0000000..68d99a3 --- /dev/null +++ b/Inc/HwA_fcsmu.h @@ -0,0 +1,671 @@ +/** + * @file HwA_fcsmu.h + * @author Flagchip + * @brief FC7xxx FCSMU hardware access layer + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _HWA_FCSMU_H_ +#define _HWA_FCSMU_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_fcsmu + * @{ + * + */ +/********* macros ************/ +typedef enum +{ + FCSMU_OPC_NONE = 0U, /*!< FCSMU operation code none */ + FCSMU_OPC_MOVE_TO_CONFIG = 1U, /*!< FCSMU operation code move to configuration state */ + FCSMU_OPC_MOVE_TO_NORMAL = 2U, /*!< FCSMU operation code move to normal state */ + FCSMU_OPC_CLEAR_FAULT_IMFO = 13U, /*!< FCSMU operation code clear fault channel information register */ + FCSMU_OPC_CLEAR_OPS_TO_IDLE = 15U, /*!< FCSMU operation code clear ops to idle */ + FCSMU_OPC_LOAD_NVR_CONFIG = 31U /*!< FCSMU operation code load configuration from nvr */ +} FCSMU_OperationCodeType; + +typedef enum +{ + FCSMU_Crc_STATE_IDLE = 0U, /*!< FCSMU crc status idle */ + FCSMU_Crc_STATE_BUSY = 1U /*!< FCSMU crc status busy */ +} FCSMU_CrcStatusType; +/********* Local typedef ************/ + +/********* Local inline function ************/ + +/********* FCSMU Register interface ************/ + +/** + * @brief Set the fcsmu CTRL register + * + * @param pFcsmu FCSMU Instance + * @param u32Value The register value + */ +LOCAL_INLINE void FCSMU_HWA_SetCrtl(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->CTRL = u32Value; +} + +/** + * @brief Get the fcsmu CTRL register + * + * @param pFcsmu FCSMU Instance + * @return CTRL register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCtrl(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->CTRL; +} + +/** + * @brief Get the fcsmu CTRL register OPS + * + * @param pFcsmu FCSMU Instance + * @return CTRL register OPS value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCtrlOps(FCSMU_Type *const pFcsmu) +{ + return ((pFcsmu->CTRL & FCSMU_CTRL_OPS_MASK) >> FCSMU_CTRL_OPS_SHIFT); +} + +/** + * @brief Set the fcsmu OPRK register + * + * @param pFcsmu FCSMU Instance + * @param u32Value The register value + */ +LOCAL_INLINE void FCSMU_HWA_SetOprk(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->OPRK = u32Value; +} + + +/** + * @brief Set the fcsmu SOCTRL register + * + * @param pFcsmu FCSMU Instance + * @param u32Value The register value + */ +LOCAL_INLINE void FCSMU_HWA_SetSoctrl(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->SOCTRL = u32Value; +} + +/** + * @brief Get the fcsmu SOCTRL register + * + * @param pFcsmu FCSMU Instance + * @return SOCTRL register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetSoctrl(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->SOCTRL; +} + +/** + * @brief Set the fcsmu FCCR0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FCCR0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFccr0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FCCR0 = u32Value; +} + +/** + * @brief Get the fcsmu FCCR0 register + * + * @param pFcsmu FCSMU Instance + * @return FCCR0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFccr0(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FCCR0; +} + +/** + * @brief Set the fcsmu FRST0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FRST0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFRST0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FRST0 = u32Value; +} + +/** + * @brief Get the fcsmu FRST0 register + * + * @param pFcsmu FCSMU Instance + * @return FRST0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFRST0(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FRST0; +} + +/** + * @brief Set the fcsmu FST0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FST0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFst0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FST0 = u32Value; +} + +/** + * @brief Get the fcsmu FST0 register + * + * @param pFcsmu FCSMU Instance + * @return FST0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFst0(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FST0; +} + +/** + * @brief Set the fcsmu FST_UNLK register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FST_UNLK register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFunlk(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FST_UNLK = u32Value; +} + +/** + * @brief Set the fcsmu FE0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FE0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFe0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FE0 = u32Value; +} + +/** + * @brief Get the fcsmu FE0 register + * + * @param pFcsmu FCSMU Instance + * @return FE0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFE0(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FE0; +} + +/** + * @brief Set the fcsmu WARNING_EN0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value WARNING_EN0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetWarningEn0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->WARNING_EN0 = u32Value; +} + +/** + * @brief Get the fcsmu WARNING_EN0 register + * + * @param pFcsmu FCSMU Instance + * @return WARNING_EN0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetWarningEn0(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->WARNING_EN0; +} + +/** + * @brief Set the fcsmu WARNING_TO register + * + * @param pFcsmu FCSMU Instance + * @param u32Value WARNING_TO register value + */ +LOCAL_INLINE void FCSMU_HWA_SetWaringTo(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->WARNING_TO = u32Value; +} + +/** + * @brief Get the fcsmu WARNING_TO register + * + * @param pFcsmu FCSMU Instance + * @return WARNING_TO register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetWaringTo(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->WARNING_TO; +} + +/** + * @brief Set the fcsmu CFG_TO register + * + * @param pFcsmu FCSMU Instance + * @param u32Value CFG_TO register value + */ +LOCAL_INLINE void FCSMU_HWA_SetCfgTo(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->CFG_TO = u32Value; +} + +/** + * @brief Get the fcsmu CFG_TO register + * + * @param pFcsmu FCSMU Instance + * @return CFG_TO register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCfgTo(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->CFG_TO; +} + +/** + * @brief Set the fcsmu SOUT_DIAG register + * + * @param pFcsmu FCSMU Instance + * @param u32Value SOUT_DIAG register value + */ +LOCAL_INLINE void FCSMU_HWA_SetSoutDiag(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->SOUT_DIAG = u32Value; +} + +/** + * @brief Get the fcsmu SOUT_DIAG register + * + * @param pFcsmu FCSMU Instance + * @return SOUT_DIAG register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetSoutDiag(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->SOUT_DIAG; +} + +/** + * @brief Get the fcsmu STATUS register + * + * @param pFcsmu FCSMU Instance + * @return STATUS register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetStatus(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->STATUS; +} + +/** + * @brief Get the fcsmu STATUS register FIF value + * + * @param pFcsmu FCSMU Instance + * @return STATUS register FIF value + */ +LOCAL_INLINE bool FCSMU_HWA_GetFaultState(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->STATUS & FCSMU_STATUS_FIF_MASK) == FCSMU_STATUS_FIF_MASK ? true : false; +} + +/** + * @brief Get the fcsmu STATUS register STAT value + * + * @param pFcsmu FCSMU Instance + * @return STATUS register STAT value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetState(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->STATUS & FCSMU_STATUS_STAT_MASK) >> FCSMU_STATUS_STAT_SHIFT; +} + +/** + * @brief Get the fcsmu NTW register + * + * @param pFcsmu FCSMU Instance + * @return NTW register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetNtw(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->NTW; +} + +/** + * @brief Get the fcsmu WTF register + * + * @param pFcsmu FCSMU Instance + * @return WTF register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetWtf(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->WTF; +} + +/** + * @brief Get the fcsmu NTF register + * + * @param pFcsmu FCSMU Instance + * @return NTF register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetNtf(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->NTF; +} + +/** + * @brief Get the fcsmu FTW register + * + * @param pFcsmu FCSMU Instance + * @return FTW register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFtw(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FTW; +} + +/** + * @brief Set the fcsmu INJECT register + * + * @param pFcsmu FCSMU Instance + * @param u32Value INJECT register value + */ +LOCAL_INLINE void FCSMU_HWA_SetInject(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->INJECT = u32Value; +} + +/** + * @brief Get the fcsmu IRQ_STAT register + * + * @param pFcsmu FCSMU Instance + * @return IRQ_STAT register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetIrqStat(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->IRQ_STAT; +} + +/** + * @brief Set the fcsmu IRQ_STAT register + * + * @param pFcsmu FCSMU Instance + * @param u32Value IRQ_STAT register value + */ +LOCAL_INLINE void FCSMU_HWA_ClearCfgToIrq(FCSMU_Type *const pFcsmu) +{ + pFcsmu->IRQ_STAT |= FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK; +} + + +/** + * @brief Set the fcsmu IRQ_EN register + * + * @param pFcsmu FCSMU Instance + * @param bEnable IRQ_EN register value + */ +LOCAL_INLINE void FCSMU_HWA_EnableCfgToIrq(FCSMU_Type *const pFcsmu, bool bEnable) +{ + pFcsmu->IRQ_EN = (pFcsmu->IRQ_EN & ~FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK) | FCSMU_IRQ_EN_CFG_TO_IEN(bEnable); +} + +/** + * @brief Set the fcsmu TEMP_UNLK register + * + * @param pFcsmu FCSMU Instance + * @param u32Value TEMP_UNLK register value + */ +LOCAL_INLINE void FCSMU_HWA_SetTempUnlk(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->TEMP_UNLK = u32Value; +} + +/** + * @brief Set the fcsmu PERMNT_LOCK register + * + * @param pFcsmu FCSMU Instance + * @param u32Value PERMNT_LOCK register value + */ +LOCAL_INLINE void FCSMU_HWA_SetPermntLock(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->PERMNT_LOCK = u32Value; +} + +/** + * @brief Set the fcsmu STMR register + * + * @param pFcsmu FCSMU Instance + * @param u32Value STMR register value + */ +LOCAL_INLINE void FCSMU_HWA_SetStmr(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->STMR = u32Value; +} + + +/** + * @brief Set the fcsmu WARNING_IEN0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value WARNING_IEN0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetWarningIen(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->WARNING_IEN0 = u32Value; +} + +/** + * @brief Set the fcsmu FAULT_IEN0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FAULT_IEN0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFaultIen(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FAULT_IEN0 = u32Value; +} + +/** + * @brief Set the fcsmu SOUT_EN0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value SOUT_EN0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetSoutEn(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->SOUT_EN0 = u32Value; +} + +/** + * @brief Get the fcsmu WARNING_TMR register + * + * @param pFcsmu FCSMU Instance + * @return WARNING_TMR register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetWarningTmr(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->WARNING_TMR; +} + +/** + * @brief Get the fcsmu SM_TMR register + * + * @param pFcsmu FCSMU Instance + * @return SM_TMR register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetSafeModeTmr(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->SM_TMR; +} + +/** + * @brief Get the fcsmu CFG_TMR register + * + * @param pFcsmu FCSMU Instance + * @return CFG_TMR register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetConfigTmr(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->CFG_TMR; +} + +/** + * @brief Get the fcsmu SOUT_TMR register + * + * @param pFcsmu FCSMU Instance + * @return SOUT_TMR register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetSoutTmr(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->SOUT_TMR; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + * @param u32Value CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_SetCrcCtrl(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->CRC_CTRL = u32Value; +} + +/** + * @brief Get the fcsmu CRC_CTRL register BUSY value + * + * @param pFcsmu FCSMU Instance + * @return BUSY value + */ +LOCAL_INLINE bool FCSMU_HWA_GetCrcBusy(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_BUSY_MASK) == FCSMU_CRC_CTRL_BUSY_MASK ? true : false; +} + +/** + * @brief Get the fcsmu CRC_CTRL register EF value + * + * @param pFcsmu FCSMU Instance + * @return EF value + */ +LOCAL_INLINE bool FCSMU_HWA_GetCrcErrorFlag(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_EF_MASK) == FCSMU_CRC_CTRL_EF_MASK ? true : false; +} + +/** + * @brief Clear the fcsmu CRC_CTRL register EF + * + * @param pFcsmu FCSMU Instance + * @param u32Value CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_ClearCrcErrorFlag(FCSMU_Type *const pFcsmu) +{ + pFcsmu->CRC_CTRL |= FCSMU_CRC_CTRL_EF_MASK; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + * @param u32Value CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_EnableErrorOutput(FCSMU_Type *const pFcsmu, bool bEnable) +{ + pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_EOEN_MASK) | FCSMU_CRC_CTRL_EOEN(bEnable); +} + +/** + * @brief Get the fcsmu CRC_CTRL register EOEN value + * + * @param pFcsmu FCSMU Instance + * @return EOEN value + */ +LOCAL_INLINE bool FCSMU_HWA_GetCrcErrorOutputEnable(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_EOEN_MASK) == FCSMU_CRC_CTRL_EOEN_MASK ? true : false; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + * @param bEnable CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_EnableCrcChecker(FCSMU_Type *const pFcsmu, bool bEnable) +{ + pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_CHKEN_MASK) | FCSMU_CRC_CTRL_CHKEN(bEnable); +} + +/** + * @brief Get the fcsmu CRC_CTRL register CHKEN value + * + * @param pFcsmu FCSMU Instance + * @return CHKEN value + */ +LOCAL_INLINE bool FCSMU_HWA_GetCrcCheckerEnable(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_CHKEN_MASK) == FCSMU_CRC_CTRL_CHKEN_MASK ? true : false; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + * @param bEnable CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_EnableTrigger(FCSMU_Type *const pFcsmu, bool bEnable) +{ + pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_TRGEN_MASK) | FCSMU_CRC_CTRL_TRGEN(bEnable); +} + +/** + * @brief Get the fcsmu CRC_CTRL register TRGEN value + * + * @param pFcsmu FCSMU Instance + * @return TRGEN value + */ +LOCAL_INLINE bool FCSMU_HWA_GetTriggerEnable(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_TRGEN_MASK) == FCSMU_CRC_CTRL_TRGEN_MASK ? true : false; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + */ +LOCAL_INLINE void FCSMU_HWA_GenerateCrc(FCSMU_Type *const pFcsmu) +{ + pFcsmu->CRC_CTRL |= FCSMU_CRC_CTRL_GEN(true); +} + +/** + * @brief Get the fcsmu CRC_RES register + * + * @param pFcsmu FCSMU Instance + * @return CRC_RES register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCrcResult(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->CRC_RES; +} + +/** @}*/ /* HwA_fcsmu */ + +#endif /* #ifndef _HWA_FCSMU_H_ */ diff --git a/Inc/HwA_fcspi.h b/Inc/HwA_fcspi.h new file mode 100644 index 0000000..3c204cc --- /dev/null +++ b/Inc/HwA_fcspi.h @@ -0,0 +1,478 @@ +/** + * @file HwA_fcspi.h + * @author Flagchip + * @brief FC7xxx FCSPI hardware access layer + * @version 0.1.0 + * @date 2024-01-13 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip071 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_FCSPI_H_ +#define _HWA_FCSPI_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_fcspi + * @{ + */ + +/** + * @brief Boolean false value definition for type FCSPI_AtomicBoolType used by FCSPI to ensure read/write atomic + * + */ +#define FCSPI_FALSE ((uint8_t)0) + +/** + * @brief Boolean true value definition for type FCSPI_AtomicBoolType used by FCSPI to ensure read/write atomic + * + */ +#define FCSPI_TRUE ((uint8_t)1) + +/********* Local typedef ************/ +/** + * @brief FCSPI Mode type, master or slave. + */ +typedef enum { + FCSPI_MODE_SLAVE = 0, + FCSPI_MODE_MASTER = 1 +} FCSPI_MasterSlaveModeType; + +/** + * @brief Boolean type for FCSpi + */ +typedef uint8_t FCSPI_AtomicBoolType; + +/********* Local inline function ************/ + +/** + * @brief Read the FCSPI CTRL register value for all. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI CTRL regsiter value. + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetCtrlValue(FCSPI_Type *pFCSPI) +{ + return pFCSPI->CTRL; +} + +/** + * @brief Set FCSPI CTRL value, users should write the whole value to this register. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value which will be written to the CTRL register. + */ +LOCAL_INLINE void FCSPI_HWA_SetCtrlValue(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->CTRL = u32Value; +} + +/** + * @brief Enable the feature of FCSPI hardware, only for starting the feature of SPI module. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + */ +LOCAL_INLINE void FCSPI_HWA_ModuleEnable(FCSPI_Type *pFCSPI) +{ + pFCSPI->CTRL |= FCSPI_CTRL_M_EN(1); +} + +/** + * @brief Disable the feature of FCSPI, and shutdown the FCSPI module. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + */ +LOCAL_INLINE void FCSPI_HWA_ModuleDisable(FCSPI_Type *pFCSPI) +{ + pFCSPI->CTRL &= (~(FCSPI_CTRL_M_EN_MASK)); +} + +/** + * @brief Getting the FCSPI transfer status by reading the STATUS register. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return the whole status of FCSPI transfer, which can be read in STATUS register. + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetStatus(FCSPI_Type *pFCSPI) +{ + return pFCSPI->STATUS; +} + +/** + * @brief Clear FCSPI STATUS register for certain function. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_ClearStatus(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->STATUS = u32Value; +} + +/** + * @brief Get FCSPI INT_EN register value for checking which interrupt is enabled. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI INT_EN regsiter value will be returned. + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetIntrruptEnableReg(FCSPI_Type *pFCSPI) +{ + return pFCSPI->INT_EN; +} + +/** + * @brief Set the FCSPI INT_EN register value for enable or disable some interrupts. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetInterruptEnableReg(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->INT_EN = u32Value; +} + +/** + * @brief Getting the DMA enabled status through the regsiter FCSPI DMA_EN value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI DMA_EN regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetDMAEnableReg(FCSPI_Type *pFCSPI) +{ + return pFCSPI->DMA_EN; +} + +/** + * @brief Enable or disable the DMA feature by setting the FCSPI DMA_EN register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetDMAEnableReg(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->DMA_EN = u32Value; +} + +/** + * @brief Get FCSPI CFG0 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI CFG0 regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetCFG0Reg(FCSPI_Type *pFCSPI) +{ + return pFCSPI->CFG0; +} + +/** + * @brief Set FCSPI CFG0 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetCFG0Reg(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->CFG0 = u32Value; +} + +/** + * @brief Get FCSPI CFG1 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI CFG1 regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetCFG1Reg(FCSPI_Type *pFCSPI) +{ + return pFCSPI->CFG1; +} + +/** + * @brief Set FCSPI CFG1 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetCFG1Reg(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->CFG1 = u32Value; +} + +/** + * @brief Set the FCSPI to master mode. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + */ +LOCAL_INLINE void FCSPI_HWA_SetMasterMode(FCSPI_Type *pFCSPI) +{ + pFCSPI->CFG1 |= FCSPI_CFG1_MASTER(1); +} + +/** + * @brief Set FCSPI to slave mode. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + */ +LOCAL_INLINE void FCSPI_HWA_SetSlaveMode(FCSPI_Type *pFCSPI) +{ + pFCSPI->CFG1 &= (~(FCSPI_CFG1_MASTER_MASK)); +} + +/** + * @brief Check the current mode status, master or slave. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return the mode type of FCSPI, FCSPI_MODE_MASTER or FCSPI_MODE_SLAVE + */ +LOCAL_INLINE FCSPI_MasterSlaveModeType FCSPI_HWA_CheckMode(FCSPI_Type *pFCSPI) +{ + FCSPI_MasterSlaveModeType eRet = FCSPI_MODE_SLAVE; + + if ((pFCSPI->CFG1 & FCSPI_CFG1_MASTER_MASK) == FCSPI_CFG1_MASTER(1)) + { + eRet = FCSPI_MODE_MASTER; + } + + return eRet; +} + +/** + * @brief Get FCSPI MATCH0 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI MATCH0 regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetMatch0Value(FCSPI_Type *pFCSPI) +{ + return pFCSPI->DATA_MATCH0; +} + +/** + * @brief Set FCSPI MATCH0 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetMatch0Value(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->DATA_MATCH0 = u32Value; +} + +/** + * @brief Get FCSPI MATCH1 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI MATCH1 regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetMatch1Value(FCSPI_Type *pFCSPI) +{ + return pFCSPI->DATA_MATCH1; +} + +/** + * @brief Set FCSPI MATCH1 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetMatch1Value(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->DATA_MATCH1 = u32Value; +} + +/** + * @brief Get FCSPI CLK_CFG register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI CLK_CFG regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetClockConfig(FCSPI_Type *pFCSPI) +{ + return pFCSPI->CLK_CFG; +} + +/** + * @brief Set FCSPI CLK_CFG register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetClockConfig(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->CLK_CFG = u32Value; +} + +/** + * @brief Get FCSPI FIFO_WTM register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI FIFO_WTM regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetFIFOWaterMark(FCSPI_Type *pFCSPI) +{ + return pFCSPI->FIFO_WTM; +} + +/** + * @brief Set FCSPI FIFO_WTM register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u8RxWatermark the rx water mark value. + * @param u8TxWatermark the tx water mark value. + */ +LOCAL_INLINE void FCSPI_HWA_SetWatermark(FCSPI_Type *pFCSPI, uint8_t u8RxWatermark, uint8_t u8TxWatermark) +{ + uint32_t u32Flag = 0U; + + u32Flag |= ((uint32_t)u8RxWatermark << FCSPI_FIFO_WTM_RXWATER_SHIFT); + u32Flag |= ((uint32_t)u8TxWatermark << FCSPI_FIFO_WTM_TXWATER_SHIFT); + + pFCSPI->FIFO_WTM = u32Flag; +} + +/** + * @brief Get FCSPI RX FIFO count. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return the real count value of rx fifo. + */ +LOCAL_INLINE uint8_t FCSPI_HWA_GetRxFifoStoredCount(FCSPI_Type *pFCSPI) +{ + return (uint8_t)(((pFCSPI->FIFO_STATUS) & FCSPI_FIFO_STATUS_RXCNT_MASK) >> FCSPI_FIFO_STATUS_RXCNT_SHIFT); +} + +/** + * @brief Get FCSPI TX FIFO count value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return the real count of tx fifo. + */ +LOCAL_INLINE uint8_t FCSPI_HWA_GetTxFifoStoredCount(FCSPI_Type *pFCSPI) +{ + return (uint8_t)(((pFCSPI->FIFO_STATUS) & FCSPI_FIFO_STATUS_TXCNT_MASK) >> FCSPI_FIFO_STATUS_TXCNT_SHIFT); +} + +/** + * @brief Get FCSPI TR_CTRL register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI TR_CTRL regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetTxRxControl(FCSPI_Type *pFCSPI) +{ + return pFCSPI->TR_CTRL; +} + +/** + * @brief Set FCSPI TR_CTRL register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetTxRxControl(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->TR_CTRL = u32Value; +} + +/** + * @brief Set RX enable status in register FCSPI TR_CTRL. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param eEnable FCSPI_TRUE for enabled, FCSPI_FALSE for disable. + */ +LOCAL_INLINE void FCSPI_HWA_EnableRxDataMask(FCSPI_Type *pFCSPI, FCSPI_AtomicBoolType eEnable) +{ + if (FCSPI_FALSE == eEnable) + { + pFCSPI->TR_CTRL |= FCSPI_TR_CTRL_RX_MSK_MASK; + } + else + { + pFCSPI->TR_CTRL &= (~(FCSPI_TR_CTRL_RX_MSK_MASK)); + } +} + +/** + * @brief Set TX enable status in register FCSPI TR_CTRL. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param eEnable FCSPI_TRUE for enabled, FCSPI_FALSE for disable. + */ +LOCAL_INLINE void FCSPI_HWA_EnableTxDataMask(FCSPI_Type *pFCSPI, FCSPI_AtomicBoolType eEnable) +{ + if (FCSPI_FALSE == eEnable) + { + pFCSPI->TR_CTRL |= FCSPI_TR_CTRL_TX_MSK_MASK; + } + else + { + pFCSPI->TR_CTRL &= (~(FCSPI_TR_CTRL_TX_MSK_MASK)); + } +} + +/** + * @brief Set FCSPI TX_DATA register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_WriteData(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->TX_DATA = u32Value; +} + +/** + * @brief Get the address of FCSPI TX_DATA register,return value is the pointer address of TX_DATA. + * + * @param pFCSPI FCSPI instance，e.g. FCSPI0, FCSPI1. + * @return FCSPI TX_DATA address. + */ +LOCAL_INLINE uint32_t volatile *FCSPI_HWA_GetTxDataAddr(FCSPI_Type *pFCSPI) +{ + return (uint32_t volatile *)&(pFCSPI->TX_DATA); +} + +/** + * @brief Read FCSPI RX_STATUS register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI RX_STATUS regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetRxStatus(FCSPI_Type *pFCSPI) +{ + return pFCSPI->RX_STATUS; +} + +/** + * @brief Read FCSPI RX_DATA register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI RX_DATA regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_ReadData(FCSPI_Type *pFCSPI) +{ + return pFCSPI->RX_DATA; +} + +/** + * @brief Get the address of FCSPI RX_DATA register,return value is the pointer address of RX_DATA. + * + * @param pFCSPI FCSPI instance，e.g. FCSPI0, FCSPI1. + * @return FCSPI RX_DATA address. + */ +LOCAL_INLINE uint32_t volatile const *FCSPI_HWA_GetRxDataAddr(FCSPI_Type *pFCSPI) +{ + return &(pFCSPI->RX_DATA); +} + + +#endif /* #ifndef _HWA_FCPIT_H_ */ diff --git a/Inc/HwA_fcuart.h b/Inc/HwA_fcuart.h new file mode 100644 index 0000000..1cb80a5 --- /dev/null +++ b/Inc/HwA_fcuart.h @@ -0,0 +1,830 @@ +/** + * @file HwA_fcuart.h + * @author Flagchip + * @brief FC7xxx FCUart register API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 Flagchip0122 N/A FC7xxx internal release version + ********************************************************************************/ + +#ifndef _HWA_FCUART_H_ +#define _HWA_FCUART_H_ + +#include "device_header.h" + + +/** + * @addtogroup HwA_fcuart + * @{ + */ + + +/********* Local typedef ************/ + +/** + * @brief UART STAT register flag + * + */ +typedef enum +{ + FCUART_STAT_LBKDIF = (int32_t)FCUART_STAT_LBKDIF_MASK, /**< FCUART_STAT_LBKDIF LIN Break Detect Interrupt Flag, w1c */ + FCUART_STAT_RPAEIF = (int32_t)FCUART_STAT_RPAEIF_MASK, /**< FCUART_STAT_RPAEIF RXD Pin Active Edge Interrupt Flag, w1c */ + FCUART_STAT_MSBF = (int32_t)FCUART_STAT_MSBF_MASK, /**< FCUART_STAT_MSBF MSB First, RW */ + FCUART_STAT_RXINV = (int32_t)FCUART_STAT_RXINV_MASK, /**< FCUART_STAT_RXINV Receive Data Inversion, RW */ + FCUART_STAT_RWUID = (int32_t)FCUART_STAT_RWUID_MASK, /**< FCUART_STAT_RWUID Receive Wake Up Idle Detect, RW */ + FCUART_STAT_BCGL = (int32_t)FCUART_STAT_BCGL_MASK, /**< FCUART_STAT_BCGL Break Character Generation Length, RW */ + FCUART_STAT_LBKDE = (int32_t)FCUART_STAT_LBKDE_MASK, /**< FCUART_STAT_LBKDE LIN Break Detection Enable, RW */ + FCUART_STAT_RAF = (int32_t)FCUART_STAT_RAF_MASK, /**< FCUART_STAT_RAF Receiver Active Flag, RO */ + FCUART_STAT_TDREF = (int32_t)FCUART_STAT_TDREF_MASK, /**< FCUART_STAT_TDREF Transmit Data Register Empty Flag, RO */ + FCUART_STAT_TCF = (int32_t)FCUART_STAT_TCF_MASK, /**< FCUART_STAT_TCF Transmission Complete Flag, RO */ + FCUART_STAT_RDRFF = (int32_t)FCUART_STAT_RDRFF_MASK, /**< FCUART_STAT_RDRFF Receive Data Register Full Flag, RO */ + FCUART_STAT_IDLEF = (int32_t)FCUART_STAT_IDLEF_MASK, /**< FCUART_STAT_IDLEF Idle Line Flag, w1c */ + FCUART_STAT_RORF = (int32_t)FCUART_STAT_RORF_MASK, /**< FCUART_STAT_RORF Receiver Overrun Flag, w1c */ + FCUART_STAT_NF = (int32_t)FCUART_STAT_NF_MASK, /**< FCUART_STAT_NF Noise Flag, w1c */ + FCUART_STAT_FEF = (int32_t)FCUART_STAT_FEF_MASK, /**< FCUART_STAT_FEF Frame Error Flag, w1c */ + FCUART_STAT_PEF = (int32_t)FCUART_STAT_PEF_MASK, /**< FCUART_STAT_PEF Parity Error Flag, w1c */ + FCUART_STAT_M0F = (int32_t)FCUART_STAT_M0F_MASK, /**< FCUART_STAT_M0F Match address 0 Flag, w1c */ + FCUART_STAT_M1F = (int32_t)FCUART_STAT_M1F_MASK, /**< FCUART_STAT_M1F Match address 1 Flag, w1c */ + FCUART_STAT_RPEF = (int32_t)FCUART_STAT_RPEF_MASK, /**< FCUART_STAT_RPEF Receive Data Parity Error Flag, w1c */ + FCUART_STAT_TPEF = (int32_t)FCUART_STAT_TPEF_MASK /**< FCUART_STAT_TPEF Transmit Data Parity Error Flag, w1c */ +} FCUART_StatType; + +/** + * @brief UART data bit length mode + * + */ +typedef enum +{ + UART_BITMODE_8 = 0, /**< UART_BITMODE_8 */ + UART_BITMODE_9 /**< UART_BITMODE_9 */ +} FCUART_BitModeType; + +/** + * @brief UART stop bits number + * + */ +typedef enum +{ + UART_STOPBIT_NUM_1 = 0, /**< UART_STOPBIT_NUM_1 */ + UART_STOPBIT_NUM_2 /**< UART_STOPBIT_NUM_2 */ +} FCUART_StopBitNumType; + +/** + * @brief UART parity check type + * + */ +typedef enum +{ + UART_PARITY_EVEN = 0, /**< UART_PARITY_EVEN */ + UART_PARITY_ODD /**< UART_PARITY_ODD */ +} FCUART_ParityType; + + + + +/********* Local inline function ************/ +/** + * @brief Get Stat Flag + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_SetSoftWareReset(FCUART_Type *pUart) +{ + pUart->RST |= FCUART_RST_RST_MASK; + pUart->RST &= ~FCUART_RST_RST_MASK; +} + +/** + * @brief Get Stat Flag + * + * @param pUart UART instance value + * @param eStatusType stat type + * @return FCUART STAT status flag + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetStatus(FCUART_Type *pUart, FCUART_StatType eStatusType) +{ + return (pUart->STAT & (uint32_t)eStatusType); +} + +/** + * @brief Clear Stat Flag + * + * @param pUart UART instance value + * @param u32StatusType stat type + */ +LOCAL_INLINE void FCUART_HWA_ClearStatus(FCUART_Type *pUart, uint32_t u32StatusType) +{ + pUart->STAT |= u32StatusType; +} + +/** + * @brief Enable Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableInterrupt(FCUART_Type *pUart, uint32 u32Value) +{ + pUart->CTRL |= u32Value; /* Interrupt Enable */ +} + +/** + * @brief Disable Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableInterrupt(FCUART_Type *pUart, uint32 u32Value) +{ + pUart->CTRL &= ~u32Value; /* Interrupt Disable */ +} + +/** + * @brief Enable Receive Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableReceiveInterrupt(FCUART_Type *pUart) +{ + pUart->CTRL |= FCUART_CTRL_RIE_MASK; /* Receive Interrupt Enable */ +} + +/** + * @brief Disable Receive Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableReceiveInterrupt(FCUART_Type *pUart) +{ + pUart->CTRL &= ~FCUART_CTRL_RIE_MASK; /* Receive Interrupt Enable */ + +} + +/** + * @brief Enable Error Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableErrorInterrupt(FCUART_Type *pUart) +{ + pUart->CTRL |= FCUART_CTRL_ORIE_MASK | /* Overrun Interrupt Enable */ + FCUART_CTRL_NEIE_MASK | /* Noise Error Interrupt Enable */ + FCUART_CTRL_FEIE_MASK | /* Frame Error Interrupt Enable */ + FCUART_CTRL_PEIE_MASK; /* Parity Error Interrupt Enable */ +} + +/** + * @brief Disable Error Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableErrorInterrupt(FCUART_Type *pUart) +{ + pUart->CTRL &= ~(FCUART_CTRL_ORIE_MASK | /* Overrun Interrupt Enable */ + FCUART_CTRL_NEIE_MASK | /* Noise Error Interrupt Enable */ + FCUART_CTRL_FEIE_MASK | /* Frame Error Interrupt Enable */ + FCUART_CTRL_PEIE_MASK); /* Parity Error Interrupt Enable */ + +} + +/** + * @brief Set FCUART Ctrl register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetCtrl(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->CTRL = u32Value; +} + +/** + * @brief Get FCUART Ctrl register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetCtrl(FCUART_Type *pUart) +{ + return pUart->CTRL; +} + +/** + * @brief Attach FCUART Ctrl register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachCtrl(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->CTRL |= u32Value; +} + +/** + * @brief Set FCUART Baud register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetBaud(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->BAUD = u32Value; +} + +/** + * @brief Get FCUART baud register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetBaud(FCUART_Type *pUart) +{ + return pUart->BAUD; +} + +/** + * @brief Attach FCUART Baud register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachBaud(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->BAUD |= u32Value; +} + +/** + * @brief Set FCUART Fifo register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetFifo(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->FIFO = u32Value; +} + +/** + * @brief Get FCUART fifo register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetFifo(FCUART_Type *pUart) +{ + return pUart->FIFO; +} + +/** + * @brief Get FCUART fifo register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE bool FCUART_HWA_GetEnStatusRxFifo(FCUART_Type *pUart) +{ + return ((((pUart->FIFO & FCUART_FIFO_RXFEN_MASK) >> FCUART_FIFO_RXFEN_SHIFT) == 1U) ? true: false); +} + +/** + * @brief Get FCUART fifo register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE bool FCUART_HWA_GetEnStatusTxFifo(FCUART_Type *pUart) +{ + return ((((pUart->FIFO & FCUART_FIFO_TXFEN_MASK) >> FCUART_FIFO_TXFEN_SHIFT) == 1U) ? true: false); +} + +/** + * @brief Attach FCUART Fifo register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachFifo(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->FIFO |= u32Value; +} + +/** + * @brief Set FCUART WaterMark register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetWaterMark(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->WATERMARK = u32Value; +} + +/** + * @brief Get FCUART Rx WaterMark + * + * @param pUart UART instance value + * @return Rxcount value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetRxWaterMark(FCUART_Type *pUart) +{ + return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_RXWATER_MASK) >> FCUART_WATERMARK_RXWATER_SHIFT)); +} + +/** + * @brief Get FCUART Tx WaterMark + * + * @param pUart UART instance value + * @return Rxcount value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetTxWaterMark(FCUART_Type *pUart) +{ + return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_TXWATER_MASK) >> FCUART_WATERMARK_TXWATER_SHIFT)); +} + +/** + * @brief Get FCUART WaterMark Rxcount + * + * @param pUart UART instance value + * @return Rxcount value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetFifoRxCount(FCUART_Type *pUart) +{ + return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_RXCOUNT_MASK) >> FCUART_WATERMARK_RXCOUNT_SHIFT)); +} + +/** + * @brief Get FCUART WaterMark Txcount + * + * @param pUart UART instance value + * @return Rxcount value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetFifoTxCount(FCUART_Type *pUart) +{ + return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_TXCOUNT_MASK) >> FCUART_WATERMARK_TXCOUNT_SHIFT)); +} + +/** + * @brief Attach FCUART WaterMark register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachWaterMark(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->WATERMARK |= u32Value; +} + +/** + * @brief Set FCUART Match register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetMatch(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->MATCH = u32Value; +} + +/** + * @brief Attach FCUART Match register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachMatch(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->MATCH |= u32Value; +} + +/** + * @brief Get FCUART Match register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetMatch(FCUART_Type *pUart) +{ + return pUart->MATCH; +} + +/** + * @brief Read FCUART STAT register + * + * @param pUart UART instance value + * @return STAT read value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetSTAT(FCUART_Type *pUart) +{ + return pUart->STAT; +} + +/** + * @brief Write 1 Clear FCUART STAT register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_WriteClearSTAT(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->STAT |= u32Value; +} + +/** + * @brief Set Bit Mode and Parity + * + * @param pUart UART instance value + * @param eBitMode is bit mode, 8 or 9 bits + */ +LOCAL_INLINE void FCUART_HWA_SetBitMode(FCUART_Type *pUart, FCUART_BitModeType eBitMode) +{ + uint32_t u32RegVal = pUart->CTRL; + pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_BMSEL_MASK)) | FCUART_CTRL_BMSEL(eBitMode)); +} + +/** + * @brief Set Bit Mode and Parity + * + * @param pUart UART instance value + * @param bParityEnable If enable Parity, set 1U, or set 0U + * @param eParityType Parity type, odd-even + */ +LOCAL_INLINE void FCUART_HWA_SetParity(FCUART_Type *pUart, FCUART_ParityType eParityType, bool bParityEnable) +{ + uint32_t u32RegVal = pUart->CTRL; + pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_PE_MASK | FCUART_CTRL_PT_MASK)) | + FCUART_CTRL_PE(bParityEnable) | + FCUART_CTRL_PT(eParityType) ); +} + +/** + * @brief Set Bit Mode and Parity + * + * @param pUart UART instance value + * @param eStopBit stop bits number 1 or 2 bits + */ +LOCAL_INLINE void FCUART_HWA_SetStopBit(FCUART_Type *pUart, FCUART_StopBitNumType eStopBit) +{ + uint32_t u32RegVal = pUart->BAUD; + pUart->BAUD = ((u32RegVal & (~ FCUART_BAUD_SBNS_MASK)) | FCUART_BAUD_SBNS(eStopBit)); +} + +/** + * @brief Enable Receive DMA + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableReceiveDMA(FCUART_Type *pUart) +{ + pUart->BAUD |= FCUART_BAUD_RDMAEN_MASK; +} + +/** + * @brief Disable Receive DMA + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableReceiveDMA(FCUART_Type *pUart) +{ + pUart->BAUD &= ~FCUART_BAUD_RDMAEN_MASK; + +} + +/** + * @brief Enable Receive FIFO + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableReceiveFIFO(FCUART_Type *pUart) +{ + pUart->FIFO |= FCUART_FIFO_RXFEN_MASK; +} + +/** + * @brief Disable Receive FIFO + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableReceiveFIFO(FCUART_Type *pUart) +{ + pUart->FIFO &= ~FCUART_FIFO_RXFEN_MASK; + +} + +/** + * @brief Clear Fifo Overflow/Underflow flag + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_ClearFIFOErrorFlag(FCUART_Type *pUart) +{ + pUart->FIFO |= FCUART_FIFO_TXOF_MASK | FCUART_FIFO_RXUF_MASK; +} + + +/** + * @brief Set Data Value + * + * @param pUart UART instance value + * @param u32Data Set data + */ +LOCAL_INLINE void FCUART_HWA_SetData(FCUART_Type *pUart, uint32_t u32Data) +{ + pUart->DATA = u32Data; /* data 32 bit */ +} + +/** + * @brief Get Data Value + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetData(FCUART_Type *pUart) +{ + uint8_t u8Data; + + u8Data = *((volatile uint8_t *)&pUart->DATA); /* data 32 bit */ + + return u8Data; +} + +/** + * @brief Set R8T9 bit + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE void FCUART_HWA_SetR8T9(FCUART_Type *pUart, uint8_t u8Data) +{ + uint32_t u32RegVal = pUart->CTRL; + pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_R8T9_MASK)) | FCUART_CTRL_R8T9(u8Data)); +} + +/** + * @brief Get R8T9 bit + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetR8T9(FCUART_Type *pUart) +{ + return (uint8_t)((pUart->CTRL & FCUART_CTRL_R8T9_MASK) >> FCUART_CTRL_R8T9_SHIFT); +} + +/** + * @brief Set R9T8 bit + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE void FCUART_HWA_SetR9T8(FCUART_Type *pUart, uint8_t u8Data) +{ + uint32_t u32RegVal = pUart->CTRL; + pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_R9T8_MASK)) | FCUART_CTRL_R9T8(u8Data)); +} + +/** + * @brief Get R9T8 bit + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetR9T8(FCUART_Type *pUart) +{ + return (uint8_t)((pUart->CTRL & FCUART_CTRL_R9T8_MASK) >> FCUART_CTRL_R9T8_SHIFT); +} + +/** + * @brief Reset the instance by software. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_SoftwareReset(FCUART_Type *pUart) +{ + pUart->RST |= FCUART_RST_RST_MASK; + pUart->RST &= ~FCUART_RST_RST_MASK; +} + +/** + * @brief Set fcuart TX Transfer enable or disable. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetTxTransfer(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->CTRL |= FCUART_CTRL_TE_MASK; + } + else + { + pUart->CTRL &= ~FCUART_CTRL_TE_MASK; + } +} + +/** + * @brief Set fcuart RX Transfer enable or disable. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetRxTransfer(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->CTRL |= FCUART_CTRL_RE_MASK; + } + else + { + pUart->CTRL &= ~FCUART_CTRL_RE_MASK; + } +} + +/** + * @brief Set lin break detect interrupt. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetLinBreakDetectInterrupt(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->BAUD |= FCUART_BAUD_LBKDIE_MASK; + } + else + { + pUart->BAUD &= ~FCUART_BAUD_LBKDIE_MASK; + } +} + +/** + * @brief Set lin break detect feature enable. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetLinBreakDetectEnable(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->STAT |= (FCUART_STAT_LBKDE_MASK | FCUART_STAT_BCGL_MASK); + } + else + { + pUart->STAT &= ~(FCUART_STAT_LBKDE_MASK | FCUART_STAT_BCGL_MASK); + } +} + +/** + * @brief Send a lin break field. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_SendBreakField(FCUART_Type *pUart) +{ + pUart->DATA |= FCUART_DATA_FETSC_MASK; +} + +/** + * @brief Set uart receive active interrupt. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetReceiveActiveInterrupt(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->BAUD |= FCUART_BAUD_RIAEIE_MASK; + } + else + { + pUart->BAUD &= ~FCUART_BAUD_RIAEIE_MASK; + } +} + +/** + * @brief Set uart receive active interrupt. + * + * @param pUart UART instance value + * @param return false for disable, true for enable. + */ +LOCAL_INLINE bool FCUART_HWA_GetReceiveActiveInterrupt(FCUART_Type *pUart) +{ + bool bRetVal = false; + + if (0U != (pUart->BAUD & FCUART_BAUD_RIAEIE_MASK)) + { + bRetVal = true; + } + + return bRetVal; +} + +/** + * @brief Set FCUART inverse feature. + * + * @param pUart UART instance value + * @param bEnable false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetReceiveDataInverse(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->STAT |= FCUART_STAT_RXINV_MASK; + } + else + { + pUart->STAT &= ~FCUART_STAT_RXINV_MASK; + } +} + +/** + * @brief Get the FCUART inverse bit value. + * + * @param pUart UART instance value + * @param return false for disable, true for enable. + */ +LOCAL_INLINE bool FCUART_HWA_GetReceiveDataInverse(FCUART_Type *pUart) +{ + bool bRetVal = false; + + if (0U != (pUart->STAT & FCUART_STAT_RXINV_MASK)) + { + bRetVal = true; + } + + return bRetVal; +} + +/** + * @brief Set the FCUART frame error interrupt. + * + * @param pUart UART instance value + * @param bEnable false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetFrameErrorInterrupt(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->CTRL |= FCUART_CTRL_FEIE_MASK; + } + else + { + pUart->CTRL &= ~FCUART_CTRL_FEIE_MASK; + } +} + +/** + * @brief Enable the FCUART loop mode. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableLoopMode(FCUART_Type *pUart) +{ + pUart->CTRL |= FCUART_CTRL_LOOPMS_MASK; +} + +/** + * @brief Disable the FCUART loop mode. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableLoopMode(FCUART_Type *pUart) +{ + pUart->CTRL &= ~FCUART_CTRL_LOOPMS_MASK; +} + +/** + * \brief Set FCUART MODIR value + * + * \param pUart UART instance value + * \param u32Data Set data + */ +LOCAL_INLINE void FCUART_HWA_SetModir(FCUART_Type *pUart, uint32_t u32Data) +{ + pUart->MODIR = u32Data; /* data 32 bit */ +} + +/** + * \brief Get FCUART MODIR value + * + * \param pUart UART instance value + * \param u32Data Get data + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetModir(FCUART_Type *pUart) +{ + return pUart->MODIR ; +} + +/** @}*/ + +#endif /* end for #ifndef _HWA_FCUART_H_ */ diff --git a/Inc/HwA_flexcan.h b/Inc/HwA_flexcan.h new file mode 100644 index 0000000..0a3d69b --- /dev/null +++ b/Inc/HwA_flexcan.h @@ -0,0 +1,1001 @@ +/** + * @file fc7xxx_driver_flexcan.h + * @author Flagchip + * @brief FC7xxx FlexCAN register API + * @version 0.1.0 + * @date 2024-1-13 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Author Descriptions + * --------- ---------- ------------ --------------- + * 0.1.0 2024-1-13 Flagchip0112 First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_FLEXCAN_H_ +#define _HWA_FLEXCAN_H_ + +#include "device_header.h" + + + + + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + +/* ****************************** Message Buffer Structure ************************************* */ + +/* ************************************************ 8bytes data ******************************************************* */ +/* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 */ +/* 0x00 | EDL | BRS | ESI | | CODE | | SRR | IDE | RTR | DLC | TIME STAMP | */ +/* 0x04 | PRIO | ID (STD/EXT high 11bits) | ID (EXT low 18bits) | */ +/* 0x08 | Data Byte 0 | Data Byte 1 | Data Byte 2 | Data Byte 3 | */ +/* 0x0C | Data Byte 4 | Data Byte 5 | Data Byte 6 | Data Byte 7 | */ + + +/* ************************************************ 16bytes data ****************************************************** */ +/* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 */ +/* 0x00 | EDL | BRS | ESI | | CODE | | SRR | IDE | RTR | DLC | TIME STAMP | */ +/* 0x04 | PRIO | ID (STD/EXT high 11bits) | ID (EXT low 18bits) | */ +/* 0x08 | Data Byte 0 | Data Byte 1 | Data Byte 2 | Data Byte 3 | */ +/* 0x0C | Data Byte 4 | Data Byte 5 | Data Byte 6 | Data Byte 7 | */ +/* ................................ */ +/* 0x1C | Data Byte 12 | Data Byte 13 | Data Byte 14 | Data Byte 15| */ + + +/* ************************************************ 32bytes data ****************************************************** */ +/* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 */ +/* 0x00 | EDL | BRS | ESI | | CODE | | SRR | IDE | RTR | DLC | TIME STAMP | */ +/* 0x04 | PRIO | ID (STD/EXT high 11bits) | ID (EXT low 18bits) | */ +/* 0x08 | Data Byte 0 | Data Byte 1 | Data Byte 2 | Data Byte 3 | */ +/* 0x0C | Data Byte 4 | Data Byte 5 | Data Byte 6 | Data Byte 7 | */ +/* ................................ */ +/* 0x30 | Data Byte 28 | Data Byte 29 | Data Byte 30 | Data Byte 31| */ + + +/* ************************************************ 64bytes data ****************************************************** */ +/* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 */ +/* 0x00 | EDL | BRS | ESI | | CODE | | SRR | IDE | RTR | DLC | TIME STAMP | */ +/* 0x04 | PRIO | ID (STD/EXT high 11bits) | ID (EXT low 18bits) | */ +/* 0x08 | Data Byte 0 | Data Byte 1 | Data Byte 2 | Data Byte 3 | */ +/* 0x0C | Data Byte 4 | Data Byte 5 | Data Byte 6 | Data Byte 7 | */ +/* ................................ */ +/* 0x44 | Data Byte 60 | Data Byte 61 | Data Byte 62 | Data Byte 63| */ + + +/** + * @addtogroup HwA_flexcan + * @{ + */ + + +/** Register address with offset */ +#define FLEXCAN_REGISTER_WITHOFFSET(reg,offset1,offset2) ((uint32_t)(reg)+(uint32_t)(offset1)+(uint32_t)(offset2)) +/** Get register value */ +#define FLEXCAN_REG32_CONTENT(reg) (*((uint32_t*)(reg))) + + + + +/** U32 value around */ +#define FLEXCAN_U32MACRO(var) ((uint32_t)(var)) +#define FLEXCAN_U32SHIFT(var,mask,shift) ((uint32_t)((((uint32_t)(var))&(mask))<<(shift))) +#define FLEXCAN_U32NOTSHIFT(mask,shift) ((uint32_t)(~(((uint32_t)(mask))<<(shift)))) + + +/* legacy message buffer */ + +/** Legacy/EnHanced Message Buffer Header */ +#define FLEXCAN_MB_HEADER_BYTELEN 8UL +/** Legacy Message Buffer Address */ +#define FLEXCAN_MB_ADDR(mbOffset, mbIndex, dataLen) FLEXCAN_U32MACRO(FLEXCAN_U32MACRO(mbOffset)+FLEXCAN_U32MACRO(mbIndex)*(FLEXCAN_U32MACRO(dataLen)+FLEXCAN_MB_HEADER_BYTELEN)) + + +/** Legacy Message Buffer word n Address */ +#define FLEXCAN_MB_WORDN_ADDR(mbOffset, mbIndex, dataLen, offset) (FLEXCAN_MB_ADDR((mbOffset), (mbIndex), (dataLen))+FLEXCAN_U32MACRO(offset)) + +/** Legacy Message Buffer Data Address */ +/* #define FLEXCAN_MB_DATA_ADDR_GET(mbOffset, mbIndex, dataLen) (FLEXCAN_MB_WORDN_ADDR((mbOffset), (mbIndex), (dataLen),2U)) */ + +/** Legacy Message Buffer EDL Get */ +#define FLEXCAN_MB_EDL_GET(edlAddr) ((FLEXCAN_REG32_CONTENT(edlAddr)>>31)&0x01U) +/** Legacy Message Buffer EDL Clear */ +#define FLEXCAN_MB_EDL_CLR(edlAddr) (FLEXCAN_REG32_CONTENT(edlAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,31)) +/** Legacy Message Buffer EDL Attach */ +#define FLEXCAN_MB_EDL_ATTACH(edlAddr,var) (FLEXCAN_REG32_CONTENT(edlAddr) |= FLEXCAN_U32SHIFT(var,0x01U,31)) +/** Legacy Message Buffer EDL Set */ +#define FLEXCAN_MB_EDL_SET(edlAddr,var) FLEXCAN_MB_EDL_CLR(edlAddr); FLEXCAN_MB_EDL_ATTACH(edlAddr,var) + + +/** Legacy Message Buffer BRS Get */ +#define FLEXCAN_MB_BRS_GET(brsAddr) (((FLEXCAN_REG32_CONTENT(brsAddr))>>30)&0x01U) +/** Legacy Message Buffer BRS Clear */ +#define FLEXCAN_MB_BRS_CLR(brsAddr) (FLEXCAN_REG32_CONTENT(brsAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,30)) +/** Legacy Message Buffer BRS Attach */ +#define FLEXCAN_MB_BRS_ATTACH(brsAddr,var) (FLEXCAN_REG32_CONTENT(brsAddr) |= FLEXCAN_U32SHIFT(var,0x01U,30)) +/** Legacy Message Buffer BRS set */ +#define FLEXCAN_MB_BRS_SET(brsAddr,var) FLEXCAN_MB_BRS_CLR(brsAddr); FLEXCAN_MB_BRS_ATTACH(brsAddr,var) + +/** Legacy Message Buffer ESI Get */ +#define FLEXCAN_MB_ESI_GET(esiAddr) (((FLEXCAN_REG32_CONTENT(esiAddr))>>29)&0x01U) +/** Legacy Message Buffer ESI Clear */ +#define FLEXCAN_MB_ESI_CLR(esiAddr) (FLEXCAN_REG32_CONTENT(esiAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,29)) +/** Legacy Message Buffer ESI Attach */ +#define FLEXCAN_MB_ESI_ATTACH(esiAddr,var) (FLEXCAN_REG32_CONTENT(esiAddr) |= FLEXCAN_U32SHIFT(var,0x01U,29)) +/** Legacy Message Buffer ESI Set */ +#define FLEXCAN_MB_ESI_SET(esiAddr,var) FLEXCAN_MB_ESI_CLR(esiAddr); FLEXCAN_MB_ESI_ATTACH(esiAddr,var) + +/** Legacy Message Buffer CODE Get */ +#define FLEXCAN_MB_CODE_GET(codeAddr) (((FLEXCAN_REG32_CONTENT(codeAddr))>>24)&0x0FU) +/** Legacy Message Buffer CODE Clear */ +#define FLEXCAN_MB_CODE_CLR(codeAddr) (FLEXCAN_REG32_CONTENT(codeAddr) &= FLEXCAN_U32NOTSHIFT(0x0FU,24)) +/** Legacy Message Buffer CODE Attach */ +#define FLEXCAN_MB_CODE_ATTACH(codeAddr,var) (FLEXCAN_REG32_CONTENT(codeAddr) |= FLEXCAN_U32SHIFT(var,0x0FU,24)) +/** Legacy Message Buffer CODE set */ +#define FLEXCAN_MB_CODE_SET(codeAddr,var) FLEXCAN_MB_CODE_CLR(codeAddr); FLEXCAN_MB_CODE_ATTACH(codeAddr,var) + + +/** Legacy Message Buffer SRR Get */ +#define FLEXCAN_MB_SRR_GET(srrAddr) (((FLEXCAN_REG32_CONTENT(srrAddr)) >>22)&0x01U) +/** Legacy Message Buffer SRR Clear */ +#define FLEXCAN_MB_SRR_CLR(srrAddr) (FLEXCAN_REG32_CONTENT(srrAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,22)) +/** Legacy Message Buffer SRR Attach */ +#define FLEXCAN_MB_SRR_ATTACH(srrAddr,var) (FLEXCAN_REG32_CONTENT(srrAddr) |= FLEXCAN_U32SHIFT(var,0x01U,22)) +/** Legacy Message Buffer SRR set */ +#define FLEXCAN_MB_SRR_SET(srrAddr,var) FLEXCAN_MB_SRR_CLR(srrAddr); FLEXCAN_MB_SRR_ATTACH(srrAddr,var) + +/** Legacy Message Buffer IDE Get */ +#define FLEXCAN_MB_IDE_GET(ideAddr) (((FLEXCAN_REG32_CONTENT(ideAddr))>>21)&0x01U) +/** Legacy Message Buffer IDE Clear */ +#define FLEXCAN_MB_IDE_CLR(ideAddr) (FLEXCAN_REG32_CONTENT(ideAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,21)) +/** Legacy Message Buffer IDE Attach */ +#define FLEXCAN_MB_IDE_ATTACH(ideAddr,var) (FLEXCAN_REG32_CONTENT(ideAddr) |= FLEXCAN_U32SHIFT(var,0x01U,21)) +/** Legacy Message Buffer IDE set */ +#define FLEXCAN_MB_IDE_SET(ideAddr,var) FLEXCAN_MB_IDE_CLR(ideAddr); FLEXCAN_MB_IDE_ATTACH(ideAddr,var) + + +/** Legacy Message Buffer RTR Get */ +#define FLEXCAN_MB_RTR_GET(rtrAddr) (((FLEXCAN_REG32_CONTENT(rtrAddr))>>20)&0x01U) +/** Legacy Message Buffer RTR Clear */ +#define FLEXCAN_MB_RTR_CLR(rtrAddr) (FLEXCAN_REG32_CONTENT(rtrAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,20)) +/** Legacy Message Buffer RTR Attach */ +#define FLEXCAN_MB_RTR_ATTACH(rtrAddr,var) (FLEXCAN_REG32_CONTENT(rtrAddr) |= FLEXCAN_U32SHIFT(var,0x01U,20)) +/** Legacy Message Buffer RTR set */ +#define FLEXCAN_MB_RTR_SET(rtrAddr,var) FLEXCAN_MB_RTR_CLR(rtrAddr); FLEXCAN_MB_RTR_ATTACH(rtrAddr,var) + +/** Legacy Message Buffer DLC Get */ +#define FLEXCAN_MB_DLC_GET(dlcAddr) (((FLEXCAN_REG32_CONTENT(dlcAddr))>>16)&0x0FU) +/** Legacy Message Buffer DLC Clear */ +#define FLEXCAN_MB_DLC_CLR(dlcAddr) (FLEXCAN_REG32_CONTENT(dlcAddr) &= FLEXCAN_U32NOTSHIFT(0x0FU,16)) +/** Legacy Message Buffer DLC Attach */ +#define FLEXCAN_MB_DLC_ATTACH(dlcAddr,var) (FLEXCAN_REG32_CONTENT(dlcAddr) |= FLEXCAN_U32SHIFT(var,0x0FU,16)) +/** Legacy Message Buffer DLC Set */ +#define FLEXCAN_MB_DLC_SET(dlcAddr,var) FLEXCAN_MB_DLC_CLR(dlcAddr); FLEXCAN_MB_DLC_ATTACH(dlcAddr,var) + +/** Legacy Message Buffer TIME STAMP Get */ +#define FLEXCAN_MB_TIMESTAMP_GET(timestampAddr) (FLEXCAN_REG32_CONTENT(timestampAddr)&0xFFFFU) +/** Legacy Message Buffer TIME STAMP Clear */ +#define FLEXCAN_MB_TIMESTAMP_CLR(timestampAddr) (FLEXCAN_REG32_CONTENT(timestampAddr) &= FLEXCAN_U32NOTSHIFT(0xFFFFU,0)) +/** Legacy Message Buffer TIME STAMP Attach */ +#define FLEXCAN_MB_TIMESTAMP_ATTACH(timestampAddr,var) (FLEXCAN_REG32_CONTENT(timestampAddr) |= FLEXCAN_U32SHIFT(var,0xFFFFU,0)) +/** Legacy Message Buffer TIME STAMP Set */ +#define FLEXCAN_MB_TIMESTAMP_SET(timestampAddr,var) FLEXCAN_MB_TIMESTAMP_CLR(timestampAddr); FLEXCAN_MB_TIMESTAMP_ATTACH(timestampAddr,var) + +/** Legacy Message Buffer PRIO Get */ +#define FLEXCAN_MB_PRIO_GET(prioAddr) (((FLEXCAN_REG32_CONTENT(prioAddr))>>29)&0x07U) +/** Legacy Message Buffer PRIO Clear */ +#define FLEXCAN_MB_PRIO_CLR(prioAddr) (FLEXCAN_REG32_CONTENT(prioAddr) &= FLEXCAN_U32NOTSHIFT(0x07U,29)) +/** Legacy Message Buffer PRIO Attach */ +#define FLEXCAN_MB_PRIO_ATTACH(prioAddr,var) (FLEXCAN_REG32_CONTENT(prioAddr) |= FLEXCAN_U32SHIFT(var,0x07U,29)) +/** Legacy Message Buffer PRIO Set */ +#define FLEXCAN_MB_PRIO_SET(prioAddr,var) FLEXCAN_MB_PRIO_CLR(prioAddr); FLEXCAN_MB_PRIO_ATTACH(prioAddr,var) + +/** Legacy Message Buffer STD ID Get */ +#define FLEXCAN_MB_STDID_GET(stdidAddr) (((FLEXCAN_REG32_CONTENT(stdidAddr))>>18)&0x7FFU) +/** Legacy Message Buffer STD ID CLR */ +#define FLEXCAN_MB_STDID_CLR(stdidAddr) (FLEXCAN_REG32_CONTENT(stdidAddr) &= FLEXCAN_U32NOTSHIFT(0x7FFU,18)) +/** Legacy Message Buffer STD ID Attach */ +#define FLEXCAN_MB_STDID_ATTACH(stdidAddr,var) (FLEXCAN_REG32_CONTENT(stdidAddr) |= FLEXCAN_U32SHIFT(var,0x7FFU,18)) +/** Legacy Message Buffer STD ID set */ +#define FLEXCAN_MB_STDID_SET(stdidAddr,var) FLEXCAN_MB_STDID_CLR(stdidAddr); FLEXCAN_MB_STDID_ATTACH(stdidAddr,var) + +/** Legacy Message Buffer EXT ID Get */ +#define FLEXCAN_MB_EXTID_GET(extidAddr) ((FLEXCAN_REG32_CONTENT(extidAddr))&0x1FFFFFFF) +/** Legacy Message Buffer EXT ID Clear */ +#define FLEXCAN_MB_EXTID_CLR(extidAddr) (FLEXCAN_REG32_CONTENT(extidAddr) &= FLEXCAN_U32NOTSHIFT(0x1FFFFFFF,0)) +/** Legacy Message Buffer EXT ID Attach */ +#define FLEXCAN_MB_EXTID_ATTACH(extidAddr,var) (FLEXCAN_REG32_CONTENT(extidAddr) |= FLEXCAN_U32SHIFT(var,0x1FFFFFFF,0)) +/** Legacy Message Buffer EXT ID set */ +#define FLEXCAN_MB_EXTID_SET(extidAddr,var) FLEXCAN_MB_EXTID_CLR(extidAddr); FLEXCAN_MB_EXTID_ATTACH(extidAddr,var) + +/* enhanced fifo message buffer */ + +/** Enhanced FIFO Message Buffer EDL Get */ +#define FLEXCAN_EFIFOMB_EDL_GET() ((pCan->ERX_FIFO[0U]>>31)&0x01U) + +/** Enhanced FIFO Message Buffer BRS Get */ +#define FLEXCAN_EFIFOMB_BRS_GET() ((pCan->ERX_FIFO[0U]>>30)&0x01U) + +/** Enhanced FIFO Message Buffer ESI Get */ +#define FLEXCAN_EFIFOMB_ESI_GET() ((pCan->ERX_FIFO[0U]>>29)&0x01U) + +/** Enhanced FIFO Message Buffer SRR Get */ +#define FLEXCAN_EFIFOMB_SRR_GET() ((pCan->ERX_FIFO[0U] >>22)&0x01U) + +/** Enhanced FIFO Message Buffer IDE Get */ +#define FLEXCAN_EFIFOMB_IDE_GET() ((pCan->ERX_FIFO[0U]>>21)&0x01U) + +/** Enhanced FIFO Message Buffer RTR Get */ +#define FLEXCAN_EFIFOMB_RTR_GET() ((pCan->ERX_FIFO[0U]>>20)&0x01U) + +/** Enhanced FIFO Message Buffer DLC Get */ +#define FLEXCAN_EFIFOMB_DLC_GET() ((pCan->ERX_FIFO[0U]>>16)&0x0FU) + +/** Enhanced FIFO Message Buffer TIME STAMP Get */ +#define FLEXCAN_EFIFOMB_TIMESTAMP_GET() (pCan->ERX_FIFO[0U]&0xFFU) + +/** Enhanced FIFO Message Buffer STD ID Get */ +#define FLEXCAN_EFIFOMB_STDID_GET() ((pCan->ERX_FIFO[1U]>>18)&0x7FFU) + +/** Enhanced FIFO Message Buffer EXT ID Get */ +#define FLEXCAN_EFIFOMB_EXTID_GET() (pCan->ERX_FIFO[1U]&0x1FFFFFFF) + +/** Enhanced FIFO Message Buffer Data Get */ +#define FLEXCAN_EFIFOMB_DATAADDR_GET(wordIndex) (&(pCan->ERX_FIFO[2U+(wordIndex)])) + +/** Enhanced FIFO Message Buffer IDHIT Get */ +#define FLEXCAN_EFIFOMB_IDHIT_GET(dataWordLen) ((pCan->ERX_FIFO[2U+(dataWordLen)])&0x1FFU) + +/** Enhanced FIFO Message Buffer HR Time Stamp Get */ +#define FLEXCAN_EFIFOMB_HRTIMESTAMP_GET(dataWordLen) (pCan->ERX_FIFO[3U+(dataWordLen)]) + +/* enhanced fifo message buffer from user buffer*/ + +/** Enhanced FIFO Message Buffer EDL Get */ +#define FLEXCAN_EFIFOMB_EDL_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>31)&0x01U) + +/** Enhanced FIFO Message Buffer BRS Get */ +#define FLEXCAN_EFIFOMB_BRS_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>30)&0x01U) + +/** Enhanced FIFO Message Buffer ESI Get */ +#define FLEXCAN_EFIFOMB_ESI_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>29)&0x01U) + +/** Enhanced FIFO Message Buffer SRR Get */ +#define FLEXCAN_EFIFOMB_SRR_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U] >>22)&0x01U) + +/** Enhanced FIFO Message Buffer IDE Get */ +#define FLEXCAN_EFIFOMB_IDE_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>21)&0x01U) + +/** Enhanced FIFO Message Buffer RTR Get */ +#define FLEXCAN_EFIFOMB_RTR_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>20)&0x01U) + +/** Enhanced FIFO Message Buffer DLC Get */ +#define FLEXCAN_EFIFOMB_DLC_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>16)&0x0FU) + +/** Enhanced FIFO Message Buffer TIME STAMP Get */ +#define FLEXCAN_EFIFOMB_TIMESTAMP_GET_FROM_BUFFER(Addr) (((uint32_t*)Addr)[0U]&0xFFU) + +/** Enhanced FIFO Message Buffer STD ID Get */ +#define FLEXCAN_EFIFOMB_STDID_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[1U]>>18)&0x7FFU) + +/** Enhanced FIFO Message Buffer EXT ID Get */ +#define FLEXCAN_EFIFOMB_EXTID_GET_FROM_BUFFER(Addr) (((uint32_t*)Addr)[1U]&0x1FFFFFFF) + +/** Enhanced FIFO Message Buffer Data Get */ +#define FLEXCAN_EFIFOMB_DATAADDR_GET_FROM_BUFFER(Addr, wordIndex) (&(((uint32_t*)Addr)[2U+(wordIndex)])) + +/** Enhanced FIFO Message Buffer IDHIT Get */ +#define FLEXCAN_EFIFOMB_IDHIT_GET_FROM_BUFFER(Addr, dataWordLen) ((((uint32_t*)Addr)[2U+(dataWordLen)])&0x1FFU) + +/** Enhanced FIFO Message Buffer HR Time Stamp Get */ +#define FLEXCAN_EFIFOMB_HRTIMESTAMP_GET_FROM_BUFFER(Addr, dataWordLen) (((uint32_t*)Addr)[3U+(dataWordLen)]) + +/* ################################################################################## */ +/* ################################### Type define ################################## */ + +/** + * \brief FLEXCAN Clock Source Select Enumeration + * + */ +typedef enum +{ + FLEXCAN_CLOCK_FUNCTION = 0x00U,/**< FLEXCAN_CLOCK_FUNCTION clock from asynchronous clock */ + FLEXCAN_CLOCK_MODULE = 0x01U /**< FLEXCAN_CLOCK_MODULE clock from peripheral clock */ +} FLEXCAN_ClockSrcType; + + + +/* ################################################################################## */ +/* ################################## Local Inline ################################## */ + + + +/** + * \brief Set Module Disable + * + * \param pCan FLEXCAN instance value + * \param bDisable set whether disable + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMcrDisable(FLEXCAN_Type *const pCan, uint8_t bDisable) +{ + if (bDisable == TRUE) + { + pCan->MCR |= FLEXCAN_MCR_MDIS_MASK; /* bitMDIS=1: Disable module before selecting clock */ + } + else + { + pCan->MCR &= ~FLEXCAN_MCR_MDIS_MASK; + } +} + +/** + * \brief Set Module Freeze + * + * \param pCan FLEXCAN instance value + * \param bFreeze set whether freeze + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMcrFreeze(FLEXCAN_Type *const pCan, uint8_t bFreeze) +{ + if (bFreeze == TRUE) + { + pCan->MCR |= FLEXCAN_MCR_FRZ_MASK; /* bitMDIS=1: Disable module before selecting clock */ + } + else + { + pCan->MCR &= ~FLEXCAN_MCR_FRZ_MASK; + } +} + + +/** + * \brief Set Module Halt and Freeze + * + * \param pCan FLEXCAN instance value + * \param bFreeze set whether freeze + */ +LOCAL_INLINE void FLEXCAN_HWA_SetHaltFreeze(FLEXCAN_Type *const pCan) +{ + pCan->MCR |= FLEXCAN_MCR_FRZ_MASK | FLEXCAN_MCR_HALT_MASK; +} + +/** + * \brief Wait FLEXCAN Module Enter Freezen mode + * + * \param pCan FLEXCAN instance value + * \param u32TimeoutTick Timeout tick + * \return 0U is really in freezen mode + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_WaitMcrFreezen(FLEXCAN_Type *const pCan, uint32_t u32TimeoutTick) +{ + /* wait for bitFRZACK=1 on freeze mode entry/exit */ + while ( (!((pCan->MCR & FLEXCAN_MCR_FRZACK_MASK) >> FLEXCAN_MCR_FRZACK_SHIFT)) && (u32TimeoutTick-->0U) ) + { + + } + + return (u32TimeoutTick==0U); +} + +/** + * \brief Wait FLEXCAN Module Exit Freezen mode + * + * \param pCan FLEXCAN instance value + * \param u32TimeoutTick Timeout tick + * \return 1U is really in freezen mode + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_WaitMcrExitFreezen(FLEXCAN_Type *const pCan, uint32_t u32TimeoutTick) +{ + while ( ((pCan->MCR & FLEXCAN_MCR_FRZACK_MASK) >> FLEXCAN_MCR_FRZACK_SHIFT) && (u32TimeoutTick-->0U) ) + {} + /* wait for bitFRZACK to clear (not in freeze mode) */ + + return (u32TimeoutTick==0U); +} + +/** + * \brief Wait FLEXCAN Module Ready + * + * \param pCan FLEXCAN instance value + * \param u32TimeoutTick Timeout tick + * \return 1U is really ready + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_WaitMcrReady(FLEXCAN_Type *const pCan, uint32_t u32TimeoutTick) +{ + while ( ((pCan->MCR & FLEXCAN_MCR_NOTRDY_MASK) >> FLEXCAN_MCR_NOTRDY_SHIFT) && (u32TimeoutTick-->0U) ) + {} + /* wait for bitNOTRDY to clear (module ready) */ + + return (u32TimeoutTick==0U); +} + +/** + * \brief Wait FLEXCAN Module Not Ready + * + * \param pCan FLEXCAN instance value + * \param u32TimeoutTick Timeout tick + * \return 1U is really not ready + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_WaitMcrNoReady(FLEXCAN_Type *const pCan, uint32_t u32TimeoutTick) +{ + while ( (!((pCan->MCR & FLEXCAN_MCR_NOTRDY_MASK) >> FLEXCAN_MCR_NOTRDY_SHIFT)) && (u32TimeoutTick-->0U) ) + {} + /* wait for bitNOTRDY to set (module ready) */ + + return (u32TimeoutTick==0U); +} + +/** + * \brief Set FLEXCAN MCR value + * + * \param pCan FLEXCAN instance value + * \param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMCR(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->MCR = u32Value; +} + +/** + * \brief Get FLEXCAN MCR value + * + * \param pCan FLEXCAN instance value + * \return MCR value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetMCR(FLEXCAN_Type *const pCan) +{ + return (uint32_t)pCan->MCR; +} + +/** + * \brief Attach FLEXCAN MCR value + * + * \param pCan FLEXCAN instance value + * \param u32Value attached value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachMCR(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->MCR |= u32Value; +} + + +/** + * \brief Set FLEXCAN baudrate clock source + * + * \param pCan FLEXCAN instance value + * \param tBaudClk Baudrate clock source + */ +LOCAL_INLINE void FLEXCAN_HWA_SetCtrl1BaudSrc(FLEXCAN_Type *const pCan, FLEXCAN_ClockSrcType tBaudClk) +{ + if (tBaudClk == FLEXCAN_CLOCK_MODULE) + { + pCan->CTRL1 |= FLEXCAN_CTRL1_CLKSRC_MASK; + } + else + { + pCan->CTRL1 &= ~FLEXCAN_CTRL1_CLKSRC_MASK; + } +} + +/** + * \brief Set FLEXCAN ctrl1 value + * + * \param pCan FLEXCAN instance value + * \param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetCtrl1(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CTRL1 = u32Value; +} + +/** + * \brief Attach FLEXCAN ctrl1 value + * + * \param pCan FLEXCAN instance value + * \param u32Value attached value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachCtrl1(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CTRL1 |= u32Value; +} + + +/** + * \brief Get IFLAG1 Flag + * + * \param pCan FLEXCAN instance value + * \return flag1 value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetFlag1(FLEXCAN_Type *const pCan) +{ + return pCan->IFLAG1; +} + + +/** + * \brief Clear IFLAG1 Flag + * + * \param pCan FLEXCAN instance value + * \param u32W1cFlag write clear value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetFlag1(FLEXCAN_Type *const pCan, uint32_t u32W1cFlag) +{ + pCan->IFLAG1 = u32W1cFlag; +} + +/** + * \brief Clear Rx Flag and unlock MB + * + * \param pCan FLEXCAN instance value + * \param u32MbIndex Message Buffer Index + */ +LOCAL_INLINE void FLEXCAN_HWA_UnlockMbNoFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32MbIndex) +{ + (void)pCan->TIMER; /* Read TIMER to unlock message buffers */ + pCan->IFLAG1 = 1U << u32MbIndex; +} + +/** + * \brief Clear MB Flag + * + * \param pCan FLEXCAN instance value + * \param u32MbIndex Message Buffer Index + */ +LOCAL_INLINE void FLEXCAN_HWA_W1cFlag1NoFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32MbIndex) +{ + pCan->IFLAG1 = 1U << u32MbIndex; +} + +/** + * \brief Get MB Flag + * + * \param pCan FLEXCAN instance value + * \param u32MbIndex Message Buffer Index + * \return flag value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetFlag1NoFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32MbIndex) +{ + return (pCan->IFLAG1 >> u32MbIndex) & 0x01U; +} + +/** + * \brief Get Legacy Fifo Rx Flag + * + * \param pCan FLEXCAN instance value + * \return flag fifo value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetIFLAG1FifoFlag(FLEXCAN_Type *const pCan) +{ + /* IFLAG1[BIT5] (Frames available in Rx FIFO) is asserted when there is at least one frame available to be read from the FIFO. */ + return (pCan->IFLAG1 >> 5) & 0x01U; +} + +/** + * \brief Clear Legacy Fifo Rx Flag + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ClearIFLAG1FifoFlag(FLEXCAN_Type *const pCan) +{ + /* Read TIMER to unlock message buffers */ + (void)pCan->TIMER; + + pCan->IFLAG1 = 1U << 5; +} + +/** + * \brief Set special message buffer interrupt + * + * \param pCan FLEXCAN instance value + * \param u32Mask Message Buffer interrupt mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMaskMbInterrupt(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->IMASK1 = u32Mask; +} + +/** + * \brief Attach special message buffer interrupt + * + * \param pCan FLEXCAN instance value + * \param u32MbIndex Message Buffer index + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachMaskMbInterrupt(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->IMASK1 |= u32Mask; +} + +/** + * \brief Attach special message buffer interrupt + * + * \param pCan FLEXCAN instance value + * \param u32MbIndex Message Buffer index + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachMbIndexInterrupt(FLEXCAN_Type *const pCan, uint32_t u32MbIndex) +{ + pCan->IMASK1 |= 1U << u32MbIndex; +} + +/** + * \brief Set Legacy Fifo Rx interrupt + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMaskFifoInterrupt(FLEXCAN_Type *const pCan) +{ + pCan->IMASK1 = 1U << 5U; +} + +/** + * \brief Set CTRL2 value + * + * \param pCan FLEXCAN instance value + * \param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetCtrl2(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CTRL2 = u32Value; +} + +/** + * \brief Attach FLEXCAN ctrl2 value + * + * \param pCan FLEXCAN instance value + * \param u32Value attached value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachCtrl2(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CTRL2 |= u32Value; +} + +/** + * \brief Set CBT value + * + * \param pCan FLEXCAN instance value + * \param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetCBT(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CBT = u32Value; +} + +/** + * \brief Set FDCBT value + * + * \param pCan FLEXCAN instance value + * \param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetFDCBT(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->FDCBT = u32Value; +} + +/** + * \brief Set FDCTRL value + * + * \param pCan FLEXCAN instance value + * \param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetFDCTRL(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->FDCTRL = u32Value; +} + + +/** + * \brief This Function is used to get FLEXCAN rx timestamp + * + * \param pCan is FLEXCAN instance value + * \return timestamp Register Value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetTimeStamp(FLEXCAN_Type *const pCan) +{ + return pCan->TIMER; +} + +/** + * \brief This Function is used to get FLEXCAN error + * + * \param pCan is FLEXCAN instance value + * \return ESR1 Register Value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetErrorInfo(FLEXCAN_Type *const pCan) +{ + return pCan->ESR1; +} + +/** + * \brief This Function is used to get FLEXCAN error with interrupt + * + * \param pCan is FLEXCAN instance value + * \return ESR1 Register Value with interrupt mask + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetErrorIntInfo(FLEXCAN_Type *const pCan) +{ + uint32_t u32IntMask = 0U; + + u32IntMask = ((0U == (pCan->CTRL1 & FLEXCAN_CTRL1_ERRMSK_MASK))?0U:FLEXCAN_ESR1_ERRINT_MASK); + u32IntMask |= ((0U == (pCan->CTRL1 & FLEXCAN_CTRL1_BOFFMSK_MASK))?0U:FLEXCAN_ESR1_BOFFINT_MASK); + u32IntMask |= ((0U == (pCan->CTRL2 & FLEXCAN_CTRL2_ERRMSK_FAST_MASK))?0U:FLEXCAN_ESR1_ERRINT_FAST_MASK); + u32IntMask |= ((0U == (pCan->CTRL2 & FLEXCAN_CTRL2_BOFFDONEMSK_MASK))?0U:FLEXCAN_ESR1_BOFFDONEINT_MASK); + + return (pCan->ESR1 & u32IntMask); +} + +/** + * \brief Clear Error Info + * + * \param pCan FLEXCAN instance value + * \param u32ErrorEsr1 is read from FLEXCAN_GetErrorInfo + */ +LOCAL_INLINE void FLEXCAN_HWA_ClrErrorInfo(FLEXCAN_Type *const pCan, uint32_t u32ErrorEsr1) +{ + pCan->ESR1 = u32ErrorEsr1; +} + +/** + * \brief This Function is used to get FLEXCAN error count + * + * \param pCan is FLEXCAN instance value + * \return ECR Register Value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetErrorCount(FLEXCAN_Type *const pCan) +{ + return pCan->ECR; +} + +/** + * \brief Enable FLEXCAN Legacy Fifo + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_EnableLegacyFifo(FLEXCAN_Type *const pCan) +{ + /* if enable legacy fifo, FD fifo must be disabled */ + pCan->MCR |= FLEXCAN_MCR_RFEN_MASK; /* set legacy fifo */ +} + +/** + * \brief Disable FLEXCAN Legacy Fifo + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_DisableLegacyFifo(FLEXCAN_Type *const pCan) +{ + /* if enable legacy fifo, FD fifo must be disabled */ + pCan->MCR &= ~FLEXCAN_MCR_RFEN_MASK; /* clear legacy fifo */ +} + +/** + * \brief Enable FLEXCAN FD Fifo + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_EnableFDFifo(FLEXCAN_Type *const pCan) +{ + /* if enable fd fifo, legacy fifo must be disabled */ + pCan->ERFCR |= FLEXCAN_ERFCR_ERFEN_MASK; /* set enhanced fifo */ +} + +/** + * \brief Disable FLEXCAN FD Fifo + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_DisableFDFifo(FLEXCAN_Type *const pCan) +{ + /* if enable fd fifo, legacy fifo must be disabled */ + pCan->ERFCR &= ~FLEXCAN_ERFCR_ERFEN_MASK; /* clear enhanced fifo */ +} + + + +/** + * \brief Check FLEXCAN legacy fifo if enabled + * + * \param pCan FLEXCAN instance value + * \return 1 is legacy fifo enabled, 0 is disabled + */ +LOCAL_INLINE uint8_t FLEXCAN_HWA_CheckLegacyFifoEnabled(FLEXCAN_Type *const pCan) +{ + uint8_t u8RetVal; + uint32_t u32Value; + + /* get legacy fifo */ + u32Value = (pCan->MCR & FLEXCAN_MCR_RFEN_MASK) >> FLEXCAN_MCR_RFEN_SHIFT; + + u8RetVal = u32Value == 0U ? (uint8_t)0x0U : (uint8_t)0x1U; + + return u8RetVal; +} + +/** + * \brief Check FLEXCAN FD fifo if enabled + * + * \param pCan FLEXCAN instance value + * \return 1 is legacy fifo enabled, 0 is disabled + */ +LOCAL_INLINE uint8_t FLEXCAN_HWA_CheckFdFifoEnabled(FLEXCAN_Type *const pCan) +{ + uint8_t u8RetVal; + uint32_t u32Value; + /* get enhanced fifo */ + u32Value = (pCan->ERFCR & FLEXCAN_ERFCR_ERFEN_MASK) >> FLEXCAN_ERFCR_ERFEN_SHIFT; + + u8RetVal = u32Value == 0U ? (uint8_t)0x0U : (uint8_t)0x1U; + + return u8RetVal; +} + +/** + * \brief Set legacy fifo filter number number + * + * \param pCan FLEXCAN instance value + * \param u32FilterNum is total filter number + */ +LOCAL_INLINE void FLEXCAN_HWA_SetLegacyFifoFilterNum(FLEXCAN_Type *const pCan, uint32_t u32FilterNum) +{ + pCan->CTRL2 &= ~FLEXCAN_CTRL2_RFFN_MASK; /* clear fifo filter number */ + pCan->CTRL2 |= ((u32FilterNum - 1U) << FLEXCAN_CTRL2_RFFN_SHIFT)&FLEXCAN_CTRL2_RFFN_MASK; +} + + +/** + * \brief Check FLEXCAN FD enable + * + * \param pCan FLEXCAN instance value + * \return 1 is fd enabled, 0 is disabled + */ +LOCAL_INLINE uint8_t FLEXCAN_HWA_CheckFd(FLEXCAN_Type *const pCan) +{ + uint8_t u8RetVal; + uint32_t u32Value; + + /* get fd enable */ + u32Value = (pCan->MCR & FLEXCAN_MCR_FDEN_MASK) >> FLEXCAN_MCR_FDEN_SHIFT; + + u8RetVal = u32Value == 0U ? (uint8_t)0x0U : (uint8_t)0x1U; + + return u8RetVal; +} + + +/** + * \brief Set RXIMR for FLEXCAN + * + * \param pCan FLEXCAN instance value + * \param u32MbIndex Message Buffer Index + * \param u32Mask ID Mask + */ +LOCAL_INLINE void FLEXCAN_HWA_SetIndividualMask(FLEXCAN_Type *const pCan, uint32_t u32MbIndex, uint32_t u32Mask) +{ + pCan->RXIMR[u32MbIndex] = u32Mask; +} + +/** + * \brief Set global mask value + * + * \param pCan FLEXCAN instance value + * \param u32Mask mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetGlobalMask(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->RXMGMASK = u32Mask; +} + +/** + * \brief Set rx14 mask value + * + * \param pCan FLEXCAN instance value + * \param u32Mask mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetRx14Mask(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->RX14MASK = u32Mask; +} + +/** + * \brief Set rx15 mask value + * + * \param pCan FLEXCAN instance value + * \param u32Mask mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetRx15Mask(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->RX15MASK = u32Mask; +} + +/** + * \brief Set value to FLEXCAN RAM + * + * \param pCan FLEXCAN instance value + * \param u32RamIndex RAM index for FLEXCAN + * \param u32Value written value + */ +LOCAL_INLINE void FLEXCAN_HWA_MbRam(FLEXCAN_Type *const pCan, uint32_t u32RamIndex, uint32_t u32Value) +{ + pCan->RAM[u32RamIndex] = u32Value; +} + + +/** + * \brief Set ERFCR value + * + * \param pCan FLEXCAN instance value + * \param u32Value written value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetERFCR(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->ERFCR = u32Value; +} + +/** + * \brief Reset Enhanced FIFO Engine + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ERFSRResetEnhancedFifo(FLEXCAN_Type *const pCan) +{ + /* Write one to ERFSR[ERFCLR] to reset Enhanced Rx FIFO engine */ + pCan->ERFSR |= FLEXCAN_ERFSR_ERFCLR_MASK; +} + + +/** + * \brief Clear Enhanced Fifo Flag with mask + * + * \param pCan FLEXCAN instance value + * \param u32Shift flag shift + * \param u32Mask flag mask + * \return flag value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_ERFSRGetEnhancedFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32Shift, uint32_t u32Mask) +{ + /* Write one clear status */ + return ((pCan->ERFSR & u32Mask) >> u32Shift); +} + +/** + * \brief Clear Enhanced Fifo status + * + * \param pCan FLEXCAN instance value + * \param u32ClearMask clear mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_ERFSRClearEnhancedFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32ClearMask) +{ + /* Write one clear status */ + pCan->ERFSR |= u32ClearMask; +} + + + +/** + * \brief Set Enhance Fifo interrupt value + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetERFIERDataInterrupt(FLEXCAN_Type *const pCan) +{ + pCan->ERFIER |= FLEXCAN_ERFIER_ERFDAIE_MASK; +} + +/** + * \brief Set Enhanced Fifo filter value + * + * \param pCan FLEXCAN instance value + * \param u32FilterIndex Filter index + * \param u32Value filter value + */ +LOCAL_INLINE void FLEXCAN_HWA_EnhancedFifoFilter(FLEXCAN_Type *const pCan, uint32_t u32FilterIndex, uint32_t u32Value) +{ + pCan->ERFFEL[u32FilterIndex] = u32Value; +} + +/** @}*/ + +#endif diff --git a/Inc/HwA_fmc.h b/Inc/HwA_fmc.h new file mode 100644 index 0000000..bd9b913 --- /dev/null +++ b/Inc/HwA_fmc.h @@ -0,0 +1,402 @@ +/** + * @file HwA_cpm.h + * @author Flagchip + * @brief FC7xxx FMC register API + * @version 0.1.0 + * @date 2024-1-5 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-1-5 Flagchip120 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_FMC_H_ +#define HWA_INCLUDE_HWA_FMC_H_ +#include "device_header.h" +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + + + +/** + * @brief Read the FMC FAPC0 register value for all. + * + * @param pFMC FMC instance. + * @return FMC FAPC0 regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFAPC0Value(FMC_Type *pFMC) +{ + return pFMC->FAPC0; +} + +/** + * @brief Set FMC FAPC0 value, users should write the whole value to this register. + * + * @param pFMC FMC instance. + * @param u32Value the value which will be written to the FAPC0 register. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC0Value(FMC_Type *pFMC, uint32_t u32Value) +{ + pFMC->FAPC0 = u32Value; +} + +/** + * @brief Set FAPC0 data bus prefetch enable + * + * @param bEnable 0:Data prefetching is disabled. 1:Data prefetching is enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC0DataPrefechEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC0 = ((pFMC->FAPC0 & (~FMC_FAPC0_DBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC0_DBPEN_SHIFT)); +} + +/** + * @brief Set FAPC0 code bus prefetch enable + * + * @param bEnable 0:Code prefetching is disabled. 1:Code prefetching is disabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC0CodePrefechEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC0 = ((pFMC->FAPC0 & (~FMC_FAPC0_CBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC0_CBPEN_SHIFT)); +} + +/** + * @brief Set FAPC0 data bus read buffers enable + * + * @param bEnable 0:Read data buffers are disabled. 1:Read data buffers are enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC0DataBuffersEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC0 = ((pFMC->FAPC0 & (~FMC_FAPC0_DBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC0_DBBEN_SHIFT)); +} + +/** + * @brief Set FAPC0 code bus read buffers enable + * + * @param bEnable 0:Read code buffers are disabled. 1:Read code buffers are enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC0CodeBuffersEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC0 = ((pFMC->FAPC0 & (~FMC_FAPC0_CBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC0_CBBEN_SHIFT)); +} + +/** + * @brief Set FAPC1 data bus prefetch enable + * + * @param bEnable 0:Data prefetching is disabled. 1:Data prefetching is enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC1DataPrefechEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC1 = ((pFMC->FAPC1 & (~FMC_FAPC1_DBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC1_DBPEN_SHIFT)); +} + +/** + * @brief Set FAPC1 code bus prefetch enable + * + * @param bEnable 0:Code prefetching is disabled. 1:Code prefetching is disabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC1CodePrefechEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC1 = ((pFMC->FAPC1 & (~FMC_FAPC1_CBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC1_CBPEN_SHIFT)); +} + +/** + * @brief Set FAPC1 data bus read buffers enable + * + * @param bEnable 0:Read data buffers are disabled. 1:Read data buffers are enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC1DataBuffersEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC1 = ((pFMC->FAPC1 & (~FMC_FAPC1_DBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC1_DBBEN_SHIFT)); +} + +/** + * @brief Set FAPC1 code bus read buffers enable + * + * @param bEnable 0:Read code buffers are disabled. 1:Read code buffers are enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC1CodeBuffersEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC1 = ((pFMC->FAPC1 & (~FMC_FAPC1_CBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC1_CBBEN_SHIFT)); +} + +/** + * @brief Set FAPC2 data bus prefetch enable + * + * @param bEnable 0:Data prefetching is disabled. 1:Data prefetching is enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC2DataPrefechEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC2 = ((pFMC->FAPC2 & (~FMC_FAPC2_DBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC2_DBPEN_SHIFT)); +} + +/** + * @brief Set FAPC2 code bus prefetch enable + * + * @param bEnable 0:Code prefetching is disabled. 1:Code prefetching is disabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC2CodePrefechEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC2 = ((pFMC->FAPC2 & (~FMC_FAPC2_CBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC2_CBPEN_SHIFT)); +} + +/** + * @brief Set FAPC2 data bus read buffers enable + * + * @param bEnable 0:Read data buffers are disabled. 1:Read data buffers are enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC2DataBuffersEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC2 = ((pFMC->FAPC2 & (~FMC_FAPC2_DBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC2_DBBEN_SHIFT)); +} + +/** + * @brief Set FAPC2 code bus read buffers enable + * + * @param bEnable 0:Read code buffers are disabled. 1:Read code buffers are enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC2CodeBuffersEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC2 = ((pFMC->FAPC2 & (~FMC_FAPC2_CBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC2_CBBEN_SHIFT)); +} + +/** + * @brief Read the FMC FEEC register value for all. + * + * @param pFMC FMC instance. + * @return FMC FEEC regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFEECValue(FMC_Type *pFMC) +{ + return pFMC->FEEC; +} + +/** + * @brief Set FMC FEEC value, users should write the whole value to this register. + * + * @param pFMC FMC instance. + * @param u32Value the value which will be written to the FEEC register. + */ +LOCAL_INLINE void FMC_HWA_SetFEECValue(FMC_Type *pFMC, uint32_t u32Value) +{ + pFMC->FEEC = u32Value; +} + +/** + * @brief Read the FMC FEIPC register value for all. + * + * @param pFMC FMC instance. + * @return FMC FEIPC regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFEIPCValue(FMC_Type *pFMC) +{ + return pFMC->FEIPC; +} + +/** + * @brief Set the date error position 1 & position 2 + * + * @param pFMC FMC instance. + * @param u32Position1 Data error position 1 + * @param u32Position2 Data error position 2 + */ +LOCAL_INLINE void FMC_HWA_SetInjectPositon(FMC_Type *pFMC, uint32_t u32Position1, uint32_t u32Position2) +{ + pFMC->FEIPC = (pFMC->FEIPC & ~FMC_FEIPC_EDATA_POS1_MASK) | FMC_FEIPC_EDATA_POS1(u32Position1); + pFMC->FEIPC = (pFMC->FEIPC & ~FMC_FEIPC_EDATA_POS2_MASK) | FMC_FEIPC_EDATA_POS2(u32Position2); +} + +/** + * @brief Read the FMC FPESA_L register value for all. + * + * @param pFMC FMC instance. + * @return FMC FPESA_L regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFPESALValue(FMC_Type *pFMC) +{ + return pFMC->FPESA_L; +} + +/** + * @brief Set FMC FPESA_L value. + * + * @param pFMC FMC instance. + * @param u32Value the value which will be written to the FPESA_L register. + */ +LOCAL_INLINE void FMC_HWA_SetFPESALValue(FMC_Type *pFMC, uint32_t u32Value) +{ + pFMC->FPESA_L = u32Value; +} + +/** + * @brief Read the FMC FPESA_P register value for all. + * + * @param pFMC FMC instance. + * @return FMC FPESA_P regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFPESAPValue(FMC_Type *pFMC) +{ + return pFMC->FPESA_P; +} + +/** + * @brief Read the FMC FB_FPELCK register value for all. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @return FMC FB_FPELCK regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFBFPELCKValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + return pFMC->FB_FPELCK[u8SeqGroupIndex]; +} + +/** + * @brief Set FMC FB_FPELCK value. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @param u32Value the value which will be written to the FB_FPELCK register. + */ +LOCAL_INLINE void FMC_HWA_SetFBFPELCKValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex, uint32_t u32Value) +{ + pFMC->FB_FPELCK[u8SeqGroupIndex] = u32Value; +} + +/** + * @brief NVI program erase Lock + * + * @param bEnable 0:unlock. 1:locked. + */ +LOCAL_INLINE void FMC_HWA_SetNVRLocked(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FN_FPELCK = ((pFMC->FN_FPELCK & (~FMC_FN_FPELCK_FPELCK_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FN_FPELCK_FPELCK_SHIFT)); +} + +/** + * @brief Get NVR lock status. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return the NVR status(1:locked 0:unlocked). + */ +LOCAL_INLINE uint8_t FCSPI_HWA_GetNVRLockedStatus(FMC_Type *pFMC) +{ + return (uint8_t)(((pFMC->FN_FPELCK) & FMC_FN_FPELCK_FPELCK_MASK) >> FMC_FN_FPELCK_FPELCK_SHIFT); +} + +/** + * @brief Read the FMC FB_CPELCK register value for all. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @return FMC FB_CPELCK regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFBCPELCKValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + return pFMC->FB_CPELCK[u8SeqGroupIndex]; +} + +/** + * @brief Set FMC FB_CPELCK value. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @param u32Value the value which will be written to the FB_CPELCK register. + */ +LOCAL_INLINE void FMC_HWA_SetFBCPELCKValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex, uint32_t u32Value) +{ + pFMC->FB_CPELCK[u8SeqGroupIndex] = u32Value; +} + +/** + * @brief Set OTA register lock + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @param bEnable 0:OTA_CTRL can be written. 1:OTA_CTRL is locked. + */ +LOCAL_INLINE void FMC_HWA_SetOTALock(FMC_Type *pFMC, uint8_t u8SeqGroupIndex, bool bEnable) +{ + pFMC->OTA_CTRL[u8SeqGroupIndex] = ((pFMC->OTA_CTRL[u8SeqGroupIndex] & (~FMC_OTA_CTRL_OTA_LOCK_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_OTA_CTRL_OTA_LOCK_SHIFT)); +} + +/** + * @brief Set OTA active block + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @param bEnable 0: block0 is the currently active OTA region. 1: block1 is the currently active OTA region. + */ +LOCAL_INLINE void FMC_HWA_SetOTAActive(FMC_Type *pFMC, uint8_t u8SeqGroupIndex, bool bEnable) +{ + pFMC->OTA_CTRL[u8SeqGroupIndex] = ((pFMC->OTA_CTRL[u8SeqGroupIndex] & (~FMC_OTA_CTRL_OTA_ACTIVE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_OTA_CTRL_OTA_ACTIVE_SHIFT)); +} + +/** + * @brief Enable OTA + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE void FMC_HWA_SetOTAEnable(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + pFMC->OTA_CTRL[u8SeqGroupIndex] = ((pFMC->OTA_CTRL[u8SeqGroupIndex] & (~FMC_OTA_CTRL_OTA_EN_MASK)) | FMC_OTA_CTRL_OTA_EN(0xA)); +} + +/** + * @brief Disable OTA + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE void FMC_HWA_SetOTADisable(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + pFMC->OTA_CTRL[u8SeqGroupIndex] = ((pFMC->OTA_CTRL[u8SeqGroupIndex] & (~FMC_OTA_CTRL_OTA_EN_MASK)) | FMC_OTA_CTRL_OTA_EN(0x15)); +} + +/** + * @brief Read the FMC OTA_CTRL register value for all. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @return FMC OTA_CTRL regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetOTACtrlValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + return pFMC->OTA_CTRL[u8SeqGroupIndex]; +} + +/** + * @brief Read the FMC OTA_VER_LOC register value for all. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @return FMC OTA_VER_LOC regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetOTAVerLocValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + return pFMC->OTA_VER_LOC[u8SeqGroupIndex]; +} + +/** + * @brief Read the FMC OTA_ACT_VER register value for all. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @return FMC OTA_ACT_VER regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetOTAActVerValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + return pFMC->OTA_ACT_VER[u8SeqGroupIndex]; +} + + +/** @}*/ + +#endif /* HWA_INCLUDE_HWA_FMC_H_ */ diff --git a/Inc/HwA_fpu.h b/Inc/HwA_fpu.h new file mode 100644 index 0000000..f7fcb0d --- /dev/null +++ b/Inc/HwA_fpu.h @@ -0,0 +1,52 @@ +/** + * @file HwA_fpu.h + * @author Flagchip051 + * @brief FC4xxx FPU hardware access layer + * @version 0.1.0 + * @date 2024-01-11 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_FPU_H_ +#define _HWA_FPU_H_ + +#include "device_header.h" + +/* CPACR Bit Fields */ +#define FC7240_SCB_CPACR_CP10_MASK 0x300000u +#define FC7240_SCB_CPACR_CP10_SHIFT 20u +#define FC7240_SCB_CPACR_CP10_WIDTH 2u +#define FC7240_SCB_CPACR_CP10(x) (((uint32_t)(((uint32_t)(x))<CPACR |= (FC7240_SCB_CPACR_CP10(3) | FC7240_SCB_CPACR_CP11(3)); /* set CP10 and CP11 Full Access */ +} + +/** + * @brief disable fpu + * + */ +LOCAL_INLINE void FPU_HWA_Disable(void) +{ + SCB->CPACR &= ~((FC7240_SCB_CPACR_CP10(3) | FC7240_SCB_CPACR_CP11(3))); /* Access denied. Any attempted access generates a NOCP UsageFault */ +} + + +#endif /* HWA_INCLUDE_HWA_FPU_H_ */ diff --git a/Inc/HwA_freqm.h b/Inc/HwA_freqm.h new file mode 100644 index 0000000..de384e9 --- /dev/null +++ b/Inc/HwA_freqm.h @@ -0,0 +1,229 @@ +/** + * @file HwA_freqm.h + * @author Flagchip + * @brief FC7xxx freqm hardware access layer + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_FREQM_H_ +#define _HWA_FREQM_H_ + +#include "device_header.h" + +/** + * @brief Select the measured clock + * + */ +typedef enum +{ + MES_RSVD00 = 0U, + MES_SLOW_CLK = 1U, + MES_PLL1_FEEDBACK = 2U, + MES_PLL0_FEEDBACK = 3U, + MES_SCG_CLKOUT = 4U, + MES_RTC_CLK = 5U, + MES_AON_CLK = 6U, + MES_SIRC128K_CLK = 7U, + MES_RSVD01 = 8U, + MES_RSVD02 = 9U, + MES_FCPIT0_FUN_CLK = 10U, + MES_RSVD03 = 11U, + MES_RSVD04 = 12U, + MES_FCSPI0_FUN_CLK = 13U, + MES_FCSPI1_FUN_CLK = 14U, + MES_FCSPI2_FUN_CLK = 15U, + MES_RSVD05 = 16U, + MES_FCUART0_FUN_CLK = 17U, + MES_FCUART1_FUN_CLK = 18U, + MES_FCUART2_FUN_CLK = 19U, + MES_RSVD06 = 20U, + MES_TRGSEL1_OUT4 = 21U, + MES_FTU0_FUN_CLK = 22U, + MES_FTU1_FUN_CLK = 23U, + MES_RSVD07 = 24U, + MES_FTU2_FUN_CLK = 25U, + MES_FTU3_FUN_CLK = 26U, + MES_ADC0_FUN_CLK = 27U, + MES_RSVD08 = 28U, + MES_ADC1_FUN_CLK = 29U, + MES_RSVD09 = 30U, + MES_RSVD10 = 31U, + MES_RSVD11 = 32U, + MES_FOSC_DIVL = 33U, + MES_SIRC_DIVL = 34U, + MES_FIRC_DIVL = 35U, + MES_RSVD12 = 36U, + MES_PLL1_DIVL = 37U, + MES_PLL0_DIVL = 38U, + MES_RSVD13 = 39U, + MES_RSVD14 = 40U, + MES_FOSC_DIVM = 41U, + MES_SIRC_DIVM = 42U, + MES_FIRC_DIVM = 43U, + MES_RSVD15 = 44U, + MES_PLL1_DIVM = 45U, + MES_PLL0_DIVM = 46U, + MES_RSVD16 = 47U, + MES_RSVD17 = 48U, + MES_FOSC_DIVH = 49U, + MES_SIRC_DIVH = 50U, + MES_FIRC_DIVH = 51U, + MES_RSVD18 = 52U, + MES_PLL1_DIVH = 53U, + MES_PLL0_DIVH = 54U, + MES_RSVD19 = 55U, + MES_RSVD20 = 56U, + MES_SENT0_FUN_CLK = 57U, + MES_FLEXCAN0_FUN_CLK = 58U, + MES_FLEXCAN1_FUN_CLK = 59U, + MES_RSVD21 = 60U, + MES_MSC0_FUN_CLK = 61U, + MES_TPU_FUN_CLK = 62U, + MES_RSVD22 = 63U, +} FREQM_MesClkSelType; + +/** + * @brief Set the clock selection + * + * @param pFreqm the base address of the FREQM + * @param eClkSel the clock selection index + */ +LOCAL_INLINE void FREQM_HWA_MesClkSel(FREQM_Type *pFreqm,FREQM_MesClkSelType eClkSel) +{ + pFreqm->CTRL &= ~FREQM_CTRL_MES_CLK_SEL_MASK; + pFreqm->CTRL |= FREQM_CTRL_MES_CLK_SEL((uint32_t)eClkSel); +} + +/** + * @brief Set the clock selection + * + * @param pFreqm the base address of the FREQM + * @param u8PredivVal the measure clock prediv value + */ +LOCAL_INLINE void FREQM_HWA_MesClk_PreDiv(FREQM_Type *pFreqm,uint8_t u8PredivVal) +{ + pFreqm->CTRL &= ~FREQM_CTRL_MES_CLK_PREDIV_MASK; + pFreqm->CTRL |= FREQM_CTRL_MES_CLK_PREDIV(u8PredivVal); +} + +/** + * @brief Enable count event interrupt + * + * @param pFreqm the base address of the FREQM + */ +LOCAL_INLINE void FREQM_HWA_EnableCntEventInterrupt(FREQM_Type *pFreqm) +{ + pFreqm->CTRL |= FREQM_CTRL_CNT_EVENT_IE_MASK; +} + +/** + * @brief Disable count event interrupt + * + * @param pFreqm the base address of the FREQM + */ +LOCAL_INLINE void FREQM_HWA_DisableCntEventInterrupt(FREQM_Type *pFreqm) +{ + pFreqm->CTRL &= ~((uint32_t)FREQM_CTRL_CNT_EVENT_IE_MASK); +} + +/** + * @brief Set counting length of measure counter + * + * @param pFreqm the base address of the FREQM + * @param u32MesLen counting length of measure counter + */ +LOCAL_INLINE void FREQM_HWA_SetMesLength(FREQM_Type *pFreqm,uint32_t u32MesLen) +{ + pFreqm->MES_LENGTH = u32MesLen; +} + +/** + * @brief Set timeout value of reference counter + * + * @param pFreqm the base address of the FREQM + * @param u32RefTo timeout value of reference counter + */ +LOCAL_INLINE void FREQM_HWA_SetRefTimeout(FREQM_Type *pFreqm,uint32_t u32RefTo) +{ + pFreqm->REF_TIMEOUT = u32RefTo; +} + +/** + * @brief Set value of reference counter + * + * @param pFreqm the base address of the FREQM + * @param u32RefCnt value of reference counter + */ +LOCAL_INLINE void FREQM_HWA_SetRefCnt(FREQM_Type *pFreqm,uint32_t u32RefCnt) +{ + pFreqm->REF_CNT = u32RefCnt; +} + +/** + * @brief Clear counter event interrupt flag + * + * @param pFreqm the base address of the FREQM + */ +LOCAL_INLINE void FREQM_HWA_ClearInterruptFlag(FREQM_Type *pFreqm) +{ + pFreqm->CNT_STATUS |= FREQM_CNT_STATUS_CNT_EVENT_MASK; +} + +/** + * @brief Get counter event interrupt flag + * + * @param pFreqm the base address of the FREQM + * @param return false for disable, true for enable. + */ +LOCAL_INLINE bool FREQM_HWA_GetInterruptFlag(FREQM_Type *pFreqm) +{ + return ((pFreqm->CNT_STATUS & FREQM_CNT_STATUS_CNT_EVENT_MASK) == FREQM_CNT_STATUS_CNT_EVENT_MASK) ? true : false; +} + +/** + * @brief Get counter status + * + * @param pFreqm the base address of the FREQM + * @param return Counter status. + */ +LOCAL_INLINE uint32_t FREQM_HWA_GetCntStatus(FREQM_Type *pFreqm) +{ + uint32_t u32Mask = (FREQM_CNT_STATUS_MES_CNT_START_MASK|FREQM_CNT_STATUS_MES_CNT_STOP_MASK|FREQM_CNT_STATUS_REF_CNT_STOP_MASK); + return (pFreqm->CNT_STATUS & u32Mask); +} + +/** + * @brief Set value of measure counter + * + * @param pFreqm the base address of the FREQM + * @param u32MesCnt value of measure counter + */ +LOCAL_INLINE void FREQM_HWA_SetMesCnt(FREQM_Type *pFreqm,uint32_t u32MesCnt) +{ + pFreqm->MES_CNT = u32MesCnt; +} + +/** + * @brief Get saved reference counter value + * + * @param pFreqm the base address of the FREQM + * @param return saved reference counter value. + */ +LOCAL_INLINE uint32_t FREQM_HWA_GetRefCntSave(FREQM_Type *pFreqm) +{ + return pFreqm->REF_CNT_SAVE; +} + +#endif /* #ifndef _HWA_FREQM_H_ */ diff --git a/Inc/HwA_ftu.h b/Inc/HwA_ftu.h new file mode 100644 index 0000000..db782eb --- /dev/null +++ b/Inc/HwA_ftu.h @@ -0,0 +1,1924 @@ +/** + * @file HwA_ftu.h + * @author Flagchip070 + * @brief FC7xxx FTU hardware access layer + * @version 0.1.0 + * @date 2022-11-15 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-15 Flagchip070 N/A First version for FC7300 + ******************************************************************************** */ + +#ifndef _HWA_FTU_H_ +#define _HWA_FTU_H_ + +#include "device_header.h" +/********* Local typedef ************/ +/** + * @brief The definition of enable the deadtime of channel and channel+1 + * + */ +#define FTU_CHCTRL_DEADTIME_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 4U)) +/** + * @brief The definition of enable the complement of channel + * + */ +#define FTU_CHCTRL_COMPLEMENT_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 1U)) +/** + * @brief The definition of enable the synchronization for channel and channel+1 + * + */ +#define FTU_CHCTRL_SYNCEN_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 5U)) +/** + * @brief The definition of enable the Phase shift mode for channel and channel+1 + * + */ +#define FTU_CHCTRL_PHASE_CHANNEL(channel) (uint32_t)((uint32_t)1U << (((uint32_t)(channel) >> 1U) << 3U)) +/** + * @brief The definition of enable the Enhanced Phase shift mode for channel and channel+1 + * + */ +#define FTU_CHCTRL_EPHASE_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 7U)) +/** + * @brief The definition of enable the fault control in channel and channel+1 + * + */ +#define FTU_CHCTRL_FAULT_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 6U)) + +/********* Local typedef ************/ +/** + * @brief Select the FTU Debug Mode + * + */ +typedef enum +{ + FTU_DBG_COUNTER_STOP_CHN_WORKS = 0U, /*!< FTU counter stopped, channel works as function mode. */ + FTU_DBG_COUNTER_STOP_CHN_FORCE_SAFE = 1U, /*!< FTU counter stopped, channel output force to safe state. */ + FTU_DBG_COUNTER_STOP_CHN_FROZEN = 2U, /*!< FTU counter stopped, channel output is frozen. */ + FTU_DBG_COUNTER_WORKS_CHN_WORKS = 3U /*!< FTU counter works as function mode, channel works as function mode. */ +} FTU_DebugModeType; + +typedef enum +{ + FTU_CHANNEL_MODE_INPUT = 0u, + FTU_CHANNEL_MODE_OUTPUT_COMPARE = 1u, + FTU_CHANNEL_MODE_EDGE_ALIGN_PWM = 2u, + FTU_CHANNEL_MODE_DO_NOT_CARE = 3u, +} FTU_ChannelModeType; + +typedef enum +{ + FTU_CHANNEL_EDGE_NOT_USED = 0u, + FTU_CHANNEL_EDGE_RISING = 1u, + FTU_CHANNEL_EDGE_FALLING = 2u, + FTU_CHANNEL_EDGE_BOTH = 3u, + FTU_CHANNEL_OC_TOGGLE = 1u, + FTU_CHANNEL_OC_CLEAR = 2u, + FTU_CHANNEL_OC_SET = 3u, + FTU_CHANNEL_PWM_HIGH_TRUE = 2u, + FTU_CHANNEL_PWM_LOW_TRUE = 3u, +} FTU_ChannelEdgeLevelType; +/** + * @brief Select the prescaler of the FTU + * + */ +typedef enum +{ + FTU_DIV_1 = 0U, + FTU_DIV_2, + FTU_DIV_4, + FTU_DIV_8, + FTU_DIV_16, + FTU_DIV_32, + FTU_DIV_64, + FTU_DIV_128 +} FTU_PrescalerType; + +/** + * @brief Select the prescaler of the FTU filter + * + */ +typedef enum +{ + FTU_FLT_DIV_1 = 0U, + FTU_FLT_DIV_2, + FTU_FLT_DIV_3, + FTU_FLT_DIV_4, + FTU_FLT_DIV_5, + FTU_FLT_DIV_6, + FTU_FLT_DIV_7, + FTU_FLT_DIV_8, + FTU_FLT_DIV_9, + FTU_FLT_DIV_10, + FTU_FLT_DIV_11, + FTU_FLT_DIV_12, + FTU_FLT_DIV_13, + FTU_FLT_DIV_14, + FTU_FLT_DIV_15, + FTU_FLT_DIV_16 +} FTU_FilterPrescalerType; + +/** + * @brief selects the encoding mode used in the Quadrature Decoder mode + * + */ +typedef enum +{ + FTU_QUADMODE_PHA_PHB_ENCODING_MODE = 0U, /*!< Phase A and phase B encoding mode */ + FTU_QUADMODE_COUNT_DIR_ENCODING_MODE, /*!< Count and direction encoding mode */ +} FTU_QuadratureModeType; + +/** + * @brief FTU Counter Direction In Quadrature Decoder Mode + * + */ +typedef enum +{ + FTU_QUADIR_DECREMENT = 0U, /*!< FTU counter decrement */ + FTU_QUADIR_INCREMENT, /*!< FTU counter increment */ +} FTU_QuadratureDirectionType; + +/** + * @brief Timer Overflow Direction In Quadrature Decoder Mode + * + */ +typedef enum +{ + FTU_TOFDIR_TOF_SET_ON_BOTTOM = 0U, /*!< TOF bit was set on the bottom of counting */ + FTU_TOFDIR_TOF_SET_ON_TOP, /*!< TOF bit was set on the top of counting */ +}FTU_TimerOverflowDirectionType; + +/** + * @brief register bit status + * + */ +typedef enum +{ + FTU_BIT_LOW = 0U, + FTU_BIT_HIGH +} FTU_BitStatusType; + +/** + * @brief Ftu module clock source + * + */ +typedef enum +{ + FTU_MODULE_NO_CLK = 0U, /*!< No clock selected */ + FTU_MODULE_INTERNAL_CLK = 1U, /*!< FTU input clock */ + FTU_MODULE_EXTERNAL_CLK = 3U, /*!< External pin input clock */ +} FTU_ModuleClkSrcType; + +/** + * @brief Disable channel match trigger/interrupt when count-up/down in CPWM/QUAD mode + * + */ +typedef enum +{ + FTU_DISABLE_TRIG_INTR_NONE = 0U, /*!< No effect */ + FTU_DISABLE_TRIG_INTR_CNT_DOWN = 1U, /*!< Disable trigger/interrupt when count-down */ + FTU_DISABLE_TRIG_INTR_CNT_UP = 2U, /*!< Disable trigger/interrupt when count-up */ + FTU_DISABLE_TRIG_INTR_CNT_UP_DOWN = 3U, /*!< Disable trigger/interrupt when count-up/down */ +}FTU_UpDownDisableType; + +/** + * @brief hardware trig(n) mode + * + */ +typedef enum +{ + FTU_CLEARS_TRIG_WHEN_DETECTED = 0x0U, /*!< FTU clears the TRIG(n) bit when the hardware trigger j is detected, where n = 0, 1,2. */ + FTU_NOT_CLEARS_TRIG_WHEN_DETECTED = 0x01U /*!< FTU does not clear the TRIG(n) bit when the hardware trigger j is detected, where n = 0, 1,2. */ +} FTU_TrigModeType; + +/** + * @brief fault mode enumeration + * + */ +typedef enum +{ + FTU_FAULT_MODE_DISABLED = 0x00U, /*!< Fault control is disabled for all channels */ + FTU_FAULT_MODE_EVEN_CHANNEL = 0x01U, /*!< Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing */ + FTU_FAULT_MODE_CHANNEL_ALL = 0x02U, /*!< Fault control is enabled for all channels, and the selected mode is the manual fault clearing */ + FTU_FAULT_MODE_AUTO = 0x03U /*!< Fault control is enabled for all channels, and the selected mode is the automatic fault clearing */ +} FTU_FaultModeType; + +/** + * @brief external clock enumeration + * + */ +typedef enum +{ + FTU_TCLK0_USED = 0U, /*!< FTU_TCLK0 pin as FTU external clock */ + FTU_TCLK1_USED = 1U, /*!< FTU_TCLK1 pin as FTU external clock */ + FTU_TCLK2_USED = 2U, /*!< FTU_TCLK2 pin as FTU external clock */ + FTU_NO_CLK_USED = 3U, /*!< No clock input */ +} FTU_TclkSelType; + +/** + * @brief Deadtime Prescaler Value + * + */ +typedef enum +{ + FTU_DEADTIME_PRESCALER_DIV_1 = 0U, /*!< Divide the FTU input clock by 1 */ + FTU_DEADTIME_PRESCALER_DIV_4 = 2U, /*!< Divide the FTU input clock by 4 */ + FTU_DEADTIME_PRESCALER_DIV_16 = 3U, /*!< Divide the FTU input clock by 16 */ +} FTU_DeadTimePrescalerType; + +/** + * @brief Trigger output control + * + */ +typedef enum +{ + FTU_TRIG_OUTPUT_AS_CHANNEL_MODE = 0U, /*!< channel outputs will be controlled by channel mode */ + FTU_TRIG_OUTPUT_AS_TRIGGER = 1U, /*!< If a match in the channel occurs, channel output will be a trigger */ +}FTU_TrigOutputModeType; + +/** + * @brief Fault disable channel output delay value selection + * + */ +typedef enum +{ + FTU_FAULT_DISABLE_DELAY_NO_DELAY = 0u, /*!< Select no delay */ + FTU_FAULT_DISABLE_DELAY_VALUE_0 = 1u, /*!< Select delay value 0 */ + FTU_FAULT_DISABLE_DELAY_VALUE_1 = 2u /*!< Select delay value 1 */ +}FTU_FaultDisableDelayType; + +/** + * @brief Input Capture Measurement Mode + * + */ +typedef enum +{ + FTU_MEASURE_MODE_OFF = 0u, /*!< Do not use measurement mode */ + FTU_MEASURE_MODE_DUTY_CYCLE = 1u, /*!< Duty-cycle Measure */ + FTU_MEASURE_MODE_PERIOD = 2u, /*!< Period Measure */ + FTU_MEASURE_EDGE_NUMBER = 3u, /*!< Edge Number Measure */ + FTU_MEASURE_EXPECT_EDGE_NUMBER = 4u, /*!< Expect Edge Number Measure */ + FTU_MEASURE_ICENM_WIND_WRITE = 7u, /*!< Configure ICENM Window */ +}FTU_MeasurementModeType; + +/********* Local inline function ************/ + +/** + * @brief Clear FTU module registers + * + * @param pFtu FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearModuleRegister(FTU_Type *pFtu) +{ + uint32_t u32Loop; + pFtu->SC &= 0U; + pFtu->CNT = 0U; + pFtu->MOD = 0U; + for(u32Loop = 0u; u32Loop < FTU_CHANNEL_CONTROLS_COUNT; u32Loop++) + { + pFtu->CONTROLS[u32Loop].CSCn = (uint32_t)0u; + pFtu->CONTROLS[u32Loop].CVn = (uint32_t)0u; + } + pFtu->CNTIN = 0U; + pFtu->STATUS |= FTU_STATUS_CHNF_MASK; + pFtu->MODE = 0x00000004U; + pFtu->SYNC = 0U; + pFtu->OUTINIT = 0U; + pFtu->OUTMASK = 0U; + pFtu->CHCTRL = 0U; + pFtu->DEADTIME = 0U; + pFtu->TRIGCONF = 0U; + pFtu->POL = 0U; + pFtu->FMS &= 0U; + pFtu->FILTER = 0U; + pFtu->FLTCTRL = 0U; + pFtu->QDCTRL = 0U; + pFtu->CONF = FTU_CONF_DBG(3u); + pFtu->FLTPOL = 0U; + pFtu->SYNCONF = 0U; + pFtu->INVCTRL = 0U; + pFtu->SWOCTRL = 0U; + pFtu->PWMLOAD = 0U; + pFtu->PAIRDEADTIME0 = 0U; + pFtu->PAIRDEADTIME1 = 0U; + pFtu->PAIRDEADTIME2 = 0U; + pFtu->PAIRDEADTIME3 = 0U; +} + +/** + * @brief Disable Global Time Base Enable + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableGlobalTimeBase(FTU_Type *pFtu) +{ + pFtu->CONF &= ~FTU_CONF_GTBEEN_MASK; +} + +/** + * @brief Enable Global Time Base Enable + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableGlobalTimeBase(FTU_Type *pFtu) +{ + pFtu->CONF |= FTU_CONF_GTBEEN_MASK; +} + +/** + * @brief Set the LDOK flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetPwmLoadEnable(FTU_Type *pFtu) +{ + pFtu->PWMLOAD |= FTU_PWMLOAD_LDOK_MASK; +} + +/** + * @brief Clear the LDOK flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearPwmLoadEnable(FTU_Type *pFtu) +{ + pFtu->PWMLOAD &= ~FTU_PWMLOAD_LDOK_MASK; +} + +/** + * @brief Set the CNTINC flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetCntinSync(FTU_Type *pFtu) +{ + pFtu->SYNCONF |= FTU_SYNCONF_CNTINC_MASK; +} + +/** + * @brief Clear the CNTINC flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearCntinSync(FTU_Type *pFtu) +{ + pFtu->SYNCONF &= ~FTU_SYNCONF_CNTINC_MASK; +} + +/** + * @brief Set the SYNCEN flag + * + * @param pFtu the base address of the FTU instance + * @param u32Index the index of SYNCEN + */ +LOCAL_INLINE void FTU_HWA_SetChannelSyncEnable(FTU_Type *pFtu, uint32_t u32Index) +{ + const uint32_t u32MaskTab[4] = {FTU_CHCTRL_SYNCEN0_MASK, FTU_CHCTRL_SYNCEN1_MASK, + FTU_CHCTRL_SYNCEN2_MASK, FTU_CHCTRL_SYNCEN3_MASK}; + pFtu->CHCTRL |= u32MaskTab[u32Index]; +} + +/** + * @brief Clear the SYNCEN flag + * + * @param pFtu the base address of the FTU instance + * @param u32Index the index of SYNCEN + */ +LOCAL_INLINE void FTU_HWA_ClearChannelSyncEnable(FTU_Type *pFtu, uint32_t u32Index) +{ + const uint32_t u32MaskTab[4] = {FTU_CHCTRL_SYNCEN0_MASK, FTU_CHCTRL_SYNCEN1_MASK, + FTU_CHCTRL_SYNCEN2_MASK, FTU_CHCTRL_SYNCEN3_MASK}; + pFtu->CHCTRL &= ~u32MaskTab[u32Index]; +} + +/** + * @brief Set the PWMSYNC flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetPwmSyncMode(FTU_Type *pFtu) +{ + pFtu->MODE |= FTU_MODE_PWMSYNC_MASK; +} + +/** + * @brief Clear the PWMSYNC flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearPwmSyncMode(FTU_Type *pFtu) +{ + pFtu->MODE &= ~FTU_MODE_PWMSYNC_MASK; +} + +/** + * @brief Set the REINIT flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetReinitBySync(FTU_Type *pFtu) +{ + pFtu->SYNC |= FTU_SYNC_REINIT_MASK; +} + +/** + * @brief Clear the REINIT flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearReinitBySync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~FTU_SYNC_REINIT_MASK; +} + +/** + * @brief Set the CNTMAX flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableMaxLoadPoint(FTU_Type *pFtu) +{ + pFtu->SYNC |= FTU_SYNC_CNTMAX_MASK; +} + +/** + * @brief Clear the CNTMAX flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableMaxLoadPoint(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~FTU_SYNC_CNTMAX_MASK; +} + +/** + * @brief Set the CNTMIN flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableMinLoadPoint(FTU_Type *pFtu) +{ + pFtu->SYNC |= FTU_SYNC_CNTMIN_MASK; +} + +/** + * @brief Clear the CNTMIN flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableMinLoadPoint(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~FTU_SYNC_CNTMIN_MASK; +} + +/** + * @brief Set the CHNSEL flag of a channel + * + * @param pFtu the base address of the FTU instance + * @param u32Channel channel index + */ +LOCAL_INLINE void FTU_HWA_EnableChannelMatchReload(FTU_Type *pFtu, uint32_t u32Channel) +{ + pFtu->PWMLOAD |= FTU_PWMLOAD_CHNSEL((uint32_t)1u << u32Channel); +} + +/** + * @brief Clear the CHNSEL flag of a channel + * + * @param pFtu the base address of the FTU instance + * @param u32Channel channel index + */ +LOCAL_INLINE void FTU_HWA_DisableChannelMatchReload(FTU_Type *pFtu, uint32_t u32Channel) +{ + pFtu->PWMLOAD &= ~FTU_PWMLOAD_CHNSEL((uint32_t)1u << u32Channel); +} + +/** + * @brief configure the frequency of the reload opportunities + * + * @param pFtu the base address of the FTU instance + * @param u8Freq the number of enabled reload opportunities that should happen until an + * enabled reload opportunity becomes a reload point + */ +LOCAL_INLINE void FTU_HWA_ConfigFreqOfReloadOp(FTU_Type *pFtu, uint8_t u8Freq) +{ + pFtu->CONF &= ~FTU_CONF_LDFQ_MASK; + pFtu->CONF |= FTU_CONF_LDFQ(u8Freq); +} + +/** + * @brief Selects the FTU behavior in Debug mode + * + * @param pFtu the base address of the FTU instance + * @param u32Mode debug mode + */ +LOCAL_INLINE void FTU_HWA_ConfigDebugMode(FTU_Type *pFtu, uint32_t u32Mode) +{ + pFtu->CONF &= ~FTU_CONF_DBG_MASK; + pFtu->CONF |= FTU_CONF_DBG(u32Mode); +} + +/** + * @brief Disable channel match trigger/interrupt when count-up/down in CPWM/QUAD mode + * + * @param pFtu the base address of the FTU instance + * @param eUpdownDisable up-down disable mode + */ +LOCAL_INLINE void FTU_HWA_ConfigUpDownDisable(FTU_Type *pFtu, FTU_UpDownDisableType eUpdownDisable) +{ + pFtu->SC &= ~FTU_SC_UPDOWN_DIS_MASK; + pFtu->SC |= FTU_SC_UPDOWN_DIS((uint32_t)eUpdownDisable); +} + +/** + * @brief Enable reload point interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableReloadPointInterrupt(FTU_Type *pFtu) +{ + pFtu->SC |= FTU_SC_RIE_MASK; +} + +/** + * @brief Disable reload point interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableReloadPointInterrupt(FTU_Type *pFtu) +{ + pFtu->SC &= ~((uint32_t)FTU_SC_RIE_MASK); +} + +/** + * @brief Enable software output control of channels + * + * @param pFtu the base address of the FTU instance + * @param u32Mask channel mask + */ +LOCAL_INLINE void FTU_HWA_EnalbeSWOControl(FTU_Type *pFtu, uint32_t u32Mask) +{ + pFtu->SWOCTRL |= FTU_SWOCTRL_CHNOC(u32Mask); +} + +/** + * @brief Disable software output control of channels + * + * @param pFtu the base address of the FTU instance + * @param u32Mask channel mask + */ +LOCAL_INLINE void FTU_HWA_DisalbeSWOControl(FTU_Type *pFtu, uint32_t u32Mask) +{ + pFtu->SWOCTRL &= ~FTU_SWOCTRL_CHNOC(u32Mask); +} + +/** + * @brief Set the software output control value + * + * @param pFtu the base address of the FTU instance + * @param u32Mask channel mask + */ +LOCAL_INLINE void FTU_HWA_SetSWOValue(FTU_Type *pFtu, uint32_t u32Mask) +{ + pFtu->SWOCTRL |= FTU_SWOCTRL_CHNOCV(u32Mask); +} + +/** + * @brief Clear the software output control value + * + * @param pFtu the base address of the FTU instance + * @param u32Mask channel mask + */ +LOCAL_INLINE void FTU_HWA_ClearSWOValue(FTU_Type *pFtu, uint32_t u32Mask) +{ + pFtu->SWOCTRL &= ~FTU_SWOCTRL_CHNOCV(u32Mask); +} + +/** + * @brief Configure the pair deadtime prescaler value + * + * @param pFtu the base address of the FTU instance + * @param u32Channel channel index + * @param ePrescaler prescaler value + */ +LOCAL_INLINE void FTU_HWA_ConfigPairDeadtimePrescaler(FTU_Type *pFtu, uint32_t u32Channel, FTU_DeadTimePrescalerType ePrescaler) +{ + uint32_t u32RegValue; + volatile uint32_t *pPairDeadtime = &pFtu->PAIRDEADTIME0; + u32Channel = u32Channel >> 1u; + u32RegValue = pPairDeadtime[(u32Channel << 1u)]; + u32RegValue &= ~(uint32_t)FTU_DEADTIME_DTPS_MASK; + u32RegValue |= FTU_DEADTIME_DTPS(ePrescaler); + *pPairDeadtime = u32RegValue; +} + +/** + * @brief Configure the deadtime value + * + * @param pFtu the base address of the FTU instance + * @param u32Channel channel index + * @param u32Value deadtime value + */ +LOCAL_INLINE void FTU_HWA_ConfigPairDeadtimeValue(FTU_Type *pFtu, uint32_t u32Channel, uint32_t u32Value) +{ + uint32_t u32RegValue; + volatile uint32_t *pPairDeadtime = &pFtu->PAIRDEADTIME0; + u32Channel = u32Channel >> 1u; + u32RegValue = pPairDeadtime[(u32Channel << 1u)]; + u32RegValue &= ~(uint32_t)FTU_DEADTIME_DTVAL_MASK; + u32RegValue &= ~(uint32_t)FTU_DEADTIME_DTVALEX_MASK; + u32RegValue |= FTU_DEADTIME_DTVAL(u32Value & 0x3Fu); + u32RegValue |= FTU_DEADTIME_DTVALEX(u32Value >> 6); + *pPairDeadtime = u32RegValue; +} + +/** + * @brief Configure the deadtime prescaler value + * + * @param pFtu the base address of the FTU instance + * @param ePrescaler prescaler value + */ +LOCAL_INLINE void FTU_HWA_ConfigDeadtimePrescaler(FTU_Type *pFtu, FTU_DeadTimePrescalerType ePrescaler) +{ + uint32_t u32RegValue = pFtu->DEADTIME; + u32RegValue &= ~(uint32_t)FTU_DEADTIME_DTPS_MASK; + u32RegValue |= FTU_DEADTIME_DTPS(ePrescaler); + pFtu->DEADTIME = u32RegValue; +} + +/** + * @brief Configure the deadtime value + * + * @param pFtu the base address of the FTU instance + * @param u32Value deadtime value + */ +LOCAL_INLINE void FTU_HWA_ConfigDeadtimeValue(FTU_Type *pFtu, uint32_t u32Value) +{ + uint32_t u32RegValue = pFtu->DEADTIME; + u32RegValue &= ~(uint32_t)FTU_DEADTIME_DTVAL_MASK; + u32RegValue &= ~(uint32_t)FTU_DEADTIME_DTVALEX_MASK; + u32RegValue |= FTU_DEADTIME_DTVAL(u32Value & 0x3Fu); + u32RegValue |= FTU_DEADTIME_DTVALEX(u32Value >> 6); + pFtu->DEADTIME = u32RegValue; +} + +/** + * @brief Get the counter value of the selected FTU module + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE uint32_t FTU_HWA_GetCounterValue(FTU_Type *pFtu) +{ + return (uint32_t)pFtu->CNT; +} + +/** + * @brief Clear FTU counter + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue CNT register value + */ +LOCAL_INLINE void FTU_HWA_ClearModuleCounter(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->CNT = u32RegValue; +} + +/** + * @brief Configure FTU channel + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + * @param u32RegValue the value to write to CSC register + */ +LOCAL_INLINE void FTU_HWA_ConfigChannel(FTU_Type *pFtu, uint8_t u8Channel, uint32_t u32RegValue) +{ + pFtu->CONTROLS[u8Channel].CSCn = u32RegValue; +} + +/** + * @brief Get FTU channel value + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + * @return CVn register value + */ +LOCAL_INLINE uint32_t FTU_HWA_GetChannelValue(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (pFtu->CONTROLS[u8Channel].CVn); +} + +/** + * @brief Set FTU channel value + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + * @param u32RegValue CVn register value + */ +LOCAL_INLINE void FTU_HWA_SetChannelValue(FTU_Type *pFtu, uint8_t u8Channel, uint32_t u32RegValue) +{ + pFtu->CONTROLS[u8Channel].CVn = u32RegValue; +} + +/** + * @brief Set FTU counter compare val + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue MOD register value + */ +LOCAL_INLINE void FTU_HWA_SetModuleCompareValue(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->MOD = u32RegValue & FTU_MOD_MASK; +} + +/** + * @brief Set FTU counter initial value + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue CNTIN register value + */ +LOCAL_INLINE void FTU_HWA_SetCounterInitialValue(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->CNTIN = u32RegValue & FTU_CNTIN_INIT_MASK; +} + +/** + * @brief Configure FTU mode + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue MODE register value + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleMode(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->MODE = u32RegValue; +} + +/** + * @brief Configure FTU deadtime + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue DEADTIME register value + */ +LOCAL_INLINE void FTU_HWA_ConfigDeadtime(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->DEADTIME = u32RegValue; +} + +/** + * @brief Configure input capture filter + * + * @param pFtu the base address of the FTU instance + * @param u32Channel Channel of FTU instance + * @param u32FilterValue Filter value + */ +LOCAL_INLINE void FTU_HWA_ConfigInputCaptureFilter(FTU_Type *pFtu, uint32_t u32Channel, uint32_t u32FilterValue) +{ + pFtu->FILTER &= ~((uint32_t)0xFu << (u32Channel << 2)); + pFtu->FILTER |= u32FilterValue << (u32Channel << 2); +} + +/** + * @brief Enable FTU module fault + * + * @param pFtu the base address of the FTU instance + * @param u8InputMask Fault input mask, 0-3 bit indicate fault 0-3 + */ +LOCAL_INLINE void FTU_HWA_EnableModuleFault(FTU_Type *pFtu, uint8_t u8InputMask) +{ + pFtu->FLTCTRL |= ((uint32_t)u8InputMask & (uint32_t)0xFU); +} + +/** + * @brief get the fault input enable status + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE uint32_t FTU_HWA_GetFaultEnable(FTU_Type *pFtu) +{ + uint32_t u32RegValue = pFtu->FLTCTRL; + return u32RegValue & (uint32_t)0xFU; +} + +/** + * @brief Disable FTU module fault + * + * @param pFtu the base address of the FTU instance + * @param u8Input Fault input number, 0-3 bit indicate fault 0-3 + */ +LOCAL_INLINE void FTU_HWA_DisableModuleFault(FTU_Type *pFtu, uint8_t u8Input) +{ + pFtu->FLTCTRL &= ~((uint32_t)u8Input & (uint32_t)0xFU); +} + +/** + * @brief Enable FTU module fault glitch filter + * + * @param pFtu the base address of the FTU instance + * @param u8Input Fault input number, 0-3 bit indicate fault 0-3 + */ +LOCAL_INLINE void FTU_HWA_EnableModuleFaultGlitchFilter(FTU_Type *pFtu, uint8_t u8Input) +{ + pFtu->FLTCTRL |= (((uint32_t)u8Input & (uint32_t)0xFU) << 4U); +} + +/** + * @brief Disable FTU module fault glitch filter + * + * @param pFtu the base address of the FTU instance + * @param u8Input Fault input number, 0-3 bit indicate fault 0-3 + */ +LOCAL_INLINE void FTU_HWA_DisableModuleFaultGlitchFilter(FTU_Type *pFtu, uint8_t u8Input) +{ + pFtu->FLTCTRL &= ~(((uint32_t)u8Input & (uint32_t)0xFU) << FTU_FLTCTRL_FLT0GFEN_SHIFT); +} + +/** + * @brief Set FTU module fault filter value + * + * @param pFtu the base address of the FTU instance + * @param u8Value FTU fault filter value + */ +LOCAL_INLINE void FTU_HWA_SetModuleFaultFilterValue(FTU_Type *pFtu, uint8_t u8Value) +{ + uint32_t u32TempRegValue = pFtu->FLTCTRL; + pFtu->FLTCTRL = (u32TempRegValue & ~(uint32_t)FTU_FLTCTRL_FFVAL_MASK) | FTU_FLTCTRL_FFVAL(u8Value); +} + +/** + * @brief Set FTU module fault disable channel output delay value0 + * + * @param pFtu the base address of the FTU instance + * @param u8Value FTU fault delay value0 + */ +LOCAL_INLINE void FTU_HWA_SetFaultDelay0(FTU_Type *pFtu, uint8_t u8Value) +{ + pFtu->FLTCTRL &= ~(uint32_t)FTU_FLTCTRL_FDLYV0_MASK; + pFtu->FLTCTRL |= FTU_FLTCTRL_FDLYV0(u8Value); +} + +/** + * @brief Set FTU module fault disable channel output delay value + * + * @param pFtu the base address of the FTU instance + * @param u8Value FTU fault delay value1 + */ +LOCAL_INLINE void FTU_HWA_SetFaultDelay1(FTU_Type *pFtu, uint8_t u8Value) +{ + pFtu->FLTPOL &= ~(uint32_t)FTU_FLTPOL_FDLYV1_MASK; + pFtu->FLTPOL |= FTU_FLTPOL_FDLYV1(u8Value); +} + +/** + * @brief Configure FTU module fault polarity + * + * @param pFtu the base address of the FTU instance + * @param u32FaultIndex index of the fault + * @param u8InputPol the polarity of the fault input + */ +LOCAL_INLINE void FTU_HWA_ConfigFaultPolarity(FTU_Type *pFtu, uint32_t u32FaultIndex, uint8_t u8InputPol) +{ + uint32_t u32RegValue = pFtu->FLTPOL; + u32RegValue &= ~(FTU_FLTPOL_FLT0POL_MASK << u32FaultIndex); + u32RegValue |= FTU_FLTPOL_FLT0POL(u8InputPol) << u32FaultIndex; + pFtu->FLTPOL = u32RegValue; +} + +/** + * @brief Set FTU module prescale + * + * @param pFtu the base address of the FTU instance + * @param ePs FTU clock prescaler enumeration + */ +LOCAL_INLINE void FTU_HWA_SetModulePrescale(FTU_Type *pFtu, FTU_PrescalerType ePs) +{ + uint32_t u32RegValue = pFtu->SC; + pFtu->SC = (u32RegValue & ~(uint32_t)FTU_SC_PS_MASK) | FTU_SC_PS(ePs); +} + +/** + * @brief Read FTU module overflow flag + * + * @param pFtu the base address of the FTU instance + * @return FTU overflow flag + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadModuleOverflowFlag(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_TOF_MASK) >> FTU_SC_TOF_SHIFT); +} + +/** + * @brief Read FTU module overflow interrupt enable + * + * @param pFtu the base address of the FTU instance + * @return FTU overflow interrupt enable + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadModuleOverflowIntrEnable(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_TOIE_MASK) >> FTU_SC_TOIE_SHIFT); +} + +/** + * @brief Read FTU module reload flag + * + * @param pFtu the base address of the FTU instance + * @return FTU reload flag + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadModuleReloadFlag(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_RF_MASK) >> FTU_SC_RF_SHIFT); +} + +/** + * @brief Read FTU module reload interrupt enable + * + * @param pFtu the base address of the FTU instance + * @return reload interrupt enable + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadReloadIntrEnable(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_RIE_MASK) >> FTU_SC_RIE_SHIFT); +} + +/** + * @brief Read FTU channel interrupt flag + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @return FTU channel interrupt flag + */ +LOCAL_INLINE bool FTU_HWA_ReadChannelInterruptFlag(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (0u != (pFtu->CONTROLS[u8Channel].CSCn & (uint32_t)FTU_CSC_CHF_MASK)); +} + +/** + * @brief Configure the channel output mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param eMode output mode of the selected channel. + */ +LOCAL_INLINE void FTU_HWA_ConfigTrigOutputMode(FTU_Type *pFtu, uint8_t u8Channel, FTU_TrigOutputModeType eMode) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_TRIGMODE_MASK; + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_TRIGMODE(eMode); +} + +/** + * @brief Select fault disable channel output delay value + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param eSelection Fault disable channel output delay value selection. + */ +LOCAL_INLINE void FTU_HWA_SelectFaultDelay(FTU_Type *pFtu, uint8_t u8Channel, FTU_FaultDisableDelayType eSelection) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_FDLYSEL_MASK; + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_FDLYSEL(eSelection); +} + +/** + * @brief Read FTU channel interrupt enable flag + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @return FTU channel interrupt flag + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadChannelInterruptEnableFlag(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (uint8_t)((pFtu->CONTROLS[u8Channel].CSCn & (uint32_t)FTU_CSC_CHIE_MASK) >> FTU_CSC_CHIE_SHIFT); +} + +/** + * @brief Read FTU module fault(n) flag + * + * @param pFtu the base address of the FTU instance + * @return FTU fault flag + */ +LOCAL_INLINE uint32_t FTU_HWA_ReadModuleFaultFlag(FTU_Type *pFtu) +{ + return (uint32_t)(pFtu->FMS & (uint32_t)0xFU); +} + +/** + * @brief Read FTU module fault interrupt enable + * + * @param pFtu the base address of the FTU instance + * @return FTU fault interrupt enable + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadFaultIntrEnable(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->MODE & (uint32_t)FTU_MODE_FAULTIE_MASK) >> FTU_MODE_FAULTIE_SHIFT); +} + +/** + * @brief Read FTU module fault detection flag + * + * @param pFtu the base address of the FTU instance + * @return FTU fault detection flag + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadModuleFaultDetectionFlag(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->FMS & (uint32_t)FTU_FMS_FAULTF_MASK) >> FTU_FMS_FAULTF_SHIFT); +} + +/** + * @brief Enable FTU module channel(n) output + * + * @param pFtu the base address of the FTU instance + * @param u8ChannelMask 0-7 bit indicate 0-7 channel + */ +LOCAL_INLINE void FTU_HWA_EnableChannelsOutput(FTU_Type *pFtu, uint8_t u8ChannelMask) +{ + pFtu->SC |= (uint32_t)FTU_SC_CHNOUTEN(u8ChannelMask); +} + +/** + * @brief Get cpwm mode of the FTU module + * + * @param pFtu the base address of the FTU instance + * @return cpwm mode bit value of the FTU module + */ +LOCAL_INLINE uint8_t FTU_HWA_GetModuleCpwmMode(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_CPWMS_MASK) >> FTU_SC_CPWMS_SHIFT); +} + +/** + * @brief Enable FTU module cpwm mode + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableModuleCpwmMode(FTU_Type *pFtu) +{ + pFtu->SC |= (uint32_t)FTU_SC_CPWMS_MASK; +} + +/** + * @brief Disable FTU module cpwm mode + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableModuleCpwmMode(FTU_Type *pFtu) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_CPWMS_MASK; +} + +/** + * @brief Set FTU module filter prescale + * + * @param pFtu the base address of the FTU instance + * @param eFilterPs FTU clock filter prescaler enumeration + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleFilterPrescale(FTU_Type *pFtu, FTU_FilterPrescalerType eFilterPs) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_FLTPS_MASK; + pFtu->SC |= FTU_SC_FLTPS(eFilterPs); +} + +/** + * @brief Selects the external clock as the FTU function clock + * + * @param pFtu the base address of the FTU instance + * @param eTclk FTU external clock enumeration + */ +LOCAL_INLINE void FTU_HWA_ConfigExternalClkSrc(FTU_Type *pFtu, FTU_TclkSelType eTclk) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_TCKSEL_MASK; + pFtu->SC |= FTU_SC_TCKSEL(eTclk); +} + +LOCAL_INLINE void FTU_HWA_ConfigChannelMode(FTU_Type *pFtu, uint8_t u8Channel, FTU_ChannelModeType eMode) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)(FTU_CSC_MSB_MASK | FTU_CSC_MSA_MASK); + pFtu->CONTROLS[u8Channel].CSCn |= (eMode << FTU_CSC_MSA_SHIFT) & (uint32_t)(FTU_CSC_MSB_MASK | FTU_CSC_MSA_MASK); +} + +LOCAL_INLINE void FTU_HWA_ConfigChannelEdgeLevel(FTU_Type *pFtu, uint8_t u8Channel, FTU_ChannelEdgeLevelType eEdgeLevel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)(FTU_CSC_ELSB_MASK | FTU_CSC_ELSA_MASK); + pFtu->CONTROLS[u8Channel].CSCn |= (eEdgeLevel << FTU_CSC_ELSA_SHIFT) & (uint32_t)(FTU_CSC_ELSB_MASK | FTU_CSC_ELSA_MASK); +} + +LOCAL_INLINE uint8_t FTU_HWA_GetEdgeNumberCount(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (uint8_t)((pFtu->CONTROLS[u8Channel].CSCn & FTU_CSC_ICM_ICEXP_NUM_ICM_ECNT_MASK) >> FTU_CSC_ICM_ICEXP_NUM_ICM_ECNT_SHIFT); +} + +LOCAL_INLINE void FTU_HWA_ConfigEdgeNumber(FTU_Type *pFtu, uint8_t u8Channel, uint8_t u8EdgeNumber) +{ + pFtu->CONTROLS[u8Channel].CSCn &= (uint32_t)~FTU_CSC_ICM_ICEXP_NUM_ICM_ECNT_MASK; + pFtu->CONTROLS[u8Channel].CSCn |= FTU_CSC_ICM_ICEXP_NUM_ICM_ECNT(u8EdgeNumber); +} + +/** + * @brief Re-start measurement when in single mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_SingleMeasurement(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_ICM_SINGLE_MASK; +} +/** + * @brief Set the measurement channel to continuous mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_EnableMeasureContinous(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_ICM_CONT_MASK; +} +/** + * @brief Set the measurement channel to single mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_DisableMeasureContinous(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_ICM_CONT_MASK; +} +/** + * @brief Set the channel starts measuring after the first edge is detected + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_EnableMeasureStartImmd(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_ICM_START_MASK; +} + +LOCAL_INLINE void FTU_HWA_ConfigInputCaptureMeasureMode(FTU_Type *pFtu, uint8_t u8Channel, FTU_MeasurementModeType eMode) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_ICM_MODE_MASK; + pFtu->CONTROLS[u8Channel].CSCn |= FTU_CSC_ICM_MODE(eMode); +} + +/** + * @brief Set the measurement starts immediately after activating the channel + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_DisableMeasureStartImmd(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_ICM_START_MASK; +} + +/** + * @brief Get channel measure mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel + * @return measure mode + */ +LOCAL_INLINE FTU_MeasurementModeType FTU_HWA_GetMeasureMode(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (FTU_MeasurementModeType)((pFtu->CONTROLS[u8Channel].CSCn & FTU_CSC_ICM_MODE_MASK) >> FTU_CSC_ICM_MODE_SHIFT); +} + +/** + * @brief Configure Edge-Aligned pwm mode channel to High-true pulses(clear output on match) + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_SetChannelEpwmHighTrue(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_ELSA_MASK; + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)(FTU_CSC_MSB_MASK | FTU_CSC_ELSB_MASK); +} + +/** + * @brief Configure Edge-Aligned pwm mode channel to Low-true pulses(set output on match) + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_SetChannelEpwmLowTrue(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)(FTU_CSC_MSB_MASK | FTU_CSC_ELSA_MASK); +} + +/** + * @brief Configure pwm link mode channel + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_ConfigChannelPwmLinkMode(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)(FTU_CSC_ELSA_MASK | FTU_CSC_MSB_MASK | FTU_CSC_MSA_MASK); + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_ELSB_MASK; +} + +/** + * @brief Enable FTU channel interrupt + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_EnableChannelInterrupt(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_CHIE_MASK; +} + +/** + * @brief Set MODE[FTUEN], this field define different free running counter and synchronization behavior. + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetModuleUpdateRegBySync(FTU_Type *pFtu) +{ + pFtu->MODE |= (uint32_t)FTU_MODE_FTUEN_MASK; +} + +/** + * @brief Clear MODE[FTUEN], this field define different free running counter and synchronization behavior. + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearModuleUpdateRegBySync(FTU_Type *pFtu) +{ + pFtu->MODE &= ~(uint32_t)FTU_MODE_FTUEN_MASK; +} + +/** + * @brief Enable FTU module fault interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableModuleFaultInterrupt(FTU_Type *pFtu) +{ + pFtu->MODE |= (uint32_t)FTU_MODE_FAULTIE_MASK; +} + + +/** + * @brief Enable FTU channel dma + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_EnableChannelDma(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_DMA_MASK; +} + + +/** + * @brief Configure FTU module fault mode + * + * @param pFtu the base address of the FTU instance + * @param eMode Fault mode type + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleFaultMode(FTU_Type *pFtu, FTU_FaultModeType eMode) +{ + pFtu->MODE &= ~(uint32_t)FTU_MODE_FAULTM_MASK; + pFtu->MODE |= FTU_MODE_FAULTM(eMode); +} + +/** + * @brief Enable synchronization hardware trigger 0 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableTrigger0Sync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_TRIG0_MASK; +} + +/** + * @brief Enable synchronization hardware trigger 1 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableTrigger1Sync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_TRIG1_MASK; +} + +/** + * @brief Enable synchronization hardware trigger 2 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableTrigger2Sync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_TRIG2_MASK; +} + +/** + * @brief Enable FTU module output mask synchronization + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableOutputMaskBySync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_SYNCHOM_MASK; +} + +/** + * @brief Disable FTU module output mask synchronization + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableOutputMaskBySync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_SYNCHOM_MASK; +} + +/** + * @brief Generate FTU software trigger + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_GenerateSwSync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_SWSYNC_MASK; +} + +/** + * @brief Configure FTU trigger mode + * + * @param pFtu the base address of the FTU instance + * @param eTrigMode Trigger mode type + */ +LOCAL_INLINE void FTU_HWA_ConfigTrigMode(FTU_Type *pFtu, FTU_TrigModeType eTrigMode) +{ + pFtu->SYNCONF &= ~(uint32_t)FTU_SYNCONF_HWTRIGMODE_MASK; + pFtu->SYNCONF |= (uint32_t)FTU_SYNCONF_HWTRIGMODE(eTrigMode); +} + +/** + * @brief Enable channel(n/n+1) deadtime functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelDeadtime(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_DEADTIME_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel(n/n+1) complement functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelComplement(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_COMPLEMENT_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel(n/n+1) synchronization functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelSync(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_SYNCEN_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel(n/n+1) Phase Shift Mode functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelPhase(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_PHASE_CHANNEL(u8Channel); +} +/** + * @brief Disable channel(n/n+1) Phase Shift Mode functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelPhase(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_PHASE_CHANNEL(u8Channel); +} +/** + * @brief Enable channel(n/n+1) Enhanced Phase Shift Mode functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelEnhancedPhase(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_EPHASE_CHANNEL(u8Channel); +} +/** + * @brief Disable channel(n/n+1) Enhanced Phase Shift Mode functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelEnhancedPhase(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_EPHASE_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel(n/n+1) fault functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelFault(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_FAULT_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel trigger out + * + * @param pFtu the base address of the FTU instance + * @param u8ChannelMask FTU channel mask, bit 0-7 indicate channel 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelTriggerOut(FTU_Type *pFtu, uint8_t u8ChannelMask) +{ + + uint32_t u32TempRegValue = FTU_TRIGCONF_CH7TRIG(((uint32_t)u8ChannelMask >> 7u) & 1u) | + FTU_TRIGCONF_CH6TRIG(((uint32_t)u8ChannelMask >> 6u) & 1u) | + FTU_TRIGCONF_CH5TRIG(((uint32_t)u8ChannelMask >> 5u) & 1u) | + FTU_TRIGCONF_CH4TRIG(((uint32_t)u8ChannelMask >> 4u) & 1u) | + FTU_TRIGCONF_CH3TRIG(((uint32_t)u8ChannelMask >> 3u) & 1u) | + FTU_TRIGCONF_CH2TRIG(((uint32_t)u8ChannelMask >> 2u) & 1u) | + FTU_TRIGCONF_CH1TRIG(((uint32_t)u8ChannelMask >> 1u) & 1u) | + FTU_TRIGCONF_CH0TRIG((uint32_t)u8ChannelMask & 1u); + pFtu->TRIGCONF |= u32TempRegValue; +} + +/** + * @brief Disable channel trigger out + * + * @param pFtu the base address of the FTU instance + * @param u8ChannelMask FTU channel mask, bit 0-7 indicate channel 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelTriggerOut(FTU_Type *pFtu, uint8_t u8ChannelMask) +{ + uint32_t u32TempRegValue = FTU_TRIGCONF_CH7TRIG(((uint32_t)u8ChannelMask >> 7u) & 1u) | + FTU_TRIGCONF_CH6TRIG(((uint32_t)u8ChannelMask >> 6u) & 1u) | + FTU_TRIGCONF_CH5TRIG(((uint32_t)u8ChannelMask >> 5u) & 1u) | + FTU_TRIGCONF_CH4TRIG(((uint32_t)u8ChannelMask >> 4u) & 1u) | + FTU_TRIGCONF_CH3TRIG(((uint32_t)u8ChannelMask >> 3u) & 1u) | + FTU_TRIGCONF_CH2TRIG(((uint32_t)u8ChannelMask >> 2u) & 1u) | + FTU_TRIGCONF_CH1TRIG(((uint32_t)u8ChannelMask >> 1u) & 1u) | + FTU_TRIGCONF_CH0TRIG((uint32_t)u8ChannelMask & 1u); + pFtu->TRIGCONF &= ~u32TempRegValue; +} + +/** + * @brief clear the channel trigger flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearChannelTriggerFlag(FTU_Type *pFtu) +{ + pFtu->TRIGCONF &= ~FTU_TRIGCONF_TRIGF_MASK; +} + +/** + * @brief Enable reload trigger + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableReloadTrigger(FTU_Type *pFtu) +{ + pFtu->TRIGCONF |= (uint32_t)FTU_TRIGCONF_RELOADTRIGEN_MASK; +} + +/** + * @brief Set channel polarity + * + * @param pFtu the base address of the FTU instance + * @param u8Mask FTU channel mask, bit 0-7 indicate channel 0-7 + */ +LOCAL_INLINE void FTU_HWA_SetChannelPolarity(FTU_Type *pFtu, uint8_t u8Mask) +{ + pFtu->POL |= FTU_POL_POLN(u8Mask); +} + +/** + * @brief Set FTU module outmask + * + * @param pFtu the base address of the FTU instance + * @param u8Channel Bit of channel indicate channel number, range: 0~7 bit + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleOutmask(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->OUTMASK &= ~(uint32_t)0xFFU; + pFtu->OUTMASK |= (uint32_t)u8Channel & (uint32_t)0xFFU; +} + +/** + * @brief Set channel filter value + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-3 + * @param u8FilterVal FTU filter value + */ +LOCAL_INLINE void FTU_HWA_ConfigChannelFilterValue(FTU_Type *pFtu, uint8_t u8Channel, uint8_t u8FilterVal) +{ + pFtu->FILTER &= ~((uint32_t)0xFu << ((uint32_t)u8Channel << 2U)); + pFtu->FILTER |= ((uint32_t)u8FilterVal << ((uint32_t)u8Channel << 2U)); +} + +/** + * @brief Configure quadrature mode + * + * @param pFtu the base address of the FTU instance + * @param eMode FTU quadrature mode + */ +LOCAL_INLINE void FTU_HWA_ConfigQuadratureMode(FTU_Type *pFtu, FTU_QuadratureModeType eMode) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_QUADMODE_MASK; + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_QUADMODE(eMode); +} + +/** + * @brief Configure FTU Counter Direction In Quadrature Decoder Mode + * + * @param pFtu the base address of the FTU instance + * @param eDir the counting direction + */ +LOCAL_INLINE void FTU_HWA_ConfigQuadDirection(FTU_Type *pFtu, FTU_QuadratureDirectionType eDir) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_QUADIR_MASK; + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_QUADIR(eDir); +} + +/** + * @brief Configure Timer Overflow Direction In Quadrature Decoder Mode + * + * @param pFtu the base address of the FTU instance + * @param eDir Indicates if the TOF bit was set on the top or the bottom of counting + */ +LOCAL_INLINE void FTU_HWA_ConfigTimerOverflowDir(FTU_Type *pFtu, FTU_TimerOverflowDirectionType eDir) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_TOFDIR_MASK; + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_TOFDIR(eDir); +} + +/** + * @brief inverted polarity of phase B input signal + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnablePhbInv(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_PHBPOL_MASK; +} + +/** + * @brief do not inverted polarity of phase B input signal + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisablePhbInv(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_PHBPOL_MASK; +} + +/** + * @brief inverted polarity of phase A input signal + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnablePhaInv(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_PHAPOL_MASK; +} + +/** + * @brief do not inverted polarity of phase B input signal + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisablePhaInv(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_PHAPOL_MASK; +} + +/** + * @brief Enable phase A glitch filter + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnablePhaGlitchFilter(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_PHAGFEN_MASK; +} + +/** + * @brief Disable phase A glitch filter + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisablePhaGlitchFilter(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_PHAGFEN_MASK; +} + +/** + * @brief Enable phase B glitch filter + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnablePhbGlitchFilter(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_PHBGFEN_MASK; +} + +/** + * @brief Disable phase B glitch filter + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisablePhbGlitchFilter(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_PHBGFEN_MASK; +} + +/** + * @brief Enable FTU module quadrature mode + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableQuadratureMode(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_QUADEN_MASK; +} + +/** + * @brief Disable FTU module quadrature mode + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableQuadratureMode(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_QUADEN_MASK; +} + +/** + * @brief Configure FTU module debug mode + * + * @param pFtu the base address of the FTU instance + * @param eDbgMode debug mode enumeration + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleDebugMode(FTU_Type *pFtu, FTU_DebugModeType eDbgMode) +{ + pFtu->CONF &= ~(uint32_t)FTU_CONF_DBG_MASK; + pFtu->CONF |= FTU_CONF_DBG(eDbgMode); +} + +/** + * @brief Set FTU module clock source + * + * @param pFtu the base address of the FTU instance + * @param eClkSrc FTU module clock source type + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleClkSrc(FTU_Type *pFtu, FTU_ModuleClkSrcType eClkSrc) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_CLKS_MASK; + pFtu->SC |= FTU_SC_CLKS(eClkSrc); +} + +/** + * @brief Clear FTU module overflow flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearOverflowFlag(FTU_Type *pFtu) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_TOF_MASK; +} + +/** + * @brief Clear FTU module reload flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearReloadFlag(FTU_Type *pFtu) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_RF_MASK; +} + +/** + * @brief Enable FTU module interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableOverflowInterrupt(FTU_Type *pFtu) +{ + pFtu->SC |= (uint32_t)FTU_SC_TOIE_MASK; +} + +/** + * @brief Disable FTU module overflow interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableOverflowInterrupt(FTU_Type *pFtu) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_TOIE_MASK; +} + +/** + * @brief Clear FTU channel interrupt flag + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_ClearChannelInterruptFlag(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_CHF_MASK; +} + +/** + * @brief Disable channel interrupt + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_DisableChannelInterrupt(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_CHIE_MASK; +} + +/** + * @brief Disable write protection + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableWriteProtection(FTU_Type *pFtu) +{ + pFtu->MODE |= (uint32_t)FTU_MODE_WPDIS_MASK; +} + +/** + * @brief Disable FTU module fault interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableModuleFaultInterrupt(FTU_Type *pFtu) +{ + pFtu->MODE &= ~(uint32_t)FTU_MODE_FAULTIE_MASK; +} + +/** + * @brief Disable synchronization hardware trigger 0 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableTrigger0Sync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_TRIG0_MASK; +} + +/** + * @brief Disable synchronization hardware trigger 1 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableTrigger1Sync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_TRIG1_MASK; +} + +/** + * @brief Disable synchronization hardware trigger 2 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableTrigger2Sync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_TRIG2_MASK; +} + +/** + * @brief Disable generate FTU software trigger + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableGenerateSwSync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_SWSYNC_MASK; +} + +/** + * @brief Disable reload trigger + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableReloadTrigger(FTU_Type *pFtu) +{ + pFtu->TRIGCONF &= ~(uint32_t)FTU_TRIGCONF_RELOADTRIGEN_MASK; +} + +/** + * @brief Disable channel(n/n+1) deadtime functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelDeadtime(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_DEADTIME_CHANNEL(u8Channel); +} + +/** + * @brief Disable channel(n/n+1) complement functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelComplement(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_COMPLEMENT_CHANNEL(u8Channel); +} + +/** + * @brief Disable channel(n/n+1) synchronization functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelSync(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_SYNCEN_CHANNEL(u8Channel); +} + +/** + * @brief Disable channel(n/n+1) fault functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelFault(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_FAULT_CHANNEL(u8Channel); +} + +/** + * @brief Clear channel polarity + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel, bit 0-7 indicate channel 0-7 + */ +LOCAL_INLINE void FTU_HWA_ClearChannelPolarity(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->POL &= ~FTU_POL_POLN(u8Channel); +} + +/** + * @brief Get channel polarity + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel, bit 0-7 indicate channel 0-7 + * @return polarity of the channels + */ +LOCAL_INLINE uint32_t FTU_HWA_GetChannelPolarity(FTU_Type *pFtu, uint8_t u8Channel) +{ + return pFtu->POL & FTU_POL_POLN(u8Channel); +} + +/** + * @brief Clear FTU module fault flag + * + * @param pFtu the base address of the FTU instance + * @param u8Flag bit 0-3 indicate fault flag 0-3. + */ +LOCAL_INLINE void FTU_HWA_ClearModuleFaultFlag(FTU_Type *pFtu, uint8_t u8Flag) +{ + pFtu->FMS &= ~(uint32_t)((uint32_t)u8Flag & 0xFu); +} + +/** + * @brief Clear FTU global fault flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearGlobalFaultFlag(FTU_Type *pFtu) +{ + pFtu->FMS &= ~(uint32_t)FTU_FMS_FAULTF_MASK; +} + +#endif /* #ifndef _HWA_FTU_H_ */ diff --git a/Inc/HwA_gpio.h b/Inc/HwA_gpio.h new file mode 100644 index 0000000..ca7629e --- /dev/null +++ b/Inc/HwA_gpio.h @@ -0,0 +1,245 @@ +/** + * @file HwA_gpio.h + * @author Flagchip + * @brief FC7xxx GPIO hardware access layer + * @version 0.1.0 + * @date 2023-02-13 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-18 Flagchip071 N/A First version for FC7xxx + ******************************************************************************** */ + +#ifndef _HWA_GPIO_H_ +#define _HWA_GPIO_H_ + +#include "device_header.h" + +/** @brief GPIO initialization level */ +typedef enum +{ + GPIO_LOW = 0U, + GPIO_HIGH = 1U +} GPIO_PinLevelType; + + +/** + * @brief Set port data output, port output can set 1 or 0 + * + * @param pGpio Gpio instance + * @param u32Value Written value + */ +LOCAL_INLINE void GPIO_HWA_ConfigPortDataOutput(GPIO_Type *pGpio, uint32_t u32Value) +{ + pGpio->PDOR = u32Value; +} + +/** + * @brief Set pin data output, pin output can set 1 or 0 + * + * @param pGpio Gpio instance + * @param u32Pin Pin mask + * @param ePinLevel Pin level + */ +LOCAL_INLINE void GPIO_HWA_ConfigPinDataOutput(GPIO_Type *pGpio, uint32_t u32Pin, GPIO_PinLevelType ePinLevel) +{ + if (GPIO_HIGH == ePinLevel) + { + pGpio->PDOR |= GPIO_PDOR_PDO(u32Pin); + } + else + { + pGpio->PDOR &= ~GPIO_PDOR_PDO(u32Pin); + } +} + +/** + * @brief Set port output to 1 + * + * @param pGpio Gpio instance + * @param u32Value Written value + */ +LOCAL_INLINE void GPIO_HWA_SetPortOutput(GPIO_Type *pGpio, uint32_t u32Value) +{ + pGpio->PSOR |= u32Value; +} + +/** + * @brief Set port output to 0 + * + * @param pGpio Gpio instance + * @param u32Value Written value + */ +LOCAL_INLINE void GPIO_HWA_ClearPortOutput(GPIO_Type *pGpio, uint32_t u32Value) +{ + pGpio->PCOR |= u32Value; +} + +/** + * @brief Toggle port output + * + * @param pGpio Gpio instance + * @param u32Value Written value + */ +LOCAL_INLINE void GPIO_HWA_TogglePort(GPIO_Type *pGpio, uint32_t u32Value) +{ + pGpio->PTOR = u32Value; +} + +/** + * @brief Set port direction + * + * @param pGpio Gpio instance + * @param u32Value Written value + */ +LOCAL_INLINE void GPIO_HWA_SetPortDirection(GPIO_Type *pGpio, uint32_t u32Value) +{ + pGpio->PDDR = u32Value; +} + +/** + * @brief Set port input disable + * + * @param pGpio Gpio instance + * @param u32Value Written value + */ +LOCAL_INLINE void GPIO_HWA_SetPortInputDisable(GPIO_Type *pGpio, uint32_t u32Value) +{ + pGpio->PIDR = u32Value; +} + + +/** + * @brief Read port data output + * + * @param pGpio Gpio instance + * @return PDOR register value + */ +LOCAL_INLINE uint32_t GPIO_HWA_ReadPortDataOutput(GPIO_Type *pGpio) +{ + return pGpio->PDOR; +} + +/** + * @brief Read port data input, this register indicate data on pad. + * + * @param pGpio Gpio instance + * @return PDIR register value + */ +LOCAL_INLINE uint32_t GPIO_HWA_ReadPortDataInput(GPIO_Type *pGpio) +{ + return pGpio->PDIR; +} + + +/** + * @brief Set pin data output, pin output can set 1 or 0 + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_SetPinDataOutput(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PDOR |= (uint32_t)1 << u8Pin; +} + +/** + * @brief Set pin output to 1 + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_SetPinOutput(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PSOR |= (uint32_t)1 << u8Pin; +} + +/** + * @brief Set pin output to 0 + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_ClearPinOutput(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PCOR |= (uint32_t)1 << u8Pin; +} + +/** + * @brief Toggle pin + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_TogglePin(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PTOR |= (uint32_t)1 << u8Pin; +} + +/** + * @brief Set pin direction + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_SetPinDirection(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PDDR |= (uint32_t)1 << u8Pin; +} + +/** + * @brief Set pin input disable + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_SetPinInputDisable(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PIDR |= (uint32_t)1 << u8Pin; +} + + +/** + * @brief Clear pin data output + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_ClearPinDataOutput(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PDOR &= ~((uint32_t)1 << u8Pin); +} + +/** + * @brief Clear pin direction + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_ClearPinDirection(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PDDR &= ~((uint32_t)1 << u8Pin); +} + +/** + * @brief Clear pin input disable + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_ClearPinInputDisable(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PIDR &= ~((uint32_t)1 << u8Pin); +} + + + + +#endif /* #ifndef _HWA_GPIO_H_ */ diff --git a/Inc/HwA_intm.h b/Inc/HwA_intm.h new file mode 100644 index 0000000..5016a93 --- /dev/null +++ b/Inc/HwA_intm.h @@ -0,0 +1,179 @@ +/** + * @file HwA_intm.h + * @author Flagchip + * @brief FC7240 INTM HWA driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version + ******************************************************************************** */ + +#ifndef _HWA_INTM_H_ +#define _HWA_INTM_H_ + +#include "device_header.h" + +typedef struct +{ + __IO uint32_t IRQSELR; /* INTM Interrupt Request Select Register*/ + __IO uint32_t LATR; /* INTM Latency Register */ + __IO uint32_t TMR; /* INTM Timer Register */ + __I uint32_t SR; /* INTM Status Register */ +} INTM_MonitorType, *INTM_MonitorMemMapPtr; + +/** + * @brief Enable the INTM. + * @param pIntm INTM instance. INTM instance. + * @param bEnable Enable the ITNM. + */ +LOCAL_INLINE void INTM_HWA_Enable(INTM_Type *const pIntm, bool bEnable) +{ + if (bEnable) + { + pIntm->ER = INTM_ER_EN_MASK; + } + else + { + pIntm->ER = 0U; + } +} + +/** + * @brief Get the instance of interrupt monitor. + * @param pIntm INTM instance. + * @param u8IrqMonitorIndex Interrupt monitor index. + * @return Monitor Instance. + */ +LOCAL_INLINE INTM_MonitorType *INTM_HWA_GetIrqMonitor(INTM_Type *const pIntm, uint8_t u8IrqMonitorIndex) +{ + return (INTM_MonitorType *)((uint32_t) & (pIntm->IRQSELR0) + (uint32_t)u8IrqMonitorIndex * 0x10U); +} + +/** + * @brief Set the interrupt acknowledge. + * @param pIntm INTM instance. + * @param u16IrqNum Interrupt number to be monitored. + */ +LOCAL_INLINE void INTM_HWA_SetIACKR(INTM_Type *const pIntm, uint16_t u16IrqNum) +{ + pIntm->IACKR = u16IrqNum; +} + +/** + * @brief Set which interrupt to be monoterd. + * @param pIntm INTM instance. + * @param u16IrqNum Interrupt number to be monitored. + */ +LOCAL_INLINE void INTM_HWA_SetIRQReqNum(INTM_MonitorType *const pIrqMon, uint16_t u16IrqNum) +{ + pIrqMon->IRQSELR = u16IrqNum; +} + +/** + * @brief Enable reset when interrupt delays overtime. + * @param pIrqMon Interrupt monitor instance. + * @param bEnable Enable reset. + */ +LOCAL_INLINE void INTM_HWA_EnableReset(INTM_MonitorType *const pIrqMon, bool bEnable) +{ + pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_RSTE_MASK) | INTM_IRQSELR_RSTE(bEnable); +} + +/** + * @brief Enable interrupt when monitored interrupt delays overtime. + * @param pIrqMon Interrupt monitor instance. + * @param bEnable Enabel the interrupt. + */ +LOCAL_INLINE void INTM_HWA_EnableInterrupt(INTM_MonitorType *const pIrqMon, bool bEnable) +{ + pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_INTE_MASK) | INTM_IRQSELR_INTE(bEnable); +} + +/** + * @brief Enable inactive mode. + * @param pIrqMon Interrupt monitor instance. + * @param bEnable Enable inactive mode. + */ +LOCAL_INLINE void INTM_HWA_EnableInactiveMode(INTM_MonitorType *const pIrqMon, bool bEnable) +{ + pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_IACTE_MASK) | INTM_IRQSELR_IACTE(bEnable); + __asm volatile( + "dmb \n" + "ldr r8, [%[IRQSELR]] \n"/* Must Read IRQSELR after set. */ + : : [IRQSELR] "r"(&pIrqMon->IRQSELR) : "r8", "memory" + ); +} + +/** + * @brief Start the inactive mode. + * @param pIrqMon Interrupt monitor instance. + */ +LOCAL_INLINE void INTM_HWA_StartInactiveMode(INTM_MonitorType *const pIrqMon) +{ + pIrqMon->IRQSELR |= INTM_IRQSELR_IACTST_MASK; + __asm volatile( + "dmb \n" + "ldr r8, [%[IRQSELR]] \n"/* Must Read IRQSELR after set. */ + : : [IRQSELR] "r"(&pIrqMon->IRQSELR) : "r8", "memory" + ); +} + +/** + * @brief Stop the inactive mode. + * @param pIrqMon Interrupt monitor instance. + * @param bEnable + */ +LOCAL_INLINE void INTM_HWA_StopInactiveMode(INTM_MonitorType *const pIrqMon) +{ + pIrqMon->IRQSELR &= ~INTM_IRQSELR_IACTST_MASK; +} + +/** + * @brief Set the timeout value of interrupt. + * @param pIrqMon Interrupt monitor instance. + * @param u32Latency the timeout value of interrupt monitor. + */ +LOCAL_INLINE void INTM_HWA_SetLatency(INTM_MonitorType *const pIrqMon, uint32_t u32Latency) +{ + pIrqMon->LATR = u32Latency; +} + +/** + * @brief Get the value of timer. + * @param pIrqMon Interrupt monitor instance. + * @return Timer value + */ +LOCAL_INLINE uint32_t INTM_HWA_GetTimerCounter(INTM_MonitorType *const pIrqMon) +{ + return pIrqMon->TMR; +} + +/** + * @brief Set the value of timer. + * @param pIrqMon Interrupt monitor instance. + * @param u32Value The value to be set. + */ +LOCAL_INLINE void INTM_HWA_SetTimerCounter(INTM_MonitorType *const pIrqMon, uint32_t u32Value) +{ + pIrqMon->TMR = u32Value; +} + +/** + * @brief Read interrupt status. + * @param pIrqMon Interrupt monitor instance. + * @return Interrupt status. + */ +LOCAL_INLINE bool INTM_HWA_ReadStatus(INTM_MonitorType *const pIrqMon) +{ + return (pIrqMon->SR & INTM_SR_MASK) == INTM_SR_MASK ? true : false; +} + +#endif /*#ifndef _HWA_INTM_H_*/ diff --git a/Inc/HwA_ism.h b/Inc/HwA_ism.h new file mode 100644 index 0000000..38eef1a --- /dev/null +++ b/Inc/HwA_ism.h @@ -0,0 +1,645 @@ +/** + * @file HwA_ism.h + * @author Flagchip084 + * @brief FC7xxx ISM hardware access layer + * @version 0.2.0 + * @date 2023-02-13 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-18 Flagchip084 N/A First version for FC7xxx + * 0.2.0 2023-02-13 Flagchip084 N/A FC7xxx release version + ******************************************************************************** */ +#ifndef _HWA_ISM_H_ +#define _HWA_ISM_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_ism + * @{ + * + */ +/********* macros ************/ + +/********* Local typedef ************/ + +typedef struct +{ + __IO uint32_t FPC_STATUS; + __IO uint32_t FPC_CTRL; + __IO uint32_t FPC_CONFIG; + __IO uint32_t FPC_TIMER; +} FPC_Type, *FPC_MemMapPtr; + +typedef struct +{ + __IO uint32_t LAM_STATUS; + __IO uint32_t LAM_CTRL; + __IO uint32_t LAM_CONFIG; + __IO uint32_t LAM_CONTER; +} LAM_Type, *LAM_MemMapPtr; + +typedef enum +{ + ISM_FPC_DETECT_NO_FILTER = 0U, /*No filter mode. Copy input to SOUT directly, which is LAM input.*/ + ISM_FPC_DETECT_IMMI_FILTER = 1U, /*Immediate filter mode.*/ + ISM_FPC_DETECT_DELAY_MODE = 2U, /*Delay mode.*/ + ISM_FPC_DETECT_PRESCALER_MODE = 3U /*Prescaler mode.*/ +} ISM_FPC_EdgeDetectModeType; + +typedef enum +{ + ISM_FPC_DELAY_FIXED0 = 0U, /*Fixed delay mode.*/ + ISM_FPC_DELAY_FIXED1 = 1U, /*Fixed delay mode.*/ + ISM_FPC_DELAY_SMART_DELAY0 = 2U, /*Smart delay mode. The counter is decremented when a glitch happens.*/ + ISM_FPC_DELAY_SMART_DELAY1 = 3U /*Smart delay mode. The counter is reset when a glitch happens.*/ +} ISM_FPC_EdgeDelayModeType; + + +typedef enum +{ + ISM_LAM_EVT_WIN_NON_INVERT = 0U, /*Event window non-inverted.*/ + ISM_LAM_EVT_WIN_INVERT = 1U /*Event window inverted.*/ +} ISM_LAM_InvertEventWindowType; + +typedef enum +{ + ISM_LAM_NTR_CLEAR_NTR_GATE = 0U, /*Neither edge used to clear the event window counter. Neither edge used to gate event generation.*/ + ISM_LAM_POS_CLEAR_NTR_GATE = 1U, /*Positive edge used to clear the event window counter. Neither edge used to gate event generation.*/ + ISM_LAM_NEG_CLEAR_NTR_GATE = 2U, /*Negative edge used to clear the event window counter. Neither edge used to gate event generation.*/ + ISM_LAM_ETR_CLEAR_NTR_GATE = 3U, /*Either edge used to clear the event window counter. Neither edge used to gate event generation.*/ + ISM_LAM_NTR_CLEAR_POS_GATE = 4U, /*Neither edge used to clear the event window counter. Positive edge used to gate event generation.*/ + ISM_LAM_POS_CLEAR_POS_GATE = 5U, /*Positive edge used to clear the event window counter. Positive edge used to gate event generation.*/ + ISM_LAM_NEG_CLEAR_POS_GATE = 6U, /*Negative edge used to clear the event window counter. Positive edge used to gate event generation.*/ + ISM_LAM_ETR_CLEAR_POS_GATE = 7U, /*Either edge used to clear the event window counter. Positive edge used to gate event generation.*/ + ISM_LAM_NTR_CLEAR_NEG_GATE = 8U, /*Neither edge used to clear the event window counter. Negative edge used to gate event generation.*/ + ISM_LAM_POS_CLEAR_NEG_GATE = 9U, /*Positive edge used to clear the event window counter. Negative edge used to gate event generation.*/ + ISM_LAM_NEG_CLEAR_NEG_GATE = 10U, /*Negative edge used to clear the event window counter. Negative edge used to gate event generation.*/ + ISM_LAM_ETR_CLEAR_NEG_GATE = 11U, /*Either edge used to clear the event window counter. Negative edge used to gate event generation.*/ + ISM_LAM_NTR_CLEAR_ETR_GATE = 12U, /*Neither edge used to clear the event window counter. Either edge used to gate event generation.*/ + ISM_LAM_POS_CLEAR_ETR_GATE = 13U, /*Positive edge used to clear the event window counter. Either edge used to gate event generation.*/ + ISM_LAM_NEG_CLEAR_ETR_GATE = 14U, /*Negative edge used to clear the event window counter. Either edge used to gate event generation.*/ + ISM_LAM_ETR_CLEAR_ETR_GATE = 15U /*Either edge used to clear the event window counter. Either edge used to gate event generation.*/ +} ISM_LAM_EventWindowEdgeType; + +typedef enum +{ + ISM_LAM_EVT_WIN_SEL_REF = 0U, /*Event window generation is determined from the reference signal.*/ + ISM_LAM_EVT_WIN_SEL_MON = 1U /*Event window generation is determined from the monitor signal.*/ +} ISM_LAM_EventWindowSelectType; + +typedef enum +{ + ISM_LAM_RUN_FREE = 0U, /*Event window generation is free-running.*/ + ISM_LAM_RUN_GATED = 1U /*Event window generation is gated with the monitor or reference signal.*/ +} ISM_LAM_RunModeSelectType; + + +typedef enum +{ + ISM_LAM_SRC_FPC_MON = 0U, /* Monitor signal is sourced directly from FPC monitor channel.*/ + ISM_LAM_SRC_EXORD_FPC_REF = 1U /* Monitor signal is EXOR'd with FPC reference channel.*/ +} ISM_LAM_MonitorSourceType; + +typedef enum +{ + ISM_LAM_FPC_MON_NON_INVERT = 0U, /* Do not invert the monitor signal from FPC.*/ + ISM_LAM_FPC_MON_INVERT = 1U /* Invert the monitor signal from FPC.*/ +} ISM_LAM_InvertMonitorType; + +typedef enum +{ + ISM_LAM_FPC_REF_NON_INVERT = 0U, /* Do not invert the reference signal from FPC.*/ + ISM_LAM_FPC_REF_INVERT = 1U /* Invert the reference signal from FPC.*/ +} ISM_LAM_InvertReferenceType; + +/********* Local inline function ************/ + +/********* ISM Register interface ************/ + +/** + * @brief Get ISM ECM count + * + * @param pIsm ISM Instance + * @return ECM count + */ +LOCAL_INLINE uint8_t ISM_HWA_PARAM_ECMC(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->PARAM & ISM_PARAM_ECMC_MASK) >> ISM_PARAM_ECMC_SHIFT); +} + +/** + * @brief Get ISM FPC count + * + * @param pIsm ISM Instance + * @return FPC count + */ +LOCAL_INLINE uint8_t ISM_HWA_PARAM_FPC(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->PARAM & ISM_PARAM_FPC_MASK) >> ISM_PARAM_FPC_SHIFT); +} + +/** + * @brief Get ISM LAM count + * + * @param pIsm ISM Instance + * @return LAM count + */ +LOCAL_INLINE uint8_t ISM_HWA_PARAM_LAM(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->PARAM & ISM_PARAM_LAM_MASK) >> ISM_PARAM_LAM_SHIFT); +} + +/** + * @brief Enable ISM + * + * @param pIsm ISM Instance + * @param bEnable EN value + */ +LOCAL_INLINE void ISM_HWA_Enable(ISM_Type *const pIsm, bool bEnable) +{ + pIsm->CTRL = (pIsm->CTRL & ~ISM_CTRL_EN_MASK) | ISM_CTRL_EN(bEnable); +} + +/** + * @brief Enable ISM Interrupt + * + * @param pIsm ISM Instance + * @param bEnable IEN value + */ +LOCAL_INLINE void ISM_HWA_InterruptEnable(ISM_Type *const pIsm, bool bEnable) +{ + pIsm->CTRL = (pIsm->CTRL & ~ISM_CTRL_IEN_MASK) | ISM_CTRL_IEN(bEnable); +} + +/** + * @brief Get ECS of ISM_E_STATUS register + * + * @param pIsm ISM Instance + * @return ECS value + */ +LOCAL_INLINE uint8_t ISM_HWA_GetEcs(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->E_STATUS & ISM_E_STATUS_ECS_MASK) >> ISM_E_STATUS_ECS_SHIFT); +} + +/** + * @brief Clear ECS of ISM_E_STATUS register + * + * @param pIsm ISM Instance + * @param u32Channels ECM channels + */ +LOCAL_INLINE void ISM_HWA_ClearEcs(ISM_Type *const pIsm, uint32_t u32Channels) +{ + pIsm->E_STATUS = (u32Channels << ISM_E_STATUS_ECS_SHIFT) & ISM_E_STATUS_ECS_MASK; +} + +/** + * @brief Get ES of ISM_E_STATUS register + * + * @param pIsm ISM Instance + * @return ES value + */ +LOCAL_INLINE uint16_t ISM_HWA_GetEs(ISM_Type *const pIsm) +{ + return (uint16_t)((pIsm->E_STATUS & ISM_E_STATUS_ES_MASK) >> ISM_E_STATUS_ES_SHIFT); +} + +/** + * @brief Clear ES of ISM_E_STATUS register + * + * @param pIsm ISM Instance + * @param u32Channels ECM channels + */ +LOCAL_INLINE void ISM_HWA_ClearEs(ISM_Type *const pIsm, uint32_t u32Channels) +{ + pIsm->E_STATUS = (u32Channels << ISM_E_STATUS_ES_SHIFT) & ISM_E_STATUS_ES_MASK; +} + +/** + * @brief Enable ISM ECM channels system event + * + * @param pIsm ISM Instance + * @param u32Channels ECM Channels + * @param bEnable enable value + */ +LOCAL_INLINE void ISM_HWA_EnableEcmSystemEvent(ISM_Type *const pIsm, uint32_t u32Channels, bool bEnable) +{ + if (bEnable) + { + pIsm->E_CTRL = pIsm->E_CTRL | (u32Channels << ISM_E_CTRL_ECE_SHIFT); + } + else + { + pIsm->E_CTRL = pIsm->E_CTRL & ~(u32Channels << ISM_E_CTRL_ECE_SHIFT); + } +} + +/** + * @brief Get Enabled ISM ECM channels system event + * + * @param pIsm ISM Instance + * @return Enabled ECM event + */ +LOCAL_INLINE uint8_t ISM_HWA_GetEnabledEcmSystemEvent(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->E_CTRL & ISM_E_CTRL_ECE_MASK) >> ISM_E_CTRL_ECE_SHIFT); +} + +/** + * @brief Enable ISM LAM channels system event + * + * @param pIsm ISM Instance + * @param u32Channels LAM Channels + * @param bEnable enable value + */ +LOCAL_INLINE void ISM_HWA_EnableLamSystemEvent(ISM_Type *const pIsm, uint32_t u32Channels, bool bEnable) +{ + if (bEnable) + { + pIsm->E_CTRL = pIsm->E_CTRL | (u32Channels << ISM_E_CTRL_EE_SHIFT); + } + else + { + pIsm->E_CTRL = pIsm->E_CTRL & ~(u32Channels << ISM_E_CTRL_EE_SHIFT); + } +} + +/** + * @brief Get Enabled ISM LAM channels system event + * + * @param pIsm ISM Instance + * @return Enabled LAM event + */ +LOCAL_INLINE uint16_t ISM_HWA_GetEnabledLamSystemEvent(ISM_Type *const pIsm) +{ + return (uint16_t)((pIsm->E_CTRL & ISM_E_CTRL_EE_MASK) >> ISM_E_CTRL_EE_SHIFT); +} + +/** + * @brief Set the EC_CTRL register + * + * @param pIsm ISM Instance + * @param u32Value register Value + */ +LOCAL_INLINE void ISM_HWA_SetEcCtrl(ISM_Type *const pIsm, uint32_t u32Value) +{ + pIsm->EC_CTRL = u32Value; +} + +/** + * @brief Set THRL and LAM channel of ECM0 + * + * @param pIsm ISM Instance + * @param u32Value THRL value + * @param u32LamChannel Lam channel + */ +LOCAL_INLINE void ISM_HWA_SetEcm0EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel) +{ + uint32_t u32TempValue = pIsm->EC_CTRL; + + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_0_MASK) | ISM_EC_CTRL_SEL_0(u32LamChannel); + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_0_MASK) | ISM_EC_CTRL_THRL_0(u32Value); + pIsm->EC_CTRL = u32TempValue; +} + +/** + * @brief Set THRL and LAM channel of ECM1 + * + * @param pIsm ISM Instance + * @param u32Value THRL value + * @param u32LamChannel Lam channel + */ +LOCAL_INLINE void ISM_HWA_SetEcm1EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel) +{ + uint32_t u32TempValue = pIsm->EC_CTRL; + + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_1_MASK) | ISM_EC_CTRL_SEL_1(u32LamChannel); + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_1_MASK) | ISM_EC_CTRL_THRL_1(u32Value); + pIsm->EC_CTRL = u32TempValue; +} + +/** + * @brief Set THRL and LAM channel of ECM2 + * + * @param pIsm ISM Instance + * @param u32Value THRL value + * @param u32LamChannel Lam channel + */ +LOCAL_INLINE void ISM_HWA_SetEcm2EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel) +{ + uint32_t u32TempValue = pIsm->EC_CTRL; + + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_2_MASK) | ISM_EC_CTRL_SEL_2(u32LamChannel); + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_2_MASK) | ISM_EC_CTRL_THRL_2(u32Value); + pIsm->EC_CTRL = u32TempValue; +} + +/** + * @brief Set THRL and LAM channel of ECM3 + * + * @param pIsm ISM Instance + * @param u32Value THRL value + * @param u32LamChannel Lam channel + */ +LOCAL_INLINE void ISM_HWA_SetEcm3EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel) +{ + uint32_t u32TempValue = pIsm->EC_CTRL; + + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_3_MASK) | ISM_EC_CTRL_SEL_3(u32LamChannel); + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_3_MASK) | ISM_EC_CTRL_THRL_3(u32Value); + pIsm->EC_CTRL = u32TempValue; +} + +/** + * @brief Get the RGD value of FPC_STATUS + * + * @param pFpc FPC Instance + * @return RGD value + */ +LOCAL_INLINE bool ISM_HWA_GetFpcRgd(FPC_Type *const pFpc) +{ + return (pFpc->FPC_STATUS & ISM_FPC_STATUS_RGD_MASK) == ISM_FPC_STATUS_RGD_MASK ? true : false; +} + +/** + * @brief Clear the RGD value of FPC_STATUS + * + * @param pFpc FPC Instance + */ +LOCAL_INLINE void ISM_HWA_ClearFpcRgd(FPC_Type *const pFpc) +{ + pFpc->FPC_STATUS = ISM_FPC_STATUS_RGD_MASK; +} + +/** + * @brief Get the FGD value of FPC_STATUS + * + * @param pFpc FPC Instance + * @return FGD value + */ +LOCAL_INLINE bool ISM_HWA_GetFpcFgd(FPC_Type *const pFpc) +{ + return (pFpc->FPC_STATUS & ISM_FPC_STATUS_FGD_MASK) == ISM_FPC_STATUS_FGD_MASK ? true : false; +} + +/** + * @brief Clear the FGD value of FPC_STATUS + * + * @param pFpc FPC Instance + */ +LOCAL_INLINE void ISM_HWA_ClearFpcFgd(FPC_Type *const pFpc) +{ + pFpc->FPC_STATUS = ISM_FPC_STATUS_FGD_MASK; +} + +/** + * @brief Set the EN of FPC_CTRL + * + * @param pFpc FPC Instance + * @param bEnable EN value + */ +LOCAL_INLINE void ISM_HWA_SetFpcCtrlEn(FPC_Type *const pFpc, bool bEnable) +{ + pFpc->FPC_CTRL = (pFpc->FPC_CTRL & ~ISM_FPC_CTRL_EN_MASK) | ISM_FPC_CTRL_EN(bEnable); +} + +/** + * @brief Set the IEN of FPC_CTRL + * + * @param pFpc FPC Instance + * @param bEnable IEN value + */ +LOCAL_INLINE void ISM_HWA_SetFpcCtrlIen(FPC_Type *const pFpc, bool bEnable) +{ + pFpc->FPC_CTRL = (pFpc->FPC_CTRL & ~ISM_FPC_CTRL_IEN_MASK) | ISM_FPC_CTRL_IEN(bEnable); +} + +/** + * @brief Get the IEN of FPC_CTRL + * + * @param pFpc FPC Instance + * @return Interrupt enable bit + */ +LOCAL_INLINE bool ISM_HWA_GetFpcCtrlIen(FPC_Type *const pFpc) +{ + return (pFpc->FPC_CTRL & ISM_FPC_CTRL_IEN_MASK) == ISM_FPC_CTRL_IEN_MASK ? true : false; +} + +/** + * @brief Set the FEG of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param eMode FEG mode + */ +LOCAL_INLINE void ISM_HWA_SetFpcFallingDetectMode(FPC_Type *const pFpc, ISM_FPC_EdgeDetectModeType eMode) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_FEG_MASK) | ISM_FPC_CONFIG_FEG(eMode); +} + +/** + * @brief Set the FED of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param eMode FED mode + */ +LOCAL_INLINE void ISM_HWA_SetFpcFallingDelayMode(FPC_Type *const pFpc, ISM_FPC_EdgeDelayModeType eMode) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_FED_MASK) | ISM_FPC_CONFIG_FED(eMode); +} + +/** + * @brief Set the REG of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param eMode REG mode + */ +LOCAL_INLINE void ISM_HWA_SetFpcRisingDetectMode(FPC_Type *const pFpc, ISM_FPC_EdgeDetectModeType eMode) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_REG_MASK) | ISM_FPC_CONFIG_REG(eMode); +} + +/** + * @brief Set the RED of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param eMode RED mode + */ +LOCAL_INLINE void ISM_HWA_SetFpcRisingDelayMode(FPC_Type *const pFpc, ISM_FPC_EdgeDelayModeType eMode) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_RED_MASK) | ISM_FPC_CONFIG_RED(eMode); +} + +/** + * @brief Set the CMP of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param u32Value FPC threshold value that is compared with the 16-bit timer. + */ +LOCAL_INLINE void ISM_HWA_SetFpcConfigCmp(FPC_Type *const pFpc, uint32_t u32Value) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_CMP_MASK) | ISM_FPC_CONFIG_CMP(u32Value); +} + +/** + * @brief Set the value of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param u32Value Register value + */ +LOCAL_INLINE void ISM_HWA_SetFpcConfig(FPC_Type *const pFpc, uint32_t u32Value) +{ + pFpc->FPC_CONFIG = u32Value; +} + +/** + * @brief Get the TIM of FPC_TIMER + * + * @param pFpc FPC Instance + * @return TIM value + */ +LOCAL_INLINE uint16_t ISM_HWA_GetFpcTimer(FPC_Type *const pFpc) +{ + return (uint16_t)((pFpc->FPC_TIMER & ISM_FPC_TIMER_TIM_MASK) >> ISM_FPC_TIMER_TIM_SHIFT); +} + +/** + * @brief Clear the TIM of FPC_TIMER + * + * @param pFpc FPC Instance + */ +LOCAL_INLINE void ISM_HWA_ClearFpcTimer(FPC_Type *const pFpc) +{ + pFpc->FPC_TIMER = ISM_FPC_TIMER_TIM_MASK; +} + +/** + * @brief Get the COUNT of LAM_STATUS + * + * @param pLam LAM Instance + * @return COUNT value + */ +LOCAL_INLINE uint32_t ISM_HWA_GetLamStatusCounter(LAM_Type *const pLam) +{ + return (pLam->LAM_STATUS & ISM_LAM_STATUS_COUNT_MASK) >> ISM_LAM_STATUS_COUNT_SHIFT; +} + +/** + * @brief Clear the COUNT of LAM_STATUS + * + * @param pLam LAM Instance + */ +LOCAL_INLINE void ISM_HWA_ClearLamStatusCounter(LAM_Type *const pLam) +{ + pLam->LAM_STATUS = ISM_LAM_STATUS_COUNT_MASK; +} + +/** + * @brief Get the OVFL of LAM_STATUS + * + * @param pLam LAM Instance + * @return OVFL value + */ +LOCAL_INLINE bool ISM_HWA_GetLamStatusOvfl(LAM_Type *const pLam) +{ + return (pLam->LAM_STATUS & ISM_LAM_STATUS_OVFL_MASK) == ISM_LAM_STATUS_OVFL_MASK ? true : false; +} + +/** + * @brief Clear the OVFL of LAM_STATUS + * + * @param pLam LAM Instance + */ +LOCAL_INLINE void ISM_HWA_ClearLamStatusOvfl(LAM_Type *const pLam) +{ + pLam->LAM_STATUS = ISM_LAM_STATUS_OVFL_MASK; +} + +/** + * @brief Set the IEN of LAM_CTRL + * + * @param pLam LAM Instance + * @param bEnable IEN value, LAM Channel Overflow Interrupt Enable + */ +LOCAL_INLINE void ISM_HWA_SetLamCtrIen(LAM_Type *const pLam, bool bEnable) +{ + pLam->LAM_CTRL = (pLam->LAM_CTRL & ~ISM_LAM_CTRL_IEN_MASK) | ISM_LAM_CTRL_IEN(bEnable); +} + +/** + * @brief Get the IEN of LAM_CTRL + * + * @param pLam LAM Instance + * @return LAM Channel Overflow Interrupt Enable bit + */ +LOCAL_INLINE bool ISM_HWA_GetLamCtrIen(LAM_Type *const pLam) +{ + return (pLam->LAM_CTRL & ISM_LAM_CTRL_IEN_MASK) == ISM_LAM_CTRL_IEN_MASK ? true : false; +} + +/** + * @brief Set the EN of LAM_CTRL + * + * @param pLam LAM Instance + * @param bEnable EN value, LAM Channel Enable + */ +LOCAL_INLINE void ISM_HWA_SetLamCtrEn(LAM_Type *const pLam, bool bEnable) +{ + pLam->LAM_CTRL = (pLam->LAM_CTRL & ~ISM_LAM_CTRL_EN_MASK) | ISM_LAM_CTRL_EN(bEnable); +} + +/** + * @brief Set the value of LAM_CONFIG + * + * @param pLam LAM Instance + * @param u32Value Reigster value + */ +LOCAL_INLINE void ISM_HWA_SetLamConfig(LAM_Type *const pLam, uint32_t u32Value) +{ + pLam->LAM_CONFIG = u32Value; +} + +/** + * @brief Set the value of LAM_COUNTER + * + * @param pLam LAM Instance + * @param u32Value Reigster value + */ +LOCAL_INLINE void ISM_HWA_SetLamCounter(LAM_Type *const pLam, uint32_t u32Value) +{ + pLam->LAM_CONTER = u32Value; +} + +/** + * @brief Get the FPC instance. + * @param pIsm ISM Instance + * @param u8FpcIndex FPC index + * @return FPC Instance + */ +LOCAL_INLINE FPC_Type *ISM_HWA_GetFpc(ISM_Type *const pIsm, uint8_t u8FpcIndex) +{ + return (FPC_Type *)((uint32_t) & (pIsm->FPC_STATUS0) + (uint32_t)u8FpcIndex * 0x10U); +} + +/** + * @brief Get the LAM instance. + * @param pIsm ISM Instance + * @param u8FpcIndex LAM index + * @return LAM Instance + */ +LOCAL_INLINE LAM_Type *ISM_HWA_GetLam(ISM_Type *const pIsm, uint8_t u8LamIndex) +{ + return (LAM_Type *)((uint32_t) & (pIsm->LAM_STATUS0) + (uint32_t)u8LamIndex * 0x10U); +} + +/** @}*/ /* HwA_ism */ + +#endif /* #ifndef _HWA_ISM_H_ */ diff --git a/Inc/HwA_lu.h b/Inc/HwA_lu.h new file mode 100644 index 0000000..f94599d --- /dev/null +++ b/Inc/HwA_lu.h @@ -0,0 +1,248 @@ +/** + * @file HwA_lu.h + * @author Flagchip0103 + * @brief FC7xxx LU hardware access layer + * @version 0.1.0 + * @date 2023-12-19 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-19 Flagchip0103 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_LU_H_ +#define _HWA_LU_H_ + +#include "device_header.h" + +/********* Local typedef ************/ +/** @brief LU LG instance */ +typedef enum +{ + LU_LG_0 = 0U, + LU_LG_1, + LU_LG_2, + LU_LG_3 +} LU_LgType; + +/** @brief LU AOI mode */ +typedef enum +{ + LU_NO_BYPASS = 0U, + LU_AOI0_BYPASS, + LU_AOI1_BYPASS, + LU_AOI0_AOI1_BYPASS +} LU_BypassModeType; + +/** @brief LU FF mode */ +typedef enum +{ + LU_BYPASS_MODE0 = 0U, + LU_RS_MODE, + LU_TFF_MODE, + LU_DFF_MODE, + LU_JKFF_MODE, + LU_LATCH_MODE +} LU_ConfigModeType; + +/** @brief LU Input(n) type */ +typedef enum +{ + LU_INPUT_N_A = 0U, + LU_INPUT_N_B, + LU_INPUT_N_C, + LU_INPUT_N_D +} LU_InputNType; +/********* Local inline function ************/ +/** + * @brief Configure LU LG(n) AOI0 configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue AOI0 register value + */ +LOCAL_INLINE void LU_HWA_ConfigAOI0(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].AOI_0 = u32RegValue; +} + +/** + * @brief Configure LU LG(n) AOI1 configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue AOI1 register value + */ +LOCAL_INLINE void LU_HWA_ConfigAOI1(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].AOI_1 = u32RegValue; +} + +/** + * @brief Configure LU LG(n) contrl configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue CTRL register value + */ +LOCAL_INLINE void LU_HWA_ConfigCtrl(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].CTRL = u32RegValue; +} + +/** + * @brief Configure LU LG(n) filter configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue FILT register value + */ +LOCAL_INLINE void LU_HWA_ConfigFilter(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].FILT = u32RegValue; +} + +/** + * @brief Set LG bypass control + * + * @param pLu LU instance + * @param eLg LG instance + * @param eMode LG bypass control mode + */ +LOCAL_INLINE void LU_HWA_SetLgBypassControl(LU_Type* pLu, LU_LgType eLg, LU_BypassModeType eMode) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].CTRL; + pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_BYPASS_MASK) | LU_CTRL_BYPASS(eMode)); +} + +/** + * @brief Set LG Flip-Flop mode + * + * @param pLu LU instance + * @param eLg LG instance + * @param eMode Flip-Flop mode + */ +LOCAL_INLINE void LU_HWA_SetLgFlipFlopMode(LU_Type* pLu, LU_LgType eLg, LU_ConfigModeType eMode) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].CTRL; + pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_MOD_MASK) | LU_CTRL_MOD(eMode)); +} + +/** + * @brief Set LG inputs synchronous control + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value LG input bit,0-3 bit indicate INPUT(n)A/INPUT(n)B/INPUT(n)C/INPUT(n)D + */ +LOCAL_INLINE void LU_HWA_SetLgInputsSyncCtrl(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].CTRL; + pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_SYNC_MASK) | LU_CTRL_SYNC(u32Value)); +} + +/** + * @brief Set LG output feedback override control + * + * @param pLu LU instance + * @param eLg LG instance + * @param eInput Feedback to LG input + */ +LOCAL_INLINE void LU_HWA_SetLgFeedbackOverrideCtrl(LU_Type* pLu, LU_LgType eLg, LU_InputNType eInput) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].CTRL; + pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_FB_OVRD_MASK) | LU_CTRL_FB_OVRD(eInput)); +} + +/** + * @brief Configure the output of flip-flop as "1" + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_ConfigFlipFlopTo1(LU_Type* pLu, LU_LgType eLg) +{ + pLu->LG[eLg].CTRL |= (uint32_t)LU_CTRL_FF_INIT_MASK; +} + +/** + * @brief Generate enable pulse + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_EnableControlFlipFlopInitOutput(LU_Type* pLu, LU_LgType eLg) +{ + pLu->LG[eLg].CTRL |= (uint32_t)LU_CTRL_INIT_EN_MASK; +} + +/** + * @brief Input filter sample count for AOI0 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample count value + */ +LOCAL_INLINE void LU_HWA_SetAOI0InputFilterSampleCount(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].FILT; + pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_CNT0_MASK) | LU_FILT_CNT0(u32Value)); +} + +/** + * @brief Input filter sample period for AOI0 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample period value + */ +LOCAL_INLINE void LU_HWA_SetAOI0InputFilterSamplePeriod(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].FILT; + pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_PRE0_MASK) | LU_FILT_PRE0(u32Value)); +} + +/** + * @brief Input filter sample count for AOI1 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample count value + */ +LOCAL_INLINE void LU_HWA_SetAOI1InputFilterSampleCount(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].FILT; + pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_CNT1_MASK) | LU_FILT_CNT1(u32Value)); +} + +/** + * @brief Input filter sample period for AOI1 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample period value + */ +LOCAL_INLINE void LU_HWA_SetAOI1InputFilterSamplePeriod(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].FILT; + pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_PRE1_MASK) | LU_FILT_PRE1(u32Value)); +} + +/** + * @brief Configure the output of flip-flop as "0" + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_ConfigFlipFlopTo0(LU_Type* pLu, LU_LgType eLg) +{ + pLu->LG[eLg].CTRL &= ~(uint32_t)LU_CTRL_FF_INIT_MASK; +} + +#endif /* #ifndef _HWA_LU_H_ */ diff --git a/Inc/HwA_mam.h b/Inc/HwA_mam.h new file mode 100644 index 0000000..4897dec --- /dev/null +++ b/Inc/HwA_mam.h @@ -0,0 +1,126 @@ +/** + * @file HwA_mam.h + * @author Flagchip + * @brief Hardware access layer for MAM + * @version 0.2.0 + * @date 2023-02-08 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-02-08 Flagchip054 N/A First version for FC7300 + ******************************************************************************** */ +#ifndef _HWA_MAM_H_ +#define _HWA_MAM_H_ +#include "device_header.h" + +/** + * @brief Set Mam module Matrix Configure register + * + * @param1 MAM base pointer + * + * @param2 u32Value Matrix Configure register value + */ +LOCAL_INLINE void Mam_HWA_SetMatrixCfg(MAM_Type *MAMInstance, uint32_t u32Value) +{ + MAMInstance->MAXCFG = u32Value; +} + +/** + * @brief Read Mam module Ctrl register + * + * @param MAM base pointer + * + * @return Matrix Configure register value + */ +LOCAL_INLINE uint32_t Mam_HWA_GetMatrixCfg(MAM_Type *MAMInstance) +{ + return (uint32_t)(MAMInstance->MAXCFG); +} + +/** + * @brief Set Mam module Wdgctr register + * + * @param1 MAM base pointer + * + * @param2 u32Value Wdgctr register value + */ +LOCAL_INLINE void Mam_HWA_Set_Wdgctr(MAM_Type *MAMInstance, uint32_t u32Value) +{ + MAMInstance->WDGCR = u32Value; +} + +/** + * @brief Read Mam module Wdgctr register + * + * @param MAM base pointer + * + * @return Wdgctr register value + */ +LOCAL_INLINE uint32 Mam_HWA_Get_Wdgctr(MAM_Type *MAMInstance) +{ + return MAMInstance->WDGCR; +} + +/** + * @brief Set Mam module ACR register + * + * @param1 MAM base pointer + * + * @param2 idx ACR register index + * + * @param3 u32Value ACR register value + */ +LOCAL_INLINE void Mam_HWA_Set_ACR(MAM_Type *MAMInstance, uint32_t idx, uint32_t u32Value) +{ + MAMInstance->ACR[idx] = u32Value; +} + +/** + * @brief Read Mam module ACR register + * + * @param1 MAM base pointer + * + * @param2 idx ACR register index + * + * @return ACR register value + */ +LOCAL_INLINE uint32_t Mam_HWA_Get_ACR(MAM_Type *MAMInstance, uint32_t idx) +{ + return MAMInstance->ACR[idx]; +} + +/** + * @brief Set Mam module ACLR register + * + * @param1 MAM base pointer + * + * @param2 idx ACLR register index + * + * @param3 u32Value ACLR register value + */ +LOCAL_INLINE void Mam_HWA_Set_ACLR(MAM_Type *MAMInstance, uint32_t idx, uint32_t u32Value) +{ + MAMInstance->ACLR[idx] = u32Value; +} + +/** + * @brief Read Mam module ACLR register + * + * @param1 MAM base pointer + * + * @param2 idx ACLR register index + * + * @return ACLR register value + */ +LOCAL_INLINE uint32_t Mam_HWA_Get_ACLR(MAM_Type *MAMInstance, uint32_t idx) +{ + return MAMInstance->ACLR[idx]; +} + +#endif diff --git a/Inc/HwA_mb.h b/Inc/HwA_mb.h new file mode 100644 index 0000000..9cfb2cb --- /dev/null +++ b/Inc/HwA_mb.h @@ -0,0 +1,408 @@ +/** + * @file HwA_mb.h + * @author Flagchip070 + * @brief FC7xxx Mailbox hardware access layer + * @version 0.1.0 + * @date 2022-11-15 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-15 Flagchip070 N/A First version for FC7300 + ******************************************************************************** */ + +#ifndef _HWA_MAILBOX_H_ +#define _HWA_MAILBOX_H_ +#include "device_header.h" + +/** + * @brief The definition of mask all events + * + */ +#define MB_EVENT_NONE 0u +/** + * @brief The definition of receiving all events + * + */ +#define MB_EVENT_ALL 0xFFFFFFFFu +/** + * @brief The definition of receiving all request events + * + */ +#define MB_EVENT_ALL_REQ 0x0000FFFFu +/** + * @brief The definition of receiving all done events + * + */ +#define MB_EVENT_ALL_DONE 0xFFFF0000u +/** + * @brief The definition of request events on ch + * + */ +#define MB_EVENT_REQ(ch) (uint32_t)((uint32_t)1u << (ch)) +/** + * @brief The definition of done events on ch + * + */ +#define MB_EVENT_DONE(ch) (uint32_t)((uint32_t)1u << ((ch) + 16u)) +/** + * @brief The definition of issue to no core + * + */ +#define MB_CORE_MASK_CORE_NONE 0u +/** + * @brief The definition of issue to core 0 + * + */ +#define MB_CORE_MASK_CORE_0 1u +/** + * @brief The definition of issue to HSM + * + */ +#define MB_CORE_MASK_HSM 2u +/** + * @brief The definition of issue to all cores + * + */ +#define MB_CORE_MASK_ALL 0x3u +/** + * @brief The definition of issue to core + * + */ +#define MB_CORE_MASK(core) (uint32_t)(1ul << (core)) + +enum +{ + MB_CORE_INDEX_CORE_0 = 0, /*!< Core index of core 0 */ + MB_CORE_INDEX_HSM, /*!< Core index of HSM */ +}; + +/** + * @brief Configure receive events of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask configuration for receiving events + */ +LOCAL_INLINE void MB_HWA_ConfigFlagMask(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_FLG_MASK_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_FLG_MASK = u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_FLG_MASK_LOCK_MASK; +} + +/** + * @brief Enable receive events of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask indicates the events to be enabled + */ +LOCAL_INLINE void MB_HWA_EnableEvent(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_FLG_MASK_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_FLG_MASK |= u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_FLG_MASK_LOCK_MASK; +} + +/** + * @brief Disable receive events of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask indicates the events to be enabled + */ +LOCAL_INLINE void MB_HWA_DisableEvent(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_FLG_MASK_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_FLG_MASK &= ~u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_FLG_MASK_LOCK_MASK; +} + +/** + * @brief Configure the interrupt of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask configuration for interrupts + */ +LOCAL_INLINE void MB_HWA_ConfigIntrEnable(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_INTEN_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_INTEN = u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_INTEN_LOCK_MASK; +} + +/** + * @brief Enable the interrupt of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask indicates the interrupts to be enabled + */ +LOCAL_INLINE void MB_HWA_EnableIntr(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_INTEN_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_INTEN |= u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_INTEN_LOCK_MASK; +} + +/** + * @brief Disable the interrupt of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask indicates the interrupts to be disabled + */ +LOCAL_INLINE void MB_HWA_DisableIntr(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_INTEN_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_INTEN &= ~u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_INTEN_LOCK_MASK; +} + +/** + * @brief Clear the flag of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask indicates the flags to be cleared + */ +LOCAL_INLINE void MB_HWA_ClearFlag(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_FLG_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_FLG |= u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_FLG_LOCK_MASK; +} + +/** + * @brief Get the flag masks of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask the mask to get + * @return the flag masks of the mailbox interrupt channel + */ +LOCAL_INLINE uint32_t MB_HWA_GetFlagMask(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + uint32_t u32RegValue = MB->INTR[u32CoreIndex].MB_INTn_FLG_MASK & u32Mask; + return u32RegValue; +} + +/** + * @brief Get the flags of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask the mask to get + * @return the flags of the mailbox interrupt channel + */ +LOCAL_INLINE uint32_t MB_HWA_GetFlag(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + uint32_t u32RegValue = MB->INTR[u32CoreIndex].MB_INTn_FLG & u32Mask; + return u32RegValue; +} + +/** + * @brief Get the result of flag & inten of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask the mask to get + * @return the result of flag & inten of the mailbox interrupt channel + */ +LOCAL_INLINE uint32_t MB_HWA_GetFlagStat(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + uint32_t u32RegValue = MB->INTR[u32CoreIndex].MB_INTn_FLG_STAT & u32Mask; + return u32RegValue; +} + +/** + * @brief Get the master ID of the currently obtained channel + * + * @param u32Channel the index of the channel + * @return the master ID + */ +LOCAL_INLINE uint32_t MB_HWA_GetMasterID(uint32_t u32Channel) +{ + uint32_t u32MasterId = MB->CHANNEL[u32Channel].MB_CCn_STAT; + u32MasterId = (u32MasterId & MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_MASK) >> MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_SHIFT; + return u32MasterId; +} + +/** + * @brief Get the security information of the currently obtained channel + * + * @param u32Channel the index of the channel + * @return the security information + */ +LOCAL_INLINE uint32_t MB_HWA_GetSecure(uint32_t u32Channel) +{ + uint32_t u32Secure = MB->CHANNEL[u32Channel].MB_CCn_STAT & MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_MASK; + return u32Secure; +} + +/** + * @brief Get the processing mode of the currently obtained channel + * + * @param u32Channel the index of the channel + * @return the processing mode + */ +LOCAL_INLINE uint32_t MB_HWA_GetSupervisor(uint32_t u32Channel) +{ + uint32_t u32Supervisor = MB->CHANNEL[u32Channel].MB_CCn_STAT & MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_MASK; + return u32Supervisor; +} + +/** + * @brief Send data to the mailbox channel + * + * @param u32Channel the index of the channel + * @param pData the buffer to be written + */ +LOCAL_INLINE void MB_HWA_WriteData(uint32_t u32Channel, uint32_t *pData) +{ + MB->CHANNEL[u32Channel].MB_CCn_DATA0 = pData[0]; + MB->CHANNEL[u32Channel].MB_CCn_DATA1 = pData[1]; +} + +/** + * @brief Receive data from the mailbox channel + * + * @param u32Channel the index of the channel + * @param pData the buffer to receive data + */ +LOCAL_INLINE void MB_HWA_GetData(uint32_t u32Channel, uint32_t *pData) +{ + pData[0] = MB->CHANNEL[u32Channel].MB_CCn_DATA0; + pData[1] = MB->CHANNEL[u32Channel].MB_CCn_DATA1; +} + +/** + * @brief Get the automatically clear status of the mailbox channel + * + * @param u32Channel the index of the channel + * @param u32CoreIndex the index of the core + * @return automatically clear the channel lock enable bit + */ +LOCAL_INLINE uint32_t MB_HWA_GetAutoClear(uint32_t u32Channel, uint32_t u32CoreIndex) +{ + uint32_t u32SemaUnlock = MB->CHANNEL[u32Channel].MB_CCn_SEMA_UNLK; + u32SemaUnlock &= (uint32_t)1u << (u32CoreIndex + MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_SHIFT); + return u32SemaUnlock; +} + +/** + * @brief Release the mailbox channel + * + * @param u32Channel the index of the channel + */ +LOCAL_INLINE void MB_HWA_ReleaseChannel(uint32_t u32Channel) +{ + MB->CHANNEL[u32Channel].MB_CCn_DONE = MB_MASTER_DONE_CODE; +} + +/** + * @brief Software clears channel lock + * + * @param u32Channel the index of the channel + */ +LOCAL_INLINE void MB_HWA_UnlockChanne(uint32_t u32Channel) +{ + MB->CHANNEL[u32Channel].MB_CCn_CLR = MB_FORCE_UNLOCK_CODE; +} + +/** + * @brief Issue a done event + * + * @param u32Channel the index of the channel + * @param u32DoneMask the cores to issue + */ +LOCAL_INLINE void MB_HWA_SetDone(uint32_t u32Channel, uint32_t u32DoneMask) +{ + MB->CHANNEL[u32Channel].MB_CCn_DONE |= (u32DoneMask & MB_CCn_DONE_DONE_MASK); +} + +/** + * @brief Try to lock a channel + * + * @param u32Channel the index of the channel + * @return Channel Lock Acquisition + */ +LOCAL_INLINE uint32_t MB_HWA_LockChannel(uint32_t u32Channel) +{ + uint32_t u32RegValue = MB->CHANNEL[u32Channel].MB_CCn_SEMA; + return u32RegValue & MB_CCn_SEMA_LOCK_MASK; +} + +/** + * @brief Configure the master ID of the core that generates a done event + * + * @param u32Channel the index of the channel + * @param u32MasterId master ID + */ +LOCAL_INLINE void MB_HWA_ConfigDoneMasterId(uint32_t u32Channel, uint32_t u32MasterId) +{ + MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK &= ~MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK; + MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK |= MB_CCn_DONE_MASK_DONE_MASTER_ID(u32MasterId); +} + +/** + * @brief Get the master ID of the core that generates a done event + * + * @param u32Channel the index of the channel + * @return the master ID + */ +LOCAL_INLINE uint32_t MB_HWA_GetDoneMasterId(uint32_t u32Channel) +{ + uint32_t u32MasterId = + (MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK & MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK) + >> MB_CCn_DONE_MASK_DONE_MASTER_ID_SHIFT; + return u32MasterId; + +} + +/** + * @brief Configure the mask of the done events + * + * @param u32Channel the index of the channel + * @param u32DoneMask the cores to issue + */ +LOCAL_INLINE void MB_HWA_ConfigDoneMask(uint32_t u32Channel, uint32_t u32DoneMask) +{ + MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK &= ~MB_CCn_DONE_DONE_MASK; + MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK |= (u32DoneMask << MB_CCn_DONE_DONE_SHIFT) & MB_CCn_DONE_DONE_MASK; +} + +/** + * @brief Get the mask of the done events + * + * @param u32Channel the index of the channel + * @return the mask of the done events + */ +LOCAL_INLINE uint32_t MB_HWA_GetDoneMask(uint32_t u32Channel) +{ + uint32_t u32Mask = MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK & MB_CCn_DONE_DONE_MASK; + return u32Mask; +} + +/** + * @brief Configure the automatically clear of the lock enable bit + * + * @param u32Channel the index of the channel + * @param u32AutoUnlockMask the automatically clear of the lock enable bit + */ +LOCAL_INLINE void MB_HWA_ConfigAutoUnlock(uint32_t u32Channel, uint32_t u32AutoUnlockMask) +{ + MB->CHANNEL[u32Channel].MB_CCn_SEMA_UNLK = MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN(u32AutoUnlockMask); +} + +/** + * @brief Issue request events + * + * @param u32Channel the index of the channel + * @param u32RequestMask the cores to issue + */ +LOCAL_INLINE void MB_HWA_ConfigRequest(uint32_t u32Channel, uint32_t u32RequestMask) +{ + MB->CHANNEL[u32Channel].MB_CCn_REQUEST = MB_CCn_REQUEST_REQ(u32RequestMask); +} + +#endif + diff --git a/Inc/HwA_mpu.h b/Inc/HwA_mpu.h new file mode 100644 index 0000000..aeee8a1 --- /dev/null +++ b/Inc/HwA_mpu.h @@ -0,0 +1,320 @@ +/** + * @file HwA_mpu.h + * @author Flagchip085 + * @brief FC7xxx MPU hardware access layer + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _HWA_MPU_H_ +#define _HWA_MPU_H_ + +#include "device_header.h" + +/** + * @brief The MPU registers struct + * + */ +typedef struct { + __I uint32_t MPU_TYPE; /* TYPE, offset: 0x0 */ + __IO uint32_t MPU_CTRL; /* CTRL, offset: 0x4 */ + __IO uint32_t MPU_RNR; /* RNR, offset: 0x8 */ + __IO uint32_t MPU_RBAR; /* RBAR, offset: 0xC */ + __IO uint32_t MPU_RASR; /* RASR, offset: 0x10 */ +} CORTEX_MPU_Type, *PCORTEX_MPU_Type; + +/** mpu base Address */ +#define CORTEX_MPU_BASE (0xE000ED90U) +#define CORTEX_MPU ((CORTEX_MPU_Type *)CORTEX_MPU_BASE) + + +/** TYPE Bit Fields **/ +#define CORTEX_MPU_TYPE_IREGION_MASK 0xFF0000U + +#define CORTEX_MPU_TYPE_IREGION_SHIFT 16U + +#define CORTEX_MPU_TYPE_IREGION_WIDTH 8U + +#define CORTEX_MPU_TYPE_IREGION(x) (((uint32_t)(((uint32_t)(x))<MPU_TYPE; +} + +/** + * @brief disable fault exceptions + * + * + */ +LOCAL_INLINE void MPU_HWA_Fault_Disable(void) +{ + SCB->SHCSR &= ~((uint32_t)SCB_SHCSR_MEMFAULTENA_Msk); +} + +/** + * @brief enable fault exceptions + * + * + */ +LOCAL_INLINE void MPU_HWA_Fault_Enable(void) +{ + SCB->SHCSR |= (uint32_t)SCB_SHCSR_MEMFAULTENA_Msk; +} + +/** + * @brief set mpu control register + * + * @param u32RegValue the value write to register + * @return LOCAL_INLINE + */ +LOCAL_INLINE void MPU_HWA_Set_CR(uint32_t u32RegValue) +{ + CORTEX_MPU->MPU_CTRL = u32RegValue; +} + +/** + * @brief set mpu number register + * + * @param u32RegValue the value write to register + * @return LOCAL_INLINE + */ +LOCAL_INLINE void MPU_HWA_Set_NR(uint8_t u32RegValue) +{ + CORTEX_MPU->MPU_RNR = (MPU_REGION_MASK_U32 & u32RegValue); +} + +/** + * @brief set mpu base address register + * + * @param u32RegValue the value write to register + * @return LOCAL_INLINE + */ +LOCAL_INLINE void MPU_HWA_Set_BAR(uint32_t u32RegValue) +{ + CORTEX_MPU->MPU_RBAR = u32RegValue; +} + + +/** + * @brief set mpu attribute and size register + * + * @param u32RegValue the value write to registe + * @return LOCAL_INLINE + */ +LOCAL_INLINE void MPU_HWA_Set_ASR(uint32_t u32RegValue) +{ + CORTEX_MPU->MPU_RASR = u32RegValue; +} + + +#endif /* _HWA_MPU_H_ */ + diff --git a/Inc/HwA_msc.h b/Inc/HwA_msc.h new file mode 100644 index 0000000..4498f9c --- /dev/null +++ b/Inc/HwA_msc.h @@ -0,0 +1,841 @@ +/** + * @file HwA_msc.h + * @author Flagchip + * @brief FC7240 MSC HWA driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version + ******************************************************************************** */ + +#ifndef _HWA_MSC_H_ +#define _HWA_MSC_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_msc + * @{ + * + */ +/********* macros ************/ + +typedef enum +{ + MSC_RSV_SUCCESS = 0x0U, /*!< MSC receive status is successful. */ + MSC_RSV_PARITY_ERROR = 0x1U, /*!< MSC receive has parity error. */ + MSC_RSV_STOP_ERROR = 0x2U /*!< MSC receive has stop error. */ +} MSC_ReceiveStatusType; + +/********* Local typedef ************/ + +/********* Local inline function ************/ + +/********* xxx Register interface ************/ + +/** + * @brief Get the msc TCCTR register + * + * @param pMsc MSCInstance + * @param u32Value TCCTR register value + */ +LOCAL_INLINE void MSC_HWA_SetTcctr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCCTR = u32Value; +} + +/** + * @brief Get the msc TCCTR register DTS bit + * + * @param pMsc MSCInstance + * @return DTS value + */ +LOCAL_INLINE bool MSC_HWA_GetDataNeedSend(MSC_Type *const pMsc) +{ + return (pMsc->TCCTR & MSC_TCCTR_DTS_MASK) == MSC_TCCTR_DTS_MASK ? true : false; +} + +/** + * @brief Set the msc TCCTR register DTS bit + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_SetDataNeedSend(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_SDTS_MASK; +} + +/** + * @brief Get the msc TCCTR register CTS bit + * + * @param pMsc MSCInstance + * @return CTS value + */ +LOCAL_INLINE bool MSC_HWA_GetCmdNeedSend(MSC_Type *const pMsc) +{ + return (pMsc->TCCTR & MSC_TCCTR_CTS_MASK) == MSC_TCCTR_CTS_MASK ? true : false; +} + +/** + * @brief Get the CFB value of TCSTR register + * + * @param pMsc MSCInstance + * @return CFB value + */ +LOCAL_INLINE bool MSC_HWA_GetCfb(MSC_Type *const pMsc) +{ + return (bool)(((pMsc->TCSTR & (uint32_t)MSC_TCSTR_CFB_MASK) != 0U) ? true : false); +} + +/** + * @brief Get the DFB value of TCSTR register + * + * @param pMsc MSCInstance + * @return DFB value + */ +LOCAL_INLINE bool MSC_HWA_GetDfb(MSC_Type *const pMsc) +{ + return ((pMsc->TCSTR & (uint32_t)MSC_TCSTR_DFB_MASK) != 0U) ? true : false; +} + +/** + * @brief Set the NP value of TCSTR register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_SetNp(MSC_Type *const pMsc, uint8_t u8Np) +{ + pMsc->TCSTR = (pMsc->TCSTR & ~MSC_TCSTR_NP_MASK) | MSC_TCSTR_NP(u8Np); +} + +/** + * @brief Get the NP value of TCSTR register + * + * @param pMsc MSCInstance + * @return NP value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetNp(MSC_Type *const pMsc) +{ + return ((pMsc->TCSTR & (uint32_t)MSC_TCSTR_NP_MASK)) >> MSC_TCSTR_NP_SHIFT; +} + +/** + * @brief Set the msc TCDAR register + * + * @param pMsc MSCInstance + * @param u32Value TCDAR value + */ +LOCAL_INLINE void MSC_HWA_SetTcdar(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCDAR = u32Value; +} + +/** + * @brief Set the TDH of TCDAR register + * + * @param pMsc MSCInstance + * @param u16Value TDH value + */ +LOCAL_INLINE void MSC_HWA_SetTcdarTdh(MSC_Type *const pMsc, uint16_t u16Value) +{ + pMsc->TCDAR = (pMsc->TCDAR & ~MSC_TCDAR_TDH_MASK) | MSC_TCDAR_TDH(u16Value); +} + +/** + * @brief Set the TDL of TCDAR register + * + * @param pMsc MSCInstance + * @param u16Value TDL value + */ +LOCAL_INLINE void MSC_HWA_SetTcdarTdl(MSC_Type *const pMsc, uint16_t u16Value) +{ + pMsc->TCDAR = (pMsc->TCDAR & ~MSC_TCDAR_TDL_MASK) | MSC_TCDAR_TDL(u16Value); +} + +/** + * @brief Set the TCCOR register + * + * @param pMsc MSCInstance + * @param u32Value TCCOR value + */ +LOCAL_INLINE void MSC_HWA_SetTccor(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCCOR = u32Value; +} + +/** + * @brief Set the TCH of TCCOR register + * + * @param pMsc MSCInstance + * @param u16Value TCH value + */ +LOCAL_INLINE void MSC_HWA_SetTccorTch(MSC_Type *const pMsc, uint16_t u16Value) +{ + pMsc->TCCOR = (pMsc->TCCOR & ~MSC_TCCOR_TCH_MASK) | MSC_TCCOR_TCH(u16Value); +} + +/** + * @brief Set the TCL of TCCOR register + * + * @param pMsc MSCInstance + * @param u16Value TCL value + */ +LOCAL_INLINE void MSC_HWA_SetTccorTcl(MSC_Type *const pMsc, uint16_t u16Value) +{ + pMsc->TCCOR = (pMsc->TCCOR & ~MSC_TCCOR_TCL_MASK) | MSC_TCCOR_TCL(u16Value); +} + +/** + * @brief Set the TCSLR register + * + * @param pMsc MSCInstance + * @param u32Value TCSLR value + */ +LOCAL_INLINE void MSC_HWA_SetTcslr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCSLR = u32Value; +} + +/** + * @brief Set the TCSHR register + * + * @param pMsc MSCInstance + * @param u32Value TCSHR value + */ +LOCAL_INLINE void MSC_HWA_SetTcshr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCSHR = u32Value; +} + +/** + * @brief Set the TCELR register + * + * @param pMsc MSCInstance + * @param u32Value TCELR value + */ +LOCAL_INLINE void MSC_HWA_SetTcelr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCELR = u32Value; +} + +/** + * @brief Get the IOCR register value + * + * @param pMsc MSCInstance + * @return IOCR value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetIocr(MSC_Type *const pMsc) +{ + return pMsc->IOCR; +} + +/** + * @brief Set the IOCR register + * + * @param pMsc MSCInstance + * @param u32Value IOCR value + */ +LOCAL_INLINE void MSC_HWA_SetIocr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->IOCR = u32Value; +} + +/** + * @brief Set the ISCR register + * + * @param pMsc MSCInstance + * @param u32Value ISCR value + */ +LOCAL_INLINE void MSC_HWA_SetIscr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->ISCR = u32Value; +} + +/** + * @brief Set the msc TCDIS + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_SetTcdis(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_SDIS_MASK; +} + +/** + * @brief Clear the msc TCDIS + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearTcdis(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CDIS_MASK; +} + +/** + * @brief Clear the msc CRFI + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearCrfi(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CRFI_MASK; +} + +/** + * @brief Clear the msc CTFI + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearCtfi(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CTFI_MASK; +} + +/** + * @brief Clear the msc CCFI + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearCcfi(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CCFI_MASK; +} + +/** + * @brief Clear the msc CDFI + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearCdfi(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CDFI_MASK; +} + +/** + * @brief Get the msc INSR register + * + * @param pMsc MSCInstance + * @return INSR register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetInsr(MSC_Type *const pMsc) +{ + return pMsc->INSR & (uint32_t)MSC_INSR_MASK; +} + +/** + * @brief Set the INCR register + * + * @param pMsc MSCInstance + * @param u32Value INCR value + */ +LOCAL_INLINE void MSC_HWA_SetIncr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->INCR = u32Value; +} + +/** + * @brief Check the RFIE of INCR register + * + * @param pMsc MSCInstance + * @return RFIE enable + */ +LOCAL_INLINE bool MSC_HWA_GetRfieEnable(MSC_Type *const pMsc) +{ + return (pMsc->INCR & MSC_INCR_RFIE_MASK) != 0U ? true : false; +} + +/** + * @brief Set the RFIE of INCR register + * + * @param pMsc MSCInstance + * @param bEnable enable RFIE + */ +LOCAL_INLINE void MSC_HWA_SetRfieEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->INCR = (pMsc->INCR & ~MSC_INCR_RFIE_MASK) | MSC_INCR_RFIE(bEnable); +} + +/** + * @brief Check the TFIE of INCR register + * + * @param pMsc MSCInstance + * @return TFIE enable + */ +LOCAL_INLINE bool MSC_HWA_GetTfieEnable(MSC_Type *const pMsc) +{ + return (pMsc->INCR & MSC_INCR_TFIE_MASK) == MSC_INCR_TFIE_MASK ? true : false; +} + +/** + * @brief Set the TFIE of INCR register + * + * @param pMsc MSCInstance + * @param bEnable enable TFIE + */ +LOCAL_INLINE void MSC_HWA_SetTfieEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->INCR = (pMsc->INCR & ~MSC_INCR_TFIE_MASK) | MSC_INCR_TFIE(bEnable); +} + +/** + * @brief Check the CFIE of INCR register + * + * @param pMsc MSCInstance + * @return CFIE enable + */ +LOCAL_INLINE bool MSC_HWA_GetCfieEnable(MSC_Type *const pMsc) +{ + return (pMsc->INCR & MSC_INCR_CFIE_MASK) == MSC_INCR_CFIE_MASK ? true : false; +} + +/** + * @brief Set the CFIE of INCR register + * + * @param pMsc MSCInstance + * @param bEnable enable CFIE + */ +LOCAL_INLINE void MSC_HWA_SetCfieEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->INCR = (pMsc->INCR & ~MSC_INCR_CFIE_MASK) | MSC_INCR_CFIE(bEnable); +} + +/** + * @brief Check the DFIE of INCR register + * + * @param pMsc MSCInstance + * @return DFIE enable + */ +LOCAL_INLINE bool MSC_HWA_GetDfieEnable(MSC_Type *const pMsc) +{ + return (pMsc->INCR & MSC_INCR_DFIE_MASK) == MSC_INCR_DFIE_MASK ? true : false; +} + +/** + * @brief Set the DFIE of INCR register + * + * @param pMsc MSCInstance + * @param bEnable enable DFIE + */ +LOCAL_INLINE void MSC_HWA_SetDfieEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->INCR = (pMsc->INCR & ~MSC_INCR_DFIE_MASK) | MSC_INCR_DFIE(bEnable); +} + +/** + * @brief Check the TOIE of RTOR register + * + * @param pMsc MSCInstance + * @return TOIE enable + */ +LOCAL_INLINE bool MSC_HWA_GetToieEnable(MSC_Type *const pMsc) +{ + return (pMsc->RTOR & MSC_RTOR_TOIE_MASK) == MSC_RTOR_TOIE_MASK ? true : false; +} + +/** + * @brief Set the TOIE of RTOR register + * + * @param pMsc MSCInstance + * @param bEnable enable TOIE + */ +LOCAL_INLINE void MSC_HWA_SetToieEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->RTOR = (pMsc->RTOR & ~MSC_RTOR_TOIE_MASK) | MSC_RTOR_TOIE(bEnable); +} + +/** + * @brief Check the TOF of RTOR register + * + * @param pMsc MSCInstance + * @return TOIE enable + */ +LOCAL_INLINE bool MSC_HWA_GetTofEnable(MSC_Type *const pMsc) +{ + return (pMsc->RTOR & MSC_RTOR_TOF_MASK) == MSC_RTOR_TOF_MASK ? true : false; +} + +/** + * @brief Check the TOF of RTOR register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearTofEnable(MSC_Type *const pMsc) +{ + pMsc->RTOR = (pMsc->RTOR & (~(MSC_RTOR_TOFC_MASK | MSC_RTOR_TOFS_MASK))) | MSC_RTOR_TOFC_MASK; +} + +/** + * @brief Check the RX busy status of RCCSR register + * + * @param pMsc MSCInstance + * @return rx busy status + */ +LOCAL_INLINE bool MSC_HWA_GetRxBusy(MSC_Type *const pMsc) +{ + return (pMsc->RCCSR & MSC_RCCSR_RX_BUSY_MASK) == MSC_RCCSR_RX_BUSY_MASK ? true : false; +} + +/** + * @brief Get the msc RCCSR register + * + * @param pMsc MSCInstance + * @return RCCSR register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetRccsr(MSC_Type *const pMsc) +{ + return pMsc->RCCSR; +} + +/** + * @brief Set the RCCSR register + * + * @param pMsc MSCInstance + * @param u32Value RCCSR value + */ +LOCAL_INLINE void MSC_HWA_SetRccsr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->RCCSR = u32Value; +} + +/** + * @brief Get the DATA of RDR0 register + * + * @param pMsc MSCInstance + * @return RDATA value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr0Data(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR0 & MSC_RDR0_RDATA_MASK) >> MSC_RDR0_RDATA_SHIFT); +} + +/** + * @brief Get the LAF of RDR0 register + * + * @param pMsc MSCInstance + * @return LAF value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr0Addr(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR0 & MSC_RDR0_LAF_MASK) >> MSC_RDR0_LAF_SHIFT); +} + +/** + * @brief Get the VLD of RDR0 register + * + * @param pMsc MSCInstance + * @return VLD value + */ +LOCAL_INLINE bool MSC_HWA_GetRdr0Vld(MSC_Type *const pMsc) +{ + return (pMsc->RDR0 & MSC_RDR0_VLD_MASK) == MSC_RDR0_VLD_MASK ? true : false; +} + +/** + * @brief Get the RERR of RDR0 register + * + * @param pMsc MSCInstance + * @return RERR value + */ +LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr0Rerr(MSC_Type *const pMsc) +{ + uint32_t u32Tempvalue = (pMsc->RDR0 & MSC_RDR0_RERR_MASK) >> MSC_RDR0_RERR_SHIFT; + return (MSC_ReceiveStatusType)u32Tempvalue; +} + +/** + * @brief Clear the VLD of register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearRdr0Vld(MSC_Type *const pMsc) +{ + pMsc->RDR0 |= MSC_RDR0_CLR_MASK; +} + + +/** + * @brief Get the DATA of RDR1 register + * + * @param pMsc MSCInstance + * @return RDATA value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr1Data(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR1 & MSC_RDR1_RDATA_MASK) >> MSC_RDR1_RDATA_SHIFT); +} + +/** + * @brief Get the LAF of RDR1 register + * + * @param pMsc MSCInstance + * @return LAF value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr1Addr(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR1 & MSC_RDR1_LAF_MASK) >> MSC_RDR1_LAF_SHIFT); +} + +/** + * @brief Get the VLD of RDR1 register + * + * @param pMsc MSCInstance + * @return VLD value + */ +LOCAL_INLINE bool MSC_HWA_GetRdr1Vld(MSC_Type *const pMsc) +{ + return (pMsc->RDR1 & MSC_RDR1_VLD_MASK) == MSC_RDR1_VLD_MASK ? true : false; +} + +/** + * @brief Get the RERR of RDR1 register + * + * @param pMsc MSCInstance + * @return RERR value + */ +LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr1Rerr(MSC_Type *const pMsc) +{ + uint32_t u32Tempvalue = (pMsc->RDR1 & MSC_RDR1_RERR_MASK) >> MSC_RDR1_RERR_SHIFT; + return (MSC_ReceiveStatusType)u32Tempvalue ; +} + +/** + * @brief Clear the VLD of register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearRdr1Vld(MSC_Type *const pMsc) +{ + pMsc->RDR1 |= MSC_RDR1_CLR_MASK; +} + + +/** + * @brief Get the DATA of RDR2 register + * + * @param pMsc MSCInstance + * @return RDATA value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr2Data(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR2 & MSC_RDR2_RDATA_MASK) >> MSC_RDR2_RDATA_SHIFT); +} + +/** + * @brief Get the LAF of RDR2 register + * + * @param pMsc MSCInstance + * @return LAF value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr2Addr(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR2 & MSC_RDR2_LAF_MASK) >> MSC_RDR2_LAF_SHIFT); +} + +/** + * @brief Get the VLD of RDR2 register + * + * @param pMsc MSCInstance + * @return VLD value + */ +LOCAL_INLINE bool MSC_HWA_GetRdr2Vld(MSC_Type *const pMsc) +{ + return (pMsc->RDR2 & MSC_RDR2_VLD_MASK) == MSC_RDR2_VLD_MASK ? true : false; +} + +/** + * @brief Get the RERR of RDR2 register + * + * @param pMsc MSCInstance + * @return RERR value + */ +LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr2Rerr(MSC_Type *const pMsc) +{ + uint32_t u32Tempvalue = (pMsc->RDR2 & MSC_RDR2_RERR_MASK) >> MSC_RDR2_RERR_SHIFT; + return (MSC_ReceiveStatusType)u32Tempvalue; +} + +/** + * @brief Clear the VLD of register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearRdr2Vld(MSC_Type *const pMsc) +{ + pMsc->RDR2 |= MSC_RDR2_CLR_MASK; +} + + +/** + * @brief Get the DATA of RDR3 register + * + * @param pMsc MSCInstance + * @return RDATA value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr3Data(MSC_Type *const pMsc) +{ + return (uint8_t)(pMsc->RDR3 & MSC_RDR3_RDATA_MASK) >> MSC_RDR3_RDATA_SHIFT; +} + +/** + * @brief Get the LAF of RDR3 register + * + * @param pMsc MSCInstance + * @return LAF value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr3Addr(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR3 & MSC_RDR3_LAF_MASK) >> MSC_RDR3_LAF_SHIFT); +} + +/** + * @brief Get the VLD of RDR3 register + * + * @param pMsc MSCInstance + * @return VLD value + */ +LOCAL_INLINE bool MSC_HWA_GetRdr3Vld(MSC_Type *const pMsc) +{ + return (pMsc->RDR3 & MSC_RDR3_VLD_MASK) == MSC_RDR3_VLD_MASK ? true : false; +} + +/** + * @brief Get the RERR of RDR3 register + * + * @param pMsc MSCInstance + * @return RERR value + */ +LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr3Rerr(MSC_Type *const pMsc) +{ + uint32_t u32Tempvalue = (pMsc->RDR3 & MSC_RDR3_RERR_MASK) >> MSC_RDR3_RERR_SHIFT; + return (MSC_ReceiveStatusType)u32Tempvalue; +} + +/** + * @brief Clear the VLD of register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearRdr3Vld(MSC_Type *const pMsc) +{ + pMsc->RDR3 |= MSC_RDR3_CLR_MASK; +} + +/** + * @brief Reset the msc + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_SetMsrRst(MSC_Type *const pMsc) +{ + pMsc->MSR |= MSC_MSR_RST_MASK; +} + +/** + * @brief Get the reset status + * + * @param pMsc MSCInstance + * @return reset status + */ +LOCAL_INLINE bool MSC_HWA_GetMsrRdone(MSC_Type *const pMsc) +{ + return (bool)(((pMsc->MSR & MSC_MSR_RDONE_MASK) != 0U) ? true : false); +} + +/** + * @brief clear reset status + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearMsrDone(MSC_Type *const pMsc) +{ + pMsc->SRCR = MSC_SRCR_RCLR_MASK; +} + +/** + * @brief Get the msc RTOR register + * + * @param pMsc MSCInstance + * @return RTOR register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetRtor(MSC_Type *const pMsc) +{ + return pMsc->RTOR; +} + +/** + * @brief Set the msc RTOR register + * + * @param pMsc MSCInstance + * @param u32Value RTOR value + */ +LOCAL_INLINE void MSC_HWA_SetRtor(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->RTOR = u32Value; +} + +/** + * @brief Get the msc TCCTR1 register + * + * @param pMsc MSCInstance + * @return TCCTR1 register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetTcctr1(MSC_Type *const pMsc) +{ + return pMsc->TCCTR1; +} + +/** + * @brief Set the msc TCCTR1 register + * + * @param pMsc MSCInstance + * @param u32Value TCCTR1 value + */ +LOCAL_INLINE void MSC_HWA_SetTcctr1(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCCTR1 = u32Value; +} + +/** + * @brief Set the EN msc GCR register + * + * @param pMsc MSCInstance + * @param bEnable EN value + */ +LOCAL_INLINE void MSC_HWA_SetMscEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->GCR = (pMsc->GCR & ~MSC_GCR_EN_MASK) | MSC_GCR_EN(bEnable); +} + +/** + * @brief Set the WP_EN of msc GCR register + * + * @param pMsc MSCInstance + * @param bEnable WP_EN value + */ +LOCAL_INLINE void MSC_HWA_SetMscWriteProtection(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->GCR = (pMsc->GCR & ~MSC_GCR_WP_EN_MASK) | MSC_GCR_WP_EN(bEnable); +} + +/** + * @brief Unlock the msc CCULR register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_Unlock(MSC_Type *const pMsc) +{ + pMsc->CCULR = 0x10248888U; +} + + +/** @}*/ /* HwA_msc */ + +#endif /* #ifndef _HWA_MSC_H_ */ diff --git a/Inc/HwA_overlay.h b/Inc/HwA_overlay.h new file mode 100644 index 0000000..1e181b5 --- /dev/null +++ b/Inc/HwA_overlay.h @@ -0,0 +1,315 @@ +/** + * @file HwA_overlay.h + * @author Flagchip + * @brief FC4xxx Overlay hardware access layer + * @version 0.1.0 + * @date 2023-12-25 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ + +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-29 Flagchip0038 N/A First version for FC7240 +********************************************************************************/ + +#ifndef _HWA_OVERLAY_H_ +#define _HWA_OVERLAY_H_ + +#include "device_header.h" + +/** + * @defgroup HwA_overlay + * @ingroup fc7xxx_hwa_overlay + * @{ + */ + + +/** Overlay Region Count */ +#define OVERLYA_REGION_CNT 3U + +/** FAR source address */ +#define OVERLAY_FAR_SRC 0x08000000U + +/** FAR max size */ +#define OVERLAY_FAR_SIZE_MAX 0x2000000U +/** FAR size align */ +#define OVERLAY_FAR_SIZE_ALIGN 0x10000U +/** FAR size max mask **/ +#define OVERLAY_FAR_SIZE_MASK 0xFFFFU + +/** + * @brief OVERlay Region size + * + */ +typedef enum +{ + OVERLAY_OVERLAYSIZE_1KB = 0x1, /**< OVERLAY_OVERLAYSIZE_1KB, remapping overlay region size to 1KB */ + OVERLAY_OVERLAYSIZE_2KB = 0x2, /**< OVERLAY_OVERLAYSIZE_2KB, remapping overlay region size to 2KB */ + OVERLAY_OVERLAYSIZE_4KB = 0x4, /**< OVERLAY_OVERLAYSIZE_4KB, remapping overlay region size to 4KB */ + OVERLAY_OVERLAYSIZE_8KB = 0x8, /**< OVERLAY_OVERLAYSIZE_8KB, remapping overlay region size to 8KB */ + OVERLAY_OVERLAYSIZE_16KB = 0x10, /**< OVERLAY_OVERLAYSIZE_16KB, remapping overlay region size to 16KB */ + OVERLAY_OVERLAYSIZE_32KB = 0x20, /**< OVERLAY_OVERLAYSIZE_32KB, remapping overlay region size to 32KB */ + OVERLAY_OVERLAYSIZE_64KB = 0x40 /**< OVERLAY_OVERLAYSIZE_64KB, remapping overlay region size to 64KB */ +}OVERLAY_OverlaySizeType; + +/** + * @brief FAR Size + * + */ +typedef enum +{ + OVERLAY_FARUINTSIZE_64KB = 0x10000, /**< OVERLAY_FARUINTSIZE_64KB, remapping far uint size to 64KB */ +}OVERLAY_FARSizeType; + +/** + * @brief enable overlay global switch + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayEnable(void) +{ + AHB_OVERLAY->GLOBAL_EN |= AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK; +} + +/** + * @brief disable overlay global switch + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayDisable(void) +{ + AHB_OVERLAY->GLOBAL_EN &= ~((uint32_t)AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK); +} + +/** + * @brief enable far global switch + * + */ +LOCAL_INLINE void OVERLAY_HWA_FAREnable(void) +{ + AHB_OVERLAY->GLOBAL_EN |= AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK; +} + +/** + * @brief disable far global switch + * + */ +LOCAL_INLINE void OVERLAY_HWA_FARDisable(void) +{ + AHB_OVERLAY->GLOBAL_EN &= ~((uint32_t)AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK); +} + +/** + * @brief enable overlay region 0 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion0Enable(void) +{ + AHB_OVERLAY->REGION_0_EN |= AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK; +} + +/** + * @brief disable overlay region 0 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion0Disable(void) +{ + AHB_OVERLAY->REGION_0_EN &= ~((uint32_t)AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK); +} + +/** + * @brief Set Overlay Region 0 Source + * + * @param u32Src Source address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Src(uint32_t u32Src) +{ + AHB_OVERLAY->REGION_0_SRC = AHB_OVERLAY_REGION_0_SRC_REGION0_SRC(u32Src); +} + +/** + * @brief Set Overlay Region 0 Destination + * + * @param u32Dst Destination address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Dst(uint32_t u32Dst) +{ + AHB_OVERLAY->REGION_0_DST = AHB_OVERLAY_REGION_0_DST_REGION0_DST(u32Dst); +} + +/** + * @brief Set Overlay Region 0 Size + * + * @param eSize size + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Size(OVERLAY_OverlaySizeType eSize) +{ + AHB_OVERLAY->REGION_0_SIZE = AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE((uint32_t)eSize); +} + + + +/** + * @brief enable overlay region 1 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion1Enable(void) +{ + AHB_OVERLAY->REGION_1_EN |= AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK; +} + +/** + * @brief disable overlay region 1 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion1Disable(void) +{ + AHB_OVERLAY->REGION_1_EN &= ~((uint32_t)AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK); +} + +/** + * @brief Set Overlay Region 1 Source + * + * @param u32Src Source address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Src(uint32_t u32Src) +{ + AHB_OVERLAY->REGION_1_SRC = AHB_OVERLAY_REGION_1_SRC_REGION1_SRC(u32Src); +} + +/** + * @brief Set Overlay Region 1 Destination + * + * @param u32Dst Destination address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Dst(uint32_t u32Dst) +{ + AHB_OVERLAY->REGION_1_DST = AHB_OVERLAY_REGION_1_DST_REGION1_DST(u32Dst); +} + +/** + * @brief Set Overlay Region 1 Size + * + * @param eSize size + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Size(OVERLAY_OverlaySizeType eSize) +{ + AHB_OVERLAY->REGION_1_SIZE = AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE((uint32_t)eSize); +} + + +/** + * @brief enable overlay region 2 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion2Enable(void) +{ + AHB_OVERLAY->REGION_2_EN |= AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK; +} + +/** + * @brief disable overlay region 2 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion2Disable(void) +{ + AHB_OVERLAY->REGION_2_EN &= ~((uint32_t)AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK); +} + +/** + * @brief Set Overlay Region 2 Source + * + * @param u32Src Source address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Src(uint32_t u32Src) +{ + AHB_OVERLAY->REGION_2_SRC = AHB_OVERLAY_REGION_2_SRC_REGION2_SRC(u32Src); +} + +/** + * @brief Set Overlay Region 2 Destination + * + * @param u32Dst Destination address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Dst(uint32_t u32Dst) +{ + AHB_OVERLAY->REGION_2_DST = AHB_OVERLAY_REGION_2_DST_REGION2_DST(u32Dst); +} + +/** + * @brief Set Overlay Region 2 Size + * + * @param eSize size + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Size(OVERLAY_OverlaySizeType eSize) +{ + AHB_OVERLAY->REGION_2_SIZE = AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE((uint32_t)eSize); +} + + + + +/** + * @brief Set Far Destination + * + * @param u32Dst Destination address, must pflash + */ +LOCAL_INLINE void OVERLAY_HWA_SetFarDst(uint32_t u32Dst) +{ + AHB_OVERLAY->FAR_DST = AHB_OVERLAY_FAR_DST_FAR_DST_ADDR(u32Dst); +} + +/** + * @brief Set Far Size + * + * @param u32Size size=(u32Size+1)*64KB + */ +LOCAL_INLINE void OVERLAY_HWA_SetFarSize(uint32_t u32Size) +{ + AHB_OVERLAY->FAR_SIZE = AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL(u32Size); +} + + +/** + * @brief enable error interrupt + * + */ +LOCAL_INLINE void OVERLAY_HWA_ErrorInterruptEnable(void) +{ + AHB_OVERLAY->INTR_EN |= AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK; +} + +/** + * @brief disable error interrupt + * + */ +LOCAL_INLINE void OVERLAY_HWA_ErrorInterruptDisable(void) +{ + AHB_OVERLAY->INTR_EN &= ~((uint32_t)AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK); +} + +/** + * @brief get error flag + * + */ +LOCAL_INLINE uint32 OVERLAY_HWA_GetErrorFlag(void) +{ + return (AHB_OVERLAY->INTR_FLAG & AHB_OVERLAY_INTR_FLAG_MASK); +} + +/** + * @brief clear error flag + * + */ +LOCAL_INLINE uint32 OVERLAY_HWA_ClrErrorFlag(uint32_t u32ClrBits) +{ + return AHB_OVERLAY->INTR_CLR |= AHB_OVERLAY_INTR_FLAG_MASK & u32ClrBits; +} + + +/** @}*/ + +#endif /* _HWA_OVERLAY_H_ */ diff --git a/Inc/HwA_pcc.h b/Inc/HwA_pcc.h new file mode 100644 index 0000000..980c653 --- /dev/null +++ b/Inc/HwA_pcc.h @@ -0,0 +1,191 @@ +/** + * @file HwA_pcc.h + * @author Flagchip085 + * @brief FC7xxx PCC register API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef HWA_INCLUDE_HWA_PCC_H_ +#define HWA_INCLUDE_HWA_PCC_H_ +#include "device_header.h" + +/** + * @defgroup HwA_pcc + * @ingroup HwA_pcc + * @{ + */ + +/** @brief Marco for PCCn Bit Field definition */ +#define PCC_CGC_MASK 0x800000U +#define PCC_CGC_SHIFT 23U +#define PCC_CGC_WIDTH 1U +#define PCC_CGC(x) (((uint32_t)(((uint32_t)(x))<>PCC_CGC_SHIFT) + +#define PCC_SEL_MASK 0x700000U +#define PCC_SEL_SHIFT 20U +#define PCC_SEL_WIDTH 3U +#define PCC_SEL(x) (((uint32_t)(((uint32_t)(x))<>PCC_SEL_SHIFT) + +#define PCC_DIV_MASK 0x7U +#define PCC_DIV_SHIFT 0U +#define PCC_DIV_WIDTH 3U +#define PCC_DIV(x) (((uint32_t)(((uint32_t)(x))<>PCC_DIV_SHIFT) + +#define PCC_SWR_MASK 0x10000u + +/** + * @brief defined the clock source for function clock,match with PCC_XXX[SEL] bit filed. + */ +typedef enum +{ + PCC_CLKGATE_SRC_OFF_OR_TCLK = 0U, + PCC_CLKGATE_SRC_FOSCDIV = 1U, + PCC_CLKGATE_SRC_SIRCDIV = 2U, + PCC_CLKGATE_SRC_FIRCDIV = 3U, + PCC_CLKGATE_SRC_RESERVE0 = 4U, + PCC_CLKGATE_SRC_PLL1DIV = 5U, + PCC_CLKGATE_SRC_PLL0DIV = 6U, + PCC_CLKGATE_SRC_RESERVE1 = 7U, + PCC_CLKGATE_UNINVOLVED = 8U +} PCC_ClkGateSrcType; + +/** + * @brief define the clock divider,match with PCC_XXX[DIV] bit filed. + */ +typedef enum +{ + PCC_CLK_DIV_BY1 = 0U, /*!< Divide by 1 (pass-through, no clock divide) */ + PCC_CLK_DIV_BY2 = 1U, /*!< Divide by 2 */ + PCC_CLK_DIV_BY3 = 2U, /*!< Divide by 3 */ + PCC_CLK_DIV_BY4 = 3U, /*!< Divide by 4 */ + PCC_CLK_DIV_BY5 = 4U, /*!< Divide by 5 */ + PCC_CLK_DIV_BY6 = 5U, /*!< Divide by 6 */ + PCC_CLK_DIV_BY7 = 6U, /*!< Divide by 7 */ + PCC_CLK_DIV_BY8 = 7U, /*!< Divide by 8 */ + PCC_CLK_UNINVOLVED = 8U /*!< Current peripheral dose not contain DIV configuration */ +} PCC_ClkDivType; + + +/** + * @brief Get PCC register value + * + * @param u32Offset the PCC register offset + * @return uint32_t PCC register value + */ +LOCAL_INLINE uint32_t PCC_HWA_GetRegister(uint32_t u32Offset) +{ + return *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)); +} + +/** + * @brief Set PCC register value + * + * @param u32Offset the PCC register offset + * @param eValue value to set + */ +LOCAL_INLINE void PCC_HWA_SetRegister(uint32_t u32Offset,uint32_t eValue) +{ + *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)) = eValue; +} + +/** + * @brief Get PCC clock gate control + * + * @param u32Offset the PCC register offset + * @return bool PCC clock enabled or disabled + */ +LOCAL_INLINE bool PCC_HWA_GetClockGateControl(uint32_t u32Offset) +{ + uint32_t u32Value = *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)); + return (bool)PCC_GetCGC(u32Value); +} + +/** + * @brief Set PCC clock gate control + * + * @param u32Offset the PCC register offset + * @param eSrc PCC clock source + */ +LOCAL_INLINE void PCC_HWA_SetClockGateControl(uint32_t u32Offset,bool bEnable) +{ + uint32_t *pRegister = (uint32_t *)((uint32_t)PCC_BASE + u32Offset); + *pRegister = ((*pRegister) & (~PCC_CGC_MASK)) | PCC_CGC(bEnable); +} + +/** + * @brief Get PCC clock source + * + * @param u32Offset the PCC register offset + * @return PCC_ClkGateSrcType PCC clock source + */ +LOCAL_INLINE PCC_ClkGateSrcType PCC_HWA_GetClockSource(uint32_t u32Offset) +{ + uint32_t u32Value = *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)); + return (PCC_ClkGateSrcType)PCC_GetSEL(u32Value); +} + +/** + * @brief Set PCC clock source + * + * @param u32Offset the PCC register offset + * @param eSrc PCC clock source + */ +LOCAL_INLINE void PCC_HWA_SetClockSource(uint32_t u32Offset,PCC_ClkGateSrcType eSrc) +{ + uint32_t *pRegister = (uint32_t *)((uint32_t)PCC_BASE + u32Offset); + *pRegister = ((*pRegister) & (~PCC_SEL_MASK)) | PCC_SEL(eSrc); +} + +/** + * @brief PCC peripheral software reset + * + * @param u32Offset the PCC register offset + */ +LOCAL_INLINE void PCC_HWA_SoftwareReset(uint32_t u32Offset) +{ + *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)) |= (uint32_t)PCC_SWR_MASK; + *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)) &= ~(uint32_t)PCC_SWR_MASK; +} + +/** + * @brief Get PCC divider + * + * @param u32Offset the PCC register offset + * @return PCC_ClkDivType PCC clock divider + */ +LOCAL_INLINE PCC_ClkDivType PCC_HWA_GetDivider(uint32_t u32Offset) +{ + uint32_t u32Value = *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)); + return (PCC_ClkDivType)PCC_GetDIV(u32Value); +} + +/** + * @brief Set PCC register value + * + * @param u32Offset the PCC register offset + * @param eDivider PCC clock divider + */ +LOCAL_INLINE void PCC_HWA_SetDivider(uint32_t u32Offset,PCC_ClkDivType eDivider) +{ + uint32_t *pRegister = (uint32_t *)((uint32_t)PCC_BASE + u32Offset); + *pRegister = ((*pRegister) & (~PCC_DIV_MASK)) | PCC_DIV(eDivider); +} + + + +/** @}*/ + +#endif /* HWA_INCLUDE_HWA_PCC_H_ */ diff --git a/Inc/HwA_pmc.h b/Inc/HwA_pmc.h new file mode 100644 index 0000000..67ad751 --- /dev/null +++ b/Inc/HwA_pmc.h @@ -0,0 +1,92 @@ +/** + * @file HwA_pmc.h + * @author Flagchip0105 + * @brief FC7xxx PMC register API + * @version 0.1.0 + * @date 2024-01-08 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-08 Flagchip0105 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef HWA_INCLUDE_HWA_PMC_H_ +#define HWA_INCLUDE_HWA_PMC_H_ +#include "device_header.h" + +/** + * @defgroup HwA_pmc + * @ingroup fc7xxx_driver_pmc + * @{ + */ + +/** + * @brief get PMC LVCSR register + * + * @return uint32_t LVCSR register value + */ +LOCAL_INLINE uint32_t PMC_HWA_GetLVCSRRegister(void) +{ + return (uint32)(PMC->LVSCR); +} + +/** + * @brief set PMC LVCSR register. + * + * This function configures the PMC LVCSR registe. + * + * @param u32LvcsrValue Set PMC LVCSR register value. + */ +LOCAL_INLINE void PMC_HWA_SetLVCSRRegister(uint32_t u32LvcsrValue) +{ + PMC->LVSCR = u32LvcsrValue; +} + +/** + * @brief get PMC CONFIG register + * + * @return uint32_t CONFIG register value + */ +LOCAL_INLINE uint32_t PMC_HWA_GetConfigRegister(void) +{ + return (uint32)(PMC -> CONFIG); +} + +/** + * @brief set PMC CONFIG register. + * + * This function configures the PMC CONFIG registe. + * + * @param u32LVSCRValue Set PMC CONFIG register value. + */ +LOCAL_INLINE void PMC_HWA_SetConfigRegister(uint32_t u32LVSCRValue) +{ + PMC -> CONFIG = u32LVSCRValue; +} + +/** + * @brief Unlock control for V15_EXT_EN and V15_AUTOSW + * + */ +LOCAL_INLINE void PMC_HWA_UnlockConfigRegister(void) +{ + PMC->CONFIG &= ~(uint32_t)PMC_CONFIG_V15_LOCK_MASK; +} + +/** + * @brief lock control for V15_EXT_EN and V15_AUTOSW + * + */ +LOCAL_INLINE void PMC_HWA_LockConfigRegister(void) +{ + PMC->CONFIG |= (uint32_t)PMC_CONFIG_V15_LOCK_MASK; +} + +/** @}*/ + +#endif /* HWA_INCLUDE_HWA_PMC_H_ */ diff --git a/Inc/HwA_port.h b/Inc/HwA_port.h new file mode 100644 index 0000000..54f7288 --- /dev/null +++ b/Inc/HwA_port.h @@ -0,0 +1,2348 @@ +/** + * @file HwA_port.h + * @author Flagchip + * @brief FC7xxx PORT hardware access layer + * @version 0.1.0 + * @date 2023-02-13 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-18 Flagchip071 N/A First version for FC7xxx + ******************************************************************************** */ + +#ifndef _HWA_PORT_H_ +#define _HWA_PORT_H_ + +#include "device_header.h" + +/********* Local typedef ************/ +/** @brief Port Mode Type */ +typedef uint32_t Port_PinModeType; + +/** @brief PORTA 0 Mode enumeration */ +typedef enum +{ +PORTA_0_ADC1_SE30 = 0U, +PORTA_0_GPIO = 1U, +PORTA_0_FTU2_CH1 = 2U, +PORTA_0_AONTIMER0_CLK1 = 3U, +PORTA_0_SENT0_RXD3 = 4U, +PORTA_0_TPU_CH1 = 5U, +PORTA_0_FCUART0_CTS = 6U, +PORTA_0_TRGSEL_OUT3 = 7U, +} PORT_A0MuxType; + +/** @brief PORTA 1 Mode enumeration */ +typedef enum +{ +PORTA_1_ADC1_SE29 = 0U, +PORTA_1_GPIO = 1U, +PORTA_1_FTU1_CH1 = 2U, +PORTA_1_AONTIMER0_CLK2 = 3U, +PORTA_1_SENT0_RXD2 = 4U, +PORTA_1_FTU1_QD_PHB = 5U, +PORTA_1_FCUART0_RTS = 6U, +PORTA_1_TRGSEL_OUT0 = 7U, +} PORT_A1MuxType; + +/** @brief PORTA 10 Mode enumeration */ +typedef enum +{ +PORTA_10_GPIO = 1U, +PORTA_10_FTU1_CH4 = 2U, +PORTA_10_AONTIMER0_CLK0 = 3U, +PORTA_10_TPU_CH30 = 4U, +PORTA_10_FCIIC0_SCL = 5U, +PORTA_10_JTAG_TDO = 7U, +} PORT_A10MuxType; + +/** @brief PORTA 11 Mode enumeration */ +typedef enum +{ +PORTA_11_GPIO = 1U, +PORTA_11_FTU1_CH5 = 2U, +PORTA_11_LP_WAKEUP2 = 3U, +PORTA_11_TPU_CH29 = 4U, +PORTA_11_FCSPI0_PCS0 = 5U, +PORTA_11_NMI_b = 7U, +} PORT_A11MuxType; + +/** @brief PORTA 12 Mode enumeration */ +typedef enum +{ +PORTA_12_GPIO = 1U, +PORTA_12_FTU1_CH6 = 2U, +PORTA_12_FLEXCAN1_RX = 3U, +PORTA_12_FCSPI0_SOUT = 5U, +PORTA_12_FTU1_QD_PHB = 6U, +PORTA_12_TPU_CH9 = 7U, +} PORT_A12MuxType; + +/** @brief PORTA 13 Mode enumeration */ +typedef enum +{ +PORTA_13_ADC0_SE20 = 0U, +PORTA_13_GPIO = 1U, +PORTA_13_FTU1_CH7 = 2U, +PORTA_13_FLEXCAN1_TX = 3U, +PORTA_13_CMP1_OUT = 4U, +PORTA_13_FCUART0_RX = 5U, +PORTA_13_FTU1_QD_PHA = 6U, +PORTA_13_TPU_CH8 = 7U, +} PORT_A13MuxType; + +/** @brief PORTA 14 Mode enumeration */ +typedef enum +{ +PORTA_14_ADC0_SE21 = 0U, +PORTA_14_GPIO = 1U, +PORTA_14_FTU_FLT17 = 2U, +PORTA_14_AONTIMER0_CLK1 = 3U, +PORTA_14_FCUART0_TX = 5U, +PORTA_14_TPU_CH7 = 6U, +} PORT_A14MuxType; + +/** @brief PORTA 15 Mode enumeration */ +typedef enum +{ +PORTA_15_ADC0_SE26 = 0U, +PORTA_15_GPIO = 1U, +PORTA_15_FTU1_CH2 = 2U, +PORTA_15_TRGSEL_OUT0 = 5U, +PORTA_15_FLEXCAN3_RX = 6U, +PORTA_15_TPU_CH5 = 7U, +} PORT_A15MuxType; + +/** @brief PORTA 16 Mode enumeration */ +typedef enum +{ +PORTA_16_ADC0_SE28 = 0U, +PORTA_16_GPIO = 1U, +PORTA_16_FTU1_CH3 = 2U, +PORTA_16_FCSPI1_PCS2 = 3U, +PORTA_16_FTU1_QD_PHA = 4U, +PORTA_16_SENT0_RXD1 = 5U, +PORTA_16_FLEXCAN3_TX = 6U, +PORTA_16_TPU_CH4 = 7U, +} PORT_A16MuxType; + +/** @brief PORTA 17 Mode enumeration */ +typedef enum +{ +PORTA_17_GPIO = 1U, +PORTA_17_FTU0_CH6 = 2U, +PORTA_17_FTU7_CH0 = 3U, +PORTA_17_FLEXCAN2_TX = 4U, +PORTA_17_FCSPI5_PCS0 = 5U, +PORTA_17_FTU_FLT15 = 6U, +PORTA_17_FCUART3_RX = 7U, +} PORT_A17MuxType; + +/** @brief PORTA 18 Mode enumeration */ +typedef enum +{ +PORTA_18_GPIO = 1U, +PORTA_18_FTU4_CH0 = 2U, +PORTA_18_FCUART1_TX = 3U, +PORTA_18_TPU_CH0 = 4U, +PORTA_18_TPU_TCRCLK = 5U, +PORTA_18_FCSPI4_PCS1 = 6U, +} PORT_A18MuxType; + +/** @brief PORTA 19 Mode enumeration */ +typedef enum +{ +PORTA_19_GPIO = 1U, +PORTA_19_FTU4_CH1 = 2U, +PORTA_19_FCUART1_RX = 3U, +PORTA_19_TPU_CH1 = 4U, +PORTA_19_FCSPI4_PCS2 = 6U, +} PORT_A19MuxType; + +/** @brief PORTA 2 Mode enumeration */ +typedef enum +{ +PORTA_2_GPIO = 1U, +PORTA_2_FTU3_CH0 = 2U, +PORTA_2_FCIIC0_SDA = 3U, +PORTA_2_TPU_CH1 = 4U, +PORTA_2_FCSPI5_SOUT = 5U, +PORTA_2_FCUART0_RX = 6U, +} PORT_A2MuxType; + +/** @brief PORTA 20 Mode enumeration */ +typedef enum +{ +PORTA_20_GPIO = 1U, +PORTA_20_FTU4_CH2 = 2U, +PORTA_20_FCUART3_RTS = 3U, +PORTA_20_TPU_CH2 = 4U, +PORTA_20_FLEXCAN2_RX = 5U, +PORTA_20_FCSPI4_PCS3 = 6U, +} PORT_A20MuxType; + +/** @brief PORTA 21 Mode enumeration */ +typedef enum +{ +PORTA_21_GPIO = 1U, +PORTA_21_FTU4_CH3 = 2U, +PORTA_21_FCUART3_CTS = 3U, +PORTA_21_TPU_CH3 = 4U, +PORTA_21_FLEXCAN2_TX = 5U, +} PORT_A21MuxType; + +/** @brief PORTA 23 Mode enumeration */ +typedef enum +{ +PORTA_23_GPIO = 1U, +PORTA_23_FTU4_CH6 = 2U, +PORTA_23_FCUART3_RX = 3U, +PORTA_23_TPU_CH25 = 4U, +PORTA_23_FCSPI4_SCK = 6U, +} PORT_A23MuxType; + +/** @brief PORTA 24 Mode enumeration */ +typedef enum +{ +PORTA_24_GPIO = 1U, +PORTA_24_FTU4_CH7 = 2U, +PORTA_24_FCUART3_TX = 3U, +PORTA_24_TPU_CH4 = 4U, +PORTA_24_FCSPI4_SIN = 6U, +} PORT_A24MuxType; + +/** @brief PORTA 25 Mode enumeration */ +typedef enum +{ +PORTA_25_ADC0_SE0 = 0U, +PORTA_25_GPIO = 1U, +PORTA_25_FTU5_CH0 = 2U, +PORTA_25_FCSPI2_PCS2 = 3U, +PORTA_25_FTU2_CH5 = 4U, +PORTA_25_FCUART2_RX = 5U, +PORTA_25_TPU_TCRCLK = 6U, +PORTA_25_TPU_CH0 = 7U, +} PORT_A25MuxType; + +/** @brief PORTA 26 Mode enumeration */ +typedef enum +{ +PORTA_26_ADC0_SE2 = 0U, +PORTA_26_GPIO = 1U, +PORTA_26_FTU5_CH1 = 2U, +PORTA_26_FTU2_CH4 = 4U, +PORTA_26_FCSPI1_PCS0 = 5U, +PORTA_26_TPU_CH1 = 7U, +} PORT_A26MuxType; + +/** @brief PORTA 27 Mode enumeration */ +typedef enum +{ +PORTA_27_ADC0_SE6 = 0U, +PORTA_27_GPIO = 1U, +PORTA_27_FTU5_CH2 = 2U, +PORTA_27_FLEXCAN0_TX = 3U, +PORTA_27_FCUART0_TX = 4U, +PORTA_27_FCSPI1_SOUT = 5U, +PORTA_27_TPU_CH2 = 7U, +} PORT_A27MuxType; + +/** @brief PORTA 28 Mode enumeration */ +typedef enum +{ +PORTA_28_ADC0_SE7 = 0U, +PORTA_28_GPIO = 1U, +PORTA_28_FTU5_CH3 = 2U, +PORTA_28_FLEXCAN0_RX = 3U, +PORTA_28_FCUART0_RX = 4U, +PORTA_28_FCSPI1_SCK = 5U, +PORTA_28_TPU_CH4 = 7U, +} PORT_A28MuxType; + +/** @brief PORTA 29 Mode enumeration */ +typedef enum +{ +PORTA_29_ADC0_SE9 = 0U, +PORTA_29_GPIO = 1U, +PORTA_29_FTU5_CH4 = 2U, +PORTA_29_FCUART2_TX = 3U, +PORTA_29_FCSPI1_SIN = 5U, +PORTA_29_TPU_CH6 = 7U, +} PORT_A29MuxType; + +/** @brief PORTA 3 Mode enumeration */ +typedef enum +{ +PORTA_3_GPIO = 1U, +PORTA_3_FTU3_CH1 = 2U, +PORTA_3_FCIIC0_SCL = 3U, +PORTA_3_TPU_CH2 = 4U, +PORTA_3_FCSPI5_SCK = 5U, +PORTA_3_FCUART0_TX = 6U, +} PORT_A3MuxType; + +/** @brief PORTA 30 Mode enumeration */ +typedef enum +{ +PORTA_30_GPIO = 1U, +PORTA_30_FTU5_CH5 = 2U, +PORTA_30_FCUART2_RX = 3U, +PORTA_30_TPU_CH7 = 7U, +} PORT_A30MuxType; + +/** @brief PORTA 31 Mode enumeration */ +typedef enum +{ +PORTA_31_ADC0_SE13_CMP0_IN3 = 0U, +PORTA_31_GPIO = 1U, +PORTA_31_FTU5_CH6 = 2U, +PORTA_31_FLEXCAN3_TX = 3U, +PORTA_31_TPU_CH8 = 6U, +PORTA_31_FCSPI0_PCS1 = 7U, +} PORT_A31MuxType; + +/** @brief PORTA 4 Mode enumeration */ +typedef enum +{ +PORTA_4_GPIO = 1U, +PORTA_4_FTU1_CH0 = 2U, +PORTA_4_TRGSEL_OUT7 = 3U, +PORTA_4_CMP0_OUT = 4U, +PORTA_4_LP_WAKEUP4 = 5U, +PORTA_4_JTAG_TMS_SWD_DIO = 7U, +} PORT_A4MuxType; + +/** @brief PORTA 6 Mode enumeration */ +typedef enum +{ +PORTA_6_ADC1_SE9 = 0U, +PORTA_6_GPIO = 1U, +PORTA_6_FTU_FLT13 = 2U, +PORTA_6_FCSPI1_PCS1 = 3U, +PORTA_6_FTU5_CH5 = 4U, +PORTA_6_TRGSEL_OUT4 = 5U, +PORTA_6_FCUART1_CTS = 6U, +PORTA_6_FTU4_CH7 = 7U, +} PORT_A6MuxType; + +/** @brief PORTA 7 Mode enumeration */ +typedef enum +{ +PORTA_7_GPIO = 1U, +PORTA_7_FTU_FLT12 = 2U, +PORTA_7_FTU3_CH1 = 3U, +PORTA_7_FTU5_CH3 = 4U, +PORTA_7_FCSPI1_SCK = 5U, +PORTA_7_FCUART1_RTS = 6U, +PORTA_7_MSC0_EN0 = 7U, +} PORT_A7MuxType; + +/** @brief PORTA 8 Mode enumeration */ +typedef enum +{ +PORTA_8_ADC1_SE3 = 0U, +PORTA_8_GPIO = 1U, +PORTA_8_FCUART2_RX = 2U, +PORTA_8_FTU1_CH0 = 3U, +PORTA_8_CMP0_OUT = 4U, +PORTA_8_FTU_FLT21 = 5U, +PORTA_8_FCUART0_RX = 6U, +PORTA_8_TPU_CH13 = 7U, +} PORT_A8MuxType; + +/** @brief PORTA 9 Mode enumeration */ +typedef enum +{ +PORTA_9_ADC1_SE7 = 0U, +PORTA_9_GPIO = 1U, +PORTA_9_FCUART2_TX = 2U, +PORTA_9_FTU4_CH4 = 3U, +PORTA_9_FTU_FLT20 = 5U, +PORTA_9_FCUART0_TX = 6U, +PORTA_9_TPU_CH12 = 7U, +} PORT_A9MuxType; + +/** @brief PORTB 0 Mode enumeration */ +typedef enum +{ +PORTB_0_ADC1_SE10 = 0U, +PORTB_0_GPIO = 1U, +PORTB_0_FCUART0_RX = 2U, +PORTB_0_FCSPI0_PCS0 = 3U, +PORTB_0_FTU1_CH5 = 4U, +PORTB_0_FLEXCAN0_RX = 5U, +PORTB_0_FTU4_CH6 = 6U, +PORTB_0_MSC0_SDI1 = 7U, +} PORT_B0MuxType; + +/** @brief PORTB 1 Mode enumeration */ +typedef enum +{ +PORTB_1_ADC1_SE11 = 0U, +PORTB_1_GPIO = 1U, +PORTB_1_FCUART0_TX = 2U, +PORTB_1_FCSPI0_SOUT = 3U, +PORTB_1_FTU_TCK0 = 4U, +PORTB_1_FLEXCAN0_TX = 5U, +PORTB_1_FTU4_CH5 = 6U, +PORTB_1_MSC0_EN1 = 7U, +} PORT_B1MuxType; + +/** @brief PORTB 10 Mode enumeration */ +typedef enum +{ +PORTB_10_GPIO = 1U, +PORTB_10_FTU3_CH2 = 2U, +PORTB_10_FLEXCAN0_TX = 3U, +PORTB_10_SENT0_RXD0 = 4U, +PORTB_10_TRGSEL_OUT2 = 5U, +PORTB_10_TPU_CH0 = 6U, +PORTB_10_TPU_TCRCLK = 7U, +} PORT_B10MuxType; + +/** @brief PORTB 11 Mode enumeration */ +typedef enum +{ +PORTB_11_V15_BASE_DRIVER = 0U, +PORTB_11_GPIO = 1U, +PORTB_11_FTU6_CH0 = 2U, +PORTB_11_FCUART2_TX = 3U, +PORTB_11_FLEXCAN0_TX = 4U, +} PORT_B11MuxType; + +/** @brief PORTB 12 Mode enumeration */ +typedef enum +{ +PORTB_12_GPIO = 1U, +PORTB_12_FTU0_CH0 = 2U, +PORTB_12_TPU_CH26 = 5U, +PORTB_12_FCSMU_PIN0 = 7U, +} PORT_B12MuxType; + +/** @brief PORTB 13 Mode enumeration */ +typedef enum +{ +PORTB_13_GPIO = 1U, +PORTB_13_FTU0_CH1 = 2U, +PORTB_13_FCUART6_CTS = 4U, +PORTB_13_TPU_CH25 = 5U, +PORTB_13_FCSMU_PIN1 = 7U, +} PORT_B13MuxType; + +/** @brief PORTB 14 Mode enumeration */ +typedef enum +{ +PORTB_14_ADC1_SE18 = 0U, +PORTB_14_GPIO = 1U, +PORTB_14_FTU0_CH2 = 2U, +PORTB_14_FCSPI1_SCK = 3U, +PORTB_14_TPU_CH5 = 4U, +PORTB_14_FTU5_CH4 = 6U, +PORTB_14_FLEXCAN2_RX = 7U, +} PORT_B14MuxType; + +/** @brief PORTB 15 Mode enumeration */ +typedef enum +{ +PORTB_15_ADC1_SE17 = 0U, +PORTB_15_GPIO = 1U, +PORTB_15_FTU0_CH3 = 2U, +PORTB_15_FCSPI1_SIN = 3U, +PORTB_15_TPU_CH6 = 4U, +PORTB_15_FTU5_CH5 = 6U, +PORTB_15_FLEXCAN2_TX = 7U, +} PORT_B15MuxType; + +/** @brief PORTB 16 Mode enumeration */ +typedef enum +{ +PORTB_16_ADC1_SE16 = 0U, +PORTB_16_GPIO = 1U, +PORTB_16_FTU0_CH4 = 2U, +PORTB_16_FCSPI1_SOUT = 3U, +PORTB_16_TPU_CH7 = 4U, +PORTB_16_FTU5_CH6 = 6U, +} PORT_B16MuxType; + +/** @brief PORTB 17 Mode enumeration */ +typedef enum +{ +PORTB_17_GPIO = 1U, +PORTB_17_FTU0_CH5 = 2U, +PORTB_17_FCSPI1_PCS3 = 3U, +PORTB_17_FLEXCAN2_RX = 4U, +PORTB_17_TRGSEL_OUT3 = 5U, +PORTB_17_FTU5_CH7 = 6U, +PORTB_17_FCUART3_TX = 7U, +} PORT_B17MuxType; + +/** @brief PORTB 18 Mode enumeration */ +typedef enum +{ +PORTB_18_GPIO = 1U, +PORTB_18_FTU5_CH7 = 2U, +PORTB_18_FLEXCAN3_RX = 3U, +PORTB_18_FCSPI4_PCS2 = 4U, +PORTB_18_FCSPI1_PCS1 = 5U, +PORTB_18_TPU_CH9 = 6U, +} PORT_B18MuxType; + +/** @brief PORTB 19 Mode enumeration */ +typedef enum +{ +PORTB_19_CMP0_IN4 = 0U, +PORTB_19_GPIO = 1U, +PORTB_19_FTU6_CH2 = 2U, +PORTB_19_FCUART4_RX = 3U, +PORTB_19_FLEXCAN3_TX = 4U, +PORTB_19_TPU_CH5 = 6U, +} PORT_B19MuxType; + +/** @brief PORTB 20 Mode enumeration */ +typedef enum +{ +PORTB_20_ADC0_SE14 = 0U, +PORTB_20_GPIO = 1U, +PORTB_20_FTU2_CH5 = 2U, +PORTB_20_FCUART1_TX = 3U, +PORTB_20_FTU6_CH2 = 4U, +PORTB_20_TPU_CH10 = 6U, +PORTB_20_SCG_CLKOUT = 7U, +} PORT_B20MuxType; + +/** @brief PORTB 21 Mode enumeration */ +typedef enum +{ +PORTB_21_ADC0_SE15 = 0U, +PORTB_21_GPIO = 1U, +PORTB_21_FTU2_CH4 = 2U, +PORTB_21_FCUART1_RX = 3U, +PORTB_21_FTU6_CH3 = 4U, +PORTB_21_TPU_CH11 = 6U, +} PORT_B21MuxType; + +/** @brief PORTB 22 Mode enumeration */ +typedef enum +{ +PORTB_22_GPIO = 1U, +PORTB_22_FTU_FLT8 = 2U, +PORTB_22_FLEXCAN2_TX = 3U, +PORTB_22_TPU_CH12 = 4U, +PORTB_22_FTU6_CH6 = 5U, +PORTB_22_MSC0_EN0 = 6U, +PORTB_22_FCSPI3_PCS1 = 7U, +} PORT_B22MuxType; + +/** @brief PORTB 23 Mode enumeration */ +typedef enum +{ +PORTB_23_CMP1_IN6 = 0U, +PORTB_23_GPIO = 1U, +PORTB_23_FTU_FLT9 = 2U, +PORTB_23_FCUART1_RX = 3U, +PORTB_23_FTU4_CH7 = 4U, +PORTB_23_FTU7_CH7 = 5U, +PORTB_23_TPU_CH13 = 6U, +PORTB_23_MSC0_FCLP = 7U, +} PORT_B23MuxType; + +/** @brief PORTB 24 Mode enumeration */ +typedef enum +{ +PORTB_24_CMP0_IN5 = 0U, +PORTB_24_GPIO = 1U, +PORTB_24_FTU6_CH3 = 2U, +PORTB_24_FCUART4_TX = 3U, +PORTB_24_FLEXCAN3_RX = 4U, +PORTB_24_TPU_CH6 = 6U, +} PORT_B24MuxType; + +/** @brief PORTB 25 Mode enumeration */ +typedef enum +{ +PORTB_25_GPIO = 1U, +PORTB_25_FTU1_CH2 = 2U, +PORTB_25_FTU1_QD_PHB = 3U, +PORTB_25_FCSPI2_PCS0 = 4U, +PORTB_25_FTU6_CH7 = 5U, +PORTB_25_FCUART3_TX = 6U, +} PORT_B25MuxType; + +/** @brief PORTB 26 Mode enumeration */ +typedef enum +{ +PORTB_26_CMP0_IN6 = 0U, +PORTB_26_GPIO = 1U, +PORTB_26_FTU6_CH4 = 2U, +PORTB_26_FCSPI3_SCK = 3U, +PORTB_26_FCUART3_TX = 4U, +PORTB_26_TPU_CH7 = 6U, +} PORT_B26MuxType; + +/** @brief PORTB 27 Mode enumeration */ +typedef enum +{ +PORTB_27_GPIO = 1U, +PORTB_27_FTU7_CH5 = 2U, +PORTB_27_FTU2_CH2 = 3U, +PORTB_27_FCSPI2_SOUT = 4U, +PORTB_27_FCUART5_RTS = 5U, +PORTB_27_TPU_CH14 = 6U, +} PORT_B27MuxType; + +/** @brief PORTB 28 Mode enumeration */ +typedef enum +{ +PORTB_28_GPIO = 1U, +PORTB_28_FTU7_CH4 = 2U, +PORTB_28_FTU2_CH1 = 3U, +PORTB_28_FCSPI2_SIN = 4U, +PORTB_28_FCUART5_CTS = 5U, +PORTB_28_TPU_CH15 = 6U, +} PORT_B28MuxType; + +/** @brief PORTB 29 Mode enumeration */ +typedef enum +{ +PORTB_29_GPIO = 1U, +PORTB_29_FTU1_CH0 = 2U, +PORTB_29_FCUART5_TX = 3U, +PORTB_29_FCSPI2_SCK = 4U, +PORTB_29_FTU1_QD_PHB = 5U, +PORTB_29_FCUART7_RTS = 6U, +PORTB_29_TPU_CH16 = 7U, +} PORT_B29MuxType; + +/** @brief PORTB 3 Mode enumeration */ +typedef enum +{ +PORTB_3_GPIO = 1U, +PORTB_3_FTU1_CH1 = 2U, +PORTB_3_FCSPI0_SIN = 3U, +PORTB_3_FTU1_QD_PHA = 4U, +PORTB_3_FTU7_CH3 = 5U, +PORTB_3_TPU_CH10 = 6U, +PORTB_3_FCUART5_RX = 7U, +} PORT_B3MuxType; + +/** @brief PORTB 30 Mode enumeration */ +typedef enum +{ +PORTB_30_CMP0_IN7 = 0U, +PORTB_30_GPIO = 1U, +PORTB_30_FTU6_CH5 = 2U, +PORTB_30_FCSPI3_SIN = 3U, +PORTB_30_FCUART3_RX = 4U, +PORTB_30_TPU_CH8 = 6U, +} PORT_B30MuxType; + +/** @brief PORTB 31 Mode enumeration */ +typedef enum +{ +PORTB_31_CMP1_IN0 = 0U, +PORTB_31_GPIO = 1U, +PORTB_31_FTU7_CH7 = 2U, +PORTB_31_FCSPI3_SOUT = 3U, +PORTB_31_FCUART5_TX = 4U, +PORTB_31_TPU_CH9 = 5U, +} PORT_B31MuxType; + +/** @brief PORTB 4 Mode enumeration */ +typedef enum +{ +PORTB_4_GPIO = 1U, +PORTB_4_FTU0_CH4 = 2U, +PORTB_4_FCIIC1_SDA = 3U, +PORTB_4_FCSPI4_SOUT = 4U, +PORTB_4_FTU7_CH6 = 5U, +PORTB_4_ETM_TRACE_D6 = 6U, +PORTB_4_TRGSEL_OUT4 = 7U, +} PORT_B4MuxType; + +/** @brief PORTB 5 Mode enumeration */ +typedef enum +{ +PORTB_5_GPIO = 1U, +PORTB_5_FTU0_CH5 = 2U, +PORTB_5_FCIIC1_SCL = 3U, +PORTB_5_FCSPI4_PCS0 = 4U, +PORTB_5_SCG_CLKOUT = 5U, +PORTB_5_ETM_TRACE_D5 = 6U, +PORTB_5_TRGSEL_OUT5 = 7U, +} PORT_B5MuxType; + +/** @brief PORTB 6 Mode enumeration */ +typedef enum +{ +PORTB_6_XTAL = 0U, +PORTB_6_GPIO = 1U, +PORTB_6_FCIIC0_SDA = 2U, +} PORT_B6MuxType; + +/** @brief PORTB 7 Mode enumeration */ +typedef enum +{ +PORTB_7_EXTAL = 0U, +PORTB_7_GPIO = 1U, +PORTB_7_FCIIC0_SCL = 2U, +} PORT_B7MuxType; + +/** @brief PORTB 8 Mode enumeration */ +typedef enum +{ +PORTB_8_ADC1_SE28 = 0U, +PORTB_8_GPIO = 1U, +PORTB_8_FTU3_CH0 = 2U, +PORTB_8_FLEXCAN0_RX = 3U, +PORTB_8_SENT0_RXD1 = 4U, +PORTB_8_TPU_CH0 = 5U, +PORTB_8_FCUART1_CTS = 6U, +} PORT_B8MuxType; + +/** @brief PORTB 9 Mode enumeration */ +typedef enum +{ +PORTB_9_ADC1_SE25 = 0U, +PORTB_9_GPIO = 1U, +PORTB_9_FTU3_CH1 = 2U, +PORTB_9_FTU1_CH6 = 3U, +PORTB_9_TRGSEL_OUT1 = 5U, +PORTB_9_TPU_CH29 = 6U, +PORTB_9_FCSPI5_PCS0 = 7U, +} PORT_B9MuxType; + +/** @brief PORTC 0 Mode enumeration */ +typedef enum +{ +PORTC_0_GPIO = 1U, +PORTC_0_FTU0_CH0 = 2U, +PORTC_0_FLEXCAN2_RX = 3U, +PORTC_0_TPU_CH15 = 4U, +PORTC_0_FlexCore_TCLK = 5U, +PORTC_0_FTU1_CH6 = 6U, +PORTC_0_FCSPI3_PCS2 = 7U, +} PORT_C0MuxType; + +/** @brief PORTC 1 Mode enumeration */ +typedef enum +{ +PORTC_1_GPIO = 1U, +PORTC_1_FTU0_CH1 = 2U, +PORTC_1_TPU_CH16 = 3U, +PORTC_1_FCSPI2_SOUT = 4U, +PORTC_1_FlexCore_TDI = 5U, +PORTC_1_FTU1_CH7 = 6U, +PORTC_1_FCUART3_TX = 7U, +} PORT_C1MuxType; + +/** @brief PORTC 10 Mode enumeration */ +typedef enum +{ +PORTC_10_ADC1_SE12 = 0U, +PORTC_10_GPIO = 1U, +PORTC_10_FTU3_CH4 = 2U, +PORTC_10_FTU0_CH5 = 3U, +PORTC_10_FCUART6_RX = 4U, +PORTC_10_FTU7_CH1 = 6U, +PORTC_10_TPU_CH8 = 7U, +} PORT_C10MuxType; + +/** @brief PORTC 11 Mode enumeration */ +typedef enum +{ +PORTC_11_ADC1_SE13 = 0U, +PORTC_11_GPIO = 1U, +PORTC_11_FTU3_CH5 = 2U, +PORTC_11_FTU4_CH2 = 3U, +PORTC_11_FCUART6_TX = 4U, +PORTC_11_FCSPI1_PCS0 = 5U, +PORTC_11_FTU7_CH2 = 6U, +PORTC_11_TPU_CH9 = 7U, +} PORT_C11MuxType; + +/** @brief PORTC 12 Mode enumeration */ +typedef enum +{ +PORTC_12_ADC1_SE14 = 0U, +PORTC_12_GPIO = 1U, +PORTC_12_FTU3_CH6 = 2U, +PORTC_12_FTU2_CH6 = 3U, +PORTC_12_FCUART2_CTS = 4U, +PORTC_12_TRGSEL_OUT5 = 5U, +PORTC_12_FCUART7_RX = 6U, +PORTC_12_MSC0_SOP = 7U, +} PORT_C12MuxType; + +/** @brief PORTC 13 Mode enumeration */ +typedef enum +{ +PORTC_13_ADC1_SE15 = 0U, +PORTC_13_GPIO = 1U, +PORTC_13_FTU3_CH7 = 2U, +PORTC_13_FTU2_CH7 = 3U, +PORTC_13_FCUART2_RTS = 4U, +PORTC_13_TRGSEL_OUT6 = 5U, +PORTC_13_FCUART7_TX = 6U, +PORTC_13_MSC0_FCLP = 7U, +} PORT_C13MuxType; + +/** @brief PORTC 14 Mode enumeration */ +typedef enum +{ +PORTC_14_CMP1_IN7 = 0U, +PORTC_14_GPIO = 1U, +PORTC_14_FTU1_CH2 = 2U, +PORTC_14_TPU_CH11 = 3U, +PORTC_14_FCSPI2_PCS0 = 4U, +PORTC_14_FTU1_QD_PHA = 5U, +PORTC_14_TRGSEL_OUT6 = 6U, +} PORT_C14MuxType; + +/** @brief PORTC 15 Mode enumeration */ +typedef enum +{ +PORTC_15_CMP1_IN5 = 0U, +PORTC_15_GPIO = 1U, +PORTC_15_FTU1_CH3 = 2U, +PORTC_15_TPU_CH12 = 3U, +PORTC_15_FCSPI2_SCK = 4U, +PORTC_15_FTU6_CH1 = 5U, +PORTC_15_TRGSEL_OUT7 = 6U, +PORTC_15_FCUART5_TX = 7U, +} PORT_C15MuxType; + +/** @brief PORTC 16 Mode enumeration */ +typedef enum +{ +PORTC_16_CMP1_IN4 = 0U, +PORTC_16_GPIO = 1U, +PORTC_16_FTU_FLT7 = 2U, +PORTC_16_FTU4_CH0 = 3U, +PORTC_16_FCSPI2_SIN = 4U, +PORTC_16_FTU7_CH4 = 5U, +PORTC_16_TPU_CH13 = 6U, +PORTC_16_FCUART5_RX = 7U, +} PORT_C16MuxType; + +/** @brief PORTC 17 Mode enumeration */ +typedef enum +{ +PORTC_17_DEBUGMUX_P1 = 0U, +PORTC_17_GPIO = 1U, +PORTC_17_FTU_FLT6 = 2U, +PORTC_17_FTU4_CH1 = 3U, +PORTC_17_FCSPI2_PCS3 = 4U, +PORTC_17_FTU6_CH2 = 5U, +PORTC_17_TPU_CH14 = 6U, +PORTC_17_FCUART4_TX = 7U, +} PORT_C17MuxType; + +/** @brief PORTC 18 Mode enumeration */ +typedef enum +{ +PORTC_18_CMP1_IN1 = 0U, +PORTC_18_GPIO = 1U, +PORTC_18_FTU7_CH6 = 2U, +PORTC_18_FCSPI3_PCS0 = 3U, +PORTC_18_FCUART5_RX = 4U, +PORTC_18_TPU_CH10 = 5U, +} PORT_C18MuxType; + +/** @brief PORTC 19 Mode enumeration */ +typedef enum +{ +PORTC_19_GPIO = 1U, +PORTC_19_FTU7_CH3 = 2U, +PORTC_19_FCSPI2_PCS1 = 4U, +PORTC_19_TPU_CH17 = 5U, +PORTC_19_FCUART3_RX = 6U, +} PORT_C19MuxType; + +/** @brief PORTC 2 Mode enumeration */ +typedef enum +{ +PORTC_2_DEBUGMUX_P2 = 0U, +PORTC_2_GPIO = 1U, +PORTC_2_FTU0_CH2 = 2U, +PORTC_2_FLEXCAN0_RX = 3U, +PORTC_2_FCUART0_RX = 4U, +PORTC_2_FTU5_CH4 = 5U, +PORTC_2_ETM_TRACE_CLKOUT = 6U, +PORTC_2_FCSPI0_PCS2 = 7U, +} PORT_C2MuxType; + +/** @brief PORTC 20 Mode enumeration */ +typedef enum +{ +PORTC_20_GPIO = 1U, +PORTC_20_FTU7_CH2 = 2U, +PORTC_20_FCSPI2_SCK = 4U, +PORTC_20_FCUART3_RTS = 5U, +PORTC_20_TPU_CH12 = 6U, +PORTC_20_MSC0_FCLP = 7U, +} PORT_C20MuxType; + +/** @brief PORTC 21 Mode enumeration */ +typedef enum +{ +PORTC_21_GPIO = 1U, +PORTC_21_FTU7_CH1 = 2U, +PORTC_21_FCSPI2_SIN = 4U, +PORTC_21_FCUART3_CTS = 5U, +PORTC_21_TPU_CH13 = 6U, +PORTC_21_MSC0_SOP = 7U, +} PORT_C21MuxType; + +/** @brief PORTC 22 Mode enumeration */ +typedef enum +{ +PORTC_22_GPIO = 1U, +PORTC_22_FTU6_CH4 = 2U, +PORTC_22_FCSPI0_SCK = 3U, +PORTC_22_FCUART5_RX = 4U, +PORTC_22_FTU7_CH6 = 5U, +PORTC_22_TPU_CH18 = 6U, +PORTC_22_MSC0_EN2 = 7U, +} PORT_C22MuxType; + +/** @brief PORTC 23 Mode enumeration */ +typedef enum +{ +PORTC_23_GPIO = 1U, +PORTC_23_FTU7_CH0 = 2U, +PORTC_23_FCUART6_TX = 3U, +PORTC_23_FCSPI2_SOUT = 4U, +PORTC_23_TPU_CH14 = 6U, +PORTC_23_MSC0_EN3 = 7U, +} PORT_C23MuxType; + +/** @brief PORTC 24 Mode enumeration */ +typedef enum +{ +PORTC_24_GPIO = 1U, +PORTC_24_FTU4_CH3 = 2U, +PORTC_24_FCUART6_RX = 3U, +PORTC_24_FCSPI2_PCS0 = 4U, +PORTC_24_TPU_CH15 = 6U, +PORTC_24_MSC0_SDI2 = 7U, +} PORT_C24MuxType; + +/** @brief PORTC 25 Mode enumeration */ +typedef enum +{ +PORTC_25_ADC1_SE20 = 0U, +PORTC_25_GPIO = 1U, +PORTC_25_FTU4_CH1 = 2U, +PORTC_25_FCUART5_RTS = 3U, +PORTC_25_FCUART6_TX = 4U, +PORTC_25_FTU0_CH6 = 5U, +PORTC_25_SENT0_RXD0 = 6U, +PORTC_25_FCSPI4_SCK = 7U, +} PORT_C25MuxType; + +/** @brief PORTC 26 Mode enumeration */ +typedef enum +{ +PORTC_26_ADC1_SE21 = 0U, +PORTC_26_GPIO = 1U, +PORTC_26_FTU4_CH0 = 2U, +PORTC_26_FCUART5_CTS = 3U, +PORTC_26_FCUART6_RX = 4U, +PORTC_26_FTU1_CH4 = 5U, +PORTC_26_SENT0_RXD1 = 6U, +PORTC_26_FCSPI4_PCS0 = 7U, +} PORT_C26MuxType; + +/** @brief PORTC 27 Mode enumeration */ +typedef enum +{ +PORTC_27_GPIO = 1U, +PORTC_27_FTU4_CH4 = 2U, +PORTC_27_FTU3_CH3 = 3U, +PORTC_27_FCSPI4_SOUT = 4U, +PORTC_27_TPU_CH19 = 6U, +PORTC_27_MSC0_EN0 = 7U, +} PORT_C27MuxType; + +/** @brief PORTC 28 Mode enumeration */ +typedef enum +{ +PORTC_28_GPIO = 1U, +PORTC_28_FTU4_CH7 = 2U, +PORTC_28_FLEXCAN3_TX = 3U, +PORTC_28_FTU3_CH2 = 4U, +PORTC_28_TPU_CH20 = 6U, +PORTC_28_MSC0_SDI0 = 7U, +} PORT_C28MuxType; + +/** @brief PORTC 29 Mode enumeration */ +typedef enum +{ +PORTC_29_GPIO = 1U, +PORTC_29_FTU5_CH2 = 2U, +PORTC_29_FLEXCAN3_RX = 3U, +PORTC_29_FCSPI4_SIN = 4U, +PORTC_29_TPU_CH21 = 6U, +} PORT_C29MuxType; + +/** @brief PORTC 3 Mode enumeration */ +typedef enum +{ +PORTC_3_GPIO = 1U, +PORTC_3_FTU0_CH3 = 2U, +PORTC_3_FLEXCAN0_TX = 3U, +PORTC_3_FCUART0_TX = 4U, +PORTC_3_FTU5_CH2 = 5U, +PORTC_3_ETM_TRACE_D7 = 6U, +PORTC_3_FCSPI0_SOUT = 7U, +} PORT_C3MuxType; + +/** @brief PORTC 30 Mode enumeration */ +typedef enum +{ +PORTC_30_GPIO = 1U, +PORTC_30_FTU5_CH4 = 2U, +PORTC_30_FTU3_CH0 = 3U, +PORTC_30_FCSPI4_PCS0 = 4U, +PORTC_30_TPU_CH22 = 6U, +} PORT_C30MuxType; + +/** @brief PORTC 31 Mode enumeration */ +typedef enum +{ +PORTC_31_GPIO = 1U, +PORTC_31_FTU5_CH6 = 2U, +PORTC_31_FTU3_CH4 = 3U, +PORTC_31_FCIIC1_SDA = 4U, +PORTC_31_FLEXCAN1_RX = 5U, +PORTC_31_TPU_CH23 = 6U, +} PORT_C31MuxType; + +/** @brief PORTC 4 Mode enumeration */ +typedef enum +{ +PORTC_4_GPIO = 1U, +PORTC_4_JTAG_TCLK_SWD_CLK = 7U, +} PORT_C4MuxType; + +/** @brief PORTC 5 Mode enumeration */ +typedef enum +{ +PORTC_5_GPIO = 1U, +PORTC_5_FTU2_CH0 = 2U, +PORTC_5_RTC_CLKOUT = 3U, +PORTC_5_CMP1_OUT = 4U, +PORTC_5_FCIIC0_SDA = 5U, +PORTC_5_FTU2_QD_PHB = 6U, +PORTC_5_JTAG_TDI = 7U, +} PORT_C5MuxType; + +/** @brief PORTC 6 Mode enumeration */ +typedef enum +{ +PORTC_6_ADC0_SE29 = 0U, +PORTC_6_GPIO = 1U, +PORTC_6_FCUART1_RX = 2U, +PORTC_6_FLEXCAN1_RX = 3U, +PORTC_6_FTU3_CH2 = 4U, +PORTC_6_SENT0_RXD0 = 5U, +PORTC_6_TPU_CH3 = 6U, +} PORT_C6MuxType; + +/** @brief PORTC 7 Mode enumeration */ +typedef enum +{ +PORTC_7_ADC0_SE30 = 0U, +PORTC_7_GPIO = 1U, +PORTC_7_FCUART1_TX = 2U, +PORTC_7_FLEXCAN1_TX = 3U, +PORTC_7_FTU3_CH3 = 4U, +PORTC_7_TPU_CH2 = 6U, +} PORT_C7MuxType; + +/** @brief PORTC 8 Mode enumeration */ +typedef enum +{ +PORTC_8_GPIO = 1U, +PORTC_8_FCUART1_RX = 2U, +PORTC_8_FTU_FLT11 = 3U, +PORTC_8_FTU5_CH1 = 4U, +PORTC_8_FCSPI1_SIN = 5U, +PORTC_8_FCUART0_CTS = 6U, +PORTC_8_MSC0_EN1 = 7U, +} PORT_C8MuxType; + +/** @brief PORTC 9 Mode enumeration */ +typedef enum +{ +PORTC_9_GPIO = 1U, +PORTC_9_FCUART1_TX = 2U, +PORTC_9_FTU_FLT10 = 3U, +PORTC_9_FTU5_CH0 = 4U, +PORTC_9_FCSPI1_SOUT = 5U, +PORTC_9_FCUART0_RTS = 6U, +PORTC_9_FCUART5_TX = 7U, +} PORT_C9MuxType; + +/** @brief PORTD 0 Mode enumeration */ +typedef enum +{ +PORTD_0_ADC1_SE1 = 0U, +PORTD_0_GPIO = 1U, +PORTD_0_FTU0_CH2 = 2U, +PORTD_0_FTU2_CH0 = 3U, +PORTD_0_FCSPI1_SCK = 4U, +PORTD_0_TPU_CH28 = 5U, +PORTD_0_ETM_TRACE_D0 = 6U, +PORTD_0_TRGSEL_OUT1 = 7U, +} PORT_D0MuxType; + +/** @brief PORTD 1 Mode enumeration */ +typedef enum +{ +PORTD_1_ADC1_SE5 = 0U, +PORTD_1_GPIO = 1U, +PORTD_1_FTU0_CH3 = 2U, +PORTD_1_FTU2_CH1 = 3U, +PORTD_1_FCSPI1_SIN = 4U, +PORTD_1_TPU_CH29 = 5U, +PORTD_1_TRGSEL_OUT2 = 7U, +} PORT_D1MuxType; + +/** @brief PORTD 10 Mode enumeration */ +typedef enum +{ +PORTD_10_GPIO = 1U, +PORTD_10_FTU2_CH0 = 2U, +PORTD_10_FTU2_QD_PHB = 3U, +PORTD_10_SCG_CLKOUT = 4U, +PORTD_10_FlexCore_TMS = 5U, +PORTD_10_ETM_TRACE_D3 = 6U, +PORTD_10_FCSPI3_PCS3 = 7U, +} PORT_D10MuxType; + +/** @brief PORTD 11 Mode enumeration */ +typedef enum +{ +PORTD_11_GPIO = 1U, +PORTD_11_FTU2_CH1 = 2U, +PORTD_11_FTU2_QD_PHA = 3U, +PORTD_11_FCSPI4_PCS1 = 4U, +PORTD_11_FCUART2_CTS = 5U, +PORTD_11_ETM_TRACE_D2 = 6U, +PORTD_11_FCSPI3_PCS0 = 7U, +} PORT_D11MuxType; + +/** @brief PORTD 12 Mode enumeration */ +typedef enum +{ +PORTD_12_GPIO = 1U, +PORTD_12_FTU2_CH2 = 2U, +PORTD_12_FCUART4_RX = 3U, +PORTD_12_FTU6_CH7 = 4U, +PORTD_12_FCUART2_RTS = 5U, +PORTD_12_ETM_TRACE_D1 = 6U, +PORTD_12_FCSPI3_SOUT = 7U, +} PORT_D12MuxType; + +/** @brief PORTD 13 Mode enumeration */ +typedef enum +{ +PORTD_13_GPIO = 1U, +PORTD_13_FTU6_CH3 = 2U, +PORTD_13_FCUART1_TX = 3U, +PORTD_13_TPU_CH11 = 4U, +PORTD_13_FCUART7_CTS = 6U, +PORTD_13_MSC0_SOP = 7U, +} PORT_D13MuxType; + +/** @brief PORTD 15 Mode enumeration */ +typedef enum +{ +PORTD_15_ADC0_SE11_CMP0_IN1 = 0U, +PORTD_15_GPIO = 1U, +PORTD_15_FTU0_CH0 = 2U, +PORTD_15_FCUART2_RTS = 3U, +PORTD_15_TPU_CH18 = 4U, +PORTD_15_ETM_TRACE_D3 = 6U, +PORTD_15_FCSPI0_SCK = 7U, +} PORT_D15MuxType; + +/** @brief PORTD 16 Mode enumeration */ +typedef enum +{ +PORTD_16_ADC0_SE10_CMP0_IN0 = 0U, +PORTD_16_GPIO = 1U, +PORTD_16_FTU0_CH1 = 2U, +PORTD_16_TPU_CH19 = 4U, +PORTD_16_ETM_TRACE_D2 = 6U, +PORTD_16_FCSPI0_SIN = 7U, +} PORT_D16MuxType; + +/** @brief PORTD 17 Mode enumeration */ +typedef enum +{ +PORTD_17_ADC0_SE8 = 0U, +PORTD_17_GPIO = 1U, +PORTD_17_FTU6_CH1 = 2U, +PORTD_17_FCUART7_RX = 3U, +PORTD_17_FTU_FLT3 = 4U, +PORTD_17_FCSPI4_PCS0 = 6U, +PORTD_17_TPU_CH5 = 7U, +} PORT_D17MuxType; + +/** @brief PORTD 18 Mode enumeration */ +typedef enum +{ +PORTD_18_GPIO = 1U, +PORTD_18_FTU5_CH7 = 2U, +PORTD_18_FTU3_CH5 = 3U, +PORTD_18_FCSPI4_SCK = 4U, +PORTD_18_TPU_CH24 = 6U, +} PORT_D18MuxType; + +/** @brief PORTD 19 Mode enumeration */ +typedef enum +{ +PORTD_19_GPIO = 1U, +PORTD_19_FTU6_CH0 = 2U, +PORTD_19_FCSPI1_PCS2 = 3U, +PORTD_19_FCIIC1_SCL = 4U, +PORTD_19_FLEXCAN1_TX = 5U, +PORTD_19_SENT0_RXD2 = 6U, +} PORT_D19MuxType; + +/** @brief PORTD 2 Mode enumeration */ +typedef enum +{ +PORTD_2_GPIO = 1U, +PORTD_2_FTU3_CH4 = 2U, +PORTD_2_FTU6_CH5 = 3U, +PORTD_2_FCUART6_RX = 4U, +PORTD_2_FCSPI5_PCS2 = 5U, +PORTD_2_FTU1_CH1 = 6U, +PORTD_2_ISP_EN_B = 7U, +} PORT_D2MuxType; + +/** @brief PORTD 20 Mode enumeration */ +typedef enum +{ +PORTD_20_GPIO = 1U, +PORTD_20_FTU6_CH2 = 2U, +PORTD_20_FCUART5_RX = 3U, +PORTD_20_TPU_CH16 = 4U, +PORTD_20_SENT0_RXD2 = 6U, +PORTD_20_FCSPI4_SIN = 7U, +} PORT_D20MuxType; + +/** @brief PORTD 21 Mode enumeration */ +typedef enum +{ +PORTD_21_ADC1_SE22 = 0U, +PORTD_21_GPIO = 1U, +PORTD_21_FTU6_CH3 = 2U, +PORTD_21_FCUART5_TX = 3U, +PORTD_21_TPU_CH17 = 4U, +PORTD_21_SENT0_RXD3 = 6U, +PORTD_21_FCSPI4_SOUT = 7U, +} PORT_D21MuxType; + +/** @brief PORTD 22 Mode enumeration */ +typedef enum +{ +PORTD_22_ADC1_SE19 = 0U, +PORTD_22_GPIO = 1U, +PORTD_22_FTU6_CH1 = 2U, +PORTD_22_FTU0_CH1 = 3U, +PORTD_22_TPU_TCRCLK = 4U, +PORTD_22_FCSPI5_PCS3 = 5U, +PORTD_22_FLEXCAN1_RX = 6U, +} PORT_D22MuxType; + +/** @brief PORTD 23 Mode enumeration */ +typedef enum +{ +PORTD_23_GPIO = 1U, +PORTD_23_FTU6_CH5 = 2U, +PORTD_23_FLEXCAN3_TX = 4U, +PORTD_23_TPU_CH27 = 5U, +PORTD_23_FTU1_CH0 = 6U, +} PORT_D23MuxType; + +/** @brief PORTD 24 Mode enumeration */ +typedef enum +{ +PORTD_24_GPIO = 1U, +PORTD_24_FTU3_CH3 = 2U, +PORTD_24_TPU_CH28 = 3U, +PORTD_24_FCUART6_RTS = 4U, +PORTD_24_FCSPI5_PCS1 = 5U, +PORTD_24_FLEXCAN1_TX = 6U, +} PORT_D24MuxType; + +/** @brief PORTD 25 Mode enumeration */ +typedef enum +{ +PORTD_25_ADC1_SE24 = 0U, +PORTD_25_GPIO = 1U, +PORTD_25_FTU6_CH6 = 2U, +PORTD_25_FTU0_CH0 = 3U, +PORTD_25_FCUART4_RTS = 4U, +PORTD_25_TPU_CH18 = 6U, +PORTD_25_FCSPI5_SCK = 7U, +} PORT_D25MuxType; + +/** @brief PORTD 26 Mode enumeration */ +typedef enum +{ +PORTD_26_ADC1_SE26 = 0U, +PORTD_26_GPIO = 1U, +PORTD_26_FTU6_CH7 = 2U, +PORTD_26_FTU3_CH7 = 3U, +PORTD_26_FCUART4_CTS = 4U, +PORTD_26_SENT0_RXD3 = 5U, +PORTD_26_TPU_CH19 = 6U, +PORTD_26_FCSPI5_SIN = 7U, +} PORT_D26MuxType; + +/** @brief PORTD 27 Mode enumeration */ +typedef enum +{ +PORTD_27_ADC1_SE27 = 0U, +PORTD_27_GPIO = 1U, +PORTD_27_FTU7_CH0 = 2U, +PORTD_27_FCUART6_TX = 3U, +PORTD_27_FLEXCAN3_RX = 4U, +PORTD_27_TPU_CH30 = 6U, +} PORT_D27MuxType; + +/** @brief PORTD 28 Mode enumeration */ +typedef enum +{ +PORTD_28_GPIO = 1U, +PORTD_28_FTU7_CH1 = 2U, +PORTD_28_FCUART6_RX = 3U, +PORTD_28_TPU_CH31 = 6U, +PORTD_28_FCSPI5_PCS1 = 7U, +} PORT_D28MuxType; + +/** @brief PORTD 29 Mode enumeration */ +typedef enum +{ +PORTD_29_GPIO = 1U, +PORTD_29_FTU7_CH2 = 2U, +PORTD_29_FCUART7_RX = 3U, +PORTD_29_TPU_CH14 = 6U, +} PORT_D29MuxType; + +/** @brief PORTD 3 Mode enumeration */ +typedef enum +{ +PORTD_3_GPIO = 1U, +PORTD_3_FTU3_CH5 = 2U, +PORTD_3_FCSPI1_PCS0 = 3U, +PORTD_3_FCSPI5_PCS0 = 5U, +PORTD_3_FTU1_CH2 = 6U, +PORTD_3_TPU_CH3 = 7U, +} PORT_D3MuxType; + +/** @brief PORTD 30 Mode enumeration */ +typedef enum +{ +PORTD_30_ADC1_SE31 = 0U, +PORTD_30_GPIO = 1U, +PORTD_30_FTU7_CH3 = 2U, +PORTD_30_FCUART7_TX = 3U, +PORTD_30_TPU_CH15 = 6U, +} PORT_D30MuxType; + +/** @brief PORTD 31 Mode enumeration */ +typedef enum +{ +PORTD_31_ADC0_SE31 = 0U, +PORTD_31_GPIO = 1U, +PORTD_31_FTU7_CH4 = 2U, +PORTD_31_AONTIMER0_CLK0 = 3U, +PORTD_31_SENT0_RXD2 = 4U, +PORTD_31_FCUART7_RX = 5U, +PORTD_31_TPU_CH20 = 6U, +PORTD_31_FCSPI5_PCS2 = 7U, +} PORT_D31MuxType; + +/** @brief PORTD 4 Mode enumeration */ +typedef enum +{ +PORTD_4_ADC1_SE23 = 0U, +PORTD_4_GPIO = 1U, +PORTD_4_FTU_FLT16 = 2U, +PORTD_4_FTU6_CH4 = 3U, +PORTD_4_FCUART6_TX = 4U, +PORTD_4_FCSPI5_SIN = 5U, +PORTD_4_FTU1_CH3 = 6U, +PORTD_4_TPU_CH4 = 7U, +} PORT_D4MuxType; + +/** @brief PORTD 5 Mode enumeration */ +typedef enum +{ +PORTD_5_GPIO = 1U, +PORTD_5_FTU2_CH3 = 2U, +PORTD_5_FCUART4_TX = 3U, +PORTD_5_FTU_FLT5 = 4U, +PORTD_5_FTU7_CH5 = 5U, +PORTD_5_TPU_CH20 = 6U, +PORTD_5_FCSPI3_SIN = 7U, +} PORT_D5MuxType; + +/** @brief PORTD 6 Mode enumeration */ +typedef enum +{ +PORTD_6_GPIO = 1U, +PORTD_6_FCUART2_RX = 2U, +PORTD_6_FLEXCAN3_RX = 3U, +PORTD_6_FTU_FLT4 = 4U, +PORTD_6_FTU2_CH4 = 5U, +PORTD_6_TPU_CH21 = 6U, +PORTD_6_FCSPI3_SCK = 7U, +} PORT_D6MuxType; + +/** @brief PORTD 7 Mode enumeration */ +typedef enum +{ +PORTD_7_GPIO = 1U, +PORTD_7_FCUART2_TX = 2U, +PORTD_7_FLEXCAN3_TX = 3U, +PORTD_7_FCSPI4_SIN = 4U, +PORTD_7_FTU2_CH5 = 5U, +PORTD_7_ETM_TRACE_D0 = 6U, +} PORT_D7MuxType; + +/** @brief PORTD 8 Mode enumeration */ +typedef enum +{ +PORTD_8_CMP1_IN3 = 0U, +PORTD_8_GPIO = 1U, +PORTD_8_FCIIC1_SDA = 2U, +PORTD_8_FTU4_CH2 = 3U, +PORTD_8_FCSPI2_PCS2 = 4U, +PORTD_8_FlexCore_TRST = 5U, +PORTD_8_FTU1_CH4 = 6U, +PORTD_8_FCUART4_RX = 7U, +} PORT_D8MuxType; + +/** @brief PORTD 9 Mode enumeration */ +typedef enum +{ +PORTD_9_CMP1_IN2 = 0U, +PORTD_9_GPIO = 1U, +PORTD_9_FCIIC1_SCL = 2U, +PORTD_9_FTU4_CH3 = 3U, +PORTD_9_FCSPI2_PCS1 = 4U, +PORTD_9_FlexCore_TDO = 5U, +PORTD_9_FTU1_CH5 = 6U, +PORTD_9_FCUART3_RX = 7U, +} PORT_D9MuxType; + +/** @brief PORTE 0 Mode enumeration */ +typedef enum +{ +PORTE_0_ADC0_SE16 = 0U, +PORTE_0_GPIO = 1U, +PORTE_0_FCUART0_CTS = 2U, +PORTE_0_FTU_TCK1 = 3U, +PORTE_0_FCIIC1_SDA = 4U, +PORTE_0_FCSPI0_SCK = 5U, +PORTE_0_FTU_FLT19 = 6U, +PORTE_0_TPU_CH11 = 7U, +} PORT_E0MuxType; + +/** @brief PORTE 1 Mode enumeration */ +typedef enum +{ +PORTE_1_ADC0_SE17 = 0U, +PORTE_1_GPIO = 1U, +PORTE_1_FCUART0_RTS = 2U, +PORTE_1_FCIIC1_SCL = 4U, +PORTE_1_FCSPI0_SIN = 5U, +PORTE_1_FTU_FLT18 = 6U, +PORTE_1_TPU_CH10 = 7U, +} PORT_E1MuxType; + +/** @brief PORTE 10 Mode enumeration */ +typedef enum +{ +PORTE_10_ADC1_SE0 = 0U, +PORTE_10_GPIO = 1U, +PORTE_10_FTU2_CH4 = 2U, +PORTE_10_FCSPI2_PCS1 = 3U, +PORTE_10_TPU_CH26 = 4U, +PORTE_10_FCUART2_TX = 5U, +PORTE_10_SCG_CLKOUT = 6U, +PORTE_10_TRGSEL_OUT4 = 7U, +} PORT_E10MuxType; + +/** @brief PORTE 11 Mode enumeration */ +typedef enum +{ +PORTE_11_ADC1_SE4 = 0U, +PORTE_11_GPIO = 1U, +PORTE_11_FTU2_CH5 = 2U, +PORTE_11_FCSPI2_PCS0 = 3U, +PORTE_11_TPU_CH27 = 5U, +PORTE_11_TRGSEL_OUT5 = 7U, +} PORT_E11MuxType; + +/** @brief PORTE 12 Mode enumeration */ +typedef enum +{ +PORTE_12_ADC0_SE3 = 0U, +PORTE_12_GPIO = 1U, +PORTE_12_FTU6_CH0 = 2U, +PORTE_12_FCUART7_TX = 3U, +PORTE_12_FTU_FLT2 = 4U, +PORTE_12_FCSPI4_SOUT = 6U, +PORTE_12_TPU_CH3 = 7U, +} PORT_E12MuxType; + +/** @brief PORTE 13 Mode enumeration */ +typedef enum +{ +PORTE_13_ADC0_SE5 = 0U, +PORTE_13_GPIO = 1U, +PORTE_13_FTU4_CH5 = 2U, +PORTE_13_FCSPI2_SOUT = 3U, +PORTE_13_TPU_CH24 = 4U, +PORTE_13_FTU3_CH3 = 5U, +} PORT_E13MuxType; + +/** @brief PORTE 14 Mode enumeration */ +typedef enum +{ +PORTE_14_OSC32K_XTAL = 0U, +PORTE_14_GPIO = 1U, +PORTE_14_FTU2_CH7 = 2U, +PORTE_14_FTU2_QD_PHA = 3U, +PORTE_14_FTU_FLT0 = 4U, +PORTE_14_FLEXCAN0_RX = 5U, +PORTE_14_TPU_TCRCLK = 6U, +} PORT_E14MuxType; + +/** @brief PORTE 15 Mode enumeration */ +typedef enum +{ +PORTE_15_ADC1_SE2 = 0U, +PORTE_15_GPIO = 1U, +PORTE_15_FTU2_CH6 = 2U, +PORTE_15_FCSPI2_SCK = 3U, +PORTE_15_TPU_CH30 = 4U, +PORTE_15_FCUART1_CTS = 6U, +PORTE_15_TRGSEL_OUT6 = 7U, +} PORT_E15MuxType; + +/** @brief PORTE 16 Mode enumeration */ +typedef enum +{ +PORTE_16_ADC1_SE6 = 0U, +PORTE_16_GPIO = 1U, +PORTE_16_FTU2_CH7 = 2U, +PORTE_16_FCSPI2_SIN = 3U, +PORTE_16_TPU_CH31 = 4U, +PORTE_16_FCUART1_RTS = 6U, +PORTE_16_TRGSEL_OUT7 = 7U, +} PORT_E16MuxType; + +/** @brief PORTE 17 Mode enumeration */ +typedef enum +{ +PORTE_17_GPIO = 1U, +PORTE_17_FTU7_CH5 = 2U, +PORTE_17_SENT0_RXD0 = 4U, +PORTE_17_TPU_CH21 = 6U, +PORTE_17_FCSPI5_SOUT = 7U, +} PORT_E17MuxType; + +/** @brief PORTE 18 Mode enumeration */ +typedef enum +{ +PORTE_18_ADC0_SE27 = 0U, +PORTE_18_GPIO = 1U, +PORTE_18_FTU7_CH6 = 2U, +PORTE_18_FTU6_CH7 = 3U, +PORTE_18_SENT0_RXD1 = 4U, +PORTE_18_FCUART7_TX = 5U, +PORTE_18_TPU_CH22 = 6U, +PORTE_18_FCSPI5_PCS3 = 7U, +} PORT_E18MuxType; + +/** @brief PORTE 19 Mode enumeration */ +typedef enum +{ +PORTE_19_ADC0_SE23 = 0U, +PORTE_19_GPIO = 1U, +PORTE_19_SCG_CLKOUT = 2U, +PORTE_19_FCIIC0_SCL = 3U, +PORTE_19_RTC_CLKOUT = 4U, +PORTE_19_FLEXCAN2_RX = 5U, +PORTE_19_TPU_CH31 = 6U, +} PORT_E19MuxType; + +/** @brief PORTE 2 Mode enumeration */ +typedef enum +{ +PORTE_2_ADC0_SE24 = 0U, +PORTE_2_GPIO = 1U, +PORTE_2_FTU6_CH6 = 2U, +PORTE_2_AONTIMER0_CLK2 = 3U, +PORTE_2_FTU3_CH6 = 4U, +PORTE_2_SENT0_RXD3 = 5U, +PORTE_2_FCUART1_CTS = 6U, +PORTE_2_FTU1_CH7 = 7U, +} PORT_E2MuxType; + +/** @brief PORTE 20 Mode enumeration */ +typedef enum +{ +PORTE_20_ADC0_SE22 = 0U, +PORTE_20_GPIO = 1U, +PORTE_20_FTU4_CH0 = 2U, +PORTE_20_FCIIC0_SDA = 3U, +PORTE_20_FTU1_CH3 = 4U, +PORTE_20_FCSPI0_PCS0 = 5U, +} PORT_E20MuxType; + +/** @brief PORTE 21 Mode enumeration */ +typedef enum +{ +PORTE_21_GPIO = 1U, +PORTE_21_FTU4_CH1 = 2U, +PORTE_21_AONTIMER0_CLK2 = 3U, +PORTE_21_FLEXCAN0_TX = 4U, +PORTE_21_FCUART0_RTS = 5U, +} PORT_E21MuxType; + +/** @brief PORTE 22 Mode enumeration */ +typedef enum +{ +PORTE_22_GPIO = 1U, +PORTE_22_FTU4_CH2 = 2U, +PORTE_22_LP_WAKEUP0 = 3U, +PORTE_22_FLEXCAN0_RX = 4U, +PORTE_22_FCUART0_CTS = 5U, +} PORT_E22MuxType; + +/** @brief PORTE 23 Mode enumeration */ +typedef enum +{ +PORTE_23_ADC0_SE19 = 0U, +PORTE_23_GPIO = 1U, +PORTE_23_FTU4_CH3 = 2U, +PORTE_23_FCUART0_TX = 3U, +PORTE_23_TPU_CH26 = 4U, +PORTE_23_FCSPI0_PCS3 = 5U, +PORTE_23_LP_WAKEUP1 = 6U, +} PORT_E23MuxType; + +/** @brief PORTE 24 Mode enumeration */ +typedef enum +{ +PORTE_24_ADC0_SE18 = 0U, +PORTE_24_GPIO = 1U, +PORTE_24_FTU4_CH4 = 2U, +PORTE_24_FLEXCAN2_TX = 3U, +PORTE_24_TPU_CH27 = 4U, +PORTE_24_FCSPI0_PCS2 = 5U, +} PORT_E24MuxType; + +/** @brief PORTE 25 Mode enumeration */ +typedef enum +{ +PORTE_25_DEBUGMUX_P0 = 0U, +PORTE_25_GPIO = 1U, +PORTE_25_FTU4_CH5 = 2U, +PORTE_25_FCUART0_RX = 3U, +PORTE_25_TPU_CH28 = 4U, +PORTE_25_FCSPI0_PCS1 = 5U, +} PORT_E25MuxType; + +/** @brief PORTE 26 Mode enumeration */ +typedef enum +{ +PORTE_26_GPIO = 1U, +PORTE_26_FTU4_CH6 = 2U, +PORTE_26_LP_WAKEUP3 = 3U, +PORTE_26_FTU1_CH2 = 4U, +PORTE_26_FCUART1_TX = 5U, +PORTE_26_TPU_CH23 = 6U, +} PORT_E26MuxType; + +/** @brief PORTE 27 Mode enumeration */ +typedef enum +{ +PORTE_27_GPIO = 1U, +PORTE_27_FTU4_CH7 = 2U, +PORTE_27_FLEXCAN2_RX = 3U, +PORTE_27_FTU1_CH0 = 4U, +PORTE_27_FCUART1_RX = 5U, +PORTE_27_TPU_CH24 = 6U, +} PORT_E27MuxType; + +/** @brief PORTE 29 Mode enumeration */ +typedef enum +{ +PORTE_29_GPIO = 1U, +PORTE_29_FTU2_CH0 = 2U, +PORTE_29_RTC_CLKOUT = 3U, +PORTE_29_FTU1_CH1 = 4U, +PORTE_29_FLEXCAN2_TX = 5U, +PORTE_29_FTU2_QD_PHA = 6U, +PORTE_29_TPU_CH25 = 7U, +} PORT_E29MuxType; + +/** @brief PORTE 3 Mode enumeration */ +typedef enum +{ +PORTE_3_OSC32K_EXTAL = 0U, +PORTE_3_GPIO = 1U, +PORTE_3_FTU2_CH6 = 2U, +PORTE_3_FCUART2_RX = 3U, +PORTE_3_FTU_FLT1 = 4U, +PORTE_3_FTU2_QD_PHB = 5U, +PORTE_3_FTU_TCK0 = 6U, +} PORT_E3MuxType; + +/** @brief PORTE 4 Mode enumeration */ +typedef enum +{ +PORTE_4_ADC0_SE4 = 0U, +PORTE_4_GPIO = 1U, +PORTE_4_FTU6_CH0 = 2U, +PORTE_4_FTU2_QD_PHB = 3U, +PORTE_4_FCSPI1_PCS0 = 4U, +PORTE_4_FTU2_CH2 = 5U, +PORTE_4_ETM_TRACE_D1 = 6U, +PORTE_4_TPU_CH22 = 7U, +} PORT_E4MuxType; + +/** @brief PORTE 5 Mode enumeration */ +typedef enum +{ +PORTE_5_ADC0_SE1 = 0U, +PORTE_5_GPIO = 1U, +PORTE_5_FTU_TCK2 = 2U, +PORTE_5_FTU2_QD_PHA = 3U, +PORTE_5_FCSPI1_SOUT = 4U, +PORTE_5_FTU2_CH3 = 5U, +PORTE_5_TPU_CH23 = 6U, +} PORT_E5MuxType; + +/** @brief PORTE 6 Mode enumeration */ +typedef enum +{ +PORTE_6_ADC0_SE25 = 0U, +PORTE_6_GPIO = 1U, +PORTE_6_FTU7_CH7 = 2U, +PORTE_6_FTU6_CH3 = 3U, +PORTE_6_FTU3_CH7 = 4U, +PORTE_6_SENT0_RXD2 = 5U, +PORTE_6_FCUART1_RTS = 6U, +PORTE_6_TPU_CH6 = 7U, +} PORT_E6MuxType; + +/** @brief PORTE 7 Mode enumeration */ +typedef enum +{ +PORTE_7_ADC1_SE8 = 0U, +PORTE_7_GPIO = 1U, +PORTE_7_FTU0_CH7 = 2U, +PORTE_7_FTU_FLT14 = 3U, +PORTE_7_FTU5_CH6 = 4U, +PORTE_7_TRGSEL_OUT3 = 5U, +PORTE_7_SENT0_RXD3 = 6U, +PORTE_7_MSC0_SDI3 = 7U, +} PORT_E7MuxType; + +/** @brief PORTE 8 Mode enumeration */ +typedef enum +{ +PORTE_8_GPIO = 1U, +PORTE_8_FTU0_CH6 = 2U, +PORTE_8_FCSPI4_SCK = 4U, +PORTE_8_FTU7_CH7 = 5U, +PORTE_8_ETM_TRACE_D4 = 6U, +PORTE_8_FCSPI0_PCS3 = 7U, +} PORT_E8MuxType; + +/** @brief PORTE 9 Mode enumeration */ +typedef enum +{ +PORTE_9_ADC0_SE12_CMP0_IN2 = 0U, +PORTE_9_GPIO = 1U, +PORTE_9_FTU0_CH7 = 2U, +PORTE_9_FCUART2_CTS = 3U, +PORTE_9_TPU_CH17 = 4U, +PORTE_9_ETM_TRACE_CLKOUT = 6U, +PORTE_9_FCSPI0_PCS0 = 7U, +} PORT_E9MuxType; + + +/** @brief Port Pin Mux structure */ +typedef union +{ + PORT_A0MuxType ePortA0Mode; + PORT_A1MuxType ePortA1Mode; + PORT_A2MuxType ePortA2Mode; + PORT_A3MuxType ePortA3Mode; + PORT_A4MuxType ePortA4Mode; + PORT_A6MuxType ePortA6Mode; + PORT_A7MuxType ePortA7Mode; + PORT_A8MuxType ePortA8Mode; + PORT_A9MuxType ePortA9Mode; + PORT_A10MuxType ePortA10Mode; + PORT_A11MuxType ePortA11Mode; + PORT_A12MuxType ePortA12Mode; + PORT_A13MuxType ePortA13Mode; + PORT_A14MuxType ePortA14Mode; + PORT_A15MuxType ePortA15Mode; + PORT_A16MuxType ePortA16Mode; + PORT_A17MuxType ePortA17Mode; + PORT_A18MuxType ePortA18Mode; + PORT_A19MuxType ePortA19Mode; + PORT_A20MuxType ePortA20Mode; + PORT_A21MuxType ePortA21Mode; + PORT_A23MuxType ePortA23Mode; + PORT_A24MuxType ePortA24Mode; + PORT_A25MuxType ePortA25Mode; + PORT_A26MuxType ePortA26Mode; + PORT_A27MuxType ePortA27Mode; + PORT_A28MuxType ePortA28Mode; + PORT_A29MuxType ePortA29Mode; + PORT_A30MuxType ePortA30Mode; + PORT_A31MuxType ePortA31Mode; + PORT_B0MuxType ePortB0Mode; + PORT_B1MuxType ePortB1Mode; + PORT_B3MuxType ePortB3Mode; + PORT_B4MuxType ePortB4Mode; + PORT_B5MuxType ePortB5Mode; + PORT_B6MuxType ePortB6Mode; + PORT_B7MuxType ePortB7Mode; + PORT_B8MuxType ePortB8Mode; + PORT_B9MuxType ePortB9Mode; + PORT_B10MuxType ePortB10Mode; + PORT_B11MuxType ePortB11Mode; + PORT_B12MuxType ePortB12Mode; + PORT_B13MuxType ePortB13Mode; + PORT_B14MuxType ePortB14Mode; + PORT_B15MuxType ePortB15Mode; + PORT_B16MuxType ePortB16Mode; + PORT_B17MuxType ePortB17Mode; + PORT_B18MuxType ePortB18Mode; + PORT_B19MuxType ePortB19Mode; + PORT_B20MuxType ePortB20Mode; + PORT_B21MuxType ePortB21Mode; + PORT_B22MuxType ePortB22Mode; + PORT_B23MuxType ePortB23Mode; + PORT_B24MuxType ePortB24Mode; + PORT_B25MuxType ePortB25Mode; + PORT_B26MuxType ePortB26Mode; + PORT_B27MuxType ePortB27Mode; + PORT_B28MuxType ePortB28Mode; + PORT_B29MuxType ePortB29Mode; + PORT_B30MuxType ePortB30Mode; + PORT_B31MuxType ePortB31Mode; + PORT_C0MuxType ePortC0Mode; + PORT_C1MuxType ePortC1Mode; + PORT_C2MuxType ePortC2Mode; + PORT_C3MuxType ePortC3Mode; + PORT_C4MuxType ePortC4Mode; + PORT_C5MuxType ePortC5Mode; + PORT_C6MuxType ePortC6Mode; + PORT_C7MuxType ePortC7Mode; + PORT_C8MuxType ePortC8Mode; + PORT_C9MuxType ePortC9Mode; + PORT_C10MuxType ePortC10Mode; + PORT_C11MuxType ePortC11Mode; + PORT_C12MuxType ePortC12Mode; + PORT_C13MuxType ePortC13Mode; + PORT_C14MuxType ePortC14Mode; + PORT_C15MuxType ePortC15Mode; + PORT_C16MuxType ePortC16Mode; + PORT_C17MuxType ePortC17Mode; + PORT_C18MuxType ePortC18Mode; + PORT_C19MuxType ePortC19Mode; + PORT_C20MuxType ePortC20Mode; + PORT_C21MuxType ePortC21Mode; + PORT_C22MuxType ePortC22Mode; + PORT_C23MuxType ePortC23Mode; + PORT_C24MuxType ePortC24Mode; + PORT_C25MuxType ePortC25Mode; + PORT_C26MuxType ePortC26Mode; + PORT_C27MuxType ePortC27Mode; + PORT_C28MuxType ePortC28Mode; + PORT_C29MuxType ePortC29Mode; + PORT_C30MuxType ePortC30Mode; + PORT_C31MuxType ePortC31Mode; + PORT_D0MuxType ePortD0Mode; + PORT_D1MuxType ePortD1Mode; + PORT_D2MuxType ePortD2Mode; + PORT_D3MuxType ePortD3Mode; + PORT_D4MuxType ePortD4Mode; + PORT_D5MuxType ePortD5Mode; + PORT_D6MuxType ePortD6Mode; + PORT_D7MuxType ePortD7Mode; + PORT_D8MuxType ePortD8Mode; + PORT_D9MuxType ePortD9Mode; + PORT_D10MuxType ePortD10Mode; + PORT_D11MuxType ePortD11Mode; + PORT_D12MuxType ePortD12Mode; + PORT_D13MuxType ePortD13Mode; + PORT_D15MuxType ePortD15Mode; + PORT_D16MuxType ePortD16Mode; + PORT_D17MuxType ePortD17Mode; + PORT_D18MuxType ePortD18Mode; + PORT_D19MuxType ePortD19Mode; + PORT_D20MuxType ePortD20Mode; + PORT_D21MuxType ePortD21Mode; + PORT_D22MuxType ePortD22Mode; + PORT_D23MuxType ePortD23Mode; + PORT_D24MuxType ePortD24Mode; + PORT_D25MuxType ePortD25Mode; + PORT_D26MuxType ePortD26Mode; + PORT_D27MuxType ePortD27Mode; + PORT_D28MuxType ePortD28Mode; + PORT_D29MuxType ePortD29Mode; + PORT_D30MuxType ePortD30Mode; + PORT_D31MuxType ePortD31Mode; + PORT_E0MuxType ePortE0Mode; + PORT_E1MuxType ePortE1Mode; + PORT_E2MuxType ePortE2Mode; + PORT_E3MuxType ePortE3Mode; + PORT_E4MuxType ePortE4Mode; + PORT_E5MuxType ePortE5Mode; + PORT_E6MuxType ePortE6Mode; + PORT_E7MuxType ePortE7Mode; + PORT_E8MuxType ePortE8Mode; + PORT_E9MuxType ePortE9Mode; + PORT_E10MuxType ePortE10Mode; + PORT_E11MuxType ePortE11Mode; + PORT_E12MuxType ePortE12Mode; + PORT_E13MuxType ePortE13Mode; + PORT_E14MuxType ePortE14Mode; + PORT_E15MuxType ePortE15Mode; + PORT_E16MuxType ePortE16Mode; + PORT_E17MuxType ePortE17Mode; + PORT_E18MuxType ePortE18Mode; + PORT_E19MuxType ePortE19Mode; + PORT_E20MuxType ePortE20Mode; + PORT_E21MuxType ePortE21Mode; + PORT_E22MuxType ePortE22Mode; + PORT_E23MuxType ePortE23Mode; + PORT_E24MuxType ePortE24Mode; + PORT_E25MuxType ePortE25Mode; + PORT_E26MuxType ePortE26Mode; + PORT_E27MuxType ePortE27Mode; + PORT_E29MuxType ePortE29Mode; + Port_PinModeType u32PortPinMode; +} Port_PinMuxType; + +/** @brief Port interrupt configuration */ +typedef enum +{ + PORT_IRQ_DISABLE = 0U, + PORT_IRQ_LOGIC_0 = 8U, + PORT_IRQ_RISING = 9U, + PORT_IRQ_FALLING = 10U, + PORT_IRQ_BOTH_EDGE = 11U, + PORT_IRQ_LOGIC_1 = 12U +} PORT_IntConfigType; + +/** @brief Port DMA request configuration */ +typedef enum +{ + PORT_DMA_REQ_DISABLE = 0U, + PORT_DMA_REQ_RISING = 1U, + PORT_DMA_REQ_FALLING = 2U, + PORT_DMA_REQ_BOTH_EDGE = 3U, +} PORT_DMAReqType; + +/** @brief Port digital filter clock source */ +typedef enum +{ + PORT_FILTER_BUS_CLK = 0U, + PORT_FILTER_AON32K_CLK, +} PORT_DigitalFilterClkSrcType; + +/** @brief Port pull status */ +typedef enum +{ + PORT_PULL_DOWN = 0U, + PORT_PULL_UP +} PORT_PullStatusType; + +/********* Local inline function ************/ +/** + * @brief Configure pin + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u32PcrReg Pin PCR register value + */ +LOCAL_INLINE void PORT_HWA_ConfigPin(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32PcrReg) +{ + pPort->PCR[u8Pin] = u32PcrReg; +} + +/** + * @brief Configure Pin Domain Write Protection + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u32DwpValue Bit field value:Domain Write Protection + */ +LOCAL_INLINE void PORT_HWA_SelPinRegWrtPermit(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32DwpValue) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = (u32TempRegVal & (~ (uint32_t)PORT_PCR_DWP_MASK)) | PORT_PCR_DWP(u32DwpValue); +} + +/** + * @brief Configure Pin Domain Write Protection Lock + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param bEnable Enable or Disable DWP Lock + */ +LOCAL_INLINE void PORT_HWA_ConfigPinDwpLock(PORT_Type *pPort, uint8_t u8Pin, bool bEnable) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = (u32TempRegVal & (~ (uint32_t)PORT_PCR_DWPLK_MASK)) | PORT_PCR_DWPLK(bEnable); +} + +/** + * @brief Configure Pin Emergency Stop + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param bEnable Enable or Disable Emergency Stop of this Pin + */ +LOCAL_INLINE void PORT_HWA_CfgPinEmgcyStop(PORT_Type *pPort, uint8_t u8Pin, bool bEnable) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = (u32TempRegVal & (~ (uint32_t)PORT_PCR_ESTOP_MASK)) | PORT_PCR_ESTOP(bEnable); +} + +/** + * @brief Configure Global Domain Write Protection Lock + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param bEnable Enable or Disable Global DWP Lock + */ +LOCAL_INLINE void PORT_HWA_CfgGlobalDwpLock(PORT_Type *pPort, bool bEnable) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->GLDWP); + pPort->GLDWP = (u32TempRegVal & (~ (uint32_t)PORT_GLDWP_DWPLK_MASK)) | PORT_GLDWP_DWPLK(bEnable); +} + +/** + * @brief Configure Global Domain Write Protection + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u32GlbDwpValue Bit field value:Global Domain Write Protection + */ +LOCAL_INLINE void PORT_HWA_CfgGlobalRegWrtPermit(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32GlbDwpValue) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->GLDWP = (u32TempRegVal & (~ (uint32_t)PORT_GLDWP_DWP_MASK)) | PORT_GLDWP_DWP(u32GlbDwpValue); +} + +/** + * @brief Read pin interrupt flag + * + * @param pPort Port instance + * @param u8Pin Pin number + * @return interrupt flag value + */ +LOCAL_INLINE bool PORT_HWA_ReadPinInterruptFlag(PORT_Type *pPort, uint8_t u8Pin) +{ + return (bool)(pPort->PCR[u8Pin] & (uint32_t)PORT_PCR_ISF_MASK); +} + + +/** + * @brief Set pin multiplexing + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param Port_PinMuxType Pin MXU configuration value + */ +LOCAL_INLINE void PORT_HWA_SetPinMux(PORT_Type *pPort, uint8_t u8Pin, Port_PinMuxType u32PinMux) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_MUX_MASK) | PORT_PCR_MUX(u32PinMux.u32PortPinMode)); +} + +/** + * @brief Set pin interrupt mode + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u32PinIrqc Pin IRQC configuration value + */ +LOCAL_INLINE void PORT_HWA_SetPinInterruptMode(PORT_Type *pPort, uint8_t u8Pin, PORT_IntConfigType u32PinIrqc) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(u32PinIrqc)); +} + +/** + * @brief Set pin DMA request mode + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u32DMAReqMode Pin DMA request mode + */ +LOCAL_INLINE void PORT_HWA_SetPinDMAReqMode(PORT_Type *pPort, uint8_t u8Pin, PORT_DMAReqType u32DMAReqMode) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(u32DMAReqMode)); +} + +/** + * @brief Set pin pull enable + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u8PeValue Pin PE configuration value(1/0) + */ +LOCAL_INLINE void PORT_HWA_SetPinPullEnable(PORT_Type *pPort, uint8_t u8Pin, bool bPullEnable) +{ + if (bPullEnable) + { + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_PE_MASK; + } + else + { + pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_PE_MASK; + } +} + +/** + * @brief Set pin pull mode + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u8PsValue Pin PS configuration value(1/0) + */ +LOCAL_INLINE void PORT_HWA_SetPinPullMode(PORT_Type *pPort, uint8_t u8Pin, PORT_PullStatusType u8PullSelect) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_PS_MASK) | PORT_PCR_PS(u8PullSelect)); +} + +/** + * @brief Set pin drive strength 0 + * + * @param pPort Port instance + * @param u8Pin Pin number + * @note only hs PAD use this bit + */ +LOCAL_INLINE void PORT_HWA_EnablePinDriveStrength0(PORT_Type *pPort, uint8_t u8Pin) +{ + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_DSE0_MASK; +} + +/** + * @brief Set pin drive strength 1 + * + * @param pPort Port instance + * @param u8Pin Pin number + * @note only UHS PAD use this bit + */ +LOCAL_INLINE void PORT_HWA_EnablePinDriveStrength1(PORT_Type *pPort, uint8_t u8Pin) +{ + pPort->PCR[u8Pin] |= (uint32_t)(PORT_PCR_DSE1_MASK | PORT_PCR_DSE0_MASK); +} + +/** + * @brief Set pin passive filter enable + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u8PfeValue Pin PFE configuration value(1/0) + */ +LOCAL_INLINE void PORT_HWA_SetPinPassiveFilterEnable(PORT_Type *pPort, uint8_t u8Pin, bool bPfEable) +{ + if (bPfEable) + { + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_PFE_MASK; + } + else + { + pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_PFE_MASK; + } +} + +/** + * @brief Configure port digital filter + * + * @param pPort Port instance + * @param u32RegValue Enable bit,0-31 bit indicate pin 0-31 + */ +LOCAL_INLINE void PORT_HWA_ConfigDigitalFilter(PORT_Type *pPort, uint32_t u32RegValue) +{ + pPort->DFER = u32RegValue; +} + +/** + * @brief Set port digital filter enable + * + * @param pPort Port instance + * @param u8RegBit DFER register bit + */ +LOCAL_INLINE void PORT_HWA_SetDigitalFilterEnable(PORT_Type *pPort, uint8_t u8RegBit) +{ + pPort->DFER |= (uint32_t)1 << u8RegBit; +} + +/** + * @brief Set port digital filter clock source + * + * @param pPort Port instance + * @param eClkSrc Digital filter clock source + */ +LOCAL_INLINE void PORT_HWA_SetDigitalFilterClkSrc(PORT_Type *pPort, PORT_DigitalFilterClkSrcType eClkSrc) +{ + pPort->DFCR |= PORT_DFCR_CS(eClkSrc); +} + +/** + * @brief Configure digital filter width + * @param pPort Port instance + * @param u32FilterWidth Digital filter length value,range:0-31 + */ +LOCAL_INLINE void PORT_HWA_ConfigDigitalFilterWidth(PORT_Type *pPort, uint32_t u32FilterWidth) +{ + pPort->DFWR = PORT_DFWR_FILT(u32FilterWidth); +} + +/** + * @brief Clear pin interrupt mode + * + * @param pPort Port instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void PORT_HWA_ClearPinInterruptMode(PORT_Type *pPort, uint8_t u8Pin) +{ + pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_IRQC_MASK; +} + +/** + * @brief Clear pin interrupt flag + * + * @param pPort Port instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void PORT_HWA_ClearPinInterruptFlag(PORT_Type *pPort, uint8_t u8Pin) +{ + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_ISF_MASK; +} + +/** + * @brief CLear port digital filter enable + * + * @param pPort Port instance + */ +LOCAL_INLINE void PORT_HWA_ClearDigitalFilterEnable(PORT_Type *pPort) +{ + pPort->DFER = (uint32_t)0U; +} + +/** + * @brief Clear port digital filter enable for specific pin + * + * @param pPort Port instance + * @param u8RegBit DFER register bit + */ +LOCAL_INLINE void PORT_HWA_ClearDigitalFilterPin(PORT_Type *pPort, uint8_t u8RegBit) +{ + pPort->DFER &= (uint32_t)~((uint32_t)1 << u8RegBit); +} + +/** + * @brief Clear port digital filter clock source + * + * @param pPort Port instance + */ +LOCAL_INLINE void PORT_HWA_ClearDigitalFilterClkSrc(PORT_Type *pPort) +{ + pPort->DFCR &= ~(uint32_t)PORT_DFCR_CS_MASK; +} + +/** + * @brief Clear port digital filter width + * + * @param pPort Port instance + */ +LOCAL_INLINE void PORT_HWA_ClearDigitalFilterWidth(PORT_Type *pPort) +{ + pPort->DFWR &= ~(uint32_t)PORT_DFWR_FILT_MASK; +} + +/** + * @brief Write Global Pin Control Low Register( Write Regvalue to bits[15:0] of PCR0 ~ 15 ) + * + * @param pPort Port instance + * @param u32Pin Port pin number + * @param u32LowPcrRegValue Register value in bits[15:0] of PCR0 ~ 15 + */ +LOCAL_INLINE void PORT_HWA_WriteGPCLR(PORT_Type *pPort,uint32_t u32Pin,uint32_t u32LowPcrRegValue) +{ + pPort->GPCLR = PORT_GPCLR_GPWE(u32Pin) | PORT_GPCLR_GPWD(u32LowPcrRegValue); +} + +/** + * @brief Write Global Pin Control High Register( Write Regvalue to bits[15:0] of PCR16 ~ 31 ) + * + * @param pPort Port instance + * @param u32Pin Port pin number + * @param u32LowPcrRegValue Register value in bits[15:0] of PCR16 ~ 31 + */ +LOCAL_INLINE void PORT_HWA_WriteGPCHR(PORT_Type *pPort,uint32_t u32Pin,uint32_t u32LowPcrRegValue) +{ + pPort->GPCHR = (u32Pin & PORT_GPCHR_GPWE_MASK) | PORT_GPCHR_GPWD(u32LowPcrRegValue); +} + +/** + * @brief Write Global Interrupt Control Low Register( Write Regvalue to bits[31:16] of PCR0 ~ 15 ) + * + * @param pPort Port instance + * @param u32Pin Port pin number + * @param u32HighPcrRegValue Register value in bits[31:16] of PCR0 ~ 15 + */ +LOCAL_INLINE void PORT_HWA_WriteGICLR(PORT_Type *pPort,uint32_t u32Pin,uint32_t u32HighPcrRegValue) +{ + pPort->GICLR = (u32HighPcrRegValue & PORT_GICLR_GIWD_MASK) | PORT_GICLR_GIWE(u32Pin); +} + +/** + * @brief Write Global Interrupt Control High Register( Write Regvalue to bits[31:16] of PCR16 ~ 31 ) + * + * @param pPort Port instance + * @param u32Pin Port pin number + * @param u32HighPcrRegValue Register value in bits[31:16] of PCR16 ~ 31 + */ +LOCAL_INLINE void PORT_HWA_WriteGICHR(PORT_Type *pPort,uint32_t u32Pin,uint32_t u32HighPcrRegValue) +{ + pPort->GICHR = (u32HighPcrRegValue & PORT_GICHR_GIWD_MASK) & PORT_GICHR_GIWE(u32Pin); +} + + +#endif /* #ifndef _HWA_PORT_H_ */ diff --git a/Inc/HwA_ptimer.h b/Inc/HwA_ptimer.h new file mode 100644 index 0000000..3e7dbfc --- /dev/null +++ b/Inc/HwA_ptimer.h @@ -0,0 +1,701 @@ +/** + * @file HwA_ptimer.h + * @author Flagchip0126 + * @brief Hardware access layer for PTIMER + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_PTIMER_H_ +#define _HWA_PTIMER_H_ + +#include "device_header.h" + +/** + * @defgroup HwA_ptimer + * @ingroup fc4xxx_driver_ptimer + * @{ + */ + +/** + * @brief Ptimer value load mode + * + * Some Ptimer registers are buffered and will only take effect after called + * PTIMER_LoadValue() function, and this option selects when the buffered configurations + * will tack effect after PTIMER_LoadValue() is called. + * + */ +typedef enum +{ + PTIMER_LOAD_VAL_IMMEDIATELY = 0U, + /*!< Loaded immediately after load operation. */ + PTIMER_LOAD_VAL_AT_MODULO_COUNTER = 1U, + /*!< Loaded when counter hits the max count after load operation. */ + PTIMER_LOAD_VAL_AT_NEXT_TRIGGER = 2U, + /*!< Loaded when detecting an input trigger after load operation. */ + PTIMER_LOAD_VAL_AT_MODULO_COUNTER_OR_NEXT_TRIGGER = 3U + /*!< Loaded when counter hits the max count or detecting an input trigger after load operation. */ +} PTIMER_LoadValueModeType; + +/** + * @brief Ptimer clock pre-divider factor + * + * The Ptimer clock source is from core clock and the divider is a multiplication of + * PTIMER_ClockPreDividerType and PTIMER_ClockPreDivMultiplyFactorType, and thus: + * Freq = Core_Freq / (PTIMER_ClockPreDividerType * PTIMER_ClockPreDivMultiplyFactorType) + * + */ +typedef enum +{ + PTIMER_PRE_DIVIDE_BY_1 = 0U, + PTIMER_PRE_DIVIDE_BY_2 = 1U, + PTIMER_PRE_DIVIDE_BY_4 = 2U, + PTIMER_PRE_DIVIDE_BY_8 = 3U, + PTIMER_PRE_DIVIDE_BY_16 = 4U, + PTIMER_PRE_DIVIDE_BY_32 = 5U, + PTIMER_PRE_DIVIDE_BY_64 = 6U, + PTIMER_PRE_DIVIDE_BY_128 = 7U +} PTIMER_ClockPreDividerType; + +/** + * @brief Ptimer clock divider multiplication factor + * + * The Ptimer clock source is from core clock and the divider is a multiplication of + * PTIMER_ClockPreDividerType and PTIMER_ClockPreDivMultiplyFactorType, and thus: + * Freq = Core_Freq / (PTIMER_ClockPreDividerType * PTIMER_ClockPreDivMultiplyFactorType) + * + */ +typedef enum +{ + PTIMER_PRE_DIVIDER_MULTIPLY_BY_1 = 0U, + PTIMER_PRE_DIVIDER_MULTIPLY_BY_10 = 1U, + PTIMER_PRE_DIVIDER_MULTIPLY_BY_20 = 2U, + PTIMER_PRE_DIVIDER_MULTIPLY_BY_40 = 3U +} PTIMER_ClockPreDivMultiplyFactorType; + +/** + * @brief Ptimer trigger source + * + */ +typedef enum +{ + PTIMER_TRGSRC_TRGSEL = 0x00U, /*!< Ptimer trigger source from TrgSel */ + PTIMER_TRGSRC_SW = 0x0FU /*!< Ptimer trigger source from software trigger*/ +} PTIMER_TrgSrcType; + +/** + * @brief Get the STATUS_CTRL register value + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE uint32_t PTIMER_HWA_GetStatusCtrl(const PTIMER_Type *const pPtimer) +{ + return pPtimer->STATUS_CTRL; +} + +/** + * @brief Set the STATUS_CTRL register value + * + * @param pPtimer the base address of the Ptimer instance + * @param u32CfgValue the register value to set + */ +LOCAL_INLINE void PTIMER_HWA_SetStatusCtrl(PTIMER_Type *const pPtimer, uint32_t u32CfgValue) +{ + pPtimer->STATUS_CTRL = u32CfgValue; +} + +/** + * @brief Get the load mode of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return PTIMER_LoadValueModeType the load mode of the Ptimer instance + */ +LOCAL_INLINE PTIMER_LoadValueModeType PTIMER_HWA_GetLoadMode(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_LDMODE_MASK) >> PTIMER_STATUS_CTRL_LDMODE_SHIFT; + return (PTIMER_LoadValueModeType)u32TmpVal; +} + +/** + * @brief Set the load mode of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param eLoadMode the load mode of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetLoadMode(PTIMER_Type *const pPtimer, PTIMER_LoadValueModeType eLoadMode) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_LDMODE_MASK) | PTIMER_STATUS_CTRL_LDMODE(eLoadMode); +} + +/** + * @brief Get whether sequence error interrupt is enabled + * + * @param pPtimer the base address of the Ptimer instance + * @return true sequence error interrupt is enabled + * @return false sequence error interrupt is disabled + */ +LOCAL_INLINE bool PTIMER_HWA_GetSeqErrIntEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_SERR_INTEN_MASK) >> PTIMER_STATUS_CTRL_SERR_INTEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable sequence error interrupt + * + * @param pPtimer the base address of the Ptimer instance + * @param bEnable whether to enable sequence error interrupt + */ +LOCAL_INLINE void PTIMER_HWA_SetSeqErrIntEnableFlag(PTIMER_Type *const pPtimer, bool bEnable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_SERR_INTEN_MASK) | PTIMER_STATUS_CTRL_SERR_INTEN( + bEnable ? 1U : 0U); +} + +/** + * @brief Generate software trigger signal for Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_GenerateSwTrigger(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_SWTRG_MASK; +} + +/** + * @brief Get whether DMA is enabled for the Ptimer insstance + * + * @param pPtimer the base address of the Ptimer instance + * @return true DMA is enabled + * @return false DMA is disabled + */ +LOCAL_INLINE bool PTIMER_HWA_GetDMAEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_DMAEN_MASK) >> PTIMER_STATUS_CTRL_DMAEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable Ptimer DMA + * + * @param pPtimer the base address of the Ptimer instance + * @param bEnable whether to enable DMA for the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetDMAEnableFlag(PTIMER_Type *const pPtimer, bool bEnable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_DMAEN_MASK) | PTIMER_STATUS_CTRL_DMAEN(bEnable ? 1U : 0U); +} + +/** + * @brief Get the predivider value of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return PTIMER_ClockPreDividerType the predivider of the Ptimer instance + */ +LOCAL_INLINE PTIMER_ClockPreDividerType PTIMER_HWA_GetDivPrescaler(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_PRESCALER_MASK) >> PTIMER_STATUS_CTRL_PRESCALER_SHIFT; + return (PTIMER_ClockPreDividerType)u32TmpVal; +} + +/** + * @brief Set the predivider value of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param eDivPrescaler the predivider of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetDivPrescaler(PTIMER_Type *const pPtimer, PTIMER_ClockPreDividerType eDivPrescaler) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_PRESCALER_MASK) | PTIMER_STATUS_CTRL_PRESCALER( + eDivPrescaler); +} + +/** + * @brief Get the trigger source of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return PTIMER_TRGSRC_TRGSEL the trigger source is from TrgSel + * @return PTIMER_TRGSRC_SW the trigger source is from software + */ +LOCAL_INLINE PTIMER_TrgSrcType PTIMER_HWA_GetTriggerSource(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_TRGSEL_MASK) >> PTIMER_STATUS_CTRL_TRGSEL_SHIFT; + return (PTIMER_TrgSrcType)u32TmpVal; +} + +/** + * @brief Set the trigger source of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param eTriggerSource the trigger source of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetTriggerSource(PTIMER_Type *const pPtimer, PTIMER_TrgSrcType eTriggerSource) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_TRGSEL_MASK) | PTIMER_STATUS_CTRL_TRGSEL( + eTriggerSource); +} + +/** + * @brief Get whether the Ptimer instance is enabled + * + * @param pPtimer the base address of the Ptimer instance + * @return true the Ptimer instance is enabled + * @return false the Ptimer instance is disabled + */ +LOCAL_INLINE bool PTIMER_HWA_GetEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_ENABLE_MASK) >> PTIMER_STATUS_CTRL_ENABLE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_Enable(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_ENABLE_MASK; +} + +/** + * @brief Disable the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_Disable(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL &= ~PTIMER_STATUS_CTRL_ENABLE_MASK; +} + +/** + * @brief Get the delay interrupt flag of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return true the delay interrupt flag of the Ptimer instance is generated + * @return false the delay interrupt flag of the Ptimer instance is not generated + */ +LOCAL_INLINE bool PTIMER_HWA_GetInterruptFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_INTFLAG_MASK) >> PTIMER_STATUS_CTRL_INTFLAG_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the delay interrupt flag of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_ClearInterruptFlag(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL &= ~PTIMER_STATUS_CTRL_INTFLAG_MASK; +} + +/** + * @brief Get whether delay interrupt is enabled for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE bool PTIMER_HWA_GetInterruptEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_INTEN_MASK) >> PTIMER_STATUS_CTRL_INTEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable delay interrupt for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param bEnable whether to enable delay interrupt for the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetInterruptEnableFlag(PTIMER_Type *const pPtimer, bool bEnable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_INTEN_MASK) | PTIMER_STATUS_CTRL_INTEN(bEnable ? 1U : 0U); +} + +/** + * @brief Get the multiply factor of the predivider of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return PTIMER_ClockPreDivMultiplyFactorType the multiply factor of the Ptimer instance + */ +LOCAL_INLINE PTIMER_ClockPreDivMultiplyFactorType PTIMER_HWA_GetDivMultiply(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_MULT_MASK) >> PTIMER_STATUS_CTRL_MULT_SHIFT; + return (PTIMER_ClockPreDivMultiplyFactorType)u32TmpVal; +} + +/** + * @brief Set the multiply factor of the predivider of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param eMultFactor the multiply factor of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetDivMultiply(PTIMER_Type *const pPtimer, + PTIMER_ClockPreDivMultiplyFactorType eMultFactor) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_MULT_MASK) | PTIMER_STATUS_CTRL_MULT(eMultFactor); +} + +/** + * @brief Get whether continuous mode is enabled for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return true continuous mode is enabled for the Ptimer instance + * @return false continuous mode is disabled for the Ptimer instance + */ +LOCAL_INLINE bool PTIMER_HWA_GetContinuoiusModeFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_CONT_MASK) >> PTIMER_STATUS_CTRL_CONT_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable continuous mode for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param bEnable whether to enable continuous mode for the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetContinuoiusModeFlag(PTIMER_Type *const pPtimer, bool bEnable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_CONT_MASK) | PTIMER_STATUS_CTRL_CONT(bEnable ? 1U : 0U); +} + +/** + * @brief Get the config value loading status + * + * @param pPtimer the base address of the Ptimer instance + * @return true the config values are in loading status + * @return false the config values are loaded + */ +LOCAL_INLINE bool PTIMER_HWA_GetValueLoadStatus(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_LDOK_MASK) >> PTIMER_STATUS_CTRL_LDOK_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Load the buffered values into register + * + * @note Some Ptimer registers are buffered and will only take effect after called + * this function + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_LoadValue(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_LDOK_MASK; +} + +/** + * @brief Get the Ptimer max counter period + * When the Ptimer counter reaches the period, it will return to zero + * + * @param pPtimer the base address of the Ptimer instance + * @return uint16_t the Ptimer max count + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetMaxCount(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->MAX_CNT & PTIMER_MAX_CNT_MAX_CNT_MASK) >> PTIMER_MAX_CNT_MAX_CNT_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set the Ptimer max counter period + * When the Ptimer counter reaches the period, it will return to zero + * + * @note the period parameter is buffered and will take effect only after called PTIMER_LoadValue() + * function. + * + * @param pPtimer the base address of the Ptimer instance + * @param u16MaxCnt the Ptimer max count + */ +LOCAL_INLINE void PTIMER_HWA_SetMaxCount(PTIMER_Type *const pPtimer, uint16_t u16MaxCnt) +{ + pPtimer->MAX_CNT = PTIMER_MAX_CNT_MAX_CNT(u16MaxCnt); +} + +/** + * @brief Get the Ptimer current count value + * + * @param pPtimer the base address of the Ptimer instance + * @return uint16_t the Ptimer current count value + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetCounterValue(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->CNT & PTIMER_CNT_CNT_MASK) >> PTIMER_CNT_CNT_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get the ptimer interrupt period + * + * @param pPtimer the base address of the Ptimer instance + * @return uint16_t the Ptimer interrupt period + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetInterruptDelay(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->INT_DLY & PTIMER_INT_DLY_INT_DLY_MASK) >> PTIMER_INT_DLY_INT_DLY_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set the ptimer interrupt period + * + * @param pPtimer the base address of the Ptimer instance + * @param u16InterruptDelay the Ptimer interrupt period + */ +LOCAL_INLINE void PTIMER_HWA_SetInterruptDelay(PTIMER_Type *const pPtimer, uint16_t u16InterruptDelay) +{ + pPtimer->INT_DLY = PTIMER_INT_DLY_INT_DLY(u16InterruptDelay); +} + +/** + * @brief Get whether back to back trigger is enbaled for the Ptimer channel + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return true back to back trigger is enbaled for the Ptimer channel + * @return false back to back trigger is disabled for the Ptimer channel + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelBackToBackFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerCtrlIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_BTB(1UL << u8PtimerCtrlIdx)) >> + (PTIMER_CTRL_CH_BTB_SHIFT + u8PtimerCtrlIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether pre-trigger output is enbaled for the Ptimer channel + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return true pre-trigger output is enbaled for the Ptimer channel + * @return false pre-trigger output is disabled for the Ptimer channel + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelPretriggerOutputFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerCtrlIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_PTOS(1UL << u8PtimerCtrlIdx)) >> + (PTIMER_CTRL_CH_PTOS_SHIFT + u8PtimerCtrlIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether pre-trigger is enbaled for the Ptimer channel + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return true pre-trigger is enbaled for the Ptimer channel + * @return false pre-trigger is disabled for the Ptimer channel + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelPretriggerEnableFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerCtrlIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_PTEN(1UL << u8PtimerCtrlIdx)) >> + (PTIMER_CTRL_CH_PTEN_SHIFT + u8PtimerCtrlIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Ptimer channel control flags + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @param bEnablePretrigger whether to enable pre-trigger + * @param bEnablePretriggerOutput whether to enable pre-trigger output + * @param bEnableBackToBack whether to enable back to back trigger + */ +LOCAL_INLINE void PTIMER_HWA_SetChannelControl(PTIMER_Type *const pPtimer, uint8_t u8Channel, bool bEnablePretrigger, + bool bEnablePretriggerOutput, bool bEnableBackToBack) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerCtrlIdx = u8Channel % 8U; + uint32_t u32CtrlMask = PTIMER_CTRL_CH_PTEN(1UL << u8PtimerCtrlIdx) | + PTIMER_CTRL_CH_PTOS(1UL << u8PtimerCtrlIdx) | + PTIMER_CTRL_CH_BTB(1UL << u8PtimerCtrlIdx); + pPtimer->CH[u8PtimerChannelIdx].CTRL = (pPtimer->CH[u8PtimerChannelIdx].CTRL & ~u32CtrlMask) | + PTIMER_CTRL_CH_PTEN((bEnablePretrigger ? 1UL : 0UL) << u8PtimerCtrlIdx) | + PTIMER_CTRL_CH_PTOS((bEnablePretriggerOutput ? 1UL : 0UL) << u8PtimerCtrlIdx) | + PTIMER_CTRL_CH_BTB((bEnableBackToBack ? 1UL : 0UL) << u8PtimerCtrlIdx); +} + +/** + * @brief Get whether the Ptimer counter matches the channel counter + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return true the Ptimer counter matches the channel counter + * @return false the Ptimer counter has not reached the channel counter + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelCounterFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerStatusIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].STATUS & PTIMER_STATUS_CH_CHN_FLAG(1UL << u8PtimerStatusIdx)) >> + (PTIMER_STATUS_CH_CHN_FLAG_SHIFT + u8PtimerStatusIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the Ptimer channel counter match flag + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + */ +LOCAL_INLINE void PTIMER_HWA_ClearChannelCounterFlag(PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerStatusIdx = u8Channel % 8U; + pPtimer->CH[u8PtimerChannelIdx].STATUS &= ~PTIMER_STATUS_CH_CHN_FLAG(1UL << u8PtimerStatusIdx); +} + +/** + * @brief Get the sequence error status of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the channel related to the sequence error + * @return true the selected channel has sequence error + * @return false the selected channel does not have sequence error + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelSequenceErrorFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerStatusIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].STATUS & PTIMER_STATUS_CH_SERR_FLAG(1UL << u8PtimerStatusIdx)) >> + (PTIMER_STATUS_CH_SERR_FLAG_SHIFT + u8PtimerStatusIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the sequence error flag of the selected Ptimer channel + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel to clear the sequence error flag + */ +LOCAL_INLINE void PTIMER_HWA_ClearChannelSequenceErrorFlag(PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerStatusIdx = u8Channel % 8U; + pPtimer->CH[u8PtimerChannelIdx].STATUS &= ~PTIMER_STATUS_CH_SERR_FLAG(1UL << u8PtimerStatusIdx); +} + +/** + * @brief Get the channel delay value + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return uint16_t the channel delay value + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetChannelDelay(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / PTIMER_CH_DLY_CNT; + uint8_t u8PtimerDelayIdx = u8Channel % PTIMER_CH_DLY_CNT; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].DLY[u8PtimerDelayIdx] & PTIMER_DLY_CH_CHNDLY_MASK) >> + PTIMER_DLY_CH_CHNDLY_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set the channel delay value + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @param u16Delay the channel delay value + */ +LOCAL_INLINE void PTIMER_HWA_SetChannelDelay(PTIMER_Type *const pPtimer, uint8_t u8Channel, uint16_t u16Delay) +{ + uint8_t u8PtimerChannelIdx = u8Channel / PTIMER_CH_DLY_CNT; + uint8_t u8PtimerDelayIdx = u8Channel % PTIMER_CH_DLY_CNT; + pPtimer->CH[u8PtimerChannelIdx].DLY[u8PtimerDelayIdx] = PTIMER_DLY_CH_CHNDLY(u16Delay); +} + +/** + * @brief Get whether pulse-out is enabled + * + * @param pPtimer the base address of the Ptimer instance + * @return true pulse-out is enabled + * @return false pulse-out is disabled + */ +LOCAL_INLINE bool PTIMER_HWA_GetPulseOutEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->POEN & PTIMER_POEN_POEN_MASK) >> PTIMER_POEN_POEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable pulse-out for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_EnablePulseOut(PTIMER_Type *const pPtimer) +{ + pPtimer->POEN |= PTIMER_POEN_POEN_MASK; +} + +/** + * @brief Disable pulse-out for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_DisablePulseOut(PTIMER_Type *const pPtimer) +{ + pPtimer->POEN &= ~PTIMER_POEN_POEN_MASK; +} + +/** + * @brief Get the delay high value for the pulse-out function + * When the Ptimer counter reach the delay high value, the pulse output goes high + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetPulseOutDelayHigh(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->PODLY & PTIMER_PODLY_DLY1_MASK) >> PTIMER_PODLY_DLY1_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get the delay low value for the pulse-out function + * When the Ptimer counter reach the delay low value, the pulse output goes low + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetPulseOutDelayLow(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->PODLY & PTIMER_PODLY_DLY2_MASK) >> PTIMER_PODLY_DLY2_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set the pulse out delay value + * When the Ptimer counter reach the delay high value, the pulse output goes high + * When the Ptimer counter reach the delay low value, the pulse output goes low + * The delay high value can be either greater or less than the delay low value + * + * @param pPtimer the base address of the Ptimer instance + * @param u16DelayHigh the delay high value + * @param u16DelayLow the delay low value + */ +LOCAL_INLINE void PTIMER_HWA_SetPulseOutDelay(PTIMER_Type *const pPtimer, uint16_t u16DelayHigh, uint16_t u16DelayLow) +{ + pPtimer->PODLY = PTIMER_PODLY_DLY1(u16DelayHigh) | PTIMER_PODLY_DLY2(u16DelayLow); +} + +/** @}*/ + +#endif /* _HWA_PTIMER_H_ */ diff --git a/Inc/HwA_rgm.h b/Inc/HwA_rgm.h new file mode 100644 index 0000000..22ccab7 --- /dev/null +++ b/Inc/HwA_rgm.h @@ -0,0 +1,427 @@ +/** + * @file HwA_rgm.h + * @author Flagchip + * @brief FC7xxx RGM hardware access layer + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_RGM_H_ +#define _HWA_RGM_H_ + +#include "device_header.h" +/********* Local typedef ************/ +/** @brief Rgm reset event */ +typedef enum +{ + RGM_WAKEUP = 0x00000001U, + RGM_LVD = 0x00000002U, + RGM_CLKERR1 = 0x00000004U, + RGM_CLKERR0 = 0x00000008U, + RGM_FSCMU = 0x00000010U, + RGM_HSMWDOG = 0x00000020U, + RGM_PIN = 0x00000040U, + RGM_POR = 0x00000080U, + RGM_JTAG = 0x00000100U, + RGM_SYSAP = 0x00000800U, + RGM_WDOG1 = 0x00001000U, + RGM_SACKERR = 0x00002000U, + RGM_CMU = 0x00004000U, + RGM_LBIST = 0x00008000U, + RGM_FSMERR = 0x20000000U, + RGM_PINRSTTOUT = 0x40000000U, + RGM_SYSRSTTOUT = 0x80000000U +} RGM_ResetEventType; + +/** @brief Rgm reset interrupt delay cycles type. */ +typedef enum +{ + RGM_8_CLOCK_CYCLES = 0x00U, + RGM_32_CLOCK_CYCLES = 0x01U, + RGM_128_CLOCK_CYCLES = 0x02U, + RGM_512_CLOCK_CYCLES = 0x03U +} RGM_ResetDelayType; + +/** @brief Rgm reset interrupt event manger */ +typedef enum +{ + RGM_INT_CLKERR0 = 0x0008U, + RGM_INT_FCSMU = 0x0010U, + RGM_INT_WDG = 0x0020U, + RGM_INT_PIN = 0x0040U, + RGM_INT_JTAG = 0x0100U, + RGM_INT_CPULOC = 0x0200U, + RGM_INT_SW = 0x0400U, + RGM_INT_SYSAP = 0x0800U, + RGM_INT_WDOG1 = 0x1000U, + RGM_INT_SACKERR = 0x2000U, + RGM_INT_CMU = 0x4000U +} RGM_ResetIntMangerType; + +/** @brief Select the Rgm CORE Write protection */ +typedef enum +{ + RGM_WPB_ALL = 0x00U, + RGM_WPB_CPU0 = 0x01U, + RGM_WPB_NOCORE = 0x04U +} RGM_WriteprotectionBitType; + +/** @brief Rgm CPU0,1,2 related interrupt event manger */ +typedef enum +{ + RGM_CPU_INT_LOCKUP = 0x01U, + RGM_CPU_INT_SYSRST = 0x02U, + RGM_CPU_INT_WDOG = 0x04U, + RGM_CPU_INT_INTM = 0x08U, + RGM_CPU_INT_SWRST = 0x10U +} RGM_CPUIntMangerType; + +/** @brief Rgm CPU0,1,2 software reset status */ +typedef enum +{ + RGM_CPU_OUT_RST_UNDER = 0x00U, + RGM_CPU_OUT_RST_OUT = 0x01U +} RGM_CPUOutResetType; + +/** @brief Rgm CPU0,1,2 reset event */ +typedef enum +{ + RGM_CPU_WAKEUP = 0x00000001U, + RGM_CPU_LVD = 0x00000002U, + RGM_CPU_CLKERR1 = 0x00000004U, + RGM_CPU_CLKERR0 = 0x00000008U, + RGM_CPU_FSCMU = 0x00000010U, + RGM_CPU_HSMWDOG = 0x00000020U, + RGM_CPU_PIN = 0x00000040U, + RGM_CPU_POR = 0x00000080U, + RGM_CPU_JTAG = 0x00000100U, + RGM_CPU_SYSAP = 0x00000800U, + RGM_CPU_WDOG1 = 0x00001000U, + RGM_CPU_SACKERR = 0x00002000U, + RGM_CPU_CMU = 0x00004000U, + RGM_CPU_LBIST = 0x00008000U, + RGM_CPU_LOCKUP = 0x00010000U, + RGM_CPU_SYSRST = 0x00020000U, + RGM_CPU_WDOG = 0x00040000U, + RGM_CPU_INTM = 0x00080000U, + RGM_CPU_SWRST = 0x00100000U, + RGM_CPU_FSMERR = 0x20000000U, + RGM_CPU_PINRSTTOUT = 0x40000000U, + RGM_CPU_SYSRSTTOUT = 0x80000000U +} RGM_CPUResetEventType; + +/** @brief Rgm CPU1,2 system reset enable flag */ +typedef enum +{ + RGM_CPU_EN_LOCKUP = 0x00010000U, + RGM_CPU_EN_SYSRST = 0x00020000U, + RGM_CPU_EN_WDOG = 0x00040000U, + RGM_CPU_EN_INTM = 0x00080000U, + RGM_CPU_EN_SWRST = 0x00100000U, +} RGM_CPUSystemRstMangerType; +/********* Local inline function ************/ +/** + * @brief Read last reset flag + * + * @return Last reset flag + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadLastResetFlag(void) +{ + return (uint32_t)RGM->SRS; +} + +/** + * @brief Read all reset flag before POR,SSRS register is reset on POR only + * + * @return All reset flag before POR + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadAllResetFlagBeforePOR(void) +{ + return (uint32_t)RGM->SSRS; +} + +/** + * @brief Read reset pin filter register + * + * @return Reset pin filter register + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadResetPinFilterEnable(void) +{ + return (uint32_t)RGM->RSTFLT; +} + +/** + * @brief This api can clear reset flag of SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + * @param eReset Reset flag + */ +LOCAL_INLINE void RGM_HWA_ClearResetFlagAfterPOR(RGM_ResetEventType eReset) +{ + RGM->SSRS = (uint32_t)(eReset); +} + +/** + * @brief This api can clear all reset flag of SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +LOCAL_INLINE void RGM_HWA_ClearAllResetFlagAfterPOR(void) +{ + RGM->SSRS = (uint32_t)0xE000F9FFU; +} + +/** + * @brief Set reset pin filter bus clock filter width + * + * @param u8Value Bus clock filter width value + */ +LOCAL_INLINE void RGM_HWA_SetBusClockFilterWidth(uint8_t u8Value) +{ + uint32_t u32RegValue = RGM->RSTFLT; + RGM->RSTFLT = (u32RegValue & ~(uint32_t)RGM_RSTFLT_RSTFLT_BUSW_MASK) | RGM_RSTFLT_RSTFLT_BUSW(u8Value); +} + +/** + * @brief Enable reset pin filter bus clock + * + */ +LOCAL_INLINE void RGM_HWA_EnableBusClockFilter(void) +{ + RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_BUS_MASK; +} + +/** + * @brief Enable reset pin filter AON32K clock + * + */ +LOCAL_INLINE void RGM_HWA_EnableAon32kClockFilter(void) +{ + RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_AON_MASK; +} + +/** + * @brief Enable reset pin filter AON32K low power clock + * + */ +LOCAL_INLINE void RGM_HWA_EnableAon32kLPClockFilter(void) +{ + RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_AON_LP_MASK; +} + +/** + * @brief Clear reset pin filter bus clock filter width + * + */ +LOCAL_INLINE void RGM_HWA_ClearBusClockFilterWidth(void) +{ + RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_BUSW_MASK; +} + +/** + * @brief Disable reset pin filter bus clock + * + */ +LOCAL_INLINE void RGM_HWA_DisableBusClockFilter(void) +{ + RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_BUS_MASK; +} + +/** + * @brief Disable reset pin filter AON32K clock + * + */ +LOCAL_INLINE void RGM_HWA_DisableAon32kClockFilter(void) +{ + RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_AON_MASK; +} + +/** + * @brief Disable reset pin filter AON32K low power clock + * + */ +LOCAL_INLINE void RGM_HWA_DisableAon32kLPClockFilter(void) +{ + RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_AON_LP_MASK; +} + +/** + * @brief Set Reset delay + * + * @param eDelay Reset delay type + */ +LOCAL_INLINE void RGM_HWA_SetResetDelay(RGM_ResetDelayType eDelay) +{ + uint32_t u32RegValue = RGM->SRIE; + RGM->SRIE = (u32RegValue & ~(uint32_t)RGM_SRIE_DELAY_MASK) | RGM_SRIE_DELAY(eDelay); +} + +/** + * @brief Clear Reset delay + */ +LOCAL_INLINE void RGM_HWA_ClearResetDelay(void) +{ + RGM->SRIE &= ~(uint32_t)RGM_SRIE_DELAY_MASK; +} + +/** + * @brief Enable global reset interrupt + * + */ +LOCAL_INLINE void RGM_HWA_EnableGlobalResetInterrupt(void) +{ + RGM->SRIE |= (uint32_t)RGM_SRIE_GLOBAL_RIE_MASK; +} + +/** + * @brief Enable reset interrupt + * + * @param eResetInterrupt Reset interrupt type + */ +LOCAL_INLINE void RGM_HWA_EnableResetInterrupt(RGM_ResetIntMangerType eResetInterrupt) +{ + RGM->SRIE |= (uint32_t)((uint32_t)eResetInterrupt & (RGM_SRIE_CLKERR0_RIE_MASK | RGM_SRIE_WDG_RIE_MASK | + RGM_SRIE_PIN_RIE_MASK | RGM_SRIE_JTAG_RIE_MASK | RGM_SRIE_CPULOC_RIE_MASK | RGM_SRIE_SW_RIE_MASK | + RGM_SRIE_SYSAP_RIE_MASK | RGM_SRIE_WDOG1_RIE_MASK | RGM_SRIE_SACKERR_RIE_MASK)); +} + +/** + * @brief Disable reset interrupt + * + * @param eResetInterrupt Reset interrupt type + */ +LOCAL_INLINE void RGM_HWA_DisableResetInterrupt(RGM_ResetIntMangerType eResetInterrupt) +{ + RGM->SRIE &= ~(uint32_t)((uint32_t)eResetInterrupt & (RGM_SRIE_CLKERR0_RIE_MASK | RGM_SRIE_WDG_RIE_MASK | + RGM_SRIE_PIN_RIE_MASK | RGM_SRIE_JTAG_RIE_MASK | RGM_SRIE_CPULOC_RIE_MASK | RGM_SRIE_SW_RIE_MASK | + RGM_SRIE_SYSAP_RIE_MASK | RGM_SRIE_WDOG1_RIE_MASK | RGM_SRIE_SACKERR_RIE_MASK)); +} + +/** + * @brief Get enabling status of system reset + * + * @return Interrupt enabling status of system reset + */ +LOCAL_INLINE uint32_t RGM_HWA_GetResetInterrupt(void) +{ + return (uint32_t)(RGM->SRIE & (RGM_SRIE_CLKERR0_RIE_MASK | RGM_SRIE_WDG_RIE_MASK | + RGM_SRIE_PIN_RIE_MASK | RGM_SRIE_GLOBAL_RIE_MASK | RGM_SRIE_JTAG_RIE_MASK | RGM_SRIE_CPULOC_RIE_MASK | + RGM_SRIE_SW_RIE_MASK | RGM_SRIE_SYSAP_RIE_MASK | RGM_SRIE_WDOG1_RIE_MASK | RGM_SRIE_SACKERR_RIE_MASK)); +} + +/** + * @brief Perform system reset. + * + */ +LOCAL_INLINE void CM7_HWA_SystemReset(void) +{ + uint32 u32Temp; + u32Temp = SCB->AIRCR; + u32Temp &= ~(uint32)(SCB_AIRCR_VECTKEY_Msk); + u32Temp |= (uint32)((((uint32_t)(((uint32_t)(0x5FAU))<AIRCR = u32Temp; +} + +/** + * @brief Enable CPU0 interrupt + * + * @param eCPU0ResetInterrupt CPU0 related interrupt type + */ +LOCAL_INLINE void RGM_HWA_EnableCPU0InterruptFlag(RGM_CPUIntMangerType eCPU0ResetInterrupt) +{ + RGM->C0_CFG |= (uint32_t)((uint32_t)eCPU0ResetInterrupt & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK | + RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK)); +} + +/** + * @brief Disable CPU0 interrupt + * + * @param eCPU0ResetInterrupt CPU0 related interrupt type + */ +LOCAL_INLINE void RGM_HWA_DisableCPU0InterruptFlag(RGM_CPUIntMangerType eCPU0ResetInterrupt) +{ + RGM->C0_CFG &= ~(uint32_t)((uint32_t)eCPU0ResetInterrupt & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK | + RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK)); +} + +/** + * @brief Get enabling status of CPU0 core related reset + * + * @return Interrupt enabling status of CPU0 core related reset + */ +LOCAL_INLINE uint32_t RGM_HWA_GetCPU0ResetInterrupt(void) +{ + return (uint32_t)(RGM->C0_CFG & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK | + RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK)); +} + +/** + * @brief Get the CPU0 exit reset flag + * + * @return RGM_CPU_OUT_RST_UNDER CPU0 is under reset + * @return RGM_CPU_OUT_RST_OUT CPU0 is out of reset + */ +LOCAL_INLINE RGM_CPUOutResetType RGM_HWA_GetCPU0OutResetFlag(void) +{ + uint8_t u8TmpVal = (uint8_t)(RGM->C0_RST & RGM_C0_RST_C0_OUT_OF_RST_MASK) >> RGM_C0_RST_C0_OUT_OF_RST_SHIFT; + return (RGM_CPUOutResetType)u8TmpVal; +} + +/** + * @brief Issue a CPU0 software reset. + * + */ +LOCAL_INLINE void RGM_HWA_CPU0SWReset(void) +{ + RGM->C0_RST |= (uint32_t)RGM_C0_RST_C0_SWRST_MASK; +} + +/** + * @brief Read CPU0 last reset flag + * + * @return CPU0 last reset flag + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadCPU0LastResetFlag(void) +{ + return (uint32_t)RGM->C0_SRS; +} + +/** + * @brief Read CPU0 all reset flag before POR,SSRS register is reset on POR only + * + * @return CPU0 all reset flag before POR + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadCPU0AllResetFlagBeforePOR(void) +{ + return (uint32_t)RGM->C0_SSRS; +} + +/** + * @brief This api can clear reset flag of RGM_C0_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + * @param eReset Reset flag + */ +LOCAL_INLINE void RGM_HWA_ClearC0ResetFlagAfterPOR(RGM_CPUResetEventType eReset) +{ + RGM->C0_SSRS = (uint32_t)(eReset); +} + +/** + * @brief This api can clear all reset flag of SSRGM_C0_SSRSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +LOCAL_INLINE void RGM_HWA_ClearC0AllResetFlagAfterPOR(void) +{ + RGM->C0_SSRS = (uint32_t)0xE01FF9FFU; +} +#endif /* #ifndef _HWA_RGM_H_ */ diff --git a/Inc/HwA_rtc.h b/Inc/HwA_rtc.h new file mode 100644 index 0000000..576f811 --- /dev/null +++ b/Inc/HwA_rtc.h @@ -0,0 +1,276 @@ +/** + * @file HwA_rtc.h + * @author Flagchip + * @brief FC7xxx rtc hardware access layer + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_RTC_H_ +#define HWA_INCLUDE_HWA_RTC_H_ + + +#include "device_header.h" + +/** + * @addtogroup HwA_RTC + * @{ + * + */ + +/********* Local typedef ************/ + +/** + * @brief in the second interrupt mode, this type indicates the interrupt frequency. + * in the clkout mode , this type indicates the clkout frequency . + * + * */ +typedef enum +{ + RTC_FREQ_1HZ = 0, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 1Hz */ + RTC_FREQ_2HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 2Hz */ + RTC_FREQ_4HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 4Hz */ + RTC_FREQ_8HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 8Hz */ + RTC_FREQ_16HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 16Hz */ + RTC_FREQ_32hZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 32Hz */ + RTC_FREQ_64HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 64Hz */ + RTC_FREQ_128HZ /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 128Hz */ +} RTC_ClkoutSecIntFreqType; +/********* Local inline function ************/ + +/** + * @brief Read second value + * + * @return Second value + */ +LOCAL_INLINE uint32_t RTC_HWA_ReadSecondValue(void) +{ + return (uint32_t)RTC->SR; +} + +/** + * @brief Read RTC SR overflow flag + * + * @return true means Overflow flag is 1 ;false means Overflow flag is 0. + */ +LOCAL_INLINE bool RTC_HWA_GetOverflowFlag(void) +{ + return (bool)(((RTC->STR & (uint32_t)RTC_STR_TOF_MASK)!=0u)? true:false); +} + +/** + * @brief Read RTC IER overflow enable bit + * + * @return true means enable Overflow Interrupt ;false means disable Overflow Interrupt + */ +LOCAL_INLINE bool RTC_HWA_GetOverflowEnable(void) +{ + return (bool)(((RTC->IER & (uint32_t)RTC_IER_TOIE_MASK)!=0u) ? true:false); +} + +/** + * @brief Read RTC alarm flag + * + * @return true means alarm flag is 1 ;false means alarm flag is 0. + */ +LOCAL_INLINE bool RTC_HWA_GetAlarmFlag(void) +{ + return (bool)(((RTC->STR & (uint32_t)RTC_STR_TAF_MASK)!=0u)?true:false); +} + +/** + * @brief Read RTC alarm Enable + * + * @return true means enable alarm Interrupt ;false means disable alarm Interrupt + */ +LOCAL_INLINE bool RTC_HWA_GetAlarmEnable(void) +{ + return (bool)(((RTC->IER & (uint32_t)RTC_IER_TAIE_MASK)!=0u)?true:false); +} + +/** + * @brief Read RTC second interrupt Enable + * + * @return true means enable second Interrupt ;false means disable second Interrupt + */ +LOCAL_INLINE bool RTC_HWA_GetSecondEnable(void) +{ + return (bool)(((RTC->IER & (uint32_t)RTC_IER_TSIE_MASK)!=0u)?true:false); +} + +/** + * @brief Set RTC prescaler register + * + * @param u16Value PR register value + */ +LOCAL_INLINE void RTC_HWA_SetPrescalerCounterValue(uint16_t u16Value) +{ + RTC->PR = (uint32_t)u16Value; +} + +/** + * @brief Set RTC seconds register + * + * @param u32Value SR register value + */ +LOCAL_INLINE void RTC_HWA_SetSecondCounterValue(uint32_t u32Value) +{ + RTC->SR = u32Value; +} + +/** + * @brief Set RTC alarm value + * + * @param u32Value TAR register value + */ +LOCAL_INLINE void RTC_HWA_SetAlarmCounterValue(uint32_t u32Value) +{ + RTC->AR = u32Value; +} + +/** + * @brief Set RTC interrupt value + * + * @param u32Value IER register value + */ +LOCAL_INLINE void RTC_HWA_SetInterruptValue(uint32_t u32Value) +{ + RTC->IER = u32Value; +} + +/** + * @brief Configure control register + * + * @param u32Value Control value + */ +LOCAL_INLINE void RTC_HWA_ConfigControl(uint32_t u32Value) +{ + RTC->CR = u32Value; +} + +/** + * @brief Enable RTC time counter + * + */ +LOCAL_INLINE void RTC_HWA_EnableRtcCounter(void) +{ + RTC->STR |= (uint32_t)RTC_STR_TCE_MASK; +} + +/** + * @brief Set RTC_CLKOUT is from the 32.768 khz clock + * + */ +LOCAL_INLINE void RTC_HWA_SetClkoutFreqStable(void) +{ + RTC->CR |= (uint32_t)RTC_CR_CKPS_MASK; +} + +/** + * @brief Enable alarm interrupt + * + */ +LOCAL_INLINE void RTC_HWA_EnableAlarmInterrupt(void) +{ + RTC->IER |= (uint32_t)RTC_IER_TAIE_MASK; +} + +/** + * @brief Enable second interrupt + * + */ +LOCAL_INLINE void RTC_HWA_EnableSecondInterrupt(void) +{ + RTC->IER |= (uint32_t)RTC_IER_TSIE_MASK; +} + +/** + * @brief Enable overflow interrupt + * + */ +LOCAL_INLINE void RTC_HWA_EnableOverflowInterrupt(void) +{ + RTC->IER |= (uint32_t)RTC_IER_TOIE_MASK; +} + +/** + * @brief Unlock lock/status/control/compensation register + * + */ +LOCAL_INLINE void RTC_HWA_UnlockStatusControlCompensationReg(void) +{ + RTC->LR |= (uint32_t)(RTC_LR_LRL_MASK | RTC_LR_STRL_MASK | RTC_LR_CRL_MASK | RTC_LR_CPL_MASK); +} + +/** + * @brief Set second interrupt and RTC_CLKOUT frequency + * + * @param eFreq Frequency value + */ +LOCAL_INLINE void RTC_HWA_SetSecondAndClkoutFreq(RTC_ClkoutSecIntFreqType eFreq) +{ + uint32_t u32RegValue = RTC->IER; + RTC->IER &= ~(uint32_t)RTC_IER_TSIE_MASK; + RTC->IER = (u32RegValue & ~(uint32_t)RTC_IER_TSIC_MASK) | RTC_IER_TSIC(eFreq); +} + +/** + * @brief Disable RTC time counter + * + */ +LOCAL_INLINE void RTC_HWA_DisableRtcCounter(void) +{ + RTC->STR &= ~(uint32_t)RTC_STR_TCE_MASK; +} + +/** + * @brief Set RTC_CLKOUT is from the prescaler output clock selected by IER[TSIC] + * + */ +LOCAL_INLINE void RTC_HWA_SetClkoutFromSelectFreq(void) +{ + RTC->CR &= ~(uint32_t)RTC_CR_CKPS_MASK; +} + +/** + * @brief Disable alarm interrupt + * + */ +LOCAL_INLINE void RTC_HWA_DisableAlarmInterrupt(void) +{ + RTC->IER &= ~(uint32_t)RTC_IER_TAIE_MASK; +} + +/** + * @brief Disable second interrupt + * + */ +LOCAL_INLINE void RTC_HWA_DisableSecondInterrupt(void) +{ + RTC->IER &= ~(uint32_t)RTC_IER_TSIE_MASK; +} + +/** + * @brief Disable overflow interrupt + * + */ +LOCAL_INLINE void RTC_HWA_DisableOverflowInterrupt(void) +{ + RTC->IER &= ~(uint32_t)RTC_IER_TOIE_MASK; +} + + + +/** @}*/ /* HwA_RTC */ +#endif /* HWA_INCLUDE_HWA_RTC_H_ */ diff --git a/Inc/HwA_scg.h b/Inc/HwA_scg.h new file mode 100644 index 0000000..efd3664 --- /dev/null +++ b/Inc/HwA_scg.h @@ -0,0 +1,917 @@ +/** + * @file HwA_SCG.h + * @author Flagchip + * @brief FC7xxx SCG hardware access layer + * @version 0.1.0 + * @date 2023-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _HWA_SCG_H_ +#define _HWA_SCG_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_SCG + * @{ + * + */ +/********* macros ************/ +#define UNKNOWN_CLOCK 0xFFFFFFFFU + +#define SCG_CORE_CLOCK_SYMBOL CORE +#define SCG_BUS_CLOCK_SYMBOL BUS +#define SCG_SLOW_CLOCK_SYMBOL SLOW +#define SCG_SIRC_CLOCK_SYMBOL SIRC +#define SCG_SIRC32K_CLOCK_SYMBOL SIRC32K +#define SCG_FIRC_CLOCK_SYMBOL FIRC +#define SCG_FOSC_CLOCK_SYMBOL FOSC +#define SCG_SOSC_CLOCK_SYMBOL SOSC +#define SCG_PLL0_CLOCK_SYMBOL PLL0 +#define SCG_PLL1_CLOCK_SYMBOL PLL1 + +/* PLL related */ +#define SCG_PLLCSR_LK_MASK 0x800000u +#define SCG_PLLCSR_EN_MASK 0x1u +#define SCG_PLLCSR_CMRE_MASK 0x20000u +#define SCG_PLLCSR_CMRE_SHIFT 17u +#define SCG_PLLCSR_CMRE(x) (((uint32_t)(((uint32_t)(x))<_pll_##CSR = val +#define SCG_HWA_SetPllCsr(pll, val) _SCG_HWA_SetPllCsr(pll, val) + +#define _SCG_HWA_UnlockPllCsr(_pll_) SCG->_pll_##CSR &= ~(uint32_t)SCG_PLLCSR_LK_MASK +#define SCG_HWA_UnlockPllCsr(pll) _SCG_HWA_UnlockPllCsr(pll) + +#define _SCG_HWA_LockPllCsr(_pll_) SCG->_pll_##CSR |= (uint32_t)SCG_PLLCSR_LK_MASK +#define SCG_HWA_LockPllCsr(pll) _SCG_HWA_LockPllCsr(pll) + +#define _SCG_HWA_EnablePllClockMonitor(_pll_) SCG->_pll_##CSR |= (uint32_t)SCG_PLLCSR_CM_MASK +#define SCG_HWA_EnablePllClockMonitor(pll) _SCG_HWA_EnablePllClockMonitor(pll) + +#define _SCG_HWA_EnablePllClockMonitorReset(_pll_) SCG->_pll_##CSR |= (uint32_t)SCG_PLLCSR_CMRE_MASK +#define SCG_HWA_EnablePllClockMonitorReset(pll) _SCG_HWA_EnablePllClockMonitorReset(pll) + +#define _SCG_HWA_SetPllCfg(_pll_, val) SCG->_pll_##CFG = val +#define SCG_HWA_SetPllCfg(pll, val) _SCG_HWA_SetPllCfg(pll, val) + +#define _SCG_HWA_SetPllDiv(_pll_, val) SCG->_pll_##DIV = val +#define SCG_HWA_SetPllDiv(pll, val) _SCG_HWA_SetPllDiv(pll, val) + +#define _SCG_HWA_EnablePll(_pll_) SCG->_pll_##CSR |= (uint32_t)(SCG_PLLCSR_EN_MASK) +#define SCG_HWA_EnablePll(pll) _SCG_HWA_EnablePll(pll) + + + +#define _SCG_HWA_GetPllMult(_pll_) (uint32_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_MULT_MASK) >> SCG_PLLCFG_MULT_SHIFT) +#define SCG_HWA_GetPllMult(pll) _SCG_HWA_GetPllMult(pll) + +#define _SCG_HWA_GetPllPrediv(_pll_) (uint32_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_PREDIV_MASK) >> SCG_PLLCFG_PREDIV_SHIFT) +#define SCG_HWA_GetPllPrediv(pll) _SCG_HWA_GetPllPrediv(pll) + +#define _SCG_HWA_GetPllPstdiv(_pll_) (uint32_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_PSTDIV_MASK) >> SCG_PLLCFG_PSTDIV_SHIFT) +#define SCG_HWA_GetPllPstdiv(pll) _SCG_HWA_GetPllPstdiv(pll) + +#define _SCG_HWA_GetPllSrc(_pll_) (uint32_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_SOURCE_MASK) >> SCG_PLLCFG_SOURCE_SHIFT) +#define SCG_HWA_GetPllSrc(pll) _SCG_HWA_GetPllSrc(pll) + +/* Clock valid and div related */ +#define _SCG_HWA_GetClockVliad(_clock_) (bool)((((uint32_t)SCG->_clock_##CSR & (uint32_t)SCG_##_clock_##CSR_VLD_MASK) != 0U) ? true : false) +#define SCG_HWA_GetClockVliad(_clock_) _SCG_HWA_GetClockVliad(_clock_) + +#define _SCG_HWA_GetClockDiv(_clock_) (uint32_t)SCG->_clock_##DIV +#define SCG_HWA_GetClockDiv(_clock_) _SCG_HWA_GetClockDiv(_clock_) + +#define SCG_CLOCKDIV_DIVL_ACK_MASK 0x40000000u +#define SCG_CLOCKDIV_DIVM_ACK_MASK 0x20000000u +#define SCG_CLOCKDIV_DIVH_ACK_MASK 0x10000000u +#define SCG_CLOCKDIV_DIVL_ACK_SHIFT 30u +#define SCG_CLOCKDIV_DIVM_ACK_SHIFT 29u +#define SCG_CLOCKDIV_DIVH_ACK_SHIFT 28u + +#define SCG_CLOCKDIV_DIVL_EN_MASK 0x4000000u +#define SCG_CLOCKDIV_DIVM_EN_MASK 0x2000000u +#define SCG_CLOCKDIV_DIVH_EN_MASK 0x1000000u +#define SCG_CLOCKDIV_DIVL_EN_SHIFT 26u +#define SCG_CLOCKDIV_DIVM_EN_SHIFT 25u +#define SCG_CLOCKDIV_DIVH_EN_SHIFT 24u + +#define SCG_CLOCKDIV_EN2ACK_SHIFT 4u + +#define SCG_CLOCKDIV_DIVL_VAL_MASK 0x70000u +#define SCG_CLOCKDIV_DIVM_VAL_MASK 0x700u +#define SCG_CLOCKDIV_DIVH_VAL_MASK 0x7u +#define SCG_CLOCKDIV_DIVL_VAL_SHIFT 16u +#define SCG_CLOCKDIV_DIVM_VAL_SHIFT 8u +#define SCG_CLOCKDIV_DIVH_VAL_SHIFT 0u + +#define SCG_CHECK_DIVL_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIVL_ACK_MASK) >> SCG_CLOCKDIV_DIVL_ACK_SHIFT) +#define SCG_CHECK_DIVM_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIVM_ACK_MASK) >> SCG_CLOCKDIV_DIVM_ACK_SHIFT) +#define SCG_CHECK_DIVH_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIVH_ACK_MASK) >> SCG_CLOCKDIV_DIVH_ACK_SHIFT) +#define SCG_CHECK_DIVL_EN(reg_val) ((reg_val & SCG_CLOCKDIV_DIVL_EN_MASK) >> SCG_CLOCKDIV_DIVL_EN_SHIFT) +#define SCG_CHECK_DIVM_EN(reg_val) ((reg_val & SCG_CLOCKDIV_DIVM_EN_MASK) >> SCG_CLOCKDIV_DIVM_EN_SHIFT) +#define SCG_CHECK_DIVH_EN(reg_val) ((reg_val & SCG_CLOCKDIV_DIVH_EN_MASK) >> SCG_CLOCKDIV_DIVH_EN_SHIFT) +#define SCG_GET_DIVL_VAL(reg_val) ((0U == ((reg_val & SCG_CLOCKDIV_DIVL_VAL_MASK) >> SCG_CLOCKDIV_DIVL_VAL_SHIFT)) ? 1U : ((reg_val & SCG_CLOCKDIV_DIVL_VAL_MASK) >> SCG_CLOCKDIV_DIVL_VAL_SHIFT)) +#define SCG_GET_DIVM_VAL(reg_val) ((0U == ((reg_val & SCG_CLOCKDIV_DIVM_VAL_MASK) >> SCG_CLOCKDIV_DIVM_VAL_SHIFT)) ? 1U : ((reg_val & SCG_CLOCKDIV_DIVM_VAL_MASK) >> SCG_CLOCKDIV_DIVM_VAL_SHIFT)) +#define SCG_GET_DIVH_VAL(reg_val) ((0U == ((reg_val & SCG_CLOCKDIV_DIVH_VAL_MASK) >> SCG_CLOCKDIV_DIVH_VAL_SHIFT)) ? 1U : ((reg_val & SCG_CLOCKDIV_DIVH_VAL_MASK) >> SCG_CLOCKDIV_DIVH_VAL_SHIFT)) +#define SCG_CALCULATE_DIVL_FREQ(clk_freq, reg_val) (((1U == SCG_CHECK_DIVL_EN(reg_val)) && (clk_freq != UNKNOWN_CLOCK)) ? (uint32_t)clk_freq >> (uint8_t)(SCG_GET_DIVL_VAL(reg_val) - 1U) : (uint32_t)UNKNOWN_CLOCK) +#define SCG_CALCULATE_DIVM_FREQ(clk_freq, reg_val) (((1U == SCG_CHECK_DIVM_EN(reg_val)) && (clk_freq != UNKNOWN_CLOCK)) ? (uint32_t)clk_freq >> (uint8_t)(SCG_GET_DIVM_VAL(reg_val) - 1U) : (uint32_t)UNKNOWN_CLOCK) +#define SCG_CALCULATE_DIVH_FREQ(clk_freq, reg_val) (((1U == SCG_CHECK_DIVH_EN(reg_val)) && (clk_freq != UNKNOWN_CLOCK)) ? (uint32_t)clk_freq >> (uint8_t)(SCG_GET_DIVH_VAL(reg_val) - 1U) : (uint32_t)UNKNOWN_CLOCK) + + +typedef enum +{ + SCG_CLOCK_DIV_H = 0x01000000U, /* DIVH clock enable bit [24] */ + SCG_CLOCK_DIV_M = 0x02000000U, /* DIVM clock enable bit [25] */ + SCG_CLOCK_DIV_L = 0x04000000U, /* DIVL clock enable bit [26] */ + SCG_CLOCK_DIV_ALL = 0x07000000U, /* DIVH DIVM DIVL clock enable bit [26:24] */ +}SCG_DivEnableType; + +/********* Local inline function ************/ + +/** + * @brief Get clock out configure register CLKOUTSEL value + */ +LOCAL_INLINE uint8_t SCG_HWA_GetClkOutSel(void) +{ + return (uint8_t)(((uint32_t)SCG->CLKOUTCFG & SCG_CLKOUTCFG_CLKOUTSEL_MASK) >> SCG_CLKOUTCFG_CLKOUTSEL_SHIFT); +} + +/** + * @brief Get clock out configure register value + */ +LOCAL_INLINE uint32_t SCG_HWA_GetClkOutCfg(void) +{ + return SCG->CLKOUTCFG; +} + +/** + * @brief Unlock SOSC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_UnlockSoscCsrReg(void) +{ + SCG->SOSCCSR &= ~(uint32_t)(SCG_SOSCCSR_LK_MASK); +} + +/** + * @brief Lock SOSC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_LockSoscCsrReg(void) +{ + SCG->SOSCCSR |= (uint32_t)(SCG_SOSCCSR_LK_MASK); +} + +/** + * @brief Enable SOSC clock monitor + * + */ +LOCAL_INLINE void SCG_HWA_EnableSoscClockMonitor(void) +{ + SCG->SOSCCSR |= (uint32_t)(SCG_SOSCCSR_CM_MASK); +} + +/** + * @brief Enable SOSC clock monitor Reset + * + */ +LOCAL_INLINE void SCG_HWA_EnableSoscClockMonitorReset(void) +{ + SCG->SOSCCSR |= (uint32_t)(SCG_SOSCCSR_CMRE_MASK); +} + +/** + * @brief Set SOSC enable + */ +LOCAL_INLINE void SCG_HWA_EnableSosc(void) +{ + SCG->SOSCCSR |= (uint32_t)SCG_SOSCCSR_EN_MASK; +} + +/** + * @brief Diable SOSC + */ +LOCAL_INLINE void SCG_HWA_DisableSosc(void) +{ + SCG->SOSCCSR &= ~(uint32_t)SCG_SOSCCSR_EN_MASK; +} + +/** + * @brief Set recommend value to SOSCCFG register + * + */ +LOCAL_INLINE void SCG_HWA_SetSoscRecommendCfg(void) +{ + SCG->SOSCCFG = (uint32_t)(SCG_SOSCCFG_EOCV(64U) | SCG_SOSCCFG_GM_SEL(3U) | SCG_SOSCCFG_CURPRG_SF(3U) | SCG_SOSCCFG_CURPRG_COMP(3U)); +} + +/** + * @brief Set SOSC CSR register value + * + * @param u32CsrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSoscCsr(uint32_t u32CsrValue) +{ + SCG->SOSCCSR = u32CsrValue; +} + +/** + * @brief Get SOSC CSR register value + * + */ +LOCAL_INLINE uint32_t SCG_HWA_GetSoscCsr(void) +{ + return (uint32_t)SCG->SOSCCSR; +} + +/********* Fosc Register interface ************/ +/** + * @brief Enable FOSC + */ +LOCAL_INLINE void SCG_HWA_EnableFosc(void) +{ + SCG->FOSCCSR |= (uint32_t)SCG_FOSCCSR_EN_MASK; +} + +/** + * @brief Disable FOSC + */ +LOCAL_INLINE void SCG_HWA_DisableFosc(void) +{ + SCG->FOSCCSR &= ~SCG_FOSCCSR_EN_MASK; +} + +/** + * @brief Set FOSCCFG register value + * + * @param u32CfgValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFoscCfg(uint32_t u32CfgValue) +{ + SCG->FOSCCFG = u32CfgValue; +} + +/** + * @brief Set FOSCCSR register value + * + * @param u32CsrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFoscCsr(uint32_t u32CsrValue) +{ + SCG->FOSCCSR = u32CsrValue; +} + +/** + * @brief Get FOSCCSR register value + * + */ +LOCAL_INLINE uint32_t SCG_HWA_GetFoscCsr(void) +{ + return (uint32_t)SCG->FOSCCSR; +} + +/** + * @brief Unlock FOSC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_UnlockFoscCsrReg(void) +{ + SCG->FOSCCSR &= ~(uint32_t)(SCG_FOSCCSR_LK_MASK); +} + +/** + * @brief lock FOSC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_LockFoscCsrReg(void) +{ + SCG->FOSCCSR |= (uint32_t)(SCG_FOSCCSR_LK_MASK); +} + +/** + * @brief Enable FOSC clock monitor + * + */ +LOCAL_INLINE void SCG_HWA_EnableFoscClockMonitor(void) +{ + SCG->FOSCCSR |= (uint32_t)(SCG_FOSCCSR_CM_MASK); +} + +/** + * @brief Enable FOSC clock monitor Reset + * + */ +LOCAL_INLINE void SCG_HWA_EnableFoscClockMonitorReset(void) +{ + SCG->FOSCCSR |= (uint32_t)(SCG_FOSCCSR_CMRE_MASK); +} + +/** + * @brief enable FOSCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_EnableFoscDiv(SCG_DivEnableType DivEn) +{ + SCG->FOSCDIV |= (uint32_t)DivEn; +} + +/** + * @brief Disable FOSCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_DiableFoscDiv(SCG_DivEnableType DivEn) +{ + SCG->FOSCDIV &= ~(uint32_t)DivEn; +} + +/** + * @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnableFoscDiv + * @param DivEn the or value of SCG_DivEnableType + * @return bool true : The enabled DIV clocks are acknowledged + * false : The enabled DIV clocks are not acknowledged + */ +LOCAL_INLINE bool SCG_HWA_GetFoscDivAck(SCG_DivEnableType DivEn) +{ + return (bool)((SCG->FOSCDIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)); +} + +/** + * @brief Set FOSCDIV register value + * + * @param u32DivValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFoscDiv(uint32_t u32DivValue) +{ + SCG->FOSCDIV = u32DivValue; +} + +/** + * @brief Set Low Power Wakeup WDOG Register + * + * @param u8MSBVal Most Significant value, if OSC is 40M + * and FOSC not valid after 1.8ms wakeup, + * the chip will reset and RGM register will + * report clock error reset reason. + */ +LOCAL_INLINE void SCG_HWA_SetWKPWDG(uint8_t u8MSBVal) +{ + SCG->WKPWDG = SCG_WKPWDG_MSB(u8MSBVal) | SCG_WKPWDG_EN_MASK; +} + + + +/********* Sirc Register interface ************/ +/** + * @brief Set SIRCCSR register value + * + * @param u32CsrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSircCsr(uint32_t u32CsrValue) +{ + SCG->SIRCCSR = u32CsrValue; +} + +/** + * @brief Get SIRCCSR register value + * + */ +LOCAL_INLINE uint32_t SCG_HWA_GetSircCsr(void) +{ + return (uint32_t)SCG->SIRCCSR; +} + +/** + * @brief Unlock SIRC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_UnlockSircCsrReg(void) +{ + SCG->SIRCCSR &= ~(uint32_t)SCG_SIRCCSR_LK_MASK; +} + +/** + * @brief Lock SIRC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_LockSircCsrReg(void) +{ + SCG->SIRCCSR |= (uint32_t)SCG_SIRCCSR_LK_MASK; +} + +/** + * @brief Enable SIRC clock monitor + * + */ +LOCAL_INLINE void SCG_HWA_EnableSircClockMonitor(void) +{ + SCG->SIRCCSR |= (uint32_t)(SCG_SIRCCSR_CM_MASK); +} + +/** + * @brief Set SIRCDIV register value + * + * @param u32DivValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSircDiv(uint32_t u32DivValue) +{ + SCG->SIRCDIV = u32DivValue; +} + +/** + * @brief enable SIRCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_EnableSircDiv(SCG_DivEnableType DivEn) +{ + SCG->SIRCDIV |= (uint32_t)DivEn; +} + +/** + * @brief Disable SIRCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_DiableSircDiv(SCG_DivEnableType DivEn) +{ + SCG->SIRCDIV &= ~(uint32_t)DivEn; +} + +/** + * @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnableSircDiv + * @param DivEn the or value of SCG_DivEnableType + * @return bool true : The enabled DIV clocks are acknowledged + * false : The enabled DIV clocks are not acknowledged + */ +LOCAL_INLINE bool SCG_HWA_GetSircDivAck(SCG_DivEnableType DivEn) +{ + return (bool)((SCG->SIRCDIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)); +} + +/** + * @brief Set SIRCTCFG register value for SIRC Trim configure. + * + * @param u32TcfgValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSircTcfg(uint32_t u32TcfgValue) +{ + SCG->SIRCTCFG = u32TcfgValue; +} + +/********* Sirc32k Register interface ************/ +/** + * @brief Enable SIRC32KCSR register + * + */ +LOCAL_INLINE void SCG_HWA_EnableSirc32kCsr(void) +{ + SCG->SIRC32KCSR |= (uint32_t)SCG_SIRC32KCSR_EN_MASK; +} + +/** + * @brief Disable SIRC32KCSR register + * + */ +LOCAL_INLINE void SCG_HWA_DisableSirc32kCsr(void) +{ + SCG->SIRC32KCSR &= ~(uint32_t)SCG_SIRC32KCSR_EN_MASK; +} + +/** + * @brief Unlock SIRC32K CSR register + */ +LOCAL_INLINE void SCG_HWA_UnlockSirc32kCsrReg(void) +{ + SCG->SIRC32KCSR &= ~(uint32_t)(SCG_SIRC32KCSR_LK_MASK); +} + +/** + * @brief Lock SIRC32K CSR register + */ +LOCAL_INLINE void SCG_HWA_LockSirc32kCsrReg(void) +{ + SCG->SIRC32KCSR |= (uint32_t)(SCG_SIRC32KCSR_LK_MASK); +} + +/********* Firc Register interface ************/ +/** + * @brief Get FIRC CSR register value. + */ +LOCAL_INLINE uint32_t SCG_HWA_GetFircCsr(void) +{ + return (uint32_t)SCG->FIRCCSR; +} + +/** + * @brief Enable FIRC. + */ +LOCAL_INLINE void SCG_HWA_EnableFirc(void) +{ + SCG->FIRCCSR |= (uint32_t)SCG_FIRCCSR_EN_MASK; +} + +/** + * @brief Unlock FIRC CSR register + */ +LOCAL_INLINE void SCG_HWA_UnlockFircCsrReg(void) +{ + SCG->FIRCCSR &= ~(uint32_t)(SCG_FIRCCSR_LK_MASK); +} + +/** + * @brief Lock FIRC CSR register + */ +LOCAL_INLINE void SCG_HWA_LockFircCsrReg(void) +{ + SCG->FIRCCSR |= (uint32_t)(SCG_FIRCCSR_LK_MASK); +} + +/** + * @brief Enable FIRC clock monitor + * + */ +LOCAL_INLINE void SCG_HWA_EnableFircClockMonitor(void) +{ + SCG->FIRCCSR |= (uint32_t)(SCG_FIRCCSR_CM_MASK); +} + +/** + * @brief Disable FIRC. + */ +LOCAL_INLINE void SCG_HWA_DisableFirc(void) +{ + SCG->FIRCCSR &= ~(uint32_t)SCG_FIRCCSR_EN_MASK; +} + +/** + * @brief Set FIRCCSR register value + * + * @param u32CsrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFircCsr(uint32_t u32CsrValue) +{ + SCG->FIRCCSR = u32CsrValue; +} + +/** + * @brief Set FIRCCFG register value + * + * @param u32CfgValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFircCfg(uint32_t u32CfgValue) +{ + SCG->FIRCCFG = u32CfgValue; +} + +/** + * @brief Set FOSCDIV register value + * + * @param u32DivValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFircDiv(uint32_t u32DivValue) +{ + SCG->FIRCDIV = u32DivValue; +} + +/** + * @brief enable FIRCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_EnableFircDiv(SCG_DivEnableType DivEn) +{ + SCG->FIRCDIV |= (uint32_t)DivEn; +} + +/** + * @brief Disable FIRCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_DiableFircDiv(SCG_DivEnableType DivEn) +{ + SCG->FIRCDIV &= ~(uint32_t)DivEn; +} + +/** + * @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnableFircDiv + * @param DivEn the or value of SCG_DivEnableType + * @return bool true : The enabled DIV clocks are acknowledged + * false : The enabled DIV clocks are not acknowledged + */ +LOCAL_INLINE bool SCG_HWA_GetFircDivAck(SCG_DivEnableType DivEn) +{ + return (bool)((SCG->FIRCDIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)); +} + +/** + * @brief Set FIRCTCFG register value for FIRC clock trim configure. + * + * @param u32TcfgValue configured register value. + */ +LOCAL_INLINE void SCG_HWA_SetFircTcfg(uint32_t u32TcfgValue) +{ + SCG->FIRCTCFG = u32TcfgValue; +} + + +/********* PLL0 clock Register interface ************/ +/** + * @brief enable PLL0DIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_EnablePll0Div(SCG_DivEnableType DivEn) +{ + SCG->PLL0DIV |= (uint32_t)DivEn; +} + +/** + * @brief Disable FOSCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_DiablePll0Div(SCG_DivEnableType DivEn) +{ + SCG->PLL0DIV &= ~(uint32_t)DivEn; +} + +/** + * @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnablePll0Div + * @param DivEn the or value of SCG_DivEnableType + * @return bool true : The enabled DIV clocks are acknowledged + * false : The enabled DIV clocks are not acknowledged + */ +LOCAL_INLINE bool SCG_HWA_GetPll0DivAck(SCG_DivEnableType DivEn) +{ + return (bool)((SCG->PLL0DIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)); +} + + +/********* PLL1 clock Register interface ************/ +/** + * @brief enable PLL0DIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_EnablePll1Div(SCG_DivEnableType DivEn) +{ + SCG->PLL1DIV |= (uint32_t)DivEn; +} + +/** + * @brief Disable FOSCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_DiablePll1Div(SCG_DivEnableType DivEn) +{ + SCG->PLL1DIV &= ~(uint32_t)DivEn; +} + +/** + * @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnablePll1Div + * @param DivEn the or value of SCG_DivEnableType + * @return bool true : The enabled DIV clocks are acknowledged + * false : The enabled DIV clocks are not acknowledged + */ +LOCAL_INLINE bool SCG_HWA_GetPll1DivAck(SCG_DivEnableType DivEn) +{ + return (bool)((SCG->PLL1DIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)); +} + +/********* System clock Register interface ************/ +/** + * @brief Get system clock CCR register value + * + * @return system clock CCR register value + */ +LOCAL_INLINE uint32_t SCG_HWA_GetCCR(void) +{ + return SCG->CCR; +} + +/** + * @brief Set system clock CCR register value + * + * @param u32CcrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetCCR(uint32_t u32CcrValue) +{ + SCG->CCR = u32CcrValue; +} + +/** + * @brief Set system clock + * + * @param u8SystemCLock System clock value + */ +LOCAL_INLINE void SCG_HWA_SetSystemClock(uint8_t u8SystemCLock) +{ + SCG->CCR = ((SCG->CCR & ~(uint32_t)SCG_CCR_SCS_MASK) | SCG_CCR_SCS(u8SystemCLock)); +} + +/** + * @brief Get system clock source. used to calculate system clock frequency at startup. + * used to check if the target clock soure successfully switched. + * @return uint8_t. system clock source. + */ +LOCAL_INLINE uint8_t SCG_HWA_GetSysClkSrc(void) +{ + return (uint8_t)(((uint32_t)(SCG->CSR) & (uint32_t)SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT); +} + +/** + * @brief Get system clock valid status, use this status to check system clock update finished or not. + * @return bool. true as updated; false as not updated. + */ +LOCAL_INLINE bool SCG_HWA_GetSysClkUPRD(void) +{ + return (bool)((((uint32_t)SCG->CSR & (uint32_t)SCG_CSR_CCR_UPRD_MASK) != 0U) ? true : false); +} + +/** + * @brief Get system clock Divcore. used to calculate core clock frequency at startup. + * @return uint8_t. system clock Divcore. + */ +LOCAL_INLINE uint8_t SCG_HWA_GetSysClkDivCore(void) +{ + return (uint8_t)(((uint32_t)(SCG->CSR) & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT); +} + +/** + * @brief Get system clock Divbus. used to calculate bus clock frequency at startup. + * @return uint8_t. system clock Divbus. + */ +LOCAL_INLINE uint8_t SCG_HWA_GetSysClkDivBus(void) +{ + return (uint8_t)(((uint32_t)(SCG->CSR) & SCG_CSR_DIVBUS_MASK) >> SCG_CSR_DIVBUS_SHIFT); +} + +/** + * @brief Get system clock Divslow. used to calculate slow clock frequency at startup. + * @return uint8_t. system clock Divslow. + */ +LOCAL_INLINE uint8_t SCG_HWA_GetSysClkDivSlow(void) +{ + return (uint8_t)(((uint32_t)(SCG->CSR) & SCG_CSR_DIVSLOW_MASK) >> SCG_CSR_DIVSLOW_SHIFT); +} + +/********* Clkout Register interface ************/ +/** + * @brief Select clock out source + * + * @param u8ClkOutSel Clock out select + */ +LOCAL_INLINE void SCG_HWA_SetClkOutSel(uint8_t u8ClkOutSel) +{ + SCG->CLKOUTCFG = ((SCG->CLKOUTCFG & ~(uint32_t)SCG_CLKOUTCFG_CLKOUTSEL_MASK) | SCG_CLKOUTCFG_CLKOUTSEL(u8ClkOutSel)); +} + +/** + * @brief Set Nvm clock source + * + * @param u32NvmClkMask Nvm clock source mask + */ +LOCAL_INLINE void SCG_HWA_SetNvmClk(uint32_t u32NvmClkMask) +{ + SCG->CLKOUTCFG &= ~(uint32_t)(SCG_CLKOUTCFG_NVMCLK_FIRC_MASK | SCG_CLKOUTCFG_NVMCLK_SIRC_MASK); + SCG->CLKOUTCFG |= u32NvmClkMask; +} + +/** + * @brief Set CMU4 clock source + * + * @param u32Cmu4ClkMask CMU4 clock source mask + */ +LOCAL_INLINE void SCG_HWA_SetCmu4Clk(uint32_t u32Cmu4ClkMask) +{ + SCG->CLKOUTCFG &= ~(uint32_t)(SCG_CLKOUTCFG_CMU4CLK_FOSC_MASK | SCG_CLKOUTCFG_CMU4CLK_SIRC_MASK); + SCG->CLKOUTCFG |= u32Cmu4ClkMask; +} + +/********* CRC Register interface ************/ +/** + * @brief Generate SCG register CRC value + */ +LOCAL_INLINE void SCG_HWA_GenCrcVal(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_GEN_MASK; +} + +/** + * @brief Enable SCG register CRC check + */ +LOCAL_INLINE void SCG_HWA_EnableCrcCheck(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_CHKEN_MASK; +} + +/** + * @brief Disable SCG register CRC check + */ +LOCAL_INLINE void SCG_HWA_DisableCrcCheck(void) +{ + SCG->CRCCSR &= ~(uint32_t)SCG_CRCCSR_CHKEN_MASK; +} + +/** + * @brief Enable SCG register CRC error output + */ +LOCAL_INLINE void SCG_HWA_EnableCrcErrorOutput(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_EOEN_MASK; +} + +/** + * @brief Disable SCG register CRC error output + */ +LOCAL_INLINE void SCG_HWA_DisableCrcErrorOutput(void) +{ + SCG->CRCCSR &= ~(uint32_t)SCG_CRCCSR_EOEN_MASK; +} + +/** + * @brief Get CRC busy status + */ +LOCAL_INLINE bool SCG_HWA_GetCrcBusyStatus(void) +{ + return (0U != (SCG->CRCCSR & (uint32_t)SCG_CRCCSR_BUSY_MASK)); +} + +/** + * @brief Get CRC error status + */ +LOCAL_INLINE bool SCG_HWA_GetCrcErrorStatus(void) +{ + return (0U != (SCG->CRCCSR & (uint32_t)SCG_CRCCSR_ERR_MASK)); +} + +/** + * @brief Clear CRC error flag + */ +LOCAL_INLINE void SCG_HWA_ClearCrcErrorFlag(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_ERR_MASK; +} + +/** + * @brief Get CRC result + */ +LOCAL_INLINE uint32_t SCG_HWA_GetCrcResult(void) +{ + return SCG->CRCRES; +} + +/** + * @brief Enable SCG register CRC trigger mode + */ +LOCAL_INLINE void SCG_HWA_EnableCrcTriggerMode(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_TRGEN_MASK; +} + +/** + * @brief Disable SCG register CRC trigger mode + */ +LOCAL_INLINE void SCG_HWA_DisableCrcTriggerMode(void) +{ + SCG->CRCCSR &= ~(uint32_t)SCG_CRCCSR_TRGEN_MASK; +} + +/** @}*/ /* HwA_SCG */ + +#endif /* #ifndef _HWA_SCG_H_ */ diff --git a/Inc/HwA_scm.h b/Inc/HwA_scm.h new file mode 100644 index 0000000..40e5e72 --- /dev/null +++ b/Inc/HwA_scm.h @@ -0,0 +1,2388 @@ +/** + * @file HwA_scm.h + * @author Flagchip085 + * @brief Hardware access layer for SCM + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_SCM_H_ +#define _HWA_SCM_H_ +#include "device_header.h" + +/********* Local typedef ************/ + +/** + * @brief WPB cpu type + * + */ +typedef enum +{ + SCM_WP_CPU_ALL = 0U, /*!< All CPUs are allowed to write this peripheral */ + SCM_WP_CPU_0 = 1U, /*!< Only CPU0 is allowed to control this peripheral */ + SCM_WP_CPU_NONE /*!< No CPU is allowed to control this peripheral */ +} SCM_WPB_CpuType; + +/** + * @brief ECC Enable mode Control type + * + */ +typedef enum +{ + SCM_ECC_WRITE_EN_READ_DIS = 2U, /*!< ECC Generate Enable During Write, ECC Check Disable During Read */ + SCM_ECC_WRITE_EN_READ_EN = 3U /*!< ECC Generate Enable During Write, ECC Check Enable During Read */ +} SCM_EccEnModeType; + +/** + * @brief MAMECCEN0 MAM ECC Enable group 0 type + * + */ +typedef enum +{ + SCM_MAM0_S0_ECC = 0U, /*!< MAM0 S0 ROM Array ECC Enable Control */ + SCM_MAM0_S1_ECC = 1U, /*!< MAM0 S1 PFlash Slave ECC Enable Control */ + SCM_MAM0_S2_ECC = 3U, /*!< MAM0 S2 DFlash Slave ECC Enable Control */ + SCM_MAM0_S3_ECC = 4U, /*!< MAM0 S3 SRAM0 Slave ECC Enable Control */ + SCM_MAM0_S4_ECC = 5U, /*!< MAM0 S4 SRAM1 Slave ECC Enable Control */ + SCM_MAM0_S5_ECC = 7U, /*!< MAM0 S5 TCM Slave ECC Enable Control */ + SCM_MAM0_S6_ECC = 8U, /*!< MAM0 S6 AFCB0 Slave ECC Enable Control */ + SCM_MAM0_S7_ECC = 9U, /*!< MAM0 S7 AFCB1 Slave ECC Enable Control */ + SCM_MAM0_S8_ECC = 10U, /*!< MAM0 S8 GPIO Slave ECC Enable Control */ + SCM_SRAM0_ECC = 11U, /*!< SRAM0 Array ECC Enable Control */ + SCM_SRAM1_ECC = 12U /*!< SRAM1 Array ECC Enable Control */ +} SCM_MAMEccCtrlGrp0Type; + +/** + * @brief MAMECCEN1 MAM ECC Enable group 1 type + * + */ +typedef enum +{ + SCM_HSM_ECC = 0U, /*!< HSM Master ECC Enable Control */ + SCM_DMA0_ECC = 2U, /*!< DMA0 Master ECC Enable Control */ + SCM_DMA0_CFG_ECC = 4U, /*!< DMA0 CFG Memory ECC Enable Control */ + SCM_HSM_DRAM_ECC = 5U, /*!< HSM DRAM Memory ECC Enable Control */ + SCM_HSM_IRAM_ECC = 6U /*!< HSM IRAM Memory ECC Enable Control */ +} SCM_MAMEccCtrlGrp1Type; + +/** + * @brief CPU0 ECC Enable Register type + * + */ +typedef enum +{ + SCM_CPUXECCEN_CPUX_AHBM_ECC = 0U, /*!< SCM_CPUXECCEN_CPUX_AHBM_ECC peripheral */ + SCM_CPUXECCEN_CPUX_AHBP_ECC = 1U, /*!< SCM_CPUXECCEN_CPUX_AHBP_ECC peripheral */ + SCM_CPUXECCEN_CPUX_AHBS_ECC = 2U, /*!< SCM_CPUXECCEN_CPUX_AHBS_ECC peripheral */ + SCM_CPUXECCEN_CPUX_DTCM0_ECC = 3U, /*!< SCM_CPUXECCEN_CPUX_DTCM0_ECC peripheral */ + SCM_CPUXECCEN_CPUX_DTCM1_ECC = 4U, /*!< SCM_CPUXECCEN_CPUX_DTCM1_ECC peripheral */ + SCM_CPUXECCEN_CPUX_ITCM_ECC = 5U /*!< SCM_CPUXECCEN_CPUX_ITCM_ECC peripheral */ +} SCM_CPUEccCtrlType; + +/** + * @brief FCSPI monitor type + * + */ +typedef enum +{ + SCM_MON_FCSPI0 = 0U, /*!< Monitor FCSPI0's transmit interface */ + SCM_MON_FCSPI1, /*!< Monitor FCSPI1's transmit interface */ + SCM_MON_FCSPI2, /*!< Monitor FCSPI2's transmit interface */ + SCM_MON_FCSPI3, /*!< Monitor FCSPI3's transmit interface */ + SCM_MON_FCSPI4, /*!< Monitor FCSPI4's transmit interface */ + SCM_MON_FCSPI5 /*!< Monitor FCSPI5's transmit interface */ +} SCM_FCSPIxType; + +/** + * @brief FCUART monitor type + * + */ +typedef enum +{ + SCM_MON_FCUART0 = 0U, /*!< Monitor FCUART0's transmit interface */ + SCM_MON_FCUART1, /*!< Monitor FCUART1's transmit interface */ + SCM_MON_FCUART2, /*!< Monitor FCUART2's transmit interface */ + SCM_MON_FCUART3, /*!< Monitor FCUART3's transmit interface */ + SCM_MON_FCUART4, /*!< Monitor FCUART4's transmit interface */ + SCM_MON_FCUART5, /*!< Monitor FCUART5's transmit interface */ + SCM_MON_FCUART6, /*!< Monitor FCUART6's transmit interface */ + SCM_MON_FCUART7 /*!< Monitor FCUART7's transmit interface */ +} SCM_MON_FCUARTxType; + +/** + * @brief PTIMER Loop Mode Select type + * + */ +typedef enum +{ + SCM_LM_PTMR0CH0_PTMR1CH0 = 0U,/*!< PTIMER0 CH0 loop, PTIMER1 CH0 loop */ + SCM_LM_PTMR1CH0_CH1 = 1U,/*!< PTIMER1 CH0 and CH1 in loop mode */ + SCM_LM_PTMR0CH0_CH1 = 2U,/*!< PTIMER0 CH0 and CH1 in loop mode */ + SCM_LM_PTMR0CH0CH1_PTMR1CH0CH1 = 3U,/*!< PTIMER1 CH0 and CH1 in loop mode, PTIMER0 CH0 and CH1 in loop mode */ + SCM_LM_PTMR0_PTMR1_CH0 = 4U /*!< PTIMER0 CH0 and PTIMER1 CH0 in loop mode */ +} SCM_PTimerLMSelType; + +/** + * @brief ADC Trigger Source type + * + */ +typedef enum +{ + SCM_ADC_TRIGGER_SRC_PTIMER = 0U, /*!< ADC Trigger Source PTIMER output */ + SCM_ADC_TRIGGER_SRC_TRGSEL = 1U /*!< ADC Trigger Source TRGSEL output */ +} SCM_AdcTriggerSrcType; + +/** + * @brief ADC PreTrigger Source type + * + */ +typedef enum +{ + SCM_ADC_PRETRIGGER_PTIMER = 0U, /*!< ADC Pre-trigger PTIMER */ + SCM_ADC_PRETRIGGER_SCMSOFTWARE = 2U /*!< ADC Pre-trigger SCM software */ +} SCM_AdcPreTriggerSrcType; + +/** + * @brief ADC SCM software Pre-trigger Sources type + * + */ +typedef enum +{ + SCM_SOFTWARE_PRETRIGGER_DISABLED = 0U, /*!< SCM Software pre-trigger disabled */ + SCM_SOFTWARE_PRETRIGGER_0 = 4U, /*!< SCM Software pre-trigger 0 */ + SCM_SOFTWARE_PRETRIGGER_1 = 5U, /*!< SCM Software pre-trigger 1 */ + SCM_SOFTWARE_PRETRIGGER_2 = 6U, /*!< SCM Software pre-trigger 2 */ + SCM_SOFTWARE_PRETRIGGER_3 = 7U /*!< SCM Software pre-trigger 3 */ +} SCM_SoftwarePreTriggerType; + +/** + * @brief FTUx output source selection type + * + */ +typedef enum +{ + SCM_FTU_OUTPUT_STD = 0U, /*!< FTUx CHx output will direct route to corresponding pad(standard) */ + SCM_FTU_OUT_COMBINE /*!< FTUx pad output is equal to FTUx CHx output & FTUx CH1 output(combine) */ +} SCM_FTU_OutputSelType; + +/** + * @brief FTU2 CH1 input selection type + * + */ +typedef enum +{ + SCM_FTU_INPUT_STD = 0U, /*!< FTU2_CH1 input */ + SCM_FTU_INPUT_OR /*!< OR of FTU2_CH0,FTU2_CH1,and FTU1_CH1 */ +} SCM_FTU2_CH1_InputSelType; + +/** + * @brief FTUx CH0 input selection type + * + */ +typedef enum +{ + SCM_FTU_CH0_INPUT_STD = 0U, /*!< FTU2_CH0 input */ + SCM_FTU_CH0_INPUT_CMP0, /*!< CMP0 output */ + SCM_FTU_CH0_INPUT_CMP1 /*!< CMP1 output */ +} SCM_FTUx_CH0_InputSelType; + +/** + * @brief FTU Global Time Base Control type + * + */ +typedef enum +{ + SCM_FTU0_GTBC = 0x01U, /*!< FTU0 Global Time Base Control Select */ + SCM_FTU1_GTBC = 0x02U, /*!< FTU1 Global Time Base Control Select */ + SCM_FTU2_GTBC = 0x04U, /*!< FTU2 Global Time Base Control Select */ + SCM_FTU3_GTBC = 0x08U, /*!< FTU3 Global Time Base Control Select */ + SCM_FTU4_GTBC = 0x10U, /*!< FTU4 Global Time Base Control Select */ + SCM_FTU5_GTBC = 0x20U, /*!< FTU5 Global Time Base Control Select */ + SCM_FTU6_GTBC = 0x40U, /*!< FTU6 Global Time Base Control Select */ + SCM_FTU7_GTBC = 0x80U, /*!< FTU7 Global Time Base Control Select */ +} SCM_FTUGTBCtrlType; + +/** + * @brief FTU SYNC Control type + * + */ +typedef enum +{ + SCM_FTU0_SYNC = SCM_FTU_SYNC_FTU0SYNC_MASK, /*!< FTU0 Sync Control */ + SCM_FTU1_SYNC = SCM_FTU_SYNC_FTU1SYNC_MASK, /*!< FTU1 Sync Control */ + SCM_FTU2_SYNC = SCM_FTU_SYNC_FTU2SYNC_MASK, /*!< FTU2 Sync Control */ + SCM_FTU3_SYNC = SCM_FTU_SYNC_FTU3SYNC_MASK, /*!< FTU3 Sync Control */ + SCM_FTU4_SYNC = SCM_FTU_SYNC_FTU4SYNC_MASK, /*!< FTU4 Sync Control */ + SCM_FTU5_SYNC = SCM_FTU_SYNC_FTU5SYNC_MASK, /*!< FTU5 Sync Control */ + SCM_FTU6_SYNC = SCM_FTU_SYNC_FTU6SYNC_MASK, /*!< FTU6 Sync Control */ + SCM_FTU7_SYNC = SCM_FTU_SYNC_FTU7SYNC_MASK, /*!< FTU7 Sync Control */ +} SCM_FTUSyncCtrlType; + +/** + * @brief Trace clock selection + * + */ +typedef enum +{ + SCM_TRACE_CORE_CLK = 0U, /*!< Select platform fclk to trace clock */ + SCM_TRACE_PLL1DIVH_CLK = 1U /*!< Select SCG PLL1 platform clock to trace clock */ +} SCM_TraceClkSrcType; + +/** + * @brief Software trigger to TRGSEL0/TRGSEL1 + * + */ +typedef enum +{ + SCM_SW_TRIG_0 = 1U, /*!< Generate software trigger0 to (TRGSEL0 & TRGSEL4) */ + SCM_SW_TRIG_1 = 2U, /*!< Generate software trigger1 to (TRGSEL0 & TRGSEL4) */ + SCM_SW_TRIG_2 = 4U, /*!< Generate software trigger2 to (TRGSEL0 & TRGSEL4) */ + SCM_SW_TRIG_3 = 8U, /*!< Generate software trigger3 to (TRGSEL0 & TRGSEL4) */ + SCM_SW_TRIG_4 = 1U, /*!< Generate software trigger4 to (TRGSEL1 & TRGSEL5) */ + SCM_SW_TRIG_5 = 2U, /*!< Generate software trigger5 to (TRGSEL1 & TRGSEL5) */ + SCM_SW_TRIG_6 = 4U, /*!< Generate software trigger6 to (TRGSEL1 & TRGSEL5) */ + SCM_SW_TRIG_7 = 8U /*!< Generate software trigger7 to (TRGSEL1 & TRGSEL5) */ +} SCM_SwTrigxType; + +/** + * @brief Software trigger to TRGSEL0/TRGSEL1 + * + */ +typedef enum +{ + SCM_CCM0_STATUS_CPU_STOP_SYS_SLAVE = SCM_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_MASK, /*!< CCM0 FCG Stop Sys Slave Ack */ + SCM_CCM0_STATUS_CPU_STOP_MASTER = SCM_CCM0_STATUS_CPU0_STOP_MASTER_MASK, /*!< CCM0 FCG Stop Master Ack */ + SCM_CCM0_STATUS_CPU_STOP_SLOW_SLAVE = SCM_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_MASK,/*!< CCM0 FCG Stop Slow Slave Ack */ + SCM_CCM0_STATUS_CPU_STOP_BUS_SLAVE = SCM_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_MASK, /*!< CCM0 FCG Stop Bus Slave Ack */ + SCM_CCM0_STATUS_CPU_DEEPSLEEPING = SCM_CCM0_STATUS_CPU0_DEEPSLEEPING_MASK, /*!< CPU0 Sleepdeep */ + SCM_CCM0_STATUS_CPU_SLEEPING = SCM_CCM0_STATUS_CPU0_SLEEPING_MASK /*!< CPU0 Sleeping */ +} SCM_CCMxStatusType; + +/** + * @brief SDDF channel clock output selection + * + */ +typedef enum +{ + SCM_SDDF0_RESERVE = 0U, /*!< Reserved */ + SCM_SDDF0_CLKO0, /*!< SDDF0 CLKO0 */ + SCM_SDDF0_CLKO1, /*!< SDDF0 CLKO1 */ + SCM_SDDF0_CLKO2 /*!< SDDF0 CLKO2 */ +} SCM_SDDF_ClkOutSelType; + +/** + * @brief SDDF channel clock input selection + * + */ +typedef enum +{ + SCM_SDDF0_CLK0_IND = 0U, /*!< SDDF0 CLK0_IND */ + SCM_SDDF0_CLK1_IND, /*!< SDDF0 CLK1_IND */ + SCM_SDDF0_CLK2_IND, /*!< SDDF0 CLK2_IND */ + SCM_SDDF0_CLK3_IND /*!< SDDF0 CLK3_IND */ +} SCM_SDDF_ClkInSelType; + +/** + * @brief FLEXCAN routing selection + * + */ +typedef enum +{ + SCM_FLEXCAN_9_9_OR_8_8 = 0U, /*!< FLEXCAN 9 Rx/Tx pad from/to FLEXCAN 9 Rx/Tx pad or + FLEXCAN 8 Rx/Tx pad from/to FLEXCAN 8 Rx/Tx pad */ + SCM_FLEXCAN_9_1_OR_8_0, /*!< FLEXCAN 9 Rx/Tx pad from/to FLEXCAN 1 Rx/Tx pad or + FLEXCAN 8 Rx/Tx pad from/to FLEXCAN 0 Rx/Tx pad */ + SCM_FLEXCAN_9_3_OR_8_2, /*!< FLEXCAN 9 Rx/Tx pad from/to FLEXCAN 3 Rx/Tx pad or + FLEXCAN 8 Rx/Tx pad from/to FLEXCAN 2 Rx/Tx pad */ + SCM_FLEXCAN_9_5_OR_8_4 /*!< FLEXCAN 9 Rx/Tx pad from/to FLEXCAN 5 Rx/Tx pad or + FLEXCAN 8 Rx/Tx pad from/to FLEXCAN 4 Rx/Tx pad */ +} SCM_FlexCanRouterType; + +/** + * @brief MSC routing selection + * + */ +typedef enum +{ + SCM_MSC_FTU0_TO_MSC = 0U, /*!< Select FTU0 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU1_TO_MSC, /*!< Select FTU1 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU2_TO_MSC, /*!< Select FTU2 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU3_TO_MSC, /*!< Select FTU3 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU4_TO_MSC, /*!< Select FTU4 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU5_TO_MSC, /*!< Select FTU5 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU6_TO_MSC, /*!< Select FTU6 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU7_TO_MSC /*!< Select FTU7 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ +} SCM_MSCAltInSelType; + +/** + * @brief ISM routing selection + * + */ +typedef enum +{ + SCM_ISM_FTU0_TO_TRGSEL3 = 0U, /*!< Select FTU0 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU1_TO_TRGSEL3, /*!< Select FTU1 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU2_TO_TRGSEL3, /*!< Select FTU2 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU3_TO_TRGSEL3, /*!< Select FTU3 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU4_TO_TRGSEL3, /*!< Select FTU4 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU5_TO_TRGSEL3, /*!< Select FTU5 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU6_TO_TRGSEL3, /*!< Select FTU6 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU7_TO_TRGSEL3 /*!< Select FTU7 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ +} SCM_ISMRouterType; + +/** + * @brief Matrix status register 0 type + * + */ +typedef enum +{ + SCM_MATRIX_STATUS0_MAM0_S5_M = SCM_MATRIX_STATUS0_MAM0_S5_M_MASK, /*!< MAM0_S5 slave ECC multi bit data error */ + SCM_MATRIX_STATUS0_MAM0_S5_AT = SCM_MATRIX_STATUS0_MAM0_S5_AT_MASK, /*!< MAM0_S5 slave ECC attribute error */ + SCM_MATRIX_STATUS0_MAM0_S5_D = SCM_MATRIX_STATUS0_MAM0_S5_D_MASK, /*!< MAM0_S5 slave ECC single bit data error */ + SCM_MATRIX_STATUS0_MAM0_S5_A = SCM_MATRIX_STATUS0_MAM0_S5_A_MASK, /*!< MAM0_S5 slave ECC address error */ + SCM_MATRIX_STATUS0_MAM0_S4_M = SCM_MATRIX_STATUS0_MAM0_S4_M_MASK, /*!< MAM0_S4 slave ECC multi bit data error */ + SCM_MATRIX_STATUS0_MAM0_S4_AT = SCM_MATRIX_STATUS0_MAM0_S4_AT_MASK, /*!< MAM0_S4 slave ECC attribute error */ + SCM_MATRIX_STATUS0_MAM0_S4_D = SCM_MATRIX_STATUS0_MAM0_S4_D_MASK, /*!< MAM0_S4 slave ECC single bit data error */ + SCM_MATRIX_STATUS0_MAM0_S4_A = SCM_MATRIX_STATUS0_MAM0_S4_A_MASK, /*!< MAM0_S4 slave ECC address error */ + SCM_MATRIX_STATUS0_MAM0_S3_M = SCM_MATRIX_STATUS0_MAM0_S3_M_MASK, /*!< MAM0_S3 slave ECC multi bit data error */ + SCM_MATRIX_STATUS0_MAM0_S3_AT = SCM_MATRIX_STATUS0_MAM0_S3_AT_MASK, /*!< MAM0_S3 slave ECC attribute error */ + SCM_MATRIX_STATUS0_MAM0_S3_D = SCM_MATRIX_STATUS0_MAM0_S3_D_MASK, /*!< MAM0_S3 slave ECC single bit data error*/ + SCM_MATRIX_STATUS0_MAM0_S3_A = SCM_MATRIX_STATUS0_MAM0_S3_A_MASK, /*!< MAM0_S3 slave ECC address error */ + SCM_MATRIX_STATUS0_MAM0_S2_M = SCM_MATRIX_STATUS0_MAM0_S2_M_MASK, /*!< MAM0_S2 slave ECC multi bit data error*/ + SCM_MATRIX_STATUS0_MAM0_S2_AT = SCM_MATRIX_STATUS0_MAM0_S2_AT_MASK, /*!< MAM0_S2 slave ECC attribute error */ + SCM_MATRIX_STATUS0_MAM0_S2_D = SCM_MATRIX_STATUS0_MAM0_S2_D_MASK, /*!< MAM0_S2 slave ECC single bit data error*/ + SCM_MATRIX_STATUS0_MAM0_S2_A = SCM_MATRIX_STATUS0_MAM0_S2_A_MASK, /*!< MAM0_S2 slave ECC address error */ + SCM_MATRIX_STATUS0_MAM0_S1_M = SCM_MATRIX_STATUS0_MAM0_S1_M_MASK, /*!< MAM0_S1 slave ECC multi bit data error */ + SCM_MATRIX_STATUS0_MAM0_S1_AT = SCM_MATRIX_STATUS0_MAM0_S1_AT_MASK, /*!< MAM0_S1 slave ECC attribute error */ + SCM_MATRIX_STATUS0_MAM0_S1_D = SCM_MATRIX_STATUS0_MAM0_S1_D_MASK, /*!< MAM0_S1 slave ECC single bit data error */ + SCM_MATRIX_STATUS0_MAM0_S1_A = SCM_MATRIX_STATUS0_MAM0_S1_A_MASK, /*!< MAM0_S1 slave ECC address error */ + SCM_MATRIX_STATUS0_ROM_M = SCM_MATRIX_STATUS0_ROM_M_MASK, /*!< ROM array ECC multi bit data error */ + SCM_MATRIX_STATUS0_ROM_D = SCM_MATRIX_STATUS0_ROM_D_MASK, /*!< ROM array ECC single bit data error */ + SCM_MATRIX_STATUS0_ROM_A = SCM_MATRIX_STATUS0_ROM_A_MASK /*!< ROM array ECC address error */ +} SCM_MatrixStatus0Type; + +/** + * @brief Matrix status register 1 type + * + */ +typedef enum +{ + SCM_MATRIX_STATUS1_DMA0_M = SCM_MATRIX_STATUS1_DMA0_M_MASK, /*!< DMA0 master ECC multi bit data error */ + SCM_MATRIX_STATUS1_DMA0_D = SCM_MATRIX_STATUS1_DMA0_D_MASK, /*!< DMA0 master ECC single bit data error */ + SCM_MATRIX_STATUS1_DMA0_A = SCM_MATRIX_STATUS1_DMA0_A_MASK, /*!< DMA0 master ECC address error */ + SCM_MATRIX_STATUS1_HSM_M = SCM_MATRIX_STATUS1_HSM_M_MASK, /*!< HSM master ECC multi bit data error */ + SCM_MATRIX_STATUS1_HSM_D = SCM_MATRIX_STATUS1_HSM_D_MASK, /*!< HSM master ECC single bit data error */ + SCM_MATRIX_STATUS1_HSM_A = SCM_MATRIX_STATUS1_HSM_A_MASK, /*!< HSM master ECC address error */ + SCM_MATRIX_STATUS1_MAM0_S5_DS_M = SCM_MATRIX_STATUS1_MAM0_S5_DS_M_MASK, /*!< MAM0_S5 downsize ECC multi bit data error */ + SCM_MATRIX_STATUS1_MAM0_S5_DS_D = SCM_MATRIX_STATUS1_MAM0_S5_DS_D_MASK, /*!< MAM0_S5 downsize ECC single bit data error */ + SCM_MATRIX_STATUS1_MAM0_S5_DS_A = SCM_MATRIX_STATUS1_MAM0_S5_DS_A_MASK, /*!< MAM0_S5 downsize ECC address error */ + SCM_MATRIX_STATUS1_MAM0_S8_M = SCM_MATRIX_STATUS1_MAM0_S8_M_MASK, /*!< MAM0_S8 slave ECC multi bit data error */ + SCM_MATRIX_STATUS1_MAM0_S8_AT = SCM_MATRIX_STATUS1_MAM0_S8_AT_MASK, /*!< MAM0_S8 slave ECC attribute error */ + SCM_MATRIX_STATUS1_MAM0_S8_D = SCM_MATRIX_STATUS1_MAM0_S8_D_MASK, /*!< MAM0_S8 slave ECC single bit data error */ + SCM_MATRIX_STATUS1_MAM0_S8_A = SCM_MATRIX_STATUS1_MAM0_S8_A_MASK, /*!< MAM0_S8 slave ECC address error */ + SCM_MATRIX_STATUS1_MAM0_S7_M = SCM_MATRIX_STATUS1_MAM0_S7_M_MASK, /*!< MAM0_S7 slave ECC multi bit data error */ + SCM_MATRIX_STATUS1_MAM0_S7_AT = SCM_MATRIX_STATUS1_MAM0_S7_AT_MASK, /*!< MAM0_S7 slave ECC attribute error */ + SCM_MATRIX_STATUS1_MAM0_S7_D = SCM_MATRIX_STATUS1_MAM0_S7_D_MASK, /*!< MAM0_S7 slave ECC single bit data error */ + SCM_MATRIX_STATUS1_MAM0_S7_A = SCM_MATRIX_STATUS1_MAM0_S7_A_MASK, /*!< MAM0_S7 slave ECC address error */ + SCM_MATRIX_STATUS1_MAM0_S6_M = SCM_MATRIX_STATUS1_MAM0_S6_M_MASK, /*!< MAM0_S6 slave ECC multi bit data error */ + SCM_MATRIX_STATUS1_MAM0_S6_AT = SCM_MATRIX_STATUS1_MAM0_S6_AT_MASK, /*!< MAM0_S6 slave ECC attribute error */ + SCM_MATRIX_STATUS1_MAM0_S6_D = SCM_MATRIX_STATUS1_MAM0_S6_D_MASK, /*!< MAM0_S6 slave ECC single bit data error*/ + SCM_MATRIX_STATUS1_MAM0_S6_A = SCM_MATRIX_STATUS1_MAM0_S6_A_MASK, /*!< MAM0_S6 slave ECC address error */ +} SCM_MatrixStatus1Type; + +/** + * @brief Matrix status register 2 type + * + */ +typedef enum +{ + SCM_MATRIX_STATUS2_C0_OVERLAY = SCM_MATRIX_STATUS2_C0_OVERLAY_MASK, /*!< CPU0 AHB Overlay error */ + SCM_MATRIX_STATUS2_C0_LOCKSTEP = SCM_MATRIX_STATUS2_C0_LOCKSTEP_MASK, /*!< CPU0 Lockstep error */ + SCM_MATRIX_STATUS2_C0_DTCM1_A = SCM_MATRIX_STATUS2_C0_DTCM1_A_MASK, /*!< CPU0 DTCM1 ECC Address error */ + SCM_MATRIX_STATUS2_C0_DTCM1_M = SCM_MATRIX_STATUS2_C0_DTCM1_M_MASK, /*!< CPU0 DTCM1 ECC Multi Bit Data error */ + SCM_MATRIX_STATUS2_C0_DTCM1_S = SCM_MATRIX_STATUS2_C0_DTCM1_S_MASK, /*!< CPU0 DTCM1 ECC Single Bit Data error */ + SCM_MATRIX_STATUS2_C0_DTCM0_A = SCM_MATRIX_STATUS2_C0_DTCM0_A_MASK, /*!< CPU0 DTCM0 ECC Address error */ + SCM_MATRIX_STATUS2_C0_DTCM0_M = SCM_MATRIX_STATUS2_C0_DTCM0_M_MASK, /*!< CPU0 DTCM0 ECC Multi Bit Data error */ + SCM_MATRIX_STATUS2_C0_DTCM0_S = SCM_MATRIX_STATUS2_C0_DTCM0_S_MASK, /*!< CPU0 DTCM0 ECC Single Bit Data error */ + SCM_MATRIX_STATUS2_C0_ITCM_A = SCM_MATRIX_STATUS2_C0_ITCM_A_MASK, /*!< CPU0 ITCM ECC Address error */ + SCM_MATRIX_STATUS2_C0_ITCM_M = SCM_MATRIX_STATUS2_C0_ITCM_M_MASK, /*!< CPU0 ITCM ECC Multi Bit Data error */ + SCM_MATRIX_STATUS2_C0_ITCM_S = SCM_MATRIX_STATUS2_C0_ITCM_S_MASK, /*!< CPU0 ITCM ECC Single Bit Data error */ + SCM_MATRIX_STATUS2_C0_DCACHE = SCM_MATRIX_STATUS2_C0_DCACHE_MASK, /*!< CPU0 DCache Array error */ + SCM_MATRIX_STATUS2_C0_ICACHE = SCM_MATRIX_STATUS2_C0_ICACHE_MASK, /*!< CPU0 ICache Array error */ + SCM_MATRIX_STATUS2_C0_DTCM1_DEC = SCM_MATRIX_STATUS2_C0_DTCM1_DEC_MASK, /*!< CPU0 DTCM1 decode monitor error */ + SCM_MATRIX_STATUS2_C0_DTCM0_DEC = SCM_MATRIX_STATUS2_C0_DTCM0_DEC_MASK, /*!< CPU0 DTCM0 decode monitor error */ + SCM_MATRIX_STATUS2_C0_ITCM_DEC = SCM_MATRIX_STATUS2_C0_ITCM_DEC_MASK, /*!< CPU0 ITCM decode monitor error */ + SCM_MATRIX_STATUS2_C0_AHBP_F2S = SCM_MATRIX_STATUS2_C0_AHBP_F2S_MASK, /*!< CPU0 AHBP fast to slow monitor error */ + SCM_MATRIX_STATUS2_C0_AHBM_M = SCM_MATRIX_STATUS2_C0_AHBM_M_MASK, /*!< CPU0 AHBM master ECC multi bit data error */ + SCM_MATRIX_STATUS2_C0_AHBM_D = SCM_MATRIX_STATUS2_C0_AHBM_D_MASK, /*!< CPU0 AHBM master ECC single bit data error */ + SCM_MATRIX_STATUS2_C0_AHBM_A = SCM_MATRIX_STATUS2_C0_AHBM_A_MASK, /*!< CPU0 AHBM master ECC address error */ + SCM_MATRIX_STATUS2_C0_AHBS_M = SCM_MATRIX_STATUS2_C0_AHBS_M_MASK, /*!< CPU0 AHBS master ECC multi bit data error */ + SCM_MATRIX_STATUS2_C0_AHBS_D = SCM_MATRIX_STATUS2_C0_AHBS_D_MASK, /*!< CPU0 AHBS master ECC single bit data error */ + SCM_MATRIX_STATUS2_C0_AHBS_A = SCM_MATRIX_STATUS2_C0_AHBS_A_MASK, /*!< CPU0 AHBS master ECC address error */ + SCM_MATRIX_STATUS2_C0_AHBP_M = SCM_MATRIX_STATUS2_C0_AHBP_M_MASK, /*!< CPU0 AHBP master ECC multi bit data error */ + SCM_MATRIX_STATUS2_C0_AHBP_D = SCM_MATRIX_STATUS2_C0_AHBP_D_MASK, /*!< CPU0 AHBP master ECC single bit data error */ + SCM_MATRIX_STATUS2_C0_AHBP_A = SCM_MATRIX_STATUS2_C0_AHBP_A_MASK, /*!< CPU0 AHBP master ECC address error */ +} SCM_MatrixStatus2Type; + +/** + * @brief Matrix status register 5 type + * + */ +typedef enum +{ + + SCM_MATRIX_STATUS5_DMA0_CFG_M = SCM_MATRIX_STATUS5_DMA0_CFG_M_MASK, /*!< DMA0_CFG ECC Multi Bit Data Error */ + SCM_MATRIX_STATUS5_DMA0_LOCKSTEP = SCM_MATRIX_STATUS5_DMA0_LOCKSTEP_MASK,/*!< DMA0 Lockstep Error */ + SCM_MATRIX_STATUS5_DMA0_CFG_S = SCM_MATRIX_STATUS5_DMA0_CFG_S_MASK, /*!< DMA0_CFG ECC Single Bit Data Error */ + SCM_MATRIX_STATUS5_DMA0_CFG_A = SCM_MATRIX_STATUS5_DMA0_CFG_A_MASK, /*!< DMA0_CFG ECC Address Error */ + SCM_MATRIX_STATUS5_EDC_HI = SCM_MATRIX_STATUS5_EDC_HI_MASK, /*!< Flash Control OCM EDC FCCU Alarm High Error */ + SCM_MATRIX_STATUS5_LINE_SBC = SCM_MATRIX_STATUS5_LINE_SBC_MASK, /*!< FCCU Alarm Linebuffer Self ECC Single Bit Error */ + SCM_MATRIX_STATUS5_LINE_MULTI = SCM_MATRIX_STATUS5_LINE_MULTI_MASK, /*!< FCCU Alarm Linebuffer Self ECC Multi Bit Error */ + SCM_MATRIX_STATUS5_ENC = SCM_MATRIX_STATUS5_ENC_MASK, /*!< FLASH Control OCM ENC FCCU Alarm Error */ + SCM_MATRIX_STATUS5_EDC = SCM_MATRIX_STATUS5_EDC_MASK, /*!< Flash Control OCM EDC FCCU Alarm Error */ + SCM_MATRIX_STATUS5_P2_D_M = SCM_MATRIX_STATUS5_P2_D_M_MASK, /*!< Flash Control Port 2 Data Multi Error */ + SCM_MATRIX_STATUS5_P1_D_M = SCM_MATRIX_STATUS5_P1_D_M_MASK, /*!< Flash Control Port 1 Data Multi Error */ + SCM_MATRIX_STATUS5_P0_D_M = SCM_MATRIX_STATUS5_P0_D_M_MASK, /*!< Flash Control Port 0 Data Multi Error */ + SCM_MATRIX_STATUS5_P2_C_M = SCM_MATRIX_STATUS5_P2_C_M_MASK, /*!< Flash Control Port 2 Code Multi Error */ + SCM_MATRIX_STATUS5_P1_C_M = SCM_MATRIX_STATUS5_P1_C_M_MASK, /*!< Flash Control Port 1 Code Multi Error */ + SCM_MATRIX_STATUS5_P0_C_M = SCM_MATRIX_STATUS5_P0_C_M_MASK, /*!< Flash Control Port 0 Code Multi Error */ + SCM_MATRIX_STATUS5_P2_D_S = SCM_MATRIX_STATUS5_P2_D_S_MASK, /*!< Flash Control Port 2 Data Single Error */ + SCM_MATRIX_STATUS5_P1_D_S = SCM_MATRIX_STATUS5_P1_D_S_MASK, /*!< Flash Control Port 1 Data Single Error */ + SCM_MATRIX_STATUS5_P0_D_S = SCM_MATRIX_STATUS5_P0_D_S_MASK, /*!< Flash Control Port 0 Data Single Error */ + SCM_MATRIX_STATUS5_P2_C_S = SCM_MATRIX_STATUS5_P2_C_S_MASK, /*!< Flash Control Port 2 Code Single Error */ + SCM_MATRIX_STATUS5_P1_C_S = SCM_MATRIX_STATUS5_P1_C_S_MASK, /*!< Flash Control Port 1 Code Single Error */ + SCM_MATRIX_STATUS5_P0_C_S = SCM_MATRIX_STATUS5_P0_C_S_MASK /*!< Flash Control Port 0 Code Single Error */ +} SCM_MatrixStatus5Type; + +/** + * @brief Matrix status register 6 type + * + */ +typedef enum +{ + SCM_MATRIX_STATUS6_STALL_ERR = SCM_MATRIX_STATUS6_STALL_ERR_MASK, /*!< MAM Stall Error */ + SCM_MATRIX_STATUS6_MAM0_S8_DS = SCM_MATRIX_STATUS6_MAM0_S8_DS_MASK, /*!< MAM0_S8 Downsize Monitor Error */ + SCM_MATRIX_STATUS6_MAM0_S5_DS = SCM_MATRIX_STATUS6_MAM0_S5_DS_MASK, /*!< MAM0_S5 Downsize Monitor Error */ + SCM_MATRIX_STATUS6_MAM0_S5_S2F = SCM_MATRIX_STATUS6_MAM0_S5_S2F_MASK, /*!< MAM0_S5 Slow to Fast Gasket Monitor Error */ + SCM_MATRIX_STATUS6_SRAM1_DEC = SCM_MATRIX_STATUS6_SRAM1_DEC_MASK, /*!< SARM1 Decode Monitor Error */ + SCM_MATRIX_STATUS6_SRAM0_DEC = SCM_MATRIX_STATUS6_SRAM0_DEC_MASK, /*!< SARM0 Decode Monitor Error */ + SCM_MATRIX_STATUS6_AFCB1_MON = SCM_MATRIX_STATUS6_AFCB1_MON_MASK, /*!< AFCB0 Monitor Error */ + SCM_MATRIX_STATUS6_AFCB0_MON = SCM_MATRIX_STATUS6_AFCB0_MON_MASK, /*!< AFCB1 Monitor Error */ + SCM_MATRIX_STATUS6_STCU_ST = SCM_MATRIX_STATUS6_STCU_ST_MASK, /*!< STCU Self Test Monitor Error */ + SCM_MATRIX_STATUS6_DCM_SCAN = SCM_MATRIX_STATUS6_DCM_SCAN_MASK, /*!< FCM Scan ECC Error */ + SCM_MATRIX_STATUS6_NON_USER = SCM_MATRIX_STATUS6_NON_USER_MASK, /*!< STCU Nonuser Error */ + SCM_MATRIX_STATUS6_SCM_CRC = SCM_MATRIX_STATUS6_SCM_CRC_MASK, /*!< SCM CRC Error */ + SCM_MATRIX_STATUS6_SCG_CRC = SCM_MATRIX_STATUS6_SCG_CRC_MASK, /*!< SCG CRC Error */ + SCM_MATRIX_STATUS6_SRAM1_CTRL_MON = SCM_MATRIX_STATUS6_SRAM1_CTRL_MON_MASK, /*!< SRAM1 Control Monitor Error */ + SCM_MATRIX_STATUS6_SRAM0_CTRL_MON = SCM_MATRIX_STATUS6_SRAM0_CTRL_MON_MASK, /*!< SRAM0 Control Monitor Error */ + SCM_MATRIX_STATUS6_SRAM1_M = SCM_MATRIX_STATUS6_SRAM1_M_MASK, /*!< SRAM1 Multi Bit Data Error */ + SCM_MATRIX_STATUS6_SRAM1_EDC = SCM_MATRIX_STATUS6_SRAM1_EDC_MASK, /*!< SRAM1 EDC Error */ + SCM_MATRIX_STATUS6_SRAM1_A = SCM_MATRIX_STATUS6_SRAM1_A_MASK, /*!< SRAM1 Address Error */ + SCM_MATRIX_STATUS6_SRAM1_S = SCM_MATRIX_STATUS6_SRAM1_S_MASK, /*!< SRAM1 Single Bit Data Error */ + SCM_MATRIX_STATUS6_SAM0_M = SCM_MATRIX_STATUS6_SAM0_M_MASK, /*!< SRAM0 Multi Bit Data Error */ + SCM_MATRIX_STATUS6_SRAM0_EDC = SCM_MATRIX_STATUS6_SRAM0_EDC_MASK, /*!< SRAM0 EDC Error */ + SCM_MATRIX_STATUS6_SRAM0_A = SCM_MATRIX_STATUS6_SRAM0_A_MASK, /*!< SRAM0 Address Error */ + SCM_MATRIX_STATUS6_SRAM0_S = SCM_MATRIX_STATUS6_SRAM0_S_MASK /*!< SRAM0 Single Bit Data Error */ +} SCM_MatrixStatus6Type; + +/** + * @brief Matrix status register 7 type + * + */ +typedef enum +{ + SCM_MATRIX_STATUS7_HSM_IRAM_M = SCM_MATRIX_STATUS7_HSM_IRAM_M_MASK, /*!< HSM IRAM Multi Bit Data Error */ + SCM_MATRIX_STATUS7_HSM_IRAM_S = SCM_MATRIX_STATUS7_HSM_IRAM_S_MASK, /*!< HSM IRAM Single Bit Data Error */ + SCM_MATRIX_STATUS7_HSM_DRAM_M = SCM_MATRIX_STATUS7_HSM_DRAM_M_MASK, /*!< HSM DRAM Multi Bit Data Error*/ + SCM_MATRIX_STATUS7_HSM_DRAM_S = SCM_MATRIX_STATUS7_HSM_DRAM_S_MASK, /*!< HSM DRAM Single Bit Data Error */ + SCM_MATRIX_STATUS7_HSM_WDOG = SCM_MATRIX_STATUS7_HSM_WDOG_MASK, /*!< HSM WDOG Request */ + SCM_MATRIX_STATUS7_MAM0_ERR = SCM_MATRIX_STATUS7_MAM0_ERR_MASK, /*!< MAM0 Timeout Error*/ + SCM_MATRIX_STATUS7_FOSC_ERR = SCM_MATRIX_STATUS7_FOSC_ERR_MASK, /*!< FOSC Loss of Clock Error*/ + SCM_MATRIX_STATUS7_PLL1_ERR = SCM_MATRIX_STATUS7_PLL1_ERR_MASK, /*!< PLL1 Loss of Clock Error*/ + SCM_MATRIX_STATUS7_PLL0_ERR = SCM_MATRIX_STATUS7_PLL0_ERR_MASK /*!< PLL0 Loss of Clock Error */ +} SCM_MatrixStatus7Type; + +/** + * @brief Matrix ID status type + * + */ +typedef enum +{ + SCM_MATRIX_ID_STATUS0_MAM0_S3_ID = 0U, /*!< MAM0_S3 Slave ECC Error with Which Master Access */ + SCM_MATRIX_ID_STATUS0_MAM0_S4_ID = 1U, /*!< MAM0_S4 Slave ECC Error with Which Master Access */ + SCM_MATRIX_ID_STATUS0_MAM0_S5_ID = 3U, /*!< MAM0_S5 Slave ECC Error with Which Master Access */ + SCM_MATRIX_ID_STATUS0_SRAM0_ID = 4U, /*!< SARM0 ECC error with which master access */ + SCM_MATRIX_ID_STATUS0_SRAM1_ID = 5U /*!< SARM1 ECC Error with Which Master Access */ +} SCM_MatrixIDStatusType; + +/** + * @brief Matrix ID status master type + * + */ +typedef enum +{ + SCM_MATRIX_ID_STATUS0_MASTER_CPU0 = 0x0U, /*!< SARM2 ECC error with CPU0 access */ + SCM_MATRIX_ID_STATUS0_MASTER_HSM = 0x8U, /*!< SARM1 ECC error with HSM access */ + SCM_MATRIX_ID_STATUS0_MASTER_DMA0 = 0xAU, /*!< SARM0 ECC error with DMA0 access */ +} SCM_MatrixIDStatusMasterType; + +/** + * @brief SCM SYSAP control Status2 Register Selection typ + * + */ +typedef enum +{ + SCM_SYSAP_STATUS2_SEL_UID0 = 0U, /*!< Select UID0 */ + SCM_SYSAP_STATUS2_SEL_UID1 = 1U, /*!< Select UID1 */ + SCM_SYSAP_STATUS2_SEL_UID2 = 2U, /*!< Select UID2 */ + SCM_SYSAP_STATUS2_SEL_UID3 = 3U, /*!< Select UID3 */ + SCM_SYSAP_STATUS2_SEL_NVRVERSION = 4U /*!< Select NVR version */ +} SCM_SysAPStatus2SelType; + +/** + * @brief Mass erase type + * + */ +typedef enum +{ + SCM_SECTORERASE_AS_MASSERASE = 0U, /*!< Use sector erase for mass erase */ + SCM_CHIPERASE_AS_MASSERASE /*!< Use chip erase for mass erase */ +} SCM_SysApMassEraseType; + +/** + * @brief Cpu Type of forcing to halt + * + */ +typedef enum +{ + SCM_DEBUG_CPU0 = 1U, /*!< Force CPU0 to halt */ +} SCM_SysApCpuDebugReqType; + +/** + * @brief Subsystem status type + * + */ +typedef enum +{ + SCM_SUBSYS_STATUS_CHIP_IS_FT = SCM_SUBSYS_STATUS_CHIP_IS_FT_MASK, /*!< SEC dc lifecycle ft */ + SCM_SUBSYS_STATUS_CHIP_IS_VIRGIN = SCM_SUBSYS_STATUS_CHIP_IS_VIRGIN_MASK, /*!< SEC dc lifecycle virgin */ + SCM_SUBSYS_STATUS_TPU_CLK_EN = SCM_SUBSYS_STATUS_TPU_CLK_EN_MASK, /*!< TPU Clock Enable */ + SCM_SUBSYS_STATUS_HSM_RST = SCM_SUBSYS_STATUS_HSM_RST_MASK, /*!< Subsystem reset state */ + SCM_SUBSYS_STATUS_HSM_SYS_ERR_INT = SCM_SUBSYS_STATUS_HSM_SYS_ERR_INT_MASK, /*!< Subsystem error interrupt */ + SCM_SUBSYS_STATUS_WDG_RST = SCM_SUBSYS_STATUS_WDG_RST_MASK, /*!< Subsystem WDG generated reset flag */ + SCM_SUBSYS_STATUS_INIT_DONE = SCM_SUBSYS_STATUS_INIT_DONE_MASK, /*!< Subsystem Initial done flag */ + SCM_SUBSYS_STATUS_ISP_TOGGLE = SCM_SUBSYS_STATUS_ISP_TOGGLE_MASK, /*!< Subsystem ISP PIN toggle flag */ + SCM_SUBSYS_STATUS_SUBSYS_SLEEP = SCM_SUBSYS_STATUS_HSM_SLEEP_MASK, /*!< Subsystem sleep state */ + SCM_SUBSYS_STATUS_STOP_ACK = SCM_SUBSYS_STATUS_STOP_ACK_MASK /*!< Subsystem stop mode ack */ +} SCM_SUBSYSStatusType; + +/** + * @brief Master halt request type + * + */ +typedef enum +{ + SCM_MASTER_HALT_REQ_HSM_REQ = 0U, /*!< HSM Halt Request */ + SCM_MASTER_HALT_REQ_DMA0_REQ = 2U, /*!< DMA0 Halt Request */ +} SCM_HaltReqType; + +/** + * @brief Master halt request type + * + */ +typedef enum +{ + SCM_MASTER_HALT_REQ_NOT_HALTED = 0U, /*!< Not Halted state */ + SCM_MASTER_HALT_REQ_HALTED_STATE = 1U, /*!< Halted state */ +} SCM_HaltReqAckType; + + +/********* Local inline function ************/ +/** + * @brief Get UIDL data(Unique identification for the chip. Loaded from NVR) + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDL(void) +{ + return SCM->UIDL; +} + +/** + * @brief Get UIDML data(Unique identification for the chip. Loaded from NVR) + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDML(void) +{ + return SCM->UIDML; +} + +/** + * @brief Get UIDMH data(Unique identification for the chip. Loaded from NVR) + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDMH(void) +{ + return SCM->UIDMH; +} + +/** + * @brief Get UIDH data(Unique identification for the chip. Loaded from NVR) + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDH(void) +{ + return SCM->UIDH; +} + +/** + * @brief Get Family Identification + * + * @return return value + */ +LOCAL_INLINE uint8_t SCM_HWA_GetData_FamilyID(void) +{ + return (uint8_t)((SCM->PARTID0 & (uint32_t)SCM_PARTID0_FAM_ID_MASK) >> (uint32_t)SCM_PARTID0_FAM_ID_SHIFT); +} + +/** + * @brief Get Revision Identification + * + * @return return value + */ +LOCAL_INLINE uint8_t SCM_HWA_GetData_RevID(void) +{ + return (uint8_t)((SCM->PARTID0 & (uint32_t)SCM_PARTID0_REVID_MASK)); +} + +/** + * @brief Get CHIPCFG0 register status + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_CHIPCFG0(void) +{ + return SCM->CHIPCFG0; +} + +/** + * @brief Get CPU lock step enable/disable status + * + * @return 1: CPU lock step is enabled + * 0: CPU lock step is disabled + */ +LOCAL_INLINE uint32_t SCM_HWA_GetLockStepStatus_Cpu0(void) +{ + return ((SCM->CHIPCFG0 & (uint32_t)SCM_CHIPCFG0_CPU0_LOCKSTEP_EN_MASK)>>(uint32_t)SCM_CHIPCFG0_CPU0_LOCKSTEP_EN_SHIFT); +} + +/** + * @brief Get CANFD enable/disable status + * + * @return 1: CANFD is enabled + * 0: CANFD is disabled + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_CANFD(void) +{ + return ((SCM->CHIPCFG0 & (uint32_t)SCM_CHIPCFG0_CAN_FD_MASK)>>(uint32_t)SCM_CHIPCFG0_CAN_FD_SHIFT); +} + +/** + * @brief Get device ID + * + * @return The device ID + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_DeviceID(void) +{ + return ((SCM->CHIPCFG1 & (uint32_t)SCM_CHIPCFG1_DEVICE_ID_MASK) >> (uint32_t)SCM_CHIPCFG1_DEVICE_ID_SHIFT); +} + +/** + * @brief Lock the CPU permission(WPB) in MAMECCEN0 register, and WPB cannot be written until a power-on reset + * + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN0_LockWritePermit(void) +{ + SCM->MAMECCEN0 |= (uint32_t)SCM_MAMECCEN0_WPB_LOCK_MASK; +} + +/** + * @brief Get the lock status of CPU permission(WPB) in MAMECCEN0 register + * + * @return 1: The WPB of MAMECCEN0 register is locked + * 0: The WPB of MAMECCEN0 register is not locked + */ +LOCAL_INLINE uint32_t SCM_HWA_MAMECCEN0_GetWPBLockStatus(void) +{ + return (SCM->MAMECCEN0 & (uint32_t)SCM_MAMECCEN0_WPB_LOCK_MASK) >> SCM_MAMECCEN0_WPB_LOCK_SHIFT; +} + +/** + * @brief Get the CPU type of writing permission to MAMECCEN0 register + * + * @return SCM_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE SCM_WPB_CpuType SCM_HWA_MAMECCEN0_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((SCM->MAMECCEN0 & (uint32_t)SCM_MAMECCEN0_WPB_MASK) >> SCM_MAMECCEN0_WPB_SHIFT); + return (SCM_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set CPU to control the MAMECCEN0 register + * + * @param eCpuType CPU allowed to control peripheral + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN0_SetCpuWritePermit(SCM_WPB_CpuType eCpuType) +{ + SCM->MAMECCEN0 = ((SCM->MAMECCEN0 & (~(uint32_t)SCM_MAMECCEN0_WPB_MASK)) | SCM_MAMECCEN0_WPB(eCpuType)); +} + +/** + * @brief Get the value of MAMECCEN0 register + * @return register value + */ +LOCAL_INLINE uint32_t SCM_HWA_MAMECCEN0_GetValue(void) +{ + return SCM->MAMECCEN0; +} + +/** + * @brief Set the value of MAMECCEN0 register + * @param u32Value value to be set, the value must be the or value of SCM_MAMEccCtrlGrp0Type + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN0_SetValue(uint32_t u32Value) +{ + SCM->MAMECCEN0 = u32Value & 0x03FFCFCFu; +} + +/** + * @brief Set the MAMECCEN0 ECC enable + * @param eMamEccType the MAM peripheral to enable ECC + * @param eEnable the ECC enable mode + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN0_Ctrl(SCM_MAMEccCtrlGrp0Type eMamEccType, SCM_EccEnModeType eEnable) +{ + + SCM->MAMECCEN0 = (SCM->MAMECCEN0 & (~(SCM_MAMECCEN0_ECC_MASK << ((uint32_t)eMamEccType * SCM_MAMECCEN0_ECC_WIDTH)))) | + SCM_MAMECCEN0_ECC(eEnable) << ((uint32_t)eMamEccType * SCM_MAMECCEN0_ECC_WIDTH); +} + +/** + * @brief Lock the CPU permission(WPB) in MAMECCEN1 register, and WPB cannot be written until a power-on reset + * + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN1_LockWritePermit(void) +{ + SCM->MAMECCEN1 |= (uint32_t)SCM_MAMECCEN1_WPB_LOCK_MASK; +} + +/** + * @brief Get the lock status of CPU permission(WPB) in MAMECCEN1 register + * + * @return 1: The WPB of MAMECCEN1 register is locked + * 0: The WPB of MAMECCEN1 register is not locked + */ +LOCAL_INLINE uint32_t SCM_HWA_MAMECCEN1_GetWPBLockStatus(void) +{ + return (SCM->MAMECCEN1 & (uint32_t)SCM_MAMECCEN1_WPB_LOCK_MASK) >> SCM_MAMECCEN1_WPB_LOCK_SHIFT; +} + +/** + * @brief Get the CPU type of writing permission to MAMECCEN1 register + * + * @return SCM_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE SCM_WPB_CpuType SCM_HWA_MAMECCEN1_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((SCM->MAMECCEN1 & (uint32_t)SCM_MAMECCEN1_WPB_MASK) >> SCM_MAMECCEN1_WPB_SHIFT); + return (SCM_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set CPU to control the MAMECCEN1 register + * + * @param eCpuType CPU allowed to control peripheral + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN1_SetCpuWritePermit(SCM_WPB_CpuType eCpuType) +{ + SCM->MAMECCEN1 = ((SCM->MAMECCEN1 & (~(uint32_t)SCM_MAMECCEN1_WPB_MASK)) | SCM_MAMECCEN1_WPB(eCpuType)); +} + +/** + * @brief Get the value of MAMECCEN1 register + * @return register value + */ +LOCAL_INLINE uint32_t SCM_HWA_MAMECCEN1_GetValue(void) +{ + return SCM->MAMECCEN1; +} + +/** + * @brief Set the value of MAMECCEN1 register + * @param u32Value value to be set + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN1_SetValue(uint32_t u32Value) +{ + SCM->MAMECCEN1 = u32Value & 0x00003D33u; +} + +/** + * @brief Set the MAMECCEN1 ECC enable + * @param eMamEccType the MAM peripheral to enable ECC + * @param eEnable the ECC enable mode + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN1_Ctrl(SCM_MAMEccCtrlGrp1Type eMamEccType, SCM_EccEnModeType eEnable) +{ + if(SCM_DMA0_CFG_ECC == eMamEccType) + { + SCM->MAMECCEN1 = (SCM->MAMECCEN1 & (~(SCM_MAMECCEN1_DMA0_CFG_ECC_MASK))) | + SCM_MAMECCEN1_DMA0_CFG_ECC(eEnable); + } + else + { + SCM->MAMECCEN1 = (SCM->MAMECCEN1 & (~(SCM_MAMECCEN1_ECC_MASK << ((uint32_t)eMamEccType * SCM_MAMECCEN1_ECC_WIDTH)))) | + SCM_MAMECCEN1_ECC(eEnable) << ((uint32_t)eMamEccType * SCM_MAMECCEN1_ECC_WIDTH); + } +} + +/** + * @brief Lock the CPU permission(WPB) in CPU0ECCEN register, and WPB cannot be written until a power-on reset + * + */ +LOCAL_INLINE void SCM_HWA_CPU0ECCEN_LockWritePermit(void) +{ + SCM->CPU0ECCEN |= (uint32_t)SCM_CPU0ECCEN_WPB_LOCK_MASK; +} + +/** + * @brief Get the lock status of CPU permission(WPB) in CPU0ECCEN register + * + * @return 1: The WPB of CPU0ECCEN register is locked + * 0: The WPB of CPU0ECCEN register is not locked + */ +LOCAL_INLINE uint32_t SCM_HWA_CPU0ECCEN_GetWPBLockStatus(void) +{ + return (SCM->CPU0ECCEN & (uint32_t)SCM_CPU0ECCEN_WPB_LOCK_MASK) >> SCM_CPU0ECCEN_WPB_LOCK_SHIFT; +} + +/** + * @brief Get the CPU type of writing permission to CPU0ECCEN register + * + * @return SCM_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE SCM_WPB_CpuType SCM_HWA_CPU0ECCEN_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((SCM->CPU0ECCEN & (uint32_t)SCM_CPU0ECCEN_WPB_MASK) >> SCM_CPU0ECCEN_WPB_SHIFT); + return (SCM_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set CPU to control the CPU0ECCEN register + * + * @param eCpuType CPU allowed to control peripheral + */ +LOCAL_INLINE void SCM_HWA_CPU0ECCEN_SetCpuWritePermit(SCM_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = SCM->CPU0ECCEN; + SCM->CPU0ECCEN = ((u32RegVal & (~(uint32_t)SCM_CPU0ECCEN_WPB_MASK)) | SCM_CPU0ECCEN_WPB(eCpuType)); +} + +/** + * @brief Get the value of CPU0ECCEN register + * @return register value + */ +LOCAL_INLINE uint32_t SCM_HWA_CPU0ECCEN_GetValue(void) +{ + return SCM->CPU0ECCEN; +} + +/** + * @brief Set the value of CPU0ECCEN register + * @param u32Value value to be set + */ +LOCAL_INLINE void SCM_HWA_CPU0ECCEN_SetValue(uint32_t u32Value) +{ + SCM->CPU0ECCEN = u32Value & 0x00000FFFu; +} + +/** + * @brief Set the peripheral ECC enable of CPU0 + * @param eCpuEccType the peripheral to enable ECC + * @param eEnable the ECC enable mode + */ +LOCAL_INLINE void SCM_HWA_CPU0ECCEN_Ctrl(SCM_CPUEccCtrlType eCpuEccType, SCM_EccEnModeType eEnable) +{ + SCM->CPU0ECCEN = (SCM->CPU0ECCEN & (~(SCM_CPU0ECCEN_CPU0_ECC_MASK << ((uint32_t)eCpuEccType * SCM_CPU0ECCEN_CPU0_ECC_WIDTH)))) | + SCM_CPU0ECCEN_CPU0_ECC(eEnable) << ((uint32_t)eCpuEccType * SCM_CPU0ECCEN_CPU0_ECC_WIDTH); +} + +/** + * @brief Get SRAM1 ECC Detect Control + * @return 0: Disable EDC error when SRAM1 Multi Bit ECC Error Exist + * 1: Only Enable EDC error when SRAM1 Multi Bit ECC Error Exist + */ +LOCAL_INLINE uint32_t SCM_HWA_SRAM1_EDCErrorEnStatus(void) +{ + return (SCM->SRAM_EDC_CTRL & SCM_SRAM_EDC_CTRL_SRAM1_EDC_MASK) >> SCM_SRAM_EDC_CTRL_SRAM1_EDC_SHIFT; +} + +/** + * @brief Set SRAM1 ECC Detect Control + * @param bEnable true: Disable EDC error when SRAM1 Multi Bit ECC Error Exist + * false: Only Enable EDC error when SRAM1 Multi Bit ECC Error Exist + */ +LOCAL_INLINE void SCM_HWA_SRAM1_EDCErrorEnable(bool bEnable) +{ + SCM->SRAM_EDC_CTRL = (SCM->SRAM_EDC_CTRL & (~SCM_SRAM_EDC_CTRL_SRAM1_EDC_MASK)) | SCM_SRAM_EDC_CTRL_SRAM1_EDC(bEnable); +} + +/** + * @brief Get SRAM0 ECC Detect Control + * @return 0: Disable EDC error when SRAM0 Multi Bit ECC Error Exist + * 1: Only Enable EDC error when SRAM0 Multi Bit ECC Error Exist + */ +LOCAL_INLINE uint32_t SCM_HWA_SRAM0_EDCErrorEnStatus(void) +{ + return (SCM->SRAM_EDC_CTRL & SCM_SRAM_EDC_CTRL_SRAM0_EDC_MASK) >> SCM_SRAM_EDC_CTRL_SRAM0_EDC_SHIFT; +} + +/** + * @brief Set SRAM0 ECC Detect Control + * @param bEnable false: Disable EDC error when SRAM0 Multi Bit ECC Error Exist + * true: Only Enable EDC error when SRAM0 Multi Bit ECC Error Exist + */ +LOCAL_INLINE void SCM_HWA_SRAM0_EDCErrorEnable(bool bEnable) +{ + SCM->SRAM_EDC_CTRL = (SCM->SRAM_EDC_CTRL & (~SCM_SRAM_EDC_CTRL_SRAM0_EDC_MASK)) | SCM_SRAM_EDC_CTRL_SRAM0_EDC(bEnable); +} + +/** + * @brief Lock ROM Configuration Register + * + */ +LOCAL_INLINE void SCM_HWA_LockROMCFG(void) +{ + SCM->ROMCFG |= (uint32_t)SCM_ROMCFG_LOCK_MASK; +} + +/** + * @brief Get ROMCFG register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_ROMCFG_GetLockStatus(void) +{ + return(SCM->ROMCFG & (uint32_t)SCM_ROMCFG_LOCK_MASK) >> SCM_ROMCFG_LOCK_SHIFT; +} + +/** + * @brief Get HSM ROM Power Gating Enable status + * @return 0: Not Power Gating + * 1: Power Gating + */ +LOCAL_INLINE uint32_t SCM_HWA_GetHsmRomPowerGatingEnStatus(void) +{ + return (SCM->ROMCFG & SCM_ROMCFG_HSMROM_PGEN_MASK) >> SCM_ROMCFG_HSMROM_PGEN_SHIFT; +} + +/** + * @brief Set HSM ROM Power Gating Enable + * @param bEnable false: Not Power Gating + * true: Power Gating + */ +LOCAL_INLINE void SCM_HWA_HsmRomPowerGatingEnable(bool bEnable) +{ + SCM->ROMCFG = (SCM->ROMCFG & (~SCM_ROMCFG_HSMROM_PGEN_MASK)) | SCM_ROMCFG_HSMROM_PGEN(bEnable); +} + +/** + * @brief Get System ROM Power Gating Enable status + * @return 0: Not Power Gating + * 1: Power Gating + */ +LOCAL_INLINE uint32_t SCM_HWA_GetSysRomPowerGatingEnStatus(void) +{ + return (SCM->ROMCFG & SCM_ROMCFG_SYSROM_PGEN_MASK) >> SCM_ROMCFG_SYSROM_PGEN_SHIFT; +} + +/** + * @brief Set System ROM Power Gating Enable + * @param bEnable false: Not Power Gating + * true: Power Gating + */ +LOCAL_INLINE void SCM_HWA_SysRomPowerGatingEnable(bool bEnable) +{ + SCM->ROMCFG = (SCM->ROMCFG & (~SCM_ROMCFG_SYSROM_PGEN_MASK)) | SCM_ROMCFG_SYSROM_PGEN(bEnable); +} + +/** + * @brief Use FCSPI5 to monitor other FCSPI's transmit interface + * + * @param eSPIxType SPI type + */ +LOCAL_INLINE void SCM_HWA_FCSPI5MonSPIx(SCM_FCSPIxType eSPIxType) +{ + uint32_t u32RegVal = SCM->FCSPI_ROUTING; + SCM->FCSPI_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FCSPI_ROUTING_SPI5_ROUTER_MASK)) | SCM_FCSPI_ROUTING_SPI5_ROUTER(eSPIxType)); +} + +/** + * @brief Use FCSPI4 to monitor other FCSPI's transmit interface + * + * @param eSPIxType SPI type + */ +LOCAL_INLINE void SCM_HWA_FCSPI4MonSPIx(SCM_FCSPIxType eSPIxType) +{ + uint32_t u32RegVal = SCM->FCSPI_ROUTING; + SCM->FCSPI_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FCSPI_ROUTING_SPI4_ROUTER_MASK)) | SCM_FCSPI_ROUTING_SPI4_ROUTER(eSPIxType)); +} + +/** + * @brief Use FCSPI3 to monitor other FCSPI's transmit interface + * + * @param eSPIxType SPI type + */ +LOCAL_INLINE void SCM_HWA_FCSPI3MonSPIx(SCM_FCSPIxType eSPIxType) +{ + uint32_t u32RegVal = SCM->FCSPI_ROUTING; + SCM->FCSPI_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FCSPI_ROUTING_SPI3_ROUTER_MASK)) | SCM_FCSPI_ROUTING_SPI3_ROUTER(eSPIxType)); +} + +/** + * @brief Use FCSPI2 to monitor other FCSPI's transmit interface + * + * @param eSPIxType SPI type + */ +LOCAL_INLINE void SCM_HWA_FCSPI2MonSPIx(SCM_FCSPIxType eSPIxType) +{ + uint32_t u32RegVal = SCM->FCSPI_ROUTING; + SCM->FCSPI_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FCSPI_ROUTING_SPI2_ROUTER_MASK)) | SCM_FCSPI_ROUTING_SPI2_ROUTER(eSPIxType)); +} + +/** + * @brief Use FCSPI1 to monitor other FCSPI's transmit interface + * + * @param eSPIxType SPI type + */ +LOCAL_INLINE void SCM_HWA_FCSPI1MonSPIx(SCM_FCSPIxType eSPIxType) +{ + uint32_t u32RegVal = SCM->FCSPI_ROUTING; + SCM->FCSPI_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FCSPI_ROUTING_SPI1_ROUTER_MASK)) | SCM_FCSPI_ROUTING_SPI1_ROUTER(eSPIxType)); +} + +/** + * @brief Use FCSPI0 to monitor other FCSPI's transmit interface + * + * @param eSPIxType SPI type + */ +LOCAL_INLINE void SCM_HWA_FCSPI0MonSPIx(SCM_FCSPIxType eSPIxType) +{ + uint32_t u32RegVal = SCM->FCSPI_ROUTING; + SCM->FCSPI_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FCSPI_ROUTING_SPI0_ROUTER_MASK)) | SCM_FCSPI_ROUTING_SPI0_ROUTER(eSPIxType)); +} + +/** + * @brief Use FCUART7 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART7MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART7_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART7_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART6 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART6MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART6_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART6_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART5 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART5MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART5_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART5_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART4 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART4MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART4_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART4_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART3 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART3MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART3_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART3_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART2 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART2MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART2_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART2_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART1 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART1MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART1_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART1_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART0 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART0MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART0_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART0_ROUTER(eUartxType)); +} + +/** + * @brief Set PTIMER Loop Mode selection + * + * @param ePTimerLoopMode PTIMER Loop Mode + */ +LOCAL_INLINE void SCM_HWA_PTimerLoopModeSel(SCM_PTimerLMSelType ePTimerLoopMode) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & + (~(uint32_t)(SCM_ADC_ROUTING_PTIMER01LOOP_MASK | + SCM_ADC_ROUTING_PTIMER01LOOP_1_MASK | + SCM_ADC_ROUTING_PTIMER01LOOP_2_MASK))) | + SCM_ADC_ROUTING_PTIMER01LOOP((uint32_t)ePTimerLoopMode >> 2U)) | + SCM_ADC_ROUTING_PTIMER01LOOP_1((uint32_t)ePTimerLoopMode >> 1U) | + SCM_ADC_ROUTING_PTIMER01LOOP_2((uint32_t)ePTimerLoopMode); +} + +/** + * @brief Set ADC1 Trigger Source selection + * + * @param eAdcTriggerSrc ADC1 Trigger Source + */ +LOCAL_INLINE void SCM_HWA_ADC1TriggerSrcSel(SCM_AdcTriggerSrcType eAdcTriggerSrc) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & (~(uint32_t)SCM_ADC_ROUTING_ADC1_TRGSEL_MASK)) | + SCM_ADC_ROUTING_ADC1_TRGSEL(eAdcTriggerSrc)); +} + +/** + * @brief Set ADC1 Pre-trigger Source selection + * + * @param eAdcTriggerSrc ADC1 Pre-trigger Source + */ +LOCAL_INLINE void SCM_HWA_ADC1PreTriggerSrcSel(SCM_AdcPreTriggerSrcType eAdcPreTriggerSrc) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & (~(uint32_t)SCM_ADC_ROUTING_ADC1_PRETRGSEL_MASK)) | + SCM_ADC_ROUTING_ADC1_PRETRGSEL(eAdcPreTriggerSrc)); +} + +/** + * @brief Set ADC1 SCM Pre-trigger Source selection + * + * @param eScmSoftwarePreTriggerSrc ADC1 SCM software Pre-trigger Source + */ +LOCAL_INLINE void SCM_HWA_ADC1ScmSoftWarePreTriggerSrcSel(SCM_SoftwarePreTriggerType eScmSoftwarePreTriggerSrc) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & (~(uint32_t)SCM_ADC_ROUTING_ADC1_SWPRETRG_MASK)) | + SCM_ADC_ROUTING_ADC1_SWPRETRG(eScmSoftwarePreTriggerSrc)); +} + +/** + * @brief Set ADC0 Trigger Source selection + * + * @param eAdcTriggerSrc ADC0 Trigger Source + */ +LOCAL_INLINE void SCM_HWA_ADC0TriggerSrcSel(SCM_AdcTriggerSrcType eAdcTriggerSrc) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & (~(uint32_t)SCM_ADC_ROUTING_ADC0_TRGSEL_MASK)) | + SCM_ADC_ROUTING_ADC0_TRGSEL(eAdcTriggerSrc)); +} + +/** + * @brief Set ADC0 Pre-trigger Source selection + * + * @param eAdcTriggerSrc ADC0 Pre-trigger Source + */ +LOCAL_INLINE void SCM_HWA_ADC0PreTriggerSrcSel(SCM_AdcPreTriggerSrcType eAdcPreTriggerSrc) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & (~(uint32_t)SCM_ADC_ROUTING_ADC0_PRETRGSEL_MASK)) | + SCM_ADC_ROUTING_ADC0_PRETRGSEL(eAdcPreTriggerSrc)); +} + +/** + * @brief Set ADC0 SCM Pre-trigger Source selection + * + * @param eScmSoftwarePreTriggerSrc ADC0 SCM software Pre-trigger Source + */ +LOCAL_INLINE void SCM_HWA_ADC0ScmSoftWarePreTriggerSrcSel(SCM_SoftwarePreTriggerType eScmSoftwarePreTriggerSrc) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & (~(uint32_t)SCM_ADC_ROUTING_ADC0_SWPRETRG_MASK)) | + SCM_ADC_ROUTING_ADC0_SWPRETRG(eScmSoftwarePreTriggerSrc)); +} + +/** + * @brief Select the FTU3 output source, should be ignored when FTU3 in input mode + * + * @param eOutSelType FTU3 output source selection type + */ +LOCAL_INLINE void SCM_HWA_SetOutSel_FTU3(SCM_FTU_OutputSelType eOutSelType) +{ + uint32_t u32RegVal = SCM->FTU_ROUTING; + SCM->FTU_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FTU_ROUTING_FTU3_OUTSEL_MASK)) | SCM_FTU_ROUTING_FTU3_OUTSEL(eOutSelType)); +} + +/** + * @brief Select the FTU0 output source, should be ignored when FTU0 in input mode + * + * @param eOutSelType FTU0 output source selection type + */ +LOCAL_INLINE void SCM_HWA_SetOutSel_FTU0(SCM_FTU_OutputSelType eOutSelType) +{ + uint32_t u32RegVal = SCM->FTU_ROUTING; + SCM->FTU_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FTU_ROUTING_FTU0_OUTSEL_MASK)) | SCM_FTU_ROUTING_FTU0_OUTSEL(eOutSelType)); +} + +/** + * @brief Selects FTU2 CH1 input + * + * @param eInputSelType FTU2 CH1 input selection type + */ +LOCAL_INLINE void SCM_HWA_SetInSel_FTU2_CH1(SCM_FTU2_CH1_InputSelType eInputSelType) +{ + uint32_t u32RegVal = SCM->FTU_ROUTING; + SCM->FTU_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FTU_ROUTING_FTU2_CH1SEL_MASK)) | SCM_FTU_ROUTING_FTU2_CH1SEL(eInputSelType)); +} + +/** + * @brief Selects FTU2 CH0 input + * + * @param eInputSelType FTU2 CH0 input selection type + */ +LOCAL_INLINE void SCM_SetInSel_FTU2_CH0(SCM_FTUx_CH0_InputSelType eInputSelType) +{ + uint32_t u32RegVal = SCM->FTU_ROUTING; + SCM->FTU_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FTU_ROUTING_FTU2_CH0SEL_MASK)) | SCM_FTU_ROUTING_FTU2_CH0SEL(eInputSelType)); +} + +/** + * @brief Selects FTU1 CH0 input + * + * @param eInputSelType FTU1 CH0 input selection type + */ +LOCAL_INLINE void SCM_SetInSel_FTU1_CH0(SCM_FTUx_CH0_InputSelType eInputSelType) +{ + uint32_t u32RegVal = SCM->FTU_ROUTING; + SCM->FTU_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FTU_ROUTING_FTU1_CH0SEL_MASK)) | SCM_FTU_ROUTING_FTU1_CH0SEL(eInputSelType)); +} + +/** + * @brief Lock FTU Routing Register + * + */ +LOCAL_INLINE void SCM_HWA_LockFTU_ROUTING(void) +{ + SCM->FTU_ROUTING |= (uint32_t)SCM_FTU_ROUTING_LOCK_MASK; +} + +/** + * @brief Get FTU_ROUTING register lock status + * + * @return Lock status + * 1: FTU_ROUTING register is lock + * 0: FTU_ROUTING register is not lock + */ +LOCAL_INLINE uint32_t SCM_HWA_FTU_ROUTING_GetLockStatus(void) +{ + return (SCM->FTU_ROUTING & (uint32_t)SCM_FTU_ROUTING_LOCK_MASK) >> SCM_FTU_ROUTING_LOCK_SHIFT; +} + +/** + * @brief Lock FTU Global Time Base Control Register + * + */ +LOCAL_INLINE void SCM_HWA_LockFTU_GTB(void) +{ + SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_LOCK_MASK; +} + +/** + * @brief Get FTU GTB register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_FTU_GTB_GetLockStatus(void) +{ + return (SCM->FTU_GTBC & (uint32_t)SCM_FTU_GTBC_LOCK_MASK) >> SCM_FTU_GTBC_LOCK_SHIFT; +} + +/** + * @brief Configure FTU global time base control selection + * + * @param u32SelectedFtu The GTBC mask of Selected Ftu instance,it is the or value of SCM_FTUGTBCtrlType. + * eg.u32SelectedFtu == 1 means FTU0 selected, u32SelectedFtu == 5 means FTU0 and FTU2 selected. + */ +LOCAL_INLINE void SCM_HWA_ConfigFtuGTBSelect(uint32_t u32SelectedFtu) +{ + SCM->FTU_GTBC &= ~(uint32_t)SCM_FTU_GTBC_FTU_GTBC_MASK; + SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_FTU_GTBC(u32SelectedFtu); +} + +/** + * @brief Set FTU global time base control selection + * + * @param u32SelectedFtu The GTBC mask of Selected Ftu instance,it is the or value of SCM_FTUGTBCtrlType. + * eg.u32SelectedFtu == 1 means FTU0 selected, u32SelectedFtu == 5 means FTU0 and FTU2 selected. + */ +LOCAL_INLINE void SCM_HWA_SetFtuGTBSelect(uint32_t u32SelectedFtu) +{ + SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_FTU_GTBC(u32SelectedFtu); +} + +/** + * @brief Clear FTU global time base control selection + * + * @param u32SelectedFtu The GTBC mask of Selected Ftu instance,it is the or value of SCM_FTUGTBCtrlType. + * eg.u32SelectedFtu == 1 means FTU0 selected, u32SelectedFtu == 5 means FTU0 and FTU2 selected. + */ +LOCAL_INLINE void SCM_HWA_ClearFtuGTBSelect(uint32_t u32SelectedFtu) +{ + SCM->FTU_GTBC &= ~(uint32_t)SCM_FTU_GTBC_FTU_GTBC(u32SelectedFtu); +} + +/** + * @brief Configure TPU global time base control selection + * + * @param bEn Enable or disable TPU Global Time Base + */ +LOCAL_INLINE void SCM_HWA_ConfigTpuGTBSelect(bool bEn) +{ + SCM->FTU_GTBC &= ~(uint32_t)SCM_FTU_GTBC_TPU_GTBC_MASK; + SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_TPU_GTBC(bEn); +} + +/** + * @brief Set the value of TPU Global Time Base Control Mask Register + * + * @param u32Value Value to be set + */ +LOCAL_INLINE void SCM_HWA_SetTpuGTBMValue(uint32_t u32Value) +{ + SCM->FTU_GTBCM = u32Value; +} + +/** + * @brief Configure TPU Channel [31:24] Source Select + * + * @param eTrgSelMask The TPU Channel [31:24] Source Select mask bits + */ +LOCAL_INLINE void SCM_HWA_ConfigTpuTrgSel(uint8_t eTrgSelMask) +{ + SCM->FTU_GTBCM = (SCM->FTU_GTBCM & (~(uint32_t)SCM_TPU_GTBCM_TPU_TRGSEL_MASK)) | + (uint32_t)SCM_TPU_GTBCM_TPU_TRGSEL(eTrgSelMask); +} + +/** + * @brief Configure TPU GTBC Mask is corresponding to channel trigger of TSTMP1 + * + * @param eTpuGTBMask The TPU GTBC Mask (must be 0 ~ 15) + */ +LOCAL_INLINE void SCM_HWA_ConfigTpuGTBMask(uint8_t eTpuGTBMask) +{ + SCM->FTU_GTBCM = (SCM->FTU_GTBCM & (~(uint32_t)SCM_TPU_GTBCM_TPU_GTBCM_MASK)) | + (uint32_t)SCM_TPU_GTBCM_TPU_GTBCM(eTpuGTBMask); +} + +/** + * @brief Configure FTU Global Time Base Control Mask Register + * + * @param u8FtuIndex The selected FTU instance (must be 0 ~ 7) + * @param u32Value Value to be set (must be 0 ~ 15) + */ +LOCAL_INLINE void SCM_HWA_ConfigFtuGTBMask(uint8_t u8FtuIndex, uint32_t u32Value) +{ + SCM->FTU_GTBCM &= ~ ((uint32_t)SCM_FTU_GTBCM_FTU0_GTBCM_MASK << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex)); + SCM->FTU_GTBCM |= (((uint32_t)u32Value & SCM_FTU_GTBCM_FTU0_GTBCM_MASK) << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex)); +} + +/** + * @brief Clear FTU Global Time Base Control Mask Register + * + * @param u8FtuIndex The selected FTU instance (must be 0 ~ 7) + */ +LOCAL_INLINE void SCM_HWA_ClearFtuGTBMask(uint8_t u8FtuIndex) +{ + SCM->FTU_GTBCM &= ~ ((uint32_t)SCM_FTU_GTBCM_FTU0_GTBCM_MASK << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex)); +} + +/** + * @brief Set FTU sync control + * + * @param u32Value The sync mask of selected FTU instance + * u32Value must be the or value of SCM_FTUSyncCtrlType + */ +LOCAL_INLINE void SCM_HWA_SetFTUSync(uint32_t u32Value) +{ + SCM->FTU_SYNC = u32Value & SCM_FTU_SYNC_MASK; +} + +/** + * @brief Lock FTU GTB Register + * + */ +LOCAL_INLINE void SCM_HWA_LockDEBUG_TRACE(void) +{ + SCM->DEBUG_TRACE |= (uint32_t)SCM_DEBUG_TRACE_LOCK_MASK; +} + +/** + * @brief Get FTU GTB register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_DEBUG_TRACE_GetLockStatus(void) +{ + return(SCM->DEBUG_TRACE & (uint32_t)SCM_DEBUG_TRACE_LOCK_MASK) >> SCM_DEBUG_TRACE_LOCK_SHIFT; +} + +/** + * @brief Set debug atclk enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_DebugATClk(bool bEnable) +{ + SCM->DEBUG_TRACE = (SCM->DEBUG_TRACE & (~(SCM_DEBUG_TRACE_DEBUG_ATCLK_EN_MASK))) | + SCM_DEBUG_TRACE_DEBUG_ATCLK_EN(bEnable); +} + +/** + * @brief Set trace clock divider value + * + * @param u32Value The divider value to be set + */ +LOCAL_INLINE void SCM_HWA_SetTraceClkDiv(uint32_t u32Value) +{ + SCM->DEBUG_TRACE = ((SCM->DEBUG_TRACE & (~(uint32_t)SCM_DEBUG_TRACE_TRACECLK_DIV_MASK)) | + SCM_DEBUG_TRACE_TRACECLK_DIV(u32Value)); +} + +/** + * @brief Set trace clock selection + * + * @param eSrcClkType Clock selection + */ +LOCAL_INLINE void SCM_HWA_SetTraceClkSrc(SCM_TraceClkSrcType eSrcClkType) +{ + SCM->DEBUG_TRACE = ((SCM->DEBUG_TRACE & (~(uint32_t)SCM_DEBUG_TRACE_TRACECLK_SEL_MASK)) | + SCM_DEBUG_TRACE_TRACECLK_SEL(eSrcClkType)); +} + +/** + * @brief Set trace clock divider enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_TraceClk(bool bEnable) +{ + SCM->DEBUG_TRACE = (SCM->DEBUG_TRACE & (~(SCM_DEBUG_TRACE_TRACECLK_EN_MASK))) | + SCM_DEBUG_TRACE_TRACECLK_EN(bEnable); +} + +/** + * @brief Lock the SOCMISC register + * + */ +LOCAL_INLINE void SCM_HWA_SOCMISC_LockWritePermit(void) +{ + SCM->SOCMISC |= (uint32_t)SCM_SOCMISC_WPB_LOCK_MASK; +} + +/** + * @brief Get the SOCMISC register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_SOCMISC_GetWPBLockStatus(void) +{ + return (SCM->SOCMISC & (uint32_t)SCM_SOCMISC_WPB_LOCK_MASK) >> SCM_SOCMISC_WPB_LOCK_SHIFT; +} + +/** + * @brief Get the CPU type of writing permission to SOCMISC register + * + * @return SCM_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE SCM_WPB_CpuType SCM_HWA_SOCMISC_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = (SCM->SOCMISC & (uint32_t)SCM_SOCMISC_WPB_MASK) >> SCM_SOCMISC_WPB_SHIFT; + return (SCM_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set cpu to control SOCMISC register + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void SCM_HWA_SOCMISC_SetCpuWritePermit(SCM_WPB_CpuType eCpuType) +{ + SCM->SOCMISC = ((SCM->SOCMISC & (~(uint32_t)SCM_SOCMISC_WPB_MASK)) | SCM_SOCMISC_WPB(eCpuType)); +} + +/** + * @brief Set software trigger 4~7 to TRGSEL1 & TRGSEL5 + * + * @param eTriggerType software trigger number (SCM_SW_TRIG_0 ~ SCM_SW_TRIG_3) + */ +LOCAL_INLINE void SCM_HWA_SetSwTrigx_Trgsel15(SCM_SwTrigxType eTriggerType) +{ + SCM->SOCMISC = ((SCM->SOCMISC & (~(uint32_t)SCM_SOCMISC_GPR_SW_TRIG_7_4_MASK)) | + SCM_SOCMISC_GPR_SW_TRIG_7_4(eTriggerType)); +} + +/** + * @brief Set software trigger 0~3 to TRGSEL0 & TRGSEL4 + * + * @param eTriggerType software trigger number (SCM_SW_TRIG_4 ~ SCM_SW_TRIG_7) + */ +LOCAL_INLINE void SCM_HWA_SetSwTrigx_Trgsel04(SCM_SwTrigxType eTriggerType) +{ + SCM->SOCMISC = ((SCM->SOCMISC & (~(uint32_t)SCM_SOCMISC_GPR_SW_TRIG_3_0_MASK)) | + SCM_SOCMISC_GPR_SW_TRIG_3_0(eTriggerType)); +} + +/** + * @brief Get CCM0 status + * + * @return CCM0 Status, it is the or value of SCM_CCMxStatusType + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_CCM0( void ) +{ + return SCM->CCM0_STATUS & SCM_CCM0_STATUS_MASK; +} + +/** + * @brief Lock FLEXCAN_ROUTING Register + * + */ +LOCAL_INLINE void SCM_HWA_LockFLEXCAN_ROUTING(void) +{ + SCM->FLEXCAN_ROUTING |= (uint32_t)SCM_FLEXCAN_ROUTING_LOCK_MASK; +} + +/** + * @brief Get FLEXCAN_ROUTING register lock status + * + * @return Lock status + * 1: FLEXCAN_ROUTING register is lock + * 0: FLEXCAN_ROUTING register is not lock + */ +LOCAL_INLINE uint32_t SCM_HWA_FLEXCAN_ROUTING_GetLockStatus(void) +{ + return (SCM->FLEXCAN_ROUTING & (uint32_t)SCM_FLEXCAN_ROUTING_LOCK_MASK) >> SCM_FLEXCAN_ROUTING_LOCK_SHIFT; +} + +/** + * @brief Select TRESEL input from pad TRGSEL_IN0~TRGSEL_IN15 for FLEXCAN0/1/2/3 RX + * + * @param u16TrgSel Enable Select TRESEL input from pad TRGSEL_IN0~TRGSEL_IN15 for FLEXCAN0/1/2/3 RX + */ +LOCAL_INLINE void SCM_HWA_FLEXCAN_ROUTING_SetTriggerSel(uint16_t u16TrgSel) +{ + SCM->FLEXCAN_ROUTING = ((SCM->FLEXCAN_ROUTING & (~(uint32_t)SCM_FLEXCAN_ROUTING_FLEXCAN_TRIGGER_MASK_MASK)) | + SCM_FLEXCAN_ROUTING_FLEXCAN_TRIGGER_MASK(u16TrgSel)); +} + +/** + * @brief Set MSC0 ALTIN high higher bits[31:24] source selection + * + * @param eInSelType Router selection + */ +LOCAL_INLINE void SCM_HWA_SetSel_MSC0AltInHH(SCM_MSCAltInSelType eInSelType) +{ + uint32_t u32RegVal = SCM->MSC0_ROUTING; + SCM->MSC0_ROUTING = ((u32RegVal & (~(uint32_t)SCM_MSC0_ROUTING_MSC0_31_24_SEL_MASK)) | SCM_MSC0_ROUTING_MSC0_31_24_SEL(eInSelType)); +} + +/** + * @brief Set MSC0 ALTIN high lower bits[23:16] source selection + * + * @param eInSelType Router selection + */ +LOCAL_INLINE void SCM_HWA_SetSel_MSC0AltInHL(SCM_MSCAltInSelType eInSelType) +{ + uint32_t u32RegVal = SCM->MSC0_ROUTING; + SCM->MSC0_ROUTING = ((u32RegVal & (~(uint32_t)SCM_MSC0_ROUTING_MSC0_23_16_SEL_MASK)) | SCM_MSC0_ROUTING_MSC0_23_16_SEL(eInSelType)); +} + +/** + * @brief Set MSC0 ALTIN low higher bits[15:8] source selection + * + * @param eInSelType Router selection + */ +LOCAL_INLINE void SCM_HWA_SetSel_MSC0AltInLH(SCM_MSCAltInSelType eInSelType) +{ + uint32_t u32RegVal = SCM->MSC0_ROUTING; + SCM->MSC0_ROUTING = ((u32RegVal & (~(uint32_t)SCM_MSC0_ROUTING_MSC0_15_8_SEL_MASK)) | SCM_MSC0_ROUTING_MSC0_15_8_SEL(eInSelType)); +} + +/** + * @brief Set MSC0 ALTIN low lower bits[7:0] source selection + * + * @param eInSelType Router selection + */ +LOCAL_INLINE void SCM_HWA_SetSel_MSC0AltInLL(SCM_MSCAltInSelType eInSelType) +{ + uint32_t u32RegVal = SCM->MSC0_ROUTING; + SCM->MSC0_ROUTING = ((u32RegVal & (~(uint32_t)SCM_MSC0_ROUTING_MSC0_7_0_SEL_MASK)) | SCM_MSC0_ROUTING_MSC0_7_0_SEL(eInSelType)); +} + +/** + * @brief Lock MSC0_ROUTING Register + * + */ +LOCAL_INLINE void SCM_HWA_LockMSC0_ROUTING(void) +{ + SCM->MSC0_ROUTING |= (uint32_t)SCM_MSC0_ROUTING_LOCK_MASK; +} + +/** + * @brief Get MSC0_ROUTING register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_MSC0_ROUTING_GetLockStatus(void) +{ + return(SCM->MSC0_ROUTING & (uint32_t)SCM_MSC0_ROUTING_LOCK_MASK) >> SCM_MSC0_ROUTING_LOCK_SHIFT; +} + +/** + * @brief Set FCSMU software trigger enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_FCSMUSwTrigger(bool bEnable) +{ + SCM->FCSMU_SW = (SCM->FCSMU_SW & (~(SCM_FCSMU_SW_FCSMU_SW_MASK))) | + SCM_FCSMU_SW_FCSMU_SW(bEnable); +} + +/** + * @brief FTU_IN[15:8] Source Select + * + * @param eRouterType Router source selection + */ +LOCAL_INLINE void SCM_HWA_SetIsmRouterFtuD(SCM_ISMRouterType eRouterType) +{ + SCM->ISM_ROUTING = ((SCM->ISM_ROUTING & (~(uint32_t)SCM_ISM_ROUTING_ISM_ROUT_FTU_D_MASK)) | + SCM_ISM_ROUTING_ISM_ROUT_FTU_D(eRouterType)); +} + +/** + * @brief FTU_IN[7:0] Source Select + * + * @param eRouterType Router source selection + */ +LOCAL_INLINE void SCM_HWA_SetIsmRouterFtuC(SCM_ISMRouterType eRouterType) +{ + SCM->ISM_ROUTING = ((SCM->ISM_ROUTING & (~(uint32_t)SCM_ISM_ROUTING_ISM_ROUT_FTU_C_MASK)) | + SCM_ISM_ROUTING_ISM_ROUT_FTU_C(eRouterType)); +} + +/** + * @brief Set ISM_FTU_ROUT[15:8] source select + * + * @param eRouterType Router source selection + */ +LOCAL_INLINE void SCM_HWA_SetIsmRouterFtuB(SCM_ISMRouterType eRouterType) +{ + SCM->ISM_ROUTING = ((SCM->ISM_ROUTING & (~(uint32_t)SCM_ISM_ROUTING_ISM_ROUT_FTU_B_MASK)) | + SCM_ISM_ROUTING_ISM_ROUT_FTU_B(eRouterType)); +} + +/** + * @brief Set ISM_FTU_ROUT[7:0] source select + * + * @param eRouterType Router source selection + */ +LOCAL_INLINE void SCM_HWA_SetIsmRouterFtuA(SCM_ISMRouterType eRouterType) +{ + SCM->ISM_ROUTING = ((SCM->ISM_ROUTING & (~(uint32_t)SCM_ISM_ROUTING_ISM_ROUT_FTU_A_MASK)) | + SCM_ISM_ROUTING_ISM_ROUT_FTU_A(eRouterType)); +} + +/** + * @brief Get matrix status register 0 status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_STATUS0(void) +{ + return SCM->MATRIX_STATUS0; +} + +/** + * @brief clear matrix status register 0 status + * + * @u32Status Matrix status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_STATUS0(uint32_t u32Status) +{ + SCM->MATRIX_STATUS0 |= u32Status & SCM_MATRIX_STATUS0_MASK; +} + +/** + * @brief Get matrix status register 1 status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_STATUS1(void) +{ + return SCM->MATRIX_STATUS1; +} + +/** + * @brief clear matrix status register 1 status + * + * @u32Status Matrix status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_STATUS1(uint32_t u32Status) +{ + SCM->MATRIX_STATUS1 |= u32Status & SCM_MATRIX_STATUS1_MASK; +} + +/** + * @brief Get matrix status register 2 status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_STATUS2(void) +{ + return SCM->MATRIX_STATUS2; +} + +/** + * @brief clear matrix status register 2 status + * + * @u32Status Matrix status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_STATUS2(uint32_t u32Status) +{ + SCM->MATRIX_STATUS2 |= u32Status & SCM_MATRIX_STATUS2_MASK; +} + +/** + * @brief Get matrix status register 5 status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_STATUS5(void) +{ + return SCM->MATRIX_STATUS5; +} + +/** + * @brief clear matrix status register 5 status + * + * @u32Status Matrix status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_STATUS5(uint32_t u32Status) +{ + SCM->MATRIX_STATUS5 |= u32Status & SCM_MATRIX_STATUS5_MASK; +} + +/** + * @brief Get matrix status register 6 status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_STATUS6(void) +{ + return SCM->MATRIX_STATUS6; +} + +/** + * @brief clear matrix status register 6 status + * + * @u32Status Matrix status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_STATUS6(uint32_t u32Status) +{ + SCM->MATRIX_STATUS6 |= u32Status & SCM_MATRIX_STATUS6_MASK; +} + +/** + * @brief Get matrix status register 7 status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_STATUS7(void) +{ + return SCM->MATRIX_STATUS7; +} + +/** + * @brief clear matrix status register 7 status + * + * @u32Status Matrix status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_STATUS7(uint32_t u32Status) +{ + SCM->MATRIX_STATUS7 |= u32Status & SCM_MATRIX_STATUS7_MASK; +} + +/** + * @brief Get matrix ID status register status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_ID_STATUS0(void) +{ + return SCM->MATRIX_ID_STATUS0; +} + +/** + * @brief clear matrix ID status register status + * + * @u32Status Matrix ID status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_ID_STATUS0(uint32_t u32Status) +{ + SCM->MATRIX_ID_STATUS0 |= u32Status & SCM_MATRIX_ID_STATUS0_MASK; +} + +/** + * @brief Set SCM module mailbox data out, output from device to debug + * + * @param u32Value Ouputdata value + */ +LOCAL_INLINE void SCM_HWA_SetData_MDO(uint32_t u32Value) +{ + SCM->SYSAP_MDO = u32Value; +} + +/** + * @brief Get SCM module mailbox data in, input from debug to device + * + * @return u32Value Input data value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_MDI(void) +{ + return SCM->SYSAP_MDI; +} + +/** + * @brief Select the type of Status2 Register + * + * @param eStatus2Sel Selected Status2 type + */ +LOCAL_INLINE void SCM_HWA_Status2RegisterSelection(SCM_SysAPStatus2SelType eStatus2Sel) +{ + SCM->SYSAP_CTRL = (SCM->SYSAP_CTRL & (~(SCM_SYSAP_CTRL_STATUS2_REG_SEL_MASK))) | + SCM_SYSAP_CTRL_STATUS2_REG_SEL(eStatus2Sel); +} + +/** + * @brief Get new mailbox data input available flag, + * device read MDI regiser will automatically clear the bit + * + * @return Mailbox data input available/disable + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_NewMDIAvailable(void) +{ + return ((SCM->SYSAP_CTRL & (uint32_t)SCM_SYSAP_CTRL_NEW_MDI_AVAILABLE_MASK)>>(uint32_t)SCM_SYSAP_CTRL_NEW_MDI_AVAILABLE_SHIFT); +} + +/** + * @brief Control if CPU0 hold in wait at the end of reset sequence + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_Cpu0HoldInWait(bool bEnable) +{ + SCM->SYSAP_CTRL = (SCM->SYSAP_CTRL & (~(SCM_SYSAP_CTRL_CPU0_HOLD_IN_WAIT_MASK))) | + SCM_SYSAP_CTRL_CPU0_HOLD_IN_WAIT(bEnable); +} + +/** + * @brief Control if hold CPU0 in reset at the end of reset sequence + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_Cpu0HoldInReset(bool bEnable) +{ + SCM->SYSAP_CTRL = (SCM->SYSAP_CTRL & (~(SCM_SYSAP_CTRL_CPU0_HOLD_IN_RESET_MASK))) | + SCM_SYSAP_CTRL_CPU0_HOLD_IN_RESET(bEnable); +} + +/** + * @brief Set to force a system reset, clear the bit to release system from reset + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_SystemReset(bool bEnable) +{ + SCM->SYSAP_CTRL = (SCM->SYSAP_CTRL & (~(SCM_SYSAP_CTRL_SYSTEM_RESET_REQ_MASK))) | + SCM_SYSAP_CTRL_SYSTEM_RESET_REQ(bEnable); +} + +/** + * @brief Set to force all CPU debug restarted, CPU to exit halt state + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_AllCpuDebugRestart(bool bEnable) +{ + SCM->SYSAP_CTRL = (SCM->SYSAP_CTRL & (~(SCM_SYSAP_CTRL_CPU_DEBUG_RESTART_MASK))) | + SCM_SYSAP_CTRL_CPU_DEBUG_RESTART(bEnable); +} + +/** + * @brief Set to force core to halt, if core is in stop mode. + * This bit can be used to wakeup the core and transition to halt state + * + * @param eSelType Cpu type selection + */ +LOCAL_INLINE void SCM_HWA_SetSel_CpuDebugRequest(SCM_SysApCpuDebugReqType eSelType) +{ + SCM->SYSAP_CTRL = ((SCM->SYSAP_CTRL & (~(uint32_t)SCM_SYSAP_CTRL_CPU_DEBUG_REQ_MASK)) | + SCM_SYSAP_CTRL_CPU_DEBUG_REQ(eSelType)); +} + +/** + * @brief Set to disable the debug, clear to allow debug operation + * + * @param bDisable Disable/Enable + */ +LOCAL_INLINE void SCM_HWA_SetDisable_Debug(bool bDisable) +{ + SCM->SYSAP_CTRL = ((SCM->SYSAP_CTRL & (~(uint32_t)SCM_SYSAP_CTRL_DEBUG_DIS_MASK)) | + SCM_SYSAP_CTRL_DEBUG_DIS(bDisable)); +} + +/** + * @brief Set to Trigger Flash Mass Erase.Cleared by hardware after mass erase is done + * + */ +LOCAL_INLINE void SCM_HWA_TriggerFlashMassErase(void) +{ + SCM->SYSAP_CTRL |= SCM_SYSAP_CTRL_FLASH_MASS_ERASE_MASK; +} + +/** + * @brief Lock the CPU permission(WPB) in SUBSYS_PCC register, and WPB cannot be written until a power-on reset + * + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_LockWritePermit(void) +{ + SCM->SUBSYS_PCC |= (uint32_t)SCM_SUBSYS_PCC_WPB_LOCK_MASK; +} + +/** + * @brief Get the lock status of CPU permission(WPB) in SUBSYS_PCC register + * + * @return 1: The WPB of SUBSYS_PCC register is locked + * 0: The WPB of SUBSYS_PCC register is not locked + */ +LOCAL_INLINE uint32_t SCM_HWA_SUBSYS_PCC_GetWPBLockStatus(void) +{ + return (SCM->SUBSYS_PCC & (uint32_t)SCM_SUBSYS_PCC_WPB_LOCK_MASK) >> SCM_SUBSYS_PCC_WPB_LOCK_SHIFT; +} + +/** + * @brief Get the CPU type of writing permission to SUBSYS_PCC register + * + * @return SCM_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE SCM_WPB_CpuType SCM_HWA_SUBSYS_PCC_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((SCM->SUBSYS_PCC & (uint32_t)SCM_SUBSYS_PCC_WPB_MASK) >> SCM_SUBSYS_PCC_WPB_SHIFT); + return (SCM_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set CPU to control the SUBSYS_PCC register + * + * @param eCpuType CPU allowed to control peripheral + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetCpuWritePermit(SCM_WPB_CpuType eCpuType) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_WPB_MASK)) | SCM_SUBSYS_PCC_WPB(eCpuType)); +} + +/** + * @brief Get TPU clock enable/disable status + * + * @return 1: TPU clock disabled + * 0: TPU clock enabled + */ +LOCAL_INLINE uint32_t SCM_HWA_SUBSYS_PCC_GetStatus_TPUClock(void) +{ + return (SCM->SUBSYS_PCC & SCM_SUBSYS_PCC_CLKEN_TPU_MASK) >> SCM_SUBSYS_PCC_CLKEN_TPU_SHIFT; +} + +/** + * @brief Set TPU clock enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_TPUClock(bool bEnable) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_CLKEN_TPU_MASK)) | + SCM_SUBSYS_PCC_CLKEN_TPU(bEnable)); +} + +/** + * @brief Get HSM clock enable/disable status + * + * @return 1: HSM clock disabled + * 0: HSM clock enabled + */ +LOCAL_INLINE uint32_t SCM_HWA_SUBSYS_PCC_GetStatus_HSMClock(void) +{ + return (SCM->SUBSYS_PCC & SCM_SUBSYS_PCC_CLKEN_HSM_ENGINE_MASK) >> SCM_SUBSYS_PCC_CLKEN_HSM_ENGINE_SHIFT; +} + +/** + * @brief Set HSM clock enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_HSMClock(bool bEnable) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_CLKEN_HSM_ENGINE_MASK)) | + SCM_SUBSYS_PCC_CLKEN_HSM_ENGINE(bEnable)); +} + +/** + * @brief Get SubSystem clock enable/disable status + * + * @return 1: SubSystem clock disabled + * 0: SubSystem clock enabled + */ +LOCAL_INLINE uint32_t SCM_HWA_SUBSYS_PCC_GetStatus_SubSystemClock(void) +{ + return (SCM->SUBSYS_PCC & SCM_SUBSYS_PCC_CLKEN_SUBSYS_MASK) >> SCM_SUBSYS_PCC_CLKEN_SUBSYS_SHIFT; +} + +/** + * @brief Set SubSystem clock enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_SubSystemClock(bool bEnable) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_CLKEN_SUBSYS_MASK)) | + SCM_SUBSYS_PCC_CLKEN_SUBSYS(bEnable)); +} + +/** + * @brief Set SubSystem software reset + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_SwReset(bool bEnable) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_SWRST_MASK)) | + SCM_SUBSYS_PCC_SWRST(bEnable)); +} + +/** + * @brief Set SubSystem watchdog reset + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_SubsysWdgReset(bool bEnable) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_WDG_RSTEN_MASK)) | + SCM_SUBSYS_PCC_WDG_RSTEN(bEnable)); +} + +/** + * @brief Set SubSystem stop mode request + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_SubsysStopModReq(bool bEnable) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_STOP_REQ_MASK)) | + SCM_SUBSYS_PCC_STOP_REQ(bEnable)); +} + +/** + * @brief Subsystem status register value + * + * @return Subsystem status register + */ +LOCAL_INLINE uint32_t SCM_HWA_GetValue_SUBSYS_STATUS(void) +{ + return SCM->SUBSYS_STATUS; +} + +/** + * @brief Get Subsystem Error Report + * + * @return Subsystem Error Report + */ +LOCAL_INLINE uint16_t SCM_HWA_GetStatus_SUBSYS_ERR(void) +{ + return (SCM->SUBSYS_STATUS & SCM_SUBSYS_STATUS_HSM_SYS_ERR_MASK) >> SCM_SUBSYS_STATUS_HSM_SYS_ERR_SHIFT; +} + +/** + * @brief Get Subsystem status + * + * @return true: Subsystem status asserted + * false: Subsystem status not asserted + */ +LOCAL_INLINE bool SCM_HWA_GetStatus_SUBSYS_STATUS(SCM_SUBSYSStatusType eStatusType) +{ + return ((SCM->SUBSYS_STATUS & (uint32_t)eStatusType) != 0U) ? true : false; +} + +/** + * @brief Get mailbox data output from device to debug flag + * + * @return Flag status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MDOFlag(void) +{ + return (SCM->MDO_FLAG & SCM_MDO_FLAG_MDO_FLAG_MASK) >> SCM_MDO_FLAG_MDO_FLAG_SHIFT; +} + +/** + * @brief Lock the CPU permission(WPB) in MASTER_HALT_REQ register, and WPB cannot be written until a power-on reset + * + */ +LOCAL_INLINE void SCM_HWA_MASTER_HALT_REQ_LockWritePermit(void) +{ + SCM->MASTER_HALT_REQ |= (uint32_t)SCM_MASTER_HALT_REQ_WPB_LOCK_MASK; +} + +/** + * @brief Get the lock status of CPU permission(WPB) in MASTER_HALT_REQ register + * + * @return 1: The WPB of MASTER_HALT_REQ register is locked + * 0: The WPB of MASTER_HALT_REQ register is not locked + */ +LOCAL_INLINE uint32_t SCM_HWA_MASTER_HALT_REQ_GetWPBLockStatus(void) +{ + return (SCM->MASTER_HALT_REQ & (uint32_t)SCM_MASTER_HALT_REQ_WPB_LOCK_MASK); +} + +/** + * @brief Get the CPU type of writing permission to MASTER_HALT_REQ register + * + * @return SCM_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE SCM_WPB_CpuType SCM_HWA_MASTER_HALT_REQ_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((SCM->MASTER_HALT_REQ & (uint32_t)SCM_MASTER_HALT_REQ_WPB_MASK) >> SCM_MASTER_HALT_REQ_WPB_SHIFT); + return (SCM_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set CPU to control the MASTER_HALT_REQ register + * + * @param eCpuType CPU allowed to control peripheral + */ +LOCAL_INLINE void SCM_HWA_MASTER_HALT_REQ_SetCpuWritePermit(SCM_WPB_CpuType eCpuType) +{ + SCM->MASTER_HALT_REQ = ((SCM->MASTER_HALT_REQ & (~(uint32_t)SCM_MASTER_HALT_REQ_WPB_MASK)) | + SCM_MASTER_HALT_REQ_WPB(eCpuType)); +} + +/** + * @brief Set MASTER_HALT_REQ halt request + * + * @param eHaltReq halt request defined in SCM_HaltReqType + */ +LOCAL_INLINE void SCM_HWA_SetSel_MASTER_HALT_REQ(SCM_HaltReqType eHaltReq) +{ + SCM->MASTER_HALT_REQ |= (uint32_t)1U << ((uint32_t)eHaltReq * 8U); +} + +/** + * @brief Get MASTER_HALT_ACK halt ACK status + * + * @return SCM_HaltReqAckType Ack status + */ +LOCAL_INLINE SCM_HaltReqAckType SCM_HWA_GetStatus_MASTER_HALT_ACK(SCM_HaltReqType eHaltReq) +{ + uint32_t u32RegVal = (SCM->MASTER_HALT_ACK >> ((uint32_t)eHaltReq * 8U)) & 0x7U; + return (SCM_HaltReqAckType)u32RegVal; +} + +/** + * @brief Set CPU0 NMI interrupt router enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_Cpu0NMIIrqRouter(bool bEnable) +{ + SCM->INT_ROUTER_NMI = (SCM->INT_ROUTER_NMI & (~(SCM_INT_ROUTER_NMI_C0_EN_MASK))) | + SCM_INT_ROUTER_NMI_C0_EN(bEnable); +} + +/** + * @brief Lock SCM_INT_ROUTER_NMI register + * + */ +LOCAL_INLINE void SCM_HWA_LockINT_ROUTER_NMI(void) +{ + SCM->INT_ROUTER_NMI |= (uint32_t)SCM_INT_ROUTER_NMI_LOCK_MASK; +} + +/** + * @brief Get SCM_INT_ROUTER_NMI register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_INT_ROUTER_NMI_GetLockStatus(void) +{ + return (SCM->INT_ROUTER_NMI & (uint32_t)SCM_INT_ROUTER_NMI_LOCK_MASK) >> SCM_INT_ROUTER_NMI_LOCK_SHIFT; +} + +/** + * @brief Get CRC done Flag + * + * @return CRC done Flag + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_CrcDoneFlag(void) +{ + return((SCM->CRCCSR & (uint32_t)SCM_CRCCSR_DONE_MASK)>>(uint32_t)SCM_CRCCSR_DONE_SHIFT); +} + +/** + * @brief Get CRC Error Flag + * + * @return CRC Error Flag + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_CrcErrFlag(void) +{ + return((SCM->CRCCSR & (uint32_t)SCM_CRCCSR_ERR_MASK)>>(uint32_t)SCM_CRCCSR_ERR_SHIFT); +} + +/** + * @brief Clear CRC error flag + */ +LOCAL_INLINE void SCM_HWA_ClearCrcErrorFlag(void) +{ + SCM->CRCCSR |= (uint32_t)SCM_CRCCSR_ERR_MASK; +} + +/** + * @brief Get CRC Busy Flag + * + * @return CRC Busy Flag + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_CrcBusyFlag(void) +{ + return((SCM->CRCCSR & (uint32_t)SCM_CRCCSR_BUY_MASK)>>(uint32_t)SCM_CRCCSR_BUY_SHIFT); +} + +/** + * @brief Set CRC error out enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_CrcErrOut(bool bEnable) +{ + SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_EOEN_MASK))) | SCM_CRCCSR_EOEN(bEnable); +} + +/** + * @brief Set CRC check enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_CrcCheck(bool bEnable) +{ + SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_CHKEN_MASK))) | SCM_CRCCSR_CHKEN(bEnable); +} + +/** + * @brief Set CRC trigger enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_CrcTrigger(bool bEnable) +{ + SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_TRGEN_MASK))) | SCM_CRCCSR_TRGEN(bEnable); +} + +/** + * @brief Set CRC software generate enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_CrcSwGen(bool bEnable) +{ + SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_GEN_MASK))) | SCM_CRCCSR_GEN(bEnable); +} + +/** + * @brief Get CRC result + * + * @return CRC result + */ +LOCAL_INLINE uint32_t SCM_HWA_GetCrcResult(void) +{ + return SCM->CRCRES; +} + + + + +#endif /*#ifndef _HWA_SCM_H_ */ diff --git a/Inc/HwA_sec.h b/Inc/HwA_sec.h new file mode 100644 index 0000000..2e4752a --- /dev/null +++ b/Inc/HwA_sec.h @@ -0,0 +1,859 @@ +/** + * @file HwA_sec.h + * @author Flagchip + * @brief FC7xxx sec hardware access layer + * @version 0.2.0 + * @date 2023-2-7 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.2.0 2023-2-7 Flagchip076 N/A First version for FC7300 + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_SEC_H_ +#define HWA_INCLUDE_HWA_SEC_H_ +#include "device_header.h" + +/** + * @addtogroup HwA_SEC + * @{ + * + */ + +/* DEN Bit Fields */ +/** + *@brief Enable the debug module + * */ +LOCAL_INLINE void SEC_HWA_EnDebug(void) +{ + SEC->DEN = SEC_DEN_DEN(0X5) ; +} + +/* FSEC0 Bit Fields */ +/** + * @brief Get the system security KEY0 + * */ +LOCAL_INLINE uint16_t SEC_HWA_GetSScontrol0(void) +{ + return (uint16_t)((SEC->FSEC0) & (SEC_FSEC0_SSC0_MASK)); +} + +/* FSEC1 Bit Fields */ +/** + * @brief Get the system security KEY1 + * */ +LOCAL_INLINE uint16_t SEC_HWA_GetSScontrol1(void) +{ + return (uint16_t)((SEC->FSEC1) & (SEC_FSEC1_SSC1_MASK)); +} + +/* DCWOR Bit Fields */ +/** + * @brief Re-enable the Debug mode. + * @note This register can only be write once. startup_fc4150.s has lock the register. + * */ +LOCAL_INLINE void SEC_HWA_ReEnDebug(void) +{ + SEC->DCWOR = ((SEC->DCWOR & (~SEC_DCWOR_DEA_MASK)) | SEC_DCWOR_DEA(0X5)); +} + +/** + * @brief Get the Re-enable Debug permission. + * */ +LOCAL_INLINE bool SEC_HWA_GetReEnDebug(void) +{ + bool ret = false; + uint8_t dea = (uint8_t)((SEC->DCWOR & (SEC_DCWOR_DEA_MASK)) >> SEC_DCWOR_DEA_SHIFT); + if (dea == 0x5U) + { + ret = true; + } + return ret; +} + +/** + * @brief Enable the write operation for SEC register. + * @note This register can only be write once. startup_fc4150.s has lock the register. + * */ +LOCAL_INLINE void SEC_HWA_WriteUnlock(void) +{ + SEC->DCWOR = ((SEC->DCWOR & (~SEC_DCWOR_RWL_MASK)) | SEC_DCWOR_RWL(0X5)); +} + +/** + * @brief Get the sec write permission + * @return true means allow write. false means forbid write. +*/ +LOCAL_INLINE bool SEC_HWA_GetWritePer(void) +{ + bool ret = false; + uint8_t rwl = (uint8_t)((SEC->DCWOR & (SEC_DCWOR_RWL_MASK)) >> SEC_DCWOR_RWL_SHIFT); + if ((rwl == 0x5U) || (rwl == 0xFU)) + { + ret = true; + } + return ret; +} + +/* DEK Bit Fields */ +/** + * @brief Enable the write operation for SEC register. + * */ +LOCAL_INLINE void SEC_HWA_ChangeDBK(uint8_t count, uint32_t key) +{ + + SEC->DEK[count] = SEC_DEK_DEK(key) ; + +} + +/* TME Bit Fields */ +/** + *@brief Enable the Test module + * */ +LOCAL_INLINE void SEC_HWA_EnTest(void) +{ + SEC->TME = SEC_TME_TME(0X5) ; +} + +/* TMEA Bit Fields */ +/** + * @brief Re-Enable Test mode + * */ +LOCAL_INLINE void SEC_HWA_ReEnTest(void) +{ + SEC->TMEA = SEC_TMEA_TMEA(0X5) ; +} + +/** + * @brief Get the Re-enable Test permission. + * */ +LOCAL_INLINE bool SEC_HWA_GetReEnTest(void) +{ + bool ret = false; + uint8_t tmea = (uint8_t)((SEC->TMEA & (SEC_TMEA_TMEA_MASK)) >> SEC_TMEA_TMEA_SHIFT); + if ((tmea == 0x5U) || (tmea == 0xFU)) + { + ret = true; + } + return ret; +} + +/* TMEK Bit Fields */ +/** + *@brief write Test re-enable mode key + * + */ +LOCAL_INLINE void SEC_HWA_ReEnTestKey(uint32_t testkey) +{ + SEC->TMEK = SEC_TMEK_TMEK(testkey) ; +} + +/* FCR0 Bit Fields */ +/** + * @brief Enable the Mass Erase + */ +LOCAL_INLINE void SEC_HWA_EnME(void) +{ + SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_MED_MASK)) | SEC_FCR0_MED(0x5)); +} + +/** + * @brief Enable the Block 0 NVR write . + */ +LOCAL_INLINE void SEC_HWA_EnWriteB0NVR(void) +{ + SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_NWP_MASK)) | SEC_FCR0_NWP(0x5)) ; +} + +/** + * @brief Disable the Block 0 NVR write . + */ +LOCAL_INLINE void SEC_HWA_DisWriteB0NVR(void) +{ + SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_NWP_MASK)) | SEC_FCR0_NWP(0xA)) ; +} + +/** + * @brief Enable the Block 0 NVR erase . + */ +LOCAL_INLINE void SEC_HWA_EnEraseB0NVR(void) +{ + SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_NEP_MASK)) | SEC_FCR0_NEP(0x5)) ; +} + +/** + * @brief Disable the Block 0 NVR erase . + */ +LOCAL_INLINE void SEC_HWA_DisEraseB0NVR(void) +{ + SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_NEP_MASK)) | SEC_FCR0_NEP(0xA)) ; +} + +/* NKRP Bit Fields */ +/** + * @brief NVR Key Read Protection. + * @brief Enable the Block 0 NVR read. + */ +LOCAL_INLINE void SEC_HWA_EnReadB0NVR(void) +{ + SEC->FCR0 = ((SEC->NKRP & (~SEC_NKRP_NKRP_MASK)) | SEC_NKRP_NKRP(0x5)) ; +} + +/** + * @brief Disable the Block 0 NVR read . + */ +LOCAL_INLINE void SEC_HWA_DisReadB0NVR(void) +{ + SEC->FCR0 = ((SEC->FCR0 & (~SEC_NKRP_NKRP_MASK)) | SEC_NKRP_NKRP(0xA)) ; +} + + +/* BCS Bit Fields */ +/** + * @brief Get the Fast Boot Select. + * @return 0b - Select PLL0 as the core clock source; the core clock is 300MHz + * 1b - Select FIRC as the core clock source; the core clock is 96MHz. + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetFastBootClock(void) +{ + return (uint8_t)((SEC->BCS & SEC_BCS_FBS_MASK) >> SEC_BCS_FBS_SHIFT); +} + +/** + * @brief NMI Function Enable/Disable + * @return false - NMI pin function is disabled after reset. + * true - NMI pin function is enabled + * */ +LOCAL_INLINE bool SEC_HWA_GetNmiPin(void) +{ + return (bool)((SEC->BCS & SEC_BCS_NMIDIS_MASK) >> SEC_BCS_NMIDIS_SHIFT); +} + +/** + * @brief ISP Function Enable/Disable ISP Mode Status + * @return false - ISP mode is inactive. + * true - ISP mode is active. + * */ +LOCAL_INLINE bool SEC_HWA_GetIspStatus(void) +{ + return (bool)((SEC->BCS & SEC_BCS_ISPMODE_MASK) >> SEC_BCS_ISPMODE_SHIFT); +} + +/** + * @brief Boot Rom Configuration + * @return false - Boot from GPR defined address (except ROM). + * true - Boot from ROM. + * */ +LOCAL_INLINE bool SEC_HWA_GetBootRom(void) +{ + return (bool)((SEC->BCS & SEC_BCS_BOOTROM_MASK) >> SEC_BCS_BOOTROM_SHIFT); +} + +/** + * @brief Get Chip Part Mode + * @return false - Chip is in FlexCore part mode. + * true - Chip is in HSM part mode. + * */ +LOCAL_INLINE bool SEC_HWA_GetPartMode(void) +{ + return (bool)((SEC->BCS & SEC_BCS_PART_MODE_MASK) >> SEC_BCS_PART_MODE_SHIFT); +} + +/** + * @brief Get PF_128BIT_MODE + * @return false - Chip is in FlexCore part mode. + * true - Chip is in HSM part mode. + * */ +LOCAL_INLINE bool SEC_HWA_GetPF128BitMode(void) +{ + return (bool)((SEC->BCS & SEC_BCS_PF_128BIT_MODE_MASK) >> SEC_BCS_PF_128BIT_MODE_SHIFT); +} + +/* UKAC Bit Fields */ + +/** + * @brief User Key Access Enable. Only valid under non-secure boot + * @return true means User key can be read/programmed/erased by host CPU ,false means User key is not available for host cpu + * */ +LOCAL_INLINE bool SEC_HWA_GetUKAS(void) +{ + bool ret = false; + uint8_t uake =(uint8_t)((SEC->UKAC & SEC_UKAC_UKAE_MASK) >> SEC_UKAC_UKAE_SHIFT); + if ((uake == 0x5U) || (uake == 0xFU)) + { + ret = true; + } + return ret; +} + +/* BRC0 Bit Fields */ +/** + * @brief Secure Boot Disable (Value loaded from NVR sector) + * @return true means Secure boot mode , false means Non secure boot mode. + */ +LOCAL_INLINE bool SEC_HWA_GetSB(void) +{ + bool ret = false; + uint8_t sbdis = (uint8_t)((SEC->BRC0 & SEC_BRC0_SECURE_BOOT_DIS_MASK) >> SEC_BRC0_SECURE_BOOT_DIS_SHIFT); + if (sbdis == 0x0u) + { + ret = true; + } + return ret; +} + +/** + * @brief Host Debug Auth Enable. Only valid in secure boot. (Value loaded from NVR sector) + * @return true means Host debug authentication enable. false means Host debug authentication disable. + */ +LOCAL_INLINE bool SEC_HWA_GetDEAUEn(void) +{ + bool ret = false; + uint8_t dean = (uint8_t)((SEC->BRC0 & SEC_BRC0_DEBUG_AUTH_EN_MASK) >> SEC_BRC0_DEBUG_AUTH_EN_SHIFT); + if ((dean == 0x5u) || (dean == 0xFu)) + { + ret = true; + } + return ret; +} + +/** + * @brief ISP Auth Enable. Only valid in secure boot. (Value loaded from NVR sector) + * @return true means ISP authentication enable, false means ISP authentication disable. + */ +LOCAL_INLINE bool SEC_HWA_GetISPAU(void) +{ + bool ret = false; + uint8_t isp = (uint8_t)((SEC->BRC0 & SEC_BRC0_ISP_AUTH_EN_MASK) >> SEC_BRC0_ISP_AUTH_EN_SHIFT); + if ((isp == 0x5u) || (isp == 0xFu)) + { + ret = true; + } + return ret; +} + +/* BRC1 Bit Fields */ +/** + * @brief Get the FCUART Baud Rate for ISP + * @return FCUART Baud Rate for ISP + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetUartBR(void) +{ + return (uint8_t)((SEC->BRC1 & SEC_BRC1_UARTBR_MASK) >> SEC_BRC1_UARTBR_SHIFT); +} + +/** + * @brief Get CAN Baud Rate for ISP + * @return CAN Baud Rate for ISP + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetCanBR(void) +{ + return (uint8_t)((SEC->BRC1 & SEC_BRC1_CANBR_MASK) >> SEC_BRC1_CANBR_SHIFT); +} + +/** + * @brief Get OSC Frequency + * @return OSC Frequency + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetOSCFre(void) +{ + return (uint8_t)((SEC->BRC1 & SEC_BRC1_OSCFREQ_MASK) >> SEC_BRC1_OSCFREQ_SHIFT); +} + +/** + * @brief Get whether OSC Available. + * @return true means OSC is available. false means -OSC is not available + * */ +LOCAL_INLINE bool SEC_HWA_GetOSCAvail(void) +{ + bool ret = false; + uint8_t osc = (uint8_t)((SEC->BRC1 & SEC_BRC1_OSCA_MASK) >> SEC_BRC1_OSCA_SHIFT); + if (osc == 0x0U) + { + ret = true; + } + return ret; +} + +/** + * @brief Get Debug Backdoor Key Input Enable. + * @return + * 0011b - User can input DBK through debug mailbox, ISP is not valid + * 1100b - User can input DBK through ISP, debug mailbox is not valid. + * 1111b - User can input DBK through both debug mailbox and ISP. + * Other Values - User cannot input DBK through both debug mailbox andISP + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetMBBKEN(void) +{ + return (uint32_t)((SEC->BRC1 & SEC_BRC1_DBK_IN_EN_MASK) >> SEC_BRC1_DBK_IN_EN_SHIFT); +} + +/** + * @brief Get Debug Backdoor Key Encryption Algorithm + * @return false-User code verification enable in non-secure boot mode + true- User code verification disable in non-secure boot mode. + * */ +LOCAL_INLINE bool SEC_HWA_GetNonSecVerifEN(void) +{ + bool ret = false; + uint8_t dean = (uint8_t)((SEC->BRC0 & SEC_BRC1_NON_SEC_VERIF_EN_MASK) >> SEC_BRC1_NON_SEC_VERIF_EN_SHIFT); + if (dean == 1u) + { + ret = true; + } + return ret; +} + +/** + * @brief Get User Code Verification Enable under Non-secure Boot Mode + * @return Bootloader Verification Algorithm + * 000b - AES256-CBC + * 111b - SM4-CBC. + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetDBDkeyEncrypAlg(void) +{ + return (uint8_t)((SEC->BRC1 & SEC_BRC1_DBKEA_MASK) >> SEC_BRC1_DBKEA_SHIFT); +} + +/** + * @brief ISP Function Enable/Disable，Only valid in non-secure mode + * @return false - ISP pin function is disabled after reset. + * true - ISP pin function is enabled. + * */ +LOCAL_INLINE bool SEC_HWA_GetIspEn(void) +{ + return (bool)((SEC->BRC1 & SEC_BRC1_ISP_PIN_EN_MASK) >> SEC_BRC1_ISP_PIN_EN_SHIFT); +} + +/** + * @brief GET ISP Mode whether Allowed in Recovery Mode + * @return false - ISP mode is not allowed in recovery mode + * true - ISP mode is allowed in recovery mode. + * */ +LOCAL_INLINE bool SEC_HWA_GetIspIsAllowedInRec(void) +{ + return (bool)((SEC->BRC1 & SEC_BRC1_ISPAIRM_MASK) >> SEC_BRC1_ISPAIRM_SHIFT); +} + +/** + * @brief GET Enable the Output of Plaintext Decrypted ROOT Key + * @return false - The output of plaintext decrypted ROOT key is enabled + * true - The output of plaintext decrypted ROOT key is disabled. + * */ +LOCAL_INLINE bool SEC_HWA_GetKeyPlaRoot(void) +{ + return (bool)((SEC->BRC1 & SEC_BRC1_KEY_PROT_MASK) >> SEC_BRC1_KEY_PROT_SHIFT); +} + +/** + * @brief Get ROM Loop Control Flag + * @return false - ROM executes normal run under VIRGIN and FT state. + * true - ROM enters debug loop under VIRGIN and FT state. + * */ +LOCAL_INLINE bool SEC_HWA_GetLoopCtrFlag(void) +{ + return (bool)((SEC->BRC1 & SEC_BRC1_ROM_LOOP_CTRL_MASK) >> SEC_BRC1_ROM_LOOP_CTRL_SHIFT); +} + +/** + * @brief Get Enable Software Configuration to Enter ISP + * @return false - Software configuration to enter ISP is enabled. + * true - Software configuration to enter ISP is disabled. + * */ +LOCAL_INLINE bool SEC_HWA_GetIspSoftConfig(void) +{ + return (bool)((SEC->BRC1 & SEC_BRC1_SW_CFG_ISP_EN_MASK) >> SEC_BRC1_SW_CFG_ISP_EN_SHIFT); +} + + +/* SW_CFG_ISP_FLG Bit Fields */ +/** + * @brief Software Configuration to Enter ISP Flag + * @return ISP Flag. + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetSwCfgIspFlg(void) +{ + return (uint8_t)((SEC->SW_CFG_ISP_FLG & SEC_SW_CFG_ISP_FLG_SW_CFG_ISP_FLG_MASK) >> SEC_SW_CFG_ISP_FLG_SW_CFG_ISP_FLG_SHIFT); +} + + +/* BRC2 Bit Fields */ +/** + * @brief Get USERCODE_VERIFY_MASK_MASK + * @return USERCODE_VERIFY_MASK_MASK. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetBLMask(void) +{ + return (uint32_t)((SEC->BRC2 & SEC_BRC2_USERCODE_VERIFY_MASK_MASK) >> SEC_BRC2_USERCODE_VERIFY_MASK_SHIFT); +} + +/** + * @brief Get the ISP Instance Select. + * @return ISP Instance Select + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetIspIns(void) +{ + return (uint8_t)((SEC->BRC2 & SEC_BRC2_ISP_INST_SEL_MASK) >> SEC_BRC2_ISP_INST_SEL_SHIFT); +} + +/** + * @brief Get Bootloader Verification Algorithm + * @return Bootloader Verification Algorithm + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetBLVer(void) +{ + return (uint8_t)((SEC->BRC2 & SEC_BRC2_USERCODE_VERIFICATION_ALG_MASK) >> SEC_BRC2_USERCODE_VERIFICATION_ALG_SHIFT); +} + +/** + * @brief Get Debug/ISP/PREFA Authentication and USRK decryption algorithm + * @return 1b - SM2, 0b - ECC256 + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetDecrypt(void) +{ + return (uint8_t)((SEC->BRC2 & SEC_BRC2_DECRP_ALG_MASK) >> SEC_BRC2_DECRP_ALG_SHIFT); +} + +/* IMAGEA Bit Fields */ +/** + * @brief Get the bootloader address. + * @return Bootloader Address. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetBLAddr(void) +{ + return (uint32_t)((SEC->IMGEA & SEC_IMGEA_IMAGE_ADDR_MASK) >> SEC_IMGEA_IMAGE_ADDR_SHIFT); +} + + +/* NVR VER Bit Fields */ +/** + * @brief Get C version. + * @return C version. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetCVer(void) +{ + return (uint32_t)((SEC->NVR_VER & SEC_NVR_VER_C_VER_MASK) >> SEC_NVR_VER_C_VER_SHIFT); +} + +/** + * @brief Set C version. + * @return C version. + * */ +LOCAL_INLINE void SEC_HWA_SetCVer(uint32_t C_Ver) +{ + SEC->NVR_VER=((SEC->NVR_VER & (~SEC_NVR_VER_C_VER_MASK)) | SEC_NVR_VER_C_VER(C_Ver)); +} + +/** + * @brief Get R version. + * @return R version. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetRVer(void) +{ + return (uint32_t)((SEC->NVR_VER & SEC_NVR_VER_R_VER_MASK) >> SEC_NVR_VER_R_VER_SHIFT); +} + +/** + * @brief Set R version. + * */ +LOCAL_INLINE void SEC_HWA_SetRVer(uint32_t R_Ver) +{ + SEC->NVR_VER=((SEC->NVR_VER & (~SEC_NVR_VER_R_VER_MASK)) | SEC_NVR_VER_R_VER(R_Ver)); +} + +/** + * @brief Get V version. + * @return V version. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetVVer(void) +{ + return (uint32_t)((SEC->NVR_VER & SEC_NVR_VER_V_VER_MASK) >> SEC_NVR_VER_V_VER_SHIFT); +} + +/** + * @brief Set V version. + * */ +LOCAL_INLINE void SEC_HWA_SetVVer(uint32_t V_Ver) +{ + SEC->NVR_VER=((SEC->NVR_VER & (~SEC_NVR_VER_V_VER_MASK)) | SEC_NVR_VER_V_VER(V_Ver)); +} + +/** + * @brief Get CHIP version. + * @return CHIP version. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetChipVer(void) +{ + return (uint32_t)((SEC->NVR_VER & SEC_NVR_VER_CHIP_VER_MASK) >> SEC_NVR_VER_CHIP_VER_SHIFT); +} + +/** + * @brief Set CHIP version. + * */ +LOCAL_INLINE void SEC_HWA_SetChipVer(uint32_t CHIP_Ver) +{ + SEC->NVR_VER=((SEC->NVR_VER & (~SEC_NVR_VER_CHIP_VER_MASK)) | SEC_NVR_VER_V_VER(CHIP_Ver)); +} + +/* LCSTAT Bit Fields */ +/** + * @brief Get the life cycle status of the chip. + * @return The lifecycle status + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetLCStaus(void) +{ + return (uint8_t)(SEC->LCSTAT & 0XFFU); +} + +/** + * @brief Get Lifecycle OEM Development + * @return 0b - Chip is not in this lifecycle + * 1b - Chip is in this lifecycle + * */ +LOCAL_INLINE bool SEC_HWA_GetLCOemDev(void) +{ + return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_OEM_DEV_MASK) >> SEC_LCSTAT_LIFECYCLE_OEM_DEV_SHIFT); +} + +/** + * @brief Get Lifecycle OEM Production + * @return false - Chip is not in this lifecycle + * true - Chip is in this lifecycle + * */ +LOCAL_INLINE bool SEC_HWA_GetLCOemPdt(void) +{ + return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_OEM_PDT_MASK) >> SEC_LCSTAT_LIFECYCLE_OEM_PDT_SHIFT); +} + +/** + * @brief Get Lifecycle In Field + * @return false - Chip is not in this lifecycle + * true - Chip is in this lifecycle + * */ +LOCAL_INLINE bool SEC_HWA_GetLCInField(void) +{ + return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_IN_FIELD_MASK) >> SEC_LCSTAT_LIFECYCLE_IN_FIELD_SHIFT); +} + +/** + * @brief Get Lifecycle Software Fault Analysis + * @return false - Chip is not in this lifecycle + * true - Chip is in this lifecycle + * */ +LOCAL_INLINE bool SEC_HWA_GetLCSwFa(void) +{ + return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_SWFA_MASK) >> SEC_LCSTAT_LIFECYCLE_SWFA_SHIFT); +} + +/** + * @brief Get Lifecycle Hardware Fault Analysis + * @return false - Chip is not in this lifecycle + * true - Chip is in this lifecycle + * */ +LOCAL_INLINE bool SEC_HWA_GetLCHwFa(void) +{ + return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_HWFA_MASK) >> SEC_LCSTAT_LIFECYCLE_HWFA_SHIFT); +} + +/* FAC Bit Fields */ +/** + * @brief Get the Host User Key Read Protection + * @return true - Host read access to User Key region is enabled + * false - Host read access to User Key region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHUKRead(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_UKEY_RPROT_MASK) >> SEC_FAC_HOST_UKEY_RPROT_SHIFT)); +} + +/** + * @brief Get the Host User Key write Protection + * @return true - Host write access to User Key region is enabled + * false - Host write access to User Key region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHUKWrite(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_UKEY_WPROT_MASK) >> SEC_FAC_HOST_UKEY_WPROT_SHIFT)); +} + +/** + * @brief Get the Host User Key erase Protection + * @return true - Host erase access to User Key region is enabled + * false - Host erase access to User Key region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHUKErase(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_UKEY_EPROT_MASK) >> SEC_FAC_HOST_UKEY_EPROT_SHIFT)); +} + +/** + * @brief Get the Host NVR Read Protection + * @return true - Host read access to NVR region is enabled + * false - Host read access to NVR region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHostNvrRead(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_NVR_RPROT_MASK) >> SEC_FAC_HOST_NVR_RPROT_SHIFT)); +} + +/** + * @brief Get the Host NVR write Protection + * @return true - Host write access to NVR region is enabled + * false - Host write access to NVR region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHostNvrWrite(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_NVR_WPROT_MASK) >> SEC_FAC_HOST_NVR_WPROT_SHIFT)); +} + +/** + * @brief Get the Host NVR erase Protection + * @return true - Host erase access to NVR region is enabled + * false - Host erase access to NVR region is disabled- + * */ +LOCAL_INLINE bool SEC_HWA_GetHostNvrErase(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_NVR_EPROT_MASK) >> SEC_FAC_HOST_NVR_EPROT_SHIFT)); +} + +/** + * @brief Get HSM User Key Read Protection + * @return true - HSM Read access to User Key region is disabled + * false - HSM Read access to User Key region is enabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmUKRead(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_UKEY_RPROT_MASK) >> SEC_FAC_HSM_UKEY_RPROT_SHIFT)); +} + +/** + * @brief Get HSM User Key Program Protection + * @return true - HSM Program access to User Key region is disabled + * false - HSM Program access to User Key region is enabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmUKProg(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_UKEY_WPROT_MASK) >> SEC_FAC_HSM_UKEY_WPROT_SHIFT)); +} + +/** + * @brief Get the HSM User Key Erase Protection + * @return true - HSM erase access to User Key region is enabled + * false -HSM erase access to User Key region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmUKErase(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_UKEY_EPROT_MASK) >> SEC_FAC_HSM_UKEY_EPROT_SHIFT)); +} + +/** + * @brief Get HSM NVR Key Read Protection + * @return true - HSM Read access to NVR key region is disabled + * false - HSM Read access to NVR key region is enabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmNvrKRead(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_NVR_RPROT_MASK) >> SEC_FAC_HSM_NVR_RPROT_SHIFT)); +} + +/** + * @brief Get HSM NVR Program Protection + * @return true - HSM Program access to NVR region is disabled + * false - HSM Program access to NVR region is enabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmNvrProg(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_NVR_WPROT_MASK) >> SEC_FAC_HSM_NVR_WPROT_SHIFT)); +} + +/** + * @brief Get the HSM NVR Erase Protection + * @return true - HSM erase access to NVR region is enabled + * false -HSM erase access to NVR region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmNvrErase(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_NVR_EPROT_MASK) >> SEC_FAC_HSM_NVR_EPROT_SHIFT)); +} + +/* FLEXCORE_EN Bit Fields */ +/** + * @brief Get the FlexCore Enable. + * @return true means enable ,false means disable. + * */ +LOCAL_INLINE bool SEC_HWA_GetFlexCoreEn(void)//? +{ + bool ret = false; + uint8_t srk = (uint8_t)((SEC->FLEXCORE_EN & SEC_FLEXCORE_EN_FLEXCORE_EN_MASK) >> SEC_FLEXCORE_EN_FLEXCORE_EN_SHIFT); + if (srk == 0xFU||srk == 0x5U) + { + ret = true; + } + return ret; +} +/** + * @brief Set the FlexCore Enable. + * @return true means set sucess ,false means set fail,0x5 and 0xf is enable,others is disable. + * */ +LOCAL_INLINE bool SEC_HWA_SetFlexCoreEn(uint8_t CoreEn) +{ + if(CoreEn>0xF) + return false; + SEC->FLEXCORE_EN = ((SEC->FLEXCORE_EN & (~SEC_FLEXCORE_EN_FLEXCORE_EN_MASK)) | SEC_FLEXCORE_EN_FLEXCORE_EN(CoreEn)); + return true; +} + +/** + * @brief Get SEC_FLEXCORE_EN FLEXCORE_DBG. + * @return true means enable ,false means disable. + * */ +LOCAL_INLINE bool SEC_HWA_GetFlexCoreDbgEn(void) +{ + return (bool)((SEC->FLEXCORE_EN & SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_MASK) >> SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_SHIFT); +} + +/** + * @brief Set SEC_FLEXCORE_EN FLEXCORE_DBG. + * */ +LOCAL_INLINE void SEC_HWA_SetFlexCoreDbgEn(uint8_t DbgEn) +{ + SEC->FLEXCORE_EN=((SEC->FLEXCORE_EN & (~SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_MASK)) | SEC_FLEXCORE_EN_FLEXCORE_DBG_EN(DbgEn)); +} + +/* FLEX_CODE_ADDR Bit Fields */ +/** + * @brief Get Code Header Address for FlexCore Always 4-byte aligned + * @return FLEX Code Header Address. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetFlexCodeHeadAddr(void) +{ + return (uint32_t)((SEC->FLEX_CODE_ADDR & SEC_FLEX_CODE_ADDR_FLEX_CODE_ADDR_MASK) >> SEC_FLEX_CODE_ADDR_FLEX_CODE_ADDR_SHIFT); +} + +/* PFLASH_PRLLL_EN Bit Fields */ +/** + * @brief Get PFLASH Parallel Enable + * @return + * 0101b - Disable + * Others - Enable + * */ +LOCAL_INLINE bool SEC_HWA_GetPflashPrlllEn(void) +{ + bool ret = false; + uint32_t srk=(uint32_t)((SEC->PFLASH_PRLLL_EN & SEC_PFLASH_PRLLL_EN_PFLASH_PRLLL_EN_MASK) >> SEC_PFLASH_PRLLL_EN_PFLASH_PRLLL_EN_SHIFT); + if (srk !=0x5U) + { + ret =true ; + } + return ret; +} + +/** @}*/ /* HwA_SEC */ +#endif /* HWA_INCLUDE_HWA_SEC_H_ */ diff --git a/Inc/HwA_sent.h b/Inc/HwA_sent.h new file mode 100644 index 0000000..9b2efa4 --- /dev/null +++ b/Inc/HwA_sent.h @@ -0,0 +1,1454 @@ +/** + * @file HwA_sent.h + * @author Flagchip073 + * @brief Hardware access layer for SENT + * @version 0.0.1 + * @date 2022-12-14 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.0.1 2022-12-14 Flagchip073 N/A First version for FC7300 SENT + ******************************************************************************** */ + +#ifndef _HWA_SENT_H_ +#define _HWA_SENT_H_ + +#include "device_header.h" + +#define DMA_CH_TO_DCHPRI(x) ((x) ^ 3U) + +/** + * @defgroup HwA_sent + * @ingroup fc7xxx_driver_sent + * @{ + */ + +/** + * @brief sent running status + * + */ +typedef enum +{ + SENT_NIBBLE_DATA_MODE_A = 0x0U, /*!< Frame format A */ + SENT_NIBBLE_DATA_MODE_H1 = 0x1U, /*!< Frame format H1 */ + SENT_NIBBLE_DATA_MODE_H2 = 0x2U, /*!< Frame format H2 */ + SENT_NIBBLE_DATA_MODE_H3 = 0x3U, /*!< Frame format H3 */ + SENT_NIBBLE_DATA_MODE_H4 = 0x4U, /*!< Frame format H4 */ + SENT_NIBBLE_DATA_MODE_H5 = 0x5U, /*!< Frame format H5 */ + SENT_NIBBLE_DATA_MODE_H6 = 0x6U, /*!< Frame format H6 */ + SENT_NIBBLE_DATA_MODE_H7 = 0x7U /*!< Frame format H7 */ +} SENT_NibbleDataModeType; + +/** + * @brief sent slow message type + * + */ +typedef enum +{ + SENT_SLOW_MESSAGE_SHORT = 0x0U, /*!< short serial data message */ + SENT_SLOW_MESSAGE_ENHANCE_12DATA_8ID = 0x1U, /*!< enhanced serial data message with 12-bit data and 8-bit ID */ + SENT_SLOW_MESSAGE_ENHANCE_16DATA_4ID = 0x2U, /*!< enhanced serial data message with 16-bit data and 4-bit ID */ +} SENT_SlowMessageType; + +/** + * @brief sent SPC trigger type + * + */ +typedef enum +{ + SENT_SPC_SW_TRIGGER = 0x0U, /*!< SPC pulse triggered by software method */ + SENT_SPC_HW_TRIGGER = 0x1U, /*!< SPC pulse triggered by external trigger */ +} SENT_SPCTriggerType; + +/** + * @brief sent SPC tick base + * + */ +typedef enum +{ + SENT_SPC_TICK_PRE_RECEIVED_MESSAGE = 0x0U, /*!< Previous received message tick base */ + SENT_SPC_TICK_CONFIG = 0x1U, /*!< SENT configured tick base */ +} SENT_SPCTickType; + +/** + * @brief Set SENT Global pre-scaler value + * + * @param pSent the base address of the SENT instance + * @param u8PreScaler the value of the PreSclaer. + */ +LOCAL_INLINE void SENT_HWA_SetGlobalPreScaler(SENT_Type *const pSent, uint8_t u8PreScaler) +{ + pSent->GLBL_CTL = (pSent->GLBL_CTL & ~SENT_GLBL_CTL_PRE_SCALER_MASK) | SENT_GLBL_CTL_PRE_SCALER(u8PreScaler); +} + +/** + * @brief Set SENT Global DMA watermark value + * + * @param pSent the base address of the SENT instance + * @param u8WaterMark the value of the dma watermark. + */ +LOCAL_INLINE void SENT_HWA_SetDMAWaterMark(SENT_Type *const pSent, uint8_t u8WaterMark) +{ + pSent->GLBL_CTL = (pSent->GLBL_CTL & ~SENT_GLBL_CTL_DMA_WATERMARK_MASK) | SENT_GLBL_CTL_DMA_WATERMARK(u8WaterMark); +} + +/** + * @brief Enable SENT Fast message FIFO overflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableFastMessageFIFOOverflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_F_FIFO_OVFL_IE_MASK; +} + +/** + * @brief Disable SENT Fast message FIFO overflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableFastMessageFIFOOverflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_F_FIFO_OVFL_IE_MASK; +} + +/** + * @brief Enable SENT Fast message read underflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableFastMessagedmaReadUnderflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_F_DMA_UDFL_IE_MASK; +} + +/** + * @brief Disable SENT Fast message read underflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableFastMessagedmaReadUnderflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_F_DMA_UDFL_IE_MASK; +} + +/** + * @brief Enable SENT slow message read underflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableSlowMessagedmaReadUnderflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_S_DMA_UDFL_IE_MASK; +} + +/** + * @brief Disable SENT slow message read underflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableSlowMessagedmaReadUnderflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_S_DMA_UDFL_IE_MASK; +} + +/** + * @brief Enable SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableDebugMode(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_DBG_EN_MASK; +} + +/** + * @brief Disable SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableDebugMode(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_DBG_EN_MASK; +} + +/** + * @brief Enable Global SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableGlobal(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_SENT_EN_MASK; +} + +/** + * @brief Disable Global SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableGlobal(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_SENT_EN_MASK; +} + +/** + * @brief Enable Global SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableDataOverflowFlagFastClear(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_FAST_CLR_MASK; +} + +/** + * @brief Disable Global SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableDataOverflowFlagFastClear(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_FAST_CLR_MASK; +} + +/** + * @brief Enable SENT channel receive + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelReceive(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->CHN_EN |= SENT_CHN_EN_CHN_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel receive + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelReceive(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->CHN_EN &= ~SENT_CHN_EN_CHN_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Get SENT channel receive + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE bool SENT_HWA_GetChannelReceive(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_CHN_EN_CHN_EN((uint32_t)1u << u8Channel) == (pSent->CHN_EN & SENT_CHN_EN_CHN_EN((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Get Channel slow message dma read underflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel slow message dma is underflow + */ +LOCAL_INLINE bool SENT_HWA_GetSLowMessageUnderflowFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(((uint32_t)1u << u8Channel) == (pSent->GLBL_STAT & SENT_GLBL_STAT_S_DMA_UDFL((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel slow message dma read underflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearSLowMessageUnderflowFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->GLBL_STAT |= SENT_GLBL_STAT_S_DMA_UDFL((uint32_t)1u << u8Channel); +} + +/** + * @brief Get Channel fast message ready flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel fast message is ready + */ +LOCAL_INLINE bool SENT_HWA_GetFastMessageReadyFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_FMSG_STAT_F_MSG_RDY((uint32_t)1u << u8Channel) == (pSent->FMSG_STAT & SENT_FMSG_STAT_F_MSG_RDY((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel fast message ready flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearFastMessageReadyFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FMSG_STAT |= SENT_FMSG_STAT_F_MSG_RDY((uint32_t)1u << u8Channel); +} + +/** + * @brief Get Channel slow message ready flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel slow message is ready + */ +LOCAL_INLINE bool SENT_HWA_GetSlowMessageReadyFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(((uint32_t)1u << u8Channel) == (pSent->SMSG_STAT & ((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel slow message ready flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearSlowMessageReadyFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SMSG_STAT |= SENT_FMSG_STAT_F_MSG_RDY((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel FIFO function + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFIFO(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FIFO_EN |= SENT_FIFO_EN_FIFO_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel receive function + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFIFO(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FIFO_EN &= ~SENT_FIFO_EN_FIFO_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Set SENT channel data nibble number + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u8Number the received data number + */ +LOCAL_INLINE void SENT_HWA_SetChannelNibbleNumber(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Number) +{ + pSent->DATA_NUM_CTL1 = (pSent->DATA_NUM_CTL1 & ~(SENT_DATA_NUM_CTL1_CH0_DATA_CTL_MASK >> (4u * u8Channel))) | (SENT_DATA_NUM_CTL1_CH0_DATA_CTL(u8Number) >> (4u * u8Channel)); +} + +/** + * @brief Get SENT channel data nibble number + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param uint8_t the config data number + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelNibbleNumber(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->DATA_NUM_CTL1 & (SENT_DATA_NUM_CTL1_CH0_DATA_CTL_MASK >> (4u * u8Channel))) >> (SENT_DATA_NUM_CTL1_CH0_DATA_CTL_SHIFT - (4u * u8Channel))); +} + +/** + * @brief Get Channel fast message FIFO overflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel fast message FIFO is overflow + */ +LOCAL_INLINE bool SENT_HWA_GetFastMessageFIFOOverflowFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_OVFL_UDFL_STAT_FIFO_F_OVFL_FLAG((uint32_t)1u << u8Channel) == (pSent->OVFL_UDFL_STAT & SENT_OVFL_UDFL_STAT_FIFO_F_OVFL_FLAG((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel fast message FIFO overflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearFastMessageFIFOOverflowFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->OVFL_UDFL_STAT |= SENT_OVFL_UDFL_STAT_FIFO_F_OVFL_FLAG((uint32_t)1u << u8Channel); +} + +/** + * @brief Get Channel fast message DMA underflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel fast message DMA read is underflow + */ +LOCAL_INLINE bool SENT_HWA_GetFastMessageDMAUnderflowFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_OVFL_UDFL_STAT_DMA_F_UDFL_FLAG((uint32_t)1u << u8Channel) == (pSent->OVFL_UDFL_STAT & SENT_OVFL_UDFL_STAT_DMA_F_UDFL_FLAG((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel fast message DMA underflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearFastMessageDMAUnderflowFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->OVFL_UDFL_STAT |= SENT_OVFL_UDFL_STAT_DMA_F_UDFL_FLAG((uint32_t)1u << u8Channel); +} + +/** + * @brief Set SENT channel nibble data mode + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param eMode the nibble data mode + */ +LOCAL_INLINE void SENT_HWA_SetChannelNibbleDataMode(SENT_Type *const pSent, uint8_t u8Channel, SENT_NibbleDataModeType eMode) +{ + pSent->NB_MODE1 = (pSent->NB_MODE1 & ~(SENT_NB_MODE1_CH0_NB_MODE_MASK >> (4u * u8Channel))) | (SENT_NB_MODE1_CH0_NB_MODE(eMode) >> (4u * u8Channel)); +} + +/** + * @brief Enable SENT channel fast message DMA request + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageDmaRequest(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FDMA_CTL |= SENT_FDMA_CTL_FDMA_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel fast message DMA request + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageDmaRequest(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FDMA_CTL &= ~SENT_FDMA_CTL_FDMA_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel slow message DMA request + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSlowMessageDmaRequest(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SDMA_CTL |= SENT_SDMA_CTL_SDMA_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel slow message DMA request + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSlowMessageDmaRequest(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SDMA_CTL &= ~SENT_SDMA_CTL_SDMA_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel Fast message interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FINT_CTL |= SENT_FINT_CTL_FINT_CTL((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel Fast message interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FINT_CTL &= ~SENT_FINT_CTL_FINT_CTL((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel slow message interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSlowMessageInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SINT_CTL |= SENT_SINT_CTL_SINT_CTL((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel slow message interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSlowMessageInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SINT_CTL &= ~SENT_SINT_CTL_SINT_CTL((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel Compensate + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCompensate(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CLK_CTL |= SENT_CHN_CLK_CTL_COMP_EN_MASK; +} + +/** + * @brief Disable SENT channel Compensate + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelCompensate(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CLK_CTL &= ~SENT_CHN_CLK_CTL_COMP_EN_MASK; +} + +/** + * @brief Set SENT channel pre-scaler + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u16PreScaler the related Channel Prescaler value + */ +LOCAL_INLINE void SENT_HWA_SetChannelPreScaler(SENT_Type *const pSent, uint8_t u8Channel, uint16_t u16PreScaler) +{ + pSent->SENT_CHN[u8Channel].CHN_CLK_CTL = (pSent->SENT_CHN[u8Channel].CHN_CLK_CTL & ~SENT_CHN_CLK_CTL_PRE_SCALER_MASK) | SENT_CHN_CLK_CTL_PRE_SCALER(u16PreScaler); +} + +/** + * @brief Get Channel Prescaler value after compensate + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return uint8_t the related Channel Prescaler value after compensate + */ +LOCAL_INLINE uint16_t SENT_HWA_GetChannelCompensatePreScaler(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint16_t)((pSent->SENT_CHN[u8Channel].CHN_CLK_CTL & SENT_CHN_CLK_CTL_COMPED_PRE_SCALER_MASK) >> SENT_CHN_CLK_CTL_COMPED_PRE_SCALER_SHIFT); +} + +/** + * @brief Get Channel status + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return uint32_t the related Channel status + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChannelStatus(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return pSent->SENT_CHN[u8Channel].CHN_STAT; +} + +/** + * @brief Clear Channel status + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u32W1CBit the status bits need to be clear. + */ +LOCAL_INLINE void SENT_HWA_ClearChannelStatus(SENT_Type *const pSent, uint8_t u8Channel, uint32_t u32W1CBit) +{ + pSent->SENT_CHN[u8Channel].CHN_STAT |= u32W1CBit; +} + +/** + * @brief Enable SENT channel all error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelAllErrorInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= (SENT_CHN_CTL_CAL_RESYNC_IE_MASK | SENT_CHN_CTL_CAL_20_25_IE_MASK | SENT_CHN_CTL_SMSG_OVFL_IE_MASK | \ + SENT_CHN_CTL_FMSG_OVFL_IE_MASK | SENT_CHN_CTL_PP_DIAG_ERR_IE_MASK | SENT_CHN_CTL_CAL_DIAG_ERR_IE_MASK | \ + SENT_CHN_CTL_CAL_ERR_IE_MASK | SENT_CHN_CTL_NIB_ERR_IE_MASK | SENT_CHN_CTL_S_CRC_ERR_IE_MASK | \ + SENT_CHN_CTL_F_CRC_ERR_IE_MASK | SENT_CHN_CTL_EDGE_ERR_IE_MASK | SENT_CHN_CTL_SPC_OVERRUN_IE_MASK); +} + +/** + * @brief Disable SENT channel all error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelAllErrorInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~(SENT_CHN_CTL_CAL_RESYNC_IE_MASK | SENT_CHN_CTL_CAL_20_25_IE_MASK | SENT_CHN_CTL_SMSG_OVFL_IE_MASK | \ + SENT_CHN_CTL_FMSG_OVFL_IE_MASK | SENT_CHN_CTL_PP_DIAG_ERR_IE_MASK | SENT_CHN_CTL_CAL_DIAG_ERR_IE_MASK | \ + SENT_CHN_CTL_CAL_ERR_IE_MASK | SENT_CHN_CTL_NIB_ERR_IE_MASK | SENT_CHN_CTL_S_CRC_ERR_IE_MASK | \ + SENT_CHN_CTL_F_CRC_ERR_IE_MASK | SENT_CHN_CTL_EDGE_ERR_IE_MASK | SENT_CHN_CTL_SPC_OVERRUN_IE_MASK); +} + +/** + * @brief Enable/disable SENT channel idle flag interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelBusIdleInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_BUS_IDLE_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_BUS_IDLE_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel sync/calibration pulse error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalResyncInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_RESYNC_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_RESYNC_IE_MASK; + } +} + +/** + * @brief Enable/disable Sync/calibration pulse difference eceed 1.5625% error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalERRInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Calibration 20% pass 25% fail interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalFailInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_20_25_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_20_25_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Slow message overflow interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSOVFLInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_SMSG_OVFL_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_SMSG_OVFL_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel fast message overflow interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFOVFLInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_FMSG_OVFL_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_FMSG_OVFL_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Nibble value error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelNibbleErrorInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_NIB_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_NIB_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Previous pulse diagnosis error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelPPDiagInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_PP_DIAG_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_PP_DIAG_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Calibration diagnosis over 25% error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCALDiagInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_DIAG_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_DIAG_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel SPC overrun error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSPCOverRunInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_SPC_OVERRUN_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_SPC_OVERRUN_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Fast message CRC check error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFCRCInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_F_CRC_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_F_CRC_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel slow message CRC check error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSCRCInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_S_CRC_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_S_CRC_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Falling edge number error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelEdgeERRInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_EDGE_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_EDGE_ERR_IE_MASK; + } +} + +/** + * @brief Enable SENT channel Alternative 4-bit CRC algorithm + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelAltCRC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_ALT_4BIT_CRC_MASK; +} + +/** + * @brief Disable SENT channel Alternative 4-bit CRC algorithm + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelAltCRC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_ALT_4BIT_CRC_MASK; +} + +/** + * @brief Enable SENT channel Fast message data change + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageDataChange(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_DATA_CHANGE_EN_MASK; +} + +/** + * @brief Disable SENT channel Fast message data change + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageDataChange(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_DATA_CHANGE_EN_MASK; +} + +/** + * @brief Enable SENT channel calibration valid range from 20% tp 25% + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalValid20To25(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_SEL_MASK; +} + +/** + * @brief Disable SENT channel calibration valid range from 20% tp 25% + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelCalValid20To25(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_SEL_MASK; +} + +/** + * @brief Enable SENT channel calibration valid diagnostic + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalValidDiagnostic(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_PP_CHK_DIS_MASK; +} + +/** + * @brief Disable SENT channel calibration valid diagnostic + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelCalValidDiagnostic(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_PP_CHK_DIS_MASK; +} + +/** + * @brief Enable SENT channel fast message CRC with Augmentation + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageAugmentation(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_FCRC_SEL_MASK; +} + +/** + * @brief Disable SENT channel fast message CRC with Augmentation + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageAugmentation(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_FCRC_SEL_MASK; +} + +/** + * @brief Enable SENT channel Fast message crc with S&C + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageCRCWithSC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_FCRC_SC_EN_MASK; +} + +/** + * @brief Disable SENT channel Fast message crc with S&C + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageCRCWithSC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_FCRC_SC_EN_MASK; +} + +/** + * @brief Enable SENT channel slow message CRC with Augmentation + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSlowMessageAugmentation(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_SCRC_SEL_MASK; +} + +/** + * @brief Disable SENT channel slow message CRC with Augmentation + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSlowMessageAugmentation(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_SCRC_SEL_MASK; +} + +/** + * @brief Enable SENT channel Pause pulse + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelPausePulse(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_PAUSE_DET_EN_MASK; +} + +/** + * @brief Disable SENT channel Successive calibration pulses diagnostic option1 + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelPausePulse(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_PAUSE_DET_EN_MASK; +} + +/** + * @brief Enable SENT channel Successive calibration pulses diagnostic option1 + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSPCOption1(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_SCP_CHK_MASK; +} + +/** + * @brief Disable SENT channel Pause pulse + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSPCOption1(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_SCP_CHK_MASK; +} + +/** + * @brief Enable SENT channel Fast message crc check + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageCRCCheck(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_FMSG_CRC_CHECK_OFF_MASK; +} + +/** + * @brief Disable SENT channel Fast message crc check + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageCRCCheck(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_FMSG_CRC_CHECK_OFF_MASK; +} + +/** + * @brief Set SENT channel digital filter count + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u8Count the count of channel digital filter + */ +LOCAL_INLINE void SENT_HWA_SetChannelDigitalFilterCount(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Count) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL = (pSent->SENT_CHN[u8Channel].CHN_CTL & ~SENT_CHN_CTL_FILT_CNT_MASK) | SENT_CHN_CTL_FILT_CNT(u8Count); +} + +/** + * @brief Get Channel fast message data nibble + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the corresponding channel data nibble value + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChannelDataNibble(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return pSent->SENT_CHN[u8Channel].CHN_FDATA; +} + +/** + * @brief Get Channel fast message crc nibble + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel crc nibble value + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelFastMessageCRCNibble(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_FCRC & SENT_CHN_FCRC_CRC_DATA_MASK) >> SENT_CHN_FCRC_CRC_DATA_SHIFT); +} + +/** + * @brief Get Channel fast message status communication nibble + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel status communication nibble value + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelFastMessageStatusNibble(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_FCRC & SENT_CHN_FCRC_SC_NB_MASK) >> SENT_CHN_FCRC_SC_NB_SHIFT); +} + +/** + * @brief Get Channel fast message status timestamp + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the corresponding channel timestamp value + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChannelFastMessageTimeStamp(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return ((pSent->SENT_CHN[u8Channel].CHN_FTS & SENT_CHN_FTS_TIMESTAMP_VAL_MASK) >> SENT_CHN_FTS_TIMESTAMP_VAL_SHIFT); +} + +/** + * @brief Get Channel slow message type + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return SENT_SlowMessageType the corresponding channel slow message type + */ +LOCAL_INLINE SENT_SlowMessageType SENT_HWA_GetChannelSLowMessageType(const SENT_Type *const pSent, uint8_t u8Channel) +{ + SENT_SlowMessageType eRet = SENT_SLOW_MESSAGE_SHORT; + + if(SENT_CHN_SBIT3__MSG_TYPE_MASK == (pSent->SENT_CHN[u8Channel].CHN_SBIT3 & SENT_CHN_SBIT3__MSG_TYPE_MASK)) + { + if(SENT_CHN_SBIT3__CFG_MASK == (pSent->SENT_CHN[u8Channel].CHN_SBIT3 & SENT_CHN_SBIT3__CFG_MASK)) + { + eRet = SENT_SLOW_MESSAGE_ENHANCE_16DATA_4ID; + } + else + { + eRet = SENT_SLOW_MESSAGE_ENHANCE_12DATA_8ID; + } + } + else + { + //do nothing + } + return eRet; +} + +/** + * @brief Get Channel enhanced serial message id bit 7 to bit4 or id bit 3 to id bit 0 + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel enhanced serial message id bit 7 to bit4 or id bit 3 to id bit 0 + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelBit3EnhancedID7_4_OR_ID3_0(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_SBIT3 & SENT_CHN_SBIT3__ID7_4_OR_ID3_0_MASK) >> SENT_CHN_SBIT3__ID7_4_OR_ID3_0_SHIFT); +} + +/** + * @brief Get Channel enhanced serial message id bit 3 to bit0 or data bit 15 to id bit 12 + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel enhanced serial message id bit 3 to bit0 or data bit 15 to id bit 12 + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelBit3EnhancedID3_0_OR_DATA15_12(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_SBIT3 & SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_MASK) >> SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_SHIFT); +} + +/** + * @brief Get Channel slow message bit2 with CRC + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel slow message CRC value + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelBit2CRC(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_SBIT2 & SENT_CHN_SBIT2__SMSG_CRC_MASK) >> SENT_CHN_SBIT2__SMSG_CRC_SHIFT); +} + +/** + * @brief Get Channel slow message bit2 with DATA + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint16_t the corresponding channel slow message DATA value + */ +LOCAL_INLINE uint16_t SENT_HWA_GetChannelBit2DATA(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint16_t)((pSent->SENT_CHN[u8Channel].CHN_SBIT2 & SENT_CHN_SBIT2__SMSG_DATA_MASK) >> SENT_CHN_SBIT2__SMSG_DATA_SHIFT); +} + +/** + * @brief Get Channel slow message status timestamp + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the corresponding channel timestamp value + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChannelSlowMessageTimeStamp(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return ((pSent->SENT_CHN[u8Channel].CHN_STS & SENT_CHN_STS_SMSG_TIMESTAMP_MASK) >> SENT_CHN_STS_SMSG_TIMESTAMP_SHIFT); +} + +/** + * @brief Get Channel number of received frames + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the number of received frames + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChanneReceivedFrameNumber(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return ((pSent->SENT_CHN[u8Channel].CHN_MCNT & SENT_CHN_MCNT_FRAME_CNT_MASK) >> SENT_CHN_MCNT_FRAME_CNT_SHIFT); +} + +/** + * @brief Get Channel number of received edges + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the number of received edges + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChanneReceivedEdgeNumber(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return ((pSent->SENT_CHN[u8Channel].CHN_MCNT & SENT_CHN_MCNT_EDGE_CNT_MASK) >> SENT_CHN_MCNT_EDGE_CNT_SHIFT); +} + +/** + * @brief Clear the number of received frames + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearChannelReceivedFrameNumber(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_MCNT |= SENT_CHN_MCNT_FRAME_CNT_CLR_MASK; +} + +/** + * @brief Clear the number of received edges + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearChannelReceivedEdgeNumber(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_MCNT |= SENT_CHN_MCNT_EDGE_CNT_CLR_MASK; +} + +/** + * @brief Enable SENT channel SPC mode + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSPCMode(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL |= SENT_CHN_SPC_CTL_SPC_ENABLE_MASK; +} + +/** + * @brief Disable SENT channel SPC mode + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSPCMode(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL &= ~SENT_CHN_SPC_CTL_SPC_ENABLE_MASK; +} + +/** + * @brief Enable SENT channel calibration diagnosis in SPC mod + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalibrationDiag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL &= ~SENT_CHN_SPC_CTL_CAL_DIAG_DIS_MASK; +} + +/** + * @brief Disable SENT channel calibration diagnosis in SPC mod + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelCalibrationDiag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL |= SENT_CHN_SPC_CTL_CAL_DIAG_DIS_MASK; +} + + +/** + * @brief Set the SPC pulse trigger method + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param eTrigger the SPC pulse trigger method + */ +LOCAL_INLINE void SENT_HWA_SetChannelSPCTriggerMethod(SENT_Type *const pSent, uint8_t u8Channel, SENT_SPCTriggerType eTrigger) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL = (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & ~SENT_CHN_SPC_CTL_SPC_MODE_MASK) | SENT_CHN_SPC_CTL_SPC_MODE(eTrigger); +} + +/** + * @brief Set the delay between SPC-trigger assert and finally generate a SPC pulse + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param eTrigger the delay value + */ +LOCAL_INLINE void SENT_HWA_SetChannelSPCPulseDelay(SENT_Type *const pSent, uint8_t u8Channel, uint8 u8Delay) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL = (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & ~SENT_CHN_SPC_CTL_SPC_PULSE_DELAY_MASK) | SENT_CHN_SPC_CTL_SPC_PULSE_DELAY(u8Delay); +} + +/** + * @brief Set the delay between SPC-trigger assert and finally generate a SPC pulse + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param eTick the selected tick base of SPC + */ +LOCAL_INLINE void SENT_HWA_SetChannelSPCTickBase(SENT_Type *const pSent, uint8_t u8Channel, SENT_SPCTickType eTick) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL = (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & ~SENT_CHN_SPC_CTL_SPC_TICK_BASE_MASK) | SENT_CHN_SPC_CTL_SPC_TICK_BASE(eTick); +} + +/** + * @brief trigger the SENT to generate a SPC pulse by software + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_StartChannelSPC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL |= SENT_CHN_SPC_CTL_SPC_START_MASK; +} + +/** + * @brief Set the width of the SPC pulse. + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u8Width the width of the SPC pulse. + */ +LOCAL_INLINE void SENT_HWA_SetChannelSPCPulseWidth(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Width) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL = (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & ~SENT_CHN_SPC_CTL_SPC_PULSE_WIDTH_MASK) | SENT_CHN_SPC_CTL_SPC_PULSE_WIDTH(u8Width); +} + +/** + * @brief Set the idle count determines how long the bus idle flag will assert when bus is idle + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u8Count the idle count + */ +LOCAL_INLINE void SENT_HWA_SetChannelIdleCount(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Count) +{ + pSent->SENT_CHN[u8Channel].CHN_IDLE_CTL = (pSent->SENT_CHN[u8Channel].CHN_IDLE_CTL & ~SENT_CHN_IDLE_CTL_IDLE_CNT_MASK) | SENT_CHN_IDLE_CTL_IDLE_CNT(u8Count); +} + +/** + * @brief Get the flag indicating the spc is busy + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return bool the flag indicating the spc is busy + */ +LOCAL_INLINE bool SENT_HWA_GetChanneSPCBusyFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_CHN_SPC_CTL_SPC_BUSY_MASK == (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & SENT_CHN_SPC_CTL_SPC_BUSY_MASK)) + { + return true; + } + else + { + return false; + } +} + +/** @}*/ + +#endif /* _HWA_SENT_H_ */ diff --git a/Inc/HwA_smc.h b/Inc/HwA_smc.h new file mode 100644 index 0000000..dd468b6 --- /dev/null +++ b/Inc/HwA_smc.h @@ -0,0 +1,74 @@ +/** + * @file HwA_smc.h + * @author Flagchip + * @brief FC7xxx SMC hardware access layer + * @version 0.1.0 + * @date 2022-11-21 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +#ifndef _HWA_SMC_H_ +#define _HWA_SMC_H_ + +#include "device_header.h" +/********* Local typedef ************/ +/** @brief SMC stop mode control */ +typedef enum +{ + SMC_STOP_MODE = 0U, + SMC_STANDBY_MODE = 4U +} SMC_LpwModeCtrlType; + +/** @brief SMC standby mode */ +typedef enum +{ + SMC_CFG_STANDBY_0 = 0U, + SMC_CFG_STANDBY_1 = 1U, + SMC_CFG_STANDBY_2 = 2U, + SMC_CFG_STANDBY_3 = 3U +} SMC_StandbyModeType; + +/********* Local inline function ************/ +/** + * @brief Clear stop mode control value + * + */ +LOCAL_INLINE void SMC_HWA_ClearStopModeCtrl(void) +{ + SMC->PMCTRL &= ~(uint32_t)SMC_PMCTRL_STOP_MODE_MASK; +} + +/** + * @brief Set stop mode control + * + * @param eMode Stop mode control type + */ +LOCAL_INLINE void SMC_HWA_SetStopModeCtrl(SMC_LpwModeCtrlType eMode) +{ + SMC->PMCTRL = (uint32_t)eMode; +} + +/** + * @brief Clear standby mode + * + */ +LOCAL_INLINE void SMC_HWA_ClearStandbyMode(void) +{ + SMC->STANDBY_CFG &= ~(uint32_t)SMC_STANDBY_CFG_OPTION_MASK; +} + +/** + * @brief Set standby mode + * + * @param eMode Standby mode type + */ +LOCAL_INLINE void SMC_HWA_SetStandbyMode(SMC_StandbyModeType eMode) +{ + SMC->STANDBY_CFG = (uint32_t)eMode; +} + + +#endif /* #ifndef _HWA_SMC_H_ */ diff --git a/Inc/HwA_stcu.h b/Inc/HwA_stcu.h new file mode 100644 index 0000000..3f69c69 --- /dev/null +++ b/Inc/HwA_stcu.h @@ -0,0 +1,265 @@ +/** + * @file HwA_stcu.h + * @author Flagchip + * @brief Safety Test and Control Unit + * @version 0.1.0 + * @date 2022-11-30 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 03/08/2022 Flagchip038 N/A First version for FC7xxx + ******************************************************************************** */ + +#ifndef _HWA_STCU_H_ +#define _HWA_STCU_H_ + +#include "device_header.h" +#include "fc7xxx_driver_stcu.h" + +/** + * \brief Get Self Test Status + * + * \return Status, maybe more than one status, refer to "STCU_SelfTestStatusType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetSelfTestStatus(void) +{ + return STCU->SELF_TEST_STATUS; +} + +/** + * \brief Clear all Self Test Status + */ +LOCAL_INLINE void STCU_HWA_ClearSelfTestStatus(void) +{ + STCU->SELF_TEST_STATUS = 0x0UL; +} + + +/** + * \brief Mbist select for self-test + * + * \param u32MbistSel maybe more than one + */ +LOCAL_INLINE void STCU_HWA_MbistSelect(uint32_t u32MbistSel) +{ + STCU->MBIST_SEL = u32MbistSel; +} + +/** + * \brief Get Mbist Done Flag + * + * \return All Mbist Done flags, refer to "STCU_MbistDoneType" + */ +LOCAL_INLINE uint32_t STCU_GetMbistDone(void) +{ + return STCU->MBIST_DONE_STATUS; +} + +/** + * \brief Get Mbist Fail Flag + * + * \return All Mbist Fail flags "STCU_MbistFailedType" + */ +LOCAL_INLINE uint32_t STCU_GetMbistFail(void) +{ + return STCU->MBIST_FAIL_STATUS; +} + +/** + * \brief Check Lbist execution failed status + * + * \return LBIST status, refer to "STCU_LbistStatusType" + */ +LOCAL_INLINE uint32_t STCU_HWA_CheckLbistStatus(void) +{ + return STCU->LBIST_STATUS; +} + + +/** + * \brief Get STCU Hardware Ram Initial Status + * + * \return Initial Status, refer to "STCU_HardwareInitRamStatusType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetHardwareRamInitStatus(void) +{ + return STCU->SRAM_INI_STATUS; +} + +/** + * \brief STCU RAM Init Mode set, can select more than one, for example: STCU_INIT_RAM_TYPE_SRAM0 | STCU_INIT_RAM_TYPE_SRAM1 + * + * \param u32InitRamType Init Mode + */ +LOCAL_INLINE void STCU_HWA_SetRamInitType(uint32_t u32InitRamType) +{ + STCU->SRAM_INI_SEL = u32InitRamType; +} + +/** + * \brief Set STCU Interrupt + * + * \param bIntEn Normal interrupt enable + * \param bSequenceErrorIntEn Sequence error interrupt enable + * \param bSizeErrorIntEn Size error interrupt enable + */ +LOCAL_INLINE void STCU_HWA_SetInterrupt(uint8_t bIntEn, uint8_t bSequenceErrorIntEn, uint8_t bSizeErrorIntEn) +{ + STCU->IRQ = STCU_IRQ_EN(bIntEn) | STCU_IRQ_SEQ_ERR(bSequenceErrorIntEn) | STCU_IRQ_SIZE_ERR(bSizeErrorIntEn); +} + +/** + * \brief STCU Ram Initial Start + * + * \param eInitRamMode Initial mode + * \param bEnable Enable Initial + * \param bLock Lock after initial + */ +LOCAL_INLINE void STCU_HWA_StartRamInit(STCU_InitRamModeType eInitRamMode, uint8_t bLock) +{ + STCU->SRAM_INI_CTRL = STCU_SRAM_INI_CTRL_MODE(eInitRamMode) | STCU_SRAM_INI_CTRL_EN_MASK | STCU_SRAM_INI_CTRL_LOCK(bLock) ; +} + +/** + * \brief Get Ram Initial Done flag + * + * \return All Done flag, maybe more than one flag, refer to "STCU_InitRamDoneType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetRamInitDone(void) +{ + return STCU->SRAM_INI_DONE_STATUS; +} + +/** + * \brief Get Ram Initial status + * + * \return All Done flag, maybe more than one flag, refer to "STCU_HardwareInitRamStatusType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetRamInitStatus(void) +{ + return STCU->SRAM_INI_STATUS; +} + +/** + * \brief Set the LBIST pattern amount control value N. + * + * \param u32Amount LBIST pattern amount control value N. (pattern amount = N * 256) + */ +LOCAL_INLINE void STCU_HWA_SetLBISTPatternAmount(uint32_t u32Amount) +{ + STCU->LBIST_PAT_CTRL = u32Amount; +} + +/** + * \brief Set the MBIST algorithm for SW trigger self-test + * + * \param bFullTest Enable Full test for MBIST. + * \param bSRAMInit Enable SRAM initialization at the end of software trigger self-test. + */ +LOCAL_INLINE void STCU_HWA_SetMBISTSWAlg(bool bFullTest, bool bSRAMInit) +{ + STCU->MBIST_ALG = (STCU->MBIST_ALG & ~(STCU_MBIST_ALG_TRIG_ALG_SEL_MASK | STCU_MBIST_ALG_TRIG_INI_EN_MASK)) | \ + (STCU_MBIST_ALG_TRIG_ALG_SEL(bFullTest?0X1FU:0x19U) | STCU_MBIST_ALG_TRIG_INI_EN(bSRAMInit?0x1U:0x0U)); +} + +/** + * \brief Set safety key + * + * \param u32Key Safety Key. + */ +LOCAL_INLINE void STCU_HWA_SetSafetyKey(uint32_t u32Key) +{ + STCU->SELF_TEST_KEY = u32Key; +} + +/** + * \brief Enable A self-test software trigger. + */ +LOCAL_INLINE void STCU_HWA_SwTriggerA(void) +{ + STCU->SELF_TEST_TRIG_A = STCU_SELF_TEST_TRIG_A_MASK; +} + +/** + * \brief Enable B self-test software trigger. + */ +LOCAL_INLINE void STCU_HWA_SwTriggerB(void) +{ + STCU->SELF_TEST_TRIG_B = STCU_SELF_TEST_TRIG_B_MASK; +} + +/** + * \brief Set self test ctrl register + * + * \param u32Reg Register value. + */ +LOCAL_INLINE void STCU_HWA_SetSelfTestCTRL(uint32_t u32Reg) +{ + STCU->SELF_TEST_CTRL = u32Reg; +} + +/** + * \brief Enable interrupt + */ +LOCAL_INLINE void STCU_HWA_EnableInterrupt(void) +{ + STCU->IRQ |= STCU_IRQ_EN_MASK; +} + +/** + * \brief Disable interrupt + */ +LOCAL_INLINE void STCU_HWA_DisableInterrupt(void) +{ + STCU->IRQ &= ~STCU_IRQ_EN_MASK; +} + +/** + * \brief Get STCU interrupt flags + * + * \return Status, maybe more than one status, refer to "STCU_InterruptFlagType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetInterruptFlag(void) +{ + return ((STCU->IRQ) & (STCU_IRQ_SEQ_ERR_MASK | STCU_IRQ_SIZE_ERR_MASK)); +} + +/** + * \brief Clear STCU interrupt flags + */ +LOCAL_INLINE void STCU_HWA_ClearInterruptFlag(void) +{ + STCU->IRQ &= ~(STCU_IRQ_SEQ_ERR_MASK | STCU_IRQ_SIZE_ERR_MASK); +} + +/** + * \brief Set STCU LBIST expected misr value + */ +LOCAL_INLINE void STCU_HWA_SetExpectedMisr(uint32_t u32Misr) +{ + STCU->LBIST_EXP_MISR = STCU_LBIST_EXP_MISR_MISR(u32Misr); +} + +/** + * \brief Get STCU LBIST expected misr value + */ +LOCAL_INLINE uint32_t STCU_HWA_GetExpectedMisr(void) +{ + return STCU->LBIST_EXP_MISR; +} + +/** + * \brief Get STCU LBIST actual misr value + */ +LOCAL_INLINE uint32_t STCU_HWA_GetActualMisr(void) +{ + return STCU->LBIST_ACT_MISR; +} + +#endif /*#ifndef _HWA_STCU_H_*/ diff --git a/Inc/HwA_tmu.h b/Inc/HwA_tmu.h new file mode 100644 index 0000000..601ceb6 --- /dev/null +++ b/Inc/HwA_tmu.h @@ -0,0 +1,548 @@ +/** + * @file HwA_tmu.h + * @author Flagchip + * @brief Hardware access layer for TMU + * @version 0.1.0 + * @date 2023-12-29 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/********************************************************************************* +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-29 qxw074 N/A First version for FC7240 +******************************************************************************** */ + +#ifndef _HWA_TMU_H +#define _HWA_TMU_H + +#include "device_header.h" +#include "HwA_csc.h" + +/** + * @defgroup HwA_tmu + * @ingroup fc7xxx_driver_tmu + * @{ + */ + +/** + * @brief Select the TF_CTRL and TV_CTRL register is lock or not + * + */ +typedef enum +{ + TMU_TF_TV_LOCK = 0U, /*!< TF_CTRL and TV_CTRL register is lock*/ + TMU_TF_TV_UNLOCK = 1U /*!< TF_CTRL and TV_CTRL register is unlock*/ +}TMU_LockType; + +/** + * @brief Select the Flag-based temperature sensor hysteresis control + * + */ +typedef enum +{ + TMU_TF_HYSOFF_ON = 0U, /*!< Flag-based temperature sensor hysteresis is on*/ + TMU_TF_HYSOFF_OFF = 1U /*!< Flag-based temperature sensor hysteresis is off*/ +}TMU_HysteresisType; + +/** + * @brief Select the Flag-based temperature sensor filter control + * + */ +typedef enum +{ + TMU_TF_FILT_BYP_BYPASSED = 0U, /*!< Flag-based temperature sensor filter is bypassed*/ + TMU_TF_FILT_BYP_ENABLED = 1U /*!< Flag-based temperature sensor filter is enabled*/ +}TMU_bypassType; + +/** + * @brief Get the status of whether the temperature sensor register is locked + * + * @param pTmu the base address of the TMU instance + * @return true Temperature register is locked(CTRL) + * @return false Temperature register is unlocked(CTRL) + */ +LOCAL_INLINE TMU_LockType TMU_HWA_GetTemperatureLockStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->UNLOCK & TMU_UNLOCK_UNLOCK_MASK) >> TMU_UNLOCK_UNLOCK_SHIFT; + return (TMU_LockType)u32TmpVal; +} + +/** + * @brief Set the status of whether the temperature sensor register is locked or not + * + * @param pTmu the base address of the TMU instance + * @param eLockStatus Select the TF_CTRL and TV_CTRL register is lock or not + */ +LOCAL_INLINE void TMU_HWA_SetTemperatureLockStatus(TMU_Type *const pTmu,TMU_LockType eLockStatus) +{ + if((bool)eLockStatus) + { + pTmu->UNLOCK = 0xA5A50000U | TMU_UNLOCK_UNLOCK(eLockStatus); + }else + { + pTmu->UNLOCK = TMU_UNLOCK_UNLOCK(eLockStatus); + } +} + +/** + * @brief Get the Flag-based temperature sensor over 150 Celsius interrupt flag + * + * @param pTmu the base address of the TMU instance + * @return true Temperature over 150 Celsius interrupt is enabled + * @return false Temperature over 150 Celsius interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperature150InterruptFlag(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_150F_IE_MASK) >> TMU_TF_CTRL_TF_150F_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor over 150 Celsius interrupt flag + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature over 150 Celsius interrupt + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperature150InterruptFlag(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_150F_IE_MASK) | TMU_TF_CTRL_TF_150F_IE(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor over 125 Celsius interrupt flag + * + * @param pTmu the base address of the TMU instance + * @return true Temperature over 125 Celsius interrupt is enabled + * @return false Temperature over 125 Celsius interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperature125InterruptFlag(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_125F_IE_MASK) >> TMU_TF_CTRL_TF_125F_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor over 125 Celsius interrupt flag + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature over 125 Celsius interrupt + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperature125InterruptFlag(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_125F_IE_MASK) | TMU_TF_CTRL_TF_125F_IE(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor ready interrupt flag + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor ready interrupt is enabled + * @return false Temperature sensor ready interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureReadyInterruptFlag(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_RDYF_IE_MASK) >> TMU_TF_CTRL_TF_RDYF_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor over ready interrupt flag + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature sensor ready interrupt + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureReadyInterruptFlag(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_RDYF_IE_MASK) | TMU_TF_CTRL_TF_RDYF_IE(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor hysteresis control status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor Hysteresis is off + * @return false Temperature sensor Hysteresis is on + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureHysteresisStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_HYSOFF_MASK) >> TMU_TF_CTRL_TF_HYSOFF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor hysteresis control status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to off(1)/on(0) the temperature sensor hysteresis + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureHysteresisStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_HYSOFF_MASK) | TMU_TF_CTRL_TF_HYSOFF(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor startup counter + * + * @param pTmu the base address of the TMU instance + * @return u32TmpVal count of the startup + */ +LOCAL_INLINE uint8_t TMU_HWA_GetFlagTemperatureCounter(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_START_CNT_MASK) >> TMU_TF_CTRL_TF_START_CNT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the Flag-based temperature sensor startup counter + * + * @param pTmu the base address of the TMU instance + * @param u8Counter the startup counter + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureCounter(TMU_Type *const pTmu,uint8_t u8Counter) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_START_CNT_MASK) | TMU_TF_CTRL_TF_START_CNT(u8Counter); +} + +/** + * @brief Get the Flag-based temperature sensor filter bypass control status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor Filter is enabled + * @return false Temperature sensor Filter is bypassed + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureFilterBypassStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_FILT_BYP_MASK) >> TMU_TF_CTRL_TF_FILT_BYP_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor filter bypass control status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether the temperature sensor filter is enabled(1) or bypassed(0) + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureFilterBypassStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_FILT_BYP_MASK) | TMU_TF_CTRL_TF_FILT_BYP(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor enable status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor is on + * @return false Temperature sensor is off + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureEnableStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_EN_MASK) >> TMU_TF_CTRL_TF_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor enable status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether the temperature sensor is on(1) or off(0) + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureEnableStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_EN_MASK) | TMU_TF_CTRL_TF_EN(bEnable); +} + +/** + * @brief Check whether the temperature is over 150 Celsius + * + * @param pTmu the base address of the TMU instance + * @return true the temperature is over 150 Celsius + * @return false the temperature is not over 150 Celsius + */ +LOCAL_INLINE bool TMU_HWA_Get150Status(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_150_MASK) >> TMU_TF_STATUS_TF_150_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the temperature is over 125 Celsius + * + * @param pTmu the base address of the TMU instance + * @return true the temperature is over 125 Celsius + * @return false the temperature is not over 125 Celsius + */ +LOCAL_INLINE bool TMU_HWA_Get125Status(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_125_MASK) >> TMU_TF_STATUS_TF_125_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the flag for temperature over 150 Celsius is set + * + * @param pTmu the base address of the TMU instance + * @return true the temperature has exceeded 150 Celsius since last time W1C + * @return false the temperature has not exceeded 150 Celsius since TF is ready + */ +LOCAL_INLINE bool TMU_HWA_Get150Flag(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_150F_MASK) >> TMU_TF_STATUS_TF_150F_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the temperature over 150 Celsius flag + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_Clear150Flag(TMU_Type *const pTmu) +{ + pTmu->TF_STATUS |= TMU_TF_STATUS_TF_150F(1U); +} + +/** + * @brief Check whether the flag for temperature over 125 Celsius is set + * + * @param pTmu the base address of the TMU instance + * @return true the temperature has exceeded 125 Celsius since last time W1C + * @return false the temperature has not exceeded 125 Celsius since TF is ready + */ +LOCAL_INLINE bool TMU_HWA_Get125Flag(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_125F_MASK) >> TMU_TF_STATUS_TF_125F_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the temperature over 125 Celsius flag + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_Clear125Flag(TMU_Type *const pTmu) +{ + pTmu->TF_STATUS |= TMU_TF_STATUS_TF_125F(1U); +} + +/** + * @brief Check whether the Flag-based temperature sensor is ready + * + * @param pTmu the base address of the TMU instance + * @return true the Flag-based temperature sensor is ready + * @return false the Flag-based temperature sensor is not ready + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureReady(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_RDYF_MASK) >> TMU_TF_STATUS_TF_RDYF_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the Flag-based temperature sensor ready flag + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_ClearFlagTemperatureReady(TMU_Type *const pTmu) +{ + pTmu->TF_STATUS |= TMU_TF_STATUS_TF_RDYF(1U); +} + +/** + * @brief Get the Vlotage-based temperature sensor ready interrupt flag + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor ready interrupt is enabled + * @return false Temperature sensor ready interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureReadyInterruptFlag(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_RDYF_IE_MASK) >> TMU_TV_CTRL_TV_RDYF_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Voltage-based temperature sensor over ready interrupt flag + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature sensor ready interrupt + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureReadyInterruptFlag(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_RDYF_IE_MASK) | TMU_TV_CTRL_TV_RDYF_IE(bEnable); +} + +/** + * @brief Get the Voltage-based temperature sensor startup counter + * + * @param pTmu the base address of the TMU instance + * @return u32TmpVal count of the startup + */ +LOCAL_INLINE uint8_t TMU_HWA_GetVoltageTemperatureCounter(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_START_CNT_MASK) >> TMU_TV_CTRL_TV_START_CNT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the Voltage-based temperature sensor startup counter + * + * @param pTmu the base address of the TMU instance + * @param u8Counter the startup counter + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureCounter(TMU_Type *const pTmu,uint8_t u8Counter) +{ + pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_START_CNT_MASK) | TMU_TV_CTRL_TV_START_CNT(u8Counter); +} + +/** + * @brief Get the Voltage-based temperature sensor enable status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor is on + * @return false Temperature sensor is off + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureEnableStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_EN_MASK) >> TMU_TV_CTRL_TV_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Voltage-based temperature sensor enable status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether the temperature sensor is on(1) or off(0) + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureEnableStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_EN_MASK) | TMU_TV_CTRL_TV_EN(bEnable); +} + +/** + * @brief Check whether the Voltage-based temperature sensor is ready + * + * @param pTmu the base address of the TMU instance + * @return true the Voltage-based temperature sensor is ready + * @return false the Voltage-based temperature sensor is not ready + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureReady(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_STATUS; + u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_RDYF_MASK) >> TMU_TV_STATUS_TV_RDYF_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the Voltage-based temperature sensor ready flag + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_ClearVoltageTemperatureReady(TMU_Type *const pTmu) +{ + pTmu->TV_STATUS |= TMU_TV_STATUS_TV_RDYF(1U); +} + +/** + * @brief Get the TMU_TF_CTRL config + * + * @param pTmu the base address of the TMU instance + * @return uint32_t the TMU_TF_CTRL config + */ +LOCAL_INLINE uint32_t TMU_HWA_GetFlagTempCtrl(const TMU_Type *const pTmu) +{ + return pTmu->TF_CTRL; +} + +/** + * @brief Set the TMU_TF_CTRL config + * + * @param pTmu the base address of the TMU instance + * @param u32Config the TMU_TF_CTRL config + */ +LOCAL_INLINE void TMU_HWA_SetFlagTempCtrl(TMU_Type *const pTmu, uint32_t u32Config) +{ + pTmu->TF_CTRL = u32Config; +} + +/** + * @brief Get the TMU_TV_CTRL config + * + * @param pTmu the base address of the TMU instance + * @return uint32_t the TMU_TV_CTRL config + */ +LOCAL_INLINE uint32_t TMU_HWA_GetVoltageTempCtrl(const TMU_Type *const pTmu) +{ + return pTmu->TV_CTRL; +} + +/** + * @brief Set the TMU_TV_CTRL config + * + * @param pTmu the base address of the TMU instance + * @param u32Config the TMU_TV_CTRL config + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTempCtrl(TMU_Type *const pTmu, uint32_t u32Config) +{ + pTmu->TV_CTRL = u32Config; +} + +/** + * @brief Controls the stop ack function enable or not to the TMU0 + * + * @param bEnable set the ACK enable or not + */ +LOCAL_INLINE void TMU_HWA_SetStopAck(bool bEnable) +{ + if(bEnable) + { + CSC0_HWA_MODER0_EnableStopAck(CSC_STOPMODE_TMU); + } + else + { + CSC0_HWA_MODER0_DisableStopAck(CSC_STOPMODE_TMU); + } +} + +/** + * @brief Get the TV_TRIM_TV_TCODE value + * + * @param pTmu the base address of the TMU instance + * @return uint32_t the TV_TRIM_TV_TCODE value + */ +LOCAL_INLINE uint32_t TMU_HWA_GetTemperatureCode(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_TRIM; + u32TmpVal = (u32TmpVal & TMU_TV_TRIM_TV_TCODE_MASK) >> TMU_TV_TRIM_TV_TCODE_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the TV_TRIM_TV_SLOPE value + * + * @param pTmu the base address of the TMU instance + * @return uint32_t the TV_TRIM_TV_SLOPE value + */ +LOCAL_INLINE uint32_t TMU_HWA_GetSlopeFactor(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_TRIM; + u32TmpVal = (u32TmpVal & TMU_TV_TRIM_TV_SLOPE_MASK) >> TMU_TV_TRIM_TV_SLOPE_SHIFT; + return u32TmpVal; +} + +/** @}*/ + +#endif /* _HWA_TMU_H_ */ diff --git a/Inc/HwA_tpue.h b/Inc/HwA_tpue.h new file mode 100644 index 0000000..370e737 --- /dev/null +++ b/Inc/HwA_tpue.h @@ -0,0 +1,2062 @@ +/** + * @file HwA_tpue.h + * @author Flagchip + * @brief FC7xxx TPUE hardware access layer + * @version 0.1.0 + * @date 2024-1-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +#ifndef _HWA_TPUE_H_ +#define _HWA_TPUE_H_ + +#include "device_header.h" + +/********* Local typedef ************/ + +/** @brief TPU channel digital filter control type */ +typedef enum +{ + TPUE_TWO_SAMPLE_MODE = 0U, + TPUE_BYPASS_MODE = 1U, + TPUE_THREE_SAMPLE_MODE = 2U, + TPUE_CONTINUOUS_MODE = 3U +} TPUE_FilterCtrlType; + +/** @brief TPU filter clock source selection type */ +typedef enum +{ + TPUE_TPU_CLK_DIV2 = 0U, + TPUE_TPU_CLK = 1U +} TPUE_FilterClkSrcType; + +/** @brief TPU channel digital filter control type */ +typedef enum +{ + TPUE_SYSCLK_DIV_1 = 0U, + TPUE_SYSCLK_DIV_2 = 1U, + TPUE_SYSCLK_DIV_4 = 2U, + TPUE_SYSCLK_DIV_8 = 3U, + TPUE_SYSCLK_DIV_16 = 4U, + TPUE_SYSCLK_DIV_32 = 5U, + TPUE_SYSCLK_DIV_64 = 6U, + TPUE_SYSCLK_DIV_128 = 7U +} TPUE_FilterPrescalerCtrlType; + +/** @brief TPU TCR1 clock control mode type */ +typedef enum +{ + TPUE_TCR1CLK_CLK_SRC = 0U, + TPUE_TCR1CLK_UPDOWN_CNT_MODE = 3U, + TPUE_TCR1CLK_CLK_SRC_TPUCLKDIV2 = 4U, + TPUE_TCR1CLK_SRC_TPUCLK = 5U +} TPUE_TCR1ClkCtrlModeType; + +/** @brief TPU angle tick gen clk type */ +typedef enum +{ + TPUE_TCR1_PRESCAL_OUTPUT = 0U, + TPUE_TCR2_PRESCAL_OUTPUT = 1U +} TPUE_AngleTickGenClkType; + +/** @brief TPU Angle Mode Selection type */ +typedef enum +{ + TPUE_TCR2_TIMEBASE_EAC_DISABLE = 0U, + TPUE_TOOTHSIGNAL_AS_TCRCLK_TOOTH_CH_0 = 1U, + TPUE_TOOTHSIGNAL_AS_CH1INPUT_TOOTH_CH_1 = 2U, + TPUE_TOOTHSIGNAL_AS_CH1INPUT_TOOTH_CH_2 = 3U +} TPUE_AngleModeSel; + +/** @brief TPU Angle Mode Selection type */ +typedef enum +{ + TPUE_TWO_SAMPLE_MODE_TPU_CLK_DIV2 = 0U, + TPUE_TWO_SAMPLE_MODE_CH_CLK = 1U, + TPUE_INTEGRATOR_MODE_TPU_CLK_DIV2 = 2U, + TPUE_INTEGRATOR_MODE_CH_CLK = 3U +} TPUE_TCRClkFilterType; + +/** @brief TPU TCR2 clock control mode0 type */ +typedef enum +{ + TPUE_GATED_DIV8_CLK = 0U, + TPUE_RISE_TRANSITION_INCREMENT_TCR2_PRESCALER = 1U, + TPUE_FALL_TRANSITION_INCREMENT_TCR2_PRESCALER = 2U, + TPUE_DIV8_CLK = 4U, + TPUE_UPDOWN_CNT_MODE = 5U, + TPUE_FROZEN = 7U +} TPUE_TCR1ClkCtrlMode0Type; + +typedef enum +{ + TPUE_RSING_EDGE = 1U, + TPUE_FALLING_EDGE = 2U, + TPUE_BOTH_EDGES = 3U, + TPUE_NO_EDGE = 6U, +} TPUE_TCR1ClkCtrlMode1Type; + +/** @brief Missing Tooth Counter */ +typedef enum +{ + TPUE_NOT_A_MISSING_TOOTH = 0U, + TPUE_ONE_MISSING_TOOTH = 1U, + TPUE_TWO_MISSING_TOOTH = 2U, + TPUE_THREE_MISSING_TOOTH = 3U, +} TPUE_MissToothCntType; + +/** @brief Channel Trigger Configuration */ +typedef enum +{ + TPUE_DISABLED = 0U, + TPUE_ANY_EVENT_GATED_BY_MSRTSR = 2U, + TPUE_HSA_EVENT_ON_FLEXCORE_MODE = 3U, + TPUE_MRL1_EVENT_NOT_GATED_BY_MSR = 4U, + TPUE_MRL2_EVENT_NOT_GATED_BY_MSR = 5U, + TPUE_MRL1_OR_MRL2_EVENT_NOT_GATED_BY_MSR = 6U, + TPUE_MRL1_AND_MRL2_EVENT_NOT_GATED_BY_MSR = 7U, + TPUE_TDL1_OR_TDL2_EVENT_NOT_GATED_BY_TSR = 8U, + TPUE_TDL1_AND_TDL2_EVENT_NOT_GATED_BY_TSR = 9U, + TPUE_EVENT_EQUAL_TO_CH_DO_LEVEL = 10U, + TPUE_EVENT_NEGATIVE_TO_CH_DO_LEVEL = 11U, + TPUE_EVENT_EQUAL_TO_CH_DO_PART1_LEVEL = 12U, + TPUE_EVENT_EQUAL_TO_CH_DO_PART2_LEVEL = 13U, + TPUE_EVENT_EQUAL_TO_CH_IND_LEVEL = 14U, + TPUE_EVENT_EQUAL_TO_CH_IND_LATCH_LEVEL = 15U, +} TPUE_ChTrigCFGType; + +/** @brief Filter Grade for 7 value in 1 loop */ +typedef enum +{ + TPUE_FILTER_DISABLE = 0U, + TPUE_FILTER_LOW = 1U, + TPUE_FILTER_MIDDLE = 2U, + TPUE_FILTER_HIGH = 3U, +} TPUE_FilterGradeType; + +/** @brief Channel event triggered interrupt priority */ +typedef enum +{ + TPUE_PRIORITY_DISABLE = 0U, + TPUE_PRIORITY_LOW = 1U, + TPUE_PRIORITY_MIDDLE = 2U, + TPUE_PRIORITY_HIGH = 3U, +} TPUE_EventIntPriorityType; + +/** @brief Channel time base selection of part 1. */ +typedef enum +{ + TPUE_GREATER_OR_EQUAL_CAPBASE_TCR1_MATCHBASE_TCR1 = 0U, + TPUE_GREATER_OR_EQUAL_CAPBASE_TCR1_MATCHBASE_TCR2 = 1U, + TPUE_GREATER_OR_EQUAL_CAPBASE_TCR2_MATCHBASE_TCR1 = 2U, + TPUE_GREATER_OR_EQUAL_CAPBASE_TCR2_MATCHBASE_TCR2 = 3U, + TPUE_EQUAL_ONLY_CAPBASE_TCR1_MATCHBASE_TCR1 = 4U, + TPUE_EQUAL_ONLY_CAPBASE_TCR1_MATCHBASE_TCR2 = 5U, + TPUE_EQUAL_ONLY_CAPBASE_TCR2_MATCHBASE_TCR1 = 6U, + TPUE_EQUAL_ONLY_CAPBASE_TCR2_MATCHBASE_TCR2 = 7U, +} TPUE_TimeBaseSelctionType; + +/** @brief Channel Input Pin Action Control. */ +typedef enum +{ + TPUE_NO_TRANSITIONS = 0U, + TPUE_DETECT_RISING_EDGE_ONLY = 1U, + TPUE_DETECT_FALLING_EDGE_ONLY = 2U, + TPUE_DETECT_EITHER_EDGE_ONLY = 3U, + TPUE_DETECT_SIGNAL_0_ON_MATCH = 4U, + TPUE_DETECT_SIGNAL_1_ON_MATCH = 5U, +} TPUE_IPACType; + +/** @brief Channel output Pin Action Control. */ +typedef enum +{ + TPUE_NO_CHANGE_OUTPUT = 0U, + TPUE_MATCH_SET_OUTPUT_HIGH = 1U, + TPUE_MATCH_SET_OUTPUT_LOW = 2U, + TPUE_MATCH_TOGGLE_OUTPUT = 3U, + TPUE_TRANSITION_SET_OUTPUT_HIGH = 4U, + TPUE_TRANSITION_SET_OUTPUT_LOW = 5U, + TPUE_TRANSITION_TOGGLE_OUTPUT = 6U, + TPUE_NO_CHANGE_OPAC = 7U, +} TPUE_OPACType; + +/** @brief PDCM Encoding. */ +typedef enum +{ + TPUE_EM_B_ST = 0U, + TPUE_EM_B_DT = 1U, + TPUE_EM_NB_ST = 2U, + TPUE_EM_NB_DT = 3U, + TPUE_M2_ST = 4U, + TPUE_M2_DT = 5U, + TPUE_BM_ST = 6U, + TPUE_BM_DT = 7U, + TPUE_M2_O_ST = 8U, + TPUE_M2_O_DT = 9U, + TPUE_SM_ST = 12U, + TPUE_SM_DT = 13U, + TPUE_SM_ST_E = 14U, +} TPUE_PDCMEncodeType; + +/********* Local inline function ************/ +/** + * @brief Get channel digital filter control + * + */ +LOCAL_INLINE TPUE_FilterCtrlType TPU_E_HWA_GetFilterCtrl(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_CDFC_MASK) >> TPU_E_GCR_CR_CDFC_SHIFT; + return (TPUE_FilterCtrlType)u32TmpVal; +} + +/** + * @brief Set channel digital filter control + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFilterCtrl(TPU_E_Type *const pTPUE, TPUE_FilterCtrlType eControlMode) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_CDFC_MASK) | TPU_E_GCR_CR_CDFC(eControlMode); +} + +/** + * @brief Get filter clock source + * + */ +LOCAL_INLINE TPUE_FilterClkSrcType TPU_E_HWA_GetFilterClkSrc(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_FCSS_MASK) >> TPU_E_GCR_CR_FCSS_SHIFT; + return (TPUE_FilterClkSrcType)u32TmpVal; +} + +/** + * @brief Set filter clock source + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFilterClkSrc(TPU_E_Type *const pTPUE, TPUE_FilterClkSrcType eClkSrc) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_FCSS_MASK) | TPU_E_GCR_CR_FCSS(eClkSrc); +} + +/** + * @brief Get filter prescaler clock control + * + */ +LOCAL_INLINE TPUE_FilterPrescalerCtrlType TPU_E_HWA_GetFilterPrescaler(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_FPSCK_MASK) >> TPU_E_GCR_CR_FPSCK_SHIFT; + return (TPUE_FilterPrescalerCtrlType)u32TmpVal; +} + +/** + * @brief Get filter prescaler clock control + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFilterPrescaler(TPU_E_Type *const pTPUE, TPUE_FilterPrescalerCtrlType ePrescaler) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_FPSCK_MASK) | TPU_E_GCR_CR_FPSCK(ePrescaler); +} + +/** + * @brief Whether channel function is disabled in Stop mode + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetFuncDisableInStopMode(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_HALT_CH_MASK) >> TPU_E_GCR_CR_HALT_CH_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable channel function is disabled or normal in Stop mode + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFuncDisableInStopMode(TPU_E_Type *const pTPUE, bool bEnable) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_HALT_CH_MASK) | TPU_E_GCR_CR_HALT_CH(bEnable); +} + +/** + * @brief Whether channel function is disabled in Stop mode + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTimeBaseCntStopInStopMode(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_HALT_TB_MASK) >> TPU_E_GCR_CR_HALT_TB_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable channel function is disabled or normal in Stop mode + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTimeBaseCntStopInStopMode(TPU_E_Type *const pTPUE, bool bEnable) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_HALT_TB_MASK) | TPU_E_GCR_CR_HALT_TB(bEnable); +} + +/** + * @brief Enable channel function is disabled or normal in Stop mode + * + */ +LOCAL_INLINE void TPU_E_HWA_TrigReset(TPU_E_Type *const pTPUE) +{ + pTPUE->GCR_SRR = 0xFC005AFEU; +} + +/** + * @brief Get service request status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetSRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VSR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin input status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetInputStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VIR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin output status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetoutputStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VOR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin output enable status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetoutputEnStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VOBR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL1 status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMRL1Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VM1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL2 status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMRL2Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VM2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL1 status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTDL1Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VT1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL2 status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTDL2Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VT2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL1 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMRL1EventStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_EM1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL2 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMRL2EventStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_EM2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL1 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTDL1eventStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_ET1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL2 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTDL2eventStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_ET2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get HAS status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetHSRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VHSR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Filter Grade + * + */ +LOCAL_INLINE TPUE_FilterGradeType TPU_E_HWA_GetFilterGrade(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_AFGR & TPU_E_GCR_AFGR_FLT_GRD_MASK) >> TPU_E_GCR_AFGR_FLT_GRD_SHIFT; + return (TPUE_FilterGradeType)u32TmpVal; +} + +/** + * @brief Set Filter Grade + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFilterGrade(TPU_E_Type *const pTPUE, TPUE_FilterGradeType eGrade) +{ + pTPUE->GCR_AFGR = (pTPUE->GCR_AFGR & ~TPU_E_GCR_AFGR_FLT_GRD_MASK) | TPU_E_GCR_AFGR_FLT_GRD(eGrade); +} + +/** + * @brief Get Filter Grade setting results + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetFilterGradeCFGErrFlg(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_ASR & TPU_E_GCR_ASR_ERROR_MASK) >> TPU_E_GCR_ASR_ERROR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear filter grade setting results + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearFilterGradeCFGErrFlg(TPU_E_Type *const pTPUE) +{ + pTPUE->GCR_ASR = (pTPUE->GCR_ASR & ~TPU_E_GCR_ASR_ERROR_MASK) | TPU_E_GCR_ASR_ERROR(1U); +} + +/** + * @brief Get endian configuration + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetEndianCFG(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_ASR & TPU_E_GCR_ASR_ENDIAN_MASK) >> TPU_E_GCR_ASR_ENDIAN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set endian configuration + * + */ +LOCAL_INLINE void TPU_E_HWA_SetEndianCFG(TPU_E_Type *const pTPUE) +{ + pTPUE->GCR_ASR = (pTPUE->GCR_ASR & ~TPU_E_GCR_ASR_ENDIAN_MASK) | TPU_E_GCR_ASR_ENDIAN(1U); +} + +/** + * @brief Get channel function entry table select + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetEntryFuncSel(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_AID & TPU_E_GCR_AID_ETCS_MASK) >> TPU_E_GCR_AID_ETCS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get channel function entry table condition + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetEntryFuncCond(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_AID & TPU_E_GCR_AID_COND_MASK) >> TPU_E_GCR_AID_COND_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get channel ID info + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetChIDInfo(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_AID & TPU_E_GCR_AID_ID_MASK) >> TPU_E_GCR_AID_ID_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get TCR1 prescaler. + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetTCR1Prescaler(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR1P_MASK) >> TPU_E_TBR_CR_TCR1P_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get TCR1 prescaler. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR1Prescaler(TPU_E_Type *const pTPUE, uint8_t u8Prescaler) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCR1P_MASK) | TPU_E_TBR_CR_TCR1P(u8Prescaler); +} + +/** + * @brief Get TCR1 clock control. + * + */ +LOCAL_INLINE TPUE_TCR1ClkCtrlModeType TPU_E_HWA_GetTCR1ClkControl(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR1CTL_MASK) >> TPU_E_TBR_CR_TCR1CTL_SHIFT; + return (TPUE_TCR1ClkCtrlModeType)u32TmpVal; +} + +/** + * @brief Set TCR1 clock control. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR1ClkControl(TPU_E_Type *const pTPUE, TPUE_TCR1ClkCtrlModeType eMode) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCR1CTL_MASK) | TPU_E_TBR_CR_TCR1CTL(eMode); +} + +/** + * @brief Get TCR2 prescaler. + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetTCR2Prescaler(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR2P_MASK) >> TPU_E_TBR_CR_TCR2P_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set TCR2 prescaler. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR2Prescaler(TPU_E_Type *const pTPUE, uint8_t ePrescaler) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCR2P_MASK) | TPU_E_TBR_CR_TCR2P(ePrescaler); +} + +/** + * @brief Get Angle tick generator clock. + * + */ +LOCAL_INLINE TPUE_AngleTickGenClkType TPU_E_HWA_GetATGC(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_ATGC_MASK) >> TPU_E_TBR_CR_ATGC_SHIFT; + return (TPUE_AngleTickGenClkType)u32TmpVal; +} + +/** + * @brief Set Angle tick generator clock. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetATGC(TPU_E_Type *const pTPUE, TPUE_AngleTickGenClkType eSrc) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_ATGC_MASK) | TPU_E_TBR_CR_ATGC(eSrc); +} + +/** + * @brief Get Angle Mode Selection. + * + */ +LOCAL_INLINE TPUE_AngleModeSel TPU_E_HWA_GetAM(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_AM_MASK) >> TPU_E_TBR_CR_AM_SHIFT; + return (TPUE_AngleModeSel)u32TmpVal; +} + +/** + * @brief Set Angle Mode Selection. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetAM(TPU_E_Type *const pTPUE, TPUE_AngleModeSel eMode) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_AM_MASK) | TPU_E_TBR_CR_AM(eMode); +} + +/** + * @brief Get TCRCLK signal Filter Control. + * + */ +LOCAL_INLINE TPUE_TCRClkFilterType TPU_E_HWA_GetTCRClkFilter(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCRCF_MASK) >> TPU_E_TBR_CR_TCRCF_SHIFT; + return (TPUE_TCRClkFilterType)u32TmpVal; +} + +/** + * @brief Set TCRCLK signal Filter Control. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCRClkFilter(TPU_E_Type *const pTPUE, TPUE_TCRClkFilterType eMode) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCRCF_MASK) | TPU_E_TBR_CR_TCRCF(eMode); +} + +/** + * @brief Get TCR2 clock control. + * + */ +LOCAL_INLINE TPUE_TCR1ClkCtrlMode0Type TPU_E_HWA_GetTCR2ClkControlAM0(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR2CTL_MASK) >> TPU_E_TBR_CR_TCR2CTL_SHIFT; + return (TPUE_TCR1ClkCtrlMode0Type)u32TmpVal; +} + +/** + * @brief Get TCR2 clock control. + * + */ +LOCAL_INLINE TPUE_TCR1ClkCtrlMode1Type TPU_E_HWA_GetTCR2ClkControlAM1(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR2CTL_MASK) >> TPU_E_TBR_CR_TCR2CTL_SHIFT; + return (TPUE_TCR1ClkCtrlMode1Type)u32TmpVal; +} + +/** + * @brief Set TCR2 clock control. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR2ClkControlAM1(TPU_E_Type *const pTPUE, TPUE_TCR1ClkCtrlMode1Type eMode) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCR2CTL_MASK) | TPU_E_TBR_CR_TCR2CTL(eMode); +} + +/** + * @brief Get TCR1 cnt value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetTCR1CntVal(const TPU_E_Type *const pTPUE) +{ + return pTPUE->TBR_T1R; +} + +/** + * @brief Get TCR2 cnt value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetTCR2CntVal(const TPU_E_Type *const pTPUE) +{ + return pTPUE->TBR_T2R; +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_E_HWA_NotLastTooth(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_TPR & TPU_E_TBR_TPR_LAST_MASK) >> TPU_E_TBR_TPR_LAST_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Set last tooth indication. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetLastTooth(TPU_E_Type *const pTPUE, bool bEnable) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_LAST_MASK) | TPU_E_TBR_TPR_LAST(bEnable); +} + +/** + * @brief Get missing tooth counter. + * + */ +LOCAL_INLINE TPUE_MissToothCntType TPU_E_HWA_GetMissingTooth(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_TPR & TPU_E_TBR_TPR_MISSCNT_MASK) >> TPU_E_TBR_TPR_MISSCNT_SHIFT; + return (TPUE_MissToothCntType)u32TmpVal; +} + +/** + * @brief Set missing tooth counter. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetMissingTooth(TPU_E_Type *const pTPUE, TPUE_MissToothCntType eCnt) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_MISSCNT_MASK) | TPU_E_TBR_TPR_MISSCNT(eCnt); +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_E_HWA_NoInsertTooth(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_TPR & TPU_E_TBR_TPR_IPH_MASK) >> TPU_E_TBR_TPR_IPH_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Set last tooth indication to exit halt mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_InsertPhyTooth(TPU_E_Type *const pTPUE) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_IPH_MASK) | TPU_E_TBR_TPR_IPH(1U); +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_E_HWA_NoForceEACHalt(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_TPR & TPU_E_TBR_TPR_HOLD_MASK) >> TPU_E_TBR_TPR_HOLD_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE void TPU_E_HWA_HaltEAC(TPU_E_Type *const pTPUE) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_HOLD_MASK) | TPU_E_TBR_TPR_HOLD(1U); +} + +/** + * @brief Get angle ticks number. + * + */ +LOCAL_INLINE uint16_t TPU_E_HWA_GetAngleTicksVal(const TPU_E_Type *const pTPUE) +{ + return (uint16_t)(pTPUE->TBR_TPR & TPU_E_TBR_TPR_TICKS_MASK) >> TPU_E_TBR_TPR_TICKS_SHIFT; +} + +/** + * @brief Get angle ticks number. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetAngleTicksVal(TPU_E_Type *const pTPUE, uint16_t u16Tick) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_TICKS_MASK) | TPU_E_TBR_TPR_TICKS(u16Tick); +} + +/** + * @brief Get the integer part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetIntergerPerAngleTick(const TPU_E_Type *const pTPUE) +{ + return (pTPUE->TBR_TRR & TPU_E_TBR_TRR_INTEGER_MASK) >> TPU_E_TBR_TRR_INTEGER_SHIFT; +} + +/** + * @brief Set the integer part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetIntergerPerAngleTick(TPU_E_Type *const pTPUE, uint16_t u16Integer) +{ + pTPUE->TBR_TRR = (pTPUE->TBR_TRR & ~TPU_E_TBR_TRR_INTEGER_MASK) | TPU_E_TBR_TRR_INTEGER(u16Integer); +} + +/** + * @brief Get the fraction part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetFractionPerAngleTick(const TPU_E_Type *const pTPUE) +{ + return (pTPUE->TBR_TRR & TPU_E_TBR_TRR_FRACTION_MASK) >> TPU_E_TBR_TRR_FRACTION_SHIFT; +} + +/** + * @brief Set the fraction part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFractionPerAngleTick(TPU_E_Type *const pTPUE, uint16_t u16Fraction) +{ + pTPUE->TBR_TRR = (pTPUE->TBR_TRR & ~TPU_E_TBR_TRR_FRACTION_MASK) | TPU_E_TBR_TRR_FRACTION(u16Fraction); +} + +/** + * @brief Get TCR1 overflow flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTCR1Overflow(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_T1MR & TPU_E_TBR_T1MR_OVF_MASK) >> TPU_E_TBR_T1MR_OVF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear TCR1 overflow flag. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearTCR1Overflow(TPU_E_Type *const pTPUE) +{ + pTPUE->TBR_T1MR = (pTPUE->TBR_T1MR | TPU_E_TBR_T1MR_OVF_MASK); +} + +/** + * @brief Get TCR1 IRQ enable flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTCR1OVFIRQEn(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_T1MR & TPU_E_TBR_T1MR_IRQ_EN_MASK) >> TPU_E_TBR_T1MR_IRQ_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TCR1 IRQ enable flag. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableTCR1OVFIRQ(TPU_E_Type *const pTPUE, bool bEn) +{ + pTPUE->TBR_T1MR = (pTPUE->TBR_T1MR & ~TPU_E_TBR_T1MR_IRQ_EN_MASK) | TPU_E_TBR_T1MR_IRQ_EN(bEn); +} + +/** + * @brief Get the maximum value of TCR1 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetTCR1MaxCnt(const TPU_E_Type *const pTPUE) +{ + return (pTPUE->TBR_T1MR & TPU_E_TBR_T1MR_MAX_MASK) >> TPU_E_TBR_T1MR_MAX_SHIFT; +} + +/** + * @brief Get the maximum value of TCR1 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR1MaxCnt(TPU_E_Type *const pTPUE, uint32_t u32MaxCnt) +{ + pTPUE->TBR_T1MR = (pTPUE->TBR_T1MR & ~TPU_E_TBR_T1MR_MAX_MASK) | TPU_E_TBR_T1MR_MAX(u32MaxCnt); +} + +/** + * @brief Get TCR2 overflow flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTCR2Overflow(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_T2MR & TPU_E_TBR_T2MR_OVF_MASK) >> TPU_E_TBR_T2MR_OVF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear TCR2 overflow flag. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearTCR2Overflow(TPU_E_Type *const pTPUE) +{ + pTPUE->TBR_T2MR = (pTPUE->TBR_T2MR | TPU_E_TBR_T2MR_OVF_MASK); +} + +/** + * @brief Get TCR2 IRQ enable flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTCR2OVFIRQEnable(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_T2MR & TPU_E_TBR_T2MR_IRQ_EN_MASK) >> TPU_E_TBR_T2MR_IRQ_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable TCR2 IRQ enable flag. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableTCR2OVFIRQ(TPU_E_Type *const pTPUE, bool bEn) +{ + pTPUE->TBR_T2MR = (pTPUE->TBR_T2MR & ~TPU_E_TBR_T2MR_IRQ_EN_MASK) | TPU_E_TBR_T2MR_IRQ_EN(bEn); +} + +/** + * @brief Get the maximum value of TCR2 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetTCR2MaxCnt(const TPU_E_Type *const pTPUE) +{ + return (pTPUE->TBR_T2MR & TPU_E_TBR_T2MR_MAX_MASK) >> TPU_E_TBR_T2MR_MAX_SHIFT; +} + +/** + * @brief Set the maximum value of TCR2 counter in TCR2 updown mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR2MaxCnt(TPU_E_Type *const pTPUE, uint32_t u32MaxCnt) +{ + pTPUE->TBR_T2MR = (pTPUE->TBR_T2MR & ~TPU_E_TBR_T2MR_MAX_MASK) | TPU_E_TBR_T2MR_MAX(u32MaxCnt); +} + +/** + * @brief Get channel event triggered interrupt enable flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEventIntEnable(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CIE_MASK) >> TPU_E_CHn_CR_CIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable channel event triggered interrupt. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableChEventInt(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CIE_MASK) | TPU_E_CHn_CR_CIE(bEn); +} + +/** + * @brief Get channel event triggered interrupt priority. + * + */ +LOCAL_INLINE TPUE_EventIntPriorityType TPU_E_HWA_GetChEventIntPriority(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CPR_MASK) >> TPU_E_CHn_CR_CPR_SHIFT; + return (TPUE_EventIntPriorityType)u32TmpVal; +} + +/** + * @brief Set channel event triggered interrupt priority. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEventIntPriority(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_EventIntPriorityType ePriority) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CPR_MASK) | TPU_E_CHn_CR_CPR(ePriority); +} + +/** + * @brief Get channel Filter Bypass + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChFilterBypassEnable(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CFB_MASK) >> TPU_E_CHn_CR_CFB_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel Filter Bypass + * + */ +LOCAL_INLINE void TPU_E_HWA_OpenChFilter(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CFB_MASK) | TPU_E_CHn_CR_CFB(bEn); +} + +/** + * @brief Get channel entry function + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetChEntryFunc(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CFS_MASK) >> TPU_E_CHn_CR_CFS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set channel entry function + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryFunc(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint8_t u8EntryFunc) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CFS_MASK) | TPU_E_CHn_CR_CFS(u8EntryFunc); +} + +/** + * @brief Get channel entry table pin direction + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEntryTblPinDirOutput(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_ETPD_MASK) >> TPU_E_CHn_CR_ETPD_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel entry table pin direction + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryTblPinDirOutput(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_ETPD_MASK) | TPU_E_CHn_CR_ETPD(bEn); +} + +/** + * @brief Get channel entry table condition select + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEntryTblCondSelAlt(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_ECTS_MASK) >> TPU_E_CHn_CR_ECTS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel entry table condition select + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryTblCondSelAlt(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_ECTS_MASK) | TPU_E_CHn_CR_ECTS(bEn); +} + +/** + * @brief Get channel entry table flag1 + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEntryTblflag1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_FLG1_MASK) >> TPU_E_CHn_CR_FLG1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel entry table flag1 + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryTblflag1(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_FLG1_MASK) | TPU_E_CHn_CR_FLG1(bEn); +} + +/** + * @brief Get channel entry table flag0 + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEntryTblflag0(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_FLG0_MASK) >> TPU_E_CHn_CR_FLG0_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel entry table flag0 + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryTblflag0(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_FLG0_MASK) | TPU_E_CHn_CR_FLG0(bEn); +} + +/** + * @brief Get channel output polarity + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChOutputHigh(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_OPOL_MASK) >> TPU_E_CHn_CR_OPOL_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel output polarity + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChOutputActiveHigh(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_OPOL_MASK) | TPU_E_CHn_CR_OPOL(bEn); +} + +/** + * @brief Get channel output disable + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChOutputDisable(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_ODIS_MASK) >> TPU_E_CHn_CR_ODIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel output disable + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChOutputDisable(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_ODIS_MASK) | TPU_E_CHn_CR_ODIS(bEn); +} + +/** + * @brief Get channel HSA index. + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetChHSAIdx(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CHSA_MASK) >> TPU_E_CHn_CR_CHSA_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set channel HSA index. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChHSAIdx(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint8_t u8HSAIdx) +{ + pTPUE->CH[u8Channel].CR = ((pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CHSA_MASK) | TPU_E_CHn_CR_CHSA(u8HSAIdx)); +} + +/** + * @brief Get channel event trigger interrupt status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEventTrigISRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CIS_MASK) >> TPU_E_CHn_SR_CIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel host service request (HSR) status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChHSRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CHRS_MASK) >> TPU_E_CHn_SR_CHRS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Channel HSR Info & Index . + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetChHSRIdx(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CHRI_MASK) >> TPU_E_CHn_SR_CHRI_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get channel event as interrupt status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEventReqISRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CEIS_MASK) >> TPU_E_CHn_SR_CEIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel event as interrupt status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChDMAReq(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CHDS_MASK) >> TPU_E_CHn_SR_CHDS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel trigger status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTrigStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CTS_MASK) >> TPU_E_CHn_SR_CTS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel host service acknowledge (HSA) interrupt status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChHSAReqStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CHAS_MASK) >> TPU_E_CHn_SR_CHAS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear channel interrupt by event. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearChEventISRFlg(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].SCR = TPU_E_CHn_SCR_CISC_MASK; +} + +/** + * @brief Clear channel HSA Dma. + * + */ +LOCAL_INLINE void TPU_E_HWA_ChReqDMA(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].SCR = TPU_E_CHn_SCR_CHDT_MASK; +} + +/** + * @brief Clear channel HSA. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearChHSAISR(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].SCR = TPU_E_CHn_SCR_CHAT_MASK; +} + +/** + * @brief Clear channel HSR. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearChHSR(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].SCR = TPU_E_CHn_SCR_CHRC_MASK; +} + +/** + * @brief Get channel service request. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChServiceReq(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_CSR_MASK) >> TPU_E_CHn_EFR_CSR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel service request to HOST. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChServiceReqToHost(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_CHSR_MASK) >> TPU_E_CHn_EFR_CHSR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 event status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch1Event(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_EMRL1_MASK) >> TPU_E_CHn_EFR_EMRL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 event status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch2Event(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_EMRL2_MASK) >> TPU_E_CHn_EFR_EMRL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get transition detect latch 1 event status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTransDetectLatch1Event(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_ETDL1_MASK) >> TPU_E_CHn_EFR_ETDL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get transition detect latch 2 event status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTransDetectLatch2Event(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_ETDL2_MASK) >> TPU_E_CHn_EFR_ETDL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch1En(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_MRLE1_MASK) >> TPU_E_CHn_EFR_MRLE1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch2En(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_MRLE2_MASK) >> TPU_E_CHn_EFR_MRLE2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch1Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_MRL1_MASK) >> TPU_E_CHn_EFR_MRL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch2Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_MRL2_MASK) >> TPU_E_CHn_EFR_MRL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Transition Detect latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTransDetectLatch1Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_TDL1_MASK) >> TPU_E_CHn_EFR_TDL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Transition Detect latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTransDetectLatch2Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_TDL2_MASK) >> TPU_E_CHn_EFR_TDL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get comparator selection for time base selection. + * + */ +LOCAL_INLINE TPUE_TimeBaseSelctionType TPU_E_HWA_GetChTBS1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_TBS1_MASK) >> TPU_E_CHn_CR2_TBS1_SHIFT; + return (TPUE_TimeBaseSelctionType)u32TmpVal; +} + +/** + * @brief Set comparator selection for time base selection. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChTBS1(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_TimeBaseSelctionType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_TBS1_MASK) | TPU_E_CHn_CR2_TBS1(eType); +} + +/** + * @brief Get pin state input. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChPinStateInputHigh(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_PSTI_MASK) >> TPU_E_CHn_CR2_PSTI_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin state output. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChPinStateOutputHigh(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_PSTO_MASK) >> TPU_E_CHn_CR2_PSTO_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin request service sample. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChPinReqSrvSample(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_PRSS_MASK) >> TPU_E_CHn_CR2_PRSS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Input Pin Action Control of Part 1 . + * + */ +LOCAL_INLINE TPUE_IPACType TPU_E_HWA_GetIPAC1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_IPAC1_MASK) >> TPU_E_CHn_CR2_IPAC1_SHIFT; + return (TPUE_IPACType)u32TmpVal; +} + +/** + * @brief Set Input Pin Action Control of Part 1 . + * + */ +LOCAL_INLINE void TPU_E_HWA_SetIPAC1(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_IPACType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_IPAC1_MASK) | TPU_E_CHn_CR2_IPAC1(eType); +} + +/** + * @brief Get Output Buffer Enable. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChOutputBufEn(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_OBE_MASK) >> TPU_E_CHn_CR2_OBE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Output Buffer Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableChOutputBuf(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEnable) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_OBE_MASK) | TPU_E_CHn_CR2_OBE(bEnable); +} + +/** + * @brief Get Output Pin Action Control of Part 1. + * + */ +LOCAL_INLINE TPUE_OPACType TPU_E_HWA_GetOPAC1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_OPAC1_MASK) >> TPU_E_CHn_CR2_OPAC1_SHIFT; + return (TPUE_OPACType)u32TmpVal; +} + +/** + * @brief Set Input Pin Action Control of Part 2 . + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOPAC1(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_OPACType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_OPAC1_MASK) | TPU_E_CHn_CR2_OPAC1(eType); +} + +/** + * @brief Get comparator selection for time base selection. + * + */ +LOCAL_INLINE TPUE_TimeBaseSelctionType TPU_E_HWA_GetChTBS2(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_TBS2_MASK) >> TPU_E_CHn_CR2_TBS2_SHIFT; + return (TPUE_TimeBaseSelctionType)u32TmpVal; +} + +/** + * @brief Set comparator selection for time base selection. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChTBS2(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_TimeBaseSelctionType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_TBS2_MASK) | TPU_E_CHn_CR2_TBS2(eType); +} + +/** + * @brief Get Input Pin Action Control of Part 2. + * + */ +LOCAL_INLINE TPUE_IPACType TPU_E_HWA_GetIPAC2(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_IPAC2_MASK) >> TPU_E_CHn_CR2_IPAC2_SHIFT; + return (TPUE_IPACType)u32TmpVal; +} + +/** + * @brief Set Input Pin Action Control of Part 2. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetIPAC2(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_IPACType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_IPAC2_MASK) | TPU_E_CHn_CR2_IPAC2(eType); +} + +/** + * @brief Get Output Pin Action Control of Part 1. + * + */ +LOCAL_INLINE TPUE_OPACType TPU_E_HWA_GetOPAC2(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_OPAC2_MASK) >> TPU_E_CHn_CR2_OPAC2_SHIFT; + return (TPUE_OPACType)u32TmpVal; +} + +/** + * @brief Set Input Pin Action Control of Part 2 . + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOPAC2(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_OPACType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_OPAC2_MASK) | TPU_E_CHn_CR2_OPAC2(eType); +} + +/** + * @brief Clear sevice request write enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearSrvReqEn(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR | TPU_E_CHn_MR_SRIE_MASK); +} + +/** + * @brief Get service request inhibit latch. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetSrvReqEn(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_SRI_MASK) >> TPU_E_CHn_MR_SRI_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Set service request inhibit latch. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableSrvReq(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + if (bEn) + { + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & ~TPU_E_CHn_MR_SRI_MASK) | TPU_E_CHn_MR_SRIE_MASK; + } + else + { + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_SRI_MASK) | TPU_E_CHn_MR_SRIE_MASK; + } + +} + +/** + * @brief Clear PDCM Write Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearPDCMEn(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR | TPU_E_CHn_MR_PDME_MASK); +} + +/** + * @brief Get Predefined Channel Mode. + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetPDCM(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_PDCM_MASK) >> TPU_E_CHn_MR_PDCM_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set Predefined Channel Mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetPDCM(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_PDCMEncodeType eMode) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & ~TPU_E_CHn_MR_PDCM_MASK) | TPU_E_CHn_MR_PDCM(eMode) | TPU_E_CHn_MR_PDME_MASK; +} + +/** + * @brief Get transition continuous capture enable. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTransContinueEn(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_TCCE_MASK) >> TPU_E_CHn_MR_TCCE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set Predefined Channel Mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableTransContinue(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & ~TPU_E_CHn_MR_TCCE_MASK) | TPU_E_CHn_MR_TCCE(bEn); +} + +/** + * @brief Clear UDCM Write Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearUDCMWriteEn(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR | TPU_E_CHn_MR_UDME_MASK); +} + +/** + * @brief Get User Defined Channel Mode. + * + */ +LOCAL_INLINE uint16_t TPU_E_HWA_GetUDCM(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_UDCM_MASK) >> TPU_E_CHn_MR_UDCM_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set User Defined Channel Mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableUDCM(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint16_t u16Mode) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & ~TPU_E_CHn_MR_UDCM_MASK) | TPU_E_CHn_MR_UDCM(u16Mode) | TPU_E_CHn_MR_UDME_MASK; +} + +/** + * @brief Clear Match Configuration Enable part1. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatchEn1(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 | TPU_E_CHn_ER1_ERW_MASK); +} + +/** + * @brief Get User Defined Channel Mode part1. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMatchEn(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].ER1 & TPU_E_CHn_ER1_MEF_MASK) >> TPU_E_CHn_ER1_MEF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set User Defined Channel Mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableMatch(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_MEF_MASK) | TPU_E_CHn_ER1_MEF(bEn); +} + +/** + * @brief Set ER1 value for match. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetMatchER1(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint32_t u32ER1) +{ + uint32_t u32Temp; + u32Temp = pTPUE->CH[u8Channel].ER1 | TPU_E_CHn_ER1_ERS_MASK; + pTPUE->CH[u8Channel].ER1 = (u32Temp & ~TPU_E_CHn_ER1_ER1_MASK) | TPU_E_CHn_ER1_ER1(u32ER1) | TPU_E_CHn_ER1_ERW_MASK; +} + +/** + * @brief Set ER1 value for capture. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetCaptureER1(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint32_t u32ER1) +{ + uint32_t u32Temp; + u32Temp = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_ERS_MASK) | TPU_E_CHn_ER1_ERS(0U); + pTPUE->CH[u8Channel].ER1 = (u32Temp & ~TPU_E_CHn_ER1_ER1_MASK) | TPU_E_CHn_ER1_ER1(u32ER1) | TPU_E_CHn_ER1_ERW_MASK; +} + +/** + * @brief Get Capture/Match Select for Value of ER1/ER2. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMatchSelForERx(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].ER1 & TPU_E_CHn_ER1_ERS_MASK) >> TPU_E_CHn_ER1_ERS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get ER1 value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetER1Val(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].ER1 & TPU_E_CHn_ER1_ER1_MASK) >> TPU_E_CHn_ER1_ER1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get ER1 value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetCaptureER1Val(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_ERS_MASK) | TPU_E_CHn_ER1_ERS(0U); + u32TmpVal = (pTPUE->CH[u8Channel].ER1 & TPU_E_CHn_ER1_ER1_MASK) >> TPU_E_CHn_ER1_ER1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set ER1 value. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetER1(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint32_t u32ER1) +{ + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_ER1_MASK) | TPU_E_CHn_ER1_ER1(u32ER1) | TPU_E_CHn_ER1_ERW_MASK; +} + +/** + * @brief Clear Match Configuration Enable part2. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatchEn2(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ER2 = (pTPUE->CH[u8Channel].ER2 | TPU_E_CHn_ER2_ERW_MASK); +} + +/** + * @brief Get ER2 value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetER2Val(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].ER2 & TPU_E_CHn_ER2_ER2_MASK) >> TPU_E_CHn_ER2_ER2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get ER2 value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetCaptureER2Val(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_ERS_MASK); + u32TmpVal = (pTPUE->CH[u8Channel].ER2 & TPU_E_CHn_ER2_ER2_MASK) >> TPU_E_CHn_ER2_ER2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set ER2 value. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetER2(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint32_t u32ER2) +{ + pTPUE->CH[u8Channel].ER2 = (pTPUE->CH[u8Channel].ER2 & ~TPU_E_CHn_ER2_ER2_MASK) | TPU_E_CHn_ER2_ER2(u32ER2) | TPU_E_CHn_ER2_ERW_MASK; +} + +/** + * @brief Clear Match1 Configuration Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatch1CFGFlg(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_MRE1_CLR_MASK; +} + +/** + * @brief Clear Match1 event Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatch1Event(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_MRL1_CLR_MASK; +} + +/** + * @brief Clear transition detect1 Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearTransDetect1Event(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_TDL1_CLR_MASK; +} + +/** + * @brief Clear Match2 Configuration Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatch2CFGFlg(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_MRE2_CLR_MASK; +} + +/** + * @brief Clear Match2 event Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatch2Event(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_MRL2_CLR_MASK; +} + +/** + * @brief Clear transition detect2 Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearTransDetect2Event(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_TDL2_CLR_MASK; +} + +/** + * @brief Get output user control, high or low select. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetOutputSelHigh(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].OCR & TPU_E_CHn_OCR_OUT_HIS_MASK) >> TPU_E_CHn_OCR_OUT_HIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear output user control. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOutputSelHigh(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].OCR = TPU_E_CHn_OCR_OUT_HIS(bEn); +} + +/** + * @brief Get output user control, select OPAC1. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetOutputUsrCtrlSelOPAC1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].OCR & TPU_E_CHn_OCR_OUT_OP1_MASK) >> TPU_E_CHn_OCR_OUT_OP1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set output user control, select OPAC1. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOutputSelOPAC1(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].OCR = (pTPUE->CH[u8Channel].OCR & ~TPU_E_CHn_OCR_OUT_OP1_MASK) | TPU_E_CHn_OCR_OUT_OP1(bEn); +} + +/** + * @brief Get output user control, select OPAC2. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetOutputUsrCtrlSelOPAC2(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].OCR & TPU_E_CHn_OCR_OUT_OP2_MASK) >> TPU_E_CHn_OCR_OUT_OP2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set output user control, select OPAC2. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOutputSelOPAC2(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].OCR = (pTPUE->CH[u8Channel].OCR & ~TPU_E_CHn_OCR_OUT_OP2_MASK) | TPU_E_CHn_OCR_OUT_OP2(bEn); +} + +#endif /* #ifndef _HWA_TPUE_H_ */ diff --git a/Inc/HwA_tpuh.h b/Inc/HwA_tpuh.h new file mode 100644 index 0000000..d23a900 --- /dev/null +++ b/Inc/HwA_tpuh.h @@ -0,0 +1,902 @@ +/** + * @file HwA_tpuh.h + * @author Flagchip + * @brief FC7xxx TPUH hardware access layer + * @version 0.1.0 + * @date 2024-1-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +#ifndef _HWA_TPUH_H_ +#define _HWA_TPUH_H_ + +#include "device_header.h" +#if 1 +/********* Local typedef ************/ +/** @brief TPU TCR1 clock control mode type */ +typedef enum +{ + TPUH_CLK_SRC_TCRCLK = 0U, + UTPUH_PDOWN_CNT_MODE = 3U, + TPUH_CLK_SRC_TPUCLKDIV2 = 4U, + TPUH_CLK_SRC_TPUCLK = 5U +} TPUH_TCR1ClkCtrlModeType; + +/** @brief TPU angle tick gen clk type */ +typedef enum +{ + TPUH_TCR1_PRESCAL_OUTPUT = 0U, + TPUH_TCR2_PRESCAL_OUTPUT = 1U +} TPUH_AngleTickGenClkType; + +/** @brief TPU Angle Mode Selection type */ +typedef enum +{ + TPUH_TCR2_TIMEBASE_EAC_DISABLE = 0U, + TPUH_TOOTHSIGNAL_AS_TCRCLK_TOOTH_CH_0 = 1U, + TPUH_TOOTHSIGNAL_AS_CH1INPUT_TOOTH_CH_1 = 2U, + TPUH_TOOTHSIGNAL_AS_CH2INPUT_TOOTH_CH_2 = 3U +} TPUH_AngleModeSel; + +/** @brief TPU Angle Mode Selection type */ +typedef enum +{ + TPUH_TWO_SAMPLE_MODE_TPU_CLK_DIV2 = 0U, + TPUH_TWO_SAMPLE_MODE_CH_CLK = 1U, + TPUH_INTEGRATOR_MODE_TPU_CLK_DIV2 = 2U, + TPUH_INTEGRATOR_MODE_CH_CLK = 3U +} TPUH_TCRClkFilterType; + +/** @brief TPU TCR2 clock control mode0 type */ +typedef enum +{ + TPUH_GATED_DIV8_CLK = 0U, + TPUH_RISE_TRANSITION_INCREMENT_TCR2_PRESCALER = 1U, + TPUH_FALL_TRANSITION_INCREMENT_TCR2_PRESCALER = 2U, + TPUH_DIV8_CLK = 4U, + TPUH_UPDOWN_CNT_MODE = 5U, + TPUH_FROZEN = 7U +} TPUH_TCR1ClkCtrlMode0Type; + +typedef enum +{ + TPUH_RSING_EDGE = 1U, + TPUH_FALLING_EDGE = 2U, + TPUH_BOTH_EDGES = 3U, + TPUH_NO_EDGE = 6U, +} TPUH_TCR1ClkCtrlMode1Type; + +/** @brief Missing Tooth Counter */ +typedef enum +{ + TPUH_NOT_A_MISSING_TOOTH = 0U, + TPUH_ONE_MISSING_TOOTH = 1U, + TPUH_TWO_MISSING_TOOTH = 2U, + TPUH_THREE_MISSING_TOOTH = 3U, +} TPUH_MissToothCntType; + +/** @brief Channel Trigger Configuration */ +typedef enum +{ + TPUH_DISABLED = 0U, + TPUH_ANY_EVENT_GATED_BY_MSRTSR = 2U, + TPUH_HSA_EVENT_ON_FLEXCORE_MODE = 3U, + TPUH_MRL1_EVENT_NOT_GATED_BY_MSR = 4U, + TPUH_MRL2_EVENT_NOT_GATED_BY_MSR = 5U, + TPUH_MRL1_OR_MRL2_EVENT_NOT_GATED_BY_MSR = 6U, + TPUH_MRL1_AND_MRL2_EVENT_NOT_GATED_BY_MSR = 7U, + TPUH_TDL1_OR_TDL2_EVENT_NOT_GATED_BY_TSR = 8U, + TPUH_TDL1_AND_TDL2_EVENT_NOT_GATED_BY_TSR = 9U, + TPUH_EVENT_EQUAL_TO_CH_DO_LEVEL = 10U, + TPUH_EVENT_NEGATIVE_TO_CH_DO_LEVEL = 11U, + TPUH_EVENT_EQUAL_TO_CH_DO_PART1_LEVEL = 12U, + TPUH_EVENT_EQUAL_TO_CH_DO_PART2_LEVEL = 13U, + TPUH_EVENT_EQUAL_TO_CH_IND_LEVEL = 14U, + TPUH_EVENT_EQUAL_TO_CH_IND_LATCH_LEVEL = 15U, +} TPUH_ChTrigCFGType; +#endif +/********* Local inline function ************/ +/** + * @brief Get service request status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetSRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VSR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin input status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetInputStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VIR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin output status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetoutputStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VOR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin output enable status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetoutputEnStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VOBR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL1 status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetMRL1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VM1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL2 status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetMRL2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VM2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL1 status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTDL1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VT1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL2 status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTDL2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VT2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL1 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetMRL1EventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_EM1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL2 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetMRL2EventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_EM2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL1 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTDL1eventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_ET1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL2 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTDL2eventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_ET2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get HAS status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetHASStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VHSR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TCR1 prescaler. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1Prescaler(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR1P_MASK) >> TPU_H_TBR_CR_TCR1P_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get TCR1 clock control. + * + */ +LOCAL_INLINE TPUH_TCR1ClkCtrlModeType TPU_H_HWA_GetTCR1ClkControl(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR1CTL_MASK) >> TPU_H_TBR_CR_TCR1CTL_SHIFT; + return (TPUH_TCR1ClkCtrlModeType)u32TmpVal; +} + +/** + * @brief Get TCR2 prescaler. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2Prescaler(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2P_MASK) >> TPU_H_TBR_CR_TCR2P_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get Angle tick generator clock. + * + */ +LOCAL_INLINE TPUH_AngleTickGenClkType TPU_H_HWA_GetATGC(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_ATGC_MASK) >> TPU_H_TBR_CR_ATGC_SHIFT; + return (TPUH_AngleTickGenClkType)u32TmpVal; +} + +/** + * @brief Get Angle Mode Selection. + * + */ +LOCAL_INLINE TPUH_AngleModeSel TPU_H_HWA_GetAM(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_AM_MASK) >> TPU_H_TBR_CR_AM_SHIFT; + return (TPUH_AngleModeSel)u32TmpVal; +} + +/** + * @brief Get TCRCLK signal Filter Control. + * + */ +LOCAL_INLINE TPUH_TCRClkFilterType TPU_H_HWA_GetTCRClkFilter(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCRCF_MASK) >> TPU_H_TBR_CR_TCRCF_SHIFT; + return (TPUH_TCRClkFilterType)u32TmpVal; +} + +/** + * @brief Get TCR2 clock control. + * + */ +LOCAL_INLINE TPUH_TCR1ClkCtrlMode0Type TPU_H_HWA_GetTCR2ClkControlAM0(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2CTL_MASK) >> TPU_H_TBR_CR_TCR2CTL_SHIFT; + return (TPUH_TCR1ClkCtrlMode0Type)u32TmpVal; +} + +/** + * @brief Get TCR2 clock control. + * + */ +LOCAL_INLINE TPUH_TCR1ClkCtrlMode1Type TPU_H_HWA_GetTCR2ClkControlAM1(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2CTL_MASK) >> TPU_H_TBR_CR_TCR2CTL_SHIFT; + return (TPUH_TCR1ClkCtrlMode1Type)u32TmpVal; +} + +/** + * @brief Get TCR1 cnt value. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1CntVal(const TPU_H_Type *const pTPUH) +{ + return pTPUH->TBR_T1R; +} + +/** + * @brief Get TCR2 cnt value. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2CntVal(const TPU_H_Type *const pTPUH) +{ + return pTPUH->TBR_T2R; +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_H_HWA_NotLastTooth(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_LAST_MASK) >> TPU_H_TBR_TPR_LAST_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Get missing tooth counter. + * + */ +LOCAL_INLINE TPUH_MissToothCntType TPU_H_HWA_GetMissingTooth(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_MISSCNT_MASK) >> TPU_H_TBR_TPR_MISSCNT_SHIFT; + return (TPUH_MissToothCntType)u32TmpVal; +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_H_HWA_NoInsertTooth(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_IPH_MASK) >> TPU_H_TBR_TPR_IPH_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_H_HWA_NoForceEACHalt(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_HOLD_MASK) >> TPU_H_TBR_TPR_HOLD_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Get angle ticks number. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetAngleTicksVal(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_TPR & TPU_H_TBR_TPR_TICKS_MASK) >> TPU_H_TBR_TPR_TICKS_SHIFT; +} + +/** + * @brief Get the integer part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetIntergerPerAngleTick(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_TRR & TPU_H_TBR_TRR_INTEGER_MASK) >> TPU_H_TBR_TRR_INTEGER_SHIFT; +} + +/** + * @brief Get the fraction part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetFractionPerAngleTick(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_TRR & TPU_H_TBR_TRR_FRACTION_MASK) >> TPU_H_TBR_TRR_FRACTION_SHIFT; +} + +/** + * @brief Get TCR1 overflow flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTCR1Overflow(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_OVF_MASK) >> TPU_H_TBR_T1MR_OVF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TCR1 IRQ enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_TCR1IRQEnable(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_IRQ_EN_MASK) >> TPU_H_TBR_T1MR_IRQ_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the maximum value of TCR1 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1MaxCnt(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_MAX_MASK) >> TPU_H_TBR_T1MR_MAX_SHIFT; +} + +/** + * @brief Get TCR2 overflow flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_TCR2Overflow(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_OVF_MASK) >> TPU_H_TBR_T2MR_OVF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TCR2 IRQ enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_TCR2IRQEnable(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_IRQ_EN_MASK) >> TPU_H_TBR_T2MR_IRQ_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the maximum value of TCR2 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2MaxCnt(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_MAX_MASK) >> TPU_H_TBR_T2MR_MAX_SHIFT; +} + +/** + * @brief Get channel HSA enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChHSAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHAE_MASK) >> TPU_H_CHn_CR_CHAE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel HSA enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChHSA(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHAE_MASK) | TPU_H_CHn_CR_CHAE(benable)); +} + +/** + * @brief Set channel event trigger dma enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChEventDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CDFD_MASK) | TPU_H_CHn_CR_CDFD(benable)); +} + +/** + * @brief Set channel request Dma enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChReqDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHDE_MASK) | TPU_H_CHn_CR_CHDE(benable)); +} + +/** + * @brief Get channel HSR Dma request enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChDMAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHDE_MASK) >> TPU_H_CHn_CR_CHDE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel Sync isr from flexcore enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChSyncISR(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHEE_MASK) | TPU_H_CHn_CR_CHEE(benable)); +} + +/** + * @brief Get channel HSR event as interrupt enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChHSRISREnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHEE_MASK) >> TPU_H_CHn_CR_CHEE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel channel HSR event as interrupt enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChHSRISR(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHEE_MASK) | TPU_H_CHn_CR_CHEE(benable)); +} + +/** + * @brief Get channel trigger configuration. + * + */ +LOCAL_INLINE TPUH_ChTrigCFGType TPU_H_HWA_GetChTrigCondition(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CTC_MASK) >> TPU_H_CHn_CR_CTC_SHIFT; + return (TPUH_ChTrigCFGType)u32TmpVal; +} + +/** + * @brief Set channel trigger configuration. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChTrig(TPU_H_Type *const pTPUH, uint8_t u8Channel, TPUH_ChTrigCFGType etrgcfg) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CTC_MASK) | TPU_H_CHn_CR_CTC(etrgcfg)); +} + +/** + * @brief Get channel trigger DMA enable. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTrigDMAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CDFD_MASK) >> TPU_H_CHn_CR_CDFD_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel trigger DMA enable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChTrigDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CDFD_MASK) | TPU_H_CHn_CR_CDFD(benable)); +} + +/** + * @brief Get channel HSR index. + * + */ +LOCAL_INLINE uint8 TPU_H_HWA_GetChHSRIdx(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHSR_MASK) >> TPU_H_CHn_CR_CHSR_SHIFT; + return (uint8)u32TmpVal; +} + +/** + * @brief Get channel HSR index. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChHSRIdx(TPU_H_Type *const pTPUH, uint8_t u8Channel, uint8_t u8HSRIdx) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHSR_MASK) | TPU_H_CHn_CR_CHSR(u8HSRIdx)); +} + +/** + * @brief Get channel event trigger interrupt status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChEventTrigISRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CIS_MASK) >> TPU_H_CHn_SR_CIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel host service request (HSR) status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChHSRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (uint8_t)(pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHRS_MASK) >> TPU_H_CHn_SR_CHRS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get HSA. + * + */ +LOCAL_INLINE uint8 TPU_H_HWA_GetChHSAIdx(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHRI_MASK) >> TPU_H_CHn_SR_CHRI_SHIFT; + return (uint8_t)u32TmpVal; +} + + +/** + * @brief Get channel event as interrupt status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChDMAReq(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHDS_MASK) >> TPU_H_CHn_SR_CHDS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel trigger status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTrigStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CTS_MASK) >> TPU_H_CHn_SR_CTS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel host service acknowledge (HSA) interrupt status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChHSAReqStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHAS_MASK) >> TPU_H_CHn_SR_CHAS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear channel interrupt by event. + * + */ +LOCAL_INLINE void TPU_H_HWA_ClearChEventISRFlg(TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CEIC_MASK; +} + +/** + * @brief Clear channel HSA. + * + */ +LOCAL_INLINE void TPU_H_HWA_ClearChHSA(TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CHAC_MASK; +} + +/** + * @brief Clear channel HSR. + * + */ +LOCAL_INLINE void TPU_H_HWA_ClearChHSR(TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CHRT_MASK; +} + +/** + * @brief Get channel service request. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChServiceReq(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_CSR_MASK) >> TPU_H_CHn_EFR_CSR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel service request to HOST. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChServiceReqToHost(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_CHSR_MASK) >> TPU_H_CHn_EFR_CHSR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 event status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_EMRL1_MASK) >> TPU_H_CHn_EFR_EMRL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 event status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_EMRL2_MASK) >> TPU_H_CHn_EFR_EMRL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get transition detect latch 1 event status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch1Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_ETDL1_MASK) >> TPU_H_CHn_EFR_ETDL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get transition detect latch 2 event status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch2Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_ETDL2_MASK) >> TPU_H_CHn_EFR_ETDL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1En(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRLE1_MASK) >> TPU_H_CHn_EFR_MRLE1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2En(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRLE2_MASK) >> TPU_H_CHn_EFR_MRLE2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRL1_MASK) >> TPU_H_CHn_EFR_MRL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRL2_MASK) >> TPU_H_CHn_EFR_MRL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Transition Detect latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_TDL1_MASK) >> TPU_H_CHn_EFR_TDL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Transition Detect latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_TDL2_MASK) >> TPU_H_CHn_EFR_TDL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + + +#endif /* #ifndef _HWA_TPUH_H_ */ diff --git a/Inc/HwA_trgsel.h b/Inc/HwA_trgsel.h new file mode 100644 index 0000000..7ba17ae --- /dev/null +++ b/Inc/HwA_trgsel.h @@ -0,0 +1,150 @@ +/** + * @file HwA_trgsel.h + * @author Flagchip0103 + * @brief Hardware access layer for TrgSel + * @version 0.1.0 + * @date 2023-12-19 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-19 Flagchip0103 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_TRGSEL_H_ +#define _HWA_TRGSEL_H_ + +#include "device_header.h" + +#define TRGSEL_REGSIZE 4U + +/** + * @brief Get the trigger source of the selected trigger target + * + * @param pTrgsel the base address of the TrgSel instance + * @param u32TargetIndex the trigger target to get the trigger source + * @return uint32_t the trigger source of the selected trigger target + */ +LOCAL_INLINE uint32_t TRGSEL_HWA_GetTargetTriggerSource(const TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex) +{ + uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE; + uint32_t u32SelIdx = u32TargetIndex % TRGSEL_REGSIZE; + + uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx]; + switch (u32SelIdx) + { + case 0U: + { + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_0_MASK) >> TRGSEL_OUT_SEL_SEL_0_SHIFT; + break; + } + case 1U: + { + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_1_MASK) >> TRGSEL_OUT_SEL_SEL_1_SHIFT; + break; + } + case 2U: + { + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_2_MASK) >> TRGSEL_OUT_SEL_SEL_2_SHIFT; + break; + } + case 3U: + { + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_3_MASK) >> TRGSEL_OUT_SEL_SEL_3_SHIFT; + break; + } + + default: + break; + } + + return (uint32_t)u32Tmp; +} + +/** + * @brief Set the trigger source of the selected trigger target + * + * @param pTrgsel the base address of the TrgSel instance + * @param u32TargetIndex the trigger target to set the trigger source + * @param u32SourceIndex the selected trigger source to trig the target + */ +LOCAL_INLINE void TRGSEL_HWA_SetTargetTriggerSource(TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex, + uint32_t u32SourceIndex) +{ + uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE; + uint32_t u32SelIdx = u32TargetIndex % TRGSEL_REGSIZE; + uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx]; + + switch (u32SelIdx) + { + case 0U: + { + u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_0_MASK) | TRGSEL_OUT_SEL_SEL_0(u32SourceIndex); + break; + } + case 1U: + { + u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_1_MASK) | TRGSEL_OUT_SEL_SEL_1(u32SourceIndex); + break; + } + case 2U: + { + u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_2_MASK) | TRGSEL_OUT_SEL_SEL_2(u32SourceIndex); + break; + } + case 3U: + { + u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_3_MASK) | TRGSEL_OUT_SEL_SEL_3(u32SourceIndex); + break; + } + + default: + break; + } + + pTrgsel->OUT_SEL[u32RegIdx] = u32Tmp; +} + +/** + * @brief Get wether the trigger source of the selected target is locked + * + * @param pTrgsel the base address of the TrgSel instance + * @param u32TargetIndex the trigger target to get the lock status + * @return true the trigger source of the selected target cannot be modified + * @return false the trigger source of the selected target can be modified + */ +LOCAL_INLINE bool TRGSEL_HWA_GetTargetLockStatus(const TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex) +{ + uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE; + + uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx]; + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_LOCK_MASK) >> TRGSEL_OUT_SEL_LOCK_SHIFT; + + return (bool)((u32Tmp != 0U) ? true : false); +} + +/** + * @brief Lock the trigger source of the selected target + * + * @note The trigger target is grouped by four, so if you lock the trigger source of one target, the + * adjacent three trigger targets in the same register group are also be locked. So please ensure the + * trigger sources are not to be modified before lock the trigger target. + * + * @param pTrgsel the base address of the TrgSel instance + * @param u32TargetIndex the trigger target to lock the trigger source + */ +LOCAL_INLINE void TRGSEL_HWA_LockTargetTriggerSource(TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex) +{ + uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE; + + pTrgsel->OUT_SEL[u32RegIdx] |= TRGSEL_OUT_SEL_LOCK_MASK; +} + +/** @}*/ + +#endif /* _HWA_TRGSEL_H_ */ diff --git a/Inc/HwA_tstmp.h b/Inc/HwA_tstmp.h new file mode 100644 index 0000000..830fcd9 --- /dev/null +++ b/Inc/HwA_tstmp.h @@ -0,0 +1,222 @@ +/** + * @file HwA_tstmp.h + * @author Flagchip + * @brief FC7xxx TSTMP hardware access layer + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +/******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 Flagchip0122 N/A FC7xxx internal release version + ********************************************************************************/ + + +#ifndef _HWA_TSTMP_H_ +#define _HWA_TSTMP_H_ + +#include "device_header.h" +/********* Local typedef ************/ +/** @brief Tstmp modulate number */ +typedef enum +{ + TSTMP_MOD0 = 0U, + TSTMP_MOD1, + TSTMP_MOD2, + TSTMP_MOD3, +} TSTMP_ModulateType; + +/** @brief Tstmp running mode */ +typedef enum +{ + TSTMP_MODE_ALWAYS_RUNNING = 0U, + TSTMP_MODE_PERIOD_RUNNING = 1U +} TSTMP_ModeCounterRunningMode; + +typedef enum +{ + TSTMP_SIRC1M_CLK = 0U, + TSTMP_AON_CLK = 1U +} TSTMP_ClockSourceType; +/********* Local inline function ************/ +/** + * @brief Read TSTMP value + * + * @param pTstmp TSTMP instance + * @return TSTMP value + */ +LOCAL_INLINE uint64_t TSTMP_HWA_ReadTstmpValue(TSTMP_Type *pTstmp) +{ + uint32_t u32TstmpL, u32TstmpH; + uint64_t u64TempValue; + u32TstmpL = pTstmp->VALL; + u32TstmpH = pTstmp->VALH; + + u64TempValue = u32TstmpH; + u64TempValue = (u64TempValue << 32U) + u32TstmpL; + return u64TempValue; +} + +/** + * @brief Read TSTMP interrupt enable bits + * + * @param pTstmp TSTMP instance + * @return TSTMP interrupt enable bits + */ +LOCAL_INLINE uint32_t TSTMP_HWA_ReadTstmpInterruptEnable(TSTMP_Type *pTstmp) +{ + return (uint32_t)pTstmp->MOD_INTEN; +} + +/** + * @brief Enable TSTMP MOD(n) match interrupt + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_EnableModMatchInterrupt(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod) +{ + pTstmp->MOD_INTEN |= ((uint32_t)1U << (uint32_t)eMod); +} + +/** + * @brief Disable TSTMP MOD(n) match interrupt + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_DisableModMatchInterrupt(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod) +{ + pTstmp->MOD_INTEN &= ~((uint32_t)1U << (uint32_t)eMod); +} + +/** + * @brief Set the counting modes of TSTMP MOD(n) + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + * @param eCounterMode Counting mode set + */ +LOCAL_INLINE void TSTMP_HWA_SetModCounterMode(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod, TSTMP_ModeCounterRunningMode eCounterMode) +{ + pTstmp->MOD_INTEN = (pTstmp->MOD_INTEN & ~((uint32_t)0x100U << (uint32_t)eMod)) | + (((uint32_t)eCounterMode << TSTMP_MOD_INTEN_MOD0_MODE_SHIFT) << (uint32_t)eMod); +} + +/** + * @brief Enable TSTMP MOD(n) counter + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_EnableModCounter(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod) +{ + pTstmp->MOD_INTEN |= (TSTMP_MOD_INTEN_MOD0_ENABLE_MASK << (uint32_t)eMod); +} + +/** + * @brief Disable TSTMP MOD(n) counter + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_DisableModCounter(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod) +{ + pTstmp->MOD_INTEN &= ~(TSTMP_MOD_INTEN_MOD0_ENABLE_MASK << (uint32_t)eMod); +} + +/** + * @brief Select TSTMP MOD(n) clock source + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_SelectClkSource(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod, TSTMP_ClockSourceType eClk) +{ + pTstmp->MOD_INTEN |= (((uint32_t)eClk) << (TSTMP_MOD_INTEN_MOD0_CLK_SHIFT + (uint32_t)eMod)); +} + +/** + * @brief Read TSTMP all MOD match flag + * + * @param pTstmp TSTMP instance + * @return TSTMP all MOD match flag + */ +LOCAL_INLINE uint32_t TSTMP_HWA_ReadModMatchFlag(TSTMP_Type *pTstmp) +{ + return ((uint32_t)(pTstmp->MOD_STATUS) & (uint32_t)(TSTMP_MOD_STATUS_MOD0_MATCH_MASK | TSTMP_MOD_STATUS_MOD1_MATCH_MASK + | TSTMP_MOD_STATUS_MOD2_MATCH_MASK | TSTMP_MOD_STATUS_MOD3_MATCH_MASK)); +} + +/** + * @brief Clear TSTMP all MOD(0) match flag + * + * @param pTstmp TSTMP instance + */ +LOCAL_INLINE void TSTMP_HWA_ClearMod0MatchFlag(TSTMP_Type *pTstmp) +{ + pTstmp->MOD_STATUS = (uint32_t)(TSTMP_MOD_STATUS_MOD0_MATCH_MASK); +} + +/** + * @brief Clear TSTMP all MOD(1,2,3) match flag + * + * @param pTstmp TSTMP instance + */ +LOCAL_INLINE void TSTMP_HWA_ClearAllMod123MatchFlag(TSTMP_Type *pTstmp) +{ + pTstmp->MOD_STATUS = (uint32_t)(TSTMP_MOD_STATUS_MOD1_MATCH_MASK | TSTMP_MOD_STATUS_MOD2_MATCH_MASK | + TSTMP_MOD_STATUS_MOD3_MATCH_MASK); +} + +/** + * @brief Clear TSTMP single MOD(1,2,3) match flag + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_ClearSingleMod123MatchFlag(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod) +{ + pTstmp->MOD_STATUS = ((uint32_t)1U << (uint32_t)eMod); +} + +/** + * @brief Set MOD match value + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + * @param u32ModValue MOD value + */ +LOCAL_INLINE void TSTMP_HWA_SetModMatchValue(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod, uint32_t u32ModValue) +{ + switch(eMod) + { + case TSTMP_MOD0: + pTstmp->MOD0_SETVAL = u32ModValue; + break; + + case TSTMP_MOD1: + pTstmp->MOD1_SETVAL = u32ModValue; + break; + + case TSTMP_MOD2: + pTstmp->MOD2_SETVAL = u32ModValue; + break; + + case TSTMP_MOD3: + pTstmp->MOD3_SETVAL = u32ModValue; + break; + + default: + break; + } +} + +#endif /* #ifndef _HWA_TSTMP_H_ */ diff --git a/Inc/HwA_wdog.h b/Inc/HwA_wdog.h new file mode 100644 index 0000000..5edfd57 --- /dev/null +++ b/Inc/HwA_wdog.h @@ -0,0 +1,115 @@ +/** + * @file HwA_WDOG.h + * @author Flagchip + * @brief FC7xxx Wdog hardware access layer + * @version 0.1.0 + * @date 2022-04-16 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/********************************************************************************* +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-29 qxw0074 N/A First version for FC7240 +******************************************************************************** */ + +#ifndef _HWA_WDOG_H_ +#define _HWA_WDOG_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_WDOG + * @{ + */ + +/********* Local typedef ************/ + +/********* Local inline function ************/ + +/********* Wdog Register interface ************/ +/** + * @brief Set CS register value, for Wdog working mode configuration. + * + * @param WDOG_Type *pWdog. point to wdog instance base register address. + * + * @param uint32_t u32Cs. configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetCs(WDOG_Type *pWdog, uint32_t u32Cs) +{ + pWdog->CS = u32Cs; +} + +/** + * @brief Get CS register value, for WDOG working mode configuration. + * @return uint32_t CS register value. + */ +LOCAL_INLINE uint32_t WDOG_HWA_GetCs(WDOG_Type *pWdog) +{ + uint32_t u32Temp = 0U; + u32Temp = pWdog->CS; + return u32Temp; +} + +/** + * @brief Clear Wdog interrupt flag. + * + * @param WDOG_Type *pWdog. point to wdog instance base register address. + */ +LOCAL_INLINE void WDOG_HWA_ClearInterruptFlag(WDOG_Type *pWdog) +{ + pWdog->CS |= WDOG_CS_FLAG_MASK; +} + +/** + * @brief Get WDOG unlock status, if locked, register can't be written. + * @return bool. true as unlocked. false as locked. + */ +LOCAL_INLINE bool WDOG_HWA_GetUnlockStatus(WDOG_Type *pWdog) +{ + return (bool)((((uint32_t)pWdog->CS & (uint32_t)WDOG_CS_ULK_STAT_MASK) != 0U) ? true : false); +} + +/** + * @brief Set COUNTER register value. for Wdog unlock and refresh usage. + * + * @param pWdog. point to wdog instance base register address. + * + * @param u32Counter. configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetCounter(WDOG_Type *pWdog, uint32_t u32Counter) +{ + pWdog->COUNTER = u32Counter; +} + +/** + * @brief Set TIMEOUT register value. for WDOG timeout value + * + * @param WDOG_Type *pWdog. point to wdog instance base register address. + * + * @param uint16_t u16Timeout configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetTimeout(WDOG_Type *pWdog, uint16_t u16Timeout) +{ + pWdog->TIMEOUT = u16Timeout; +} + +/** + * @brief Set WINDOW register value. for windowed WDOG low threshold value. + * + * @param WDOG_Type *pWdog. point to wdog instance base register address. + * + * @param uint16_t u16Window. configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetWindow(WDOG_Type *pWdog, uint16_t u16Window) +{ + pWdog->WINDOW = u16Window; +} + +/** @}*/ /* HwA_WODG */ + +#endif /* #ifndef _HWA_WDOG_H_ */ diff --git a/Inc/HwA_wku.h b/Inc/HwA_wku.h new file mode 100644 index 0000000..2972187 --- /dev/null +++ b/Inc/HwA_wku.h @@ -0,0 +1,147 @@ +/** + * @file HwA_wku.h + * @author Flagchip + * @brief FC7xxx WKU hardware access layer + * @version 0.1.0 + * @date 2024-01-05 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +#ifndef _HWA_WKU_H_ +#define _HWA_WKU_H_ + +#include "device_header.h" +/********* Local typedef ************/ +/** @brief Wku input */ +typedef enum +{ + WKU_INPUT_FCSPI0 = 0x000040U, + WKU_INPUT_FCUART = 0x000080U, + WKU_INPUT_CMP0 = 0x000400U, + WKU_INPUT_CMP1 = 0x000800U, + WKU_INPUT_TSTMP0 = 0x002000U, + WKU_INPUT_RTC_ALARM = 0x004000U, + WKU_INPUT_RTC_SECONDS = 0x008000U, + WKU_INPUT_FCPIT0 = 0x010000U, + WKU_INPUT_CMU0 = 0x020000U, + WKU_INPUT_AONTIMER = 0x040000U, + WKU_INPUT_GPIOA = 0x080000U, + WKU_INPUT_GPIOC = 0x100000U, + WKU_INPUT_GPIOE = 0x200000U, + WKU_INPUT_GPIOF = 0x400000U, + WKU_INPUT_GPIOG = 0x800000U, + WKU_INPUT_MAX = 0xFFFFFFU +} WKU_WakeupInputType; + + +/********* mcaro ************/ +#define WKU_INPUT_ALL_MASK (WKU_INPUT_FCSPI0 |\ + WKU_INPUT_FCUART |\ + WKU_INPUT_CMP0 |\ + WKU_INPUT_CMP1 |\ + WKU_INPUT_TSTMP0 |\ + WKU_INPUT_RTC_ALARM |\ + WKU_INPUT_RTC_SECONDS |\ + WKU_INPUT_FCPIT0 |\ + WKU_INPUT_CMU0 |\ + WKU_INPUT_AONTIMER |\ + WKU_INPUT_GPIOA |\ + WKU_INPUT_GPIOC |\ + WKU_INPUT_GPIOE |\ + WKU_INPUT_GPIOF |\ + WKU_INPUT_GPIOG |\ + WKU_INPUT_MAX) + +/********* Local inline function ************/ +/** + * @brief Enable wakeup delay counter + * + */ +LOCAL_INLINE void WKU_HWA_EnableDelayCounter(void) +{ + WKU->MDC |= (uint32_t)WKU_MDC_DLYEN_MASK; +} + +/** + * @brief Disable wakeup delay counter + * + */ +LOCAL_INLINE void WKU_HWA_DisableDelayCounter(void) +{ + WKU->MDC &= ~((uint32_t)WKU_MDC_DLYEN_MASK); +} + +/** + * @brief Set wakeup delay time + * + * @param u8DelayTime delay time + */ +LOCAL_INLINE void WKU_HWA_SetDelayTime(uint8_t u8DelayTime) +{ + uint32_t u32RegVal = WKU->MDC; + WKU->MDC = ((u32RegVal & (~WKU_MDC_DELAYTIME_MASK)) | WKU_MDC_DELAYTIME(u8DelayTime)); +} + +/** + * @brief Enable wakeup source + * + * @param eWakeup Wakeup source type + */ +LOCAL_INLINE void WKU_HWA_EnableWakeupSource(const WKU_WakeupInputType eWakeup) +{ + if (eWakeup < WKU_INPUT_CMP0) + { + WKU->MWER0 |= (uint32_t)eWakeup; + } + else if ((eWakeup < WKU_INPUT_FCPIT0) && (eWakeup > WKU_INPUT_FCUART)) + { + WKU->MWER1 |= ((uint32_t)eWakeup >> 8U); + } + else + { + WKU->MWER2 |= ((uint32_t)eWakeup >> 16U); + } +} + +/** + * @brief Disable wakeup source + * + * @param eWakeup Wakeup source type + */ +LOCAL_INLINE void WKU_HWA_DisableWakeupSource(const WKU_WakeupInputType eWakeup) +{ + if (eWakeup < WKU_INPUT_CMP0) + { + WKU->MWER0 &= ((~((uint32_t)eWakeup)) & (uint32_t)0xFF); + } + else if ((eWakeup < WKU_INPUT_FCPIT0) && (eWakeup > WKU_INPUT_FCUART)) + { + WKU->MWER1 &= ((~(uint32_t)((uint32_t)eWakeup >> 8U)) & (uint32_t)0xFF); + } + else + { + WKU->MWER2 &= ((~(uint32_t)((uint32_t)eWakeup >> 16U)) & (uint32_t)0xFF); + } +} + +/** + * @brief Read WKU wakeup source + * + * @return WKU wakeup source value + */ +LOCAL_INLINE uint32_t WKU_HWA_ReadWakeupSource(void) +{ + uint32_t u32WakeupSource = 0U; + + u32WakeupSource = (uint32_t)(WKU->MWER0); + u32WakeupSource |= (uint32_t)((uint32_t)(WKU->MWER1) << 8U); + u32WakeupSource |= (uint32_t)((uint32_t)(WKU->MWER2) << 16U); + + return u32WakeupSource; +} + + +#endif /* #ifndef _HWA_WKU_H_ */ diff --git a/modular.json b/modular.json new file mode 100644 index 0000000..174bad2 --- /dev/null +++ b/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ] + } +}