192 lines
5.9 KiB
C
192 lines
5.9 KiB
C
/**
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* @file HwA_pcc.h
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* @author Flagchip085
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* @brief FC7xxx PCC register API
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* @version 0.1.0
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* @date 2024-01-12
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*
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* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
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******************************************************************************** */
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#ifndef HWA_INCLUDE_HWA_PCC_H_
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#define HWA_INCLUDE_HWA_PCC_H_
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#include "device_header.h"
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/**
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* @defgroup HwA_pcc
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* @ingroup HwA_pcc
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* @{
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*/
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/** @brief Marco for PCCn Bit Field definition */
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#define PCC_CGC_MASK 0x800000U
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#define PCC_CGC_SHIFT 23U
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#define PCC_CGC_WIDTH 1U
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#define PCC_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_CGC_SHIFT))&PCC_CGC_MASK)
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#define PCC_GetCGC(x) ((((uint32_t)(x))&PCC_CGC_MASK)>>PCC_CGC_SHIFT)
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#define PCC_SEL_MASK 0x700000U
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#define PCC_SEL_SHIFT 20U
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#define PCC_SEL_WIDTH 3U
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#define PCC_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_SEL_SHIFT))&PCC_SEL_MASK)
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#define PCC_GetSEL(x) ((((uint32_t)(x))&PCC_SEL_MASK)>>PCC_SEL_SHIFT)
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#define PCC_DIV_MASK 0x7U
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#define PCC_DIV_SHIFT 0U
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#define PCC_DIV_WIDTH 3U
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#define PCC_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCC_DIV_SHIFT))&PCC_DIV_MASK)
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#define PCC_GetDIV(x) ((((uint32_t)(x))&PCC_DIV_MASK)>>PCC_DIV_SHIFT)
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#define PCC_SWR_MASK 0x10000u
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/**
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* @brief defined the clock source for function clock,match with PCC_XXX[SEL] bit filed.
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*/
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typedef enum
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{
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PCC_CLKGATE_SRC_OFF_OR_TCLK = 0U,
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PCC_CLKGATE_SRC_FOSCDIV = 1U,
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PCC_CLKGATE_SRC_SIRCDIV = 2U,
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PCC_CLKGATE_SRC_FIRCDIV = 3U,
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PCC_CLKGATE_SRC_RESERVE0 = 4U,
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PCC_CLKGATE_SRC_PLL1DIV = 5U,
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PCC_CLKGATE_SRC_PLL0DIV = 6U,
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PCC_CLKGATE_SRC_RESERVE1 = 7U,
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PCC_CLKGATE_UNINVOLVED = 8U
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} PCC_ClkGateSrcType;
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/**
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* @brief define the clock divider,match with PCC_XXX[DIV] bit filed.
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*/
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typedef enum
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{
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PCC_CLK_DIV_BY1 = 0U, /*!< Divide by 1 (pass-through, no clock divide) */
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PCC_CLK_DIV_BY2 = 1U, /*!< Divide by 2 */
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PCC_CLK_DIV_BY3 = 2U, /*!< Divide by 3 */
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PCC_CLK_DIV_BY4 = 3U, /*!< Divide by 4 */
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PCC_CLK_DIV_BY5 = 4U, /*!< Divide by 5 */
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PCC_CLK_DIV_BY6 = 5U, /*!< Divide by 6 */
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PCC_CLK_DIV_BY7 = 6U, /*!< Divide by 7 */
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PCC_CLK_DIV_BY8 = 7U, /*!< Divide by 8 */
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PCC_CLK_UNINVOLVED = 8U /*!< Current peripheral dose not contain DIV configuration */
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} PCC_ClkDivType;
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/**
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* @brief Get PCC register value
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*
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* @param u32Offset the PCC register offset
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* @return uint32_t PCC register value
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*/
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LOCAL_INLINE uint32_t PCC_HWA_GetRegister(uint32_t u32Offset)
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{
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return *((uint32_t *)((uint32_t)PCC_BASE + u32Offset));
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}
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/**
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* @brief Set PCC register value
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*
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* @param u32Offset the PCC register offset
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* @param eValue value to set
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*/
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LOCAL_INLINE void PCC_HWA_SetRegister(uint32_t u32Offset,uint32_t eValue)
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{
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*((uint32_t *)((uint32_t)PCC_BASE + u32Offset)) = eValue;
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}
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/**
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* @brief Get PCC clock gate control
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*
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* @param u32Offset the PCC register offset
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* @return bool PCC clock enabled or disabled
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*/
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LOCAL_INLINE bool PCC_HWA_GetClockGateControl(uint32_t u32Offset)
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{
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uint32_t u32Value = *((uint32_t *)((uint32_t)PCC_BASE + u32Offset));
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return (bool)PCC_GetCGC(u32Value);
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}
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/**
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* @brief Set PCC clock gate control
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*
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* @param u32Offset the PCC register offset
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* @param eSrc PCC clock source
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*/
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LOCAL_INLINE void PCC_HWA_SetClockGateControl(uint32_t u32Offset,bool bEnable)
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{
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uint32_t *pRegister = (uint32_t *)((uint32_t)PCC_BASE + u32Offset);
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*pRegister = ((*pRegister) & (~PCC_CGC_MASK)) | PCC_CGC(bEnable);
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}
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/**
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* @brief Get PCC clock source
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*
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* @param u32Offset the PCC register offset
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* @return PCC_ClkGateSrcType PCC clock source
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*/
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LOCAL_INLINE PCC_ClkGateSrcType PCC_HWA_GetClockSource(uint32_t u32Offset)
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{
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uint32_t u32Value = *((uint32_t *)((uint32_t)PCC_BASE + u32Offset));
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return (PCC_ClkGateSrcType)PCC_GetSEL(u32Value);
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}
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/**
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* @brief Set PCC clock source
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*
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* @param u32Offset the PCC register offset
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* @param eSrc PCC clock source
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*/
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LOCAL_INLINE void PCC_HWA_SetClockSource(uint32_t u32Offset,PCC_ClkGateSrcType eSrc)
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{
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uint32_t *pRegister = (uint32_t *)((uint32_t)PCC_BASE + u32Offset);
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*pRegister = ((*pRegister) & (~PCC_SEL_MASK)) | PCC_SEL(eSrc);
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}
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/**
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* @brief PCC peripheral software reset
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*
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* @param u32Offset the PCC register offset
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*/
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LOCAL_INLINE void PCC_HWA_SoftwareReset(uint32_t u32Offset)
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{
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*((uint32_t *)((uint32_t)PCC_BASE + u32Offset)) |= (uint32_t)PCC_SWR_MASK;
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*((uint32_t *)((uint32_t)PCC_BASE + u32Offset)) &= ~(uint32_t)PCC_SWR_MASK;
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}
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/**
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* @brief Get PCC divider
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*
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* @param u32Offset the PCC register offset
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* @return PCC_ClkDivType PCC clock divider
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*/
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LOCAL_INLINE PCC_ClkDivType PCC_HWA_GetDivider(uint32_t u32Offset)
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{
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uint32_t u32Value = *((uint32_t *)((uint32_t)PCC_BASE + u32Offset));
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return (PCC_ClkDivType)PCC_GetDIV(u32Value);
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}
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/**
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* @brief Set PCC register value
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*
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* @param u32Offset the PCC register offset
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* @param eDivider PCC clock divider
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*/
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LOCAL_INLINE void PCC_HWA_SetDivider(uint32_t u32Offset,PCC_ClkDivType eDivider)
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{
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uint32_t *pRegister = (uint32_t *)((uint32_t)PCC_BASE + u32Offset);
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*pRegister = ((*pRegister) & (~PCC_DIV_MASK)) | PCC_DIV(eDivider);
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}
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/** @}*/
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#endif /* HWA_INCLUDE_HWA_PCC_H_ */
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