428 lines
12 KiB
C
428 lines
12 KiB
C
/**
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* @file HwA_rgm.h
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* @author Flagchip
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* @brief FC7xxx RGM hardware access layer
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* @version 0.1.0
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* @date 2024-01-12
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*
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* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
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*
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* @details
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240
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******************************************************************************** */
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#ifndef _HWA_RGM_H_
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#define _HWA_RGM_H_
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#include "device_header.h"
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/********* Local typedef ************/
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/** @brief Rgm reset event */
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typedef enum
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{
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RGM_WAKEUP = 0x00000001U,
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RGM_LVD = 0x00000002U,
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RGM_CLKERR1 = 0x00000004U,
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RGM_CLKERR0 = 0x00000008U,
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RGM_FSCMU = 0x00000010U,
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RGM_HSMWDOG = 0x00000020U,
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RGM_PIN = 0x00000040U,
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RGM_POR = 0x00000080U,
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RGM_JTAG = 0x00000100U,
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RGM_SYSAP = 0x00000800U,
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RGM_WDOG1 = 0x00001000U,
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RGM_SACKERR = 0x00002000U,
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RGM_CMU = 0x00004000U,
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RGM_LBIST = 0x00008000U,
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RGM_FSMERR = 0x20000000U,
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RGM_PINRSTTOUT = 0x40000000U,
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RGM_SYSRSTTOUT = 0x80000000U
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} RGM_ResetEventType;
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/** @brief Rgm reset interrupt delay cycles type. */
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typedef enum
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{
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RGM_8_CLOCK_CYCLES = 0x00U,
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RGM_32_CLOCK_CYCLES = 0x01U,
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RGM_128_CLOCK_CYCLES = 0x02U,
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RGM_512_CLOCK_CYCLES = 0x03U
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} RGM_ResetDelayType;
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/** @brief Rgm reset interrupt event manger */
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typedef enum
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{
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RGM_INT_CLKERR0 = 0x0008U,
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RGM_INT_FCSMU = 0x0010U,
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RGM_INT_WDG = 0x0020U,
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RGM_INT_PIN = 0x0040U,
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RGM_INT_JTAG = 0x0100U,
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RGM_INT_CPULOC = 0x0200U,
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RGM_INT_SW = 0x0400U,
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RGM_INT_SYSAP = 0x0800U,
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RGM_INT_WDOG1 = 0x1000U,
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RGM_INT_SACKERR = 0x2000U,
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RGM_INT_CMU = 0x4000U
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} RGM_ResetIntMangerType;
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/** @brief Select the Rgm CORE Write protection */
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typedef enum
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{
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RGM_WPB_ALL = 0x00U,
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RGM_WPB_CPU0 = 0x01U,
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RGM_WPB_NOCORE = 0x04U
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} RGM_WriteprotectionBitType;
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/** @brief Rgm CPU0,1,2 related interrupt event manger */
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typedef enum
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{
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RGM_CPU_INT_LOCKUP = 0x01U,
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RGM_CPU_INT_SYSRST = 0x02U,
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RGM_CPU_INT_WDOG = 0x04U,
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RGM_CPU_INT_INTM = 0x08U,
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RGM_CPU_INT_SWRST = 0x10U
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} RGM_CPUIntMangerType;
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/** @brief Rgm CPU0,1,2 software reset status */
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typedef enum
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{
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RGM_CPU_OUT_RST_UNDER = 0x00U,
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RGM_CPU_OUT_RST_OUT = 0x01U
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} RGM_CPUOutResetType;
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/** @brief Rgm CPU0,1,2 reset event */
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typedef enum
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{
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RGM_CPU_WAKEUP = 0x00000001U,
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RGM_CPU_LVD = 0x00000002U,
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RGM_CPU_CLKERR1 = 0x00000004U,
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RGM_CPU_CLKERR0 = 0x00000008U,
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RGM_CPU_FSCMU = 0x00000010U,
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RGM_CPU_HSMWDOG = 0x00000020U,
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RGM_CPU_PIN = 0x00000040U,
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RGM_CPU_POR = 0x00000080U,
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RGM_CPU_JTAG = 0x00000100U,
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RGM_CPU_SYSAP = 0x00000800U,
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RGM_CPU_WDOG1 = 0x00001000U,
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RGM_CPU_SACKERR = 0x00002000U,
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RGM_CPU_CMU = 0x00004000U,
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RGM_CPU_LBIST = 0x00008000U,
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RGM_CPU_LOCKUP = 0x00010000U,
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RGM_CPU_SYSRST = 0x00020000U,
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RGM_CPU_WDOG = 0x00040000U,
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RGM_CPU_INTM = 0x00080000U,
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RGM_CPU_SWRST = 0x00100000U,
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RGM_CPU_FSMERR = 0x20000000U,
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RGM_CPU_PINRSTTOUT = 0x40000000U,
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RGM_CPU_SYSRSTTOUT = 0x80000000U
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} RGM_CPUResetEventType;
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/** @brief Rgm CPU1,2 system reset enable flag */
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typedef enum
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{
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RGM_CPU_EN_LOCKUP = 0x00010000U,
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RGM_CPU_EN_SYSRST = 0x00020000U,
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RGM_CPU_EN_WDOG = 0x00040000U,
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RGM_CPU_EN_INTM = 0x00080000U,
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RGM_CPU_EN_SWRST = 0x00100000U,
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} RGM_CPUSystemRstMangerType;
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/********* Local inline function ************/
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/**
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* @brief Read last reset flag
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*
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* @return Last reset flag
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*/
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LOCAL_INLINE uint32_t RGM_HWA_ReadLastResetFlag(void)
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{
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return (uint32_t)RGM->SRS;
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}
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/**
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* @brief Read all reset flag before POR,SSRS register is reset on POR only
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*
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* @return All reset flag before POR
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*/
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LOCAL_INLINE uint32_t RGM_HWA_ReadAllResetFlagBeforePOR(void)
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{
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return (uint32_t)RGM->SSRS;
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}
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/**
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* @brief Read reset pin filter register
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*
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* @return Reset pin filter register
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*/
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LOCAL_INLINE uint32_t RGM_HWA_ReadResetPinFilterEnable(void)
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{
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return (uint32_t)RGM->RSTFLT;
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}
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/**
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* @brief This api can clear reset flag of SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
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*
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* @param eReset Reset flag
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*/
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LOCAL_INLINE void RGM_HWA_ClearResetFlagAfterPOR(RGM_ResetEventType eReset)
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{
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RGM->SSRS = (uint32_t)(eReset);
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}
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/**
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* @brief This api can clear all reset flag of SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
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*
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*/
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LOCAL_INLINE void RGM_HWA_ClearAllResetFlagAfterPOR(void)
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{
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RGM->SSRS = (uint32_t)0xE000F9FFU;
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}
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/**
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* @brief Set reset pin filter bus clock filter width
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*
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* @param u8Value Bus clock filter width value
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*/
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LOCAL_INLINE void RGM_HWA_SetBusClockFilterWidth(uint8_t u8Value)
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{
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uint32_t u32RegValue = RGM->RSTFLT;
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RGM->RSTFLT = (u32RegValue & ~(uint32_t)RGM_RSTFLT_RSTFLT_BUSW_MASK) | RGM_RSTFLT_RSTFLT_BUSW(u8Value);
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}
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/**
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* @brief Enable reset pin filter bus clock
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*
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*/
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LOCAL_INLINE void RGM_HWA_EnableBusClockFilter(void)
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{
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RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_BUS_MASK;
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}
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/**
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* @brief Enable reset pin filter AON32K clock
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*
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*/
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LOCAL_INLINE void RGM_HWA_EnableAon32kClockFilter(void)
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{
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RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_AON_MASK;
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}
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/**
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* @brief Enable reset pin filter AON32K low power clock
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*
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*/
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LOCAL_INLINE void RGM_HWA_EnableAon32kLPClockFilter(void)
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{
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RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_AON_LP_MASK;
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}
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/**
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* @brief Clear reset pin filter bus clock filter width
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*
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*/
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LOCAL_INLINE void RGM_HWA_ClearBusClockFilterWidth(void)
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{
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RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_BUSW_MASK;
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}
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/**
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* @brief Disable reset pin filter bus clock
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*
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*/
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LOCAL_INLINE void RGM_HWA_DisableBusClockFilter(void)
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{
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RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_BUS_MASK;
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}
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/**
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* @brief Disable reset pin filter AON32K clock
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*
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*/
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LOCAL_INLINE void RGM_HWA_DisableAon32kClockFilter(void)
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{
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RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_AON_MASK;
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}
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/**
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* @brief Disable reset pin filter AON32K low power clock
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*
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*/
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LOCAL_INLINE void RGM_HWA_DisableAon32kLPClockFilter(void)
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{
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RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_AON_LP_MASK;
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}
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/**
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* @brief Set Reset delay
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*
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* @param eDelay Reset delay type
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*/
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LOCAL_INLINE void RGM_HWA_SetResetDelay(RGM_ResetDelayType eDelay)
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{
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uint32_t u32RegValue = RGM->SRIE;
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RGM->SRIE = (u32RegValue & ~(uint32_t)RGM_SRIE_DELAY_MASK) | RGM_SRIE_DELAY(eDelay);
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}
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/**
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* @brief Clear Reset delay
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*/
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LOCAL_INLINE void RGM_HWA_ClearResetDelay(void)
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{
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RGM->SRIE &= ~(uint32_t)RGM_SRIE_DELAY_MASK;
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}
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/**
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* @brief Enable global reset interrupt
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*
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*/
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LOCAL_INLINE void RGM_HWA_EnableGlobalResetInterrupt(void)
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{
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RGM->SRIE |= (uint32_t)RGM_SRIE_GLOBAL_RIE_MASK;
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}
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/**
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* @brief Enable reset interrupt
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*
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* @param eResetInterrupt Reset interrupt type
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*/
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LOCAL_INLINE void RGM_HWA_EnableResetInterrupt(RGM_ResetIntMangerType eResetInterrupt)
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{
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RGM->SRIE |= (uint32_t)((uint32_t)eResetInterrupt & (RGM_SRIE_CLKERR0_RIE_MASK | RGM_SRIE_WDG_RIE_MASK |
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RGM_SRIE_PIN_RIE_MASK | RGM_SRIE_JTAG_RIE_MASK | RGM_SRIE_CPULOC_RIE_MASK | RGM_SRIE_SW_RIE_MASK |
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RGM_SRIE_SYSAP_RIE_MASK | RGM_SRIE_WDOG1_RIE_MASK | RGM_SRIE_SACKERR_RIE_MASK));
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}
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/**
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* @brief Disable reset interrupt
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*
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* @param eResetInterrupt Reset interrupt type
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*/
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LOCAL_INLINE void RGM_HWA_DisableResetInterrupt(RGM_ResetIntMangerType eResetInterrupt)
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{
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RGM->SRIE &= ~(uint32_t)((uint32_t)eResetInterrupt & (RGM_SRIE_CLKERR0_RIE_MASK | RGM_SRIE_WDG_RIE_MASK |
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RGM_SRIE_PIN_RIE_MASK | RGM_SRIE_JTAG_RIE_MASK | RGM_SRIE_CPULOC_RIE_MASK | RGM_SRIE_SW_RIE_MASK |
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RGM_SRIE_SYSAP_RIE_MASK | RGM_SRIE_WDOG1_RIE_MASK | RGM_SRIE_SACKERR_RIE_MASK));
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}
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/**
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* @brief Get enabling status of system reset
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*
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* @return Interrupt enabling status of system reset
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*/
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LOCAL_INLINE uint32_t RGM_HWA_GetResetInterrupt(void)
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{
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return (uint32_t)(RGM->SRIE & (RGM_SRIE_CLKERR0_RIE_MASK | RGM_SRIE_WDG_RIE_MASK |
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RGM_SRIE_PIN_RIE_MASK | RGM_SRIE_GLOBAL_RIE_MASK | RGM_SRIE_JTAG_RIE_MASK | RGM_SRIE_CPULOC_RIE_MASK |
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RGM_SRIE_SW_RIE_MASK | RGM_SRIE_SYSAP_RIE_MASK | RGM_SRIE_WDOG1_RIE_MASK | RGM_SRIE_SACKERR_RIE_MASK));
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}
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/**
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* @brief Perform system reset.
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*
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*/
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LOCAL_INLINE void CM7_HWA_SystemReset(void)
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{
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uint32 u32Temp;
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u32Temp = SCB->AIRCR;
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u32Temp &= ~(uint32)(SCB_AIRCR_VECTKEY_Msk);
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u32Temp |= (uint32)((((uint32_t)(((uint32_t)(0x5FAU))<<SCB_AIRCR_VECTKEY_Pos))&SCB_AIRCR_VECTKEY_Msk) |
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SCB_AIRCR_SYSRESETREQ_Msk | SCB_AIRCR_PRIGROUP_Msk);
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SCB->AIRCR = u32Temp;
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}
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/**
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* @brief Enable CPU0 interrupt
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*
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* @param eCPU0ResetInterrupt CPU0 related interrupt type
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*/
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LOCAL_INLINE void RGM_HWA_EnableCPU0InterruptFlag(RGM_CPUIntMangerType eCPU0ResetInterrupt)
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{
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RGM->C0_CFG |= (uint32_t)((uint32_t)eCPU0ResetInterrupt & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK |
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RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK));
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}
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/**
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* @brief Disable CPU0 interrupt
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*
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* @param eCPU0ResetInterrupt CPU0 related interrupt type
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*/
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LOCAL_INLINE void RGM_HWA_DisableCPU0InterruptFlag(RGM_CPUIntMangerType eCPU0ResetInterrupt)
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{
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RGM->C0_CFG &= ~(uint32_t)((uint32_t)eCPU0ResetInterrupt & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK |
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RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK));
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}
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/**
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* @brief Get enabling status of CPU0 core related reset
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*
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* @return Interrupt enabling status of CPU0 core related reset
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*/
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LOCAL_INLINE uint32_t RGM_HWA_GetCPU0ResetInterrupt(void)
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{
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return (uint32_t)(RGM->C0_CFG & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK |
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RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK));
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}
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/**
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* @brief Get the CPU0 exit reset flag
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*
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* @return RGM_CPU_OUT_RST_UNDER CPU0 is under reset
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* @return RGM_CPU_OUT_RST_OUT CPU0 is out of reset
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*/
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LOCAL_INLINE RGM_CPUOutResetType RGM_HWA_GetCPU0OutResetFlag(void)
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{
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uint8_t u8TmpVal = (uint8_t)(RGM->C0_RST & RGM_C0_RST_C0_OUT_OF_RST_MASK) >> RGM_C0_RST_C0_OUT_OF_RST_SHIFT;
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return (RGM_CPUOutResetType)u8TmpVal;
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}
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/**
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* @brief Issue a CPU0 software reset.
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*
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*/
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LOCAL_INLINE void RGM_HWA_CPU0SWReset(void)
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{
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RGM->C0_RST |= (uint32_t)RGM_C0_RST_C0_SWRST_MASK;
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}
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/**
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* @brief Read CPU0 last reset flag
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*
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* @return CPU0 last reset flag
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*/
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LOCAL_INLINE uint32_t RGM_HWA_ReadCPU0LastResetFlag(void)
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{
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return (uint32_t)RGM->C0_SRS;
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}
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/**
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* @brief Read CPU0 all reset flag before POR,SSRS register is reset on POR only
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*
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* @return CPU0 all reset flag before POR
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*/
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LOCAL_INLINE uint32_t RGM_HWA_ReadCPU0AllResetFlagBeforePOR(void)
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{
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return (uint32_t)RGM->C0_SSRS;
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}
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/**
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* @brief This api can clear reset flag of RGM_C0_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
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*
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* @param eReset Reset flag
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*/
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LOCAL_INLINE void RGM_HWA_ClearC0ResetFlagAfterPOR(RGM_CPUResetEventType eReset)
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{
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RGM->C0_SSRS = (uint32_t)(eReset);
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}
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/**
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* @brief This api can clear all reset flag of SSRGM_C0_SSRSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
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*
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*/
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LOCAL_INLINE void RGM_HWA_ClearC0AllResetFlagAfterPOR(void)
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{
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RGM->C0_SSRS = (uint32_t)0xE01FF9FFU;
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}
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#endif /* #ifndef _HWA_RGM_H_ */
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