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58
Inc/fc7xxx_board_conf.h Normal file
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/**
* @file fc7xxx_board_conf.h
* @author Flagchip032
* @brief FC7xxx board configuration file
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip032 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_BOARD_CONF_H_
#define _DRIVER_FC7XXX_BOARD_CONF_H_
#include "device_header.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_board_conf
* @{
*/
/******************* Oscillator Values *******************/
/**
* @brief Fast OSC frequency
*/
#ifndef FOSC_FREQUENCY
#define FOSC_FREQUENCY 24000000U
#endif
/**
* @brief Slow OSC frequency
*/
#ifndef SOSC_FREQUENCY
#define SOSC_FREQUENCY 32768U
#endif
/**
* @brief FTU input TCLK frequency
*/
#ifndef PCC_FTU_TCLK_FREQ
#define PCC_FTU_TCLK_FREQ 0U
#endif
/** @}*/ /* fc7xxx_board_conf */
#if defined(__cplusplus)
}
#endif
#endif

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Inc/fc7xxx_driver_adc.h Normal file
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/**
* @file fc7xxx_driver_adc.h
* @author Flagchip0126
* @brief FC7xxx ADC driver type definition and API
* @version 0.1.0
* @date 2024-01-15
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_ADC_H_
#define _DRIVER_FC7XXX_DRIVER_ADC_H_
#include "device_header.h"
#include "HwA_adc.h"
#include "fc7xxx_driver_dma.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_adc
* @{
*/
/**
* @name ADC0 Internal Channels
* @brief Available internal ADC channels for ADC Instance 0
*
* @{
*/
#define ADC0_CHANNEL_VBG_BUFFER ADC_CHANNEL_INTERNAL_0
#define ADC0_CHANNEL_V25 ADC_CHANNEL_INTERNAL_1
#define ADC0_CHANNEL_V11 ADC_CHANNEL_INTERNAL_2
#define ADC0_CHANNEL_CMP0_DAC ADC_CHANNEL_INTERNAL_4
#define ADC0_CHANNEL_TEMPSENSOR_OUT ADC_CHANNEL_INTERNAL_5 /* Must be in differential mode */
/** @}*/
/**
* @name ADC1 Internal channels
* @brief Available internal ADC channels for ADC Instance 1
*
* @{
*/
#define ADC1_CHANNEL_V11_PD0 ADC_CHANNEL_INTERNAL_0
#define ADC1_CHANNEL_VREFH ADC_CHANNEL_INTERNAL_1
#define ADC1_CHANNEL_VDDA ADC_CHANNEL_INTERNAL_2
#define ADC1_CHANNEL_V15 ADC_CHANNEL_INTERNAL_3
#define ADC1_CHANNEL_CMP1_DAC ADC_CHANNEL_INTERNAL_4
/** @}*/
/**
* @brief The ADC conversion complete callback function prototype
*
*/
typedef void (*ADC_ConvCompleteCallbackType)(const uint32_t *const pBuff);
/**
* @brief The ADC overrun callback function prototype
*
*/
typedef void (*ADC_OverRunInterruptCallbackType)(void);
/**
* @brief The ADC compare callback function prototype
*
*/
typedef void (*ADC_CompareInterruptCallbackType)(void);
/**
* @brief The ADC end of sequence group callback function prototype
*
*/
typedef void (*ADC_EndOfSeqGroupInterruptCallbackType)(uint8_t u8SeqGroupIdx);
/**
* @brief The instance index of the ADC peripheral
*
*/
typedef enum
{
ADC_INSTANCE_0 = 0U, /*!< ADC instance 0 is selected */
ADC_INSTANCE_1 = 1U, /*!< ADC instance 1 is selected */
} ADC_InstanceType;
/**
* @brief The channel selected for ADC conversion
*
*/
typedef enum
{
ADC_CHANNEL_0 = 0U,
ADC_CHANNEL_1 = 1U,
ADC_CHANNEL_2 = 2U,
ADC_CHANNEL_3 = 3U,
ADC_CHANNEL_4 = 4U,
ADC_CHANNEL_5 = 5U,
ADC_CHANNEL_6 = 6U,
ADC_CHANNEL_7 = 7U,
ADC_CHANNEL_8 = 8U,
ADC_CHANNEL_9 = 9U,
ADC_CHANNEL_10 = 10U,
ADC_CHANNEL_11 = 11U,
ADC_CHANNEL_12 = 12U,
ADC_CHANNEL_13 = 13U,
ADC_CHANNEL_14 = 14U,
ADC_CHANNEL_15 = 15U,
ADC_CHANNEL_16 = 16U,
ADC_CHANNEL_17 = 17U,
ADC_CHANNEL_18 = 18U,
ADC_CHANNEL_19 = 19U,
ADC_CHANNEL_20 = 20U,
ADC_CHANNEL_21 = 21U,
ADC_CHANNEL_22 = 22U,
ADC_CHANNEL_23 = 23U,
ADC_CHANNEL_24 = 24U,
ADC_CHANNEL_25 = 25U,
ADC_CHANNEL_26 = 26U,
ADC_CHANNEL_27 = 27U,
ADC_CHANNEL_28 = 28U,
ADC_CHANNEL_29 = 29U,
ADC_CHANNEL_30 = 30U,
ADC_CHANNEL_31 = 31U,
ADC_CHANNEL_INTERNAL_0 = 32U,
ADC_CHANNEL_INTERNAL_1 = 33U,
ADC_CHANNEL_INTERNAL_2 = 34U,
ADC_CHANNEL_INTERNAL_3 = 35U,
ADC_CHANNEL_INTERNAL_4 = 36U,
ADC_CHANNEL_INTERNAL_5 = 37U
} ADC_ChannelType;
/**
* @brief The channel selected for ADC conversion in differential mode
*
*/
typedef enum
{
ADC_CHANNEL_0_4 = 0U,
ADC_CHANNEL_1_5 = 1U,
ADC_CHANNEL_2_6 = 2U,
ADC_CHANNEL_3_7 = 3U,
ADC_CHANNEL_TEMPSENSOR = 37U
} ADC_DifferentialChannelType;
/**
* @brief The ADC sample time option for selection
*
*/
typedef enum
{
ADC_SAMPLE_TIME_OPTION_0 = 0U,
ADC_SAMPLE_TIME_OPTION_1 = 1U,
ADC_SAMPLE_TIME_OPTION_2 = 2U,
ADC_SAMPLE_TIME_OPTION_3 = 3U
} ADC_SampleTimeOptionType;
/**
* @brief The ADC SequenceGroup Index
*
*/
typedef enum
{
ADC_SEQUENCE_GROUP_0 = 0U,
ADC_SEQUENCE_GROUP_1 = 1U,
ADC_SEQUENCE_GROUP_2 = 2U,
ADC_SEQUENCE_GROUP_3 = 3U
} ADC_SequenceGroupIndex;
/**
* @brief ADC operation return values
*
*/
typedef enum
{
ADC_STATUS_SUCCESS = 0x0U, /*!< The ADC operation is succeed */
ADC_STATUS_ERROR = 0x1U, /*!< The ADC operation is failed */
ADC_STATUS_TIMEOUT = 0x2U /*!< The ADC operation is failed because of time out */
} ADC_StatusType;
/**
* @brief Defines the converter configuration
*
* This structure is used to configure the ADC converter
*
* Implements : ADC_InitType
*/
typedef struct
{
ADC_ResolutionType eResolution; /*!< ADC eResolution (8,10,12 bit) */
ADC_AlignType eAlign; /*!< ADC alignment (left, right) */
ADC_TrigModeType eTriggerMode; /*!< ADC trigger type (software, hardware)
- affects only the first control channel */
bool bWaitEnable; /*!< Whether to enable ADC wait conversion mode */
bool bSequenceGroupModeEnable; /*!< Whether to enable ADC sequence group mode, if true, ignore eSequenceMode*/
bool bCalEnable; /*!< Whether to enable ADC calibration > */
int32_t s32CalOffset; /*!< ADC calibration offset value > */
int32_t s32CalGain; /*!< ADC calibration gain value > */
ADC_TrgLatchUnitPri eTrgLatchUnitPri; /*!< Select priority of Trigger Latch Unit */
ADC_ClockDivideType eClockDivider; /*!< ADC clock divider */
ADC_SeqModeType eSequenceMode; /*!< ADC sequence mode (single, continuous, discontinuous) */
bool bAutoDis; /*!< Whether to enable audo disable mode, only set this when adc in off state */
ADC_OvrModeType eOverrunMode; /*!< Whether to preserve data when ADC overruns */
ADC_RefType eVoltageRef; /*!< Voltage reference used (external, internal) */
bool bHwAvgEnable; /*!< Enable averaging functionality */
ADC_AverageType eHwAverage; /*!< Selection for number of samples used for averaging */
uint8_t aSampleTimes[ADC_SAMPLE_TIME_OPTION_CNT]; /*!< ADC sample time options, range: 4 ~ 257 */
} ADC_InitType;
/**
* @brief The configuration option for the ADC channel
*
*/
typedef struct
{
ADC_ChannelType eChannel; /*!< Selected ADC channel */
ADC_SampleTimeOptionType eSampleTimeOption; /*!< The sample time selection for the channel */
bool bDiff; /*!< Whether diff mode, if a channel do not support differential mode, ignore this */
} ADC_ChannelCfgType;
/**
* @brief The configuration option for the ADC sequence group
*
*/
typedef struct
{
uint8_t u8Start; /*!< Sequence channel start */
uint8_t u8Len; /*!< Sequence group length, is must be >= 0 */
} ADC_SequenceGroupType;
/**
* @brief Defines the hardware compare configuration
*
* This structure is used to configure the hardware compare feature for the ADC
*
* Implements : ADC_CompareType
*/
typedef struct
{
/* ADC_CMP_CTRL */
bool bCmpEnable; /*!< Enable hardware compare */
ADC_CmpChannelType eCmpSingleChn; /*!< 0: ADC compare on all channels;
1: ADC compare on the selected channel */
uint8_t u8CmpChnSel; /*!< Compare channel selection */
/* ADC_CMP_TR */
uint16_t u16HighThres; /*!< Compare high threshold */
uint16_t u16LowThres; /*!< Compare low threshold */
} ADC_CompareType;
/**
* @brief Defines the interrupt configuration
*
* This structure is used to configure the enabled interrupts and interrupt
* callbacks for ADC
*
*/
typedef struct
{
/* ADC_INT_ENABLE */
bool bConversionCompleteIntEn; /*!< Enable interrupt when conversion completed */
bool bOverRunIntEn; /*!< Enable interrupt when overrun occured */
bool bAnalogCmpIntEn; /*!< Enable interrupt when conversion result lays in the compare threshold */
bool bEndOfSeqGroupIntEn; /*!< Enable interrupt when sequence group complete >*/
uint32_t *pResultBuffer; /*!< When conversion complete interrupt is enabled, you shall provide the
result buffer to store the conversion results, this buffer only used for mode 0 ~ 3 */
uint32_t *pSequenceGroupResultBuffer[ADC_SEQUENCE_GROUP_CNT]; /*!< When conversion complete interrupt is enabled, you shall provide the
result buffer to store the conversion results, these buffer only used for mode 4 */
ADC_ConvCompleteCallbackType pConvCompleteNotify; /*!< Conversion complete interrupt callback */
ADC_OverRunInterruptCallbackType pOverRunNotify; /*!< Overrun interrupt callback */
ADC_CompareInterruptCallbackType pCompareNotify; /*!< Compare interrupt callback */
ADC_EndOfSeqGroupInterruptCallbackType pEndOfSeqGroupNotify; /*!< End of Sequence End callback >*/
} ADC_InterruptType;
/**
* @brief Defines the DMA configuretion
*
* This structure is used to configure the DMA result transfer feature for ADC
*
*/
typedef struct
{
bool bDmaEnable; /*!< Enable DMA for the ADC */
ADC_SequenceGroupIndex eSeqGroupIndex; /*!< Only valid when SequenceGroupEn = true, otherwish ignore this */
DMA_InstanceType eDmaInstance; /*!< The instance of DMA to use */
DMA_ChannelType eDmaChannel; /*!< The DMA channel used to transfer the ADC conversion results */
uint8_t u8ChannelPriority; /*!< The DMA channel priority, higher value means higher priority.
The priority for different channels must be unique. Default priority
value is same the channel number */
uint32_t *pResultBuffer; /*!< Buffer to store the ADC conversion results */
ADC_ConvCompleteCallbackType pConvCompleteNotify; /*!< DMA transfer complete callback */
} ADC_DmaType;
/**
* @brief Provide the default values of ADC_InitType
*
* @param pInitCfg the structure to initialize
*/
void ADC_InitStructure(ADC_InitType *const pInitCfg);
/**
* @brief Initialize the ADC instance
*
* @param eInstance the ADC instance to init
* @param pInitCfg the configurations of the ADC instance
*/
void ADC_Init(const ADC_InstanceType eInstance, const ADC_InitType *const pInitCfg);
/**
* @brief De-initialize the ADC instance
*
* Restore the ADC instance to its reset state
*
* @param eInstance the ADC instance to de-init
*/
void ADC_DeInit(const ADC_InstanceType eInstance);
/**
* @brief Configure the ADC sample channels
*
* @param eInstance the ADC instance to use
* @param pChannels the channels to use
* @param u8ChnCnt the quantity of channels
*/
void ADC_InitChannel(const ADC_InstanceType eInstance, const ADC_ChannelCfgType aChannels[],
const uint8_t u8ChnCnt);
/**
* @brief Configure the Sequence groups
*
* @param eInstance the ADC instance to use
* @param aSeqGroup the sequence groups to use
* @param u8SeqGroupCnt the quantity of sequence groups
*/
void ADC_InitSequenceGroup(const ADC_InstanceType eInstance, const ADC_SequenceGroupType aSeqGroup[],
const uint8_t u8SeqGroupCnt);
/**
* @brief Configure the hardware compare feature of ADC
*
* @param eInstance the ADC instance to use
* @param pCmpCfg the compare paremeters
*/
void ADC_InitCompare(const ADC_InstanceType eInstance, const ADC_CompareType *const pCmpCfg);
/**
* @brief Configure the interrupt of ADC
*
* @param eInstance the ADC instance to use
* @param pInterruptCfg the interrupt paremeters
*/
void ADC_InitInterrupt(const ADC_InstanceType eInstance,
const ADC_InterruptType *const pInterruptCfg);
/**
* @brief Configure the DMA feature of ADC
*
* @param eInstance the ADC instance to use
* @param pAdcDmaCfg the DMA paremeters for the ADC instance
*/
void ADC_InitDmaChannel(const ADC_InstanceType eInstance, const ADC_DmaType *const pAdcDmaCfg);
/**
* @brief Enable the ADC instance
*
* @param eInstance the ADC instance to enable
* @return ADC_StatusType whether ADC is enabled successfully
*/
ADC_StatusType ADC_Enable(const ADC_InstanceType eInstance);
/**
* @brief Disable the ADC instance
*
* @param eInstance the ADC instance to disable
* @return ADC_StatusType whether ADC is disabled successfully
*/
ADC_StatusType ADC_Disable(const ADC_InstanceType eInstance);
/**
* @brief Start the ADC conversion
*
* If the ADC sequence mode is single or continuous, and the trigger mode is ADC_TRIGMODE_SW,
* the adc conversion will start immediately. Otherwise, the ADC will wait for the trigger
* signal to start the conversion
*
* @param eInstance the ADC instance to start
*/
void ADC_Start(const ADC_InstanceType eInstance);
/**
* @brief Stop the ADC conversion
*
* If the ADC sequence mode is single, it will stop the ongoing conversion. If no ongoing
* conversion, it will have no effect. If the ADC sequence mode is continuous or discontinuous,
* it will stop the ongoing conversion and meanwhile the further conversions.
*
* @param eInstance the ADC instance to stop
* @return ADC_StatusType whether ADC is stopped successfully
*/
ADC_StatusType ADC_Stop(const ADC_InstanceType eInstance);
/**
* @brief Reset the ADC hardware
*
* @param eInstance the ADC instance to reset
*/
void ADC_Reset(const ADC_InstanceType eInstance);
/** @}*/
/** @}*/ /* fc7xxx_driver_adc */
#if defined(__cplusplus)
}
#endif
#endif

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/**
* @file fc7xxx_driver_aontimer.h
* @author Flagchip
* @brief FC7xxx aontimer driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240
********************************************************************************/
#ifndef DRIVER_INCLUDE_FC7XXX_DRIVER_AONTIMER_H_
#define DRIVER_INCLUDE_FC7XXX_DRIVER_AONTIMER_H_
#include "HwA_aontimer.h"
/**
* @addtogroup fc7xxx_driver_aontimer
* @{
*/
/** @brief Aontimer return type. */
typedef enum
{
AONTIMER_STATUS_SUCCESS = 0U, /**< Aontimer status is success.*/
AONTIMER_STATUS_PARAM_INVALID = 1U, /**< Aontimer failed for param invalid.*/
AONTIMER_STATUS_CLOCK_INVALID = 2U /**< Aontimer failed for colck invalid.*/
} AONTIMER_StatusType;
/** @brief Aontimer debug mode */
typedef enum
{
AONTIMER_DBG_COUNTER_STOP = 0x00U, /**< Aontimer is stop in debug mode.*/
AONTIMER_DBG_COUNTER_RUNNING = 0x01U /**< Aontimer is running in debug mode.*/
} AONTIMER_DebugType;
/** @brief Aontimer mode. */
typedef enum
{
AONTIMER_COUNTER_MODE = 0, /**< In this mode ,the clock source is internal.*/
AONTIMER_PULSE_MODE /**< In this mode ,the clock source is external(pin/trgsel).*/
} AONTIMER_ModeType;
/** @brief callback function type */
typedef void (*Aontimer_InterruptCallBackType)(void);
typedef struct
{
bool bIntEn; /**< whether to use interrupt */
Aontimer_InterruptCallBackType pIsrNotify; /**< the notification function of interrupt */
} AONTIMER_IntType;
/** @brief Aontimer Initialization struct type */
typedef struct
{
AONTIMER_ModeType eMode; /**< enumeration of aontier mode */
AONTIMER_DebugType eDbgMode; /**< enumeration of aontier debug mode */
bool bBypassEn; /**< Whether to use prescaler in counter mode or use glitch filter in pulse mode,
if set input value is true ,then not use the prescaler or glitch filter.*/
AONTIMER_PulseClkSrcType ePulseClkSrc; /**< clock source of pulse mode */
AONTIMER_PulsePolarityType ePulsePol; /**< polarity of pulse mode */
uint8_t u8PulseFilterWidth; /**< the width of glitch filter in pulse mode , the range of the input value is :1~15,
and the range of glitch filter is :2^1 ~ 2^15. */
uint8_t u8Prescaler; /**< the width of prescaler in counter mode, the range of the input value is :0~15,
and the range of prescaler is :2^1 ~ 2^16. */
AONTIMER_ClkSrcType eClkSrc; /**< clock source of counter mode */
uint16_t u16StartValue; /**< start value of counter mode ,the range is : 0 ~ 65535 */
} AONTIMER_InitType;
/* global function */
/**
* @brief Initialize aontimer instance
*
* @param pInitStruct Aontimer Initialize structure
*/
void AONTIMER_Init(const AONTIMER_InitType *const pInitStruct);
/**
* @brief De-initialize aontimer instance
*
*/
void AONTIMER_Deinit(void);
/**
* @brief Initialize aontimer interrupt functionality
*
* @param pIntStruct Aontimer interrupt structure
* @return Aontimer return type
* @note this function will disable timer
*/
AONTIMER_StatusType AONTIMER_InitInterrupt(const AONTIMER_IntType *const pIntStruct);
/**
* @brief Enable AONTIMER interrupt
* @note this function will enable AONTIEMR timer.
*/
void AONTIMER_EnableInterrupt(void);
/**
* @brief Disable AONTIMER interrupt
* @note this function will enable AONTIEMR timer.
*
*/
void AONTIMER_DisableInterrupt(void);
/**
* @brief Start Aontimer
*
*/
void AONTIMER_StartTimer(void);
/**
* @brief Stop Aontimer
*
*/
void AONTIMER_StopTimer(void);
/**
* @brief Update value of aontimer counter
*
* @param u16StartValue input value, range : 0~65535
*/
void AONTIMER_UpdateCounterValue(const uint16_t u16StartValue);
/** @}*/ /* fc7xxx_driver_aontimer */
#endif /* DRIVER_INCLUDE_FC7XXX_DRIVER_AONTIMER_H_ */

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/**
* @file fc7xxx_driver_cmp.h
* @author Flagchip
* @brief FC7xxx CMP driver type definition and API
* @version 0.1.0
* @date 2024-01-15
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_CMP_H_
#define _DRIVER_FC7XXX_DRIVER_CMP_H_
#include "HwA_cmp.h"
#if defined(__cplusplus)
extern "C" {
#endif
/********* Local typedef ************/
/**
* @brief The CMP complete interrupt callback function prototype
*
*/
typedef void (*CMP_CompleteIntCallback)(void);
/**
* @brief The instance index of the CMP Dac parts
*/
typedef struct
{
bool bDacEn; /*!< CMP DAC enable/disable */
uint8_t u8DacData; /*!< CMP DAC output voltage, output = Vin / 256 * (aDacData + 1) */
CMP_DacEnableSrcType eDacEnsrc; /*!< CMP DAC enable selection(DCR,CCR0) */
CMP_DacVinRefSelType eVinRefSel; /*!< CMP DAC high voltage reference (vrefh0,vrefh1) */
} CMP_DacType;
/**
* @brief The instance index of the CMP Mux parts
*/
typedef struct
{
CMP_INSrcSelType eINPSel; /*!< CMP input positive select(DAC or analog mux) */
CMP_INSrcSelType eINNSel; /*!< CMP input negative select(DAC or analog mux) */
CMP_MuxSelType ePSelMux; /*!< CMP input positive mux select, this is ignored in channel scan mode */
CMP_MuxSelType eNSelMux; /*!< CMP input negative mux select, this is ignored in channel scan mode */
CMP_MuxSelType eChannelScanFixedChannel; /*!< CMP channel scan fixed channel select, this is ignored if DAC is enabled */
CMP_PortSelType eChannelScanFixedPort; /*!< CMP channel scan fixed channel port select */
} CMP_MuxType;
/**
* @brief The instance index of the CMP Comparator parts
*/
typedef struct
{
bool bStopModEn; /*!< CMP stop mode enable */
bool bOutToPackagePinEn; /*!< CMP output to package pin enable */
bool bWinSampleInvertEn; /*!< CMP window/sample signal invert enable */
bool bEventCloseWinEn; /*!< CMP out event close window enable */
bool bAnalogConfTransByp; /*!< CMP analog configuration transition bypass enable */
uint16 u16AnalogConfTransBypCnt; /*!< Target count value for bypass function */
uint8_t u8FilterPeriod; /*!< CMP set Filter Sample Period */
CMP_ModSelType eModSel; /*!< CMP set function mode */
CMP_InvertType eInvert; /*!< CMP output Invert or not(invert, non-invert) */
CMP_OutSelectType eOutSelect; /*!< CMP output filter or not(CMPO = CMPOUT_FILTER/CMPOUT_WIN) */
CMP_OutWinLevelType eOutWinLevel; /*!< CMP output when window close(hold, userdefine) */
CMP_OutWinLevel_UserDefType eOutWin; /*!< CMP output under userdefine (0, 1) */
CMP_EventType eEventSelect; /*!< CMP output event cause window close(rising edge, falling edge) */
CMP_FilterCntType eFilterCnt; /*!< CMP filter count numbers(0,1,2,3,4) */
CMP_SpeedModSelType eSpeedMod; /*!< CMP speed mode(low,high) */
CMP_HystCtrlType eHystCrtl; /*!< CMP hysteresis internal control(0,1,2,3) */
} CMP_ComparatorType;
/**
* @brief Defines the comparator interrupt configuration
*
* @note This structure is used to configure CMP interrupt
* Implements : CMP_InterruptType
*/
typedef struct
{
bool bRisingIntEn; /*!< Enable/disable rising interrupt */
bool bFallingIntEn; /*!< Enable/disable falling interrupt */
bool bChannelScanFlagIntEn; /*!< Enable/disable channel scan flag interrupt */
CMP_CompleteIntCallback pInterrupterNotify; /*!< CMP complete interrupt callback */
} CMP_InterruptType;
/**
* @brief Defines the comparator dma configuration
*
* @note This structure is used to configure CMP dma
* Implements : CMP_DmaType
*/
typedef struct
{
bool bRisingDmaEn; /*!< Enable/disable rising edge trigger dma */
bool bFallingDmaEn; /*!< Enable/disable falling edge trigger dma */
} CMP_DmaType;
/**
* @brief Defines the comparator channel selected in channel scan mode
*
* @note This structure is used to configure a CMP channel that want to be enabled in channel scan sequence
* Implements : CMP_ChannelScanChannelCfgType
*/
typedef struct
{
CMP_MuxSelType eChannel; /*!< Enabled channel */
bool bPreSetState; /*!< Preset state for the given channel */
bool bCurState; /*!< Current state for the given channel */
} CMP_ChannelScanChannelCfgType;
/**
* @brief Defines the comparator channel scan configuration
*
* @note This structure is used to configure CMP channel scan
* Implements : CMP_ChannelScanType
*/
typedef struct
{
uint8_t u8ChannelScanInitModulus; /*!<Compartor and DAC initialization delay modulus */
uint8_t u8ChannelScanNumOfSampleClocks; /*!<Number of smaple clocks later the the sample operation takes place */
bool bComparisonResultAutoClear; /*!<Enable/disable comparison result auto clear */
} CMP_ChannelScanType;
/**
* @brief Defines the comparator configuration
*
* @note This structure is used to configure CMP
* Implements : CMP_InitType
*/
typedef struct
{
CMP_DacType tDacConfig; /*!< CMP DAC configure */
CMP_MuxType tMuxConfig; /*!< CMP MUX configure */
CMP_ComparatorType tComparatorConfig; /*!< CMP comparator configure */
CMP_ChannelScanType tChannelScanConfig;/*!< CMP channel scan configure */
} CMP_InitType;
/********* Local function ************/
/**
* @brief set CMP module enable
*
* @param eInstance the CMP instance to use
*/
void CMP_Enable(const CMP_InstanceType eInstance);
/**
* @brief set CMP module disable
*
* @param eInstance the CMP instance to use
*/
void CMP_Disable(const CMP_InstanceType eInstance);
/**
* @brief set CMP module channel scan mode enable
*
* @param eInstance the CMP instance to use
*/
void CMP_CSEnable(const CMP_InstanceType eInstance);
/**
* @brief set CMP module channel scan mode disable
*
* @param eInstance the CMP instance to use
*/
void CMP_CSDisable(const CMP_InstanceType eInstance);
/**
* @brief set CMP init
*
* @param eInstance the CMP instance to use
* @param pInitCfg the CMP init type
*/
void CMP_Init(const CMP_InstanceType eInstance, const CMP_InitType *const pInitCfg);
/**
* @brief set CMP init interrupt
*
* @param eInstance the CMP instance to use
* @param pInterruptCfg the CMP init interrupter type
*/
void CMP_InitInterrupt(const CMP_InstanceType eInstance, const CMP_InterruptType *const pInterruptCfg);
/**
* @brief set CMP init interrupt dma
*
* @param eInstance the CMP instance to use
* @param pInterruptDmaCfg the CMP init interrupt dma type
*/
void CMP_InitInterrupt_Dma(const CMP_InstanceType eInstance, const CMP_DmaType *const pInterruptDmaCfg);
/**
* @brief get CMP filtered output
*
* @param eInstance the CMP instance to use
* @return CMP filtered output
*/
bool CMP_GetCmpOut(const CMP_InstanceType eInstance);
/**
* @brief set CMP Dac output
*
* @param eInstance the CMP instance to use
* @param eDacData input voltage value
* @note voltage = (VinRef / 256) * (eDacData + 1)
*/
void CMP_SetDacData(const CMP_InstanceType eInstance, uint8_t u8Data);
/**
* @brief get CMP interrupter flag status
*
* @param eInstance the CMP instance to use
* @return CMP output status
*/
CMP_OutStatus CMP_GetOutFlagStatus(const CMP_InstanceType eInstance);
/**
* @brief get CMP channel scan flag status
*
* @param eInstance the CMP instance to use
* @return CMP channel scan status
*/
bool CMP_GetChannelScanFlagStatus(const CMP_InstanceType eInstance);
/**
* @brief clear CMP interrupter flag
*
* @param eInstance the CMP instance to use
*/
void CMP_ClearIntFlag(const CMP_InstanceType eInstance);
/**
* @brief set CMP rising & falling edge interrupter enable/disable
*
* @param eInstance the CMP instance to use
* @param bRisingEn rising edge enable/disable flag
* @param bFallingEn falling edge enable/disable flag
*/
void CMP_SetIntEn(const CMP_InstanceType eInstance, const CMP_InterruptType *const pInterruptCfg);
/**
* @brief set CMP dma enable
*
* @param eInstance the CMP instance to use
*/
void CMP_DmaEnable(const CMP_InstanceType eInstance);
/**
* @brief set CMP dma disable
*
* @param eInstance the CMP instance to use
*/
void CMP_DmaDisable(const CMP_InstanceType eInstance);
/**
* @brief set CMP channel scan channels
*
* @param eInstance the CMP instance to use
* @param s_tChnCfg the structure array of CMP channel channels
* @param u8ChnCnt the length of s_tChnCfg array
*/
void CMP_SetCSChannls(const CMP_InstanceType eInstance, const CMP_ChannelScanChannelCfgType s_tChnCfg[], const uint8_t u8ChnCnt);
/**
* @brief get CMP channel scan channels out
*
* @param eInstance the CMP instance to use
* @param s_tChnCfg the structure array of CMP channel channels
* @param u8ChnCnt the length of s_tChnCfg array
*/
void CMP_GetCSChannlsOut(const CMP_InstanceType eInstance, CMP_ChannelScanChannelCfgType s_tChnCfg[], const uint8_t u8ChnCnt);
/**
* @brief get CMP channel scan status
*
* @param eInstance the CMP instance to use
*/
bool CMP_GetCmpCSActive(const CMP_InstanceType eInstance);
/* fc7xxx_driver_cmp */
#ifdef __cplusplus
}
#endif
#endif /* _DRIVER_FC4XXX_DRIVER_CMP_H_ */

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/**
* @file fc7xxx_driver_cmu.h
* @author Flagchip085
* @brief FC7xxx CMU driver type definition and API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_CMU_H_
#define _DRIVER_FC7XXX_DRIVER_CMU_H_
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_cmu
* @{
*/
#include "device_header.h"
/** @brief CMU Instance type. */
typedef enum
{
CMU_INSTANCE_0 = 0,
CMU_INSTANCE_1 = 1,
CMU_INSTANCE_2 = 2,
CMU_INSTANCE_3 = 3,
CMU_INSTANCE_4 = 4,
CMU_INSTANCE_INVALID = CMU_INSTANCE_COUNT
} CMU_InstanceType;
/**
* @brief CMU operation return values
*
*/
typedef enum
{
CMU_VALID = 0x0U, /*!< The CMU status valid */
CMU_CLK_ERROR = 0x1U, /*!< The CMU related clock error */
} CMU_StatusType;
typedef enum
{
CMU_CMU4_REF_CLK_NONE = 0U, /*Not Select Cmu4 Reference clock.*/
CMU_CMU4_REF_CLK_FOSC = 1U, /*Select the FOSC as Cmu4 Reference clock.*/
CMU_CMU4_REF_CLK_SIRC = 2U /*Select the SIRC as Cmu4 Reference clock.*/
} CMU_Cmu4ClkSrcType;
typedef enum
{
CMU_INTERRUPT_NONE = 0, /*!< No CMU interrupt. */
CMU_INTERRUPT_LOC = 1, /*!< CMU_ST[LOC] bit, Monitor clock is loss. */
CMU_INTERRUPT_MIS = 2 /*!< CMU_ST[MIS] bit, Monitor clock is mismatched. */
} CMU_InterruptType;
typedef enum
{
CMU_STOP_MODE = 0, /*!< CMU enable in Stop Mode. */
CMU_STANDBY_MODE = 1 /*!< CMU enable in Standby Mode. */
} CMU_LowpowerModeType;
typedef enum
{
CMU_REFCLK_NODIV = 0U, /*!< Clock output is disabled. */
CMU_REFCLK_DIV_BY2 = 1U, /*!< Divided by 2. */
CMU_REFCLK_DIV_BY4 = 2U, /*!< Divided by 4. */
CMU_REFCLK_DIV_BY8 = 3U, /*!< Divided by 8. */
CMU_REFCLK_DIV_BY16 = 4U, /*!< Divided by 16. */
CMU_REFCLK_DIV_BY32 = 5U, /*!< Divided by 32. */
CMU_REFCLK_DIV_BY64 = 6U, /*!< Divided by 64. */
CMU_REFCLK_DIV_BY128 = 7U /*!< Divided by 128. */
} CMU_RefClockDivType;
/**
* @brief CMU Channel ISR callback function prototype
*
*/
typedef void (*CMU_ISRCallbackType)(const CMU_InstanceType eInstance, const CMU_InterruptType eStatus);
/** @brief CMU configure structure. */
typedef struct
{
bool bIntEnable; /*!< CMU_CTRL[IRQ_EN] bit, interrupt enable, if this bit asserted, either LOC or MIS asserted can lead the interrupt.*/
bool bLpen; /*!< CMU_CTRL[LP_EN] bit, standby mode enable, need STOP_EN asserted.*/
bool bSten; /*!< CMU_CTRL[STOP_EN] bit, stop mode enable.*/
bool bEnable; /*!< CMU_CTRL[EN] bit, CMU enable on initialization. If bEnable is false, the CMU is configured only,
and should be enabled by calling CMU_Enable.*/
uint8_t u8PerMonitorWindow; /*!< CMU_PERIOD[WINDOW] bits, Period Monitor mode WIDOW. If u8PerMonitorWindow exceed the max period,
the max period value will be used instead of u8PerMonitorWindow.*/
bool bPerMonitorEnable; /*!< CMU_PERIOD[EN] bit, Period Monitor mode ENABLE.*/
CMU_RefClockDivType eDiv; /*!< Divider of reference clock.*/
CMU_ISRCallbackType pIsrCallback; /*!< ISR Callback.*/
} CMU_CfgType;
/* global functions */
/**
* @brief Initialize the CMU instance.
*
* @param eInstance Cmu instance.
* @param pInitCfg Init configuration.
* @return Cmu status.
*/
CMU_StatusType CMU_Init(CMU_InstanceType eInstance, const CMU_CfgType *pInitCfg);
/**
* @brief Enable CMU
*
* @param eInstance CMU Instance
*/
void CMU_Enable(CMU_InstanceType eInstance);
/**
* @brief Disable CMU instance, this would needed for low powermode if monitor/referrence clock would be shut down
*
* @param eInstance CMU Instance
*/
void CMU_Disable(CMU_InstanceType eInstance);
/**
* @brief Get the interrupt type of CMU.
*
* @param eInstance CMU Instance
* @return The interrupt type.
*/
CMU_InterruptType CMU_GetInterruptType(CMU_InstanceType eInstance);
/**
* @brief Set the cmu4 reference source clock.
*
* @param eSrc Source clock type.
* @return CMU_VALID Set CMU reference clock successfully
* CMU_CLK_ERROR Set CMU reference clock failed
*/
CMU_StatusType CMU_SetCmu4RefSrc(CMU_Cmu4ClkSrcType eSrc);
/**
* @brief Enable CMU interrupt.
*
* @param eInstance CMU Instance.
*/
void CMU_EnableInterrupt(CMU_InstanceType eInstance);
/**
* @brief Disable CMU interrupt.
*
* @param eInstance CMU Instance.
*/
void CMU_DisableInterrupt(CMU_InstanceType eInstance);
/**
* @brief Get CMU counter value.
*
* @param eInstance CMU Instance.
*/
uint32_t CMU_GetCount(CMU_InstanceType eInstance);
/**
* @brief Get Min counter value.
*
* @param eInstance CMU Instance.
*/
uint32_t CMU_GetMinCount(CMU_InstanceType eInstance);
/**
* @brief Get Max counter value.
*
* @param eInstance CMU Instance.
*/
uint32_t CMU_GetMaxCount(CMU_InstanceType eInstance);
/**
* @brief Enable cmu low power mode.
*
* @param eInstance CMU Instance.
* @param eMode Low power mode.
* @param bModeEnable Mode enable
* @param bRestartEnable Restart enable.
*/
void CMU_LowPowerModeEnable(CMU_InstanceType eInstance, CMU_LowpowerModeType eMode, bool bModeEnable, bool bRestartEnable);
/** @}*/ /* fc7xxx_driver_cmu */
#if defined(__cplusplus)
}
#endif
#endif

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/**
* @file fc7xxx_driver_cordic.h
* @author Flagchip
* @brief FC7xxx Cordic driver type definition and API
* @version 0.1.0
* @date 2024-01-11
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_CORDIC_H_
#define _DRIVER_FC7XXX_DRIVER_CORDIC_H_
#include "device_header.h"
#include "HwA_cordic.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @brief The circular Sin and cos type
*
*/
typedef struct
{
float sinx;
float cosx;
} CORDIC_SinCos_Type;
/**
* @brief The circular Sinh and cosh type
*
*/
typedef struct
{
float sinxh;
float cosxh;
} CORDIC_SinhCosh_Type ;
/**
* @brief The radical type
*
*/
typedef float CORDIC_Radical_Type;
/**
* @brief The arctan type
*
*/
typedef float CORDIC_Arctan_Type;
/**
* @brief The arctanh type
*
*/
typedef float CORDIC_Arctanh_Type;
/**
* @brief The arctan type
*
*/
typedef float CORDIC_Ln_Type;
/**
* @brief The arctanh type
*
*/
typedef float CORDIC_Sqrt_Type;
/**
* @brief The function to calculate sin & cos
*
* @param radian the input value to calculate
*/
CORDIC_SinCos_Type Cordic_Circular_Sin_Cos(const float radian);
/**
* @brief The function to calculate circular radical add
*
* @param1 x the first input value
*
* @param2 y the second input value
*/
CORDIC_Radical_Type Cordic_Circular_Radical_Add(const float x, const float y);
/**
* @brief The function to calculate circular arctan
*
* @param y the input value
*/
CORDIC_Arctan_Type Cordic_Circular_Arctan_F(const float y);
/**
* @brief The function to calculate circular arctan
*
* @param1 x the first input value
*
* @param2 y the second input value
*/
CORDIC_Arctan_Type Cordic_Circular_Arctan(const int32_t x, const int32_t y);
/**
* @brief The function to calculate circular Sinh & Cosh
*
* @param z the input value
*/
CORDIC_SinhCosh_Type Cordic_Circular_Sinh_Cosh(const float z);
/**
* @brief The function to calculate circular radical sub
*
* @param1 x the first input value
*
* @param2 y the second input value
*/
CORDIC_Radical_Type Cordic_Circular_Radical_Sub(const float x, const float y);
/**
* @brief The function to calculate circular arctanh
*
* @param y the input value
*/
CORDIC_Arctanh_Type Cordic_Circular_Arctanh(const float y);
/**
* @brief The function to calculate ln
*
* @param y the input value
*/
CORDIC_Ln_Type Cordic_Extended_LN(const float y);
/**
* @brief The function to calculate sqrt
*
* @param y the input value (0.0267120594,2.3397671865)
*/
CORDIC_Sqrt_Type Cordic_Extended_Sqrt(const float y);
#if defined(__cplusplus)
}
#endif
#endif /* end of DRIVER_UART_H_ */

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/**
* @file fc7xxx_driver_cpm.h
* @author Flagchip
* @brief FC7xxx CPM driver type definition and API
* @version 0.1.0
* @date 2024-01-5
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-1-5 Flagchip120 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_CPM_H_
#define _DRIVER_FC7XXX_DRIVER_CPM_H_
#include "device_header.h"
#include "HwA_cpm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_cpm
* @{
*/
/** @brief Cpm interrupt notification type */
typedef void (*CPM_InterruptCallBackType)(void);
/** @brief Cpm interrupt configuration type */
typedef struct
{
uint8_t u8CpmEnable; /**< whether enable cpm interrupt */
FPU_IntType eFPU_IntType; /**< the type of interrupt */
CPM_InterruptCallBackType pIsrNotify; /**< Cpm interrupt notification function pointer */
} CPM_InterruptType;
#ifdef FPU_USED_ENABLE
/**
* @brief CPM_Read_FPSCR
* Return the current value of FPSCR
* @return u32RetVal
*/
uint32_t CPM_Read_FPSCR(void);
/**
* @brief CPM_Write_FPSCR
*
* @param u32SetVal set the value for FPSCR
*/
void CPM_Write_FPSCR(uint32_t u32SetVal);
/**
* @brief Deinit Cpm set interrupt
*
* Restore the Cpm FISCR to its reset state
*/
void CPM_DeInitInterrupt(void);
#endif
/* ----------------------------------------------------------------------------
-- Global Api
---------------------------------------------------------------------------- */
/**
* @brief Configures the CPM module interrupts.
*
* This function configures the CPM module interrupts to enable/disable various interrupt sources.
*
* @param eIntSrc CPM FPU interrupt type. refer CPM FISCR register
* @param bEnable true: interrupt enable, false:interrupt disable.
*/
void CPM_FpuIntMode(FPU_IntType eIntSrc, bool bEnable);
/**
* @brief Get CPM Interrupt occurred flag
*
* This function returns the interrupt flag.
*
* @param eIntSrc CPM FPU interrupt type. refer CPM FISCR register
* @return true interrupt occurred
* @return false No interrupt
*/
bool CPM_GetFpuIntStatus(FPU_IntType eIntSrc);
/**
* @brief Cpm set interrupt
*
* @param pIntStruct interrupt structure pointer
* @return Cpm return type
*/
CPM_RetType CPM_InitInterrupt(const CPM_InterruptType *pIntStruct);
#if defined(__cplusplus)
}
#endif
/** @}*/ /* fc7xxx_driver_cpm */
#endif

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/**
* @file fc7xxx_driver_crc.h
* @author Flagchip
* @brief FC7xxx CRC driver type definition and API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_CRC_H_
#define _DRIVER_FC7XXX_DRIVER_CRC_H_
#include "HwA_crc.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_crc
* @{
*/
#define CRC_INSTANCE (0U)
#define CRC_DEFAULT_POLY (0x1021U)
#define CRC_DEFAULT_INTVAL (0U)
/********* Local typedef ************/
/**
* @brief Defines the crc configuration
*
* This structure is used to configure the crc
*
* Implements : CRC_InitType
*/
typedef struct
{
uint32_t u32Polynomial; /*!< the polynomial value of crc */
uint32_t u32SeedValue; /*!< the seed value of crc */
CRC_WriteDataSwapType eWriteDataSwap; /*!< the data swap for write(none,bits,bytes or both) */
CRC_ReadDataSwapType eReadDataSwap; /*!< the data swap for read(none,bits,bytes or both) */
CRC_ReadDataFXORType eReadDataFXOR; /*!< complement of reading crc data(none or FXOR) */
CRC_BitWidthType eBitWidth;
} CRC_InitType;
/******* Function Prototype *********/
/**
* @brief set CRC module initialization
*
* @param eInstance the CRC instance to use
* @param pInitCfg the CRC_InitType type
*/
void CRC_Init(uint8_t u8Instance, const CRC_InitType *const pInitCfg);
/**
* @brief CRC default Init
*
* @param eInstance the CRC instance to use
* @note initialization CRC module with default value
* CRC-32, initial value(seed value) = 0,
* polynomial value = 0x1021,
* none swap and FXOR
*/
void CRC_DeInit(uint8_t u8Instance);
/**
* @brief get CRC result
*
* @param eInstance the CRC instance to use
*/
uint32_t CRC_GetCrcResult(uint8_t u8Instance);
/**
* @brief set CRC DATA register 8bits
*
* @param eInstance the CRC instance to use
* @param u8Data the data to be set
*/
void CRC_SetCalcData_U8(uint8_t u8Instance, uint8_t u8Data);
/**
* @brief set CRC DATA register 16bits
*
* @param eInstance the CRC instance to use
* @param u16Data the data to be set
*/
void CRC_SetCalcData_U16(uint8_t u8Instance, uint16_t u16Data);
/**
* @brief set CRC low lower register
*
* @param eInstance the CRC instance to use
* @param u32Data the data to be set
*/
void CRC_SetCalcData_U32(uint8_t u8Instance, uint32_t u32Data);
/**
* @brief set CRC seed value
*
* @param eInstance the CRC instance to use
* @param u32SeedVal seed value
*/
void CRC_SetSeed(uint8_t u8Instance, uint32_t u32SeedVal);
/**
* @brief set CRC input data
*
* @param eInstance the CRC instance to use
* @param pData data pointer
* @param u32DataSize input data size
*/
void CRC_SetInputData(uint8_t u8Instance, const uint8_t * pData, uint32_t u32DataSize);
/** @}*/ /* fc7xxx_driver_crc */
#if defined(__cplusplus)
}
#endif
#endif /* _DRIVER_FC4XXX_DRIVER_CRC_H_ */

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/**
* @file fc7xxx_driver_csc.h
* @author Flagchip085
* @brief FC7xxx csc driver type definition and API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_CSC_H_
#define _DRIVER_FC7XXX_DRIVER_CSC_H_
#include "HwA_csc.h"
/********* Local defines ************/
#define CSC0_AONCLK_128K 128000U
#define CSC0_AONCLK_32K 32000U
#define CSC0_AONCLK_SOSC_32K 32768U
#define CSC0_AONCLK_1K 1000U
/********* Local typedef ************/
/**
* @brief Stop ack status type
*
*/
typedef enum
{
STOPMODE_PROCESSS = 0U, /*!< The peripheral is processing(not in stop mode) */
STOPMODE_READY = 1U /*!< The peripheral is already in stop mode*/
} CSC_StopModeStatusType;
/**
* @brief CSC return status
*
*/
typedef enum
{
CSC_E_OK = 0U, /*!< Return ok */
CSC_E_NOT_OK, /*!< Return not ok */
CSC_E_LOCK, /*!< Return error because the register is locked */
CSC_E_NO_PERM, /*!< Return error because the CPU has no permission */
CSC_E_PARAM /*!< Return error because the parameter is invalid */
} CSC_RetStatusType;
/**
* @brief CSC setting target
*
*/
typedef enum
{
CSC_STOPACK = 0U, /*!< stop ack */
CSC_STOPREQ /*!< stop request */
} CSC_SetTargetType;
/**
* @brief CSC stop mode/ack/request control group info
* @note Must match with peripheal enum
*/
typedef enum
{
CSC_STOP_CTRL_GROUP_0 = 0U, /*!< CSC stop mode/ack/request control group 0 */
CSC_STOP_CTRL_GROUP_1, /*!< CSC stop mode/ack/request control group 1 */
CSC_STOP_CTRL_GROUP_2, /*!< CSC stop mode/ack/request control group 2 */
} CSC_PeriphGrpType;
/**
* @brief CSC0_AONCLKSR clock source info
*
*/
typedef struct
{
bool HclkEn; /*!< CPUx HCLOCK Enable */
CSC_HandShakeModeType eHandShakeMode; /*!< CCMx Handshake Mode */
} CSC_CCMCfgType;
/**
* @brief Indicate the clock status for each clock source in clock tree list
*
*/
typedef enum
{
CSC0_CLOCK_UNDEFINE = 0U, /*!< Clock status undefined from power on */
CSC0_CLOCK_DISABLE = 1U, /*!< clock source set as disabled */
CSC0_CLOCK_VALID = 2U, /*!< clock set succeed */
CSC0_CLOCK_ERROR = 3U, /*!< clock set failed */
CSC0_CLOCK_UNKNOWN = 4U
} CSC0_ClockStatusDef;
/**
* @brief CSC0 clock source type for clock infomation querry
*
*/
typedef enum
{
CSC0_AON32K_CLK = 0U, /*!< AON32K_CLK */
CSC0_RTC_CLK = 1U, /*!< RTC_CLK */
CSC0_AON_CLK = 2U, /*!< AON_CLK */
CSC0_CLKOUT_CLK = 3U, /*!< CLKOUT_CLK */
CSC0_END_OF_CLOCKS = 4U /*!< End of CSC0 clocks */
} CSC0_ClkSrcType;
/**
* @brief CSC0_SMU control group info
*
*/
typedef enum
{
CSC0_SMU_CTRL_GROUP_0 = 0U, /*!< CSC0_SMU control group 0 */
CSC0_SMU_CTRL_GROUP_1, /*!< CSC0_SMU control group 1 */
CSC0_SMU_CTRL_GROUP_4, /*!< CSC0_SMU control group 4 */
CSC0_SMU_CTRL_GROUP_5 /*!< CSC0_SMU control group 5 */
} CSC0_SmuCtrlGrpType;
/**
* @brief Module clock status and frequency record structure
*
* */
typedef struct
{
CSC0_ClockStatusDef eClkStatus; /*!< Indicate the clock status for each clock source in clock tree list */
uint32_t u32Freq; /*!< frequency value */
} CSC0_ClockInfoType;
/**
* @brief Data type for register CSC0_CLKOUT_CTRL,mainly focus on CLKOUT setting
*
*/
typedef struct
{
bool bEnable; /*!< CSC0 ClockOut enable */
CSC0_ClockOutSrcType eClkOutSrc; /*!< CSC0 ClockOut source select */
CSC0_ClockOutDivType eDivider; /*!< CSC0 ClockOut divide ratio */
} CSC0_ClkoutType;
/**
* @brief CSC0_AONCLKSR clock source info
*
*/
typedef struct
{
CSC0_AON32KClkSrcType eAon32KSel; /*!< CSC0 32 KHz Always-on Clock Source Select */
CSC0_RTCClkSrcType eRtcSel; /*!< CSC0 RTC Clock Source Select */
CSC0_AONClkSrcType eAonSel; /*!< CSC0 AON Clock Source Select */
} CSC0_AONCLKSRType;
/**
* @brief CSC0_LP_WAKEUP low power wakeup configure type
*
*/
typedef struct
{
CSC0_LPWakeupSrcType eCfgGrp0; /*!< LP_WAKEUP_PAD0 Configure Source */
CSC0_LPWakeupSrcType eCfgGrp1; /*!< LP_WAKEUP_PAD1 Configure Source */
CSC0_LPWakeupSrcType eCfgGrp2; /*!< LP_WAKEUP_PAD2 Configure Source */
CSC0_LPWakeupSrcType eCfgGrp3; /*!< LP_WAKEUP_PAD3 Configure Source */
CSC0_LPWakeupSrcType eCfgGrp4; /*!< LP_WAKEUP_PAD4 Configure Source */
CSC0_LPWakeupPolType ePolGrp0; /*!< LP_WAKEUP_CFG0 Wakeup Polarity */
CSC0_LPWakeupPolType ePolGrp1; /*!< LP_WAKEUP_CFG1 Wakeup Polarity */
CSC0_LPWakeupPolType ePolGrp2; /*!< LP_WAKEUP_CFG2 Wakeup Polarity */
CSC0_LPWakeupPolType ePolGrp3; /*!< LP_WAKEUP_CFG3 Wakeup Polarity */
CSC0_LPWakeupPolType ePolGrp4; /*!< LP_WAKEUP_CFG4 Wakeup Polarity */
} CSC0_LPWakeupCfgType;
/********* Local function ************/
/**
* @brief set clock out. with clock out pin configure, the clock would be monitored.
* This Function may combined with SCG_ClkOut setting
* need to call SCG_SetClkOut,if clock out source set to SCG_CLKOUT. *
* @param pCsc0ClkOut to Csc0ClkOut instance for clock out configuration
* @param bLockStatus to lock current register
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_LOCK: The register has been locked and can not be written
* @note configuration sequence:
* 1. Disable CLKOUTEN
* 2. Set CLKOUTSEL
* 3. Enable CLKOUTEN
*/
CSC_RetStatusType CSC0_SetClockOut(const CSC0_ClkoutType *const pCsc0ClkOut, bool bLockStatus);
/**
* @brief set always on clock source configuration include AON32K, RTC, AONCLK clock.
*
* @param pAonclkSrcType pointer to AONCLKSR instance for AON clock source configuration
* @param bLockStatus to lock current register
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_LOCK: The register has been locked and can not be written
*/
CSC_RetStatusType CSC0_SetAonClkSrc(const CSC0_AONCLKSRType *const pAonclkSrcType, bool bLockStatus);
/**
* @brief Report the clock source status and frequency configured in MCU run time.
* The clock frequency and status would change by clock set function.
*
* @param eClkkName: the CSC0 clock source to query
* @param pFreq: frequency variable point to get the frequency value
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eClkkName invalid
*/
CSC_RetStatusType CSC0_GetCSC0ClockFreq(CSC0_ClkSrcType eClkkName, uint32_t *const pFreq);
/**
* @brief SCG MAM stall request.
* @details Need to assert the SCG_STALL to stall MAM when configuring the SCG clock source.
*
* @param bEnable: true asserts SCG MAM stall request
* false do not asserts SCG MAM stall request
* @param bLockStatus: Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK).
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eClkkName invalid
*/
CSC_RetStatusType CSC0_ScgMAMStallRequest(bool bEnable, bool bLockStatus);
/**
* @brief Set request to SMU of group 0.
*
* @param u32Value Value to be set(the or bits defined in CSC_SMU_CtrlGrp0Type,do not involve lock bit)
* @param bLockStatus Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK).
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: The u32Value contains invalid bits
* CSC_E_LOCK: The register has been locked
*/
CSC_RetStatusType CSC0_SetReqToSMUGrp0(uint32_t u32Value, bool bLockStatus);
/**
* @brief Set request to SMU of group 1.
*
* @param u32Value Value to be set(the or bits defined in CSC_SMU_CtrlGrp1Type,do not involve lock bit)
* @param bLockStatus Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK).
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: The u32Value contains invalid bits
* CSC_E_LOCK: The register has been locked
*/
CSC_RetStatusType CSC0_SetReqToSMUGrp1(uint32_t u32Value, bool bLockStatus);
/**
* @brief Set request to SMU of group 4.
*
* @param u32Value Value to be set(the or bits defined in CSC_SMU_CtrlGrp4Type,do not involve lock bit)
* @param bLockStatus Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK).
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: The u32Value contains invalid bits
* CSC_E_LOCK: The register has been locked
*/
CSC_RetStatusType CSC0_SetReqToSMUGrp4(uint32_t u32Value, bool bLockStatus);
/**
* @brief Set request to SMU of group 5.
*
* @param u32Value Value to be set(the or bits defined in CSC_SMU_CtrlGrp5Type,do not involve lock bit)
* @param bLockStatus Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK).
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: The u32Value contains invalid bits
* CSC_E_LOCK: The register has been locked
*/
CSC_RetStatusType CSC0_SetReqToSMUGrp5(uint32_t u32Value, bool bLockStatus);
/**
* @brief Set request to SMU .
*
* @param eCtrlGrp CSC0_SMU control group
* @param u32Value Value to be set(the or bits defined in CSC_SMU_CtrlGrp5Type,do not involve lock bit)
* @param bLockStatus Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK).
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_PARAM: The eCtrlGrp is invalid
* CSC_E_NOT_OK: The u32Value contains invalid bits
* CSC_E_LOCK: The register has been locked
* @note Group must be matched with u32Value which select from CSC0_SmuCtrlGrpType
*/
CSC_RetStatusType CSC0_SetReqToSMU(CSC0_SmuCtrlGrpType eCtrlGrp, uint32_t u32Value, bool bLockStatus);
/**
* @brief Configure the low power wakeup PAD output in CSC0_LP_WAKEUP register.
*
* @param eLPWakeupCfg: the low power wakeup PAD source and polarity configuration
* @param bLockStatus: Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK).
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_LOCK: The WPB of CSCx_STOP_MODERx is already locked
*/
CSC_RetStatusType CSC0_LP_WakeupPadOutputCfg(const CSC0_LPWakeupCfgType * const eLPWakeupCfg, bool bLockStatus);
/**
* @brief Set CPU stop mode control permission.
* @detail This API is used to set the CPU write permission of a CPU's stop mode registers.
* eg.If the CPU(eTargetCpuType) enter stop mode, it acknowledges the peripherals according to the configuration
* in CSCx_STOP_MODERy (x: (CPUID) range[0] , y:(GROUP) range[0,1,2]), and the CPU(eCtrlCpuType)
* has the write permission of CSCx_STOP_MODERy registers, the permission is controlled by this API.
*
* @param eTargetCpuType The target CPU to set.
* @param eCtrlCpuType The CPU that has the write permission to the CSCx_STOP_MODERy register.
* @param ePeriphGrp Peripheral group (range:0,1,2)
* @param bLockStatus Lock the WPB of CSCx_STOP_MODERx.Once locked, calling the API returns an error(CSC_E_LOCK).
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_LOCK: The WPB of CSCx_STOP_MODERx is already locked
*/
CSC_RetStatusType CSC_SetStopModeAckPermission(CSC_WPB_CpuType eTargetCpuType, CSC_WPB_CpuType eCtrlCpuType,
CSC_PeriphGrpType ePeriphGrp, bool bLockStatus);
/**
* @brief Set CPU stop mode request control permission.
* @detail This API is used to set the CPU write permission of a CPU's stop mode request registers
* to generate a stop request to peripherals
*
* @param eTargetCpuType The target CPU to acknowledges stop mode to the enabled peripherals.
* @param eCtrlCpuType The CPU that has the write permission to the CSCx_STOP_REQRx register.
* @param ePeriphGrp Peripheral group (range:0,1,2)
* @param bLockStatus Lock the WPB of CSCx_STOP_REQRx.Once locked, calling the API returns an error(CSC_E_LOCK).
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_LOCK: The WPB of CSCx_STOP_REQRx is already locked
*/
CSC_RetStatusType CSC_SetStopRequestPermission(CSC_WPB_CpuType eTargetCpuType, CSC_WPB_CpuType eCtrlCpuType,
CSC_PeriphGrpType ePeriphGrp, bool bLockStatus);
/**
* @brief Set the stop mode ack of peripheral group 0 in CSC.
*
* @param eTargetCpuType The target CPU which acknowledges the ePeriphType when entering stop mode.
* @param ePeriphType the peripheral to enable or disable the stop mode ACK
* @param bEnable true: enable the stop mode ACK
* false: disable the stop mode ACK
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_NO_PERM: Current CPU has no permission to access the register
*/
CSC_RetStatusType CSC_SetStopModeAckGrp0(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg0_PeriphType ePeriphType, bool bEnable);
/**
* @brief Set the stop request of peripheral group 0 in CSC.
*
* @param eTargetCpuType The target CPU which acknowledges the ePeriphType when entering stop mode.
* @param ePeriphType the peripheral to set stop request
* @param bEnable true: set the stop request
* false: clear the stop request
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_NO_PERM: Current CPU has no permission to access the register
*/
CSC_RetStatusType CSC_SetStopRequestGrp0(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg0_PeriphType ePeriphType, bool bEnable);
/**
* @brief Set the stop mode ACK of peripheral group 1 in CSC.
*
* @param eTargetCpuType The target CPU which acknowledges the ePeriphType when entering stop mode.
* @param ePeriphType the peripheral to enable or disable the stop mode ACK
* @param bEnable true: enable the stop mode ACK
* false: disable the stop mode ACK
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_NO_PERM: Current CPU has no permission to access the register
*/
CSC_RetStatusType CSC_SetStopModeAckGrp1(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg1_PeriphType ePeriphType, bool bEnable);
/**
* @brief Set the stop request of peripheral group 1 in CSC.
*
* @param eTargetCpuType The target CPU which acknowledges the ePeriphType when entering stop mode.
* @param ePeriphType the peripheral to set stop request
* @param bEnable true: set the stop request
* false: clear the stop request
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_NO_PERM: Current CPU has no permission to access the register
*/
CSC_RetStatusType CSC_SetStopRequestGrp1(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg1_PeriphType ePeriphType, bool bEnable);
/**
* @brief Set the stop mode ACK of peripheral group 2 in CSC.
*
* @param eTargetCpuType The target CPU which acknowledges the ePeriphType when entering stop mode.
* @param ePeriphType the peripheral to enable or disable the stop mode ACK
* @param bEnable true: enable the stop mode ACK
* false: disable the stop mode ACK
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_NO_PERM: Current CPU has no permission to access the register
*/
CSC_RetStatusType CSC_SetStopModeAckGrp2(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg2_PeriphType ePeriphType, bool bEnable);
/**
* @brief Set the stop request of peripheral group 2 in CSC.
*
* @param eTargetCpuType The target CPU which acknowledges the ePeriphType when entering stop mode.
* @param ePeriphType the peripheral to set stop request
* @param bEnable true: set the stop request
* false: clear the stop request
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_NO_PERM: Current CPU has no permission to access the register
*/
CSC_RetStatusType CSC_SetStopRequestGrp2(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg2_PeriphType ePeriphType, bool bEnable);
/**
* @brief Set the stop mode ACK of all group peripherals in CSC.
*
* @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode.
* @param ePeriphGrp the group of peripherals to set the stop mode ACK value
* @param u32Value the CSCx_STOP_MODERx register value
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_PARAM: ePeriphGrp or u32Value invalid
* CSC_E_NO_PERM: Current CPU has no permission to access the register
*/
CSC_RetStatusType CSC_SetStopModeAck(CSC_WPB_CpuType eTargetCpuType, CSC_PeriphGrpType ePeriphGrp, uint32_t u32Value);
/**
* @brief Set the stop request of all group peripherals in CSC.
*
* @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode.
* @param ePeriphGrp the group of peripherals to set the stop request value
* @param u32Value the CSCx_STOP_REQRx register value
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_PARAM: ePeriphGrp or u32Value invalid
* CSC_E_NO_PERM: Current CPU has no permission to access the register
*/
CSC_RetStatusType CSC_SetStopRequest(CSC_WPB_CpuType eTargetCpuType, CSC_PeriphGrpType ePeriphGrp, uint32_t u32Value);
/**
* @brief Get the stop Acknowledge status of peripherals group0 in CSC.
*
* @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode.
* @param ePeriphType the peripheral to get stop acknowledge status
* @param pStatus Output parameter,to save the stop ACK status of the peripheral indicated by ePeriphType
* true: Stop acknowledge is asserted (the module is in Stop mode)
* false: Stop acknowledge is not asserted
* @return CSC_RetStatusType Operation success/failed
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
*/
CSC_RetStatusType CSC_GetStopAckStatusGrp0(CSC_WPB_CpuType eTargetCpuType,CSCx_Reg0_PeriphType ePeriphType, bool * const pStatus);
/**
* @brief Get the stop Acknowledge status of peripherals group1 in CSC.
*
* @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode.
* @param ePeriphType the peripheral to get stop acknowledge status
* @param pStatus Output parameter,to save the stop ACK status of the peripheral indicated by ePeriphType
* true: Stop acknowledge is asserted (the module is in Stop mode)
* false: Stop acknowledge is not asserted
* @return CSC_RetStatusType Operation success/failed
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
*/
CSC_RetStatusType CSC_GetStopAckStatusGrp1(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg1_PeriphType ePeriphType, bool * const pStatus);
/**
* @brief Get the stop Acknowledge status of peripherals group2 in CSC.
*
* @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode.
* @param ePeriphType the peripheral to get stop acknowledge status
* @param pStatus Output parameter,to save the stop ACK status of the peripheral indicated by ePeriphType
* true: Stop acknowledge is asserted (the module is in Stop mode)
* false: Stop acknowledge is not asserted
* @return CSC_RetStatusType Operation success/failed
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
*/
CSC_RetStatusType CSC_GetStopAckStatusGrp2(CSC_WPB_CpuType eTargetCpuType,CSCx_Reg2_PeriphType ePeriphType, bool * const pStatus);
/**
* @brief Get the stop Acknowledge status of all group peripherals in CSC.
*
* @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode.
* @param ePeriphType the peripheral to get stop acknowledge status
* @param pU32Status Output parameter,to save the stop ACK status of all the peripherals in the group indicated by ePeriphGrp.
* The corresponding bit is 1, indicates that stop acknowledge is asserted,and 0 not asserted.
* @return CSC_RetStatusType Operation success/failed
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
*/
CSC_RetStatusType CSC_GetStopAckStatus(CSC_WPB_CpuType eTargetCpuType,CSC_PeriphGrpType ePeriphGrp, uint32_t * const pU32Status);
/**
* @brief Set the CPU write permission of CSCx_CCMx_CFG register in CSC.
*
* @param eTargetCpuType The target CPU controlled by CSCx_CCMx_CFG register.
* @param eCtrlCpuType The CPU that has the permission to access the CSCx_CCMx_CFG register.
* @param bLockStatus Lock the WPB of CSCx_CCMx_CFG register.Once locked, calling the API returns an error(CSC_E_LOCK).
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_LOCK: WPB is locked(WPB_LOCK set 1) and can not be written
*/
CSC_RetStatusType CSC_SetCCMCfgPermission(CSC_WPB_CpuType eTargetCpuType, CSC_WPB_CpuType eCtrlCpuType, bool bLockStatus);
/**
* @brief Set the CCM configuration of CPUx indicated by eTargetCpuType.
*
* @param eTargetCpuType The target CPU controlled by CSCx_CCMx_CFG register.
* @param pCCMCfg Pointer to the configuration of CSCx_CCMx_CFG register.
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_LOCK: Current CPU has no permission to access the register
*/
CSC_RetStatusType CSC_SetCCMConfiguration(CSC_WPB_CpuType eTargetCpuType,const CSC_CCMCfgType *const pCCMCfg);
/**
* @brief Get the CCM stop clock status.
*
* @param eTargetCpuType The target CPU controlled by CSCx_CCMx_CFG register.
* @param eCCMType CCM stop clock type.
* @param pStatus Pointer to memory to save the clock status.
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
*/
CSC_RetStatusType CSC_GetCCMStopClockStatus(CSC_WPB_CpuType eTargetCpuType, CSCx_CCM_StopClockType eCCMType, bool * const pStatus);
/**
* @brief Set the CPU write permission of CSCx_CPUx_INT register in CSC.
*
* @param eTargetCpuType The target CPU controlled by CSCx_CPUx_INT register.
* @param eCtrlCpuType The CPU that has the permission to access the CSCx_CPUx_INT register.
* @param bLockStatus Lock the WPB of CSCx_CPUx_INT register.Once locked, calling the API returns an error(CSC_E_LOCK).
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_LOCK: WPB is locked(WPB_LOCK set 1) and can not be written
*/
CSC_RetStatusType CSC_SetCpuIntPermission(CSC_WPB_CpuType eTargetCpuType, CSC_WPB_CpuType eCtrlCpuType, bool bLockStatus);
/**
* @brief Generate software interrupt via CSCx_CPUx_INT.
*
* @param eTargetCpuType The target CPU to generate interrupt.
* @param bEnable true: Generate software interrupt.
* false: Do not generate software interrupt.
*
* @return CSC_RetStatusType
* CSC_E_OK: The API is successfully called
* CSC_E_NOT_OK: eTargetCpuType invalid
* CSC_E_LOCK: The current CPU has no permission to access this bit
*/
CSC_RetStatusType CSC_CpuSwInterruptGen(CSC_WPB_CpuType eTargetCpuType, bool bEnable);
#endif /* End of _DRIVER_CSC_H_ */

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/**
* @file fc7xxx_driver_dma.h
* @author Flagchip0126
* @brief FC7xxx DMA driver type definition and API
* @version 0.1.0
* @date 2024-01-15
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC240
******************************************************************************** */
#ifndef _DRIVER_FC4XXX_DRIVER_DMA_H_
#define _DRIVER_FC4XXX_DRIVER_DMA_H_
#include "device_header.h"
#include "HwA_dma.h"
#include "HwA_dmamux.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_dma
* @{
*/
/**
* @brief DMA transfer complete callback function prototype
*
*/
typedef void (*DMA_TransferCompleteCallbackType)(void);
/**
* @brief DMA transfer error callback function prototype
*
*/
typedef void (*DMA_TransferErrorCallbackType)(void);
/**
* @brief Available DMA Instances
*
*/
typedef enum
{
DMA_INSTANCE_0 = 0U,
DMA_INSTANCE_MAX = DMA_INSTANCE_COUNT
} DMA_InstanceType;
/**
* @brief Available DMA channels
*
*/
typedef enum
{
DMA_CHANNEL_0 = 0U,
DMA_CHANNEL_1 = 1U,
DMA_CHANNEL_2 = 2U,
DMA_CHANNEL_3 = 3U,
DMA_CHANNEL_4 = 4U,
DMA_CHANNEL_5 = 5U,
DMA_CHANNEL_6 = 6U,
DMA_CHANNEL_7 = 7U,
DMA_CHANNEL_8 = 8U,
DMA_CHANNEL_9 = 9U,
DMA_CHANNEL_10 = 10U,
DMA_CHANNEL_11 = 11U,
DMA_CHANNEL_12 = 12U,
DMA_CHANNEL_13 = 13U,
DMA_CHANNEL_14 = 14U,
DMA_CHANNEL_15 = 15U,
DMA_CHANNEL_MAX = DMA_CFG_COUNT
} DMA_ChannelType;
/**
* @brief DMA operation return values
*
*/
typedef enum
{
DMA_STATUS_SUCCESS = 0x00U, /*!< The DMA operation is succeeded */
DMA_STATUS_ERROR = 0x01U, /*!< The DMA operation is failed */
DMA_STATUS_BUSY = 0x02U, /*!< The DMA operation is failed because DMA engine is busy */
DMA_STATUS_TIMEOUT = 0x03U, /*!< The DMA operation is failed because operation time out */
DMA_STATUS_UNSUPPORTED = 0x04U, /*!< The DMA configuration parameter is unsupported */
DMA_STATUS_INVALID_ADDRESS = 0x05U, /*!< The DMA source/destination address is invalid */
DMA_STATUS_NO_RESOURCE = 0x06U /*!< The DMA operation is failed because there is no resource */
} DMA_StatusType;
/**
* @brief DMA data increment size
*
* Specify the data increment size after DMA engine transferred a datum
*
*/
typedef enum
{
DMA_INCREMENT_DISABLE = 0x0U, /*!< The data address not increase */
DMA_INCREMENT_DATA_SIZE = 0x1U, /*!< The data address increase by the data size */
DMA_INCREMENT_DATA_SIZE_4BYTE_ALIGNED = 0x2U /*!< The data address increase by the data size,
and is 4 byte aligned */
} DMA_IncrementModeType;
/**
* @brief The size of the circular buffer
*
* @note The start address of the circular buffer should be aligned by the circular
* buffer size
*
*/
typedef enum
{
DMA_CIRCULAR_BUFFER_SIZE_1B = (int32)0x1U,
DMA_CIRCULAR_BUFFER_SIZE_2B = (int32)0x2U,
DMA_CIRCULAR_BUFFER_SIZE_4B = (int32)0x4U,
DMA_CIRCULAR_BUFFER_SIZE_8B = (int32)0x8U,
DMA_CIRCULAR_BUFFER_SIZE_16B = (int32)0x10U,
DMA_CIRCULAR_BUFFER_SIZE_32B = (int32)0x20U,
DMA_CIRCULAR_BUFFER_SIZE_64B = (int32)0x40U,
DMA_CIRCULAR_BUFFER_SIZE_128B = (int32)0x80U,
DMA_CIRCULAR_BUFFER_SIZE_256B = (int32)0x100U,
DMA_CIRCULAR_BUFFER_SIZE_512B = (int32)0x200U,
DMA_CIRCULAR_BUFFER_SIZE_1KB = (int32)0x400U,
DMA_CIRCULAR_BUFFER_SIZE_2KB = (int32)0x800U,
DMA_CIRCULAR_BUFFER_SIZE_4KB = (int32)0x1000U,
DMA_CIRCULAR_BUFFER_SIZE_8KB = (int32)0x2000U,
DMA_CIRCULAR_BUFFER_SIZE_16KB = (int32)0x4000U,
DMA_CIRCULAR_BUFFER_SIZE_32KB = (int32)0x8000U,
DMA_CIRCULAR_BUFFER_SIZE_64KB = (int32)0x10000U,
DMA_CIRCULAR_BUFFER_SIZE_128KB = (int32)0x20000U,
DMA_CIRCULAR_BUFFER_SIZE_256KB = (int32)0x40000U,
DMA_CIRCULAR_BUFFER_SIZE_512KB = (int32)0x80000U,
DMA_CIRCULAR_BUFFER_SIZE_1MB = (int32)0x100000U,
DMA_CIRCULAR_BUFFER_SIZE_2MB = (int32)0x200000U,
DMA_CIRCULAR_BUFFER_SIZE_4MB = (int32)0x400000U,
DMA_CIRCULAR_BUFFER_SIZE_8MB = (int32)0x800000U,
DMA_CIRCULAR_BUFFER_SIZE_16MB = (int32)0x1000000U,
DMA_CIRCULAR_BUFFER_SIZE_32MB = (int32)0x2000000U,
DMA_CIRCULAR_BUFFER_SIZE_64MB = (int32)0x4000000U,
DMA_CIRCULAR_BUFFER_SIZE_128MB = (int32)0x8000000U,
DMA_CIRCULAR_BUFFER_SIZE_256MB = (int32)0x10000000U,
DMA_CIRCULAR_BUFFER_SIZE_512MB = (int32)0x20000000U,
DMA_CIRCULAR_BUFFER_SIZE_1GB = (int32)0x40000000U,
DMA_CIRCULAR_BUFFER_SIZE_2GB = (int32)0x80000000U,
} DMA_CircularBufferSizeType;
/**
* @brief The eBufferRole of the circular buffer
*
*/
typedef enum
{
DMA_CIRCULAR_BUFFEER_ROLE_SOURCE = 0x0U, /*!< The circular buffer is used as the data source */
DMA_CIRCULAR_BUFFEER_ROLE_DESTINATION = 0x1U /*!< The circular buffer is used as the data destination */
} DMA_CircularBufferRoleType;
/**
* @brief The configuration parameters of the DMA engine
*
*/
typedef struct
{
DMA_ArbitrationAlgorithmType eArbitrationAlgorithm; /*!< Channel Arbitration Algorithm */
bool bHaltOnError; /*!< Whether DMA halts when error occured */
} DMA_InitType;
/**
* @brief The interrupt configurations of the DMA channel
*
*/
typedef struct
{
bool bTransferCompleteIntEn; /*!< Enable interrupt after transfer complete */
DMA_TransferCompleteCallbackType pTransferCompleteNotify; /*!< transfer complete notification */
bool bTransferErrorIntEn; /*!< Enable interrupt when transfer error occured */
DMA_TransferErrorCallbackType pTransferErrorNotify; /*!< transfer error notification */
} DMA_InterruptCfgType;
/**
* @brief The configutation parameters of the DMA channel
*
* @note The u8ChannelPriority must be unique for different channels, the default is the channel number.
* The u16BlockCount must be greater than 0.
* @note When Circular buffer is enabled, the data address should be power of 2 aligned to the buffer size.
* For example, if the circular buffer size is 32 byte, the data address should be 32 byte aligned. If the
* circular buffer size is 40 byte, then the data address should be 64 byte aligned.
*
*/
typedef struct
{
const volatile void *pSrcBuffer; /*!< the source address of the data */
volatile void *pDestBuffer; /*!< the destination address of the data */
uint32_t u32BlockSize; /*!< the data size of one block in byte */
uint16_t u16BlockCount; /*!< the number of data blocks in one transfer */
uint8_t u8ChannelPriority; /*!< channel priority, greater number means higher priority */
DMA_TransferSizeType eSrcDataSize; /*!< source data size */
DMA_TransferSizeType eDestDataSize; /*!< destination data size */
DMA_IncrementModeType eSrcIncMode; /*!< source data address increment mode */
DMA_IncrementModeType eDestIncMode; /*!< destination data address increment mode */
bool bSrcBlockOffsetEn; /*!< whether to add a block offset to the source address after
a block transfer */
bool bDestBlockOffsetEn; /*!< whether to add a block offset to the destination address after
a block transfer */
int32_t s32BlockOffset; /*!< the signed address offset applied to the src/dest address
after a block transfer */
bool bSrcAddrLoopbackEn; /*!< whether the source address return to the set value after transfer */
bool bDestAddrLoopbackEn; /*!< whether the destination address return to the set value after transfer */
bool bAutoStop; /*!< whether the DMA channel transfer automatically stops after one
transfer finishes when the channel is triggered by hardware */
bool bSrcCircularBufferEn; /*!< the source buffer of the DMA channel is a circular buffer */
uint32_t u32SrcCircBufferSize; /*!< the source circular buffer size in byte, the buffer size is suggested
to be power of 2 aligned */
bool bDestCircularBufferEn; /*!< the destination buffer of the DMA channel is a circular buffer */
uint32_t u32DestCircBufferSize; /*!< the destination circular buffer size in byte, the buffer size is suggested
to be power of 2 aligned */
bool bInnerChannelChain;
DMA_RequestSourceType eTriggerSrc; /*!< Select the DMA channel trigger source, if the trigger source is
DMA_REQ_DISABLED, the channel is triggered by software */
} DMA_ChannelCfgType;
/**
* @brief The parameters to configure the DMA channel as a circular buffer engine
*
*/
typedef struct
{
bool bCircularBufferEn; /*!< enable the DMA channel as a circular buffer engine */
DMA_CircularBufferRoleType eBufferRole; /*!< the source or the destination address is a circular buffer */
DMA_CircularBufferSizeType eBufferSize; /*!< the circular buffer size */
} DMA_CircularBufferType;
/**
* @brief The paarameters to configure the DMA chainned transfer
*
*/
typedef struct
{
bool bChanelChainEn; /*!< Whether to start the chained channel when the current completed */
uint8_t u8ChainedChannel; /*!< The chained channel */
} DMA_ChainTransferType;
/**
* @brief Initialize the DMA instance
*
* @param pInitCfg the configuration of the DMA instance
*/
void DMA_Init(const DMA_InstanceType eDma_Instance, const DMA_InitType *const pInitCfg);
/**
* @brief De-initialize the DMA instance
*
* Disable the DMA and restore its configure values to default
*
*/
void DMA_DeInit(const DMA_InstanceType eDma_Instance);
/**
* @brief Initialize the DMA channel
*
* @param u8Channel the DMA channel to initialize
* @param pChnCfg the configuration of the channel
* @return DMA_StatusType whether the channel is initiallized successfully
*/
DMA_StatusType DMA_InitChannel(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel, const DMA_ChannelCfgType *const pChnCfg);
/**
* @brief De-initialize the DMA channel
*
* @param u8Channel the DMA channel to de-initialize
*/
void DMA_DeinitChannel(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel);
/**
* @brief Initialize the DMA channel interrupt
*
* @param u8Channel the DMA channel to use
* @param pInterruptCfg the interrupt configuration of the DMA channel
*/
void DMA_InitChannelInterrupt(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel, const DMA_InterruptCfgType *const pInterruptCfg);
/**
* @brief Config the DMA channel chained transfer
*
* @param u8Channel the DMA channel to use
* @param pChainTransferCfg the parameters of the chained channel
*/
void DMA_ConfigChainedTransfer(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel,
const DMA_ChainTransferType *const pChainTransferCfg);
/**
* @brief Modify the source and destination address of the DMA channel
*
* @note This function should be called when the DMA channel is not actively transferring
*
* @param u8Channel the channel to modify
* @param pSrcBuffer the new source address of data, set NULL to remain unmodified
* @param pDestBuffer the new destination address of data, set NULL to remain unmodified
* @return DMA_StatusType whether the address is successfully modified
*/
DMA_StatusType DMA_ModifyAddress(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel,
const volatile void *pSrcBuffer, const volatile void *pDestBuffer);
/**
* @brief Start the DMA channel transfer
*
* If the trigger source for the DMA channel is DMA_REQ_DISABLED, the channel will start
* immediately after called this function. Otherwise, the channel will start when the
* trigger source is generated on the channel.
*
* @param u8Channel the DMA channel to start
*/
void DMA_StartChannel(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel);
/**
* @brief Stop the DMA channel transfer
*
* If the trigger source for the DMA channel is DMA_REQ_DISABLED, the channel will stop
* automatically after the transfer completed. Otherwise, you should call this function
* manually if you do not want the DMA to be triggered when hardware request is generated.
*
* @note If there is ongoing transfer on the channel, the channel will be stopped after the
* transfer completed.
*
* @param u8Channel the DMA channel to stop
*/
void DMA_StopChannel(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel);
/**
* @brief Cancel the ongoing DMA transfer
*
* @param bGenerateErr whether an error will be generated on the transferring channel
* @return DMA_StatusType whether the transfer is stopped successfully
*/
DMA_StatusType DMA_CancelTransfer(const DMA_InstanceType eDma_Instance, bool bGenerateErr);
/**
* @brief Get the request source of the selected channel
*
* @param u8Channel the DMA channel to get the request source
* @return DMA_RequestSourceType the request source of the selected channel
*/
DMA_RequestSourceType DMA_GetChannelRequestSrc(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel);
/**
* @brief Get the status of the DMA engine
*
* @return DMA_RunningStatusType the status of the DMA engine
*/
DMA_RunningStatusType DMA_GetStatus(const DMA_InstanceType eDma_Instance);
/**
* @brief Get the status of the DMA channel
*
* @param u8Channel the DMA channel to get the status
* @return DMA_RunningStatusType the status of the DMA channel
*/
DMA_RunningStatusType DMA_GetChannelStatus(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel);
/** @}*/ /* fc7xxx_driver_dma */
#if defined(__cplusplus)
}
#endif
#endif

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/**
* @file fc7xxx_driver_dsp.h
* @author Flagchip051
* @brief FC4xxx DSP driver type definition and API
* @version 0.1.0
* @date 2024-01-11
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details @verbatim
If only want use FPU,
1) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard) -> FPU Type set to "fpv5-sp-d16"
2) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> GNU Arm Cross C Compiler -> Preprocessor -> Defined symbols(-D) -> Add "__FPU_PRESENT=1" (without ")
3) and call FPU_Enable to enable FPU at the beginning of program.
If want to use DSP,
1) configure FCIDE to enable FPU compiler support, Properties -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard)
2) add MACRO "DRIVER_CM7_DSP_ENABLE" in FCIDE Properties -> C/C++ General -> Paths and Symbols -> Symbols -> GNU C and GNU C++ and Assembly
3) add Include Path to project Properties -> C/C++ General -> Paths and Symbols -> Includes -> GNU C and GNU C++ and Assembly:
../../../../../Template/Device/CMSIS5_590/DSP/Include
../../../../../Template/Device/CMSIS5_590/Core/Include
../../../../../Template/Device/CMSIS5_590/DSP/PrivateInclude
4) and call FPU_Enable to enable FPU at the beginning of program.
@endverbatim
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC4XXX_DRIVER_DSP_H_
#define _DRIVER_FC4XXX_DRIVER_DSP_H_
#include "device_header.h"
#if defined(__cplusplus)
extern "C" {
#endif
#if defined(__cplusplus)
}
#endif
#endif /* _DRIVER_FC4XXX_DRIVER_DSP_H_ */

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/**
* @file fc7xxx_driver_eim.h
* @author Flagchip
* @brief FC7xxx EIM driver type definition and API
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- -------------------
* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_EIM_H_
#define _DRIVER_FC7XXX_DRIVER_EIM_H_
#include "HwA_eim.h"
#include "device_header.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc4xxx_driver_eim
* @{
*/
/**
* @brief Initialize EIM function
*
* @param pEimInitCfg Initialization structure of EIM
* @return return 0: initialize successful. 1: invalid parameter
*/
EIM_RetType EIM_Init(const EIM_InitType *pEimInitCfg);
/**
* @brief Initialize EIM function
*
* @param eEimChannel channel want to set
* @param eDwpType Cpu to use
* @param bLockStatus Lock the cpu control settings
* @return Set operation success/failed
*/
EIM_RetType EIM_SetDwpMode(const EIM_ChannelType eEimChannel, const EIM_DWPType eDwpType, bool bLockStatus);
/**
* @brief Deinin EIM function
*
*/
void Eim_Deinit(void);
/**
* @brief Enable CPU lockstep monitor
*
* @param eEimCpuType EIM_CPU0_LOCKSTEP or EIM_CPU1_LOCKSTEP
* @param eMonitorType EIM_MONITOR0 or EIM_MONITOR1
*/
void EIM_CpuLockStepMonitorSet_MonSet(const EIM_CPU_ChnType eEimCpuType,const EIM_MONType eMonitorType);
/**
* @brief Clear CPU lockstep monitor
*
* @param eEimCpuType EIM_CPU0_LOCKSTEP or EIM_CPU1_LOCKSTEP
* @param eMonitorType EIM_MONITOR0 or EIM_MONITOR1
*/
void EIM_CpuLockStepMonitorSet_MonClr(const EIM_CPU_ChnType eEimCpuType,const EIM_MONType eMonitorType);
/**
* @brief Clean CPU lockstep monitor bit
*
* @param eEimCpuType EIM_CPU0_LOCKSTEP or EIM_CPU1_LOCKSTEP
* @param eMonitorType EIM_MONITOR0 or EIM_MONITOR1
*/
void EIM_CpuLockStepMonitorClr(const EIM_CPU_ChnType eEimCpuType, const EIM_MONType eMonitorType);
/** @} */ /* fc7xxx_driver_eim */
#if defined(__cplusplus)
}
#endif
#endif /* _DRIVER_FC4XXX_DRIVER_EIM_H_ */

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/**
* @file fc7xxx_driver_erm.h
* @author Flagchip
* @brief FC7xxx ERM driver type definition and API
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_ERM_H_
#define _DRIVER_FC7XXX_DRIVER_ERM_H_
#include "HwA_erm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* @addtogroup fc7xxx_driver_erm
* @{
*/
typedef enum
{
ERM_STATUS_SUCCESS = 0U, /**< ERM status success */
ERM_STATUS_PARAM_INVALID = 1U /**< ERM status parameter invalid */
} ERM_RetType;
/** @brief Erm interrupt notification type */
typedef void (*ERM_InterruptCallBackType)(void);
/**
* @brief Structure to configure ERM Init type
*
*/
typedef struct
{
ERM_ChannelType eChannel; /*!< ERM enable memory No, No 0-31 */
ERM_InterruptType eInt; /*!< ERM Interrupt type */
uint8 u8ErmEnable; /*!< ERM enable Interrupt */
ERM_InterruptCallBackType pIsrNotify; /**< Erm interrupt notification function pointer */
} ERM_MemorytInitType;
/**
* @brief Initialize ERM function
*
* @param pErmInt_cfg Initialization structure of ERM
* @return return 0: initialize successful. 1: invalid parameter
*/
ERM_RetType Erm_Init(const ERM_MemorytInitType *pErmInt_cfg);
/**
* @brief De-initialize ERM function
* Restore the ERM instance to its reset state
*/
void Erm_DeInit(void);
/**
* @brief ERM Read EARn address.
* @param eChannel The channel type
* @return u32Address The error address
*/
//uint32_t ERM_ReadAddress(ERM_channelType eChannel);
/**
* @brief ERM Clear SRn register.
*
* This function Clear ERM SR0 register.
*/
void ERM_ClearSRnRegister(void);
/**
* @brief ERM read SRn register.
*
* This function Clear ERM SR0 register.
* @param u8Index the SRn channel
*/
uint32_t ERM_ReadSRnVal(uint8_t u8Index);
/**
* @brief ERM clear CRn register.
*
* This function Clear ERM CRn register.
* @param u8Index of the CRn channel
*/
void ERM_ClearCRnVal(uint8_t u8Index);
/**
* @brief ERM clear SRn register.
*
* This function Clear ERM SR0 register.
* @param u8Index the SRn channel
*/
uint32_t ERM_ClearSRnVal(uint8_t u8Index);
/** @} */ /* fc7xxx_driver_erm */
#if defined(__cplusplus)
}
#endif
#endif /* _DRIVER_FC4XXX_DRIVER_ERM_H_ */

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/**
* @file fc7xxx_driver_fciic.h
* @author Flagchip
* @brief FC7xxx FCIIC driver type definition and API
* @version 0.2.0
* @date 2022-12-05
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022/12/31 qxw0052 N/A First version for FC7300
* 0.2.0 2023/02/14 qxw0052 N/A Fix MISRA issues
*********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_FCIIC_H_
#define _DRIVER_FC7XXX_DRIVER_FCIIC_H_
#include "HwA_fciic.h"
/**
* @addtogroup fc7xxx_driver_iic
* @{
*/
/**
* \brief IIC initial data define
*
*/
typedef struct
{
uint32_t u32ClkSrcHz; /**< module clock hz */
uint8_t bMasterMode; /**< bMasterMode=1 master mode */
uint8_t u8SlaveAddr; /**< if bMasterMode=0, this is used, and address format is 7bits , not ended with R/W bit */
uint8_t bTxFifoWMrk; /**< Tx FIFO Water Mark, FIFO always on, transmit FIFO is equal or less than TXWATER, set TDF */
uint8_t bRxFifoWMrk; /**< Tx FIFO Water Mark, FIFO always on, receive FIFO is greater than RXWATER, set RDF */
uint8_t bEnDma; /**< Enable DMA) */
uint32_t u32Frequency; /**< normal frequency, only used in master mode */
} FCIIC_InitType;
/**
* \brief IIC transmit data define
*
*/
typedef struct
{
FCIIC_TX_CMDType eCmd; /**< command type */
uint8_t u8Data; /**< 8bit data */
} FCIIC_TxDataType;
/**
* \brief IIC receive data define
*
*/
typedef struct
{
uint8_t u8Data; /**< 8bit data */
} FCIIC_RxDataType;
/** Error call back function type */
typedef void (*FCIIC_ErrorInterrupt_CallBackType)(uint8_t u8IicIndex, uint8_t bMaster, uint32_t u32Error);
/** Receive call back function type */
typedef void (*FCIIC_RxInterrupt_CallBackType)(uint8_t u8IicIndex, FCIIC_RxDataType *pRxCfg);
/**
* \brief IIC interrupt callback setting
*
*/
typedef struct
{
uint8_t bEnErrorInterrupt; /**< enable error interrupt */
FCIIC_ErrorInterrupt_CallBackType pErrorNotify; /**< error interrupt callback function address */
uint8_t bEnRxInterrupt; /**< enable receive interrupt */
FCIIC_RxInterrupt_CallBackType pRxNotify; /**< receive interrupt callback function address */
} FCIIC_InterruptType;
/**
* \brief This Function is used to initial IIC instance
*
* \param u8IicIndex Iic Index, 0,1
* \param pInitCfg is the structure address of IIC initial configuration parameters, and it contains IIC instance
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Init(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg);
/**
* \brief This Function is used to de-initial IIC instance
*
* \param u8IicIndex Iic Index, 0,1
* \param pInitCfg is the structure address of IIC initial configuration parameters, bMaster should be set
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_DeInit(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg);
/**
* \brief This Function is used to configure IIC master interrupt
*
* \param u8IicIndex Iic Index, 0,1
* \param pIntCfg contains IIC instance and interrupt callback functions
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Master_SetInterrupt(uint8_t u8IicIndex, FCIIC_InterruptType *pIntCfg);
/**
* \brief This Function is used to transmit data in master mode
*
* \param u8IicIndex Iic Index, 0,1
* \param pTxData contains IIC instance and buffer address
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Master_Transmit(uint8_t u8IicIndex, FCIIC_TxDataType *pTxData);
/**
* \brief This Function is used to get master status
*
* \param u8IicIndex Iic Index, 0,1
* \param eStatus is status type enumeration
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Master_GetStatus(uint8_t u8IicIndex, FCIIC_MasterStatusType eStatus);
/**
* \brief This Function is used to receive data when polling (not used when rx interrupt enabled) in master mode
*
* \param u8IicIndex Iic Index, 0,1
* \param pRxData contains IIC instance
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Master_Receive(uint8_t u8IicIndex, FCIIC_RxDataType *pRxData);
/**
* \brief This Function is used to get master error value
*
* \param u8IicIndex Iic Index, 0,1
* \return error value
*/
uint32_t FCIIC_Master_GetError(uint8_t u8IicIndex);
/**
* \brief This Function is used to clear master error value
*
* \param u8IicIndex Iic Index, 0,1
*/
void FCIIC_Master_ClrError(uint8_t u8IicIndex);
/**
* \brief This Function is used to configure IIC slave interrupt
*
* \param u8IicIndex Iic Index, 0,1
* \param pIntCfg contains IIC instance and interrupt callback functions
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Slave_SetInterrupt(uint8_t u8IicIndex, FCIIC_InterruptType *pIntCfg);
/**
* \brief This Function is used to transmit data in slave mode
*
* \param u8IicIndex Iic Index, 0,1
* \param pTxData contains IIC instance and buffer address
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Slave_Transmit(uint8_t u8IicIndex, FCIIC_TxDataType *pTxData);
/**
* \brief This Function is used to receive data when polling (not used when rx interrupt enabled) in slave mode
*
* \param u8IicIndex Iic Index, 0,1
* \param pRxData contains IIC instance and buffer address
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Slave_Receive(uint8_t u8IicIndex, FCIIC_RxDataType *pRxData);
/**
* \brief This Function is used to get slave error value
*
* \param u8IicIndex Iic Index, 0,1
* \return error value
*/
uint32_t FCIIC_Slave_GetError(uint8_t u8IicIndex);
/**
* \brief This Function is used to clear slave error value
*
* \param u8IicIndex Iic Index, 0,1
*/
void FCIIC_Slave_ClrError(uint8_t u8IicIndex);
#ifdef FCIIC_MASTER_STOP
uint8_t FCIIC_Master_Stop(uint8_t u8IicIndex);
#endif
/** @}*/
#endif

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/**
* @file fc7xxx_driver_fcpit.h
* @author Flagchip
* @brief FC7xxx FCPIT driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_FCPIT_H_
#define _DRIVER_FC7XXX_DRIVER_FCPIT_H_
#include "HwA_fcpit.h"
/**
* @addtogroup fc7xxx_driver_fcpit
* @{
*/
/** @brief Fcpit return type. */
typedef enum
{
FCPIT_STATUS_SUCCESS = 0U,
FCPIT_STATUS_PARAM_INVALID = 1U,
FCPIT_STATUS_FUNCTION_ERROR = 2U
} FCPIT_StatusType;
/** @brief Fcpit trigger source */
typedef enum
{
FCPIT_TRIGGER_INTERNAL_0 = 0,
FCPIT_TRIGGER_INTERNAL_1,
FCPIT_TRIGGER_INTERNAL_2,
FCPIT_TRIGGER_INTERNAL_3,
FCPIT_TRIGGER_EXTERNAL
} FCPIT_TriggerSelectType;
/** @brief callback function type */
typedef void (*FCPIT_InterruptCallBackType)(void);
typedef struct
{
FCPIT_ChannelType eFcpitChannel; /**< Fcpit channel number */
FCPIT_TriggerSelectType eTriggerSel; /**< trigger source */
bool bStartOnTrigger; /**< Fcpit timer start when triggered */
bool bStopOnInterrupt; /**< Fcpit timer stop on interrupt */
bool bReloadOnTrigger; /**< Fcpit timer reload when triggered */
} FCPIT_TrggerType;
/** @brief Fcpit interrupt structure */
typedef struct
{
FCPIT_ChannelType eFcpitChannel; /**< Fcpit channel number */
bool bChannelIsrEn; /**< whether to use interrupt */
FCPIT_InterruptCallBackType pIsrNotify; /**< interrupt notification function */
} FCPIT_IntType;
/** @brief Fcpit initialization type */
typedef struct
{
FCPIT_ChannelType eFcpitChannel; /**< Fcpit channel number */
FCPIT_TimerModeType eMode; /**< Fcpit counter mode */
bool bChainModeEn; /**< whether to use chain mode, if use this mode, channel must not be the channel 0 */
uint32_t u32TimerValue; /**< timer compare value, the range of value is related to the counter mode */
bool bDebugEn; /**< whether to use debug mode ,if enable this mode, the counter will stop when debugging. */
bool bLowPowerModeEn; /**< Configure the timer channels to continue running or stop when the device enters the LPM mode */
} FCPIT_InitType;
/** @brief FCPIT instance number */
typedef enum
{
FCPIT_0 = 0U,
} FCPIT_InstanceType;
/* global functions */
/**
* @brief Initialize Fcpit instance.
* @param eFcpit instance
* @param pInitStruct Fcpit initialization structure
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_Init(const FCPIT_InstanceType eFcpit, const FCPIT_InitType *const pInitStruct);
/**
* @brief Initialize Fcpit trigger configuration
* @param eFcpit instance
* @param pTrgStruct Fcpit trigger structure
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_InitTrigger(const FCPIT_InstanceType eFcpit, const FCPIT_TrggerType *const pTrgStruct);
/**
* @brief De-initialize Fcpit instance.
* @param eFcpit instance
*/
FCPIT_StatusType FCPIT_Deinit(const FCPIT_InstanceType eFcpit);
/**
* @brief Initialize Fcpit interrupt functionality
* @param eFcpit instance
* @param pTrgStruct Fcpit interrupt structure
* @return Fcpit return type
* @note this function will stop timer
*/
FCPIT_StatusType FCPIT_InitInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_IntType *const pIntStruct);
/**
* @brief Enable Fcpit interrupt
* @param eFcpit instance
* @param pIntStruct Fcpit interrupt structure
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_EnableInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel);
/**
* @brief Disable Fcpit interrupt
* @param eFcpit instance
* @param eChannel Fcpit channel
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_DisableInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel);
/**
* @brief Fcpit start timer
* @param eFcpit instance
* @param eChannel Fcpit channel
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_Start(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel);
/**
* @brief Fcpit stop
* @param eFcpit instance
* @param eChannel Fcpit channel
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_Stop(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel);
/**
* @brief Update Fcpit channel value
* @param eFcpit instance
* @param eChannel Fcpit channel
* @param u32ChannelValue in/Out value
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_UpdateChannelValue(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel, const uint32_t u32ChannelValue);
/**
* @brief read Fcpit channel time stamps.
* @param eFcpit instance
* @param eChannel Fcpit channel
* @param *u32timeStampValue channel value
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_ReadTimstamp(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel,uint32_t *u32timeStampValue);
/**
* @brief Immediately update Fcpit channel value
* @param eFcpit instance
* @param eChannel Fcpit channel
* @param u32ChannelValue in/Out value
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_ImmediateUpdateChannelValue(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel, const uint32_t u32ChannelValue);
/** @}*/ /* fc7xxx_driver_fcpit */
#endif

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/**
* @file fc7xxx_driver_fcsmu.h
* @author Flagchip
* @brief FC7xxx FCSMU driver type definition and API
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_FCSMU_H_
#define _DRIVER_FC7XXX_DRIVER_FCSMU_H_
#include "device_header.h"
#include "HwA_fcsmu.h"
/**
* @addtogroup fc7xxx_driver_fcsmu
* @{
. */
typedef enum
{
FCSMU_INSTANCE_0 = 0U, /*!< FCSMU instance 0 is selected. */
} FCSMU_InstanceType;
typedef enum
{
FCSMU_STATUS_SUCCESS = 0U, /*!< FCSMU operation is succeed. */
FCSMU_STATUS_ERROR = 1U /*!< FCSMU operation is failed. */
} FCSMU_StatusType;
typedef enum
{
FCSMU_STATE_NORMAL = 0U, /*!< FCSMU state normal */
FCSMU_STATE_CONGIG = 1U, /*!< FCSMU state config */
FCSMU_STATE_WARN = 2U, /*!< FCSMU state warn */
FCSMU_STATE_FAULT = 3U /*!< FCSMU state fault */
} FCSMU_StateType;
typedef enum
{
FCSMU_OP_STATE_IDLE = 0U, /*!< FCSMU operation status idle */
FCSMU_OP_STATE_BUSY = 1U, /*!< FCSMU operation status busy */
FCSMU_OP_STATE_FAILED = 2U, /*!< FCSMU operation status failed */
FCSMU_OP_STATE_SUCCESSFUL = 3U /*!< FCSMU operation status successful */
} FCSMU_OperationStatusType;
typedef enum
{
FCSMU_CRC_SW_MODE = 0U, /*!< FCSMU crc software mode. */
FCSMU_CRC_TRIGGER_MODE = 1U /*!< FCSMU crc trigger mode. */
} FCSMU_CrcModeType;
typedef enum
{
FCSMU_SOUT_CTRL_BY_FSM = 0U, /*!< SOUT is controlled by the FSM. */
FCSMU_SOUT_CTRL_KEEP_LOW = 1U, /*!< SOUT keeps low. */
FCSMU_SOUT_CTRL_BY_FSM2 = 2U, /*!< SOUT is controlled by the FSM. */
FCSMU_SOUT_CTRL_KEEP_HIGH_THEN_FSM = 3U /*!< SOUT keeps high until a fault occures on a channel, then controlled by FSM. */
} FCSMU_SoutControlType;
typedef enum
{
FCSMU_SOUT_DEFAUT_POLARITY = 0U, /*!< Default polarity. */
FCSMU_SOUT_SWITCH_POLARITY = 1U /*!< Switch polarity. */
} FCSMU_SoutPolarityType;
typedef enum
{
FCSMU_SOUT_PROTOCOL_DUAL_RAIL = 0U,
FCSMU_SOUT_PROTOCOL_TIME_SWITCH = 1U,
FCSMU_SOUT_PROTOCOL_BISTABLE = 2U,
FCSMU_SOUT_PROTOCOL_FAULT_TOGGLE = 3U,
FCSMU_SOUT_PROTOCOL_TIME_DUAL_RAIL = 4U,
FCSMU_SOUT_PROTOCOL_DIAG0 = 5U,
FCSMU_SOUT_PROTOCOL_DIAG1 = 6U,
FCSMU_SOUT_PROTOCOL_DIAG2 = 7U,
} FCSMU_SoutProtocolType;
typedef enum
{
FCSMU_WARNING_IRQ = 0U,
FCSMU_FAULT_IRQ = 1U,
FCSMU_CFG_TIMEOUT = 2U
} FCSMU_IQRType;
typedef enum
{
FCSMU_FAULT_CHANNEL_NONE = 0x0U,
FCSMU_FAULT_CHANNEL_TEMP_ERROR = 0x1U, /*!< Event from temperature sensor. */
FCSMU_FAULT_CHANNEL_PMC_ERROR = 0x2U, /*!< Voltage out of range indication from PMC. */
FCSMU_FAULT_CHANNEL_NVR_ERROR = 0x4U, /*!< NVR load error/System abnormal alarm signal. */
FCSMU_FAULT_CHANNEL_STCU_BIST_ERROR = 0x8U, /*!< STCU MBIST or LBIST fail. */
FCSMU_FAULT_CHANNEL_STCU_LS0_ERROR = 0x10U, /*!< Lockstep compare fault. */
FCSMU_FAULT_CHANNEL_SYSTEM_CPU0_ERROR = 0x40U, /*!< System RAM CPU0 access error. */
FCSMU_FAULT_CHANNEL_SYSTEM_NON_CPU_ERROR = 0x200U, /*!< System RAM None CPU access error. */
FCSMU_FAULT_CHANNEL_SCM_CPU0_ERROR = 0x400U, /*!< Matrix Access Monitor ECC check CPU0 error. */
FCSMU_FAULT_CHANNEL_SCM_NON_CPU_ERROR = 0x2000U, /*!< Matrix Access Monitor ECC check non CPU error. */
FCSMU_FAULT_CHANNEL_CPU0_ECC_ERROR = 0x4000U, /*!< Including ITCM/DTCM/ICACHE/DCACHE. */
FCSMU_FAULT_CHANNEL_CMU4_FAIL_ERROR = 0x80000U, /*!< CMU4 failure interrupt. */
FCSMU_FAULT_CHANNEL_CMU_FAIL_ERROR = 0x100000U, /*!< CMU1/2 failure interrupt. */
FCSMU_FAULT_CHANNEL_FLASH_ECC_ERROR = 0x200000U, /*!< Flash ECC error. */
FCSMU_FAULT_CHANNEL_SCG_PLL_FOSC_ERROR = 0x400000U, /*!< PLL/FOSC loss of clock. */
FCSMU_FAULT_CHANNEL_DMA0_ERROR = 0x800000U, /*!< DM0 AHB Error/LS Error/CFG RAM Error. */
FCSMU_FAULT_CHANNEL_INTM0_ERROR = 0x2000000U, /*!< Interrupt Monitor error. */
FCSMU_FAULT_CHANNEL_FMC_ERROR = 0x10000000U, /*!< FMC ECC error. */
FCSMU_FAULT_CHANNEL_SCG_SCM_CRC_ERROR = 0x20000000U, /*!< SCG and SCM etc. CRC check error. */
FCSMU_FAULT_CHANNEL_MAM_WDG_ERROR = 0x80000000U, /*!< MAM master access time out error. */
} FCSMU_ChannelAssignmentType;
/**
* @brief FCSMU Channel ISR callback function prototype
*
*/
typedef void (*FCSMU_ISRCallbackType)(FCSMU_IQRType eIrqType, uint32_t u32IrqChannel);
typedef struct
{
bool bEnable; /*!< Enable or disable status output. */
bool eFastMode; /*!< Enable or disable fast mode. */
bool bDivex; /*!< SOUT Divider Extend Control. */
FCSMU_SoutControlType eSoutCtrl; /*!< Configure Sout Control. */
FCSMU_SoutPolarityType ePolarity; /*!< Status output polarity. */
FCSMU_SoutProtocolType eProtocal; /*!< Status output protocal. */
uint32_t u32Delaytimer; /*!< Configure the safe mode request delay in cycles of CLKSAFE. */
uint32_t u32Divder; /*!< Configure the status output divider ratio.
bDevex = 0, SOUT_freq = CLKSAFE_freq/((SOUT_DIV+1)*2*256)
bDevex = 1, SOUT_freq = CLKSAFE_freq/((SOUT_DIV+1)*2*64)
*/
uint32_t u32SoutChannel; /*!< Configure the status output channel. */
} FCSMU_StatusOutputConfigType;
typedef struct
{
uint32_t u32WarnTo; /*!< FCSMU warning timeoout value. */
uint32_t u32WarnChannel; /*!< FCSMU warning channel. */
uint32_t u32FaultChannel; /*!< FCSMU fault channel. */
uint32_t u32WarnInterruptChannel; /*!< FCSMU warning interrupt channel. */
uint32_t u32FaultInterruptChannel; /*!< FCSMU fault interrupt channel. */
uint32_t u32FaultResetChannel; /*!< FCSMU fault reset channel. */
uint32_t u32SoftwareClearedChannel; /*!< FCSMU fault is Cleard by software. */
FCSMU_ISRCallbackType pISRCallback; /*!< ISR callback. */
} FCSMU_InitCfgType;
/**
* @brief Init the FCSMU.
*
* @param pInitConfig FCSMU initial configuration.
*/
FCSMU_StatusType FCSMU_init(const FCSMU_InitCfgType *pInitConfig);
/**
* @brief Config the FCSMU status output.
*
* @param pInitConfig FCSMU status output configuration.
*/
FCSMU_StatusType FCSMU_ConfigStatusOutput(FCSMU_StatusOutputConfigType *pInitConfig);
/**
* @brief Generate the CRC.
*
*/
void FCSMU_CrcGen(void);
/**
* @brief Query CRC busy status.
*
* @return FCSMU_CrcModeType CRC status.
*/
bool FCSMU_IsCrcBusy(void);
/**
* @brief Configure the FCSMU CRC.
*
* @param eMode Crc mode.
* @return FCSMU_StatusType Status of configuration.
*/
FCSMU_StatusType FCSMU_CrcConfig(FCSMU_CrcModeType eMode);
/**
* @brief Clear the falut flag.
*
* @param u32FaultChannel Channel flag to be cleared.
* @return FCSMU_StatusType Status of clear.
*/
FCSMU_StatusType FCSMU_ClearFaultFlag(uint32_t u32FaultChannel);
/**
* @brief Transform state from configuration to normal.
*
* @return FCSMU_StatusType Status of Transformation.
*/
FCSMU_StatusType FCSMU_TransStateCTN(void);
/**
* @brief Transform state from normal to configuration.
*
* @return FCSMU_StatusType Status of Transformation.
*/
FCSMU_StatusType FCSMU_TransStateNTC(void);
/**
* @brief Inject the fault tp fcsmu.
*
* @param u32ChannelIndex channel to be injected.
*/
void FCSMU_InjectionFault(uint32_t u32ChannelIndex);
/**
* @brief Get the fault channels fcsmu.
*
* @return Fault channels.
*/
uint32_t FCSMU_GetFaultChannel(void);
/**
* @brief Get the interrupt state of fcsmu.
*
* @return interrupt state.
*/
uint32_t FCSMU_GetIrqState(void);
/**
* @brief Get the NTF flags of fcsmu.
*
* @return NTF flags.
*/
uint32_t FCSMU_GetNtfFlag(void);
/**
* @brief Get the WTF flags of fcsmu.
*
* @return WTF flags.
*/
uint32_t FCSMU_GetWtfFlag(void);
/**
* @brief Get the NTW flags of fcsmu.
*
* @return NTW flags.
*/
uint32_t FCSMU_GetNtwFlag(void);
/** @}*/ /* fc7xxx_driver_fcsmu. */
#endif

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/**
* @file fc7xxx_driver_fcspi.h
* @author Flagchip
* @brief FC7xxx FCSPI driver type definition and API
* @version 0.1.0
* @date 2024-1-12
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024/01/12 Flagchip071 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_FCSPI_H_
#define _DRIVER_FC7XXX_DRIVER_FCSPI_H_
#include "device_header.h"
#include "HwA_fcspi.h"
#include "fc7xxx_driver_dma.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc4xxx_driver_fcspi
* @{
*/
/**
* @brief Status returned by FCSpi APIs
*
*/
typedef enum {
FCSPI_STATUS_SUCCESS = 0, /*!< API execute successfully */
FCSPI_STATUS_INSTANCE_ERROR, /*!< FCSpi instance index parameter error */
FCSPI_STATUS_PARAM_ERR, /*!< parameter error */
FCSPI_STATUS_ERROR, /*!< some error occur in API */
FCSPI_STATUS_NO_DATA, /*!< user want to transfer nothing */
FCSPI_STATUS_BUSY, /*!< FCSpi hardware is busy, not available */
FCSPI_STATUS_SYNC_TIMEOUT, /*!< FCSpi synchronous transfer timeout */
FCSPI_STATUS_TRANSFER_FAIL, /*!< FCSpi transfer fail */
FCSPI_STATUS_TRIGGER_OK, /*!< FCSpi user trigger successfully */
FCSPI_STATUS_TRIGGER_ABORT_TX_FAIL, /*!< FCSpi user trigger fail due to send underrun */
FCSPI_STATUS_TRIGGER_ABORT_RX_FAIL, /*!< FCSpi user trigger fail due to receive overflow */
FCSPI_STATUS_TRIGGER_FINISH /*!< FCSpi user trigger finish, all data already send */
} FCSPI_StatusType;
/**
* @name Type definition for FCSpi master/slave mode
*
*/
/**@{*/
/**
* @brief FCSpi hardware instances
*
* FCSpi consist of multiple hardware instances, for example, FCSPI0, FCSPI1...
* Just as the enumeration type "FCSPI_InstanceType" definition shows.
* We use variables of this type to indicate which hardware instance to use.
*/
typedef enum {
FCSPI_0 = 0,
FCSPI_1 = 1,
FCSPI_2 = 2,
FCSPI_3 = 3,
FCSPI_4 = 4,
FCSPI_5 = 5,
} FCSPI_InstanceType;
/**
* @brief PCS(Peripheral Chip Select) pin select
*
* FCSPI has four PCS lines, in our driver code,
* we use FCSPI_PCS_0/FCSPI_PCS_1/FCSPI_PCS_2/FCSPI_PCS_3 to present them.
* Like the above, we use enumeration type "FCSPI_PCSType" to indicate
* which PCS to connect to the external device,
* "PCS" is short for Peripheral Chip Select,
* which usually use low level voltage to select the external chip to communicate.
*/
typedef enum {
FCSPI_PCS_0 = 0U,
FCSPI_PCS_1 = 1U,
FCSPI_PCS_2 = 2U,
FCSPI_PCS_3 = 3U
} FCSPI_PCSType;
/**
* @brief Valid PCS pin voltage polarity
*
* The external device determines the voltage polarity (low or high) of PCS to enable it.
* So, FCSpi use enumeration type "FCSPI_PcsPolarityType" to indicate
* the polarity the PCS output when select the external device
*/
typedef enum {
FCSPI_PCS_POL_ACTIVE_HIGH = 1, /*!< pcs use high level to select external device */
FCSPI_PCS_POL_ACTIVE_LOW = 0 /*!< pcs use low level to select external device */
} FCSPI_PcsPolarityType;
/**
* @brief SCK(serial clock) active phase
*
* Just as the SPI bus specification says, clock polarity (CPOL) and clock phase (CPHA) determine the sample point.
* FCSpi use enumeration type "FCSPI_SckPolarityType" to present CPOL configuration.
*/
typedef enum {
FCSPI_SCK_ACTIVE_HIGH = 0, /*!< sck is high level when active (idles low). */
FCSPI_SCK_ACTIVE_LOW = 1 /*!< sck is low level when active (idles high). */
} FCSPI_SckPolarityType;
/**
* @brief SCK(serial clock) sample edge
*
* Just as the SPI bus specification says,
* clock polarity (CPOL) and clock phase (CPHA) determine the sample point.
* FCSpi use enumeration type "FCSPI_SckSamplePhaseType" to present CPHA configuration.
*/
typedef enum {
FCSPI_SCK_SAMPLE_FIRST_EDGE = 0, /*!< sample on first edge of sck active polarity, change on second */
FCSPI_SCK_SAMPLE_SECOND_EDGE = 1 /*!< changed on first edge of sck active polarity, sample on second */
} FCSPI_SckSamplePhaseType;
/**
* @brief The order of rx/tx handles bit
*
* When send or receive data, the MOSI and MISO handle only one bit at a time,
* FCSpi map the bit data order according to the specific configuration.
* FCSpi driver provides the enumeration type "FCSPI_BitFirstOrderType" to indicate the order.
*/
typedef enum {
FCSPI_MSB_FIRST = 0, /*!< most significant bit first handle, from msb to lsb */
FCSPI_LSB_FIRST = 1 /*!< least significant bit first handle, from lsb to msb */
} FCSPI_BitFirstOrderType;
/**
* @brief Transfer method between memory and FCSpi's registers
*
* FCSpi support transferring data by ISR, DMA, or user poll.
*
* If use ISR method, in interrupt handler function,
* the driver will write data to register "FCSPI_TX_DATA" to push it into Tx FIFO
* and read the register "FCSPI_RX_DATA" to pop data from Rx FIFO.
* When finish, the hardware will create an interrupt to notify the end.
*
* If use DMA, the DMA channel and priority should also be configured.
* After configuring these, driver user doesn't need to take care of the detail of transferring.
* Just send data or send & receive at same time. When finish, the hardware will create an interrupt to notify the end.
*
* If use User Poll mode, driver user should call
* "FCSPI_SyncTransfer" API to move the data until it return error or finished.
* In this mode, the interrupt in driver is disabled.
*/
typedef enum {
FCSPI_TRANSFER_TRIGGER_SRC_ISR = 0, /*!< software(interrupt function) move data between register and memory, when finish, notified by interrupt */
FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR, /*!< hardware(DMA) move data between register and memory, when finish, notified by interrupt */
FCSPI_TRANSFER_TRIGGER_SRC_USER_POLL /*!< NOT use ISR and DMA!!! driver user use API to move data between register and memory, notified by return value when finish */
} FCSPI_TriggerSrcType;
/**
* @brief transfer stop callback function's prototype
*
* FCSpi use this type to define one function pointer variable,
* which is called when the transfer is aborted or finished.
*/
typedef void (*FCSPI_StopCbType)(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInIsr);
/**
* @brief Type return by semaphore callback function
*
* If want to use synchronous tranfer API, driver user need to provide semaphore callback,
* these callback function should return value of this enumeration defined.
*/
typedef enum {
FCSPI_SEMAPHORE_SUCCESS = 0, /*!< semaphore function execute successfully */
FCSPI_SEMAPHORE_FAIL = 1, /*!< semaphore function execute fail */
FCSPI_SEMAPHORE_TIMEOUT = 2 /*!< wait to get semaphore until reaching deadline */
} FCSPI_SemaphoreStatType;
/**
* @brief Callback function to reset semaphore
*
* After calling this function, the semaphore variable has a zero semaphore count.
* Then if try to take the semaphore, the take API will blocks.
*
* If the RTOS is FreeRTOS, the reference code as following.
*
* @code
* FCSPI_SemaphoreStatType SpiSemaphoreReset(FCSPI_InstanceType eInst)
* {
* while ( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) == pdTRUE );
* return FCSPI_SEMAPHORE_SUCCESS;
* }
* @endcode
*/
typedef FCSPI_SemaphoreStatType (*FCSPI_SemaphoreResetCbType)(FCSPI_InstanceType eInst);
/**
* @brief Callback function to obtain semaphore
*
* This function will only try to obtain the semaphore before the time expires.
*
* If the RTOS is FreeRTOS, the reference code as following.
*
* @code
* FCSPI_SemaphoreStatType SpiSemaphoreTake(FCSPI_InstanceType eInst, uint32_t u32Timeout)
* {
* if ( xSemaphoreTake( xSemaphore, ( TickType_t ) u32Timeout ) == pdTRUE )
* return FCSPI_SEMAPHORE_SUCCESS;
* else
* return FCSPI_SEMAPHORE_TIMEOUT;
* }
* @endcode
*/
typedef FCSPI_SemaphoreStatType (*FCSPI_SemaphoreTakeCbType)(FCSPI_InstanceType eInst, uint32_t u32Timeout);
/**
* @brief Callback function to release semaphore
*
* This function will only release semaphore.
*
* If the RTOS is FreeRTOS, the reference code as following.
*
* @code
* static FCSPI_SemaphoreStatType SpiSemaphorePost(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInIsr)
* {
* FCSPI_SemaphoreStatType eRet = FCSPI_SEMAPHORE_SUCCESS;
*
* (void)eInst;
* if (FCSPI_TRUE == bIsInIsr)
* {
* BaseType_t tBase = pdFALSE;
*
* if ( xSemaphoreGiveFromISR( xSemaphore, &tBase ) == pdPASS )
* {
* portYIELD_FROM_ISR(tBase);
* eRet = FCSPI_SEMAPHORE_SUCCESS;
* }
* else
* {
* eRet = FCSPI_SEMAPHORE_FAIL;
* }
* }
* else
* {
* if ( xSemaphoreGive( xSemaphore ) == pdPASS )
* eRet = FCSPI_SEMAPHORE_SUCCESS;
* else
* eRet = FCSPI_SEMAPHORE_FAIL;
* }
*
* return eRet;
* }
* @endcode
*/
typedef FCSPI_SemaphoreStatType (*FCSPI_SemaphorePostCbType)(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInIsr);
/**
* @brief Asynchronous Transfer data buffer information
*
* @note @verbatim
if init frame bit count need N bytes to store, for example, 7bits need N=1 byte, 9bits need N=2bytes, 23bits need N=3bytes.
N = 1, one frame data stored in pSendBuffer using uint8_t, driver read data using step 1byte.
N = 2, one frame data stored in pSendBuffer using uint16_t, driver read data using step 2byte.
N = 3, one frame data stored in pSendBuffer using uint32_t, driver read data using step 4byte.The highest byte is dropped.
N > 3, byte count of frame data stored in the parameter pointer pSendBuffer aligned with 4bytes,
for example, one frame uses 5bytes, it will need two uint32_t, the highest 3bytes are dropped,
driver API user need declare as "uint32_t data[N]"; it use index 0 to 1, the next frame is 2 to 3.
@endverbatim
*/
typedef struct {
const uint8_t *pSendBuffer; /*!< The buffer containing data to be send, must keep valid before sending is terminated or finished, can be NULL */
uint8_t *pReceiveBuffer; /*!< Optional, can be NULL. Buffer to store the data received.The data received is 1byte aligned, no dummy data insert. */
uint16_t u16FrameCount; /*!< The frame count to be sent, the data stored in pSendBuffer is divided into many frames. */
} FCSPI_AsyncDataInfType;
/**
* @brief Synchronous Transfer data buffer information
*
* @note @verbatim
if init frame bit count need N bytes to store, for example, 7bits need N=1 byte, 9bits need N=2bytes, 23bits need N=3bytes.
N = 1, one frame data stored in pSendBuffer using uint8_t, driver read data using step 1byte.
N = 2, one frame data stored in pSendBuffer using uint16_t, driver read data using step 2byte.
N = 3, one frame data stored in pSendBuffer using uint32_t, driver read data using step 4byte.The highest byte is dropped.
N > 3, byte count of frame data stored in the parameter pointer pSendBuffer aligned with 4bytes,
for example, one frame uses 5bytes, it will need two uint32_t, the highest 3bytes are dropped,
driver API user need declare as "uint32_t data[N]"; it use index 0 to 1, the next frame is 2 to 3.
@endverbatim
*/
typedef struct {
const uint8_t *pSendBuffer; /*!< The buffer containing data to be send, must keep valid before sending is terminated or finished, can be NULL */
uint8_t *pReceiveBuffer; /*!< Optional, can be NULL. Buffer to store the data received.The data received is 1byte aligned, no dummy data insert. */
uint16_t u16FrameCount; /*!< The frame count to be sent, the data stored in pSendBuffer is divided into many frames. */
uint32_t u32Timeout; /*!< The timeout value, it will only be passed to the semaphore callback API configured by driver user */
} FCSPI_SyncDataInfType;
/**
* @brief tx/rx remain information
*
*
*/
typedef struct {
uint32_t u32ByteCountSendRemained; /*!< byte count remains to be sent */
uint32_t u32ByteCountReceiveRemained; /*!< byte count remains to be get */
} FCSPI_TransferRemainInfType;
/**
* @brief configuration when use DMA
*
*
*/
typedef struct {
DMA_InstanceType eDMAInstance; /*!< DMA Instance number, if DMA not used, this ignored */
uint8_t u8RxDMAChannel; /*!< DMA channel number for Rx, if DMA not used, this ignored */
uint8_t u8TxDMAChannel; /*!< DMA channel number for Tx, if DMA not used, this ignored */
uint8_t u8RxDMAChannelPriority; /*!< DMA channel priority for Rx, should differ from others in project scope */
uint8_t u8TxDMAChannelPriority; /*!< DMA channel priority for Tx, should differ from others in project scope */
} FCSPI_TriggerDmaInfType;
/**@}*/
/**
* @name Type definition for FCSpi master mode
*
*/
/**@{*/
/**
* @brief FCSpi Master mode configuration
*
* When One FCSpi instance used as master side, API "FCSPI_Master_Init" need this parameter to configure the driver.
*
*/
typedef struct {
uint32_t u32FCSpiSrcClk; /*!< fcspi hardware module source clock */
/* peripheral chip select configuration */
FCSPI_PCSType ePcs; /*!< chip select pin */
FCSPI_PcsPolarityType ePcsPolarity; /*!< chip select pin polarity */
FCSPI_AtomicBoolType eIsPcsContinuous; /*!< keep PCS select enable until transfer finish */
/* about sample point, sample bit order */
FCSPI_SckSamplePhaseType eSckSamplePhase; /*!< select which edge of active sck clock to capture data */
FCSPI_SckPolarityType eSckPolarity; /*!< select output sclk clock polarity */
FCSPI_BitFirstOrderType eBitFirstOrder; /*!< transmit LSB/MSB first */
uint32_t u32BitCntPerSecond; /*!< baud rate in bits per second, actual baudrate is calculated in driver, it's the nearest value to this parameter */
uint16_t u16BitCountPerFrame; /*!< bit count of one frame, should >= 8, we call the data after pcs select, before pcs become invalid, as a frame, */
FCSPI_TriggerSrcType eTransferTriggerSrc; /*!< type of transfer data between memory and data register of FCSPI */
/* if eTransferTriggerSrc is "FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR", these following fields should be set, or ingore */
FCSPI_TriggerDmaInfType tTriggerDmaInf; /*!< if trigger src is DMA, this MUST configure */
/* if to be notified when transmittion successfully or aborted, need set these following fields */
FCSPI_StopCbType pStopNotifyCb; /*!< transfer stop(transfer successfully or aborted) callback function, can be NULL */
/* if want to use semaphore to synchronous transfer, the following need to be set */
FCSPI_SemaphoreResetCbType pSemaResetCb; /*!< function to reset the semaphore to init state */
FCSPI_SemaphoreTakeCbType pSemaTakeCb; /*!< function pointer to get the semaphore */
FCSPI_SemaphorePostCbType pSemaPostCb; /*!< function pointer to release the semaphore */
} FCSPI_MasterCfgType;
/**
* @brief parameters about the holding time (in us) between PCS and SCK
*
* Configure the duration (in us) of the clock voltage between PCS and SCK
*/
typedef struct {
uint32_t u32PCStoPCSHoldUs; /*!< Configures the delay cycles from the PCS negation to the next PCS assertion, in microsecond(us) */
uint32_t u32SCKtoPCSHoldUs; /*!< Configure the delay cycles from the last SCK edge to the PCS negation, in microsecond(us) */
uint32_t u32PCStoSCKHoldUs; /*!< Configure the delay cycles from the PCS assertion to the first SCK edge, in microsecond(us) */
} FCSPI_MasterSckPcsHoldTimeType;
/**
* @brief parameters about the holding time (in PCS/100) between PCS and SCK
*
* Configure the duration (in PCS/100) of the clock voltage between PCS and SCK
*/
typedef struct {
uint32_t u32PCStoPCSHoldPercentage; /*!< Configure the delay cycles from the PCS negation to the next PCS assertion, in PCS/100 */
uint32_t u32SCKtoPCSHoldPercentage; /*!< Configure the delay cycles from the last SCK edge to the PCS negation, in PCS/100 */
uint32_t u32PCStoSCKHoldPercentage; /*!< Configure the delay cycles from the PCS assertion to the first SCK edge, in PCS/100 */
} FCSPI_MasterSckPcsHoldSckCycleType;
/**
* @brief parameters about the PCS and its Polarity
*
* Configure the specific PCS to be used and its active polarity when FCSPI running as master side
*/
typedef struct {
FCSPI_PCSType ePcs; /*!< Which PCS pin to configure */
FCSPI_PcsPolarityType ePolarity; /*!< Pin's active polarity */
} FCSPI_MasterPcsConfType;
/**@}*/
/**
* @name Type definition for FCSpi slave mode
*
*/
/**@{*/
/**
* @brief FCSpi Slave mode configuration
*
* When One FCSpi instance used as slave side, API "FCSPI_Slave_Init" need this parameter to configure the driver.
*/
typedef struct {
FCSPI_BitFirstOrderType eBitFirstOrder; /*!< transmit LSB/MSB first */
uint16_t u16BitCountPerFrame; /*!< bit count of one frame, should >= 8 */
FCSPI_PcsPolarityType ePcsPolarity; /*!< pcs polarity */
FCSPI_PCSType ePcs; /*!< chip select pin */
FCSPI_SckSamplePhaseType eSckSamplePhase; /*!< select which edge of active sck clock to capture data */
FCSPI_SckPolarityType eSckPolarity; /*!< selects clock polarity */
FCSPI_TriggerSrcType eTransferTriggerSrc; /*!< type of transfer data between memory and data register of FCSPI */
/* if eTransferTriggerSrc is "FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR", these following fields should be set, or ingore */
FCSPI_TriggerDmaInfType tTriggerDmaInf; /*!< if trigger src is DMA, this MUST configure */
/* if to be notified when transmittion stop(successfully, fail, aborted), need set these following fields */
FCSPI_StopCbType pStopNotifyCb; /*!< transfer stop(successfully or fail, or aborted) callback function, can be NULL */
/* if want to use semaphore to synchronous transfer, the following need to be set */
FCSPI_SemaphoreResetCbType pSemaResetCb; /*!< function to reset the semaphore to init state */
FCSPI_SemaphoreTakeCbType pSemaTakeCb; /*!< function pointer to get the semaphore */
FCSPI_SemaphorePostCbType pSemaPostCb; /*!< function pointer to release the semaphore */
} FCSPI_SlaveCfgType;
/**@}*/
/**
* @name API declaration for FCSpi master mode
*
*/
/**@{*/
/**
* @brief Init the FCSpi instance as spi master side
*
* @param eInst Which FCSpi Hardware instance
* @param pCfg Configuration of the FCSpi, MUST NOT NULL
* @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, some error occur.
*/
FCSPI_StatusType FCSPI_Master_Init(const FCSPI_InstanceType eInst, const FCSPI_MasterCfgType *pCfg);
/**
* @brief Configure the holding time (in us) between PCS and SCK
*
* @param eInst Which FCSpi Hardware instance
* @param pCfg Configure the delay parameters between PCS and SCK, MUST NOT null
* @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, the hardware is busy now.
*/
FCSPI_StatusType FCSPI_Master_SetSckPcsHoldTime(const FCSPI_InstanceType eInst, const FCSPI_MasterSckPcsHoldTimeType *pCfg);
/**
* @brief Configure the holding time (in SCK/100) between PCS and SCK
*
* @param eInst Which FCSpi Hardware instance
* @param pCfg Configure the delay parameters between PCS and SCK, MUST NOT null
* @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, the hardware is busy now.
*/
FCSPI_StatusType FCSPI_Master_SetSckPcsHoldSckPercentage(const FCSPI_InstanceType eInst, const FCSPI_MasterSckPcsHoldSckCycleType *pCfg);
/**
* @brief Select the PCS to use and configure
*
* @param eInst Which FCSpi Hardware instance
* @param pCfg Parameters about PCS configuration, MUST NOT null
* @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, the hardware is busy now.
*/
FCSPI_StatusType FCSPI_Master_SelectPcs(const FCSPI_InstanceType eInst, const FCSPI_MasterPcsConfType *pCfg);
/**@}*/
/**
* @name API declaration for FCSpi slave mode
*
*/
/**@{*/
/**
* @brief Init the FCSpi instance as spi slave side
*
* @param eInst Which FCSpi Hardware instance
* @param pCfg Configuration of the FCSpi
* @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, some error occur.
*/
FCSPI_StatusType FCSPI_Slave_Init(const FCSPI_InstanceType eInst, const FCSPI_SlaveCfgType *pCfg);
/**@}*/
/**
* @name Type definition for FCSpi master/slave mode
*
*/
/**@{*/
/**
* @brief Send and receive asynchronously
* 1) If the trigger source is driver user poll, this api not support this mode.
* 2) If the trigger source is interrupt or DMA, this api will start the transmission, then return immediately.
* After transmission stop, it will trigger an interrupt.
* During the transmission, the send data buffer and receive data buffer
* should keep valid until the transmission stop.
* @param eInst Which FCSpi Hardware instance
* @param pCfg the data information, MUST NOT null
* @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when start transfer successfully. Others, some error occur.
*/
FCSPI_StatusType FCSPI_AsyncTransfer(const FCSPI_InstanceType eInst, const FCSPI_AsyncDataInfType *pCfg);
/**
* @brief Send and receive synchronously
* 1) If the semaphore callbacks are configured,
* and the driver is configured transmitting triggered by interrupt, or by DMA,
* the driver will use semaphore to wait the transmission stopped.
* In this case, the timeout value is passed to semaphore callback directly.
* 2) If the semaphore callbacks are not configured,
* this api will poll the status when triggered by interrupt or DMA,
* or poll to trigger the transmission when the mode is "FCSPI_TRANSFER_TRIGGER_SRC_USER_POLL".
* In this case, the timeout value has different meaning for different trigger mode.
* Read the source code for detail.
* @param eInst Which FCSpi Hardware instance
* @param pCfg the data information, MUST NOT null
* @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when transfer successfully. Others, some error occur.
*/
FCSPI_StatusType FCSPI_SyncTransfer(const FCSPI_InstanceType eInst, const FCSPI_SyncDataInfType *pCfg);
/**
* @brief If it's in transfer, get its stat, or get the last transfer's stat.
*
* @param eInst Which FCSpi Hardware instance
* @param pCfg the transfer information, can be null
* @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when the last transfer is finish successfully. Others, busy or error occur.
*/
FCSPI_StatusType FCSPI_GetLatestTransferStat(const FCSPI_InstanceType eInst, FCSPI_TransferRemainInfType *pCfg);
/**
* @brief Abort current transfer if exist, or just recovery the hardware.
*
* @param eInst Which FCSpi Hardware instance
*/
void FCSPI_AbortTransfer(const FCSPI_InstanceType eInst);
/**
* @brief Deinit the FCSpi
*
* @param eInst Which FCSpi Hardware instance
* @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when deinit the FCSpi successfully. Others, the hardware is busy now.
*/
FCSPI_StatusType FCSPI_Deinit(const FCSPI_InstanceType eInst);
/**
* @brief Select the trigger source(DMA with interrupt / interrupt / user poll)
*
* @param eInst Which FCSpi Hardware instance
* @param eSrc three source, 1) DMA move data between memory and registers, notified when finish by interrupt; 2) purely by interrupt; 3) purely by user poll.
* @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when successfully. Others, error.
*/
FCSPI_StatusType FCSPI_SelectTriggerSrc(FCSPI_InstanceType eInst, FCSPI_TriggerSrcType eSrc);
/**
* @brief fcspi 0 interrupt handler
*
* @note This function should be called as/in FCSPI 0 interrupt handler
*/
void FCSPI0_IRQHandler(void);
/**
* @brief fcspi 1 interrupt handler
*
* @note This function should be called as/in FCSPI 1 interrupt handler
*/
void FCSPI1_IRQHandler(void);
/**
* @brief fcspi 2 interrupt handler
*
* @note This function should be called as/in FCSPI 2 interrupt handler
*/
void FCSPI2_IRQHandler(void);
/**
* @brief fcspi 3 interrupt handler
*
* @note This function should be called as/in FCSPI 3 interrupt handler
*/
void FCSPI3_IRQHandler(void);
/**
* @brief fcspi 4 interrupt handler
*
* @note This function should be called as/in FCSPI 4 interrupt handler
*/
void FCSPI4_IRQHandler(void);
/**
* @brief fcspi 5 interrupt handler
*
* @note This function should be called as/in FCSPI 5 interrupt handler
*/
void FCSPI5_IRQHandler(void);
/**@}*/
/** @}*/ /* fc7xxx_driver_fcspi */
#if defined(__cplusplus)
}
#endif
#endif /* _DRIVER_FC7XXX_DRIVER_FCSPI_H_ */

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@ -0,0 +1,434 @@
/**
* @file fc7xxx_driver_fcuart.h
* @author Flagchip
* @brief FC7xxx FCUart driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip0122 N/A FC7xxx internal release version
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_FCUART_H_
#define _DRIVER_FC7XXX_DRIVER_FCUART_H_
#include "HwA_fcuart.h"
/**
* @addtogroup fc7xxx_driver_fcuart
* @{
*/
/********* Macro ************/
#define FCUART_FIFO_DEPTH 16U
#define ESCAPE_CHARACTER (char)0x5c
#define ENTER (uint8_t)0x0d
#define NEW_LINE (uint8_t)0x0a
#define SPACE (uint8_t)0x20
#define FLOAT_ZERO 0.00000001
/********* Local typedef ************/
/**
* @brief FCUART error status
*
*/
typedef enum
{
FCUART_ERROR_OK = 0x00U, /**< FCUART_ERROR_OK means no error */
FCUART_ERROR_INVALID_VERSION = 0x01U, /**< FCUART_ERROR_INVALID_VERSION means version is not same */
FCUART_ERROR_FAILED = 0x02U, /**< FCUART_ERROR_FAILED means operation is failed */
FCUART_ERROR_INVALID_PARAM = 0x04U, /**< FCUART_ERROR_INVALID_PARAM means parameters are invalid */
FCUART_ERROR_INVALID_SIZE = 0x08U, /**< FCUART_ERROR_INVALID_SIZE means size is invalid */
FCUART_ERROR_INVALID_SEQUENCE = 0x10U, /**< FCUART_ERROR_INVALID_SEQUENCE means sequence is error */
FCUART_ERROR_TIMEOUT = 0x20U, /**< FCUART_ERROR_TIMEOUT means operation is timeout */
}FCUART_ErrorTypeEnum;
/**
* @brief UART fifo receive idle character number
*/
typedef enum
{
FCUART_FIFO_RX_IDLE_DISABLE = 0U,
FCUART_FIFO_RX_IDLE_CHARACTER_1,
FCUART_FIFO_RX_IDLE_CHARACTER_2,
FCUART_FIFO_RX_IDLE_CHARACTER_4,
FCUART_FIFO_RX_IDLE_CHARACTER_8,
FCUART_FIFO_RX_IDLE_CHARACTER_16,
FCUART_FIFO_RX_IDLE_CHARACTER_32,
FCUART_FIFO_RX_IDLE_CHARACTER_64
} FCUART_Fifo_RxIdleCharNumType;
/**
* @brief UART CTRL register interrupt
*
*/
typedef enum
{
FCUART_INT_CTRL_ORIE = FCUART_CTRL_ORIE_MASK,
FCUART_INT_CTRL_NEIE = FCUART_CTRL_NEIE_MASK,
FCUART_INT_CTRL_FEIE = FCUART_CTRL_FEIE_MASK,
FCUART_INT_CTRL_PEIE = FCUART_CTRL_PEIE_MASK,
FCUART_INT_CTRL_TIE = FCUART_CTRL_TIE_MASK,
FCUART_INT_CTRL_TCIE = FCUART_CTRL_TCIE_MASK,
FCUART_INT_CTRL_RIE = FCUART_CTRL_RIE_MASK,
FCUART_INT_CTRL_IIE = FCUART_CTRL_IIE_MASK,
FCUART_INT_CTRL_TE = FCUART_CTRL_TE_MASK,
FCUART_INT_CTRL_RE = FCUART_CTRL_RE_MASK,
FCUART_INT_CTRL_M0IE = FCUART_CTRL_M0IE_MASK,
FCUART_INT_CTRL_M1IE = FCUART_CTRL_M1IE_MASK
} FCUART_InterruptSel;
/**
* @brief UART error status type
*
*/
typedef enum
{
FCUART_ERROR_NONE = 0x0000U, /**< FCUART_ERROR_NONE No Error, */
FCUART_ERROR_RORF = 0x0001U, /**< FCUART_ERROR_RORF Receiver Overrun Flag, */
FCUART_ERROR_NF = 0x0002U, /**< FCUART_ERROR_NF Noise Flag, */
FCUART_ERROR_FEF = 0x0004U, /**< FCUART_ERROR_FEF Frame Error Flag, */
FCUART_ERROR_PEF = 0x0008U, /**< FCUART_ERROR_PEF Parity Error Flag, */
FCUART_ERROR_RPEF = 0x0010U, /**< FCUART_ERROR_RPEF Receive Data Parity Error Flag, */
FCUART_ERROR_TPEF = 0x0020U /**< FCUART_ERROR_TPEF Transmit Data Parity Error Flag, */
}FCUART_ErrorStatusType;
/**
* @brief UART idle character number
*/
typedef enum
{
FCUART_IDLE_CHARCTER_1 = 0U,
FCUART_IDLE_CHARCTER_2,
FCUART_IDLE_CHARCTER_4,
FCUART_IDLE_CHARCTER_8,
FCUART_IDLE_CHARCTER_16,
FCUART_IDLE_CHARCTER_32,
FCUART_IDLE_CHARCTER_64,
FCUART_IDLE_CHARCTER_128
} FCUART_IdleCharNumType;
/**
* @brief UART idle type
*/
typedef enum
{
FCUART_START_AFTER_STARTBIT = 0U,
FCUART_START_AFTER_STOPBIT
} FCUART_IdleStartType;
/**
* @brief UART initial data define
*
*/
typedef struct
{
uint32_t u32ClkSrcHz; /**< module clock hz */
FCUART_BitModeType eBitMode; /**< 8bits or 9bits */
bool bParityEnable; /**< Parity Enable=1 */
FCUART_ParityType eParityType; /**< parity type */
FCUART_StopBitNumType eStopBit; /**< stop bit num; */
bool bEnTxFifo; /**< Enable Tx FIFO, 16 data words depth */
uint8_t u8TxFifoWaterMark; /**< Tx FIFO,When FIFO/buffer number equal or less than this
an interrupt or a DMA request will be generated */
bool bEnRxFifo; /**< Enable Rx FIFO, 16 data words depth */
uint8_t u8RxFifoWaterMark; /**< Rx FIFO, When FIFO/buffer number greater than this
an interrupt or a DMA request will be generated */
FCUART_Fifo_RxIdleCharNumType eFifoRxIdleCharNum; /**< Fifo Rx idle character number */
bool bEnTxEmptyDma; /**< Enable transmit DMA */
bool bEnRxFullDma; /**< Enable receiver full DMA */
bool bEnRxIdleDma; /**< Enable Rx Idle DMA */
FCUART_IdleCharNumType eIdleCharNum; /**< Idle character number */
FCUART_IdleStartType eIdleStart; /**< Idle character start type */
uint32_t u32Baudrate; /**< normal baud-rate */
uint32_t u32TransmitTimeout; /**< transmit timeout tick, default 3000U */
} FCUART_InitType;
/**
* @brief UART transmit and receive data define
*
*/
typedef struct
{
uint8_t* pDatas; /**< Data buffer point, Must be initial with a array address */
uint32_t u32DataLen; /**< data length */
}FCUART_DataType;
/** Error call back function type, errors are combine with FCUART_ErrorStatusType */
typedef void (*FCUART_ErrorInterrupt_CallBackType)(uint8_t u8UartIndex, uint32_t u32Error);
/** Transmit/Receive call back function type */
typedef void (*FCUART_TxRxInterrupt_CallBackType)(uint8_t u8UartIndex, FCUART_DataType *pTxRxCfg);
/** Idle call back function type */
typedef void (*FCUART_IdleInterrupt_CallBackType)(uint8_t u8UartIndex);
/**
* @brief UART callback functions data define
*
*/
typedef struct
{
bool bEnErrorInterrupt; /**< enable error interrupt */
FCUART_ErrorInterrupt_CallBackType pErrorNotify; /**< error interrupt callback function address */
bool bEnRxInterrupt; /**< enable receive interrupt */
FCUART_DataType *pRxBuf; /**< receive interrupt message buffer */
FCUART_TxRxInterrupt_CallBackType pRxNotify; /**< receive interrupt callback function address */
bool bEnTxInterrupt; /**< enable receive interrupt */
FCUART_DataType *pTxBuf; /**< transfer interrupt message buffer */
FCUART_TxRxInterrupt_CallBackType pTxEmptyNotify; /**< transfer empty interrupt callback function address */
FCUART_TxRxInterrupt_CallBackType pTxCompleteNotify; /**< transfer complete interrupt callback function address */
bool bEnIdleInterrupt; /**< enable idle interrupt */
FCUART_IdleInterrupt_CallBackType pIdleNotify; /**< idle interrupt callback function address */
} FCUART_InterruptType;
/**
* @brief UART WakeUp functions data define
*
*/
typedef struct
{
bool bEnWakeup; /**< enable wake-up */
uint32_t u32WakeUpData; /**< wake-up data */
} FCUART_WakeupType;
/** Errortype Define as uint8 */
typedef uint8_t FCUART_ErrorType;
/* ################################################################################## */
/* ########################### Global Prototype Functions ########################### */
/**
* @brief Initial UART variables Memory
*
*/
void FCUART_InitMemory(uint8_t u8UartIndex);
/**
* @brief This Function is used to initial UART instance
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param pInitCfg contains clock, baud-rate, Bit Mode, parity and so on.
* @return FCUART_ERROR_OK is ok, others are not ok
*/
FCUART_ErrorType FCUART_Init(uint8_t u8UartIndex, FCUART_InitType *pInitCfg);
/**
* @brief This Function is used to de-initial UART instance
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @return FCUART_ERROR_OK is ok, others are not ok
*/
FCUART_ErrorType FCUART_DeInit(uint8_t u8UartIndex);
/**
* @brief This Function is used to set UART interrupt
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param pInterruptCfg contains callback functions
* @return FCUART_ERROR_OK is ok, others are not ok
*/
FCUART_ErrorType FCUART_SetInterrupt(uint8_t u8UartIndex, FCUART_InterruptType *pInterruptCfg);
/**
* @brief This Function is used to set UART WakeUp
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param pWakeupCfg contains UART wake-up parameters
* @return FCUART_ERROR_OK is ok, others are not ok
*/
FCUART_ErrorType FCUART_SetWakeup(uint8_t u8UartIndex, FCUART_WakeupType *pWakeupCfg);
/**
* @brief This Function is used to start receiving
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @return FCUART_ERROR_OK is ok, others are not ok
*/
FCUART_ErrorType FCUART_StartReceive(uint8_t u8UartIndex);
/**
* @brief This Function is used to stop receiving
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @return FCUART_ERROR_OK is ok, others are not ok
*/
FCUART_ErrorType FCUART_StopReceive(uint8_t u8UartIndex);
/**
* @brief This Function is used to start transmit
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @return FCUART_ERROR_OK is ok, others are not ok
*/
FCUART_ErrorType FCUART_StartTransmit(uint8_t u8UartIndex);
/**
* @brief This Function is used to stop transmitting
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @return FCUART_ERROR_OK is ok, others are not ok
*/
FCUART_ErrorType FCUART_StopTransmit(uint8_t u8UartIndex);
/**
* @brief This Function is used to transmit UART data
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param pUartData contains UART data and length
* @return FCUART_ERROR_OK is ok, others are not ok
*/
FCUART_ErrorType FCUART_Transmit(uint8_t u8UartIndex, FCUART_DataType *pUartData);
/**
* @brief This Function is used to print ASCII char from UART
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param fmt is char format
* @return FCUART_ERROR_OK is ok, others are not ok
*/
FCUART_ErrorType FCUART_Printf(uint8_t u8UartIndex, char* fmt,...);
/**
* @brief Get Stat Flag
*
* @param u8UartIndex UART instance
* @param eStatusType stat type
* @return FCUART STAT status flag
*/
uint32_t FCUART_GetStatus(uint8_t u8UartIndex, FCUART_StatType eStatusType);
/**
* @brief This Function is used to receive data when polling (not used when rx interrupt enabled)
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param pRxMsg is data buffer address, and pDatas need to be initialed with external buffer
* @return FCUART_ERROR_OK is ok, others are not ok
*/
FCUART_ErrorType FCUART_Receive_Polling(uint8_t u8UartIndex, FCUART_DataType *pRxMsg);
/**
* @brief This Function is used to get error when polling (not used when error interrupt enabled)
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param pErrorValue is error value
* @return FCUART_ERROR_OK is ok, others are not ok
*/
FCUART_ErrorType FCUART_Error_Polling(uint8_t u8UartIndex, uint32_t *pErrorValue);
/**
* @brief This Function is used to enable fcuart loop mode
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param bStatus enable/disable status of loop mode
* @return FCUART_ERROR_OK is ok, others are not ok
*
*/
FCUART_ErrorType FCUART_SetLoopMode(uint8_t u8UartIndex, bool bStatus);
/**
* @brief This Function is used to deal with FCUART TxRx interrupt
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
*
*/
void FCUARTN_RxTx_IRQHandler(uint8_t u8UartIndex);
/**
* @brief This Function is used to send 9 bits data
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param u16Data data to send
* @return FCUART_ERROR_OK is ok, others are not ok
*
*/
FCUART_ErrorType FCUART_SendData_9Bits(uint8_t u8UartIndex, uint16_t u16Data);
/**
* @brief This Function is used to Get 9 bits data
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param pData pointer to data
* @return FCUART_ERROR_OK is ok, others are not ok
*
*/
FCUART_ErrorType FCUART_GetData_9Bits(uint8_t u8UartIndex, uint16_t *pData);
/**
* @brief This Function is used to send 10 bits data
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param u16Data data to send
* @return FCUART_ERROR_OK is ok, others are not ok
*
*/
FCUART_ErrorType FCUART_SendData_10Bits(uint8_t u8UartIndex, uint16_t u16Data);
/**
* @brief This Function is used to Get 10 bits data
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param pData pointer to data
* @return FCUART_ERROR_OK is ok, others are not ok
*
*/
FCUART_ErrorType FCUART_GetData_10Bits(uint8_t u8UartIndex, uint16_t *pData);
/**
* @brief This Function is used to set bit mode,parity and stop bit
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param pData pointer to data
* @return FCUART_ERROR_OK is ok, others are not ok
*
*/
FCUART_ErrorType FCUART_SetBitModeAndParity( uint8_t u8UartIndex,
FCUART_BitModeType eBitMode,
FCUART_StopBitNumType eStopBit,
FCUART_ParityType eParityType,
bool bParityEnable
);
/**
* @brief This Function is used to Get current interrupt mode
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param u32Data Interrupt type to get
* @return true/false
*
*/
bool FCUART_GetInterruptMode(uint8_t u8UartIndex, uint32_t u32Data);
/**
* @brief This Function is used to assign data to send through interrupt
*
* @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U)
* @param pData data pointer
* @param u32Length data length to send
* @return FCUART_ERROR_OK is ok, others are not ok
*
*/
FCUART_ErrorType FCUART_AssignTxInterruptData(uint8_t u8UartIndex, uint8_t * pData, uint32_t u32Length);
/** @}*/
#endif

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/**
* @file fc7xxx_driver_flash.c
* @author Flagchip
* @brief FC7xxx Flash driver type definition and API
* @version 0.1.0
* @date 2024-01-11
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7200
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_FLASH_H_
#define _DRIVER_FC7XXX_DRIVER_FLASH_H_
#include "device_header.h"
/**
* @addtogroup fc7xxx_driver_flash
* @{
*/
/***********************************************************************************************************************
* DEFINES
**********************************************************************************************************************/
/* ------------------------- PFlash ------------------------ */
/** PFlash start address */
#define PFLASH_ADDR_START 0x01000000U
#define PFLASH_ADDR_END 0x011FFFFFU
#define PFLASH_SIZE 0x00200000U /* 256KB */
#define PFLASH_BANK_SIZE 0x00100000U
#define PFLASH_LAST256K_OFFSET 0xC0000UL
/** Program minimum size */
#define PFLASH_PROGRAM_PAGE_MIN_SIZE 0x08U /* 8 bytes */
/** Program maximum */
#define PFLASH_PROGRAM_PAGE_MAX_SIZE 0x80U /* 128 bytes */
/** Erase size */
#define PFLASH_ERASE_SECTOR_SIZE 0x800U /* 2 KBytes */
/** Erase value of flash memory */
#define PFLASH_ERASED_VALUE 0xFFU
/** 4 PFlash Banks, every bank is 2MB */
#define PFLASH_BANK_NUM 0x02U
/* ------------------------- DFlash ------------------------ */
/** DFlash total size */
#define DFLASH_SIZE 0x00040000U /* 256KB */
/** DFlash start address */
#define DFLASH_ADDR_START 0x04000000U
/** DFlash end address */
#define DFLASH_ADDR_END 0x0401FFFFU
/** Program minimum size */
#define DFLASH_PROGRAM_PAGE_MIN_SIZE 0x08U /* 16 bytes */
/** Program maximum */
#define DFLASH_PROGRAM_PAGE_MAX_SIZE 0x80U /* 128 bytes */
/** Erase size */
#define DFLASH_ERASE_SECTOR_SIZE 0x800U /* 8 KBytes */
/** Erase value of flash memory */
#define DFLASH_ERASED_VALUE 0xFFU
/** 1 DFlash Banks, every bank is 2MB */
#define DFLASH_BANK_NUM 0x01U
/** DFlash Bank 0 size */
#define DFLASH_BANK0_SIZE 0x00040000U
#define FLASH_256KB_SIZE 0x00040000U
/** ########################################## Error Code ################################################ */
/**
* \brief FLASH API error status
*
*/
typedef enum
{
FLASH_ERROR_OK = 0x00U,/**< FLASH_ERROR_OK means no error */
FLASH_ERROR_NO_INIT, /**< FLASH_ERROR_NO_INIT means rom code api address is not initialed */
FLASH_ERROR_INVALID_VERSION, /**< FLASH_ERROR_INVALID_VERSION means rom code api version is not same */
FLASH_ERROR_FAILED, /**< FLASH_ERROR_FAILED means operation is failed */
FLASH_ERROR_INVALID_PARAM, /**< FLASH_ERROR_INVALID_PARAM means parameters are invalid */
FLASH_ERROR_INVALID_ADDR, /**< FLASH_ERROR_INVALID_ADDR means address is invalid */
FLASH_ERROR_INVALID_SIZE, /**< FLASH_ERROR_INVALID_SIZE means size is invalid */
FLASH_ERROR_INVALID_SEQUENCE, /**< FLASH_ERROR_INVALID_SEQUENCE means sequence is error */
FLASH_ERROR_TIMEOUT, /**< FLASH_ERROR_TIMEOUT means operation is timeout */
FLASH_ERROR_END = 0xFFFFFFFFU /**< FLASH_ERROR_END make aligned 32bits */
}FLASH_StatusType;
typedef enum
{
FLASH_BLOCK_SELECT0 =0x000u,
FLASH_BLOCK_SELECT1 =0x001u,
FLASH_DATA_BLOCK_SELECT0 =0x002u
}FLASH_API_BLOCK_SELECT_TYPE;
/** ########################################## Type define ################################################ */
/**
* \brief Flash driver parameter define
*
*/
typedef struct
{
uint32_t u32Address; /**< Logical target address */
uint32_t u32Length; /**< Length in logical sectors or bytes */
uint8_t *pData; /**< Pointer to data buffer (read only) */
uint8_t (*wdTriggerFct)(void); /**< Pointer to watchdog handling function */
uint32_t u32ErrorAddress; /**< Error address */
} FLASH_DRIVER_ParamType;
/**
* \brief Initial Flash api address
*
*/
void FLASHDRIVER_Init(void);
/**
* \brief flash driver erase block function
*
* \param blk_sel c
* \return ErrorType
*/
FLASH_StatusType FLASHDRIVER_FlashEraseBlock ( FLASH_API_BLOCK_SELECT_TYPE blk_sel );
/**
* \brief Pflash driver erase function, called after FLASHDRIVER_ArrayCopyToRam
*
* \param pFlashParam contains flash erase function parameter, address is align to 0x400, and length is align to 0x400
* \return ErrorType
*/
FLASH_StatusType FLASHDRIVER_PFlashEraseSector ( FLASH_DRIVER_ParamType * pFlashParam );
/**
* \brief Pflash driver write function, called after FLASHDRIVER_ArrayCopyToRam
*
* \param pFlashParam contains flash write function parameter, address is align to 0x08, and length is align to 0x08
* \return ErrorType
*/
FLASH_StatusType FLASHDRIVER_PFlashWrite ( FLASH_DRIVER_ParamType * pFlashParam );
/**
* \brief DFlash Driver Function for Erasing
*
* \param pFlashParam flash driver erase parameter
* \return ErrorType
*/
FLASH_StatusType FLASHDRIVER_DFlashEraseSector(FLASH_DRIVER_ParamType *pFlashParam);
/**
* \brief DFlash Driver Function for Writing
*
* \param pFlashParam flash driver write parameter
* \return ErrorType
*/
FLASH_StatusType FLASHDRIVER_DFlashWrite(FLASH_DRIVER_ParamType *pFlashParam);
#endif /* end of DRIVER_FLASH_H_ */

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/**
* @file fc7xxx_driver_flexcan.h
* @author Flagchip
* @brief FC7xxx CAN driver type definition and API
* @version 0.1.0
* @date 2022-02-20
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Author Descriptions
* --------- ---------- ------------ ---------------
* 0.1.0 2024-1-13 Flagchip0112 First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC4XXX_DRIVER_FLEXCAN_H_
#define _DRIVER_FC4XXX_DRIVER_FLEXCAN_H_
#include "HwA_flexcan.h"
/* ################################################################################## */
/* ####################################### Macro #################################### */
#define FLEXCAN_CHECK_PARAMETERS STD_ON
/* ################################################################################## */
/* ################################### Type define ################################## */
/**
* @addtogroup fc7xxx_driver_can
* @{
*/
/**
* @brief FLEXCAN ID Type
*
*/
typedef enum
{
FLEXCAN_ID_STD = 0x00U, /**< FLEXCAN_ID_STD standard id */
FLEXCAN_ID_EXT = 0x01U /**< FLEXCAN_ID_EXT extended id */
} FLEXCAN_IdType;
/**
* @brief FLEXCAN Data Frame Type
*
*/
typedef enum
{
FLEXCAN_FRAME_DATA = 0x00U, /**< FLEXCAN_FRAME_DATA data frame */
FLEXCAN_FRAME_REMOTE = 0x01U /**< FLEXCAN_FRAME_REMOTE remote frame */
} FLEXCAN_DataType;
/**
* @brief FLEXCAN baud-rate clock source
*
*/
typedef enum
{
FLEXCAN_BAUDCLK_HZ_8M = 8000000U, /**< FLEXCAN_BAUDCLK_HZ_8M 8MHz clock source */
FLEXCAN_BAUDCLK_HZ_12M = 12000000U, /**< FLEXCAN_BAUDCLK_HZ_12M 12MHz clock source */
FLEXCAN_BAUDCLK_HZ_16M = 16000000U, /**< FLEXCAN_BAUDCLK_HZ_16M 16MHz clock source */
FLEXCAN_BAUDCLK_HZ_24M = 24000000U, /**< FLEXCAN_BAUDCLK_HZ_24M 24MHz clock source */
FLEXCAN_BAUDCLK_HZ_48M = 48000000U, /**< FLEXCAN_BAUDCLK_HZ_48M 48MHz clock source */
FLEXCAN_BAUDCLK_HZ_96M = 96000000U, /**< FLEXCAN_BAUDCLK_HZ_96M 96MHz clock source */
FLEXCAN_BAUDCLK_HZ_120M = 120000000U,/**< FLEXCAN_BAUDCLK_HZ_120M 120MHz clock source */
FLEXCAN_BAUDCLK_HZ_150M = 150000000U /**< FLEXCAN_BAUDCLK_HZ_150M 150MHz clock source */
} FLEXCAN_BaudClkType;
/**
* @brief FLEXCAN baud-rate source
*
*/
typedef enum
{
FLEXCAN_BAUD_100K = 100000U, /**< FLEXCAN_BAUD_100K normal bit 100Kbps */
FLEXCAN_BAUD_125K = 125000U, /**< FLEXCAN_BAUD_100K normal bit 125Kbps */
FLEXCAN_BAUD_250K = 250000U, /**< FLEXCAN_BAUD_250K normal bit 250Kbps */
FLEXCAN_BAUD_500K = 500000U, /**< FLEXCAN_BAUD_500K normal bit 500Kbps */
FLEXCAN_BAUD_800K = 800000U, /**< FLEXCAN_BAUD_500K normal bit 800Kbps */
FLEXCAN_BAUD_1M = 1000000U,/**< FLEXCAN_BAUD_1M normal bit 1Mbps */
FLEXCAN_BAUD_2M = 2000000U,/**< FLEXCAN_BAUD_2M normal bit 2Mbps */
FLEXCAN_BAUD_3M = 3000000U,/**< FLEXCAN_BAUD_3M normal bit 3Mbps */
FLEXCAN_BAUD_4M = 4000000U,/**< FLEXCAN_BAUD_4M normal bit 4Mbps */
FLEXCAN_BAUD_5M = 5000000U,/**< FLEXCAN_BAUD_5M normal bit 5Mbps */
FLEXCAN_BAUD_6M = 6000000U,/**< FLEXCAN_BAUD_6M normal bit 6Mbps */
FLEXCAN_BAUD_8M = 8000000U /**< FLEXCAN_BAUD_8M normal bit 8Mbps */
} FLEXCAN_BaudType;
/**
* @brief FLEXCAN data length type
*
*/
typedef enum
{
FLEXCAN_DATAWIDTH_8 = 8U, /**< FLEXCAN_DATALEN_8 8 bytes data width */
FLEXCAN_DATAWIDTH_16 = 16U,/**< FLEXCAN_DATALEN_16 16 bytes data width */
FLEXCAN_DATAWIDTH_32 = 32U,/**< FLEXCAN_DATALEN_32 32 bytes data width */
FLEXCAN_DATAWIDTH_64 = 64U /**< FLEXCAN_DATALEN_64 64 bytes data width */
} FLEXCAN_DataWidthType;
/**
* @brief FLEXCAN data length type
*
*/
typedef enum
{
FLEXCAN_DIR_DISABLE = 0U, /**< FLEXCAN_DATALEN_8 8 bytes data width */
FLEXCAN_DIR_ENABLE_WITHOUT_TRIG = 1U, /**< FLEXCAN_DATALEN_8 8 bytes data width */
FLEXCAN_DIR_ENABLE_WITH_TRIG = 3U /**< FLEXCAN_DATALEN_8 8 bytes data width */
} FLEXCAN_DirectType;
/**
* @brief FLEXCAN init structure definition
*/
typedef struct
{
FLEXCAN_ClockSrcType eClkSrcSel; /**< Clock Source Select */
FLEXCAN_BaudClkType eClkSrcHz; /**< clock hz for baud-rate */
uint8_t bListenOnly;
uint8_t bEnFd; /**< enable FLEXCAN fd */
uint8_t bEnBrs; /**< data bit baud-rate used */
uint8_t bEnRxFifo; /**< Rx FIFO */
uint8_t bEnDma; /**< The DMA feature FLEXCAN only be used in Rx FIFO */
uint8_t u8EnhancedFifoDmaWM; /**< The DMA watermark only work in CANFD FIFO mode, range 1- 12 */
FLEXCAN_BaudType eBaudrate; /**< normal baud-rate */
FLEXCAN_BaudType eDataBaud; /**< data baud-rate */
FLEXCAN_DataWidthType eMbDataWidth; /**< when bEnFd=0, only FLEXCAN be set 8; when bEnFd=1, FLEXCAN be set as 8/16/32/64 */
FLEXCAN_DirectType eDirect; /**<Enable Direct Connection for CAN Tx and Rx */
} FLEXCAN_InitType;
/**
* @brief Transmit Message Buffer Configuration
*
*/
typedef struct
{
FLEXCAN_IdType eRxFrameType; /**< FLEXCAN ID type, 0 STD, 1 EXT */
uint32_t u32TxCanId; /**< FLEXCAN Transmit ID */
} FLEXCAN_TxMbConfigType;
/**
* @brief Receive Message Buffer Configuration
*
*/
typedef struct
{
FLEXCAN_IdType eRxFrameType; /**< FLEXCAN ID type, 0 STD, 1 EXT */
uint32_t u32RxCanId; /**< FLEXCAN received ID */
uint32_t u32RxCanIdMask; /**< FLEXCAN received ID mask, if mask bit is 1, received FLEXCAN id bit must same to u32RxCanId, or mask bit is 0, id bit is ignored */
} FLEXCAN_RxMbFilterType;
/**
* @brief FLEXCAN transmit message
*/
typedef struct
{
uint8_t u8TxHandler; /**< one message buffer used one handler, range 0 ~ txMbCnt-1 */
uint8_t bWaitTxCompleted;/**< wait transmit complete and clear iflag */
uint16_t u16WaitTxTimeout; /**< wait transmit complete timeout */
uint8_t bEnFd; /**< enable FLEXCAN fd */
uint8_t bEnBrs; /**< enable canfd data bit switch */
uint32_t u32CanId; /**< FLEXCAN id */
FLEXCAN_IdType eFrameType; /**< 0 STD, 1 EXT */
FLEXCAN_DataType eDataType; /**< 0 Data, 1 remote */
uint32_t u32DataLen; /**< data length */
uint8_t aData[64]; /**< data buffer */
} FLEXCAN_TxMsgType;
/**
* @brief FLEXCAN receive message
*/
typedef struct
{
uint8_t u8CanIndex; /**< FLEXCAN Index, 0,1,2..NUM */
uint8_t u8MbIndex; /**< Mb Index, 0,1,2...31 */
uint8_t bEnFd; /**< enable FLEXCAN fd */
uint8_t bEnBrs; /**< enable canfd data bit switch */
uint32_t u32CanId; /**< FLEXCAN id */
FLEXCAN_IdType eFrameType; /**< 0 STD, 1 EXT */
FLEXCAN_DataType eDataType; /**< 0 Data, 1 remote */
uint32_t u32DataLen; /**< data length */
uint8_t aData[80]; /**< data buffer */
} FLEXCAN_RxMsgType;
/**
* @brief FLEXCAN polling receive message
*/
typedef struct
{
uint8_t u8RxMsgCnt; /**< Receive Message Buffer Count */
FLEXCAN_RxMsgType *pRxMsgBuf; /**< Receive Message Buffer Address */
} FLEXCAN_RxMsgListType;
/**
* @brief FLEXCAN rx config structure definition
*/
typedef struct
{
FLEXCAN_RxMbFilterType *pRxFilterFifoList; /**< rx id list, occupy first n MB, one filter in one MB, or fifo */
uint8_t u8RxFilterFifoCnt; /**< rx id filter count, if set enhanced rx fifo, standard id number must multiple of 2 */
FLEXCAN_RxMbFilterType *pRxFilterMBList; /**< rx id list, occupy first n MB, one filter in one MB, or fifo */
uint8_t u8RxFilterMBCnt; /**< rx id filter count, if set enhanced rx fifo, standard id number must multiple of 2 */
uint8_t u8TxMsgCnt; /**< tx occupy next n MB, every id occupy one MB */
FLEXCAN_RxMsgType *pRxBuf; /**< receive buffer address, length same to u8RxFilterCnt */
} FLEXCAN_MBConfigType;
typedef struct
{
uint8_t u8Error_FLEXCAN_ESR1_BIT1ERR_FAST;
uint8_t u8Error_FLEXCAN_ESR1_BIT0ERR_FAST;
uint8_t u8Error_FLEXCAN_ESR1_CRCERR_FAST;
uint8_t u8Error_FLEXCAN_ESR1_FRMERR_FAST;
uint8_t u8Error_FLEXCAN_ESR1_STFERR_FAST;
uint8_t u8Error_FLEXCAN_ESR1_ERROVR;
uint8_t u8Error_FLEXCAN_ESR1_ERRINT_FAST;
uint8_t u8Error_FLEXCAN_ESR1_BOFFDONEINT;
uint8_t u8Error_FLEXCAN_ESR1_TWRNINT;
uint8_t u8Error_FLEXCAN_ESR1_RWRNINT;
uint8_t u8Error_FLEXCAN_ESR1_BIT1ERR;
uint8_t u8Error_FLEXCAN_ESR1_BIT0ERR;
uint8_t u8Error_FLEXCAN_ESR1_ACKERR;
uint8_t u8Error_FLEXCAN_ESR1_CRCERR;
uint8_t u8Error_FLEXCAN_ESR1_FRMERR;
uint8_t u8Error_FLEXCAN_ESR1_STFERR;
uint8_t u8Error_FLEXCAN_ESR1_TXWRN;
uint8_t u8Error_FLEXCAN_ESR1_RXWRN;
uint8_t u8Error_FLEXCAN_ESR1_FLTCONF;
uint8_t u8Error_FLEXCAN_ESR1_BOFFINT;
uint8_t u8Error_FLEXCAN_ESR1_ERRINT;
}FLEXCAN_ErrorDetailType;
/**
* @brief FLEXCAN Error Information
*
*/
typedef struct
{
uint32_t u32RxErrCnt_Fast; /**< Receive Error Counter for fast bits */
uint32_t u32RxErrCnt; /**< Receive Error Counter */
uint32_t u32TxErrCnt_Fast; /**< Transmit Error Counter for fast bits */
uint32_t u32TxErrCnt; /**< Transmit Error Counter */
uint32_t u32ErrorValue; /**< Error Register ESR1 Value */
FLEXCAN_ErrorDetailType tErrorDetail; /**< Detail error information for u32ErrorValue */
} FLEXCAN_ErrorInfoType;
/** Error callback function type */
typedef void (*FLEXCAN_ErrorInterruptCallBackType)(uint8_t u8CanIndex, FLEXCAN_ErrorInfoType *pErrorInfo);
/** transmit callback function type, u8TxHandler (0,1,2 and so on) */
typedef void (*FLEXCAN_TxInterruptCallBackType)(uint8_t u8CanIndex, uint8_t u8TxHandler);
/** Receive callback function type */
typedef void (*FLEXCAN_RxInterruptCallBackType)(uint8_t u8CanIndex, FLEXCAN_RxMsgType *pRxCfg);
/**
* @brief FLEXCAN interrupt callback setting
*
*/
typedef struct
{
uint8_t bEnErrorInterrupt; /**< enable error interrupt */
FLEXCAN_ErrorInterruptCallBackType pErrorNotify; /**< error interrupt callback function address */
uint8_t bEnTxMBInterrupt; /**< enable transmit interrupt */
FLEXCAN_TxInterruptCallBackType pTxMBNotify; /**< transmit interrupt callback function address */
uint8_t bEnRxMBInterrupt; /**< enable message buffer receive interrupt */
FLEXCAN_RxInterruptCallBackType pRxMBNotify; /**< receive message buffer interrupt callback function address */
uint8_t bEnRxFifoInterrupt; /**< enable receive fifo interrupt */
FLEXCAN_RxInterruptCallBackType pRxFifoNotify; /**< receive fifo interrupt callback function address */
} FLEXCAN_InterruptType;
/**
* @brief FLEXCAN error status
*
*/
typedef enum
{
FLEXCAN_ERROR_OK = 0x00U, /**< FLEXCAN_ERROR_OK means no error */
FLEXCAN_ERROR_INVALID_VERSION = 0x01U, /**< FLEXCAN_ERROR_INVALID_VERSION means version is not same */
FLEXCAN_ERROR_FAILED = 0x02U, /**< FLEXCAN_ERROR_FAILED means operation is failed */
FLEXCAN_ERROR_INVALID_PARAM = 0x04U, /**< FLEXCAN_ERROR_INVALID_PARAM means parameters are invalid */
FLEXCAN_ERROR_INVALID_SIZE = 0x08U, /**< FLEXCAN_ERROR_INVALID_SIZE means size is invalid */
FLEXCAN_ERROR_INVALID_SEQUENCE = 0x10U, /**< FLEXCAN_ERROR_INVALID_SEQUENCE means sequence is error */
FLEXCAN_ERROR_TIMEOUT = 0x20U, /**< FLEXCAN_ERROR_TIMEOUT means operation is timeout */
FLEXCAN_ERROR_BUSY = 0x40U, /**< FLEXCAN_ERROR_BUSY means current mb is busy */
} FLEXCAN_ErrorTypeEnum;
/** FLEXCAN Error Type */
typedef uint8_t FLEXCAN_ErrorType;
/* ################################################################################## */
/* ################################ Global Functions ################################ */
/**
* @brief Initial FLEXCAN variables Memory
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
*/
void FLEXCAN_InitMemory(uint8_t u8CanIndex);
/**
* @brief Initial CAN
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
* @param pInitCfg clock, baud-rate, canfd, data length and so on.
* @return 0 is ok, others are not ok
*/
FLEXCAN_ErrorType FLEXCAN_Init(uint8_t u8CanIndex, const FLEXCAN_InitType *const pInitCfg);
/**
* @brief De-initial can instance
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
* @return 0 is ok, others are not ok
*/
FLEXCAN_ErrorType FLEXCAN_DeInit(uint8_t u8CanIndex);
/**
* @brief Configure can receive message box and id filter
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
* @param pRxMbCfg contains CAN Instance, Rx CAN ID and Mask
* @return 0 is ok
*/
FLEXCAN_ErrorType FLEXCAN_RxFilterConfig(uint8_t u8CanIndex, const FLEXCAN_MBConfigType *const pRxMbCfg);
/**
* @brief Configure can interrupt
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
* @param pIntCfg Contians interrupt enable and call back function points
* @return 0 is ok
*/
FLEXCAN_ErrorType FLEXCAN_SetInterrupt(uint8_t u8CanIndex, const FLEXCAN_InterruptType *const pIntCfg);
/**
* @brief Start can instance
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
* @return 0 is ok
*/
FLEXCAN_ErrorType FLEXCAN_Start(uint8_t u8CanIndex);
/**
* @brief Stop can instance
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
*/
FLEXCAN_ErrorType FLEXCAN_Stop(uint8_t u8CanIndex);
/**
* @brief Transmit data, if tx disable, must call FLEXCAN_TransmitProcess after transmiting
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
* @param pTxMsg contains CAN instance, CAN ID, CAN FD and CAN data.
* @return 0 is ok
*/
FLEXCAN_ErrorType FLEXCAN_TransmitData(uint8_t u8CanIndex, const FLEXCAN_TxMsgType *const pTxMsg);
/**
* @brief Process flag after transmit
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
* @param u8Handler Transmit Handler
* @return 1 means process successfully and can transmit next time, 0 means no active flag, 0xff means out of range
*/
uint8_t FLEXCAN_TransmitProcess(uint8_t u8CanIndex, uint8_t u8TxHandler);
/**
* @brief Abort transmit with special transmit handler
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
* @param u8TxHandler Transmit handler
* @return 0 is ok
*/
FLEXCAN_ErrorType FLEXCAN_TransmitAbort(uint8_t u8CanIndex, uint8_t u8TxHandler);
/**
* @brief Receive data when polling (not used when rx interrupt enabled)
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
* @param pRxBufList is FLEXCAN_RxMsgType type point point, and don't need to be initialed
* @return 0 is ok
*/
FLEXCAN_ErrorType FLEXCAN_Receive_Polling(uint8_t u8CanIndex, FLEXCAN_RxMsgListType *const pRxBufList);
/**
* @brief Get can error
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
* @param pErrorInfo is error information
* @return 0 is no error, others contains error
*/
FLEXCAN_ErrorType FLEXCAN_GetErrorInfo(uint8_t u8CanIndex, FLEXCAN_ErrorInfoType *const pErrorInfo);
/**
* @brief Clear can error
*
* @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT
* @param pErrorInfo is error information
* @return 0 is no error, others contains error
*/
FLEXCAN_ErrorType FLEXCAN_ClrErrorInfo(uint8_t u8CanIndex, const FLEXCAN_ErrorInfoType *const pErrorInfo);
/**
* @brief Transfer Data length to DLC
*
* @param u32DataLen data length
* @return DLC
*/
uint32_t FLEXCAN_DataLenToDlc(uint32_t u32DataLen);
/**
* @brief Transfer DLC to Data length
*
* @param u32Dlc DLC Data Length
* @return
*/
uint32_t FLEXCAN_DlcToDataLen(uint32_t u32Dlc);
/**
* @brief Can interrupt process
*
* @param u8CanIndex Can Index, Must less than FLEXCAN_INSTANCE_COUNT
*/
void FLEXCAN_IRQHandler(uint8_t u8CanIndex);
/** @}*/
#endif

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/**
* @file fc7xxx_driver_fmc.h
* @author Flagchip
* @brief FC7xxx FMC driver type definition and API
* @version 0.1.0
* @date 2024-01-5
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-1-5 Flagchip120 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_FMC_H_
#define _DRIVER_FC7XXX_DRIVER_FMC_H_
#include "device_header.h"
#include "HwA_fmc.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_fmc
* @{
*/
/***********************************************************************************************************************
* DEFINES
**********************************************************************************************************************/
/** Program minimum size */
#define FLASH_PROGRAM_PAGE_SIZE 0x10U /* 16 bytes */
/** Erase size */
#define FLASH_ERASE_SECTOR_SIZE 0x800U /* 2 KBytes */
/* ------------------------- PFlash ------------------------ */
/** PFlash start address */
#define PFLASH_ADDR_START 0x01000000U
/** Erase value of flash memory */
#define PFLASH_ERASED_VALUE 0xFFU
/** 2 PFlash Banks, every bank is 1MB */
#define PFLASH_BANK_NUM 0x02U
#define PFLASH_TOTAL_SIZE 0x200000U
#define PFLASH_BANK_SIZE 0x100000U
#define PFLASH_PHANTOM_OFFSET 0xC0000UL
/* ------------------------- DFlash ------------------------ */
/** DFlash total size */
#define DFLASH_SIZE 0x00020000U /* 128KB */
/** DFlash start address */
#define DFLASH_ADDR_START 0x04000000U
/** DFlash end address */
#define DFLASH_ADDR_END 0x0401FFFFU
/** Erase value of flash memory */
#define DFLASH_ERASED_VALUE 0xFFU
/** 1 DFlash Banks, every bank is 2MB */
#define DFLASH_BANK_NUM 0x01U
/** DFlash Bank 0 size */
#define DFLASH_BANK0_SIZE 0x00020000U
#define FLASH_256KB_SIZE 0x00040000U
/** ########################################## Error Code ################################################ */
/**
* \brief FMC lock API error status
*
*/
typedef enum
{
FMC_LOCK_ERROR_OK = 0x00U,/**< FMC_LOCK_ERROR_OK means no error */
FMC_LOCK_ERROR_FAILED, /**< FMC_LOCK_ERROR_FAILED means operation is failed */
FMC_LOCK_ERROR_INVALID_PARAM, /**< FMC_LOCK_ERROR_INVALID_PARAM means parameters are invalid */
FMC_LOCK_ERROR_INVALID_ADDR, /**< FMC_LOCK_ERROR_INVALID_ADDR means address is invalid */
FMC_LOCK_ERROR_INVALID_SIZE, /**< FMC_LOCK_ERROR_INVALID_SIZE means size is invalid */
FMC_LOCK_ERROR_INVALID_SEQUENCE /**< FMC_LOCK_ERROR_INVALID_SEQUENCE means sequence is error */
} FMC_Lock_StatusType;
/** ########################################## Type define ################################################ */
/**
* \brief The instance index of the FMC peripheral
*
*/
typedef enum
{
FMC_INSTANCE_0 = 0x000u, /*!< FMC instance 0 is selected */
FMC_INSTANCE_1 = 0x001u /*!< FMC instance 1 is selected */
} FMC_InstanceType;
/**
* \brief FMC lock type
*
*/
typedef enum
{
FMC_UNLOCK = 0x000u,
FMC_LOCK = 0x001u
} FMC_API_LOCK_TYPE;
/**
* \brief FMC Flash type
*
*/
typedef enum
{
FMC_PFlash = 0x000u,
FMC_DFlash = 0x001u
} FMC_API_FLASH_TYPE;
/**
* \brief FMC Flash type
*
*/
typedef enum
{
FMC_Page = 0x000u,
FMC_Sector = 0x001u
} FMC_API_CLASS_TYPE;
/**
* \brief FMC active block type
*
*/
typedef enum
{
FMC_Active0 = 0x000u,
FMC_Active1 = 0x001u
} FMC_API_ACTIVE_BLOCK_TYPE;
/**
* \brief Flash driver parameter define
*
*/
typedef struct
{
uint32_t u32Address; /**< Logical target address */
uint32_t u32Length; /**< Length in logical sectors or pages */
uint32_t u32ErrorAddress; /**< Error address */
FMC_API_LOCK_TYPE bLock; /**< lock type */
FMC_API_FLASH_TYPE bFlash; /**< flash type */
FMC_API_CLASS_TYPE bClass; /**< class type */
FMC_InstanceType bFMC; /**< FMC instance */
} FMC_DRIVER_Lock_ParamType;
/**
* \brief FMC Driver Function for flash lock
*
* \param pFmcParam FMC driver flash lock parameter
* \return ErrorType
*/
FMC_Lock_StatusType FMCDRIVER_FlashLock(FMC_DRIVER_Lock_ParamType *pFmcParam);
/**
* \brief FMC set ota active block
*
* \param eInstance FMC instance
* \param bLock 0U-active block 0, 1U-active block 1
*/
void FMCDRIVER_SwapBlock(const FMC_InstanceType eInstance, FMC_API_ACTIVE_BLOCK_TYPE bActive);
#if defined(__cplusplus)
}
#endif
/** @}*/ /* fc7xxx_driver_fmc */
#endif

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/**
* @file fc7xxx_driver_fpu.h
* @author Flagchip051
* @brief FC4xxx FPU driver type definition and API
* @version 0.1.0
* @date 2024-01-11
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC4XXX_DRIVER_FPU_H_
#define _DRIVER_FC4XXX_DRIVER_FPU_H_
#include "HwA_fpu.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_fpu
* @{
*/
/**
* @brief Enable the FPU hardware.
*
* Usually, driver user only need use this API at the beginning of program. Nothing else about FPU need to be done.
* @details @verbatim
If only want use FPU,
1) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard) -> FPU Type set to "fpv5-sp-d16"
2) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> GNU Arm Cross C Compiler -> Preprocessor -> Defined symbols(-D) -> Add "__FPU_PRESENT=1" (without ")
3) and call FPU_Enable to enable FPU at the beginning of program.
If want to use DSP,
1) configure FCIDE to enable FPU compiler support, Properties -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard)
2) add MACRO "DRIVER_CM7_DSP_ENABLE" in FCIDE Properties -> C/C++ General -> Paths and Symbols -> Symbols -> GNU C and GNU C++ and Assembly
3) add Include Path to project Properties -> C/C++ General -> Paths and Symbols -> Includes -> GNU C and GNU C++ and Assembly:
../../../../../../Template/Device/CMSIS5_590/DSP/Include
../../../../../../Template/Device/CMSIS5_590/Core/Include
../../../../../../Template/Device/CMSIS5_590/DSP/PrivateInclude
4) and call FPU_Enable to enable FPU at the beginning of program.
@endverbatim
*/
void FPU_Enable(void);
/**
* @brief Disable the FPU hardware.
*
*/
void FPU_Disable(void);
/** @} */ /* fc7xxx_driver_fpu */
#if defined(__cplusplus)
}
#endif
#endif /* _DRIVER_FC4XXX_DRIVER_FPU_H_ */

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/**
* @file fc7xxx_driver_freqm.h
* @author Flagchip
* @brief FC7xxx FREQM driver type definition and API
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC4XXX_DRIVER_FREQM_H_
#define _DRIVER_FC4XXX_DRIVER_FREQM_H_
#include "HwA_freqm.h"
#include "stddef.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @brief FREQM operation return values
*
*/
typedef enum
{
FREQM_STATUS_SUCCESS = 0U, /*!< The FREQM operation is succeed */
FREQM_STATUS_PARAM_INVALID, /*!< The FREQM operation is failed because of parameter error */
FREQM_STATUS_TIMEOUT, /*!< The FREQM operation is failed because of time out */
} FREQM_StatusType;
/**
* @brief The FREQM measure counter start interrupt callback function prototype
*
*/
typedef void (*FREQM_MesCntStartCallBackType)(void);
/**
* @brief The FREQM measure counter stop interrupt callback function prototype
*
*/
typedef void (*FREQM_MesCntStopCallBackType)(void);
/**
* @brief The FREQM reference counter stop interrupt callback function prototype
*
*/
typedef void (*FREQM_RefCntStopCallBackType)(void);
/**
* @brief The FREQM fault interrupt callback function prototype
*
*/
typedef void (*FREQM_FaultCallBackType)(void);
/**
* @brief The configuration option for the FREQM interrupt
*
*/
typedef struct
{
bool bIntEnable; /*!< interrupt enable mask */
FREQM_MesCntStartCallBackType pMesCntStartCallback; /*!< Measure Counter Start interrupt callback */
FREQM_MesCntStopCallBackType pMesCntStopCallback; /*!< Measure Counter Stop interrupt callback */
FREQM_RefCntStopCallBackType pRefCntStopCallback; /*!< Reference Counter Stop interrupt callback */
FREQM_FaultCallBackType pFaultCallback; /*!< Fault interrupt callback */
} FREQM_InterruptType;
/**
* @brief The basic configuration option for the FREQM peripheral
*
*/
typedef struct
{
uint32_t u32MesLen;
uint32_t u32RefTo;
FREQM_MesClkSelType eClkSel; /*!< Ftu clock source */
uint8_t u8PredivVal; /*!< Frequency of the Reload Opportunities. Range is 0-31, */
} FREQM_InitType;
/**
* @brief Initialize FREQM configuration
*
* @param pInitStruct the basic configurations of the FREQM
* @return FREQM_StatusType whether the operation is successfully
*/
FREQM_StatusType FREQM_Init(const FREQM_InitType *const pInitStruct);
/**
* @brief De-initialize the FREQM
*
* @param eInstance the selected FREQM
* @return FREQM_StatusType whether the operation is successfully
*/
FREQM_StatusType FREQM_DeInit(void);
/**
* @brief Start the FREQM
*
* @return FREQM_StatusType whether the operation is successfully
*/
FREQM_StatusType FREQM_ClearStatus(void);
/**
* @brief Start the reference/measure counter
*
*/
void FREQM_StartMeasureCnt(void);
/**
* @brief Get saved reference counter value
*
* @return uint32_t saved reference counter value
*/
uint32_t FREQM_GetRefCntSave(void);
/**
* @brief Interrupt IRQ handle of FREQM
*
*/
void FREQM_IRQHandler(void);
/**
* @brief FREQM initialize interrupt function
*
* @param pIntStruct FREQM interrupt structure
* @return FREQM_StatusType whether the operation is successfully
*/
FREQM_StatusType FREQM_InterruptInit(const FREQM_InterruptType *const pIntrStruct);
/** @}*/ /* fc7xxx_driver_freqm */
#if defined(__cplusplus)
}
#endif
#endif

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/**
* @file fc7xxx_driver_ftu.h
* @author Flagchip070
* @brief FC7xxx FTU driver type definition and API
* @version 0.1.0
* @date 2022-11-15
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022-11-15 Flagchip070 N/A First version for FC7300
********************************************************************************/
#ifndef _DRIVER_FC4XXX_DRIVER_FTU_H_
#define _DRIVER_FC4XXX_DRIVER_FTU_H_
#include "HwA_ftu.h"
#include "stddef.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_ftu
* @{
*/
/**
* @name FTU Channel Bit Flag
* @brief Bit of channel indicate channel number
*
* @{
*/
#define BIT_FTU_CHANNEL_0 0x01U
#define BIT_FTU_CHANNEL_1 0x02U
#define BIT_FTU_CHANNEL_2 0x04U
#define BIT_FTU_CHANNEL_3 0x08U
#define BIT_FTU_CHANNEL_4 0x10U
#define BIT_FTU_CHANNEL_5 0x20U
#define BIT_FTU_CHANNEL_6 0x40U
#define BIT_FTU_CHANNEL_7 0x80U
/** @}*/
/**
* @name FTU Fault Bit Flag
* @brief Bit of fault flag
*
* @{
*/
#define FTU_FAULT_INPUT_0 0x01U
#define FTU_FAULT_INPUT_1 0x02U
/** @}*/
/**
* @brief Max number of Ftu fault
*
*/
#define FTU_FAULT_COUNT 2u
/**
* @brief Max number of Ftu input count
*
*/
#define FTU_INPUT_FILTER_COUNT 4u
/**
* @brief FTU operation return values
*
*/
typedef enum
{
FTU_STATUS_SUCCESS = 0U, /*!< The FTU operation is success */
FTU_STATUS_PARAM_INVALID, /*!< The FTU operation is failed because of parameter error */
FTU_STATUS_NO_CLOCK_SOURCE, /*!< The FTU operation is failed because of instance clock source is not set */
} FTU_StatusType;
/**
* @brief The FTU overflow and reload point callback function prototype
*
*/
typedef void (*FTU_InterruptCallBackType)(void);
/**
* @brief The FTU fault callback function prototype
*
*/
typedef void (*FTU_FaultCallBackType)(uint32_t);
/**
* @brief The FTU channel callback function prototype
*
*/
typedef void (*FTU_ChannelCallBackType)(uint32_t, uint32_t);
/**
* @brief The instance index of the FTU peripheral
*
*/
typedef enum
{
FTU_INSTANCE_0 = 0U,
FTU_INSTANCE_1,
FTU_INSTANCE_2,
FTU_INSTANCE_3,
FTU_INSTANCE_4,
FTU_INSTANCE_5,
FTU_INSTANCE_6,
FTU_INSTANCE_7,
} FTU_InstanceType;
/**
* @brief The channel index of the FTU peripheral
*
*/
typedef enum
{
FTU_CHANNEL_0 = 0U,
FTU_CHANNEL_1,
FTU_CHANNEL_2,
FTU_CHANNEL_3,
FTU_CHANNEL_4,
FTU_CHANNEL_5,
FTU_CHANNEL_6,
FTU_CHANNEL_7
} FTU_ChannelType;
/**
* @brief The clock source of FTU peripheral
*
*/
typedef enum
{
FTU_NO_CLK = 0U, /*!< No clock selected */
FTU_INTERNAL_CLK = 1U, /*!< FTU input clock */
FTU_EXTERNAL_CLK0 = 3U, /*!< External pin 0 input clock */
FTU_EXTERNAL_CLK1 = 4U, /*!< External pin 1 input clock */
FTU_EXTERNAL_CLK2 = 5U /*!< External pin 2 input clock */
} FTU_ClkSrcType;
/**
* @brief The channel operation of output compare mode
*
*/
typedef enum
{
FTU_OUTPUT_TOGGLE_PIN = 0U, /*!< Toggle Output on match */
FTU_OUTPUT_CLEAR_PIN, /*!< Clear Output on match */
FTU_OUTPUT_SET_PIN /*!< Set Output on match */
} FTU_OutputComparePinModeType;
/**
* @brief The initial level of the output compare channel
*
*/
typedef enum
{
FTU_OUTPUT_CMP_INIT_LOW = 0U, /*!< The initial level is low */
FTU_OUTPUT_CMP_INIT_HIGH, /*!< The initial level is high */
} FTU_OutputCompareInitLevelType;
/**
* @brief The channel operation of PWM mode
*
*/
typedef enum
{
FTU_PWM_HIGH_TRUE_PULSE = 0U, /*!< High-true pulses in PWM */
FTU_PWM_LOW_TRUE_PULSE, /*!< Low-true pulses in PWM */
} FTU_PwmPinModeType;
/**
* @brief PWM Aligned Mode
*
*/
typedef enum
{
FTU_EDGE_ALIGNED_PWM = 0u, /*!< Edge-Aligned PWM */
FTU_CENTER_ALIGNED_PWM /*!< Center-Aligned PWM */
}FTU_PwmAlignedType;
/**
* @brief The measurement is single or continuous
*
*/
typedef enum
{
FTU_MEASURE_SINGLE_MODE = 0u, /*!< Single mode */
FTU_MEASURE_CONTINUOUS_MODE /*!< Continuous mode */
} FTU_MeasureContModeType;
/**
* @brief Timing of start measurement
*
*/
typedef enum
{
FTU_MEASURE_START_AFTER_EDGE = 0u, /*!< The channel starts measuring after the first edge is detected */
FTU_MEASURE_START_IMMEDIATELY /*!< The measurement starts immediately after activating the channel */
}FTU_MeasureStartModeType;
/**
* @brief The reload point flag of FTU peripheral
*
*/
typedef enum
{
FTU_RELOAD_POINT_CNTMAX = 1u, /*!< Maximum Loading Point */
FTU_RELOAD_POINT_CNTMIN = (1u << 1), /*!< Minimum Loading Point */
FTU_RELOAD_POINT_CHANNEL_0 = (1u << 2), /*!< Channel 0 match is included as a reload opportunity */
FTU_RELOAD_POINT_CHANNEL_1 = (1u << 3), /*!< Channel 1 match is included as a reload opportunity */
FTU_RELOAD_POINT_CHANNEL_2 = (1u << 4), /*!< Channel 2 match is included as a reload opportunity */
FTU_RELOAD_POINT_CHANNEL_3 = (1u << 5), /*!< Channel 3 match is included as a reload opportunity */
FTU_RELOAD_POINT_CHANNEL_4 = (1u << 6), /*!< Channel 4 match is included as a reload opportunity */
FTU_RELOAD_POINT_CHANNEL_5 = (1u << 7), /*!< Channel 5 match is included as a reload opportunity */
FTU_RELOAD_POINT_CHANNEL_6 = (1u << 8), /*!< Channel 6 match is included as a reload opportunity */
FTU_RELOAD_POINT_CHANNEL_7 = (1u << 9), /*!< Channel 7 match is included as a reload opportunity */
} FTU_ReloadPointCfgType;
/**
* @brief The synchronization flag of FTU peripheral
*
*/
typedef enum
{
FTU_SYNC_FLAG_FTUEN = 1u, /*!< FTU Enable */
FTU_SYNC_FLAG_LDOK = (1u << 1), /*!< Load Enable */
FTU_SYNC_FLAG_CNTINC = (1u << 2), /*!< CNTIN Register Synchronization */
FTU_SYNC_FLAG_PWMSYNC = (1u << 3), /*!< Synchronization Mode: Selects which triggers can be used
by MOD, CV, OUTMASK, and FTU counter synchronization. */
FTU_SYNC_FLAG_REINIT = (1u << 4), /*!< FTU Counter re-initialization by Synchronization */
FTU_SYNC_FLAG_SYNCHOM = (1u << 5), /*!< Selects when the OUTMASK register is updated with the
value of its buffer */
FTU_SYNC_FLAG_SYNCEN01 = (1u << 6), /*!< synchronization of registers C(0)V and C(1)V. */
FTU_SYNC_FLAG_SYNCEN23 = (1u << 7), /*!< synchronization of registers C(2)V and C(3)V. */
FTU_SYNC_FLAG_SYNCEN45 = (1u << 8), /*!< synchronization of registers C(4)V and C(5)V. */
FTU_SYNC_FLAG_SYNCEN67 = (1u << 9), /*!< synchronization of registers C(6)V and C(7)V. */
FTU_SYNC_FLAG_HW_TRIG0 = (1u << 10), /*!< hardware trigger 0 to the synchronization */
FTU_SYNC_FLAG_HW_TRIG1 = (1u << 11), /*!< hardware trigger 1 to the synchronization */
FTU_SYNC_FLAG_HW_TRIG2 = (1u << 12), /*!< hardware trigger 2 to the synchronization */
} FTU_SyncFlagType;
/**
* @brief The interrupt enable/disable mask of FTU peripheral
*
*/
typedef enum
{
FTU_INTR_MASK_CHANNEL_0 = 1u, /*!< interrupt mask of channel 0 */
FTU_INTR_MASK_CHANNEL_1 = (1u << 1), /*!< interrupt mask of channel 1 */
FTU_INTR_MASK_CHANNEL_2 = (1u << 2), /*!< interrupt mask of channel 2 */
FTU_INTR_MASK_CHANNEL_3 = (1u << 3), /*!< interrupt mask of channel 3 */
FTU_INTR_MASK_CHANNEL_4 = (1u << 4), /*!< interrupt mask of channel 4 */
FTU_INTR_MASK_CHANNEL_5 = (1u << 5), /*!< interrupt mask of channel 5 */
FTU_INTR_MASK_CHANNEL_6 = (1u << 6), /*!< interrupt mask of channel 6 */
FTU_INTR_MASK_CHANNEL_7 = (1u << 7), /*!< interrupt mask of channel 7 */
FTU_INTR_MASK_OVERFLOW = (1u << 8), /*!< interrupt mask of overflow */
FTU_INTR_MASK_FAULT = (1u << 9), /*!< interrupt mask of fault */
FTU_INTR_MASK_RELOAD_POINT = (1u << 10), /*!< interrupt mask of reload point */
} FTU_IntrMaskType;
/**
* @brief The fault control enable/disable mask for channels
*
*/
typedef enum
{
FTU_FAULT_FOR_CHANNEL01 = 1u, /*!< fault control for channel 0 and channel 1 */
FTU_FAULT_FOR_CHANNEL23 = (1u << 1), /*!< fault control for channel 2 and channel 3 */
FTU_FAULT_FOR_CHANNEL45 = (1u << 2), /*!< fault control for channel 4 and channel 5 */
FTU_FAULT_FOR_CHANNEL67 = (1u << 3), /*!< fault control for channel 6 and channel 7 */
} FTU_FaultChannelEnableType;
/**
* @brief the fault input polarity
*
*/
typedef enum
{
FTU_FAULT_POL_ACTIVE_HIGH = 0u, /*!< The fault input polarity is active high.
1 at the fault input indicates a fault */
FTU_FAULT_POL_ACTIVE_LOW = 1u, /*!< The fault input polarity is active low.
0 at the fault input indicates a fault */
}FTU_FaultPolActiveType;
/**
* @brief the output trigger mask
*
*/
typedef enum
{
FTU_TRIG_OUTPUT_MASK_CHANNEL_0_MATCH = 1u, /*!< Enables/Disables the channel 0 match trigger */
FTU_TRIG_OUTPUT_MASK_CHANNEL_1_MATCH = (1u << 1), /*!< Enables/Disables the channel 1 match trigger */
FTU_TRIG_OUTPUT_MASK_CHANNEL_2_MATCH = (1u << 2), /*!< Enables/Disables the channel 2 match trigger */
FTU_TRIG_OUTPUT_MASK_CHANNEL_3_MATCH = (1u << 3), /*!< Enables/Disables the channel 3 match trigger */
FTU_TRIG_OUTPUT_MASK_CHANNEL_4_MATCH = (1u << 4), /*!< Enables/Disables the channel 4 match trigger */
FTU_TRIG_OUTPUT_MASK_CHANNEL_5_MATCH = (1u << 5), /*!< Enables/Disables the channel 5 match trigger */
FTU_TRIG_OUTPUT_MASK_CHANNEL_6_MATCH = (1u << 6), /*!< Enables/Disables the channel 6 match trigger */
FTU_TRIG_OUTPUT_MASK_CHANNEL_7_MATCH = (1u << 7), /*!< Enables/Disables the channel 7 match trigger */
FTU_TRIG_OUTPUT_MASK_ALL_CHANNEL_MATCH = (0xFFu), /*!< Enables/Disables all channel match trigger */
FTU_TRIG_OUTPUT_MASK_RELOAD = (1u << 8), /*!< Enables/Disables reload trigger */
}FTU_TriggerOutputMaskType;
/** @brief Ftu input capture mode */
typedef enum
{
FTU_INPUT_RISING_EDGE = 0U, /*!< capture on rising edge only */
FTU_INPUT_FALLING_EDGE, /*!< capture on falling edge only */
FTU_INPUT_BOTH_EDGE /*!< capture on rising or falling edge */
} FTU_InputCapturePinModeType;
/** @brief Ftu Global Time Base instance start mask */
typedef enum
{
FTU_GTB_INSTANCE_START_FTU0 = 1u, /*!< FTU0 GTB start */
FTU_GTB_INSTANCE_START_FTU1 = (1u << 1), /*!< FTU1 GTB start */
FTU_GTB_INSTANCE_START_FTU2 = (1u << 2), /*!< FTU2 GTB start */
FTU_GTB_INSTANCE_START_FTU3 = (1u << 3), /*!< FTU3 GTB start */
FTU_GTB_INSTANCE_START_FTU4 = (1u << 4), /*!< FTU4 GTB start */
FTU_GTB_INSTANCE_START_FTU5 = (1u << 5), /*!< FTU5 GTB start */
FTU_GTB_INSTANCE_START_FTU6 = (1u << 6), /*!< FTU6 GTB start */
FTU_GTB_INSTANCE_START_FTU7 = (1u << 7), /*!< FTU7 GTB start */
} FTU_GlobalTimeBaseStartInstanceType;
/** @brief Ftu Global Time Base start mask */
typedef enum
{
FTU_GTB_START_AT_ONCE = 1u, /*!< GTB start at once */
FTU_GTB_START_AT_TSTMP1_MOD0 = (1u << 1), /*!< GTB start at modulate timer 0 of TSTMP1 */
FTU_GTB_START_AT_TSTMP1_MOD1 = (1u << 2), /*!< GTB start at modulate timer 1 of TSTMP1 */
FTU_GTB_START_AT_TSTMP1_MOD2 = (1u << 3), /*!< GTB start at modulate timer 2 of TSTMP1 */
FTU_GTB_START_AT_TSTMP1_MOD3 = (1u << 4), /*!< GTB start at modulate timer 3 of TSTMP1 */
} FTU_GlobalTimeBaseStartType;
/** @brief FTU signal measurement mode type */
typedef enum
{
FTU_SIGNAL_MEASURE_HIGH_TIME = 0u, /*!< Measurement high time */
FTU_SIGNAL_MEASURE_LOW_TIME = 1u, /*!< Measurement low time */
FTU_SIGNAL_MEASURE_PERIOD_RISING_EDGE = 2u, /*!< Measurement period of rising edge */
FTU_SIGNAL_MEASURE_PERIOD_FALLING_EDGE = 3u /*!< Measurement period of falling edge */
} FTU_SignalMeasureModeType;
/** @brief FTU signal measurement configuration type */
typedef struct
{
uint8_t u8Channel; /*!< selected FTU channel */
FTU_SignalMeasureModeType eMeasureMode; /*!< signal measurement mode type */
FTU_MeasureContModeType eContinuouslyMode; /*!< The measurement is single or continuous */
FTU_MeasureStartModeType eStartMode; /*!< Timing of start measurement */
} FTU_SignalMeasureType;
/** @brief FTU signal measurement result time */
typedef struct
{
uint32_t u32StartTime; /*!< start time of measured signal */
uint32_t u32EndTime; /*!< end time of measured signal */
} FTU_SignalMeasureValueType;
/** @brief Expect edge number result time */
typedef struct
{
uint32_t u32FirstEdgeTime; /*!< first edge time of measured signal */
uint32_t u32LastEdgeTime; /*!< last edge time of measured signal */
} FTU_ExpectEdgeNumberResultType;
/** @brief FTU edge number measurement configuration type */
typedef struct
{
uint8_t u8Channel; /*!< selected FTU channel */
FTU_InputCapturePinModeType eEdgeMode; /*!< input capture mode */
FTU_MeasureContModeType eContinuouslyMode; /*!< The measurement is single or continuous */
uint32_t u32StartWindow; /*!< start-point window */
uint32_t u32EndWindow; /*!< end-point window */
} FTU_EdgeNumberMeasureType;
/** @brief FTU expect edge number measurement configuration type */
typedef struct
{
uint8_t u8Channel; /*!< selected FTU channel */
FTU_InputCapturePinModeType eEdgeMode; /*!< input capture mode */
uint8_t u8ExpectEdgeNumber; /*!< Expected number of edges */
FTU_MeasureContModeType eContinuouslyMode; /*!< The measurement is single or continuous */
} FTU_ExpectEdgeNumberMeasureType;
/**
* @brief The configuration option for the FTU interrupt
*
*/
typedef struct
{
uint32_t u32InterruptMask; /*!< interrupt enable mask */
FTU_ChannelCallBackType pChannelCallback; /*!< channel interrupt callback */
FTU_FaultCallBackType pFaultCallback; /*!< fault interrupt callback */
FTU_InterruptCallBackType pOverflowCallback; /*!< overflow interrupt callback */
FTU_InterruptCallBackType pReloadPointCallback; /*!< reload point interrupt callback */
} FTU_InterruptType;
/**
* @brief The configuration for the Pwm channel
*
*/
typedef struct
{
uint8_t u8Channel; /*!< selected FTU channel */
FTU_PwmPinModeType ePinMode; /*!< pwm mode */
uint32_t u32PwmDuty; /*!< pwm duty (timer ticks) */
uint32_t u32PhaseShift; /*!< pwm phase shift (timer ticks)*/
bool bLinkMode; /*!< pwm channel link mode enable, channel num must be even,and the linked channel is current_channel+1*/
bool bLinkChannelComplement; /*!< pwm link channel output complement */
bool bDeadtimeEnable; /*!< Deadtime Enable */
uint32_t u32ChannelDeadtime; /*!< The separated deadtime (source clock ticks) */
} FTU_PwmChannelType;
/**
* @brief The configuration option for the Pwm Mode
*
*/
typedef struct
{
uint32_t u32PwmPeriod; /*!< pwm period (timer ticks) */
uint32_t u32PublicDeadtime; /*!< pwm deadtime (source clock ticks) */
FTU_PwmAlignedType eAlignedMode; /*!< pwm Aligned Mode */
uint32_t u32ChannelCount; /*!< channel count of the Ftu instance */
FTU_PwmChannelType *pPwmChannels; /*!< point to the pwm channel */
} FTU_PwmModeType;
/**
* @brief The configuration option for the output compare mode
*
*/
typedef struct
{
uint8_t u8Channel; /*!< selected FTU channel */
FTU_OutputComparePinModeType eOutputMode; /*!< ouput compare mode */
uint32_t u32CompareValue; /*!< output compare value (timer ticks) */
FTU_OutputCompareInitLevelType eInitLevel; /*!< the initial level of the channel */
} FTU_OutputCompareModeType;
/**
* @brief The configuration option for the time counter mode
*
*/
typedef struct
{
uint32_t u32CounterValue; /*!< counter overflow value (timer ticks) */
uint32_t u32InitialValue; /*!< counter initial value (timer ticks) */
} FTU_CounterModeType;
/**
* @brief The basic configuration option for the FTU peripheral
*
*/
typedef struct
{
FTU_PrescalerType ePrescaler; /*!< Ftu prescaler */
FTU_ClkSrcType eClkSrc; /*!< Ftu clock source */
FTU_FilterPrescalerType eFliterPrescaler; /*!< Select the prescaler of the FTU filter */
uint32_t u32OverflowValue; /*!< Ftu modulo value */
uint16_t u16ReloadPoints; /*!< Ftu Synchronization points to update the buffered registers.Multiple
update modes can be used by providing an OR'ed list of options
available in enumeration ::FTU_ReloadPointCfgType. */
uint8_t u8ReloadFreq; /*!< Frequency of the Reload Opportunities. Range is 0-31, */
uint16_t u16SyncFlag; /*!< Ftu Synchronization flags to config the Synchronization and update of
the buffered registers. Multiple update modes can be used by
providing an OR'ed list of options available in
enumeration ::FTU_SyncFlagType. */
FTU_TrigModeType eHwTrigMode; /*!< hardware trigger mode */
FTU_DebugModeType eDbgMode; /*!< Ftu debug mode */
FTU_UpDownDisableType eUpDownDisable; /*!< Disable channel match trigger/interrupt when count-up/down in CPWM/QUAD mode */
bool bGtbEnable; /*!< Global Time Base Enable */
} FTU_CommonType;
/**
* @brief The configuration option for initializing FTU fault
*
*/
typedef struct
{
FTU_FaultModeType eFaultMode; /*!< fault control mode */
uint8_t u8FilterValue; /*!< selects the filter value for the fault inputs */
uint8_t u8FaultChannelEnable; /*!< fault control for channel */
uint8_t u8FaultDisableDelay0; /*!< Fault Disable Channel Output Delay Value 0 (timer ticks) */
uint8_t u8FaultDisableDelay1; /*!< Fault Disable Channel Output Delay Value 1 (timer ticks) */
} FTU_FaultInitType;
/**
* @brief The configuration option for enabling a FTU fault
*
*/
typedef struct
{
uint8_t u8FaultIndex; /*!< fault index */
FTU_FaultPolActiveType eFaultPol; /*!< the fault input active polarity */
bool bFaultFilterEnable; /*!< whether to enable fault input glitch filter*/
} FTU_FaultControlType;
/**
* @brief The configuration option for a input capture channel
*
*/
typedef struct
{
uint8_t u8Channel; /*!< selected FTU channel */
FTU_InputCapturePinModeType eInputMode; /*!< input capture mode */
uint8_t u8FilterValue; /*!< selects the filter value for the channel input */
} FTU_InputChannelType;
/**
* @brief The configuration option for the quadrature decoder mode
*
*/
typedef struct
{
FTU_QuadratureModeType eQuadMode; /*!< selects the encoding mode used in the Quadrature Decoder mode */
FTU_QuadratureDirectionType eQuadDirection; /*!< indicates the counting direction */
FTU_TimerOverflowDirectionType eOveflowDirection; /*!< Indicates if the TOF bit was set on the top or the bottom of counting */
uint8_t u8PhaFilterVal; /*!< The filter value for the phase A input */
uint8_t u8PhbFilterVal; /*!< The filter value for the phase B input */
bool bPhaInverted; /*!< whether to inverted polarity of phase A input */
bool bPhbInverted; /*!< whether to inverted polarity of phase B input */
uint16_t u16TopValue; /*!< the top value of counting */
uint16_t u16BottomValue; /*!< the bottom value of counting */
} FTU_QuadratureInitType;
/**
* @brief Initialize FTU basic configuration
*
* @param eInstance the selected FTU instance
* @param pCommonStruct the basic configurations of the FTU instance
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_CommonInit(const FTU_InstanceType eInstance, const FTU_CommonType *const pCommonStruct);
/**
* @brief Fills in the FTU configuration structure with the default settings.
*
* @param pCommonStruct Pointer to the user configuration structure
*/
void FTU_GetDefaultInitCfg(FTU_CommonType *pCommonStruct);
/**
* @brief Configure FTU to counter mode
*
* @param eInstance the selected FTU instance
* @param pCounterStruct the configurations of the counter mode
* @return FTU_StatusType whether the operation is successfully
* @note This function will stop timer
*/
FTU_StatusType FTU_CounterModeInit(const FTU_InstanceType eInstance,
const FTU_CounterModeType *const pCounterStruct);
/**
* @brief Configure FTU to output compare mode
*
* @param eInstance the selected FTU instance
* @param pOutputModeStruct the configurations of the output compare mode
* @return FTU_StatusType whether the operation is successfully
* @note This function will stop timer
*/
FTU_StatusType FTU_OutputCompareModeInit(const FTU_InstanceType eInstance,
const FTU_OutputCompareModeType *const pOutputModeStruct);
/**
* @brief Configure Configure FTU to PWM mode
*
* @param eInstance the selected FTU instance
* @param pPwmModeStruct the configurations of the PWM mode
* @return FTU_StatusType whether the operation is successfully
* @note This function will stop timer
*/
FTU_StatusType FTU_PwmModeInit(const FTU_InstanceType eInstance, const FTU_PwmModeType *const pPwmModeStruct);
/**
* @brief Update the duty cycle of the FTU instance
*
* @param eInstance the selected FTU instance
* @param u8Channel the selected FTU channel
* @param u32Duty duty cycle of the PWM mode
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_PwmUpdateDuty(const FTU_InstanceType eInstance, uint8_t u8Channel, uint32_t u32Duty);
/**
* @brief Ftu initialize interrupt function
*
* @param eInstance the selected FTU instance
* @param pIntStruct the configurations of the interrupt
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_InterruptInit(const FTU_InstanceType eInstance, const FTU_InterruptType *const pIntStruct);
/**
* @brief Enable FTU interrupt
*
* @param eInstance the selected FTU instance
* @param u32InterruptMask interrupt enable mask
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_EnableInterrupt(const FTU_InstanceType eInstance, uint32_t u32InterruptMask);
/**
* @brief Enable FTU interrupt
*
* @param eInstance the selected FTU instance
* @param u32InterruptMask interrupt disable mask
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_DisableInterrupt(const FTU_InstanceType eInstance, uint32_t u32InterruptMask);
/**
* @brief Start the FTU instance
*
* @param eInstance the selected FTU instance
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_StartTimer(const FTU_InstanceType eInstance);
/**
* @brief Stop the FTU global time base
*
* @param u32InstanceMask The selected FTU, each bit represents an instance
*/
void FTU_StopGlobalTimeBase(uint32_t u32InstanceMask);
/**
* @brief Start the FTU global time base
*
* @param u32InstanceMask The selected FTU, each bit represents an instance
* @param u32StartMask Start time, refer to FTU_GlobalTimeBaseStartType
*/
void FTU_StartGlobalTimeBase(uint32_t u32InstanceMask, uint32_t u32StartMask);
/**
* @brief Stop the FTU instance
*
* @param eInstance the selected FTU instance
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_StopTimer(const FTU_InstanceType eInstance);
/**
* @brief De-initialize the FTU instance
*
* @param eInstance the selected FTU instance
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_DeInit(const FTU_InstanceType eInstance);
/**
* @brief initialize fault input of the selected Ftu instance
*
* @param eInstance the selected FTU instance
* @param pFaultInit the fault configurations of the FTU instance
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_FaultInit(const FTU_InstanceType eInstance, const FTU_FaultInitType *const pFaultInit);
/**
* @brief Enable a fault input
*
* @param eInstance the selected FTU instance
* @param pFaultCtrl configurations of the fault input
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_FaultEnable(const FTU_InstanceType eInstance, const FTU_FaultControlType *const pFaultCtrl);
/**
* @brief Select fault disable channel output delay value
*
* @param eInstance the selected FTU instance
* @param u8Channel FTU channel number, range is 0-7.
* @param eDelaySelection Fault disable channel output delay value selection.
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_FaultSelectDelayValue(const FTU_InstanceType eInstance, uint8_t u8Channel, FTU_FaultDisableDelayType eDelaySelection);
/**
* @brief Get Edge number counter
*
* @param eInstance the selected FTU instance
* @param u8Channel FTU channel number.
* @return uint8_t Edge number counter
*/
uint8_t FTU_GetEdgeNumberCount(const FTU_InstanceType eInstance, uint8_t u8Channel);
/**
* @brief Initialize a Edge Number Measurement channel
*
* @param eInstance the selected FTU instance
* @param pEdgeNumMeasure measurement configuration.
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_EdgeNumberMeasureChannelInit(const FTU_InstanceType eInstance, FTU_EdgeNumberMeasureType *pEdgeNumMeasure);
/**
* @brief Initialize a signal measure channel
*
* @param eInstance the selected FTU instance
* @param pMeasure measurement configuration.
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_SignalMeasureChannelInit(const FTU_InstanceType eInstance, FTU_SignalMeasureType *pMeasure);
/**
* @brief Re-start measurement when in single mode
*
* @param eInstance the selected FTU instance
* @param u8Channel FTU channel number, range is 0-7.
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_SignalMeasureChannelSingle(const FTU_InstanceType eInstance, uint8_t u8Channel);
/**
* @brief Get the measurement result of the channel
*
* @param eInstance the selected FTU instance
* @param u8Channel FTU channel number, range is 0-7.
* @param pResult point to the result buffer.
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_GetSignaMeasureResult(const FTU_InstanceType eInstance, uint8_t u8Channel, FTU_SignalMeasureValueType *pResult);
/**
* @brief Disable a fault input
*
* @param eInstance the selected FTU instance
* @param u32FaultIndex index of the fault input
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_FaultDisable(const FTU_InstanceType eInstance, uint32_t u32FaultIndex);
/**
* @brief Clear the fault flag of the FTU instance
*
* @param eInstance the selected FTU instance
* @param u32FaultFlag flag to clear
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_ClearFault(const FTU_InstanceType eInstance, uint32_t u32FaultFlag);
/**
* @brief Get the fault flag of the FTU instance
*
* @param eInstance the selected FTU instance
* @return uint32_t the fault flag of the selected Ftu instance
*/
uint32_t FTU_GetFaultFlag(const FTU_InstanceType eInstance);
/**
* @brief initialize a input capture channel of the selected Ftu instance
*
* @param eInstance the selected FTU instance
* @param pInputChannel configurations of the input capture channel
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_InputCaptureChannelInit(const FTU_InstanceType eInstance,
const FTU_InputChannelType *const pInputChannel);
/**
* @brief enable the synchronization of the selected FTU
*
* @param eInstance the selected FTU instance
* @param u16ReloadPoints The synchronization flag
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_EnableSync(const FTU_InstanceType eInstance, uint16_t u16SyncFlag);
/**
* @brief disable the synchronization of the selected FTU
*
* @param eInstance the selected FTU instance
* @param u16SyncFlag The synchronization flag
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_DisableSync(const FTU_InstanceType eInstance, uint16_t u16SyncFlag);
/**
* @brief Enable the output trigger of the selected FTU instance
*
* @param eInstance the selected FTU instance
* @param u32TriggerOutputMask the output trigger mask
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_EnableTriggerOutput(const FTU_InstanceType eInstance, uint32_t u32TriggerOutputMask);
/**
* @brief Disable the output trigger of the selected FTU instance
*
* @param eInstance the selected FTU instance
* @param u32TriggerOutputMask the output trigger mask
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_DisableTriggerOutput(const FTU_InstanceType eInstance, uint32_t u32TriggerOutputMask);
/**
* @brief initialize the quadrature decoder mode
*
* @param eInstance the selected FTU instance
* @param pQuadInit configurations of the quadrature decoder
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_QuadratureModeInit(const FTU_InstanceType eInstance,
const FTU_QuadratureInitType *const pQuadInit);
/**
* @brief Enable the reload points of the selected FTU instance
*
* @param eInstance the selected FTU instance
* @param u16ReloadPoints The reload points flag
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_EnableReloadPoints(const FTU_InstanceType eInstance, uint16_t u16ReloadPoints);
/**
* @brief Disable the reload points of the selected FTU instance
*
* @param eInstance the selected FTU instance
* @param u16ReloadPoints The reload points flag
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_DisableReloadPoints(const FTU_InstanceType eInstance, uint16_t u16ReloadPoints);
/**
* @brief Enable ftu channel DMA
*
* @param eInstance the selected FTU instance
* @param u32DmaMask The dma channel mask.
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_EnableChannelDma(const FTU_InstanceType eInstance, uint32_t u32DmaMask);
/**
* @brief Get the expect edge number result of the channel
*
* @param eInstance the selected FTU instance
* @param u8Channel FTU channel number, range is 0-7.
* @param pResult point to the result buffer.
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_GetExpectEdgeNumberResult(const FTU_InstanceType eInstance, uint8_t u8Channel, FTU_ExpectEdgeNumberResultType *pResult);
/**
* @brief Initialize a Expect Edge Number Measurement channel
*
* @param eInstance the selected FTU instance
* @param pExpectEdgeNumMeasure measurement configuration.
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_ExpectEdgeNumberMeasureChannelInit(const FTU_InstanceType eInstance, FTU_ExpectEdgeNumberMeasureType *pExpectEdgeNumMeasure);
/**
* @brief Get the measurement result of the channel
*
* @param eInstance the selected FTU instance
* @param u8Channel FTU channel number, range is 0-7.
* @param pResult point to the result buffer.
* @return FTU_StatusType whether the operation is successfully
*/
FTU_StatusType FTU_GetSignalMeasureResult(const FTU_InstanceType eInstance, uint8_t u8Channel, FTU_SignalMeasureValueType *pResult);
/**
* @brief Interrupt IRQ handle of FTU instance
*
* @param eInstance the selected FTU instance
*/
void FTUn_IRQHandler(const FTU_InstanceType eInstance);
/** @}*/ /* fc7xxx_driver_ftu */
#if defined(__cplusplus)
}
#endif
#endif

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/**
* @file fc7xxx_driver_gpio.h
* @author Flagchip
* @brief FC7xxx GPIO driver type definition and API
* @version 0.1.0
* @date 2023-2-14
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022/12/31 Flagchip071 N/A First version for FC7240
********************************************************************************/
#ifndef DRIVER_GPIO_H_
#define DRIVER_GPIO_H_
#include "HwA_gpio.h"
/**
* @addtogroup fc7xxx_driver_port
* @{
*/
/********* global define ************/
#define GPIO_MAX_PORT_PINS 32
#define GPIO_PIN_0 ((uint32_t)0x00000001) /**< GPIO Pin 0 select */
#define GPIO_PIN_1 ((uint32_t)0x00000002) /**< GPIO Pin 1 select */
#define GPIO_PIN_2 ((uint32_t)0x00000004) /**< GPIO Pin 2 select */
#define GPIO_PIN_3 ((uint32_t)0x00000008) /**< GPIO Pin 3 select */
#define GPIO_PIN_4 ((uint32_t)0x00000010) /**< GPIO Pin 4 select */
#define GPIO_PIN_5 ((uint32_t)0x00000020) /**< GPIO Pin 5 select */
#define GPIO_PIN_6 ((uint32_t)0x00000040) /**< GPIO Pin 6 select */
#define GPIO_PIN_7 ((uint32_t)0x00000080) /**< GPIO Pin 7 select */
#define GPIO_PIN_8 ((uint32_t)0x00000100) /**< GPIO Pin 8 select */
#define GPIO_PIN_9 ((uint32_t)0x00000200) /**< GPIO Pin 9 select */
#define GPIO_PIN_10 ((uint32_t)0x00000400) /**< GPIO Pin 10 select */
#define GPIO_PIN_11 ((uint32_t)0x00000800) /**< GPIO Pin 11 select */
#define GPIO_PIN_12 ((uint32_t)0x00001000) /**< GPIO Pin 12 select */
#define GPIO_PIN_13 ((uint32_t)0x00002000) /**< GPIO Pin 13 select */
#define GPIO_PIN_14 ((uint32_t)0x00004000) /**< GPIO Pin 14 select */
#define GPIO_PIN_15 ((uint32_t)0x00008000) /**< GPIO Pin 15 select */
#define GPIO_PIN_16 ((uint32_t)0x00010000) /**< GPIO Pin 16 select */
#define GPIO_PIN_17 ((uint32_t)0x00020000) /**< GPIO Pin 17 select */
#define GPIO_PIN_18 ((uint32_t)0x00040000) /**< GPIO Pin 18 select */
#define GPIO_PIN_19 ((uint32_t)0x00080000) /**< GPIO Pin 19 select */
#define GPIO_PIN_20 ((uint32_t)0x00100000) /**< GPIO Pin 20 select */
#define GPIO_PIN_21 ((uint32_t)0x00200000) /**< GPIO Pin 21 select */
#define GPIO_PIN_22 ((uint32_t)0x00400000) /**< GPIO Pin 22 select */
#define GPIO_PIN_23 ((uint32_t)0x00800000) /**< GPIO Pin 23 select */
#define GPIO_PIN_24 ((uint32_t)0x01000000) /**< GPIO Pin 24 select */
#define GPIO_PIN_25 ((uint32_t)0x02000000) /**< GPIO Pin 25 select */
#define GPIO_PIN_26 ((uint32_t)0x04000000) /**< GPIO Pin 26 select */
#define GPIO_PIN_27 ((uint32_t)0x08000000) /**< GPIO Pin 27 select */
#define GPIO_PIN_28 ((uint32_t)0x10000000) /**< GPIO Pin 28 select */
#define GPIO_PIN_29 ((uint32_t)0x20000000) /**< GPIO Pin 29 select */
#define GPIO_PIN_30 ((uint32_t)0x40000000) /**< GPIO Pin 30 select */
#define GPIO_PIN_31 ((uint32_t)0x80000000) /**< GPIO Pin 31 select */
/************************************global typedef ***************************************/
/** @brief GPIO return structure */
typedef enum
{
GPIO_STATUS_SUCCESS = 0U,
GPIO_STATUS_PARAM_INVALID = 1U
} GPIO_StatusType;
/** @brief GPIO instance number */
typedef enum
{
GPIO_A = 0U,
GPIO_B,
GPIO_C,
GPIO_D,
GPIO_E
} GPIO_InstanceType;
/** @brief GPIO direction */
typedef enum
{
GPIO_OUT = 0U, /* GPIO pin directon is output */
GPIO_IN = 1U, /* GPIO pin directon is input */
GPIO_ZERO = 2U /* GPIO pin directon is input disable */
} GPIO_PinDirectionType;
typedef struct
{
uint32_t u32GpioPins;
GPIO_PinDirectionType ePinDirection;
GPIO_PinLevelType ePinLevel;
}GPIO_InitType;
/************************************global typedef ***************************************/
/**
* @brief Initialize GPIO.
*
* @param eGpio GPIO instance
* @param pInitStruct Initialization structure of GPIO.
*/
GPIO_StatusType GPIO_InitPins(const GPIO_InstanceType eGpio, const GPIO_InitType *const pInitStruct);
/**
* @brief Initialize GPIO.
*
* @param eGpio GPIO instance
* @param u32Pins The bit of u32Pins indicate the pin number of this GPIO.
*/
GPIO_StatusType GPIO_Deinit(const GPIO_InstanceType eGpio, const uint32_t u32Pins);
/**
* @brief Read level of input port pins.
*
* @param ePort Port instance for GPIO functionality
* @param u32Pins The bit of u32Pins indicate the pin number of this Port.
* @return Pins level
*/
uint32_t GPIO_ReadPins(const GPIO_InstanceType ePort, const uint32_t u32Pins);
/**
* @brief Write gpio level to u32Pins.
*
* @param ePort Port instance for GPIO functionality
* @param u32Pins The bit of u32Pins indicate the pin number of this Port.
* @param eOutput Output level enumeration
* @return Port return type.
*/
GPIO_StatusType GPIO_WritePins(const GPIO_InstanceType ePort, const uint32_t u32Pins, const GPIO_PinLevelType eOutput);
/**
* @brief Toggle gpio api
*
* @param ePort ePort Port instance for GPIO functionality
* @param u32Pins The bit of u32Pins indicate the pin number of this Port.
* @return Port return type.
*/
GPIO_StatusType GPIO_Toggle(const GPIO_InstanceType ePort, const uint32_t u32Pins);
#endif /* end of DRIVER_GPIO_H_ */

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/**
* @file fc7xxx_driver_intm.h
* @author Flagchip
* @brief FC7240 INTM driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version
******************************************************************************** */
#ifndef _DRIVER_INTM_H_
#define _DRIVER_INTM_H_
#include "HwA_intm.h"
typedef enum
{
INTM_INSTANCE_0 = 0U,
INTM_INSTANCE_MAX = 1u
} INTM_InstanceType;
typedef enum
{
INTM_IRQ_MONITOR_0 = 0U,
INTM_IRQ_MONITOR_1 = 1U,
INTM_IRQ_MONITOR_MAX = 2U
} INTM_IrqMonitorType;
typedef enum
{
INTM_RETURN_OK = 0x00U, /*!< The INTM operation is succeeded */
INTM_RETURN_E_NOT_OK = 0x01U, /*!< The INTM operation is failed */
INTM_RETURN_E_ALREADY_INIT = 0x02U, /*!< The INTM has been initialized. */
INTM_RETURN_E_UNINIT = 0x03U, /*!< The INTM is not initialized */
INTM_RETURN_E_PARAM = 0x04U /*!< The INTM parameter is incorrect or out of range. */
} INTM_ReturnType;
typedef enum
{
INTM_INTERRUPT_MODE_ACTIVE = 0x00U, /*!< INTM is configured as active mode */
INTM_INTERRUPT_MODE_INACTIVE /*!< INTM is configured as inactive mode */
} INTM_InterruptModeType;
/**
* @brief INTM Channel ISR callback function prototype
*
*/
typedef void (*INTM_ISRCallbackType)(void);
typedef struct
{
INTM_InterruptModeType eMode; /*!< INTM active mode */
bool bEnReset; /*!< Enable Reset */
bool bEnInterrupt; /*!< Enable Interrupt */
uint32_t u32SrcDelayCnt; /*!< Enable Interrupt */
uint16_t u16IrqNumber; /*!< Monitored interrupt number */
INTM_ISRCallbackType pIntmIsrCallback; /*!< INTM interrupt callback. */
} INTM_InitType;
/**
* @brief Init the INTM.
* @param eInstance INTM instance.
* @param eIrqMonitorIndex Monitor index.
* @param pInitCfg Init Configuration.
* @return INTM_ReturnType INTM Status.
*/
INTM_ReturnType INTM_Init(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex, INTM_InitType *pInitCfg);
/**
* @brief Enable INTM.
*
* @param eInstance INTM instance.
* @param bEnable Enable INTM.
* @return INTM_ReturnType INTM Status.
*/
INTM_ReturnType INTM_enable(INTM_InstanceType eInstance, bool bEnable);
/**
* @brief Start INTM inactive mode.
* @param eInstance INTM instance.
* @param eIrqMonitorIndex Monitor index.
* @return INTM_ReturnType INTM Status.
*/
INTM_ReturnType INTM_StartInactiveMode(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex);
/**
* @brief
* @param eInstance INTM instance.
* @param eIrqMonitorIndex Monitor index.
* @return INTM_ReturnType INTM Status.
*/
INTM_ReturnType INTM_StopInactiveMode(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex);
/**
* @brief Write the interrupt acknowledge.
*
* @param eInstance INTM instance.
* @param u16IrqNumber Interrupt nunmber.
* @return INTM_ReturnType INTM Status.
*/
INTM_ReturnType INTM_SetAcknowledge(INTM_InstanceType eInstance, uint16_t u16IrqNumber);
/**
* @brief Return counter value.
*
* @param eInstance INTM instance.
* @param eIrqMonitorIndex Monitor index.
* @return Counter value.
*/
uint32_t INTM_GetCounterValue(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex);
/**
* @brief Clear the interrupt flag.
*
* @param eInstance INTM instance.
* @param eIrqMonitorIndex Monitor index.
*/
INTM_ReturnType INTM_ClearIntFlag(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex);
/**
* @brief Get the timeout flag. Return true if INTM_TMR value has exceeded the INTM_LATR value.
*
* @param eInstance INTM instance.
* @param eIrqMonitorIndex Monitor index.
* @return Timeout flag.
*/
bool INTM_GetTimeoutStatus(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex);
#endif /* end of _DRIVER_INTM_H_ */

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/**
* @file fc7xxx_driver_ism.h
* @author Flagchip084
* @brief FC7xxx ISM driver type definition and API
* @version 0.2.0
* @date 2023-02-13
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022-11-18 Flagchip084 N/A First version for FC7xxx
* 0.2.0 2023-02-13 Flagchip084 N/A FC7xxx release version
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_ISM_H_
#define _DRIVER_FC7XXX_DRIVER_ISM_H_
#include "device_header.h"
#include "HwA_ism.h"
/**
* @addtogroup fc7xxx_driver_ism
* @{
*/
#define ISM_ECM_CHANNEL(x) (1<<(x))
#define ISM_LAM_CHANNEL(x) (1<<(x))
#define ISM_FPC_CHANNEL(x) (1<<(x))
typedef enum
{
ISM_INSTANCE_0 = 0U, /*!< ISM instance 0 is selected. */
} ISM_InstanceType;
typedef enum
{
FPC_RISING_GLITCH_DETECTED = 0x01U, /*!< PFC Rising Glitch Detected. */
FPC_FALLING_GLITCH_DETECTED = 0x02U /*!< PFC Falling Glitch Detected. */
} FPC_GlitchDetectType;
/**
* @brief ISM Channel ISR callback function prototype
*
*/
typedef void (*ISM_EventISRCallbackType)(const uint16_t u16LamStatus, const uint8_t u8EcmStatus);
/**
* @brief FPC Channel Glitch dectection ISR callback function prototype
*
*/
typedef void (*FPC_ISRCallbackType)(const uint32_t u32Status);
/**
* @brief LAM Channel Overflow ISR callback function prototype
*
*/
typedef void (*LAM_ISRCallbackType)(void);
typedef struct
{
bool bIntEnable;
ISM_EventISRCallbackType pEventIsrCallback;
} ISM_InitCfgType;
typedef struct
{
bool bGlitchIntEnable;
ISM_FPC_EdgeDetectModeType eFallingDetectMode;
ISM_FPC_EdgeDelayModeType eFallingDelayNode;
ISM_FPC_EdgeDetectModeType eRisingDetectMode;
ISM_FPC_EdgeDelayModeType eRisingDelayNode;
uint16_t u32ThresholdValue;
FPC_ISRCallbackType pFpcIsrCallback;
} ISM_FpcCfgType;
typedef struct
{
bool bOvflIntEnable;
uint8_t u8SrcSel;
uint8_t u8MonSel;
ISM_LAM_InvertEventWindowType eInvWin;
ISM_LAM_EventWindowEdgeType eWinEdgSel;
ISM_LAM_EventWindowSelectType eEvtWinSel;
ISM_LAM_RunModeSelectType eRunMode;
ISM_LAM_MonitorSourceType eMonSrcSel;
ISM_LAM_InvertMonitorType eInvMon;
ISM_LAM_InvertReferenceType eInvRef;
uint32_t u32EvtCntThreshold;
LAM_ISRCallbackType pLamOverFlowIsrCallback;
} ISM_LamCfgType;
/**
* @brief Init the ISM.
*
* @param pInitConfig ISMInstance initial configuration.
*/
void ISM_Init(const ISM_InitCfgType *pInitConfig);
/**
* @brief Get the channels mask of ECM that has event happened.
*
* @return Channels mask.
*/
uint8_t ISM_GetEcmEventHappenedChannels(void);
/**
* @brief Get the channels mask of LAM that has event happened.
*
* @return Channels mask.
*/
uint16_t ISM_GetLamEventHappenedChannels(void);
/**
* @brief Clear the channels status of ECM that has event happened.
*
* @param u8Channels Channels mask.
*/
void ISM_ClearEcmEventHappenedChannels(uint8_t u8Channels);
/**
* @brief Clear the channels status of LAM that has event happened.
*
* @param u16Channels Channels mask.
*/
void ISM_ClearLamEventHappenedChannels(uint16_t u16Channels);
/**
* @brief Enable or disable ISM.
*
* @param bEnable Enable value.
*/
void ISM_Enable(bool bEnable);
/**
* @brief Enable or disable ISM interrupt.
*
* @param bEnable Enable value.
*/
void ISM_InterruptEnable(bool bEnable);
/**
* @brief ENable LAM overflow interrupt.
*
* @param u8LamIndex LAM index.
* @param bEnable Enable value.
*/
void ISM_LamOverflowInterruptEnable(uint8_t u8LamIndex, bool bEnable);
/**
* @brief Enable LAM Channel.
*
* @param u8LamIndex LAM index.
* @param bEnable Enable value.
*/
void ISM_LamEnable(uint8_t u8LamIndex, bool bEnable);
/**
* @brief Config the LAM channel.
*
* @param u8LamIndex LAM index.
* @param pConfig LAM configuration.
*/
void ISM_LamConfig(uint8_t u8LamIndex, const ISM_LamCfgType *pConfig);
/**
* @brief Enable FPC glitch interrupt.
*
* @param u8FpcIndex FPC index.
* @param bEnable Enable value.
*/
void ISM_FpcGlitchInterruptEnable(uint8_t u8FpcIndex, bool bEnable);
/**
* @brief Enable FPC channel.
*
* @param u8FpcIndex FPC index.
* @param bEnable Enable value.
*/
void ISM_FpcEnable(uint8_t u8FpcIndex, bool bEnable);
/**
* @brief Config the FPC channel.
*
* @param u8FpcIndex FPC index.
* @param pConfig FPC configuration.
*/
void ISM_FpcConfig(uint8_t u8FpcIndex, const ISM_FpcCfgType *pConfig);
/**
* @brief Enable ECM system event
*
* @param u32Channels Channel masks.
* @param bEnable Enable value.
*/
void ISM_EnableEcmSystemEvent(uint32_t u32Channels, bool bEnable);
/**
* @brief Enable LAM system event
*
* @param u32Channels Channel masks.
* @param bEnable Enable value.
*/
void ISM_EnableLamSystemEvent(uint32_t u32Channels, bool bEnable);
/**
* @brief Enable LAM system event
*
* @param u32LamIndex Lam channel index.
* @param u32EcmIndex Ecm channel index.
* @param u8EventCount Threshold of the ECM channel counter value.
*/
void ISM_EcmEventConfig(uint8_t u32LamIndex, uint8_t u32EcmIndex, uint8_t u8EventCount);
/**
* @brief Clears the value of the LAM counter.
*
* @param u32LamIndex Lam channel index.
*/
void ISM_ClearLamStatusCounter(uint8_t u8LamIndex);
/**
* @brief Gets the value of the LAM counter when a LAM event is triggered.
*
* @param u32LamIndex Lam channel index.
* @return Counter value.
*/
uint32_t ISM_GetLamStatusCounter(uint8_t u8LamIndex);
/**
* @brief Clears LAM Timer Overflow Flag.
*
* @param u32LamIndex Lam channel index.
*/
void ISM_ClearLamStatusOvfl(uint8_t u8LamIndex);
/**
* @brief Gets LAM Timer Overflow Flag.
*
* @param u32LamIndex Lam channel index.
* @return Overflow flag.
*/
bool ISM_GetLamStatusOvfl(uint8_t u8LamIndex);
/** @}*/ /* fc7xxx_driver_ism. */
#endif

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/**
* @file fc7xxx_driver_lin.h
* @author Flagchip0122
* @brief FC7xxx LIN driver type definition and API
* @version 0.1.0
* @date 2023-12-26
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-26 Flagchip0122 N/A First version for FC7xxx
******************************************************************************** */
#ifndef _DRIVER_FC4XXX_DRIVER_LIN_H_
#define _DRIVER_FC4XXX_DRIVER_LIN_H_
#include "HwA_fcuart.h"
#include "device_header.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc4xxx_driver_lin
* @{
*/
/**
* @brief LIN status type use in API.
*/
typedef enum
{
LIN_STATUS_SUCCESS = 0x00U, /*!< API execute successfully */
LIN_STATUS_ERROR, /*!< API excute error */
LIN_STATUS_BUSY, /*!< currently instance busy. */
LIN_STATUS_TIMEOUT, /*!< timeout status */
LIN_STATUS_PARAM_ERROR, /*!< Parameter error. */
LIN_STATUS_NOT_INIT, /*!< LIN node has not been initialized. */
LIN_STATUS_USEED, /*!< LIN node has not been initialized. */
LIN_STATUS_NOT_START, /*!< LIN node has not been started. */
LIN_STATUS_UNSUPPORTED, /*!< unsupport status */
} LIN_StatusType;
/**
* @brief LIN node type use in API, master or slave.
*/
typedef enum
{
LIN_NODE_MASTER, /*!< LIN Master node. */
LIN_NODE_SLAVE, /*!< LIN slave node. */
} LIN_NodeType;
/**
* @brief A callback function to get the interval time value in nanoseconds.
*/
typedef uint32_t (*lin_get_interval_time_t)(uint32_t *nanoSeconds);
/**
* @brief Structure for LIN hardware configurations.
*/
typedef struct
{
LIN_NodeType nodeMode; /*!< Node mode as Master node or Slave node. 0: slave 1: master */
uint32_t baudRate; /*!< baudrate configurations for LIN protocol. */
uint32_t clockSrcFreq; /*!< LIN instance clock source frequency. */
lin_get_interval_time_t getIntervalTimeValueCallback; /*!< Callback function to get time interval in nanoseconds */
uint8_t *classicPID; /*!< List of PIDs use classic checksum */
uint8_t numOfClassicPID; /*!< Number of PIDs use classic checksum */
} lin_config_t;
/**
* @brief Types for an event related Identifier.
*/
typedef enum
{
LIN_NO_EVENT = 0x00U, /*!< No event occurred. */
LIN_WAKEUP_SIGNAL, /*!< Wakeup signal */
LIN_BAUDRATE_ADJUSTED, /*!< Baudrate was adjusted in slave autobaud mode. */
LIN_RECV_BREAK_FIELD_OK, /*!< Break Field was received */
LIN_SYNC_OK, /*!< Sync field is correct */
LIN_SYNC_ERROR, /*!< Sync field is incorrect */
LIN_PID_OK, /*!< PID receive correct */
LIN_PID_ERROR, /*!< PID receive incorrect */
LIN_FRAME_ERROR, /*!< Frame receive error */
LIN_READBACK_ERROR, /*!< Readback words are incorrect */
LIN_CHECKSUM_ERROR, /*!< Checksum byte error */
LIN_TX_COMPLETED, /*!< TX data completed */
LIN_RX_COMPLETED, /*!< rx data completed */
LIN_RX_OVERRUN, /*!< RX overflow occurred */
LIN_TIMEOUT, /*!< RX overflow occurred */
} lin_event_id_t;
/*!
* @brief Define type for an enumerating LIN Node state.
*/
typedef enum
{
LIN_NODE_STATE_UNINIT = 0x00U, /*!< LIN hardware uninitialized state */
LIN_NODE_STATE_SLEEP_MODE, /*!< LIN node in sleep mode state */
LIN_NODE_STATE_IDLE, /*!< LIN node in idle state */
LIN_NODE_STATE_SEND_BREAK_FIELD, /*!< LIN node in send break field state */
LIN_NODE_STATE_RECV_SYNC, /*!< LIN node in receive the synchronization byte state */
LIN_NODE_STATE_SEND_PID, /*!< LIN node in rend PID state */
LIN_NODE_STATE_RECV_PID, /*!< LIN node in receive PID state */
LIN_NODE_STATE_RECV_DATA, /*!< LIN node in receive data state */
LIN_NODE_STATE_RECV_DATA_COMPLETED, /*!< LIN node in receive data completed state */
LIN_NODE_STATE_SEND_DATA, /*!< LIN node in send data state */
LIN_NODE_STATE_SEND_DATA_COMPLETED /*!< LIN node in send data completed state */
} lin_node_state_t;
/*!
* @brief LIN Driver callback function type
*/
typedef void (*lin_callback_t)(uint8_t u8LinIndex, void *linState);
/*!
* @brief Runtime state of the LIN driver.
*
* Note that the caller provides memory for the driver state structures during
* initialization because the driver does not statically allocate memory.
* Implements : lin_state_t_Class
*/
typedef struct
{
const uint8_t *txBuff; /*!< The buffer of data being sent. */
uint8_t *rxBuff; /*!< The buffer of received data. */
uint8_t cntByte; /*!< To count number of bytes already transmitted or received. */
volatile uint8_t txSize; /*!< The remaining number of bytes to be transmitted. */
volatile uint8_t rxSize; /*!< The remaining number of bytes to be received. */
uint8_t checkSum; /*!< Checksum byte. */
volatile bool isTxBusy; /*!< True if the LIN interface is transmitting frame data. */
volatile bool isRxBusy; /*!< True if the LIN interface is receiving frame data. */
volatile bool isBusBusy; /*!< True if there are data, frame headers being transferred on bus */
volatile bool isTxBlocking; /*!< True if transmit is blocking transaction. */
volatile bool isRxBlocking; /*!< True if receive is blocking transaction. */
lin_callback_t Callback; /*!< Callback function to invoke after receiving a byte or transmitting a byte. */
uint8_t currentId; /*!< Current ID */
uint8_t currentPid; /*!< Current PID */
volatile lin_event_id_t currentEventId; /*!< Current ID Event */
volatile lin_node_state_t currentNodeState; /*!< Current Node state */
volatile uint32_t timeoutCounter; /*!< Value of the timeout counter */
volatile bool timeoutCounterFlag; /*!< Timeout counter flag */
} lin_xfer_state_t;
/**@}*/
/**
* @name API declaration for LIN driver.
*
*/
/**@{*/
/**
* @brief Init the LIN instance for LIN network. This API will help initialize the FCUART to expect state,
* but will nots start the TX&RX function, if users want to start the LIN protocol transfer, please
* call the function LIN_DrvStart() after this API is called.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @param pConfig Configuration for LIN hardware, must not be null.
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - LIN_STATUS_USEED : The instance has been used, user should use another instance or de-initialize this instance firstly.
* - LIN_STATUS_ERROR : the baudrate has not been set successfully.
*/
LIN_StatusType LIN_DrvInit(uint8_t u8LinIndex, lin_config_t *pConfig);
/**
* @brief De-Init the LIN instance used by LIN network.
* This API will help disable the fcuart interrupts and stop the TX/RX transfer.
*
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - LIN_STATUS_NOT_INIT : The instance has not been initialized.
*/
LIN_StatusType LIN_DrvDeInit(uint8_t u8LinIndex);
/**
* @brief Help users get the default configuration of LIN node. users should provide the configuration structure
* in app code, and transfer the ptr address to driver code. uses can also set this parameters in the application code
* as designed.
*
* @param u8NodeMode LIN node mode select, 0 for slave mode and 1 for master mode.
* @param pConfig default configuration for LIN node, must not be null.
*/
void LIN_DrvGetDefaultConfig(LIN_NodeType eNodeMode, lin_config_t *pConfig);
/**
* @brief Start LIN node transfer, this API should be called after LIN hardware has been initialized, and must
* be called before starting a LIN node transfer. Users should provide a tansfer structure for storing the
* transfer state, ant LIN node state changed will be stored to this xfer state.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @param pXferState Transfer state structure which will help store the trasnfer state.
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - LIN_STATUS_PARAM_ERROR: the parameter setting maybe not correct, maybe instance has bot been initialized.
*/
LIN_StatusType LIN_DrvStart(uint8_t u8LinIndex, lin_xfer_state_t *pXferState);
/**
* @brief This function will help install callback function that used by application code.
* users can handle some needed operations in driver code or get some important states.
* or uses can also setting this in transfer state structure.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @param callback user's callbak function that need be called in driver code.
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - LIN_STATUS_NOT_INIT : The instance required has bot been initialized.
*/
LIN_StatusType LIN_DrvInstallUserCallback(uint8_t u8LinIndex, lin_callback_t callback);
/**
* @brief This function will help users send a header in master node which will help start a new
* frame transfer. please do not used this API will LIN instance is configured as slave node.
* This API will make a parity ID, and only send a break field to the protocol, all the other
* filed like sync filed and pid byte will be handled in FCUART IRQHandler. more details can
* refer to IRQ routine.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @param u8Id The ID data that useds need to send in header.
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - LIN_STATUS_NOT_INIT : Instance required has not been intialized.
* - LIN_STATUS_UNSUPPORTED : Current node is slave not, could not send header to protocol.
* - LIN_STATUS_BUSY : Bus busy which means node is sending or receiving another frame.
*/
LIN_StatusType LIN_DrvSendHeader(uint8_t u8LinIndex, uint8_t u8Id);
/**
* @brief This API will help users send a frame data through LIN protocol, and will return only when
* all frame data has been sent to the protocol, or while timeout occurred, so please configure
* the u32TimeOut parameter as needed. And currentlyt this API has not implement the OS feature,
* so do not call this API in interrupt routine, otherwise, routine maybe halted by this API.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @param pTxBuf TX buffer whihc will be sent to protocol, MUST NOT BE NULL.
* @param u8Length bytes lengths in TX buffer.
* @param u32TimeOut Timeout value, 0 indicates timeout feature is not used, in unit of millieconds.
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - LIN_STATUS_NOT_INIT : Instance required has not been initialized.
* - LIN_STATUS_BUSY : Bus busy, node is transfer state.
*/
LIN_StatusType LIN_DrvSendFrameBlocking(uint8_t u8LinIndex, uint8_t *pTxBuf, uint8_t u8Length, uint32_t u32TimeOut);
/**
* @brief This API will help users send a frame data through LIN protocol, this API will return immediately.
* data will be stored in txbuffer, users can check the transmit status while data is sending.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @param pTxBuf TX buffer whihc will be sent to protocol, MUST NOT BE NULL.
* @param u8Length bytes lengths in TX buffer.
* @param u32TimeOut Timeout value, 0 indicates timeout feature is not used, in unit of millieconds.
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - LIN_STATUS_NOT_INIT : Instance required has not been initialized.
* - LIN_STATUS_BUSY : Bus busy, node is transfer state.
*/
LIN_StatusType LIN_DrvSendFrameNonBlocking(uint8_t u8LinIndex, uint8_t *pTxBuf, uint8_t u8Length);
/**
* @brief This API will help users get the LIN transfer status while data is sending. and will also
* help user get remainning byte in transfer still need sending in buffer.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @param pRemainBytes Address to be stored the remain byte value, should not be NULL.
* @return operation status:
* - LIN_STATUS_TIMEOUT : node transfer timeout occurred.
* - LIN_STATUS_SUCCESS : transfer complete.
* - LIN_STATUS_BUSY : transfer is going
*/
LIN_StatusType LIN_DrvGetTransmitStatus(uint8_t u8LinIndex, uint8_t *pRemainBytes);
/**
* @brief This API will help users receive frame data through LIN protocol, this API will return only when
* all frame data has been received from the protocol, or while timeout occurred, so please configure
* the u32TimeOut parameter as needed. And currently, this API has not implement the OS feature,
* so do not call this API in interrupt routine, otherwise, routine maybe halted by this API.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @param pRxBuf RX buffer which will be received from protocol, MUST not be NULL.
* @param u8Length bytes lengths should be received.
* @param u32TimeOut Timeout value, 0 indicates timeout feature is not used, in millieconds.
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - LIN_STATUS_NOT_INIT : Instance has not been initialized
* - LIN_STATUS_BUSY : Bus in busy state, need wait bus idle.
* - LIN_STATUS_TIMEOUT : Timeout occurred, data received may not successful.
*/
LIN_StatusType LIN_DrvReceiveFrameBlocking(uint8_t u8LinIndex, uint8_t *pRxBuf, uint8_t u8Length, uint32_t u32TimeOut);
/**
* @brief This API will help users received frame data through LIN protocol, this API will return immediately.
* data will be stored in rxbuffer, users can check the receive status while using this API.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @param pRxBuf RX buffer which will be received from protocol, MUST not be NULL.
* @param u8Length bytes lengths should be received.
* @param u32TimeOut Timeout value, 0 indicates timeout feature is not used, in millieconds.
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - LIN_STATUS_NOT_INIT : Instance has not been initialized
* - LIN_STATUS_BUSY : Bus in busy state, need wait bus idle.
* - LIN_STATUS_TIMEOUT : Timeout occurred, data received may not successful.
*/
LIN_StatusType LIN_DrvReceiveFrameNonBlocking(uint8_t u8LinIndex, uint8_t *pRxBuf, uint8_t u8Length);
/**
* @brief This API will help users get the LIN transfer status while data is receiving. and will also
* help user get remainning byte in transfer still need receiving in buffer.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @param pRemainBytes Address to be stored the remain byte value, should not be NULL.
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - others are not successfully.
*/
LIN_StatusType LIN_DrvGetReceiveStatus(uint8_t u8LinIndex, uint8_t *pRemainBytes);
/**
* @brief Abort transfer both sending or receiving data, actually, call this APU will enter IDLE state.
* will stop end and receive even data transfer is on going.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
*/
LIN_StatusType LIN_DrvAbortTransfer(uint8_t u8LinIndex);
/**
* @brief This API should be called while no data is transferring, once this API is called, node will
* enter sleep mode, TX/RX and interrupts will also be disabled, and node will wait a wakeup signal
* on the protocol. This API will enable receive active interrupt, once a wakeup signal triggered,
* routine will entern uart IRQHandler to handle this case, and then wakeup the LIN node.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
*/
LIN_StatusType LIN_DrvGoToSleepMode(uint8_t u8LinIndex);
/**
* @brief THis API will help confgure the mode into IDLE state. In IDLE state, node will enable receive interrupt and break
* field detect interrupt, slave node will wait the break field from master node, master node will prepare to send a
* new break filed to start a new frame.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
*/
LIN_StatusType LIN_DrvGoToIdleMode(uint8_t u8LinIndex);
/**
* @brief Sending a wakeup signal to the protocol, all LIN network nodes receive this signal will
* wakeup from sleep mode. Actually, the master will send a character which will cause a 150us
* larger active level to the protocol. while receiving this signal, LIN node will wake up
* from sleep mode.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - LIN_STATUS_NOT_INIT : Instance required is not initialized.
* - LIN_STATUS_BUSY ：LIN node state is not correct, need update state firstly.
*/
LIN_StatusType LIN_DrvSendWakeupSignal(uint8_t u8LinIndex);
/**
* @brief Get the LIN node state.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @return the node current state, refer to @lin_node_state_t
*/
lin_node_state_t LIN_DrvGetNodeState(uint8_t u8LinIndex);
/**
* @brief This API should be called by user's application code, and the timeout periods should be 500ms once.
* Better to provide a timer IRQhandler to call this APIs 500ms onces.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - others are not successfully.
*/
LIN_StatusType LIN_DrvTimeOutService(uint8_t u8LinIndex);
/**
* @brief This API will help users set the timeout counter with one API, users should use this feature with LIN_DrvTimeOutService()
* called every fixed time.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @param u32TimeOutValue Timeout value.
* @return operation status:
* - LIN_STATUS_SUCCESS : operation is successfully.
* - LIN_STATUS_NOT_INIT : Instance required is not initialized.
*/
LIN_StatusType LIN_DrvSetTimeOutCounter(uint8_t u8LinIndex, uint32_t u32TimeOutValue);
/**
* @brief This API will help users get the Node timeout flag status.
*
* @param u8LinIndex LIN hardware instance, 0U...
* @return true for timeout occurred, false indicate no timeout.
*/
bool LIN_DrvGetTimeOutFlag(uint8_t u8LinIndex);
/**
* @brief This is LIN IRQ routine code, uses should call this in the FCUART IRQhandler code. please must implement
* the feature in application code.
*
* @param u8LinIndex LIN hardware instance, 0U...
*/
void LIN_DrvIRQHandler(uint8_t u8LinIndex);
/**@}*/
/** @}*/ /* fc4xxx_driver_lin */
#if defined(__cplusplus)
}
#endif
#endif /* _DRIVER_FC4XXX_DRIVER_LIN_H_ */

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/**
* @file fc7xxx_driver_lu.h
* @author Flagchip0103
* @brief FC7xxx LU driver header file
* @version 0.1.0
* @date 2023-12-19
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-19 Flagchip0103 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC4XXX_DRIVER_LU_H_
#define _DRIVER_FC4XXX_DRIVER_LU_H_
#include "HwA_lu.h"
/**
* @addtogroup fc7xxx_driver_lu
* @{
*/
#define LU_AOI_IN_N_CFG_N(AoiIn, AoiInN, InNCfgNType) ((((uint32_t)(InNType) & 0x3U) << (((uint32_t)3U - (uint32_t)(AoiInN)) << 3U)) << (((uint32_t)3U - (uint32_t)(AoiIn)) << 3U))
#define LU_AOI_IN_N_CFG_N_MASK(AoiIn, AoiInN) (((uint32_t)0x3U << (((uint32_t)3U - (uint32_t)(AoiInN)) << 3U)) << (((uint32_t)3U - (uint32_t)(AoiIn)) << 3U))
#define LU_AOI_IN_CFG(AoiInN, CfgNType) ((((uint32_t)(CfgNType) & 0x3U) << (((uint32_t)3U - (uint32_t)(AoiInN)) << 1U)))
#define LU_AOI_IN_CFG_MASK(AoiInN) ((((uint32_t)0x3U) << (((uint32_t)3U - (uint32_t)(AoiInN)) << 1U)))
#define LU_AOI_IN_N_CFG(AoiIn, InNType) ((((uint32_t)(InNType) & 0xFFU) << (((uint32_t)3U - (uint32_t)(AoiIn)) << 3U)))
#define LU_AOI_IN_N_CFG_MASK(AoiIn) ((((uint32_t)0xFFU) << (((uint32_t)3U - (uint32_t)(AoiIn)) << 3U)))
#define LU_SYNC_CONTROL_INPUT_N(InputN, value) ((uint32_t)(value) << (InputN))
/** @brief LU return structure */
typedef enum
{
LU_STATUS_SUCCESS = 0U,
LU_STATUS_PARAM_INVALID = 1U
} LU_StatusType;
/** @brief LU IN type */
typedef enum
{
LU_AOI_IN_0 = 0U,
LU_AOI_IN_1,
LU_AOI_IN_2,
LU_AOI_IN_3,
} LU_AoiInType;
/** @brief LU IN(n) configuration type */
typedef enum
{
LU_AOI_IN_N_A = 0U,
LU_AOI_IN_N_B,
LU_AOI_IN_N_C,
LU_AOI_IN_N_D
} LU_AoiInNType;
/** @brief LU IN(n) configuration */
typedef enum
{
FORCE_ITEM_AS_ZERO = 0U, /**< force item as logic zero */
PASS_THROUGH_ITEM, /**< pass through item */
COMPLEMENT_ITEM, /**< complement item */
FORCE_ITEM_AS_ONE /**< force item as logic one */
} LU_InModeType;
/** @brief LU output initialization value */
typedef enum
{
LU_OUTPUT_INIT_ZERO = 0U,
LU_OUTPUT_INIT_ONE,
LU_OUTPUT_INIT_DISABLE
} LU_OutputInitValueType;
/** @brief LU IN(n) configuration register type */
typedef struct
{
LU_InModeType eInNACfg; /**< AOI IN(n) A configuration */
LU_InModeType eInNBCfg; /**< AOI IN(n) B configuration */
LU_InModeType eInNCCfg; /**< AOI IN(n) C configuration */
LU_InModeType eInNDCfg; /**< AOI IN(n) D configuration */
} LU_InConfigType;
/** @brief LU AOI IN(n) configuration type */
typedef struct
{
LU_InConfigType tIn0Config; /**< AOI IN0 configuration */
LU_InConfigType tIn1Config; /**< AOI IN1 configuration */
LU_InConfigType tIn2Config; /**< AOI IN2 configuration */
LU_InConfigType tIn3Config; /**< AOI IN3 configuration */
} LU_AoiConfigType;
/** @brief LU LG inputs synchronous control */
typedef struct
{
bool bInputNA; /**< LU IN(n) A sync control */
bool bInputNB; /**< LU IN(n) B sync control */
bool bInputNC; /**< LU IN(n) C sync control */
bool bInputND; /**< LU IN(n) D sync control */
} LU_InputsSyncCtrlType;
/** @brief LU initialization type */
typedef struct
{
LU_LgType eLgNum; /**< LG number */
LU_AoiConfigType tAoi0Config; /**< aoi0 configuration */
LU_AoiConfigType tAoi1Config; /**< aoi1 configuration */
LU_InputsSyncCtrlType tSyncCtrl; /**< inputs sync control, when set, would sync input product with bus clock */
LU_BypassModeType eAoiMode; /**< AOI mode */
LU_ConfigModeType eFFMode; /**< flip-flop mode */
LU_OutputInitValueType eFFInitValue; /**< flip-flop initial value */
LU_InputNType eFbMode; /**< feedback override control in JKFF mode */
uint8_t u8Aoi0FiltCnt; /**< aoi0 input filter sample count */
uint8_t u8Aoi0Period; /**< aoi0 input filter sample period */
uint8_t u8Aoi1FiltCnt; /**< aoi1 input filter sample count */
uint8_t u8Aoi1Period; /**< aoi1 input filter sample period */
} LU_InitType;
/* global functions */
/**
* @brief Initialize LU instance
* @param pInitStruct LU initialization structure
* @return LU return type
*/
LU_StatusType LU_Init(const LU_InitType *const pInitStruct);
/**
* @brief De-initialize LU instance
*/
void LU_Deinit(void);
/** @}*/ /* fc7xxx_driver_lu */
#endif

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/**
* @file fc7xxx_driver_mam.h
* @author Flagchip
* @brief FC7xxx MAM driver type definition and API
* @version 0.2.0
* @date 2023-02-08
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-02-08 Flagchip095 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_MAM_H_
#define _DRIVER_FC7XXX_DRIVER_MAM_H_
#include "device_header.h"
#include "HwA_mam.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @brief The master index of the mam peripheral
*
*/
typedef enum {
MAM_MASTER_CPU0_AXIM = 0,
MAM_MASTER_CPU0_AHBP,
MAM_MASTER_DMA0,
MAM_MASTER_HSM,
MAM_MASTER_NUM
} MAM_Master_Type;
/**
* @brief The mam index
*
*/
typedef enum {
NVM_MAM0 = 0,
RAM_MAM1,
PERIPHERAL_MAM2
} MAM_Index_Type;
/**
* @brief the MAM slave information
*
*/
typedef struct
{
uint8_t error;
uint32_t block_num;
} MAM_Inf_Type;
typedef enum {
FORBID_READ_ACCESS = 1,
FORBID_WRITE_ACCESS = 2,
FORBID_EXECUTE_ACCESS = 4,
FORBID_USER_ACCESS = 8
} MAM_Forbid_Access_Type;
/**
* @brief The function of software reset to MAM
*
* @param number mam index
*/
void MAM_Reset(MAM_Index_Type idx);
/**
* @brief The function to enable MAM watch dog
*
* @param1 Master The master index
*
* @param2 u32Addr The input address
*/
uint8_t MAM_Enable_Wdg(MAM_Master_Type Master,uint32_t u32Addr);
/**
* @brief The function to disable MAM watch dog
*
* @param1 Master The master index
*
* @param2 u32Addr The input address
*/
uint8_t MAM_Disable_Wdg(MAM_Master_Type Master,uint32_t u32Addr);
/**
* @brief The function to config MAM
*
* @param1 Master The master index
*
* @param2 u32Addr The input address
*
* @param3 u32Val The value to set
*/
uint8_t MAM_Config(MAM_Master_Type Master, uint32_t u32Addr, uint32_t u32Val);
#if defined(__cplusplus)
}
#endif
#endif /* end of DRIVER_UART_H_ */

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/**
* @file fc7xxx_driver_mb.h
* @author Flagchip070
* @brief FC7xxx Mailbox driver type definition and API
* @version 0.1.0
* @date 2022-11-15
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022-11-15 Flagchip070 N/A First version for FC7300
********************************************************************************/
#ifndef _DRIVER_fc7xxx_driver_mb_H_
#define _DRIVER_fc7xxx_driver_mb_H_
#include "device_header.h"
#include "HwA_mb.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_mb
* @{
*/
/**
* @brief Mailbox channel bit flag of security information
*
*/
#define MB_CHANNEL_STATUS_SECURE 2u
/**
* @brief Mailbox channel bit flag of processing information
*
*/
#define MB_CHANNEL_STATUS_PRIVILEGED 1u
/**
* @name Mailbox channel bit mask
* @brief Bit of channel indicate channel number
*
* @{
*/
#define MB_CHANNEL_MASK_NONE 0u
#define MB_CHANNEL_MASK_ALL 0xFFFFu
#define MB_CHANNEL_MASK(ch) ((uint32_t)(1ul << (ch)))
/** @}*/
/**
* @brief Mailbox has not initialized, the core index will be MB_NOT_INIT
*
*/
#define MB_NOT_INIT 0xFFFFFFFFu
/**
* @brief Mailbox operation return values
*
*/
typedef enum {
MB_STATUS_SUCCESS = 0u, /*!< The Mailbox operation is success */
MB_STATUS_FAILED, /*!< The Mailbox operation is failed */
MB_STATUS_PARAM_ERROR, /*!< The Mailbox operation is failed because of parameter error*/
MB_STATUS_ALREADY_INITED, /*!< The Mailbox operation is failed because of
Mailbox has already initialized*/
MB_STATUS_UNINIT, /*!< The Mailbox operation is failed because of
Mailbox has not initialized*/
MB_STATUS_LOCKED, /*!< The Mailbox channel is locked */
MB_STATUS_NO_REQUEST, /*!< No valid requests */
} MB_StatusType;
/**
* @brief Configuration of a Mailbox request
*
*/
typedef struct
{
uint8_t u8Channel; /*!< The selected Mailbox channel */
uint8_t u8RequestMask; /*!< The mask for issuing requests */
uint8_t u8DoneMasterIndex; /*!< The master ID of the core that generates a done event */
uint8_t u8DoneMask; /*!< The mask for the done events */
uint8_t u8AutoReleaseFlag; /*!< Automatically clear the channel lock enable bit */
uint8_t u8Reserved[3];
uint32_t aData[2]; /*!< Sending data */
} MB_RequestType;
/**
* @brief Configuration of a receiving request
*
*/
typedef struct
{
uint8_t u8Channel; /*!< The selected Mailbox channel */
uint8_t u8MasterCoreIndex; /*!< Buffer to store the master core index */
uint8_t u8ChannelStatus; /*!< Buffer to store the security information
and processing mode of the channel*/
uint8_t u8Reserved;
uint32_t aData[2]; /*!< Buffer to store the receiving data */
} MB_ReceiveType;
/**
* @brief Configuration of the Mailbox
*
*/
typedef struct
{
uint32_t u32EventMask; /*!< Mask for the request events and done events */
uint32_t u32IntrMask; /*!< Mask for enable the interrupts */
void (*pRequestCallback)(MB_ReceiveType *pReceive); /*!< Callback of the request events */
void (*pDoneCallback)(uint32_t u32ChannelMask); /*!< Callback of the done events */
} MB_InitType;
/**
* @brief Initialize the Mailbox
*
* @param pInitConfig the configurations of the Mailbox
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_Init(const MB_InitType *pInitConfig);
/**
* @brief De-initialize the Mailbox
*
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_DeInit(void);
/**
* @brief Attempt to acquire a Mailbox channel
*
* @param u32Channel the selected Mailbox channel
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_LockChannel(uint32_t u32Channel);
/**
* @brief Release a Mailbox channel
*
* @param u32Channel the selected Mailbox channel
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_ReleaseChannel(uint32_t u32Channel);
/**
* @brief Get the index of the core
*
* @return uint32_t index of the core
*/
uint32_t MB_GetCoreIndex(void);
/**
* @brief Launching a Mailbox request
*
* @param pRequest Configuration of the request
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_SendRequest(MB_RequestType *pRequest);
/**
* @brief Attempt to receive a request from the selected channel
*
* @param pReceive Configuration of the receiving request
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_ReceiveChannel(MB_ReceiveType *pReceive);
/**
* @brief Software clears channel lock
*
* @param u32Channel the selected Mailbox channel
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_UnlockChannel(uint32_t u32Channel);
/**
* @brief Polling the done event of all channels
*
* @param u32PollMask mask of the done event
* @param pDoneMask buffer to store the done events
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_PollDone(uint32_t u32PollMask, uint32_t *pDoneMask);
/**
* @brief Issue a done event to the selected channel
*
* @param u32Channel the selected Mailbox channel
* @param u32DoneMask The mask for issuing done
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_DoneChannel(uint32_t u32Channel, uint32_t u32DoneMask);
/**
* @brief Interrupt IRQ handle of Mailbox
*
*/
void MB_IRQProcess(void);
/** @}*/ /* fc7xxx_driver_mb */
#if defined(__cplusplus)
}
#endif
#endif

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/**
* @file fc7xxx_driver_mpu.h
* @author Flagchip085
* @brief FC7xxx MPU driver type definition and API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details The MPU only checks the CPU master access to CTCM and DTCM memory. When access denied, it will cause MemManage Interrupt.
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_MPU_H_
#define _DRIVER_FC7XXX_DRIVER_MPU_H_
#include "HwA_mpu.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_mpu
* @{
*/
/**
* @brief Status enumeration used by Flagchip MPU Driver
*
*/
typedef enum {
MPU_STATUS_SUCCESS = 0, /*!< MPU API execute successfully */
MPU_STATUS_ERROR, /*!< Some error occur in MPU API */
} MPU_StatusType;
/**
* @brief
*
*/
typedef enum {
MPU_EN_HFNMI_PRIVDEF_NONE = 0U, /*!< disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault,
MPU is disabled during hard fault, NMI, and FAULTMASK handlers */
MPU_EN_HARDFAULT_NMI = 1, /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
MPU_EN_PRIVILEGED_DEFAULT = 2, /*!< enables use of the default memory map as a background region for privileged software accesses.
When enabled, the background region acts as if it is region number -1.
Any region that is defined and enabled has priority over this default map. */
MPU_EN_HFNMI_PRIVDEF = 3, /*!< same with MPU_EN_HARDFAULT_NMI | MPU_EN_PRIVILEGED_DEFAULT */
} MPU_EnableOptionType;
/**
* @brief Enable Status for Sub-region configuration
*
*/
typedef enum {
MPU_REGION_SRD_ENABLE_SUBREGION = 0, /*!< sub-region is enabled */
MPU_REGION_SRD_DISABLE_SUBREGION = 1, /*!< sub-region is not enabled */
} MPU_RegionSubDisableType;
/**
* @brief Configure the code in the region whether can be execute
*
*/
typedef enum {
MPU_REGION_XN_EXECUTE_ENABLE = 0x0,
MPU_REGION_XN_EXECUTE_DISABLE = 0x1
} MPU_RegionExecuteNeverType;
/**
* @brief region Shareable configuration
*
*/
typedef enum {
MPU_REGION_S_DISABLE = 0,
MPU_REGION_S_ENABLE = 1
} MPU_RegionShareableType;
/**
* @brief Region Cacheable configuration
*
*/
typedef enum {
MPU_REGION_C_DISABLE = 0,
MPU_REGION_C_ENABLE = 1
} MPU_RegionCacheableType;
/**
* @brief Region Bufferable configuration
*
*/
typedef enum {
MPU_REGION_B_DISABLE = 0,
MPU_REGION_B_ENABLE = 1
} MPU_RegionBufferableType;
/**
* @brief Region Type Extend Level configuration
*
*/
typedef enum {
MPU_REGION_TEX_LEVEL_0 = 0,
MPU_REGION_TEX_LEVEL_1 = 1,
MPU_REGION_TEX_LEVEL_2 = 2
} MPU_RegionTypeExtLevelType;
/**
* @brief Region size enumeration for enabling MPU region
*
*/
typedef enum {
MPU_REGION_SIZE_32B = 0x04,
MPU_REGION_SIZE_64B = 0x05,
MPU_REGION_SIZE_128B = 0x06,
MPU_REGION_SIZE_256B = 0x07,
MPU_REGION_SIZE_512B = 0x08,
MPU_REGION_SIZE_1KB = 0x09,
MPU_REGION_SIZE_2KB = 0x0A,
MPU_REGION_SIZE_4KB = 0x0B,
MPU_REGION_SIZE_8KB = 0x0C,
MPU_REGION_SIZE_16KB = 0x0D,
MPU_REGION_SIZE_32KB = 0x0E,
MPU_REGION_SIZE_64KB = 0x0F,
MPU_REGION_SIZE_128KB = 0x10,
MPU_REGION_SIZE_256KB = 0x11,
MPU_REGION_SIZE_512KB = 0x12,
MPU_REGION_SIZE_1MB = 0x13,
MPU_REGION_SIZE_2MB = 0x14,
MPU_REGION_SIZE_4MB = 0x15,
MPU_REGION_SIZE_8MB = 0x16,
MPU_REGION_SIZE_16MB = 0x17,
MPU_REGION_SIZE_32MB = 0x18,
MPU_REGION_SIZE_64MB = 0x19,
MPU_REGION_SIZE_128MB = 0x1A,
MPU_REGION_SIZE_256MB = 0x1B,
MPU_REGION_SIZE_512MB = 0x1C,
MPU_REGION_SIZE_1GB = 0x1D,
MPU_REGION_SIZE_2GB = 0x1E,
MPU_REGION_SIZE_4GB = 0x1F
} MPU_RegionSizeType;
/**
* @brief MPU Permission Enumeration
*
*/
typedef enum {
MPU_REGION_AP_NO_ACCESS = 0x00, /*!< Any access generates a permission fault */
MPU_REGION_AP_PRIV_RW = 0x01, /*!< Privileged access only, unprivileged no access */
MPU_REGION_AP_PRIV_RW_URO = 0x02, /*!< Any unprivileged write generates a permission fault */
MPU_REGION_AP_FULL_ACCESS = 0x03, /*!< Full access */
MPU_REGION_AP_PRIV_RO = 0x05, /*!< Privileged read-only, unprivileged no access */
MPU_REGION_AP_PRIV_RO_URO = 0x06 /*!< Privileged and unprivileged read-only */
} MPU_RegionAccessPermissionType;
typedef enum {
MPU_REGION_NUMBER_0 = 0x0, /*!< lowest priority */
MPU_REGION_NUMBER_1 = 0x1,
MPU_REGION_NUMBER_2 = 0x2,
MPU_REGION_NUMBER_3 = 0x3,
MPU_REGION_NUMBER_4 = 0x4,
MPU_REGION_NUMBER_5 = 0x5,
MPU_REGION_NUMBER_6 = 0x6,
MPU_REGION_NUMBER_7 = 0x7,
MPU_REGION_NUMBER_8 = 0x8,
MPU_REGION_NUMBER_9 = 0x9,
MPU_REGION_NUMBER_10 = 0xA,
MPU_REGION_NUMBER_11 = 0xB,
MPU_REGION_NUMBER_12 = 0xC,
MPU_REGION_NUMBER_13 = 0xD,
MPU_REGION_NUMBER_14 = 0xE,
MPU_REGION_NUMBER_15 = 0xF /*!< highest priority */
} MPU_RegionNumberType;
typedef struct {
uint32_t u32BaseAddr; /*!< the start address of region, the least significant 5 bits should be 0 */
MPU_RegionSizeType eRegionSize; /*!< region size */
MPU_RegionAccessPermissionType eAccessPermission; /*!< region access permission */
MPU_RegionExecuteNeverType eExecuteNever; /*!< region data can be execute or not */
MPU_RegionTypeExtLevelType eTypeExtLevel; /*!< region type extend level */
MPU_RegionShareableType eShareable; /*!< region shareable */
MPU_RegionCacheableType eCacheable; /*!< region cacheable */
MPU_RegionBufferableType eBufferable; /*!< region bufferable */
MPU_RegionSubDisableType eSubRegionDis_0; /*!< sub-region 0 disable or not */
MPU_RegionSubDisableType eSubRegionDis_1; /*!< sub-region 1 disable or not */
MPU_RegionSubDisableType eSubRegionDis_2; /*!< sub-region 2 disable or not */
MPU_RegionSubDisableType eSubRegionDis_3; /*!< sub-region 3 disable or not */
MPU_RegionSubDisableType eSubRegionDis_4; /*!< sub-region 4 disable or not */
MPU_RegionSubDisableType eSubRegionDis_5; /*!< sub-region 5 disable or not */
MPU_RegionSubDisableType eSubRegionDis_6; /*!< sub-region 6 disable or not */
MPU_RegionSubDisableType eSubRegionDis_7; /*!< sub-region 7 disable or not */
} MPU_RegionConfigurationType;
/**
* @brief Check the MPU exist or not
*
* @return MPU_StatusType if exist return MPU_STATUS_SUCCESS, others not exist
*/
MPU_StatusType MPU_CheckExist(void);
/**
* @brief Enable the MPU
*
* @param eOption Enable Options
*/
void MPU_Enable(MPU_EnableOptionType eOption);
/**
* @brief Disable MPU
*
*/
void MPU_Disable(void);
/**
* @brief Disable region
*
* @param eRegion Region index
* @return MPU_StatusType MPU_STATUS_SUCCESS when disable successfully, others fail
*/
MPU_StatusType MPU_RegionDisable(MPU_RegionNumberType eRegion);
/**
* @brief Enable region
*
* @param eRegion Region index
* @param pConfig Region Configuration Parameter
* @return MPU_StatusType MPU_STATUS_SUCCESS when disable successfully, others fail
*/
MPU_StatusType MPU_RegionEnable(MPU_RegionNumberType eRegion, const MPU_RegionConfigurationType *pConfig);
/** @} */ /* fc7xxx_driver_mpu */
#if defined(__cplusplus)
}
#endif
#endif /* _DRIVER_FC7XXX_DRIVER_MPU_H_ */

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/**
* @file fc7xxx_driver_msc.h
* @author Flagchip
* @brief FC7240 MSC driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_MSC_H_
#define _DRIVER_FC7XXX_DRIVER_MSC_H_
#include "device_header.h"
#include "HwA_msc.h"
/**
* @addtogroup fc7xxx_driver_msc
* @{
. */
typedef enum
{
MSC_RETURN_OK = 0x00U, /*!< The SENT operation is succeeded */
MSC_RETURN_E_NOT_OK = 0x01U, /*!< The SENT operation is failed */
MSC_RETURN_E_PARAM = 0x04U, /*!< The SENT parameter is incorrect or out of range. */
} MSC_ReturnType;
typedef enum
{
MSC_RDR0 = 0x0U,
MSC_RDR1 = 0x1U,
MSC_RDR2 = 0x2U,
MSC_RDR3 = 0x3U,
MSC_RDRx_COUNT = 0x4U
} MSC_RDRxIndexType;
typedef enum
{
MSC_INSTANCE_0 = 0U, /*!< MSC instance 0 is selected. */
MSC_INSTANCE_1 = 1U /*!< MSC instance 1 is selected. */
} MSC_InstanceType;
typedef enum
{
MSC_RFIE_DISABLE = 0x0U, /*!< Interrupt generation disabled. */
MSC_RFIE_MODE1 = 0x1U, /*!< The interrupt is generated when data is received and written into the RDRx. */
MSC_RFIE_MODE2 = 0x2U, /*!< The interrupt is generated when received data is not equal to 0. */
MSC_RFIE_MODE3 = 0x3U /*!< The interrupt is generated when data is received and written into register RDR3. */
} MSC_RFIEModeType;
typedef enum
{
MSC_DFIE_DISABLE = 0x0U, /*!< Disable. */
MSC_DFIE_MODE1 = 0x1U, /*!< Interrupt is generated when the last data bit has been shifted. */
MSC_DFIE_MODE2 = 0x2U /*!< Interrupt is generated when the first data bit has been shifted. */
} MSC_DFIEModeType;
/**
* @brief MSC Channel ISR callback function prototype
*
*/
typedef void (*MSC_ISRCallbackType)(const MSC_InstanceType eInstance);
/** @brief MSC interrupt configure structure. */
typedef struct
{
bool bCFIntEnable; /*!< MSC_INCR[CFIE] bit, interrupt enable, if this bit asserted, command frame can lead the interrupt. */
bool bTFIntEnable; /*!< MSC_INCR[TFIE] bit, interrupt enable, if this bit asserted, time frame can lead the interrupt. */
MSC_RFIEModeType eRFIEMode; /*!< Interrupt mode of RFIE. */
MSC_DFIEModeType eDFIEMode; /*!< Interrupt mode of DFIE. */
bool bTOIntEnable; /*!< Enable the interrupt of timeout. */
uint16_t u16TimeoutValue; /*!< Timeout value of timeout interrupt. */
MSC_ISRCallbackType pReceiveFrameISRCallback; /*!< Receive frame ISR callback. */
MSC_ISRCallbackType pTimeFrameISRCallback; /*!< Time Frame ISR callback. */
MSC_ISRCallbackType pCommandFrameISRCallback; /*!< Command Frame ISR callback. */
MSC_ISRCallbackType pDataFrameISRCallback; /*!< Data Frame ISR callback. */
MSC_ISRCallbackType pReceiveTimeOutISRCallback; /*!< Data Frame ISR callback. */
} MSC_InterruptCfgType;
typedef enum
{
MSC_SDI_SEL_SDI0 = 0x0U, /*!< SDI0 input is selected for SDI. */
MSC_SDI_SEL_SDI1 = 0x1U, /*!< SDI1 input is selected for SDI. */
MSC_SDI_SEL_SDI2 = 0x2U, /*!< SDI2 input is selected for SDI. */
MSC_SDI_SEL_SDI3 = 0x3U, /*!< SDI3 input is selected for SDI. */
MSC_SDI_SEL_SDI4 = 0x4U, /*!< SDI4 input is selected for SDI. */
MSC_SDI_SEL_SDI5 = 0x5U, /*!< SDI5 input is selected for SDI. */
MSC_SDI_SEL_SDI6 = 0x6U, /*!< SDI6 input is selected for SDI. */
MSC_SDI_SEL_SDI7 = 0x7U /*!< SDI7 input is selected for SDI. */
} MSC_SDISelectionType;
typedef enum
{
MSC_ENC_SEL_EN0 = 0x0U, /*!< EN0 is selected for ENC. */
MSC_ENC_SEL_EN1 = 0x1U, /*!< EN1 is selected for ENC. */
MSC_ENC_SEL_EN2 = 0x2U, /*!< EN2 is selected for ENC. */
MSC_ENC_SEL_EN3 = 0x3U /*!< EN3 is selected for ENC. */
} MSC_ENCSelectionType;
typedef enum
{
MSC_ENH_SEL_EN0 = 0x0U, /*!< EN0 is selected for ENH. */
MSC_ENH_SEL_EN1 = 0x1U, /*!< EN1 is selected for ENH. */
MSC_ENH_SEL_EN2 = 0x2U, /*!< EN2 is selected for ENH. */
MSC_ENH_SEL_EN3 = 0x3U /*!< EN3 is selected for ENH. */
} MSC_ENHSelectionType;
typedef enum
{
MSC_ENL_SEL_EN0 = 0x0U, /*!< EN0 is selected for ENL. */
MSC_ENL_SEL_EN1 = 0x1U, /*!< EN1 is selected for ENL. */
MSC_ENL_SEL_EN2 = 0x2U, /*!< EN2 is selected for ENL. */
MSC_ENL_SEL_EN3 = 0x3U /*!< EN3 is selected for ENL. */
} MSC_ENLSelectionType;
typedef enum
{
MSC_EN_SELECTION_0 = 0x00, /*!< EN0 is selected for ENX. */
MSC_EN_SELECTION_1 = 0x01, /*!< EN1 is selected for ENX. */
MSC_EN_SELECTION_2 = 0x02, /*!< EN2 is selected for ENX. */
MSC_EN_SELECTION_3 = 0x03, /*!< EN3 is selected for ENX. */
} Msc_ENxActiveType;
typedef enum
{
MSC_ENC = 0x00,
MSC_ENL = 0x01,
MSC_ENH = 0x02,
} Msc_ENxType;
typedef enum
{
MSC_FLC_ACTIVE_ON_FRAMES = 0x0U, /*!< FCL is actived only during the active phases of frames. */
MSC_FLC_ALWAYS_ACTIVE = 0x1U /*!< FCL is always active whether or not a downstream frame is transmitted currently.. */
} MSC_FCLControlType;
typedef enum
{
MSC_INPUT_IDENTICAL = 0x0U, /*!< SDI and SI signal polarities are identical. */
MSC_INPUT_INVERTED = 0x1U /*!< SDI and SI signal polarities are inverted. */
} MSC_InputPolarityType;
typedef enum
{
MSC_ENX_IDENTICAL = 0x0U, /*!< Enx and ENL, ENH, ENC signal polarities are identical (high active). */
MSC_ENX_INVERTED = 0x1U /*!< ENx and ENL, ENH, ENC signal polarities are inverted (low active). */
} MSC_ENxPolarityType;
typedef enum
{
MSC_SO_IDENTICAL = 0x0U, /*!< SOP and SO signal polarity is identical. */
MSC_SO_INVERTED = 0x1U /*!< SOP and SO signal polarity is inverted. */
} MSC_SOPolarityType;
typedef enum
{
MSC_FLC_IDENTICAL = 0x0U, /*!< FCLP and FCL polarity is identical. */
MSC_FLC_INVERTED = 0x1U /*!< FCLP and FCL polarity is inverted. */
} MSC_FCLpolarityType;
typedef struct
{
MSC_SDISelectionType eSDIsel; /*!< SDI seletion. */
MSC_ENCSelectionType eENCSel; /*!< ENC seletion. */
MSC_ENHSelectionType eENHSel; /*!< ENH seletion. */
MSC_ENLSelectionType eENLSel; /*!< ENL seletion. */
MSC_FCLControlType eFclCtrl; /*!< FCL Control. */
MSC_InputPolarityType eSDIPol; /*!< SDI Polarity. */
MSC_ENxPolarityType eENXPol; /*!< ENX Polarity. */
MSC_SOPolarityType eSOPPol; /*!< SO Polarity. */
MSC_FCLpolarityType eFCLPPol; /*!< FCL Polarity. */
} MSC_IOControlInitType;
typedef enum
{
MSC_TRANS_SOURCE_DATA_REG = 0x0U, /*!< SSL[x] is taken from TCDAR.DL[x]. */
MSC_TRANS_SOURCE_ALTIN = 0x2U, /*!< SSL[x] is taken from the ALTINL input line x. */
MSC_TRANS_SOURCE_ALTIN_INV = 0x3U, /*!< SSL[x] is taken from the ALTINL input line x in inverted state. */
} MSC_TransSourceType;
typedef enum
{
MSC_TRIGGER_MODE = 0x00U, /*!< Trigger work mode. */
MSC_REPETITION_MODE = 0x01U /*!< Repetition work mode. */
} MSC_WorkModeType;
typedef enum
{
MSC_EVEN_PARITY = 0x00U, /*!< Reception even parity. */
MSC_ODD_PARITY = 0x01U /*!< Reception odd parity. */
} MSC_ParityType;
typedef enum
{
MSC_RECEIVE_DISABLED = 0x00U, /*!< Receiving channel is disabled. */
MSC_BAUDRATE_FMSC_DIV4 = 0x01U, /*!< Baud rate=fmsc/4. */
MSC_BAUDRATE_FMSC_DIV8 = 0x02U, /*!< Baud rate=fmsc/8. */
MSC_BAUDRATE_FMSC_DIV16 = 0x03U, /*!< Baud rate=fmsc/16. */
MSC_BAUDRATE_FMSC_DIV32 = 0x04U, /*!< Baud rate=fmsc/32. */
MSC_BAUDRATE_FMSC_DIV64 = 0x05U, /*!< Baud rate=fmsc/64. */
MSC_BAUDRATE_FMSC_DIV128 = 0x06U, /*!< Baud rate=fmsc/128. */
MSC_BAUDRATE_FMSC_DIV256 = 0x07U /*!< Baud rate=fmsc/256. */
} MSC_ReceiveBaudRateType;
typedef enum
{
MSC_FRAME_12_BIT = 0x00U, /*!< 12-bit frame selected. */
MSC_FRAME_16_BIT = 0x01U /*!< 16-bit frame selected. */
} MSC_ReceiveFrameType;
typedef struct
{
uint8_t u8PassiveLength; /*!< Frame Passive length. */
uint8_t u8PTFNumber; /*!< The number of passive time frames that are inserted in repetition mode between two data frames. */
MSC_WorkModeType eWorkMode; /*!< MSC work mode. */
uint8_t u8CommandBitLength; /*!< Bit length of command frame. */
bool bSelSRH; /*!< Select SRH. */
uint8_t u8SRHDataBitLength; /*!< Bit length of SRH. */
bool bSelSRL; /*!< Select SRL. */
uint8_t u8SRLDataBitLength; /*!< Bit length of SRL. */
bool bDelayControl; /*!< Hardware Receive Interrupt Delay Control. */
MSC_ParityType eParity; /*!< Parity mode. */
MSC_ReceiveBaudRateType eBaudRate; /*!< Baudrate. */
MSC_ReceiveFrameType eRsvFrameType; /*!< Frame type. */
} MSC_InitCfgType;
/**
* @brief Init the MSC.
*
* @param eInstance MSCInstance.
* @param pInitConfig MSCInstance initial configuration.
*/
MSC_ReturnType MSC_init(const MSC_InstanceType eInstance, const MSC_InitCfgType *pInitConfig);
/**
* @brief Init the MSC interrupt.
*
* @param eInstance MSCInstance.
* @param pInteruptConfig MSCInstance interrupt configuration.
*/
void MSC_initInterrupt(const MSC_InstanceType eInstance, const MSC_InterruptCfgType *pInteruptConfig);
/**
* @brief Select the transmitting sources.
*
* @param eInstance MSCInstance.
* @param u32SourceMask Transmitting sources.
* @param eSourceType Transmitting sources type.
*/
void MSC_SelTranmittingSource(const MSC_InstanceType eInstance, uint32_t u32SourceMask, MSC_TransSourceType eSourceType);
/**
* @brief Set Emergency load value.
*
* @param eInstance MSCInstance.
* @param u32Value Emergency load value.
*/
void MSC_SetEmergencyLoad(const MSC_InstanceType eInstance, uint32_t u32Value);
/**
* @brief Configure the MSC IO control.
*
* @param eInstance MSCInstance.
* @param pIOConfig MSC IO control configuration.
*/
void MSC_SetIOControl(const MSC_InstanceType eInstance, const MSC_IOControlInitType *pIOConfig);
/**
* @brief Enable MSC.
*
* @param eInstance MSCInstance.
*/
void MSC_Enable(const MSC_InstanceType eInstance);
/**
* @brief Disable MSC.
*
* @param eInstance MSCInstance.
*/
void MSC_Disable(const MSC_InstanceType eInstance);
/**
* @brief MSC set data frame.
*
* @param eInstance MSCInstance.
* @param u32Data Data to be sent.
*/
void MSC_SetDataFrame(const MSC_InstanceType eInstance, uint32_t u32Data);
/**
* @brief MSC send data frame.
*
* @param eInstance MSCInstance.
*/
void MSC_SendDataFrame(const MSC_InstanceType eInstance);
/**
* @brief MSC send command frame.
*
* @param eInstance MSCInstance.
* @param u32Command command to be sent.
*/
void MSC_SendCommandFrame(const MSC_InstanceType eInstance, uint32_t u32Command);
/**
* @brief Get the msc received data address.
*
* @param eInstance MSCInstance.
* @param eIndex Receive data register index.
* @return uint8_t Receiverd data address.
*/
uint8_t MSC_GetReceivedFrameAddr(const MSC_InstanceType eInstance, MSC_RDRxIndexType eIndex);
/**
* @brief Get the msc received data.
*
* @param eInstance MSCInstance.
* @param eIndex Receive data register index.
* @param pData Received data value.
* @return MSC_ReceiveStatusType Status of getting received data.
*/
MSC_ReceiveStatusType MSC_GetReceivedFrame(const MSC_InstanceType eInstance, MSC_RDRxIndexType eIndex, uint8_t *pData);
/**
* @brief Get the msc interrupt status.
*
* @param eInstance MSCInstance.
* @return uint32_t Interrupt status.
*/
uint32_t MSC_GetInterruptStatus(const MSC_InstanceType eInstance);
/**
* @brief Get the msc interrupt status.
*
* @param eInstance MSCInstance.
* @param bEnable Enable transmit channel.
*/
void MSC_EnableTrasmit(const MSC_InstanceType eInstance, bool bEnable);
/**
* @brief Enable the msc data frame interrupt.
*
* @param eInstance MSCInstance.
*/
void MSC_EnableDataFrameInterrupt(const MSC_InstanceType eInstance, bool bEnable);
/**
* @brief Enable the msc command frame interrupt.
*
* @param eInstance MSCInstance.
*/
void MSC_EnableCommandFrameInterrupt(const MSC_InstanceType eInstance, bool bEnable);
/**
* @brief Enable the msc time frame interrupt.
*
* @param eInstance MSCInstance.
*/
void MSC_EnableTimeFrameInterrupt(const MSC_InstanceType eInstance, bool bEnable);
/**
* @brief Enable the msc receive interrupt.
*
* @param eInstance MSCInstance.
*/
void MSC_EnableReceiveInterrupt(const MSC_InstanceType eInstance, bool bEnable);
/**
* @brief Enable the msc timeout interrupt.
*
* @param eInstance MSCInstance.
*/
void MSC_EnableTimeoutInterrupt(const MSC_InstanceType eInstance, bool bEnable);
/**
* @brief Switch ENC/ENH/ENL active EN selection.
* @param eInstance MSCInstance.
* @param eEnx ENC/ENH/ENL.
* @param eENn ENX selection.
* @param u32TimeoutLoops Wait timeout if transmission is busy.
* @return
*/
MSC_ReturnType Msc_SwitchENXChannel(const MSC_InstanceType eInstance, Msc_ENxType eEnx, Msc_ENxActiveType eENn, uint32_t u32TimeoutLoops);
/**
* @brief Switch the SDI Channel.
* @param eInstance MSCInstance.
* @param eSDIChannel SDI channel.
* @param u32TimeoutLoops Wait timeout if receiving is busy.
* @return
*/
MSC_ReturnType Msc_SwitchSDIChannel(const MSC_InstanceType eInstance, MSC_SDISelectionType eSDIChannel, uint32_t u32TimeoutLoops);
/** @}*/ /* fc7xxx_driver_msc. */
#endif

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/**
* @file fc7xxx_driver_overlay.h
* @author Flagchip
* @brief FC7xxx overlay driver type definition and API
* @version 0.1.0
* @date 2023-12-25
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-25 Flagchip0038 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_OVERLAY_H_
#define _DRIVER_FC7XXX_DRIVER_OVERLAY_H_
#include "HwA_overlay.h"
/**
* @addtogroup fc7xxx_driver_overlay
* @{
*/
/**
* @brief Overlay Error Information
*
*/
typedef enum
{
OVERLAY_ERROR_OK, /**< no error */
OVERLAY_ERROR_ADDR, /**< error address */
OVERLAY_ERROR_SIZE, /**< error size */
OVERLAY_ERROR_FLAG, /**< error flag */
} OVERLAY_ErrorType;
/**
* @brief Overlay Region parameters
*
*/
typedef struct
{
uint32_t aOverlayRegionEn[OVERLYA_REGION_CNT]; /**< Overlay region enable array */
uint32_t aOverlayRegionSrc[OVERLYA_REGION_CNT]; /**< Overlay region source array, pflash */
uint32_t aOverlayRegionDst[OVERLYA_REGION_CNT]; /**< Overlay region destination array, sram */
OVERLAY_OverlaySizeType aOverlayRegionSize[OVERLYA_REGION_CNT]; /**< Overlay region size array */
}OVERLAY_OverlayRegionInitType;
/**
* @brief FAR parameter
*
*/
typedef struct
{
uint32_t u32FAREn; /**< Overlay region enable array */
uint32_t u32FARDst; /**< Overlay region destination array, pflash, source always is 0x08000000 */
uint32_t u32FARSize; /**< Overlay region size array, must align to 64KB */
}OVERLAY_FARInitType;
/**
* @brief Error Info
*
*/
typedef struct
{
uint8_t bError_FAR_SIZE_INTR; /**< bit 17, The FAR of size value is invalid */
uint8_t bError_FAR_DST_OVERFLOW_INTR; /**< bit 16, FAR of destination region is overflow with size */
uint8_t bError_FAR_DST_NO_FLASH_INTR; /**< bit 15, FAR of destination address is not flash */
uint8_t bError_REGION2_D_CROS_INTR; /**< bit 14, The range of region 2 destination address is crossed with other region */
uint8_t bError_REGION2_S_CROS_INTR; /**< bit 13, The range of region 2 source address is crossed with other region */
uint8_t bError_REGION2_SIZE_INTR; /**< bit 12, The region 2 of size value is invalid */
uint8_t bError_REGION2_DST_INTR; /**< bit 11, The region 2 of destination address is not aligned with size */
uint8_t bError_REGION2_SRC_INTR; /**< bit 10, The region 2 of source address is not aligned with size */
uint8_t bError_REGION1_D_CROS_INTR; /**< bit 9, The range of region 1 destination address is crossed with other region */
uint8_t bError_REGION1_S_CROS_INTR; /**< bit 8, The range of region 1 source address is crossed with other region */
uint8_t bError_REGION1_SIZE_INTR; /**< bit 7, The region 1 of size value is invalid */
uint8_t bError_REGION1_DST_INTR; /**< bit 6, The region 1 of destination address is not aligned with size */
uint8_t bError_REGION1_SRC_INTR; /**< bit 5, The region 1 of source address is not aligned with size */
uint8_t bError_REGION0_D_CROS_INTR; /**< bit 4, The range of region 0 destination address is crossed with other region */
uint8_t bError_REGION0_S_CROS_INTR; /**< bit 3, The range of region 0 source address is crossed with other region */
uint8_t bError_REGION0_SIZE_INTR; /**< bit 2, The region 0 of size value is invalid */
uint8_t bError_REGION0_DST_INTR; /**< bit 1, The region 0 of destination address is not aligned with size */
uint8_t bError_REGION0_SRC_INTR; /**< bit 0, The region 0 of source address is not aligned with size */
}OVERLAY_ErrorInfoType;
/** Overlay Setting Error callback type */
typedef void (*OVERLAY_ErrorCallback_Type)(OVERLAY_ErrorInfoType u16ErrorFlag);
/**
* @brief Interrupt Parameter
*
*/
typedef struct
{
uint32_t bEnableInterrupt; /**< Enable interrupt, 0 is disable, 1 is enable */
OVERLAY_ErrorCallback_Type pCallBack; /**< Callback function for error interrupt */
}OVERLAY_InterruptType;
/**
* @brief Overlay region initial function
*
* @param pOverlayInitCfg initial parameters
* @return ERROR_OK is ok, others are not ok
*/
OVERLAY_ErrorType OVERLAY_RegionInit(OVERLAY_OverlayRegionInitType *pOverlayInitCfg);
/**
* @brief De-Init Overlay Region
*
* @return ERROR_OK is ok, others are not ok
*/
OVERLAY_ErrorType OVERLAY_RegionDeInit(void);
/**
* @brief Far initial function
*
* @param pFarInitCfg initial parameters
* @return ERROR_OK is ok, others are not ok
*/
OVERLAY_ErrorType OVERLAY_FARInit(OVERLAY_FARInitType *pFarInitCfg);
/**
* @brief De-Init FAR Region
*
* @return ERROR_OK is ok, others are not ok
*/
OVERLAY_ErrorType OVERLAY_FARDeInit(void);
/**
* @brief Enable or Disable Interrupt
*
* @param pInterruptCfg interrupt config parameter
*/
void OVERLAY_SetInterrupt(OVERLAY_InterruptType *pInterruptCfg);
/**
* @brief Get Error Info
*
* @param pErrorInfo error info point
*/
void OVERLAY_GetErrorInfo(OVERLAY_ErrorInfoType *pErrorInfo);
/**
* @brief Clear Error Info
*
* @param pErrorInfo error info point
*/
void OVERLAY_ClrErrorInfo(OVERLAY_ErrorInfoType *pErrorInfo);
/**
* @brief Call Me in Overlay Error interrupt handler
*
*/
void OVERLAY_ErrorInterruptRoutine(void);
/** @}*/ /* fc7xxx_driver_overlay */
#endif

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/**
* @file fc7xxx_driver_pcc.h
* @author Flagchip085
* @brief FC7xxx PCC driver type definition and API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_PCC_H_
#define _DRIVER_FC7XXX_DRIVER_PCC_H_
#include "HwA_pcc.h"
/**
* @addtogroup fc7xxx_driver_pcc
* @{
*/
#define PCC_MUX_MAX_NUMBER 8U
/** @brief PCC clock list */
typedef enum
{
PCC_CLK_DMA0 = 0U,
PCC_CLK_DMAMUX0,
PCC_CLK_ROMC,
PCC_CLK_ERM0,
PCC_CLK_EIM0,
PCC_CLK_INTM0,
PCC_CLK_ISM0,
PCC_CLK_WDOG0,
PCC_CLK_TRGSEL0,
PCC_CLK_TRGSEL1,
PCC_CLK_TRGSEL2,
PCC_CLK_TRGSEL3,
PCC_CLK_CRC0,
PCC_CLK_CORDIC,
PCC_CLK_TSTMP0,
PCC_CLK_TSTMP1,
PCC_CLK_FCPIT0,
PCC_CLK_AONTIMER0,
PCC_CLK_RTC,
PCC_CLK_CMU0,
PCC_CLK_CMU1,
PCC_CLK_CMU2,
PCC_CLK_CMU3,
PCC_CLK_CMU4,
PCC_CLK_PTIMER0,
PCC_CLK_PTIMER1,
PCC_CLK_ADC0,
PCC_CLK_ADC1,
PCC_CLK_WKU0,
PCC_CLK_CMP0,
PCC_CLK_CMP1,
PCC_CLK_TMU0,
PCC_CLK_SENT0,
PCC_CLK_MB0,
PCC_CLK_FTU0,
PCC_CLK_FTU1,
PCC_CLK_FTU2,
PCC_CLK_FTU3,
PCC_CLK_FCSPI0,
PCC_CLK_FCSPI1,
PCC_CLK_FCSPI2,
PCC_CLK_FCIIC0,
PCC_CLK_FCUART0,
PCC_CLK_FCUART1,
PCC_CLK_FCUART2,
PCC_CLK_FCUART3,
PCC_CLK_LU0,
PCC_CLK_FREQM,
PCC_CLK_STCU,
PCC_CLK_FLEXCAN0,
PCC_CLK_FLEXCAN1,
PCC_CLK_WDOG1,
PCC_CLK_TRGSEL4,
PCC_CLK_TRGSEL5,
PCC_CLK_FCSPI3,
PCC_CLK_FCSPI4,
PCC_CLK_FCSPI5,
PCC_CLK_FTU4,
PCC_CLK_FTU5,
PCC_CLK_FTU6,
PCC_CLK_FTU7,
PCC_CLK_FCIIC1,
PCC_CLK_FCUART4,
PCC_CLK_FCUART5,
PCC_CLK_FCUART6,
PCC_CLK_FCUART7,
PCC_CLK_MSC0,
PCC_CLK_FLEXCAN2,
PCC_CLK_FLEXCAN3,
PCC_END_OF_CLOCKS
} PCC_ClkSrcType;
/**
* @brief Pcc clock status
*/
typedef enum
{
PCC_STATUS_SUCCESS = 0U,
PCC_STATUS_CLOCK_INVALID = 1U,
PCC_STATUS_CONFIGURED_NOT_SUPPORT = 1U,
} PCC_StatusType;
/**
* @brief define the PCC module initialization structure.
*/
typedef struct
{
PCC_ClkSrcType eClockName; /*!< Peripheral clock */
bool bEn; /*!< Peripheral clock enable or disable */
PCC_ClkGateSrcType eClkSrc; /*!< Peripheral function clock source select */
PCC_ClkDivType eDivider; /*!< Peripheral clock divider value */
} PCC_CtrlType;
/**
* @brief get PCC function clock status and value.
*
* @param pcc_ClkSrcType eClockName: used for choose PCC clock source to query.
* @return uint32_t Pcc function clock frequency, if PCC is not enable or do not have clock mux configuration,
* the function will return 0
*/
uint32_t PCC_GetPccFunctionClock(const PCC_ClkSrcType eClockName);
/**
* @brief get PCC interface clock status and value.
*
* @param pcc_ClkSrcType eClockName: used for choose PCC clock source to query.
*/
uint32_t PCC_GetPccInterfaceClock(const PCC_ClkSrcType eClockName);
/**
* @brief set PCC one peripheral clock configuration.
*
* @param PCC_CtrlType* pConfig: the PCC initialize value point set by user.
* @return PCC_StatusType pcc function status
*/
PCC_StatusType PCC_SetPcc(const PCC_CtrlType *const pConfig);
/**
* @brief Generate peripheral reset
*
*/
void PCC_GenPeripheralReset(const PCC_ClkSrcType eClockName);
/** @}*/ /* fc7xxx_driver_pcc */
#endif

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/* @file fc7xxx_driver_pmc.h
* @author Flagchip032
* @brief FC7xxx PMC driver type definition and API
* @version 0.1.0
* @date 2022-11-21
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials Descriptions
* --------- ---------- ------------ ---------------
* 0.1.0 2022-11-21 Flagchip032 First version for FC7xxx
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_PMC_H_
#define _DRIVER_FC7XXX_DRIVER_PMC_H_
#include "HwA_pmc.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_pmc
* @{
*/
/***************** typedef *********************/
/**
* @brief PMC voltage flags.
*
*/
typedef enum
{
PMC_HVD5V_FLAG = PMC_LVSCR_HVD5V_FLAG_MASK, /**< interrupt flag on V5 domain in FPM */
PMC_HVD2P5V_FLAG = PMC_LVSCR_HVD2P5V_FLAG_MASK, /**< interrupt flag on V25 domain in FPM */
PMC_HVD1P1V_FLAG = PMC_LVSCR_HVD1P1V_FLAG_MASK, /**< interrupt flag on V11 domain in FPM */
PMC_LVD5V_FLAG = PMC_LVSCR_LVD5V_FLAG_MASK, /**< interrupt flag on V5 domain in FPM */
PMC_LVD1P5V_FLAG = PMC_LVSCR_LVD1P5V_FLAG_MASK, /**< interrupt flag on V15 domain in FPM */
PMC_HVD1P5V_FLAG = PMC_LVSCR_HVD1P5V_FLAG_MASK, /**< interrupt flag on V15 domain in FPM */
PMC_LVR5V_FPM_FLAG = PMC_LVSCR_LVR5V_FPM_FLAG_MASK, /**< Low voltage reset flag of V5 domain in FPM */
PMC_LVR5V_RPM_FLAG = PMC_LVSCR_LVR5V_RPM_FLAG_MASK, /**< Low voltage reset flag of V5 domain in RPM */
PMC_LVR2P5V_FPM_FLAG = PMC_LVSCR_LVR2P5V_FPM_FLAG_MASK, /**< Low voltage reset flag of V25 domain in FPM */
PMC_LVR2P5V_RPM_FLAG = PMC_LVSCR_LVR2P5V_RPM_FLAG_MASK, /**< Low voltage reset flag of V25 domain in RPM */
PMC_LVR1P1V_FPM_FLAG = PMC_LVSCR_LVR1P1V_FPM_FLAG_MASK, /**< Low voltage reset flag of V11 domain in FPM */
PMC_LVR1P1V_RPM_FLAG = PMC_LVSCR_LVR1P1V_RPM_FLAG_MASK, /**< Low voltage reset flag of V11 domain in RPM */
PMC_POR_FLAG = PMC_LVSCR_POR_FLAG_MASK /**< POR flag */
} PMC_FlagType;
/**
* @brief PMC voltage status.
*
*/
typedef enum
{
PMC_HVD5V_STATUS = PMC_LVSCR_HVD5V_STATUS_MASK, /**< HVD5V status on V5 domain in FPM */
PMC_HVD2P5V_STATUS = PMC_LVSCR_HVD2P5V_STATUS_MASK, /**< HVD25 status on V25 domain in FPM */
PMC_HVD1P1V_STATUS = PMC_LVSCR_HVD1P1V_STATUS_MASK, /**< HVD11 status on V11 domain in FPM */
PMC_LVD5V_STATUS = PMC_LVSCR_LVD5V_STATUS_MASK, /**< LVD5V status on V5 domain in FPM */
PMC_LVD1P5V_STATUS = PMC_LVSCR_LVD1P5V_STATUS_MASK, /**< LVD1P5V status on V15 domain in FPM */
PMC_HVD1P5V_STATUS = PMC_LVSCR_HVD1P5V_STATUS_MASK, /**< HVD1P5V status on V15 domain in FPM */
PMC_V15_LDO_STATUS = PMC_LVSCR_V15_STATUS(0U), /**< V15 is working on internal V15 LDO */
PMC_V15_ON_BOARD_NPN_STATUS = PMC_LVSCR_V15_STATUS(1U), /**< V15 is working on internal V15 controller with on board NPN */
PMC_V15_DRIVEN_BY_EXTERNAL_STATUS = PMC_LVSCR_V15_STATUS(2U) /**< V15 is driven by external driver such as on board DCDC, V15_CFG PAD is driven high */
} PMC_StatusType;
typedef void (*PMC_VolIntCallbackType)(void);
/** @brief Pmc control type */
typedef struct
{
boolean bLvdIntEn; /**< bit9, low voltage detect interrupt enable */
boolean bHvdIntEn; /**< bit8, high voltage detect interrupt enable */
boolean b5VBMonEn; /**< bit6, VDD5V_B LVR monitor enable during RPM */
boolean bV15CtrlEn; /**< bit5, V15 controller with on board NPN enable */
boolean bV15AutoswEn; /**< bit4, V15 auto switch enable */
boolean bRpmV25En; /**< bit3, V25 domain enable during RPM */
PMC_VolIntCallbackType pIsrNotify; /**< interrupt notification */
} PMC_CtrlType;
/***************** macro *********************/
/**< All flags of LVCSR MSASK */
#define PMC_LVCSR_ALLFLAG_MASK (uint32_t)(PMC_LVSCR_HVD5V_FLAG_MASK|\
PMC_LVSCR_HVD2P5V_FLAG_MASK|\
PMC_LVSCR_HVD1P1V_FLAG_MASK|\
PMC_LVSCR_LVD5V_FLAG_MASK|\
PMC_LVSCR_LVD1P5V_FLAG_MASK|\
PMC_LVSCR_HVD1P5V_FLAG_MASK|\
PMC_LVSCR_LVR5V_FPM_FLAG_MASK|\
PMC_LVSCR_LVR5V_RPM_FLAG_MASK|\
PMC_LVSCR_LVR2P5V_FPM_FLAG_MASK|\
PMC_LVSCR_LVR2P5V_RPM_FLAG_MASK|\
PMC_LVSCR_LVR1P1V_FPM_FLAG_MASK|\
PMC_LVSCR_LVR1P1V_RPM_FLAG_MASK|\
PMC_LVSCR_POR_FLAG_MASK)
#define PMC_LVCSR_ALLSTATUS_MASK (uint32_t)(PMC_LVSCR_HVD5V_STATUS_MASK|\
PMC_LVSCR_HVD2P5V_STATUS_MASK|\
PMC_LVSCR_HVD1P1V_STATUS_MASK|\
PMC_LVSCR_LVD5V_STATUS_MASK|\
PMC_LVSCR_LVD1P5V_STATUS_MASK|\
PMC_LVSCR_HVD1P5V_STATUS_MASK|\
PMC_LVSCR_V15_STATUS_MASK)
/***************** API *********************/
/**
* @brief Get LVCSRRegister Value
*
* @return uint32_t LVCSRRegister Value
*/
uint32_t PMC_GetLVCSRRegister(void);
/**
* @brief Get All voltage flag
*
* @return uint32_t All voltage flag
*/
uint32_t PMC_GetAllVolFlag(void);
/**
* @brief Get specific voltage flag
*
* @param eFlag Voltage flag
* @return boolean If return true, the specific voltage flag is 0, otherwise, the flag is 1.
*/
boolean PMC_GetSpecificVolFlag(const PMC_FlagType eFlag);
/**
* @brief Clear all voltage flag
*
*/
void PMC_ClearAllVolFlag(void);
/**
* @brief Clear specific voltage flag
*
* @param eFlag Voltage flag
*/
void PMC_ClearSpecificVolFlag(const PMC_FlagType eFlag);
/**
* @brief Get All voltage status
*
* @return uint32_t All voltage status
*/
uint32_t PMC_GetAllVolStatus(void);
/**
* @brief Get specific voltage status
*
* @param eStatus Specific voltage status
* @return boolean If return true, the specific voltage status is 0, otherwise, the status is 1.
*/
boolean PMC_GetSpecificVolStatus(const PMC_StatusType eStatus);
/**
* @brief Configure Voltage
*
* @param pCtrl Configuration of voltage
*/
void PMC_ConfigVoltage(const PMC_CtrlType *const pCtrl);
/**
* @brief Clear all PMC register
*
*/
void PMC_Deinit(void);
#if defined(__cplusplus)
}
#endif
/** @}*/ /* fc7xxx_driver_pmc */
#endif

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/**
* @file fc7xxx_driver_port.h
* @author Flagchip
* @brief FC7xxx PORT driver type definition and API
* @version 0.1.0
* @date 2023-2-14
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022/12/31 Flagchip0121 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_PORT_H_
#define _DRIVER_FC7XXX_DRIVER_PORT_H_
#include "HwA_port.h"
#include <stddef.h>
/**
* @addtogroup fc7xxx_driver_port
* @{
*/
/********* global define ************/
/** @brief Max number of Port */
#define MAX_PORT_NUM 5U
/** @brief Max number of Port Pin */
#define PORT_PIN_NUM_MAX (uint32_t)(MAX_PORT_NUM*PORT_PCR_COUNT)
/** @brief number of Port Pin */
#define PORT_PIN_NUM(port,pin) (((uint32_t)(port) << 5U)+(uint32_t)(pin))
#define PORT_PIN_0 ((uint32_t)0x00000001) /**< PORT Pin 0 select */
#define PORT_PIN_1 ((uint32_t)0x00000002) /**< PORT Pin 1 select */
#define PORT_PIN_2 ((uint32_t)0x00000004) /**< PORT Pin 2 select */
#define PORT_PIN_3 ((uint32_t)0x00000008) /**< PORT Pin 3 select */
#define PORT_PIN_4 ((uint32_t)0x00000010) /**< PORT Pin 4 select */
#define PORT_PIN_5 ((uint32_t)0x00000020) /**< PORT Pin 5 select */
#define PORT_PIN_6 ((uint32_t)0x00000040) /**< PORT Pin 6 select */
#define PORT_PIN_7 ((uint32_t)0x00000080) /**< PORT Pin 7 select */
#define PORT_PIN_8 ((uint32_t)0x00000100) /**< PORT Pin 8 select */
#define PORT_PIN_9 ((uint32_t)0x00000200) /**< PORT Pin 9 select */
#define PORT_PIN_10 ((uint32_t)0x00000400) /**< PORT Pin 10 select */
#define PORT_PIN_11 ((uint32_t)0x00000800) /**< PORT Pin 11 select */
#define PORT_PIN_12 ((uint32_t)0x00001000) /**< PORT Pin 12 select */
#define PORT_PIN_13 ((uint32_t)0x00002000) /**< PORT Pin 13 select */
#define PORT_PIN_14 ((uint32_t)0x00004000) /**< PORT Pin 14 select */
#define PORT_PIN_15 ((uint32_t)0x00008000) /**< PORT Pin 15 select */
#define PORT_PIN_16 ((uint32_t)0x00010000) /**< PORT Pin 16 select */
#define PORT_PIN_17 ((uint32_t)0x00020000) /**< PORT Pin 17 select */
#define PORT_PIN_18 ((uint32_t)0x00040000) /**< PORT Pin 18 select */
#define PORT_PIN_19 ((uint32_t)0x00080000) /**< PORT Pin 19 select */
#define PORT_PIN_20 ((uint32_t)0x00100000) /**< PORT Pin 20 select */
#define PORT_PIN_21 ((uint32_t)0x00200000) /**< PORT Pin 21 select */
#define PORT_PIN_22 ((uint32_t)0x00400000) /**< PORT Pin 22 select */
#define PORT_PIN_23 ((uint32_t)0x00800000) /**< PORT Pin 23 select */
#define PORT_PIN_24 ((uint32_t)0x01000000) /**< PORT Pin 24 select */
#define PORT_PIN_25 ((uint32_t)0x02000000) /**< PORT Pin 25 select */
#define PORT_PIN_26 ((uint32_t)0x04000000) /**< PORT Pin 26 select */
#define PORT_PIN_27 ((uint32_t)0x08000000) /**< PORT Pin 27 select */
#define PORT_PIN_28 ((uint32_t)0x10000000) /**< PORT Pin 28 select */
#define PORT_PIN_29 ((uint32_t)0x20000000) /**< PORT Pin 29 select */
#define PORT_PIN_30 ((uint32_t)0x40000000) /**< PORT Pin 30 select */
#define PORT_PIN_31 ((uint32_t)0x80000000) /**< PORT Pin 31 select */
#define PORT_DWP_CPU0_ALLOWED ((uint32_t)0x00000001) /**< Only CPU0 is allowed to write PCR and GPIO register corresponding to this pin. */
#define PORT_DWP_DMA0_ALLOWED ((uint32_t)0x00000008) /**< Only DMA0 is allowed to write PCR and GPIO register corresponding to this pin. */
#define PORT_DWP_FlexCore_ALLOWED ((uint32_t)0x00000010) /**< Only DMA1 is allowed to write PCR and GPIO register corresponding to this pin. */
/** @brief Port Alternate 0 Mode */
#define PORT_ALT0_FUNC_MODE ((Port_PinModeType)0)
/** @brief Port GPIO Mode */
#define PORT_GPIO_MODE ((Port_PinModeType)1)
/** @brief Port Alternate 2 Mode */
#define PORT_ALT2_FUNC_MODE ((Port_PinModeType)2)
/** @brief Port Alternate 3 Mode */
#define PORT_ALT3_FUNC_MODE ((Port_PinModeType)3)
/** @brief Port Alternate 4 Mode */
#define PORT_ALT4_FUNC_MODE ((Port_PinModeType)4)
/** @brief Port Alternate 5 Mode */
#define PORT_ALT5_FUNC_MODE ((Port_PinModeType)5)
/** @brief Port Alternate 6 Mode */
#define PORT_ALT6_FUNC_MODE ((Port_PinModeType)6)
/** @brief Port Alternate 7 Mode */
#define PORT_ALT7_FUNC_MODE ((Port_PinModeType)7)
/********* global typedef ************/
/** @brief Port return structure */
typedef enum
{
PORT_STATUS_SUCCESS = 0U,
PORT_STATUS_PARAM_INVALID = 1U
} PORT_StatusType;
/** @brief Port instance number */
typedef enum
{
PORT_A = 0U,
PORT_B,
PORT_C,
PORT_D,
PORT_E
} PORT_InstanceType;
typedef enum
{
PORT_TRIGGER_DISABLE = 0U,
PORT_TRIGGER_INPUT_CONSISTENT_WITH_PAD = 1U,
PORT_TRIGGER_INPUT_OPPOSITE_WITH_PAD = 2U
} PORT_TriggerInputType;
/** @brief Port interrupt notification type */
typedef void (*PORT_PinInterruptCallBackType)(void);
/** @brief Port initialization structure */
typedef struct
{
uint32_t u32PortPins; /**< Port pin, 0~31 bit indicates the pin 0~31 */
Port_PinMuxType uPortPinMux; /**< Port pin mode */
PORT_TriggerInputType eTriggrtMode; /**< Port trigger mode */
bool bPullEn; /**< whether to pull the port pin */
PORT_PullStatusType ePullSel; /**< pull status, pull up or pull down */
bool bDrvStrength0En; /**< whether to enable pad drive strength 0 , only hs PAD used */
bool bDrvStrength1En; /**< whether to enable pad drive strength 1, only uhs PAD used */
bool u8PassiveFilterEn; /**< whether to use passive filter, please refer to reference manual for details */
} PORT_InitType;
/** @brief Port interrupt configuration structure */
typedef struct
{
uint32_t u32PortPins; /**< Port pin, 0~31 bit indicates the pin 0~31 */
PORT_IntConfigType ePortIsrMode; /**< Port interrupt mode */
PORT_PinInterruptCallBackType pIsrNotify; /**< Port interrupt notification pointer */
} PORT_InterruptType;
/** @brief Port digital filter configuration structure */
typedef struct
{
uint32_t u32PortPinsEn; /**< Port pin, 0~31 bit indicates the pin 0~31 */
PORT_DigitalFilterClkSrcType eClkSrc; /**< Port clock source */
uint8_t u8FilterLength; /**< digital filter length, the range is :0~31 */
} PORT_DigitalFilterType;
/********* global API ************/
/**
* @brief Initialize port pins
*
* @param ePort Port instance
* @param pInitStruct Initialization structure of port
* @return Port return type.
*/
PORT_StatusType PORT_InitPins(const PORT_InstanceType ePort, const PORT_InitType *const pInitStruct);
/**
* @brief De-initialize the Port instance
*
* @param ePort Port instance enumeration
* @param u32Pins The bit of u32Pins indicate the Pin number of this Port.
* @return Port return type.
*/
PORT_StatusType PORT_Deinit(const PORT_InstanceType ePort, const uint32_t u32Pins);
/**
* @brief Enable interrupt function of port
*
* @param ePort Port instance enumeration
* @param pIntStruct Interrupt structure of port.
* @return Port return type.
*/
PORT_StatusType PORT_InitInterrupt(const PORT_InstanceType ePort, const PORT_InterruptType *const pIntStruct);
/**
* @brief Enable interrupt function of port
*
* @param ePort Port instance enumeration
* @param u32Pins The bit of u32Pins indicate the Pin number of this Port.
* @return Port return type.
*/
PORT_StatusType PORT_EnableInterrupt(const PORT_InstanceType ePort, const uint32_t u32Pins);
/**
* @brief Disable interrupt function of port
*
* @param ePort Port instance enumeration
* @param u32Pins The bit of u32Pins indicate the Pin number of this Port.
* @return Port return type.
*/
PORT_StatusType PORT_DisableInterrupt(const PORT_InstanceType ePort, const uint32_t u32Pins);
PORT_StatusType PORT_SetPinsDmaReqMode(const PORT_InstanceType ePort, const uint32_t u32Pins, const PORT_DMAReqType eDMAReqMode);
/**
* @brief Initialize digital filter for Port instance
*
* @param ePort Port instance enumeration
* @param pDFStruct Digital filter initialization structure of port
* @return Port return type.
*/
PORT_StatusType PORT_InitDigitalFilterPort(const PORT_InstanceType ePort,
const PORT_DigitalFilterType *pDFStruct);
/**
* @brief De-initialize digital filter for Port instance
*
* @param ePort Port instance enumeration
* @return Port return type.
*/
PORT_StatusType PORT_DeinitDigitalFilterPort(const PORT_InstanceType ePort);
/**
* @brief Enable the digital filter function for the specific pin.
*
* @param ePort Port instance enumeration
* @param u32Pins The bit of u32Pins indicate the Pin number of this Port.
* @return Port return type.
*/
PORT_StatusType PORT_EnableDigitalFilterPin(const PORT_InstanceType ePort, const uint32_t u32Pins);
/**
* @brief Disable the digital filter function for the specific pin.
*
* @param ePort Port instance enumeration
* @param u32Pins The bit of u32Pins indicate the Pin number of this Port.
* @return Port return type.
*/
PORT_StatusType PORT_DisableDigitalFilterPin(const PORT_InstanceType ePort, const uint32_t u32Pins);
/** @}*/ /* fc7xxx_driver_port */
#endif

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/**
* @file fc7xxx_driver_ptimer.h
* @author Flagchip0126
* @brief FC7xxx PTIMER driver type definition and API
* @version 0.1.0
* @date 2024-01-15
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_PTIMER_H_
#define _DRIVER_FC7XXX_DRIVER_PTIMER_H_
#include "device_header.h"
#include "HwA_ptimer.h"
#include "HwA_scm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_ptimer
* @{
*/
/**
* @brief PTIMER interrupt callback function prototype
*
*/
typedef void (*PTIMER_InterruptCallbackType)(void);
/**
* @brief PTIMER sequence error callback function prototype
*
*/
typedef void (*PTIMER_SeqErrorCallbackType)(uint8_t u8Channel);
/**
* @brief The instance index of the PTIMER peripheral
*
*/
typedef enum
{
PTIMER_INSTANCE_0 = 0U,
PTIMER_INSTANCE_1 = 1U
} PTIMER_InstanceType;
/**
* @brief Ptimer instance initialization parameters
*
*/
typedef struct
{
PTIMER_LoadValueModeType eLoadValueMode; /*!< Select the load mode */
PTIMER_ClockPreDividerType eClkPreDiv; /*!< Select the prescaler divider */
PTIMER_ClockPreDivMultiplyFactorType eClkPreMultFactor; /*!< Select multiplication factor for prescaler */
PTIMER_TrgSrcType eTriggerInput; /*!< Select the trigger input source */
bool bContinuousModeEnable; /*!< Enable the continuous mode */
bool bDmaEnable; /*!< Enable the dma for timer */
} PTIMER_InitType;
/**
* @brief Ptimer interrupt configuration parameters
*
*/
typedef struct
{
bool bDelayIntEnable; /*!< Enable the interrupt for timer */
uint32_t u32IntDelayPeriodUs; /*!< The period in micro second */
PTIMER_InterruptCallbackType pIntNotify; /*!< Ptimer interrupt callback function pointer */
bool bSeqErrIntEnable; /*!< Enable PTIMER Sequence Error Interrupt */
PTIMER_SeqErrorCallbackType pSeqErrorNotify; /*!< Ptimer sequence error callback function pointer */
} PTIMER_InterruptType;
/**
* @brief Ptimer channel configuration parameters
*
*/
typedef struct
{
uint32_t u32DelayUs; /*!< Setting pre_trigger's delay in microsecond. */
bool bPreTriggerEnable; /*!< Enable the pre_trigger. */
bool bPreTriggerOutputEnable; /*!< Enable the pre_trigger output. */
bool bPreTriggerBackToBackEnable; /*!< Enable the back to back mode for ADC pre_trigger. */
} PTIMER_ChannelCfgType;
/**
* @brief Ptimer pulse out configgurations
*
* When the Ptimer counter time reaches u32PulseOutDlyHighUs, the pulse-out goes high;
* When the Ptimer counter time reaches u32PulseOutDlyLowUs, the pulse-out goes low.
*
*/
typedef struct
{
uint32_t u32PulseOutDlyHighUs; /*!< Microsecond delay for pulse out to output high */
uint32_t u32PulseOutDlyLowUs; /*!< Microsecond delay for pulse out to output low */
} PTIMER_PulseOutType;
/**
* @brief Initialize the Ptimer instance
*
* @param eInstance the Ptimer instance to use
* @param pInitCfg the Ptimer initialization parameters
*/
void PTIMER_Init(const PTIMER_InstanceType eInstance, const PTIMER_InitType *const pInitCfg);
/**
* @brief De-initialize the Ptimer instance
* Disable the Ptimer instance and reset the configurations to its reset values
*
* @param eInstance the Ptimer instance to use
*/
void PTIMER_DeInit(const PTIMER_InstanceType eInstance);
/**
* @brief Initialize the Ptimer interrupt
*
* @note the interrupt delay value is buffered and will take effect only after called PTIMER_LoadValue()
* function.
*
* @param eInstance the Ptimer instance to configure
* @param pInterruptCfg the Ptimer initialization parameters
*/
void PTIMER_InitInterrupt(const PTIMER_InstanceType eInstance,
const PTIMER_InterruptType *const pInterruptCfg);
/**
* @brief Initialize the Ptimer channels
*
* @note the channel delay value is buffered and will take effect only after called PTIMER_LoadValue()
* function.
*
* @param eInstance the Ptimer instance to use
* @param aChannelCfg the array of channels to config
* @param u8ChnNum the channel numbers in the channel array
*/
void PTIMER_InitChannel(const PTIMER_InstanceType eInstance,
const PTIMER_ChannelCfgType aChannelCfg[], const uint8_t u8ChnNum);
/**
* @brief Set the Ptimer max counter period in microsecond
* When the Ptimer counter reaches the period, it will return to zero
*
* @note the period parameter is buffered and will take effect only after called PTIMER_LoadValue()
* function.
*
* @param eInstance the Ptimer instance to use
* @param u32PeriodUs the max counter period in microsecond
*/
void PTIMER_SetPeriod(const PTIMER_InstanceType eInstance, uint32_t u32PeriodUs);
/**
* @brief Set the Ptimer pulse-out function
*
* @note the pulse-out delay values are buffered and will take effect only after called PTIMER_LoadValue()
* function.
*
* @param eInstance the Ptimer instance to use
* @param pPulseOutCfg the pulse-out configuration
*/
void PTIMER_SetPulseOut(const PTIMER_InstanceType eInstance, const PTIMER_PulseOutType *pPulseOutCfg);
/**
* @brief Load the buffered values into register
*
* Some Ptimer registers are buffered and will only take effect after called
* this function
*
* @param eInstance the Ptimer instance to use
*/
void PTIMER_LoadValue(const PTIMER_InstanceType eInstance);
/**
* @brief Enable the Ptimer instance
*
* @param eInstance the Ptimer instance to use
*/
void PTIMER_Enable(const PTIMER_InstanceType eInstance);
/**
* @brief Disable the Ptimer instance
*
* @param eInstance the Ptimer instance to use
*/
void PTIMER_Disable(const PTIMER_InstanceType eInstance);
/**
* @brief Enable the Ptimer pulse-out function
*
* @param eInstance the Ptimer instance to use
*/
void PTIMER_EnablePulseOut(const PTIMER_InstanceType eInstance);
/**
* @brief Disable the Ptimer pulse-out function
*
* @param eInstance the Ptimer instance to use
*/
void PTIMER_DisablePulseOut(const PTIMER_InstanceType eInstance);
void PTIMER_SelectInstance01BackToBackMode(SCM_PTimerLMSelType ePTimerLoopMode);
/**
* @brief Generate the software trigger signal for the Ptimer instance
*
* If the Ptimer trigger source is selected as PTIMER_TRGSRC_SW, call this function
* will make the Ptimer instance to start.
*
* @param eInstance the Ptimer instance to use
*/
void PTIMER_GenerateSWTrigger(const PTIMER_InstanceType eInstance);
/** @}*/ /* fc7xxx_driver_ptimer */
#if defined(__cplusplus)
}
#endif
#endif

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/**
* @file fc7xxx_driver_rgm.h
* @author Flagchip
* @brief FC7xxx RGM driver type definition and API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_RCM_H_
#define _DRIVER_FC7XXX_DRIVER_RCM_H_
#include "HwA_rgm.h"
/**
* @addtogroup fc7xxx_driver_rcgm
* @{
*/
/** @brief Get which core currently belongs to. */
#define GET_CORE_NUM (*(uint32_t *)0xE0080004)
/** @brief Rgm return type. */
typedef enum
{
RGM_STATUS_SUCCESS = 0U,
RGM_STATUS_PARAM_INVALID = 1U,
RGM_STATUS_COREID_INVALID = 2U
} RGM_StatusType;
/** @brief Rgm reset pin filter clock type. */
typedef enum
{
RGM_RESET_FILTER_BUS_CLOCK = 0U,
RGM_RESET_FILTER_AON32K_CLOCK = 1U
} RGM_FilterClkSrc;
/** @brief Rgm interrupt notification type */
typedef void (*RGM_InterruptCallBackType)(uint32_t u32SRS);
/**
* @brief This api can get RGM_SRS register that indicate the source of the most recent reset.
*
* @return RGM->RGM_SRS register, bit 0-15,29-31 corresponding to RGM_ResetEventType, refer to reference manual for details.
* @note Multiple flags can be set if multiple reset events occur at the same time
*/
uint32_t RGM_GetLastResetFLag(void);
/**
* @brief This api can get RGM_SSRS register that indicate all reset sources since the last POR or LVD that have not been cleared by software.
*
* @returnRGM->RGM_SSRS register, bit 0-15,29-31 corresponding to RGM_ResetEventType, refer to reference manual for details.
*/
uint32_t RGM_GetAllResetFlag(void);
/**
* @brief This api can clear reset flag of RGM_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
*
* @param eReset Enumeration of reset event flag
*/
void RGM_ClearResetFlagAfterPOR(const RGM_ResetEventType eReset);
/**
* @brief This api can clear all reset flag of RGM_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
*
*/
void RGM_ClearAllResetFlagAfterPOR(void);
/**
* @brief Enable reset pin filter
*
* @param eClk Reset pin filter clock source
* @param u8BusClockFilterWidth Bus clock filter width
* @param bLpClkEn select whether enable reset pin filter using AON32clock in low power mode
* @return RGM return type
* @note If use AON32K clock, A reset signal whose length is less than 2 AON32K clock periods will be filtered
*/
RGM_StatusType RGM_EnableResetFilter(RGM_FilterClkSrc eClk, uint8_t u8BusClockFilterWidth, bool bLpClkEn);
/**
* @brief Disable reset pin filter
*
* @param eClk Reset pin filter clock source
* @param bLpClkEn select whether disable reset pin filter using AON32clock in low power mode
* @return RGM return type
*/
RGM_StatusType RGM_DisableResetFilter(RGM_FilterClkSrc eClk, bool bLpClkEn);
/**
* @brief This api can enable interrupt before an system reset appear.
*
* @param eDelay Enumeration of delay cycles
* @param eResetInterrupt Reset event flag, like: RGM_INT_CLKERR0 | RGM_INT_FCSMU
* @return RGM return type
*/
RGM_StatusType RGM_EnableSystemResetInt(RGM_ResetDelayType eDelay, RGM_ResetIntMangerType eResetInterrupt);
/**
* @brief This api can disable interrupt before an system reset appear.
*
* @param eResetInterrupt Reset event flag, like: RGM_INT_CLKERR0 | RGM_INT_FCSMU
* @param bClearDelay Whether to clear delay configuration
* @return RGM return type
*/
RGM_StatusType RGM_DisableSystemResetInt(RGM_ResetIntMangerType eResetInterrupt, bool bClearDelay);
/**
* @brief Generate software reset through cotex-m register
*
*/
void RGM_GenerateSwReset(void);
/**
* @brief This api can enable interrupt before an CPU0 core related reset appear.
*
* @param eCPU0Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST
* @param pIsrNotify Interrupt function
* @return RGM return type
*/
RGM_StatusType RGM_EnableCPU0CoreResetInt(RGM_CPUIntMangerType eCPU0Interrupt,RGM_InterruptCallBackType pIsrNotify);
/**
* @brief This api can disable interrupt before an CPU0 core related reset appear.
*
* @param eCPU0Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST
* @return RGM return type
*/
RGM_StatusType RGM_DisableCPU0CoreResetInt(RGM_CPUIntMangerType eCPU0Interrupt);
/**
* @brief Get the CPU0 exit reset flag
*
* @return RGM_CPU_OUT_RST_UNDER CPU0 is under reset
* @return RGM_CPU_OUT_RST_OUT CPU0 is out of reset
*/
RGM_CPUOutResetType RGM_GetCPU0OutResetFlag(void);
/**
* @brief Generate a CPU0 software reset.
*
*/
void RGM_GenerateCPU0SwReset(void);
/**
* @brief This api can get RGM_C0_SRS register that indicate the source of the most recent CPU0 reset.
*
* @return RGM->RGM_C0_SRS register, bit 0-20 corresponding to RGM_ResetEventType, refer to reference manual for details.
* @note Multiple flags can be set if multiple reset events occur at the same time
*/
uint32_t RGM_GetCPU0LastResetFLag(void);
/**
* @brief This api can get RGM_C0_SSRS register that indicate all CPU0 reset sources since the last POR or LVD that have not been cleared by software.
*
* @returnRGM->RGM_C0_SSRS register, bit 0-20,29-31 corresponding to RGM_CPUResetEventType, refer to reference manual for details.
*/
uint32_t RGM_GetCPU0AllResetFlag(void);
/**
* @brief This api can clear reset flag of RGM_C0_SSRS register which indicate CPU0 all reset sources since the last POR or LVD that have not been cleared by software.
*
* @param eReset Enumeration of reset event flag
*/
void RGM_ClearCPU0ResetFlagAfterPOR(const RGM_CPUResetEventType eReset);
/**
* @brief This api can clear all reset flag of RGM_C0_SSRS register which indicate CPU0 all reset sources since the last POR or LVD that have not been cleared by software.
*
*/
void RGM_ClearCPU0AllResetFlagAfterPOR(void);
/** @}*/ /* fc7xxx_driver_rgm */
#endif /* end of _DRIVER_FC7XXX_DRIVER_RGM_H_ */

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/**
* @file fc7xxx_driver_rtc.h
* @author Flagchip
* @brief FC7xxx rtc driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240
********************************************************************************/
#ifndef DRIVER_INCLUDE_FC7XXX_DRIVER_RTC_H_
#define DRIVER_INCLUDE_FC7XXX_DRIVER_RTC_H_
#include"HwA_rtc.h"
/**
* @addtogroup fc7xxx_driver_rtc
* @{
*/
/** @brief Rtc return type. */
typedef enum
{
RTC_STATUS_SUCCESS = 0U, /**< rtc status is success */
RTC_STATUS_PARAM_INVALID = 1U, /**< rtc status is failed because the param is invalid */
RTC_STATUS_FUNCTION_ERROR = 2U, /**< rtc status is failed because the function is error */
RTC_STATUS_CLOCK_INVALID = 3U /**< rtc status is failed because the clock is invalid */
} RTC_StatusType;
/** @brief Rtc mode */
typedef enum
{
RTC_ALARM_INT = 0U, /**< rtc interrupt mode is alarm */
RTC_SECOND_INT = 1U, /**< rtc interrupt mode is second */
RTC_OVERFLOW_INT = 2U /**< rtc interrupt mode is overflow */
} RTC_IntEventType;
/** @brief Rtc interrupt notification type */
typedef void (*RTC_InterruptCallBackType)(void);
/** @brief Rtc interrupt configuration type */
typedef struct
{
bool bAlarmIntEn; /**< whether enable rtc alarm interrupt */
RTC_InterruptCallBackType pIsrAlarmNotify; /**< rtc alarm notification function pointer */
bool bSecondIntEn; /**< whether to use the second interrupt */
RTC_InterruptCallBackType pIsrSecondNotify; /**< second interrupt notification function pointer */
bool bOverflowIntEn ; /**< overflow interrupt notification function pointer */
RTC_InterruptCallBackType pIsrOverflowNotify; /**< overflow interrupt notification function pointer */
} RTC_InterruptType;
/** @brief Rtc initialization type */
typedef struct
{
uint32_t u32AlarmValue; /**< rtc alarm value */
RTC_ClkoutSecIntFreqType eSecIntAndClkoutFreq; /**< Select the RTC Seconds interrupt and the RTC_CLKOUT prescaler output frequency */
bool bStableClkoutFreq; /**< Select the RTC Seconds interrupt and the RTC_CLKOUT prescaler output frequency or RTC_CLKOUT is from the 32.768 kHz clock. */
} RTC_InitType;
/* global functions */
/**
* @brief Initialize Rtc instance
* @param pInitStruct Rtc initialization structure
*/
void RTC_Init(const RTC_InitType *const pInitStruct);
/**
* @brief Rtc set interrupt
*
* @param pIntStruct interrupt structure pointer
* @return Rtc return type
* @note this function will stop Rtc timer
*/
RTC_StatusType RTC_InitInterrupt(const RTC_InterruptType *const pIntStruct);
/**
* @brief De-initialize Rtc instance
*
*/
void RTC_Deinit(void);
/**
* @brief Rtc enable interrupt
*
* @param bAlarmIntEn whether enable alarm interrupt
* @param bSecondIntEn whether enable second interrupt
*/
void RTC_EnableInterrupt(const bool bAlarmIntEn, const bool bSecondIntEn, const bool bOverflowIntEn);
/**
* @brief Rtc disable interrupt
*
* @param bAlarmIntEn whether disable alarm interrupt
* @param bSecondIntEn whether disable second interrupt
*/
void RTC_DisableInterrupt(const bool bAlarmIntEn, const bool bSecondIntEn, const bool boverflowIntEn);
/**
* @brief Rtc start
*
*/
void RTC_Start(void);
/**
* @brief Rtc stop
*
*/
void RTC_Stop(void);
/**
* @brief Rtc alarm value
*
* @param u32AlarmValue Input value
*/
void RTC_UpdateAlarmValue(const uint32_t u32AlarmValue);
/**
* @brief Get Rtc counter value
*
* @return Rtc counter value
*/
uint32_t RTC_GetTime(void);
/**
* @brief Check RTC overflow flag
*
* @return Overflow flag
*/
bool RTC_CheckOverflowFlag(void);
/**
* @brief Set second counter value
* @param u32Value the second value.
* */
void RTC_SetSecondCounterValue(uint32_t u32Value);
/** @}*/ /* fc7xxx_driver_rtc */
#endif /* DRIVER_INCLUDE_FC7XXX_DRIVER_RTC_H_ */

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/**
* @file fc7xxx_driver_scg.h
* @author Flagchip085
* @brief FC7xxx SCG driver type definition and API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_SCG_H_
#define _DRIVER_FC7XXX_DRIVER_SCG_H_
#include "HwA_scg.h"
#include "HwA_csc.h"
/**
* @addtogroup fc7xxx_driver_scg
* @{
*/
/** @brief clock list for internal clock tree */
typedef enum
{
/* Main clocks */
SCG_CORE_CLK = 0U, /*!< Core clock */
SCG_BUS_CLK = 1U, /*!< Bus clock */
SCG_SLOW_CLK = 2U, /*!< Slow clock */
/* Other internal clocks used by peripherals. */
SCG_FOSC_CLK = 3U, /*!< FOSC clock */
SCG_FIRC_CLK = 4U, /*!< FIRC clock */
SCG_PLL0_CLK = 5U, /*!< PLL0 clock */
SCG_PLL1_CLK = 6U, /*!< PLL1 clock */
SCG_SIRC_CLK = 7U, /*!< SIRC clock */
SCG_SIRC32K_CLK = 8U, /*!< SIRC32K clock */
SCG_SOSC_CLK = 9U, /*!< SOSC clock */
SCG_SCG_CLKOUT_CLK = 10U, /*!< SCG CLK_OUT clock */
SCG_SIRCDIVH_CLK = 11U, /*!< SIRCDIVH functional clock */
SCG_SIRCDIVM_CLK = 12U, /*!< SIRCDIVM functional clock */
SCG_SIRCDIVL_CLK = 13U, /*!< SIRCDIVL functional clock */
SCG_FIRCDIVH_CLK = 14U, /*!< FIRCDIVH functional clock */
SCG_FIRCDIVM_CLK = 15U, /*!< FIRCDIVM functional clock */
SCG_FIRCDIVL_CLK = 16U, /*!< FIRCDIVL functional clock */
SCG_FOSCDIVH_CLK = 17U, /*!< FOSCDIVH functional clock */
SCG_FOSCDIVM_CLK = 18U, /*!< FOSCDIVM functional clock */
SCG_FOSCDIVL_CLK = 19U, /*!< FOSCDIVL functional clock */
SCG_PLL0DIVH_CLK = 20U, /*!< PLL0DIVH functional clock */
SCG_PLL0DIVM_CLK = 21U, /*!< PLL0DIVM functional clock */
SCG_PLL0DIVL_CLK = 22U, /*!< PLL0DIVL functional clock */
SCG_PLL1DIVH_CLK = 23U, /*!< PLL1DIVH functional clock */
SCG_PLL1DIVM_CLK = 24U, /*!< PLL1DIVM functional clock */
SCG_PLL1DIVL_CLK = 25U, /*!< PLL1DIVL functional clock */
SCG_NVMINIT_CLK = 26U, /*!< NVM initial clock source */
SCG_CMU4REF_CLK = 27U, /*!< CMU4 reference clock */
SCG_END_OF_CLOCKS = 28U /*!< End of SCG clocks */
} SCG_ClkSrcType;
/**
* @brief PLL clock type
*/
typedef enum
{
SCG_PLL0 = 0U, /*!< PLL0 clock */
SCG_PLL1 = 1U /*!< PLL1 clock */
} SCG_PllClkType;
/**
* @brief indicate the clock function status
*
*/
typedef enum
{
SCG_STATUS_SUCCESS = 0U, /*!< function called success */
SCG_STATUS_SEQUENCE_ERROR = 1U, /*!< function called report sequence error */
SCG_STATUS_TIMEOUT = 2U, /*!< function called report timeout error */
SCG_STATUS_IRC_ERROR = 3U, /*!< function called report internal clock error */
SCG_STATUS_PARAM_ERROR = 4U /*!< function called report internal clock error */
} SCG_StatusType;
/**
* @brief indicate the CRC check result
*
*/
typedef enum
{
SCG_CRC_CHECK_SUCCESS = 0U, /*!< CRC check success *//**< SCG_CRC_CHECK_SUCCESS */
SCG_CRC_GEN_TIMEOUT = 1U, /*!< CRC Generate Timeout *//**< SCG_CRC_GEN_TIMEOUT */
SCG_CRC_CHECK_FAILED = 2U /*!< CRC check failed */ /**< SCG_CRC_CHECK_FAILED */
} SCG_CrcCheckResType;
/**
* @brief SCG xxxIRC TRIMSRC type.
*/
typedef enum
{
SCG_IRC_TRIMSRC_RESERVE0 = 0U, /*!< Clock Trim source reserve0 */
SCG_IRC_TRIMSRC_RESERVE1 = 1U, /*!< Clock Trim source reserve1 */
SCG_IRC_TRIMSRC_FOSC = 2U, /*!< Clock Trim source FOSC */
SCG_IRC_TRIMSRC_SOSC = 3U, /*!< Clock Trim source SOSC */
} SCG_IrcTrimSrcType;
/**
* @brief SCG_CCR [SCS] to Select system clock source
*
*/
typedef enum
{
SCG_CLOCK_SRC_FOSC = 1U, /*!< System OSC. */
SCG_CLOCK_SRC_SIRC = 2U, /*!< Slow IRC 12MHz. */
SCG_CLOCK_SRC_FIRC = 3U, /*!< Fast IRC. */
SCG_CLOCK_SRC_PLL0 = 6U, /*!< System PLL. */
SCG_CLOCK_SRC_NONE = 255U /*!< MAX value. */
} SCG_ClockSrcType;
/**
* @brief SCG_CCR [DIVCORE ]/ SCG_CCR [DIVBUS ]/ SCG_CCR [DIVSLOW ] to Select system clock source.
*
*/
typedef enum
{
SCG_CLOCK_DIV_BY1 = 0U, /*!< Divided by 1. */
SCG_CLOCK_DIV_BY2 = 1U, /*!< Divided by 2. */
SCG_CLOCK_DIV_BY3 = 2U, /*!< Divided by 3. */
SCG_CLOCK_DIV_BY4 = 3U /*!< Divided by 4. */
} SCG_ClockDivType;
/**
* @brief SCG_ CLKOUTCFG [CLKOUTSEL] to Select system clock source.
*/
typedef enum
{
SCG_CLOCKOUT_SRC_OFF = 0U, /*!< SCG OFF. */
SCG_CLOCKOUT_SRC_FOSC = 1U, /*!< Fast OSC. */
SCG_CLOCKOUT_SRC_SIRC = 2U, /*!< Slow IRC. */
SCG_CLOCKOUT_SRC_FIRC = 3U, /*!< Fast IRC. */
SCG_CLOCKOUT_SRC_SOSC = 4U, /*!< Slow OSC. */
SCG_CLOCKOUT_SRC_PLL1 = 5U, /*!< System PLL1. */
SCG_CLOCKOUT_SRC_PLL0 = 6U, /*!< System PLL0. */
SCG_CLOCKOUT_SRC_SIRC32K = 7U, /*!< SIRC32K_CLK.*/
} SCG_ClockoutSrcType;
/**
* @brief NVM clock source enumeration
*/
typedef enum
{
SCG_NVMCLK_SRC_SIRC = 30u, /*!< NVM source choose SIRC. */
SCG_NVMCLK_SRC_FIRC = 31u /*!< NVM source choose FIRC. */
} SCG_NvmClkSrcType;
/**
* @brief CMU4 clock source enumeration
*/
typedef enum
{
SCG_CMU4CLK_SRC_SIRC = 28u, /*!< NVM source choose SIRC. */
SCG_CMU4CLK_SRC_FOSC = 29u /*!< NVM source choose FORC. */
} SCG_Cmu4ClkSrcType;
/**
* @brief SCG registers CRC trigger mode
*/
typedef enum
{
SCG_CRC_SW_MODE = 0U, /*!< SCG registers CRC software mode. */
SCG_CRC_TRIGGER_MODE = 1U /*!< SCG registers CRC trigger mode. */
} SCG_CrcModeType;
/** @brief [DIVL]/[DIVM]/[DIVH] bit field definition for SCG_SIRC/ SCG_FIRC/ SCG_FOSC/ SCG_PLL0 registers */
typedef enum
{
SCG_ASYNC_CLOCK_DISABLE = 0U, /*!< Clock output is disabled. */
SCG_ASYNCCLOCKDIV_BY1 = 1U, /*!< Divided by 1. */
SCG_ASYNCCLOCKDIV_BY2 = 2U, /*!< Divided by 2. */
SCG_ASYNCCLOCKDIV_BY4 = 3U, /*!< Divided by 4. */
SCG_ASYNCCLOCKDIV_BY8 = 4U, /*!< Divided by 8. */
SCG_ASYNCCLOCKDIV_BY16 = 5U, /*!< Divided by 16. */
SCG_ASYNCCLOCKDIV_BY32 = 6U, /*!< Divided by 32. */
SCG_ASYNCCLOCKDIV_BY64 = 7U /*!< Divided by 64. */
} SCG_AsyncClockDivType;
/** @brief SCG_ PLLCFG[PREDIV] for PLL clock calculation. The pre-div value range is 0 ~ 31 */
typedef uint8_t SCG_PllPredivType;
/** @brief SCG_ PLLCFG[PSTDIV] for PLL clock calculation */
typedef enum
{
SCG_PLLPSTDIV_BY2 = 1U,
SCG_PLLPSTDIV_BY4 = 2U,
SCG_PLLPSTDIV_BY8 = 3U
} SCG_PllPstdivType;
/** @brief SCG_ PLLCFG[SOURCE] to Select PLL clock source */
typedef enum
{
SCG_PLLSOURCE_FOSC = 0U,
SCG_PLLSOURCE_FIRC = 1U
} SCG_PllSourceType;
/** @brief SCG_ PLLCFG [MULT] for PLL clock calculation. The mult value range is 96 ~ 512 */
typedef uint16_t SCG_PllMultiplyType;
/** @brief FOSC initial definition, include register SCG_FOSCCSR/SCG_FOSCDIV/SCG_FOSCCFG. */
typedef struct
{
bool bLock; /*!< SCG_FOSCCSR[LK] bit, Write to set the register can be written or not */
bool bCm; /*!< SCG_FOSCCSR[CM] bit, Clock Monitor is enable */
bool bCmre; /*!< SCG_FOSCCSR[CMRE] bit, Clock Monitor Reset Enable
0 Generates interrupt, 1 Generates rese */
bool bSten; /*!< SCG_FOSCCSR[STEN] bit, Clock Stop in Stop modes */
bool bBypass; /*!< SCG_FOSCCFG[BYPASS] bit, Configures FOSC for bypassing the internal oscillator.*/
SCG_AsyncClockDivType eDivH; /*!< SCG_FOSCDIV[DIVH] bit field definition, 0 means disable. */
SCG_AsyncClockDivType eDivM; /*!< SCG_FOSCDIV[DIVM] bit field definition, 0 means disable. */
SCG_AsyncClockDivType eDivL; /*!< SCG_FOSCDIV[DIVL] bit field definition, 0 means disable. */
} SCG_FoscType;
/** @brief SIRC initial definition, include register SCG_ SIRCCSR/ SCG_ SIRCDIV/ SCG_ SIRCTCCFG. */
typedef struct
{
bool bLock; /*!< SCG_SIRCCSR[LK] bit, Write to set the register can be written or not */
bool bCm; /*!< SCG_SIRCCSR[CM] bit, SIRC Clock Monitor Enable */
bool bTrEn; /*!< SCG_SIRCCSR[TREN] bit, IRC software trim enable (auto trim) */
bool bLpen; /*!< SCG_SIRCCSR[LPEN] bit, Clock Stop Enable */
bool bSten; /*!< SCG_SIRCCSR[STEN] bit, Clock Standby Enable */
SCG_AsyncClockDivType eDivH; /*!< SCG_SIRCDIV[DIVH] bit field definition.*/
SCG_AsyncClockDivType eDivM; /*!< SCG_SIRCDIV[DIVM] bit field definition.*/
SCG_AsyncClockDivType eDivL; /*!< SCG_SIRCDIV[DIVL] bit field definition.*/
uint8_t u8TrimSrc; /*!< SCG_SIRCTCFG[TRIMSRC] IRC clock auto trim reference clock source select.*/
} SCG_SircType;
typedef struct
{
bool bLock; /*!< SIRC32KCSR[LK] bit, Write to set the register can be written or not */
} SCG_Sirc32kType;
/** @brief FIRC initial definition, include register SCG_ FIRCCSR/ SCG_ FIRCDIV/ SCG_ FIRCFG. */
typedef struct
{
bool bLock; /*!< SCG_FIRCCSR[LK] bit, Write to set the register can be written or not */
bool bCm; /*!< SCG_FIRCCSR[CM] bit, FIRC Clock Monitor Enable */
bool bTrEn; /*!< SCG_FIRCCSR[TREN] bit, IRC software trim enable (auto trim) */
bool bSten; /*!< SCG_FIRCCSR[STEN] bit, Clock Standby Enable */
SCG_AsyncClockDivType eDivH; /*!< SCG_FIRCDIV[DIVH] bit field definition.*/
SCG_AsyncClockDivType eDivM; /*!< SCG_FIRCDIV[DIVM] bit field definition.*/
SCG_AsyncClockDivType eDivL; /*!< SCG_FIRCDIV[DIVL] bit field definition.*/
uint8_t u8TrimSrc; /*!< SCG_FIRCTCFG[TRIMSRC] IRC clock auto trim reference clock source select.*/
} SCG_FircType;
/** @brief SOSC definition, include register SCG_SOSCCFG. */
typedef struct
{
bool bLock; /*!< SCG_SOSCCSR[LK] bit, Write to set the register can be written or not.*/
bool bBypass; /*!< SCG_SOSCCSR[BYPASS] bit, Configures SOSC for bypassing the internal oscillator.*/
bool bCm; /*!< SCG_SOSCCSR[CM] bit,Clock Monitor enable.*/
bool bCmre; /*!< SCG_SOSCCSR[CMRE] bit, 1:Clock Monitor Reset, 0: interrupt*/
} SCG_SoscType;
/** @brief PLL definition, include register SCG_PLLCSR/ SCG_PLLDIV/SCG_PLL0CFG. */
typedef struct
{
bool bLock; /*!< SCG_PLLCSR[LK] bit, Write to set the register can be written or not.*/
bool bCm; /*!< SCG_PLLCSR[CM] bit,Clock Monitor enable.*/
bool bCmre; /*!< SCG_PLLCSR[CMRE] bit, 1:Clock Monitor Reset, 0: interrupt*/
bool bSten; /*!< SCG_PLLCSR[STEN] bit, Clock Standby Enable */
SCG_AsyncClockDivType eDivH; /*!< SCG_PLLDIV[DIVH] bit field definition.*/
SCG_AsyncClockDivType eDivM; /*!< SCG_PLLDIV[DIVM] bit field definition.*/
SCG_AsyncClockDivType eDivL; /*!< SCG_PLLDIV[DIVL] bit field definition.*/
SCG_PllPredivType u8Prediv; /*!< SCG_PLLCFG[PREDIV] bit field definition, the range is 0~31. [Pre-divider = u8Prediv + 1] */
SCG_PllPstdivType ePstDiv; /*!< SCG_PLLCFG[PSTDIV] bit field definition. [Post Divider = (ePstDiv == 0 ? 2 : 2^ePstDiv)] */
SCG_PllMultiplyType u16Mult; /*!< SCG_PLLCFG[MULT] bit field definition, this value need to be greater than 95.
[Multiplier = u16Mult + 1] */
SCG_PllSourceType eSrc; /*!< SCG_PLLCFG[SOURCE] bit field definition.*/
} SCG_PllType;
/** @brief Current system clock definition, include register SCG_CCR. */
typedef struct
{
bool bSysClkMonitor; /*!< SCG_CCR[SYSCLK_CME], System Clock monitor bit.*/
SCG_ClockSrcType eSrc; /*!< SCG_CCR[SCS], System Clock Source.*/
SCG_ClockDivType eDivSlow; /*!< SCG_CCR[DIVSLOW], Slow Clock Divide Ratio.*/
SCG_ClockDivType eDivBus; /*!< SCG_CCR[DIVBUS], Bus Clock Divide Ratio.*/
SCG_ClockDivType eDivCore; /*!< SCG_CCR[DIVCORE], Core Clock Divide Ratio.*/
} SCG_ClockCtrlType;
/**
* @brief Enable SOSC
*
* @param pSoscConfig SOSC configuration
* @return SCG_StatusType Function status
*/
SCG_StatusType SCG_EnableSOSC(const SCG_SoscType *const pSoscConfig);
/**
* @brief Disable SOSC
*
* @return SCG_StatusType Funtion status
*/
SCG_StatusType SCG_DisableSOSC(void);
/**
* @brief Enable FOSC clock with input configuration
*
* @param pFoscConfig FOSC configuration
* @return SCG_StatusType function status
*/
SCG_StatusType SCG_EnableFOSC(const SCG_FoscType *const pFoscConfig);
/**
* @brief Disable FOSC
*
* @return SCG_StatusType function status
*/
SCG_StatusType SCG_DisableFOSC(void);
/**
* @brief Set SIRC configuration and configure SIRC DIV
*
* @param pSircConfig SIRC configuation
* @return SCG_StatusType function status
*/
SCG_StatusType SCG_SetSIRC(const SCG_SircType *const pSircConfig);
/**
* @brief Disable SIRC DIV and clear DIV configuration
*
* @return SCG_StatusType function status
*/
SCG_StatusType SCG_ClearSIRC(void);
/**
* @brief Enable SIRC32K
*
* @param pSirc32kConfig SIRC32K configuration
* @return SCG_StatusType function status
*/
SCG_StatusType SCG_EnableSIRC32K(const SCG_Sirc32kType *const pSirc32kConfig);
/**
* @brief Disable SIRC32K
*
* @return SCG_StatusType function status
*/
SCG_StatusType SCG_DisableSIRC32K(void);
/**
* @brief Enable FIRC
*
* @param pFircConfig FIRC configuration
* @return SCG_StatusType function status
*/
SCG_StatusType SCG_EnableFIRC(const SCG_FircType *const pFircConfig);
/**
* @brief Disable FIRC
*
* @return SCG_StatusType function status
*/
SCG_StatusType SCG_DisableFIRC(void);
/**
* @brief Enable PLL
*
* @param ePll PLL instance
* @param pPllConfig PLL configuration
* @return SCG_StatusType function status
*/
SCG_StatusType SCG_EnablePLL(const SCG_PllClkType ePll, const SCG_PllType *const pPllConfig);
/**
* @brief Disable PLL
*
* @param ePll PLL instance
* @return SCG_StatusType function status
*/
SCG_StatusType SCG_DisablePLL(const SCG_PllClkType ePll);
/**
* @brief Set system run time clock and related CORE/BUS/SLOW clock.
*
* @param pSysClkConfig pointer to the clockCtrlType structure data instance,which defined for system clock selection.
* @return SCG_StatusType function status
* SCG_STATUS_SUCCESS : clock source and dividers are valid,and switch system clock successfully
* SCG_STATUS_SEQUENCE_ERROR: new clock source is not enabled
* SCG_STATUS_PARAM_ERROR: the core bus slow divider are invalid
* SCG_STATUS_TIMEOUT: switch system clock procedure time out
*/
SCG_StatusType SCG_SetClkCtrl(const SCG_ClockCtrlType *const pSysClkConfig);
/**
* @brief Get clock frequency
*
* @param eScgClockName Clock source type
* @return uint32_t frequency value
*/
uint32_t SCG_GetScgClockFreq(const SCG_ClkSrcType eScgClockName);
/**
* @brief Select clock out source
*
* @param eClkoutSel clock out source
*/
void SCG_SetClkOut(const SCG_ClockoutSrcType eClkoutSel);
/**
* @brief Select NVM clock source
*
* @param eNvmClkSrc NVM clock source
* @return uint32_t function status
*/
SCG_StatusType SCG_SetNvmClk(const SCG_NvmClkSrcType eNvmClkSrc);
/**
* @brief Select CMU4 clock source
*
* @param eCmu4ClkSrc CMU4 clock source
* @return SCG_StatusType function status
*/
SCG_StatusType SCG_SetCmu4Clk(const SCG_Cmu4ClkSrcType eCmu4ClkSrc);
/**
* @brief Generate the origion SCG register CRC result, and configure the SCG register CRC option.
*
* @param eMode The SCG register CRC trigger mode
* @return CRC configure status
* SCG_STATUS_SUCCESS : CRC configure successfully
* SCG_STATUS_TIMEOUT : CRC configure time out
*/
SCG_StatusType SCG_RegCrcConfig(SCG_CrcModeType eMode);
/**
* @brief Trigger the SCG register CRC generation by software
*
*/
void SCG_RegCrcGenerate(void);
/**
* @brief Trigger the SCG register CRC generation by software,and wait the CRC check result
*
* @return CRC check result
*/
SCG_CrcCheckResType SCG_RegCrcGenerateWaitResult(void);
/**
* @brief Clock source De-init
*
* @return SCG_StatusType function status
*/
SCG_StatusType SCG_Deinit(void);
/** @}*/ /* fc7xxx_driver_scg */
#endif

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/**
* @file fc7xxx_driver_scm.h
* @author Flagchip085
* @brief FC7xxx SCM driver type definition and API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_SCM_H_
#define _DRIVER_SCM_H_
#include "HwA_scm.h"
#include "HwA_csc.h"
#include "interrupt_manager.h"
/********* Local typedef ************/
/**
* @brief SCM return status
*
*/
typedef enum
{
SCM_E_OK = 0U, /*!< Return ok */
SCM_E_NOT_OK, /*!< Return not ok */
SCM_E_PARAM, /*!< Return invalid parameters */
SCM_E_LOCK, /*!< Return register has been locked */
SCM_E_TIMEOUT, /*!< Return operation timeout */
SCM_E_CRC /*!< Return CRC check failed */
} SCM_RetStatusType;
/**
* @brief CCMx type
*
*/
typedef enum
{
SCM_CCM0 = 0U /*!< CCM0 */
} SCM_CCM_Type;
/**
* @brief Matrixx type
*
*/
typedef enum
{
SCM_MatrixStatus_0 = 0U, /*!< Matrix status 0 */
SCM_MatrixStatus_1, /*!< Matrix status 1 */
SCM_MatrixStatus_2, /*!< Matrix status 2 */
SCM_MatrixStatus_5, /*!< Matrix status 5 */
SCM_MatrixStatus_6, /*!< Matrix status 6 */
SCM_MatrixStatus_7, /*!< Matrix status 7 */
SCM_MatrixStatus_ID /*!< Matrix ID status */
} SCM_MatrixStatusType;
/**
* @brief SCM registers CRC trigger mode
*/
typedef enum
{
SCM_CRC_SW_MODE = 0U, /*!< SCM registers CRC software mode. */
SCM_CRC_TRIGGER_MODE = 1U /*!< SCM registers CRC trigger mode. */
} SCM_CrcModeType;
/********* Local function ************/
/**
* @brief Get unique identification for the chip, loaded from NVR.
*
* @param pUid Pointer to UID
*
*/
void SCM_GetChip_UID(uint32 *pUid);
/**
* @brief Get CCMx status.
*
* @param eCCMType CCM type
* @param u32Value The or value of SCM_CCMxStatusType to select the status to get
*
*/
uint32_t SCM_GetStatus_CCMx(SCM_CCM_Type eCCMType, uint32_t u32Value);
/**
* @brief Get matrix status.
*
* @param eMatrixType Matrix type
* @param u32Value selection to get
*
*/
uint32_t SCM_GetStatus_Matrix(SCM_MatrixStatusType eMatrixType, uint32_t u32Value);
/**
* @brief Set cpu to control MAM ECC enable register 0.
*
* @param eCpuType Cpu to use
* @param bLockStatus Lock the cpu control settings
*
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetCpuCtrl_MAMECCR0(const SCM_WPB_CpuType eCpuType, bool bLockStatus);
/**
* @brief Set cpu to control MAM ECC enable register 1.
*
* @param eCpuType Cpu to use
* @param bLockStatus Lock the cpu control settings
*
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetCpuCtrl_MAMECCR1(const SCM_WPB_CpuType eCpuType, bool bLockStatus);
/**
* @brief Set cpu to control CPU0 ECC enable register.
*
* @param eCpuType Cpu to use
* @param bLockStatus Lock the cpu control settings
*
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetCpuCtrl_CPU0ECCEN(const SCM_WPB_CpuType eCpuType, bool bLockStatus);
/**
* @brief Set cpu to control SOCMISC register.
*
* @param eCpuType Cpu to use
* @param bLockStatus Lock the cpu control settings
*
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetCpuCtrl_SOCMISC(const SCM_WPB_CpuType eCpuType, bool bLockStatus);
/**
* @brief Set cpu to control Subsystem pcc register.
*
* @param eCpuType Cpu to use
* @param bLockStatus Lock the cpu control settings
*
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetCpuCtrl_SUBSYS_PCC(const SCM_WPB_CpuType eCpuType, bool bLockStatus);
/**
* @brief Set cpu to control master halt request register.
*
* @param eCpuType Cpu to use
* @param bLockStatus Lock the cpu control settings
*
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetCpuCtrl_MASTER_HALT_REQ(const SCM_WPB_CpuType eCpuType, bool bLockStatus);
/**
* @brief Set lock FTU_ROUTING register.
*
*/
void SCM_SetLock_FTU_ROUTING(void);
/**
* @brief Set lock FTU_GTB register.
*
*/
void SCM_SetLock_FTU_GTB(void);
/**
* @brief Set lock DEBUG_TRACE register.
*
*/
void SCM_SetLock_DEBUG_TRACE(void);
/**
* @brief Set lock FLEXCAN_ROUTING register.
*
*/
void SCM_SetLock_FLEXCAN_ROUTING(void);
/**
* @brief Set lock MSC0_ROUTING register.
*
*/
void SCM_SetLock_MSC0_ROUTING(void);
/**
* @brief Set lock INT_ROUTER_NMI register.
*
*/
void SCM_SetLock_INT_ROUTER_NMI(void);
/**
* @brief Set NMI interrupt router .
*
* @param eCpuType Cpu to use
* @param bEnable Enable/Disable
* @return Set operation success/failed
* SCM_E_OK: Set NMI interrupt router successfully
* SCM_E_PARAM: eCpuType invalid
*/
SCM_RetStatusType SCM_SetEnable_NMIIntRouter(const SCM_WPB_CpuType eCpuType, bool bEnable);
/**
* @brief Generate the origion SCM register CRC result, and configure the SCM register CRC option.
*
* @param eMode The SCM register CRC trigger mode
* @return CRC configure status
* SCM_E_OK : CRC configure successfully
* SCM_E_TIMEOUT : CRC configure time out
*/
SCM_RetStatusType SCM_RegCrcConfig(SCM_CrcModeType eMode);
/**
* @brief Trigger the SCM register CRC generation by software
*
*/
void SCM_RegCrcGenerate(void);
/**
* @brief Trigger the SCM register CRC generation by software,and wait the CRC check result
*
* @return CRC check result
*/
SCM_RetStatusType SCM_RegCrcGenerateWaitResult(void);
#endif /* end of _DRIVER_SCM_H_ */

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/**
* @file fc7xxx_driver_scst.h
* @author Flagchip
* @brief FC7xxx scst driver type definition and API
* @version 0.1.0
* @date 2023-12-29
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/*********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-29 qxw074 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_SCST_H_
#define _DRIVER_FC7XXX_DRIVER_SCST_H_
#include "device_header.h"
/**
* @addtogroup fc7xxx_driver_scst
* @{
*/
/**
* @brief typed of test result returned
*
*/
typedef enum
{
M7ST_FaultInjectError,
M7ST_ErrorAluTest,
M7ST_ErrorAluMLATest,
M7ST_ErrorAluSHIFTTest,
M7ST_ErrorAluTes1t,
M7ST_ErrorAluTest2,
M7ST_ErrorAluTest3,
M7ST_ErrorAluTest4,
M7ST_ErrorAluTest5,
M7ST_ErrorAluTest6,
M7ST_ErrorRegbankTest1,
M7ST_ErrorRegbankTest2,
M7ST_ErrorRegbankTest3,
M7ST_ErrorRegbankTest4,
M7ST_ErrorRegbankTest5,
M7ST_ErrorRegbankTest6,
M7ST_ErrorLoadStoreTest1,
M7ST_ErrorLoadStoreTest2,
M7ST_ErrorLoadStoreTest3,
M7ST_ErrorLoadStoreTest4,
M7ST_ErrorLoadStoreTest5,
M7ST_ErrorLoadStoreTest6,
M7ST_ErrorSimdSatTest1,
M7ST_ErrorSimdSatTest2,
M7ST_ErrorSimdSatTest3,
M7ST_ErrorSimdSatTest4,
M7ST_ErrorMacTest1,
M7ST_ErrorMacTest2,
M7ST_ErrorFetchTest,
M7ST_ErrorStatusTest1,
M7ST_ErrorStatusTest2,
M7ST_ErrorBranchTest1,
M7ST_ErrorBranchTest2,
M7ST_ErrorIntSvcTest,
M7ST_ErrorIntBusFaultTest,
M7ST_ErrorIntHardFaultTest1,
M7ST_ErrorIntHardFaultTest2,
M7ST_ErrorIntUsageFaultTest,
M7ST_ErrorIntSystickTest,
M7ST_ErrorIntPendSvTest,
M7ST_ErrorIntMemFaultTest,
M7ST_ErrorIntMaskingTest,
M7ST_ErrorIntHandlerThreadsTest,
M7ST_ErrorIntNMIHfTest,
M7ST_ErrorIntTailChainTest,
M7ST_ErrorIntAluTest,
M7ST_ErrorIntBranchTest,
M7ST_ErrorIntStatusTest,
M7ST_ErrorM7ST_TestPass
} Type_M7ST_AtomicStatus;
/**
* @brief typed of test index
*
*/
typedef enum
{
M7ST_AluTest,
M7ST_AluMLATest,
M7ST_AluSHIFTTest,
M7ST_AluTes1t,
M7ST_AluTest2,
M7ST_AluTest3,
M7ST_AluTest4,
M7ST_AluTest5,
M7ST_AluTest6,
M7ST_RegbankTest1,
M7ST_RegbankTest2,
M7ST_RegbankTest3,
M7ST_RegbankTest4,
M7ST_RegbankTest5,
M7ST_RegbankTest6,
M7ST_LoadStoreTest1,
M7ST_LoadStoreTest2,
M7ST_LoadStoreTest3,
M7ST_LoadStoreTest4,
M7ST_LoadStoreTest5,
M7ST_LoadStoreTest6,
M7ST_SimdSatTest1,
M7ST_SimdSatTest2,
M7ST_SimdSatTest3,
M7ST_SimdSatTest4,
M7ST_MacTest1,
M7ST_MacTest2,
M7ST_FetchTest,
M7ST_StatusTest1,
M7ST_StatusTest2,
M7ST_BranchTest1,
M7ST_BranchTest2,
M7ST_RegressionTest
} SCST_TestIndexType;
/**
* @brief This function is used to get the result of the executed test
*
* @param test_index is test number,0U..32U
* @param s_u32RamBase The first address of the 1k memory that the program needs to run
* @return M7ST_ErrorM7ST_TestPass is ok, others are not ok
*/
Type_M7ST_AtomicStatus SCST_ExecuteTest(SCST_TestIndexType test_index,uint32_t *s_u32RamBase);
/** @}*/ /* fc7xxx_driver_scst */
#endif

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/**
* @file fc7xxx_driver_sec.h
* @author Flagchip
* @brief FC7xxx sec driver type definition and API
* @version 0.2.0
* @date 2023-2-7
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.2.0 2023-2-7 Flagchip076 N/A First version for FC7300
********************************************************************************/
#ifndef _DRIVER_SEC_H_
#define _DRIVER_SEC_H_
#include "HwA_sec.h"
#include "device_header.h"
/**
* @addtogroup fc7xxx_driver_sec
* @{
*/
/**
* @brief Debug Re-Enable Key
* @note Only if four 32-bit writes match, it will set the DEN to 0x5 to enable
debug and unlock SEC registers. The key is up to the user to decide in advance.
* */
typedef struct
{
uint32_t Re_key0; /*!< The Debug Re-enable key 0*/
uint32_t Re_key1; /*!< The Debug Re-enable key 1*/
uint32_t Re_key2; /*!< The Debug Re-enable key 2*/
uint32_t Re_key3; /*!< The Debug Re-enable key 3*/
} ReEnDebug_Keys;
typedef enum
{
SEC_STATUS_SUCCESS = 0U, /*!< SEC status success */
SEC_STATUS_FAILED = 1U /*!< SEC status failed */
}SEC_RetType;
/**
* @brief NVR write and read Permissions.
* @*/
typedef struct
{
bool WritEn; /*!< The NVR write permission*/
bool ReadEn; /*!< The NVR read permission*/
bool EraseEn; /*!< The NVR Erase permission*/
} NVR_Per;
/**
* @brief Indicate the system state
*
* */
typedef enum
{
Securedstate = 0u, /*!< The system is in secured state*/
UnSecuredstate = 1u /*!< The system is in no secured state*/
} Systemstate;
/**
* @brief Indicate the ISP instance
*
* */
typedef enum
{
ISP_FCUART1 = 0U, /*!< The ISP instance is FCUART1 */
ISP_FCUART3 = 1U, /*!< The ISP instance is FCUART3 */
ISP_FLEXCAN1 = 2U, /*!< The ISP instance is FLEXCAN1 */
ISP_FLEXCAN5 = 3U /*!< The ISP instance is FLEXCAN3 */
}Isp_Instance;
/**
* @brief Indicate the FCUART Baud Rate for ISP
*
* */
typedef enum
{
ISP_FCUART_2MBPS =0u, /*!< the FCUART Baud Rate is 2Mbps*/
ISP_FCUART_1MBPS =1u, /*!< the FCUART Baud Rate is 1Mbps*/
ISP_FCUART_512KBPS =2u, /*!< the FCUART Baud Rate is 512kbps*/
ISP_FCUART_115200BPS =3u, /*!< the FCUART Baud Rate is 115200bps*/
ISP_FCUART_INVALID = 4u /*!< the ISP instance is not FCUART*/
}FCUART_ISP_BAUDRATE;
/**
* @brief Indicate the FLEXCAN Baud Rate for ISP
*
* */
typedef enum
{
ISP_FLEXCANFD_4MBPS =0u, /*!< the CANFD Baud Rate is 4Mbps*/
ISP_FLEXCANFD_2MBPS =1u, /*!< the CANFD Baud Rate is 2Mbps*/
ISP_FLEXCAN_1MBPS =2u, /*!< the CAN Baud Rate is 1Mbps*/
ISP_FLEXCAN_500kBPS =3u, /*!< the FCUART Baud Rate is 500kbps*/
ISP_FLEXCAN_INVALID = 4u /*!< the ISP instance is not FLEXCAN*/
}FLEXCAN_ISP_BAUDRATE;
/**
* @brief Indicate the ISP information.
*
* */
typedef struct
{
bool IspModeEn; /*!< true means - ISP mode is active.*/
bool IspPinEn; /*!< true means - ISP pin is active.The associated pin defaults to internal pull up enabled.*/
bool IspAuthEn; /*!<*true means - ISP Auth Enable. Only valid in secure boot. (Value loaded from NVR sector)*/
Isp_Instance Ispinstance; /*!< the Isp instance*/
FCUART_ISP_BAUDRATE Ispfcuartbaudrate; /*!< Indicate the FCUART Baud Rate for ISP*/
FLEXCAN_ISP_BAUDRATE Ispflexcanbaudrate; /*!< Indicate the FLEXCAN Baud Rate for ISP*/
}SEC_IspInfo;
/**
* @brief Indicate the fast boot speed.
*
* */
typedef enum
{
FASTBOOT_300MHZ = 0u, /*!< Select PLL0 as the core clock source; the core clock is 300MHz.*/
FASTBOOT_96MHZ = 1u /*!< Select FIRC as the core clock source; the core clock is 96MHz.*/
}FastBoot_Speed;
/**
* @brief Indicate the OSC Frequency
*
* */
typedef enum
{
OSC_8MHZ = 0u, /*!<OSC Frequency is 8 MHZ*/
OSC_12MHZ = 1u, /*!<OSC Frequency is 12 MHZ*/
OSC_16MHZ = 2u, /*!<OSC Frequency is 16 MHZ*/
OSC_24MHZ = 3u, /*!<OSC Frequency is 24 MHZ*/
OSC_25MHZ = 4u, /*!<OSC Frequency is 25 MHZ*/
OSC_32MHZ = 5u, /*!<OSC Frequency is 32 MHZ*/
OSC_48MHZ = 6u, /*!<OSC Frequency is 48 MHZ*/
OSC_40MHZ = 7u /*!<OSC Frequency is 40 MHZ*/
}Osc_FreqInfo;
/**
* @brief Indicate the lifecycle of the chip.
*
* */
typedef enum
{
LIFECYCLE_INVALID = 0U, /*!<no Lifcycle */
LIFECYCLE_OEM_DEV = 0X1U, /*!<Lifcycle OEM Development*/
LIFECYCLE_OEM_PDT = 0X2U, /*!<Lifcycle OEM Production*/
LIFECYCLE_INFIELD = 0X4U, /*!<Lifcycle In Field*/
LIFECYCLE_PREFA = 0X8U, /*!<Lifcycle Pre Fault Analysis*/
LIFECYCLE_FA = 0X10U /*!<Lifcycle Analysis*/
}SC_LifeCycle;
/**
* @brief Indicate the boot information.
*
* */
typedef struct
{
bool BootRom; /*!< true means - boot from rom.*/
bool NmiPinEn; /*!< true means - nmi pin is active.The associated pin defaults to internal pull up enabled.*/
bool SecBootEn; /*!< true means - secure boot enable false means no secure boot mode..*/
bool OscEn; /*!< true means - OSC is available.*/
FastBoot_Speed FastBootSpeed; /*!< the fast boot speed.*/
Osc_FreqInfo OscFreq; /*!<Indicate the OSC Frequency*/
}SEC_BootInfo;
/**
* @brief Indicate the Host User Key Read/Write/Erase Protection
*
* */
typedef struct
{
bool HostUKReadEn; /*!< true means - Host read access to User Key region is enabled.*/
bool HostUKWriteEn; /*!< true means - Host write access to User Key region is enabled.*/
bool HostUKEraseEn; /*!< true means - Host eraseaccess to User Key region is enabled.*/
}HostUKPermission;
/**
* @brief Indicate the Host NVR Read/Write/Erase Protection
*
* */
typedef struct
{
bool HostNVRReadEn; /*!< true means - Host read access to NVRregion is enabled.*/
bool HostNVRWriteEn; /*!< true means - Host write access to NVR region is enabled.*/
bool HostNVREraseEn; /*!< true means - Host eraseaccess to NVR region is enabled.*/
}HostNVRPermission;
/**
* @brief Indicate the Bootloader Verification Algorithm
*
* */
typedef enum
{
BL_ALGORITHM_CMAC = 0U, /*!< the Bootloader Verification Algorithm is CMAC*/
BL_ALGORITHM_ECC256_SHA256 = 1U, /*!< the Bootloader Verification Algorithm is ECC256/SHA256*/
BL_ALGORITHM_SM2_SM3 = 7U /*!< the Bootloader Verification Algorithm is SM2/SM3*/
}BL_VerifyAlgorithm;
/**
* @brief Indicate the Debug/ISP/PREFA Authentication and USRK decryption algorithm
*
* */
typedef enum
{
DECRYPTTION_ECC256 = 0U, /*!< the Debug/ISP/PREFA Authentication and USRK decryption algorithm is ecc256*/
DECRYPTTION_SM2 = 1U, /*!< the Debug/ISP/PREFA Authentication and USRK decryption algorithm is sm2*/
}Decryption_Algorithm;
/**
* @brief This function can be used to enable the Debug mode.
* @return true means enable debug success ,false means enable debug failed.
* */
bool SEC_EnDebugMode(void);
/**
* @brief This function can be used to re-enable the Debug mode by the re-enable keys.
* @param keys The Debug mode re-enable keys.The key is up to the user to decide in advance.
* @return true means re-enable success,false means re-enable failed.
* */
bool SEC_ReEnDebugMode(ReEnDebug_Keys keys);
/**
* @brief This function can get the system state (secured or no secured).
* */
Systemstate SEC_SystemSecureState(void);
/**
* @brief This function can enable the test mode.
* @return true means enable test mode success,false means enable test mode failed.
* */
bool SEC_EnTestMode(void);
/**
*@brief This function can Re-enable the test mode by the re-enable key.
*@param key The test mode re-enable key.
*@return true means re-enable success,false means re-enable failed.
* */
bool SEC_ReEnTestMode(uint32_t key);
/**
* @brief This function can used to set the NVR write and read permission.
* @return true means setPer success,false means setPer failed.
* */
bool SEC_SetNvrPer(NVR_Per per);
/**
* @brief Get Secure Boot Enable Status
*
* @return true is enable and false is disable
*/
bool SEC_GetSecureStatus(void);
/**
* @brief Get ISP Status
*
* @return true is active and false is inactive
*/
bool SEC_GetISPModeStatus(void);
/**
* @brief Get User setting bootloader address
*
* @return bootloader address
*/
uint32_t SEC_GetBootAddress(void);
/**
* @brief Get the lifecycle.
*
* @return the lifecycle.
*/
SC_LifeCycle SEC_GetLifeCycle(void);
/**
* @brief User Key Access Enable. Only valid under non-secure boot
* @return true means User key can be read/programmed/erased by host CPU
* */
bool SEC_HostUKAccess(void);
/**
* @brief get the Bootloader Verification Algorithm
* @return the Bootloader Verification Algorithm
* */
BL_VerifyAlgorithm SEC_GetBLVerifyAlgorithm(void);
/**
* @brief get the Debug/ISP/PREFA Authentication and USRK decryption algorithm
* @return decryption algorithm
* */
Decryption_Algorithm SEC_GetDecryptAlgorithm(void);
/**
* @brief Indicate the Host User Key Read/Write/Erase Protection
* @param PHostUKAccess the structure for information
* */
void SEC_GetHostUKAccess(HostUKPermission *const PHostUKAccess);
/**
* @brief Indicate the Host NVR Read/Write/Erase Protection
* @param PHostNvrAccess the structure for information
* */
void SEC_GetHostNVRAccess(HostNVRPermission *const PHostNvrAccess);
/**
* @brief Get the HSM User Key Erase Protection
* @return true - HSM erase access to User Key region is enabled
* false -HSM erase access to User Key region is disabled
* */
bool SEC_GethsmUKEraseAccess(void);
/**
* @brief Get the HSM NVR Erase Protection
* @return true - HSM erase access to NVR region is enabled
* false -HSM erase access to NVR region is disabled
* */
bool SEC_GethsmNVREraseAccess(void);
/**
* @brief Get Bootloader Verification Mask
* @return Bootloader Verification Mask.
* */
uint32_t SEC_GetBLVerMask(void);
/**
* @brief Get whether Debug Mailbox Backdoor Key Enable.
* @return true means user can enable debug by writing debug backdoor key, false means user can not enable debug
* */
uint32_t SEC_GetDMBDkeyEn(void);
/**
* @brief Host Debug Auth Enable. Only valid in secure boot. (Value loaded from NVR sector)
* @return true means Host debug authentication enable. false means Host debug authentication disable.
*/
bool SEC_GetDebugAuthEn(void);
/**
* @brief Get the isp information.
* @param pIspInfo the structure for information
* @return Get whether operation is success.
*
* */
SEC_RetType SEC_GetIspInfo(SEC_IspInfo *const pIspInfo);
/**
* @brief Get the boot information.
* @param pBootInfo the structure for information.
* @return Get whether operation is success.
*
* */
SEC_RetType SEC_GetBootInfo(SEC_BootInfo *const pBootInfo);
/** @}*/ /* fc4xxx_driver_sec */
#endif /* end of _DRIVER_SEC_H_ */

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/**
* @file fc4xxx_driver_sent.h
* @author Flagchip073
* @brief FC7xxx SENT driver type definition and API
* @version 0.1.0
* @date 2022-12-14
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022-12-14 Flagchip073 N/A First version for FC7300 SENT module
******************************************************************************** */
#ifndef _DRIVER_FC4XXX_DRIVER_SENT_H_
#define _DRIVER_FC4XXX_DRIVER_SENT_H_
#include "device_header.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_sent
* @{
*/
/**
* @brief SENT buffer address and size in DMA mode
*
*/
#define SENT0_GET_FAST_MSG_DMA_ADDR(echannel) (&(SENT->SENT_CHN[echannel].CHN_DFD))
#define SENT_GET_FAST_MSG_DMA_BYTELENGTH (12U)
#define SENT0_GET_SLOW_MSG_DMA_ADDR(echannel) (&(SENT->SENT_CHN[echannel].CHN_DSB3))
#define SENT_GET_SLOW_MSG_DMA_BYTELENGTH (12U)
/**
* @brief SENT operation return values
*
*/
typedef enum
{
SENT_RETURN_OK = 0x00U, /*!< The SENT operation is succeeded */
SENT_RETURN_E_NOT_OK = 0x01U, /*!< The SENT operation is failed */
SENT_RETURN_E_ALREADY_INIT = 0x02U, /*!< The SENT has been initialized. */
SENT_RETURN_E_UNINIT = 0x03U, /*!< The SENT is not initialized */
SENT_RETURN_E_PARAM = 0x04U, /*!< The SENT parameter is incorrect or out of range. */
}
Sent_ReturnType;
/**
* @brief SENT Channel index
*
*/
typedef enum
{
SENT_CHANNEL_0 = 0x00U, /*!< The SENT channel 0 */
SENT_CHANNEL_1 = 0x01U, /*!< The SENT channel 1 */
SENT_CHANNEL_2 = 0x02U, /*!< The SENT channel 2 */
SENT_CHANNEL_3 = 0x03U, /*!< The SENT channel 3 */
SENT_CHANNEL_MAX = SENT_CHANNEL_COUNT
} Sent_ChannelType;
/**
* @brief SENT instance index
*
*/
typedef enum
{
SENT_INSTANCE_0 = 0x00U, /*!< The SENT channel 0 */
SENT_INSTANCE_1 = 0x01U, /*!< The SENT channel 1 */
SENT_INSTANCE_MAX = SENT_INSTANCE_COUNT
} Sent_InstanceType;
/**
* @brief SENT nibble data mode control. Refer to SENT SAE J2716 2010 for detail protocol definition
*
*/
typedef enum
{
SENT_DATA_NIBBLE_MODE_A = 0x0U, /*!< Frame format A */
SENT_DATA_NIBBLE_MODE_H1 = 0x1U, /*!< Frame format H1 */
SENT_DATA_NIBBLE_MODE_H2 = 0x2U, /*!< Frame format H2 */
SENT_DATA_NIBBLE_MODE_H3 = 0x3U, /*!< Frame format H3 */
SENT_DATA_NIBBLE_MODE_H4 = 0x4U, /*!< Frame format H4 */
SENT_DATA_NIBBLE_MODE_H5 = 0x5U, /*!< Frame format H5 */
SENT_DATA_NIBBLE_MODE_H6 = 0x6U, /*!< Frame format H6 */
SENT_DATA_NIBBLE_MODE_H7 = 0x7U /*!< Frame format H7 */
} Sent_DataNibbleModeType;
/**
* @brief SENT calibration valid type
*
*/
typedef enum
{
SENT_CALIBRATION_VALID_DISABLE = 0x0U, /*!< The successive calibration pulses diagnostic will be disabled */
SENT_CALIBRATION_VALID_WITHIN_20 = 0x1U, /*!< The difference of received calibration pulse and receiver configuration is within 20%, the message is deemed to be valid */
SENT_CALIBRATION_VALID_FROM_20_TO_25 = 0x2U, /*!< The difference of received calibration pulse and receiver configuration is more than 20% but less than 25%, the message is deemed to be valid */
} Sent_CalibrationValidType;
/**
* @brief SENT Successive calibration pulses diagnostic option
*
*/
typedef enum
{
SENT_CALIBRATION_PULSE_DIAG_OPTION2 = 0x0U, /*!< Option 2 i.e. Low Latency Option as per SAE Specification */
SENT_CALIBRATION_PULSE_DIAG_OPTION1 = 0x1U, /*!< Option 1 i.e. Preferred but High Latency Option as per SAE Specification */
} Sent_CalDiagOptionType;
/**
* @brief Determines how long the bus idle flag will assert when SENT bus is idle
*
*/
typedef enum
{
SENT_IDLE_COUNT_FLAG_DISABLE = 0x0U, /*!< The bus idle flag will never assert */
SENT_IDLE_COUNT_FLAG_254_TICKS = 0x1U, /*!< The bus is idle for more than 127*2 ticks, then the bus idle flag will assert */
SENT_IDLE_COUNT_FLAG_508_TICKS = 0x2U, /*!< The bus is idle for more than 127*2 ticks, then the bus idle flag will assert */
SENT_IDLE_COUNT_FLAG_1016_TICKS = 0x4U, /*!< The bus is idle for more than 127*2 ticks, then the bus idle flag will assert */
SENT_IDLE_COUNT_FLAG_2032_TICKS = 0x8U, /*!< The bus is idle for more than 127*2 ticks, then the bus idle flag will assert */
} Sent_IdleCountType;
/**
* @brief SENT Slow message type.
*
*/
typedef enum
{
SENT_SERIAL_MESSAGE_SHORT = 0x0U, /*!< short serial data message */
SENT_SERIAL_MESSAGE_ENHANCE_12DATA_8ID = 0x1U, /*!< enhanced serial data message with 12-bit data and 8-bit ID */
SENT_SERIAL_MESSAGE_ENHANCE_16DATA_4ID = 0x2U, /*!< enhanced serial data message with 16-bit data and 4-bit ID */
} Sent_SerialMessageType;
/**
* @brief SENT trigger type in SPC mode
*
*/
typedef enum
{
SENT_SPC_SOFTWARE_TRIGGER = 0x0U, /*!< SPC pulse triggered by software method */
SENT_SPC_EXTERNAL_TRIGGER = 0x1U, /*!< SPC pulse triggered by external trigger */
} Sent_SpcTriggerType;
/**
* @brief Select the tick base in SPC mode
*
*/
typedef enum
{
SENT_SPC_TICK_BASE_PRE_MSG = 0x0U, /*!< Previous received message tick base */
SENT_SPC_TICK_BASE_CONFIGURED = 0x1U, /*!< SENT configured tick base */
} Sent_SpcTickBaseType;
/**
* @brief Sent global interrupt type.
*
*/
typedef enum
{
SENT_SLOW_MSG_DMA_UF_IT = 0U, /*!< Slow message dma read underflow interrupt enable. */
SENT_FAST_MSG_DMA_DF_IT = 1U, /*!< Fast message dma read underflow interrupt enable. */
SENT_FAST_MSG_READY_IT = 2U, /*!< Fast message ready interrupt enable. */
SENT_SLOW_MSG_READY_IT = 3U, /*!< Slow message ready interrupt enable. */
SENT_FAST_MSG_FIFO_OF_IT = 4U, /*!< Fast message FIFO overflow interrupt enable. */
} Sent_GlobalInterruptType;
/**
* @brief Structure to enable or disable the channel interrupts.
*
*/
typedef struct
{
bool bBusIdleITEn; /*!< Bus idle interrupt enable. */
bool bSpcOverrunITEn; /*!< SPC overrun interrupt enable. */
bool bCalResyncErrITEn; /*!< Continuous 2 sync/calibration pulse difference exceed 1.5625% error interrupt enable. */
bool bCalFailITEn; /*!< Calibation 20% pass 25% fail interrupt enable. */
bool bSlowMsgOFITEn; /*!< Slow message overflow interrupt enable. */
bool bFastMsgOFITEn; /*!< Fast message overflow interrupt enable. */
bool bNibbleValueErrITEn; /*!< Nibble value more than 15 or less than 0 error interrupt enable. */
bool bPrePulseDiagErrITEn; /*!< Previous pulse diagnosis error interrupt enable. */
bool bCalDiagErrITEn; /*!< Calibration diagnosis over 25% error interrupt enable. */
bool bCalErrITEn; /*!< Sync/calibration pulse difference eceed 1.5625% error interrupt enable. */
bool bSlowMsgCrcErrITEn; /*!< Slow message CRC check error interrupt enable. */
bool bFastMsgCrcErrITEn; /*!< Fast message CRC check error interrupt enable. */
bool bFallingEdgeNumErrITEn; /*!< Falling edge number error interrupt enable. */
} Sent_ChannelInterruptType;
/**
* @brief Structure for fast message buffer.
*
*/
typedef struct
{
uint8_t u8CRC; /*!< Receied fast message CRC data. */
uint8_t u8SC; /*!< Fast message status communication nibble value. */
uint32_t u32Timestamp; /*!< Fast message timestamp value. */
uint32_t u32Data; /*!< Received fast message data nibble. */
} Sent_FastMessageDataType;
/**
* @brief Structure for slow message buffer.
*
*/
typedef struct
{
Sent_SerialMessageType eMsgType; /*!< Slow message type. */
uint8_t u8CRC; /*!< Slow message crc data. */
uint8_t u8ID; /*!< Slow message ID. */
uint16_t u16Data; /*!< Slow message data. */
uint32_t u32Timestamp; /*!< Slow message timestamp value. */
} Sent_SlowMessageDataType;
/**
* @brief SENT Global ISR callback function prototype
*
*/
typedef void (*SENT_GBISRCallbackType)(Sent_ChannelType eChannel, const Sent_GlobalInterruptType eInterrupt);
/**
* @brief SENT Channel ISR callback function prototype
*
*/
typedef void (*SENT_CHISRCallbackType)(Sent_ChannelType eChannel, const uint32_t u32ChannelStatus);
/**
* @brief structure to configure the SENT.
*
*/
typedef struct
{
uint8_t u8PreScaler; /*<! This value is used to divide the function clock to count the timestamp */
uint8_t u8DmaWaterMark; /*<! When Fast message DMA request is enabled, the request will asserts if data number in FIFO is more than watermark */
bool bDebugModeEn; /*<! If enable, the SENT will keep running under debug mode. */
bool bAutoClearReadyFlag; /*!< When enabled after data ready read of received data, crc and timestamp register will prevent the assert of data overflow flag. */
SENT_GBISRCallbackType pGBCallback; /*<! Global interrupt callback function */
SENT_CHISRCallbackType pCHCallback; /*<! Channel interrupt callback function */
} Sent_ConfigType;
/**
* @brief structure to configure the SENT channel.
*
*/
typedef struct
{
uint8_t u8DataNibbleNumber; /*!< The received data number will be configured value plus 1, 0 and value bigger than 5 is forbidden. */
uint8_t u8DigitalFilterCount; /*!< The input signal needs keep stable for (filt_cnt<<2)* function_clk cycles to pass through the digital filter. */
uint16_t u16TickScaler; /*!< The value plus 1 is used to divide the function clock to tick clock. */
Sent_CalDiagOptionType eCalDiagOption; /*!< Successive calibration pulses diagnostic option. */
Sent_DataNibbleModeType eDataNibbleMode; /*!< Refer to SENT SAE J2716 2010 for detail protocol definition. */
Sent_CalibrationValidType eCalValid; /*!< Select valid Calibration pulse range */
Sent_IdleCountType eIdleCount; /*!< Select how long the bus idle flag will assert when bus is idle */
bool bFastMessageFifoEn; /*!< Enable Channel FIFO function. */
bool bTickCompensateEn; /*!< Enable the tick period compensate function. */
bool bUseAlternativeCrc; /*!< Use alternative 4-bit CRC algorithm instead of SAE CRC algorithm. */
bool bFastMsgCRCCheckEn; /*!< Enable Fast message CRC check. */
bool bFastMsgDataChangeEn; /*!< If enabled, the SENT will only assert the fast message ready flag when received data has changed compared with previous data */
bool bFastMsgCRCAugEn; /*!< Augmentation is selected for Fast Message CRC calculation. */
bool bFastMsgCRCWithSCEn; /*!< If enabled, the crc calculation will includes S&C nibble. */
bool bSlowMsgCRCAugEn; /*!< Augmentation is selected for Short Serial Message CRC calculation. */
bool bPausePulseEn; /*!< If enabled, a pause pulse will be appended at the end of a frame. */
bool bChannelEn; /*!< Enable the SENT Channel. */
} Sent_ChannelConfigType;
/**
* @brief structure to configure the SENT channel DMA.
*
*/
typedef struct
{
bool bFastMsgDmaEn; /*!< Fast message DMA request enable. */
bool bSlowMsgDmaEn; /*!< Slow message DMA request enable. */
} Sent_DMAConfigType;
/**
* @brief structure to configure the SENT channel SPC.
*
*/
typedef struct
{
uint8_t u8PulseWidth; /*!< Configure the width of the SPC pulse. */
uint8_t u8PulseDelay; /*!< Configure the delay between SPC-trigger assert and finally generate a SPC pulse. */
Sent_SpcTickBaseType eSpcTickBase; /*!< Select the tick base of SPC */
Sent_SpcTriggerType eSpcTrigger; /*!< Select the SPC pulse trigger type. */
bool bCalDiagEn; /*!< Enable Calibration diagnosis. */
bool bSpcModeEn; /*!< Enable SPC mode. */
} Sent_SpcConfigType;
/**
* @brief Initialize SENT configuration
*
* @param eInstance The instance of SENT
* @param ConfigPtr The basic configurations of the SENT
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_Init(const Sent_InstanceType eInstance, const Sent_ConfigType *ConfigPtr);
/**
* @brief Set SENT channel configuration
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @param ConfigPtr The channel configurations of the SENT
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_SetChannelConfig(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, const Sent_ChannelConfigType *pCfg);
/**
* @brief Set SENT DMA configuration
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @param ConfigPtr The channel configurations of the DMA
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_SetDMAConfig(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, Sent_DMAConfigType *pCfg);
/**
* @brief Set SENT SPC configuration
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @param ConfigPtr The channel configurations of the SPC
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_SetSPCConfig(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, const Sent_SpcConfigType *pCfg);
/**
* @brief Get Fast message data.
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @param pMsg The Fast message structure buffer.
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_GetFastMessageData(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, Sent_FastMessageDataType *pMsg);
/**
* @brief Get Slow message data.
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @param pMsg The slow message structure buffer.
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_GetSlowMessageData(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, Sent_SlowMessageDataType *pMsg);
/**
* @brief Decode the fast message with DMA buffer.
*
* @param pDmaBuffer The pointer for DMA buffer. the buffer length should be 12bytes.
* @param u32BufferLength The byte length of dma buffer.
* @param pMsg The fast message structure buffer.
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_DecodeFastMessageWithDMABuffer(uint32_t *pDmaBuffer, uint32_t u32BufferLength, Sent_FastMessageDataType *pMsg);
/**
* @brief Decode the slow message with DMA buffer.
*
* @param pDmaBuffer The pointer for DMA buffer. the buffer length should be 12bytes.
* @param u32BufferLength The byte length of dma buffer.
* @param pMsg The slow message structure buffer.
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_DecodeSlowMessageWithDMABuffer(uint32_t *pDmaBuffer, uint32_t u32BufferLength, Sent_SlowMessageDataType *pMsg);
/**
* @brief Enable the fast message ready interrupt
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_EnableGlobalFastMsgNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel);
/**
* @brief Disable the fast message ready interrupt
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_DisableGlobalFastMsgNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel);
/**
* @brief Enable the slow message ready interrupt
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_EnableGlobalSlowMsgNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel);
/**
* @brief Disable the slow message ready interrupt
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_DisableGlobalSlowMsgNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel);
/**
* @brief Enable the fast message fifo interrupt
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_EnableGlobalFastFifoMsgNotification(const Sent_InstanceType eInstance);
/**
* @brief Disable the fast message fifo interrupt
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_DisableGlobalFastFifoMsgNotification(const Sent_InstanceType eInstance);
/**
* @brief configure the channel interrupt.
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @param sInterruptEn the structure of interrupt enable
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_ConfigChannelStatusNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, const Sent_ChannelInterruptType *sInterruptEn);
/**
* @brief Request the SPC pulse
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_RequestSPCPulse(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel);
/**
* @brief Get the fast message ready flag
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @param pFlag The point of flag(true or false)
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_GetFastMsgReadyFlag(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, bool *pFlag);
/**
* @brief Get the slow message ready flag
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @param pFlag The point of flag(true or false)
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_GetSlowMsgReadyFlag(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, bool *pFlag);
/**
* @brief Get the channel status
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @param pStatus The point of channel status
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_GetChannelStatus(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, uint32_t *pStatus);
/**
* @brief Clear the channel status
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @param Status The channel status, the bits are used for W1c
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_ClearChannelStatus(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, uint32_t Status);
/**
* @brief Get the channel SPC busy flag
*
* @param eInstance The instance of SENT
* @param eChannel The channel of the selected SENT instance
* @param pflag The point of flag(true or false)
* @return Sent_ReturnType whether the operation is successfully
*/
Sent_ReturnType SENT_GetChannelSPCBusyFlag(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, bool *pflag);
/** @}*/ /* fc7xxx_driver_sent */
#if defined(__cplusplus)
}
#endif
#endif

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/**
* @file fc7xxx_driver_smc.h
* @author Flagchip
* @brief FC7xxx SMC driver type definition and API
* @version 0.1.0
* @date 2022-11-21
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
#ifndef _DRIVER_FC4XXX_DRIVER_SMC_H_
#define _DRIVER_FC4XXX_DRIVER_SMC_H_
#include "HwA_smc.h"
#include "HwA_pmc.h"
#include "HwA_cm7.h"
/**
* @addtogroup fc7xxx_driver_smc
* @{
*/
/** @brief Smc return type. */
typedef enum
{
SMC_STATUS_SUCCESS = 0U,
SMC_STATUS_PARAM_INVALID = 1U
} SMC_StatusType;
/** @brief Smc mode */
typedef enum
{
SMC_MODE_RUN = 0U, /**< The MCU can run at full speed and the internal supply is fully regulated, that is, in run regulation */
SMC_MODE_STOP, /**< Core enters sleep mode and no other clock is gated. Only the core clock is gated. */
SMC_MODE_WAIT, /**< Both core and bus clocks are gated off. */
SMC_MODE_STANBY_0, /**< All clocks except some low-power clocks can keep on are gated off and the PD1 domain is powered off. please refer to reference manual for detail about standby mode 0. */
SMC_MODE_STANBY_1, /**< All clocks except some low-power clocks can keep on are gated off and the PD1 domain is powered off. please refer to reference manual for detail about standby mode 1. */
SMC_MODE_STANBY_2, /**< All clocks except some low-power clocks can keep on are gated off and the PD1 domain is powered off. please refer to reference manual for detail about standby mode 2. */
SMC_MODE_STANBY_3 /**< All clocks except some low-power clocks can keep on are gated off and the PD1 domain is powered off. please refer to reference manual for detail about standby mode 3. */
} SMC_ModeType;
#define SMC_MODE_MAX_ID 6U
/* global functions */
/**
* @brief Set system mode
*
* @param eMode MCU low power mode
* @return Smc return type
*/
SMC_StatusType SMC_SetSystemMode(const SMC_ModeType eMode);
/** @}*/ /* fc7xxx_driver_smc */
#endif

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/**
* @file fc7xxx_driver_stcu.h
* @author Flagchip
* @brief FC4xxx stcu driver type definition and API
* @version 0.1.0
* @date 2022-02-20
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Author CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 12/08/2022 Flagchip038 N/A First version for FC7300
******************************************************************************** */
#ifndef _DRIVER_STCU_H_
#define _DRIVER_STCU_H_
/** @brief STCU self test status flag */
typedef enum
{
STCU_SELFTEST_NONE = 0x00U, /**<! No any status flag. >*/
STCU_SELFTEST_DONE = 0x01U, /**<! Self-test Done Flag. >*/
STCU_SELFTEST_ABORT = 0x02U, /**<! Self-test Abort Flag. >*/
STCU_SELFTEST_LBIST_ERROR = 0x10U, /**<! LBIST Error Flag. >*/
STCU_SELFTEST_MBIST_ERROR = 0x20U, /**<! MBIST Error Flag. >*/
STCU_SELFTEST_TIMEOUT_ERROR = 0x40U, /**<! Self-test Timeout Error Flag. >*/
STCU_SELFTEST_NVRLOAD_ERROR = 0x100U, /**<! NVR Load Error Flag. >*/
STCU_SELFTEST_SELFCHECK_ERROR = 0x200u /**<! STCU Self Check Error Flag. >*/
}STCU_SelfTestStatusType;
/** @brief STCU interrupt flag */
typedef enum
{
STCU_INTERRUPT_FLAG_NONE = 0x00U, /**<! No any Interrupt flag. >*/
STCU_INTERRUPT_FLAG_SIZE_ERR = 0x01U, /**<! STCU Register Access Size Error IRQ Flag. >*/
STCU_INTERRUPT_FLAG_SEQ_ERR = 0x02U, /**<! Illegal Register Access Sequence IRQ Flag. >*/
}STCU_InterruptFlagType;
/** @brief The items select for MBIST */
typedef enum
{
STCU_MBIST_SEL_NONE = 0x00U, /**<! No any MBist item selected. >*/
STCU_MBIST_SEL_SRAM = 0x01U, /**<! SRAM Select for MBIST. >*/
STCU_MBIST_SEL_ITCM_CPU0 = 0x02U, /**<! ITCM_CPU0 SRAM Select for MBIST. >*/
STCU_MBIST_SEL_DTCM0_CPU0 = 0x04U, /**<! DTCM0_CPU0 SRAM Select for MBIST. >*/
STCU_MBIST_SEL_DTCM1_CPU0 = 0x08U, /**<! DTCM1_CPU0 SRAM Select for MBIST. >*/
STCU_MBIST_SEL_CACHE_CPU0 = 0x10U, /**<! CACHE_CPU0 SRAM Select for MBIST. >*/
STCU_MBIST_SEL_SUBSYS = 0x20U, /**<! SUBSYS SRAM Select for MBIST. >*/
STCU_MBIST_SEL_SRAM_HSM = 0x40U, /**<! HSM SRAM Select for MBIST. >*/
STCU_MBIST_SEL_SRAM_DMACAN = 0x80U, /**<! DMA_FLEXCAN SRAM Select for MBIST. >*/
STCU_MBIST_SEL_ROM_HOST = 0x100U, /**<! System ROM Select for MBIST. >*/
STCU_MBIST_SEL_ROM_HSM = 0x200U /**<! HSM ROM Select for MBIST. >*/
}STCU_MbistSelType;
/** @brief MBIST done status flag. */
typedef enum
{
STCU_MBIST_DONE_NONE = 0x00U, /**<! No any MBIST done flag. >*/
STCU_MBIST_DONE_SRAM = 0x01U, /**<! SRAM MBIST Done Dlag. >*/
STCU_MBIST_DONE_ITCM_CPU0 = 0x02U, /**<! ITCM_CPU0 SRAM MBIST Done Dlag. >*/
STCU_MBIST_DONE_DTCM0_CPU0 = 0x04U, /**<! DTCM0_CPU0 SRAM MBIST Done Dlag. >*/
STCU_MBIST_DONE_DTCM1_CPU0 = 0x08U, /**<! DTCM1_CPU0 SRAM MBIST Done Dlag. >*/
STCU_MBIST_DONE_CACHE_CPU0 = 0x10U, /**<! CACHE_CPU0 SRAM MBIST Done Flag. >*/
STCU_MBIST_DONE_SUBSYS = 0x20U, /**<! SUBSYS SRAM MBIST Done. >*/
STCU_MBIST_DONE_SRAM_HSM = 0x40U, /**<! HSM SRAM MBIST Done Flag. >*/
STCU_MBIST_DONE_SRAM_DMACAN = 0x80U, /**<! DMA_FLEXCAN SRAM MBIST Done Flag. >*/
STCU_MBIST_DONE_ROM_HOST = 0x100U, /**<! System ROM MBIST Done Dlag. >*/
STCU_MBIST_DONE_ROM_HSM = 0x200U /**<! HSM ROM MBIST Done Dlag. >*/
}STCU_MbistDoneType;
/** @brief MBIST fail status flag. */
typedef enum
{
STCU_MBIST_FAIL_NONE = 0x00U, /**<! No any MBIST fail flag. >*/
STCU_MBIST_FAIL_SRAM = 0x01U, /**<! SRAM MBIST Fail Flag. >*/
STCU_MBIST_FAIL_ITCM_CPU0 = 0x02U, /**<! ITCM_CPU0 SRAM MBIST Fail Flag. >*/
STCU_MBIST_FAIL_DTCM0_CPU0 = 0x04U, /**<! DTCM0_CPU0 SRAM MBIST Fail Flag. >*/
STCU_MBIST_FAIL_DTCM1_CPU0 = 0x08U, /**<! DTCM1_CPU0 SRAM MBIST Fail Flag. >*/
STCU_MBIST_FAIL_CACHE_CPU0 = 0x10U, /**<! CACHE_CPU0 SRAM MBIST Fail Flag. >*/
STCU_MBIST_FAIL_SUBSYS = 0x20U, /**<! SUBSYS SRAM MBIST Fail Flag. >*/
STCU_MBIST_FAIL_SRAM_HSM = 0x40U, /**<! HSM SRAM MBIST Fail Flag. >*/
STCU_MBIST_FAIL_SRAM_DMACAN = 0x80U, /**<! DMA_FLEXCAN SRAM MBIST fail flag. >*/
STCU_MBIST_FAIL_ROM_HOST = 0x100U, /**<! System ROM MBIST Fail Flag. >*/
STCU_MBIST_FAIL_ROM_HSM = 0x200U /**<! HSM ROM MBIST Fail Flag. >*/
}STCU_MbistFailedType;
/** @brief Hardware SRAM initialization mode. */
typedef enum
{
STCU_INIT_RAM_MODE_POR_OR_WAKEUP4STANDBY0 = 0U, /**<! After POR or wakeup from STANDBY0, Hardware SRAM initialization. >*/
STCU_INIT_RAM_MODE_AFTER_WAKEUP4STANDBY1, /**<! After wakeup from STANDBY1, Hardware SRAM initialization. >*/
STCU_INIT_RAM_MODE_AFTER_WAKEUP4STANDBY2, /**<! After wakeup from STANDBY2, Hardware SRAM initialization. >*/
STCU_INIT_RAM_MODE_AFTER_WAKEUP4STANDBY3 /**<! After wakeup from STANDBY3, Hardware SRAM initialization. >*/
}STCU_InitRamModeType;
/** @brief The items select for Hardware SRAM Initialization. */
typedef enum
{
STCU_INIT_RAM_TYPE_NONE = 0x00U, /**<! No any SRAM need to be initialized. >*/
STCU_INIT_RAM_TYPE_SRAM = 0x01U, /**<! SRAM Select for Hardware SRAM Initialization. >*/
STCU_INIT_RAM_TYPE_ITCM_CPU0 = 0x02U, /**<! ITCM_CPU0 SRAM Select for Hardware SRAM Initialization. >*/
STCU_INIT_RAM_TYPE_DTCM0_CPU0 = 0x04U, /**<! DTCM0_CPU0 SRAM Select for Hardware SRAM Initialization. >*/
STCU_INIT_RAM_TYPE_DTCM1_CPU0 = 0x08U, /**<! DTCM1_CPU0 SRAM Select for Hardware SRAM Initialization. >*/
}STCU_InitRamType;
/** @brief Init Ram done status flag. */
typedef enum
{
STCU_INIT_RAM_DONE_TYPE_NONE = 0x00U, /**<! No any Init Ram done flag. >*/
STCU_INIT_RAM_DONE_TYPE_SRAM = 0x01U, /**<! SRAM Initialization Done Flag. >*/
STCU_INIT_RAM_DONE_TYPE_ITCM_CPU0 = 0x02U, /**<! ITCM_CPU0 SRAM Initialization Done Flag. >*/
STCU_INIT_RAM_DONE_TYPE_DTCM0_CPU0 = 0x04U, /**<! DTCM0_CPU0 SRAM Initialization Done Flag. >*/
STCU_INIT_RAM_DONE_TYPE_DTCM1_CPU0 = 0x08U, /**<! DTCM1_CPU0 SRAM Initialization Done Flag. >*/
}STCU_InitRamDoneType;
/** @brief Init Ram status flag. */
typedef enum
{
STCU_HARDWARE_INIT_RAM_STATUS_NONE = 0U, /**<! No any SRAN Initialization flag. >*/
STCU_HARDWARE_INIT_RAM_STATUS_DONE = 1U, /**<! Hardware SRAM Initialization Done Flag. >*/
STCU_HARDWARE_INIT_RAM_STATUS_BUSY = 2U, /**<! Hardware SRAM Initialization Busy Flag. >*/
STCU_HARDWARE_INIT_RAM_STATUS_ABORT = 4U /**<! Hardware SRAM Initialization Abort Flag. >*/
}STCU_HardwareInitRamStatusType;
/** @brief LBIST status flag. */
typedef enum
{
STCU_LBIST_STATUS_NONE = 0U, /**<! No any LBIST flag. >*/
STCU_LBIST_STATUS_DONE = 1U, /**<! LBIST Done Flag. >*/
STCU_LBIST_STATUS_FAILED = 2U /**<! LBIST Fail Flag. >*/
}STCU_LbistStatusType;
/** @brief LBIST Clock Divider. */
typedef enum
{
STCU_LBIST_CLK_DIVIDER_BY_2 = 1U, /**<! LBIST clock is Divided by 2. >*/
STCU_LBIST_CLK_DIVIDER_BY_3 = 2U, /**<! LBIST clock is Divided by 3. >*/
STCU_LBIST_CLK_DIVIDER_BY_4 = 3U, /**<! LBIST clock is Divided by 4. >*/
}STCU_LbistClkDivType;
/** @brief clock source of self-test. */
typedef enum
{
STCU_CLK_SOURCE_FIRC = 0U, /**<! FIRC clock source. >*/
STCU_CLK_SOURCE_PLL = 1U /**<! PLL clock source. >*/
}STCU_ClkSourceType;
/** @brief Self-test Port Pull Selection. */
typedef enum
{
STCU_PORT_PULL_DISABLE = 0U, /**<! Disable self test port pull function. >*/
STCU_PORT_PULL_DOWN, /**<! self test port pull down. >*/
STCU_PORT_PULL_UP /**<! self test port pull up. >*/
}STCU_PortPullModeType;
/** @brief Stcu call back function type, the u32status should refer to "STCU_InterruptFlagType" */
typedef void (*Stcu_IRQCallback)(uint32_t u32Status);
typedef struct
{
bool bLbistEn; /**<! LBIST Enable >*/
bool bMbistLPC; /**<! MBIST Low Power Control Enable >*/
bool bMbistEn; /**<! MBIST Enable >*/
bool bMbistFullTest; /**<! MBIST Full test Enable >*/
bool bMbistSramInit; /**<! Enable SRAM initialization at the end of power on self-test. >*/
bool bInterruptEn; /**<! STCU Interrupt Enable >*/
STCU_PortPullModeType ePortPullMode; /**<! Self-test Port Pull Selection >*/
STCU_ClkSourceType eClkSource; /**<! Select the clock source of self-test >*/
STCU_LbistClkDivType eLbistClkDivider; /**<! LBIST Clock Divider Control. Note:A slower LBIST clock will cause less power consumption but a longer test time. >*/
uint16_t u16MaxTime; /**<! The maximum time allowed for self-test execution.(unit : ms) >*/
uint32_t u32MbistSel; /**<! Refer to "STCU_MbistSelType", use OR to select the MBIST range. */
Stcu_IRQCallback pIrqCallback; /**<! Callback function for STCU IRQ >*/
}STCU_ConfigType;
typedef struct
{
STCU_InitRamModeType eInitMode; /**< RAM Initial Mode */
uint8_t bLockAfterEn; /**< Lock STCU after RAM Initial */
uint32_t u32InitRamType; /**< RAM Type, DTCM, ITCM, SRAM, refer to "STCU_InitRamType" and use OR to combine them */
}STCU_InitRamConfigType;
/**
* \brief Init the STCU module
*
* \param pConfig the configuration structure
*/
void STCU_Init(STCU_ConfigType *pConfig);
/**
* \brief Trigger to start Software self test
*
*/
void STCU_StartSelfTest(void);
/**
* \brief Check Software Trigger Self-test result
*
* \return refer to "STCU_SelfTestStatusType" enum.
*/
uint32_t STCU_CheckTriggerResult(void);
/**
* \brief Initial RAM with hardware
*
* \param pConfig the configuration structure
*/
void STCU_StartRamInit(STCU_InitRamConfigType *pInitCfg);
/**
* \brief Get status of RAM initialize action
*
* \return the status of ram initialize action, refer to "STCU_HardwareInitRamStatusType"
*/
uint32_t STCU_GetRamInitStatus(void);
/**
* \brief Get if the LBIST test result is Fail
*
* \return true means LBIST fail. false means LBIST pass.
*/
bool STCU_GetLbistFailResult(void);
/**
* \brief Get each MBIST Fail result
*
* \return refer to "STCU_MbistFailedType" enum.
*/
uint32_t STCU_GetMbistFailResult(void);
/**
* \brief Get each done status of SRAM initialize
*
* \return the done status of SRAM initialize action, refer to "STCU_InitRamDoneType"
*/
uint32_t STCU_GetRamInitDoneStatus(void);
/**
* \brief Set the LBIST Pattern value and expected misr value.
* The two value should be load from NVR, but also can reconfigure by this API.
* The expected misr value is calculated from pattern, so please make sure this two value is right, or the LBST would fail.
*
* \param u16Pattern the LBIST Pattern value
* \param u16Pattern the LBIST expected misr value
*/
void STCU_LBIST_Set_Pattern_Misr(uint16_t u16Pattern, uint32_t u32ExpectedMisr);
/**
* \brief Get LBIST actual MISR value, the value should be read and use DFT tool to decode it, if LBIST test resault is fail.
*
* \return the LBIST actual MISR value
*/
uint32_t STCU_GetLbistAcutalMisr(void);
/**
* @brief STCU 0 interrupt handler
*
* @note This function should be called as/in STCU 0 interrupt handler
*/
void STCU0_IRQHandler(void);
#endif /* end of _DRIVER_STCU_H_ */

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#ifndef _DRIVER_CORE_SYSTICK_H_
#define _DRIVER_CORE_SYSTICK_H_
#include "device_header.h"
/**
* \brief Config system tick
*
* \param u32ReloadVal reload value, val is decrease from reload value
* \return 0 is ok, and others are not ok
*/
uint8_t Core_SysTick_Config(uint32_t u32ReloadVal);
void Core_SysTick_DeConfig(void);
void Core_SysTick_SetValue(uint32_t u32Value);
void Core_SysTick_ClearValue(void);
uint32_t Core_SysTick_GetValue(void);
void Core_SysTick_Enable(void);
void Core_SysTick_Disable(void);
#endif /* end of _DRIVER_CORE0_SYSTICK_H_ */

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/**
* @file fc7xxx_driver_tmu.h
* @author Flagchip
* @brief FC7xxx TMU driver type definition and API
* @version 0.1.0
* @date 2023-12-29
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/*********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-29 qxw074 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_TMU_H_
#define _DRIVER_FC7XXX_DRIVER_TMU_H_
#include "device_header.h"
#include "HwA_tmu.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc7xxx_driver_tmu
* @{
*/
/**
* @brief The Flag-based temperature sensor over 150 Celsius callback function prototype
*
*/
typedef void (*TMU_TempOver150InterruptCallbackType)(void);
/**
* @brief The Flag-based temperature sensor over 125 Celsius callback function prototype
*
*/
typedef void (*TMU_TempOver125InterruptCallbackType)(void);
/**
* @brief The Flag-based temperature sensor ready callback function prototype
*
*/
typedef void (*TMU_TempFlagReadyInterruptCallbackType)(void);
/**
* @brief The Voltage-based temperature sensor ready callback function prototype
*
*/
typedef void (*TMU_TempVoltageReadyInterruptCallbackType)(void);
/**
* @brief TMU operation return values
*
*/
typedef enum
{
TMU_STATUS_ERROR = 0x0U, /*!< The TMU operation is failed */
TMU_STATUS_SUCCESS = 0x1U, /*!< The TMU operation is succeed */
TMU_STATUS_TIMEOUT = 0x2U /*!< The TMU operation is failed because of time out */
} TMU_StatusType;
/**
* @brief Defines the temperature sensor configuration
*
* This structure is used to configure for Flag-based temperature sensor ane Voltage-based temperature sensor
*
* Implements : TMU_InitType
*/
typedef struct
{
TMU_LockType eTempRegisterLockCon; /*!<Temperature Register lock status */
bool bTemperatureOver150IntEn; /*!< Enable interrupt when Temperature over 150 Celsius */
bool bTemperatureOver125IntEn; /*!< Enable interrupt when Temperature over 125 Celsius */
bool bFlagTempReadyIntEn; /*!< Enable interrupt when Flag-based temperature sensor ready */
TMU_HysteresisType eFlagTempHysteresisCon; /*!< Flag-based temperature sensor hysteresis control (on,off) */
TMU_bypassType eFlagTempFilterBypassCon; /*!< Flag-based temperature sensor filter bypass control */
bool bFlagTempEn; /*!< Flag-based temperature sensor enable */
bool bVoltageTempReadyIntEn; /*!< Enable interrupt when VVoltage-based temperature sensor ready */
bool bVoltageTempEn; /*!< Voltage-based temperature sensor enable */
bool bSmicsStopAckEn; /*!< Controls the stop ack function enable or not to the TMU0 */
TMU_TempOver150InterruptCallbackType pTemp150Notify; /*!< Flag-based temperature over 150 Celsius interrupt callback */
TMU_TempOver125InterruptCallbackType pTemp125Notify; /*!< Flag-based temperature over 125 Celsius interrupt callback */
TMU_TempFlagReadyInterruptCallbackType pFlagReadyNotify; /*!< Flag-based temperature ready interrupt callback */
TMU_TempVoltageReadyInterruptCallbackType pVoltagReadyNotify;/*!< Voltage-based temperature ready interrupt callback */
}TMU_InitType;
/**
* @brief Initialize the TMU instance
*
* @param pInitCfg the configurations of the TMU instance
*/
void TMU_Init(const TMU_InitType *const pInitCfg);
/**
* @brief Enable the Flag-based temperature sensor
*
* @return TMU_StatusType TMU_STATUS_SUCCESS when enable successfully, others fail
*/
TMU_StatusType TMU_FlagTempEnable(void);
/**
* @brief Disable the Flag-based temperature sensor
*
* @return TMU_StatusType TMU_STATUS_SUCCESS when disable successfully, others fail
*/
TMU_StatusType TMU_FlagTempDisable(void);
/**
* @brief Enable the Voltage-based temperature sensor
*
* @return TMU_StatusType TMU_STATUS_SUCCESS when enable successfully, others fail
*/
TMU_StatusType TMU_VoltageTempEnable(void);
/**
* @brief Disable the Voltage-based temperature sensor
*
* @return TMU_StatusType TMU_STATUS_SUCCESS when disable successfully, others fail
*/
TMU_StatusType TMU_VoltageTempDisable(void);
/**
* @brief Check if cleaning flag is required
*
*/
void TMU_TempOverClear(void);
/**
* @brief Get the temperature code from ADC
*
* @return uint32_t the value records the ADC conversion results for voltage-based temperature sensor result in 135 Celsius
*/
uint32_t TMU_GetTcode(void);
/**
* @brief Get the slope factor
*
* @return uint32_t the value records the slope factor for voltage-based temperature sensor
*/
uint32_t TMU_GetTslope(void);
/** @}*/ /* fc7xxx_driver_tmu */
#if defined(__cplusplus)
}
#endif
#endif

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/**
* @file module_driver_tpu.c
* @author Flagchip099
* @brief FC7xxx TPU driver source code
* @version 0.1.0
* @date 2024-1-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-1-12 Flagchip099 N/A First version for FC7240
******************************************************************************** */
#ifndef FC7XXX_DRIVER_TPU_H
#define FC7XXX_DRIVER_TPU_H
/* ----------------------------------------------------------------------------
-- TPU_H Peripheral Access Layer
---------------------------------------------------------------------------- */
#include "HwA_tpuh.h"
#include "HwA_tpue.h"
#include "HwA_scm.h"
#define TPU_TCR1_MAXVALUE 0xFFFFFFU
#define TPU_CHANNEL_NUM 32U
extern void RTT_Printf(char *fmt, ...);
#define DEBUG_INFO(str, ...) RTT_Printf(str, ##__VA_ARGS__)
/**
* @brief TPU event callback function prototype
*
*/
typedef void (*TPU_EventCallbackType)(void);
typedef void (*TPU_TCR1OverflowCallbackType)(void);
typedef void (*TPU_TCR2OverflowCallbackType)(void);
typedef void (*TPU_HSACallbackType)(void);
typedef enum
{
TPU_DutyMeasurementActiveHigh = 0x0U,
TPU_DutyMeasurementActiveLow = 0x1U,
TPU_PeriodMeasurement = 0x2U,
} TPU_MeasureModeType;
typedef enum
{
TPU_CHANNEL_0 = 0U,
TPU_CHANNEL_1 = 1U,
TPU_CHANNEL_2 = 2U,
TPU_CHANNEL_3 = 3U,
TPU_CHANNEL_4 = 4U,
TPU_CHANNEL_5 = 5U,
TPU_CHANNEL_6 = 6U,
TPU_CHANNEL_7 = 7U,
TPU_CHANNEL_8 = 8U,
TPU_CHANNEL_9 = 9U,
TPU_CHANNEL_10 = 10U,
TPU_CHANNEL_11 = 11U,
TPU_CHANNEL_12 = 12U,
TPU_CHANNEL_13 = 13U,
TPU_CHANNEL_14 = 14U,
TPU_CHANNEL_15 = 15U,
TPU_CHANNEL_16 = 16U,
TPU_CHANNEL_17 = 17U,
TPU_CHANNEL_18 = 18U,
TPU_CHANNEL_19 = 19U,
TPU_CHANNEL_20 = 20U,
TPU_CHANNEL_21 = 21U,
TPU_CHANNEL_22 = 22U,
TPU_CHANNEL_23 = 23U,
TPU_CHANNEL_24 = 24U,
TPU_CHANNEL_25 = 25U,
TPU_CHANNEL_26 = 26U,
TPU_CHANNEL_27 = 27U,
TPU_CHANNEL_28 = 28U,
TPU_CHANNEL_29 = 29U,
TPU_CHANNEL_30 = 30U,
TPU_CHANNEL_31 = 31U,
TPU_CHANNEL_MAX = TPU_E_CH_COUNT
} TPU_ChannelType;
/** TPU_H - Register Layout Typedef */
/** @brief ETPU config type */
typedef struct
{
TPUE_TimeBaseSelctionType eTBS1; /**< modulate 0 value */
TPUE_TimeBaseSelctionType eTBS2; /**< modulate 1 value */
bool bPwmUseTCR1; /**< modulate 2 value */
bool bPwmUseTCR2; /**< modulate 3 value */
uint32_t u32ActiveTime;
uint32_t u32PeriodTime;
bool bActiveHigh;
} TPU_PwmCfgType;
typedef struct
{
uint32_t u32PeriodTime;
TPU_MeasureModeType eMeasureMode;
TPUE_IPACType eInputType;
uint32_t u32SampleTime;
uint32_t u32ActiveTime;
uint32_t LastTime;
uint32_t StartTime;
} TPU_CaptureCfgType;
/**
* @brief The interrupt configurations of the Tpu channel
*
*/
typedef struct
{
bool bEventIntEn; /*!< Enable interrupt after match */
bool bTCR1OverFlowEventIntEn; /*!< Enable interrupt after TCR1 OverFlow */
bool bTCR2OverFlowEventIntEn; /*!< Enable interrupt after TCR2 OverFlow */
TPU_EventCallbackType pEventNotify; /*!< transfer complete notification */
TPU_HSACallbackType pHSANotify; /*!< HSA notification */
TPU_TCR1OverflowCallbackType pTCR1OverflowNotify;
TPU_TCR2OverflowCallbackType pTCR2OverflowNotify;
TPUH_ChTrigCFGType eChTrigType;
} TPU_InterruptCfgType;
void TPU_InitChannelInterrupt(uint8_t u8Channel, const TPU_InterruptCfgType *const pInterruptCfg);
void TPU_PwmModeInit(uint8_t u8channel, const TPU_PwmCfgType *const p_etpu_config);
void TPU_PwmServiceReq(uint8_t u8channel, uint32_t u32ActiveTime, uint32_t u32Period);
void TPU_CaptureModeInit(uint8_t u8channel, const TPU_CaptureCfgType *const p_etpu_config);
void TPU_StartChannel(void);
void TPU_SetHSR(uint8_t u8channel, uint8_t u8HSRIdx);
void TPU_SendHSR(uint8_t u8channel);
uint8_t TPU_GetHSA(uint8_t u8Channel);
void TPU_InitChannelHSAInterrupt(uint8_t u8Channel, const TPU_InterruptCfgType *const pInterruptCfg);
void TPU_InitChannelOverflowInterrupt(const TPU_InterruptCfgType *const pInterruptCfg);
void TPU_EnableSubSystem(void);
void TPU_EnableEventTrigDma(uint8_t u8Channel);
void TPU_CaptureMeasPeriodServiceReq(uint8_t u8channel, TPU_CaptureCfgType *p_etpu_config);
void TPU_CaptureMeasActivePeriodServiceReq(uint8_t u8channel, TPU_CaptureCfgType *p_etpu_config);
void TPU_DeInit(void);
void TPU_Init(void);
void TPU_EnableFlexcoreTrigDma(uint8_t u8Channel);
void TPU_EnableEventTrigTrgSel(uint8_t u8Channel, const TPU_InterruptCfgType *const pInterruptCfg);
/*!
* @}
*/ /* end of group TPU_H_Peripheral_Access_Layer */
#endif /* #ifndef FC7XXX_DRIVER_TPU_H */

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/**
* @file fc7xxx_driver_trgsel.h
* @author Flagchip0103
* @brief FC7xxx TRGSEL driver header file
* @version 0.1.0
* @date 2023-12-19
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-19 Flagchip0103 N/A First version for FC7240
******************************************************************************** */
#ifndef _DRIVER_FC7XXX_DRIVER_TRGSEL_H_
#define _DRIVER_FC7XXX_DRIVER_TRGSEL_H_
#include "device_header.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @addtogroup fc4xxx_driver_trgsel
* @{
*/
/**
* @brief TrgSel trigger targets
*
*/
typedef uint32_t TRGSEL_TargetType;
/**
* @brief TrgSel trigger sources
*
*/
typedef uint32_t TRGSEL_SourceType;
/**
* @brief The TrgSel eInstance to select
*
*/
typedef enum
{
TRGSEL_INSTANCE_0 = 0U,
TRGSEL_INSTANCE_1 = 1U,
TRGSEL_INSTANCE_2 = 2U,
TRGSEL_INSTANCE_3 = 3U,
TRGSEL_INSTANCE_4 = 4U,
TRGSEL_INSTANCE_5 = 5U,
} TRGSEL_InstanceType;
/**
* @brief TrgSel instance 0 trigger targets
*
*/
typedef enum
{
TRGSEL0_TARGET_LU0_INPUT0A = 0U,
TRGSEL0_TARGET_LU0_INPUT0B = 1U,
TRGSEL0_TARGET_LU0_INPUT0C = 2U,
TRGSEL0_TARGET_LU0_INPUT0D = 3U,
TRGSEL0_TARGET_LU0_INPUT1A = 4U,
TRGSEL0_TARGET_LU0_INPUT1B = 5U,
TRGSEL0_TARGET_LU0_INPUT1C = 6U,
TRGSEL0_TARGET_LU0_INPUT1D = 7U,
TRGSEL0_TARGET_LU0_INPUT2A = 8U,
TRGSEL0_TARGET_LU0_INPUT2B = 9U,
TRGSEL0_TARGET_LU0_INPUT2C = 10U,
TRGSEL0_TARGET_LU0_INPUT2D = 11U,
TRGSEL0_TARGET_LU0_INPUT3A = 12U,
TRGSEL0_TARGET_LU0_INPUT3B = 13U,
TRGSEL0_TARGET_LU0_INPUT3C = 14U,
TRGSEL0_TARGET_LU0_INPUT3D = 15U,
TRGSEL0_TARGET_TRGSEL1_INPUT0 = 16U,
TRGSEL0_TARGET_TRGSEL1_INPUT1 = 17U,
TRGSEL0_TARGET_TRGSEL1_INPUT2 = 18U,
TRGSEL0_TARGET_TRGSEL1_INPUT3 = 19U,
TRGSEL0_TARGET_TRGSEL1_INPUT4 = 20U,
TRGSEL0_TARGET_TRGSEL1_INPUT5 = 21U,
TRGSEL0_TARGET_TRGSEL1_INPUT6 = 22U,
TRGSEL0_TARGET_TRGSEL1_INPUT7 = 23U,
TRGSEL0_TARGET_FTU0_TRG0 = 24U,
TRGSEL0_TARGET_FTU1_TRG0 = 25U,
TRGSEL0_TARGET_FTU2_TRG0 = 26U,
TRGSEL0_TARGET_FTU3_TRG0 = 27U,
TRGSEL0_TARGET_FTU4_TRG0 = 28U,
TRGSEL0_TARGET_FTU5_TRG0 = 29U,
TRGSEL0_TARGET_FTU6_TRG0 = 30U,
TRGSEL0_TARGET_FTU7_TRG0 = 31U,
TRGSEL0_TARGET_SENT0_CH0TRG = 32U,
TRGSEL0_TARGET_SENT0_CH1TRG = 33U,
TRGSEL0_TARGET_SENT0_CH2TRG = 34U,
TRGSEL0_TARGET_SENT0_CH3TRG = 35U,
TRGSEL0_TARGET_CMP0_SAMPLE_EN = 36U,
TRGSEL0_TARGET_CMP1_SAMPLE_EN = 37U,
} TrgSel0_TargetType;
/**
* @brief TrgSel instance 1 trigger targets
*
*/
typedef enum
{
TRGSEL1_TARGET_DMA_CH0 = 0U,
TRGSEL1_TARGET_DMA_CH1 = 1U,
TRGSEL1_TARGET_DMA_CH2 = 2U,
TRGSEL1_TARGET_DMA_CH3 = 3U,
TRGSEL1_TARGET_TRGSEL_OUT0 = 4U,
TRGSEL1_TARGET_TRGSEL_OUT1 = 5U,
TRGSEL1_TARGET_TRGSEL_OUT2 = 6U,
TRGSEL1_TARGET_TRGSEL_OUT3 = 7U,
TRGSEL1_TARGET_TRGSEL_OUT4 = 8U,
TRGSEL1_TARGET_TRGSEL_OUT5 = 9U,
TRGSEL1_TARGET_TRGSEL_OUT6 = 10U,
TRGSEL1_TARGET_TRGSEL_OUT7 = 11U,
TRGSEL1_TARGET_FCUART0_TRGI = 12U,
TRGSEL1_TARGET_FCUART1_TRGI = 13U,
TRGSEL1_TARGET_FCUART2_TRGI = 14U,
TRGSEL1_TARGET_FCUART3_TRGI = 15U,
TRGSEL1_TARGET_FCUART4_TRGI = 16U,
TRGSEL1_TARGET_FCUART5_TRGI = 17U,
TRGSEL1_TARGET_FCUART6_TRGI = 18U,
TRGSEL1_TARGET_FCUART7_TRGI = 19U,
TRGSEL1_TARGET_FCSPI0_TRGI = 20U,
TRGSEL1_TARGET_FCSPI1_TRGI = 21U,
TRGSEL1_TARGET_FCSPI2_TRGI = 22U,
TRGSEL1_TARGET_FCSPI3_TRGI = 23U,
TRGSEL1_TARGET_FCSPI4_TRGI = 24U,
TRGSEL1_TARGET_FCSPI5_TRGI = 25U,
TRGSEL1_TARGET_FCIIC0_TRGI = 26U,
TRGSEL1_TARGET_FCIIC1_TRGI = 27U
} TrgSel1_TargetType;
/**
* @brief TrgSel instance 2 trigger targets
*
*/
typedef enum
{
TRGSEL2_TARGET_FTU0_FLT0 = 0U,
TRGSEL2_TARGET_FTU0_FLT1 = 1U,
TRGSEL2_TARGET_FTU1_FLT0 = 2U,
TRGSEL2_TARGET_FTU1_FLT1 = 3U,
TRGSEL2_TARGET_FTU2_FLT0 = 4U,
TRGSEL2_TARGET_FTU2_FLT1 = 5U,
TRGSEL2_TARGET_FTU3_FLT0 = 6U,
TRGSEL2_TARGET_FTU3_FLT1 = 7U,
TRGSEL2_TARGET_FTU4_FLT0 = 8U,
TRGSEL2_TARGET_FTU4_FLT1 = 9U,
TRGSEL2_TARGET_FTU5_FLT0 = 10U,
TRGSEL2_TARGET_FTU5_FLT1 = 11U,
TRGSEL2_TARGET_FTU6_FLT0 = 12U,
TRGSEL2_TARGET_FTU6_FLT1 = 13U,
TRGSEL2_TARGET_FTU7_FLT0 = 14U,
TRGSEL2_TARGET_FTU7_FLT1 = 15U,
TRGSEL2_TARGET_FTU0_TRG1 = 16U,
TRGSEL2_TARGET_FTU1_TRG1 = 17U,
TRGSEL2_TARGET_FTU2_TRG1 = 18U,
TRGSEL2_TARGET_FTU3_TRG1 = 19U,
TRGSEL2_TARGET_FTU4_TRG1 = 20U,
TRGSEL2_TARGET_FTU5_TRG1 = 21U,
TRGSEL2_TARGET_FTU6_TRG1 = 22U,
TRGSEL2_TARGET_FTU7_TRG1 = 23U,
TRGSEL2_TARGET_MSC0_INJ0 = 24U,
TRGSEL2_TARGET_MSC0_INJ1 = 25U,
TRGSEL2_TARGET_TPU_FLTIN0 = 26U,
TRGSEL2_TARGET_TPU_FLTIN1 = 27U,
TRGSEL2_TARGET_TPU_FLTIN2 = 28U,
TRGSEL2_TARGET_TPU_FLTIN3 = 29U,
} TrgSel2_TargetType;
/**
* @brief TrgSel instance 3 trigger targets
*
*/
typedef enum
{
TRGSEL3_TARGET_ISM0_MON0 = 0U,
TRGSEL3_TARGET_ISM0_MON1 = 1U,
TRGSEL3_TARGET_ISM0_MON2 = 2U,
TRGSEL3_TARGET_ISM0_MON3 = 3U,
TRGSEL3_TARGET_ISM0_MON4 = 4U,
TRGSEL3_TARGET_ISM0_MON5 = 5U,
TRGSEL3_TARGET_ISM0_MON6 = 6U,
TRGSEL3_TARGET_ISM0_MON7 = 7U,
TRGSEL3_TARGET_ISM0_REF0 = 8U,
TRGSEL3_TARGET_ISM0_REF1 = 9U,
TRGSEL3_TARGET_ISM0_REF2 = 10U,
TRGSEL3_TARGET_ISM0_REF3 = 11U,
TRGSEL3_TARGET_ISM0_REF4 = 12U,
TRGSEL3_TARGET_ISM0_REF5 = 13U,
TRGSEL3_TARGET_ISM0_REF6 = 14U,
TRGSEL3_TARGET_ISM0_REF7 = 15U,
} TrgSel3_TargetType;
/**
* @brief TrgSel instance 4 trigger targets
*
*/
typedef enum
{
TRGSEL4_TARGET_ADC0_TRG0 = 0U,
TRGSEL4_TARGET_ADC0_TRG1 = 1U,
TRGSEL4_TARGET_ADC0_TRG2 = 2U,
TRGSEL4_TARGET_ADC0_TRG3 = 3U,
TRGSEL4_TARGET_ADC1_TRG0 = 4U,
TRGSEL4_TARGET_ADC1_TRG1 = 5U,
TRGSEL4_TARGET_ADC1_TRG2 = 6U,
TRGSEL4_TARGET_ADC1_TRG3 = 7U,
TRGSEL4_TARGET_PTIMER0_TRG = 8U,
TRGSEL4_TARGET_PTIMER1_TRG = 9U,
} TrgSel4_TargetType;
/**
* @brief TrgSel instance 5 trigger targets
*
*/
typedef enum
{
TRGSEL5_TARGET_TPU_INT_CH24 = 0U,
TRGSEL5_TARGET_TPU_INT_CH25 = 1U,
TRGSEL5_TARGET_TPU_INT_CH26 = 2U,
TRGSEL5_TARGET_TPU_INT_CH27 = 3U,
TRGSEL5_TARGET_TPU_INT_CH28 = 4U,
TRGSEL5_TARGET_TPU_INT_CH29 = 5U,
TRGSEL5_TARGET_TPU_INT_CH30 = 6U,
TRGSEL5_TARGET_TPU_INT_CH31 = 7U,
TRGSEL5_TARGET_FCPIT0_TRG_CH0 = 8U,
TRGSEL5_TARGET_FCPIT0_TRG_CH1 = 9U,
TRGSEL5_TARGET_FCPIT0_TRG_CH2 = 10U,
TRGSEL5_TARGET_FCPIT0_TRG_CH3 = 11U,
TRGSEL5_TARGET_AONTIMER0_CLK3 = 12U,
} TrgSel5_TargetType;
/**
* @brief TrgSel instance 0 trigger sources
*
*/
typedef enum
{
TRGSEL0_SRC_VSS = 0U,
TRGSEL0_SRC_VDD = 1U,
TRGSEL0_SRC_SCM0_SW_TRG0 = 2U,
TRGSEL0_SRC_SCM0_SW_TRG1 = 3U,
TRGSEL0_SRC_SCM0_SW_TRG2 = 4U,
TRGSEL0_SRC_SCM0_SW_TRG3 = 5U,
TRGSEL0_SRC_TRGSEL_IN0 = 6U,
TRGSEL0_SRC_TRGSEL_IN1 = 7U,
TRGSEL0_SRC_TRGSEL_IN2 = 8U,
TRGSEL0_SRC_TRGSEL_IN3 = 9U,
TRGSEL0_SRC_TRGSEL_IN4 = 10U,
TRGSEL0_SRC_TRGSEL_IN5 = 11U,
TRGSEL0_SRC_TRGSEL_IN6 = 12U,
TRGSEL0_SRC_TRGSEL_IN7 = 13U,
TRGSEL0_SRC_TRGSEL_IN8 = 14U,
TRGSEL0_SRC_TRGSEL_IN9 = 15U,
TRGSEL0_SRC_TRGSEL_IN10 = 16U,
TRGSEL0_SRC_TRGSEL_IN11 = 17U,
TRGSEL0_SRC_TRGSEL_IN12 = 18U,
TRGSEL0_SRC_TRGSEL_IN13 = 19U,
TRGSEL0_SRC_TRGSEL_IN14 = 20U,
TRGSEL0_SRC_TRGSEL_IN15 = 21U,
TRGSEL0_SRC_CMP0_OUT = 22U,
TRGSEL0_SRC_CMP1_OUT = 23U,
TRGSEL0_SRC_FCPIT0_CH0 = 24U,
TRGSEL0_SRC_FCPIT0_CH1 = 25U,
TRGSEL0_SRC_FCPIT0_CH2 = 26U,
TRGSEL0_SRC_FCPIT0_CH3 = 27U,
TRGSEL0_SRC_AONTIMER0_TRGO = 28U,
TRGSEL0_SRC_FTU0_RELOAD_TRG = 29U,
TRGSEL0_SRC_FTU0_MATCH_TRG = 30U,
TRGSEL0_SRC_FTU1_RELOAD_TRG = 31U,
TRGSEL0_SRC_FTU1_MATCH_TRG = 32U,
TRGSEL0_SRC_FTU2_RELOAD_TRG = 33U,
TRGSEL0_SRC_FTU2_MATCH_TRG = 34U,
TRGSEL0_SRC_FTU3_RELOAD_TRG = 35U,
TRGSEL0_SRC_FTU3_MATCH_TRG = 36U,
TRGSEL0_SRC_FTU4_RELOAD_TRG = 37U,
TRGSEL0_SRC_FTU4_MATCH_TRG = 38U,
TRGSEL0_SRC_FTU5_RELOAD_TRG = 39U,
TRGSEL0_SRC_FTU5_MATCH_TRG = 40U,
TRGSEL0_SRC_FTU6_RELOAD_TRG = 41U,
TRGSEL0_SRC_FTU6_MATCH_TRG = 42U,
TRGSEL0_SRC_FTU7_RELOAD_TRG = 43U,
TRGSEL0_SRC_FTU7_MATCH_TRG = 44U,
TRGSEL0_SRC_LU0_OUT0A = 45U,
TRGSEL0_SRC_LU0_OUT1A = 46U,
TRGSEL0_SRC_LU0_OUT2A = 47U,
TRGSEL0_SRC_LU0_OUT3A = 48U,
TRGSEL0_SRC_LU0_OUT0B = 49U,
TRGSEL0_SRC_LU0_OUT1B = 50U,
TRGSEL0_SRC_LU0_OUT2B = 51U,
TRGSEL0_SRC_LU0_OUT3B = 52U,
TRGSEL0_SRC_PTIMER0_ADCCH0_TRG = 53U,
TRGSEL0_SRC_PTIMER0_PULSE = 54U,
TRGSEL0_SRC_ADC0_EOSG0 = 55U,
TRGSEL0_SRC_ADC0_EOSG1 = 56U,
TRGSEL0_SRC_ADC0_EOSG2 = 57U,
TRGSEL0_SRC_ADC0_EOSG3 = 58U,
TRGSEL0_SRC_PTIMER1_ADCCH0_TRG = 59U,
TRGSEL0_SRC_PTIMER1_PULSE = 60U,
TRGSEL0_SRC_ADC1_EOSG0 = 61U,
TRGSEL0_SRC_ADC1_EOSG1 = 62U,
TRGSEL0_SRC_ADC1_EOSG2 = 63U,
TRGSEL0_SRC_ADC1_EOSG3 = 64U,
TRGSEL0_SRC_RTC_ALARM = 65U,
TRGSEL0_SRC_RTC_SECOND = 66U,
TRGSEL0_SRC_GPIOA_TRG = 67U,
TRGSEL0_SRC_GPIOB_TRG = 68U,
TRGSEL0_SRC_GPIOC_TRG = 69U,
TRGSEL0_SRC_GPIOD_TRG = 70U,
TRGSEL0_SRC_GPIOE_TRG = 71U,
TRGSEL0_SRC_FTU0_CH0_OUT = 72U,
TRGSEL0_SRC_FTU0_CH1_OUT = 73U,
TRGSEL0_SRC_FTU0_CH2_OUT = 74U,
TRGSEL0_SRC_FTU0_CH3_OUT = 75U,
TRGSEL0_SRC_FTU0_CH4_OUT = 76U,
TRGSEL0_SRC_FTU0_CH5_OUT = 77U,
TRGSEL0_SRC_FTU0_CH6_OUT = 78U,
TRGSEL0_SRC_FTU0_CH7_OUT = 79U,
TRGSEL0_SRC_FTU3_CH0_OUT = 80U,
TRGSEL0_SRC_FTU3_CH1_OUT = 81U,
TRGSEL0_SRC_FTU3_CH2_OUT = 82U,
TRGSEL0_SRC_FTU3_CH3_OUT = 83U,
TRGSEL0_SRC_FTU3_CH4_OUT = 84U,
TRGSEL0_SRC_FTU3_CH5_OUT = 85U,
TRGSEL0_SRC_FTU3_CH6_OUT = 86U,
TRGSEL0_SRC_FTU3_CH7_OUT = 87U,
TRGSEL0_SRC_FTU6_CH0_OUT = 88U,
TRGSEL0_SRC_FTU6_CH1_OUT = 89U,
TRGSEL0_SRC_FTU6_CH2_OUT = 90U,
TRGSEL0_SRC_FTU6_CH3_OUT = 91U,
TRGSEL0_SRC_FTU6_CH4_OUT = 92U,
TRGSEL0_SRC_FTU6_CH5_OUT = 93U,
TRGSEL0_SRC_FTU6_CH6_OUT = 94U,
TRGSEL0_SRC_FTU6_CH7_OUT = 95U,
TRGSEL0_SRC_TPU_TRG0 = 96U,
TRGSEL0_SRC_TPU_TRG1 = 97U,
TRGSEL0_SRC_TPU_TRG2 = 98U,
TRGSEL0_SRC_TPU_TRG3 = 99U,
TRGSEL0_SRC_TPU_TRG4 = 100U,
TRGSEL0_SRC_TPU_TRG5 = 101U,
TRGSEL0_SRC_TPU_TRG6 = 102U,
TRGSEL0_SRC_TPU_TRG7 = 103U,
TRGSEL0_SRC_TPU_TRG8 = 104U,
TRGSEL0_SRC_TPU_TRG9 = 105U,
TRGSEL0_SRC_TPU_TRG10 = 106U,
TRGSEL0_SRC_TPU_TRG11 = 107U,
TRGSEL0_SRC_TPU_TRG12 = 108U,
TRGSEL0_SRC_TPU_TRG13 = 109U,
TRGSEL0_SRC_TPU_TRG14 = 110U,
TRGSEL0_SRC_TPU_TRG15 = 111U,
TRGSEL0_SRC_TPU_TRG16 = 112U,
TRGSEL0_SRC_TPU_TRG17 = 113U,
TRGSEL0_SRC_TPU_TRG18 = 114U,
TRGSEL0_SRC_TPU_TRG19 = 115U,
TRGSEL0_SRC_TPU_TRG20 = 116U,
TRGSEL0_SRC_TPU_TRG21 = 117U,
TRGSEL0_SRC_TPU_TRG22 = 118U,
TRGSEL0_SRC_TPU_TRG23 = 119U,
TRGSEL0_SRC_TPU_TRG24 = 120U,
TRGSEL0_SRC_TPU_TRG25 = 121U,
TRGSEL0_SRC_TPU_TRG26 = 122U,
TRGSEL0_SRC_TPU_TRG27 = 123U,
TRGSEL0_SRC_TPU_TRG28 = 124U,
TRGSEL0_SRC_TPU_TRG29 = 125U,
TRGSEL0_SRC_TPU_TRG30 = 126U,
TRGSEL0_SRC_TPU_TRG31 = 127U,
} TrgSel0_SourceType;
/**
* @brief TrgSel instance 1 trigger sources
*
*/
typedef enum
{
TRGSEL1_SRC_VSS = 0U,
TRGSEL1_SRC_VDD = 1U,
TRGSEL1_SRC_SCM0_SW_TRG4 = 2U,
TRGSEL1_SRC_SCM0_SW_TRG5 = 3U,
TRGSEL1_SRC_SCM0_SW_TRG6 = 4U,
TRGSEL1_SRC_SCM0_SW_TRG7 = 5U,
TRGSEL1_SRC_TRGSEL_IN0 = 6U,
TRGSEL1_SRC_TRGSEL_IN1 = 7U,
TRGSEL1_SRC_TRGSEL_IN2 = 8U,
TRGSEL1_SRC_TRGSEL_IN3 = 9U,
TRGSEL1_SRC_TRGSEL_IN4 = 10U,
TRGSEL1_SRC_TRGSEL_IN5 = 11U,
TRGSEL1_SRC_TRGSEL_IN6 = 12U,
TRGSEL1_SRC_TRGSEL_IN7 = 13U,
TRGSEL1_SRC_TRGSEL_IN8 = 14U,
TRGSEL1_SRC_TRGSEL_IN9 = 15U,
TRGSEL1_SRC_TRGSEL_IN10 = 16U,
TRGSEL1_SRC_TRGSEL_IN11 = 17U,
TRGSEL1_SRC_TRGSEL_IN12 = 18U,
TRGSEL1_SRC_TRGSEL_IN13 = 19U,
TRGSEL1_SRC_TRGSEL_IN14 = 20U,
TRGSEL1_SRC_TRGSEL_IN15 = 21U,
TRGSEL1_SRC_CMP0_OUT = 22U,
TRGSEL1_SRC_CMP1_OUT = 23U,
TRGSEL1_SRC_FCPIT0_CH0 = 24U,
TRGSEL1_SRC_FCPIT0_CH1 = 25U,
TRGSEL1_SRC_FCPIT0_CH2 = 26U,
TRGSEL1_SRC_FCPIT0_CH3 = 27U,
TRGSEL1_SRC_AONTIMER0_TRGO = 28U,
TRGSEL1_SRC_LU0_OUT0A = 29U,
TRGSEL1_SRC_LU0_OUT1A = 30U,
TRGSEL1_SRC_LU0_OUT2A = 31U,
TRGSEL1_SRC_LU0_OUT3A = 32U,
TRGSEL1_SRC_LU0_OUT0B = 33U,
TRGSEL1_SRC_LU0_OUT1B = 34U,
TRGSEL1_SRC_LU0_OUT2B = 35U,
TRGSEL1_SRC_LU0_OUT3B = 36U,
TRGSEL1_SRC_RTC_ALARM = 37U,
TRGSEL1_SRC_RTC_SECOND = 38U,
TRGSEL1_SRC_GPIOA_TRG = 39U,
TRGSEL1_SRC_GPIOB_TRG = 40U,
TRGSEL1_SRC_GPIOC_TRG = 41U,
TRGSEL1_SRC_GPIOD_TRG = 42U,
TRGSEL1_SRC_GPIOE_TRG = 43U,
TRGSEL1_SRC_TRGSEL1_INPUT0 = 44U,
TRGSEL1_SRC_TRGSEL1_INPUT1 = 45U,
TRGSEL1_SRC_TRGSEL1_INPUT2 = 46U,
TRGSEL1_SRC_TRGSEL1_INPUT3 = 47U,
TRGSEL1_SRC_TRGSEL1_INPUT4 = 48U,
TRGSEL1_SRC_TRGSEL1_INPUT5 = 49U,
TRGSEL1_SRC_TRGSEL1_INPUT6 = 50U,
TRGSEL1_SRC_TRGSEL1_INPUT7 = 51U,
TRGSEL1_SRC_FCIIC0_MTRG = 52U,
TRGSEL1_SRC_FCIIC0_STRG = 53U,
TRGSEL1_SRC_FCIIC1_MTRG = 54U,
TRGSEL1_SRC_FCIIC1_STRG = 55U,
TRGSEL1_SRC_FCSPI0_FRAME = 56U,
TRGSEL1_SRC_FCSPI0_RX_DONE = 57U,
TRGSEL1_SRC_FCSPI1_FRAME = 58U,
TRGSEL1_SRC_FCSPI1_RX_DONE = 59U,
TRGSEL1_SRC_FCSPI2_FRAME = 60U,
TRGSEL1_SRC_FCSPI2_RX_DONE = 61U,
TRGSEL1_SRC_FCSPI3_FRAME = 62U,
TRGSEL1_SRC_FCSPI3_RX_DONE = 63U,
TRGSEL1_SRC_FCSPI4_FRAME = 64U,
TRGSEL1_SRC_FCSPI4_RX_DONE = 65U,
TRGSEL1_SRC_FCSPI5_FRAME = 66U,
TRGSEL1_SRC_FCSPI5_RX_DONE = 67U,
TRGSEL1_SRC_FCUART0_RX_DONE = 68U,
TRGSEL1_SRC_FCUART0_TX_DONE = 69U,
TRGSEL1_SRC_FCUART0_RX_IDLE = 70U,
TRGSEL1_SRC_FCUART1_RX_DONE = 71U,
TRGSEL1_SRC_FCUART1_TX_DONE = 72U,
TRGSEL1_SRC_FCUART1_RX_IDLE = 73U,
TRGSEL1_SRC_FCUART2_RX_DONE = 74U,
TRGSEL1_SRC_FCUART2_TX_DONE = 75U,
TRGSEL1_SRC_FCUART2_RX_IDLE = 76U,
TRGSEL1_SRC_FCUART3_RX_DONE = 77U,
TRGSEL1_SRC_FCUART3_TX_DONE = 78U,
TRGSEL1_SRC_FCUART3_RX_IDLE = 79U,
TRGSEL1_SRC_FCUART4_RX_DONE = 80U,
TRGSEL1_SRC_FCUART4_TX_DONE = 81U,
TRGSEL1_SRC_FCUART4_RX_IDLE = 82U,
TRGSEL1_SRC_FCUART5_RX_DONE = 83U,
TRGSEL1_SRC_FCUART5_TX_DONE = 84U,
TRGSEL1_SRC_FCUART5_RX_IDLE = 85U,
TRGSEL1_SRC_FCUART6_RX_DONE = 86U,
TRGSEL1_SRC_FCUART6_TX_DONE = 87U,
TRGSEL1_SRC_FCUART6_RX_IDLE = 88U,
TRGSEL1_SRC_FCUART7_RX_DONE = 89U,
TRGSEL1_SRC_FCUART7_TX_DONE = 90U,
TRGSEL1_SRC_FCUART7_RX_IDLE = 91U,
TRGSEL1_SRC_ADC0_CMP = 92U,
TRGSEL1_SRC_ADC1_CMP = 93U
} TrgSel1_SourceType;
/**
* @brief TrgSel instance 2 trigger sources
*
*/
typedef enum
{
TRGSEL2_SRC_VSS = 0U,
TRGSEL2_SRC_VDD = 1U,
TRGSEL2_SRC_TRGSEL_OUT0 = 2U,
TRGSEL2_SRC_TRGSEL_OUT1 = 3U,
TRGSEL2_SRC_TRGSEL_OUT2 = 4U,
TRGSEL2_SRC_TRGSEL_OUT3 = 5U,
TRGSEL2_SRC_TRGSEL_OUT4 = 6U,
TRGSEL2_SRC_TRGSEL_OUT5 = 7U,
TRGSEL2_SRC_TRGSEL_OUT6 = 8U,
TRGSEL2_SRC_TRGSEL_OUT7 = 9U,
TRGSEL2_SRC_FTU_FLT0 = 10U,
TRGSEL2_SRC_FTU_FLT1 = 11U,
TRGSEL2_SRC_FTU_FLT2 = 12U,
TRGSEL2_SRC_FTU_FLT3 = 13U,
TRGSEL2_SRC_FTU_FLT4 = 14U,
TRGSEL2_SRC_FTU_FLT5 = 15U,
TRGSEL2_SRC_FTU_FLT6 = 16U,
TRGSEL2_SRC_FTU_FLT7 = 17U,
TRGSEL2_SRC_FTU_FLT8 = 18U,
TRGSEL2_SRC_FTU_FLT9 = 19U,
TRGSEL2_SRC_FTU_FLT10 = 20U,
TRGSEL2_SRC_FTU_FLT11 = 21U,
TRGSEL2_SRC_FTU_FLT12 = 22U,
TRGSEL2_SRC_FTU_FLT13 = 23U,
TRGSEL2_SRC_FTU_FLT14 = 24U,
TRGSEL2_SRC_FTU_FLT15 = 25U,
TRGSEL2_SRC_FTU_FLT16 = 26U,
TRGSEL2_SRC_FTU_FLT17 = 27U,
TRGSEL2_SRC_FTU_FLT18 = 28U,
TRGSEL2_SRC_FTU_FLT19 = 29U,
TRGSEL2_SRC_FTU_FLT20 = 30U,
TRGSEL2_SRC_FTU_FLT21 = 31U
} TrgSel2_SourceType;
/**
* @brief TrgSel instance 3 trigger sources
*
*/
typedef enum
{
TRGSEL3_SRC_VSS = 0U,
TRGSEL3_SRC_VDD = 1U,
TRGSEL3_SRC_TRGSEL_OUT0 = 2U,
TRGSEL3_SRC_TRGSEL_OUT1 = 3U,
TRGSEL3_SRC_TRGSEL_OUT2 = 4U,
TRGSEL3_SRC_TRGSEL_OUT3 = 5U,
TRGSEL3_SRC_TRGSEL_OUT4 = 6U,
TRGSEL3_SRC_TRGSEL_OUT5 = 7U,
TRGSEL3_SRC_TRGSEL_OUT6 = 8U,
TRGSEL3_SRC_TRGSEL_OUT7 = 9U,
TRGSEL3_SRC_TRGSEL1_INPUT0 = 10U,
TRGSEL3_SRC_TRGSEL1_INPUT1 = 11U,
TRGSEL3_SRC_TRGSEL1_INPUT2 = 12U,
TRGSEL3_SRC_TRGSEL1_INPUT3 = 13U,
TRGSEL3_SRC_TRGSEL1_INPUT4 = 14U,
TRGSEL3_SRC_TRGSEL1_INPUT5 = 15U,
TRGSEL3_SRC_TRGSEL1_INPUT6 = 16U,
TRGSEL3_SRC_TRGSEL1_INPUT7 = 17U,
TRGSEL3_SRC_LU0_OUT0A = 18U,
TRGSEL3_SRC_LU1_OUT0A = 19U,
TRGSEL3_SRC_LU2_OUT0A = 20U,
TRGSEL3_SRC_LU3_OUT0A = 21U,
TRGSEL3_SRC_FTU_IN0 = 22U,
TRGSEL3_SRC_FTU_IN1 = 23U,
TRGSEL3_SRC_FTU_IN2 = 24U,
TRGSEL3_SRC_FTU_IN3 = 25U,
TRGSEL3_SRC_FTU_IN4 = 26U,
TRGSEL3_SRC_FTU_IN5 = 27U,
TRGSEL3_SRC_FTU_IN6 = 28U,
TRGSEL3_SRC_FTU_IN7 = 29U,
TRGSEL3_SRC_FTU_IN8 = 30U,
TRGSEL3_SRC_FTU_IN9 = 31U,
TRGSEL3_SRC_FTU_IN10 = 32U,
TRGSEL3_SRC_FTU_IN11 = 33U,
TRGSEL3_SRC_FTU_IN12 = 34U,
TRGSEL3_SRC_FTU_IN13 = 35U,
TRGSEL3_SRC_FTU_IN14 = 36U,
TRGSEL3_SRC_FTU_IN15 = 37U,
TRGSEL3_SRC_FTU_OUT0 = 38U,
TRGSEL3_SRC_FTU_OUT1 = 39U,
TRGSEL3_SRC_FTU_OUT2 = 40U,
TRGSEL3_SRC_FTU_OUT3 = 41U,
TRGSEL3_SRC_FTU_OUT4 = 42U,
TRGSEL3_SRC_FTU_OUT5 = 43U,
TRGSEL3_SRC_FTU_OUT6 = 44U,
TRGSEL3_SRC_FTU_OUT7 = 45U,
TRGSEL3_SRC_FTU_OUT8 = 46U,
TRGSEL3_SRC_FTU_OUT9 = 47U,
TRGSEL3_SRC_FTU_OUT10 = 48U,
TRGSEL3_SRC_FTU_OUT11 = 49U,
TRGSEL3_SRC_FTU_OUT12 = 50U,
TRGSEL3_SRC_FTU_OUT13 = 51U,
TRGSEL3_SRC_FTU_OUT14 = 52U,
TRGSEL3_SRC_FTU_OUT15 = 53U,
TRGSEL3_SRC_TPU_CH0 = 54U,
TRGSEL3_SRC_TPU_CH1 = 55U,
TRGSEL3_SRC_TPU_CH2 = 56U,
TRGSEL3_SRC_TPU_CH3 = 57U,
TRGSEL3_SRC_TPU_CH4 = 58U,
TRGSEL3_SRC_TPU_CH5 = 59U,
TRGSEL3_SRC_TPU_CH6 = 60U,
TRGSEL3_SRC_TPU_CH7 = 61U,
} TrgSel3_SourceType;
/**
* @brief TrgSel instance 4 trigger sources
*
*/
typedef enum
{
TRGSEL4_SRC_VSS = 0U,
TRGSEL4_SRC_VDD = 1U,
TRGSEL4_SRC_SCM0_SW_TRG0 = 2U,
TRGSEL4_SRC_SCM0_SW_TRG1 = 3U,
TRGSEL4_SRC_SCM0_SW_TRG2 = 4U,
TRGSEL4_SRC_SCM0_SW_TRG3 = 5U,
TRGSEL4_SRC_TRGSEL_IN8 = 6U,
TRGSEL4_SRC_TRGSEL_IN9 = 7U,
TRGSEL4_SRC_TRGSEL_IN10 = 8U,
TRGSEL4_SRC_TRGSEL_IN11 = 9U,
TRGSEL4_SRC_TRGSEL_IN12 = 10U,
TRGSEL4_SRC_TRGSEL_IN13 = 11U,
TRGSEL4_SRC_TRGSEL_IN14 = 12U,
TRGSEL4_SRC_TRGSEL_IN15 = 13U,
TRGSEL4_SRC_LU0_OUT0A = 14U,
TRGSEL4_SRC_LU0_OUT1A = 15U,
TRGSEL4_SRC_LU0_OUT2A = 16U,
TRGSEL4_SRC_LU0_OUT3A = 17U,
TRGSEL4_SRC_LU0_OUT0B = 18U,
TRGSEL4_SRC_LU0_OUT1B = 19U,
TRGSEL4_SRC_LU0_OUT2B = 20U,
TRGSEL4_SRC_LU0_OUT3B = 21U,
TRGSEL4_SRC_FCPIT0_CH0 = 22U,
TRGSEL4_SRC_FCPIT0_CH1 = 23U,
TRGSEL4_SRC_FCPIT0_CH2 = 24U,
TRGSEL4_SRC_FCPIT0_CH3 = 25U,
TRGSEL4_SRC_TRGSEL1_INPUT0 = 26U,
TRGSEL4_SRC_TRGSEL1_INPUT1 = 27U,
TRGSEL4_SRC_TRGSEL1_INPUT2 = 28U,
TRGSEL4_SRC_TRGSEL1_INPUT3 = 29U,
TRGSEL4_SRC_TRGSEL1_INPUT4 = 30U,
TRGSEL4_SRC_TRGSEL1_INPUT5 = 31U,
TRGSEL4_SRC_TRGSEL1_INPUT6 = 32U,
TRGSEL4_SRC_TRGSEL1_INPUT7 = 33U,
TRGSEL4_SRC_FTU0_RELOAD_TRG = 34U,
TRGSEL4_SRC_FTU0_MATCH_TRG = 35U,
TRGSEL4_SRC_FTU1_RELOAD_TRG = 36U,
TRGSEL4_SRC_FTU1_MATCH_TRG = 37U,
TRGSEL4_SRC_FTU2_RELOAD_TRG = 38U,
TRGSEL4_SRC_FTU2_MATCH_TRG = 39U,
TRGSEL4_SRC_FTU3_RELOAD_TRG = 40U,
TRGSEL4_SRC_FTU3_MATCH_TRG = 41U,
TRGSEL4_SRC_FTU4_RELOAD_TRG = 42U,
TRGSEL4_SRC_FTU4_MATCH_TRG = 43U,
TRGSEL4_SRC_FTU5_RELOAD_TRG = 44U,
TRGSEL4_SRC_FTU5_MATCH_TRG = 45U,
TRGSEL4_SRC_FTU6_RELOAD_TRG = 46U,
TRGSEL4_SRC_FTU6_MATCH_TRG = 47U,
TRGSEL4_SRC_FTU7_RELOAD_TRG = 48U,
TRGSEL4_SRC_FTU7_MATCH_TRG = 49U,
TRGSEL4_SRC_FTU0_CH0_OUT = 50U,
TRGSEL4_SRC_FTU0_CH1_OUT = 51U,
TRGSEL4_SRC_FTU0_CH2_OUT = 52U,
TRGSEL4_SRC_FTU0_CH3_OUT = 53U,
TRGSEL4_SRC_FTU0_CH4_OUT = 54U,
TRGSEL4_SRC_FTU0_CH5_OUT = 55U,
TRGSEL4_SRC_FTU0_CH6_OUT = 56U,
TRGSEL4_SRC_FTU0_CH7_OUT = 57U,
TRGSEL4_SRC_FTU3_CH0_OUT = 58U,
TRGSEL4_SRC_FTU3_CH1_OUT = 59U,
TRGSEL4_SRC_FTU3_CH2_OUT = 60U,
TRGSEL4_SRC_FTU3_CH3_OUT = 61U,
TRGSEL4_SRC_FTU3_CH4_OUT = 62U,
TRGSEL4_SRC_FTU3_CH5_OUT = 63U,
TRGSEL4_SRC_FTU3_CH6_OUT = 64U,
TRGSEL4_SRC_FTU3_CH7_OUT = 65U,
TRGSEL4_SRC_PTIMER0_ADCCH0_TRG = 66U,
TRGSEL4_SRC_PTIMER0_PULSE = 67U,
TRGSEL4_SRC_ADC0_EOSG0 = 68U,
TRGSEL4_SRC_ADC0_EOSG1 = 69U,
TRGSEL4_SRC_ADC0_EOSG2 = 70U,
TRGSEL4_SRC_ADC0_EOSG3 = 71U,
TRGSEL4_SRC_PTIMER1_ADCCH0_TRG = 72U,
TRGSEL4_SRC_PTIMER1_PULSE = 73U,
TRGSEL4_SRC_ADC1_EOSG0 = 74U,
TRGSEL4_SRC_ADC1_EOSG1 = 75U,
TRGSEL4_SRC_ADC1_EOSG2 = 76U,
TRGSEL4_SRC_ADC1_EOSG3 = 77U,
TRGSEL4_SRC_CMP0_OUT = 78U,
TRGSEL4_SRC_CMP1_OUT = 79U,
TRGSEL4_SRC_TPU_TRG0 = 80U,
TRGSEL4_SRC_TPU_TRG1 = 81U,
TRGSEL4_SRC_TPU_TRG2 = 82U,
TRGSEL4_SRC_TPU_TRG3 = 83U,
TRGSEL4_SRC_TPU_TRG4 = 84U,
TRGSEL4_SRC_TPU_TRG5 = 85U,
TRGSEL4_SRC_TPU_TRG6 = 86U,
TRGSEL4_SRC_TPU_TRG7 = 87U,
TRGSEL4_SRC_TPU_TRG8 = 88U,
TRGSEL4_SRC_TPU_TRG9 = 89U,
TRGSEL4_SRC_TPU_TRG10 = 90U,
TRGSEL4_SRC_TPU_TRG11 = 91U,
TRGSEL4_SRC_TPU_TRG12 = 92U,
TRGSEL4_SRC_TPU_TRG13 = 93U,
TRGSEL4_SRC_TPU_TRG14 = 94U,
TRGSEL4_SRC_TPU_TRG15 = 95U,
TRGSEL4_SRC_TPU_TRG16 = 96U,
TRGSEL4_SRC_TPU_TRG17 = 97U,
TRGSEL4_SRC_TPU_TRG18 = 98U,
TRGSEL4_SRC_TPU_TRG19 = 99U,
TRGSEL4_SRC_TPU_TRG20 = 100U,
TRGSEL4_SRC_TPU_TRG21 = 101U,
TRGSEL4_SRC_TPU_TRG22 = 102U,
TRGSEL4_SRC_TPU_TRG23 = 103U,
TRGSEL4_SRC_TPU_TRG24 = 104U,
TRGSEL4_SRC_TPU_TRG25 = 105U,
TRGSEL4_SRC_TPU_TRG26 = 106U,
TRGSEL4_SRC_TPU_TRG27 = 107U,
TRGSEL4_SRC_TPU_TRG28 = 108U,
TRGSEL4_SRC_TPU_TRG29 = 109U,
TRGSEL4_SRC_TPU_TRG30 = 110U,
TRGSEL4_SRC_TPU_TRG31 = 111U
} TrgSel4_SourceType;
/**
* @brief TrgSel instance 5 trigger sources
*
*/
typedef enum
{
TRGSEL5_SRC_VSS = 0U,
TRGSEL5_SRC_VDD = 1U,
TRGSEL5_SRC_SCM0_SW_TRG4 = 2U,
TRGSEL5_SRC_SCM0_SW_TRG5 = 3U,
TRGSEL5_SRC_SCM0_SW_TRG6 = 4U,
TRGSEL5_SRC_SCM0_SW_TRG7 = 5U,
TRGSEL5_SRC_TRGSEL_IN8 = 6U,
TRGSEL5_SRC_TRGSEL_IN9 = 7U,
TRGSEL5_SRC_TRGSEL_IN10 = 8U,
TRGSEL5_SRC_TRGSEL_IN11 = 9U,
TRGSEL5_SRC_TRGSEL_IN12 = 10U,
TRGSEL5_SRC_TRGSEL_IN13 = 11U,
TRGSEL5_SRC_ADC0_CMP = 12U,
TRGSEL5_SRC_ADC1_CMP = 13U,
TRGSEL5_SRC_CMP0_OUT = 14U,
TRGSEL5_SRC_CMP1_OUT = 15U,
TRGSEL5_SRC_FTU0_RELOAD_TRG = 16U,
TRGSEL5_SRC_FTU0_MATCH_TRG = 17U,
TRGSEL5_SRC_FTU1_RELOAD_TRG = 18U,
TRGSEL5_SRC_FTU1_MATCH_TRG = 19U,
TRGSEL5_SRC_FTU2_RELOAD_TRG = 20U,
TRGSEL5_SRC_FTU2_MATCH_TRG = 21U,
TRGSEL5_SRC_FTU3_RELOAD_TRG = 22U,
TRGSEL5_SRC_FTU3_MATCH_TRG = 23U,
TRGSEL5_SRC_FTU4_RELOAD_TRG = 24U,
TRGSEL5_SRC_FTU4_MATCH_TRG = 25U,
TRGSEL5_SRC_FTU5_RELOAD_TRG = 26U,
TRGSEL5_SRC_FTU5_MATCH_TRG = 27U,
TRGSEL5_SRC_FTU6_RELOAD_TRG = 28U,
TRGSEL5_SRC_FTU6_MATCH_TRG = 29U,
TRGSEL5_SRC_FTU7_RELOAD_TRG = 30U,
TRGSEL5_SRC_FTU7_MATCH_TRG = 31U,
TRGSEL5_SRC_LU0_OUT0A = 32U,
TRGSEL5_SRC_LU0_OUT1A = 33U,
TRGSEL5_SRC_LU0_OUT2A = 34U,
TRGSEL5_SRC_LU0_OUT3A = 35U,
TRGSEL5_SRC_LU0_OUT0B = 36U,
TRGSEL5_SRC_LU0_OUT1B = 37U,
TRGSEL5_SRC_LU0_OUT2B = 38U,
TRGSEL5_SRC_LU0_OUT3B = 39U,
TRGSEL5_SRC_ADC0_EOSG0 = 40U,
TRGSEL5_SRC_ADC0_EOSG1 = 41U,
TRGSEL5_SRC_ADC0_EOSG2 = 42U,
TRGSEL5_SRC_ADC0_EOSG3 = 43U,
TRGSEL5_SRC_ADC1_EOSG0 = 44U,
TRGSEL5_SRC_ADC1_EOSG1 = 45U,
TRGSEL5_SRC_ADC1_EOSG2 = 46U,
TRGSEL5_SRC_ADC1_EOSG3 = 47U,
TRGSEL5_SRC_FTU0_CH0_OUT = 48U,
TRGSEL5_SRC_FTU0_CH1_OUT = 49U,
TRGSEL5_SRC_FTU0_CH2_OUT = 50U,
TRGSEL5_SRC_FTU0_CH3_OUT = 51U,
TRGSEL5_SRC_FTU0_CH4_OUT = 52U,
TRGSEL5_SRC_FTU0_CH5_OUT = 53U,
TRGSEL5_SRC_FTU0_CH6_OUT = 54U,
TRGSEL5_SRC_FTU0_CH7_OUT = 55U,
TRGSEL5_SRC_TRGSEL1_INPUT0 = 56U,
TRGSEL5_SRC_TRGSEL1_INPUT1 = 57U,
TRGSEL5_SRC_TRGSEL1_INPUT2 = 58U,
TRGSEL5_SRC_TRGSEL1_INPUT3 = 59U,
TRGSEL5_SRC_TRGSEL1_INPUT4 = 60U,
TRGSEL5_SRC_TRGSEL1_INPUT5 = 61U,
TRGSEL5_SRC_TRGSEL1_INPUT6 = 62U,
TRGSEL5_SRC_TRGSEL1_INPUT7 = 63U,
} TrgSel5_SourceType;
/**
* @brief Software trigger channels for SMISC software trigger channel 0~7
*
*/
typedef enum
{
TRGSEL_SW_TRIGGER_CHANNEL_0 = 0U,
TRGSEL_SW_TRIGGER_CHANNEL_1 = 1U,
TRGSEL_SW_TRIGGER_CHANNEL_2 = 2U,
TRGSEL_SW_TRIGGER_CHANNEL_3 = 3U,
TRGSEL_SW_TRIGGER_CHANNEL_4 = 4U,
TRGSEL_SW_TRIGGER_CHANNEL_5 = 5U,
TRGSEL_SW_TRIGGER_CHANNEL_6 = 6U,
TRGSEL_SW_TRIGGER_CHANNEL_7 = 7U
} TRGSEL_SwTriggerChannelType;
/**
* @brief Get the trigger source of the selected trigger eTarget
*
* @param eInstance the TrgSel instance to which the trigger target belongs
* @param eTarget the trigger target to get the trigger source
* @return TRGSEL_SourceType the trigger source of the selected trigger target
*/
TRGSEL_SourceType TRGSEL_GetTargetTriggerSource(const TRGSEL_InstanceType eInstance, const TRGSEL_TargetType eTarget);
/**
* @brief Set the trigger source of the selected trigger target
*
* @param eInstance the TrgSel instance to which the trigger target belongs
* @param eTarget the trigger target to set the trigger source
* @param eSource the selected trigger source to trig the target
*/
void TRGSEL_SetTargetTriggerSource(const TRGSEL_InstanceType eInstance, const TRGSEL_TargetType eTarget,
const TRGSEL_SourceType eSource);
/**
* @brief Get wether the trigger source of the selected target is locked
*
* @param eInstance the TrgSel instance to which the trigger target belongs
* @param eTarget the trigger target to get the lock status
* @return true the trigger source of the selected target cannot be modified
* @return false the trigger source of the selected target can be modified
*/
bool TRGSEL_GetTargetLockStatus(const TRGSEL_InstanceType eInstance, const TRGSEL_TargetType eTarget);
/**
* @brief Lock the trigger source of the selected target
*
* @note The trigger target is grouped by four, so if you lock the trigger source of one target, the
* adjacent three trigger targets in the same register group are also be locked. So please ensure the
* trigger sources are not to be modified before lock the trigger target.
*
* @param eInstance the TrgSel instance to which the trigger target belongs
* @param eTarget the trigger target to lock the trigger source
*/
void TRGSEL_LockTargetTriggerSource(const TRGSEL_InstanceType eInstance, const TRGSEL_TargetType eTarget);
/**
* @brief Generate trigger signal for the selected software trigger source channel
*
* @param eChannel the selected software trigger source channel
*/
void TRGSEL_GenerateSwTrigger(const TRGSEL_SwTriggerChannelType eChannel);
/** @}*/ /* fc7xxx_driver_trgsel */
#if defined(__cplusplus)
}
#endif
#endif

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/**
* @file fc7xxx_driver_tstmp.h
* @author Flagchip
* @brief FC7xxx TSTMP driver type definition and API
* @version 0.1.0
* @date 2023-12-22
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-18 Flagchip0122 N/A FC7xxx internal release version
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_TSTMP_H_
#define _DRIVER_FC7XXX_DRIVER_TSTMP_H_
#include "HwA_tstmp.h"
/**
* @addtogroup fc7xxx_driver_tstmp
* @{
*/
/** @brief TSTMP max mod number*/
#define MAX_MOD_NUMBER 4U
/** @brief TSTMP return type. */
typedef enum
{
TSTMP_STATUS_SUCCESS = 0U,
TSTMP_STATUS_PARAM_INVALID = 1U
} TSTMP_StatusType;
/** @brief TSTMP instance */
typedef enum
{
TSTMP_INSTANCE_0 = 0U,
TSTMP_INSTANCE_1 = 1U,
TSTMP_INSTANCE_MAX
} TSTMP_InstanceType;
/** @brief TSTMP interrupt notification function type */
typedef void (*TSTMP_InterruptCallBackType)(void);
/** @brief TSTMP interrupt type */
typedef struct
{
bool bModulateIntEn[MAX_MOD_NUMBER]; /**< whether use the modulate n interrupt */
TSTMP_InterruptCallBackType pIsrModNotify[MAX_MOD_NUMBER]; /**< modulate n interrupt function pointer */
} TSTMP_IntType;
/** @brief TSTMP initialization type */
typedef struct
{
uint32_t u32Modulate0Value; /**< modulate 0 value */
uint32_t u32Modulate1Value; /**< modulate 1 value */
uint32_t u32Modulate2Value; /**< modulate 2 value */
uint32_t u32Modulate3Value; /**< modulate 3 value */
TSTMP_ClockSourceType pClk[MAX_MOD_NUMBER];
} TSTMP_InitType;
/** @brief TSTMP update type */
typedef struct
{
TSTMP_ModulateType eMod; /**< TSTMP modulate */
uint32_t u32ModValue; /**< TSTMP modulate value */
bool bIntEn; /**< whether enable TSTMP modulate interrupt */
TSTMP_InterruptCallBackType pIsrModNotify; /**< TSTMP interrupt notification */
} TSTMP_UpdateType;
/* global functions */
/**
* @brief Initialize TSTMP instance
*
* @param eInstance TSTMP instance
* @param pInitStruct TSTMP initialization structure
* @return TSTMP_StatusType TSTMP return type
* @note TSTMP0 clock source is 1MHZ and TSTMP1,TSTMP2,TSTMP3 clock source is bus clock
*/
TSTMP_StatusType TSTMP_Init(const TSTMP_InstanceType eInstance, const TSTMP_InitType *const pInitStruct);
/**
* @brief Set the Counting mode of modulate timer counter0,1,2,3
*
* @param eInstance TSTMP instance
* @param eCounter0Mode Counting mode of counter0
* @param eCounter1Mode Counting mode of counter1
* @param eCounter2Mode Counting mode of counter2
* @param eCounter3Mode Counting mode of counter3
* @return TSTMP_StatusType TSTMP return type
*/
TSTMP_StatusType TSTMP_SetCounterRunningMode(const TSTMP_InstanceType eInstance, const TSTMP_ModeCounterRunningMode eCounter0Mode,
const TSTMP_ModeCounterRunningMode eCounter1Mode,const TSTMP_ModeCounterRunningMode eCounter2Mode,
const TSTMP_ModeCounterRunningMode eCounter3Mode);
/**
* @brief De-initialize TSTMP instance
*
* @param eInstance TSTMP instance
* @return TSTMP_StatusType TSTMP return type
*/
TSTMP_StatusType TSTMP_Deinit(const TSTMP_InstanceType eInstance);
/**
* @brief Initialize TSTMP interrupt functionality
*
* @param eInstance TSTMP instance
* @param pIntStruct TSTMP interrupt structure
* @return TSTMP_StatusType TSTMP return type
*/
TSTMP_StatusType TSTMP_InitInterrupt(const TSTMP_InstanceType eInstance, const TSTMP_IntType *const pIntStruct);
/**
* @brief Enable TSTMP interrupt function
*
* @param eInstance TSTMP instance
* @param eMod TSTMP modulate enumeration
* @return TSTMP_StatusType TSTMP return type
*/
TSTMP_StatusType TSTMP_EnableInterrupt(const TSTMP_InstanceType eInstance, const TSTMP_ModulateType eMod);
/**
* @brief Disable TSTMP interrupt function
*
* @param eInstance TSTMP instance
* @param eMod TSTMP modulate enumeration
* @return TSTMP_StatusType TSTMP return type
*/
TSTMP_StatusType TSTMP_DisableInterrupt(const TSTMP_InstanceType eInstance, const TSTMP_ModulateType eMod);
/**
* @brief Get TSTMP count value
*
* @param eInstance TSTMP instance
* @param u64TstmpValue in/out value
* @return TSTMP_StatusType TSTMP return type
*/
TSTMP_StatusType TSTMP_GetTstmpValue(const TSTMP_InstanceType eInstance, uint64_t *const u64TstmpValue);
/**
* @brief Update Modulate configuration
*
* @param eInstance TSTMP instance
* @param pUpdateStruct TSTMP update structure pointer
* @return TSTMP_StatusType TSTMP return type
*/
TSTMP_StatusType TSTMP_UpdateMod(const TSTMP_InstanceType eInstance,
const TSTMP_UpdateType *const pUpdateStruct);
/**
* @brief Set counter MOD(n) counting on or off
*
* @param eInstance TSTMP instance
* @param eMod MOD number
* @param bCounterEn Whether enable the selected Modulate Timer Counter
* @return TSTMP_StatusType TSTMP return type
*/
TSTMP_StatusType TSTMP_SetModCountConfig(const TSTMP_InstanceType eInstance, const TSTMP_ModulateType eMod,const bool bCounterEn);
/** @}*/ /* fc7xxx_driver_tstmp */
#endif

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/**
* @file fc7xxx_driver_wdog.h
* @author Flagchip
* @brief FC7xxx WDOG driver type definition and API
* @version 0.1.0
* @date 2023-12-29
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-29 qxw0074 N/A First version for FC7240
********************************************************************************/
#ifndef _DRIVER_FC7XXX_DRIVER_WDOG_H_
#define _DRIVER_FC7XXX_DRIVER_WDOG_H_
#include "HwA_wdog.h"
/**
* @addtogroup fc7xxx_driver_wdog
* @{
*/
/** @brief WDOG ISR callback function declaration. */
typedef void (*WDOG_IRQ_Callback)(void);
/** @brief WDOG clock instance declaration. */
typedef enum
{
WDOG_INSTANCE_0 = 0U, /*!< WDOG instance 0 is selected */
WDOG_INSTANCE_1 = 1U, /*!< WDOG instance 1 is selected */
WDOG_INSTANCE_MAX /*!< WDOG instance MAX number */
} WDOG_InstanceType;
/** @brief WDOG clock source select, mapping with WDOG_CS[CLK_SEL] bit filed definition. */
typedef enum
{
WDOG_BUS_CLK = 0x00U, /* Bus clock */
WDOG_AON_CLK = 0x01U, /* AON clock, if choose this clock need to configure AON clock in SMISC setting */
WDOG_SOSC_CLK = 0x02U, /* SOSC clock */
WDOG_SIRC_CLK = 0x03U /* SIRC clock */
} WDOG_ClkSelType;
/** @brief WDOG test mode, mapping with WDOG_CS[TST] bit filed definition. */
typedef enum
{
WDOG_TST_DISABLED = 0x00U, /* Test mode disabled */
WDOG_USER_MODE = 0x01U, /* User mode enabled. (Test mode disabled.) */
WDOG_TST_MODE_LOW = 0x02U, /* Test mode enabled, only the low byte is used. */
WDOG_TST_MODE_HIGH = 0x03U /* Test mode enabled, only the high byte is used. */
} WDOG_TestType;
/** @brief WDOG delay time to generate the reset. */
typedef enum
{
WDOG_REACTION_INT_128_CYCLE = 0x00U, /* Enable the timeout interrupt, and the delay to generate the reset is configured to 128 bus clock cycles */
WDOG_REACTION_INT_256_CYCLE = 0x01U, /* Enable the timeout interrupt, and the delay to generate the reset is configured to 256 bus clock cycles */
WDOG_REACTION_INT_512_CYCLE = 0x02U, /* Enable the timeout interrupt, and the delay to generate the reset is configured to 512 bus clock cycles */
WDOG_REACTION_INT_1024_CYCLE = 0x03U, /* Enable the timeout interrupt, and the delay to generate the reset is configured to 1024 bus clock cycles */
WDOG_REACTION_NO_INT = 0x04U /* Disable the timeout interrupt, and generate the reset immediately */
} WDOG_TimeoutReactionType;
/** @brief WDOG init module type, include register setting for WDOG_CS/WDOG_TIMEOUT/WDOG_WINDOW. */
typedef struct
{
bool bWinEnable; /**@ windowed watch dog mode */
bool bPrescalerEnable; /**@ fixed 256 prescaler from clock input */
WDOG_ClkSelType eClkSource; /**@ WDOG clock source */
WDOG_TimeoutReactionType eTimeoutReaction; /**@ WDOG timeout reaction. */
bool bEnable; /**@ WDOG enable bit */
WDOG_TestType eTesttype; /**@ WDOG_CS[TST] */
bool bEnableInDebug; /**@ WDOG_CS[DBG] */
bool bEnableInWait; /**@ WDOG_CS[WAIT] */
bool bEnableInStop; /**@ WDOG_CS[STOP] */
uint16_t u16WindowValue; /**@ The window value */
uint16_t u16TimeoutValue; /**@ The timeout value */
WDOG_IRQ_Callback pISRCallback; /**@ The WDOG ISR callback function. */
} WDOG_CfgType;
/**
* @brief unlock the wdog before Watch dog reconfigure set.
* @param eInstance: WDOG module instance: WDOG0/WDOG1 defined in FC4150.
*/
void WDOG_Unlock(WDOG_InstanceType eInstance);
/**
* @brief feed the watch dog by writing typical CMD to counter.
* @param eInstance: WDOG module instance: WDOG0/WDOG1 defined in FC4150.
*/
void WDOG_Refresh(WDOG_InstanceType eInstance);
/**
* @brief Initialize the WDOG configuration setting.
* @param eInstance: WDOG module instance: WDOG0/WDOG1 defined in FC4150.
* @param pWdogCfg: point to WDOG initial module type.
*/
void WDOG_Init(WDOG_InstanceType eInstance, WDOG_CfgType* pWdogCfg);
/**
* @brief WDOG_ReInit reserved. *
* @param eInstance Wdog instance for re-init.
*/
void WDOG_ReInit(WDOG_InstanceType eInstance);
/** @}*/ /* fc7xxx_driver_wdog */
#endif

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/**
* @file fc7xxx_driver_wku.h
* @author Flagchip
* @brief FC7xxx WKU driver type definition and API
* @version 0.1.0
* @date 2024-01-05
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
#ifndef _DRIVER_FC7XXX_DRIVER_WKU_H_
#define _DRIVER_FC7XXX_DRIVER_WKU_H_
#include "HwA_wku.h"
/**
* @addtogroup fc7xxx_driver_wku
* @{
*/
/** @brief WKU return type. */
typedef enum
{
WKU_STATUS_SUCCESS = 0U,
WKU_STATUS_PARAM_INVALID = 1U
} WKU_StatusType;
/* global apis */
/**
* @brief WKU Enable wakeup source for single input
*
* @param u32Input Number of input, WKU_WakeupInputType type is wakeup source definition
* @return WKU return type
*/
WKU_StatusType WKU_EnableWakeupSource(const uint32_t u32Input);
/**
* @brief WKU Disable wakeup source for single input
*
* @param u32Input Number of input, WKU_WakeupInputType type is wakeup source definition
* @return WKU return type
*/
WKU_StatusType WKU_DisableWakeupSource(const uint32_t u32Input);
/**
* @brief WKU get wakeup source
*
* @return output wakeup source
*/
uint32_t WKU_GetWakeupSources(void);
/**
* @brief WKU Disable wakeup source for single input
*
* @param u8Delaytime The delay time is 2^(u8Delaytime+3) AON_CLK cycles
*/
void WKU_SetWakeupDelay(uint8_t u8Delaytime);
/** @}*/ /* fc7xxx_driver_wku */
#endif

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Src/fc7xxx_driver_adc.c Normal file
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@ -0,0 +1,791 @@
/**
* @file fc7xxx_driver_adc.c
* @author Flagchip0126
* @brief FC7xxx ADC driver source code
* @version 0.1.0
* @date 2024-01-15
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Author CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_adc.h"
#include "fc7xxx_driver_scg.h"
#include "fc7xxx_driver_pcc.h"
#include "fc7xxx_driver_dma.h"
/**
* @name ADC default values
* @brief ADC default configuration parameters
*
* @{
*/
#define ADC_DEFAULT_SAMPLE_TIME_OPTION_0 (0x04U)
#define ADC_DEFAULT_SAMPLE_TIME_OPTION_1 (0x0AU)
#define ADC_DEFAULT_SAMPLE_TIME_OPTION_2 (0x22U)
#define ADC_DEFAULT_SAMPLE_TIME_OPTION_3 (0x82U)
#define ADC_DEFAULT_STARTUP_COUNTER (0xC0U)
#define ADC_DEFAULT_WATER_MARK (0x10U)
#define ADC_DEFAULT_COMPARE_HIGH_THRESHOLD (0x000U)
#define ADC_DEFAULT_COMPARE_LOW_THRESHOLD (0x200U)
#define ADC_DEFAULT_SC_CHANNEL (0x3FU)
/** @}*/
/********* Local Variables ************/
static ADC_Type *const s_apAdcBase[ADC_INSTANCE_COUNT] = ADC_BASE_PTRS;
static ADC_ConvCompleteCallbackType s_apAdcCoCoNotify[ADC_INSTANCE_COUNT] = {NULL};
static ADC_OverRunInterruptCallbackType s_apAdcOvrNotify[ADC_INSTANCE_COUNT] = {NULL};
static ADC_CompareInterruptCallbackType s_apAdcCmpNotify[ADC_INSTANCE_COUNT] = {NULL};
static ADC_EndOfSeqGroupInterruptCallbackType s_apEndOfSeqGroupNotify[ADC_INSTANCE_COUNT] = {NULL};
static uint32_t *s_apAdcResultBuffer[ADC_INSTANCE_COUNT] = {NULL};
static uint32_t *s_apAdcSeqGroupResultBuffer[ADC_INSTANCE_COUNT][ADC_SEQUENCE_GROUP_CNT] = {NULL};
static uint8_t s_u8ChannelCnt[ADC_INSTANCE_COUNT] = {0U};
static uint8_t s_u8SeqGroupCnt[ADC_INSTANCE_COUNT] = {0U};
/******* Local Function Prototype *********/
/**
* @brief The internal interrupt handler function for ADC instances
*
* @param eInstance the ADC instance selected
*/
static void ADCn_IRQHandler(const ADC_InstanceType eInstance);
/**
* @brief The internal DMA handler function for ADC instances
*
* @param eInstance the ADC instance selected
*/
static void ADCn_DMAHandler(const ADC_InstanceType eInstance);
/**
* @brief The internal DMA handler function for ADC instance 0
*
*/
static void ADC0_DMAHandler(void);
/**
* @brief The internal DMA handler function for ADC instance 1
*
*/
static void ADC1_DMAHandler(void);
/**
* @brief The interrupt handler function for ADC instance 0
*
*/
void ADC0_IRQHandler(void);
/**
* @brief The interrupt handler function for ADC instance 1
*
*/
void ADC1_IRQHandler(void);
/********* Local Functions ************/
/***************ADC IRQ Functions*****************/
static void ADCn_IRQHandler(const ADC_InstanceType eInstance)
{
ADC_Type *const pAdc = s_apAdcBase[eInstance];
bool bConvCompleted;
bool bSeqGroupCompleted;
uint32_t u32CurSeqGroupIdx;
uint32_t u32SeqGroupStart;
uint32_t u32SeqGroupEnd;
uint8_t u8Idx;
uint8_t u8BufferIdx;
if (ADC_HWA_GetSeqGpEn(pAdc) == true)
{
bSeqGroupCompleted = false;
for (u8Idx = 0U; u8Idx < ADC_SEQUENCE_GROUP_CNT; u8Idx++)
{
if (ADC_HWA_GetEndOfSequenceGroupInterruptFlag(pAdc, u8Idx) == true)
{
bSeqGroupCompleted = true;
u32CurSeqGroupIdx = u8Idx;
break;
}
}
if (bSeqGroupCompleted)
{
DEV_ASSERT(s_apAdcSeqGroupResultBuffer[eInstance] != NULL);
u8BufferIdx = 0U;
u32SeqGroupStart = ADC_HWA_GetSeqGroupStartPoint(pAdc, u32CurSeqGroupIdx);
u32SeqGroupEnd = ADC_HWA_GetSeqGroupEndPoint(pAdc, u32CurSeqGroupIdx);
for (u8Idx = u32SeqGroupStart; u8Idx < u32SeqGroupEnd + 1U; u8Idx++)
{
s_apAdcSeqGroupResultBuffer[eInstance][u32CurSeqGroupIdx][u8BufferIdx++] = ADC_HWA_GetChannelData(pAdc, u8Idx);
}
if (s_apEndOfSeqGroupNotify[eInstance] != NULL)
{
s_apEndOfSeqGroupNotify[eInstance](u32CurSeqGroupIdx);
}
}
}
else if (ADC_HWA_GetSequenceMode(pAdc) == ADC_SEQMODE_DISCONTINUOUS_1)
{
bConvCompleted = true;
for (u8Idx = 0U; u8Idx < s_u8ChannelCnt[eInstance]; u8Idx++)
{
if (ADC_HWA_GetChannelConvertComplete(pAdc, u8Idx) == false)
{
bConvCompleted = false;
break;
}
if (u8Idx == s_u8ChannelCnt[eInstance] - 1 && ADC_HWA_GetChannelInterruptEnable(pAdc, u8Idx) == false)
{
bConvCompleted = false;
break;
}
}
if (bConvCompleted)
{
DEV_ASSERT(s_apAdcResultBuffer[eInstance] != NULL);
for (u8Idx = 0U; u8Idx < s_u8ChannelCnt[eInstance]; u8Idx++)
{
s_apAdcResultBuffer[eInstance][u8Idx] = ADC_HWA_GetChannelData(pAdc, u8Idx);
}
if (s_apAdcCoCoNotify[eInstance] != NULL)
{
s_apAdcCoCoNotify[eInstance](s_apAdcResultBuffer[eInstance]);
}
}
}
else
{
bool bAdcSequenceComplete = ADC_HWA_GetEndOfSequence(pAdc);
bool bAdcFifoFull = ADC_HWA_GetFull(pAdc);
if ((bAdcSequenceComplete == true) ||
(bAdcFifoFull == true))
{
DEV_ASSERT(s_apAdcResultBuffer[eInstance] != NULL);
u8Idx = 0U;
while ((ADC_HWA_GetEmpty(pAdc) == false) && (u8Idx != s_u8ChannelCnt[eInstance]))
{
s_apAdcResultBuffer[eInstance][u8Idx] = ADC_HWA_GetFIFOData(pAdc);
u8Idx++;
}
if (ADC_HWA_GetEndOfSequence(pAdc))
{
ADC_HWA_ClearEndOfSequence(pAdc);
}
if (ADC_HWA_GetEndOfConversion(pAdc))
{
ADC_HWA_ClearEndOfConversion(pAdc);
}
if (ADC_HWA_GetEndOfSample(pAdc))
{
ADC_HWA_ClearEndOfSample(pAdc);
}
if (ADC_HWA_GetReady(pAdc))
{
ADC_HWA_ClearReady(pAdc);
}
if (s_apAdcCoCoNotify[eInstance] != NULL)
{
s_apAdcCoCoNotify[eInstance](s_apAdcResultBuffer[eInstance]);
}
}
}
if (ADC_HWA_GetOverRun(pAdc))
{
ADC_HWA_ClearOverRun(pAdc);
if (s_apAdcOvrNotify[eInstance] != NULL)
{
s_apAdcOvrNotify[eInstance]();
}
}
if (ADC_HWA_GetCompareFlag(pAdc))
{
ADC_HWA_ClearCompareFlag(pAdc);
if (s_apAdcCmpNotify[eInstance] != NULL)
{
s_apAdcCmpNotify[eInstance]();
}
}
}
void ADC0_IRQHandler(void)
{
ADCn_IRQHandler(ADC_INSTANCE_0);
}
void ADC1_IRQHandler(void)
{
ADCn_IRQHandler(ADC_INSTANCE_1);
}
static void ADCn_DMAHandler(const ADC_InstanceType eInstance)
{
ADC_Type *const pAdc = s_apAdcBase[eInstance];
uint8_t u8Idx;
uint32_t u32CurSeqGroupIdx;
for (u8Idx = 0U; u8Idx < ADC_SEQUENCE_GROUP_CNT; u8Idx++)
{
if (ADC_HWA_GetEndOfSequenceGroupInterruptFlag(pAdc, u8Idx) == true)
{
u32CurSeqGroupIdx = u8Idx;
break;
}
}
if (ADC_HWA_GetEndOfSequence(pAdc))
{
ADC_HWA_ClearEndOfSequence(pAdc);
}
if (ADC_HWA_GetEndOfConversion(pAdc))
{
ADC_HWA_ClearEndOfConversion(pAdc);
}
if (ADC_HWA_GetEndOfSample(pAdc))
{
ADC_HWA_ClearEndOfSample(pAdc);
}
if (ADC_HWA_GetFIFOReady(pAdc))
{
ADC_HWA_ClearFIFOReady(pAdc);
}
if (s_apAdcCoCoNotify[eInstance] != NULL)
{
s_apAdcCoCoNotify[eInstance](s_apAdcResultBuffer[eInstance]);
}
if (s_apEndOfSeqGroupNotify[eInstance] != NULL)
{
s_apEndOfSeqGroupNotify[eInstance](u32CurSeqGroupIdx);
}
}
static void ADC0_DMAHandler(void)
{
ADCn_DMAHandler(ADC_INSTANCE_0);
}
static void ADC1_DMAHandler(void)
{
ADCn_DMAHandler(ADC_INSTANCE_1);
}
/***************** Global Functions *********************/
void ADC_InitStructure(ADC_InitType *const pInitCfg)
{
DEV_ASSERT(pInitCfg != NULL);
pInitCfg->eResolution = ADC_RESOLUTION_12_BIT; /* 12 bit Resolution */
pInitCfg->eAlign = ADC_ALIGN_RIGHT; /* Align right */
pInitCfg->eTriggerMode = ADC_TRIGMODE_SW; /* Software trigger */
pInitCfg->bWaitEnable = false; /* Disable wait conversion mode */
pInitCfg->bSequenceGroupModeEnable = false; /* Disable sequence group mode */
pInitCfg->eTrgLatchUnitPri = TRG_LATCH_UNIT_PRI_ROUND_ROBIN; /* Round Robin priority */
pInitCfg->eClockDivider = ADC_CLOCK_DIV_1; /* Adc clock divided by 1 */
pInitCfg->eSequenceMode = ADC_SEQMODE_SINGLE; /* Single sequence mode */
pInitCfg->bAutoDis = false; /* Disable auto disable mode */
pInitCfg->eOverrunMode = ADC_OVERRUN_MODE_PRESERVE; /* Old conversion data preserved when overrun occured */
pInitCfg->eVoltageRef = ADC_REF_INTERNAL; /* Use internal reference */
pInitCfg->bHwAvgEnable = false; /* Disable averaging functionality */
pInitCfg->eHwAverage = ADC_AVERAGE_4; /* Average by 4 samples if average is enabled */
pInitCfg->aSampleTimes[0] = ADC_DEFAULT_SAMPLE_TIME_OPTION_0; /* Sample time option 0 is 4 ADC Clock */
pInitCfg->aSampleTimes[1] = ADC_DEFAULT_SAMPLE_TIME_OPTION_1; /* Sample time option 1 is 10 ADC Clock */
pInitCfg->aSampleTimes[2] = ADC_DEFAULT_SAMPLE_TIME_OPTION_2; /* Sample time option 2 is 34 ADC Clock */
pInitCfg->aSampleTimes[3] = ADC_DEFAULT_SAMPLE_TIME_OPTION_3; /* Sample time option 3 is 130 ADC Clock */
}
void ADC_Init(const ADC_InstanceType eInstance, const ADC_InitType *const pInitCfg)
{
DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT);
DEV_ASSERT(pInitCfg != NULL);
ADC_Type *const pAdc = s_apAdcBase[eInstance];
uint32_t u32TimeOut = 15000000U;
uint32_t u32Cfg1;
uint32_t u32Cfg2;
uint32_t u32Cal;
ADC_TrigSrcType eTriggerSrc;
ADC_TrigModeType eTriggerMode;
uint32_t u32ClockDiv;
uint32_t u32StartupCnt;
if (pInitCfg->bSequenceGroupModeEnable == false)
{
if (pInitCfg->eSequenceMode == ADC_SEQMODE_DISCONTINUOUS_1)
{
eTriggerSrc = ADC_TRIGSRC_PTIMER;
eTriggerMode = ADC_TRIGMODE_RISING_EDGE;
}
else
{
eTriggerSrc = ADC_TRIGSRC_TRGSEL;
eTriggerMode = pInitCfg->eTriggerMode;
}
}
else
{
eTriggerSrc = ADC_TRIGSRC_TRIG_LATCH_UNIT;
eTriggerMode = ADC_TRIGMODE_RISING_EDGE;
}
PCC_ClkSrcType eAdcClkName = PCC_CLK_ADC0;
uint32_t u32AdcClk;
switch (eInstance)
{
case ADC_INSTANCE_0:
{
eAdcClkName = PCC_CLK_ADC0;
break;
}
case ADC_INSTANCE_1:
{
eAdcClkName = PCC_CLK_ADC1;
break;
}
default:
break;
}
u32ClockDiv = 1U << pInitCfg->eClockDivider;
u32AdcClk = PCC_GetPccFunctionClock(eAdcClkName);
/* The start up count shall be around 5us */
u32StartupCnt = u32AdcClk / u32ClockDiv / 1000000U * 5U + 1U;
if (u32StartupCnt < 2U)
{
u32StartupCnt = 2U;
}
else if (u32StartupCnt > 255U)
{
u32StartupCnt = 255U;
}
else
{}
ADC_HWA_Reset(pAdc);
u32Cfg1 = ADC_CFG1_OVRMOD(pInitCfg->eOverrunMode) |
ADC_CFG1_SEQGP_EN(pInitCfg->bSequenceGroupModeEnable) |
ADC_CFG1_SEQ_LEN(0) |
ADC_CFG1_SEQ_MOD(pInitCfg->eSequenceMode) |
ADC_CFG1_AUTO_DIS(pInitCfg->bAutoDis) |
ADC_CFG1_WAIT(pInitCfg->bWaitEnable) |
ADC_CFG1_TRIGSRC(eTriggerSrc) |
ADC_CFG1_TRIGMODE(eTriggerMode) |
ADC_CFG1_ALIGN(pInitCfg->eAlign) |
ADC_CFG1_RES(pInitCfg->eResolution) |
ADC_CFG1_DMAEN(false);
ADC_HWA_SetConfig1(pAdc, u32Cfg1);
u32Cfg2 = ADC_CFG2_FWMARK(ADC_DEFAULT_WATER_MARK) |
ADC_CFG2_TRG_PRI(pInitCfg->eTrgLatchUnitPri) |
ADC_CFG2_TRG_CLR(1U) |
ADC_CFG2_AVG_EN(pInitCfg->bHwAvgEnable) |
ADC_CFG2_AVG_LEN(pInitCfg->eHwAverage) |
ADC_CFG2_REF_EXT(pInitCfg->eVoltageRef) |
ADC_CFG2_STCNT(u32StartupCnt);
ADC_HWA_SetConfig2(pAdc, u32Cfg2);
u32Cal = ADC_CAL_CAL_EN(pInitCfg->bCalEnable) |
ADC_CAL_OFFSET(pInitCfg->s32CalOffset) |
ADC_CAL_GAIN(pInitCfg->s32CalGain);
ADC_HWA_SetCal(pAdc, u32Cal);
ADC_HWA_SetClockGatingEnableFlag(pAdc, true);
while ((ADC_HWA_GetClockGatingAck(pAdc) != true) && (u32TimeOut != 0))
{
u32TimeOut--;
}
if (ADC_HWA_GetClockGatingAck(pAdc) == true)
{
ADC_HWA_SetClockDivider(pAdc, pInitCfg->eClockDivider);
}
u32TimeOut = 15000000U;
ADC_HWA_SetClockGatingEnableFlag(pAdc, false);
while ((ADC_HWA_GetClockGatingAck(pAdc) != false) && (u32TimeOut != 0))
{
u32TimeOut--;
}
uint8_t u8SmprIndex;
for (u8SmprIndex = 0U; u8SmprIndex < ADC_SAMPLE_TIME_OPTION_CNT; u8SmprIndex++)
{
ADC_HWA_SetSampleTime(pAdc, u8SmprIndex, pInitCfg->aSampleTimes[u8SmprIndex] - 2U);
}
}
void ADC_DeInit(const ADC_InstanceType eInstance)
{
DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT);
ADC_Type *const pAdc = s_apAdcBase[eInstance];
uint32_t u32Cfg1;
uint32_t u32Cfg2;
ADC_HWA_Reset(pAdc);
ADC_HWA_SetInterruptEnable(pAdc, 0U);
u32Cfg1 = ADC_CFG1_OVRMOD(ADC_OVERRUN_MODE_PRESERVE) |
ADC_CFG1_SEQGP_EN(false) |
ADC_CFG1_SEQ_LEN(0U) |
ADC_CFG1_SEQ_MOD(ADC_SEQMODE_SINGLE) |
ADC_CFG1_AUTO_DIS(false) |
ADC_CFG1_WAIT(false) |
ADC_CFG1_TRIGSRC(ADC_TRIGSRC_PTIMER) |
ADC_CFG1_TRIGMODE(ADC_TRIGMODE_SW) |
ADC_CFG1_ALIGN(ADC_ALIGN_RIGHT) |
ADC_CFG1_RES(ADC_RESOLUTION_12_BIT) |
ADC_CFG1_DMAEN(false);
ADC_HWA_SetConfig1(pAdc, u32Cfg1);
u32Cfg2 = ADC_CFG2_FWMARK(ADC_DEFAULT_WATER_MARK) |
ADC_CFG2_TRG_PRI(TRG_LATCH_UNIT_PRI_ROUND_ROBIN) |
ADC_CFG2_TRG_CLR(1U) |
ADC_CFG2_AVG_EN(false) |
ADC_CFG2_AVG_LEN(ADC_AVERAGE_4) |
ADC_CFG2_REF_EXT(ADC_REF_INTERNAL) |
ADC_CFG2_STCNT(ADC_DEFAULT_STARTUP_COUNTER);
ADC_HWA_SetConfig2(pAdc, u32Cfg2);
ADC_HWA_SetSampleTime(pAdc, 0U, ADC_DEFAULT_SAMPLE_TIME_OPTION_0 - 2U);
ADC_HWA_SetSampleTime(pAdc, 1U, ADC_DEFAULT_SAMPLE_TIME_OPTION_1 - 2U);
ADC_HWA_SetSampleTime(pAdc, 2U, ADC_DEFAULT_SAMPLE_TIME_OPTION_2 - 2U);
ADC_HWA_SetSampleTime(pAdc, 3U, ADC_DEFAULT_SAMPLE_TIME_OPTION_3 - 2U);
ADC_HWA_SetHwCompareEnableFlag(pAdc, false);
ADC_HWA_SetHwCompareChannel(pAdc, ADC_CMP_CHANNEL_ALL, 0U);
ADC_HWA_SetHwCompareThreshold(pAdc, ADC_DEFAULT_COMPARE_LOW_THRESHOLD, ADC_DEFAULT_COMPARE_HIGH_THRESHOLD);
uint8_t u8ChnIndex;
for (u8ChnIndex = 0U; u8ChnIndex < ADC_SC_COUNT; u8ChnIndex++)
{
ADC_HWA_SetChannelSampleTimeIndex(pAdc, u8ChnIndex, 0U);
ADC_HWA_SetChannelInterruptEnable(pAdc, u8ChnIndex, false);
ADC_HWA_SetChannelInput(pAdc, u8ChnIndex, ADC_DEFAULT_SC_CHANNEL);
}
/* TODO : CAL Rregister */
}
void ADC_InitChannel(const ADC_InstanceType eInstance, const ADC_ChannelCfgType aChannels[],
const uint8_t u8ChnCnt)
{
DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT);
DEV_ASSERT(u8ChnCnt < ADC_SC_COUNT);
DEV_ASSERT(aChannels != NULL);
ADC_Type *const pAdc = s_apAdcBase[eInstance];
s_u8ChannelCnt[eInstance] = u8ChnCnt;
uint8_t u8ChnIndex;
for (u8ChnIndex = 0U; u8ChnIndex < u8ChnCnt; u8ChnIndex++)
{
ADC_HWA_SetChannelDiff(pAdc, u8ChnIndex, aChannels[u8ChnIndex].bDiff);
ADC_HWA_SetChannelSampleTimeIndex(pAdc, u8ChnIndex, aChannels[u8ChnIndex].eSampleTimeOption);
ADC_HWA_SetChannelInterruptEnable(pAdc, u8ChnIndex, false);
ADC_HWA_SetChannelInput(pAdc, u8ChnIndex, aChannels[u8ChnIndex].eChannel);
}
if (ADC_HWA_GetSeqGpEn(pAdc) != true && ADC_HWA_GetSequenceMode(pAdc) != ADC_SEQMODE_DISCONTINUOUS_1)
{
ADC_HWA_SetSequenceLength(pAdc, u8ChnCnt - 1U);
ADC_HWA_SetFIFOWaterMark(pAdc, u8ChnCnt - 1U);
}
}
void ADC_InitSequenceGroup(const ADC_InstanceType eInstance, const ADC_SequenceGroupType aSeqGroup[],
const uint8_t u8SeqGroupCnt)
{
DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT);
DEV_ASSERT(u8SeqGroupCnt < ADC_SEQUENCE_GROUP_CNT);
DEV_ASSERT(aSeqGroup != NULL);
ADC_Type *const pAdc = s_apAdcBase[eInstance];
s_u8SeqGroupCnt[eInstance] = u8SeqGroupCnt;
uint8_t u8ChnIndex;
for (u8ChnIndex = 0U; u8ChnIndex < u8SeqGroupCnt; u8ChnIndex++)
{
ADC_HWA_SetSeqGroupStartEndPoint(pAdc, u8ChnIndex, aSeqGroup[u8ChnIndex].u8Start, aSeqGroup[u8ChnIndex].u8Start + aSeqGroup[u8ChnIndex].u8Len);
ADC_HWA_SetEndOfSequenceGroupInterruptEnable(pAdc, u8ChnIndex, false);
}
}
void ADC_InitCompare(const ADC_InstanceType eInstance, const ADC_CompareType *const pCmpCfg)
{
DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT);
DEV_ASSERT(pCmpCfg != NULL);
ADC_Type *const pAdc = s_apAdcBase[eInstance];
ADC_HWA_SetHwCompareChannel(pAdc, pCmpCfg->eCmpSingleChn, pCmpCfg->u8CmpChnSel);
ADC_HWA_SetHwCompareThreshold(pAdc, pCmpCfg->u16LowThres, pCmpCfg->u16HighThres);
ADC_HWA_SetHwCompareEnableFlag(pAdc, pCmpCfg->bCmpEnable);
}
void ADC_InitInterrupt(const ADC_InstanceType eInstance, const ADC_InterruptType *const pInterruptCfg)
{
DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT);
DEV_ASSERT(pInterruptCfg != NULL);
DEV_ASSERT(s_u8ChannelCnt[eInstance] > 0U);
ADC_Type *const pAdc = s_apAdcBase[eInstance];
uint32_t u32InterruptCfg;
uint8_t u8SeqGroupIndex;
if (ADC_HWA_GetSeqGpEn(pAdc) == false)
{
s_apAdcResultBuffer[eInstance] = pInterruptCfg->pResultBuffer;
if (ADC_HWA_GetSequenceMode(pAdc) == ADC_SEQMODE_DISCONTINUOUS_1)
{
u32InterruptCfg = ADC_INT_ENABLE_TRGERR_IE(false) |
ADC_INT_ENABLE_FIFO_RDY_IE(false) |
ADC_INT_ENABLE_ACMP_IE(pInterruptCfg->bAnalogCmpIntEn) |
ADC_INT_ENABLE_OVRIE(false) |
ADC_INT_ENABLE_EOSEQIE(false) |
ADC_INT_ENABLE_EOCIE(false) |
ADC_INT_ENABLE_EOSMPIE(false) |
ADC_INT_ENABLE_ADRDYIE(false);
ADC_HWA_SetInterruptEnable(pAdc, u32InterruptCfg);
ADC_HWA_SetChannelInterruptEnable(pAdc, s_u8ChannelCnt[eInstance] - 1U, pInterruptCfg->bConversionCompleteIntEn);
}
else
{
u32InterruptCfg = ADC_INT_ENABLE_TRGERR_IE(false) |
ADC_INT_ENABLE_FIFO_RDY_IE(false) |
ADC_INT_ENABLE_ACMP_IE(pInterruptCfg->bAnalogCmpIntEn) |
ADC_INT_ENABLE_OVRIE(pInterruptCfg->bOverRunIntEn) |
ADC_INT_ENABLE_EOSEQIE(pInterruptCfg->bConversionCompleteIntEn) |
ADC_INT_ENABLE_EOCIE(false) |
ADC_INT_ENABLE_EOSMPIE(false) |
ADC_INT_ENABLE_ADRDYIE(false);
ADC_HWA_SetInterruptEnable(pAdc, u32InterruptCfg);
}
}
else
{
for (u8SeqGroupIndex = 0U; u8SeqGroupIndex < ADC_SEQUENCE_GROUP_CNT; u8SeqGroupIndex++)
{
s_apAdcSeqGroupResultBuffer[eInstance][u8SeqGroupIndex] = pInterruptCfg->pSequenceGroupResultBuffer[u8SeqGroupIndex];
}
u32InterruptCfg = ADC_INT_ENABLE_TRGERR_IE(false) |
ADC_INT_ENABLE_FIFO_RDY_IE(false) |
ADC_INT_ENABLE_ACMP_IE(pInterruptCfg->bAnalogCmpIntEn) |
ADC_INT_ENABLE_OVRIE(false) |
ADC_INT_ENABLE_EOSEQIE(false) |
ADC_INT_ENABLE_EOCIE(false) |
ADC_INT_ENABLE_EOSMPIE(false) |
ADC_INT_ENABLE_ADRDYIE(false);
ADC_HWA_SetInterruptEnable(pAdc, u32InterruptCfg);
for (u8SeqGroupIndex = 0U; u8SeqGroupIndex < s_u8SeqGroupCnt[eInstance]; u8SeqGroupIndex++)
{
ADC_HWA_SetEndOfSequenceGroupInterruptEnable(pAdc, u8SeqGroupIndex, true);
}
}
s_apAdcCoCoNotify[eInstance] = pInterruptCfg->pConvCompleteNotify;
s_apAdcOvrNotify[eInstance] = pInterruptCfg->pOverRunNotify;
s_apAdcCmpNotify[eInstance] = pInterruptCfg->pCompareNotify;
s_apEndOfSeqGroupNotify[eInstance] = pInterruptCfg->pEndOfSeqGroupNotify;
}
void ADC_InitDmaChannel(const ADC_InstanceType eInstance, const ADC_DmaType *const pAdcDmaCfg)
{
DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT);
DEV_ASSERT(pAdcDmaCfg != NULL);
uint32_t u32ResultStart;
uint32_t u32ResultEnd;
ADC_Type *const pAdc = s_apAdcBase[eInstance];
if (pAdcDmaCfg->bDmaEnable == true)
{
s_apAdcResultBuffer[eInstance] = pAdcDmaCfg->pResultBuffer;
s_apAdcCoCoNotify[eInstance] = pAdcDmaCfg->pConvCompleteNotify;
DMA_ChannelCfgType tDmaCfg;
if (ADC_HWA_GetSeqGpEn(pAdc) == true)
{
u32ResultStart = ADC_HWA_GetSeqGroupStartPoint(pAdc, (uint8_t)pAdcDmaCfg->eSeqGroupIndex);
u32ResultEnd = ADC_HWA_GetSeqGroupEndPoint(pAdc, (uint8_t)pAdcDmaCfg->eSeqGroupIndex);
tDmaCfg.pSrcBuffer = &pAdc->RESULT[u32ResultStart];
tDmaCfg.pDestBuffer = pAdcDmaCfg->pResultBuffer;
tDmaCfg.u32BlockSize = 4U;
tDmaCfg.u16BlockCount = u32ResultStart - u32ResultEnd;
tDmaCfg.eSrcIncMode = DMA_INCREMENT_DATA_SIZE;
}
else if (ADC_HWA_GetSequenceMode(pAdc) == ADC_SEQMODE_DISCONTINUOUS_1)
{
tDmaCfg.pSrcBuffer = &pAdc->RESULT[0U];
tDmaCfg.pDestBuffer = pAdcDmaCfg->pResultBuffer;
tDmaCfg.u32BlockSize = 4U;
tDmaCfg.u16BlockCount = s_u8ChannelCnt[eInstance];
tDmaCfg.eSrcIncMode = DMA_INCREMENT_DATA_SIZE;
}
else
{
tDmaCfg.pSrcBuffer = &pAdc->FIFO_DATA;
tDmaCfg.pDestBuffer = pAdcDmaCfg->pResultBuffer;
tDmaCfg.u32BlockSize = 4U * s_u8ChannelCnt[eInstance];
tDmaCfg.u16BlockCount = 1U;
tDmaCfg.eSrcIncMode = DMA_INCREMENT_DISABLE;
}
tDmaCfg.eDestIncMode = DMA_INCREMENT_DATA_SIZE;
tDmaCfg.eSrcDataSize = DMA_TRANSFER_SIZE_4B;
tDmaCfg.eDestDataSize = DMA_TRANSFER_SIZE_4B;
tDmaCfg.u8ChannelPriority = pAdcDmaCfg->u8ChannelPriority;
tDmaCfg.bSrcBlockOffsetEn = false;
tDmaCfg.bDestBlockOffsetEn = false;
tDmaCfg.s32BlockOffset = 0;
tDmaCfg.bSrcAddrLoopbackEn = true;
tDmaCfg.bDestAddrLoopbackEn = true;
tDmaCfg.bAutoStop = false;
tDmaCfg.bSrcCircularBufferEn = false;
tDmaCfg.u32SrcCircBufferSize = DMA_CIRCULAR_BUFFER_SIZE_1B;
tDmaCfg.bDestCircularBufferEn = false;
tDmaCfg.u32DestCircBufferSize = DMA_CIRCULAR_BUFFER_SIZE_1B;
if (eInstance == ADC_INSTANCE_0)
{
tDmaCfg.eTriggerSrc = DMA_REQ_ADC0;
}
else if (eInstance == ADC_INSTANCE_1)
{
tDmaCfg.eTriggerSrc = DMA_REQ_ADC1;
}
else
{}
DMA_InterruptCfgType dmaIntCfg = {0};
dmaIntCfg.bTransferCompleteIntEn = true;
if (eInstance == ADC_INSTANCE_0)
{
dmaIntCfg.pTransferCompleteNotify = ADC0_DMAHandler;
}
else if (eInstance == ADC_INSTANCE_1)
{
dmaIntCfg.pTransferCompleteNotify = ADC1_DMAHandler;
}
else
{}
dmaIntCfg.bTransferErrorIntEn = false;
dmaIntCfg.pTransferErrorNotify = NULL;
ADC_HWA_SetDMAEnableFlag(pAdc, true);
DMA_InitChannel(pAdcDmaCfg->eDmaInstance, pAdcDmaCfg->eDmaChannel, &tDmaCfg);
DMA_InitChannelInterrupt(pAdcDmaCfg->eDmaInstance, pAdcDmaCfg->eDmaChannel, &dmaIntCfg);
}
else
{
ADC_HWA_SetDMAEnableFlag(pAdc, false);
}
}
ADC_StatusType ADC_Enable(const ADC_InstanceType eInstance)
{
DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT);
ADC_StatusType eRet = ADC_STATUS_SUCCESS;
uint32_t u32TimeOut = 15000000U;
ADC_Type *const pAdc = s_apAdcBase[eInstance];
ADC_HWA_Enable(pAdc);
while ((ADC_HWA_GetReady(pAdc) != true) && (u32TimeOut != 0U))
{
u32TimeOut--;
}
if (u32TimeOut != 0U)
{
ADC_HWA_ClearReady(pAdc);
eRet = ADC_STATUS_SUCCESS;
}
else
{
eRet = ADC_STATUS_TIMEOUT;
}
return eRet;
}
ADC_StatusType ADC_Disable(const ADC_InstanceType eInstance)
{
DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT);
ADC_StatusType eRet = ADC_STATUS_SUCCESS;
uint32_t u32TimeOut = 15000000U;
ADC_Type *const pAdc = s_apAdcBase[eInstance];
if (ADC_HWA_GetStart(pAdc) == true)
{
eRet = ADC_Stop(eInstance);
}
if (eRet == ADC_STATUS_SUCCESS)
{
ADC_HWA_Disable(pAdc);
while ((ADC_HWA_GetEnable(pAdc) == true) && (u32TimeOut != 0U))
{
u32TimeOut--;
}
if (u32TimeOut != 0U)
{
eRet = ADC_STATUS_SUCCESS;
}
else
{
eRet = ADC_STATUS_TIMEOUT;
}
}
return eRet;
}
void ADC_Start(const ADC_InstanceType eInstance)
{
DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT);
ADC_Type *const pAdc = s_apAdcBase[eInstance];
ADC_HWA_Start(pAdc);
}
ADC_StatusType ADC_Stop(const ADC_InstanceType eInstance)
{
DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT);
ADC_StatusType eRet = ADC_STATUS_ERROR;
uint32_t u32TimeOut = 15000000U;
ADC_Type *const pAdc = s_apAdcBase[eInstance];
ADC_HWA_Stop(pAdc);
while ((ADC_HWA_GetStop(pAdc) == true) && (u32TimeOut != 0U))
{
u32TimeOut--;
}
if (u32TimeOut != 0U)
{
eRet = ADC_STATUS_SUCCESS;
}
else
{
eRet = ADC_STATUS_TIMEOUT;
}
return eRet;
}
void ADC_Reset(const ADC_InstanceType eInstance)
{
DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT);
ADC_Type *const pAdc = s_apAdcBase[eInstance];
ADC_HWA_Reset(pAdc);
}

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/**
* @file fc7xxx_driver_aontimer.c
* @author Flagchip
* @brief FC7xxx aontimer driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_aontimer.h"
#include "fc7xxx_driver_csc.h"
extern void AONTIMER_IRQHandler(void);
/** @brief Aontimer common interrupt handle function */
static void Aontimer_CommonProcessInterrupt(void);
/** @brief Aontimer user defined interrupt function */
static Aontimer_InterruptCallBackType s_pAontimerNotifyPtr = NULL;
/**
* @brief Initialize aontimer instance
*
* @param pInitStruct Aontimer Initialize structure
*/
void AONTIMER_Init(const AONTIMER_InitType *const pInitStruct)
{
DEV_ASSERT(pInitStruct != NULL);
/* Disable the Aontimer, and clear control register. */
AONTIMER_HWA_ConfigModule((uint32_t)0U);
AONTIMER_HWA_ConfigModulePrescale((uint32_t)0U);
AONTIMER->CSR |= AONTIMER_CSR_DBGEN(pInitStruct->eDbgMode);
if (AONTIMER_PULSE_MODE == pInitStruct->eMode)
{
AONTIMER_HWA_SelectClkSrcOnPulseMode(pInitStruct->ePulseClkSrc);
AONTIMER_HWA_ConfigModulePolarity(pInitStruct->ePulsePol);
AONTIMER_HWA_EnablePulseMode();
if (pInitStruct->bBypassEn)
{
AONTIMER_HWA_EnableBypassMode();
}
else
{
AONTIMER_HWA_DisableBypassMode();
}
AONTIMER_HWA_SetPrescale(pInitStruct->u8PulseFilterWidth);
}
else
{
AONTIMER_HWA_SetPrescale(pInitStruct->u8Prescaler);
}
AONTIMER_HWA_SetModuleRunOnDebug();
AONTIMER_HWA_SelectModuleClkSrc(pInitStruct->eClkSrc);
AONTIMER_HWA_SetModuleCompareValue((uint32_t)pInitStruct->u16StartValue);
}
/**
* @brief De-initialize aontimer instance
*
*/
void AONTIMER_Deinit(void)
{
AONTIMER_HWA_ConfigModule((uint32_t)0U);
AONTIMER_HWA_ConfigModulePrescale((uint32_t)0U);
AONTIMER_HWA_SetModuleCompareValue((uint32_t)0xFFFFFFFFU);
s_pAontimerNotifyPtr = NULL;
}
/**
* @brief Initialize aontimer interrupt functionality
*
* @param pIntStruct Aontimer interrupt structure
* @return Aontimer return type
* @note this function will disable timer
*/
AONTIMER_StatusType AONTIMER_InitInterrupt(const AONTIMER_IntType *const pIntStruct)
{
AONTIMER_StatusType eRet = AONTIMER_STATUS_SUCCESS;
if (NULL == pIntStruct)
{
eRet = AONTIMER_STATUS_PARAM_INVALID;
}
else
{
AONTIMER_HWA_DisableTimer();
if (pIntStruct->bIntEn)
{
AONTIMER_HWA_EnableModuleInterrupt();
s_pAontimerNotifyPtr = pIntStruct->pIsrNotify;
}
else
{
AONTIMER_HWA_DisableModuleInterrupt();
s_pAontimerNotifyPtr = NULL;
}
}
return eRet;
}
/**
* @brief Enable AONTIMER interrupt
* @note this function will enable AONTIEMR timer.
*/
void AONTIMER_EnableInterrupt(void)
{
AONTIMER_HWA_DisableTimer();
AONTIMER_HWA_EnableModuleInterrupt();
AONTIMER_HWA_EnableTimer();
}
/**
* @brief Disable AONTIMER interrupt
* @note this function will enable AONTIEMR timer.
*
*/
void AONTIMER_DisableInterrupt(void)
{
AONTIMER_HWA_DisableTimer();
AONTIMER_HWA_DisableModuleInterrupt();
AONTIMER_HWA_EnableTimer();
}
/**
* @brief Start Aontimer
*
*/
void AONTIMER_StartTimer(void)
{
AONTIMER_HWA_EnableTimer();
}
/**
* @brief Stop Aontimer
*
*/
void AONTIMER_StopTimer(void)
{
AONTIMER_HWA_DisableTimer();
}
/**
* @brief Update value of aontimer counter
*
* @param u16StartValue input value, range : 0~65535
*/
void AONTIMER_UpdateCounterValue(const uint16_t u16StartValue)
{
if (0U == (AONTIMER->CSR & AONTIMER_CSR_TMS_MASK))
{
AONTIMER_HWA_DisableTimer();
AONTIMER_HWA_SetModuleCompareValue((uint32_t)u16StartValue);
AONTIMER_HWA_EnableTimer();
}
}
/**
* @brief Aontimer common interrupt handle function
*
*/
static void Aontimer_CommonProcessInterrupt(void)
{
if (NULL != s_pAontimerNotifyPtr)
{
s_pAontimerNotifyPtr();
}
}
/**
* @brief Aontimer interrupt entry
*
*/
void AONTIMER_IRQHandler(void)
{
Aontimer_CommonProcessInterrupt();
AONTIMER_HWA_ClearInterruptFlag();
AONTIMER_HWA_EnableTimer();
}

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/**
* @file fc7xxx_driver_cmp.c
* @author Flagchip0126
* @brief FC7xxx CMP driver source code
* @version 0.1.0
* @date 2024-01-15
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Author CR# Descriptions
* --------- ---------- ------------ ---------- ------------------------
* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240
**********************************************************************************/
#include "fc7xxx_driver_cmp.h"
#include "interrupt_manager.h"
/********* Local Variables ************/
static CMP_Type *const s_apCmpBase[CMP_INSTANCE_COUNT] = CMP_BASE_PTRS;
static CMP_CompleteIntCallback s_apCmpIntNotify[CMP_INSTANCE_COUNT] = {NULL};
/******* Local Function Prototype *********/
/**
* @brief set CMPn IRQHandler
*
* @param eInstance the CMP instance to use
*/
static void CMPn_IRQHandler(const CMP_InstanceType eInstance);
void CMP0_IRQHandler(void);
void CMP1_IRQHandler(void);
static void CMPn_IRQHandler(const CMP_InstanceType eInstance)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
/*callback function*/
if (s_apCmpIntNotify[eInstance] != NULL)
{
s_apCmpIntNotify[eInstance]();
}
else
{
/*Noting to do*/
}
/*clear interrupter status regs*/
CMP_ClearIntFlag(eInstance);
}
void CMP0_IRQHandler(void)
{
CMPn_IRQHandler(CMP_INSTANCE_0);
}
void CMP1_IRQHandler(void)
{
CMPn_IRQHandler(CMP_INSTANCE_1);
}
/********* Local Functions ************/
void CMP_Enable(const CMP_InstanceType eInstance)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
CMP_Type *const pCmp = s_apCmpBase[eInstance];
CMP_HWA_Enable(pCmp);
}
void CMP_Disable(const CMP_InstanceType eInstance)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
CMP_Type *const pCmp = s_apCmpBase[eInstance];
CMP_HWA_Disable(pCmp);
}
void CMP_CSEnable(const CMP_InstanceType eInstance)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
CMP_Type *const pCmp = s_apCmpBase[eInstance];
CMP_HWA_CSEnable(pCmp);
}
void CMP_CSDisable(const CMP_InstanceType eInstance)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
CMP_Type *const pCmp = s_apCmpBase[eInstance];
CMP_HWA_CSDisable(pCmp);
}
bool CMP_GetCmpOut(const CMP_InstanceType eInstance)
{
bool CmpOut;
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
CMP_Type *const pCmp = s_apCmpBase[eInstance];
CmpOut = CMP_HWA_GetCmpOut(pCmp);
return CmpOut;
}
void CMP_SetDacData(const CMP_InstanceType eInstance, uint8_t u8Data)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
CMP_Type *const pCmp = s_apCmpBase[eInstance];
CMP_HWA_SetDacData(pCmp, u8Data);
}
CMP_OutStatus CMP_GetOutFlagStatus(const CMP_InstanceType eInstance)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
bool bCFF_Status = false;
bool bCFR_Status = false;
CMP_Type *const pCmp = s_apCmpBase[eInstance];
CMP_OutStatus eRetVal = CMP_OUT_NONE;
bCFF_Status = CMP_HWA_GetIntFlag_Falling(pCmp);
bCFR_Status = CMP_HWA_GetIntFlag_Rising(pCmp);
if ((bCFF_Status == true) && (bCFR_Status == false))
{
eRetVal = CMP_OUT_FALLING_EDGE;
}
else if ((bCFF_Status == false) && (bCFR_Status == true))
{
eRetVal = CMP_OUT_RISING_EDGE;
}
else
{
eRetVal = CMP_OUT_NONE;
}
return eRetVal;
}
bool CMP_GetChannelScanFlagStatus(const CMP_InstanceType eInstance)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
bool bCSF_Status = false;
CMP_Type *const pCmp = s_apCmpBase[eInstance];
bCSF_Status = CMP_HWA_GetIntFlag_ChannelScan(pCmp);
return bCSF_Status;
}
void CMP_ClearIntFlag(const CMP_InstanceType eInstance)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
CMP_Type *const pCmp = s_apCmpBase[eInstance];
CMP_HWA_ClearIntFlag_Rising(pCmp);
CMP_HWA_ClearIntFlag_Falling(pCmp);
CMP_HWA_ClearIntFlag_ChannelScan(pCmp);
}
void CMP_Init(const CMP_InstanceType eInstance, const CMP_InitType *const pInitCfg)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
DEV_ASSERT(pInitCfg != NULL);
CMP_Type *const pCmp = s_apCmpBase[eInstance];
/* disable CMP module */
CMP_HWA_Disable(pCmp);
/* determine comparator function mode */
CMP_HWA_SetComparatorMod(pCmp, (pInitCfg->tComparatorConfig).eModSel, ((pInitCfg->tComparatorConfig).u8FilterPeriod), ((pInitCfg->tComparatorConfig).eFilterCnt));
/* configure CMP module */
/* CCR0 register */
CMP_HWA_SetEnStopMod(pCmp, (pInitCfg->tComparatorConfig).bStopModEn);
CMP_HWA_SetDacEnableSrc(pCmp, (pInitCfg->tDacConfig).eDacEnsrc);
/* CCR1 register */
CMP_HWA_SetCmpOutInvert(pCmp, (pInitCfg->tComparatorConfig).eInvert);
CMP_HWA_SetCmpOutSel(pCmp, (pInitCfg->tComparatorConfig).eOutSelect);
CMP_HWA_SetEnCmpOutPack(pCmp, (pInitCfg->tComparatorConfig).bOutToPackagePinEn);
CMP_HWA_SetCmpOutWinLevel(pCmp, (pInitCfg->tComparatorConfig).eOutWinLevel);
CMP_HWA_SetCmpOutWin(pCmp, (pInitCfg->tComparatorConfig).eOutWin);
CMP_HWA_SetEnWinSampleInvert(pCmp, (pInitCfg->tComparatorConfig).bWinSampleInvertEn);
CMP_HWA_SetEnEventCloseWin(pCmp, (pInitCfg->tComparatorConfig).bEventCloseWinEn);
CMP_HWA_SetEventCloseWin(pCmp, (pInitCfg->tComparatorConfig).eEventSelect);
/* CCR2 register */
CMP_HWA_SetSpeedMod(pCmp, (pInitCfg->tComparatorConfig).eSpeedMod);
CMP_HWA_SetHystCtrl(pCmp, (pInitCfg->tComparatorConfig).eHystCrtl);
CMP_HWA_SetPSelMux(pCmp, (pInitCfg->tMuxConfig).ePSelMux);
CMP_HWA_SetNSelMux(pCmp, (pInitCfg->tMuxConfig).eNSelMux);
CMP_HWA_SetINPSel(pCmp, (pInitCfg->tMuxConfig).eINPSel);
CMP_HWA_SetINNSel(pCmp, (pInitCfg->tMuxConfig).eINNSel);
/* CCR3 register */
CMP_HWA_SetAnalogConfTransByp(pCmp, (pInitCfg->tComparatorConfig).bAnalogConfTransByp);
CMP_HWA_SetAnalogConfTransBypCnt(pCmp, (pInitCfg->tComparatorConfig).u16AnalogConfTransBypCnt);
/* DCR register */
CMP_HWA_SetEnDac(pCmp, (pInitCfg->tDacConfig).bDacEn);
CMP_HWA_SetVinRefSel(pCmp, (pInitCfg->tDacConfig).eVinRefSel);
CMP_HWA_SetDacData(pCmp, (pInitCfg->tDacConfig).u8DacData);
if ((pInitCfg->tComparatorConfig).eModSel == CMP_MOD_CHANNEL_SCAN)
{
/* CSCR0 register */
CMP_HWA_SetCSInitModulus(pCmp, (pInitCfg->tChannelScanConfig).u8ChannelScanInitModulus);
CMP_HWA_SetCSNumOfSampleClocks(pCmp, (pInitCfg->tChannelScanConfig).u8ChannelScanNumOfSampleClocks);
/* CSCR1 register */
CMP_HWA_SetCSFixedChannel(pCmp, (pInitCfg->tMuxConfig).eChannelScanFixedChannel);
CMP_HWA_SetCSFixedPort(pCmp, (pInitCfg->tMuxConfig).eChannelScanFixedPort);
/* CSCSR register */
CMP_HWA_SetCSComparisonResultsAutoClearEn(pCmp, (pInitCfg->tChannelScanConfig).bComparisonResultAutoClear);
}
}
void CMP_InitInterrupt(const CMP_InstanceType eInstance, const CMP_InterruptType *const pInterruptCfg)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
DEV_ASSERT(pInterruptCfg != NULL);
CMP_Type *const pCmp = s_apCmpBase[eInstance];
/*disable DMA*/
CMP_HWA_DmaDisable(pCmp);
/*clear interrupter flag*/
CMP_ClearIntFlag(eInstance);
/*configure interrupter */
CMP_SetIntEn(eInstance, pInterruptCfg);
s_apCmpIntNotify[eInstance] = pInterruptCfg->pInterrupterNotify;
}
void CMP_InitInterrupt_Dma(const CMP_InstanceType eInstance, const CMP_DmaType *const pInterruptDmaCfg)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
DEV_ASSERT(pInterruptDmaCfg != NULL);
CMP_InterruptType pInterruptCfg;
pInterruptCfg.bRisingIntEn = pInterruptDmaCfg->bRisingDmaEn;
pInterruptCfg.bFallingIntEn = pInterruptDmaCfg->bFallingDmaEn;
pInterruptCfg.bChannelScanFlagIntEn = false;
pInterruptCfg.pInterrupterNotify = NULL;
/* Set rising/falling edge interrupt to trigger Dma*/
CMP_SetIntEn(eInstance, &pInterruptCfg);
if ((pInterruptDmaCfg->bRisingDmaEn == true) || (pInterruptDmaCfg->bFallingDmaEn == true))
{
CMP_DmaEnable(eInstance);
}
else
{
CMP_DmaDisable(eInstance);
}
}
void CMP_SetIntEn(const CMP_InstanceType eInstance, const CMP_InterruptType *const pInterruptCfg)
{
CMP_Type *const pCmp = s_apCmpBase[eInstance];
/*set rising edges interrupter enable*/
CMP_HWA_SetIntEn_Rising(pCmp, pInterruptCfg->bRisingIntEn);
/*set falling edges interrupter enable*/
CMP_HWA_SetIntEn_Falling(pCmp, pInterruptCfg->bFallingIntEn);
/*set channel scan flag interrupter enable*/
CMP_HWA_SetIntEn_ChannelScan(pCmp, pInterruptCfg->bChannelScanFlagIntEn);
}
void CMP_DmaEnable(const CMP_InstanceType eInstance)
{
CMP_Type *const pCmp = s_apCmpBase[eInstance];
CMP_HWA_DmaEnable(pCmp);
}
void CMP_DmaDisable(const CMP_InstanceType eInstance)
{
CMP_Type *const pCmp = s_apCmpBase[eInstance];
CMP_HWA_DmaDisable(pCmp);
}
void CMP_SetCSChannls(const CMP_InstanceType eInstance, const CMP_ChannelScanChannelCfgType s_tChnCfg[], const uint8_t u8ChnCnt)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
uint8_t u8ChnIndex;
CMP_Type *const pCmp = s_apCmpBase[eInstance];
for (u8ChnIndex = 0U; u8ChnIndex < u8ChnCnt; u8ChnIndex++)
{
CMP_HWA_SetCSChannelEn(pCmp, s_tChnCfg[u8ChnIndex].eChannel, true);
CMP_HWA_SetCSChannelPresetstate(pCmp, s_tChnCfg[u8ChnIndex].eChannel, s_tChnCfg[u8ChnIndex].bPreSetState);
}
}
void CMP_GetCSChannlsOut(const CMP_InstanceType eInstance, CMP_ChannelScanChannelCfgType s_tChnCfg[], const uint8_t u8ChnCnt)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
uint8_t u8ChnIndex;
CMP_Type *const pCmp = s_apCmpBase[eInstance];
for (u8ChnIndex = 0U; u8ChnIndex < u8ChnCnt; u8ChnIndex++)
{
s_tChnCfg[u8ChnIndex].bCurState = CMP_HWA_GetCSChannelsOut(pCmp, s_tChnCfg[u8ChnIndex].eChannel);
}
}
bool CMP_GetCmpCSActive(const CMP_InstanceType eInstance)
{
DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT);
CMP_Type *const pCmp = s_apCmpBase[eInstance];
return CMP_HWA_GetCSActive(pCmp);
}

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/**
* @file fc7xxx_driver_cmu.c
* @author Flagchip085
* @brief FC7xxx CMU driver type definition and API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_cmu.h"
#include "fc7xxx_driver_scg.h"
#include "fc7xxx_driver_csc.h"
#include "HwA_cmu.h"
#define CMU_MULTIPLY_FACTOR 100U
#define CMU_PERCENT_FACTOR 100U
#define CMU_DIVID_FACTOR_1K 1000U
/** @brief CMU Reference clock div type. */
/**
* @brief Defines the CMU_ClkFrequenceType
*
* This structure is used to configure the CMU frequence include Reference clock and monitor clock
*
*/
typedef struct
{
uint32_t u32RefClk; /*!< The Reference clock frequence */
uint32_t u32MonitorClk; /*!< The target monitored clock frequence. */
} CMU_ClkFrequenceType;
typedef struct
{
uint32_t u32RefWindow; /*!< CMU_REF_WINDOW (Reference Window). */
uint32_t u32IdealMonitorCnts; /*!< Ideal monitor counter value, used to calculate the MIN,Max threshold. */
uint32_t u32MinThreshold; /*!< CMU_MIN (Minimum threshold). */
uint32_t u32MaxThreshold; /*!< CMU_MAX (Maximum threshold). */
uint32_t u32PerWindow; /*!< CMU_PERIOD (Period monitor mode configuration). */
} CMU_RegMapType;
static CMU_Type *const s_apCmuBase[CMU_INSTANCE_COUNT] = CMU_BASE_PTRS;
static CMU_ISRCallbackType s_apCmuISRCallback[CMU_INSTANCE_COUNT] = {NULL};
void CMU0_IRQHandler(void);
void CMU1_IRQHandler(void);
void CMU2_IRQHandler(void);
void CMU3_IRQHandler(void);
void CMU4_IRQHandler(void);
/* Check Reference clock and monitor clock status.*/
static CMU_StatusType CMU_ClkStatusCheck(CMU_InstanceType eInstance, CMU_ClkFrequenceType *ptCmuFreq)
{
CSC_RetStatusType bCscClkStatus;
CMU_StatusType bCmuClkStatus = CMU_VALID;
if (eInstance == CMU_INSTANCE_0)
{
/* Instance ---- Reference CLK ---- Monitored CLK.*/
/* CMU0 ---- SIRC ---- RTC_CLK.*/
ptCmuFreq->u32RefClk = SCG_GetScgClockFreq(SCG_SIRC_CLK);
bCscClkStatus = CSC0_GetCSC0ClockFreq(CSC0_RTC_CLK, &(ptCmuFreq->u32MonitorClk));
if (bCscClkStatus != CSC_E_OK)
{
bCmuClkStatus = CMU_CLK_ERROR;
}
}
else if (eInstance == CMU_INSTANCE_1)
{
/* Instance ---- Reference CLK ---- Monitored CLK.*/
/* CMU1 ---- SIRC ---- FOSC.*/
ptCmuFreq->u32RefClk = SCG_GetScgClockFreq(SCG_SIRC_CLK);
ptCmuFreq->u32MonitorClk = SCG_GetScgClockFreq(SCG_FOSC_CLK);
}
else if (eInstance == CMU_INSTANCE_2)
{
/* Instance ---- Reference CLK ---- Monitored CLK.*/
/* CMU2 ---- SIRC ---- FIRC.*/
ptCmuFreq->u32RefClk = SCG_GetScgClockFreq(SCG_SIRC_CLK);
ptCmuFreq->u32MonitorClk = SCG_GetScgClockFreq(SCG_FIRC_CLK);
}
else if (eInstance == CMU_INSTANCE_3)
{
/* Instance ---- Reference CLK ---- Monitored CLK.*/
/* CMU3 ---- FIRC ---- SIRC.*/
ptCmuFreq->u32RefClk = SCG_GetScgClockFreq(SCG_FIRC_CLK);
ptCmuFreq->u32MonitorClk = SCG_GetScgClockFreq(SCG_SIRC_CLK);
}
else if (eInstance == CMU_INSTANCE_4)
{
/* Instance ---- Reference CLK ---- Monitored CLK.*/
/* CMU4 ---- SIRC ---- SLOW CLOCK.*/
ptCmuFreq->u32MonitorClk = SCG_GetScgClockFreq(SCG_SLOW_CLK);
ptCmuFreq->u32RefClk = SCG_GetScgClockFreq(SCG_CMU4REF_CLK);
}
else
{
/* Never come here */
bCmuClkStatus = CMU_CLK_ERROR;
}
if(bCmuClkStatus == CMU_VALID)
{
if ((ptCmuFreq->u32MonitorClk == 0U) || (ptCmuFreq->u32RefClk == 0U))
{
bCmuClkStatus = CMU_CLK_ERROR;
}
}
return bCmuClkStatus;
}
CMU_StatusType CMU_Init(CMU_InstanceType eInstance, const CMU_CfgType *pInitCfg)
{
CMU_StatusType eStatus;
CMU_Type *pCmu;
CMU_RefClockDivType eDiv;
CMU_ClkFrequenceType tCmuFreq;
uint32_t u32RefWindow, u32MaxRefWindow, u32MinRefWindow;
uint32_t u32MonitorCnts, u32MinMonitorCnts, u32MaxMonitorCnts;
uint32_t u32RefClk, u32MonitorClk;
uint32_t u32Temp;
DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT);
DEV_ASSERT(pInitCfg != NULL);
pCmu = s_apCmuBase[(uint8_t)eInstance];
eDiv = pInitCfg->eDiv;
/* Check Reference clock and monitor clock status.*/
eStatus = CMU_ClkStatusCheck(eInstance, &tCmuFreq);
if (eStatus == CMU_VALID)
{
/* divide the clock value by 1K_factor */
u32RefClk = (tCmuFreq.u32RefClk >> eDiv) / CMU_DIVID_FACTOR_1K;
u32MonitorClk = tCmuFreq.u32MonitorClk / CMU_DIVID_FACTOR_1K;
if (u32RefClk / u32MonitorClk <= 0x100U)
{
u32MaxRefWindow = (0xffffffU - 3U) / u32MonitorClk * u32RefClk / 105U * CMU_PERCENT_FACTOR - 2U;
if (u32MaxRefWindow > 0xffffffU)
{
u32MaxRefWindow = 0xffffffU;
}
}
else
{
u32MaxRefWindow = 0xffffffU;
}
u32MinRefWindow = 6U + 5U * u32RefClk / u32MonitorClk;
u32RefWindow = 100U * u32MinRefWindow;
if (u32RefWindow > u32MaxRefWindow)
{
u32RefWindow = u32MaxRefWindow;
}
u32MonitorCnts = u32MonitorClk * (u32RefWindow + 2U) / u32RefClk;
u32MinMonitorCnts = u32MonitorCnts * 95U / CMU_PERCENT_FACTOR - 3U;
u32MaxMonitorCnts = u32MonitorCnts * 105U / CMU_PERCENT_FACTOR + 3U;
CMU_HWA_SetRefWindow(pCmu, u32RefWindow);
CMU_HWA_SetMinCnts(pCmu, u32MinMonitorCnts);
CMU_HWA_SetMaxCnts(pCmu, u32MaxMonitorCnts);
/* Program program PERIOD[EN] and PERIOD[WINDOW]. */
CMU_HWA_SetPeriodEnable(pCmu, false);
if (pInitCfg->bPerMonitorEnable == true)
{
uint8_t u8MaxPeriod = (uint8_t)(u32RefClk / u32RefWindow);
if ((u8MaxPeriod >> (uint8_t)CMU_PERIOD_WINDOW_WIDTH) != 0U)
{
u8MaxPeriod = (1U << (uint8_t)CMU_PERIOD_WINDOW_WIDTH) - 1U;
}
if (u8MaxPeriod != 0U)
{
if (pInitCfg->u8PerMonitorWindow <= u8MaxPeriod)
{
CMU_HWA_SetPeriodWindow(pCmu, (uint32_t)(pInitCfg->u8PerMonitorWindow));
}
else
{
CMU_HWA_SetPeriodWindow(pCmu, (uint32_t)(u8MaxPeriod));
}
CMU_HWA_SetPeriodEnable(pCmu, pInitCfg->bPerMonitorEnable);
}
}
/* Program DIV,IRQ_EN,LP_EN,STOP_EN,ENABLE */
u32Temp = CMU_HWA_GetCTRL(pCmu);
u32Temp &= ~(uint32_t)(CMU_CTRL_REF_DIV_MASK | CMU_CTRL_IRQ_EN_MASK | \
CMU_CTRL_LP_EN_MASK | CMU_CTRL_STOP_EN_MASK | CMU_CTRL_ENABLE_MASK);
u32Temp |= (uint32_t)(CMU_CTRL_REF_DIV(eDiv) | CMU_CTRL_IRQ_EN(pInitCfg->bIntEnable) | \
CMU_CTRL_LP_EN(pInitCfg->bLpen) | CMU_CTRL_STOP_EN(pInitCfg->bSten) | \
CMU_CTRL_ENABLE(pInitCfg->bEnable));
CMU_HWA_SETCTRL(pCmu, u32Temp);
s_apCmuISRCallback[(uint8_t)eInstance] = pInitCfg->pIsrCallback;
}
else
{
/* clock status invalid, change, do nothing */
}
return eStatus;
}
void CMU_Enable(CMU_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT);
CMU_HWA_Enable(s_apCmuBase[(uint8_t)eInstance]);
}
void CMU_Disable(CMU_InstanceType eInstance)
{
CMU_Type *pCmu;
DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT);
pCmu = s_apCmuBase[(uint8_t)eInstance];
CMU_HWA_Disable(pCmu);
CMU_HWA_ClearST(pCmu);
}
void CMU_EnableInterrupt(CMU_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT);
CMU_HWA_IrqEnable(s_apCmuBase[(uint8_t)eInstance],true);
}
void CMU_DisableInterrupt(CMU_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT);
CMU_HWA_IrqEnable(s_apCmuBase[(uint8_t)eInstance],false);
}
CMU_InterruptType CMU_GetInterruptType(CMU_InstanceType eInstance)
{
uint32_t u32Temp;
CMU_InterruptType eStatus;
DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT);
u32Temp = CMU_HWA_GetST(s_apCmuBase[(uint8_t)eInstance]);
if ((u32Temp & CMU_ST_LOC_MASK) != 0U)
{
eStatus = CMU_INTERRUPT_LOC;
}
else if ((u32Temp & CMU_ST_MIS_MASK) != 0U)
{
eStatus = CMU_INTERRUPT_MIS;
}
else
{
eStatus = CMU_INTERRUPT_NONE;
}
return eStatus;
}
CMU_StatusType CMU_SetCmu4RefSrc(CMU_Cmu4ClkSrcType eSrc)
{
SCG_StatusType eStatus;
SCG_HWA_SetCmu4Clk(0U);
if (CMU_CMU4_REF_CLK_FOSC == eSrc)
{
eStatus = SCG_SetCmu4Clk(SCG_CMU4CLK_SRC_FOSC);
}
else if (CMU_CMU4_REF_CLK_SIRC == eSrc)
{
eStatus = SCG_SetCmu4Clk(SCG_CMU4CLK_SRC_SIRC);
}
else
{
eStatus = SCG_STATUS_PARAM_ERROR;
}
return (eStatus == SCG_STATUS_SUCCESS) ? CMU_VALID : CMU_CLK_ERROR;
}
uint32_t CMU_GetCount(CMU_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT);
return CMU_HWA_GetCount(s_apCmuBase[(uint8_t)eInstance]);
}
uint32_t CMU_GetMinCount(CMU_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT);
return CMU_HWA_GetMinCnts(s_apCmuBase[(uint8_t)eInstance]);
}
uint32_t CMU_GetMaxCount(CMU_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT);
return CMU_HWA_GetMaxCnts(s_apCmuBase[(uint8_t)eInstance]);
}
void CMU_LowPowerModeEnable(CMU_InstanceType eInstance, CMU_LowpowerModeType eMode, bool bModeEnable, bool bRestartEnable)
{
CMU_Type *pCmu;
DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT);
pCmu = s_apCmuBase[(uint8_t)eInstance];
if (eMode == CMU_STANDBY_MODE)
{
CMU_HWA_StopModeEnable(pCmu, bModeEnable);
CMU_HWA_StanbyModeEnable(pCmu, bModeEnable);
}
else if (eMode == CMU_STOP_MODE)
{
CMU_HWA_StopModeEnable(pCmu, bModeEnable);
}
else
{
}
CMU_HWA_LPRestartEnable(pCmu, bRestartEnable);
}
/***************CMU IRQ Functions*****************/
static void CMU_IRQHandler(CMU_InstanceType eInstance)
{
CMU_Type *pCmu;
CMU_InterruptType eStatus;
DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT);
pCmu = s_apCmuBase[(uint8_t)eInstance];
eStatus = CMU_GetInterruptType(eInstance);
if (s_apCmuISRCallback[(uint8_t)eInstance] != NULL)
{
s_apCmuISRCallback[(uint8_t)eInstance](eInstance, eStatus);
}
CMU_HWA_ClearST(pCmu);
}
void CMU0_IRQHandler(void)
{
CMU_IRQHandler(CMU_INSTANCE_0);
}
void CMU1_IRQHandler(void)
{
CMU_IRQHandler(CMU_INSTANCE_1);
}
void CMU2_IRQHandler(void)
{
CMU_IRQHandler(CMU_INSTANCE_2);
}
void CMU3_IRQHandler(void)
{
CMU_IRQHandler(CMU_INSTANCE_3);
}
void CMU4_IRQHandler(void)
{
CMU_IRQHandler(CMU_INSTANCE_4);
}

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/**
* @file fc7xxx_driver_cordic.c
* @author Flagchip
* @brief FC7xxx Cordic driver source code
* @version 0.1.0
* @date 2024-01-11
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_cordic.h"
#include "interrupt_manager.h"
#define CORDIC_SIGN_BIT 0x80000000UL
#define CORDIC_EXP_BIT 0x7F800000UL
#define CORDIC_TAIL_BIT 0x007FFFFFUL
#define REVERSE_SCALEING_FACTOR_K 0x4dba76b2
#define REVERSE_SCALEING_FACTOR_KA 0x9A8F4314
#define USE_FPU_HARDWARE 0
/**
* @brief Floating-point conversion to 24 bit fixed-point
*
* @param nFloat Input value
*/
/*************** Local Functions ***************/
/**
* @brief Clips Q63 to Q31 values.
*/
__attribute__((always_inline)) static inline int32_t clip_q63_to_q31(
int64_t x)
{
return ((int32_t)(x >> 32) != ((int32_t) x >> 31)) ?
((0x7FFFFFFF ^ ((int32_t)(x >> 63)))) : (int32_t) x;
}
static int32_t Float2Fix_Convert(const float data)
{
return clip_q63_to_q31((int64_t)(data * 2147483648.0f));
}
/***************** Global Functions *******************/
/**
* @brief The function to calculate sin & cos
*
* @param radian the input value to calculate
*
* input range (−90°, +90°)/180°
*/
CORDIC_SinCos_Type Cordic_Circular_Sin_Cos(const float radian)
{
/* angles are expressed in radian, multiplied by a constant number. 𝜃/180 * 𝜋c (where 𝜋c is 13.42177) */
CORDIC_SinCos_Type tRetVal;
//float tmp = REVERSE_SCALEING_FACTOR_K;
float tmp = 0;
int32_t fix_radian = Float2Fix_Convert(radian);
int32_t x_input = REVERSE_SCALEING_FACTOR_K;
Cordic_HWA_Set_XInput(x_input);
Cordic_HWA_Set_YInput(0);
Cordic_HWA_Set_ZInput(fix_radian);
/* Disable interrupt + Iteration Number16 + Trigonometric system + Rotate mode */
Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(0, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Trigonometric, (uint32_t)CORDIC_Rotate));
while (!Cordic_HWA_Get_Stat()) {}
tmp = (int32_t)Cordic_HWA_Get_YOutput() / 2147483648.f; //134217728.f;
tRetVal.sinx = tmp;
tmp = (int32_t)Cordic_HWA_Get_XOutput() / 2147483648.f; //134217728.f;
tRetVal.cosx = tmp;
return tRetVal;
}
/**
* @brief The function to calculate circular radical add
*
* @param1 x the first input value
*
* @param2 y the second input value
*/
CORDIC_Radical_Type Cordic_Circular_Radical_Add(const float x, const float y)
{
CORDIC_Radical_Type tRetVal;
/*** 40752053.5625 = REVERSE_SCALEING_FACTOR_K / 32 ***/
int32_t x_input = (int32_t)(40752053.5625 * x);
int32_t y_input = (int32_t)(40752053.5625 * y);
Cordic_HWA_Set_XInput(x_input);
Cordic_HWA_Set_YInput(y_input);
Cordic_HWA_Set_ZInput(0);
/* Disable interrupt + Iteration Number16 + Trigonometric system + Vector mode */
Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(5, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Trigonometric, (uint32_t)CORDIC_Vector));
while (!Cordic_HWA_Get_Stat()) {}
/*** 67,108,864 = 2147483648.f / 32 ***/
tRetVal = Cordic_HWA_Get_XOutput() / 67108864.f;
return tRetVal;
}
/**
* @brief The function to calculate circular arctan
*
* @param y the input value
*/
CORDIC_Arctan_Type Cordic_Circular_Arctan_F(const float y)
{
CORDIC_Arctan_Type tRetVal;
if ((y > 96.6) || (y < -96.6))
{
tRetVal = 89.4069;
}
else
{
int32_t x_input = 2147484;
int32_t y_input = (int32_t)(y * 2147484);
Cordic_HWA_Set_XInput(x_input);
Cordic_HWA_Set_YInput(y_input);
Cordic_HWA_Set_ZInput(0);
/* Disable interrupt + Iteration Number16 + Trigonometric system + Vector mode */
Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(0, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Trigonometric, (uint32_t)CORDIC_Vector));
while (!Cordic_HWA_Get_Stat()) {}
/*** 11,930,464.711111 = 12147483648 / 180 ***/;
tRetVal = (int32_t)Cordic_HWA_Get_ZOutput() / 11930464.711111;
}
return tRetVal;
}
/**
* @brief The function to calculate circular arctan
*
* @param1 x the first input value
*
* @param2 y the second input value
*/
CORDIC_Arctan_Type Cordic_Circular_Arctan(const int32_t x, const int32_t y)
{
CORDIC_Arctan_Type tRetVal;
Cordic_HWA_Set_XInput(x);
Cordic_HWA_Set_YInput(y);
Cordic_HWA_Set_ZInput(0);
/* Disable interrupt + Iteration Number16 + Trigonometric system + Vector mode */
Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(0, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Trigonometric, (uint32_t)CORDIC_Vector));
while (!Cordic_HWA_Get_Stat()) {}
/*** 11,930,464.711111 = 12147483648 / 180 ***/;
tRetVal = (int32_t)Cordic_HWA_Get_ZOutput() / 11930464.711111;
return tRetVal;
}
/**
* @brief The function to calculate circular Sinh & Cosh
*
* @param z the input value
*/
CORDIC_SinhCosh_Type Cordic_Circular_Sinh_Cosh(const float z)
{
CORDIC_SinhCosh_Type tRetVal;
float tmp = 0;
/*** 1073741824 = 2147483648 / 2 ***/
int32_t z_input = (int32_t)(z * 1073741824.f);
/*** 1296540042 = REVERSE_SCALEING_FACTOR_KA / 2 ***/
int32_t x_input = 1296540042;
Cordic_HWA_Set_XInput(x_input);
Cordic_HWA_Set_YInput(0);
Cordic_HWA_Set_ZInput(z_input);
/* Scale 1 + Disable interrupt + Iteration Number16 + Hyperbolic system + Rotate mode */
Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(1, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Hyperbolic, (uint32_t)CORDIC_Rotate));
while (!Cordic_HWA_Get_Stat()) {}
/*** 1073741824 = 2147483648 / 2 ***/
tmp = (int32_t)Cordic_HWA_Get_YOutput() / 1073741824.f ;
tRetVal.sinxh = tmp;
/*** 1073741824 = 2147483648 / 2 ***/
tmp = (int32_t)Cordic_HWA_Get_XOutput() / 1073741824.f;
tRetVal.cosxh = tmp;
return tRetVal;
}
/**
* @brief The function to calculate circular radical sub
*
* @param1 x the first input value
*
* @param2 y the second input value
*/
CORDIC_Radical_Type Cordic_Circular_Radical_Sub(const float x, const float y)
{
CORDIC_Radical_Type tRetVal;
/*** 162067505 = REVERSE_SCALEING_FACTOR_KA / 16 ***/
int32_t x_input = (int32_t)(162067505.f * x);
int32_t y_input = (int32_t)(162067505.f * y);
Cordic_HWA_Set_XInput(x_input);
Cordic_HWA_Set_YInput(y_input);
Cordic_HWA_Set_ZInput(0);
/* Disable interrupt + Iteration Number16 + Hyperbolic system + Vector mode */
Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(4, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Hyperbolic, (uint32_t)CORDIC_Vector));
while (!Cordic_HWA_Get_Stat()) {}
/*** 134217728 = 2147483648.f / 16 ***/
tRetVal = Cordic_HWA_Get_XOutput() / 134217728.f;
return tRetVal;
}
/**
* @brief The function to calculate circular arctanh
*
* @param y the input value
*/
CORDIC_Arctanh_Type Cordic_Circular_Arctanh(const float y)
{
CORDIC_Arctanh_Type tRetVal;
/*** 1073741824 = 2147483648 / 2 ***/
int32_t x_input = 1073741824;
int32_t y_input = (int32_t)(y * 1073741824.f);
Cordic_HWA_Set_XInput(x_input);
Cordic_HWA_Set_YInput(y_input);
Cordic_HWA_Set_ZInput(0);
/* Disable interrupt + Iteration Number16 + Hyperbolic system + Vector mode */
Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(1, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Hyperbolic, (uint32_t)CORDIC_Vector));
while (!Cordic_HWA_Get_Stat()) {}
/*** 1073741824 = 2147483648 / 2 ***/
tRetVal = (int32_t)Cordic_HWA_Get_ZOutput() / 1073741824.f;
return tRetVal;
}
/**
* @brief The function to calculate ln
*
* @param y the input value (0.1068482375 , 9.3590687463)
*/
CORDIC_Ln_Type Cordic_Extended_LN(const float y)
{
CORDIC_Ln_Type tRetVal;
/*** 134217728 = 2147483648 / 16 ***/
int32_t x_input = (int32_t)((y + 1) * 134217728.f);
int32_t f_input = (int32_t)((y - 1) * 134217728.f);
Cordic_HWA_Set_XInput(x_input);
Cordic_HWA_Set_YInput(f_input);
Cordic_HWA_Set_ZInput(0);
/* Disable interrupt + Iteration Number16 + Hyperbolic system + Vector mode */
Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(4, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Hyperbolic, (uint32_t)CORDIC_Vector));
while (!Cordic_HWA_Get_Stat()) {}
/*** 67108864 = 12147483648.f / 32 ***/;
tRetVal = (int32_t)Cordic_HWA_Get_ZOutput() / 67108864.f;
return tRetVal;
}
/**
* @brief The function to calculate sqrt
*
* @param y the input value (0.0267120594,2.3397671865)
*/
CORDIC_Ln_Type Cordic_Extended_Sqrt(const float y)
{
CORDIC_Radical_Type tRetVal;
/*** 648270021 = 2593080084 / 4 ***/
int32_t x_input = (int32_t)(648270021.f * (y + 0.25));
int32_t y_input = (int32_t)(648270021.f * (y - 0.25));
Cordic_HWA_Set_XInput(x_input);
Cordic_HWA_Set_YInput(y_input);
Cordic_HWA_Set_ZInput(0);
/* Disable interrupt + Iteration Number16 + Hyperbolic system + Vector mode */
Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(2, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Hyperbolic, (uint32_t)CORDIC_Vector));
while (!Cordic_HWA_Get_Stat()) {}
/*** 536870912 = 2147483648 / 4 ***/
tRetVal = Cordic_HWA_Get_XOutput() / 536870912.f;
return tRetVal;
}

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/* @file fc7xxx_driver_cpm.c
* @author Flagchip
* @brief FC7xxx CPM driver type definition and API
* @version 0.1.0
* @date 2024-01-5
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-1-5 Flagchip120 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_cpm.h"
#include "interrupt_manager.h"
#include "fc7xxx_driver_fcuart.h"
/**
* @brief Cpm user defined interrupt function
* */
static CPM_InterruptCallBackType s_pCpmNotifyPtr = NULL;
/* ################################################################################## */
/* ########################### Local Prototype Functions ############################ */
void CPM_IRQHandler(void);
/* ################################################################################## */
/* ################################ Global Functions ################################ */
/**
*
* @brief Configures the CPM module interrupts.
*
* This function configures the CPM module interrupts to enable/disable various interrupt sources.
*
* @param eIntSrc CPM FPU interrupt type. refer CPM FISCR register
* @param bEnable 1: interrupt enable, 0:interrupt disable.
*/
void CPM_FpuIntMode(FPU_IntType eIntSrc, bool bEnable)
{
switch (eIntSrc)
{
case CPM_FPU_FIO:
CPM_HWA_SetFioceInt(bEnable);
break;
case CPM_FPU_FDZ:
CPM_HWA_SetFdzceInt(bEnable);
break;
case CPM_FPU_FOF:
CPM_HWA_SetFofceInt(bEnable);
break;
case CPM_FPU_FUF:
CPM_HWA_SetFufceInt(bEnable);
break;
case CPM_FPU_FIX:
CPM_HWA_SetFixceInt(bEnable);
break;
case CPM_FPU_FID:
CPM_HWA_SetFidceInt(bEnable);
break;
default :
/* Invalid parameter: return */
break;
}
}
/**
* @brief Get CPM Interrupt occurred flag
*
* This function returns the interrupt flag.
*
* @param eIntSrc CPM FPU interrupt type. refer CPM FISCR register
* @return true interrupt occurred
* @return false No interrupt
*/
bool CPM_GetFpuIntStatus(FPU_IntType eIntSrc)
{
bool bRetVal = false;
switch(eIntSrc){
case CPM_FPU_FIO:
bRetVal = CPM_HWA_GetFpuFiocFlag();
break;
case CPM_FPU_FDZ:
bRetVal = CPM_HWA_GetFpuFdzcFlag();
break;
case CPM_FPU_FOF:
bRetVal = CPM_HWA_GetFpuFofcFlag();
break;
case CPM_FPU_FUF:
bRetVal = CPM_HWA_GetFpuFufcFlag();
break;
case CPM_FPU_FIX:
bRetVal = CPM_HWA_GetFpuFixcFlag();
break;
case CPM_FPU_FID:
bRetVal = CPM_HWA_GetFpuFidcFlag();
break;
default:
break;
}
return bRetVal;
}
#ifdef FPU_USED_ENABLE
/**
* @brief CPM_Read_FPSCR
* Return the current value of FPSCR
* @return u32RetVal
*/
uint32_t CPM_Read_FPSCR(void)
{
uint32_t u32RetVal = 0U;
__asm(
"vmrs %0, fpscr" : "=r" (u32RetVal)
);
return u32RetVal;
}
/**
* @brief CPM_Write_FPSCR
*
* @param u32SetVal set the value for FPSCR
*/
void CPM_Write_FPSCR(uint32_t u32SetVal)
{
__asm(
"vmsr fpscr, %0" : : "r" (u32SetVal)
);
}
/**
* @brief Deinit Cpm set interrupt
*
* Restore the Cpm FISCR to its reset state
*/
void CPM_DeInitInterrupt(void)
{
uint32_t u32RetVal;
CPM_HWA_SetFiscr(0x0U);
u32RetVal = CPM_Read_FPSCR();
/* Clear FPSCR IDC/IXC/UFC/OPF/DZC/IOC flag*/
u32RetVal &=0xFFFFFF90u;
CPM_Write_FPSCR(u32RetVal);
}
#endif
/**
* @brief CPM interrupt function
*
*/
void CPM_IRQHandler(void)
{
if(s_pCpmNotifyPtr != NULL)
{
s_pCpmNotifyPtr();
}
}
/**
* @brief Cpm set interrupt
*
* @param pIntStruct interrupt structure pointer
* @return Cpm return type
*/
CPM_RetType CPM_InitInterrupt(const CPM_InterruptType *pIntStruct)
{
CPM_RetType eRet = CPM_STATUS_SUCCESS;
if(NULL == pIntStruct)
{
eRet = CPM_STATUS_PARAM_INVALID;
}
else
{
if(pIntStruct->u8CpmEnable != 0U)
{
if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FIOC_MASK) == CPM_FPU_FIO)
{
CPM_FpuIntMode(CPM_FPU_FIO,true);
}
if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FDZC_MASK) == CPM_FPU_FDZ)
{
CPM_FpuIntMode(CPM_FPU_FDZ,true);
}
if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FUFC_MASK) == CPM_FPU_FUF)
{
CPM_FpuIntMode(CPM_FPU_FUF,true);
}
if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FOFC_MASK) == CPM_FPU_FOF)
{
CPM_FpuIntMode(CPM_FPU_FOF,true);
}
if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FIDC_MASK) == CPM_FPU_FID)
{
CPM_FpuIntMode(CPM_FPU_FID,true);
}
if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FIXC_MASK) == CPM_FPU_FIX)
{
CPM_FpuIntMode(CPM_FPU_FIX,true);
}
}
s_pCpmNotifyPtr = pIntStruct->pIsrNotify;
}
return eRet;
}

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/**
* @file fc7xxx_driver_crc.c
* @author Flagchip
* @brief FC7xxx CRC driver source code
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_crc.h"
/********* Local Variables ************/
static CRC_Type *const s_apCrcBase[CRC_INSTANCE_COUNT] = CRC_BASE_PTRS;
/********* Local Functions ************/
void CRC_Init(uint8_t u8Instance, const CRC_InitType *const pInitCfg)
{
DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT);
DEV_ASSERT(pInitCfg != NULL);
CRC_Type *const pCrc = s_apCrcBase[u8Instance];
if (pInitCfg->eBitWidth == CRC_BIT_8)
{
/* set CRC bit width(8-bit) */
CRC_HWA_Set_8Bit_Width(pCrc, (CRC_BitWidthType)(pInitCfg->eBitWidth - 1));
CRC_HWA_SetBitWidth(pCrc, (CRC_BitWidthType)0);
}
else
{
/* set CRC bit width(16-bit or 32-bit) */
CRC_HWA_Set_8Bit_Width(pCrc, (CRC_BitWidthType)0);
CRC_HWA_SetBitWidth(pCrc, pInitCfg->eBitWidth);
}
/* set CRC write/read swap and FXOR */
CRC_HWA_SetWriteDataSwap(pCrc, pInitCfg->eWriteDataSwap);
CRC_HWA_SetReadDataSwap(pCrc, pInitCfg->eReadDataSwap);
CRC_HWA_SetReadDataFXOR(pCrc, pInitCfg->eReadDataFXOR);
/* set CRC polynomial value */
CRC_HWA_SetPolyVal(pCrc, pInitCfg->u32Polynomial);
/* set CRC seed value */
CRC_SetSeed(u8Instance, pInitCfg->u32SeedValue);
}
void CRC_DeInit(uint8_t u8Instance)
{
DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT);
CRC_Type *const pCrc = s_apCrcBase[u8Instance];
/* set CRC bit width(32-bit) */
CRC_HWA_SetBitWidth(pCrc, CRC_BIT_32);
/* set CRC write/read swap and FXOR */
CRC_HWA_SetWriteDataSwap(pCrc, WRITE_DATASWAP_NONE);
CRC_HWA_SetReadDataSwap(pCrc, READ_DATASWAP_NONE);
CRC_HWA_SetReadDataFXOR(pCrc, READ_DATA_NORMAL);
/* set CRC polynomial value */
CRC_HWA_SetPolyVal(pCrc, CRC_DEFAULT_POLY);
/* set CRC seed value */
CRC_SetSeed(u8Instance, CRC_DEFAULT_INTVAL);
}
uint32_t CRC_GetCrcResult(uint8_t u8Instance)
{
DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT);
CRC_Type *const pCrc = s_apCrcBase[u8Instance];
CRC_ReadDataSwapType eTempVal;
uint32_t u32Ret;
eTempVal = CRC_HWA_GetReadDataSwap(pCrc);
if (CRC_BIT_8 == CRC_HWA_Get8BitWidth(pCrc))
{
/* Returns upper 8 bits of CRC because of swap in 8 bits mode */
if ((eTempVal == READ_DATASWAP_BIT_BYTE) || (eTempVal == READ_DATASWAP_BYTE))
{
u32Ret = CRC_HWA_GetData_U8_H(pCrc);
}
else
{
u32Ret = CRC_HWA_GetData_U8_L(pCrc);
}
return u32Ret;
}
else if (CRC_BIT_16 == CRC_HWA_GetBitWidth(pCrc))
{
/* Returns upper 16 bits of CRC because of swap in 16 bits mode */
if ((eTempVal == READ_DATASWAP_BIT_BYTE) || (eTempVal == READ_DATASWAP_BYTE))
{
u32Ret = CRC_HWA_GetData_U16_H(pCrc);
}
else
{
u32Ret = CRC_HWA_GetData_U16_L(pCrc);
}
}
else
{
u32Ret = CRC_HWA_GetData_U32(pCrc);
}
return u32Ret;
}
void CRC_SetCalcData_U8(uint8_t u8Instance, uint8_t u8Data)
{
DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT);
CRC_Type *const pCrc = s_apCrcBase[u8Instance];
CRC_HWA_SetData_U8(pCrc, u8Data);
}
void CRC_SetCalcData_U16(uint8_t u8Instance, uint16_t u16Data)
{
DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT);
CRC_Type *const pCrc = s_apCrcBase[u8Instance];
CRC_HWA_SetData_U16(pCrc, u16Data);
}
void CRC_SetCalcData_U32(uint8_t u8Instance, uint32_t u32Data)
{
DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT);
CRC_Type *const pCrc = s_apCrcBase[u8Instance];
CRC_HWA_SetData_U32(pCrc, u32Data);
}
void CRC_SetSeed(uint8_t u8Instance, uint32_t u32SeedVal)
{
DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT);
CRC_Type *const pCrc = s_apCrcBase[u8Instance];
CRC_HWA_SetDataOrSeed(pCrc, WRITE_COMMAND_SEED);
CRC_HWA_SetData_U32(pCrc, u32SeedVal);
CRC_HWA_SetDataOrSeed(pCrc, WRITE_COMMAND_DATA);
}
void CRC_SetInputData(uint8_t u8Instance, const uint8_t pData[], uint32_t u32DataSize)
{
DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT);
uint32_t i;
for (i = 0U; i < u32DataSize; i++)
{
CRC_SetCalcData_U8(u8Instance, pData[i]);
}
}

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/**
* @file fc7xxx_driver_dma.c
* @author Flagchip0126
* @brief FC7xxx DMA driver source code
* @version 0.1.0
* @date 2024-01-15
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Author CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_dma.h"
#include "interrupt_manager.h"
#define DMA_CHANNEL_INVALID (0xFFU)
#define CPM_CORE_ID_CORE0 (0x0U)
#define CPM_CORE_ID_CORE1 (0x2U)
#define CPM_CORE_ID_CORE2 (0x4U)
static uint8_t s_aDmaDumoUsedStatus[DMA_DUMO_COUNT] = {DMA_CHANNEL_INVALID, DMA_CHANNEL_INVALID, DMA_CHANNEL_INVALID, DMA_CHANNEL_INVALID};
static DMA_TransferCompleteCallbackType s_dmaTransferCompleteNotify[DMA_INSTANCE_COUNT][DMA_CFG_COUNT] = {NULL};
static DMA_TransferErrorCallbackType s_dmaTransferErrorNotify[DMA_INSTANCE_COUNT][DMA_CFG_COUNT] = {NULL};
/**
* @brief DMA IRQ function prototypes
*
*/
void DMA0_IRQHandler(void);
void DMA1_IRQHandler(void);
void DMA2_IRQHandler(void);
void DMA3_IRQHandler(void);
void DMA4_IRQHandler(void);
void DMA5_IRQHandler(void);
void DMA6_IRQHandler(void);
void DMA7_IRQHandler(void);
void DMA8_IRQHandler(void);
void DMA9_IRQHandler(void);
void DMA10_IRQHandler(void);
void DMA11_IRQHandler(void);
void DMA12_IRQHandler(void);
void DMA13_IRQHandler(void);
void DMA14_IRQHandler(void);
void DMA15_IRQHandler(void);
void DMA_Error_IRQHandler(void);
/**
* @brief Get the first unused DUMO register index
*
* @param [out] pDumoIndex the DUMO register index
* @return DMA_StatusType whether there is unused DUMO index
* @return DMA_STATUS_SUCCESS the DUMO register index is successfully get
* @return DMA_STATUS_NO_RESOURCE all DUMO registers are already occupied
*/
static inline DMA_StatusType DMA_GetDumoIndex(uint8_t *pDumoIndex);
/**
* @brief Check whether the value is power of 2 and return the ceil value of the log2(u32Value)
*
* @param [in] u32Value the value to check
* @param [out] u8Log2 the ceil value of log2(u32Value)
* @return true the u32Value is power of 2
* @return false the u32Value is not power of 2
*/
static bool DMA_IsPowerOf2(uint32_t u32Value, uint8_t *u8Log2);
/**
* @brief Reset the DMAMUX config values
* @param Dmamux_Instance the selected DMA Instance
*
*/
static inline void Dmamux_Reset(DMAMUX_Type * const Dmamux_Instance);
/**
* @brief Get the data offset value of the selected increment mode and data size
*
* @param eIncMode the selected increment mode
* @param eDataSize the selected data size
* @return int16_t the calculated data offset
*/
static inline uint16_t DMA_GetDataOffset(DMA_IncrementModeType eIncMode,
DMA_TransferSizeType eDataSize);
/**
* @brief Get the IRQ number of the selected DMA channel
*
* @param u8Channel the selected DMA channel
* @return IRQn_Type the IRQ number of the selected DMA channel
*/
//static inline IRQn_Type DMA_GetChannelIRQn(const DMA_InstanceType eDma_Instance);
/**
* @brief The internal interrupt handler for DMA transfer complete
*
* @param u8Channel the channel of the DMA interrpt
*/
static inline void DMA_Transfer_Complete_IRQHandler(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel);
static inline DMA_StatusType DMA_GetDumoIndex(uint8_t *pDumoIndex)
{
DMA_StatusType ret = DMA_STATUS_ERROR;
for (*pDumoIndex = 0U; *pDumoIndex < DMA_DUMO_COUNT; (*pDumoIndex)++)
{
if (s_aDmaDumoUsedStatus[*pDumoIndex] == DMA_CHANNEL_INVALID)
{
ret = DMA_STATUS_SUCCESS;
break;
}
}
if (*pDumoIndex == DMA_DUMO_COUNT)
{
ret = DMA_STATUS_NO_RESOURCE;
}
return ret;
}
static bool DMA_IsPowerOf2(uint32_t u32Value, uint8_t *u8Log2)
{
bool ret = (bool)false;
*u8Log2 = 0U;
while (u32Value > (1UL << *u8Log2))
{
(*u8Log2)++;
}
if ((u32Value & ((1UL << *u8Log2) - 1U)) == 0U)
{
ret = (bool)true;
}
return ret;
}
static inline uint16_t DMA_GetDataOffset(DMA_IncrementModeType eIncMode,
DMA_TransferSizeType eDataSize)
{
uint16_t u16DataOffset = 0U;
switch (eIncMode)
{
case DMA_INCREMENT_DISABLE:
{
u16DataOffset = 0U;
break;
}
case DMA_INCREMENT_DATA_SIZE:
{
u16DataOffset = (uint16_t)(1UL << ((uint8_t)eDataSize));
break;
}
case DMA_INCREMENT_DATA_SIZE_4BYTE_ALIGNED:
{
switch (eDataSize)
{
case DMA_TRANSFER_SIZE_1B:
case DMA_TRANSFER_SIZE_2B:
case DMA_TRANSFER_SIZE_4B:
u16DataOffset = 4U;
break;
case DMA_TRANSFER_SIZE_8B:
u16DataOffset = 8U;
break;
case DMA_TRANSFER_SIZE_32B:
u16DataOffset = 32U;
break;
default:
break;
}
break;
}
default:
break;
}
return u16DataOffset;
}
void DMA0_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_0);
}
void DMA1_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_1);
}
void DMA2_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_2);
}
void DMA3_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_3);
}
void DMA4_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_4);
}
void DMA5_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_5);
}
void DMA6_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_6);
}
void DMA7_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_7);
}
void DMA8_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_8);
}
void DMA9_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_9);
}
void DMA10_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_10);
}
void DMA11_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_11);
}
void DMA12_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_12);
}
void DMA13_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_13);
}
void DMA14_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_14);
}
void DMA15_IRQHandler(void)
{
DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_15);
}
void DMA_Error_IRQHandler(void)
{
uint8_t u8Channel;
DMA_InstanceType eDma_Instance;
DMA_Type *pDma;
DMA_Type * aDma[] = DMA_BASE_PTRS;
eDma_Instance = DMA_INSTANCE_0;
pDma = aDma[DMA_INSTANCE_0];
for (u8Channel = 0U; u8Channel < DMA_CFG_COUNT; u8Channel++)
{
if (DMA_HWA_GetChannelErrorFlag(pDma, u8Channel) == true)
{
DMA_HWA_ClearChannelErrorFlag(pDma, u8Channel);
if (s_dmaTransferErrorNotify[eDma_Instance][u8Channel] != NULL)
{
s_dmaTransferErrorNotify[eDma_Instance][u8Channel]();
}
}
}
}
static inline void DMA_Transfer_Complete_IRQHandler(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel)
{
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
DMA_HWA_ClearChannelInterruptFlag(pDma, (uint8_t)eChannel);
if (s_dmaTransferCompleteNotify[eDma_Instance][eChannel] != NULL)
{
s_dmaTransferCompleteNotify[eDma_Instance][eChannel]();
}
}
static inline void Dmamux_Reset(DMAMUX_Type * const Dmamux_Instance)
{
uint8_t u8Index;
for (u8Index = 0U; u8Index < DMAMUX_CHCFG_COUNT; u8Index++)
{
DMAMUX_HWA_SetRequestSource(Dmamux_Instance, u8Index, false, DMA_REQ_DISABLED);
}
for (u8Index = 0U; u8Index < DMAMUX_CHTRG_TRG_COUNT; u8Index++)
{
//DMAMUX_HWA_SetPeriodicTrigFlag(Dmamux_Instance, u8Index, false);
}
}
void DMA_Init(const DMA_InstanceType eDma_Instance, const DMA_InitType *const pInitCfg)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
DEV_ASSERT(pInitCfg != NULL);
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
DMA_DeInit(eDma_Instance);
DMA_HWA_SetHaltOnErrorFlag(pDma, pInitCfg->bHaltOnError);
DMA_HWA_SetArbitrationAlgorithm(pDma, pInitCfg->eArbitrationAlgorithm);
DMA_HWA_SetInnerLoopMappingEnableFlag(pDma, true);
}
void DMA_DeInit(const DMA_InstanceType eDma_Instance)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
uint8_t u8Index;
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
DMAMUX_Type * aDmamux[] = DMAMUX_BASE_PTRS;
DMAMUX_Type *const pDmamux = aDmamux[eDma_Instance];
DMA_HWA_SetControlRegister(pDma, 0U);
DMA_HWA_DisableAllChannelErrorInterrupt(pDma);
DMA_HWA_DisableAllChannelRequest(pDma);
DMA_HWA_ClearAllChannelDoneStatus(pDma);
DMA_HWA_ClearAllChannelErrorFlag(pDma);
DMA_HWA_ClearAllChannelInterruptFlag(pDma);
pDma->DUME[0] = 0U;
for (u8Index = 0U; u8Index < DMA_DUMO_COUNT; u8Index++)
{
DMA_HWA_SetUnalignModulo(pDma, u8Index, 0U, 0U);
}
for (u8Index = 0U; u8Index < DMA_CFG_COUNT; u8Index++)
{
DMA_HWA_SetUnalignModuloEnableFlag(pDma, u8Index, false, false);
DMA_HWA_SetPriority(pDma, u8Index, u8Index);
DMA_HWA_SetSrcAddr(pDma, u8Index, 0U);
DMA_HWA_SetSrcOffset(pDma, u8Index, 0);
DMA_HWA_SetSrcLastAddrAdjustment(pDma, u8Index, 0);
DMA_HWA_SetDestAddr(pDma, u8Index, 0U);
DMA_HWA_SetDestOffset(pDma, u8Index, 0);
DMA_HWA_SetDestLastAddrAdjustment(pDma, u8Index, 0);
DMA_HWA_SetSrcDataSize(pDma, u8Index, DMA_TRANSFER_SIZE_1B);
DMA_HWA_SetSrcModulo(pDma, u8Index, 0U);
DMA_HWA_SetDestDataSize(pDma, u8Index, DMA_TRANSFER_SIZE_1B);
DMA_HWA_SetDestModulo(pDma, u8Index, 0U);
DMA_HWA_SetInnerLoopSize(pDma, u8Index, 0U);
DMA_HWA_SetChannelControlStatus(pDma, u8Index, 0U);
DMA_HWA_SetChannelToChannelTrig(pDma, u8Index, false, 0U);
DMA_HWA_SetLoopCount(pDma, u8Index, 0U);
}
Dmamux_Reset(pDmamux);
}
DMA_StatusType DMA_InitChannel(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel, const DMA_ChannelCfgType *const pChnCfg)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
DEV_ASSERT(eChannel < DMA_CHANNEL_MAX);
DEV_ASSERT(pChnCfg != NULL);
DEV_ASSERT(pChnCfg->u16BlockCount > 0U);
DEV_ASSERT(pChnCfg->u32BlockSize > 0U);
DEV_ASSERT(((pChnCfg->u32BlockSize >> pChnCfg->eSrcDataSize) << pChnCfg->eSrcDataSize == pChnCfg->u32BlockSize) &&
((pChnCfg->u32BlockSize >> pChnCfg->eDestDataSize) << pChnCfg->eDestDataSize == pChnCfg->u32BlockSize));
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
DMAMUX_Type * aDmamux[] = DMAMUX_BASE_PTRS;
DMAMUX_Type *const pDmamux = aDmamux[eDma_Instance];
DMA_StatusType ret;
uint16_t u16SrcDataOffset = DMA_GetDataOffset(pChnCfg->eSrcIncMode, pChnCfg->eSrcDataSize);
uint16_t u16DestDataOffset = DMA_GetDataOffset(pChnCfg->eDestIncMode, pChnCfg->eDestDataSize);
int32_t s32SrcLastOffset;
int32_t s32DestLastOffset;
uint8_t u8SrcMod = 0U;
uint8_t u8DestMod = 0U;
bool bUseSrcDumo = (bool)false;
bool bUseDestDumo = (bool)false;
uint8_t u8DumoIndex = 0U;
uint16_t u16Sumo = 0U;
uint16_t u16Dumo = 0U;
if ((pChnCfg->bSrcCircularBufferEn == true) || (pChnCfg->bDestCircularBufferEn == true))
{
/* If the circular buffer size is not power of 2 aligned, need to use the DUMO */
if (pChnCfg->bSrcCircularBufferEn == true)
{
DEV_ASSERT(pChnCfg->u32SrcCircBufferSize != 0U);
bUseSrcDumo = (bool)(DMA_IsPowerOf2(pChnCfg->u32SrcCircBufferSize, &u8SrcMod) ? false : true);
}
if (pChnCfg->bDestCircularBufferEn == true)
{
DEV_ASSERT(pChnCfg->u32DestCircBufferSize != 0U);
bUseDestDumo = (bool)(DMA_IsPowerOf2(pChnCfg->u32DestCircBufferSize, &u8DestMod) ? false : true);
}
/* If circular buffer is enabled, the buffer address must be power of 2 aligned */
if (((pChnCfg->bSrcCircularBufferEn == true) &&
(((uint32_t)pChnCfg->pSrcBuffer & ((1UL << u8SrcMod) - 1U)) != 0U)) ||
((pChnCfg->bDestCircularBufferEn == true) &&
(((uint32_t)pChnCfg->pDestBuffer & ((1UL << u8DestMod) - 1U)) != 0U)))
{
ret = DMA_STATUS_INVALID_ADDRESS;
}
/* If circular buffer is enabled, the buffer size must not less than the data offset */
else if (((pChnCfg->bSrcCircularBufferEn == true) &&
(pChnCfg->u32SrcCircBufferSize < u16SrcDataOffset)) ||
((pChnCfg->bDestCircularBufferEn == true) &&
(pChnCfg->u32DestCircBufferSize < u16SrcDataOffset)))
{
ret = DMA_STATUS_UNSUPPORTED;
}
/* If source or destination unalign modulo is used, check whether all DUMO registers are occupied */
else if ((bUseSrcDumo == true) || (bUseDestDumo == true))
{
ret = DMA_GetDumoIndex(&u8DumoIndex);
if (ret == DMA_STATUS_SUCCESS)
{
s_aDmaDumoUsedStatus[u8DumoIndex] = (uint8_t)eChannel;
}
}
else
{
ret = DMA_STATUS_SUCCESS;
}
}
else
{
ret = DMA_STATUS_SUCCESS;
}
if (ret == DMA_STATUS_SUCCESS)
{
if (pChnCfg->bSrcAddrLoopbackEn == true)
{
if (pChnCfg->bSrcBlockOffsetEn == false)
{
s32SrcLastOffset = -((int32_t)((pChnCfg->u32BlockSize >> pChnCfg->eSrcDataSize) * u16SrcDataOffset) *
(int32_t)(pChnCfg->u16BlockCount));
}
else
{
s32SrcLastOffset = -(((int32_t)((pChnCfg->u32BlockSize >> pChnCfg->eSrcDataSize) * u16SrcDataOffset)) *
(int32_t)(pChnCfg->u16BlockCount)) - ((pChnCfg->s32BlockOffset) * (int32_t)(pChnCfg->u16BlockCount - 1U));
}
}
else
{
s32SrcLastOffset = 0;
}
if (pChnCfg->bDestAddrLoopbackEn == true)
{
if (pChnCfg->bDestBlockOffsetEn == false)
{
s32DestLastOffset = -(((pChnCfg->u32BlockSize >> pChnCfg->eDestDataSize) * u16DestDataOffset) *
(pChnCfg->u16BlockCount));
}
else
{
s32DestLastOffset = -(((int32_t)((pChnCfg->u32BlockSize >> pChnCfg->eDestDataSize) * u16DestDataOffset)) *
(int32_t)(pChnCfg->u16BlockCount)) - ((pChnCfg->s32BlockOffset) * (int32_t)(pChnCfg->u16BlockCount - 1U));
}
}
else
{
s32DestLastOffset = 0;
}
DMA_HWA_SetSrcAddr(pDma, (uint8_t)eChannel, (uint32_t)pChnCfg->pSrcBuffer);
DMA_HWA_SetDestAddr(pDma, (uint8_t)eChannel, (uint32_t)pChnCfg->pDestBuffer);
DMA_HWA_SetPriority(pDma, (uint8_t)eChannel, pChnCfg->u8ChannelPriority);
if ((pChnCfg->bSrcCircularBufferEn == true) && (pChnCfg->bDestCircularBufferEn == true))
{
DMA_HWA_SetSrcDataSize(pDma, (uint8_t)eChannel, pChnCfg->eSrcDataSize);
DMA_HWA_SetSrcModulo(pDma, (uint8_t)eChannel, u8SrcMod);
DMA_HWA_SetDestDataSize(pDma, (uint8_t)eChannel, pChnCfg->eDestDataSize);
DMA_HWA_SetDestModulo(pDma, (uint8_t)eChannel, u8DestMod);
}
else if (pChnCfg->bSrcCircularBufferEn == true)
{
DMA_HWA_SetSrcDataSize(pDma, (uint8_t)eChannel, pChnCfg->eSrcDataSize);
DMA_HWA_SetSrcModulo(pDma, (uint8_t)eChannel, u8SrcMod);
DMA_HWA_SetDestDataSize(pDma, (uint8_t)eChannel, pChnCfg->eDestDataSize);
DMA_HWA_SetDestModulo(pDma, (uint8_t)eChannel, 0U);
}
else if (pChnCfg->bDestCircularBufferEn == true)
{
DMA_HWA_SetSrcDataSize(pDma, (uint8_t)eChannel, pChnCfg->eSrcDataSize);
DMA_HWA_SetSrcModulo(pDma, (uint8_t)eChannel, 0U);
DMA_HWA_SetDestDataSize(pDma, (uint8_t)eChannel, pChnCfg->eDestDataSize);
DMA_HWA_SetDestModulo(pDma, (uint8_t)eChannel, u8DestMod);
}
else
{
DMA_HWA_SetSrcDataSize(pDma, (uint8_t)eChannel, pChnCfg->eSrcDataSize);
DMA_HWA_SetSrcModulo(pDma, (uint8_t)eChannel, 0U);
DMA_HWA_SetDestDataSize(pDma, (uint8_t)eChannel, pChnCfg->eDestDataSize);
DMA_HWA_SetDestModulo(pDma, (uint8_t)eChannel, 0U);
}
if (bUseSrcDumo == true)
{
u16Sumo = (uint16_t)((pChnCfg->u32SrcCircBufferSize / u16SrcDataOffset - 1U) * u16SrcDataOffset);
}
if (bUseDestDumo == true)
{
u16Dumo = (uint16_t)((pChnCfg->u32DestCircBufferSize / u16DestDataOffset - 1U) * u16DestDataOffset);
}
if ((bUseSrcDumo == true) || (bUseDestDumo == true))
{
DMA_HWA_SetUnalignModulo(pDma, u8DumoIndex, u16Sumo, u16Dumo);
DMA_HWA_SetUnalignModuloEnableFlag(pDma, (uint8_t)eChannel, bUseSrcDumo, bUseDestDumo);
DMA_HWA_SetUnalignModuloSel(pDma, (uint8_t)eChannel, u8DumoIndex);
}
DMA_HWA_SetAutoDisableReuqestEnableFlag(pDma, (uint8_t)eChannel, pChnCfg->bAutoStop);
DMA_HWA_SetSrcOffset(pDma, (uint8_t)eChannel, (int16_t)u16SrcDataOffset);
DMA_HWA_SetDestOffset(pDma, (uint8_t)eChannel, (int16_t)u16DestDataOffset);
DMA_HWA_SetInnerLoopOffset(pDma, (uint8_t)eChannel, pChnCfg->bSrcBlockOffsetEn, pChnCfg->bDestBlockOffsetEn,
pChnCfg->s32BlockOffset);
DMA_HWA_SetInnerLoopSize(pDma, (uint8_t)eChannel, pChnCfg->u32BlockSize);
if ((pChnCfg->u16BlockCount > 1U) && (true == pChnCfg->bInnerChannelChain))
{
DMA_HWA_SetChannelToChannelTrig(pDma, (uint8_t)eChannel, true, (uint8_t)eChannel);
DMA_HWA_SetLoopCount(pDma, (uint8_t)eChannel, pChnCfg->u16BlockCount);
}
else
{
DMA_HWA_SetChannelToChannelTrig(pDma, (uint8_t)eChannel, false, 0U);
DMA_HWA_SetLoopCount(pDma, (uint8_t)eChannel, pChnCfg->u16BlockCount);
}
DMA_HWA_SetSrcLastAddrAdjustment(pDma, (uint8_t)eChannel, s32SrcLastOffset);
DMA_HWA_SetDestLastAddrAdjustment(pDma, (uint8_t)eChannel, s32DestLastOffset);
if (pChnCfg->eTriggerSrc == DMA_REQ_DISABLED)
{
DMAMUX_HWA_SetRequestSource(pDmamux, (uint8_t)eChannel, false, DMA_REQ_DISABLED);
}
else
{
DMAMUX_HWA_SetRequestSource(pDmamux, (uint8_t)eChannel, true, pChnCfg->eTriggerSrc);
}
}
return ret;
}
void DMA_DeinitChannel(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
DEV_ASSERT(eChannel < DMA_CHANNEL_MAX);
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
uint8_t u8DumoIndex;
for (u8DumoIndex = 0U; u8DumoIndex < DMA_DUMO_COUNT; u8DumoIndex++)
{
if (s_aDmaDumoUsedStatus[u8DumoIndex] == (uint8_t)eChannel)
{
s_aDmaDumoUsedStatus[u8DumoIndex] = DMA_CHANNEL_INVALID;
DMA_HWA_SetUnalignModulo(pDma, u8DumoIndex, 0U, 0U);
}
}
DMA_HWA_SetUnalignModuloEnableFlag(pDma, (uint8_t)eChannel, false, false);
DMA_HWA_DisableChannelErrorInterrupt(pDma, (uint8_t)eChannel);
DMA_HWA_DisableChannelRequest(pDma, (uint8_t)eChannel);
DMA_HWA_ClearChannelDoneStatus(pDma, (uint8_t)eChannel);
DMA_HWA_ClearChannelErrorFlag(pDma, (uint8_t)eChannel);
DMA_HWA_ClearChannelInterruptFlag(pDma, (uint8_t)eChannel);
DMA_HWA_SetSrcAddr(pDma, (uint8_t)eChannel, 0U);
DMA_HWA_SetSrcOffset(pDma, (uint8_t)eChannel, 0);
DMA_HWA_SetSrcLastAddrAdjustment(pDma, (uint8_t)eChannel, 0);
DMA_HWA_SetDestAddr(pDma, (uint8_t)eChannel, 0U);
DMA_HWA_SetDestOffset(pDma, (uint8_t)eChannel, 0);
DMA_HWA_SetDestLastAddrAdjustment(pDma, (uint8_t)eChannel, 0);
DMA_HWA_SetSrcDataSize(pDma, (uint8_t)eChannel, DMA_TRANSFER_SIZE_1B);
DMA_HWA_SetSrcModulo(pDma, (uint8_t)eChannel, 0U);
DMA_HWA_SetDestDataSize(pDma, (uint8_t)eChannel, DMA_TRANSFER_SIZE_1B);
DMA_HWA_SetDestModulo(pDma, (uint8_t)eChannel, 0U);
DMA_HWA_SetInnerLoopOffset(pDma, (uint8_t)eChannel, false, false, 0);
DMA_HWA_SetInnerLoopSize(pDma, (uint8_t)eChannel, 0U);
DMA_HWA_SetChannelControlStatus(pDma, (uint8_t)eChannel, 0U);
DMA_HWA_SetChannelToChannelTrig(pDma, (uint8_t)eChannel, false, 0U);
DMA_HWA_SetLoopCount(pDma, (uint8_t)eChannel, 0U);
}
void DMA_InitChannelInterrupt(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel, const DMA_InterruptCfgType *const pInterruptCfg)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
DEV_ASSERT(eChannel < DMA_CHANNEL_MAX);
DEV_ASSERT(pInterruptCfg != NULL);
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
if (pInterruptCfg->bTransferCompleteIntEn)
{
s_dmaTransferCompleteNotify[eDma_Instance][eChannel] = pInterruptCfg->pTransferCompleteNotify;
DMA_HWA_EnableTransferCompleteInterrupt(pDma, (uint8_t)eChannel);
//IntMgr_EnableInterrupt(DMA_GetChannelIRQn(eChannel));
}
else
{
DMA_HWA_DisableTransferCompleteInterrupt(pDma, (uint8_t)eChannel);
s_dmaTransferCompleteNotify[eDma_Instance][eChannel] = NULL;
//IntMgr_DisableInterrupt(DMA_GetChannelIRQn(eChannel));
}
if (pInterruptCfg->bTransferErrorIntEn)
{
s_dmaTransferErrorNotify[eDma_Instance][eChannel] = pInterruptCfg->pTransferErrorNotify;
DMA_HWA_EnableChannelErrorInterrupt(pDma, (uint8_t)eChannel);
//IntMgr_EnableInterrupt(DMA_error_IRQn);
}
else
{
DMA_HWA_DisableChannelErrorInterrupt(pDma, (uint8_t)eChannel);
s_dmaTransferErrorNotify[eDma_Instance][eChannel] = NULL;
//if (DMA_HWA_GetAllChannelErrorInterruptEnableFlag(pDma) == 0U)
//{
//IntMgr_DisableInterrupt(DMA_error_IRQn);
//}
}
}
void DMA_ConfigChainedTransfer(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel,
const DMA_ChainTransferType *const pChainTransferCfg)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
DEV_ASSERT(eChannel < DMA_CHANNEL_MAX);
DEV_ASSERT(pChainTransferCfg != NULL);
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
DMA_HWA_SetOuterLoopTrigEnableFlag(pDma, (uint8_t)eChannel, pChainTransferCfg->bChanelChainEn);
DMA_HWA_SetOuterLoopTrigChannel(pDma, (uint8_t)eChannel, pChainTransferCfg->u8ChainedChannel);
}
DMA_StatusType DMA_ModifyAddress(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel,
const volatile void *pSrcBuffer, const volatile void *pDestBuffer)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
DEV_ASSERT(eChannel < DMA_CHANNEL_MAX);
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
DMA_StatusType ret;
if (DMA_GetChannelStatus(eDma_Instance, eChannel) == DMA_RUNNING_STATUS_IDLE)
{
if (pSrcBuffer != NULL)
{
DMA_HWA_SetSrcAddr(pDma, (uint8_t)eChannel, (uint32_t)pSrcBuffer);
}
if (pDestBuffer != NULL)
{
DMA_HWA_SetDestAddr(pDma, (uint8_t)eChannel, (uint32_t)pDestBuffer);
}
ret = DMA_STATUS_SUCCESS;
}
else
{
ret = DMA_STATUS_BUSY;
}
return ret;
}
void DMA_StartChannel(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
DEV_ASSERT(eChannel < DMA_CHANNEL_MAX);
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
if (DMA_GetChannelRequestSrc(eDma_Instance, eChannel) == DMA_REQ_DISABLED)
{
DMA_HWA_SetChannelStart(pDma, (uint8_t)eChannel);
}
else
{
DMA_HWA_EnableChannelRequest(pDma, (uint8_t)eChannel);
}
}
void DMA_StopChannel(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
DEV_ASSERT(eChannel < DMA_CHANNEL_MAX);
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
DMA_HWA_DisableChannelRequest(pDma, (uint8_t)eChannel);
}
DMA_StatusType DMA_CancelTransfer(const DMA_InstanceType eDma_Instance, bool bGenerateErr)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
DMA_StatusType eRet;
uint32_t u32TimeOut = 15000000U;
if (bGenerateErr)
{
DMA_HWA_ErrorCancelTransfer(pDma);
while ((DMA_HWA_GetErrorCancelTransferStatus(pDma) == true) && (u32TimeOut != 0U))
{
u32TimeOut--;
}
}
else
{
DMA_HWA_CancelTransfer(pDma);
while ((DMA_HWA_GetCancelTransferStatus(pDma) == true) && (u32TimeOut != 0U))
{
u32TimeOut--;
}
}
if (u32TimeOut != 0U)
{
eRet = DMA_STATUS_SUCCESS;
}
else
{
eRet = DMA_STATUS_TIMEOUT;
}
return eRet;
}
DMA_RequestSourceType DMA_GetChannelRequestSrc(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
DEV_ASSERT(eChannel < DMA_CHANNEL_MAX);
DMAMUX_Type * aDmamux[] = DMAMUX_BASE_PTRS;
DMAMUX_Type *const pDmamux = aDmamux[eDma_Instance];
DMA_RequestSourceType eReqSrc = DMAMUX_HWA_GetRequestSource(pDmamux, (uint8_t)eChannel);
return eReqSrc;
}
DMA_RunningStatusType DMA_GetStatus(const DMA_InstanceType eDma_Instance)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
DMA_RunningStatusType eDMAStatus = DMA_HWA_GetStatus(pDma);
return eDMAStatus;
}
DMA_RunningStatusType DMA_GetChannelStatus(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel)
{
DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX);
DEV_ASSERT(eChannel < DMA_CHANNEL_MAX);
DMA_Type * aDma[] = DMA_BASE_PTRS;
DMA_Type *const pDma = aDma[eDma_Instance];
DMA_RunningStatusType eChannelStatus = DMA_HWA_GetChannelActiveStatus(pDma, (uint8_t)eChannel);
return eChannelStatus;
}

38
Src/fc7xxx_driver_dsp.c Normal file
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@ -0,0 +1,38 @@
/**
* @file fc7xxx_driver_dsp.c
* @author Flagchip051
* @brief FC4xxx DSP driver type definition and API
* @version 0.1.0
* @date 2022-04-23
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022-04-23 Flagchip054 N/A First version for FC7300
******************************************************************************** */
#include "fc7xxx_driver_dsp.h"
/*
* @details @verbatim
If only want use FPU,
1) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard) -> FPU Type set to "fpv5-sp-d16"
2) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> GNU Arm Cross C Compiler -> Preprocessor -> Defined symbols(-D) -> Add "__FPU_PRESENT=1" (without ")
3) and call FPU_Enable to enable FPU at the beginning of program.
If want to use DSP,
1) configure FCIDE to enable FPU compiler support, Properties -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard)
2) add MACRO "DRIVER_CM7_DSP_ENABLE" in FCIDE Properties -> C/C++ General -> Paths and Symbols -> Symbols -> GNU C and GNU C++ and Assembly
3) add Include Path to project Properties -> C/C++ General -> Paths and Symbols -> Includes -> GNU C and GNU C++ and Assembly:
../../../../../../Template/Device/CMSIS5_590/DSP/Include
../../../../../../Template/Device/CMSIS5_590/Core/Include
../../../../../../Template/Device/CMSIS5_590/DSP/PrivateInclude
4) and call FPU_Enable to enable FPU at the beginning of program.
@endverbatim
*/

217
Src/fc7xxx_driver_eim.c Normal file
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/**
* @file fc7xxx_driver_eim.c
* @author Flagchip
* @brief FC7xxx EIM driver type definition and API
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_eim.h"
#include "fc7xxx_driver_pcc.h"
/******************* Local Variables ***********************/
/******************* Local Function Prototype **************/
/****************** Global Functions ***********************/
/**
* @brief Initialize EIM function
*
* @param pEimInitCfg Initialization structure of EIM
* @return return 0: initialize successful. 1: invalid parameter
*/
EIM_RetType EIM_Init(const EIM_InitType *pEimInitCfg)
{
EIM_RetType eRet = EIM_STATUS_SUCCESS;
uint32_t u32CtrlVal = 0U;
uint32_t u32BusVal = 0U;
uint8_t u8BusChn;
if (NULL == pEimInitCfg)
{
eRet = EIM_STATUS_PARAM_INVALID;
}
else
{
u32CtrlVal |= EIM_CTRL_REG_BUS_SEL(pEimInitCfg->u8BusSelIdx);
u8BusChn = (uint8_t)pEimInitCfg->u8BusSelIdx;
if(pEimInitCfg->u8Attreenable != 0U)
{
if((pEimInitCfg->u8EimChn>=1U) && (pEimInitCfg->u8EimChn<=23U))
{
u32CtrlVal |= EIM_CTRL_REG_ATTREIE(1U);
u32BusVal |= EIM_BUS_REG_ATTR(pEimInitCfg->u8AttrPosition);
}
else
{
eRet = EIM_STATUS_PARAM_INVALID;
}
}
if(pEimInitCfg->u8Addreenable != 0U)
{
if((pEimInitCfg->u8EimChn>=1U) && (pEimInitCfg->u8EimChn<=23U))
{
u32CtrlVal |= EIM_CTRL_REG_ADDREIE(1U);
u32BusVal |= EIM_BUS_REG_ADDR(pEimInitCfg->u8AddrePosition);
}
else
{
eRet = EIM_STATUS_PARAM_INVALID;
}
}
if(pEimInitCfg->u8Data0enable != 0U)
{
u32CtrlVal |= EIM_CTRL_REG_DATA0EIE(1U);
u32BusVal |= EIM_BUS_REG_DATA0(pEimInitCfg->u8Data0Val);
}
if(pEimInitCfg->u8Data1enable != 0U)
{
u32CtrlVal |= EIM_CTRL_REG_DATA1EIE(1U);
u32BusVal |= EIM_BUS_REG_DATA1(pEimInitCfg->u8Data1Val);
}
EIM_HWA_Set_BUSRegn(u8BusChn,u32BusVal);
EIM_HWA_Set_CtrlRegn((uint8_t)pEimInitCfg->u8EimChn,u32CtrlVal);
EIM_HWA_EnableGlobalErrorInjection();
}
return eRet;
}
/**
* @brief Initialize EIM function
*
* @param eEimChannel channel want to set
* @param eDwpType Cpu to use
* @param bLockStatus Lock the cpu control settings
* @return Set operation success/failed
*/
EIM_RetType EIM_SetDwpMode(const EIM_ChannelType eEimChannel, const EIM_DWPType eDwpType, bool bLockStatus)
{
uint8_t u8ChnIdx = (uint8_t)eEimChannel;
EIM_RetType eRet = EIM_STATUS_SUCCESS;
if (0U == EIM_HWA_GetCtrlDWPLockStatus(u8ChnIdx))
{
EIM_HWA_Set_CtrlLockMode((uint8_t)eEimChannel,(uint8_t)eDwpType);
if(true == bLockStatus)
{
/* Lock the dwp mode until reset */
EIM_HWA_CtrlRegnWritePermit(u8ChnIdx);
}
}
else
{
eRet = EIM_STATUS_PARAM_INVALID;
}
return eRet;
}
/**
* @brief Enable CPU lockstep monitor
*
* @param eEimCpuType EIM_CPU0_LOCKSTEP or EIM_CPU1_LOCKSTEP
* @param eMonitorType EIM_MONITOR0 or EIM_MONITOR1
*/
void EIM_CpuLockStepMonitorSet_MonSet(const EIM_CPU_ChnType eEimCpuType,const EIM_MONType eMonitorType)
{
uint32_t u32val = 0U;
u32val = EIM_HWA_Get_CPULockstep((uint8_t)eEimCpuType);
if(eMonitorType == EIM_MONITOR0)
{
u32val &= 0xFFFFFFFD;//clear mon0 clr
u32val |= EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET(1U);
}
if(eMonitorType == EIM_MONITOR1)
{
u32val &= 0xFFFFFFFE;//clear mon1 clr
u32val |= EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET(1U);
}
EIM_HWA_Set_CPULockstep((uint8_t)eEimCpuType, u32val);
}
/**
* @brief Clear CPU lockstep monitor
*
* @param eEimCpuType EIM_CPU0_LOCKSTEP or EIM_CPU1_LOCKSTEP
* @param eMonitorType EIM_MONITOR0 or EIM_MONITOR1
*/
void EIM_CpuLockStepMonitorSet_MonClr(const EIM_CPU_ChnType eEimCpuType,const EIM_MONType eMonitorType)
{
uint32_t u32val = 0U;
u32val = EIM_HWA_Get_CPULockstep((uint8_t)eEimCpuType);
if(eMonitorType == EIM_MONITOR0)
{
u32val |= EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR(1U);
}
if(eMonitorType == EIM_MONITOR1)
{
u32val |= EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR(1U);
}
EIM_HWA_Set_CPULockstep((uint8_t)eEimCpuType, u32val);
}
/**
* @brief Clean CPU lockstep monitor bit
*
* @param eEimCpuType EIM_CPU0_LOCKSTEP or EIM_CPU1_LOCKSTEP
* @param eMonitorType EIM_MONITOR0 or EIM_MONITOR1
*/
void EIM_CpuLockStepMonitorClr(const EIM_CPU_ChnType eEimCpuType, const EIM_MONType eMonitorType)
{
uint32_t u32val = 0U;
u32val = EIM_HWA_Get_CPULockstep((uint8_t)eEimCpuType);
if(eMonitorType == EIM_MONITOR0)
{
u32val &= 0xFFFFFFF5;//clear mon0 clr
}
if(eMonitorType == EIM_MONITOR1)
{
u32val &= 0xFFFFFFFA;//clear mon1 clr
}
EIM_HWA_Set_CPULockstep((uint8_t)eEimCpuType, u32val);
}
/**
* @brief Deinin EIM function
*
*/
void Eim_Deinit(void)
{
uint8_t u8loop;
EIM_HWA_DisableGlobalErrorInjection();
for (u8loop = 0U; u8loop < EIM_CTRL_REG_COUNT; u8loop++)
{
EIM_HWA_Set_CtrlRegn(u8loop, 0U);
}
EIM_HWA_Set_CPULockstep(EIM_CPU0_LOCKSTEP, 0U);
EIM_HWA_Set_CPULockstep(EIM_DMA0_LOCKSTEP, 0U);
for (u8loop = 0U; u8loop < EIM_BUS_REG_COUNT; u8loop++)
{
EIM_HWA_Set_BUSRegn(u8loop, 0U);
}
}

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/**
* @file fc7xxx_driver_erm.c
* @author Flagchip
* @brief FC7xxx ERM driver type definition and API
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_erm.h"
#include "fc7xxx_driver_pcc.h"
#include "interrupt_manager.h"
/* ############################## Local Variables ################################ */
/**
* @brief Erm user defined interrupt function
* */
static ERM_InterruptCallBackType s_pErmNotifyPtr = NULL;
/* ################################################################################## */
/* ########################### Global Prototype Functions ########################### */
void ERM_fault_IRQHandler(void);
/* ################################################################################## */
/* ################################ Local Functions ################################# */
/**
* @brief Initialize ERM function
*
* @param pErmInt_cfg Initialization structure of ERM
* @return return 0: initialize successful. 1: invalid parameter
*/
ERM_RetType Erm_Init(const ERM_MemorytInitType *pErmInt_cfg)
{
ERM_RetType eRet = ERM_STATUS_SUCCESS;
uint32_t u32ErmCrVal = 0U;
ERM_ClearSRnRegister();
if (NULL == pErmInt_cfg)
{
eRet = ERM_STATUS_PARAM_INVALID;
}
else
{
if(pErmInt_cfg->u8ErmEnable != 0U)
{
if ((uint32_t)pErmInt_cfg->eChannel < 8U)
{
u32ErmCrVal |= (uint32_t)((uint32_t)pErmInt_cfg->eInt << (30UL - (uint32)pErmInt_cfg->eChannel*4U));
ERM_HWA_Set_CRn(0, u32ErmCrVal);
}
else if (((uint32_t)pErmInt_cfg->eChannel >= 8U) && ((uint32_t)pErmInt_cfg->eChannel < 16U))
{
u32ErmCrVal |= (uint32_t)((uint32_t)pErmInt_cfg->eInt << (62UL - (uint32)pErmInt_cfg->eChannel*4U));
ERM_HWA_Set_CRn(1, u32ErmCrVal);
}
else if (((uint32_t)pErmInt_cfg->eChannel >= 16U) && ((uint32_t)pErmInt_cfg->eChannel < 24U))
{
u32ErmCrVal |= (uint32_t)((uint32_t)pErmInt_cfg->eInt << (94UL - (uint32)pErmInt_cfg->eChannel*4U));
ERM_HWA_Set_CRn(2, u32ErmCrVal);
}
else if (((uint32_t)pErmInt_cfg->eChannel >= 24U) && ((uint32_t)pErmInt_cfg->eChannel < 32U))
{
u32ErmCrVal |= (uint32_t)((uint32_t)pErmInt_cfg->eInt << (126UL - (uint32)pErmInt_cfg->eChannel*4U));
ERM_HWA_Set_CRn(3, u32ErmCrVal);
}
else
{
eRet = ERM_STATUS_PARAM_INVALID;
}
if(eRet == ERM_STATUS_SUCCESS)
{
s_pErmNotifyPtr = pErmInt_cfg->pIsrNotify;
}
}
}
return eRet;
}
/**
* @brief De-initialize ERM function
* Restore the ERM instance to its reset state
*/
void Erm_DeInit(void)
{
uint8_t u8loop;
for (u8loop = 0U; u8loop < 4U; u8loop++)
{
ERM_HWA_Set_CRn(u8loop, 0x0U);
ERM_HWA_Set_SRn(u8loop, 0x0U);
}
}
/**
* @brief ERM Clear SR0 register.
*
* This function Clear ERM SR0 register.
*/
void ERM_ClearSRnRegister(void)
{
uint8_t u8loop;
for (u8loop = 0U; u8loop < 4U; u8loop++)
{
ERM_HWA_Set_SRn(u8loop, ERM_SR_MASK);
}
}
/**
* @brief ERM read SRn register.
*
* This function Clear ERM SRn register.
* @param u8Index the SRn channel
*/
uint32_t ERM_ReadSRnVal(uint8_t u8Index)
{
uint32_t u32Val;
u32Val = ERM_HWA_Get_SRn(u8Index);
return u32Val;
}
/**
* @brief ERM clear CRn register.
*
* This function Clear ERM CRn register.
* @param u8Index of the CRn channel
*/
void ERM_ClearCRnVal(uint8_t u8Index)
{
ERM_HWA_Set_CRn(u8Index, 0UL);
}
/**
* @brief ERM clear SRn register.
*
* This function Clear ERM SR0 register.
* @param u8Index the SRn channel
*/
uint32_t ERM_ClearSRnVal(uint8_t u8Index)
{
uint32_t u32Val;
u32Val = ERM_HWA_Get_SRn(u8Index);
ERM_HWA_Set_SRn(u8Index, u32Val);
return u32Val;
}
/**
* @brief ERM interrupt function
*/
void ERM_fault_IRQHandler(void)
{
if(s_pErmNotifyPtr != NULL)
{
s_pErmNotifyPtr();
}
}
/**
* @brief ERM Read EARn address.
* @param eChannel The channel type
* @return u32Address The error address
*/
/*
uint32_t ERM_ReadAddress(ERM_channelType eChannel)
{
uint32_t u32Address = 0U;
u32Address = ERM_HWA_GetEARn(eChannel);
return u32Address;
}*/

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/**
* @file fc7xxx_driver_fciic.c
* @author Flagchip
* @brief FC7xxx FCIIC driver type definition and API
* @version 0.1.0
* @date 2022-12-31
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024/1/10 qxw0095 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_fciic.h"
#include "interrupt_manager.h"
#include "stdarg.h"
#include "stdio.h"
#include "string.h"
#include "stdlib.h"
/* #define FCIIC_RX_FIFO */
/* iic instance value */
static FCIIC_Type *const s_aFCIIC_InstanceTable[FCIIC_INSTANCE_COUNT] = FCIIC_BASE_PTRS;
/* store notify callback function point */
static FCIIC_ErrorInterrupt_CallBackType s_aFCIIC_ErrorNotifyTable[FCIIC_INSTANCE_COUNT] = {NULL};
static FCIIC_RxInterrupt_CallBackType s_aFCIIC_RxNotifyTable[FCIIC_INSTANCE_COUNT] = {NULL};
#ifdef FCIIC_RX_ALL_POLLING
/* check every pFciic instance whether is used */
static uint8_t s_aFCIIC_IicMasterUsed[FCIIC_INSTANCE_COUNT];
static uint8_t s_aFCIIC_IicSlaveUsed[FCIIC_INSTANCE_COUNT];
#endif
/* ################################################################################## */
/* ########################### Local Prototype Functions ############################ */
#if 0
static void CheckAndClear(FCIIC_Type *pFciic);
#endif
static void FCIIC_LL_MasterIRQnHandler(uint8_t u8IicIndex);
static void FCIIC_LL_SlaveIRQnHandler(uint8_t u8IicIndex);
static uint8_t FCIIC_Init_Master(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg);
static uint8_t FCIIC_Init_Slave(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg);
/* ################################################################################## */
/* ########################### Global Prototype Functions ########################### */
void FCIIC0_IRQHandler(void);
void FCIIC1_IRQHandler(void);
/* ################################################################################## */
/* ################################ Local Functions ################################# */
#if 0
static void CheckAndClear(FCIIC_Type *pFciic)
{
FCIIC_Master_HwA_CheckClearStatus(pFciic, FCIIC_MSR_EPF_STATUS);
FCIIC_Master_HwA_CheckClearStatus(pFciic, FCIIC_MSR_SDF_STATUS);
FCIIC_Master_HwA_CheckClearStatus(pFciic, FCIIC_MSR_NDF_STATUS);
FCIIC_Master_HwA_CheckClearStatus(pFciic, FCIIC_MSR_FEF_STATUS);
FCIIC_Master_HwA_CheckClearStatus(pFciic, FCIIC_MSR_ALF_STATUS);
}
#endif
/***************************************************
* FCIIC_LL_MasterIRQnHandler
* @detail: Iic n interrupt process
*
* param in : u8IicIndex, 0,1,2,3
* param out: none
*
* return : none
* ************************************************/
static void FCIIC_LL_MasterIRQnHandler(uint8_t u8IicIndex)
{
/* uint8_t iic_status; */
uint8_t u8RetVal;
FCIIC_RxDataType pRxData;
uint32_t u32ErrorValue;
/* check pFciic receive data */
u8RetVal = FCIIC_Master_Receive(u8IicIndex, &pRxData);
if ((s_aFCIIC_RxNotifyTable[u8IicIndex] != NULL) && (u8RetVal == 0U))
{
s_aFCIIC_RxNotifyTable[u8IicIndex](u8IicIndex, &pRxData);
}
/* check error */
u32ErrorValue = FCIIC_Master_GetError(u8IicIndex);
if ((u32ErrorValue != 0U) && (s_aFCIIC_ErrorNotifyTable[u8IicIndex] != NULL))
{
s_aFCIIC_ErrorNotifyTable[u8IicIndex](u8IicIndex, 1U, u32ErrorValue);
FCIIC_Master_ClrError(u8IicIndex);
}
}
/***************************************************
* FCIIC_LL_SlaveIRQnHandler
* @detail: Iic n interrupt process
*
* param in : u8IicIndex, 0,1,2,3
* param out: none
*
* return : none
* ************************************************/
static void FCIIC_LL_SlaveIRQnHandler(uint8_t u8IicIndex)
{
/* uint8_t iic_status; */
uint8_t u8RetVal;
FCIIC_RxDataType pRxData;
uint32_t u32ErrorValue;
/* check pFciic receive data */
u8RetVal = FCIIC_Slave_Receive(u8IicIndex, &pRxData);
if ((s_aFCIIC_RxNotifyTable[u8IicIndex] != NULL) && (u8RetVal == 0U))
{
s_aFCIIC_RxNotifyTable[u8IicIndex](u8IicIndex, &pRxData);
}
/* check error */
u32ErrorValue = FCIIC_Slave_GetError(u8IicIndex);
if ((u32ErrorValue != 0U) && (s_aFCIIC_ErrorNotifyTable[u8IicIndex] != NULL))
{
s_aFCIIC_ErrorNotifyTable[u8IicIndex](u8IicIndex, 0U, u32ErrorValue);
FCIIC_Slave_ClrError(u8IicIndex);
}
}
/***************************************************
* FCIIC_Init_Master
* @detail: Iic device master mode initial
*
* param in : pInitCfg, pFciic initial config parameters
* structure address
* param out: none
*
* return : 0 is ok, others are not ok
* ************************************************/
static uint8_t FCIIC_Init_Master(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg)
{
uint32_t u32TempMcr, u32TempMder, u32TempMcfgr0, u32TempMcfgr1, u32TempMcfgr2, u32TempMcfgr3, u32TempMccr0;
uint32_t u32TempMFCR;
FCIIC_Type *pFciic;
uint32_t u32ClkSrcHz;
uint32_t u32FreqDeltaCur, u32FreqDeltaOld;
uint32_t u32FreqDesired, u32FreqCur;
uint32_t u32Prescale, u8PrescaleTemp;
uint32_t u32CLKHI, u32CLKHITemp;
uint32_t u32CLKLO, u32CLKLOTemp;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
u32ClkSrcHz = pInitCfg->u32ClkSrcHz;
u32FreqDesired = pInitCfg->u32Frequency;
u32FreqDeltaOld = u32FreqDesired;
/* SCL_LATENCY is defined as ROUNDDOWN ((2 + FILTSCL + SCL_RISETIME) / (2 ^ PRESCALE)) */
/* CLKLO: Minimum value is 0x3 */
/* CLKHI: Minimum value is 0x1 */
/* SCL clock period: (CLKHI + CLKLO + 2 + SCL_LATENCY) <20><> (2 ^ PRESCALE) <20><> function clock period */
for(u32CLKHITemp=1U; (u32CLKHITemp < 63U); u32CLKHITemp++)
{
for(u32CLKLOTemp=3U; (u32CLKLOTemp < 63U); u32CLKLOTemp++)
{
/* get the linear prescale */
for (u8PrescaleTemp = 0U; u8PrescaleTemp < 8U; u8PrescaleTemp++)
{
u32FreqCur = u32ClkSrcHz / Fc_Power(2U, (uint32_t)u8PrescaleTemp)/(u32CLKHITemp+u32CLKLOTemp+2U);
/* If the current frequency is less than the desired frequency,
* compare the delta with the previous one and select the parameter with the smallest delta
* */
if(u32FreqCur <= u32FreqDesired)
{
u32FreqDeltaCur = u32FreqDesired - u32FreqCur;
if (u32FreqDeltaCur < u32FreqDeltaOld)
{
u32FreqDeltaOld = u32FreqDeltaCur;
u32Prescale = u8PrescaleTemp;
u32CLKHI = u32CLKHITemp;
u32CLKLO = u32CLKLOTemp;
}
break;
}
}
if(u32FreqDeltaOld == 0U)
{
break;
}
}
if(u32FreqDeltaOld==0U)
{
break;
}
}
u32TempMcr = FCIIC_MCR_RRF(0U) |
FCIIC_MCR_RTF(0U) |
FCIIC_MCR_DBGEN(0U) |
FCIIC_MCR_RST(0U) |
FCIIC_MCR_MEN(1U); /* master enable */
u32TempMder = FCIIC_MDER_RDDE(pInitCfg->bEnDma) | /* enable receive dma */
FCIIC_MDER_TDDE(pInitCfg->bEnDma); /* enable transmit dma */
u32TempMcfgr0 = FCIIC_MCFGR0_RDMO(0U) |
FCIIC_MCFGR0_TRGEN(0U);
u32TempMcfgr1 = FCIIC_MCFGR1_PINCFG(0U) | /* 0=open drain; 1=push-pull mode */
FCIIC_MCFGR1_MATCFG(0U) |
FCIIC_MCFGR1_TIMECFG(0U) |
FCIIC_MCFGR1_IGNACK(1U) |
FCIIC_MCFGR1_AUTOSTOP(0U) |
FCIIC_MCFGR1_PRESCALE(u32Prescale); /* Prescaler = 2^n */
u32TempMcfgr2 = FCIIC_MCFGR2_FILTSDA(0U) |
FCIIC_MCFGR2_FILTSCL(0U) |
FCIIC_MCFGR2_BUSIDLE(0U);
u32TempMcfgr3 = FCIIC_MCFGR3_PINLOW(0U);
u32TempMccr0 = FCIIC_MCCR_DATAVD(0x09U) |
FCIIC_MCCR_SETHOLD(0x13U) |
FCIIC_MCCR_CLKHI(u32CLKHI) |
FCIIC_MCCR_CLKLO(u32CLKLO); /* 0x09131327; */
u32TempMFCR = FCIIC_MFCR_TXWATER(pInitCfg->bTxFifoWMrk) | FCIIC_MFCR_RXWATER(pInitCfg->bRxFifoWMrk);
FCIIC_HWA_SetMder(pFciic, u32TempMder);
FCIIC_HWA_SetMCFGR0(pFciic, u32TempMcfgr0);
FCIIC_HWA_SetMCFGR1(pFciic, u32TempMcfgr1);
FCIIC_HWA_SetMCFGR2(pFciic, u32TempMcfgr2);
FCIIC_HWA_SetMCFGR3(pFciic, u32TempMcfgr3);
FCIIC_HWA_SetMCCR(pFciic, u32TempMccr0);
FCIIC_HWA_SetMFCR(pFciic, u32TempMFCR);
FCIIC_HWA_SetMcr(pFciic, u32TempMcr); /* | FCIIC_MCR_RRF_MASK | FCIIC_MCR_RTF_MASK | FCIIC_MCR_DBGEN_MASK | FCIIC_MCR_RST_MASK; */
#ifdef FCIIC_INIT_WAITRESET
u8RetVal = 1;
while (u8RetVal)
{
u8RetVal = (pFciic->MCR & FCIIC_MCR_RST_MASK) >> FCIIC_MCR_RST_SHIFT;
pFciic->MCR = u32TempMcr;
}
#endif
return 0U;
}
/***************************************************
* FCIIC_DeInit_Master
* @detail: Iic device master mode de-initial
*
* param in : u8IicIndex
* param out: none
*
* return : 0 is ok, others are not ok
* ************************************************/
static uint8_t FCIIC_DeInit_Master(uint8_t u8IicIndex)
{
uint32_t u32TempMcr, u32TempMder;
FCIIC_Type *pFciic;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
u32TempMcr = FCIIC_MCR_RRF(0U) |
FCIIC_MCR_RTF(0U) |
FCIIC_MCR_DBGEN(0U) |
FCIIC_MCR_RST(0U) |
FCIIC_MCR_MEN(0U); /* master enable */
u32TempMder = FCIIC_MDER_RDDE(0U) | /* disable receive dma */
FCIIC_MDER_TDDE(0U); /* disable transmit dma */
FCIIC_HWA_SetMder(pFciic, u32TempMder);
FCIIC_HWA_SetMcr(pFciic, u32TempMcr); /* | FCIIC_MCR_RRF_MASK | FCIIC_MCR_RTF_MASK | FCIIC_MCR_DBGEN_MASK | FCIIC_MCR_RST_MASK; */
return 0U;
}
/***************************************************
* FCIIC_Init_Slave
* @detail: Iic device master mode initial
*
* param in : u8IicIndex
* param out: none
*
* return : 0 is ok, others are not ok
* ************************************************/
static uint8_t FCIIC_Init_Slave(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg)
{
uint32_t u32TempScr, u32TempSder, u32TempScfgr1, u32TempScfgr2, u32TempSamr;
FCIIC_Type *pFciic;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
u32TempScr = FCIIC_SCR_FILTEN(0U) |
FCIIC_SCR_RST(0U) |
FCIIC_SCR_SEN(1U); /* slave enable */
u32TempSder = FCIIC_SDER_AVDE(pInitCfg->bEnDma) |
FCIIC_SDER_RDDE(pInitCfg->bEnDma) | /* enable receive dma */
FCIIC_SDER_TDDE(pInitCfg->bEnDma); /* enable transmit dma */
u32TempScfgr1 = FCIIC_SCFGR1_ADDRCFG(0U) | /* Address Configuration, 7bit */
FCIIC_SCFGR1_HSMEN(0U) |
FCIIC_SCFGR1_IGNACK(1U) |
FCIIC_SCFGR1_RXCFG(0U) |
FCIIC_SCFGR1_TXCFG(0U) |
FCIIC_SCFGR1_SAEN(0U) |
FCIIC_SCFGR1_GCEN(0U) |
FCIIC_SCFGR1_ACKSTALL(0U) |
FCIIC_SCFGR1_TXDSTALL(0U) |
FCIIC_SCFGR1_RXSTALL(0U) |
FCIIC_SCFGR1_ADRSTALL(0U);
u32TempScfgr2 = FCIIC_SCFGR2_FILTSDA(0U) |
FCIIC_SCFGR2_FILTSCL(0U) |
FCIIC_SCFGR2_DATAVD(0x09U) |
FCIIC_SCFGR2_CLKHOLD(1U);
u32TempSamr = FCIIC_SAMR_ADDR1(0U) |
FCIIC_SAMR_ADDR0(pInitCfg->u8SlaveAddr);
FCIIC_HWA_SetSDER(pFciic, u32TempSder);
FCIIC_HWA_SetSCFGR1(pFciic, u32TempScfgr1);
FCIIC_HWA_SetSCFGR2(pFciic, u32TempScfgr2);
FCIIC_HWA_SetSAMR(pFciic, u32TempSamr);
FCIIC_HWA_SetSCR(pFciic, u32TempScr);
return 0U;
}
/***************************************************
* FCIIC_DeInit_Slave
* @detail: Iic device master mode de-initial
*
* param in : pInitCfg, pFciic initial config parameters
* structure address
* param out: none
*
* return : 0 is ok, others are not ok
* ************************************************/
static uint8_t FCIIC_DeInit_Slave(uint8_t u8IicIndex)
{
uint32_t u32TempScr, u32TempSder;
FCIIC_Type *pFciic;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
u32TempScr = FCIIC_SCR_FILTEN(0U) |
FCIIC_SCR_RST(0U) |
FCIIC_SCR_SEN(0U); /* slave enable */
u32TempSder = FCIIC_SDER_AVDE(0U) |
FCIIC_SDER_RDDE(0U) | /* disable receive dma */
FCIIC_SDER_TDDE(0U); /* disable transmit dma */
FCIIC_HWA_SetSDER(pFciic, u32TempSder);
FCIIC_HWA_SetSCR(pFciic, u32TempScr);
return 0U;
}
/* ################################################################################## */
/* ################################ Global Functions ################################ */
/**
* \brief This Function is used to initial IIC instance
*
* \param u8IicIndex Iic Index, 0,1
* \param pInitCfg is the structure address of IIC initial configuration parameters, and it contains IIC instance
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Init(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg)
{
/* master mode */
if (pInitCfg->bMasterMode != 0U)
{
FCIIC_Init_Master(u8IicIndex, pInitCfg);
#ifdef FCIIC_RX_ALL_POLLING
s_aFCIIC_IicMasterUsed[u8IicIndex] = 1U;
s_aFCIIC_IicSlaveUsed[u8IicIndex] = 0U;
#endif
}
else /* slave mode */
{
FCIIC_Init_Slave(u8IicIndex, pInitCfg);
#ifdef FCIIC_RX_ALL_POLLING
s_aFCIIC_IicMasterUsed[u8IicIndex] = 0U;
s_aFCIIC_IicSlaveUsed[u8IicIndex] = 1U;
#endif
}
#if (defined(__ICCARM__))
u8IicIndex = u8IicIndex;
#elif defined __GNUC__
(void)u8IicIndex;
#endif
return 0U;
}
/**
* \brief This Function is used to de-initial IIC instance
*
* \param u8IicIndex Iic Index, 0,1
* \param pInitCfg is the structure address of IIC initial configuration parameters, bMaster should be set
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_DeInit(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg)
{
/* master mode */
if (pInitCfg->bMasterMode != 0U)
{
FCIIC_DeInit_Master(u8IicIndex);
#ifdef FCIIC_RX_ALL_POLLING
s_aFCIIC_IicMasterUsed[u8IicIndex] = 0U;
s_aFCIIC_IicSlaveUsed[u8IicIndex] = 0U;
#endif
}
else /* slave mode */
{
FCIIC_DeInit_Slave(u8IicIndex);
#ifdef FCIIC_RX_ALL_POLLING
s_aFCIIC_IicMasterUsed[u8IicIndex] = 0U;
s_aFCIIC_IicSlaveUsed[u8IicIndex] = 0U;
#endif
}
#if (defined(__ICCARM__))
u8IicIndex = u8IicIndex;
#elif defined __GNUC__
(void)u8IicIndex;
#endif
return 0U;
}
/**
* \brief This Function is used to configure IIC master interrupt
*
* \param u8IicIndex Iic Index, 0,1
* \param pIntCfg contains IIC instance and interrupt callback functions
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Master_SetInterrupt(uint8_t u8IicIndex, FCIIC_InterruptType *pIntCfg)
{
FCIIC_Type *pFciic;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
if ((pIntCfg->bEnErrorInterrupt != 0U) || (pIntCfg->bEnRxInterrupt != 0U))
{
/* enable global interrupt for pFciic */
IntMgr_EnableInterrupt((IRQn_Type)((uint8_t)((uint8_t)FCIIC0_IRQn + u8IicIndex)));
/* IntMag_ReplaceHandler(FCIIC0_IRQn+u8IicIndex,u8IicIndex==0?FCIIC0_IRQHandler:FCIIC1_IRQHandler); */
}
if (pIntCfg->bEnErrorInterrupt != 0U)
{
FCIIC_Master_HWA_EnableErrorInterrupt(pFciic);
s_aFCIIC_ErrorNotifyTable[u8IicIndex] = pIntCfg->pErrorNotify;
}
if (pIntCfg->bEnRxInterrupt != 0U)
{
/* pFciic->MIER |= FCIIC_MIER_RDIE_MASK; */
FCIIC_Master_HWA_EnableReceiveInterrupt(pFciic);
s_aFCIIC_RxNotifyTable[u8IicIndex] = pIntCfg->pRxNotify;
}
return 0U;
}
/**
* \brief This Function is used to transmit data in master mode
*
* \param u8IicIndex Iic Index, 0,1
* \param pTxData contains IIC instance and buffer address
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Master_Transmit(uint8_t u8IicIndex, FCIIC_TxDataType *pTxData)
{
uint8_t u8RetVal;
FCIIC_Type *pFciic;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
/* clear error flag */
/* CheckAndClear(pFciic); */
/* check tx data flag */
u8RetVal = FCIIC_Master_HWA_GetStatus(pFciic, FCIIC_MSR_TDF_STATUS);
/* pFciic->MSR |= FCIIC_MSR_FEF_MASK; */ /* clear fifo error error */
if (u8RetVal == 1U)
{
FCIIC_Master_HWA_Transmit(pFciic, pTxData->eCmd, pTxData->u8Data);
}
return (uint8_t)(1U >> u8RetVal);
}
/**
* \brief This Function is used to get master status
*
* \param u8IicIndex is IIC instance
* \param eStatus is status type enumeration
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Master_GetStatus(uint8_t u8IicIndex, FCIIC_MasterStatusType eStatus)
{
FCIIC_Type *pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
return (uint8_t)(1U >> FCIIC_Master_HWA_GetStatus(pFciic, eStatus));
}
/**
* \brief This Function is used to receive data when polling (not used when rx interrupt enabled) in master mode
*
* \param u8IicIndex Iic Index, 0,1
* \param pRxData contains IIC instance
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Master_Receive(uint8_t u8IicIndex, FCIIC_RxDataType *pRxData)
{
FCIIC_Type *pFciic;
uint8_t u8RetVal;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
/* CheckAndClear(pFciic); */
/* check receive flag */
u8RetVal = FCIIC_Master_HWA_GetStatus(pFciic, FCIIC_MSR_RDF_STATUS);
/* u8RetVal = (pFciic->MRDR & FCIIC_MRDR_RXEMPTY_MASK)>>FCIIC_MRDR_RXEMPTY_SHIFT; */
if (u8RetVal == 1U)
{
/* copy data */
pRxData->u8Data = FCIIC_Master_HWA_Receive(pFciic);
}
return (uint8_t)(1U >> u8RetVal);
}
/**
* \brief This Function is used to get master error value
*
* \param u8IicIndex Iic Index, 0,1
* \return error value
*/
uint32_t FCIIC_Master_GetError(uint8_t u8IicIndex)
{
FCIIC_Type *pFciic;
uint32_t u32RetVal;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
/* check receive flag */
u32RetVal = FCIIC_Master_HWA_GetErrorFlag(pFciic);
return u32RetVal;
}
/**
* \brief This Function is used to clear master error value
*
* \param u8IicIndex Iic Index, 0,1
*/
void FCIIC_Master_ClrError(uint8_t u8IicIndex)
{
FCIIC_Type *pFciic;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
/* clear receive flag */
FCIIC_Master_HWA_ClrErrorFlag(pFciic);
}
/**
* \brief This Function is used to configure IIC slave interrupt
*
* \param u8IicIndex Iic Index, 0,1
* \param pIntCfg contains IIC instance and interrupt callback functions
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Slave_SetInterrupt(uint8_t u8IicIndex, FCIIC_InterruptType *pIntCfg)
{
FCIIC_Type *pFciic;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
if ((pIntCfg->bEnErrorInterrupt != 0U) || (pIntCfg->bEnRxInterrupt != 0U))
{
/* enable global interrupt for pFciic */
IntMgr_EnableInterrupt((IRQn_Type)((uint8_t)((uint8_t)FCIIC0_IRQn + u8IicIndex)));
/* IntMag_ReplaceHandler(FCIIC0_IRQn+u8IicIndex,u8IicIndex==0?FCIIC0_IRQHandler:FCIIC1_IRQHandler); */
}
if (pIntCfg->bEnErrorInterrupt != 0U)
{
FCIIC_Slave_HWA_EnableErrorInterrupt(pFciic);
s_aFCIIC_ErrorNotifyTable[u8IicIndex] = pIntCfg->pErrorNotify;
}
if (pIntCfg->bEnRxInterrupt != 0U)
{
FCIIC_Slave_HWA_EnableReceiveInterrupt(pFciic);
s_aFCIIC_RxNotifyTable[u8IicIndex] = pIntCfg->pRxNotify;
}
return 0U;
}
/**
* \brief This Function is used to transmit data in slave mode
*
* \param u8IicIndex Iic Index, 0,1
* \param pTxData contains IIC instance and buffer address
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Slave_Transmit(uint8_t u8IicIndex, FCIIC_TxDataType *pTxData)
{
#ifdef FCIIC_TX_CHECK
uint8_t u8RetVal;
uint32_t u32TryTick;
uint32_t u32TryCount;
#endif
FCIIC_Type *pFciic;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
#ifdef FCIIC_TX_CHECK
/* u8RetVal = (pFciic->SSR & FCIIC_SSR_TDF_MASK)>> FCIIC_SSR_TDF_SHIFT; */
/* pFciic->SSR |= FCIIC_SSR_TREF_MASK; */ /* clear receive & transmit error error */
/* if(u8RetVal) */
{
#endif
FCIIC_Slave_HWA_Transmit(pFciic, pTxData->u8Data);
#ifdef FCIIC_TX_CHECK
/* after transmit completed, close TE */
/* u8RetVal = 0; */
/* u32TryCount = 0; */
/* while(u8RetVal==0 && u32TryCount++<100) */
/* { */
/* u8RetVal = (pFciic->SSR & FCIIC_SSR_TDF_MASK)>> FCIIC_SSR_TDF_SHIFT; */
/* u32TryTick = 0; */
/* while(u32TryTick++<100){} */
/* } */
}
#endif
return 0U;
}
/**
* \brief This Function is used to receive data when polling (not used when rx interrupt enabled) in slave mode
*
* \param u8IicIndex Iic Index, 0,1
* \param pRxData contains IIC instance and buffer address
* \return 0 is ok, others are not ok
*/
uint8_t FCIIC_Slave_Receive(uint8_t u8IicIndex, FCIIC_RxDataType *pRxData)
{
FCIIC_Type *pFciic;
uint8_t u8RetVal;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
/* check slave receive flag */
u8RetVal = FCIIC_Slave_HWA_GetStatus(pFciic, FCIIC_SSR_RDF_STATUS);
/* u8RetVal = (pFciic->MRDR & FCIIC_MRDR_RXEMPTY_MASK)>>FCIIC_MRDR_RXEMPTY_SHIFT; */
if (u8RetVal != 0U)
{
/* get received data */
pRxData->u8Data = FCIIC_Slave_HWA_Receive(pFciic);
}
return (uint8_t)(1U >> u8RetVal);
}
/**
* \brief This Function is used to get slave error value
*
* \param u8IicIndex Iic Index, 0,1
* \return error value
*/
uint32_t FCIIC_Slave_GetError(uint8_t u8IicIndex)
{
FCIIC_Type *pFciic;
uint32_t u32RetVal;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
/* check receive flag */
u32RetVal = FCIIC_Slave_HWA_GetErrorFlag(pFciic);
return u32RetVal;
}
/**
* \brief This Function is used to clear slave error value
*
* \param u8IicIndex Iic Index, 0,1
*/
void FCIIC_Slave_ClrError(uint8_t u8IicIndex)
{
FCIIC_Type *pFciic;
pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex];
/* clear receive flag */
FCIIC_Slave_HWA_ClrErrorFlag(pFciic);
}
/* ################################################################################## */
/* ############################## Interrupt Services ################################ */
void FCIIC0_IRQHandler(void)
{
FCIIC_LL_MasterIRQnHandler(0U);
FCIIC_LL_SlaveIRQnHandler(0U);
}
void FCIIC1_IRQHandler(void)
{
FCIIC_LL_MasterIRQnHandler(1U);
FCIIC_LL_SlaveIRQnHandler(1U);
}

524
Src/fc7xxx_driver_fcpit.c Normal file
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@ -0,0 +1,524 @@
/**
* @file fc7xxx_driver_fcpit.h
* @author Flagchip
* @brief FC7xxx FCPIT driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_fcpit.h"
#include "interrupt_manager.h"
/********* Local Variables ************/
/** @brief FCPIT instance list */
static FCPIT_Type *s_pFcpitInstanceTable[FCPIT_INSTANCE_COUNT] = FCPIT_BASE_PTRS;
/** @brief Fcpit user defined interrupt function */
static FCPIT_InterruptCallBackType s_aFcpitIntNotifyTab[FCPIT_INSTANCE_COUNT][MAX_FCPIT_CHANNEL_NUM] = {0};
/** @brief Fcpit interrupt entry */
void FCPIT0_IRQHandler(void);
/** @brief Fcpit common interrupt handle function */
static void Fcpit_CommonProcessInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel);
/**
* @brief Initialize Fcpit instance.
* @param eFcpit instance
* @param pInitStruct Fcpit initialization structure
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_Init(const FCPIT_InstanceType eFcpit, const FCPIT_InitType *const pInitStruct)
{
FCPIT_Type *pFcpit;
FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS;
if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || (NULL == pInitStruct) )
{
eRet = FCPIT_STATUS_PARAM_INVALID;
}
else
{
pFcpit = s_pFcpitInstanceTable[eFcpit];
/*Enable module clock*/
FCPIT_HWA_EnableModule(pFcpit);
if (pInitStruct->bDebugEn)
{
FCPIT_HWA_SetChannelRunOnDebug(pFcpit);
}
else
{
FCPIT_HWA_SetChannelStopOnDebug(pFcpit);
}
if (pInitStruct->bLowPowerModeEn)
{
FCPIT_HWA_SetChannelRunOnLpm(pFcpit);
}
else
{
FCPIT_HWA_SetChannelStopOnLpm(pFcpit);
}
/* w1c , clear channel interrupt flag*/
FCPIT_HWA_ClearChannelsInterruptFlag(pFcpit, (uint32_t)1U << (uint32_t)pInitStruct->eFcpitChannel);
FCPIT_HWA_ConfigChannel(pFcpit, pInitStruct->eFcpitChannel, (uint32_t)0U);
FCPIT_HWA_ConfigChannelMode(pFcpit, pInitStruct->eFcpitChannel, pInitStruct->eMode);
if (pInitStruct->bChainModeEn)
{
if (pInitStruct->eFcpitChannel > FCPIT_CHANNEL_0)
{
FCPIT_HWA_EnableChannelChainMode(pFcpit, pInitStruct->eFcpitChannel);
}
else
{
/* channel 0 is the first channel can not be chained to last channel */
eRet = FCPIT_STATUS_PARAM_INVALID;
}
}
else
{
/*Chain mode is not enabled, no operation */
}
FCPIT_HWA_SetChannelValue(pFcpit, pInitStruct->eFcpitChannel, pInitStruct->u32TimerValue);
}
return eRet;
}
/**
* @brief Initialize Fcpit trigger configuration
* @param eFcpit instance
* @param pTrgStruct Fcpit trigger structure
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_InitTrigger(const FCPIT_InstanceType eFcpit, const FCPIT_TrggerType *const pTrgStruct)
{
FCPIT_Type *pFcpit;
FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS;
if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || (NULL == pTrgStruct) )
{
eRet = FCPIT_STATUS_PARAM_INVALID;
}
else
{
pFcpit = s_pFcpitInstanceTable[eFcpit];
if ( (uint32_t)0U == FCPIT_HWA_ReadModuleEnable(pFcpit) )
{
eRet = FCPIT_STATUS_FUNCTION_ERROR;
}
else
{
if (pTrgStruct->bStartOnTrigger)
{
FCPIT_HWA_SetChannelStartOnTrig(pFcpit, pTrgStruct->eFcpitChannel);
}
else
{
FCPIT_HWA_ClearChannelStartOnTrig(pFcpit, pTrgStruct->eFcpitChannel);
}
if (pTrgStruct->bStopOnInterrupt)
{
FCPIT_HWA_SetChannelStopOnInterrupt(pFcpit, pTrgStruct->eFcpitChannel);
}
else
{
FCPIT_HWA_ClearChannelStopOnInterrupt(pFcpit, pTrgStruct->eFcpitChannel);
}
if (pTrgStruct->bReloadOnTrigger)
{
FCPIT_HWA_SetChannelReloadOnTrig(pFcpit, pTrgStruct->eFcpitChannel);
}
else
{
FCPIT_HWA_ClearChannelReloadOnTrig(pFcpit, pTrgStruct->eFcpitChannel);
}
if (FCPIT_TRIGGER_EXTERNAL != pTrgStruct->eTriggerSel)
{
FCPIT_HWA_SetChannelTriggerSrc(pFcpit, pTrgStruct->eFcpitChannel);
FCPIT_HWA_SelectChannelTrigger(pFcpit, pTrgStruct->eFcpitChannel, (uint8_t)pTrgStruct->eTriggerSel);
}
else
{
FCPIT_HWA_ClearChannelTriggerSrc(pFcpit, pTrgStruct->eFcpitChannel);
FCPIT_HWA_SelectChannelTrigger(pFcpit, pTrgStruct->eFcpitChannel, (uint8_t)pTrgStruct->eFcpitChannel);
}
}
}
return eRet;
}
/**
* @brief De-initialize Fcpit instance.
* @param eFcpit instance
*/
FCPIT_StatusType FCPIT_Deinit(const FCPIT_InstanceType eFcpit)
{
uint8_t u8Index;
FCPIT_Type *pFcpit;
FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS;
if ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT)
{
eRet = FCPIT_STATUS_PARAM_INVALID;
}
else
{
pFcpit = s_pFcpitInstanceTable[eFcpit];
FCPIT_HWA_ConfigModule(pFcpit, (uint32_t)FCPIT_MCR_M_CEN_MASK);
FCPIT_HWA_ClearChannelsInterruptFlag(pFcpit, (uint32_t)(FCPIT_MSR_TIF3_MASK | FCPIT_MSR_TIF2_MASK | FCPIT_MSR_TIF1_MASK |
FCPIT_MSR_TIF0_MASK));
FCPIT_HWA_DisableChannelsInterrupt(pFcpit, (uint32_t)0U);
for (u8Index = 0U; u8Index < MAX_FCPIT_CHANNEL_NUM; u8Index++)
{
FCPIT_HWA_ConfigChannel(pFcpit, (FCPIT_ChannelType)u8Index, (uint32_t)0U);
FCPIT_HWA_SetChannelValue(pFcpit, (FCPIT_ChannelType)u8Index, (uint32_t)0U);
s_aFcpitIntNotifyTab[eFcpit][u8Index] = NULL;
}
FCPIT_HWA_ConfigModule(pFcpit, (uint32_t)0U);
}
return eRet;
}
/**
* @brief Initialize Fcpit interrupt functionality
* @param eFcpit instance
* @param pIntStruct Fcpit interrupt structure
* @return Fcpit return type
* @note this function will stop timer
*/
FCPIT_StatusType FCPIT_InitInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_IntType *const pIntStruct)
{
FCPIT_Type *pFcpit;
FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS;
if ( ((uint8_t)eFcpit >= FCPIT_INSTANCE_COUNT) || (NULL == pIntStruct) )
{
eRet = FCPIT_STATUS_PARAM_INVALID;
}
else
{
pFcpit = s_pFcpitInstanceTable[eFcpit];
if ((uint32_t)0U == (uint32_t)FCPIT_HWA_ReadModuleEnable(pFcpit))
{
eRet = FCPIT_STATUS_FUNCTION_ERROR;
}
else
{
FCPIT_HWA_DisableChannel(pFcpit, pIntStruct->eFcpitChannel);
/* w1c , clear channel interrupt flag*/
FCPIT_HWA_ClearChannelsInterruptFlag(pFcpit, (uint32_t)1U << (uint32_t)pIntStruct->eFcpitChannel);
if (pIntStruct->bChannelIsrEn)
{
FCPIT_HWA_EnableChannelsInterrupt(pFcpit, (uint32_t)1U << (uint32_t)pIntStruct->eFcpitChannel);
s_aFcpitIntNotifyTab[eFcpit][pIntStruct->eFcpitChannel] = pIntStruct->pIsrNotify;
}
else
{
FCPIT_HWA_DisableChannelsInterrupt(pFcpit, (uint32_t)1U << (uint32_t)pIntStruct->eFcpitChannel);
s_aFcpitIntNotifyTab[eFcpit][pIntStruct->eFcpitChannel] = pIntStruct->pIsrNotify;
}
}
}
return eRet;
}
/**
* @brief Enable Fcpit interrupt
* @param eFcpit instance
* @param eChannel Fcpit channel
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_EnableInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel)
{
FCPIT_Type *pFcpit;
FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS;
if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || ((uint32_t)eChannel >= MAX_FCPIT_CHANNEL_NUM))
{
eRet = FCPIT_STATUS_PARAM_INVALID;
}
else
{
pFcpit = s_pFcpitInstanceTable[eFcpit];
if ((uint32_t)0U == (uint32_t)FCPIT_HWA_ReadModuleEnable(pFcpit))
{
eRet = FCPIT_STATUS_FUNCTION_ERROR;
}
else
{
FCPIT_HWA_DisableChannel(pFcpit, eChannel);
/* w1c , clear channel interrupt flag*/
FCPIT_HWA_ClearChannelsInterruptFlag(pFcpit, (uint32_t)1U << (uint32_t)eChannel);
FCPIT_HWA_EnableChannelsInterrupt(pFcpit, (uint32_t)1U << (uint32_t)eChannel);
FCPIT_HWA_EnableChannel(pFcpit, eChannel);
}
}
return eRet;
}
/**
* @brief Disable Fcpit interrupt
* @param eFcpit instance
* @param eChannel Fcpit channel
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_DisableInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel)
{
FCPIT_Type *pFcpit;
FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS;
if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || ((uint32_t)eChannel >= MAX_FCPIT_CHANNEL_NUM) )
{
eRet = FCPIT_STATUS_PARAM_INVALID;
}
else
{
pFcpit = s_pFcpitInstanceTable[eFcpit];
if ((uint32_t)0U == (uint32_t)FCPIT_HWA_ReadModuleEnable(pFcpit))
{
eRet = FCPIT_STATUS_FUNCTION_ERROR;
}
else
{
FCPIT_HWA_DisableChannel(pFcpit, eChannel);
/* w1c , clear channel interrupt flag*/
FCPIT_HWA_ClearChannelsInterruptFlag(pFcpit, (uint32_t)1U << (uint32_t)eChannel);
FCPIT_HWA_DisableChannelsInterrupt(pFcpit, (uint32_t)1U << (uint32_t)eChannel);
FCPIT_HWA_EnableChannel(pFcpit, eChannel);
}
}
return eRet;
}
/**
* @brief Fcpit start timer
* @param eFcpit instance
* @param eChannel Fcpit channel
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_Start(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel)
{
FCPIT_Type *pFcpit;
FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS;
if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || ((uint32_t)eChannel >= MAX_FCPIT_CHANNEL_NUM) )
{
eRet = FCPIT_STATUS_PARAM_INVALID;
}
else
{
pFcpit = s_pFcpitInstanceTable[eFcpit];
if ((uint32_t)0U == (uint32_t)FCPIT_HWA_ReadModuleEnable(pFcpit))
{
eRet = FCPIT_STATUS_FUNCTION_ERROR;
}
if (FCPIT_STATUS_SUCCESS == eRet)
{
FCPIT_HWA_EnableChannel(pFcpit, eChannel);
}
}
return eRet;
}
/**
* @brief Fcpit stop
* @param eFcpit instance
* @param eChannel Fcpit channel
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_Stop(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel)
{
FCPIT_Type *pFcpit;
FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS;
if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || ((uint32_t)eChannel >= MAX_FCPIT_CHANNEL_NUM) )
{
eRet = FCPIT_STATUS_PARAM_INVALID;
}
else
{
pFcpit = s_pFcpitInstanceTable[eFcpit];
if ((uint32_t)0U == (uint32_t)FCPIT_HWA_ReadModuleEnable(pFcpit))
{
eRet = FCPIT_STATUS_FUNCTION_ERROR;
}
else
{
FCPIT_HWA_DisableChannel(pFcpit, eChannel);
}
}
return eRet;
}
/**
* @brief Immediately update Fcpit channel value
* @param eFcpit instance
* @param eChannel Fcpit channel
* @param u32ChannelValue in/Out value
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_ImmediateUpdateChannelValue(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel, const uint32_t u32ChannelValue)
{
FCPIT_Type *pFcpit;
FCPIT_StatusType eRet;
pFcpit = s_pFcpitInstanceTable[eFcpit];
eRet = FCPIT_Stop(eFcpit, eChannel);
if (FCPIT_STATUS_SUCCESS == eRet)
{
FCPIT_HWA_SetChannelValue(pFcpit, eChannel, u32ChannelValue);
eRet = FCPIT_Start(eFcpit, eChannel);
}
else
{
return eRet;
}
return eRet;
}
/**
* @brief Update Fcpit channel value
* @param eFcpit instance
* @param eChannel Fcpit channel
* @param u32ChannelValue in/Out value
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_UpdateChannelValue(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel, const uint32_t u32ChannelValue)
{
FCPIT_Type *pFcpit;
FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS;
if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || ((uint32_t)eChannel >= MAX_FCPIT_CHANNEL_NUM) )
{
eRet = FCPIT_STATUS_PARAM_INVALID;
}
else
{
pFcpit = s_pFcpitInstanceTable[eFcpit];
if ((uint32_t)0U == (uint32_t)FCPIT_HWA_ReadModuleEnable(pFcpit))
{
eRet = FCPIT_STATUS_FUNCTION_ERROR;
}
if (FCPIT_STATUS_SUCCESS == eRet)
{
FCPIT_HWA_SetChannelValue(pFcpit, eChannel, u32ChannelValue);
}
}
return eRet;
}
/**
* @brief read Fcpit channel time stamps.
* #param eFcpit Fcpit instance
* @param eChannel Fcpit channel
* @param *u32timeStampValue value
* @return Fcpit return type
*/
FCPIT_StatusType FCPIT_ReadTimstamp(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel,uint32_t *u32timeStampValue)
{
FCPIT_Type *pFcpit;
FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS;
if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || ((uint32_t)eChannel >= MAX_FCPIT_CHANNEL_NUM) )
{
eRet = FCPIT_STATUS_PARAM_INVALID;
}
pFcpit = s_pFcpitInstanceTable[eFcpit];
if((uint32_t)0x3u != FCPIT_HWA_ReadChannelMode(pFcpit,eChannel))
{
eRet = FCPIT_STATUS_PARAM_INVALID;
}
else
{
*u32timeStampValue = FCPIT_HWA_ReadChannelValue(pFcpit,eChannel);
}
return eRet;
}
/**
* @brief Fcpit common interrupt handle function
* @param eFcpit instance
* @param eChannel Fcpit interrupt channel
*/
static void Fcpit_CommonProcessInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel)
{
if (NULL != s_aFcpitIntNotifyTab[eFcpit][eChannel])
{
s_aFcpitIntNotifyTab[eFcpit][eChannel]();
}
}
/**
* @brief Fcpit_0 interrupt handler entry
*
*/
void FCPIT0_IRQHandler(void)
{
uint32_t u32TifValue = FCPIT_HWA_ReadEnableInterruptFlag(FCPIT) & FCPIT_HWA_ReadInterruptFlag(FCPIT);
if ((u32TifValue & FCPIT_MSR_TIF0_MASK) != 0u)
{
Fcpit_CommonProcessInterrupt(FCPIT_0, FCPIT_CHANNEL_0);
FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT, (uint32_t)FCPIT_MSR_TIF0_MASK);
}
if ((u32TifValue & FCPIT_MSR_TIF1_MASK) != 0u)
{
Fcpit_CommonProcessInterrupt(FCPIT_0, FCPIT_CHANNEL_1);
FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT, (uint32_t)FCPIT_MSR_TIF1_MASK);
}
if ((u32TifValue & FCPIT_MSR_TIF2_MASK) != 0u)
{
Fcpit_CommonProcessInterrupt(FCPIT_0, FCPIT_CHANNEL_2);
FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT, (uint32_t)FCPIT_MSR_TIF2_MASK);
}
if ((u32TifValue & FCPIT_MSR_TIF3_MASK) != 0u)
{
Fcpit_CommonProcessInterrupt(FCPIT_0, FCPIT_CHANNEL_3);
FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT, (uint32_t)FCPIT_MSR_TIF3_MASK);
}
}

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/**
* @file fc7xxx_driver_fcsmu.c
* @author Flagchip
* @brief FC7xxx FCSMU driver type definition and API
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_fcsmu.h"
#include "HwA_csc.h"
/* ################################################################################## */
/* ####################################### Macro #################################### */
#define FCSMU_FST_UNLOCK_KEY 0x951413CFU
#define FCSMU_OPC1_UNLOCK_KEY 0xFC2020CFU
#define FCSMU_OPC2_UNLOCK_KEY 0x20FCCF20U
#define FCSMU_CONFIG_TMEP_UNLOCK_KEY 0xFCU
/* ################################################################################## */
/* ################################### Type define ################################## */
/* ################################################################################## */
/* ################################ Local Variables ################################# */
static FCSMU_Type *const s_apFcsmuBase[FCSMU_INSTANCE_COUNT] = FCSMU_BASE_PTRS;
static FCSMU_ISRCallbackType s_apFcsmuISRCallback = NULL;
/* ################################################################################## */
/* ########################### Local Prototype Functions ############################ */
/* ################################################################################## */
/* ######################### Global prototype Functions ############################ */
void FCSMU0_IRQHandler(void);
/* ################################################################################## */
/* ################################ Local Functions ################################ */
/* ################################################################################## */
/* ################################ Global Functions ################################ */
FCSMU_StatusType FCSMU_init(const FCSMU_InitCfgType *pInitConfig)
{
DEV_ASSERT(pInitConfig != NULL);
FCSMU_StatusType eRet;
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
eRet = FCSMU_TransStateNTC();
if (eRet != FCSMU_STATUS_SUCCESS)
{
return eRet;
}
if (pInitConfig->u32WarnTo > 432000U)
{
FCSMU_HWA_SetWaringTo(pFcsmu, 432000U);
}
else
{
FCSMU_HWA_SetWaringTo(pFcsmu, pInitConfig->u32WarnTo);
}
FCSMU_HWA_ClearCfgToIrq(pFcsmu);
FCSMU_HWA_SetWarningEn0(pFcsmu, pInitConfig->u32WarnChannel);
FCSMU_HWA_SetWarningIen(pFcsmu, pInitConfig->u32WarnInterruptChannel);
FCSMU_HWA_SetFaultIen(pFcsmu, pInitConfig->u32FaultInterruptChannel);
FCSMU_HWA_SetFRST0(pFcsmu, pInitConfig->u32FaultResetChannel);
FCSMU_HWA_SetFe0(pFcsmu, pInitConfig->u32FaultChannel);
FCSMU_HWA_SetFccr0(pFcsmu, pInitConfig->u32SoftwareClearedChannel);
eRet = FCSMU_TransStateCTN();
FCSMU_HWA_SetTempUnlk(pFcsmu, 0xFFU);
s_apFcsmuISRCallback = pInitConfig->pISRCallback;
return eRet;
}
FCSMU_StatusType FCSMU_ConfigStatusOutput(FCSMU_StatusOutputConfigType *pInitConfig)
{
DEV_ASSERT(pInitConfig != NULL);
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
uint32_t u32TempValue;
FCSMU_StatusType eRet;
if (pInitConfig->eFastMode == true)
{
if (pInitConfig->eProtocal != FCSMU_SOUT_PROTOCOL_DUAL_RAIL && pInitConfig->eProtocal != FCSMU_SOUT_PROTOCOL_TIME_SWITCH)
{
return FCSMU_STATUS_ERROR;
}
}
u32TempValue = FCSMU_SOCTRL_SOUT_PEN(pInitConfig->bEnable) |
FCSMU_SOCTRL_FASTEN(pInitConfig->eFastMode) |
FCSMU_SOCTRL_POLSW(pInitConfig->ePolarity) |
FCSMU_SOCTRL_SOUT_PTC(pInitConfig->eProtocal) |
FCSMU_SOCTRL_DIVEX(pInitConfig->bDivex) |
FCSMU_SOCTRL_SOUT_CTRL(pInitConfig->eSoutCtrl) |
FCSMU_SOCTRL_SOUT_DIV(pInitConfig->u32Divder) |
FCSMU_SOCTRL_SMRDT(pInitConfig->u32Delaytimer);
eRet = FCSMU_TransStateNTC();
if (eRet != FCSMU_STATUS_SUCCESS)
{
return eRet;
}
FCSMU_HWA_SetSoctrl(pFcsmu, u32TempValue);
FCSMU_HWA_SetSoutEn(pFcsmu, pInitConfig->u32SoutChannel);
eRet = FCSMU_TransStateCTN();
return eRet;
}
void FCSMU_CrcGen(void)
{
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
FCSMU_HWA_GenerateCrc(pFcsmu);
}
bool FCSMU_IsCrcBusy(void)
{
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
return FCSMU_HWA_GetCrcBusy(pFcsmu);
}
FCSMU_StatusType FCSMU_CrcConfig(FCSMU_CrcModeType eMode)
{
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
uint32_t u32TimeoutTimes = 65535U;
FCSMU_StatusType eRet = FCSMU_STATUS_SUCCESS;
FCSMU_HWA_GenerateCrc(pFcsmu);
while (FCSMU_HWA_GetCrcBusy(pFcsmu) == FCSMU_Crc_STATE_BUSY)
{
u32TimeoutTimes--;
if (u32TimeoutTimes == 0U)
{
eRet = FCSMU_STATUS_ERROR;
break;
}
}
if (eRet == FCSMU_STATUS_SUCCESS)
{
if (eMode == FCSMU_CRC_TRIGGER_MODE)
{
FCSMU_HWA_EnableTrigger(pFcsmu, true);
}
else
{
}
CSC0_HWA_CTRL4_EnableReqToSMU(CSC_SMU_SCF_IRQ);
FCSMU_HWA_EnableErrorOutput(pFcsmu, true);
FCSMU_HWA_EnableCrcChecker(pFcsmu, true);
}
return eRet;
}
FCSMU_StatusType FCSMU_ClearFaultFlag(uint32_t u32FaultChannel)
{
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
uint32_t u32TimeoutTimes = 65535U;
FCSMU_StatusType eRet = FCSMU_STATUS_SUCCESS;
FCSMU_HWA_SetFunlk(pFcsmu, FCSMU_FST_UNLOCK_KEY);
FCSMU_HWA_SetFst0(pFcsmu, u32FaultChannel);
while (FCSMU_HWA_GetCtrlOps(pFcsmu) != (uint32_t)FCSMU_OP_STATE_SUCCESSFUL)
{
u32TimeoutTimes--;
if (u32TimeoutTimes == 0U)
{
eRet = FCSMU_STATUS_ERROR;
break;
}
}
return eRet;
}
FCSMU_StatusType FCSMU_TransStateCTN(void)
{
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
uint32_t u32TimeoutTimes;
uint32_t u32RetryTimes = 65535U;
uint32_t u32Temp;
FCSMU_StatusType eRet = FCSMU_STATUS_ERROR;
while (u32RetryTimes != 0U)
{
u32TimeoutTimes = 65535U;
u32Temp = (uint32_t)FCSMU_HWA_GetCtrl(pFcsmu);
u32Temp |= (uint32_t)FCSMU_OPC_MOVE_TO_NORMAL;
FCSMU_HWA_SetOprk(pFcsmu, FCSMU_OPC2_UNLOCK_KEY);
FCSMU_HWA_SetCrtl(pFcsmu, u32Temp);
while (FCSMU_HWA_GetCtrlOps(pFcsmu) != (uint32_t)FCSMU_OP_STATE_SUCCESSFUL)
{
u32TimeoutTimes--;
if (u32TimeoutTimes == 0U)
{
break;
}
}
if (u32TimeoutTimes != 0U)
{
if (FCSMU_HWA_GetState(pFcsmu) == (uint32_t)FCSMU_STATE_NORMAL)
{
break;
}
}
u32RetryTimes--;
}
if (u32RetryTimes != 0U)
{
eRet = FCSMU_STATUS_SUCCESS;
}
return eRet;
}
FCSMU_StatusType FCSMU_TransStateNTC(void)
{
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
uint32_t u32TimeoutTimes;
uint32_t u32RetryTimes = 65535U;
FCSMU_StatusType eRet = FCSMU_STATUS_ERROR;
uint32_t u32Temp;
while (u32RetryTimes != 0U)
{
u32TimeoutTimes = 65535U;
u32Temp = FCSMU_HWA_GetCtrl(pFcsmu);
u32Temp |= (uint32_t)FCSMU_OPC_MOVE_TO_CONFIG;
FCSMU_HWA_SetTempUnlk(pFcsmu, FCSMU_CONFIG_TMEP_UNLOCK_KEY);
FCSMU_HWA_SetOprk(pFcsmu, FCSMU_OPC1_UNLOCK_KEY);
FCSMU_HWA_SetCrtl(pFcsmu, u32Temp);
while (FCSMU_HWA_GetCtrlOps(pFcsmu) != (uint32_t)FCSMU_OP_STATE_SUCCESSFUL)
{
if (FCSMU_HWA_GetCtrlOps(pFcsmu) == (uint32_t)FCSMU_OP_STATE_BUSY)
{
u32TimeoutTimes--;
if (u32TimeoutTimes == 0U)
{
break;
}
}
else
{
break;
}
}
if (u32TimeoutTimes != 0U)
{
if (FCSMU_HWA_GetState(pFcsmu) == (uint32_t)FCSMU_STATE_CONGIG)
{
break;
}
}
u32RetryTimes--;
}
if (u32RetryTimes != 0U)
{
eRet = FCSMU_STATUS_SUCCESS;
}
return eRet;
}
void FCSMU_InjectionFault(uint32_t u32ChannelIndex)
{
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
FCSMU_HWA_SetInject(pFcsmu, u32ChannelIndex);
}
uint32_t FCSMU_GetFaultChannel(void)
{
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
return FCSMU_HWA_GetFst0(pFcsmu);
}
uint32_t FCSMU_GetIrqState(void)
{
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
return FCSMU_HWA_GetIrqStat(pFcsmu);
}
uint32_t FCSMU_GetNtfFlag(void)
{
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
return FCSMU_HWA_GetNtf(pFcsmu);
}
uint32_t FCSMU_GetWtfFlag(void)
{
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
return FCSMU_HWA_GetWtf(pFcsmu);
}
uint32_t FCSMU_GetNtwFlag(void)
{
FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0];
return FCSMU_HWA_GetNtw(pFcsmu);
}
static void FCSMUn_IRQHandler(void)
{
uint32_t u32TempValue = FCSMU_GetIrqState();
uint32_t u32IrqChannel;
if ((FCSMU_IRQ_STAT_FAULT_IRQ_MASK & u32TempValue) == FCSMU_IRQ_STAT_FAULT_IRQ_MASK)
{
if ((FCSMU_GetNtfFlag() & FCSMU_NTF_FLAG_MASK) == FCSMU_NTF_FLAG_MASK)
{
u32IrqChannel = FCSMU_GetNtfFlag() & 0xFFU;
}
else
{
u32IrqChannel = FCSMU_GetWtfFlag() & 0xFFU;
}
if (u32IrqChannel == 0xFFU)
{
u32IrqChannel = FCSMU_GetFaultChannel();
}
else
{
if (u32IrqChannel > 0U && u32IrqChannel <= 32U)
{
u32IrqChannel = (uint32_t)1U << (u32IrqChannel - (uint32_t)1U);
}
else
{
u32IrqChannel = 0U;
}
}
s_apFcsmuISRCallback(FCSMU_FAULT_IRQ, u32IrqChannel);
}
else if ((FCSMU_IRQ_STAT_WARNING_IRQ_MASK & u32TempValue) == FCSMU_IRQ_STAT_WARNING_IRQ_MASK)
{
u32IrqChannel = FCSMU_GetNtwFlag() & 0xFFU;
if (u32IrqChannel == 0xFFU)
{
u32IrqChannel = FCSMU_GetFaultChannel();
}
else
{
if (u32IrqChannel > 0U && u32IrqChannel <= 32U)
{
u32IrqChannel = (uint32_t)1U << (u32IrqChannel - (uint32_t)1U);
}
else
{
u32IrqChannel = 0U;
}
}
s_apFcsmuISRCallback(FCSMU_WARNING_IRQ, u32IrqChannel);
}
else if ((FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK & u32TempValue) == FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK)
{
s_apFcsmuISRCallback(FCSMU_CFG_TIMEOUT, 0);
}
else
{
}
}
void FCSMU0_IRQHandler(void)
{
FCSMUn_IRQHandler();
}

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/**
* @file fc7xxx_driver_flash.c
* @author Flagchip
* @brief FC7xxx Flash driver source code
* @version 0.1.0
* @date 2024-01-11
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_flash.h"
/* ################################################################################## */
/* ####################################### Macro #################################### */
#define STATUS_SUCCESS 0x001UL
#define STATUS_HVOP 0x8001UL
#define FLASH_API_DISABLE 0x0UL
#define FLASH_API_ENABLE 0x1UL
#define FLASH_API_SIZE_8M 0x0UL
#define WDG_TUNE_DISABLE 0x1u
#define FLASH_AUTO_HOLD_ENABLE 0x1UL
#define FLASH_AUTO_HOLD_DISABLE 0x0UL
#define FLASH_REG_BIT_CFG_DISABLE 0x0UL
#define FLASH_REG_BIT_CFG_ENABLE 0x1UL
#define FLASH_REG_BIT_CFG_HOLD 0x2UL
#define INVAILD_ADDR ((void*)0xFFFFFFFFU)
#define FLS_MAX_ERASE_BLANK_CHECK (256U)
#define FLS_ABT_TIMEOUT_VALUE (1000000U)
#define FLS_ASYNC_WRITE_TIMEOUT_VALUE (1000U)
#define FLS_ASYNC_ERASE_TIMEOUT_VALUE (500000U)
/*=================================================================================================
* LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
=================================================================================================*/
typedef uint32_t status_t;
typedef struct {
uint32_t blk_sel;
uint32_t dest;
} FLASH_DRV_ERASESECTOR_CFG_T;
typedef struct {
uint32_t dest;
uint32_t size;
uint32_t *pData;
uint32_t wdg_tune;
uint32_t pgff;
} FLASH_DRV_PRGM_CFG_T;
typedef struct
{
uint16 u16FlashRomApiMajorVersion;
uint16 u16FlashRomApiMinorVersion;
status_t (*FLASH_DRV_EraseBlock)(FLASH_API_BLOCK_SELECT_TYPE blk_se, uint32_t int_en, uint32_t type);
status_t (*FLASH_DRV_EraseBlock_Clear)(void);
status_t (*FLASH_DRV_EraseSector)(FLASH_DRV_ERASESECTOR_CFG_T * flash_api_cfg, uint32_t int_en, uint32_t type);
status_t (*FLASH_DRV_EraseSector_Clear)(void);
uint32_t RESERVED2[2U];
status_t (*FLASH_DRV_Program)(FLASH_DRV_PRGM_CFG_T * flash_api_cfg, uint32_t int_en, uint32_t type);
status_t (*FLASH_DRV_Program_Clear)(void);
uint32_t RESERVED3[6U];
status_t (*FLASH_DRV_HV_Status_Check)(void);
uint32_t RESERVED4[8U];
status_t (*FLASH_DRV_ENABLE_HOLD_CFG)(uint32_t flash_api_cfg);
}FLASH_ROM_API_ENTRY_T;
/** flash driver header for finding function in special address */
#define FLASHAPI_IN_ROM_ADDR 0x04810200U /* flash api address in rom */
const FLASH_ROM_API_ENTRY_T *s_pFlashDriver_RomApiHeader;
/* ################################################################################## */
/* ################################ Local Variables ################################# */
/* ################################################################################## */
/* ########################### Local Prototype Functions ############################ */
/* ################################################################################## */
/* ########################### Global Prototype Functions ########################### */
/* ################################################################################## */
/* ################################ Local Functions ################################# */
/**
* \brief PFlash Driver Function for Erasing Address Check
*
* \param pFlashParam flash driver erase parameter
*/
static FLASH_StatusType FLASHDRIVER_LL_PFlashEraseCheck(FLASH_DRIVER_ParamType *pFlashParam)
{
FLASH_StatusType tRetVal;
if (s_pFlashDriver_RomApiHeader != (FLASH_ROM_API_ENTRY_T *)FLASHAPI_IN_ROM_ADDR)
{
tRetVal = FLASH_ERROR_NO_INIT;
}
else
{
tRetVal = FLASH_ERROR_OK;
/* check address align */
if (pFlashParam->u32Address & (PFLASH_ERASE_SECTOR_SIZE - 1U))
{
tRetVal = FLASH_ERROR_INVALID_ADDR;
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
}
else
{
/* check length align */
if (pFlashParam->u32Length & (PFLASH_ERASE_SECTOR_SIZE - 1U))
{
tRetVal = FLASH_ERROR_INVALID_SIZE;
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
}
}
}
return tRetVal;
}
/**
* \brief DFlash Driver Function for Erasing Address Check
*
* \param pFlashParam flash driver erase parameter
*/
static FLASH_StatusType FLASHDRIVER_LL_DFlashEraseCheck(FLASH_DRIVER_ParamType *pFlashParam)
{
FLASH_StatusType tRetVal;
if (s_pFlashDriver_RomApiHeader != (FLASH_ROM_API_ENTRY_T *)FLASHAPI_IN_ROM_ADDR)
{
tRetVal = FLASH_ERROR_NO_INIT;
}
else
{
tRetVal = FLASH_ERROR_OK;
/* check address align */
if (pFlashParam->u32Address & (DFLASH_ERASE_SECTOR_SIZE - 1U))
{
tRetVal = FLASH_ERROR_INVALID_ADDR;
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
}
else
{
/* check length align */
if (pFlashParam->u32Length & (DFLASH_ERASE_SECTOR_SIZE - 1U))
{
tRetVal = FLASH_ERROR_INVALID_SIZE;
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
}
}
}
return tRetVal;
}
/**
* \brief PFlash Driver Function for Writing address Check
*
* \param pFlashParam flash driver write parameter
*/
static FLASH_StatusType FLASHDRIVER_PFlashWriteCheck(FLASH_DRIVER_ParamType *pFlashParam)
{
FLASH_StatusType tRetVal;
if (s_pFlashDriver_RomApiHeader != (FLASH_ROM_API_ENTRY_T *)FLASHAPI_IN_ROM_ADDR)
{
tRetVal = FLASH_ERROR_NO_INIT;
}
else
{
tRetVal = FLASH_ERROR_OK;
/* check address align */
if (pFlashParam->u32Address & (PFLASH_PROGRAM_PAGE_MIN_SIZE - 1U))
{
tRetVal = FLASH_ERROR_INVALID_ADDR;
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
}
else
{
/* check length align */
if (pFlashParam->u32Length & (PFLASH_PROGRAM_PAGE_MIN_SIZE - 1U))
{
tRetVal = FLASH_ERROR_INVALID_SIZE;
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
}
}
}
return tRetVal;
}
/**
* \brief DFlash Driver Function for Writing address Check
*
* \param pFlashParam flash driver write parameter
*/
static FLASH_StatusType FLASHDRIVER_DFlashWriteCheck(FLASH_DRIVER_ParamType *pFlashParam)
{
FLASH_StatusType tRetVal;
if (s_pFlashDriver_RomApiHeader != (FLASH_ROM_API_ENTRY_T *)FLASHAPI_IN_ROM_ADDR)
{
tRetVal = FLASH_ERROR_NO_INIT;
}
else
{
tRetVal = FLASH_ERROR_OK;
/* check address align */
if (pFlashParam->u32Address & (DFLASH_PROGRAM_PAGE_MIN_SIZE - 1U))
{
tRetVal = FLASH_ERROR_INVALID_ADDR;
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
}
else
{
/* check length align */
if (pFlashParam->u32Length & (DFLASH_PROGRAM_PAGE_MIN_SIZE - 1U))
{
tRetVal = FLASH_ERROR_INVALID_SIZE;
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
}
}
}
return tRetVal;
}
/**
* \brief PFlash Driver Function for lock/unlock sector
*
* \param u32Address sector address
* \param bLock 0U-unlock, 1U-lock
*/
static void FLASHDRIVER_PFlashLockBlock(FLASH_API_BLOCK_SELECT_TYPE blk_sel, uint8_t bLock)
{
uint32_t u32Index;
uint32_t u32Temp;
u32Index = (uint32_t)blk_sel;
/* 1 bank contains more than 256KB, used FB_CPELCK for first and last 256KB used FB_FPELCK */
/* PFLASH bank index */
u32Temp = bLock ? 0xFFFFFFFFUL : 0x0UL;
if(blk_sel < FLASH_DATA_BLOCK_SELECT0)
{
FMC1->FB_CPELCK[u32Index] = u32Temp;
FMC1->FB_FPELCK[u32Index] = u32Temp;
}
else
{
FMC1->FB_FPELCK[u32Index] = u32Temp;
}
}
/**
* \brief PFlash Driver Function for lock/unlock sector
*
* \param u32Address sector address
* \param bLock 0U-unlock, 1U-lock
*/
static FLASH_StatusType FLASHDRIVER_PFlashLockSector(uint32_t u32Address, uint8_t bLock)
{
FLASH_StatusType tRetVal;
uint32_t u32Index;
uint32_t u32Length;
uint32_t u32Temp;
tRetVal = FLASH_ERROR_OK;
/* 1 bank contains more than 256KB, used FB_CPELCK for first and last 256KB used FB_FPELCK */
if ((u32Address >= PFLASH_ADDR_START) && (u32Address <= PFLASH_ADDR_END))
{
/* PFLASH bank index */
u32Index = (u32Address - PFLASH_ADDR_START) / PFLASH_BANK_SIZE;
u32Length = ((u32Address - PFLASH_ADDR_START) % PFLASH_BANK_SIZE) ;
if (u32Length < (PFLASH_BANK_SIZE - FLASH_256KB_SIZE)) /* first 1792KB */
{
u32Temp = ((uint32_t)1UL << ((u32Address - PFLASH_ADDR_START - PFLASH_BANK_SIZE * u32Index) >> 16));
u32Temp = bLock ? 0xFFFFFFFFUL : (0xFFFFFFFFUL ^ u32Temp);
FMC1->FB_CPELCK[u32Index] = u32Temp;
}
else /* last 256KB */
{
u32Temp = ((u32Address - PFLASH_ADDR_START - PFLASH_BANK_SIZE * u32Index - PFLASH_LAST256K_OFFSET) >> 13);
u32Temp = ((uint32_t)1UL << u32Temp);
u32Temp = bLock ? 0xFFFFFFFFUL : (0xFFFFFFFFUL ^ u32Temp);
/* 0x1C0000UL */
FMC1->FB_FPELCK[u32Index] = u32Temp;
}
}
else
{
tRetVal = FLASH_ERROR_INVALID_ADDR;
}
return tRetVal;
}
/**
* \brief DFlash Driver Function for lock/unlock sector
*
* \param u32Address sector address
* \param bLock 0U-unlock, 1U-lock
*/
static FLASH_StatusType FLASHDRIVER_DFlashLockSector(uint32_t u32Address, uint8_t bLock)
{
FLASH_StatusType tRetVal;
uint32_t u32Index;
uint32_t u32Temp;
tRetVal = FLASH_ERROR_OK;
/* 1 bank contains only 256KB, only used FB_FPELCK */
u32Index = 2U;
if ((u32Address >= DFLASH_ADDR_START) && (u32Address <= DFLASH_ADDR_END))
{
u32Temp = 0xFFFFFFFFUL ^ (1UL << ((u32Address - DFLASH_ADDR_START - DFLASH_BANK0_SIZE * (u32Index - 2U)) >> 13));
FMC1->FB_FPELCK[u32Index] = bLock ? 0xFFFFFFFFUL : u32Temp ;
}
else
{
tRetVal = FLASH_ERROR_INVALID_ADDR;
}
return tRetVal;
}
/**
* \brief Get Flash Configuration
*
* \param u32Address the flash address
* \param pFlash_api_cfg out flash parameter
*/
static FLASH_StatusType FLASHDRIVER_GetFlashConfig(uint32_t u32Address, FLASH_DRV_ERASESECTOR_CFG_T *pFlash_api_cfg)
{
FLASH_StatusType tRetVal;
tRetVal = FLASH_ERROR_OK;
if ((u32Address >= PFLASH_ADDR_START) && (u32Address < PFLASH_ADDR_START + PFLASH_BANK_SIZE))
{
pFlash_api_cfg->blk_sel = FLASH_BLOCK_SELECT0;
pFlash_api_cfg->dest = u32Address;
}
else if ((u32Address >= PFLASH_ADDR_START) && (u32Address < PFLASH_ADDR_START + PFLASH_BANK_SIZE*2U))
{
pFlash_api_cfg->blk_sel = FLASH_BLOCK_SELECT1;
pFlash_api_cfg->dest = u32Address;
}
else if ((u32Address >= DFLASH_ADDR_START) && (u32Address < DFLASH_ADDR_START + DFLASH_BANK0_SIZE))
{
pFlash_api_cfg->blk_sel = FLASH_DATA_BLOCK_SELECT0;
pFlash_api_cfg->dest = u32Address;
}
else
{
tRetVal = FLASH_ERROR_INVALID_ADDR;
}
return tRetVal;
}
/* ################################################################################## */
/* ################################# Global Functions ############################### */
void FLASHDRIVER_Init(void)
{
s_pFlashDriver_RomApiHeader = (FLASH_ROM_API_ENTRY_T *)FLASHAPI_IN_ROM_ADDR;
}
/**
* \brief PFlash Driver Function for Erasing
*
* \param pFlashParam flash driver erase parameter
* \return ErrorType
*/
FLASH_StatusType FLASHDRIVER_FlashEraseBlock(FLASH_API_BLOCK_SELECT_TYPE blk_sel)
{
uint32_t u32TryCount;
FLASH_StatusType tRetVal;
uint32_t u32Temp;
tRetVal = FLASH_ERROR_OK;
if(blk_sel > FLASH_DATA_BLOCK_SELECT0)
{
tRetVal = FLASH_ERROR_INVALID_PARAM;
}
else
{
s_pFlashDriver_RomApiHeader->FLASH_DRV_ENABLE_HOLD_CFG(FLASH_AUTO_HOLD_ENABLE);
FLASHDRIVER_PFlashLockBlock(blk_sel, 0);
__asm(" cpsid i");
u32Temp = s_pFlashDriver_RomApiHeader-> FLASH_DRV_EraseBlock(blk_sel, FLASH_API_DISABLE, 0);
__asm(" cpsie i");
tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED;
/* check erase operation valid */
if (tRetVal != FLASH_ERROR_OK)
{
}
else
{
/* check erasing still in progress */
tRetVal = FLASH_ERROR_FAILED;
u32TryCount = 0;
while ((tRetVal != FLASH_ERROR_OK) && (u32TryCount++ < 1000000))
{
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_HV_Status_Check();
/* check if finished */
if (u32Temp == STATUS_HVOP)
{
tRetVal = FLASH_ERROR_FAILED;
}
else
{
tRetVal = FLASH_ERROR_OK;
}
}
if (tRetVal != FLASH_ERROR_OK)
{
/* erasing timeout, exit */
*(uint32_t*)(0x00000014U) = *((uint32_t*)0x40020004U);
}
else
{
/* check erasing result */
u32Temp = s_pFlashDriver_RomApiHeader-> FLASH_DRV_EraseBlock_Clear();
tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED;
}
}
}
return tRetVal;
}
/**
* \brief PFlash Driver Function for Erasing
*
* \param pFlashParam flash driver erase parameter
* \return ErrorType
*/
FLASH_StatusType FLASHDRIVER_PFlashEraseSector(FLASH_DRIVER_ParamType *pFlashParam)
{
uint32_t u32Addr, u32Length;
uint32_t u32TryCount;
FLASH_DRV_ERASESECTOR_CFG_T tFlash_api_cfg;
FLASH_StatusType tRetVal;
uint32_t u32Temp;
tRetVal = FLASH_ERROR_OK;
/* FLASH_DRV_WDG_CFG_T tFlash_wdg_cfg; */
u32Addr = pFlashParam->u32Address;
u32Length = pFlashParam->u32Length;
tRetVal = FLASH_ERROR_OK;
pFlashParam->u32ErrorAddress = 0x0U;
tRetVal = FLASHDRIVER_LL_PFlashEraseCheck(pFlashParam);
if (tRetVal == FLASH_ERROR_OK)
{
/* config flash wdog */
//ConfigFlashWdog();
s_pFlashDriver_RomApiHeader->FLASH_DRV_ENABLE_HOLD_CFG(FLASH_AUTO_HOLD_ENABLE);
pFlashParam->u32Length = PFLASH_ERASE_SECTOR_SIZE;
/* loop erase */
for (pFlashParam->u32Address = u32Addr; pFlashParam->u32Address < u32Addr + u32Length;
pFlashParam->u32Address += PFLASH_ERASE_SECTOR_SIZE)
{
FLASHDRIVER_PFlashLockSector(pFlashParam->u32Address, 0U);
FLASHDRIVER_GetFlashConfig(pFlashParam->u32Address, &tFlash_api_cfg);
/* start erase */
__asm(" cpsid i");
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_EraseSector(&tFlash_api_cfg, FLASH_API_DISABLE, 0);
__asm(" cpsie i");
tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED;
/* check erase operation valid */
if (tRetVal != FLASH_ERROR_OK)
{
/* erase operation failed, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
/* check erasing still in progress */
tRetVal = FLASH_ERROR_FAILED;
u32TryCount = 0;
while ((tRetVal != FLASH_ERROR_OK) && (u32TryCount++ < 100000))
{
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_HV_Status_Check();
/* check if finished */
if (u32Temp == STATUS_HVOP)
{
tRetVal = FLASH_ERROR_FAILED;
}
else
{
tRetVal = FLASH_ERROR_OK;
}
}
if (tRetVal != FLASH_ERROR_OK)
{
/* erasing timeout, exit */
*(uint32_t*)(0x00000014U) = *((uint32_t*)0x40020004U);
break;
}
else
{
/* check erasing result */
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_EraseSector_Clear();
tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED;
if (tRetVal != FLASH_ERROR_OK)
{
/* erasing failed, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
if (tRetVal != FLASH_ERROR_OK)
{
/* erasing failed, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
/* trigger watchdog function */
if (pFlashParam->wdTriggerFct != ((void *)0))
{
pFlashParam->wdTriggerFct();
}
}
}
}
}
/* lock sector */
FLASHDRIVER_PFlashLockSector(pFlashParam->u32Address, 1U);
}
}
return tRetVal;
}
/**
* \brief PFlash Driver Function for Writing
*
* \param pFlashParam flash driver write parameter
* \return ErrorType
*/
FLASH_StatusType FLASHDRIVER_PFlashWrite(FLASH_DRIVER_ParamType *pFlashParam)
{
uint32_t u32Addr, u32Length, u32DataAddr, u32AlignLen, u32TempLen;
/* uint8_t *pTempBuf; */
uint32_t u32AlignOffset, u32Index, u32Count;
uint32_t u32TryCount;
FLASH_DRV_PRGM_CFG_T tFlash_api_cfg;
FLASH_StatusType tRetVal;
uint32_t u32Temp;
tRetVal = FLASH_ERROR_OK;
u32Addr = pFlashParam->u32Address;
u32Length = pFlashParam->u32Length;
pFlashParam->u32ErrorAddress = 0x0U;
tRetVal = FLASHDRIVER_PFlashWriteCheck(pFlashParam);
if (tRetVal == FLASH_ERROR_OK)
{
/* config flash wdog */
//ConfigFlashWdog();
s_pFlashDriver_RomApiHeader->FLASH_DRV_ENABLE_HOLD_CFG(FLASH_AUTO_HOLD_ENABLE);
/* align address, write must align to FLASH_PROGRAM_PAGE_MAX_SIZE */
u32AlignOffset = u32Addr & (PFLASH_PROGRAM_PAGE_MAX_SIZE - 1U);
u32AlignLen = u32Length + u32AlignOffset;
u32Count = u32AlignLen & (PFLASH_PROGRAM_PAGE_MAX_SIZE - 1U);
u32Count = u32Count > 0U ? 1U : 0U;
u32Count += u32AlignLen / PFLASH_PROGRAM_PAGE_MAX_SIZE;
u32DataAddr = (uint32_t)pFlashParam->pData;
u32TempLen = u32AlignLen;
for (u32Index = 0U; u32Index < u32Count; u32Index++)
{
/* real write length in this cycle */
u32TempLen = u32Length + u32AlignOffset;
u32TempLen = u32TempLen >= PFLASH_PROGRAM_PAGE_MAX_SIZE ? PFLASH_PROGRAM_PAGE_MAX_SIZE : u32TempLen;
u32TempLen -= u32AlignOffset;
pFlashParam->u32Address = u32Addr;
pFlashParam->u32Length = u32TempLen;
/* unlock sector */
FLASHDRIVER_PFlashLockSector(pFlashParam->u32Address, 0U);
tFlash_api_cfg.pgff = FLASH_REG_BIT_CFG_DISABLE;
tFlash_api_cfg.dest = pFlashParam->u32Address;
tFlash_api_cfg.size = (pFlashParam->u32Length / 4); /* one data is 4 bytes */
tFlash_api_cfg.pData = (uint32_t *)u32DataAddr;
tFlash_api_cfg.wdg_tune = WDG_TUNE_DISABLE;
/* next address and length */
u32Addr += u32TempLen;
u32DataAddr += u32TempLen;
u32Length -= u32TempLen;
u32AlignOffset = 0U;
/* start write */
__asm(" cpsid i");
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_Program(&tFlash_api_cfg, FLASH_API_DISABLE, 0);
__asm(" cpsie i");
tRetVal = u32Temp == STATUS_SUCCESS ? FLASH_ERROR_OK : FLASH_ERROR_FAILED;
/* check erase operation valid */
if (tRetVal != FLASH_ERROR_OK)
{
/* write operation failed, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
/* FLASHDRIVER_LL_Delay(); */
/* check write still in progress */
tRetVal = FLASH_ERROR_FAILED;
u32TryCount = 0;
while ((tRetVal != FLASH_ERROR_OK) && (u32TryCount++ < 10000))
{
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_HV_Status_Check();
/* check if finished */
if (u32Temp == STATUS_HVOP)
{
tRetVal = FLASH_ERROR_FAILED;
}
else
{
tRetVal = FLASH_ERROR_OK;
}
}
if (tRetVal != FLASH_ERROR_OK)
{
/* erasing timeout, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
/* check write result */
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_Program_Clear();
tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED;
if (tRetVal != FLASH_ERROR_OK)
{
/* write failed, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
/* trigger watchdog function */
if (pFlashParam->wdTriggerFct != ((void *)0))
{
pFlashParam->wdTriggerFct();
}
}
}
}
/* lock sector */
FLASHDRIVER_PFlashLockSector(pFlashParam->u32Address, 1U);
}
}
return tRetVal;
}
/**
* \brief DFlash Driver Function for Erasing
*
* \param pFlashParam flash driver erase parameter
* \return ErrorType
*/
FLASH_StatusType FLASHDRIVER_DFlashEraseSector(FLASH_DRIVER_ParamType *pFlashParam)
{
uint32_t u32Addr, u32Length;
uint32_t u32TryCount;
FLASH_DRV_ERASESECTOR_CFG_T tFlash_api_cfg;
FLASH_StatusType tRetVal;
uint32_t u32Temp;
tRetVal = FLASH_ERROR_OK;
u32Addr = pFlashParam->u32Address;
u32Length = pFlashParam->u32Length;
tRetVal = FLASH_ERROR_OK;
pFlashParam->u32ErrorAddress = 0x0U;
tRetVal = FLASHDRIVER_LL_DFlashEraseCheck(pFlashParam);
if (tRetVal == FLASH_ERROR_OK)
{
/* config flash wdog */
//ConfigFlashWdog();
s_pFlashDriver_RomApiHeader->FLASH_DRV_ENABLE_HOLD_CFG(FLASH_AUTO_HOLD_ENABLE);
pFlashParam->u32Length = DFLASH_ERASE_SECTOR_SIZE;
/* loop erase */
for (pFlashParam->u32Address = u32Addr; pFlashParam->u32Address < u32Addr + u32Length;
pFlashParam->u32Address += DFLASH_ERASE_SECTOR_SIZE)
{
/* unlock data flash */
FLASHDRIVER_DFlashLockSector(pFlashParam->u32Address, 0U);
FLASHDRIVER_GetFlashConfig(pFlashParam->u32Address, &tFlash_api_cfg);
/* start erase */
__asm(" cpsid i");
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_EraseSector(&tFlash_api_cfg, FLASH_API_DISABLE, 0);
__asm(" cpsie i");
tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED;
/* check erase operation valid */
if (tRetVal != FLASH_ERROR_OK)
{
/* erase operation failed, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
/* check erasing still in progress */
tRetVal = FLASH_ERROR_FAILED;
u32TryCount = 0;
while ((tRetVal != FLASH_ERROR_OK) && (u32TryCount++ < 100000))
{
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_HV_Status_Check();
/* check if finished */
if (u32Temp == STATUS_HVOP)
{
tRetVal = FLASH_ERROR_FAILED;
}
else
{
tRetVal = FLASH_ERROR_OK;
}
}
if (tRetVal != FLASH_ERROR_OK)
{
/* erasing timeout, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
/* check erasing result */
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_EraseSector_Clear();
tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED;
if (tRetVal != FLASH_ERROR_OK)
{
/* erasing failed, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
if (tRetVal != FLASH_ERROR_OK)
{
/* erasing failed, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
/* trigger watchdog function */
if (pFlashParam->wdTriggerFct != ((void *)0))
{
pFlashParam->wdTriggerFct();
}
}
}
}
}
/* lock data flash */
FLASHDRIVER_DFlashLockSector(pFlashParam->u32Address, 1U);
}
}
return tRetVal;
}
/**
* \brief DFlash Driver Function for Writing
*
* \param pFlashParam flash driver write parameter
* \return ErrorType
*/
FLASH_StatusType FLASHDRIVER_DFlashWrite(FLASH_DRIVER_ParamType *pFlashParam)
{
uint32_t u32Addr, u32Length, u32DataAddr, u32AlignLen, u32TempLen;
/* uint8_t *pTempBuf; */
uint32_t u32AlignOffset, u32Index, u32Count;
uint32_t u32TryCount;
FLASH_DRV_PRGM_CFG_T tFlash_api_cfg;
FLASH_StatusType tRetVal;
uint32_t u32Temp;
tRetVal = FLASH_ERROR_OK;
u32Addr = pFlashParam->u32Address;
u32Length = pFlashParam->u32Length;
pFlashParam->u32ErrorAddress = 0x0U;
tRetVal = FLASHDRIVER_DFlashWriteCheck(pFlashParam);
if (tRetVal == FLASH_ERROR_OK)
{
/* config flash wdog */
//ConfigFlashWdog();
s_pFlashDriver_RomApiHeader->FLASH_DRV_ENABLE_HOLD_CFG(FLASH_AUTO_HOLD_ENABLE);
/* align address, write must align to FLASH_PROGRAM_PAGE_MAX_SIZE */
u32AlignOffset = u32Addr & (DFLASH_PROGRAM_PAGE_MAX_SIZE - 1U);
u32AlignLen = u32Length + u32AlignOffset;
u32Count = u32AlignLen & (DFLASH_PROGRAM_PAGE_MAX_SIZE - 1U);
u32Count = u32Count > 0U ? 1U : 0U;
u32Count += u32AlignLen / DFLASH_PROGRAM_PAGE_MAX_SIZE;
u32DataAddr = (uint32_t)pFlashParam->pData;
u32TempLen = u32AlignLen;
for (u32Index = 0U; u32Index < u32Count; u32Index++)
{
/* real write length in this cycle */
u32TempLen = u32Length + u32AlignOffset;
u32TempLen = u32TempLen >= DFLASH_PROGRAM_PAGE_MAX_SIZE ? DFLASH_PROGRAM_PAGE_MAX_SIZE : u32TempLen;
u32TempLen -= u32AlignOffset;
pFlashParam->u32Address = u32Addr;
pFlashParam->u32Length = u32TempLen;
/* unlock sector */
FLASHDRIVER_DFlashLockSector(pFlashParam->u32Address, 0U);
tFlash_api_cfg.pgff = FLASH_REG_BIT_CFG_DISABLE;
tFlash_api_cfg.dest = pFlashParam->u32Address;
tFlash_api_cfg.size = (pFlashParam->u32Length / 4); /* one data is 4 bytes */
tFlash_api_cfg.pData = (uint32_t *)u32DataAddr;
tFlash_api_cfg.wdg_tune = WDG_TUNE_DISABLE;
/* next address and length */
u32Addr += u32TempLen;
u32DataAddr += u32TempLen;
u32Length -= u32TempLen;
u32AlignOffset = 0U;
/* start write */
__asm(" cpsid i");
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_Program(&tFlash_api_cfg, FLASH_API_DISABLE, 0);
__asm(" cpsie i");
tRetVal = u32Temp == STATUS_SUCCESS ? FLASH_ERROR_OK : FLASH_ERROR_FAILED;
/* check erase operation valid */
if (tRetVal != FLASH_ERROR_OK)
{
/* write operation failed, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
/* FLASHDRIVER_LL_Delay(); */
/* check write still in progress */
tRetVal = FLASH_ERROR_FAILED;
u32TryCount = 0;
while ((tRetVal != FLASH_ERROR_OK) && (u32TryCount++ < 10000))
{
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_HV_Status_Check();
/* check if finished */
if (u32Temp == STATUS_HVOP)
{
tRetVal = FLASH_ERROR_FAILED;
}
else
{
tRetVal = FLASH_ERROR_OK;
}
}
if (tRetVal != FLASH_ERROR_OK)
{
/* erasing timeout, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
/* check write result */
u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_Program_Clear();
tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED;
if (tRetVal != FLASH_ERROR_OK)
{
/* write failed, exit */
pFlashParam->u32ErrorAddress = pFlashParam->u32Address;
break;
}
else
{
/* trigger watchdog function */
if (pFlashParam->wdTriggerFct != ((void *)0))
{
pFlashParam->wdTriggerFct();
}
}
}
}
/* lock data flash */
FLASHDRIVER_DFlashLockSector(pFlashParam->u32Address, 1U);
}
}
return tRetVal;
}

2810
Src/fc7xxx_driver_flexcan.c Normal file
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197
Src/fc7xxx_driver_fmc.c Normal file
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@ -0,0 +1,197 @@
/**
* @file fc7xxx_driver_fmc.c
* @author Flagchip
* @brief FC7xxx Fmc driver source code
* @version 0.1.0
* @date 2024-1-5
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-1-5 Flagchip120 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_fmc.h"
/* ################################################################################## */
/* ####################################### Macro #################################### */
/* ################################################################################## */
/* ################################ Local Variables ################################# */
static FMC_Type *const s_apFmcBase[FMC_INSTANCE_COUNT] = FMC_BASE_PTRS;
/* ################################################################################## */
/* ########################### Local Prototype Functions ############################ */
/**
* \brief FMC PFlash Driver Function for lock/unlock sector
*
* \param pFMC FMC instance
* \param u32Address sector address
* \param bLock 0U-unlock, 1U-lock
*/
static FMC_Lock_StatusType FMCDRIVER_PFlashLockRegion(const FMC_InstanceType eInstance, uint32_t u32Address, uint8_t bLock);
/**
* \brief FMC DFlash Driver Function for lock/unlock sector
*
* \param pFMC FMC instance
* \param u32Address sector address
* \param bLock 0U-unlock, 1U-lock
*/
static FMC_Lock_StatusType FMCDRIVER_DFlashLockRegion(const FMC_InstanceType eInstance, uint32_t u32Address, uint8_t bLock);
/* ################################################################################## */
/* ########################### Global Prototype Functions ########################### */
/* ################################################################################## */
/* ################################ Local Functions ################################# */
/**
* \brief FMC PFlash Driver Function for lock/unlock sector
*
* \param eInstance FMC instance
* \param u32Address sector address
* \param bLock 0U-unlock, 1U-lock
*/
static FMC_Lock_StatusType FMCDRIVER_PFlashLockRegion(const FMC_InstanceType eInstance, uint32_t u32Address, uint8_t bLock)
{
FMC_Type *const pFMC = s_apFmcBase[eInstance];
FMC_Lock_StatusType tRetVal;
uint32_t u32Index;
uint32_t u32Length;
uint32_t u32Temp;
tRetVal = FMC_LOCK_ERROR_OK;
/* 1 bank contains more than 256KB, used FB_CPELCK for first and last 256KB used FB_FPELCK */
if ((u32Address >= PFLASH_ADDR_START) && (u32Address <= (PFLASH_ADDR_START + PFLASH_TOTAL_SIZE)))
{
/* PFLASH bank index */
u32Index = (u32Address - PFLASH_ADDR_START) / PFLASH_BANK_SIZE;
u32Length = ((u32Address - PFLASH_ADDR_START) % PFLASH_BANK_SIZE) ;
if (u32Length < (PFLASH_BANK_SIZE - FLASH_256KB_SIZE)) /* first 768KB */
{
u32Temp = ((uint32_t)1UL << ((u32Address - PFLASH_ADDR_START - PFLASH_BANK_SIZE * u32Index) >> 16));
u32Temp = bLock ? (FMC_HWA_GetFBCPELCKValue(pFMC, u32Index) | u32Temp) : (FMC_HWA_GetFBCPELCKValue(pFMC, u32Index) & ~u32Temp);
FMC_HWA_SetFBCPELCKValue(pFMC, u32Index, u32Temp);
}
else /* last 256KB */
{
u32Temp = ((u32Address - PFLASH_ADDR_START - PFLASH_BANK_SIZE * u32Index - PFLASH_PHANTOM_OFFSET) >> 13);
u32Temp = ((uint32_t)1UL << u32Temp);
u32Temp = bLock ? (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) | u32Temp) : (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) & ~u32Temp);
FMC_HWA_SetFBFPELCKValue(pFMC, u32Index, u32Temp);
}
}
else
{
tRetVal = FMC_LOCK_ERROR_INVALID_ADDR;
}
return tRetVal;
}
/**
* \brief FMC DFlash Driver Function for lock/unlock sector
*
* \param eInstance FMC instance
* \param u32Address sector address
* \param bLock 0U-unlock, 1U-lock
*/
static FMC_Lock_StatusType FMCDRIVER_DFlashLockRegion(const FMC_InstanceType eInstance, uint32_t u32Address, uint8_t bLock)
{
FMC_Type *const pFMC = s_apFmcBase[eInstance];
FMC_Lock_StatusType tRetVal;
uint32_t u32Index;
uint32_t u32Temp;
tRetVal = FMC_LOCK_ERROR_OK;
/* 1 bank contains only 128KB, only used FB_FPELCK */
u32Index = 2U;
if ((u32Address >= DFLASH_ADDR_START) && (u32Address <= DFLASH_ADDR_END))
{
u32Temp = 1UL << ((u32Address - DFLASH_ADDR_START - DFLASH_BANK0_SIZE * (u32Index - 2U)) >> 13);
u32Temp = bLock ? (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) | u32Temp) : (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) & ~u32Temp);
FMC_HWA_SetFBFPELCKValue(pFMC, u32Index, u32Temp);
}
else
{
tRetVal = FMC_LOCK_ERROR_INVALID_ADDR;
}
return tRetVal;
}
/* ################################################################################## */
/* ################################# Global Functions ############################### */
/**
* \brief FMC Driver Function for flash lock
*
* \param pFmcParam FMC driver flash lock parameter
* \return ErrorType
*/
FMC_Lock_StatusType FMCDRIVER_FlashLock(FMC_DRIVER_Lock_ParamType *pFmcParam)
{
uint32_t u32Addr, u32Length, u32LockSize, u32TempAddr;
FMC_Lock_StatusType tRetVal;
tRetVal = FMC_LOCK_ERROR_OK;
u32Addr = pFmcParam->u32Address;
u32Length = pFmcParam->u32Length;
u32LockSize = (pFmcParam->bClass == FMC_Page) ? FLASH_PROGRAM_PAGE_SIZE : FLASH_ERASE_SECTOR_SIZE;
/* Address and length should aligned by page/sector */
if (pFmcParam->u32Address & (u32LockSize - 1U))
{
tRetVal = FMC_LOCK_ERROR_INVALID_ADDR;
pFmcParam->u32ErrorAddress = pFmcParam->u32Address;
}
if (pFmcParam->u32Length & (u32LockSize - 1U))
{
tRetVal = FMC_LOCK_ERROR_INVALID_SIZE;
pFmcParam->u32ErrorAddress = pFmcParam->u32Address;
}
if (tRetVal == FMC_LOCK_ERROR_OK)
{
for (u32TempAddr = u32Addr; u32TempAddr < u32Addr + u32Length; u32TempAddr += u32LockSize)
{
if (pFmcParam->bFlash == FMC_PFlash)
{
tRetVal = FMCDRIVER_PFlashLockRegion(pFmcParam->bFMC, u32TempAddr, pFmcParam->bLock);
}
else
{
tRetVal = FMCDRIVER_DFlashLockRegion(pFmcParam->bFMC, u32TempAddr, pFmcParam->bLock);
}
}
}
return tRetVal;
}
/**
* \brief FMC set ota active block
*
* \param eInstance FMC instance
* \param bLock 0U-active block 0, 1U-active block 1
*/
void FMCDRIVER_SwapBlock(const FMC_InstanceType eInstance, FMC_API_ACTIVE_BLOCK_TYPE bActive)
{
FMC_Type *const pFMC = s_apFmcBase[eInstance];
if (0U == FMC_HWA_GetOTACtrlValue(pFMC, 0))
{
FMC_HWA_SetOTAActive(pFMC, 0, bActive);
FMC_HWA_SetOTAEnable(pFMC, 0);
}
}

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/**
* @file fc7xxx_driver_fpu.c
* @author Flagchip051
* @brief FC4xxx FPU driver type definition and API
* @version 0.1.0
* @date 2024-01-11
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_fpu.h"
/* Note: library user should add interrupt stack support, add compiler support */
/*
* @details @verbatim
If only want use FPU,
1) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard) -> FPU Type set to "fpv5-sp-d16"
2) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> GNU Arm Cross C Compiler -> Preprocessor -> Defined symbols(-D) -> Add "__FPU_PRESENT=1" (without ")
3) and call FPU_Enable to enable FPU at the beginning of program.
If want to use DSP,
1) configure FCIDE to enable FPU compiler support, Properties -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard)
2) add MACRO "DRIVER_CM7_DSP_ENABLE" in FCIDE Properties -> C/C++ General -> Paths and Symbols -> Symbols -> GNU C and GNU C++ and Assembly
3) add Include Path to project Properties -> C/C++ General -> Paths and Symbols -> Includes -> GNU C and GNU C++ and Assembly:
../../../../../../Template/Device/CMSIS5_590/DSP/Include
../../../../../../Template/Device/CMSIS5_590/Core/Include
../../../../../../Template/Device/CMSIS5_590/DSP/PrivateInclude
4) and call FPU_Enable to enable FPU at the beginning of program.
@endverbatim
*/
void FPU_Enable(void)
{
FPU_HWA_Enable(); /* set CP10 and CP11 Full Access */
__DSB();
__ISB();
}
void FPU_Disable(void)
{
FPU_HWA_Disable(); /* Access denied. Any attempted access generates a NOCP UsageFault */
}

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/**
* @file fc7xxx_driver_freqm.c
* @author Flagchip
* @brief FC7xxx FREQM driver type definition and API
* @version 0.1.0
* @date 2024-01-14
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_freqm.h"
#include "fc7xxx_driver_pcc.h"
#include "interrupt_manager.h"
/********* Local variable ************/
static FREQM_Type * const pFreqmPtrs = FREQM;
static FREQM_MesCntStartCallBackType s_pMesCntStartCallback = NULL;
static FREQM_MesCntStopCallBackType s_pMesCntStopCallback = NULL;
static FREQM_RefCntStopCallBackType s_pRefCntStopCallback = NULL;
static FREQM_FaultCallBackType s_pFaultCallback = NULL;
/********* Global Functions ************/
/**
* @brief Initialize FREQM configuration
*
* @param pInitStruct the basic configurations of the FREQM
* @return FREQM_StatusType whether the operation is successfully
*/
FREQM_StatusType FREQM_Init(const FREQM_InitType *const pInitStruct)
{
FREQM_StatusType eRet = FREQM_STATUS_SUCCESS;
if (NULL == pInitStruct)
{
eRet = FREQM_STATUS_PARAM_INVALID;
}
else
{
/* Configure the clock divider value */
FREQM_HWA_MesClk_PreDiv(pFreqmPtrs,pInitStruct->u8PredivVal);
/* Select the clock source to be measured */
FREQM_HWA_MesClkSel(pFreqmPtrs,pInitStruct->eClkSel);
/* Set and clear the S/W reset */
PCC_GenPeripheralReset(PCC_CLK_FREQM);
/* Configure the measure counter targer value */
FREQM_HWA_SetMesLength(pFreqmPtrs,pInitStruct->u32MesLen);
/* Configure the reference counter target value */
FREQM_HWA_SetRefTimeout(pFreqmPtrs,pInitStruct->u32RefTo);
}
return eRet;
}
/**
* @brief De-initialize the FREQM
*
* @param eInstance the selected FREQM
* @return FREQM_StatusType whether the operation is successfully
*/
FREQM_StatusType FREQM_DeInit()
{
FREQM_StatusType eStatus = FREQM_STATUS_SUCCESS;
/* Set register to reset value */
FREQM_HWA_MesClk_PreDiv(pFreqmPtrs,0U);
FREQM_HWA_MesClkSel(pFreqmPtrs,(FREQM_MesClkSelType)0);
FREQM_HWA_SetMesLength(pFreqmPtrs,0xFFFFFFFFU);
FREQM_HWA_SetRefTimeout(pFreqmPtrs,0xFFFFFFFFU);
FREQM_HWA_DisableCntEventInterrupt(pFreqmPtrs);
s_pMesCntStartCallback = NULL;
s_pMesCntStopCallback = NULL;
s_pRefCntStopCallback = NULL;
s_pFaultCallback = NULL;
return eStatus;
}
/**
* @brief Clear all FREQM status
*
* @return FREQM_StatusType whether the operation is successfully
*/
FREQM_StatusType FREQM_ClearStatus()
{
FREQM_StatusType eStatus = FREQM_STATUS_SUCCESS;
uint32_t u32TimeOutVal = 0xffff;
uint32_t u32CntStatus;
FREQM_HWA_SetRefCnt(pFreqmPtrs,0U);
do
{
u32CntStatus = FREQM_HWA_GetCntStatus(pFreqmPtrs);
u32TimeOutVal--;
}while(u32CntStatus!=0U);
if(u32TimeOutVal == 0U)
{
eStatus = FREQM_STATUS_TIMEOUT;
}
return eStatus;
}
/**
* @brief Start the reference/measure counter
*
*/
void FREQM_StartMeasureCnt()
{
FREQM_HWA_SetMesCnt(pFreqmPtrs,0U);
}
/**
* @brief Get saved reference counter value
*
* @return uint32_t saved reference counter value
*/
uint32_t FREQM_GetRefCntSave()
{
return FREQM_HWA_GetRefCntSave(pFreqmPtrs);
}
/**
* @brief FREQM initialize interrupt function
*
* @param pIntStruct FREQM interrupt structure
* @return FREQM_StatusType whether the operation is successfully
*/
FREQM_StatusType FREQM_InterruptInit(const FREQM_InterruptType *const pIntrStruct)
{
FREQM_StatusType eStatus = FREQM_STATUS_SUCCESS;
FREQM_HWA_EnableCntEventInterrupt(pFreqmPtrs);
/*register callback functions*/
s_pMesCntStartCallback = pIntrStruct->pMesCntStartCallback;
s_pMesCntStopCallback = pIntrStruct->pMesCntStopCallback;
s_pRefCntStopCallback = pIntrStruct->pRefCntStopCallback;
s_pFaultCallback = pIntrStruct->pFaultCallback;
return eStatus;
}
/**
* @brief Interrupt IRQ handle of FREQM
*
*/
void FREQM_IRQHandler(void)
{
uint32_t u32CntStatus;
bool bIntFlag;
bIntFlag = FREQM_HWA_GetInterruptFlag(pFreqmPtrs);
if(bIntFlag)
{
FREQM_HWA_ClearInterruptFlag(pFreqmPtrs);
}
u32CntStatus = FREQM_HWA_GetCntStatus(pFreqmPtrs);
if(u32CntStatus == FREQM_CNT_STATUS_MES_CNT_START_MASK)//0x4
{
s_pMesCntStartCallback();
}
else if(u32CntStatus == (FREQM_CNT_STATUS_MES_CNT_START_MASK|FREQM_CNT_STATUS_MES_CNT_STOP_MASK) )//0x6
{
s_pMesCntStopCallback();
}
else if(u32CntStatus == (FREQM_CNT_STATUS_MES_CNT_START_MASK|FREQM_CNT_STATUS_MES_CNT_STOP_MASK|FREQM_CNT_STATUS_REF_CNT_STOP_MASK) )//0x7
{
s_pRefCntStopCallback();
}
else
{
s_pFaultCallback();
}
}

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Src/fc7xxx_driver_ftu.c Normal file
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Src/fc7xxx_driver_gpio.c Normal file
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/**
* @file fc7xxx_driver_gpio.h
* @author Flagchip
* @brief FC7xxx GPIO driver type definition and API
* @version 0.1.0
* @date 2023-2-14
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 31/12/2022 Flagchip0121 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_gpio.h"
/** @brief Gpio instance list */
static GPIO_Type *s_pGpioInstanceTable[GPIO_INSTANCE_COUNT] = GPIO_BASE_PTRS;
/**
* @brief Initialize GPIO.
*
* @param eGpio GPIO instance
* @param pInitStruct Initialization structure of GPIO.
*/
GPIO_StatusType GPIO_InitPins(const GPIO_InstanceType eGpio, const GPIO_InitType *const pInitStruct)
{
GPIO_StatusType eRet = GPIO_STATUS_SUCCESS;
GPIO_Type *pGpio;
uint32_t u32TempPins = 0U;
uint8_t u8PinIndex = 0U;
if ((uint32_t)eGpio >= GPIO_INSTANCE_COUNT)
{
eRet = GPIO_STATUS_PARAM_INVALID;
}
else
{
pGpio = s_pGpioInstanceTable[(uint32_t)(eGpio)];
u32TempPins = pInitStruct->u32GpioPins;
while (u32TempPins != 0u)
{
if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u)
{
if (GPIO_OUT == pInitStruct->ePinDirection)
{
if (GPIO_LOW == pInitStruct->ePinLevel)
{
GPIO_HWA_ClearPinOutput(pGpio, u8PinIndex);
}
else
{
GPIO_HWA_SetPinOutput(pGpio, u8PinIndex);
}
GPIO_HWA_SetPinDirection(pGpio, u8PinIndex);
}
else if (GPIO_IN == pInitStruct->ePinDirection)
{
GPIO_HWA_ClearPinDirection(pGpio, u8PinIndex);
}
else
{
GPIO_HWA_SetPinInputDisable(pGpio, u8PinIndex); /* GPIO_ZERO == pInitStruct->ePinDirection */
}
}
else
{
}
u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex);
u8PinIndex++;
}
}
return eRet;
}
/**
* @brief De-initialize the GPIO pin
*
* @param eGpio Gpio instance enumeration
* @param u32Pins The bit of u32Pins indicate the Pin number of this Gpio instance.
* @return GPIO status type.
*/
GPIO_StatusType GPIO_Deinit(const GPIO_InstanceType eGpio, const uint32_t u32Pins)
{
DEV_ASSERT(eGpio < GPIO_INSTANCE_COUNT);
GPIO_StatusType eRet = GPIO_STATUS_SUCCESS;
GPIO_Type *pGpio = s_pGpioInstanceTable[(uint32_t)(eGpio)];
uint8_t u8PinIndex = 0U;
uint32_t u32TempPins = u32Pins;
while (u32TempPins != 0)
{
if (u32TempPins & ((uint32_t)1 << u8PinIndex))
{
GPIO_HWA_ClearPinDirection(pGpio, u8PinIndex);
GPIO_HWA_ClearPinDataOutput(pGpio, u8PinIndex);
GPIO_HWA_ClearPinInputDisable(pGpio, u8PinIndex);
}
u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex);
u8PinIndex++;
}
return eRet;
}
/**
* @brief Read level of input port pins.
*
* @param eGpio Port instance for GPIO functionality
* @param u32Pins The bit of u32Pins indicate the pin number of this Port.
* @return Pins level
*/
uint32_t GPIO_ReadPins(const GPIO_InstanceType eGpio, const uint32_t u32Pins)
{
DEV_ASSERT(eGpio < GPIO_INSTANCE_COUNT);
GPIO_Type *pGpio = s_pGpioInstanceTable[(uint32_t)eGpio];
return (GPIO_HWA_ReadPortDataInput(pGpio) & u32Pins);
}
/**
* @brief Write gpio level to u32Pins.
*
* @param eGpio Port instance for GPIO functionality
* @param u32Pins The bit of u32Pins indicate the pin number of this Port.
* @param eOutput Output level enumeration
* @return Port return type.
*/
GPIO_StatusType GPIO_WritePins(const GPIO_InstanceType eGpio, const uint32_t u32Pins, const GPIO_PinLevelType eOutput)
{
GPIO_StatusType eRet = GPIO_STATUS_SUCCESS;
GPIO_Type *pGpio = s_pGpioInstanceTable[(uint32_t)eGpio];
if (((uint32_t)eGpio >= GPIO_INSTANCE_COUNT) || (eOutput > GPIO_HIGH))
{
eRet = GPIO_STATUS_PARAM_INVALID;
}
else
{
if (GPIO_HIGH == eOutput)
{
GPIO_HWA_SetPortOutput(pGpio, u32Pins);
}
else
{
GPIO_HWA_ClearPortOutput(pGpio, u32Pins);
}
}
return eRet;
}
/**
* @brief Toggle gpio api
*
* @param eGpio eGpio Port instance for GPIO functionality
* @param u32Pins The bit of u32Pins indicate the pin number of this Port.
* @return Port return type.
*/
GPIO_StatusType GPIO_Toggle(const GPIO_InstanceType eGpio, const uint32_t u32Pins)
{
GPIO_StatusType eRet = GPIO_STATUS_SUCCESS;
GPIO_Type *pGpio = s_pGpioInstanceTable[(uint32_t)eGpio];
if ((uint32_t)(eGpio >= GPIO_INSTANCE_COUNT))
{
eRet = GPIO_STATUS_PARAM_INVALID;
}
else
{
GPIO_HWA_TogglePort(pGpio, u32Pins);
}
return eRet;
}

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/**
* @file fc7xxx_driver_hsm.c
* @author Flagchip0103
* @brief FC7xxx HSM driver source file
* @version 0.1.0
* @date 2023-12-20
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-20 Flagchip0103 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_hsm.h"
/* ################################################################################## */
/* ##################################### Macros ##################################### */
typedef enum {
HSM_CMD_ID_TRNG = 0xb55du,
HSM_CMD_ID_SHA = 0xfce2u,
HSM_CMD_ID_ECC_SIGN = 0xde41u,
HSM_CMD_ID_ECC_VERIFY = 0xa522u,
HSM_CMD_ID_SM2_GENKEYPAIR = 0xc9ddu,
HSM_CMD_ID_SM2_ENCRY = 0x30f1u,
HSM_CMD_ID_SM2_DECRY = 0x6351u,
HSM_CMD_ID_SM2_SIGN = 0xe814u,
HSM_CMD_ID_SM2_VERIFY = 0x6e1eu,
HSM_CMD_ID_SM2_GENZA = 0xdbbeu,
HSM_CMD_ID_SM2_GENHASH = 0x5ce5u,
HSM_CMD_ID_SM4_ENCRY = 0xfd5au,
HSM_CMD_ID_SM4_DECRY = 0x4aedu,
HSM_CMD_ID_ECC_ENCRY = 0x4d3fu,
HSM_CMD_ID_ECC_DECRY = 0x97e4u,
HSM_CMD_ID_REQUEST_AUTH = 0x33d9u,
HSM_CMD_ID_LIFECYCLE_CHANGE = 0xbe63u, /* prefa,fa not support in sdk */
HSM_CMD_ID_DEBUG_AUTH = 0x3928u, // TODO: delete
HSM_CMD_ID_ISP_AUTH = 0xAFBAu, // TODO: delete
HSM_CMD_ID_REVOKE_MRK = 0x19bbu, // TODO: delete
HSM_CMD_ID_REVOKE_UMRK = 0xfdb4u, // TODO: delete
HSM_CMD_ID_USER_KEY_ERASE = 0xac3au, // TODO: delete
HSM_CMD_ID_FLASHTEST_VERIFY = 0xcc29u, // TODO: delete
HSM_CMD_ID_UESR_CODE_VERIFY = 0x72d6u, // TODO: delete
HSM_CMD_ID_CANCEL_JOB = 0x17c3u,
HSM_CMD_ID_SELF_TEST = 0x4e93u,
HSM_CMD_ID_NVR_OTP = 0x2cd8u,
HSM_CMD_ID_LIFECYCLE_CHANGE_TAKE_EFFECT = 0x30fau,
HSM_CMD_ID_USER_KEY_MANAGE = 0xf4cfu,
HSM_CMD_ID_SPACE_MANAGE = 0x4ac0u,
HSM_CMD_ID_AES_ENCRY = 0xa2c6u,
HSM_CMD_ID_AES_DECRY = 0x6576u,
HSM_CMD_ID_CMAC_GEN = 0xf0b9u,
HSM_CMD_ID_XMAC_GEN = 0x32acu,
HSM_CMD_ID_CCM_ENCRY = 0x862fu,
HSM_CMD_ID_CCM_DECRY = 0x79a4u,
HSM_CMD_ID_GCM_ENCRY = 0xd1a6u,
HSM_CMD_ID_GCM_DECRY = 0xc0a3u,
HSM_CMD_ID_MD5 = 0x9371u,
HSM_CMD_ID_SM3 = 0xcfe5u,
HSM_CMD_ID_MONOTONIC_COUNTER = 0xdc97u,
HSM_CMD_ID_RSA = 0x866cu,
HSM_CMD_ID_USRK_GEN = 0xddb7u, // TODO: delete
HSM_CMD_ID_LOAD_FIRMWARE = 0x503du,
HSM_CMD_ID_DH_SM = 0x7F8Au,
HSM_CMD_ID_ECDH = 0x4b06u,
HSM_CMD_ID_DH = 0xb81bu,
HSM_CMD_ID_DH_PBKDF2 = 0xa47du,
HSM_CMD_ID_DH_GMPBKDF = 0xbe1fu,
HSM_CMD_ID_SCATTER_HASH = 0x465du,
HSM_CMD_ID_RAW_AESM = 0x42fdu,
HSM_CMD_ID_SCATTER_MAC = 0xa9e1u,
HSM_CMD_ID_ECC_GENKEYPAIR = 0x16b6u,
HSM_CMD_ID_RSA_SSA_PKCS1V15_SIGN = 0xd047u,
HSM_CMD_ID_RSA_SSA_PSS_SIGN = 0xd873u,
HSM_CMD_ID_RSA_ES_PKCS1V15_ENCRYPT = 0x3090u,
HSM_CMD_ID_RSA_ES_OAEP_ENCRYPT = 0x7F0Bu,
HSM_CMD_ID_RSA_SSA_PKCS1V15_VERIFY = 0x1577u,
HSM_CMD_ID_RSA_SSA_PSS_VERIFY = 0x0076u,
HSM_CMD_ID_RSA_ES_PKCS1V15_DECRYPT = 0x26d5u,
HSM_CMD_ID_RSA_ES_OAEP_DECRYPT = 0xc284u,
} HSM_CmdIdType;
#define HSMCOM_TRNG_SRC_0 0x40cau
#define HSMCOM_TRNG_SRC_1 0xc51cu
#define HSMCOM_TRNG_SRC_ANY 0x359bu
#define HSMCOM_TRNG_SRC_XOR 0x80a5u
#define HSMCOM_DRNG_SRC 0x648Cu
#define HSMCOM_LIFECYCLE_OEM_DEV 0x4792u
#define HSMCOM_LIFECYCLE_OEM_PDT 0xA4F1u
#define HSMCOM_LIFECYCLE_IN_FIELD 0xaddcu
#define HSMCOM_INCREASE_COUNTER 0xd27fu
#define HSMCOM_READ_COUNTER 0x1875u
#define HSMCOM_SET_COUNTER_VAL 0x439du
#define HSMCOM_INCREASE_COUNTER_WHEN_EQUAL 0x6834u
#define HSMCOM_READ_ALL_FLEX_COUNTERS 0x6a47u
#define HSMCOM_SET_SINGLE_CFG 0x9e4du
#define HSMCOM_GET_SINGLE_CFG 0xaf42u
#define HSMCOM_INCREASE_COUNTER2 0xd280u
#define HSMCOM_READ_COUNTER2 0x1876u
#define HSMCOM_NVR_OTP_READ 0x9C2Fu
#define HSMCOM_NVR_OTP_WRITE 0x358Cu
#define HSMCOM_KEYMANAGER_IMPORT_USER_KEY 0xdcf1u
#define HSMCOM_KEYMANAGER_REVOKE_USER_KEY 0x7278u
#define HSMCOM_KEYMANAGER_EXPORT_USER_KEY 0xd8c9u
#define HSMCOM_KEYMANAGER_GEN_UESR_KEY 0x1853u
#define HSMCOM_KEYMANAGER_ENABLE_KEY_RAM_COPY 0x5ec5u
#define HSMCOM_KEYMANAGER_DISABLE_KEY_RAM_COPY 0x5918u
#define HSMCOM_KEYSPACE_GET_STATUS 0xe39cu
#define HSMCOM_KEYSPACE_NEATEN 0xb12bu
#define HSMCOM_REVOK_UMRK0 0x5edcu
#define HSMCOM_REVOK_UMRK1 0x20d9u
#define HSMCOM_REVOK_UMRK2 0x6ba1u
#define HSMCOM_REVOK_UMRK3 0xac50u
/* ################################################################################## */
/* ################################# Local Variables ################################ */
#define AUTH_CHECK_DATA_BYTE_CNT 32
static uint32_t s_aHsmDat[8];
static HSMCom_AuthCheckType s_tHsmDummyCfg = {0, 0, &(s_aHsmDat[0]), &(s_aHsmDat[0]), &(s_aHsmDat[0]), &(s_aHsmDat[0]), &(s_aHsmDat[0]), AUTH_CHECK_DATA_BYTE_CNT};
/* ################################################################################## */
/* ########################### Local Functions Prototype ############################ */
/* ################################################################################## */
/* ################################# Local Functions ############################### */
static HSM_StatusType hsm_assign_val(HSM_CmdType *pCmd, uint32_t u32Cmd, uint32_t u32Address)
{
HSM_StatusType eRet = HSM_STATUS_SUCCESS;
if (NULL != pCmd)
{
pCmd->u32Cmd = u32Cmd;
pCmd->u32Addr = u32Address;
}
else
{
eRet = HSM_STATUS_PARAM_ERR;
}
return eRet;
}
/* ################################################################################## */
/* ################################# Global Functions ############################### */
HSM_StatusType HSM_TrueRandGetSrc0(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_TRNG << 16u) | HSMCOM_TRNG_SRC_0, (uint32_t)pCfg);
}
HSM_StatusType HSM_TrueRandGetSrc1(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_TRNG << 16u) | HSMCOM_TRNG_SRC_1, (uint32_t)pCfg);
}
HSM_StatusType HSM_TrueRandGetSrcXor(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_TRNG << 16) | HSMCOM_TRNG_SRC_XOR, (uint32_t)pCfg);
}
HSM_StatusType HSM_TrueRandGet(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_TRNG << 16) | HSMCOM_TRNG_SRC_ANY, (uint32_t)pCfg);
}
HSM_StatusType HSM_PseudoRandGet(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_TRNG << 16) | HSMCOM_DRNG_SRC, (uint32_t)pCfg);
}
HSM_StatusType HSM_Sha(HSM_CmdType *pCmd, const HSMCom_ShaType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SHA << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_ShaEx(HSM_CmdType *pCmd, const HSMCom_Sha2Type *pCfg)
{
uint32_t u32CtrBits = (pCfg->tCfg.eInputFmt & 0x1) | ((pCfg->tCfg.eOutputFmt & 0x1) << 1);
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SHA << 16) | u32CtrBits, (uint32_t)pCfg);
}
HSM_StatusType HSM_HashInitEx(HSM_CmdType *pCmd, const HSMCom_ShaType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_HASH << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_HashUpdateEx(HSM_CmdType *pCmd, const HSMCom_ShaType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_HASH << 16) | 5u, (uint32_t)pCfg);
}
HSM_StatusType HSM_HashFinallyEx(HSM_CmdType *pCmd, const HSMCom_ShaType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_HASH << 16) | 6u, (uint32_t)pCfg);
}
HSM_StatusType HSM_CmacAesm(HSM_CmdType *pCmd, const HSMCom_AesmRawApiType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RAW_AESM << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_CmacScatter(HSM_CmdType *pCmd, const HSMCom_ScatterMacType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_MAC << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_EccSign(HSM_CmdType *pCmd, const HSMCom_EccSignType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECC_SIGN << 16 | 1u), (uint32_t)pCfg);
}
HSM_StatusType HSM_EccVerify(HSM_CmdType *pCmd, const HSMCom_EccVerifyType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECC_VERIFY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_EccGenKeyPair(HSM_CmdType *pCmd, const HSMCom_EccKeyPairGenType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECC_GENKEYPAIR << 16 | 1u), (uint32_t)pCfg);
}
HSM_StatusType HSM_Sm2GenKeyPair(HSM_CmdType *pCmd, const HSMCom_Sm2GenKeyPairType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_GENKEYPAIR << 16 | 1u), (uint32_t)pCfg);
}
HSM_StatusType HSM_Sm2Encry(HSM_CmdType *pCmd, const HSMCom_Sm2EncryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_ENCRY << 16 | 1u), (uint32_t)pCfg);
}
HSM_StatusType HSM_Sm2Decry(HSM_CmdType *pCmd, const HSMCom_Sm2DecryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_DECRY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_Sm2Sign(HSM_CmdType *pCmd, const HSMCom_Sm2SignType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_SIGN << 16 | 1u), (uint32_t)pCfg);
}
HSM_StatusType HSM_Sm2Verify(HSM_CmdType *pCmd, const HSMCom_Sm2VerifyType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_VERIFY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_Sm2GenZa(HSM_CmdType *pCmd, const HSMCom_Sm2GenZaType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_GENZA << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_Sm2GenHash(HSM_CmdType *pCmd, const HSMCom_Sm2GenHashType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_GENHASH << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_Sm4Encrypt(HSM_CmdType *pCmd, const HSMCom_Sm4EncryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM4_ENCRY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_Sm4Decrypt(HSM_CmdType *pCmd, const HSMCom_Sm4DecryptType *pCfg)
{
return hsm_assign_val(pCmd, (HSM_CMD_ID_SM4_DECRY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_EccEasyEncry(HSM_CmdType *pCmd, const HSMCom_EccEasyEncryType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECC_ENCRY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_EccEasyDecry(HSM_CmdType *pCmd, const HSMCom_EccEasyDecryType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECC_DECRY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_EccPointCalc(HSM_CmdType *pCmd, const HSMCom_EccCalcType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECC_DECRY << 16) | 1u, (uint32_t)pCfg);
}
HSM_StatusType HSM_ScatterHashInit(HSM_CmdType *pCmd, const HSMCom_ScatterHashType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_HASH << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_ScatterHashUpdate(HSM_CmdType *pCmd, const HSMCom_ScatterHashType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_HASH << 16) | 5u, (uint32_t)pCfg);
}
HSM_StatusType HSM_ScatterHashFinally(HSM_CmdType *pCmd, const HSMCom_ScatterHashType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_HASH << 16) | 6u, (uint32_t)pCfg);
}
HSM_StatusType HSM_RequestAuthorization(HSM_CmdType *pCmd, const HSMCom_RequestAuthType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_REQUEST_AUTH << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_OemDevEnter(HSM_CmdType *pCmd)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_LIFECYCLE_CHANGE << 16) | HSMCOM_LIFECYCLE_OEM_DEV, (uint32_t)(&s_tHsmDummyCfg));
}
HSM_StatusType HSM_OemPdtEnter(HSM_CmdType *pCmd)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_LIFECYCLE_CHANGE << 16) | HSMCOM_LIFECYCLE_OEM_PDT, (uint32_t)(&s_tHsmDummyCfg));
}
HSM_StatusType HSM_InFieldEnter(HSM_CmdType *pCmd)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_LIFECYCLE_CHANGE << 16) | HSMCOM_LIFECYCLE_IN_FIELD, (uint32_t)(&s_tHsmDummyCfg));
}
HSM_StatusType HSM_CancelJob(HSM_CmdType *pCmd, const HSMCom_CancelJobType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CANCEL_JOB << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_SelfTest(HSM_CmdType *pCmd, const HSMCom_SelfTestType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SELF_TEST << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_NvrOtpProgram(HSM_CmdType *pCmd, const HSMCom_NvrOtpType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_NVR_OTP << 16) | HSMCOM_NVR_OTP_WRITE, (uint32_t)pCfg);
}
HSM_StatusType HSM_NvrOtpRead(HSM_CmdType *pCmd, const HSMCom_NvrOtpType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_NVR_OTP << 16) | HSMCOM_NVR_OTP_READ, (uint32_t)pCfg);
}
HSM_StatusType HSM_TakeEffect(HSM_CmdType *pCmd)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_LIFECYCLE_CHANGE_TAKE_EFFECT << 16), (uint32_t)0);
}
HSM_StatusType HSM_UserKeyRevoke(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_MANAGE << 16) | HSMCOM_KEYMANAGER_REVOKE_USER_KEY, (uint32_t)pCfg);
}
HSM_StatusType HSM_UserKeyImport(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_MANAGE << 16) | HSMCOM_KEYMANAGER_IMPORT_USER_KEY, (uint32_t)pCfg);
}
HSM_StatusType HSM_UserKeyExport(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_MANAGE << 16) | HSMCOM_KEYMANAGER_EXPORT_USER_KEY, (uint32_t)pCfg);
}
HSM_StatusType HSM_EraseKeyFlash(HSM_CmdType *pCmd, HSMCom_BasicType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_ERASE << 16) | 0xa80f, (uint32_t)pCfg);
}
HSM_StatusType HSM_UserKeyGen(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_MANAGE << 16) | HSMCOM_KEYMANAGER_GEN_UESR_KEY, (uint32_t)pCfg);
}
HSM_StatusType HSM_EnableKeyRamCopy(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_MANAGE << 16) | HSMCOM_KEYMANAGER_ENABLE_KEY_RAM_COPY, (uint32_t)pCfg);
}
HSM_StatusType HSM_DisableKeyRamCopy(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_MANAGE << 16) | HSMCOM_KEYMANAGER_DISABLE_KEY_RAM_COPY, (uint32_t)pCfg);
}
HSM_StatusType HSM_GetKeySpaceStatus(HSM_CmdType *pCmd, const HSMCom_KeySpaceStatusType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SPACE_MANAGE << 16) | HSMCOM_KEYSPACE_GET_STATUS, (uint32_t)pCfg);
}
HSM_StatusType HSM_TidyUpKeySpace(HSM_CmdType *pCmd, const HSMCom_KeySpaceStatusType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SPACE_MANAGE << 16) | HSMCOM_KEYSPACE_NEATEN, (uint32_t)pCfg);
}
HSM_StatusType HSM_AesEncrypt(HSM_CmdType *pCmd, const HSMCom_AesEncryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_AES_ENCRY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_Aes_FlexEncrypt(HSM_CmdType *pCmd, const HSMCom_FlexAesEncryptType *pCfg)
{
uint32_t u32CtrBits =0x1 |
((pCfg->tCfg.epad & 0x1) << 1) | ((pCfg->tCfg.eInputFmt & 0x1) << 2) |
((pCfg->tCfg.eOutputFmt & 0x1) << 3) | ((pCfg->tCfg.eBackend & 0x1) << 4) ;
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_AES_ENCRY << 16) | u32CtrBits, (uint32_t)pCfg);
}
HSM_StatusType HSM_AesDecrypt(HSM_CmdType *pCmd, const HSMCom_AesDecryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_AES_DECRY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_Aes_FlexDecrypt(HSM_CmdType *pCmd, const HSMCom_FlexAesDecryptType *pCfg)
{
uint32_t u32CtrBits = 0x1 |
((pCfg->tCfg.epad & 0x1) << 1) | ((pCfg->tCfg.eInputFmt & 0x1) << 2) |
((pCfg->tCfg.eOutputFmt & 0x1) << 3) | ((pCfg->tCfg.eBackend & 0x1) << 4) ;
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_AES_DECRY << 16) | u32CtrBits, (uint32_t)pCfg);
}
HSM_StatusType HSM_CMac(HSM_CmdType *pCmd, const HSMCom_CMacType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CMAC_GEN << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_CmacEx(HSM_CmdType *pCmd, const HSMCom_CMacExType *pCfg)
{
uint32_t u32CtrBits = (pCfg->tCfg.eBackend & 0x1) | ((pCfg->tCfg.eInputFmt & 0x1) << 1) | ((pCfg->tCfg.eOutputFmt & 0x1) << 2);
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CMAC_GEN << 16) | u32CtrBits, (uint32_t)pCfg);
}
HSM_StatusType HSM_XMac(HSM_CmdType *pCmd, const HSMCom_XMacType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_XMAC_GEN << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_XMacEx(HSM_CmdType *pCmd, const HSMCom_XMacExType *pCfg)
{
uint32_t u32CtrBits = (pCfg->tCfg.eBackend & 0x1) | ((pCfg->tCfg.eInputFmt & 0x1) << 1) | ((pCfg->tCfg.eOutputFmt & 0x1) << 2);
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_XMAC_GEN << 16) | u32CtrBits, (uint32_t)pCfg);
}
HSM_StatusType HSM_CcmEncry(HSM_CmdType *pCmd, const HSMCom_CcmEncryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CCM_ENCRY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_CcmEncryEx(HSM_CmdType *pCmd, const HSMCom_CcmEncryptExType *pCfg)
{
uint32_t u32CtrBits = (pCfg->tCfg.eBackend & 0x1);
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CCM_ENCRY << 16) | u32CtrBits, (uint32_t)pCfg);
}
HSM_StatusType HSM_CcmDecry(HSM_CmdType *pCmd, const HSMCom_CcmDecryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CCM_DECRY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_CcmDecryEx(HSM_CmdType *pCmd, const HSMCom_CcmDecryptExType *pCfg)
{
uint32_t u32CtrBits = (pCfg->tCfg.eBackend & 0x1);
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CCM_DECRY << 16) | u32CtrBits, (uint32_t)pCfg);
}
HSM_StatusType HSM_GcmEncry(HSM_CmdType *pCmd, const HSMCom_GcmEncryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_GCM_ENCRY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_GcmEncryEx(HSM_CmdType *pCmd, const HSMCom_GcmEncryptExType *pCfg)
{
uint32_t u32CtrBits = (pCfg->tCfg.eBackend & 0x1);
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_GCM_ENCRY << 16) | u32CtrBits, (uint32_t)pCfg);
}
HSM_StatusType HSM_GcmDecry(HSM_CmdType *pCmd, const HSMCom_GcmDecryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_GCM_DECRY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_GcmDecryEx(HSM_CmdType *pCmd, const HSMCom_GcmDecryptExType *pCfg)
{
uint32_t u32CtrBits = (pCfg->tCfg.eBackend & 0x1);
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_GCM_DECRY << 16) | u32CtrBits, (uint32_t)pCfg);
}
HSM_StatusType HSM_Md5(HSM_CmdType *pCmd, const HSMCom_Md5Type *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MD5 << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_Md5Ex(HSM_CmdType *pCmd, const HSMCom_Md5Type *pCfg)
{
uint32_t u32CtrBits = (pCfg->tCfg.eIntputFmt & 0x1) | ((pCfg->tCfg.eOutputFmt & 0x1) << 1);
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MD5 << 16) | u32CtrBits, (uint32_t)pCfg);
}
HSM_StatusType HSM_Sm3(HSM_CmdType *pCmd, const HSMCom_Sm3Type *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM3 << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_Sm3Ex(HSM_CmdType *pCmd, const HSMCom_Sm3Type *pCfg)
{
uint32_t u32CtrBits = (pCfg->tCfg.eIntputFmt & 0x1) | ((pCfg->tCfg.eOutputFmt & 0x1) << 1);
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM3 << 16) | u32CtrBits, (uint32_t)pCfg);
}
HSM_StatusType HSM_MonotonicCounterIncrease(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_INCREASE_COUNTER, (uint32_t)pCfg);
}
HSM_StatusType HSM_MonotonicCounterRead(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_READ_COUNTER, (uint32_t)pCfg);
}
HSM_StatusType HSM_MonotonicCounterSetValue(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_SET_COUNTER_VAL, (uint32_t)pCfg);
}
HSM_StatusType HSM_MonotonicIncCountWhenEqu(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_INCREASE_COUNTER_WHEN_EQUAL, (uint32_t)pCfg);
}
HSM_StatusType HSM_MonotonicReadAllFlexCounters(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_READ_ALL_FLEX_COUNTERS, (uint32_t)pCfg);
}
HSM_StatusType HSM_MonotonicCounterSetSingleCfg(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_SET_SINGLE_CFG, (uint32_t)pCfg);
}
HSM_StatusType HSM_MonotonicCounterGetSingleCfg(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_GET_SINGLE_CFG, (uint32_t)pCfg);
}
HSM_StatusType HSM_MonotonicIncreaseCounter2(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_INCREASE_COUNTER2, (uint32_t)pCfg);
}
HSM_StatusType HSM_MonotonicReadCounter2(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_READ_COUNTER2, (uint32_t)pCfg);
}
HSM_StatusType HSM_Rsa(HSM_CmdType *pCmd, const HSMCom_RsaType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_RSA_SSA_PSS_Sign(HSM_CmdType *pCmd, const HSMCom_RsaSsaPssSignType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_SSA_PSS_SIGN << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_RSA_SSA_PSS_Verify(HSM_CmdType *pCmd, const HSMCom_RsaSsaPssVerifyType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_SSA_PSS_VERIFY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_RSA_SSA_ES_PKCS1V15_Encrypt(HSM_CmdType *pCmd, const HSMCom_RsaEsPkcs1V15EncryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_ES_PKCS1V15_ENCRYPT << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_RSA_SSA_ES_PKCS1V15_Decrypt(HSM_CmdType *pCmd, const HSMCom_RsaEsPkcs1V15DecryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_ES_PKCS1V15_DECRYPT << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_RSA_SSA_ES_PKCS1V15_Verify(HSM_CmdType *pCmd, const HSMCom_RsaSsaPkcs1V15VerifyType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_SSA_PKCS1V15_VERIFY << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_RSA_SSA_ES_PKCS1V15_Sign(HSM_CmdType *pCmd, const HSMCom_RsaSsaPkcs1V15SignType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_SSA_PKCS1V15_SIGN << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_RSA_SSA_ES_OAEP_Encrypt(HSM_CmdType *pCmd, const HSMCom_RsaEsOaepEncryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_ES_OAEP_ENCRYPT << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_RSA_SSA_ES_OAEP_Decrypt(HSM_CmdType *pCmd, const HSMCom_RsaEsOaepDecryptType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_ES_OAEP_DECRYPT << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_BigNumberCalc(HSM_CmdType *pCmd, const HSMCom_BigNumberCalcType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA << 16) | 1u, (uint32_t)pCfg);
}
HSM_StatusType HSM_LoadFirmware(HSM_CmdType *pCmd)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_LOAD_FIRMWARE << 16), (uint32_t)0);
}
HSM_StatusType HSM_SMDH(HSM_CmdType *pCmd, HSMCom_SmDHType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_DH_SM << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_ECDH(HSM_CmdType *pCmd, HSMCom_ECDHType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECDH << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_DH(HSM_CmdType *pCmd, HSMCom_RsaDHType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_DH << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_PBKDF2(HSM_CmdType *pCmd, HSMCom_Pbkdf2Type *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_DH_PBKDF2 << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_GMPBKDF(HSM_CmdType *pCmd, HSMCom_GMpbkdfType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_DH_GMPBKDF << 16), (uint32_t)pCfg);
}
HSM_StatusType HSM_RevokeUmrk0(HSM_CmdType *pCmd)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_REVOKE_UMRK << 16)|HSMCOM_REVOK_UMRK0, (uint32_t)0);
}
HSM_StatusType HSM_RevokeUmrk1(HSM_CmdType *pCmd)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_REVOKE_UMRK << 16)|HSMCOM_REVOK_UMRK1, (uint32_t)0);
}
HSM_StatusType HSM_RevokeUmrk2(HSM_CmdType *pCmd)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_REVOKE_UMRK << 16)|HSMCOM_REVOK_UMRK2, (uint32_t)0);
}
HSM_StatusType HSM_RevokeUmrk3(HSM_CmdType *pCmd)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_REVOKE_UMRK << 16)|HSMCOM_REVOK_UMRK3, (uint32_t)0);
}
HSM_StatusType HSM_GenUsrk(HSM_CmdType *pCmd,const HSMCom_RsaType *pCfg)
{
return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USRK_GEN << 16), (uint32_t)pCfg);
}

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/**
* @file fc7xxx_driver_intm.c
* @author Flagchip
* @brief FC7240 INTM driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version
******************************************************************************** */
#include "fc7xxx_driver_intm.h"
#include "interrupt_manager.h"
/* ################################################################################## */
/* ##################################### Macros ##################################### */
/* ################################################################################## */
/* ################################# Local Variables ################################ */
static INTM_Type *const s_aIntm_Base[INTM_INSTANCE_MAX] = INTM_BASE_PTRS;
static INTM_ISRCallbackType s_aIntmISRCallback[INTM_INSTANCE_MAX][INTM_IRQ_MONITOR_MAX] = {NULL};
/* ################################################################################## */
/* ########################### Local Functions Prototype ############################ */
void INTM0_IRQHandler(void);
void INTMn_IRQHandler(INTM_InstanceType eInstance);
/* ################################################################################## */
/* ################################# Local Functions ############################### */
/* ################################################################################## */
/* ################################# Global Functions ############################### */
INTM_ReturnType INTM_Init(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex, INTM_InitType *pInitCfg)
{
INTM_MonitorType *pMonitor;
if ((NULL == pInitCfg) || (eInstance >= INTM_INSTANCE_MAX) || (eIrqMonitorIndex >= INTM_IRQ_MONITOR_MAX))
{
return INTM_RETURN_E_PARAM;
}
if (pInitCfg->u32SrcDelayCnt >= 0xFFFFFFU)
{
return INTM_RETURN_E_PARAM;
}
if (pInitCfg->u16IrqNumber >= IRQn_MAX)
{
return INTM_RETURN_E_PARAM;
}
pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], (uint8_t)eIrqMonitorIndex);
INTM_HWA_SetIRQReqNum(pMonitor, pInitCfg->u16IrqNumber);
INTM_HWA_EnableReset(pMonitor, pInitCfg->bEnReset);
INTM_HWA_EnableInterrupt(pMonitor, pInitCfg->bEnInterrupt);
INTM_HWA_SetLatency(pMonitor, pInitCfg->u32SrcDelayCnt);
if (pInitCfg->eMode == INTM_INTERRUPT_MODE_INACTIVE)
{
INTM_HWA_EnableInactiveMode(pMonitor, true);
}
else
{
INTM_HWA_EnableInactiveMode(pMonitor, false);
}
s_aIntmISRCallback[eInstance][eIrqMonitorIndex] = pInitCfg->pIntmIsrCallback;
return INTM_RETURN_OK;
}
INTM_ReturnType INTM_enable(INTM_InstanceType eInstance, bool bEnable)
{
if (eInstance >= INTM_INSTANCE_MAX)
{
return INTM_RETURN_E_PARAM;
}
INTM_HWA_Enable(s_aIntm_Base[eInstance], bEnable);
return INTM_RETURN_OK;
}
INTM_ReturnType INTM_StartInactiveMode(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex)
{
INTM_MonitorType *pMonitor;
if ((eInstance >= INTM_INSTANCE_MAX) || (eIrqMonitorIndex >= INTM_IRQ_MONITOR_MAX))
{
return INTM_RETURN_E_PARAM;
}
pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], (uint8_t)eIrqMonitorIndex);
INTM_HWA_StartInactiveMode(pMonitor);
return INTM_RETURN_OK;
}
INTM_ReturnType INTM_StopInactiveMode(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex)
{
INTM_MonitorType *pMonitor;
if ((eInstance >= INTM_INSTANCE_MAX) || (eIrqMonitorIndex >= INTM_IRQ_MONITOR_MAX))
{
return INTM_RETURN_E_PARAM;
}
pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], (uint8_t)eIrqMonitorIndex);
INTM_HWA_StopInactiveMode(pMonitor);
return INTM_RETURN_OK;
}
INTM_ReturnType INTM_SetAcknowledge(INTM_InstanceType eInstance, uint16_t u16IrqNumber)
{
if (eInstance >= INTM_INSTANCE_MAX)
{
return INTM_RETURN_E_PARAM;
}
INTM_HWA_SetIACKR(s_aIntm_Base[eInstance], u16IrqNumber);
return INTM_RETURN_OK;
}
uint32_t INTM_GetCounterValue(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex)
{
INTM_MonitorType *pMonitor;
if ((eInstance >= INTM_INSTANCE_MAX) || (eIrqMonitorIndex >= INTM_IRQ_MONITOR_MAX))
{
return 0;
}
pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], (uint8_t)eIrqMonitorIndex);
return INTM_HWA_GetTimerCounter(pMonitor);
}
INTM_ReturnType INTM_ClearIntFlag(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex)
{
INTM_MonitorType *pMonitor;
if ((eInstance >= INTM_INSTANCE_MAX) || (eIrqMonitorIndex >= INTM_IRQ_MONITOR_MAX))
{
return INTM_RETURN_E_PARAM;
}
pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], (uint8_t)eIrqMonitorIndex);
INTM_HWA_SetTimerCounter(pMonitor, 0U);
return INTM_RETURN_OK;
}
bool INTM_GetTimeoutStatus(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex)
{
INTM_MonitorType *pMonitor;
if ((eInstance >= INTM_INSTANCE_MAX) || (eIrqMonitorIndex >= INTM_IRQ_MONITOR_MAX))
{
return false;
}
pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], (uint8_t)eIrqMonitorIndex);
return INTM_HWA_ReadStatus(pMonitor);
}
void INTMn_IRQHandler(INTM_InstanceType eInstance)
{
uint8_t u8i;
INTM_MonitorType *pMonitor;
for (u8i = 0; u8i < (uint8_t)INTM_IRQ_MONITOR_MAX; u8i++)
{
pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], u8i);
if (INTM_HWA_ReadStatus(pMonitor))
{
if (s_aIntmISRCallback[eInstance][u8i] != NULL)
{
s_aIntmISRCallback[eInstance][u8i]();
}
}
}
}
void INTM0_IRQHandler(void)
{
INTMn_IRQHandler(INTM_INSTANCE_0);
}

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/**
* @file fc7xxx_driver_ism.c
* @author Flagchip
* @brief FC7xxx ISM driver type definition and API
* @version 0.1.0
* @date 2023-02-13
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-1-10 Flagchip095 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_ism.h"
/* ################################################################################## */
/* ####################################### Macro #################################### */
#define FPC_INSTANCE_COUNT (16U)
#define LAM_INSTANCE_COUNT (16U)
#define ECM_INSTANCE_COUNT (4U)
/* ################################################################################## */
/* ################################### Type define ################################## */
/* ################################################################################## */
/* ################################ Local Variables ################################# */
static ISM_Type *const s_apIsmBase[ISM_INSTANCE_COUNT] = ISM_BASE_PTRS;
static ISM_EventISRCallbackType s_apEventISRCallback = NULL;
static FPC_ISRCallbackType s_apFpcISRCallback[FPC_INSTANCE_COUNT] = {NULL};
static LAM_ISRCallbackType s_apLamOverFlowIsrCallback[LAM_INSTANCE_COUNT] = {NULL};
/* ################################################################################## */
/* ########################### Local Prototype Functions ############################ */
/* ################################################################################## */
/* ######################### Global prototype Functions ############################ */
void ISM0_IRQHandler(void);
/* ################################################################################## */
/* ################################ Local Functions ################################ */
/* ################################################################################## */
/* ################################ Global Functions ################################ */
void ISM_Init(const ISM_InitCfgType *pInitConfig)
{
ISM_Type *pIsm = ISM;
DEV_ASSERT(ISM_HWA_PARAM_ECMC(pIsm) == ECM_INSTANCE_COUNT);
DEV_ASSERT(ISM_HWA_PARAM_FPC(pIsm) == FPC_INSTANCE_COUNT);
DEV_ASSERT(ISM_HWA_PARAM_LAM(pIsm) == LAM_INSTANCE_COUNT);
DEV_ASSERT(pInitConfig != NULL);
s_apEventISRCallback = pInitConfig->pEventIsrCallback;
ISM_HWA_InterruptEnable(pIsm, pInitConfig->bIntEnable);
}
uint8_t ISM_GetEcmEventHappenedChannels(void)
{
ISM_Type *pIsm = ISM;
return (uint8_t)ISM_HWA_GetEcs(pIsm);
}
uint16_t ISM_GetLamEventHappenedChannels(void)
{
ISM_Type *pIsm = ISM;
return ISM_HWA_GetEs(pIsm);
}
void ISM_ClearEcmEventHappenedChannels(uint8_t u8Channels)
{
ISM_Type *pIsm = ISM;
ISM_HWA_ClearEcs(pIsm, (uint32_t)u8Channels);
}
void ISM_ClearLamEventHappenedChannels(uint16_t u16Channels)
{
ISM_Type *pIsm = ISM;
ISM_HWA_ClearEs(pIsm, (uint32_t)u16Channels);
}
void ISM_EnableEcmSystemEvent(uint32_t u32Channels, bool bEnable)
{
ISM_Type *pIsm = ISM;
ISM_HWA_EnableEcmSystemEvent(pIsm, u32Channels, bEnable);
}
void ISM_EnableLamSystemEvent(uint32_t u32Channels, bool bEnable)
{
ISM_Type *pIsm = ISM;
ISM_HWA_EnableLamSystemEvent(pIsm, u32Channels, bEnable);
}
void ISM_EcmEventConfig(uint8_t u8LamIndex, uint8_t u8EcmIndex, uint8_t u8EventCount)
{
ISM_Type *pIsm = ISM;
DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT);
DEV_ASSERT(u8EcmIndex < ECM_INSTANCE_COUNT);
if (u8EcmIndex == 0U)
{
ISM_HWA_SetEcm0EcCtrl(pIsm, u8EventCount, u8LamIndex);
}
else if (u8EcmIndex == 1U)
{
ISM_HWA_SetEcm1EcCtrl(pIsm, u8EventCount, u8LamIndex);
}
else if (u8EcmIndex == 2U)
{
ISM_HWA_SetEcm2EcCtrl(pIsm, u8EventCount, u8LamIndex);
}
else if (u8EcmIndex == 3U)
{
ISM_HWA_SetEcm3EcCtrl(pIsm, u8EventCount, u8LamIndex);
}
else
{
}
}
void ISM_ClearLamStatusCounter(uint8_t u8LamIndex)
{
LAM_Type *pLam;
DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT);
pLam = ISM_HWA_GetLam(ISM, u8LamIndex);
ISM_HWA_ClearLamStatusCounter(pLam);
}
uint32_t ISM_GetLamStatusCounter(uint8_t u8LamIndex)
{
LAM_Type *pLam;
DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT);
pLam = ISM_HWA_GetLam(ISM, u8LamIndex);
return ISM_HWA_GetLamStatusCounter(pLam);
}
void ISM_ClearLamStatusOvfl(uint8_t u8LamIndex)
{
LAM_Type *pLam;
DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT);
pLam = ISM_HWA_GetLam(ISM, u8LamIndex);
ISM_HWA_ClearLamStatusOvfl(pLam);
}
bool ISM_GetLamStatusOvfl(uint8_t u8LamIndex)
{
LAM_Type *pLam;
DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT);
pLam = ISM_HWA_GetLam(ISM, u8LamIndex);
return ISM_HWA_GetLamStatusOvfl(pLam);
}
void ISM_Enable(bool bEnable)
{
ISM_Type *pIsm = ISM;
ISM_HWA_Enable(pIsm, bEnable);
}
void ISM_InterruptEnable(bool bEnable)
{
ISM_Type *pIsm = ISM;
ISM_HWA_InterruptEnable(pIsm, bEnable);
}
void ISM_LamOverflowInterruptEnable(uint8_t u8LamIndex, bool bEnable)
{
LAM_Type *pLam;
DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT);
pLam = ISM_HWA_GetLam(ISM, u8LamIndex);
ISM_HWA_SetLamCtrIen(pLam, bEnable);
}
void ISM_LamEnable(uint8_t u8LamIndex, bool bEnable)
{
LAM_Type *pLam;
DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT);
pLam = ISM_HWA_GetLam(ISM, u8LamIndex);
ISM_HWA_SetLamCtrEn(pLam, bEnable);
}
void ISM_LamConfig(uint8_t u8LamIndex, const ISM_LamCfgType *pConfig)
{
uint32_t u32TempValue = 0;
LAM_Type *pLam;
DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT);
DEV_ASSERT(pConfig != NULL);
pLam = ISM_HWA_GetLam(ISM, u8LamIndex);
ISM_HWA_SetLamCtrIen(pLam, pConfig->bOvflIntEnable);
ISM_HWA_SetLamCounter(pLam, pConfig->u32EvtCntThreshold);
u32TempValue |= ISM_LAM_CONFIG_RCS(pConfig->u8SrcSel);
u32TempValue |= ISM_LAM_CONFIG_MCS(pConfig->u8MonSel);
u32TempValue |= ISM_LAM_CONFIG_IVW(pConfig->eInvWin);
u32TempValue |= ISM_LAM_CONFIG_EDS(pConfig->eWinEdgSel);
u32TempValue |= ISM_LAM_CONFIG_EWS(pConfig->eEvtWinSel);
u32TempValue |= ISM_LAM_CONFIG_RMS(pConfig->eRunMode);
u32TempValue |= ISM_LAM_CONFIG_MOS(pConfig->eMonSrcSel);
u32TempValue |= ISM_LAM_CONFIG_IVM(pConfig->eInvMon);
u32TempValue |= ISM_LAM_CONFIG_IVR(pConfig->eInvRef);
s_apLamOverFlowIsrCallback[u8LamIndex] = pConfig->pLamOverFlowIsrCallback;
ISM_HWA_SetLamConfig(pLam, u32TempValue);
}
void ISM_FpcGlitchInterruptEnable(uint8_t u8FpcIndex, bool bEnable)
{
FPC_Type *pFpc;
DEV_ASSERT(u8FpcIndex < FPC_INSTANCE_COUNT);
pFpc = ISM_HWA_GetFpc(ISM, u8FpcIndex);
ISM_HWA_SetFpcCtrlIen(pFpc, bEnable);
}
void ISM_FpcEnable(uint8_t u8FpcIndex, bool bEnable)
{
FPC_Type *pFpc;
DEV_ASSERT(u8FpcIndex < FPC_INSTANCE_COUNT);
pFpc = ISM_HWA_GetFpc(ISM, u8FpcIndex);
ISM_HWA_SetFpcCtrlEn(pFpc, bEnable);
}
void ISM_FpcConfig(uint8_t u8FpcIndex, const ISM_FpcCfgType *pConfig)
{
uint32_t u32TempValue = 0;
FPC_Type *pFpc;
DEV_ASSERT(u8FpcIndex < FPC_INSTANCE_COUNT);
DEV_ASSERT(pConfig != NULL);
pFpc = ISM_HWA_GetFpc(ISM, u8FpcIndex);
ISM_HWA_SetFpcCtrlIen(pFpc, pConfig->bGlitchIntEnable);
u32TempValue |= ISM_FPC_CONFIG_FED(pConfig->eFallingDelayNode);
u32TempValue |= ISM_FPC_CONFIG_FEG(pConfig->eFallingDetectMode);
u32TempValue |= ISM_FPC_CONFIG_RED(pConfig->eRisingDelayNode);
u32TempValue |= ISM_FPC_CONFIG_REG(pConfig->eRisingDetectMode);
u32TempValue |= ISM_FPC_CONFIG_CMP(pConfig->u32ThresholdValue);
s_apFpcISRCallback[u8FpcIndex] = pConfig->pFpcIsrCallback;
ISM_HWA_SetFpcConfig(pFpc, u32TempValue);
}
void ISM0_IRQHandler(void)
{
uint8_t u8i;
FPC_Type *pFpc;
LAM_Type *pLam;
uint8_t u8EcmFlags;
uint16_t u16LamFlags;
ISM_Type *pIsm = s_apIsmBase[ISM_INSTANCE_0];
u8EcmFlags = ISM_HWA_GetEcs(pIsm)&ISM_HWA_GetEnabledEcmSystemEvent(pIsm);
u16LamFlags = ISM_HWA_GetEs(pIsm)&ISM_HWA_GetEnabledLamSystemEvent(pIsm);
if (s_apEventISRCallback != NULL)
{
s_apEventISRCallback(u16LamFlags, u8EcmFlags);
}
ISM_HWA_ClearEcs(pIsm, u8EcmFlags);
ISM_HWA_ClearEs(pIsm, u16LamFlags);
for (u8i = 0; u8i < FPC_INSTANCE_COUNT; u8i++)
{
pFpc = ISM_HWA_GetFpc(s_apIsmBase[ISM_INSTANCE_0], u8i);
if (ISM_HWA_GetFpcCtrlIen(pFpc))
{
uint32_t u32Status = 0U;
if (ISM_HWA_GetFpcRgd(pFpc))
{
u32Status |= (uint32_t)FPC_RISING_GLITCH_DETECTED;
}
if (ISM_HWA_GetFpcFgd(pFpc))
{
u32Status |= (uint32_t)FPC_FALLING_GLITCH_DETECTED;
}
if (s_apFpcISRCallback[u8i] != NULL)
{
s_apFpcISRCallback[u8i](u32Status);
}
if ((u32Status & (uint32_t)FPC_RISING_GLITCH_DETECTED) == (uint32_t)FPC_RISING_GLITCH_DETECTED)
{
ISM_HWA_ClearFpcRgd(pFpc);
}
if ((u32Status & (uint32_t)FPC_FALLING_GLITCH_DETECTED) == (uint32_t)FPC_FALLING_GLITCH_DETECTED)
{
ISM_HWA_ClearFpcFgd(pFpc);
}
}
}
for (u8i = 0; u8i < LAM_INSTANCE_COUNT; u8i++)
{
pLam = ISM_HWA_GetLam(s_apIsmBase[ISM_INSTANCE_0], u8i);
if (ISM_HWA_GetLamCtrIen(pLam))
{
if (ISM_HWA_GetLamStatusOvfl(pLam))
{
if (s_apLamOverFlowIsrCallback[u8i] != NULL)
{
s_apLamOverFlowIsrCallback[u8i]();
}
}
ISM_HWA_ClearLamStatusOvfl(pLam);
}
}
}

1502
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/**
* @file fc7xxx_driver_lu.c
* @author Flagchip0103
* @brief FC7xxx LU driver type definition and API
* @version 0.1.0
* @date 2023-12-19
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-19 Flagchip0103 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_lu.h"
/**
* @brief Initialize Lu instance
*
* @param pInitStruct Lu initialization structure
* @return LU return type
*/
LU_StatusType LU_Init(const LU_InitType *const pInitStruct)
{
uint32_t u32TempReg, u32TempCfg;
LU_StatusType eRet = LU_STATUS_SUCCESS;
LU_Type* pLu = LU;
DEV_ASSERT(NULL_PTR != pInitStruct);
/* set AOI0 value */
LU_HWA_ConfigAOI0(pLu, pInitStruct->eLgNum, 0U);
/* set AOI1 value */
LU_HWA_ConfigAOI1(pLu, pInitStruct->eLgNum, 0U);
/* set CTRL value */
LU_HWA_ConfigCtrl(pLu, pInitStruct->eLgNum, 0U);
/* set FILT value */
LU_HWA_ConfigFilter(pLu, pInitStruct->eLgNum, 0U);
u32TempCfg = (uint32_t)0U |
LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi0Config.tIn0Config.eInNACfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi0Config.tIn0Config.eInNBCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi0Config.tIn0Config.eInNCCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi0Config.tIn0Config.eInNDCfg);
u32TempReg = (uint32_t)0U | LU_AOI_IN_N_CFG(LU_AOI_IN_0, u32TempCfg);
u32TempCfg = (uint32_t)0U |
LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi0Config.tIn1Config.eInNACfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi0Config.tIn1Config.eInNBCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi0Config.tIn1Config.eInNCCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi0Config.tIn1Config.eInNDCfg);
u32TempReg |= LU_AOI_IN_N_CFG(LU_AOI_IN_1, u32TempCfg);
u32TempCfg = (uint32_t)0U |
LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi0Config.tIn2Config.eInNACfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi0Config.tIn2Config.eInNBCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi0Config.tIn2Config.eInNCCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi0Config.tIn2Config.eInNDCfg);
u32TempReg |= LU_AOI_IN_N_CFG(LU_AOI_IN_2, u32TempCfg);
u32TempCfg = (uint32_t)0U |
LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi0Config.tIn3Config.eInNACfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi0Config.tIn3Config.eInNBCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi0Config.tIn3Config.eInNCCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi0Config.tIn3Config.eInNDCfg);
u32TempReg |= LU_AOI_IN_N_CFG(LU_AOI_IN_3, u32TempCfg);
/* set AOI0 value */
LU_HWA_ConfigAOI0(pLu, pInitStruct->eLgNum, u32TempReg);
u32TempCfg = (uint32_t)0U |
LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi1Config.tIn0Config.eInNACfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi1Config.tIn0Config.eInNBCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi1Config.tIn0Config.eInNCCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi1Config.tIn0Config.eInNDCfg);
u32TempReg = (uint32_t)0U | LU_AOI_IN_N_CFG(LU_AOI_IN_0, u32TempCfg);
u32TempCfg = (uint32_t)0U |
LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi1Config.tIn1Config.eInNACfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi1Config.tIn1Config.eInNBCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi1Config.tIn1Config.eInNCCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi1Config.tIn1Config.eInNDCfg);
u32TempReg |= LU_AOI_IN_N_CFG(LU_AOI_IN_1, u32TempCfg);
u32TempCfg = (uint32_t)0U |
LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi1Config.tIn2Config.eInNACfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi1Config.tIn2Config.eInNBCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi1Config.tIn2Config.eInNCCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi1Config.tIn2Config.eInNDCfg);
u32TempReg |= LU_AOI_IN_N_CFG(LU_AOI_IN_2, u32TempCfg);
u32TempCfg = (uint32_t)0U |
LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi1Config.tIn3Config.eInNACfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi1Config.tIn3Config.eInNBCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi1Config.tIn3Config.eInNCCfg) |
LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi1Config.tIn3Config.eInNDCfg);
u32TempReg |= LU_AOI_IN_N_CFG(LU_AOI_IN_3, u32TempCfg);
/* set AOI1 value */
LU_HWA_ConfigAOI1(pLu, pInitStruct->eLgNum, u32TempReg);
/* force bypass mode */
LU_HWA_SetLgBypassControl(pLu, pInitStruct->eLgNum, pInitStruct->eAoiMode);
/* set Flip-Flop mode configure */
LU_HWA_SetLgFlipFlopMode(pLu, pInitStruct->eLgNum, pInitStruct->eFFMode);
u32TempCfg = 0U;
if (pInitStruct->tSyncCtrl.bInputNA)
{
u32TempCfg |= LU_SYNC_CONTROL_INPUT_N(1U, LU_INPUT_N_A);
}
if (pInitStruct->tSyncCtrl.bInputNB)
{
u32TempCfg |= LU_SYNC_CONTROL_INPUT_N(1U, LU_INPUT_N_B);
}
if (pInitStruct->tSyncCtrl.bInputNC)
{
u32TempCfg |= LU_SYNC_CONTROL_INPUT_N(1U, LU_INPUT_N_C);
}
if (pInitStruct->tSyncCtrl.bInputND)
{
u32TempCfg |= LU_SYNC_CONTROL_INPUT_N(1U, LU_INPUT_N_D);
}
/* set LG inputs synchronous control */
LU_HWA_SetLgInputsSyncCtrl(pLu, pInitStruct->eLgNum, u32TempCfg);
if (LU_JKFF_MODE == pInitStruct->eFFMode)
{
/* set LG output feedback override control */
LU_HWA_SetLgFeedbackOverrideCtrl(pLu, pInitStruct->eLgNum, pInitStruct->eFbMode);
}
if (LU_OUTPUT_INIT_DISABLE > pInitStruct->eFFInitValue)
{
if (LU_OUTPUT_INIT_ONE == pInitStruct->eFFInitValue)
{
/* Configure the output of flip-flop as "1" */
LU_HWA_ConfigFlipFlopTo1(pLu, pInitStruct->eLgNum);
}
else
{
/* Configure the output of flip-flop as "0" */
LU_HWA_ConfigFlipFlopTo0(pLu, pInitStruct->eLgNum);
}
/* Flip-Flop initial output enable control */
LU_HWA_EnableControlFlipFlopInitOutput(pLu, pInitStruct->eLgNum);
}
/* set input filter sample count for AOI0 */
LU_HWA_SetAOI0InputFilterSampleCount(pLu, pInitStruct->eLgNum, (uint32_t)pInitStruct->u8Aoi0FiltCnt);
/* set input filter sample period for AOI0 */
LU_HWA_SetAOI0InputFilterSamplePeriod(pLu, pInitStruct->eLgNum, (uint32_t)pInitStruct->u8Aoi0Period);
/* set input filter sample count for AOI1 */
LU_HWA_SetAOI1InputFilterSampleCount(pLu, pInitStruct->eLgNum, (uint32_t)pInitStruct->u8Aoi1FiltCnt);
/* set input filter sample period for AOI0 */
LU_HWA_SetAOI1InputFilterSamplePeriod(pLu, pInitStruct->eLgNum, (uint32_t)pInitStruct->u8Aoi1Period);
return eRet;
}
/**
* @brief De-initialize Lu instance
* @param eLu LU instance
*/
void LU_Deinit()
{
uint8_t u8Index;
LU_Type* pLu = NULL_PTR;
for (u8Index = 0U; u8Index < (uint8_t)LG_CNT; u8Index++)
{
/* set AOI0 value */
LU_HWA_ConfigAOI0(pLu, (LU_LgType)u8Index, 0U);
/* set AOI1 value */
LU_HWA_ConfigAOI1(pLu, (LU_LgType)u8Index, 0U);
/* set CTRL value */
LU_HWA_ConfigCtrl(pLu, (LU_LgType)u8Index, 0U);
/* set FILT value */
LU_HWA_ConfigFilter(pLu, (LU_LgType)u8Index, 0U);
}
}

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/**
* @file fc7xxx_driver_mam.c
* @author Flagchip
* @brief FC7xxx MAM driver source code
* @version 0.1.0
* @date 2023-02-08
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip095 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_mam.h"
#include "interrupt_manager.h"
#define MAM0_MIN_ADDR 0x01000000U
#define MAM0_MAX_ADDR 0x4049FFFFU
#define ROM_START_ADDR 0x04800000U
#define ROM_END_ADDR 0x0481FFFFU
#define ROM_BLOCK_SIZE 0x20000U
#define FLASH0_START_ADDR 0x01000000U
#define FLASH0_END_ADDR 0x011FFFFFU
#define FLASH0_BLOCK_SIZE 0x20000U
#define NVR_START_ADDR 0x04400000U
#define NVR_END_ADDR 0x04411FFFU
#define NVR_BLOCK_SIZE 0x20000U
#define NVR_CFG_START_ADDR 0x04420000U
#define NVR_CFG_END_ADDR 0x04431FFFU
#define NVR_CFG_BLOCK_SIZE 0x20000U
#define FLASH1_START_ADDR 0x04000000U
#define FLASH1_END_ADDR 0x0401FFFFU
#define FLASH1_BLOCK_SIZE 0x2000U
#define SRAM_START_ADDR 0x21000000U
#define SRAM_END_ADDR 0x21017FFFU
#define SRAM_BLOCK_SIZE 0x4000U
#define CPU0_DTCM_START_ADDR 0x20000000U
#define CPU0_DTCM_END_ADDR 0x2001FFFFU
#define CPU0_DTCM_BLOCK_SIZE 0x4000U
#define CPU0_ITCM_START_ADDR 0x00000000U
#define CPU0_ITCM_END_ADDR 0x00007FFFU
#define CPU0_ITCM_BLOCK_SIZE 0x4000U
#define AFCB0_START_ADDR 0x40000000U
#define AFCB0_END_ADDR 0x4009FFFFU
#define AFCB0_BLOCK_SIZE 0x1000U
#define AFCB1_START_ADDR 0x40400000U
#define AFCB1_END_ADDR 0x4049FFFFU
#define AFCB1_BLOCK_SIZE 0x1000U
/**
* @brief Get mam information according to the address
*
* @param u32Addr Input address
*/
static MAM_Inf_Type MAM_Get_MAM_Inf(uint32_t u32Addr);
/*************** Local Functions ***************/
static MAM_Inf_Type MAM_Get_MAM_Inf(uint32_t u32Addr)
{
MAM_Inf_Type inf = {.error = 0};
if(MAM0_MIN_ADDR <= u32Addr && u32Addr < MAM0_MAX_ADDR)
{
if(ROM_START_ADDR == u32Addr)
{
inf.block_num = 0;
}
else if(FLASH0_START_ADDR <= u32Addr && u32Addr < FLASH0_END_ADDR)
{
if((u32Addr - FLASH0_START_ADDR)%FLASH0_BLOCK_SIZE == 0U)
{
inf.block_num = (u32Addr - FLASH0_START_ADDR) / FLASH0_BLOCK_SIZE + 1U;
}
else
{
inf.error = 1;
}
}
else if(NVR_START_ADDR <= u32Addr && u32Addr < NVR_END_ADDR)
{
if((u32Addr - NVR_START_ADDR)%NVR_BLOCK_SIZE == 0U)
{
inf.block_num = (u32Addr - NVR_START_ADDR) / NVR_BLOCK_SIZE + 17U;
}
else
{
inf.error = 1;
}
}
else if(NVR_CFG_START_ADDR <= u32Addr && u32Addr < NVR_CFG_END_ADDR)
{
if((u32Addr - NVR_CFG_START_ADDR)%NVR_CFG_BLOCK_SIZE == 0U)
{
inf.block_num = (u32Addr - NVR_CFG_START_ADDR) / NVR_CFG_BLOCK_SIZE + 18U;
}
else
{
inf.error = 1;
}
}
else if(FLASH1_START_ADDR <= u32Addr && u32Addr < FLASH1_END_ADDR)
{
if((u32Addr - FLASH1_START_ADDR)%FLASH1_BLOCK_SIZE == 0U)
{
inf.block_num = (u32Addr - FLASH1_START_ADDR) / FLASH1_BLOCK_SIZE + 19U;
}
else
{
inf.error = 1;
}
}
else if(SRAM_START_ADDR <= u32Addr && u32Addr < SRAM_END_ADDR)
{
if((u32Addr - SRAM_START_ADDR)%SRAM_BLOCK_SIZE == 0U)
{
inf.block_num = (u32Addr - SRAM_START_ADDR) / SRAM_BLOCK_SIZE + 35U;
}
else
{
inf.error = 1;
}
}
else if(CPU0_DTCM_START_ADDR <= u32Addr && u32Addr < CPU0_DTCM_END_ADDR)
{
if((u32Addr - CPU0_DTCM_START_ADDR)%SRAM_BLOCK_SIZE == 0U)
{
inf.block_num = (u32Addr - CPU0_DTCM_START_ADDR) / CPU0_DTCM_BLOCK_SIZE + 43U;
}
else
{
inf.error = 1;
}
}
else if(u32Addr < CPU0_ITCM_END_ADDR)
{
if((u32Addr - CPU0_ITCM_START_ADDR)%CPU0_ITCM_BLOCK_SIZE == 0U)
{
inf.block_num = (u32Addr - CPU0_ITCM_START_ADDR) / CPU0_ITCM_BLOCK_SIZE + 41U;
}
else
{
inf.error = 1;
}
}
else if(AFCB0_START_ADDR <= u32Addr && u32Addr < AFCB0_END_ADDR)
{
if((u32Addr - AFCB0_START_ADDR)%AFCB0_BLOCK_SIZE == 0U)
{
inf.block_num = (u32Addr - AFCB0_START_ADDR) / AFCB0_BLOCK_SIZE + 51U;
}
else
{
inf.error = 1;
}
}
else if(AFCB1_START_ADDR <= u32Addr && u32Addr < AFCB1_END_ADDR)
{
if((u32Addr - AFCB1_START_ADDR)%AFCB1_BLOCK_SIZE == 0U)
{
inf.block_num = (u32Addr - AFCB1_START_ADDR) / AFCB1_BLOCK_SIZE + 211U;
}
else
{
inf.error = 1;
}
}
else
{
inf.error = 1;
}
}
else
{
inf.error = 1;
}
return inf;
}
/***************** Global Functions *******************/
uint8_t MAM_Config(MAM_Master_Type Master, uint32_t u32Addr, uint32_t u32Val)
{
MAM_Inf_Type inf = MAM_Get_MAM_Inf(u32Addr);
uint32_t reg_idx = 0U;
uint32_t bit_idx = 0U;
uint8_t status = 0U;
if(inf.error == 1U)
{
status = 1;
}
else
{
reg_idx = inf.block_num / 8U + 47U*(uint32_t)Master; /* 371 block , 371/8 + 1*/
bit_idx = inf.block_num % 8U;
Mam_HWA_Set_ACR(MAM, reg_idx, u32Val << (bit_idx * 4U));
reg_idx = inf.block_num / 32U + 12U*(uint32_t)Master; /* 371 block , 371/32 + 1*/
bit_idx = inf.block_num % 32U;
Mam_HWA_Set_ACLR(MAM, reg_idx, 1UL << bit_idx);
}
return status;
}
uint8_t MAM_Enable_Wdg(MAM_Master_Type Master,uint32_t u32Addr)
{
uint8_t status = 0U;
uint32_t bit_idx = 0U;
uint32_t regval = 0U;
MAM_Inf_Type inf = MAM_Get_MAM_Inf(u32Addr);
if(Master >= MAM_MASTER_NUM || inf.error == 1U)
{
status = 1;
}
else
{
bit_idx = (uint32_t)Master;
regval = Mam_HWA_Get_Wdgctr(MAM);
regval |= 1UL << bit_idx;
Mam_HWA_Set_Wdgctr(MAM, regval);
}
return status;
}
uint8_t MAM_Disable_Wdg(MAM_Master_Type Master,uint32_t u32Addr)
{
uint8_t status = 0U;
uint32_t regval = 0U;
uint32_t bit_idx = 0U;
MAM_Inf_Type inf = MAM_Get_MAM_Inf(u32Addr);
if(Master >= MAM_MASTER_NUM || inf.error == 1U)
{
status = 1;
}
else
{
bit_idx = (uint32_t)Master;
regval = Mam_HWA_Get_Wdgctr(MAM);
regval &= ~(1U << bit_idx);
Mam_HWA_Set_Wdgctr(MAM, regval);
}
return status;
}

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/**
* @file fc7xxx_driver_mb.c
* @author Flagchip070
* @brief FC7xxx Mailbox driver type definition and API
* @version 0.1.0
* @date 2022-11-15
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022-11-15 Flagchip070 N/A First version for FC7300
******************************************************************************** */
#include "fc7xxx_driver_mb.h"
/********* Local variable ************/
static uint32_t s_u32CoreIndex = MB_NOT_INIT;
static const uint8_t s_aMasterIdTab[MB_INT_CONFIG_COUNT] = {
0u, 8u
};
static void (*s_pRequestCallback)(MB_ReceiveType *pReceive) = NULL;
static void (*s_pDoneCallback)(uint32_t u32ChannelMask) = NULL;
/******* Local Function Prototype *********/
static uint32_t core_id_2_index(uint32_t u32MasterId);
static uint8_t get_channel_status(uint32_t u32Channel);
/**
* @brief Convert core master id to index
*
* @param u32MasterId Core master ID
*
*/
static uint32_t core_id_2_index(uint32_t u32MasterId)
{
uint32_t u32Index = 0;
uint32_t u32Loop;
for(u32Loop = 0; u32Loop < MB_INT_CONFIG_COUNT; u32Loop++)
{
if(s_aMasterIdTab[u32Loop] == u32MasterId)
{
u32Index = u32Loop;
break;
}
}
return u32Index;
}
/**
* @brief Get the master security information and processing mode of the channel
*
* @param u32Channel the selected MB channel
*
*/
static uint8_t get_channel_status(uint32_t u32Channel)
{
uint8_t u8Status = 0;
if(0u == MB_HWA_GetSecure(u32Channel))
{
u8Status |= MB_CHANNEL_STATUS_SECURE;
}
if(0u != MB_HWA_GetSupervisor(u32Channel))
{
u8Status |= MB_CHANNEL_STATUS_PRIVILEGED;
}
return u8Status;
}
/********* Global Functions ************/
/**
* @brief Get the index of the core
*
* @return uint32_t index of the core
*/
uint32_t MB_GetCoreIndex(void)
{
return s_u32CoreIndex;
}
/**
* @brief Initialize the Mailbox
*
* @param pInitConfig the configurations of the Mailbox
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_Init(const MB_InitType *pInitConfig)
{
MB_StatusType eStatus = MB_STATUS_SUCCESS;
if(MB_NOT_INIT != s_u32CoreIndex)
{
eStatus = MB_STATUS_ALREADY_INITED;
}
else
{
/* Get Core Index */
#if defined(DEVICE_TYPE) && (DEVICE_TYPE == FC7XXXHSM)
s_u32CoreIndex = HSM_MAILBOX_CORE_INDEX;
#else
uint32_t u32CoreId;
uint32_t u32Index;
u32CoreId = (MCM->MICR & MCM_MICR_COREID_Msk) >> MCM_MICR_COREID_Pos;
for(u32Index = 0; u32Index < MB_INT_CONFIG_COUNT; u32Index++)
{
if(u32CoreId == s_aMasterIdTab[u32Index])
{
s_u32CoreIndex = u32Index;
break;
}
}
#endif
if(MB_NOT_INIT != s_u32CoreIndex)
{
/*Registering callback functions*/
s_pRequestCallback = pInitConfig->pRequestCallback;
s_pDoneCallback = pInitConfig->pDoneCallback;
/*Configure the event mask*/
MB_HWA_ConfigFlagMask(s_u32CoreIndex, pInitConfig->u32EventMask);
/*Enable event interrupts */
MB_HWA_ConfigIntrEnable(s_u32CoreIndex, pInitConfig->u32IntrMask);
}
else
{
eStatus = MB_STATUS_FAILED;
}
}
return eStatus;
}
/**
* @brief De-initialize the Mailbox
*
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_DeInit(void)
{
MB_StatusType eStatus = MB_STATUS_UNINIT;
if(MB_NOT_INIT != s_u32CoreIndex)
{
/*Disable all event interrupts and flag*/
MB_HWA_ConfigFlagMask(s_u32CoreIndex, 0);
MB_HWA_ConfigIntrEnable(s_u32CoreIndex, 0);
s_u32CoreIndex = MB_NOT_INIT;
}
return eStatus;
}
/**
* @brief Attempt to acquire a Mailbox channel
*
* @param u32Channel the selected Mailbox channel
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_LockChannel(uint32_t u32Channel)
{
MB_StatusType eStatus = MB_STATUS_SUCCESS;
uint32_t u32Lock;
if(MB_NOT_INIT == s_u32CoreIndex)
{
eStatus = MB_STATUS_UNINIT;
}
else
{
if(u32Channel < MB_CHANNEL_CONFIG_COUNT)
{
/*Read SEMA to lock the selected channel*/
u32Lock = MB_HWA_LockChannel(u32Channel);
if(0u == u32Lock)
{
eStatus = MB_STATUS_LOCKED;
}
}
else
{
eStatus = MB_STATUS_PARAM_ERROR;
}
}
return eStatus;
}
/**
* @brief Release a Mailbox channel
*
* @param u32Channel the selected Mailbox channel
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_ReleaseChannel(uint32_t u32Channel)
{
MB_StatusType eStatus = MB_STATUS_SUCCESS;
uint32_t u32MasterId;
if(MB_NOT_INIT == s_u32CoreIndex)
{
eStatus = MB_STATUS_UNINIT;
}
else
{
if(u32Channel < MB_CHANNEL_CONFIG_COUNT)
{
/*Check the master core of the channel*/
u32MasterId = MB_HWA_GetMasterID(u32Channel);
if(u32MasterId == s_aMasterIdTab[s_u32CoreIndex])
{
/*Release the selected channel*/
MB_HWA_ReleaseChannel(u32Channel);
}
else
{
eStatus = MB_STATUS_FAILED;
}
}
else
{
eStatus = MB_STATUS_PARAM_ERROR;
}
}
return eStatus;
}
/**
* @brief Software clears channel lock
*
* @param u32Channel the selected Mailbox channel
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_UnlockChannel(uint32_t u32Channel)
{
MB_StatusType eStatus = MB_STATUS_SUCCESS;
if(MB_NOT_INIT == s_u32CoreIndex)
{
eStatus = MB_STATUS_UNINIT;
}
else
{
if(u32Channel < MB_CHANNEL_CONFIG_COUNT)
{
MB_HWA_UnlockChanne(u32Channel);
}
else
{
eStatus = MB_STATUS_PARAM_ERROR;
}
}
return eStatus;
}
/**
* @brief Launching a Mailbox request
*
* @param pRequest Configuration of the request
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_SendRequest(MB_RequestType *pRequest)
{
MB_StatusType eStatus = MB_LockChannel(pRequest->u8Channel);
if(MB_STATUS_SUCCESS == eStatus)
{
if(pRequest->u8DoneMasterIndex < MB_INT_CONFIG_COUNT)
{
MB_HWA_ConfigDoneMasterId(pRequest->u8Channel, s_aMasterIdTab[pRequest->u8DoneMasterIndex]);
MB_HWA_ConfigDoneMask(pRequest->u8Channel, pRequest->u8DoneMask);
MB_HWA_ConfigAutoUnlock(pRequest->u8Channel, pRequest->u8AutoReleaseFlag);
MB_HWA_WriteData(pRequest->u8Channel, pRequest->aData);
MB_HWA_ConfigRequest(pRequest->u8Channel, pRequest->u8RequestMask);
}
else
{
eStatus = MB_STATUS_PARAM_ERROR;
}
}
return eStatus;
}
/**
* @brief Attempt to receive a request from the selected channel
*
* @param pReceive Configuration of the receiving request
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_ReceiveChannel(MB_ReceiveType *pReceive)
{
MB_StatusType eStatus = MB_STATUS_SUCCESS;
uint32_t u32Flag;
if(MB_NOT_INIT == s_u32CoreIndex)
{
eStatus = MB_STATUS_UNINIT;
}
else if(pReceive->u8Channel < MB_CHANNEL_CONFIG_COUNT)
{
u32Flag = MB_HWA_GetFlag(s_u32CoreIndex, MB_EVENT_REQ(pReceive->u8Channel));
if(0u != u32Flag)
{
/* Clear events flag */
MB_HWA_ClearFlag(s_u32CoreIndex, u32Flag);
/* receiving data */
MB_HWA_GetData(pReceive->u8Channel, pReceive->aData);
/* get the security information and processing mode */
pReceive->u8ChannelStatus = get_channel_status(pReceive->u8Channel);
/*get the master core index of the request*/
pReceive->u8MasterCoreIndex = (uint8_t)MB_HWA_GetMasterID(pReceive->u8Channel);
pReceive->u8MasterCoreIndex = (uint8_t)core_id_2_index((uint32_t)pReceive->u8MasterCoreIndex);
}
else
{
eStatus = MB_STATUS_NO_REQUEST;
}
}
else
{
eStatus = MB_STATUS_PARAM_ERROR;
}
return eStatus;
}
/**
* @brief Issue a done event to the selected channel
*
* @param u32Channel the selected Mailbox channel
* @param u32DoneMask The mask for issuing done
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_DoneChannel(uint32_t u32Channel, uint32_t u32DoneMask)
{
MB_StatusType eStatus = MB_STATUS_SUCCESS;
uint32_t u32DoneMasterId, u32DoneMaskAllow;
if(MB_NOT_INIT == s_u32CoreIndex)
{
eStatus = MB_STATUS_UNINIT;
}
else if(u32Channel < MB_CHANNEL_CONFIG_COUNT)
{
/* Check the done master of the channel*/
u32DoneMasterId = MB_HWA_GetDoneMasterId(u32Channel);
if(u32DoneMasterId == s_aMasterIdTab[s_u32CoreIndex])
{
/* Check if the done mask is allowed */
u32DoneMaskAllow = MB_HWA_GetDoneMask(u32Channel);
if((u32DoneMaskAllow & u32DoneMask) == u32DoneMask)
{
/* issue a done event */
MB_HWA_SetDone(u32Channel, u32DoneMask);
}
else
{
eStatus = MB_STATUS_FAILED;
}
}
else
{
eStatus = MB_STATUS_FAILED;
}
}
else
{
eStatus = MB_STATUS_PARAM_ERROR;
}
return eStatus;
}
/**
* @brief Polling the done event of all channels
*
* @param u32PollMask mask of the done event
* @param pDoneMask buffer to store the done events
* @return MB_StatusType whether the operation is successfully
*/
MB_StatusType MB_PollDone(uint32_t u32PollMask, uint32_t *pDoneMask)
{
MB_StatusType eStatus = MB_STATUS_SUCCESS;
uint32_t u32Flag, u32Index;
*pDoneMask = 0;
if(MB_NOT_INIT == s_u32CoreIndex)
{
eStatus = MB_STATUS_UNINIT;
}
else if(0u != u32PollMask)
{
for(u32Index = 0; u32Index < MB_CHANNEL_CONFIG_COUNT; u32Index++)
{
if(0u != (u32PollMask & ((uint32_t)1u << u32Index)))
{
u32Flag = MB_HWA_GetFlag(s_u32CoreIndex, MB_EVENT_DONE(u32Index));
if(0u != u32Flag)
{
/* Clear done flag */
MB_HWA_ClearFlag(s_u32CoreIndex, u32Flag);
/* store the done event */
*pDoneMask |= (uint32_t)1u << u32Index;
}
}
}
}
else
{
eStatus = MB_STATUS_PARAM_ERROR;
}
return eStatus;
}
/**
* @brief Interrupt IRQ handle of Mailbox
*
*/
void MB_IRQProcess(void)
{
uint32_t u32FlagStat = MB_HWA_GetFlagStat(s_u32CoreIndex, MB_INTn_FLG_STAT_MASK);
uint32_t u32Index, u32MasterCore, u32ChannelMask = 0;
MB_ReceiveType tReceive;
MB_HWA_ClearFlag(s_u32CoreIndex, u32FlagStat);
for(u32Index = 0; u32Index < MB_CHANNEL_CONFIG_COUNT; u32Index++)
{
/* get the master core index of the channel*/
u32MasterCore = MB_HWA_GetMasterID(u32Index);
u32MasterCore = core_id_2_index(u32MasterCore);
if(0u != (u32FlagStat & ((uint32_t)1u << u32Index)))
{
/* request event */
if(NULL != s_pRequestCallback)
{
tReceive.u8Channel = (uint8_t)u32Index;
tReceive.u8ChannelStatus = get_channel_status(u32Index);
tReceive.u8MasterCoreIndex = (uint8_t)u32MasterCore;
MB_HWA_GetData(u32Index, tReceive.aData);
/* call the request callback*/
s_pRequestCallback(&tReceive);
}
}
if(0u != (u32FlagStat & ((uint32_t)1u << (u32Index + MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_SHIFT))))
{
u32ChannelMask |= (uint32_t)1u << u32Index;
/*done event*/
if((0u == MB_HWA_GetAutoClear(u32Index, s_u32CoreIndex)) && (u32MasterCore == s_u32CoreIndex))
{
/* if channel is not automatically clear,
* and master core is self, release the channel */
MB_HWA_ReleaseChannel(u32Index);
}
}
}
if((NULL != s_pDoneCallback) && (0u != u32ChannelMask))
{
s_pDoneCallback(u32ChannelMask);
}
}

128
Src/fc7xxx_driver_mpu.c Normal file
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@ -0,0 +1,128 @@
/**
* @file fc7xxx_driver_mpu.c
* @author Flagchip085
* @brief FC7xxx MPU driver type definition and API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details The MPU only checks the CPU master access to CTCM and DTCM memory. When access denied, it will cause MemManage Interrupt.
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_mpu.h"
void MPU_Disable(void)
{
__DMB(); /* make sure outstanding transfers are done */
MPU_HWA_Fault_Disable();
MPU_HWA_Set_CR(0U); /* disable mpu and clear its control register*/
}
void MPU_Enable(MPU_EnableOptionType eOption)
{
uint32_t u32Option;
switch (eOption)
{
case MPU_EN_HARDFAULT_NMI:
u32Option = CORTEX_MPU_CTRL_HFNMIENA_MASK;
break;
case MPU_EN_PRIVILEGED_DEFAULT:
u32Option = CORTEX_MPU_CTRL_RPRIVDEFENA_MASK;
break;
case MPU_EN_HFNMI_PRIVDEF:
u32Option = (CORTEX_MPU_CTRL_HFNMIENA_MASK | CORTEX_MPU_CTRL_RPRIVDEFENA_MASK);
break;
case MPU_EN_HFNMI_PRIVDEF_NONE:
u32Option = 0U;
break;
default:
u32Option = 0U;
break;
}
MPU_HWA_Set_CR(CORTEX_MPU_CTRL_ENABLE_MASK | (((uint32_t)u32Option) & MPU_EN_MASK_U32));
MPU_HWA_Fault_Enable(); /* mpu fault MemManage INT enable */
__DSB();
__ISB();
}
MPU_StatusType MPU_RegionDisable(MPU_RegionNumberType eRegion)
{
MPU_HWA_Set_NR((uint8_t)eRegion);
MPU_HWA_Set_BAR(0x00U);
MPU_HWA_Set_ASR(0x00U);
return MPU_STATUS_SUCCESS;
}
MPU_StatusType MPU_RegionEnable(MPU_RegionNumberType eRegion, const MPU_RegionConfigurationType *pConfig)
{
MPU_StatusType eRet = MPU_STATUS_SUCCESS;
uint32_t u32Srd;
uint32_t u32Asr;
if ((NULL == pConfig) ||
((uint32_t)eRegion > (uint32_t)MPU_REGION_NUMBER_15) ||
(0U != (pConfig->u32BaseAddr & MPU_RBAR_VALID_REGION_MASK_U32)) ||
((uint32_t)pConfig->eRegionSize < (uint32_t)MPU_REGION_SIZE_32B) ||
((uint32_t)pConfig->eRegionSize > (uint32_t)MPU_REGION_SIZE_4GB))
{
eRet = MPU_STATUS_ERROR;
}
else
{
/* use bit shift is surely safe */
u32Srd = (((((uint32_t)pConfig->eSubRegionDis_0) << 0) |
(((uint32_t)pConfig->eSubRegionDis_1) << 1) |
(((uint32_t)pConfig->eSubRegionDis_2) << 2) |
(((uint32_t)pConfig->eSubRegionDis_3) << 3) |
(((uint32_t)pConfig->eSubRegionDis_4) << 4) |
(((uint32_t)pConfig->eSubRegionDis_5) << 5) |
(((uint32_t)pConfig->eSubRegionDis_6) << 6) |
(((uint32_t)pConfig->eSubRegionDis_7) << 7)) & 0xFFU);
u32Asr = CORTEX_MPU_RASR_XN(pConfig->eExecuteNever) |
CORTEX_MPU_RASR_AP(pConfig->eAccessPermission) |
CORTEX_MPU_RASR_TEX(pConfig->eTypeExtLevel) |
CORTEX_MPU_RASR_S(pConfig->eShareable) |
CORTEX_MPU_RASR_C(pConfig->eCacheable) |
CORTEX_MPU_RASR_B(pConfig->eBufferable) |
CORTEX_MPU_RASR_SRD(u32Srd) |
CORTEX_MPU_RASR_SIZE(pConfig->eRegionSize) |
CORTEX_MPU_RASR_ENABLE_MASK;
MPU_HWA_Set_NR((uint8_t)eRegion);
MPU_HWA_Set_BAR(pConfig->u32BaseAddr & MPU_RBAR_BASEADDR_MASK_U32); /* ignore VALID and REGION bits */
MPU_HWA_Set_ASR(u32Asr);
}
return eRet;
}
MPU_StatusType MPU_CheckExist(void)
{
uint32_t u32RegVal = MPU_HWA_Get_Type();
MPU_StatusType eRet = MPU_STATUS_SUCCESS;
if (0U == u32RegVal)
{
eRet = MPU_STATUS_ERROR;
}
return eRet;
}

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Src/fc7xxx_driver_msc.c Normal file
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/**
* @file fc7xxx_driver_msc.c
* @author Flagchip
* @brief FC7240 MSC driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version
******************************************************************************** */
#include "fc7xxx_driver_msc.h"
/* ################################################################################## */
/* ####################################### Macro #################################### */
/* ################################################################################## */
/* ################################### Type define ################################## */
/* ################################################################################## */
/* ################################ Local Variables ################################# */
static MSC_Type *const s_apMscBase[MSC_INSTANCE_COUNT] = MSC_BASE_PTRS;
static MSC_ISRCallbackType s_apMscRFISRCallback[MSC_INSTANCE_COUNT] = {NULL};
static MSC_ISRCallbackType s_apMscTFISRCallback[MSC_INSTANCE_COUNT] = {NULL};
static MSC_ISRCallbackType s_apMscCFISRCallback[MSC_INSTANCE_COUNT] = {NULL};
static MSC_ISRCallbackType s_apMscDFISRCallback[MSC_INSTANCE_COUNT] = {NULL};
static MSC_ISRCallbackType s_apMscTOISRCallback[MSC_INSTANCE_COUNT] = {NULL};
/* ################################################################################## */
/* ########################### Local Prototype Functions ############################ */
static void MSCn_IRQHandler(const MSC_InstanceType eInstance);
static void MSC_ClearReceiveInterruptFlag(const MSC_InstanceType eInstance);
static void MSC_ClearTimeFrameInterruptFlag(const MSC_InstanceType eInstance);
static void MSC_ClearCommandFrameInterruptFlag(const MSC_InstanceType eInstance);
static void MSC_ClearDataFrameInterruptFlag(const MSC_InstanceType eInstance);
/* ################################################################################## */
/* ######################### Global prototype Functions ############################ */
void MSC0_IRQHandler(void);
/* ################################################################################## */
/* ################################ Local Functions ################################ */
static void MSCn_IRQHandler(const MSC_InstanceType eInstance)
{
uint32_t u32IntFlag = MSC_GetInterruptStatus(eInstance);
MSC_Type *const pMsc = s_apMscBase[eInstance];
if (u32IntFlag & MSC_INSR_RFI_MASK)
{
MSC_ClearReceiveInterruptFlag(eInstance);
if (MSC_HWA_GetRfieEnable(pMsc) && s_apMscRFISRCallback[eInstance] != NULL)
{
s_apMscRFISRCallback[eInstance](eInstance);
}
}
if (u32IntFlag & MSC_INSR_TFI_MASK)
{
MSC_ClearTimeFrameInterruptFlag(eInstance);
if (MSC_HWA_GetTfieEnable(pMsc) && s_apMscTFISRCallback[eInstance] != NULL)
{
s_apMscTFISRCallback[eInstance](eInstance);
}
}
if (u32IntFlag & MSC_INSR_CFI_MASK)
{
MSC_ClearCommandFrameInterruptFlag(eInstance);
if (MSC_HWA_GetCfieEnable(pMsc) && s_apMscCFISRCallback[eInstance] != NULL)
{
s_apMscCFISRCallback[eInstance](eInstance);
}
}
if (u32IntFlag & MSC_INSR_DFI_MASK)
{
MSC_ClearDataFrameInterruptFlag(eInstance);
if (MSC_HWA_GetDfieEnable(pMsc) && s_apMscDFISRCallback[eInstance] != NULL)
{
s_apMscDFISRCallback[eInstance](eInstance);
}
}
if (MSC_HWA_GetTofEnable(pMsc))
{
MSC_HWA_ClearTofEnable(pMsc);
if (MSC_HWA_GetToieEnable(pMsc) && s_apMscTOISRCallback[eInstance] != NULL)
{
s_apMscTOISRCallback[eInstance](eInstance);
}
}
}
/* ################################################################################## */
/* ################################ Global Functions ################################ */
void MSC0_IRQHandler(void)
{
MSCn_IRQHandler(MSC_INSTANCE_0);
}
MSC_ReturnType MSC_init(const MSC_InstanceType eInstance, const MSC_InitCfgType *pInitConfig)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
DEV_ASSERT(pInitConfig != NULL);
MSC_Type *const pMsc = s_apMscBase[eInstance];
uint32_t u32TempValue;
uint32_t u32TimeoutCount = 0xFFFFFFU;
if (pInitConfig->u8CommandBitLength > 32U || pInitConfig->u8SRLDataBitLength > 16U || pInitConfig->u8SRHDataBitLength > 16U)
{
return MSC_RETURN_E_PARAM;
}
MSC_HWA_SetMsrRst(pMsc);
while (MSC_HWA_GetMsrRdone(pMsc) == false)
{
u32TimeoutCount--;
if (u32TimeoutCount == 0U)
{
break;
}
}
if (u32TimeoutCount == 0U)
{
return MSC_RETURN_E_NOT_OK;
}
MSC_HWA_ClearMsrDone(pMsc);
u32TempValue = MSC_TCCTR_PL(pInitConfig->u8PassiveLength) | MSC_TCCTR_WM(pInitConfig->eWorkMode) | MSC_TCCTR_SELH(pInitConfig->bSelSRH) | MSC_TCCTR_SELL(pInitConfig->bSelSRL) |
MSC_TCCTR_NBS(pInitConfig->u8CommandBitLength) | MSC_TCCTR_NHBS(pInitConfig->u8SRHDataBitLength) | MSC_TCCTR_NLBS(pInitConfig->u8SRLDataBitLength);
MSC_HWA_SetTcctr(pMsc, u32TempValue);
MSC_HWA_SetNp(pMsc, pInitConfig->u8PTFNumber);
u32TempValue =
MSC_RCCSR_RFT(pInitConfig->eRsvFrameType) | MSC_RCCSR_RBR(pInitConfig->eBaudRate) | MSC_RCCSR_PCTL(pInitConfig->eParity) | MSC_RCCSR_HIDC(pInitConfig->bDelayControl);
MSC_HWA_SetRccsr(pMsc, u32TempValue);
return MSC_RETURN_OK;
}
void MSC_initInterrupt(const MSC_InstanceType eInstance, const MSC_InterruptCfgType *pInteruptConfig)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
DEV_ASSERT(pInteruptConfig != NULL);
uint32_t u32TempValue;
MSC_Type *const pMsc = s_apMscBase[eInstance];
u32TempValue = MSC_INCR_RFIE(pInteruptConfig->eRFIEMode) | MSC_INCR_TFIE(pInteruptConfig->bTFIntEnable) | MSC_INCR_CFIE(pInteruptConfig->bCFIntEnable) |
MSC_INCR_DFIE(pInteruptConfig->eDFIEMode);
MSC_HWA_SetIncr(pMsc, u32TempValue);
u32TempValue = MSC_RTOR_TOIE(pInteruptConfig->bTOIntEnable) | MSC_RTOR_TOV(pInteruptConfig->u16TimeoutValue);
MSC_HWA_SetRtor(pMsc, u32TempValue);
s_apMscRFISRCallback[eInstance] = pInteruptConfig->pReceiveFrameISRCallback;
s_apMscTFISRCallback[eInstance] = pInteruptConfig->pTimeFrameISRCallback;
s_apMscCFISRCallback[eInstance] = pInteruptConfig->pCommandFrameISRCallback;
s_apMscDFISRCallback[eInstance] = pInteruptConfig->pDataFrameISRCallback;
s_apMscTOISRCallback[eInstance] = pInteruptConfig->pReceiveTimeOutISRCallback;
}
void MSC_SelTranmittingSource(const MSC_InstanceType eInstance, uint32_t u32SourceMask, MSC_TransSourceType eSourceType)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
uint32_t u32TempValue1 = 0;
uint16_t u32TempValue2;
uint8_t u8i;
u32TempValue2 = (uint16_t)(u32SourceMask & 0xFFFFU);
for (u8i = 0U; u8i < 16U; u8i++)
{
if ((u32TempValue2 & 0x01U) != 0U)
{
u32TempValue1 |= (uint32_t)eSourceType << (u8i << 1U);
}
u32TempValue2 = u32TempValue2 >> 1;
}
MSC_HWA_SetTcslr(pMsc, u32TempValue1);
u32TempValue2 = (uint16_t)((u32SourceMask >> 16) & 0xFFFFU);
for (u8i = 0U; u8i < 16U; u8i++)
{
if ((u32TempValue2 & 0x01U) != 0U)
{
u32TempValue1 |= (uint32_t)eSourceType << (u8i << 1U);
}
u32TempValue2 = u32TempValue2 >> 1;
}
MSC_HWA_SetTcshr(pMsc, u32TempValue1);
}
void MSC_SetEmergencyLoad(const MSC_InstanceType eInstance, uint32_t u32Value)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_SetTcelr(pMsc, u32Value);
}
void MSC_SetIOControl(const MSC_InstanceType eInstance, const MSC_IOControlInitType *pIOConfig)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
uint32_t u32TempValue = 0;
MSC_Type *const pMsc = s_apMscBase[eInstance];
u32TempValue |= MSC_IOCR_IDS(pIOConfig->eSDIsel);
u32TempValue |= MSC_IOCR_ESC(pIOConfig->eENCSel);
u32TempValue |= MSC_IOCR_ESH(pIOConfig->eENHSel);
u32TempValue |= MSC_IOCR_ESL(pIOConfig->eENLSel);
u32TempValue |= MSC_IOCR_FCLCTRL(pIOConfig->eFclCtrl);
u32TempValue |= MSC_IOCR_IPS(pIOConfig->eSDIPol);
u32TempValue |= MSC_IOCR_ENP(pIOConfig->eENXPol);
u32TempValue |= MSC_IOCR_SOP(pIOConfig->eSOPPol);
u32TempValue |= MSC_IOCR_FCLP(pIOConfig->eFCLPPol);
MSC_HWA_SetIocr(pMsc, u32TempValue);
}
void MSC_Enable(const MSC_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_SetMscEnable(pMsc, true);
}
void MSC_Disable(const MSC_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_SetMscEnable(pMsc, false);
}
void MSC_SetDataFrame(const MSC_InstanceType eInstance, uint32_t u32Data)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_SetTcdar(pMsc, u32Data);
}
void MSC_SendDataFrame(const MSC_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_SetDataNeedSend(pMsc);
}
void MSC_SendCommandFrame(const MSC_InstanceType eInstance, uint32_t u32Command)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_SetTccor(pMsc, u32Command);
}
uint8_t MSC_GetReceivedFrameAddr(const MSC_InstanceType eInstance, MSC_RDRxIndexType eIndex)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
DEV_ASSERT(eIndex < MSC_RDRx_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
uint8_t u8Addr = 0U;
if (eIndex == MSC_RDR0)
{
u8Addr = MSC_HWA_GetRdr0Addr(pMsc);
}
else if (eIndex == MSC_RDR1)
{
u8Addr = MSC_HWA_GetRdr1Addr(pMsc);
}
else if (eIndex == MSC_RDR2)
{
u8Addr = MSC_HWA_GetRdr2Addr(pMsc);
}
else if (eIndex == MSC_RDR3)
{
u8Addr = MSC_HWA_GetRdr3Addr(pMsc);
}
else {}
return u8Addr;
}
MSC_ReceiveStatusType MSC_GetReceivedFrame(const MSC_InstanceType eInstance, MSC_RDRxIndexType eIndex, uint8_t *pData)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
DEV_ASSERT(eIndex < MSC_RDRx_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_ReceiveStatusType eRsvStatus = MSC_RSV_SUCCESS;
if (eIndex == MSC_RDR0)
{
eRsvStatus = MSC_HWA_GetRdr0Rerr(pMsc);
if (MSC_RSV_SUCCESS == eRsvStatus)
{
*pData = MSC_HWA_GetRdr0Data(pMsc);
}
}
else if (eIndex == MSC_RDR1)
{
eRsvStatus = MSC_HWA_GetRdr1Rerr(pMsc);
if (MSC_RSV_SUCCESS == eRsvStatus)
{
*pData = MSC_HWA_GetRdr1Data(pMsc);
}
}
else if (eIndex == MSC_RDR2)
{
eRsvStatus = MSC_HWA_GetRdr2Rerr(pMsc);
if (MSC_RSV_SUCCESS == eRsvStatus)
{
*pData = MSC_HWA_GetRdr2Data(pMsc);
}
}
else if (eIndex == MSC_RDR3)
{
eRsvStatus = MSC_HWA_GetRdr3Rerr(pMsc);
if (MSC_RSV_SUCCESS == eRsvStatus)
{
*pData = MSC_HWA_GetRdr3Data(pMsc);
}
}
else {}
return eRsvStatus;
}
uint32_t MSC_GetInterruptStatus(const MSC_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
return MSC_HWA_GetInsr(pMsc);
}
void MSC_EnableTrasmit(const MSC_InstanceType eInstance, bool bEnable)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
if (bEnable)
{
MSC_HWA_ClearTcdis(pMsc);
}
else
{
MSC_HWA_SetTcdis(pMsc);
}
}
void MSC_ClearReceiveInterruptFlag(const MSC_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_ClearCrfi(pMsc);
}
void MSC_ClearTimeFrameInterruptFlag(const MSC_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_ClearCtfi(pMsc);
}
void MSC_ClearCommandFrameInterruptFlag(const MSC_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_ClearCcfi(pMsc);
}
void MSC_ClearDataFrameInterruptFlag(const MSC_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_ClearCdfi(pMsc);
}
void MSC_EnableDataFrameInterrupt(const MSC_InstanceType eInstance, bool bEnable)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_SetDfieEnable(pMsc, bEnable);
}
void MSC_EnableCommandFrameInterrupt(const MSC_InstanceType eInstance, bool bEnable)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_SetCfieEnable(pMsc, bEnable);
}
void MSC_EnableTimeFrameInterrupt(const MSC_InstanceType eInstance, bool bEnable)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_SetTfieEnable(pMsc, bEnable);
}
void MSC_EnableReceiveInterrupt(const MSC_InstanceType eInstance, bool bEnable)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_SetRfieEnable(pMsc, bEnable);
}
void MSC_EnableTimeoutInterrupt(const MSC_InstanceType eInstance, bool bEnable)
{
DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT);
MSC_Type *const pMsc = s_apMscBase[eInstance];
MSC_HWA_SetToieEnable(pMsc, bEnable);
}
MSC_ReturnType Msc_SwitchENXChannel(const MSC_InstanceType eInstance, Msc_ENxType eEnx, Msc_ENxActiveType eENn, uint32_t u32TimeoutLoops)
{
MSC_ReturnType eTempReturn = MSC_RETURN_E_NOT_OK;
uint32 u32TempValue;
uint32 u32TempTryCount = 0u;
uint8 u8CmdNeedSend;
uint8 u8CmdFrameBusy;
uint8 u8DataNeedSend;
uint8 u8DataFrameBusy;
MSC_Type *const pMsc = s_apMscBase[eInstance];
if (eEnx == MSC_ENC)
{
do
{
u8CmdFrameBusy = MSC_HWA_GetCfb(pMsc);
u8CmdNeedSend = MSC_HWA_GetCmdNeedSend(pMsc);
if ((u8CmdNeedSend == TRUE) || (u8CmdFrameBusy == TRUE))
{
u32TempValue = TRUE;
}
else
{
u32TempValue = FALSE;
}
/* check receive rc flag */
if (u32TempValue == FALSE)
{
break;
}
else
{
u32TempTryCount++;
}
} while (u32TempTryCount < u32TimeoutLoops);
if (u32TempTryCount != u32TimeoutLoops)
{
u32TempValue = (MSC_HWA_GetIocr(pMsc) & ~MSC_IOCR_ESC_MASK) | MSC_IOCR_ESC(eENn);
MSC_HWA_SetIocr(pMsc, u32TempValue);
eTempReturn = MSC_RETURN_OK;
}
}
else
{
do
{
u8DataFrameBusy = MSC_HWA_GetDfb(pMsc);
u8DataNeedSend = MSC_HWA_GetDataNeedSend(pMsc);
if ((u8DataFrameBusy == TRUE) || (u8DataNeedSend == TRUE))
{
u32TempValue = TRUE;
}
else
{
u32TempValue = FALSE;
}
/* check receive rc flag */
if (u32TempValue == FALSE)
{
break;
}
else
{
u32TempTryCount++;
}
} while (u32TempTryCount < u32TimeoutLoops);
if (u32TempTryCount != u32TimeoutLoops)
{
if (eEnx == MSC_ENH)
{
u32TempValue = (MSC_HWA_GetIocr(pMsc) & ~MSC_IOCR_ESH_MASK) | MSC_IOCR_ESH(eENn);
MSC_HWA_SetIocr(pMsc, u32TempValue);
}
else
{
u32TempValue = (MSC_HWA_GetIocr(pMsc) & ~MSC_IOCR_ESL_MASK) | MSC_IOCR_ESL(eENn);
MSC_HWA_SetIocr(pMsc, u32TempValue);
}
eTempReturn = MSC_RETURN_OK;
}
}
return eTempReturn;
}
MSC_ReturnType Msc_SwitchSDIChannel(const MSC_InstanceType eInstance, MSC_SDISelectionType eSDIChannel, uint32_t u32TimeoutLoops)
{
MSC_ReturnType eTempReturn = MSC_RETURN_E_NOT_OK;
uint32_t u32TempValue;
uint32_t u32TempTryCount = 0u;
MSC_Type *const pMsc = s_apMscBase[eInstance];
do
{
u32TempValue = MSC_HWA_GetRxBusy(pMsc);
/* check receive rc flag */
if (u32TempValue == 0U)
{
break;
}
else
{
u32TempTryCount++;
}
} while (u32TempTryCount < u32TimeoutLoops);
if (u32TempTryCount != u32TimeoutLoops)
{
u32TempValue = (MSC_HWA_GetIocr(pMsc) & ~MSC_IOCR_IDS_MASK) | MSC_IOCR_IDS(eSDIChannel);
MSC_HWA_SetIocr(pMsc, u32TempValue);
eTempReturn = MSC_RETURN_OK;
}
return eTempReturn;
}

498
Src/fc7xxx_driver_overlay.c Normal file
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@ -0,0 +1,498 @@
/**
* @file fc7xxx_driver_overlay.c
* @author Flagchip
* @brief FC7xxx overlay driver type definition and API
* @version 0.1.0
* @date 2023-12-25
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-25 Flagchip0038 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_overlay.h"
typedef void (*Void_Type)(void);
typedef void (*U32_Type)(uint32_t u32Data);
typedef void (*SizeEnum_Type)(OVERLAY_OverlaySizeType eSize);
static Void_Type const s_aRegionEnDisable[OVERLYA_REGION_CNT] =
{
OVERLAY_HWA_OverlayRegion0Disable,
OVERLAY_HWA_OverlayRegion1Disable,
OVERLAY_HWA_OverlayRegion2Disable
};
static Void_Type const s_aRegionEnEnable[OVERLYA_REGION_CNT] =
{
OVERLAY_HWA_OverlayRegion0Enable,
OVERLAY_HWA_OverlayRegion1Enable,
OVERLAY_HWA_OverlayRegion2Enable
};
static U32_Type const s_aRegionSrc[OVERLYA_REGION_CNT] =
{
OVERLAY_HWA_SetOverlayRegion0Src,
OVERLAY_HWA_SetOverlayRegion1Src,
OVERLAY_HWA_SetOverlayRegion2Src
};
static U32_Type const s_aRegionDst[OVERLYA_REGION_CNT] =
{
OVERLAY_HWA_SetOverlayRegion0Dst,
OVERLAY_HWA_SetOverlayRegion1Dst,
OVERLAY_HWA_SetOverlayRegion2Dst
};
static SizeEnum_Type const s_aRegionSize[OVERLYA_REGION_CNT] =
{
OVERLAY_HWA_SetOverlayRegion0Size,
OVERLAY_HWA_SetOverlayRegion1Size,
OVERLAY_HWA_SetOverlayRegion2Size
};
static OVERLAY_ErrorCallback_Type s_tErrorCallbackFunc;
/**
* @brief Overlay region initial function
*
* @param pOverlayInitCfg initial parameters
* @return ERROR_OK is ok, others are not ok
*/
OVERLAY_ErrorType OVERLAY_RegionInit(OVERLAY_OverlayRegionInitType *pOverlayInitCfg)
{
OVERLAY_ErrorType eRetval;
uint32_t u32Index;
uint32_t u32ErrorInfo;
eRetval = OVERLAY_ERROR_OK;
/* global overlay Disable */
OVERLAY_HWA_OverlayDisable();
/* loop all region */
for (u32Index = 0U; (u32Index < OVERLYA_REGION_CNT) && (eRetval == OVERLAY_ERROR_OK); u32Index++)
{
/* check overlay region enable */
if (pOverlayInitCfg->aOverlayRegionEn[u32Index])
{
if ((pOverlayInitCfg->aOverlayRegionSrc[u32Index] >= PFLASH_START) &&
(pOverlayInitCfg->aOverlayRegionSrc[u32Index] <= PFLASH_END) &&
(pOverlayInitCfg->aOverlayRegionDst[u32Index] >= SRAM_START) &&
(pOverlayInitCfg->aOverlayRegionDst[u32Index] <= SRAM_END)
)
{
/* disable region n */
s_aRegionEnDisable[u32Index]();
/* source */
s_aRegionSrc[u32Index](pOverlayInitCfg->aOverlayRegionSrc[u32Index]);
/* dest */
s_aRegionDst[u32Index](pOverlayInitCfg->aOverlayRegionDst[u32Index]);
/* size */
s_aRegionSize[u32Index](pOverlayInitCfg->aOverlayRegionSize[u32Index]);
/* enable region n */
s_aRegionEnEnable[u32Index]();
}
else
{
eRetval = OVERLAY_ERROR_ADDR;
}
}
else
{
/* disable region n */
s_aRegionEnDisable[u32Index]();
}
}
if (eRetval == OVERLAY_ERROR_OK)
{
/* global overlay enable */
OVERLAY_HWA_OverlayEnable();
}
/* check error flag */
u32ErrorInfo = OVERLAY_HWA_GetErrorFlag();
if (u32ErrorInfo)
{
eRetval = OVERLAY_ERROR_FLAG;
}
return eRetval;
}
/**
* @brief De-Init Overlay Region
*
* @return ERROR_OK is ok, others are not ok
*/
OVERLAY_ErrorType OVERLAY_RegionDeInit(void)
{
OVERLAY_ErrorType eRetval;
uint32_t u32Index;
eRetval = OVERLAY_ERROR_OK;
/* disable global overlay */
OVERLAY_HWA_OverlayDisable();
for (u32Index = 0U; u32Index < OVERLYA_REGION_CNT; u32Index++)
{
/* disable region n */
s_aRegionEnDisable[u32Index]();
/* source */
s_aRegionSrc[u32Index](0U);
/* dest */
s_aRegionDst[u32Index](0U);
/* size */
s_aRegionSize[u32Index](OVERLAY_OVERLAYSIZE_1KB);
}
return eRetval;
}
/**
* @brief Far initial function
*
* @param pFarInitCfg initial parameters
* @return ERROR_OK is ok, others are not ok
*/
OVERLAY_ErrorType OVERLAY_FARInit(OVERLAY_FARInitType *pFarInitCfg)
{
OVERLAY_ErrorType eRetval;
uint32_t u32ErrorInfo;
eRetval = OVERLAY_ERROR_OK;
if (pFarInitCfg->u32FAREn == 0U)
{
/* disable far */
OVERLAY_HWA_FARDisable();
}
else
{
/* must align to 64KB, */
if ((pFarInitCfg->u32FARSize <= OVERLAY_FAR_SIZE_MAX) &&
((pFarInitCfg->u32FARSize & OVERLAY_FAR_SIZE_MASK) == 0U)
)
{
if ((pFarInitCfg->u32FARDst >= PFLASH_START) &&
(pFarInitCfg->u32FARDst <= PFLASH_END)
)
{
/* disable far */
OVERLAY_HWA_FARDisable();
/* set far dest */
OVERLAY_HWA_SetFarDst(pFarInitCfg->u32FARDst);
/* set far size */
OVERLAY_HWA_SetFarSize(pFarInitCfg->u32FARSize / OVERLAY_FAR_SIZE_ALIGN - 1);
/* disable enable */
OVERLAY_HWA_FAREnable();
}
else
{
eRetval = OVERLAY_ERROR_ADDR;
}
}
else
{
eRetval = OVERLAY_ERROR_SIZE;
}
}
if (eRetval == OVERLAY_ERROR_OK)
{
/* enable far */
OVERLAY_HWA_FAREnable();
}
/* check error flag */
u32ErrorInfo = OVERLAY_HWA_GetErrorFlag();
if (u32ErrorInfo)
{
eRetval = OVERLAY_ERROR_FLAG;
}
return eRetval;
}
/**
* @brief De-Init FAR Region
*
* @return ERROR_OK is ok, others are not ok
*/
OVERLAY_ErrorType OVERLAY_FARDeInit(void)
{
OVERLAY_ErrorType eRetval;
eRetval = OVERLAY_ERROR_OK;
/* disable global far */
OVERLAY_HWA_FARDisable();
/* set far dest */
OVERLAY_HWA_SetFarDst(0x01000000U);
/* set far size */
OVERLAY_HWA_SetFarSize(0U);
return eRetval;
}
/**
* @brief Enable or Disable Interrupt
*
* @param pInterruptCfg interrupt config parameter
*/
void OVERLAY_SetInterrupt(OVERLAY_InterruptType *pInterruptCfg)
{
if (pInterruptCfg->bEnableInterrupt)
{
OVERLAY_HWA_ErrorInterruptEnable();
s_tErrorCallbackFunc = pInterruptCfg->pCallBack;
}
else
{
OVERLAY_HWA_ErrorInterruptDisable();
s_tErrorCallbackFunc = NULL;
}
}
/**
* @brief Get Error Info
*
* @param pErrorInfo error info point
*/
void OVERLAY_GetErrorInfo(OVERLAY_ErrorInfoType *pErrorInfo)
{
uint32_t u32ErrorInfo;
u32ErrorInfo = OVERLAY_HWA_GetErrorFlag();
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_MASK)
{
pErrorInfo->bError_FAR_SIZE_INTR = 1U;
}
else
{
pErrorInfo->bError_FAR_SIZE_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_MASK)
{
pErrorInfo->bError_FAR_DST_OVERFLOW_INTR = 1U;
}
else
{
pErrorInfo->bError_FAR_DST_OVERFLOW_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_MASK)
{
pErrorInfo->bError_FAR_DST_NO_FLASH_INTR = 1U;
}
else
{
pErrorInfo->bError_FAR_DST_NO_FLASH_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_MASK)
{
pErrorInfo->bError_REGION2_D_CROS_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION2_D_CROS_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_MASK)
{
pErrorInfo->bError_REGION2_S_CROS_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION2_S_CROS_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_MASK)
{
pErrorInfo->bError_REGION2_SIZE_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION2_SIZE_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_MASK)
{
pErrorInfo->bError_REGION2_DST_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION2_DST_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_MASK)
{
pErrorInfo->bError_REGION2_SRC_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION2_SRC_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_MASK)
{
pErrorInfo->bError_REGION1_D_CROS_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION1_D_CROS_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_MASK)
{
pErrorInfo->bError_REGION1_S_CROS_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION1_S_CROS_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_MASK)
{
pErrorInfo->bError_REGION1_SIZE_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION1_SIZE_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_MASK)
{
pErrorInfo->bError_REGION1_DST_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION1_DST_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_MASK)
{
pErrorInfo->bError_REGION1_SRC_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION1_SRC_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_MASK)
{
pErrorInfo->bError_REGION0_D_CROS_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION0_D_CROS_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_MASK)
{
pErrorInfo->bError_REGION0_S_CROS_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION0_S_CROS_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_MASK)
{
pErrorInfo->bError_REGION0_SIZE_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION0_SIZE_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_MASK)
{
pErrorInfo->bError_REGION0_DST_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION0_DST_INTR = 0U;
}
if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_MASK)
{
pErrorInfo->bError_REGION0_SRC_INTR = 1U;
}
else
{
pErrorInfo->bError_REGION0_SRC_INTR = 0U;
}
}
/**
* @brief Clear Error Info
*
* @param pErrorInfo error info point
*/
void OVERLAY_ClrErrorInfo(OVERLAY_ErrorInfoType *pErrorInfo)
{
uint32_t u32ErrorInfo;
u32ErrorInfo = AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR(pErrorInfo->bError_FAR_SIZE_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR(pErrorInfo->bError_FAR_DST_OVERFLOW_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR(pErrorInfo->bError_FAR_DST_NO_FLASH_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR(pErrorInfo->bError_REGION2_D_CROS_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR(pErrorInfo->bError_REGION2_S_CROS_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR(pErrorInfo->bError_REGION2_SIZE_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR(pErrorInfo->bError_REGION2_DST_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR(pErrorInfo->bError_REGION2_SRC_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR(pErrorInfo->bError_REGION1_D_CROS_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR(pErrorInfo->bError_REGION1_S_CROS_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR(pErrorInfo->bError_REGION1_SIZE_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR(pErrorInfo->bError_REGION1_DST_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR(pErrorInfo->bError_REGION1_SRC_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR(pErrorInfo->bError_REGION0_D_CROS_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR(pErrorInfo->bError_REGION0_S_CROS_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR(pErrorInfo->bError_REGION0_SIZE_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR(pErrorInfo->bError_REGION0_DST_INTR);
u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR(pErrorInfo->bError_REGION0_SRC_INTR);
OVERLAY_HWA_ClrErrorFlag(u32ErrorInfo);
}
/**
* @brief Call Me in Overlay Error interrupt handler
*
*/
void OVERLAY_ErrorInterruptRoutine(void)
{
OVERLAY_ErrorInfoType tErrorInfo;
if (s_tErrorCallbackFunc != NULL)
{
OVERLAY_GetErrorInfo(&tErrorInfo);
s_tErrorCallbackFunc(tErrorInfo);
}
}

421
Src/fc7xxx_driver_pcc.c Normal file
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/**
* @file fc7xxx_driver_pcc.c
* @author Flagchip
* @brief FC7xxx PCC driver type definition and API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_pcc.h"
#include "fc7xxx_driver_scg.h"
#include "fc7xxx_board_conf.h"
/***************** mcaro *********************/
/* PCC property MACRO, defines every peripheral clock system architecture */
#define PCC_CLK_NOT_APPLY (0U)
#define PCC_CGC_AVAILABLE (1U << 0U)
#define PCC_FUNCCLK_MUXDIVH_USED (1U << 1U)
#define PCC_FUNCCLK_MUXDIVM_USED (1U << 2U)
#define PCC_FUNCCLK_MUXDIVL_USED (1U << 3U)
#define PCC_FUNCCLK_MUXDIVHPIN_USED (1U << 4U)
#define PCC_MOUDULE_DIV_USED (1U << 5U)
#define PCC_CLK_DOMAIN_CORE (1U << 6U)
#define PCC_CLK_DOMAIN_BUS (1U << 7U)
#define PCC_CLK_DOMAIN_SLOW (1U << 8U)
#define PCC_DWP_SWR_AVAILABLE (0U << 9U)
#define PCC_PROPERTY_MUXDIV_MASK (PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVM_USED | PCC_FUNCCLK_MUXDIVL_USED)
#define PCC_PROPERTY_MUXDIV_ALL_MASK (PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVM_USED | PCC_FUNCCLK_MUXDIVL_USED | PCC_FUNCCLK_MUXDIVHPIN_USED)
/***************** Type define *********************/
/**
* @brief PCC clock attribution.
* @param u32RegOffset: the register offset base on PCC module base address 0x4002_4000h
* @param u8ClockProperty include clock domain and clock MUX information by bit filed setting.
*/
typedef struct
{
uint32_t u32RegOffset;
uint32_t u32ClockProperty;
} PCC_ClockMapType;
/**
* @brief PCC peripheral clock index map to SCG clock source
* @param ePccClkIndex: PCC peripheral clock index
* @param eScgClkIndex SCG clock source
*/
typedef struct
{
PCC_ClkGateSrcType ePccClkIndex;
SCG_ClkSrcType eScgClkIndex;
} PCC_ClockIndexMap;
/***************** Local Variables *********************/
/**
* @brief PCC clock index to SCG clock source map.
*/
static const PCC_ClockIndexMap s_tPccClocIndexkMap[PCC_MUX_MAX_NUMBER] = {
{PCC_CLKGATE_SRC_OFF_OR_TCLK, SCG_END_OF_CLOCKS},
{PCC_CLKGATE_SRC_FOSCDIV, SCG_FOSCDIVH_CLK},
{PCC_CLKGATE_SRC_SIRCDIV, SCG_SIRCDIVH_CLK},
{PCC_CLKGATE_SRC_FIRCDIV, SCG_FIRCDIVH_CLK},
{PCC_CLKGATE_SRC_RESERVE0, SCG_END_OF_CLOCKS},
{PCC_CLKGATE_SRC_PLL1DIV, SCG_PLL1DIVH_CLK},
{PCC_CLKGATE_SRC_PLL0DIV, SCG_PLL0DIVH_CLK},
{PCC_CLKGATE_SRC_RESERVE1, SCG_END_OF_CLOCKS}
};
/**
* @brief clock attribution map.
*/
static const PCC_ClockMapType s_tPccClockMap[PCC_END_OF_CLOCKS] =
{
{0x20, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* DMA0 */
{0x28, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* DMAMUX0 */
{0x4C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* ROMC */
{0x60, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* ERM0 */
{0x64, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* EIM0 */
{0x68, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* INTM0 */
{0x6C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* ISM0 */
{0x88, PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* WDOG0 */
{0x98, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* TRGSEL0 */
{0x9C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* TRGSEL1 */
{0xA0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* TRGSEL2 */
{0xA4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* TRGSEL3 */
{0xA8, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* CRC0 */
{0xAC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* CORDIC */
{0xB0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* TSTMP0 */
{0xB4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* TSTMP1 */
{0xB8, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_DWP_SWR_AVAILABLE}, /* FCPIT0 */
{0xBC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_FUNCCLK_MUXDIVL_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* AONTIMER0 */
{0xC0, PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* RTC */
{0xC4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMU0 */
{0xC8, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMU1 */
{0xCC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMU2 */
{0xD0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMU3 */
{0xD4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMU4 */
{0xDC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* PTIMER0 */
{0xE0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* PTIMER1 */
{0xEC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* ADC0 */
{0xF0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* ADC1 */
{0xFC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* WKU0 */
{0x100, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMP0 */
{0x104, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMP1 */
{0x10C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_FUNCCLK_MUXDIVL_USED | PCC_DWP_SWR_AVAILABLE}, /* TMU0 */
{0x150, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVL_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* SENT0 */
{0x160, PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* MB0 */
{0x170, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU0 */
{0x174, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU1 */
{0x178, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU2 */
{0x17C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU3 */
{0x188, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCSPI0 */
{0x18C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCSPI1 */
{0x190, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCSPI2 */
{0x198, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCIIC0 */
{0x1A0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART0 */
{0x1A4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART1 */
{0x1A8, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART2 */
{0x1AC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART3 */
{0x1C0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* LU0 */
{0x1E0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* FREQM */
{0x1FC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* STCU */
{0x200, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* FLEXCAN0 */
{0x210, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* FLEXCAN1 */
{0x34C, PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* WDOG1 */
{0x36C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* TRGSEL4 */
{0x370, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* TRGSEL5 */
{0x37C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCSPI3 */
{0x380, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCSPI4 */
{0x384, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCSPI5 */
{0x3FC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU4 */
{0x400, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU5 */
{0x404, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU6 */
{0x408, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU7 */
{0x41C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCIIC1 */
{0x420, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART4 */
{0x424, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART5 */
{0x428, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART6 */
{0x42C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART7 */
{0x450, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* MSC0 */
{0x480, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* FLEXCAN2 */
{0x490, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* FLEXCAN3 */
};
/***************** Local Prototype Functions *********************/
/***************** Local Functions *********************/
/***************** Global Functions *********************/
/**
* @brief get PCC function clock status and value.
*
* @param pcc_ClkSrcType eClockName: used for choose PCC clock source to query.
*/
uint32_t PCC_GetPccFunctionClock(const PCC_ClkSrcType eClockName)
{
uint32_t u32DivVal;
PCC_ClkGateSrcType eSelVal;
uint32_t u32ScgClkIndex = 0U;
uint32_t u32FunctionFreqVal = 0U;
uint32_t u32RegVal, u32ScgClkDivIndex;
const PCC_ClockMapType *pAttributeVal;
DEV_ASSERT((uint32_t)eClockName < (uint32_t)PCC_END_OF_CLOCKS);
/* Get peripheral PCC register value */
u32RegVal = PCC_HWA_GetRegister(s_tPccClockMap[(uint32_t)eClockName].u32RegOffset);
pAttributeVal = &s_tPccClockMap[(uint32_t)eClockName];
/* Check peripheral PCC is valid or not and peripheral have function clock or not */
if ((PCC_CGC_MASK == (u32RegVal & PCC_CGC_MASK)) && (0U != (pAttributeVal->u32ClockProperty & PCC_PROPERTY_MUXDIV_ALL_MASK)))
{
eSelVal = (PCC_ClkGateSrcType)((uint8_t)PCC_GetSEL(u32RegVal));
/* Get PCC divide value */
if (PCC_MOUDULE_DIV_USED == (pAttributeVal->u32ClockProperty & PCC_MOUDULE_DIV_USED))
{
u32DivVal = PCC_GetDIV(u32RegVal) + (uint32_t)1U;
}
else
{
u32DivVal = 1U;
}
/* Get peripheral function clock source which is from SCG or TCLK */
if (PCC_CLKGATE_SRC_OFF_OR_TCLK == eSelVal)
{
if (PCC_FUNCCLK_MUXDIVHPIN_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVHPIN_USED))
{
u32FunctionFreqVal = PCC_FTU_TCLK_FREQ;
}
else
{
u32FunctionFreqVal = 0U;
}
}
else
{
if (PCC_FUNCCLK_MUXDIVH_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVH_USED))
{
u32ScgClkDivIndex = 0U;
}
else if (PCC_FUNCCLK_MUXDIVM_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVM_USED))
{
u32ScgClkDivIndex = 1U;
}
else if (PCC_FUNCCLK_MUXDIVL_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVL_USED))
{
u32ScgClkDivIndex = 2U;
}
else
{
u32ScgClkDivIndex = 0U;
}
u32ScgClkIndex = (uint32_t)s_tPccClocIndexkMap[eSelVal].eScgClkIndex + u32ScgClkDivIndex;
}
/* If clock source is valid, calculate peripheral function clock */
if (u32ScgClkIndex < (uint32_t)SCG_END_OF_CLOCKS)
{
u32FunctionFreqVal = SCG_GetScgClockFreq((SCG_ClkSrcType)u32ScgClkIndex) / u32DivVal;
}
}
return u32FunctionFreqVal;
}
/**
* @brief get PCC interface clock status and value.
*
* @param pcc_ClkSrcType eClockName: used for choose PCC clock source to query.
*/
uint32_t PCC_GetPccInterfaceClock(const PCC_ClkSrcType eClockName)
{
uint32_t u32InterfaceFreqVal, u32AttributeVal;
DEV_ASSERT((uint32_t)eClockName < (uint32_t)PCC_END_OF_CLOCKS);
u32AttributeVal = s_tPccClockMap[(uint32_t)eClockName].u32ClockProperty;
if (PCC_CLK_DOMAIN_BUS == (u32AttributeVal & PCC_CLK_DOMAIN_BUS))
{
u32InterfaceFreqVal = SCG_GetScgClockFreq(SCG_BUS_CLK);
}
else if (PCC_CLK_DOMAIN_SLOW == (u32AttributeVal & PCC_CLK_DOMAIN_SLOW))
{
u32InterfaceFreqVal = SCG_GetScgClockFreq(SCG_SLOW_CLK);
}
else
{
u32InterfaceFreqVal = 0U;
}
return u32InterfaceFreqVal;
}
/**
* @brief set PCC one peripheral clock configuration.
*
* @param PCC_CtrlType* pConfig: the PCC initialize value point set by user.
* @return PCC_StatusType pcc function status
*/
PCC_StatusType PCC_SetPcc(const PCC_CtrlType *const pConfig)
{
PCC_StatusType eStatus = PCC_STATUS_SUCCESS;
uint32_t u32DivVal;
uint32_t u32ScgClkIndex = 0U, u32ScgClkDivIndex;
uint32_t u32FreqVal = 0U;
uint32_t u32FunctionFreqVal = 0U;
uint32_t u32RegVal = 0U;
uint32_t u32ExpectedRegVal;
const PCC_ClockMapType *pAttributeVal;
DEV_ASSERT(NULL_PTR != pConfig);
DEV_ASSERT((uint32_t)pConfig->eClockName < (uint32_t)PCC_END_OF_CLOCKS);
pAttributeVal = &s_tPccClockMap[(uint32_t)pConfig->eClockName];
/* check peripheral clock domain to calculate module clock */
if (PCC_CLK_DOMAIN_BUS == (pAttributeVal->u32ClockProperty & PCC_CLK_DOMAIN_BUS))
{
u32FreqVal = SCG_GetScgClockFreq(SCG_BUS_CLK);
}
else if (PCC_CLK_DOMAIN_SLOW == (pAttributeVal->u32ClockProperty & PCC_CLK_DOMAIN_SLOW))
{
u32FreqVal = SCG_GetScgClockFreq(SCG_SLOW_CLK);
}
else
{
/* Do nothing */
}
if (0U == u32FreqVal)
{
/* Please call SCG function first */
eStatus = PCC_STATUS_CLOCK_INVALID;
}
if (PCC_STATUS_SUCCESS == eStatus)
{
/* Disable PCC gate */
PCC_HWA_SetClockGateControl(pAttributeVal->u32RegOffset,false);
if (pConfig->bEn)
{
if (PCC_MOUDULE_DIV_USED == (pAttributeVal->u32ClockProperty & PCC_MOUDULE_DIV_USED))
{
u32DivVal = (uint32_t)pConfig->eDivider + (uint32_t)1U;
u32RegVal |= PCC_DIV(pConfig->eDivider);
}
else
{
u32DivVal = 1U;
}
if (0U != (pAttributeVal->u32ClockProperty & PCC_PROPERTY_MUXDIV_ALL_MASK))
{
u32RegVal |= PCC_SEL(pConfig->eClkSrc);
}
if (PCC_CGC_AVAILABLE == (pAttributeVal->u32ClockProperty & PCC_CGC_AVAILABLE))
{
/* Enable peripheral clock */
u32RegVal |= PCC_CGC_MASK;
}
/* Configure PCC register */
PCC_HWA_SetRegister(pAttributeVal->u32RegOffset,u32RegVal);
/* Get peripheral function clock source which is from SCG or TCLK */
if (PCC_CLKGATE_SRC_OFF_OR_TCLK == pConfig->eClkSrc)
{
if (PCC_FUNCCLK_MUXDIVHPIN_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVHPIN_USED))
{
u32FunctionFreqVal = PCC_FTU_TCLK_FREQ;
}
else
{
u32FunctionFreqVal = 0U;
}
}
else if (PCC_CLKGATE_UNINVOLVED == pConfig->eClkSrc)
{
/* do nothing */
}
else
{
if (PCC_FUNCCLK_MUXDIVH_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVH_USED))
{
u32ScgClkDivIndex = 0U;
}
else if (PCC_FUNCCLK_MUXDIVM_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVM_USED))
{
u32ScgClkDivIndex = 1U;
}
else if (PCC_FUNCCLK_MUXDIVL_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVL_USED))
{
u32ScgClkDivIndex = 2U;
}
else
{
u32ScgClkDivIndex = 0U;
}
u32ScgClkIndex = (uint32_t)s_tPccClocIndexkMap[(uint32_t)pConfig->eClkSrc].eScgClkIndex + u32ScgClkDivIndex;
}
/* Calculate peripheral function clock */
if (u32ScgClkIndex < (uint32_t)SCG_END_OF_CLOCKS)
{
u32FunctionFreqVal = SCG_GetScgClockFreq((SCG_ClkSrcType)u32ScgClkIndex) / u32DivVal;
}
u32ExpectedRegVal = u32RegVal;
}
else
{
/* Clear PCC register */
PCC_HWA_SetRegister(pAttributeVal->u32RegOffset,0U);
u32ExpectedRegVal = 0U;
u32FunctionFreqVal = 0U;
}
/* Check PCC register has been configured, If current CPU do not have permission to configure the PCC register, the except value
* will not match the actual value */
if (u32ExpectedRegVal != PCC_HWA_GetRegister(pAttributeVal->u32RegOffset))
{
/* In this case, current core does not have permission to control the register */
eStatus = PCC_STATUS_CONFIGURED_NOT_SUPPORT;
}
else if (u32FunctionFreqVal > 160000000U)
{
/* In this case, current function clock too high, must configured below 150M */
eStatus = PCC_STATUS_CONFIGURED_NOT_SUPPORT;
}
else
{
/* do nothing */
}
}
return eStatus;
}
/**
* @brief Generate peripheral reset
*
*/
void PCC_GenPeripheralReset(const PCC_ClkSrcType eClockName)
{
DEV_ASSERT((uint32_t)eClockName < (uint32_t)PCC_END_OF_CLOCKS);
PCC_HWA_SoftwareReset(s_tPccClockMap[(uint32_t)eClockName].u32RegOffset);
}

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Src/fc7xxx_driver_pmc.c Normal file
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@ -0,0 +1,175 @@
/* @file fc7xxx_driver_pmc.c
* @author Flagchip032
* @brief FC7xxx PMC driver type definition and API
* @version 0.1.0
* @date 2022-11-21
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials Descriptions
* --------- ---------- ------------ ---------------
* 0.1.0 2022-11-21 Flagchip032 First version for FC7xxx
******************************************************************************** */
#include "fc7xxx_driver_pmc.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/***************** Local variable *********************/
static PMC_VolIntCallbackType pIsrNotify = NULL_PTR;
/***************** prototype *********************/
/**
* @brief PMC interrupt function entry
*
*/
void PMC_IRQHandler(void);
/***************** Global Functions *********************/
/**
* @brief Get LVCSRRegister Value
*
* @return uint32_t LVCSRRegister Value
*/
uint32_t PMC_GetLVCSRRegister(void)
{
return PMC_HWA_GetLVCSRRegister();
}
/**
* @brief Get All voltage flag
*
* @return uint32_t All voltage flag
*/
uint32_t PMC_GetAllVolFlag(void)
{
uint32_t u32AllVolFlag = 0U;
u32AllVolFlag = (PMC_HWA_GetLVCSRRegister() & PMC_LVCSR_ALLFLAG_MASK);
return u32AllVolFlag;
}
/**
* @brief Get specific voltage flag
*
* @param eFlag Voltage flag
* @return boolean If return true, the specific voltage flag is 0, otherwise, the flag is 1.
*/
boolean PMC_GetSpecificVolFlag(const PMC_FlagType eFlag)
{
return ((PMC_HWA_GetLVCSRRegister() & eFlag) != 0U) ? true : false;
}
/**
* @brief Clear all voltage flag
*
*/
void PMC_ClearAllVolFlag(void)
{
PMC_HWA_SetLVCSRRegister(PMC_LVCSR_ALLFLAG_MASK);
}
/**
* @brief Clear specific voltage flag
*
* @param eFlag Voltage flag
*/
void PMC_ClearSpecificVolFlag(const PMC_FlagType eFlag)
{
PMC_HWA_SetLVCSRRegister(eFlag);
}
/**
* @brief Get All voltage status
*
* @return uint32_t All voltage status
*/
uint32_t PMC_GetAllVolStatus(void)
{
uint32_t u32AllVolStatus = 0U;
u32AllVolStatus = (PMC_HWA_GetLVCSRRegister() & PMC_LVCSR_ALLSTATUS_MASK);
return u32AllVolStatus;
}
/**
* @brief Get specific voltage status
*
* @param eStatus Specific voltage status
* @return boolean If return true, the specific voltage status is 0, otherwise, the status is 1.
*/
boolean PMC_GetSpecificVolStatus(const PMC_StatusType eStatus)
{
return ((PMC_HWA_GetLVCSRRegister() & eStatus) != 0U) ? true : false;
}
/**
* @brief Configure Voltage
*
* @param pCtrl Configuration of voltage
*/
void PMC_ConfigVoltage(const PMC_CtrlType *const pCtrl)
{
uint32_t u32ConfigVal = 0U;
PMC_HWA_UnlockConfigRegister();
if ((pCtrl->bLvdIntEn) || (pCtrl->bHvdIntEn) || (pCtrl->b5VBMonEn) \
|| (pCtrl->bRpmV25En) || (pCtrl->bV15AutoswEn) || (pCtrl->bV15CtrlEn))
{
pIsrNotify = pCtrl->pIsrNotify;
}
u32ConfigVal = PMC_CONFIG_LVD_IE(pCtrl->bLvdIntEn) | PMC_CONFIG_HVD_IE(pCtrl->bHvdIntEn) | PMC_CONFIG_V15_CTRL_EN(pCtrl->bV15CtrlEn) | PMC_CONFIG_V15_AUTOSW(
pCtrl->bV15AutoswEn) | PMC_CONFIG_RPM_VDD2P5_EN(pCtrl->bRpmV25En);
PMC_HWA_SetConfigRegister(u32ConfigVal);
}
/**
* @brief Clear all PMC register
*
*/
void PMC_Deinit(void)
{
PMC_HWA_SetLVCSRRegister(0x93ff0030U);
PMC_HWA_SetConfigRegister(0x8000U);
}
/**
* @brief PMC interrupt function entry
*
*/
void PMC_IRQHandler(void)
{
if (NULL_PTR != pIsrNotify)
{
pIsrNotify();
}
if(PMC_GetSpecificVolFlag(PMC_HVD5V_FLAG))
{
PMC_ClearSpecificVolFlag(PMC_HVD5V_FLAG);
}
if (PMC_GetSpecificVolFlag(PMC_HVD2P5V_FLAG))
{
PMC_ClearSpecificVolFlag(PMC_HVD2P5V_FLAG);
}
if (PMC_GetSpecificVolFlag(PMC_HVD1P1V_FLAG))
{
PMC_ClearSpecificVolFlag(PMC_HVD1P1V_FLAG);
}
if (PMC_GetSpecificVolFlag(PMC_LVD5V_FLAG))
{
PMC_ClearSpecificVolFlag(PMC_LVD5V_FLAG);
}
if (PMC_GetSpecificVolFlag(PMC_LVD1P5V_FLAG))
{
PMC_ClearSpecificVolFlag(PMC_LVD1P5V_FLAG);
}
if (PMC_GetSpecificVolFlag(PMC_HVD1P5V_FLAG))
{
PMC_ClearSpecificVolFlag(PMC_HVD1P5V_FLAG);
}
}

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/**
* @file fc7xxx_driver_port.c
* @author Flagchip
* @brief FC7xxx PORT driver type definition and API
* @version 0.1.0
* @date 2023-2-4
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 31/12/2022 Flagchip0121 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_port.h"
#include "interrupt_manager.h"
/** @brief PORTA interrupt entry */
void PORTA_IRQHandler(void);
/** @brief PORTB interrupt entry */
void PORTB_IRQHandler(void);
/** @brief PORTC interrupt entry */
void PORTC_IRQHandler(void);
/** @brief PORTD interrupt entry */
void PORTD_IRQHandler(void);
/** @brief PORTE interrupt entry */
void PORTE_IRQHandler(void);
/********* Local Variables ************/
/** @brief PORT instance list */
static PORT_Type *const s_pPortInstanceTable[PORT_INSTANCE_COUNT] = PORT_BASE_PTRS;
/** @brief PORT user defined interrupt function */
static PORT_PinInterruptCallBackType s_pPortPinNotifyTable[PORT_PIN_NUM_MAX] = {NULL};
/** @brief PORT interrupt mode table */
static PORT_IntConfigType s_aPortPinIrqTable[PORT_PIN_NUM_MAX] = {PORT_IRQ_DISABLE};
/** @brief port common interrupt handle function */
static void Port_CommonProcessInterrupt(const PORT_InstanceType ePort, const uint8_t u8Pin);
/***************PORT Global Functions*****************/
/**
* @brief Initialize port
*
* @param ePort Port instance
* @param pInitStruct Initialization structure of port
* @return Port return type.
*/
PORT_StatusType PORT_InitPins(const PORT_InstanceType ePort, const PORT_InitType *const pInitStruct)
{
PORT_StatusType eRet = PORT_STATUS_SUCCESS;
PORT_Type *pPort;
uint32_t u32PcrRegValue = 0U;
uint32_t u32LowPcrRegValue = 0U;
uint32_t u32HighPcrRegValue = 0U;
if (((uint32_t)ePort >= PORT_INSTANCE_COUNT) || (NULL == pInitStruct))
{
eRet = PORT_STATUS_PARAM_INVALID;
}
else
{
pPort = s_pPortInstanceTable[(uint32_t)ePort];
u32PcrRegValue |= PORT_PCR_MUX(pInitStruct->uPortPinMux.u32PortPinMode);
u32PcrRegValue |= PORT_PCR_IRQC(pInitStruct->eTriggrtMode);
u32PcrRegValue |= PORT_PCR_PE(pInitStruct->bPullEn);
u32PcrRegValue |= PORT_PCR_PS(pInitStruct->ePullSel);
u32PcrRegValue |= PORT_PCR_DSE0(pInitStruct->bDrvStrength0En);
u32PcrRegValue |= PORT_PCR_DSE1(pInitStruct->bDrvStrength1En);
u32PcrRegValue |= PORT_PCR_PFE(pInitStruct->u8PassiveFilterEn);
u32PcrRegValue |= PORT_PCR_ISF_MASK;
u32LowPcrRegValue = u32PcrRegValue & PORT_PCR_LOW_16BITS_MASK;
u32HighPcrRegValue = u32PcrRegValue & PORT_PCR_HIGH_16BITS_MASK;
PORT_HWA_WriteGPCLR(pPort,pInitStruct->u32PortPins,u32LowPcrRegValue);
PORT_HWA_WriteGPCHR(pPort,pInitStruct->u32PortPins,u32LowPcrRegValue);
PORT_HWA_WriteGICLR(pPort,pInitStruct->u32PortPins,u32HighPcrRegValue);
PORT_HWA_WriteGICHR(pPort,pInitStruct->u32PortPins,u32HighPcrRegValue);
}
return eRet;
}
/**
* @brief De-initialize the Port instance
*
* @param ePort Port instance enumeration
* @param u32Pins The bit of u32Pins indicate the Pin number of this Port.
* @return Port return type.
*/
PORT_StatusType PORT_Deinit(const PORT_InstanceType ePort, const uint32_t u32Pins)
{
PORT_StatusType eRet = PORT_STATUS_SUCCESS;
PORT_Type *pPort = s_pPortInstanceTable[ePort];
uint8_t u8PinIndex = 0U;
uint32_t u32TempPins = u32Pins;
if ((uint32_t)ePort >= PORT_INSTANCE_COUNT)
{
eRet = PORT_STATUS_PARAM_INVALID;
}
else
{
while (u32TempPins != 0u)
{
if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u)
{
PORT_HWA_ConfigPin(pPort, u8PinIndex, (uint32_t)0U);
s_aPortPinIrqTable[PORT_PIN_NUM(ePort, u8PinIndex)] = PORT_IRQ_DISABLE;
s_pPortPinNotifyTable[PORT_PIN_NUM(ePort, u8PinIndex)] = NULL;
}
u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex);
u8PinIndex++;
}
}
return eRet;
}
/**
* @brief Enable interrupt function of port
*
* @param ePort Port instance enumeration
* @param pIntStruct Interrupt structure of port.
* @return Port return type.
*/
PORT_StatusType PORT_InitInterrupt(const PORT_InstanceType ePort, const PORT_InterruptType *const pIntStruct)
{
PORT_StatusType eRet = PORT_STATUS_SUCCESS;
uint8_t u8PinIndex = 0U;
uint32_t u32TempPins = 0U;
PORT_Type *pPort = s_pPortInstanceTable[ePort];
if (((uint32_t)ePort >= PORT_INSTANCE_COUNT) || (NULL == pIntStruct))
{
eRet = PORT_STATUS_PARAM_INVALID;
}
else
{
u32TempPins = pIntStruct->u32PortPins;
while (u32TempPins != 0u)
{
if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u)
{
PORT_HWA_ClearPinInterruptFlag(pPort, u8PinIndex);
PORT_HWA_SetPinInterruptMode(pPort, u8PinIndex, (PORT_IntConfigType)pIntStruct->ePortIsrMode);
s_aPortPinIrqTable[PORT_PIN_NUM(ePort, u8PinIndex)] = pIntStruct->ePortIsrMode;
if (NULL != pIntStruct->pIsrNotify)
{
s_pPortPinNotifyTable[PORT_PIN_NUM(ePort, u8PinIndex)] = pIntStruct->pIsrNotify;
}
}
u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex);
u8PinIndex++;
}
/* IntMgr_EnableInterrupt((IRQn_Type)((uint32_t)PORTA_IRQn + (uint32_t)ePort)); */
}
return eRet;
}
/**
* @brief Enable interrupt function of port
*
* @param ePort Port instance enumeration
* @param u32Pins The bit of u32Pins indicate the Pin number of this Port.
* @return Port return type.
*/
PORT_StatusType PORT_EnableInterrupt(const PORT_InstanceType ePort, const uint32_t u32Pins)
{
PORT_StatusType eRet = PORT_STATUS_SUCCESS;
uint8_t u8PinIndex = 0U;
uint32_t u32TempPins = u32Pins;
PORT_Type *pPort = s_pPortInstanceTable[ePort];
if ((uint32_t)ePort >= PORT_INSTANCE_COUNT)
{
eRet = PORT_STATUS_PARAM_INVALID;
}
else
{
while (u32TempPins != 0u)
{
if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u)
{
PORT_HWA_ClearPinInterruptFlag(pPort, u8PinIndex);
PORT_HWA_SetPinInterruptMode(pPort, u8PinIndex, (PORT_IntConfigType)s_aPortPinIrqTable[PORT_PIN_NUM(ePort,
u8PinIndex)]);
}
u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex);
u8PinIndex++;
}
}
return eRet;
}
/**
* @brief Disable interrupt function of port
*
* @param ePort Port instance enumeration
* @param u32Pins The bit of u32Pins indicate the Pin number of this Port.
* @return Port return type.
*/
PORT_StatusType PORT_DisableInterrupt(const PORT_InstanceType ePort, const uint32_t u32Pins)
{
PORT_StatusType eRet = PORT_STATUS_SUCCESS;
uint8_t u8PinIndex = 0U;
uint32_t u32TempPins = u32Pins;
PORT_Type *pPort = s_pPortInstanceTable[ePort];
if ((uint32_t)ePort >= PORT_INSTANCE_COUNT)
{
eRet = PORT_STATUS_PARAM_INVALID;
}
else
{
while (u32TempPins != 0u)
{
if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u)
{
PORT_HWA_ClearPinInterruptFlag(pPort, u8PinIndex);
PORT_HWA_ClearPinInterruptMode(pPort, u8PinIndex);
}
u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex);
u8PinIndex++;
}
}
return eRet;
}
PORT_StatusType PORT_SetPinsDmaReqMode(const PORT_InstanceType ePort, const uint32_t u32Pins, const PORT_DMAReqType eDMAReqMode)
{
PORT_StatusType eRet = PORT_STATUS_SUCCESS;
uint8_t u8PinIndex = 0U;
uint32_t u32TempPins = u32Pins;
PORT_Type *pPort = s_pPortInstanceTable[ePort];
if ((uint32_t)ePort >= PORT_INSTANCE_COUNT)
{
eRet = PORT_STATUS_PARAM_INVALID;
}
else
{
while (u32TempPins != 0u)
{
if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u)
{
PORT_HWA_SetPinDMAReqMode(pPort, u8PinIndex, eDMAReqMode);
}
u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex);
u8PinIndex++;
}
}
return eRet;
}
/**
* @brief Initialize digital filter for Port instance
*
* @param ePort Port instance enumeration
* @param pDFStruct Digital filter initialization structure of port
* @return Port return type.
*/
PORT_StatusType PORT_InitDigitalFilterPort(const PORT_InstanceType ePort, const PORT_DigitalFilterType *pDFStruct)
{
PORT_StatusType eRet = PORT_STATUS_SUCCESS;
PORT_Type *pPort = s_pPortInstanceTable[ePort];
if ((NULL == pDFStruct) || ((uint32_t)ePort >= PORT_INSTANCE_COUNT))
{
eRet = PORT_STATUS_PARAM_INVALID;
}
else
{
if (pDFStruct->u32PortPinsEn != 0u)
{
if (PORT_FILTER_AON32K_CLK == pDFStruct->eClkSrc)
{
PORT_HWA_SetDigitalFilterClkSrc(pPort, pDFStruct->eClkSrc);
}
else
{
PORT_HWA_ClearDigitalFilterClkSrc(pPort);
}
PORT_HWA_ConfigDigitalFilterWidth(pPort, (uint32_t)pDFStruct->u8FilterLength);
PORT_HWA_ConfigDigitalFilter(pPort, pDFStruct->u32PortPinsEn);
}
}
return eRet;
}
/**
* @brief De-initialize digital filter for Port instance
*
* @param ePort Port instance enumeration
* @return Port return type.
*/
PORT_StatusType PORT_DeinitDigitalFilterPort(const PORT_InstanceType ePort)
{
PORT_StatusType eRet = PORT_STATUS_SUCCESS;
PORT_Type *pPort = s_pPortInstanceTable[ePort];
if ((uint32_t)ePort >= PORT_INSTANCE_COUNT)
{
eRet = PORT_STATUS_PARAM_INVALID;
}
else
{
PORT_HWA_ClearDigitalFilterClkSrc(pPort);
PORT_HWA_ClearDigitalFilterWidth(pPort);
PORT_HWA_ClearDigitalFilterEnable(pPort);
}
return eRet;
}
/**
* @brief Enable the digital filter function for the specific pin.
*
* @param ePort Port instance enumeration
* @param u32Pins The bit of u32Pins indicate the Pin number of this Port.
* @return Port return type.
*/
PORT_StatusType PORT_EnableDigitalFilterPin(const PORT_InstanceType ePort, const uint32_t u32Pins)
{
PORT_StatusType eRet = PORT_STATUS_SUCCESS;
uint8_t u8PinIndex = 0U;
uint32_t u32TempPins = u32Pins;
PORT_Type *pPort;
if ((uint32_t)ePort >= PORT_INSTANCE_COUNT)
{
eRet = PORT_STATUS_PARAM_INVALID;
}
else
{
pPort = s_pPortInstanceTable[ePort];
while (u32TempPins != 0u)
{
if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u)
{
PORT_HWA_SetDigitalFilterEnable(pPort, u8PinIndex);
}
u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex);
u8PinIndex++;
}
}
return eRet;
}
/**
* @brief Disable the digital filter function for the specific pin.
*
* @param ePort Port instance enumeration
* @param u32Pins The bit of u32Pins indicate the Pin number of this Port.
*/
PORT_StatusType PORT_DisableDigitalFilterPin(const PORT_InstanceType ePort, const uint32_t u32Pins)
{
PORT_StatusType eRet = PORT_STATUS_SUCCESS;
uint8_t u8PinIndex = 0U;
uint32_t u32TempPins = u32Pins;
PORT_Type *pPort;
if ((uint32_t)ePort >= PORT_INSTANCE_COUNT)
{
eRet = PORT_STATUS_PARAM_INVALID;
}
else
{
pPort = s_pPortInstanceTable[ePort];
while (u32TempPins != 0u)
{
if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u)
{
PORT_HWA_ClearDigitalFilterPin(pPort, u8PinIndex);
}
u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex);
u8PinIndex++;
}
}
return eRet;
}
/**
* \brief port common interrupt handle function
*
* \param ePort port instance
* \param u8Pin bit of u8Pin indicate pin number
*/
static void Port_CommonProcessInterrupt(const PORT_InstanceType ePort, const uint8_t u8Pin)
{
if (NULL != s_pPortPinNotifyTable[PORT_PIN_NUM(ePort, u8Pin)])
{
s_pPortPinNotifyTable[PORT_PIN_NUM(ePort, u8Pin)]();
}
}
/***************PORT IRQ Functions*****************/
/**
* \brief PORTA interrupt entry
*
*/
void PORTA_IRQHandler(void)
{
uint8_t u8PinIndex;
for (u8PinIndex = 0U; u8PinIndex < (uint32_t)32; u8PinIndex++)
{
if (PORT_HWA_ReadPinInterruptFlag(PORTA, u8PinIndex))
{
PORT_HWA_ClearPinInterruptFlag(PORTA, u8PinIndex);
Port_CommonProcessInterrupt(PORT_A, u8PinIndex);
}
}
}
/**
* \brief PORTB interrupt entry
*
*/
void PORTB_IRQHandler(void)
{
uint8_t u8PinIndex;
for (u8PinIndex = 0U; u8PinIndex < (uint8_t)32; u8PinIndex++)
{
if (PORT_HWA_ReadPinInterruptFlag(PORTB, u8PinIndex))
{
PORT_HWA_ClearPinInterruptFlag(PORTB, u8PinIndex);
Port_CommonProcessInterrupt(PORT_B, u8PinIndex);
}
}
}
/**
* \brief PORTC interrupt entry
*
*/
void PORTC_IRQHandler(void)
{
uint8_t u8PinIndex;
for (u8PinIndex = 0U; u8PinIndex < (uint8_t)32; u8PinIndex++)
{
if (PORT_HWA_ReadPinInterruptFlag(PORTC, u8PinIndex))
{
PORT_HWA_ClearPinInterruptFlag(PORTC, u8PinIndex);
Port_CommonProcessInterrupt(PORT_C, u8PinIndex);
}
}
}
/**
* \brief PORTD interrupt entry
*
*/
void PORTD_IRQHandler(void)
{
uint8_t u8PinIndex;
for (u8PinIndex = 0U; u8PinIndex < (uint8_t)32; u8PinIndex++)
{
if (PORT_HWA_ReadPinInterruptFlag(PORTD, u8PinIndex))
{
PORT_HWA_ClearPinInterruptFlag(PORTD, u8PinIndex);
Port_CommonProcessInterrupt(PORT_D, u8PinIndex);
}
}
}
/**
* \brief PORTE interrupt entry
*
*/
void PORTE_IRQHandler(void)
{
uint8_t u8PinIndex;
for (u8PinIndex = 0U; u8PinIndex < (uint8_t)32; u8PinIndex++)
{
if (PORT_HWA_ReadPinInterruptFlag(PORTE, u8PinIndex))
{
PORT_HWA_ClearPinInterruptFlag(PORTE, u8PinIndex);
Port_CommonProcessInterrupt(PORT_E, u8PinIndex);
}
}
}

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/**
* @file fc7xxx_driver_ptimer.c
* @author Flagchip0126
* @brief FC7xxx PTIMER driver source code
* @version 0.1.0
* @date 2024-01-15
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Author CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240
******************************************************************************** */
#include <interrupt_manager.h>
#include "fc7xxx_driver_ptimer.h"
#include "fc7xxx_driver_scg.h"
#include "HwA_scm.h"
static PTIMER_Type *const s_apPtimerBase[PTIMER_INSTANCE_COUNT] = PTIMER_BASE_PTRS;
static uint8_t s_u8ChnNum[PTIMER_INSTANCE_COUNT] = {0U};
static PTIMER_InterruptCallbackType s_apPtimerIntNotify[PTIMER_INSTANCE_COUNT] = {NULL};
static PTIMER_SeqErrorCallbackType s_apPtimerSeqErrorNotify[ADC_INSTANCE_COUNT] = {NULL};
/**
* @brief Calculate the delay value base on the delay micro seconds
*
* @param eInstance the Ptimer instance to use
* @param u32DelayUs the delay time in micro seconds
* @return uint16_t the delay time in ptimer clock count
*/
static uint16_t PTIMER_CalcDelayValue(const PTIMER_InstanceType eInstance, const uint32_t u32DelayUs);
/**
* @brief the internal Ptimer interrupt handler
*
* @param eInstance the Ptimer instance to use
*/
static void PTIMERn_IRQHandler(const PTIMER_InstanceType eInstance);
void PTIMER0_IRQHandler(void);
void PTIMER1_IRQHandler(void);
static uint16_t PTIMER_CalcDelayValue(const PTIMER_InstanceType eInstance, const uint32_t u32DelayUs)
{
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
const PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
uint32_t u32DelayVal;
uint32_t u32SysFreq;
uint32_t u32PtimerFreqUs = 0U;
PTIMER_ClockPreDividerType ePreDivider = PTIMER_HWA_GetDivPrescaler(pPtimer);
PTIMER_ClockPreDivMultiplyFactorType ePreDivMultFactor = PTIMER_HWA_GetDivMultiply(pPtimer);
uint8_t u8Prescaler = (1U << ePreDivider);
uint8_t u8PrescalerMult = 1U;
switch (ePreDivMultFactor)
{
case PTIMER_PRE_DIVIDER_MULTIPLY_BY_1:
u8PrescalerMult = 1U;
break;
case PTIMER_PRE_DIVIDER_MULTIPLY_BY_10:
u8PrescalerMult = 10U;
break;
case PTIMER_PRE_DIVIDER_MULTIPLY_BY_20:
u8PrescalerMult = 20U;
break;
case PTIMER_PRE_DIVIDER_MULTIPLY_BY_40:
u8PrescalerMult = 40U;
break;
default:
u8PrescalerMult = 1U;
break;
}
u32SysFreq = SCG_GetScgClockFreq(SCG_CORE_CLK);
u32PtimerFreqUs = u32SysFreq / 1000000U;
u32DelayVal = (u32DelayUs * u32PtimerFreqUs) / ((uint32_t)u8Prescaler * u8PrescalerMult);
DEV_ASSERT(u32DelayVal < (1U << 16U));
return (uint16_t)u32DelayVal;
}
void PTIMER0_IRQHandler(void)
{
PTIMERn_IRQHandler(PTIMER_INSTANCE_0);
}
void PTIMER1_IRQHandler(void)
{
PTIMERn_IRQHandler(PTIMER_INSTANCE_1);
}
static void PTIMERn_IRQHandler(const PTIMER_InstanceType eInstance)
{
PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
uint8_t u8Channel;
if (PTIMER_HWA_GetInterruptFlag(pPtimer) == true)
{
PTIMER_HWA_ClearInterruptFlag(pPtimer);
if (s_apPtimerIntNotify[eInstance] != NULL)
{
s_apPtimerIntNotify[eInstance]();
}
}
for (u8Channel = 0U; u8Channel < s_u8ChnNum[eInstance]; u8Channel++)
{
if (PTIMER_HWA_GetChannelSequenceErrorFlag(pPtimer, u8Channel) == true)
{
PTIMER_HWA_ClearChannelSequenceErrorFlag(pPtimer, u8Channel);
if (s_apPtimerSeqErrorNotify[eInstance] != NULL)
{
s_apPtimerSeqErrorNotify[eInstance](u8Channel);
}
}
}
}
void PTIMER_DeInit(const PTIMER_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
uint8_t u8Chn;
/* Reset PTIMER Status Ctrl Register */
PTIMER_HWA_SetStatusCtrl(pPtimer, 0U);
/* Enable PTIMER */
PTIMER_HWA_Enable(pPtimer);
/* Reset PTIMER Max Cnt Register */
PTIMER_HWA_SetMaxCount(pPtimer, 0xFFFFU);
/* Reset PTIMER Int Dly Register */
PTIMER_HWA_SetInterruptDelay(pPtimer, 0xFFFFU);
for (u8Chn = 0U; u8Chn < PTIMER_DLY_CNT; u8Chn++)
{
PTIMER_HWA_SetChannelControl(pPtimer, u8Chn, false, false, false);
PTIMER_HWA_ClearChannelCounterFlag(pPtimer, u8Chn);
PTIMER_HWA_ClearChannelSequenceErrorFlag(pPtimer, u8Chn);
PTIMER_HWA_SetChannelDelay(pPtimer, u8Chn, 0U);
}
/* For Pulse out trigger. */
PTIMER_HWA_DisablePulseOut(pPtimer);
PTIMER_HWA_SetPulseOutDelay(pPtimer, 0U, 0U);
PTIMER_HWA_LoadValue(pPtimer);
PTIMER_HWA_Disable(pPtimer);
}
void PTIMER_Init(const PTIMER_InstanceType eInstance, const PTIMER_InitType *const pInitCfg)
{
DEV_ASSERT(pInitCfg != NULL_PTR);
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
PTIMER_Type *const pPtimer = s_apPtimerBase[(uint8_t)eInstance];
PTIMER_DeInit(eInstance);
PTIMER_HWA_SetLoadMode(pPtimer, pInitCfg->eLoadValueMode);
PTIMER_HWA_SetDivPrescaler(pPtimer, pInitCfg->eClkPreDiv);
PTIMER_HWA_SetTriggerSource(pPtimer, pInitCfg->eTriggerInput);
PTIMER_HWA_SetDivMultiply(pPtimer, pInitCfg->eClkPreMultFactor);
PTIMER_HWA_SetContinuoiusModeFlag(pPtimer, pInitCfg->bContinuousModeEnable);
PTIMER_HWA_SetDMAEnableFlag(pPtimer, pInitCfg->bDmaEnable);
}
void PTIMER_InitChannel(const PTIMER_InstanceType eInstance,
const PTIMER_ChannelCfgType aChannelCfg[], const uint8_t u8ChnNum)
{
DEV_ASSERT(aChannelCfg != NULL_PTR);
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
DEV_ASSERT(u8ChnNum <= PTIMER_DLY_CNT);
PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
uint8_t u8ChnIdx;
uint16_t u16PtimerChannelDelay ;
for (u8ChnIdx = 0U; u8ChnIdx < u8ChnNum; u8ChnIdx++)
{
PTIMER_HWA_SetChannelControl(pPtimer, u8ChnIdx, aChannelCfg[u8ChnIdx].bPreTriggerEnable,
aChannelCfg[u8ChnIdx].bPreTriggerOutputEnable, aChannelCfg[u8ChnIdx].bPreTriggerBackToBackEnable);
u16PtimerChannelDelay = PTIMER_CalcDelayValue(eInstance, aChannelCfg[u8ChnIdx].u32DelayUs);
PTIMER_HWA_SetChannelDelay(pPtimer, u8ChnIdx, u16PtimerChannelDelay);
}
s_u8ChnNum[eInstance] = u8ChnNum;
}
void PTIMER_InitInterrupt(const PTIMER_InstanceType eInstance,
const PTIMER_InterruptType *const pInterruptCfg)
{
DEV_ASSERT(pInterruptCfg != NULL_PTR);
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
PTIMER_HWA_SetSeqErrIntEnableFlag(pPtimer, pInterruptCfg->bSeqErrIntEnable);
uint16_t u16IntDelay = PTIMER_CalcDelayValue(eInstance, pInterruptCfg->u32IntDelayPeriodUs);
PTIMER_HWA_SetInterruptDelay(pPtimer, u16IntDelay);
PTIMER_HWA_SetInterruptEnableFlag(pPtimer, pInterruptCfg->bDelayIntEnable);
if (pInterruptCfg->bDelayIntEnable)
{
s_apPtimerIntNotify[eInstance] = pInterruptCfg->pIntNotify;
}
else
{
s_apPtimerIntNotify[eInstance] = NULL;
}
if (pInterruptCfg->bSeqErrIntEnable)
{
s_apPtimerSeqErrorNotify[eInstance] = pInterruptCfg->pSeqErrorNotify;
}
else
{
s_apPtimerSeqErrorNotify[eInstance] = NULL;
}
if ((pInterruptCfg->bSeqErrIntEnable == true) || (pInterruptCfg->bDelayIntEnable == true))
{
switch ((uint8_t)eInstance)
{
case (uint8_t)PTIMER_INSTANCE_0:
IntMgr_EnableInterrupt(PTIMER0_IRQn);
break;
case (uint8_t)PTIMER_INSTANCE_1:
IntMgr_EnableInterrupt(PTIMER1_IRQn);
break;
default:
break;
}
}
}
void PTIMER_SetPeriod(const PTIMER_InstanceType eInstance, uint32_t u32PeriodUs)
{
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
uint16_t u16MaxCnt = PTIMER_CalcDelayValue(eInstance, u32PeriodUs);
PTIMER_HWA_SetMaxCount(pPtimer, u16MaxCnt);
}
void PTIMER_SetPulseOut(const PTIMER_InstanceType eInstance, const PTIMER_PulseOutType *pPulseOutCfg)
{
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
DEV_ASSERT(pPulseOutCfg != NULL_PTR);
PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
uint16_t u16PulseOutCfgDlyHigh = PTIMER_CalcDelayValue(eInstance, pPulseOutCfg->u32PulseOutDlyHighUs);
uint16_t u16PulseOutCfgDlyLow = PTIMER_CalcDelayValue(eInstance, pPulseOutCfg->u32PulseOutDlyLowUs);
PTIMER_HWA_SetPulseOutDelay(pPtimer, u16PulseOutCfgDlyHigh, u16PulseOutCfgDlyLow);
}
void PTIMER_LoadValue(const PTIMER_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
PTIMER_HWA_LoadValue(pPtimer);
}
void PTIMER_Enable(const PTIMER_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
PTIMER_HWA_Enable(pPtimer);
}
void PTIMER_Disable(const PTIMER_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
PTIMER_HWA_Disable(pPtimer);
}
void PTIMER_EnablePulseOut(const PTIMER_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
PTIMER_HWA_EnablePulseOut(pPtimer);
}
void PTIMER_DisablePulseOut(const PTIMER_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
PTIMER_HWA_DisablePulseOut(pPtimer);
}
void PTIMER_SelectInstance01BackToBackMode(SCM_PTimerLMSelType ePTimerLoopMode)
{
SCM_HWA_PTimerLoopModeSel(ePTimerLoopMode);
}
void PTIMER_GenerateSWTrigger(const PTIMER_InstanceType eInstance)
{
DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT);
PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance];
PTIMER_HWA_GenerateSwTrigger(pPtimer);
}

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/**
* @file fc7xxx_driver_rgm.c
* @author Flagchip
* @brief FC7xxx RGM driver source code
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_rgm.h"
#include "interrupt_manager.h"
/** @brief Rgm user defined CPU0 core related system interrupt function */
static RGM_InterruptCallBackType s_pRgmCPU0PreIntPtr = NULL;
/** @brief Rgm pre-reset interrupt entry */
void RGM_Pre_IRQHandler(void);
/**
* @brief This api can get RGM_SRS register that indicate the source of the most recent reset.
*
* @return RGM->RGM_SRS register, bit 0-15,29-31 corresponding to RGM_ResetEventType, refer to reference manual for details.
* @note Multiple flags can be set if multiple reset events occur at the same time
*/
uint32_t RGM_GetLastResetFLag(void)
{
return RGM_HWA_ReadLastResetFlag();
}
/**
* @brief This api can get RGM_SSRS register that indicate all reset sources since the last POR or LVD that have not been cleared by software.
*
* @return RGM->RGM_SSRS register, bit 0-15,29-31 corresponding to RGM_ResetEventType, refer to reference manual for details.
*/
uint32_t RGM_GetAllResetFlag(void)
{
return RGM_HWA_ReadAllResetFlagBeforePOR();
}
/**
* @brief This api can clear reset flag of RGM_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
*
* @param eReset Enumeration of reset event flag
*/
void RGM_ClearResetFlagAfterPOR(const RGM_ResetEventType eReset)
{
RGM_HWA_ClearResetFlagAfterPOR(eReset);
}
/**
* @brief This api can clear all reset flag of RGM_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
*
*/
void RGM_ClearAllResetFlagAfterPOR(void)
{
RGM_HWA_ClearAllResetFlagAfterPOR();
}
/**
* @brief Enable reset pin filter
*
* @param eClk Reset pin filter clock source
* @param u8BusClockFilterWidth Bus clock filter width
* @param bLpClkEn select whether enable reset pin filter using AON32clock in low power mode
* @return RGM return type
* @note If use AON32K clock, A reset signal whose length is less than 2 AON32K clock periods will be filtered
*/
RGM_StatusType RGM_EnableResetFilter(RGM_FilterClkSrc eClk, uint8_t u8BusClockFilterWidth, bool bLpClkEn)
{
RGM_StatusType eRet = RGM_STATUS_SUCCESS;
if(eClk > RGM_RESET_FILTER_AON32K_CLOCK)
{
eRet = RGM_STATUS_PARAM_INVALID;
}
if (RGM_STATUS_SUCCESS == eRet)
{
if (RGM_RESET_FILTER_AON32K_CLOCK == eClk)
{
if ((RGM_HWA_ReadResetPinFilterEnable() & RGM_RSTFLT_RSTFLT_BUS_MASK) >> RGM_RSTFLT_RSTFLT_BUS_SHIFT == 1U)
{
RGM_HWA_DisableBusClockFilter();
}
RGM_HWA_EnableAon32kClockFilter();
}
if (RGM_RESET_FILTER_BUS_CLOCK == eClk)
{
if ((RGM_HWA_ReadResetPinFilterEnable() & RGM_RSTFLT_RSTFLT_AON_MASK) >> RGM_RSTFLT_RSTFLT_AON_SHIFT == 1U)
{
RGM_HWA_DisableAon32kClockFilter();
}
RGM_HWA_SetBusClockFilterWidth(u8BusClockFilterWidth);
RGM_HWA_EnableBusClockFilter();
}
if (bLpClkEn)
{
RGM_HWA_EnableAon32kLPClockFilter();
}
}
return eRet;
}
/**
* @brief Disable reset pin filter
*
* @param eClk Reset pin filter clock source
* @param bLpClkEn select whether disable reset pin filter using AON32clock in low power mode
* @return RGM return type
*/
RGM_StatusType RGM_DisableResetFilter(RGM_FilterClkSrc eClk, bool bLpClkEn)
{
RGM_StatusType eRet = RGM_STATUS_SUCCESS;
if (eClk > RGM_RESET_FILTER_AON32K_CLOCK)
{
eRet = RGM_STATUS_PARAM_INVALID;
}
if (RGM_STATUS_SUCCESS == eRet)
{
if (RGM_RESET_FILTER_AON32K_CLOCK == eClk)
{
RGM_HWA_DisableAon32kClockFilter();
}
if (bLpClkEn)
{
RGM_HWA_DisableAon32kLPClockFilter();
}
if (RGM_RESET_FILTER_BUS_CLOCK == eClk)
{
RGM_HWA_ClearBusClockFilterWidth();
RGM_HWA_DisableBusClockFilter();
}
}
return eRet;
}
/**
* @brief This api can enable interrupt before an system reset appear.
*
* @param eDelay Enumeration of delay cycles
* @param eResetInterrupt Reset event flag, like: RGM_INT_CLKERR0 | RGM_INT_FCSMU
* @return RGM return type
*
* @note Here is the interrupted master switch control
*/
RGM_StatusType RGM_EnableSystemResetInt(RGM_ResetDelayType eDelay, RGM_ResetIntMangerType eResetInterrupt)
{
RGM_StatusType eRet = RGM_STATUS_SUCCESS;
if (eDelay > RGM_512_CLOCK_CYCLES)
{
eRet = RGM_STATUS_PARAM_INVALID;
}
if (RGM_STATUS_SUCCESS == eRet)
{
RGM_HWA_EnableGlobalResetInterrupt();
RGM_HWA_SetResetDelay(eDelay);
RGM_HWA_EnableResetInterrupt(eResetInterrupt);
}
return eRet;
}
/**
* @brief This api can disable interrupt before an system reset appear.
*
* @param eResetInterrupt Reset event flag, like: RGM_INT_CLKERR0 | RGM_INT_FCSMU
* @param bClearDelay Whether to clear delay configuration
* @return RGM return type
*/
RGM_StatusType RGM_DisableSystemResetInt(RGM_ResetIntMangerType eResetInterrupt, bool bClearDelay)
{
RGM_StatusType eRet = RGM_STATUS_SUCCESS;
if (bClearDelay)
{
RGM_HWA_ClearResetDelay();
}
RGM_HWA_DisableResetInterrupt(eResetInterrupt);
return eRet;
}
/**
* @brief Generate software reset through cotex-m register
*
*/
void RGM_GenerateSwReset(void)
{
CM7_HWA_SystemReset();
}
/**
* @brief This api can enable interrupt before an CPU0 core related reset appear.
*
* @param eCPU0Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST
* @param pIsrNotify Interrupt function
* @return RGM return type
*/
RGM_StatusType RGM_EnableCPU0CoreResetInt(RGM_CPUIntMangerType eCPU0Interrupt,RGM_InterruptCallBackType pIsrNotify)
{
RGM_StatusType eRet = RGM_STATUS_SUCCESS;
if((uint8_t)eCPU0Interrupt > 0x1FU)
{
eRet = RGM_STATUS_PARAM_INVALID;
}
if (RGM_STATUS_SUCCESS == eRet)
{
RGM_HWA_EnableCPU0InterruptFlag(eCPU0Interrupt);
s_pRgmCPU0PreIntPtr = pIsrNotify;
}
return eRet;
}
/**
* @brief This api can disable interrupt before an CPU0 core related reset appear.
*
* @param eCPU0Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST
* @return RGM return type
*/
RGM_StatusType RGM_DisableCPU0CoreResetInt(RGM_CPUIntMangerType eCPU0Interrupt)
{
RGM_StatusType eRet = RGM_STATUS_SUCCESS;
if((uint8_t)eCPU0Interrupt > 0x1FU)
{
eRet = RGM_STATUS_PARAM_INVALID;
}
if (RGM_STATUS_SUCCESS == eRet)
{
RGM_HWA_DisableCPU0InterruptFlag(eCPU0Interrupt);
}
return eRet;
}
/**
* @brief Get the CPU0 exit reset flag
*
* @return RGM_CPU_OUT_RST_UNDER CPU0 is under reset
* @return RGM_CPU_OUT_RST_OUT CPU0 is out of reset
*/
RGM_CPUOutResetType RGM_GetCPU0OutResetFlag(void)
{
return RGM_HWA_GetCPU0OutResetFlag();
}
/**
* @brief Generate a CPU0 software reset.
*
*/
void RGM_GenerateCPU0SwReset(void)
{
RGM_HWA_CPU0SWReset();
}
/**
* @brief This api can get RGM_C0_SRS register that indicate the source of the most recent CPU0 reset.
*
* @return RGM->RGM_C0_SRS register, bit 0-20 corresponding to RGM_ResetEventType, refer to reference manual for details.
* @note Multiple flags can be set if multiple reset events occur at the same time
*/
uint32_t RGM_GetCPU0LastResetFLag(void)
{
return RGM_HWA_ReadCPU0LastResetFlag();
}
/**
* @brief This api can get RGM_C0_SSRS register that indicate all CPU0 reset sources since the last POR or LVD that have not been cleared by software.
*
* @returnRGM->RGM_C0_SSRS register, bit 0-20,29-31 corresponding to RGM_CPUResetEventType, refer to reference manual for details.
*/
uint32_t RGM_GetCPU0AllResetFlag(void)
{
return RGM_HWA_ReadCPU0AllResetFlagBeforePOR();
}
/**
* @brief This api can clear reset flag of RGM_C0_SSRS register which indicate CPU0 all reset sources since the last POR or LVD that have not been cleared by software.
*
* @param eReset Enumeration of reset event flag
*/
void RGM_ClearCPU0ResetFlagAfterPOR(const RGM_CPUResetEventType eReset)
{
RGM_HWA_ClearC0ResetFlagAfterPOR(eReset);
}
/**
* @brief This api can clear all reset flag of RGM_C0_SSRS register which indicate CPU0 all reset sources since the last POR or LVD that have not been cleared by software.
*
*/
void RGM_ClearCPU0AllResetFlagAfterPOR(void)
{
RGM_HWA_ClearC0AllResetFlagAfterPOR();
}
/**
* @brief RGM Pre-interrupt entry
*
*/
void RGM_Pre_IRQHandler(void)
{
IntMgr_DisableGlobalInterrupt();
if (NULL != s_pRgmCPU0PreIntPtr)
{
s_pRgmCPU0PreIntPtr(RGM_GetCPU0LastResetFLag());
}
IntMgr_EnableGlobalInterrupt();
}

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/**
* @file fc7xxx_driver_rtc.c
* @author Flagchip
* @brief FC7xxx rtc driver type definition and API
* @version 0.1.0
* @date 2024-01-10
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_rtc.h"
#include "fc7xxx_driver_csc.h"
/**
* @brief Rtc user defined alarm interrupt function
* */
static RTC_InterruptCallBackType s_pRTCAlarmNotifyPtr = NULL;
/**
* @brief Rtc user defined seconds interrupt function
* */
static RTC_InterruptCallBackType s_pRTCSecondNotifyPtr = NULL;
/**
* @brief Rtc user defined overflow interrupt function
* */
static RTC_InterruptCallBackType s_pRTCOverFlowNotifyPtr = NULL;
/**
* @brief RTC common interrupt function
* */
static void Rtc_CommonProcessInterrupt(const RTC_IntEventType eIntEvent);
/**
* @brief RTC interrupt entry
* */
void RTC_IRQHandler(void);
/**
* @brief Initialize Rtc instance
*
* @param pInitStruct Rtc initialization structure
* @return Rtc return type
* @note This function could only write once after POR.
*/
void RTC_Init(const RTC_InitType *const pInitStruct)
{
DEV_ASSERT(pInitStruct != NULL);
/* Disable interrupt */
RTC_HWA_DisableOverflowInterrupt();
/*Disable Second interrupt*/
RTC_HWA_DisableSecondInterrupt();
/*Disable Alarm interrupt*/
RTC_HWA_DisableAlarmInterrupt();
/* disable the rtc clock*/
RTC_HWA_DisableRtcCounter();
/* clear PR register */
RTC_HWA_SetPrescalerCounterValue(0U);
/* clear SR register */
RTC_HWA_SetSecondCounterValue(0U);
/* clear CR register */
RTC_HWA_ConfigControl(0U);
if (pInitStruct->bStableClkoutFreq)
{
RTC_HWA_SetClkoutFreqStable();
}
else
{
RTC_HWA_SetClkoutFromSelectFreq();
}
/* TSIC should only be altered when TSIE is clear */
RTC_HWA_SetSecondAndClkoutFreq(pInitStruct->eSecIntAndClkoutFreq);
/* Set alarm value */
RTC_HWA_SetAlarmCounterValue(pInitStruct->u32AlarmValue);
}
/**
* @brief Rtc set interrupt
*
* @param pIntStruct interrupt structure pointer
* @return Rtc return type
* @note this function will stop Rtc timer
*/
RTC_StatusType RTC_InitInterrupt(const RTC_InterruptType *const pIntStruct)
{
RTC_StatusType eRet = RTC_STATUS_SUCCESS;
if (NULL == pIntStruct)
{
eRet = RTC_STATUS_PARAM_INVALID;
}
else
{
/* disable the rtc timer */
RTC_HWA_DisableRtcCounter();
if (pIntStruct->bAlarmIntEn)
{
/* enable alarm interrupt */
RTC_HWA_EnableAlarmInterrupt();
s_pRTCAlarmNotifyPtr = pIntStruct->pIsrAlarmNotify;
}
else
{
/* disable alarm interrupt */
RTC_HWA_DisableAlarmInterrupt();
s_pRTCAlarmNotifyPtr = NULL;
}
if (pIntStruct->bOverflowIntEn)
{
/* enable overflow interrupt */
RTC_HWA_EnableOverflowInterrupt();
s_pRTCOverFlowNotifyPtr = pIntStruct->pIsrOverflowNotify;
}
else
{
/* disable overflow interrupt */
RTC_HWA_DisableOverflowInterrupt();
s_pRTCOverFlowNotifyPtr = NULL;
}
if (pIntStruct->bSecondIntEn)
{
/* enable second interrupt */
RTC_HWA_EnableSecondInterrupt();
s_pRTCSecondNotifyPtr = pIntStruct->pIsrSecondNotify;
}
else
{
/* disable second interrupt */
RTC_HWA_DisableSecondInterrupt();
s_pRTCSecondNotifyPtr = NULL;
}
}
return eRet;
}
/**
* @brief De-initialize Rtc instance
*
*/
void RTC_Deinit(void)
{
/* disable the rtc timer */
RTC_HWA_DisableRtcCounter();
/* clear PR register */
RTC_HWA_SetPrescalerCounterValue(0U);
/* clear SR register */
RTC_HWA_SetSecondCounterValue(0U);
/* clear TAR register */
RTC_HWA_SetAlarmCounterValue(0U);
/* clear IER register */
RTC_HWA_SetInterruptValue(0U);
/* clear CR register */
RTC_HWA_ConfigControl(0U);
s_pRTCAlarmNotifyPtr = NULL;
s_pRTCSecondNotifyPtr = NULL;
s_pRTCOverFlowNotifyPtr = NULL;
}
/**
* @brief Rtc enable interrupt
*
* @param bAlarmIntEn whether enable alarm interrupt
* @param bSecondIntEn whether enable second interrupt
* @param bOverflowIntEn whether enable overflow interrupt
*/
void RTC_EnableInterrupt(const bool bAlarmIntEn, const bool bSecondIntEn, const bool bOverflowIntEn)
{
/* disable the rtc timer */
RTC_HWA_DisableRtcCounter();
if (bAlarmIntEn)
{
/* enable alarm interrupt */
RTC_HWA_EnableAlarmInterrupt();
}
if (bSecondIntEn)
{
/* enable second interrupt */
RTC_HWA_EnableSecondInterrupt();
}
if (bOverflowIntEn)
{
/* enable overflow interrupt */
RTC_HWA_EnableOverflowInterrupt();
}
/*enable the rtc clock*/
RTC_HWA_EnableRtcCounter();
}
/**
* @brief Rtc disable interrupt
*
* @param bAlarmIntEn whether disable alarm interrupt
* @param bSecondIntEn whether disable second interrupt
* @param boverflowIntEn whether disable overflow interrupt
*/
void RTC_DisableInterrupt(const bool bAlarmIntEn, const bool bSecondIntEn, const bool boverflowIntEn)
{
/* disable the rtc timer */
RTC_HWA_DisableRtcCounter();
if (bAlarmIntEn)
{
/* disable alarm interrupt */
RTC_HWA_DisableAlarmInterrupt();
}
if (bSecondIntEn)
{
/* disable second interrupt */
RTC_HWA_DisableSecondInterrupt();
}
if (boverflowIntEn)
{
/* disable overflow interrupt */
RTC_HWA_DisableOverflowInterrupt();
}
/*enable the rtc clock*/
RTC_HWA_EnableRtcCounter();
}
/**
* @brief rtc start
*
*/
void RTC_Start(void)
{
/*enable the rtc clock*/
RTC_HWA_EnableRtcCounter();
}
/**
* @brief Rtc stop
*
*/
void RTC_Stop(void)
{
/*disable the rtc clock*/
RTC_HWA_DisableRtcCounter();
}
/**
* @brief Rtc alarm value
*
* @param u32AlarmValue Input value
*/
void RTC_UpdateAlarmValue(const uint32_t u32AlarmValue)
{
/*disable the rtc clock*/
RTC_HWA_DisableRtcCounter();
/* clear PR register */
RTC_HWA_SetPrescalerCounterValue(0U);
/* Set alarm value */
RTC_HWA_SetAlarmCounterValue(RTC_HWA_ReadSecondValue() + u32AlarmValue - (uint32_t)1U);
/*enable the rtc clock*/
RTC_HWA_EnableRtcCounter();
}
/**
* @brief Get Rtc counter value
*
* @return Rtc counter value
*/
uint32_t RTC_GetTime(void)
{
return RTC_HWA_ReadSecondValue();
}
/**
* @brief Check RTC overflow flag
*
* @return Overflow flag
*/
bool RTC_CheckOverflowFlag(void)
{
return RTC_HWA_GetOverflowFlag();
}
/**
* @brief Set second counter value
* @param u32Value the second value.
* */
void RTC_SetSecondCounterValue(uint32_t u32Value)
{
RTC_HWA_DisableRtcCounter();
RTC_HWA_SetSecondCounterValue(u32Value);
RTC_HWA_EnableRtcCounter();
}
/**
* @brief RTC common interrupt function
*
* @param eIntEvent RTC interrupt event
*/
static void Rtc_CommonProcessInterrupt(const RTC_IntEventType eIntEvent)
{
switch (eIntEvent)
{
case RTC_ALARM_INT:
if (NULL != s_pRTCAlarmNotifyPtr)
{
s_pRTCAlarmNotifyPtr();
}
break;
case RTC_SECOND_INT:
if (NULL != s_pRTCSecondNotifyPtr)
{
s_pRTCSecondNotifyPtr();
}
break;
case RTC_OVERFLOW_INT:
if (NULL != s_pRTCOverFlowNotifyPtr)
{
s_pRTCOverFlowNotifyPtr();
}
break;
default:
/* do nothing*/
break;
}
}
/**
* @brief RTC alarm interrupt handler entry
*
*/
void RTC_IRQHandler(void)
{
bool overflow_flag = RTC_HWA_GetOverflowFlag();
bool overflow_enablebit = RTC_HWA_GetOverflowEnable();
bool alarm_flag = RTC_HWA_GetAlarmFlag();
bool alarm_enablebit = RTC_HWA_GetAlarmEnable();
if ((overflow_flag) && (overflow_enablebit))
{
/*oveflow Int*/
/*disable the rtc clock*/
RTC_HWA_DisableRtcCounter();
RTC_HWA_SetSecondCounterValue(0u);
Rtc_CommonProcessInterrupt(RTC_OVERFLOW_INT);
}
else if ((alarm_flag) && (alarm_enablebit))
{
/*alarm Int*/
RTC_HWA_SetAlarmCounterValue(0u);
Rtc_CommonProcessInterrupt(RTC_ALARM_INT);
}
else
{
/*second Int*/
Rtc_CommonProcessInterrupt(RTC_SECOND_INT);
}
}

1941
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/**
* @file fc7xxx_driver_scm.h
* @author Flagchip
* @brief FC7xxx csc driver type definition and API
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_scm.h"
/**
* @brief Get unique identification for the chip, loaded from NVR.
*
* @param pUid Pointer to UID
*
*/
void SCM_GetChip_UID(uint32 *pUid)
{
DEV_ASSERT(NULL_PTR != pUid);
pUid[0] = SCM_HWA_GetData_UIDL();
pUid[1] = SCM_HWA_GetData_UIDML();
pUid[2] = SCM_HWA_GetData_UIDMH();
pUid[3] = SCM_HWA_GetData_UIDH();
}
/**
* @brief Get CCMx status.
*
* @param eCCMType CCM type
* @param u32Value selection to get
*
*/
uint32_t SCM_GetStatus_CCMx(SCM_CCM_Type eCCMType, uint32_t u32Value)
{
uint32_t u32Temp;
DEV_ASSERT(eCCMType == SCM_CCM0);
DEV_ASSERT((u32Value & SCM_CCM0_STATUS_MASK) == 0U);
if (SCM_CCM0 == eCCMType)
{
u32Temp = SCM_HWA_GetStatus_CCM0();
}
return (u32Temp & u32Value);
}
/**
* @brief Get matrix status.
*
* @param eMatrixType Matrix type
* @param u32Value selection to get
*
*/
uint32_t SCM_GetStatus_Matrix(SCM_MatrixStatusType eMatrixType, uint32_t u32Value)
{
uint32_t u32Temp;
DEV_ASSERT((uint32_t)eMatrixType <= (uint32_t)SCM_MatrixStatus_ID);
if (SCM_MatrixStatus_0 == eMatrixType)
{
u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS0();
}
else if (SCM_MatrixStatus_1 == eMatrixType)
{
u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS1();
}
else if (SCM_MatrixStatus_2 == eMatrixType)
{
u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS2();
}
else if (SCM_MatrixStatus_5 == eMatrixType)
{
u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS5();
}
else if (SCM_MatrixStatus_6 == eMatrixType)
{
u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS6();
}
else if (SCM_MatrixStatus_7 == eMatrixType)
{
u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS7();
}
else
{
u32Temp = SCM_HWA_GetStatus_MATRIX_ID_STATUS0();
}
return (u32Temp & u32Value);
}
/**
* @brief Set cpu to control MAM ECC enable register 0.
*
* @param eCpuType Cpu to use
* @param bLockStatus Lock the cpu control settings
*
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetCpuCtrl_MAMECCR0(const SCM_WPB_CpuType eCpuType, bool bLockStatus)
{
SCM_RetStatusType eRetVal;
DEV_ASSERT((uint32_t)eCpuType < (uint32_t)SCM_WP_CPU_NONE);
if (0U == SCM_HWA_MAMECCEN0_GetWPBLockStatus())
{
SCM_HWA_MAMECCEN0_SetCpuWritePermit(eCpuType);
if (true == bLockStatus)
{
/* Lock the cpu to control settings until reset */
SCM_HWA_MAMECCEN0_LockWritePermit();
}
eRetVal = SCM_E_OK;
}
else
{
eRetVal = SCM_E_LOCK;
}
return eRetVal;
}
/**
* @brief Set cpu to control MAM ECC enable register 1.
*
* @param eCpuType Cpu to use
* @param bLockStatus Lock the cpu control settings
*
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetCpuCtrl_MAMECCR1(const SCM_WPB_CpuType eCpuType, bool bLockStatus)
{
SCM_RetStatusType eRetVal;
DEV_ASSERT((uint32_t)eCpuType < (uint32_t)SCM_WP_CPU_NONE);
if (0U == SCM_HWA_MAMECCEN1_GetWPBLockStatus())
{
SCM_HWA_MAMECCEN1_SetCpuWritePermit(eCpuType);
if (true == bLockStatus)
{
/* Lock the cpu to control settings until reset */
SCM_HWA_MAMECCEN1_LockWritePermit();
}
eRetVal = SCM_E_OK;
}
else
{
eRetVal = SCM_E_LOCK;
}
return eRetVal;
}
/**
* @brief Set cpu to control CPU0 ECC enable register.
*
* @param eCpuType Cpu to use
* @param bLockStatus Lock the cpu control settings
*
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetCpuCtrl_CPU0ECCEN(const SCM_WPB_CpuType eCpuType, bool bLockStatus)
{
SCM_RetStatusType eRetVal;
DEV_ASSERT((uint32_t)eCpuType < (uint32_t)SCM_WP_CPU_NONE);
if (0U == SCM_HWA_CPU0ECCEN_GetWPBLockStatus())
{
SCM_HWA_CPU0ECCEN_SetCpuWritePermit(eCpuType);
if (true == bLockStatus)
{
/* Lock the cpu to control settings until reset */
SCM_HWA_CPU0ECCEN_LockWritePermit();
}
eRetVal = SCM_E_OK;
}
else
{
eRetVal = SCM_E_LOCK;
}
return eRetVal;
}
/**
* @brief Set cpu to control SOCMISC register.
*
* @param eCpuType Cpu to use
* @param bLockStatus Lock the cpu control settings
*
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetCpuCtrl_SOCMISC(const SCM_WPB_CpuType eCpuType, bool bLockStatus)
{
SCM_RetStatusType eRetVal;
if (0U == SCM_HWA_SOCMISC_GetWPBLockStatus())
{
SCM_HWA_SOCMISC_SetCpuWritePermit(eCpuType);
if (true == bLockStatus)
{
/* Lock the cpu to control settings until reset */
SCM_HWA_SOCMISC_LockWritePermit();
}
eRetVal = SCM_E_OK;
}
else
{
eRetVal = SCM_E_LOCK;
}
return eRetVal;
}
/**
* @brief Set cpu to control Subsystem pcc register.
*
* @param eCpuType Cpu to use
* @param bLockStatus Lock the cpu control settings
*
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetCpuCtrl_SUBSYS_PCC(const SCM_WPB_CpuType eCpuType, bool bLockStatus)
{
SCM_RetStatusType eRetVal;
if (0U == SCM_HWA_SUBSYS_PCC_GetWPBLockStatus())
{
SCM_HWA_SUBSYS_PCC_SetCpuWritePermit(eCpuType);
if (true == bLockStatus)
{
/* Lock the cpu to control settings until reset */
SCM_HWA_SUBSYS_PCC_LockWritePermit();
}
eRetVal = SCM_E_OK;
}
else
{
eRetVal = SCM_E_LOCK;
}
return eRetVal;
}
/**
* @brief Set cpu to control master halt request register.
*
* @param eCpuType Cpu to use
* @param bLockStatus Lock the cpu control settings
*
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetCpuCtrl_MASTER_HALT_REQ(const SCM_WPB_CpuType eCpuType, bool bLockStatus)
{
SCM_RetStatusType eRetVal;
if (0U == SCM_HWA_MASTER_HALT_REQ_GetWPBLockStatus())
{
SCM_HWA_MASTER_HALT_REQ_SetCpuWritePermit(eCpuType);
if (true == bLockStatus)
{
/* Lock the cpu to control settings until reset */
SCM_HWA_MASTER_HALT_REQ_LockWritePermit();
}
eRetVal = SCM_E_OK;
}
else
{
eRetVal = SCM_E_LOCK;
}
return eRetVal;
}
/**
* @brief Set lock FTU_ROUTING register.
*
*/
void SCM_SetLock_FTU_ROUTING(void)
{
if (0U == SCM_HWA_FTU_ROUTING_GetLockStatus())
{
SCM_HWA_LockFTU_ROUTING();
}
}
/**
* @brief Set lock FTU_GTB register.
*
*/
void SCM_SetLock_FTU_GTB(void)
{
if (0U == SCM_HWA_FTU_GTB_GetLockStatus())
{
SCM_HWA_LockFTU_GTB();
}
}
/**
* @brief Set lock DEBUG_TRACE register.
*
*/
void SCM_SetLock_DEBUG_TRACE(void)
{
if (0U == SCM_HWA_DEBUG_TRACE_GetLockStatus())
{
SCM_HWA_LockDEBUG_TRACE();
}
}
/**
* @brief Set lock FLEXCAN_ROUTING register.
*
*/
void SCM_SetLock_FLEXCAN_ROUTING(void)
{
if (0U == SCM_HWA_FLEXCAN_ROUTING_GetLockStatus())
{
SCM_HWA_LockFLEXCAN_ROUTING();
}
}
/**
* @brief Set lock MSC0_ROUTING register.
*
*/
void SCM_SetLock_MSC0_ROUTING(void)
{
if (0U == SCM_HWA_MSC0_ROUTING_GetLockStatus())
{
SCM_HWA_LockMSC0_ROUTING();
}
}
/**
* @brief Set lock INT_ROUTER_NMI register.
*
*/
void SCM_SetLock_INT_ROUTER_NMI(void)
{
if (0U == SCM_HWA_INT_ROUTER_NMI_GetLockStatus())
{
SCM_HWA_LockINT_ROUTER_NMI();
}
}
/**
* @brief Set NMI interrupt router .
*
* @param eCpuType Cpu to use
* @param bEnable Enable/Disable
* @return Set operation success/failed
*/
SCM_RetStatusType SCM_SetEnable_NMIIntRouter(const SCM_WPB_CpuType eCpuType, bool bEnable)
{
SCM_RetStatusType eRetVal;
if (SCM_WP_CPU_0 == eCpuType)
{
SCM_HWA_SetEnable_Cpu0NMIIrqRouter(bEnable);
eRetVal = SCM_E_OK;
}
else
{
eRetVal = SCM_E_PARAM;
}
return eRetVal;
}
/**
* @brief Generate the origion SCM register CRC result, and configure the SCM register CRC option.
*
* @param eMode The SCM register CRC trigger mode
* @return CRC configure status
* SCM_E_OK : CRC configure successfully
* SCM_E_TIMEOUT : CRC configure time out
*/
SCM_RetStatusType SCM_RegCrcConfig(SCM_CrcModeType eMode)
{
SCM_RetStatusType eStatusVal = SCM_E_OK;
uint32_t u32Timeout = 0xFFFFU;
DEV_ASSERT((eMode == SCM_CRC_SW_MODE) || (eMode == SCM_CRC_TRIGGER_MODE));
/* Deinit CRC register */
SCM_HWA_SetEnable_CrcCheck(false);
SCM_HWA_SetEnable_CrcTrigger(false);
SCM_HWA_SetEnable_CrcErrOut(false);
SCM_HWA_ClearCrcErrorFlag();
/* Generate original CRC result */
SCM_HWA_SetEnable_CrcSwGen(true);
while (SCM_HWA_GetStatus_CrcBusyFlag() != 0U)
{
u32Timeout--;
if (u32Timeout == 0U)
{
eStatusVal = SCM_E_TIMEOUT;
break;
}
}
if (eStatusVal == SCM_E_OK)
{
if (eMode == SCM_CRC_TRIGGER_MODE)
{
SCM_HWA_SetEnable_CrcTrigger(true);
}
/* Enable SCM CRC error to FCSMU in CSC0_SMU_CTRL4[SCM_CRC] */
CSC0_HWA_CTRL4_EnableReqToSMU(CSC_SMU_SCM_CRC);
/* Generate CRC error output */
SCM_HWA_SetEnable_CrcErrOut(true);
/* Generate CRC check */
SCM_HWA_SetEnable_CrcCheck(true);
}
return eStatusVal;
}
/**
* @brief Trigger the SCM register CRC generation by software
*
*/
void SCM_RegCrcGenerate(void)
{
SCM_HWA_SetEnable_CrcSwGen(true);
}
/**
* @brief Trigger the SCM register CRC generation by software,and wait the CRC check result
*
* @return CRC check result
*/
SCM_RetStatusType SCM_RegCrcGenerateWaitResult(void)
{
SCM_RetStatusType eStatusVal = SCM_E_OK;
uint32_t u32Timeout = 0xFFFFU;
SCM_HWA_SetEnable_CrcSwGen(true);
while (SCM_HWA_GetStatus_CrcBusyFlag() != 0U)
{
u32Timeout--;
if (u32Timeout == 0U)
{
eStatusVal = SCM_E_TIMEOUT;
break;
}
}
/* Check CRC is success or not */
if (0U != SCM_HWA_GetStatus_CrcErrFlag())
{
eStatusVal = SCM_E_CRC;
}
return eStatusVal;
}

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/**
* @file fc7xxx_driver_scst.c
* @author Flagchip
* @brief FC7xxx scst driver source code
* @version 0.1.0
* @date 2023-12-29
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
*/
/*********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-29 qxw074 N/A First version for FC7240
******************************************************************************** */
#include "fc7xxx_driver_scst.h"
/**
* @brief The address of the specific implementation of the M7ST API
*
*/
#define M7ST_ROM_BASE 0x04812800
/**
* @brief The SCST Atomic Test function prototype
*
*/
typedef Type_M7ST_AtomicStatus (*Type_M7ST_RegressionTest) (uint32_t TestStart, uint32_t TestEnd, uint32_t InjectEnable, uint32_t RamBase);
/**
* @brief The SCST Run selected tests function prototype
*
*/
typedef Type_M7ST_AtomicStatus (*Type_M7ST_AtomicTest) (uint32_t TestID, uint32_t InjectEnable, uint32_t RamBase);
/**
* @brief M7ST API structure
*
*/
typedef struct Struct_M7ST_RomTable
{
Type_M7ST_RegressionTest RegressionTest;
Type_M7ST_AtomicTest AluTest;
Type_M7ST_AtomicTest AluMLATest;
Type_M7ST_AtomicTest AluSHIFTTest;
Type_M7ST_AtomicTest AluTest1;
Type_M7ST_AtomicTest AluTest2;
Type_M7ST_AtomicTest AluTest3;
Type_M7ST_AtomicTest AluTest4;
Type_M7ST_AtomicTest AluTest5;
Type_M7ST_AtomicTest AluTest6;
Type_M7ST_AtomicTest RegbankTest1;
Type_M7ST_AtomicTest RegbankTest2;
Type_M7ST_AtomicTest RegbankTest3;
Type_M7ST_AtomicTest RegbankTest4;
Type_M7ST_AtomicTest RegbankTest5;
Type_M7ST_AtomicTest RegbankTest6;
Type_M7ST_AtomicTest LoadStoreTest1;
Type_M7ST_AtomicTest LoadStoreTest2;
Type_M7ST_AtomicTest LoadStoreTest3;
Type_M7ST_AtomicTest LoadStoreTest4;
Type_M7ST_AtomicTest LoadStoreTest5;
Type_M7ST_AtomicTest LoadStoreTest6;
Type_M7ST_AtomicTest SimdSatTest1;
Type_M7ST_AtomicTest SimdSatTest2;
Type_M7ST_AtomicTest SimdSatTest3;
Type_M7ST_AtomicTest SimdSatTest4;
Type_M7ST_AtomicTest MacTest1;
Type_M7ST_AtomicTest MacTest2;
Type_M7ST_AtomicTest FetchTest;
Type_M7ST_AtomicTest StatusTest1;
Type_M7ST_AtomicTest StatusTest2;
Type_M7ST_AtomicTest BranchTest1;
Type_M7ST_AtomicTest BranchTest2;
} Type_M7ST_RomTable;
/**
* @brief This function is used to get the result of the executed test
*
* @param test_index is test number,0U..32U
* @param s_u32RamBase The first address of the 1k memory that the program needs to run
* @return M7ST_ErrorM7ST_TestPass is ok, others are not ok
*/
Type_M7ST_AtomicStatus SCST_ExecuteTest(SCST_TestIndexType test_index,uint32_t *s_u32RamBase)
{
Type_M7ST_AtomicStatus Status = M7ST_FaultInjectError;
Type_M7ST_RomTable *M7ST_RomEntry = (Type_M7ST_RomTable *)M7ST_ROM_BASE;
switch(test_index)
{
case M7ST_AluTest:
Status = M7ST_RomEntry->AluTest(0,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_AluMLATest:
Status = M7ST_RomEntry->AluMLATest(1,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_AluSHIFTTest:
Status = M7ST_RomEntry->AluSHIFTTest(2,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_AluTes1t:
Status = M7ST_RomEntry->AluTest1(3,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_AluTest2:
Status = M7ST_RomEntry->AluTest2(4,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_AluTest3:
Status = M7ST_RomEntry->AluTest3(5,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_AluTest4:
Status = M7ST_RomEntry->AluTest4(6,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_AluTest5:
Status = M7ST_RomEntry->AluTest5(7,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_AluTest6:
Status = M7ST_RomEntry->AluTest6(8,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_RegbankTest1:
Status = M7ST_RomEntry->RegbankTest1(9,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_RegbankTest2:
Status = M7ST_RomEntry->RegbankTest2(10,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_RegbankTest3:
Status = M7ST_RomEntry->RegbankTest3(11,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_RegbankTest4:
Status = M7ST_RomEntry->RegbankTest4(12,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_RegbankTest5:
Status = M7ST_RomEntry->RegbankTest5(13,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_RegbankTest6:
Status = M7ST_RomEntry->RegbankTest6(14,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_LoadStoreTest1:
Status = M7ST_RomEntry->LoadStoreTest1(15,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_LoadStoreTest2:
Status = M7ST_RomEntry->LoadStoreTest2(16,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_LoadStoreTest3:
Status = M7ST_RomEntry->LoadStoreTest3(17,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_LoadStoreTest4:
Status = M7ST_RomEntry->LoadStoreTest4(18,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_LoadStoreTest5:
Status = M7ST_RomEntry->LoadStoreTest5(19,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_LoadStoreTest6:
Status = M7ST_RomEntry->LoadStoreTest6(20,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_SimdSatTest1:
Status = M7ST_RomEntry->SimdSatTest1(21,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_SimdSatTest2:
Status = M7ST_RomEntry->SimdSatTest2(22,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_SimdSatTest3:
Status = M7ST_RomEntry->SimdSatTest3(23,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_SimdSatTest4:
Status = M7ST_RomEntry->SimdSatTest4(24,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_MacTest1:
Status = M7ST_RomEntry->MacTest1(25,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_MacTest2:
Status = M7ST_RomEntry->MacTest2(26,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_FetchTest:
Status = M7ST_RomEntry->FetchTest(27,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_StatusTest1:
Status = M7ST_RomEntry->StatusTest1(28,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_StatusTest2:
Status = M7ST_RomEntry->StatusTest2(29,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_BranchTest1:
Status = M7ST_RomEntry->BranchTest1(30,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_BranchTest2:
Status = M7ST_RomEntry->BranchTest2(31,0,(uint32_t)&s_u32RamBase[0]);
break;
case M7ST_RegressionTest:
Status = M7ST_RomEntry->RegressionTest(0,31,0,(uint32_t)&s_u32RamBase[0]);
break;
default:
break;
}
return Status;
}

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/**
* @file fc7xxx_driver_sec.c
* @author FlagchipXXX
* @brief FC7xxx SEC driver type definition and API
* @version 0.1.0
* @date 2024-1-12
*
* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2024-1-12 Flagchip113 N/A First version for FC7240
********************************************************************************/
#include "fc7xxx_driver_sec.h"
/**
* @brief This function can be used to enable the Debug mode.
* @return true means enable debug success ,false means enable debug failed.
* */
bool SEC_EnDebugMode(void)
{
bool ret = false;
if (SEC_HWA_GetWritePer())
{
SEC_HWA_EnDebug();
ret = true;
}
return ret;
}
/**
* @brief This function can be used to re-enable the Debug mode by the re-enable keys.
* @param keys The Debug mode re-enable keys.
* @return true means re-enable success,false means re-enable failed.
* */
bool SEC_ReEnDebugMode(ReEnDebug_Keys keys)
{
bool ret = false;
if (SEC_HWA_GetReEnDebug())
{
SEC_HWA_ChangeDBK(0u, keys.Re_key0);
SEC_HWA_ChangeDBK(1u, keys.Re_key1);
SEC_HWA_ChangeDBK(2u, keys.Re_key2);
SEC_HWA_ChangeDBK(3u, keys.Re_key3);
ret = true;
}
return ret;
}
/**
* @brief This function can get the system state (secured or no secured).
* */
Systemstate SEC_SystemSecureState(void)
{
Systemstate ret = Securedstate ;
uint16_t sskey0 = SEC_HWA_GetSScontrol0();
uint16_t sskey1 = SEC_HWA_GetSScontrol1();
if ((sskey0 == 0xC35AU) && (sskey1 == 0xFFFFU))
{
ret = UnSecuredstate;
}
return ret ;
}
/**
* @brief This function can enable the test mode.
* @return true means enable test mode success,false means enable test mode failed.
* */
bool SEC_EnTestMode(void)
{
bool ret = false;
if (SEC_HWA_GetWritePer())
{
SEC_HWA_EnTest();
ret = true;
}
return ret;
}
/**
*@brief This function can Re-enable the test mode by the re-enable key.
*@param key The test mode re-enable key.The key is up to the user to decide in advance.
*@return true means re-enable success,false means re-enable failed.
* */
bool SEC_ReEnTestMode(uint32_t key)
{
bool ret = false;
bool writeper = SEC_HWA_GetWritePer();
bool reentest = SEC_HWA_GetReEnTest();
if ((true == writeper) && (true == reentest))
{
SEC_HWA_ReEnTestKey(key);
ret = true;
}
return ret;
}
/**
* @brief This function can used to set the NVR write and read permission.
* @return true means setPer success,false means setPer failed.
* */
bool SEC_SetNvrPer(NVR_Per per)
{
bool ret = false;
if (SEC_HWA_GetWritePer())
{
if (per.ReadEn == true)
{
SEC_HWA_EnReadB0NVR();
}
else
{
SEC_HWA_DisReadB0NVR();
}
if (per.WritEn == true)
{
SEC_HWA_EnWriteB0NVR();
}
else
{
SEC_HWA_DisWriteB0NVR();
}
if (per.EraseEn == true)
{
SEC_HWA_EnEraseB0NVR();
}
else
{
SEC_HWA_DisEraseB0NVR();
}
ret = true;
}
return ret;
}
/**
* @brief Get Secure Boot Enable Status
*
* @return true is enable and false is disable
*/
bool SEC_GetSecureStatus(void)
{
return SEC_HWA_GetSB();
}
/**
* @brief Get ISP Status
*
* @return true is active and false is inactive
*/
bool SEC_GetISPModeStatus(void)
{
return SEC_HWA_GetIspStatus();
}
/**
* @brief Get User setting bootloader address
*
* @return bootloader address
*/
uint32_t SEC_GetBootAddress(void)
{
return SEC_HWA_GetBLAddr();
}
///**
// * @brief Get the HSM Firmware Address
// *
// * @return the HSM Firmware address
// */
//uint32_t SEC_GetHsmFwAddress(void)
//{
// return SEC_HWA_GetHsmAddr();
//}
/**
* @brief Get the lifecycle.
*
* @return the lifecycle.
*/
SC_LifeCycle SEC_GetLifeCycle(void)
{
SC_LifeCycle lifecycle = LIFECYCLE_INVALID;
uint8_t lifecycle_status;
lifecycle_status = SEC_HWA_GetLCStaus();
switch (lifecycle_status)
{
case 1u:
lifecycle = LIFECYCLE_OEM_DEV;
break;
case 2u:
lifecycle = LIFECYCLE_OEM_PDT;
break;
case 4u:
lifecycle = LIFECYCLE_INFIELD;
break;
case 8u:
lifecycle = LIFECYCLE_PREFA;
break;
case 16u:
lifecycle = LIFECYCLE_FA;
break;
default:
break;
}
return lifecycle;
}
/**
* @brief User Key Access Enable. Only valid under non-secure boot
* @return true means User key can be read/programmed/erased by host CPU
* */
bool SEC_HostUKAccess(void)
{
return SEC_HWA_GetUKAS();
}
/**
* @brief get the Bootloader Verification Algorithm
* @return the Bootloader Verification Algorithm
* */
BL_VerifyAlgorithm SEC_GetBLVerifyAlgorithm(void)
{
return (BL_VerifyAlgorithm)(uint8_t)(SEC_HWA_GetBLVer());
}
/**
* @brief get the Debug/ISP/PREFA Authentication and USRK decryption algorithm
* @return decryption algorithm
* */
Decryption_Algorithm SEC_GetDecryptAlgorithm(void)
{
return (Decryption_Algorithm)(uint8_t)(SEC_HWA_GetDecrypt());
}
/**
* @brief Indicate the Host User Key Read/Write/Erase Protection
* @param PHostUKAccess the structure for information
*
* */
void SEC_GetHostUKAccess(HostUKPermission *const PHostUKAccess)
{
PHostUKAccess->HostUKEraseEn = SEC_HWA_GetHUKErase();
PHostUKAccess->HostUKReadEn = SEC_HWA_GetHUKRead();
PHostUKAccess->HostUKWriteEn = SEC_HWA_GetHUKWrite();
}
/**
* @brief Indicate the Host NVR Read/Write/Erase Protection
*@param PHostNvrAccess the structure to initialize
* */
void SEC_GetHostNVRAccess(HostNVRPermission *const PHostNVRAccess)
{
PHostNVRAccess->HostNVREraseEn = SEC_HWA_GetHostNvrErase();
PHostNVRAccess->HostNVRReadEn = SEC_HWA_GetHostNvrRead();
PHostNVRAccess->HostNVRWriteEn = SEC_HWA_GetHostNvrWrite();
}
/**
* @brief Get the HSM User Key Erase Protection
* @return true - HSM erase access to User Key region is enabled
* false -HSM erase access to User Key region is disabled
* */
bool SEC_GethsmUKEraseAccess(void)
{
return SEC_HWA_GetHsmUKErase();
}
/**
* @brief Get the HSM NVR Erase Protection
* @return true - HSM erase access to NVR region is enabled
* false -HSM erase access to NVR region is disabled
* */
bool SEC_GethsmNVREraseAccess(void)
{
return SEC_HWA_GetHsmNvrErase();
}
/**
* @brief Get Bootloader Verification Mask
* @return Bootloader Verification Mask.
* */
uint32_t SEC_GetBLVerMask(void)
{
return SEC_HWA_GetBLMask();
}
/**
* @brief Get whether Debug Backdoor Key Input Enable.
* @return
* 0011b - User can input DBK through debug mailbox, ISP is not valid.
* 1100b - User can input DBK through ISP, debug mailbox is not valid.
* 1111b - User can input DBK through both debug mailbox and ISP.
* Other Values - User cannot input DBK through both debug mailbox andISP.
* */
uint32_t SEC_GetDMBDkeyEn(void)
{
return SEC_HWA_GetMBBKEN();
}
/**
* @brief Host Debug Auth Enable. Only valid in secure boot. (Value loaded from NVR sector)
* @return true means Host debug authentication enable. false means Host debug authentication disable.
*/
bool SEC_GetDebugAuthEn(void)
{
return SEC_HWA_GetDEAUEn();
}
/**
* @brief Get the isp information.
* @param pIspInfo the structure to information
* @return Get whether operation is success.
*
* */
SEC_RetType SEC_GetIspInfo(SEC_IspInfo *const pIspInfo)
{
SEC_RetType eRet ;
if (NULL == pIspInfo)
{
eRet = SEC_STATUS_FAILED;
}
else
{
bool ispen = SEC_HWA_GetIspStatus();
if (!ispen)
{
eRet = SEC_STATUS_FAILED;
}
else
{
pIspInfo->IspModeEn = SEC_HWA_GetIspStatus();
pIspInfo->IspPinEn = SEC_HWA_GetIspEn();
pIspInfo->IspAuthEn = SEC_HWA_GetISPAU();
Isp_Instance ispins = (Isp_Instance)(uint8_t)(SEC_HWA_GetIspIns());
if ((ispins == ISP_FCUART1) || (ispins == ISP_FCUART3))
{
pIspInfo->Ispfcuartbaudrate = (FCUART_ISP_BAUDRATE)(uint8_t)(SEC_HWA_GetUartBR());
pIspInfo->Ispflexcanbaudrate = ISP_FLEXCAN_INVALID;
}
else if ((ispins == ISP_FLEXCAN1) || (ispins == ISP_FLEXCAN5))
{
pIspInfo->Ispfcuartbaudrate = ISP_FCUART_INVALID;
pIspInfo->Ispflexcanbaudrate = (FLEXCAN_ISP_BAUDRATE)(uint8_t)(SEC_HWA_GetCanBR());
}
else
{
/*do nothing*/
}
eRet = SEC_STATUS_SUCCESS;
}
}
return eRet;
}
/**
* @brief Get the boot information.
* @param pBootInfo the structure for information
* @return Get whether operation is success.
*
* */
SEC_RetType SEC_GetBootInfo(SEC_BootInfo *const pBootInfo)
{
SEC_RetType eRet ;
if (NULL == pBootInfo)
{
eRet = SEC_STATUS_FAILED;
}
else
{
pBootInfo->BootRom = SEC_HWA_GetBootRom();
pBootInfo->NmiPinEn = SEC_HWA_GetNmiPin();
pBootInfo->SecBootEn = SEC_HWA_GetSB();
pBootInfo->OscEn = SEC_HWA_GetOSCAvail();
pBootInfo->OscFreq = (Osc_FreqInfo)(uint8_t)(SEC_HWA_GetOSCFre());
pBootInfo->FastBootSpeed = (FastBoot_Speed)(uint8_t)(SEC_HWA_GetFastBootClock());
eRet = SEC_STATUS_SUCCESS;
}
return eRet;
}

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@ -0,0 +1,896 @@
/**
* @file fc7xxx_driver_sent.c
* @author Flagchip
* @brief FC7xxx SENT driver source code
* @version 0.2.0
* @date 2022-12-30
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Author CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2022-12-14 Flagchip N/A First version for FC7300 SENT
* 0.2.0 2022-12-30 Flagchip N/A Support SPC mode for SENT
******************************************************************************** */
#include "fc7xxx_driver_sent.h"
#include "interrupt_manager.h"
#include "HwA_sent.h"
#define SENT_GLBL_CTL_PRESCALER_MAX 255U
#define SENT_GLBL_CTL_WATERMARK_MAX 16U
static SENT_Type* const aSent_Base[] = SENT_BASE_PTRS;
static bool aSentInit[SENT_INSTANCE_COUNT] = {0u};
static SENT_GBISRCallbackType aGBISRCallback[SENT_INSTANCE_MAX] = {NULL};
static SENT_CHISRCallbackType aCHISRCallback[SENT_INSTANCE_MAX] = {NULL};
void SENT0_IRQHandler(void);
void SENT1_IRQHandler(void);
static void SENT_IRQ_Handler(const Sent_InstanceType eInstance)
{
uint8_t u8Channel;
uint32_t u32ChannelStatus;
SENT_Type *pSent = aSent_Base[eInstance];
for(u8Channel = 0U; u8Channel < SENT_CHANNEL_COUNT; u8Channel++)
{
if(true == SENT_HWA_GetChannelReceive(pSent, u8Channel))
{
if(true == SENT_HWA_GetSLowMessageUnderflowFlag(pSent, u8Channel))
{
if(NULL != aGBISRCallback[eInstance])
{
SENT_HWA_ClearSLowMessageUnderflowFlag(pSent, u8Channel);
aGBISRCallback[eInstance]((Sent_ChannelType)u8Channel, SENT_SLOW_MSG_DMA_UF_IT);
}
}
if(true == SENT_HWA_GetFastMessageReadyFlag(pSent, u8Channel))
{
if(NULL != aGBISRCallback[eInstance])
{
SENT_HWA_ClearFastMessageReadyFlag(pSent, u8Channel);
aGBISRCallback[eInstance]((Sent_ChannelType)u8Channel, SENT_FAST_MSG_READY_IT);
}
}
if(true == SENT_HWA_GetSlowMessageReadyFlag(pSent, u8Channel))
{
if(NULL != aGBISRCallback[eInstance])
{
SENT_HWA_ClearSlowMessageReadyFlag(pSent, u8Channel);
aGBISRCallback[eInstance]((Sent_ChannelType)u8Channel, SENT_SLOW_MSG_READY_IT);
}
}
if(true == SENT_HWA_GetFastMessageFIFOOverflowFlag(pSent, u8Channel))
{
if(NULL != aGBISRCallback[eInstance])
{
SENT_HWA_ClearFastMessageFIFOOverflowFlag(pSent, u8Channel);
aGBISRCallback[eInstance]((Sent_ChannelType)u8Channel, SENT_FAST_MSG_FIFO_OF_IT);
}
}
if(true == SENT_HWA_GetFastMessageDMAUnderflowFlag(pSent, u8Channel))
{
if(NULL != aGBISRCallback[eInstance])
{
SENT_HWA_ClearFastMessageDMAUnderflowFlag(pSent, u8Channel);
aGBISRCallback[eInstance]((Sent_ChannelType)u8Channel, SENT_FAST_MSG_DMA_DF_IT);
}
}
u32ChannelStatus = SENT_HWA_GetChannelStatus(pSent, u8Channel);
if(0U != u32ChannelStatus)
{
if(NULL != aCHISRCallback[eInstance])
{
SENT_HWA_ClearChannelStatus(pSent, u8Channel, u32ChannelStatus);
aCHISRCallback[eInstance]((Sent_ChannelType)u8Channel, u32ChannelStatus);
}
}
}
}
}
Sent_ReturnType SENT_Init(const Sent_InstanceType eInstance, const Sent_ConfigType *pCfg)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(false == aSentInit[eInstance])
{
if((NULL != pCfg) && (eInstance < SENT_INSTANCE_MAX) && \
(pCfg->u8DmaWaterMark <= SENT_GLBL_CTL_WATERMARK_MAX) && \
(pCfg->u8PreScaler < SENT_GLBL_CTL_PRESCALER_MAX))
{
pSent = aSent_Base[eInstance];
SENT_HWA_SetGlobalPreScaler(pSent, pCfg->u8PreScaler);
SENT_HWA_SetDMAWaterMark(pSent, pCfg->u8DmaWaterMark);
if(true == pCfg->bDebugModeEn)
{
SENT_HWA_EnableDebugMode(pSent);
}
else
{
SENT_HWA_DisableDebugMode(pSent);
}
if(true == pCfg->bAutoClearReadyFlag)
{
SENT_HWA_EnableDataOverflowFlagFastClear(pSent);
}
else
{
SENT_HWA_DisableDataOverflowFlagFastClear(pSent);
}
aGBISRCallback[eInstance] = pCfg->pGBCallback;
aCHISRCallback[eInstance] = pCfg->pCHCallback;
SENT_HWA_EnableGlobal(pSent);
aSentInit[eInstance] = true;
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_ALREADY_INIT;
}
return eRet;
}
Sent_ReturnType SENT_SetChannelConfig(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, const Sent_ChannelConfigType *pCfg)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((NULL != pCfg) && (eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
if(true == pCfg->bChannelEn)
{
if((pCfg->u8DataNibbleNumber > 0U) && (pCfg->u8DataNibbleNumber < 6U))
{
SENT_HWA_DisableChannelReceive(pSent, (uint8_t)eChannel);
SENT_HWA_SetChannelIdleCount(pSent, (uint8_t)eChannel, (uint8_t)pCfg->eIdleCount);
SENT_HWA_SetChannelDigitalFilterCount(pSent, (uint8_t)eChannel, pCfg->u8DigitalFilterCount);
SENT_HWA_SetChannelNibbleNumber(pSent, (uint8_t)eChannel, pCfg->u8DataNibbleNumber);
SENT_HWA_SetChannelPreScaler(pSent, (uint8_t)eChannel, (uint16_t)pCfg->u16TickScaler);
SENT_HWA_SetChannelNibbleDataMode(pSent, (uint8_t)eChannel, (SENT_NibbleDataModeType)(pCfg->eDataNibbleMode));
if(SENT_CALIBRATION_PULSE_DIAG_OPTION1 != pCfg->eCalDiagOption)
{
SENT_HWA_DisableChannelSPCOption1(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_EnableChannelSPCOption1(pSent, (uint8_t)eChannel);
}
if(true == pCfg->bPausePulseEn)
{
SENT_HWA_EnableChannelPausePulse(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelPausePulse(pSent, (uint8_t)eChannel);
}
if(true == pCfg->bTickCompensateEn)
{
SENT_HWA_EnableChannelCompensate(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelCompensate(pSent, (uint8_t)eChannel);
}
if(true == pCfg->bFastMessageFifoEn)
{
SENT_HWA_EnableChannelFIFO(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelFIFO(pSent, (uint8_t)eChannel);
}
if(true == pCfg->bFastMsgCRCAugEn)
{
SENT_HWA_EnableChannelFastMessageAugmentation(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelFastMessageAugmentation(pSent, (uint8_t)eChannel);
}
if(true == pCfg->bFastMsgCRCCheckEn)
{
SENT_HWA_EnableChannelFastMessageCRCCheck(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelFastMessageCRCCheck(pSent, (uint8_t)eChannel);
}
if(true == pCfg->bFastMsgCRCWithSCEn)
{
SENT_HWA_EnableChannelFastMessageCRCWithSC(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelFastMessageCRCWithSC(pSent, (uint8_t)eChannel);
}
if(true == pCfg->bFastMsgDataChangeEn)
{
SENT_HWA_EnableChannelFastMessageDataChange(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelFastMessageDataChange(pSent, (uint8_t)eChannel);
}
if(true == pCfg->bSlowMsgCRCAugEn)
{
SENT_HWA_EnableChannelSlowMessageAugmentation(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelSlowMessageAugmentation(pSent, (uint8_t)eChannel);
}
if(true == pCfg->bUseAlternativeCrc)
{
SENT_HWA_EnableChannelAltCRC(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelAltCRC(pSent, (uint8_t)eChannel);
}
if(SENT_CALIBRATION_VALID_WITHIN_20 == pCfg->eCalValid)
{
SENT_HWA_DisableChannelCalValid20To25(pSent, (uint8_t)eChannel);
SENT_HWA_EnableChannelCalValidDiagnostic(pSent, (uint8_t)eChannel);
}
else if(SENT_CALIBRATION_VALID_FROM_20_TO_25 == pCfg->eCalValid)
{
SENT_HWA_EnableChannelCalValid20To25(pSent, (uint8_t)eChannel);
SENT_HWA_EnableChannelCalValidDiagnostic(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelCalValid20To25(pSent, (uint8_t)eChannel);
SENT_HWA_DisableChannelCalValidDiagnostic(pSent, (uint8_t)eChannel);
}
SENT_HWA_EnableChannelReceive(pSent, (uint8_t)eChannel);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
SENT_HWA_DisableChannelReceive(pSent, (uint8_t)eChannel);
}
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_SetDMAConfig(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, Sent_DMAConfigType *pCfg)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((NULL != pCfg) && (eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
if(true == pCfg->bFastMsgDmaEn)
{
SENT_HWA_EnableChannelFastMessageDmaRequest(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelFastMessageDmaRequest(pSent, (uint8_t)eChannel);
}
if(true == pCfg->bSlowMsgDmaEn)
{
SENT_HWA_EnableChannelSlowMessageDmaRequest(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelSlowMessageDmaRequest(pSent, (uint8_t)eChannel);
}
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_SetSPCConfig(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, const Sent_SpcConfigType *pCfg)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((NULL != pCfg) && (eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
SENT_HWA_DisableChannelSPCMode(pSent, (uint8_t)eChannel);
SENT_HWA_SetChannelSPCTickBase(pSent, (uint8_t)eChannel, (SENT_SPCTickType)(pCfg->eSpcTickBase));
SENT_HWA_SetChannelSPCTriggerMethod(pSent, (uint8_t)eChannel, (SENT_SPCTriggerType)(pCfg->eSpcTrigger));
SENT_HWA_SetChannelSPCPulseDelay(pSent, (uint8_t)eChannel, pCfg->u8PulseDelay);
SENT_HWA_SetChannelSPCPulseWidth(pSent, (uint8_t)eChannel, pCfg->u8PulseWidth);
if(true == pCfg->bCalDiagEn)
{
SENT_HWA_EnableChannelCalibrationDiag(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelCalibrationDiag(pSent, (uint8_t)eChannel);
}
if(true == pCfg->bSpcModeEn)
{
SENT_HWA_EnableChannelSPCMode(pSent, (uint8_t)eChannel);
}
else
{
SENT_HWA_DisableChannelSPCMode(pSent, (uint8_t)eChannel);
}
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_GetFastMessageData(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, Sent_FastMessageDataType *pMsg)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
uint8_t u8DataShift;
if(true == aSentInit[eInstance])
{
if((NULL != pMsg) && (eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
pMsg->u8CRC = SENT_HWA_GetChannelFastMessageCRCNibble(pSent, (uint8_t)eChannel);
pMsg->u8SC = SENT_HWA_GetChannelFastMessageStatusNibble(pSent, (uint8_t)eChannel);
pMsg->u32Timestamp = SENT_HWA_GetChannelFastMessageTimeStamp(pSent, (uint8_t)eChannel);
u8DataShift = (5U - SENT_HWA_GetChannelNibbleNumber(pSent, (uint8_t)eChannel)) << 2U;
pMsg->u32Data = SENT_HWA_GetChannelDataNibble(pSent, (uint8_t)eChannel) >> (SENT_CHN_FDATA_DATA6_SHIFT + u8DataShift);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_GetSlowMessageData(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, Sent_SlowMessageDataType *pMsg)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((NULL != pMsg) && (eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
pMsg->eMsgType = (Sent_SerialMessageType)SENT_HWA_GetChannelSLowMessageType(pSent, (uint8_t)eChannel);
pMsg->u32Timestamp = SENT_HWA_GetChannelSlowMessageTimeStamp(pSent, (uint8_t)eChannel);
if(SENT_SERIAL_MESSAGE_SHORT == pMsg->eMsgType)
{
pMsg->u8CRC = SENT_HWA_GetChannelBit2CRC(pSent, (uint8_t)eChannel) & 0xFU;
pMsg->u16Data = (uint16_t)SENT_HWA_GetChannelBit2DATA(pSent, (uint8_t)eChannel) & 0xFFU;
pMsg->u8ID = SENT_HWA_GetChannelBit2DATA(pSent, (uint8_t)eChannel) >> 8U;
}
else if(SENT_SERIAL_MESSAGE_ENHANCE_12DATA_8ID == pMsg->eMsgType)
{
pMsg->u8CRC = SENT_HWA_GetChannelBit2CRC(pSent, (uint8_t)eChannel);
pMsg->u16Data = SENT_HWA_GetChannelBit2DATA(pSent, (uint8_t)eChannel);
pMsg->u8ID = (SENT_HWA_GetChannelBit3EnhancedID7_4_OR_ID3_0(pSent, (uint8_t)eChannel) << 4U) | SENT_HWA_GetChannelBit3EnhancedID3_0_OR_DATA15_12(pSent, (uint8_t)eChannel);
}
else if(SENT_SERIAL_MESSAGE_ENHANCE_16DATA_4ID == pMsg->eMsgType)
{
pMsg->u8CRC = SENT_HWA_GetChannelBit2CRC(pSent, (uint8_t)eChannel);
pMsg->u16Data = ((uint16_t)SENT_HWA_GetChannelBit3EnhancedID3_0_OR_DATA15_12(pSent, (uint8_t)eChannel) << 12U) | (uint16_t)SENT_HWA_GetChannelBit2DATA(pSent, (uint8_t)eChannel);
pMsg->u8ID = SENT_HWA_GetChannelBit3EnhancedID7_4_OR_ID3_0(pSent, (uint8_t)eChannel);
}
else
{
eRet = SENT_RETURN_E_NOT_OK;
}
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_DecodeFastMessageWithDMABuffer(uint32_t *pDmaBuffer, uint32_t u32BufferLength, Sent_FastMessageDataType *pMsg)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
if((NULL != pMsg) && (NULL != pDmaBuffer) && (12U == u32BufferLength))
{
pMsg->u8CRC = (uint8_t)((pDmaBuffer[1] & SENT_CHN_FCRC_CRC_DATA_MASK) >> SENT_CHN_FCRC_CRC_DATA_SHIFT);
pMsg->u8SC = (uint8_t)((pDmaBuffer[1] & SENT_CHN_FCRC_SC_NB_MASK) >> SENT_CHN_FCRC_SC_NB_SHIFT);
pMsg->u32Timestamp = ((pDmaBuffer[2] & SENT_CHN_FTS_TIMESTAMP_VAL_MASK) >> SENT_CHN_FTS_TIMESTAMP_VAL_SHIFT);
pMsg->u32Data = (pDmaBuffer[0] >> SENT_CHN_FDATA_DATA6_SHIFT);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
return eRet;
}
Sent_ReturnType SENT_DecodeSlowMessageWithDMABuffer(uint32_t *pDmaBuffer, uint32_t u32BufferLength, Sent_SlowMessageDataType *pMsg)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
if((NULL != pMsg) && (NULL != pDmaBuffer) && (12U == u32BufferLength))
{
if(SENT_CHN_SBIT3__MSG_TYPE_MASK == (pDmaBuffer[0] & SENT_CHN_SBIT3__MSG_TYPE_MASK))
{
if(SENT_CHN_SBIT3__CFG_MASK == (pDmaBuffer[0] & SENT_CHN_SBIT3__CFG_MASK))
{
pMsg->eMsgType = (Sent_SerialMessageType)SENT_SLOW_MESSAGE_ENHANCE_16DATA_4ID;
}
else
{
pMsg->eMsgType = (Sent_SerialMessageType)SENT_SLOW_MESSAGE_ENHANCE_12DATA_8ID;
}
}
else
{
pMsg->eMsgType = (Sent_SerialMessageType)SENT_SLOW_MESSAGE_SHORT;
}
pMsg->u32Timestamp = ((pDmaBuffer[2] & SENT_CHN_STS_SMSG_TIMESTAMP_MASK) >> SENT_CHN_STS_SMSG_TIMESTAMP_SHIFT);
if(SENT_SERIAL_MESSAGE_SHORT == pMsg->eMsgType)
{
pMsg->u8CRC =(uint8_t)(((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_CRC_MASK) >> SENT_CHN_SBIT2__SMSG_CRC_SHIFT) & 0xFU);
pMsg->u16Data = (uint16_t)(((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_DATA_MASK) >> SENT_CHN_SBIT2__SMSG_DATA_SHIFT) & 0xFFU);
pMsg->u8ID = (uint8_t)(((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_DATA_MASK) >> SENT_CHN_SBIT2__SMSG_DATA_SHIFT) >> 8U);
}
else if(SENT_SERIAL_MESSAGE_ENHANCE_12DATA_8ID == pMsg->eMsgType)
{
pMsg->u8CRC = (uint8_t)((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_CRC_MASK) >> SENT_CHN_SBIT2__SMSG_CRC_SHIFT);
pMsg->u16Data = (uint16_t)((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_DATA_MASK) >> SENT_CHN_SBIT2__SMSG_DATA_SHIFT);
pMsg->u8ID = (uint8_t)((((pDmaBuffer[0] & SENT_CHN_SBIT3__ID7_4_OR_ID3_0_MASK) >> SENT_CHN_SBIT3__ID7_4_OR_ID3_0_SHIFT) << 4U) |\
((pDmaBuffer[0] & SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_MASK) >> SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_SHIFT));
}
else if(SENT_SERIAL_MESSAGE_ENHANCE_16DATA_4ID == pMsg->eMsgType)
{
pMsg->u8CRC = (uint8_t)((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_CRC_MASK) >> SENT_CHN_SBIT2__SMSG_CRC_SHIFT);
pMsg->u16Data = (uint16_t)((((pDmaBuffer[0] & SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_MASK) >> SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_SHIFT) << 12U) |\
((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_DATA_MASK) >> SENT_CHN_SBIT2__SMSG_DATA_SHIFT));
pMsg->u8ID = (uint8_t)((pDmaBuffer[0] & SENT_CHN_SBIT3__ID7_4_OR_ID3_0_MASK) >> SENT_CHN_SBIT3__ID7_4_OR_ID3_0_SHIFT);
}
else
{
eRet = SENT_RETURN_E_NOT_OK;
}
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
return eRet;
}
Sent_ReturnType SENT_EnableGlobalFastMsgNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
SENT_HWA_EnableChannelFastMessageInterrupt(pSent, (uint8_t)eChannel);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_DisableGlobalFastMsgNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
SENT_HWA_DisableChannelFastMessageInterrupt(pSent, (uint8_t)eChannel);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_EnableGlobalSlowMsgNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
SENT_HWA_EnableChannelSlowMessageInterrupt(pSent, (uint8_t)eChannel);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_DisableGlobalSlowMsgNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
SENT_HWA_DisableChannelSlowMessageInterrupt(pSent, (uint8_t)eChannel);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_EnableGlobalFastFifoMsgNotification(const Sent_InstanceType eInstance)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if(eInstance < SENT_INSTANCE_MAX)
{
pSent = aSent_Base[eInstance];
SENT_HWA_EnableFastMessageFIFOOverflowInterrupt(pSent);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_DisableGlobalFastFifoMsgNotification(const Sent_InstanceType eInstance)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if(eInstance < SENT_INSTANCE_MAX)
{
pSent = aSent_Base[eInstance];
SENT_HWA_DisableFastMessageFIFOOverflowInterrupt(pSent);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_ConfigChannelStatusNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, const Sent_ChannelInterruptType *sInterruptEn)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
SENT_HWA_EnableChannelBusIdleInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bBusIdleITEn);
SENT_HWA_EnableChannelSPCOverRunInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bSpcOverrunITEn);
SENT_HWA_EnableChannelCALDiagInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bCalDiagErrITEn);
SENT_HWA_EnableChannelCalFailInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bCalFailITEn);
SENT_HWA_EnableChannelCalResyncInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bCalResyncErrITEn);
SENT_HWA_EnableChannelEdgeERRInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bFallingEdgeNumErrITEn);
SENT_HWA_EnableChannelFCRCInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bFastMsgCrcErrITEn);
SENT_HWA_EnableChannelFOVFLInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bFastMsgOFITEn);
SENT_HWA_EnableChannelNibbleErrorInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bNibbleValueErrITEn);
SENT_HWA_EnableChannelPPDiagInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bPrePulseDiagErrITEn);
SENT_HWA_EnableChannelSCRCInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bSlowMsgCrcErrITEn);
SENT_HWA_EnableChannelSOVFLInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bSlowMsgOFITEn);
SENT_HWA_EnableChannelCalERRInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bCalErrITEn);
//SENT_HWA_EnableChannelAllErrorInterrupt(pSent, eChannel);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_RequestSPCPulse(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
SENT_HWA_StartChannelSPC(pSent, (uint8_t)eChannel);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_GetFastMsgReadyFlag(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, bool *pFlag)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
*pFlag = SENT_HWA_GetFastMessageReadyFlag(pSent, (uint8_t)eChannel);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_GetSlowMsgReadyFlag(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, bool *pFlag)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
*pFlag = SENT_HWA_GetSlowMessageReadyFlag(pSent, (uint8_t)eChannel);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_GetChannelStatus(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, uint32_t *pStatus)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
*pStatus = SENT_HWA_GetChannelStatus(pSent, (uint8_t)eChannel);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_ClearChannelStatus(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, uint32_t Status)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
SENT_HWA_ClearChannelStatus(pSent, (uint8_t)eChannel, Status);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
Sent_ReturnType SENT_GetChannelSPCBusyFlag(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, bool *pflag)
{
Sent_ReturnType eRet = SENT_RETURN_OK;
SENT_Type *pSent;
if(true == aSentInit[eInstance])
{
if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX))
{
pSent = aSent_Base[eInstance];
*pflag = SENT_HWA_GetChanneSPCBusyFlag(pSent, (uint8_t)eChannel);
}
else
{
eRet = SENT_RETURN_E_PARAM;
}
}
else
{
eRet = SENT_RETURN_E_UNINIT;
}
return eRet;
}
void SENT0_IRQHandler(void)
{
SENT_IRQ_Handler(SENT_INSTANCE_0);
}
void SENT1_IRQHandler(void)
{
SENT_IRQ_Handler(SENT_INSTANCE_1);
}

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