483 lines
11 KiB
C
483 lines
11 KiB
C
/**
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* @file fc7xxx_driver_scm.h
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* @author Flagchip
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* @brief FC7xxx csc driver type definition and API
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* @version 0.1.0
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* @date 2024-01-12
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*
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* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
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******************************************************************************** */
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#include "fc7xxx_driver_scm.h"
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/**
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* @brief Get unique identification for the chip, loaded from NVR.
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*
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* @param pUid Pointer to UID
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*
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*/
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void SCM_GetChip_UID(uint32 *pUid)
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{
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DEV_ASSERT(NULL_PTR != pUid);
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pUid[0] = SCM_HWA_GetData_UIDL();
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pUid[1] = SCM_HWA_GetData_UIDML();
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pUid[2] = SCM_HWA_GetData_UIDMH();
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pUid[3] = SCM_HWA_GetData_UIDH();
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}
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/**
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* @brief Get CCMx status.
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*
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* @param eCCMType CCM type
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* @param u32Value selection to get
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*
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*/
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uint32_t SCM_GetStatus_CCMx(SCM_CCM_Type eCCMType, uint32_t u32Value)
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{
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uint32_t u32Temp;
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DEV_ASSERT(eCCMType == SCM_CCM0);
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DEV_ASSERT((u32Value & SCM_CCM0_STATUS_MASK) == 0U);
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if (SCM_CCM0 == eCCMType)
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{
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u32Temp = SCM_HWA_GetStatus_CCM0();
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}
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return (u32Temp & u32Value);
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}
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/**
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* @brief Get matrix status.
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*
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* @param eMatrixType Matrix type
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* @param u32Value selection to get
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*
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*/
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uint32_t SCM_GetStatus_Matrix(SCM_MatrixStatusType eMatrixType, uint32_t u32Value)
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{
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uint32_t u32Temp;
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DEV_ASSERT((uint32_t)eMatrixType <= (uint32_t)SCM_MatrixStatus_ID);
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if (SCM_MatrixStatus_0 == eMatrixType)
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{
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u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS0();
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}
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else if (SCM_MatrixStatus_1 == eMatrixType)
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{
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u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS1();
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}
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else if (SCM_MatrixStatus_2 == eMatrixType)
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{
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u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS2();
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}
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else if (SCM_MatrixStatus_5 == eMatrixType)
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{
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u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS5();
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}
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else if (SCM_MatrixStatus_6 == eMatrixType)
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{
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u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS6();
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}
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else if (SCM_MatrixStatus_7 == eMatrixType)
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{
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u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS7();
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}
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else
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{
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u32Temp = SCM_HWA_GetStatus_MATRIX_ID_STATUS0();
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}
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return (u32Temp & u32Value);
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}
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/**
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* @brief Set cpu to control MAM ECC enable register 0.
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*
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* @param eCpuType Cpu to use
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* @param bLockStatus Lock the cpu control settings
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*
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* @return Set operation success/failed
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*/
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SCM_RetStatusType SCM_SetCpuCtrl_MAMECCR0(const SCM_WPB_CpuType eCpuType, bool bLockStatus)
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{
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SCM_RetStatusType eRetVal;
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DEV_ASSERT((uint32_t)eCpuType < (uint32_t)SCM_WP_CPU_NONE);
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if (0U == SCM_HWA_MAMECCEN0_GetWPBLockStatus())
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{
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SCM_HWA_MAMECCEN0_SetCpuWritePermit(eCpuType);
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if (true == bLockStatus)
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{
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/* Lock the cpu to control settings until reset */
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SCM_HWA_MAMECCEN0_LockWritePermit();
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}
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eRetVal = SCM_E_OK;
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}
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else
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{
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eRetVal = SCM_E_LOCK;
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}
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return eRetVal;
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}
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/**
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* @brief Set cpu to control MAM ECC enable register 1.
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*
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* @param eCpuType Cpu to use
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* @param bLockStatus Lock the cpu control settings
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*
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* @return Set operation success/failed
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*/
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SCM_RetStatusType SCM_SetCpuCtrl_MAMECCR1(const SCM_WPB_CpuType eCpuType, bool bLockStatus)
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{
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SCM_RetStatusType eRetVal;
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DEV_ASSERT((uint32_t)eCpuType < (uint32_t)SCM_WP_CPU_NONE);
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if (0U == SCM_HWA_MAMECCEN1_GetWPBLockStatus())
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{
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SCM_HWA_MAMECCEN1_SetCpuWritePermit(eCpuType);
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if (true == bLockStatus)
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{
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/* Lock the cpu to control settings until reset */
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SCM_HWA_MAMECCEN1_LockWritePermit();
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}
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eRetVal = SCM_E_OK;
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}
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else
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{
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eRetVal = SCM_E_LOCK;
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}
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return eRetVal;
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}
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/**
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* @brief Set cpu to control CPU0 ECC enable register.
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*
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* @param eCpuType Cpu to use
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* @param bLockStatus Lock the cpu control settings
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*
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* @return Set operation success/failed
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*/
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SCM_RetStatusType SCM_SetCpuCtrl_CPU0ECCEN(const SCM_WPB_CpuType eCpuType, bool bLockStatus)
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{
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SCM_RetStatusType eRetVal;
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DEV_ASSERT((uint32_t)eCpuType < (uint32_t)SCM_WP_CPU_NONE);
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if (0U == SCM_HWA_CPU0ECCEN_GetWPBLockStatus())
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{
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SCM_HWA_CPU0ECCEN_SetCpuWritePermit(eCpuType);
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if (true == bLockStatus)
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{
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/* Lock the cpu to control settings until reset */
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SCM_HWA_CPU0ECCEN_LockWritePermit();
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}
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eRetVal = SCM_E_OK;
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}
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else
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{
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eRetVal = SCM_E_LOCK;
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}
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return eRetVal;
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}
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/**
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* @brief Set cpu to control SOCMISC register.
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*
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* @param eCpuType Cpu to use
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* @param bLockStatus Lock the cpu control settings
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*
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* @return Set operation success/failed
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*/
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SCM_RetStatusType SCM_SetCpuCtrl_SOCMISC(const SCM_WPB_CpuType eCpuType, bool bLockStatus)
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{
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SCM_RetStatusType eRetVal;
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if (0U == SCM_HWA_SOCMISC_GetWPBLockStatus())
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{
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SCM_HWA_SOCMISC_SetCpuWritePermit(eCpuType);
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if (true == bLockStatus)
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{
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/* Lock the cpu to control settings until reset */
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SCM_HWA_SOCMISC_LockWritePermit();
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}
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eRetVal = SCM_E_OK;
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}
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else
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{
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eRetVal = SCM_E_LOCK;
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}
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return eRetVal;
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}
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/**
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* @brief Set cpu to control Subsystem pcc register.
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*
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* @param eCpuType Cpu to use
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* @param bLockStatus Lock the cpu control settings
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*
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* @return Set operation success/failed
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*/
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SCM_RetStatusType SCM_SetCpuCtrl_SUBSYS_PCC(const SCM_WPB_CpuType eCpuType, bool bLockStatus)
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{
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SCM_RetStatusType eRetVal;
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if (0U == SCM_HWA_SUBSYS_PCC_GetWPBLockStatus())
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{
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SCM_HWA_SUBSYS_PCC_SetCpuWritePermit(eCpuType);
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if (true == bLockStatus)
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{
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/* Lock the cpu to control settings until reset */
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SCM_HWA_SUBSYS_PCC_LockWritePermit();
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}
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eRetVal = SCM_E_OK;
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}
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else
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{
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eRetVal = SCM_E_LOCK;
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}
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return eRetVal;
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}
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/**
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* @brief Set cpu to control master halt request register.
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*
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* @param eCpuType Cpu to use
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* @param bLockStatus Lock the cpu control settings
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*
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* @return Set operation success/failed
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*/
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SCM_RetStatusType SCM_SetCpuCtrl_MASTER_HALT_REQ(const SCM_WPB_CpuType eCpuType, bool bLockStatus)
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{
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SCM_RetStatusType eRetVal;
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if (0U == SCM_HWA_MASTER_HALT_REQ_GetWPBLockStatus())
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{
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SCM_HWA_MASTER_HALT_REQ_SetCpuWritePermit(eCpuType);
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if (true == bLockStatus)
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{
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/* Lock the cpu to control settings until reset */
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SCM_HWA_MASTER_HALT_REQ_LockWritePermit();
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}
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eRetVal = SCM_E_OK;
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}
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else
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{
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eRetVal = SCM_E_LOCK;
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}
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return eRetVal;
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}
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/**
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* @brief Set lock FTU_ROUTING register.
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*
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*/
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void SCM_SetLock_FTU_ROUTING(void)
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{
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if (0U == SCM_HWA_FTU_ROUTING_GetLockStatus())
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{
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SCM_HWA_LockFTU_ROUTING();
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}
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}
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/**
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* @brief Set lock FTU_GTB register.
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*
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*/
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void SCM_SetLock_FTU_GTB(void)
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{
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if (0U == SCM_HWA_FTU_GTB_GetLockStatus())
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{
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SCM_HWA_LockFTU_GTB();
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}
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}
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/**
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* @brief Set lock DEBUG_TRACE register.
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*
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*/
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void SCM_SetLock_DEBUG_TRACE(void)
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{
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if (0U == SCM_HWA_DEBUG_TRACE_GetLockStatus())
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{
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SCM_HWA_LockDEBUG_TRACE();
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}
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}
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/**
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* @brief Set lock FLEXCAN_ROUTING register.
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*
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*/
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void SCM_SetLock_FLEXCAN_ROUTING(void)
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{
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if (0U == SCM_HWA_FLEXCAN_ROUTING_GetLockStatus())
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{
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SCM_HWA_LockFLEXCAN_ROUTING();
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}
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}
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/**
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* @brief Set lock MSC0_ROUTING register.
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*
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*/
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void SCM_SetLock_MSC0_ROUTING(void)
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{
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if (0U == SCM_HWA_MSC0_ROUTING_GetLockStatus())
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{
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SCM_HWA_LockMSC0_ROUTING();
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}
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}
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/**
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* @brief Set lock INT_ROUTER_NMI register.
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*
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*/
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void SCM_SetLock_INT_ROUTER_NMI(void)
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{
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if (0U == SCM_HWA_INT_ROUTER_NMI_GetLockStatus())
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{
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SCM_HWA_LockINT_ROUTER_NMI();
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}
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}
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/**
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* @brief Set NMI interrupt router .
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*
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* @param eCpuType Cpu to use
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* @param bEnable Enable/Disable
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* @return Set operation success/failed
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*/
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SCM_RetStatusType SCM_SetEnable_NMIIntRouter(const SCM_WPB_CpuType eCpuType, bool bEnable)
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{
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SCM_RetStatusType eRetVal;
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if (SCM_WP_CPU_0 == eCpuType)
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{
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SCM_HWA_SetEnable_Cpu0NMIIrqRouter(bEnable);
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eRetVal = SCM_E_OK;
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}
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else
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{
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eRetVal = SCM_E_PARAM;
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}
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return eRetVal;
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}
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/**
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* @brief Generate the origion SCM register CRC result, and configure the SCM register CRC option.
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*
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* @param eMode The SCM register CRC trigger mode
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* @return CRC configure status
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* SCM_E_OK : CRC configure successfully
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* SCM_E_TIMEOUT : CRC configure time out
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*/
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SCM_RetStatusType SCM_RegCrcConfig(SCM_CrcModeType eMode)
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{
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SCM_RetStatusType eStatusVal = SCM_E_OK;
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uint32_t u32Timeout = 0xFFFFU;
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DEV_ASSERT((eMode == SCM_CRC_SW_MODE) || (eMode == SCM_CRC_TRIGGER_MODE));
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/* Deinit CRC register */
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SCM_HWA_SetEnable_CrcCheck(false);
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SCM_HWA_SetEnable_CrcTrigger(false);
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SCM_HWA_SetEnable_CrcErrOut(false);
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SCM_HWA_ClearCrcErrorFlag();
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/* Generate original CRC result */
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SCM_HWA_SetEnable_CrcSwGen(true);
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while (SCM_HWA_GetStatus_CrcBusyFlag() != 0U)
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{
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u32Timeout--;
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if (u32Timeout == 0U)
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{
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eStatusVal = SCM_E_TIMEOUT;
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break;
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}
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}
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if (eStatusVal == SCM_E_OK)
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{
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if (eMode == SCM_CRC_TRIGGER_MODE)
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{
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SCM_HWA_SetEnable_CrcTrigger(true);
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}
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/* Enable SCM CRC error to FCSMU in CSC0_SMU_CTRL4[SCM_CRC] */
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CSC0_HWA_CTRL4_EnableReqToSMU(CSC_SMU_SCM_CRC);
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/* Generate CRC error output */
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SCM_HWA_SetEnable_CrcErrOut(true);
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/* Generate CRC check */
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SCM_HWA_SetEnable_CrcCheck(true);
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}
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return eStatusVal;
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}
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/**
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* @brief Trigger the SCM register CRC generation by software
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*
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*/
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void SCM_RegCrcGenerate(void)
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{
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SCM_HWA_SetEnable_CrcSwGen(true);
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}
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/**
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* @brief Trigger the SCM register CRC generation by software,and wait the CRC check result
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*
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* @return CRC check result
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*/
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SCM_RetStatusType SCM_RegCrcGenerateWaitResult(void)
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{
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SCM_RetStatusType eStatusVal = SCM_E_OK;
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uint32_t u32Timeout = 0xFFFFU;
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SCM_HWA_SetEnable_CrcSwGen(true);
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while (SCM_HWA_GetStatus_CrcBusyFlag() != 0U)
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{
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u32Timeout--;
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if (u32Timeout == 0U)
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{
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eStatusVal = SCM_E_TIMEOUT;
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break;
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}
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}
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/* Check CRC is success or not */
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if (0U != SCM_HWA_GetStatus_CrcErrFlag())
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{
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eStatusVal = SCM_E_CRC;
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}
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return eStatusVal;
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}
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