252 lines
8.7 KiB
C
252 lines
8.7 KiB
C
/**
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* @file fc7xxx_driver_fcsmu.h
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* @author Flagchip
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* @brief FC7xxx FCSMU driver type definition and API
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* @version 0.1.0
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* @date 2024-01-14
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*
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* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240
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******************************************************************************** */
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#ifndef _DRIVER_FC7XXX_DRIVER_FCSMU_H_
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#define _DRIVER_FC7XXX_DRIVER_FCSMU_H_
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#include "device_header.h"
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#include "HwA_fcsmu.h"
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/**
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* @addtogroup fc7xxx_driver_fcsmu
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* @{
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. */
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typedef enum
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{
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FCSMU_INSTANCE_0 = 0U, /*!< FCSMU instance 0 is selected. */
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} FCSMU_InstanceType;
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typedef enum
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{
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FCSMU_STATUS_SUCCESS = 0U, /*!< FCSMU operation is succeed. */
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FCSMU_STATUS_ERROR = 1U /*!< FCSMU operation is failed. */
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} FCSMU_StatusType;
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typedef enum
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{
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FCSMU_STATE_NORMAL = 0U, /*!< FCSMU state normal */
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FCSMU_STATE_CONGIG = 1U, /*!< FCSMU state config */
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FCSMU_STATE_WARN = 2U, /*!< FCSMU state warn */
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FCSMU_STATE_FAULT = 3U /*!< FCSMU state fault */
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} FCSMU_StateType;
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typedef enum
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{
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FCSMU_OP_STATE_IDLE = 0U, /*!< FCSMU operation status idle */
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FCSMU_OP_STATE_BUSY = 1U, /*!< FCSMU operation status busy */
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FCSMU_OP_STATE_FAILED = 2U, /*!< FCSMU operation status failed */
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FCSMU_OP_STATE_SUCCESSFUL = 3U /*!< FCSMU operation status successful */
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} FCSMU_OperationStatusType;
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typedef enum
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{
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FCSMU_CRC_SW_MODE = 0U, /*!< FCSMU crc software mode. */
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FCSMU_CRC_TRIGGER_MODE = 1U /*!< FCSMU crc trigger mode. */
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} FCSMU_CrcModeType;
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typedef enum
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{
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FCSMU_SOUT_CTRL_BY_FSM = 0U, /*!< SOUT is controlled by the FSM. */
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FCSMU_SOUT_CTRL_KEEP_LOW = 1U, /*!< SOUT keeps low. */
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FCSMU_SOUT_CTRL_BY_FSM2 = 2U, /*!< SOUT is controlled by the FSM. */
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FCSMU_SOUT_CTRL_KEEP_HIGH_THEN_FSM = 3U /*!< SOUT keeps high until a fault occures on a channel, then controlled by FSM. */
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} FCSMU_SoutControlType;
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typedef enum
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{
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FCSMU_SOUT_DEFAUT_POLARITY = 0U, /*!< Default polarity. */
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FCSMU_SOUT_SWITCH_POLARITY = 1U /*!< Switch polarity. */
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} FCSMU_SoutPolarityType;
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typedef enum
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{
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FCSMU_SOUT_PROTOCOL_DUAL_RAIL = 0U,
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FCSMU_SOUT_PROTOCOL_TIME_SWITCH = 1U,
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FCSMU_SOUT_PROTOCOL_BISTABLE = 2U,
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FCSMU_SOUT_PROTOCOL_FAULT_TOGGLE = 3U,
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FCSMU_SOUT_PROTOCOL_TIME_DUAL_RAIL = 4U,
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FCSMU_SOUT_PROTOCOL_DIAG0 = 5U,
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FCSMU_SOUT_PROTOCOL_DIAG1 = 6U,
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FCSMU_SOUT_PROTOCOL_DIAG2 = 7U,
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} FCSMU_SoutProtocolType;
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typedef enum
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{
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FCSMU_WARNING_IRQ = 0U,
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FCSMU_FAULT_IRQ = 1U,
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FCSMU_CFG_TIMEOUT = 2U
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} FCSMU_IQRType;
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typedef enum
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{
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FCSMU_FAULT_CHANNEL_NONE = 0x0U,
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FCSMU_FAULT_CHANNEL_TEMP_ERROR = 0x1U, /*!< Event from temperature sensor. */
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FCSMU_FAULT_CHANNEL_PMC_ERROR = 0x2U, /*!< Voltage out of range indication from PMC. */
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FCSMU_FAULT_CHANNEL_NVR_ERROR = 0x4U, /*!< NVR load error/System abnormal alarm signal. */
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FCSMU_FAULT_CHANNEL_STCU_BIST_ERROR = 0x8U, /*!< STCU MBIST or LBIST fail. */
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FCSMU_FAULT_CHANNEL_STCU_LS0_ERROR = 0x10U, /*!< Lockstep compare fault. */
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FCSMU_FAULT_CHANNEL_SYSTEM_CPU0_ERROR = 0x40U, /*!< System RAM CPU0 access error. */
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FCSMU_FAULT_CHANNEL_SYSTEM_NON_CPU_ERROR = 0x200U, /*!< System RAM None CPU access error. */
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FCSMU_FAULT_CHANNEL_SCM_CPU0_ERROR = 0x400U, /*!< Matrix Access Monitor ECC check CPU0 error. */
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FCSMU_FAULT_CHANNEL_SCM_NON_CPU_ERROR = 0x2000U, /*!< Matrix Access Monitor ECC check non CPU error. */
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FCSMU_FAULT_CHANNEL_CPU0_ECC_ERROR = 0x4000U, /*!< Including ITCM/DTCM/ICACHE/DCACHE. */
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FCSMU_FAULT_CHANNEL_CMU4_FAIL_ERROR = 0x80000U, /*!< CMU4 failure interrupt. */
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FCSMU_FAULT_CHANNEL_CMU_FAIL_ERROR = 0x100000U, /*!< CMU1/2 failure interrupt. */
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FCSMU_FAULT_CHANNEL_FLASH_ECC_ERROR = 0x200000U, /*!< Flash ECC error. */
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FCSMU_FAULT_CHANNEL_SCG_PLL_FOSC_ERROR = 0x400000U, /*!< PLL/FOSC loss of clock. */
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FCSMU_FAULT_CHANNEL_DMA0_ERROR = 0x800000U, /*!< DM0 AHB Error/LS Error/CFG RAM Error. */
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FCSMU_FAULT_CHANNEL_INTM0_ERROR = 0x2000000U, /*!< Interrupt Monitor error. */
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FCSMU_FAULT_CHANNEL_FMC_ERROR = 0x10000000U, /*!< FMC ECC error. */
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FCSMU_FAULT_CHANNEL_SCG_SCM_CRC_ERROR = 0x20000000U, /*!< SCG and SCM etc. CRC check error. */
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FCSMU_FAULT_CHANNEL_MAM_WDG_ERROR = 0x80000000U, /*!< MAM master access time out error. */
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} FCSMU_ChannelAssignmentType;
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/**
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* @brief FCSMU Channel ISR callback function prototype
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*
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*/
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typedef void (*FCSMU_ISRCallbackType)(FCSMU_IQRType eIrqType, uint32_t u32IrqChannel);
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typedef struct
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{
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bool bEnable; /*!< Enable or disable status output. */
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bool eFastMode; /*!< Enable or disable fast mode. */
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bool bDivex; /*!< SOUT Divider Extend Control. */
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FCSMU_SoutControlType eSoutCtrl; /*!< Configure Sout Control. */
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FCSMU_SoutPolarityType ePolarity; /*!< Status output polarity. */
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FCSMU_SoutProtocolType eProtocal; /*!< Status output protocal. */
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uint32_t u32Delaytimer; /*!< Configure the safe mode request delay in cycles of CLKSAFE. */
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uint32_t u32Divder; /*!< Configure the status output divider ratio.
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bDevex = 0, SOUT_freq = CLKSAFE_freq/((SOUT_DIV+1)*2*256)
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bDevex = 1, SOUT_freq = CLKSAFE_freq/((SOUT_DIV+1)*2*64)
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*/
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uint32_t u32SoutChannel; /*!< Configure the status output channel. */
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} FCSMU_StatusOutputConfigType;
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typedef struct
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{
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uint32_t u32WarnTo; /*!< FCSMU warning timeoout value. */
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uint32_t u32WarnChannel; /*!< FCSMU warning channel. */
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uint32_t u32FaultChannel; /*!< FCSMU fault channel. */
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uint32_t u32WarnInterruptChannel; /*!< FCSMU warning interrupt channel. */
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uint32_t u32FaultInterruptChannel; /*!< FCSMU fault interrupt channel. */
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uint32_t u32FaultResetChannel; /*!< FCSMU fault reset channel. */
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uint32_t u32SoftwareClearedChannel; /*!< FCSMU fault is Cleard by software. */
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FCSMU_ISRCallbackType pISRCallback; /*!< ISR callback. */
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} FCSMU_InitCfgType;
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/**
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* @brief Init the FCSMU.
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*
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* @param pInitConfig FCSMU initial configuration.
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*/
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FCSMU_StatusType FCSMU_init(const FCSMU_InitCfgType *pInitConfig);
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/**
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* @brief Config the FCSMU status output.
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*
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* @param pInitConfig FCSMU status output configuration.
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*/
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FCSMU_StatusType FCSMU_ConfigStatusOutput(FCSMU_StatusOutputConfigType *pInitConfig);
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/**
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* @brief Generate the CRC.
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*
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*/
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void FCSMU_CrcGen(void);
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/**
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* @brief Query CRC busy status.
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*
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* @return FCSMU_CrcModeType CRC status.
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*/
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bool FCSMU_IsCrcBusy(void);
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/**
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* @brief Configure the FCSMU CRC.
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*
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* @param eMode Crc mode.
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* @return FCSMU_StatusType Status of configuration.
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*/
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FCSMU_StatusType FCSMU_CrcConfig(FCSMU_CrcModeType eMode);
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/**
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* @brief Clear the falut flag.
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*
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* @param u32FaultChannel Channel flag to be cleared.
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* @return FCSMU_StatusType Status of clear.
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*/
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FCSMU_StatusType FCSMU_ClearFaultFlag(uint32_t u32FaultChannel);
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/**
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* @brief Transform state from configuration to normal.
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*
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* @return FCSMU_StatusType Status of Transformation.
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*/
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FCSMU_StatusType FCSMU_TransStateCTN(void);
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/**
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* @brief Transform state from normal to configuration.
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*
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* @return FCSMU_StatusType Status of Transformation.
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*/
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FCSMU_StatusType FCSMU_TransStateNTC(void);
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/**
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* @brief Inject the fault tp fcsmu.
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*
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* @param u32ChannelIndex channel to be injected.
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*/
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void FCSMU_InjectionFault(uint32_t u32ChannelIndex);
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/**
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* @brief Get the fault channels fcsmu.
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*
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* @return Fault channels.
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*/
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uint32_t FCSMU_GetFaultChannel(void);
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/**
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* @brief Get the interrupt state of fcsmu.
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*
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* @return interrupt state.
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*/
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uint32_t FCSMU_GetIrqState(void);
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/**
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* @brief Get the NTF flags of fcsmu.
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*
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* @return NTF flags.
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*/
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uint32_t FCSMU_GetNtfFlag(void);
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/**
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* @brief Get the WTF flags of fcsmu.
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*
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* @return WTF flags.
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*/
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uint32_t FCSMU_GetWtfFlag(void);
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/**
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* @brief Get the NTW flags of fcsmu.
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*
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* @return NTW flags.
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*/
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uint32_t FCSMU_GetNtwFlag(void);
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/** @}*/ /* fc7xxx_driver_fcsmu. */
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#endif
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