129 lines
4.2 KiB
C
129 lines
4.2 KiB
C
/**
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* @file fc7xxx_driver_mpu.c
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* @author Flagchip085
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* @brief FC7xxx MPU driver type definition and API
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* @version 0.1.0
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* @date 2024-01-12
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*
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* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
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*
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* @details The MPU only checks the CPU master access to CTCM and DTCM memory. When access denied, it will cause MemManage Interrupt.
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
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******************************************************************************** */
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#include "fc7xxx_driver_mpu.h"
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void MPU_Disable(void)
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{
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__DMB(); /* make sure outstanding transfers are done */
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MPU_HWA_Fault_Disable();
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MPU_HWA_Set_CR(0U); /* disable mpu and clear its control register*/
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}
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void MPU_Enable(MPU_EnableOptionType eOption)
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{
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uint32_t u32Option;
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switch (eOption)
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{
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case MPU_EN_HARDFAULT_NMI:
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u32Option = CORTEX_MPU_CTRL_HFNMIENA_MASK;
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break;
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case MPU_EN_PRIVILEGED_DEFAULT:
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u32Option = CORTEX_MPU_CTRL_RPRIVDEFENA_MASK;
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break;
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case MPU_EN_HFNMI_PRIVDEF:
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u32Option = (CORTEX_MPU_CTRL_HFNMIENA_MASK | CORTEX_MPU_CTRL_RPRIVDEFENA_MASK);
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break;
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case MPU_EN_HFNMI_PRIVDEF_NONE:
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u32Option = 0U;
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break;
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default:
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u32Option = 0U;
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break;
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}
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MPU_HWA_Set_CR(CORTEX_MPU_CTRL_ENABLE_MASK | (((uint32_t)u32Option) & MPU_EN_MASK_U32));
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MPU_HWA_Fault_Enable(); /* mpu fault MemManage INT enable */
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__DSB();
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__ISB();
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}
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MPU_StatusType MPU_RegionDisable(MPU_RegionNumberType eRegion)
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{
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MPU_HWA_Set_NR((uint8_t)eRegion);
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MPU_HWA_Set_BAR(0x00U);
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MPU_HWA_Set_ASR(0x00U);
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return MPU_STATUS_SUCCESS;
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}
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MPU_StatusType MPU_RegionEnable(MPU_RegionNumberType eRegion, const MPU_RegionConfigurationType *pConfig)
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{
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MPU_StatusType eRet = MPU_STATUS_SUCCESS;
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uint32_t u32Srd;
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uint32_t u32Asr;
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if ((NULL == pConfig) ||
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((uint32_t)eRegion > (uint32_t)MPU_REGION_NUMBER_15) ||
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(0U != (pConfig->u32BaseAddr & MPU_RBAR_VALID_REGION_MASK_U32)) ||
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((uint32_t)pConfig->eRegionSize < (uint32_t)MPU_REGION_SIZE_32B) ||
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((uint32_t)pConfig->eRegionSize > (uint32_t)MPU_REGION_SIZE_4GB))
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{
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eRet = MPU_STATUS_ERROR;
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}
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else
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{
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/* use bit shift is surely safe */
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u32Srd = (((((uint32_t)pConfig->eSubRegionDis_0) << 0) |
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(((uint32_t)pConfig->eSubRegionDis_1) << 1) |
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(((uint32_t)pConfig->eSubRegionDis_2) << 2) |
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(((uint32_t)pConfig->eSubRegionDis_3) << 3) |
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(((uint32_t)pConfig->eSubRegionDis_4) << 4) |
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(((uint32_t)pConfig->eSubRegionDis_5) << 5) |
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(((uint32_t)pConfig->eSubRegionDis_6) << 6) |
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(((uint32_t)pConfig->eSubRegionDis_7) << 7)) & 0xFFU);
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u32Asr = CORTEX_MPU_RASR_XN(pConfig->eExecuteNever) |
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CORTEX_MPU_RASR_AP(pConfig->eAccessPermission) |
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CORTEX_MPU_RASR_TEX(pConfig->eTypeExtLevel) |
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CORTEX_MPU_RASR_S(pConfig->eShareable) |
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CORTEX_MPU_RASR_C(pConfig->eCacheable) |
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CORTEX_MPU_RASR_B(pConfig->eBufferable) |
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CORTEX_MPU_RASR_SRD(u32Srd) |
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CORTEX_MPU_RASR_SIZE(pConfig->eRegionSize) |
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CORTEX_MPU_RASR_ENABLE_MASK;
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MPU_HWA_Set_NR((uint8_t)eRegion);
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MPU_HWA_Set_BAR(pConfig->u32BaseAddr & MPU_RBAR_BASEADDR_MASK_U32); /* ignore VALID and REGION bits */
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MPU_HWA_Set_ASR(u32Asr);
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}
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return eRet;
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}
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MPU_StatusType MPU_CheckExist(void)
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{
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uint32_t u32RegVal = MPU_HWA_Get_Type();
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MPU_StatusType eRet = MPU_STATUS_SUCCESS;
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if (0U == u32RegVal)
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{
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eRet = MPU_STATUS_ERROR;
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}
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return eRet;
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}
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