460 lines
18 KiB
C
460 lines
18 KiB
C
/**
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* @file fc7xxx_driver_scg.h
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* @author Flagchip085
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* @brief FC7xxx SCG driver type definition and API
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* @version 0.1.0
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* @date 2024-01-12
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*
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* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240
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******************************************************************************** */
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#ifndef _DRIVER_FC7XXX_DRIVER_SCG_H_
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#define _DRIVER_FC7XXX_DRIVER_SCG_H_
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#include "HwA_scg.h"
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#include "HwA_csc.h"
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/**
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* @addtogroup fc7xxx_driver_scg
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* @{
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*/
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/** @brief clock list for internal clock tree */
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typedef enum
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{
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/* Main clocks */
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SCG_CORE_CLK = 0U, /*!< Core clock */
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SCG_BUS_CLK = 1U, /*!< Bus clock */
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SCG_SLOW_CLK = 2U, /*!< Slow clock */
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/* Other internal clocks used by peripherals. */
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SCG_FOSC_CLK = 3U, /*!< FOSC clock */
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SCG_FIRC_CLK = 4U, /*!< FIRC clock */
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SCG_PLL0_CLK = 5U, /*!< PLL0 clock */
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SCG_PLL1_CLK = 6U, /*!< PLL1 clock */
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SCG_SIRC_CLK = 7U, /*!< SIRC clock */
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SCG_SIRC32K_CLK = 8U, /*!< SIRC32K clock */
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SCG_SOSC_CLK = 9U, /*!< SOSC clock */
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SCG_SCG_CLKOUT_CLK = 10U, /*!< SCG CLK_OUT clock */
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SCG_SIRCDIVH_CLK = 11U, /*!< SIRCDIVH functional clock */
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SCG_SIRCDIVM_CLK = 12U, /*!< SIRCDIVM functional clock */
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SCG_SIRCDIVL_CLK = 13U, /*!< SIRCDIVL functional clock */
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SCG_FIRCDIVH_CLK = 14U, /*!< FIRCDIVH functional clock */
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SCG_FIRCDIVM_CLK = 15U, /*!< FIRCDIVM functional clock */
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SCG_FIRCDIVL_CLK = 16U, /*!< FIRCDIVL functional clock */
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SCG_FOSCDIVH_CLK = 17U, /*!< FOSCDIVH functional clock */
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SCG_FOSCDIVM_CLK = 18U, /*!< FOSCDIVM functional clock */
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SCG_FOSCDIVL_CLK = 19U, /*!< FOSCDIVL functional clock */
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SCG_PLL0DIVH_CLK = 20U, /*!< PLL0DIVH functional clock */
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SCG_PLL0DIVM_CLK = 21U, /*!< PLL0DIVM functional clock */
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SCG_PLL0DIVL_CLK = 22U, /*!< PLL0DIVL functional clock */
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SCG_PLL1DIVH_CLK = 23U, /*!< PLL1DIVH functional clock */
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SCG_PLL1DIVM_CLK = 24U, /*!< PLL1DIVM functional clock */
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SCG_PLL1DIVL_CLK = 25U, /*!< PLL1DIVL functional clock */
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SCG_NVMINIT_CLK = 26U, /*!< NVM initial clock source */
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SCG_CMU4REF_CLK = 27U, /*!< CMU4 reference clock */
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SCG_END_OF_CLOCKS = 28U /*!< End of SCG clocks */
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} SCG_ClkSrcType;
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/**
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* @brief PLL clock type
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*/
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typedef enum
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{
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SCG_PLL0 = 0U, /*!< PLL0 clock */
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SCG_PLL1 = 1U /*!< PLL1 clock */
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} SCG_PllClkType;
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/**
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* @brief indicate the clock function status
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*
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*/
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typedef enum
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{
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SCG_STATUS_SUCCESS = 0U, /*!< function called success */
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SCG_STATUS_SEQUENCE_ERROR = 1U, /*!< function called report sequence error */
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SCG_STATUS_TIMEOUT = 2U, /*!< function called report timeout error */
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SCG_STATUS_IRC_ERROR = 3U, /*!< function called report internal clock error */
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SCG_STATUS_PARAM_ERROR = 4U /*!< function called report internal clock error */
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} SCG_StatusType;
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/**
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* @brief indicate the CRC check result
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*
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*/
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typedef enum
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{
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SCG_CRC_CHECK_SUCCESS = 0U, /*!< CRC check success *//**< SCG_CRC_CHECK_SUCCESS */
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SCG_CRC_GEN_TIMEOUT = 1U, /*!< CRC Generate Timeout *//**< SCG_CRC_GEN_TIMEOUT */
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SCG_CRC_CHECK_FAILED = 2U /*!< CRC check failed */ /**< SCG_CRC_CHECK_FAILED */
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} SCG_CrcCheckResType;
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/**
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* @brief SCG xxxIRC TRIMSRC type.
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*/
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typedef enum
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{
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SCG_IRC_TRIMSRC_RESERVE0 = 0U, /*!< Clock Trim source reserve0 */
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SCG_IRC_TRIMSRC_RESERVE1 = 1U, /*!< Clock Trim source reserve1 */
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SCG_IRC_TRIMSRC_FOSC = 2U, /*!< Clock Trim source FOSC */
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SCG_IRC_TRIMSRC_SOSC = 3U, /*!< Clock Trim source SOSC */
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} SCG_IrcTrimSrcType;
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/**
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* @brief SCG_CCR [SCS] to Select system clock source
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*
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*/
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typedef enum
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{
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SCG_CLOCK_SRC_FOSC = 1U, /*!< System OSC. */
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SCG_CLOCK_SRC_SIRC = 2U, /*!< Slow IRC 12MHz. */
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SCG_CLOCK_SRC_FIRC = 3U, /*!< Fast IRC. */
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SCG_CLOCK_SRC_PLL0 = 6U, /*!< System PLL. */
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SCG_CLOCK_SRC_NONE = 255U /*!< MAX value. */
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} SCG_ClockSrcType;
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/**
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* @brief SCG_CCR [DIVCORE ]/ SCG_CCR [DIVBUS ]/ SCG_CCR [DIVSLOW ] to Select system clock source.
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*
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*/
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typedef enum
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{
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SCG_CLOCK_DIV_BY1 = 0U, /*!< Divided by 1. */
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SCG_CLOCK_DIV_BY2 = 1U, /*!< Divided by 2. */
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SCG_CLOCK_DIV_BY3 = 2U, /*!< Divided by 3. */
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SCG_CLOCK_DIV_BY4 = 3U /*!< Divided by 4. */
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} SCG_ClockDivType;
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/**
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* @brief SCG_ CLKOUTCFG [CLKOUTSEL] to Select system clock source.
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*/
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typedef enum
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{
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SCG_CLOCKOUT_SRC_OFF = 0U, /*!< SCG OFF. */
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SCG_CLOCKOUT_SRC_FOSC = 1U, /*!< Fast OSC. */
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SCG_CLOCKOUT_SRC_SIRC = 2U, /*!< Slow IRC. */
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SCG_CLOCKOUT_SRC_FIRC = 3U, /*!< Fast IRC. */
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SCG_CLOCKOUT_SRC_SOSC = 4U, /*!< Slow OSC. */
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SCG_CLOCKOUT_SRC_PLL1 = 5U, /*!< System PLL1. */
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SCG_CLOCKOUT_SRC_PLL0 = 6U, /*!< System PLL0. */
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SCG_CLOCKOUT_SRC_SIRC32K = 7U, /*!< SIRC32K_CLK.*/
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} SCG_ClockoutSrcType;
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/**
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* @brief NVM clock source enumeration
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*/
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typedef enum
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{
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SCG_NVMCLK_SRC_SIRC = 30u, /*!< NVM source choose SIRC. */
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SCG_NVMCLK_SRC_FIRC = 31u /*!< NVM source choose FIRC. */
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} SCG_NvmClkSrcType;
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/**
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* @brief CMU4 clock source enumeration
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*/
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typedef enum
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{
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SCG_CMU4CLK_SRC_SIRC = 28u, /*!< NVM source choose SIRC. */
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SCG_CMU4CLK_SRC_FOSC = 29u /*!< NVM source choose FORC. */
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} SCG_Cmu4ClkSrcType;
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/**
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* @brief SCG registers CRC trigger mode
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*/
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typedef enum
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{
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SCG_CRC_SW_MODE = 0U, /*!< SCG registers CRC software mode. */
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SCG_CRC_TRIGGER_MODE = 1U /*!< SCG registers CRC trigger mode. */
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} SCG_CrcModeType;
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/** @brief [DIVL]/[DIVM]/[DIVH] bit field definition for SCG_SIRC/ SCG_FIRC/ SCG_FOSC/ SCG_PLL0 registers */
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typedef enum
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{
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SCG_ASYNC_CLOCK_DISABLE = 0U, /*!< Clock output is disabled. */
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SCG_ASYNCCLOCKDIV_BY1 = 1U, /*!< Divided by 1. */
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SCG_ASYNCCLOCKDIV_BY2 = 2U, /*!< Divided by 2. */
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SCG_ASYNCCLOCKDIV_BY4 = 3U, /*!< Divided by 4. */
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SCG_ASYNCCLOCKDIV_BY8 = 4U, /*!< Divided by 8. */
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SCG_ASYNCCLOCKDIV_BY16 = 5U, /*!< Divided by 16. */
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SCG_ASYNCCLOCKDIV_BY32 = 6U, /*!< Divided by 32. */
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SCG_ASYNCCLOCKDIV_BY64 = 7U /*!< Divided by 64. */
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} SCG_AsyncClockDivType;
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/** @brief SCG_ PLLCFG[PREDIV] for PLL clock calculation. The pre-div value range is 0 ~ 31 */
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typedef uint8_t SCG_PllPredivType;
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/** @brief SCG_ PLLCFG[PSTDIV] for PLL clock calculation */
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typedef enum
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{
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SCG_PLLPSTDIV_BY2 = 1U,
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SCG_PLLPSTDIV_BY4 = 2U,
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SCG_PLLPSTDIV_BY8 = 3U
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} SCG_PllPstdivType;
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/** @brief SCG_ PLLCFG[SOURCE] to Select PLL clock source */
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typedef enum
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{
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SCG_PLLSOURCE_FOSC = 0U,
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SCG_PLLSOURCE_FIRC = 1U
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} SCG_PllSourceType;
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/** @brief SCG_ PLLCFG [MULT] for PLL clock calculation. The mult value range is 96 ~ 512 */
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typedef uint16_t SCG_PllMultiplyType;
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/** @brief FOSC initial definition, include register SCG_FOSCCSR/SCG_FOSCDIV/SCG_FOSCCFG. */
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typedef struct
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{
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bool bLock; /*!< SCG_FOSCCSR[LK] bit, Write to set the register can be written or not */
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bool bCm; /*!< SCG_FOSCCSR[CM] bit, Clock Monitor is enable */
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bool bCmre; /*!< SCG_FOSCCSR[CMRE] bit, Clock Monitor Reset Enable
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0 Generates interrupt, 1 Generates rese */
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bool bSten; /*!< SCG_FOSCCSR[STEN] bit, Clock Stop in Stop modes */
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bool bBypass; /*!< SCG_FOSCCFG[BYPASS] bit, Configures FOSC for bypassing the internal oscillator.*/
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SCG_AsyncClockDivType eDivH; /*!< SCG_FOSCDIV[DIVH] bit field definition, 0 means disable. */
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SCG_AsyncClockDivType eDivM; /*!< SCG_FOSCDIV[DIVM] bit field definition, 0 means disable. */
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SCG_AsyncClockDivType eDivL; /*!< SCG_FOSCDIV[DIVL] bit field definition, 0 means disable. */
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} SCG_FoscType;
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/** @brief SIRC initial definition, include register SCG_ SIRCCSR/ SCG_ SIRCDIV/ SCG_ SIRCTCCFG. */
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typedef struct
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{
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bool bLock; /*!< SCG_SIRCCSR[LK] bit, Write to set the register can be written or not */
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bool bCm; /*!< SCG_SIRCCSR[CM] bit, SIRC Clock Monitor Enable */
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bool bTrEn; /*!< SCG_SIRCCSR[TREN] bit, IRC software trim enable (auto trim) */
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bool bLpen; /*!< SCG_SIRCCSR[LPEN] bit, Clock Stop Enable */
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bool bSten; /*!< SCG_SIRCCSR[STEN] bit, Clock Standby Enable */
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SCG_AsyncClockDivType eDivH; /*!< SCG_SIRCDIV[DIVH] bit field definition.*/
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SCG_AsyncClockDivType eDivM; /*!< SCG_SIRCDIV[DIVM] bit field definition.*/
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SCG_AsyncClockDivType eDivL; /*!< SCG_SIRCDIV[DIVL] bit field definition.*/
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uint8_t u8TrimSrc; /*!< SCG_SIRCTCFG[TRIMSRC] IRC clock auto trim reference clock source select.*/
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} SCG_SircType;
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typedef struct
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{
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bool bLock; /*!< SIRC32KCSR[LK] bit, Write to set the register can be written or not */
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} SCG_Sirc32kType;
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/** @brief FIRC initial definition, include register SCG_ FIRCCSR/ SCG_ FIRCDIV/ SCG_ FIRCFG. */
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typedef struct
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{
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bool bLock; /*!< SCG_FIRCCSR[LK] bit, Write to set the register can be written or not */
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bool bCm; /*!< SCG_FIRCCSR[CM] bit, FIRC Clock Monitor Enable */
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bool bTrEn; /*!< SCG_FIRCCSR[TREN] bit, IRC software trim enable (auto trim) */
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bool bSten; /*!< SCG_FIRCCSR[STEN] bit, Clock Standby Enable */
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SCG_AsyncClockDivType eDivH; /*!< SCG_FIRCDIV[DIVH] bit field definition.*/
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SCG_AsyncClockDivType eDivM; /*!< SCG_FIRCDIV[DIVM] bit field definition.*/
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SCG_AsyncClockDivType eDivL; /*!< SCG_FIRCDIV[DIVL] bit field definition.*/
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uint8_t u8TrimSrc; /*!< SCG_FIRCTCFG[TRIMSRC] IRC clock auto trim reference clock source select.*/
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} SCG_FircType;
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/** @brief SOSC definition, include register SCG_SOSCCFG. */
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typedef struct
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{
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bool bLock; /*!< SCG_SOSCCSR[LK] bit, Write to set the register can be written or not.*/
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bool bBypass; /*!< SCG_SOSCCSR[BYPASS] bit, Configures SOSC for bypassing the internal oscillator.*/
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bool bCm; /*!< SCG_SOSCCSR[CM] bit,Clock Monitor enable.*/
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bool bCmre; /*!< SCG_SOSCCSR[CMRE] bit, 1:Clock Monitor Reset, 0: interrupt*/
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} SCG_SoscType;
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/** @brief PLL definition, include register SCG_PLLCSR/ SCG_PLLDIV/SCG_PLL0CFG. */
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typedef struct
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{
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bool bLock; /*!< SCG_PLLCSR[LK] bit, Write to set the register can be written or not.*/
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bool bCm; /*!< SCG_PLLCSR[CM] bit,Clock Monitor enable.*/
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bool bCmre; /*!< SCG_PLLCSR[CMRE] bit, 1:Clock Monitor Reset, 0: interrupt*/
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bool bSten; /*!< SCG_PLLCSR[STEN] bit, Clock Standby Enable */
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SCG_AsyncClockDivType eDivH; /*!< SCG_PLLDIV[DIVH] bit field definition.*/
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SCG_AsyncClockDivType eDivM; /*!< SCG_PLLDIV[DIVM] bit field definition.*/
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SCG_AsyncClockDivType eDivL; /*!< SCG_PLLDIV[DIVL] bit field definition.*/
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SCG_PllPredivType u8Prediv; /*!< SCG_PLLCFG[PREDIV] bit field definition, the range is 0~31. [Pre-divider = u8Prediv + 1] */
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SCG_PllPstdivType ePstDiv; /*!< SCG_PLLCFG[PSTDIV] bit field definition. [Post Divider = (ePstDiv == 0 ? 2 : 2^ePstDiv)] */
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SCG_PllMultiplyType u16Mult; /*!< SCG_PLLCFG[MULT] bit field definition, this value need to be greater than 95.
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[Multiplier = u16Mult + 1] */
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SCG_PllSourceType eSrc; /*!< SCG_PLLCFG[SOURCE] bit field definition.*/
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} SCG_PllType;
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/** @brief Current system clock definition, include register SCG_CCR. */
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typedef struct
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{
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bool bSysClkMonitor; /*!< SCG_CCR[SYSCLK_CME], System Clock monitor bit.*/
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SCG_ClockSrcType eSrc; /*!< SCG_CCR[SCS], System Clock Source.*/
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SCG_ClockDivType eDivSlow; /*!< SCG_CCR[DIVSLOW], Slow Clock Divide Ratio.*/
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SCG_ClockDivType eDivBus; /*!< SCG_CCR[DIVBUS], Bus Clock Divide Ratio.*/
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SCG_ClockDivType eDivCore; /*!< SCG_CCR[DIVCORE], Core Clock Divide Ratio.*/
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} SCG_ClockCtrlType;
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/**
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* @brief Enable SOSC
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*
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* @param pSoscConfig SOSC configuration
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* @return SCG_StatusType Function status
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*/
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SCG_StatusType SCG_EnableSOSC(const SCG_SoscType *const pSoscConfig);
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/**
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* @brief Disable SOSC
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*
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* @return SCG_StatusType Funtion status
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*/
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SCG_StatusType SCG_DisableSOSC(void);
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/**
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* @brief Enable FOSC clock with input configuration
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*
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* @param pFoscConfig FOSC configuration
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* @return SCG_StatusType function status
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*/
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SCG_StatusType SCG_EnableFOSC(const SCG_FoscType *const pFoscConfig);
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/**
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* @brief Disable FOSC
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*
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* @return SCG_StatusType function status
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*/
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SCG_StatusType SCG_DisableFOSC(void);
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/**
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* @brief Set SIRC configuration and configure SIRC DIV
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*
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* @param pSircConfig SIRC configuation
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* @return SCG_StatusType function status
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*/
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SCG_StatusType SCG_SetSIRC(const SCG_SircType *const pSircConfig);
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/**
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* @brief Disable SIRC DIV and clear DIV configuration
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*
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* @return SCG_StatusType function status
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*/
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SCG_StatusType SCG_ClearSIRC(void);
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/**
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* @brief Enable SIRC32K
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*
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* @param pSirc32kConfig SIRC32K configuration
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* @return SCG_StatusType function status
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*/
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SCG_StatusType SCG_EnableSIRC32K(const SCG_Sirc32kType *const pSirc32kConfig);
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/**
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* @brief Disable SIRC32K
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*
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* @return SCG_StatusType function status
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*/
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SCG_StatusType SCG_DisableSIRC32K(void);
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/**
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* @brief Enable FIRC
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*
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* @param pFircConfig FIRC configuration
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* @return SCG_StatusType function status
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*/
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SCG_StatusType SCG_EnableFIRC(const SCG_FircType *const pFircConfig);
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/**
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* @brief Disable FIRC
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*
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* @return SCG_StatusType function status
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*/
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SCG_StatusType SCG_DisableFIRC(void);
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/**
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* @brief Enable PLL
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*
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* @param ePll PLL instance
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* @param pPllConfig PLL configuration
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* @return SCG_StatusType function status
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*/
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SCG_StatusType SCG_EnablePLL(const SCG_PllClkType ePll, const SCG_PllType *const pPllConfig);
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/**
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* @brief Disable PLL
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*
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* @param ePll PLL instance
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* @return SCG_StatusType function status
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*/
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SCG_StatusType SCG_DisablePLL(const SCG_PllClkType ePll);
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/**
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* @brief Set system run time clock and related CORE/BUS/SLOW clock.
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*
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* @param pSysClkConfig pointer to the clockCtrlType structure data instance,which defined for system clock selection.
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* @return SCG_StatusType function status
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* SCG_STATUS_SUCCESS : clock source and dividers are valid,and switch system clock successfully
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* SCG_STATUS_SEQUENCE_ERROR: new clock source is not enabled
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* SCG_STATUS_PARAM_ERROR: the core bus slow divider are invalid
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* SCG_STATUS_TIMEOUT: switch system clock procedure time out
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*/
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SCG_StatusType SCG_SetClkCtrl(const SCG_ClockCtrlType *const pSysClkConfig);
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/**
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* @brief Get clock frequency
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*
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* @param eScgClockName Clock source type
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* @return uint32_t frequency value
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*/
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uint32_t SCG_GetScgClockFreq(const SCG_ClkSrcType eScgClockName);
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/**
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* @brief Select clock out source
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*
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* @param eClkoutSel clock out source
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*/
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void SCG_SetClkOut(const SCG_ClockoutSrcType eClkoutSel);
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/**
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* @brief Select NVM clock source
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*
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* @param eNvmClkSrc NVM clock source
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* @return uint32_t function status
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*/
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SCG_StatusType SCG_SetNvmClk(const SCG_NvmClkSrcType eNvmClkSrc);
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/**
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* @brief Select CMU4 clock source
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*
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* @param eCmu4ClkSrc CMU4 clock source
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* @return SCG_StatusType function status
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*/
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SCG_StatusType SCG_SetCmu4Clk(const SCG_Cmu4ClkSrcType eCmu4ClkSrc);
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/**
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* @brief Generate the origion SCG register CRC result, and configure the SCG register CRC option.
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*
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* @param eMode The SCG register CRC trigger mode
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* @return CRC configure status
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* SCG_STATUS_SUCCESS : CRC configure successfully
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* SCG_STATUS_TIMEOUT : CRC configure time out
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*/
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SCG_StatusType SCG_RegCrcConfig(SCG_CrcModeType eMode);
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/**
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* @brief Trigger the SCG register CRC generation by software
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*
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*/
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void SCG_RegCrcGenerate(void);
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/**
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* @brief Trigger the SCG register CRC generation by software,and wait the CRC check result
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*
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* @return CRC check result
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*/
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SCG_CrcCheckResType SCG_RegCrcGenerateWaitResult(void);
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/**
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* @brief Clock source De-init
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*
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* @return SCG_StatusType function status
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*/
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SCG_StatusType SCG_Deinit(void);
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/** @}*/ /* fc7xxx_driver_scg */
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#endif
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