231 lines
7.3 KiB
C
231 lines
7.3 KiB
C
/**
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* @file fc7xxx_driver_scst.c
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* @author Flagchip
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* @brief FC7xxx scst driver source code
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* @version 0.1.0
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* @date 2023-12-29
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*
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* @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/*********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2023-12-29 qxw074 N/A First version for FC7240
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******************************************************************************** */
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#include "fc7xxx_driver_scst.h"
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/**
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* @brief The address of the specific implementation of the M7ST API
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*
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*/
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#define M7ST_ROM_BASE 0x04812800
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/**
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* @brief The SCST Atomic Test function prototype
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*
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*/
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typedef Type_M7ST_AtomicStatus (*Type_M7ST_RegressionTest) (uint32_t TestStart, uint32_t TestEnd, uint32_t InjectEnable, uint32_t RamBase);
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/**
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* @brief The SCST Run selected tests function prototype
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*
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*/
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typedef Type_M7ST_AtomicStatus (*Type_M7ST_AtomicTest) (uint32_t TestID, uint32_t InjectEnable, uint32_t RamBase);
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/**
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* @brief M7ST API structure
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*
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*/
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typedef struct Struct_M7ST_RomTable
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{
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Type_M7ST_RegressionTest RegressionTest;
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Type_M7ST_AtomicTest AluTest;
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Type_M7ST_AtomicTest AluMLATest;
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Type_M7ST_AtomicTest AluSHIFTTest;
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Type_M7ST_AtomicTest AluTest1;
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Type_M7ST_AtomicTest AluTest2;
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Type_M7ST_AtomicTest AluTest3;
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Type_M7ST_AtomicTest AluTest4;
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Type_M7ST_AtomicTest AluTest5;
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Type_M7ST_AtomicTest AluTest6;
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Type_M7ST_AtomicTest RegbankTest1;
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Type_M7ST_AtomicTest RegbankTest2;
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Type_M7ST_AtomicTest RegbankTest3;
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Type_M7ST_AtomicTest RegbankTest4;
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Type_M7ST_AtomicTest RegbankTest5;
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Type_M7ST_AtomicTest RegbankTest6;
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Type_M7ST_AtomicTest LoadStoreTest1;
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Type_M7ST_AtomicTest LoadStoreTest2;
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Type_M7ST_AtomicTest LoadStoreTest3;
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Type_M7ST_AtomicTest LoadStoreTest4;
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Type_M7ST_AtomicTest LoadStoreTest5;
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Type_M7ST_AtomicTest LoadStoreTest6;
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Type_M7ST_AtomicTest SimdSatTest1;
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Type_M7ST_AtomicTest SimdSatTest2;
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Type_M7ST_AtomicTest SimdSatTest3;
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Type_M7ST_AtomicTest SimdSatTest4;
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Type_M7ST_AtomicTest MacTest1;
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Type_M7ST_AtomicTest MacTest2;
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Type_M7ST_AtomicTest FetchTest;
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Type_M7ST_AtomicTest StatusTest1;
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Type_M7ST_AtomicTest StatusTest2;
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Type_M7ST_AtomicTest BranchTest1;
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Type_M7ST_AtomicTest BranchTest2;
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} Type_M7ST_RomTable;
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/**
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* @brief This function is used to get the result of the executed test
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*
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* @param test_index is test number,0U..32U
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* @param s_u32RamBase The first address of the 1k memory that the program needs to run
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* @return M7ST_ErrorM7ST_TestPass is ok, others are not ok
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*/
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Type_M7ST_AtomicStatus SCST_ExecuteTest(SCST_TestIndexType test_index,uint32_t *s_u32RamBase)
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{
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Type_M7ST_AtomicStatus Status = M7ST_FaultInjectError;
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Type_M7ST_RomTable *M7ST_RomEntry = (Type_M7ST_RomTable *)M7ST_ROM_BASE;
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switch(test_index)
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{
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case M7ST_AluTest:
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Status = M7ST_RomEntry->AluTest(0,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_AluMLATest:
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Status = M7ST_RomEntry->AluMLATest(1,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_AluSHIFTTest:
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Status = M7ST_RomEntry->AluSHIFTTest(2,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_AluTes1t:
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Status = M7ST_RomEntry->AluTest1(3,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_AluTest2:
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Status = M7ST_RomEntry->AluTest2(4,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_AluTest3:
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Status = M7ST_RomEntry->AluTest3(5,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_AluTest4:
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Status = M7ST_RomEntry->AluTest4(6,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_AluTest5:
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Status = M7ST_RomEntry->AluTest5(7,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_AluTest6:
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Status = M7ST_RomEntry->AluTest6(8,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_RegbankTest1:
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Status = M7ST_RomEntry->RegbankTest1(9,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_RegbankTest2:
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Status = M7ST_RomEntry->RegbankTest2(10,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_RegbankTest3:
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Status = M7ST_RomEntry->RegbankTest3(11,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_RegbankTest4:
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Status = M7ST_RomEntry->RegbankTest4(12,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_RegbankTest5:
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Status = M7ST_RomEntry->RegbankTest5(13,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_RegbankTest6:
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Status = M7ST_RomEntry->RegbankTest6(14,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_LoadStoreTest1:
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Status = M7ST_RomEntry->LoadStoreTest1(15,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_LoadStoreTest2:
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Status = M7ST_RomEntry->LoadStoreTest2(16,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_LoadStoreTest3:
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Status = M7ST_RomEntry->LoadStoreTest3(17,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_LoadStoreTest4:
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Status = M7ST_RomEntry->LoadStoreTest4(18,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_LoadStoreTest5:
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Status = M7ST_RomEntry->LoadStoreTest5(19,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_LoadStoreTest6:
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Status = M7ST_RomEntry->LoadStoreTest6(20,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_SimdSatTest1:
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Status = M7ST_RomEntry->SimdSatTest1(21,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_SimdSatTest2:
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Status = M7ST_RomEntry->SimdSatTest2(22,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_SimdSatTest3:
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Status = M7ST_RomEntry->SimdSatTest3(23,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_SimdSatTest4:
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Status = M7ST_RomEntry->SimdSatTest4(24,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_MacTest1:
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Status = M7ST_RomEntry->MacTest1(25,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_MacTest2:
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Status = M7ST_RomEntry->MacTest2(26,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_FetchTest:
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Status = M7ST_RomEntry->FetchTest(27,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_StatusTest1:
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Status = M7ST_RomEntry->StatusTest1(28,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_StatusTest2:
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Status = M7ST_RomEntry->StatusTest2(29,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_BranchTest1:
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Status = M7ST_RomEntry->BranchTest1(30,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_BranchTest2:
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Status = M7ST_RomEntry->BranchTest2(31,0,(uint32_t)&s_u32RamBase[0]);
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break;
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case M7ST_RegressionTest:
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Status = M7ST_RomEntry->RegressionTest(0,31,0,(uint32_t)&s_u32RamBase[0]);
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break;
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default:
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break;
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}
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return Status;
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}
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