267 lines
12 KiB
C
267 lines
12 KiB
C
/**
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* @file fc7xxx_driver_stcu.h
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* @author Flagchip
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* @brief FC4xxx stcu driver type definition and API
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* @version 0.1.0
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* @date 2022-02-20
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*
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* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Author CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 12/08/2022 Flagchip038 N/A First version for FC7300
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******************************************************************************** */
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#ifndef _DRIVER_STCU_H_
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#define _DRIVER_STCU_H_
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/** @brief STCU self test status flag */
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typedef enum
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{
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STCU_SELFTEST_NONE = 0x00U, /**<! No any status flag. >*/
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STCU_SELFTEST_DONE = 0x01U, /**<! Self-test Done Flag. >*/
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STCU_SELFTEST_ABORT = 0x02U, /**<! Self-test Abort Flag. >*/
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STCU_SELFTEST_LBIST_ERROR = 0x10U, /**<! LBIST Error Flag. >*/
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STCU_SELFTEST_MBIST_ERROR = 0x20U, /**<! MBIST Error Flag. >*/
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STCU_SELFTEST_TIMEOUT_ERROR = 0x40U, /**<! Self-test Timeout Error Flag. >*/
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STCU_SELFTEST_NVRLOAD_ERROR = 0x100U, /**<! NVR Load Error Flag. >*/
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STCU_SELFTEST_SELFCHECK_ERROR = 0x200u /**<! STCU Self Check Error Flag. >*/
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}STCU_SelfTestStatusType;
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/** @brief STCU interrupt flag */
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typedef enum
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{
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STCU_INTERRUPT_FLAG_NONE = 0x00U, /**<! No any Interrupt flag. >*/
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STCU_INTERRUPT_FLAG_SIZE_ERR = 0x01U, /**<! STCU Register Access Size Error IRQ Flag. >*/
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STCU_INTERRUPT_FLAG_SEQ_ERR = 0x02U, /**<! Illegal Register Access Sequence IRQ Flag. >*/
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}STCU_InterruptFlagType;
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/** @brief The items select for MBIST */
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typedef enum
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{
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STCU_MBIST_SEL_NONE = 0x00U, /**<! No any MBist item selected. >*/
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STCU_MBIST_SEL_SRAM = 0x01U, /**<! SRAM Select for MBIST. >*/
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STCU_MBIST_SEL_ITCM_CPU0 = 0x02U, /**<! ITCM_CPU0 SRAM Select for MBIST. >*/
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STCU_MBIST_SEL_DTCM0_CPU0 = 0x04U, /**<! DTCM0_CPU0 SRAM Select for MBIST. >*/
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STCU_MBIST_SEL_DTCM1_CPU0 = 0x08U, /**<! DTCM1_CPU0 SRAM Select for MBIST. >*/
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STCU_MBIST_SEL_CACHE_CPU0 = 0x10U, /**<! CACHE_CPU0 SRAM Select for MBIST. >*/
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STCU_MBIST_SEL_SUBSYS = 0x20U, /**<! SUBSYS SRAM Select for MBIST. >*/
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STCU_MBIST_SEL_SRAM_HSM = 0x40U, /**<! HSM SRAM Select for MBIST. >*/
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STCU_MBIST_SEL_SRAM_DMACAN = 0x80U, /**<! DMA_FLEXCAN SRAM Select for MBIST. >*/
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STCU_MBIST_SEL_ROM_HOST = 0x100U, /**<! System ROM Select for MBIST. >*/
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STCU_MBIST_SEL_ROM_HSM = 0x200U /**<! HSM ROM Select for MBIST. >*/
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}STCU_MbistSelType;
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/** @brief MBIST done status flag. */
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typedef enum
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{
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STCU_MBIST_DONE_NONE = 0x00U, /**<! No any MBIST done flag. >*/
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STCU_MBIST_DONE_SRAM = 0x01U, /**<! SRAM MBIST Done Dlag. >*/
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STCU_MBIST_DONE_ITCM_CPU0 = 0x02U, /**<! ITCM_CPU0 SRAM MBIST Done Dlag. >*/
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STCU_MBIST_DONE_DTCM0_CPU0 = 0x04U, /**<! DTCM0_CPU0 SRAM MBIST Done Dlag. >*/
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STCU_MBIST_DONE_DTCM1_CPU0 = 0x08U, /**<! DTCM1_CPU0 SRAM MBIST Done Dlag. >*/
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STCU_MBIST_DONE_CACHE_CPU0 = 0x10U, /**<! CACHE_CPU0 SRAM MBIST Done Flag. >*/
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STCU_MBIST_DONE_SUBSYS = 0x20U, /**<! SUBSYS SRAM MBIST Done. >*/
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STCU_MBIST_DONE_SRAM_HSM = 0x40U, /**<! HSM SRAM MBIST Done Flag. >*/
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STCU_MBIST_DONE_SRAM_DMACAN = 0x80U, /**<! DMA_FLEXCAN SRAM MBIST Done Flag. >*/
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STCU_MBIST_DONE_ROM_HOST = 0x100U, /**<! System ROM MBIST Done Dlag. >*/
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STCU_MBIST_DONE_ROM_HSM = 0x200U /**<! HSM ROM MBIST Done Dlag. >*/
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}STCU_MbistDoneType;
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/** @brief MBIST fail status flag. */
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typedef enum
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{
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STCU_MBIST_FAIL_NONE = 0x00U, /**<! No any MBIST fail flag. >*/
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STCU_MBIST_FAIL_SRAM = 0x01U, /**<! SRAM MBIST Fail Flag. >*/
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STCU_MBIST_FAIL_ITCM_CPU0 = 0x02U, /**<! ITCM_CPU0 SRAM MBIST Fail Flag. >*/
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STCU_MBIST_FAIL_DTCM0_CPU0 = 0x04U, /**<! DTCM0_CPU0 SRAM MBIST Fail Flag. >*/
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STCU_MBIST_FAIL_DTCM1_CPU0 = 0x08U, /**<! DTCM1_CPU0 SRAM MBIST Fail Flag. >*/
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STCU_MBIST_FAIL_CACHE_CPU0 = 0x10U, /**<! CACHE_CPU0 SRAM MBIST Fail Flag. >*/
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STCU_MBIST_FAIL_SUBSYS = 0x20U, /**<! SUBSYS SRAM MBIST Fail Flag. >*/
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STCU_MBIST_FAIL_SRAM_HSM = 0x40U, /**<! HSM SRAM MBIST Fail Flag. >*/
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STCU_MBIST_FAIL_SRAM_DMACAN = 0x80U, /**<! DMA_FLEXCAN SRAM MBIST fail flag. >*/
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STCU_MBIST_FAIL_ROM_HOST = 0x100U, /**<! System ROM MBIST Fail Flag. >*/
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STCU_MBIST_FAIL_ROM_HSM = 0x200U /**<! HSM ROM MBIST Fail Flag. >*/
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}STCU_MbistFailedType;
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/** @brief Hardware SRAM initialization mode. */
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typedef enum
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{
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STCU_INIT_RAM_MODE_POR_OR_WAKEUP4STANDBY0 = 0U, /**<! After POR or wakeup from STANDBY0, Hardware SRAM initialization. >*/
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STCU_INIT_RAM_MODE_AFTER_WAKEUP4STANDBY1, /**<! After wakeup from STANDBY1, Hardware SRAM initialization. >*/
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STCU_INIT_RAM_MODE_AFTER_WAKEUP4STANDBY2, /**<! After wakeup from STANDBY2, Hardware SRAM initialization. >*/
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STCU_INIT_RAM_MODE_AFTER_WAKEUP4STANDBY3 /**<! After wakeup from STANDBY3, Hardware SRAM initialization. >*/
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}STCU_InitRamModeType;
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/** @brief The items select for Hardware SRAM Initialization. */
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typedef enum
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{
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STCU_INIT_RAM_TYPE_NONE = 0x00U, /**<! No any SRAM need to be initialized. >*/
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STCU_INIT_RAM_TYPE_SRAM = 0x01U, /**<! SRAM Select for Hardware SRAM Initialization. >*/
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STCU_INIT_RAM_TYPE_ITCM_CPU0 = 0x02U, /**<! ITCM_CPU0 SRAM Select for Hardware SRAM Initialization. >*/
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STCU_INIT_RAM_TYPE_DTCM0_CPU0 = 0x04U, /**<! DTCM0_CPU0 SRAM Select for Hardware SRAM Initialization. >*/
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STCU_INIT_RAM_TYPE_DTCM1_CPU0 = 0x08U, /**<! DTCM1_CPU0 SRAM Select for Hardware SRAM Initialization. >*/
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}STCU_InitRamType;
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/** @brief Init Ram done status flag. */
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typedef enum
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{
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STCU_INIT_RAM_DONE_TYPE_NONE = 0x00U, /**<! No any Init Ram done flag. >*/
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STCU_INIT_RAM_DONE_TYPE_SRAM = 0x01U, /**<! SRAM Initialization Done Flag. >*/
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STCU_INIT_RAM_DONE_TYPE_ITCM_CPU0 = 0x02U, /**<! ITCM_CPU0 SRAM Initialization Done Flag. >*/
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STCU_INIT_RAM_DONE_TYPE_DTCM0_CPU0 = 0x04U, /**<! DTCM0_CPU0 SRAM Initialization Done Flag. >*/
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STCU_INIT_RAM_DONE_TYPE_DTCM1_CPU0 = 0x08U, /**<! DTCM1_CPU0 SRAM Initialization Done Flag. >*/
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}STCU_InitRamDoneType;
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/** @brief Init Ram status flag. */
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typedef enum
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{
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STCU_HARDWARE_INIT_RAM_STATUS_NONE = 0U, /**<! No any SRAN Initialization flag. >*/
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STCU_HARDWARE_INIT_RAM_STATUS_DONE = 1U, /**<! Hardware SRAM Initialization Done Flag. >*/
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STCU_HARDWARE_INIT_RAM_STATUS_BUSY = 2U, /**<! Hardware SRAM Initialization Busy Flag. >*/
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STCU_HARDWARE_INIT_RAM_STATUS_ABORT = 4U /**<! Hardware SRAM Initialization Abort Flag. >*/
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}STCU_HardwareInitRamStatusType;
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/** @brief LBIST status flag. */
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typedef enum
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{
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STCU_LBIST_STATUS_NONE = 0U, /**<! No any LBIST flag. >*/
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STCU_LBIST_STATUS_DONE = 1U, /**<! LBIST Done Flag. >*/
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STCU_LBIST_STATUS_FAILED = 2U /**<! LBIST Fail Flag. >*/
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}STCU_LbistStatusType;
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/** @brief LBIST Clock Divider. */
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typedef enum
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{
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STCU_LBIST_CLK_DIVIDER_BY_2 = 1U, /**<! LBIST clock is Divided by 2. >*/
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STCU_LBIST_CLK_DIVIDER_BY_3 = 2U, /**<! LBIST clock is Divided by 3. >*/
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STCU_LBIST_CLK_DIVIDER_BY_4 = 3U, /**<! LBIST clock is Divided by 4. >*/
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}STCU_LbistClkDivType;
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/** @brief clock source of self-test. */
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typedef enum
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{
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STCU_CLK_SOURCE_FIRC = 0U, /**<! FIRC clock source. >*/
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STCU_CLK_SOURCE_PLL = 1U /**<! PLL clock source. >*/
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}STCU_ClkSourceType;
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/** @brief Self-test Port Pull Selection. */
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typedef enum
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{
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STCU_PORT_PULL_DISABLE = 0U, /**<! Disable self test port pull function. >*/
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STCU_PORT_PULL_DOWN, /**<! self test port pull down. >*/
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STCU_PORT_PULL_UP /**<! self test port pull up. >*/
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}STCU_PortPullModeType;
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/** @brief Stcu call back function type, the u32status should refer to "STCU_InterruptFlagType" */
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typedef void (*Stcu_IRQCallback)(uint32_t u32Status);
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typedef struct
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{
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bool bLbistEn; /**<! LBIST Enable >*/
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bool bMbistLPC; /**<! MBIST Low Power Control Enable >*/
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bool bMbistEn; /**<! MBIST Enable >*/
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bool bMbistFullTest; /**<! MBIST Full test Enable >*/
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bool bMbistSramInit; /**<! Enable SRAM initialization at the end of power on self-test. >*/
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bool bInterruptEn; /**<! STCU Interrupt Enable >*/
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STCU_PortPullModeType ePortPullMode; /**<! Self-test Port Pull Selection >*/
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STCU_ClkSourceType eClkSource; /**<! Select the clock source of self-test >*/
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STCU_LbistClkDivType eLbistClkDivider; /**<! LBIST Clock Divider Control. Note:A slower LBIST clock will cause less power consumption but a longer test time. >*/
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uint16_t u16MaxTime; /**<! The maximum time allowed for self-test execution.(unit : ms) >*/
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uint32_t u32MbistSel; /**<! Refer to "STCU_MbistSelType", use OR to select the MBIST range. */
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Stcu_IRQCallback pIrqCallback; /**<! Callback function for STCU IRQ >*/
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}STCU_ConfigType;
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typedef struct
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{
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STCU_InitRamModeType eInitMode; /**< RAM Initial Mode */
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uint8_t bLockAfterEn; /**< Lock STCU after RAM Initial */
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uint32_t u32InitRamType; /**< RAM Type, DTCM, ITCM, SRAM, refer to "STCU_InitRamType" and use OR to combine them */
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}STCU_InitRamConfigType;
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/**
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* \brief Init the STCU module
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*
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* \param pConfig the configuration structure
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*/
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void STCU_Init(STCU_ConfigType *pConfig);
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/**
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* \brief Trigger to start Software self test
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*
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*/
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void STCU_StartSelfTest(void);
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/**
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* \brief Check Software Trigger Self-test result
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*
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* \return refer to "STCU_SelfTestStatusType" enum.
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*/
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uint32_t STCU_CheckTriggerResult(void);
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/**
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* \brief Initial RAM with hardware
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*
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* \param pConfig the configuration structure
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*/
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void STCU_StartRamInit(STCU_InitRamConfigType *pInitCfg);
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/**
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* \brief Get status of RAM initialize action
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*
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* \return the status of ram initialize action, refer to "STCU_HardwareInitRamStatusType"
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*/
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uint32_t STCU_GetRamInitStatus(void);
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/**
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* \brief Get if the LBIST test result is Fail
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*
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* \return true means LBIST fail. false means LBIST pass.
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*/
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bool STCU_GetLbistFailResult(void);
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/**
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* \brief Get each MBIST Fail result
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*
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* \return refer to "STCU_MbistFailedType" enum.
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*/
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uint32_t STCU_GetMbistFailResult(void);
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/**
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* \brief Get each done status of SRAM initialize
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*
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* \return the done status of SRAM initialize action, refer to "STCU_InitRamDoneType"
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*/
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uint32_t STCU_GetRamInitDoneStatus(void);
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/**
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* \brief Set the LBIST Pattern value and expected misr value.
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* The two value should be load from NVR, but also can reconfigure by this API.
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* The expected misr value is calculated from pattern, so please make sure this two value is right, or the LBST would fail.
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*
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* \param u16Pattern the LBIST Pattern value
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* \param u16Pattern the LBIST expected misr value
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*/
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void STCU_LBIST_Set_Pattern_Misr(uint16_t u16Pattern, uint32_t u32ExpectedMisr);
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/**
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* \brief Get LBIST actual MISR value, the value should be read and use DFT tool to decode it, if LBIST test resault is fail.
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*
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* \return the LBIST actual MISR value
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*/
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uint32_t STCU_GetLbistAcutalMisr(void);
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/**
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* @brief STCU 0 interrupt handler
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*
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* @note This function should be called as/in STCU 0 interrupt handler
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*/
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void STCU0_IRQHandler(void);
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#endif /* end of _DRIVER_STCU_H_ */
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