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23
cm7/arm_cortex_m7_asm.h Normal file
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#ifndef _DEVICE_CM7_ARM_CORTEXM7_ASM_H_
#define _DEVICE_CM7_ARM_CORTEXM7_ASM_H_
/** \brief Reverse byte order in a word.
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION)
#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \
| ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U))
#endif
/** \brief Enter low-power standby state
* WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts.
*/
#if defined (__GNUC__)
#define STANDBY() __asm volatile ("wfi")
#else
#define STANDBY() __asm("wfi")
#endif
#endif

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cm7/cmsis_armcc.h Normal file
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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include "cmsis_iccarm.h"
/*
* GHS Compiler
*/
#elif defined ( __ghs__ )
#include "cmsis_ghs.h"
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_ghs.h
* @brief CMSIS compiler GHS header file
* @version V5.0.4
* @date 09. April 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_GHS_H
#define __CMSIS_GHS_H
/* GHS MULTI intrinsic functions (e.g. __enable_interrupt()) */
#include <arm_ghs.h>
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __RESTRICT
#define __RESTRICT restrict
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __DMB
#define __DMB() __ASM("dmb")
#endif
#ifndef __DSB
#define __DSB() __ASM("dsb")
#endif
#ifndef __ISB
#define __ISB() __ASM("isb")
#endif
#ifndef __WFI
#define __WFI() __ASM("wfi")
#endif
#ifndef __WFE
#define __WFE() __ASM("wfe")
#endif
#ifndef __enable_irq
#define __enable_irq() __ASM("cpsie i")
#endif
#ifndef __disable_irq
#define __disable_irq() __ASM("cpsid i")
#endif
#ifndef __get_FPSCR
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
return __VMRS(__VFP_FPSCR);;
#else
return(0U);
#endif
}
#endif
#endif /* __CMSIS_GHS_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.2
* @date 25. May 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/**
* @file compiler.h
* @author Flagchip
* @brief compiler define
* @version 0.1.1
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
#ifndef DEVICE_COMPILER_H_
#define DEVICE_COMPILER_H_
#ifndef __IO
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
#endif
#if defined (__GNUC__)
#define INLINE __attribute__((always_inline)) inline
#define LOCAL_INLINE __attribute__((always_inline)) static inline
#else
#define INLINE inline
#define LOCAL_INLINE static inline
#endif
#if (defined(__ICCARM__))
#define STRINGIZE(x) #x
#define ALIGN(n) _Pragma(STRINGIZE(data_alignment=(n)))
#define PACKED __packed
#endif
#if (defined(__GNUC__))
#define ALIGN(n) __attribute__ ((aligned (n)))
#define PACKED __packed
#endif
#if (defined(__ghs__))
#define INLINE inline
#define LOCAL_INLINE static inline
#define ALIGN(n) __attribute__((aligned(n)))
#define PCAKED __attribute__((packed))
#endif
#endif /* DEVICE_COMPILER_H_ */

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/**
* @file device_header.h
* @author Flagchip
* @brief include all peripheral register files
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
#ifndef DEVICE_HEADER_H
#define DEVICE_HEADER_H
#define __FPU_PRESENT 1
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
#define __ICACHE_PRESENT 1U
#define __DCACHE_PRESENT 1U
#include <stdarg.h>
#include "typedef.h"
#include "v_def.h"
#include "fcmath.h"
#include "fcfunc.h"
#include "cmsis_compiler.h"
#include "core_cm7_regs.h"
#include "arm_cortex_m7_asm.h"
#include "mpu_armv7.h"
#include "fc7240_acc_regs.h"
#include "fc7240_adc_regs.h"
#include "fc7240_aontimer_regs.h"
#include "fc7240_cmp_regs.h"
#include "fc7240_cmu_regs.h"
#include "fc7240_cordic_regs.h"
#include "fc7240_cpm_regs.h"
#include "fc7240_crc_regs.h"
#include "fc7240_csc0_regs.h"
#include "fc7240_dmamux_regs.h"
#include "fc7240_dma_regs.h"
#include "fc7240_eim_regs.h"
#include "fc7240_erm_regs.h"
#include "fc7240_fciic_regs.h"
#include "fc7240_fcpit_regs.h"
#include "fc7240_fcsmu_regs.h"
#include "fc7240_fcspi_regs.h"
#include "fc7240_fcuart_regs.h"
#include "fc7240_flexcan_regs.h"
#include "fc7240_fmc_regs.h"
#include "fc7240_freqm_regs.h"
#include "fc7240_ftu_regs.h"
#include "fc7240_gpio_regs.h"
#include "fc7240_intm_regs.h"
#include "fc7240_ism_regs.h"
#include "fc7240_lu_regs.h"
#include "fc7240_mam_regs.h"
#include "fc7240_mb_regs.h"
#include "fc7240_msc_regs.h"
#include "fc7240_ahb_overlay_regs.h"
#include "fc7240_pcc_regs.h"
#include "fc7240_pmc_regs.h"
#include "fc7240_port_regs.h"
#include "fc7240_ptimer_regs.h"
#include "fc7240_rgm_regs.h"
#include "fc7240_rtc_regs.h"
#include "fc7240_scg_regs.h"
#include "fc7240_scm_regs.h"
#include "fc7240_stcu_regs.h"
#include "fc7240_sec_regs.h"
#include "fc7240_sent_regs.h"
#include "fc7240_smc_regs.h"
#include "fc7240_stcu_regs.h"
#include "fc7240_tmu_regs.h"
#include "fc7240_tpu_e_regs.h"
#include "fc7240_tpu_h_regs.h"
#include "fc7240_trgsel_regs.h"
#include "fc7240_tstmp_regs.h"
#include "fc7240_wdog_regs.h"
#include "fc7240_wku_regs.h"
#define PFLASH_START 0x01000000U
#define PFLASH_END 0x011FFFFFU
#define SRAM_START 0x21000000U
#define SRAM_END 0x21017FFFU
#define INLINE_FLASHDRIVER_RAM STD_OFF
#define WDOG0_RECONF_LOCK_DELAY_US 100U /* 100us */
#if (defined(__ICCARM__))
#define PROCESS_UNUSED_VAR(var) (var) = (var);
#elif defined __GNUC__
#define PROCESS_UNUSED_VAR(var) (void)(var);
#elif defined __ghs__
#define PROCESS_UNUSED_VAR(var) (void)(var);
#endif
#define FC4150F512 0x01U
#define FC4150F2M 0x02U
#define FC7300HSM 0x03U
#define FC7300CM7 0x04U
#define FC7240HOST 0x05U
#define FC7240FLEXCORE 0x06U
#define DEVICE_TYPE FC7240HOST
#endif /* DEVICE_HEADER_H */
/*******************************************************************************
* EOF
******************************************************************************/

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import os
import re
import time
def Add_Include(filePath,name):
fp = open(filePath)
lines = []
for line in fp:
lines.append(line)
fp.close()
fp.close()
del lines[:2] #delete previous define DRIVER_xxx_H
lines.insert(0, r'#ifndef _'+name.upper()+'_H_') #add in LINE+1
lines.insert(1, r'#define _'+name.upper()+'_H_') #add in LINE+1
lines.insert(2, r'#ifdef __cplusplus') #add in LINE+1
lines.insert(3, r' extern "C" {') #add in LINE+1
lines.insert(4, r'#endif') #add in LINE+1
lines.insert(len(lines)-1, r'#ifdef __cplusplus') #add in LINE+1
lines.insert(len(lines)-1, r'}') #add in LINE+1
lines.insert(len(lines)-1, r'#endif') #add in LINE+1
s = '\n'.join(lines)
fp = open(filePath, 'w')
fp.write(s)
fp.close()
if __name__=='__main__':
path = os.getcwd()
for filename in os.listdir(path):
result1 = os.path.splitext(filename)
#print(filename+', '+result1[0]+'\n')
if result1[1] == '.h' :
oldname=filename
print(filename[7:-9])
#time.sleep()
newname='fc7240_'+filename[7:-9].lower()+'_regs.h'
os.rename(oldname,newname);
result1 = os.path.splitext(newname)
Add_Include(newname,result1[0])
#print(newname+'\n')

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#ifndef _FC7240_ACC_NU_Tztufn3_REGS_H_
#define _FC7240_ACC_NU_Tztufn3_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- ACC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ACC_Peripheral_Access_Layer ACC Peripheral Access Layer
* @{
*/
/** ACC - Size of Registers Arrays */
/** ACC - Register Layout Typedef */
#define ACC_IEBR_COUNT 2
#define ACC_DEBR_COUNT 2
typedef struct {
uint8_t RESERVED_0[20];
__IO uint32_t CCR ; /* Configuration and Control Register, offset: 0x14 */
uint8_t RESERVED_1[96];
__I uint32_t CLIDR ; /* Cache Level ID Register, offset: 0x78 */
__I uint32_t CTR ; /* Cache Type Register, offset: 0x7C */
__I uint32_t CCSIDR ; /* Cache Size ID Register, offset: 0x80 */
__IO uint32_t CSSELR ; /* Cache Size Selection Register, offset: 0x84 */
uint8_t RESERVED_2[456];
__O uint32_t ICIALLU ; /* I-cache Invalidate All to PoU Register, offset: 0x250 */
uint8_t RESERVED_3[4];
__O uint32_t ICIMVAU ; /* I-cache Invalidate by MVA to PoU Register, offset: 0x258 */
__O uint32_t DCIMVAC ; /* D-cache Invalidate by MVA to PoC Register, offset: 0x25C */
__O uint32_t DCISW ; /* D-cache Invalidate by Set-way Register, offset: 0x260 */
__O uint32_t DCCMVAU ; /* D-cache Clean by MVA to PoU Register, offset: 0x264 */
__O uint32_t DCCMVAC ; /* D-cache Clean by MVA to PoC Register, offset: 0x268 */
__O uint32_t DCCSW ; /* D-cache Clean by Set-way Register, offset: 0x26C */
__O uint32_t DCCIMVAC ; /* D-cache Clean and Invalidate by MVA to PoC Register, offset: 0x270 */
__O uint32_t DCCISW ; /* D-cache Clean and Invalidate by Set-way Register, offset: 0x274 */
uint8_t RESERVED_4[36];
__IO uint32_t CACR ; /* L1 Cache Control Register, offset: 0x29C */
uint8_t RESERVED_5[16];
__IO uint32_t IEBR[ACC_IEBR_COUNT] ; /* Instruction Error Bank Register, offset: 0x2b0 */
__IO uint32_t DEBR[ACC_DEBR_COUNT] ; /* Data Error Bank Register, offset: 0x2b8 */
} ACC_Type, *ACC_MemMapPtr;
/** Number of instances of the ACC module. */
#define ACC_INSTANCE_COUNT (1u)
/* ACC - Peripheral instance base addresses */
/** Peripheral ACC base address */
#define ACC_BASE (0xE000ED00u)
/** Peripheral ACC base pointer */
#define ACC ((ACC_Type *)ACC_BASE)
/** Array initializer of ACC peripheral base addresses */
#define ACC_BASE_ADDRS {ACC_BASE}
/** Array initializer of ACC peripheral base pointers */
#define ACC_BASE_PTRS {ACC}
// need fill by yourself
///** Number of interrupt vector arrays for the ACC module. */
//#define ACC_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the ACC module. */
//#define ACC_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the ACC peripheral type */
//#define ACC_IRQS {ACC_IRQn}
/* ----------------------------------------------------------------------------
-- ACC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ACC_Register_Masks ACC Register Masks
* @{
*/
/* CCR Bit Fields */
#define ACC_CCR_BP_MASK 0x40000u
#define ACC_CCR_BP_SHIFT 18u
#define ACC_CCR_BP_WIDTH 1u
#define ACC_CCR_BP(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_BP_SHIFT))&ACC_CCR_BP_MASK)
#define ACC_CCR_IC_MASK 0x20000u
#define ACC_CCR_IC_SHIFT 17u
#define ACC_CCR_IC_WIDTH 1u
#define ACC_CCR_IC(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_IC_SHIFT))&ACC_CCR_IC_MASK)
#define ACC_CCR_DC_MASK 0x10000u
#define ACC_CCR_DC_SHIFT 16u
#define ACC_CCR_DC_WIDTH 1u
#define ACC_CCR_DC(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_DC_SHIFT))&ACC_CCR_DC_MASK)
#define ACC_CCR_STKALIGN_MASK 0x200u
#define ACC_CCR_STKALIGN_SHIFT 9u
#define ACC_CCR_STKALIGN_WIDTH 1u
#define ACC_CCR_STKALIGN(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_STKALIGN_SHIFT))&ACC_CCR_STKALIGN_MASK)
#define ACC_CCR_BFHFNMIGN_MASK 0x100u
#define ACC_CCR_BFHFNMIGN_SHIFT 8u
#define ACC_CCR_BFHFNMIGN_WIDTH 1u
#define ACC_CCR_BFHFNMIGN(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_BFHFNMIGN_SHIFT))&ACC_CCR_BFHFNMIGN_MASK)
#define ACC_CCR_DIV_0_TRP_MASK 0x10u
#define ACC_CCR_DIV_0_TRP_SHIFT 4u
#define ACC_CCR_DIV_0_TRP_WIDTH 1u
#define ACC_CCR_DIV_0_TRP(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_DIV_0_TRP_SHIFT))&ACC_CCR_DIV_0_TRP_MASK)
#define ACC_CCR_UNALIGN_TRP_MASK 0x8u
#define ACC_CCR_UNALIGN_TRP_SHIFT 3u
#define ACC_CCR_UNALIGN_TRP_WIDTH 1u
#define ACC_CCR_UNALIGN_TRP(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_UNALIGN_TRP_SHIFT))&ACC_CCR_UNALIGN_TRP_MASK)
#define ACC_CCR_USERSETMPEND_MASK 0x2u
#define ACC_CCR_USERSETMPEND_SHIFT 1u
#define ACC_CCR_USERSETMPEND_WIDTH 1u
#define ACC_CCR_USERSETMPEND(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_USERSETMPEND_SHIFT))&ACC_CCR_USERSETMPEND_MASK)
#define ACC_CCR_NONBASETHRDENA_MASK 0x1u
#define ACC_CCR_NONBASETHRDENA_SHIFT 0u
#define ACC_CCR_NONBASETHRDENA_WIDTH 1u
#define ACC_CCR_NONBASETHRDENA(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_NONBASETHRDENA_SHIFT))&ACC_CCR_NONBASETHRDENA_MASK)
/* CCR Reg Mask */
#define ACC_CCR_MASK 0x0007031Bu
/* CLIDR Bit Fields */
#define ACC_CLIDR_LOUU_MASK 0x38000000u
#define ACC_CLIDR_LOUU_SHIFT 27u
#define ACC_CLIDR_LOUU_WIDTH 3u
#define ACC_CLIDR_LOUU(x) (((uint32_t)(((uint32_t)(x))<<ACC_CLIDR_LOUU_SHIFT))&ACC_CLIDR_LOUU_MASK)
#define ACC_CLIDR_LOC_MASK 0x7000000u
#define ACC_CLIDR_LOC_SHIFT 24u
#define ACC_CLIDR_LOC_WIDTH 3u
#define ACC_CLIDR_LOC(x) (((uint32_t)(((uint32_t)(x))<<ACC_CLIDR_LOC_SHIFT))&ACC_CLIDR_LOC_MASK)
#define ACC_CLIDR_LOCT_MASK 0x7u
#define ACC_CLIDR_LOCT_SHIFT 0u
#define ACC_CLIDR_LOCT_WIDTH 3u
#define ACC_CLIDR_LOCT(x) (((uint32_t)(((uint32_t)(x))<<ACC_CLIDR_LOCT_SHIFT))&ACC_CLIDR_LOCT_MASK)
/* CLIDR Reg Mask */
#define ACC_CLIDR_MASK 0x3F000007u
/* CTR Bit Fields */
#define ACC_CTR_FMT_MASK 0xE0000000u
#define ACC_CTR_FMT_SHIFT 29u
#define ACC_CTR_FMT_WIDTH 3u
#define ACC_CTR_FMT(x) (((uint32_t)(((uint32_t)(x))<<ACC_CTR_FMT_SHIFT))&ACC_CTR_FMT_MASK)
#define ACC_CTR_CWG_MASK 0xF000000u
#define ACC_CTR_CWG_SHIFT 24u
#define ACC_CTR_CWG_WIDTH 4u
#define ACC_CTR_CWG(x) (((uint32_t)(((uint32_t)(x))<<ACC_CTR_CWG_SHIFT))&ACC_CTR_CWG_MASK)
#define ACC_CTR_ERG_MASK 0xF00000u
#define ACC_CTR_ERG_SHIFT 20u
#define ACC_CTR_ERG_WIDTH 4u
#define ACC_CTR_ERG(x) (((uint32_t)(((uint32_t)(x))<<ACC_CTR_ERG_SHIFT))&ACC_CTR_ERG_MASK)
#define ACC_CTR_DMINLINE_MASK 0xF0000u
#define ACC_CTR_DMINLINE_SHIFT 16u
#define ACC_CTR_DMINLINE_WIDTH 4u
#define ACC_CTR_DMINLINE(x) (((uint32_t)(((uint32_t)(x))<<ACC_CTR_DMINLINE_SHIFT))&ACC_CTR_DMINLINE_MASK)
#define ACC_CTR_IMINLINE_MASK 0xFu
#define ACC_CTR_IMINLINE_SHIFT 0u
#define ACC_CTR_IMINLINE_WIDTH 4u
#define ACC_CTR_IMINLINE(x) (((uint32_t)(((uint32_t)(x))<<ACC_CTR_IMINLINE_SHIFT))&ACC_CTR_IMINLINE_MASK)
/* CTR Reg Mask */
#define ACC_CTR_MASK 0xEFFF000Fu
/* CCSIDR Bit Fields */
#define ACC_CCSIDR_WT_MASK 0x80000000u
#define ACC_CCSIDR_WT_SHIFT 31u
#define ACC_CCSIDR_WT_WIDTH 1u
#define ACC_CCSIDR_WT(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_WT_SHIFT))&ACC_CCSIDR_WT_MASK)
#define ACC_CCSIDR_WB_MASK 0x40000000u
#define ACC_CCSIDR_WB_SHIFT 30u
#define ACC_CCSIDR_WB_WIDTH 1u
#define ACC_CCSIDR_WB(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_WB_SHIFT))&ACC_CCSIDR_WB_MASK)
#define ACC_CCSIDR_RA_MASK 0x20000000u
#define ACC_CCSIDR_RA_SHIFT 29u
#define ACC_CCSIDR_RA_WIDTH 1u
#define ACC_CCSIDR_RA(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_RA_SHIFT))&ACC_CCSIDR_RA_MASK)
#define ACC_CCSIDR_WA_MASK 0x10000000u
#define ACC_CCSIDR_WA_SHIFT 28u
#define ACC_CCSIDR_WA_WIDTH 1u
#define ACC_CCSIDR_WA(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_WA_SHIFT))&ACC_CCSIDR_WA_MASK)
#define ACC_CCSIDR_NUMSETS_MASK 0xFFFE000u
#define ACC_CCSIDR_NUMSETS_SHIFT 13u
#define ACC_CCSIDR_NUMSETS_WIDTH 15u
#define ACC_CCSIDR_NUMSETS(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_NUMSETS_SHIFT))&ACC_CCSIDR_NUMSETS_MASK)
#define ACC_CCSIDR_ASSOCIATIVITY_MASK 0x1FF8u
#define ACC_CCSIDR_ASSOCIATIVITY_SHIFT 3u
#define ACC_CCSIDR_ASSOCIATIVITY_WIDTH 10u
#define ACC_CCSIDR_ASSOCIATIVITY(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_ASSOCIATIVITY_SHIFT))&ACC_CCSIDR_ASSOCIATIVITY_MASK)
#define ACC_CCSIDR_LINESIZE_MASK 0x7u
#define ACC_CCSIDR_LINESIZE_SHIFT 0u
#define ACC_CCSIDR_LINESIZE_WIDTH 3u
#define ACC_CCSIDR_LINESIZE(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_LINESIZE_SHIFT))&ACC_CCSIDR_LINESIZE_MASK)
/* CCSIDR Reg Mask */
#define ACC_CCSIDR_MASK 0xFFFFFFFFu
/* CSSELR Bit Fields */
#define ACC_CSSELR_LEVEL_MASK 0xEu
#define ACC_CSSELR_LEVEL_SHIFT 1u
#define ACC_CSSELR_LEVEL_WIDTH 3u
#define ACC_CSSELR_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<ACC_CSSELR_LEVEL_SHIFT))&ACC_CSSELR_LEVEL_MASK)
#define ACC_CSSELR_IND_MASK 0x1u
#define ACC_CSSELR_IND_SHIFT 0u
#define ACC_CSSELR_IND_WIDTH 1u
#define ACC_CSSELR_IND(x) (((uint32_t)(((uint32_t)(x))<<ACC_CSSELR_IND_SHIFT))&ACC_CSSELR_IND_MASK)
/* CSSELR Reg Mask */
#define ACC_CSSELR_MASK 0x0000000Fu
/* ICIALLU Bit Fields */
#define ACC_ICIALLU_ICIALLU_MASK 0xFFFFFFFFu
#define ACC_ICIALLU_ICIALLU_SHIFT 0u
#define ACC_ICIALLU_ICIALLU_WIDTH 32u
#define ACC_ICIALLU_ICIALLU(x) (((uint32_t)(((uint32_t)(x))<<ACC_ICIALLU_ICIALLU_SHIFT))&ACC_ICIALLU_ICIALLU_MASK)
/* ICIALLU Reg Mask */
#define ACC_ICIALLU_MASK 0xFFFFFFFFu
/* ICIMVAU Bit Fields */
#define ACC_ICIMVAU_MVA_MASK 0xFFFFFFE0u
#define ACC_ICIMVAU_MVA_SHIFT 5u
#define ACC_ICIMVAU_MVA_WIDTH 27u
#define ACC_ICIMVAU_MVA(x) (((uint32_t)(((uint32_t)(x))<<ACC_ICIMVAU_MVA_SHIFT))&ACC_ICIMVAU_MVA_MASK)
/* ICIMVAU Reg Mask */
#define ACC_ICIMVAU_MASK 0xFFFFFFE0u
/* DCIMVAC Bit Fields */
#define ACC_DCIMVAC_MVA_MASK 0xFFFFFFE0u
#define ACC_DCIMVAC_MVA_SHIFT 5u
#define ACC_DCIMVAC_MVA_WIDTH 27u
#define ACC_DCIMVAC_MVA(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCIMVAC_MVA_SHIFT))&ACC_DCIMVAC_MVA_MASK)
/* DCIMVAC Reg Mask */
#define ACC_DCIMVAC_MASK 0xFFFFFFE0u
/* DCISW Bit Fields */
#define ACC_DCISW_WAY_MASK 0xC0000000u
#define ACC_DCISW_WAY_SHIFT 30u
#define ACC_DCISW_WAY_WIDTH 2u
#define ACC_DCISW_WAY(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCISW_WAY_SHIFT))&ACC_DCISW_WAY_MASK)
#define ACC_DCISW_SET_MASK 0x3FE0u
#define ACC_DCISW_SET_SHIFT 5u
#define ACC_DCISW_SET_WIDTH 9u
#define ACC_DCISW_SET(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCISW_SET_SHIFT))&ACC_DCISW_SET_MASK)
/* DCISW Reg Mask */
#define ACC_DCISW_MASK 0xC0003FE0u
/* DCCMVAU Bit Fields */
#define ACC_DCCMVAU_MVA_MASK 0xFFFFFFE0u
#define ACC_DCCMVAU_MVA_SHIFT 5u
#define ACC_DCCMVAU_MVA_WIDTH 27u
#define ACC_DCCMVAU_MVA(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCMVAU_MVA_SHIFT))&ACC_DCCMVAU_MVA_MASK)
/* DCCMVAU Reg Mask */
#define ACC_DCCMVAU_MASK 0xFFFFFFE0u
/* DCCMVAC Bit Fields */
#define ACC_DCCMVAC_MVA_MASK 0xFFFFFFE0u
#define ACC_DCCMVAC_MVA_SHIFT 5u
#define ACC_DCCMVAC_MVA_WIDTH 27u
#define ACC_DCCMVAC_MVA(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCMVAC_MVA_SHIFT))&ACC_DCCMVAC_MVA_MASK)
/* DCCMVAC Reg Mask */
#define ACC_DCCMVAC_MASK 0xFFFFFFE0u
/* DCCSW Bit Fields */
#define ACC_DCCSW_WAY_MASK 0xC0000000u
#define ACC_DCCSW_WAY_SHIFT 30u
#define ACC_DCCSW_WAY_WIDTH 2u
#define ACC_DCCSW_WAY(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCSW_WAY_SHIFT))&ACC_DCCSW_WAY_MASK)
#define ACC_DCCSW_SET_MASK 0x3FE0u
#define ACC_DCCSW_SET_SHIFT 5u
#define ACC_DCCSW_SET_WIDTH 9u
#define ACC_DCCSW_SET(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCSW_SET_SHIFT))&ACC_DCCSW_SET_MASK)
/* DCCSW Reg Mask */
#define ACC_DCCSW_MASK 0xC0003FE0u
/* DCCIMVAC Bit Fields */
#define ACC_DCCIMVAC_MVA_MASK 0xFFFFFFE0u
#define ACC_DCCIMVAC_MVA_SHIFT 5u
#define ACC_DCCIMVAC_MVA_WIDTH 27u
#define ACC_DCCIMVAC_MVA(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCIMVAC_MVA_SHIFT))&ACC_DCCIMVAC_MVA_MASK)
/* DCCIMVAC Reg Mask */
#define ACC_DCCIMVAC_MASK 0xFFFFFFE0u
/* DCCISW Bit Fields */
#define ACC_DCCISW_WAY_MASK 0xC0000000u
#define ACC_DCCISW_WAY_SHIFT 30u
#define ACC_DCCISW_WAY_WIDTH 2u
#define ACC_DCCISW_WAY(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCISW_WAY_SHIFT))&ACC_DCCISW_WAY_MASK)
#define ACC_DCCISW_SET_MASK 0x3FE0u
#define ACC_DCCISW_SET_SHIFT 5u
#define ACC_DCCISW_SET_WIDTH 9u
#define ACC_DCCISW_SET(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCISW_SET_SHIFT))&ACC_DCCISW_SET_MASK)
/* DCCISW Reg Mask */
#define ACC_DCCISW_MASK 0xC0003FE0u
/* CACR Bit Fields */
#define ACC_CACR_FORCEWT_MASK 0x4u
#define ACC_CACR_FORCEWT_SHIFT 2u
#define ACC_CACR_FORCEWT_WIDTH 1u
#define ACC_CACR_FORCEWT(x) (((uint32_t)(((uint32_t)(x))<<ACC_CACR_FORCEWT_SHIFT))&ACC_CACR_FORCEWT_MASK)
#define ACC_CACR_ECCDIS_MASK 0x2u
#define ACC_CACR_ECCDIS_SHIFT 1u
#define ACC_CACR_ECCDIS_WIDTH 1u
#define ACC_CACR_ECCDIS(x) (((uint32_t)(((uint32_t)(x))<<ACC_CACR_ECCDIS_SHIFT))&ACC_CACR_ECCDIS_MASK)
#define ACC_CACR_SIWT_MASK 0x1u
#define ACC_CACR_SIWT_SHIFT 0u
#define ACC_CACR_SIWT_WIDTH 1u
#define ACC_CACR_SIWT(x) (((uint32_t)(((uint32_t)(x))<<ACC_CACR_SIWT_SHIFT))&ACC_CACR_SIWT_MASK)
/* CACR Reg Mask */
#define ACC_CACR_MASK 0x00000007u
/* IEBR Bit Fields */
#define ACC_IEBR_TOE_MASK 0x20000u
#define ACC_IEBR_TOE_SHIFT 17u
#define ACC_IEBR_TOE_WIDTH 1u
#define ACC_IEBR_TOE(x) (((uint32_t)(((uint32_t)(x))<<ACC_IEBR_TOE_SHIFT))&ACC_IEBR_TOE_MASK)
#define ACC_IEBR_RB_MASK 0x10000u
#define ACC_IEBR_RB_SHIFT 16u
#define ACC_IEBR_RB_WIDTH 1u
#define ACC_IEBR_RB(x) (((uint32_t)(((uint32_t)(x))<<ACC_IEBR_RB_SHIFT))&ACC_IEBR_RB_MASK)
#define ACC_IEBR_RL_MASK 0xFFFCu
#define ACC_IEBR_RL_SHIFT 2u
#define ACC_IEBR_RL_WIDTH 14u
#define ACC_IEBR_RL(x) (((uint32_t)(((uint32_t)(x))<<ACC_IEBR_RL_SHIFT))&ACC_IEBR_RL_MASK)
#define ACC_IEBR_LOCKED_MASK 0x2u
#define ACC_IEBR_LOCKED_SHIFT 1u
#define ACC_IEBR_LOCKED_WIDTH 1u
#define ACC_IEBR_LOCKED(x) (((uint32_t)(((uint32_t)(x))<<ACC_IEBR_LOCKED_SHIFT))&ACC_IEBR_LOCKED_MASK)
#define ACC_IEBR_VALID_MASK 0x1u
#define ACC_IEBR_VALID_SHIFT 0u
#define ACC_IEBR_VALID_WIDTH 1u
#define ACC_IEBR_VALID(x) (((uint32_t)(((uint32_t)(x))<<ACC_IEBR_VALID_SHIFT))&ACC_IEBR_VALID_MASK)
/* IEBR0 Reg Mask */
#define ACC_IEBR_MASK 0x0003FFFFu
/* DEBR Bit Fields */
#define ACC_DEBR_TOE_MASK 0x20000u
#define ACC_DEBR_TOE_SHIFT 17u
#define ACC_DEBR_TOE_WIDTH 1u
#define ACC_DEBR_TOE(x) (((uint32_t)(((uint32_t)(x))<<ACC_DEBR_TOE_SHIFT))&ACC_DEBR_TOE_MASK)
#define ACC_DEBR_RB_MASK 0x10000u
#define ACC_DEBR_RB_SHIFT 16u
#define ACC_DEBR_RB_WIDTH 1u
#define ACC_DEBR_RB(x) (((uint32_t)(((uint32_t)(x))<<ACC_DEBR_RB_SHIFT))&ACC_DEBR_RB_MASK)
#define ACC_DEBR_RL_MASK 0xFFFCu
#define ACC_DEBR_RL_SHIFT 2u
#define ACC_DEBR_RL_WIDTH 14u
#define ACC_DEBR_RL(x) (((uint32_t)(((uint32_t)(x))<<ACC_DEBR_RL_SHIFT))&ACC_DEBR_RL_MASK)
#define ACC_DEBR_LOCKED_MASK 0x2u
#define ACC_DEBR_LOCKED_SHIFT 1u
#define ACC_DEBR_LOCKED_WIDTH 1u
#define ACC_DEBR_LOCKED(x) (((uint32_t)(((uint32_t)(x))<<ACC_DEBR_LOCKED_SHIFT))&ACC_DEBR_LOCKED_MASK)
#define ACC_DEBR_VALID_MASK 0x1u
#define ACC_DEBR_VALID_SHIFT 0u
#define ACC_DEBR_VALID_WIDTH 1u
#define ACC_DEBR_VALID(x) (((uint32_t)(((uint32_t)(x))<<ACC_DEBR_VALID_SHIFT))&ACC_DEBR_VALID_MASK)
/* DEBR0 Reg Mask */
#define ACC_DEBR_MASK 0x0003FFFFu
/*!
* @}
*/ /* end of group ACC_Register_Masks */
/*!
* @}
*/ /* end of group ACC_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7240_adc_regs.h Normal file
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@ -0,0 +1,831 @@
#ifndef _FC7240_ADC_NU_Tztufn20_REGS_H_
#define _FC7240_ADC_NU_Tztufn20_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- ADC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
* @{
*/
/** ADC - Size of Registers Arrays */
/** ADC - Register Layout Typedef */
#define ADC_SGCSR_COUNT 4
#define ADC_SC_COUNT 32
#define ADC_RESULT_COUNT 32
#define ADC_SAMPLE_TIME_OPTION_CNT 4U
#define ADC_SEQUENCE_GROUP_CNT 4U
typedef struct {
__IO uint32_t INT_STATUS ; /* Interrupt Status Register, offset: 0x0 */
__IO uint32_t INT_ENABLE ; /* Interrupt Enable Register, offset: 0x4 */
__IO uint32_t CONTROL ; /* Control Register, offset: 0x8 */
__IO uint32_t CFG1 ; /* Configuration1 Register, offset: 0xC */
__IO uint32_t CFG2 ; /* Configuration2 Register, offset: 0x10 */
__IO uint32_t SMPR ; /* Sampling Rate Register, offset: 0x14 */
__IO uint32_t CMP_CTRL ; /* Compare Control Register, offset: 0x18 */
__IO uint32_t CMP_TR ; /* Compare Threshold Register, offset: 0x1C */
uint8_t RESERVED_0[8];
__IO uint32_t SGCSR[ADC_SGCSR_COUNT] ; /* Sequence Group Control and Status Register, offset: 0x28 */
uint8_t RESERVED_1[12];
__IO uint32_t CAL ; /* Calibration Register, offset: 0x44 */
uint8_t RESERVED_2[4];
__IO uint32_t FIFO_DATA ; /* FIFO Data Register, offset: 0x4C */
__IO uint32_t SC[ADC_SC_COUNT] ; /* Sequence Configuration Register, offset: 0x50 */
__IO uint32_t RESULT[ADC_RESULT_COUNT] ; /* Result Register, offset: 0xd0 */
} ADC_Type, *ADC_MemMapPtr;
/** Number of instances of the ADC module. */
#define ADC_INSTANCE_COUNT (2u)
/* ADC - Peripheral instance base addresses */
/** Peripheral ADC0 base address */
#define ADC0_BASE (0x4003b000u)
/** Peripheral ADC0 base pointer */
#define ADC0 ((ADC_Type *)ADC0_BASE)
/** Peripheral ADC1 base address */
#define ADC1_BASE (0x4003c000u)
/** Peripheral ADC1 base pointer */
#define ADC1 ((ADC_Type *)ADC1_BASE)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS {ADC0_BASE, ADC1_BASE}
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS {ADC0, ADC1}
// need fill by yourself
///** Number of interrupt vector arrays for the ADC module. */
//#define ADC_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the ADC module. */
//#define ADC_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the ADC peripheral type */
//#define ADC_IRQS {ADC0_IRQn, ADC1_IRQn}
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/* INT_STATUS Bit Fields */
#define ADC_INT_STATUS_TRGERR_MASK 0xF000000u
#define ADC_INT_STATUS_TRGERR_SHIFT 24u
#define ADC_INT_STATUS_TRGERR_WIDTH 4u
#define ADC_INT_STATUS_TRGERR(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_TRGERR_SHIFT))&ADC_INT_STATUS_TRGERR_MASK)
#define ADC_INT_STATUS_TRG_STATUS_MASK 0xF0000u
#define ADC_INT_STATUS_TRG_STATUS_SHIFT 16u
#define ADC_INT_STATUS_TRG_STATUS_WIDTH 4u
#define ADC_INT_STATUS_TRG_STATUS(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_TRG_STATUS_SHIFT))&ADC_INT_STATUS_TRG_STATUS_MASK)
#define ADC_INT_STATUS_TRG_PRO_NUM_MASK 0x6000u
#define ADC_INT_STATUS_TRG_PRO_NUM_SHIFT 13u
#define ADC_INT_STATUS_TRG_PRO_NUM_WIDTH 2u
#define ADC_INT_STATUS_TRG_PRO_NUM(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_TRG_PRO_NUM_SHIFT))&ADC_INT_STATUS_TRG_PRO_NUM_MASK)
#define ADC_INT_STATUS_FIFO_RDY_MASK 0x100u
#define ADC_INT_STATUS_FIFO_RDY_SHIFT 8u
#define ADC_INT_STATUS_FIFO_RDY_WIDTH 1u
#define ADC_INT_STATUS_FIFO_RDY(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_FIFO_RDY_SHIFT))&ADC_INT_STATUS_FIFO_RDY_MASK)
#define ADC_INT_STATUS_ACMP_MASK 0x80u
#define ADC_INT_STATUS_ACMP_SHIFT 7u
#define ADC_INT_STATUS_ACMP_WIDTH 1u
#define ADC_INT_STATUS_ACMP(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_ACMP_SHIFT))&ADC_INT_STATUS_ACMP_MASK)
#define ADC_INT_STATUS_EMPTY_MASK 0x40u
#define ADC_INT_STATUS_EMPTY_SHIFT 6u
#define ADC_INT_STATUS_EMPTY_WIDTH 1u
#define ADC_INT_STATUS_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_EMPTY_SHIFT))&ADC_INT_STATUS_EMPTY_MASK)
#define ADC_INT_STATUS_FULL_MASK 0x20u
#define ADC_INT_STATUS_FULL_SHIFT 5u
#define ADC_INT_STATUS_FULL_WIDTH 1u
#define ADC_INT_STATUS_FULL(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_FULL_SHIFT))&ADC_INT_STATUS_FULL_MASK)
#define ADC_INT_STATUS_OVR_MASK 0x10u
#define ADC_INT_STATUS_OVR_SHIFT 4u
#define ADC_INT_STATUS_OVR_WIDTH 1u
#define ADC_INT_STATUS_OVR(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_OVR_SHIFT))&ADC_INT_STATUS_OVR_MASK)
#define ADC_INT_STATUS_EOSEQ_MASK 0x8u
#define ADC_INT_STATUS_EOSEQ_SHIFT 3u
#define ADC_INT_STATUS_EOSEQ_WIDTH 1u
#define ADC_INT_STATUS_EOSEQ(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_EOSEQ_SHIFT))&ADC_INT_STATUS_EOSEQ_MASK)
#define ADC_INT_STATUS_EOC_MASK 0x4u
#define ADC_INT_STATUS_EOC_SHIFT 2u
#define ADC_INT_STATUS_EOC_WIDTH 1u
#define ADC_INT_STATUS_EOC(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_EOC_SHIFT))&ADC_INT_STATUS_EOC_MASK)
#define ADC_INT_STATUS_EOSMP_MASK 0x2u
#define ADC_INT_STATUS_EOSMP_SHIFT 1u
#define ADC_INT_STATUS_EOSMP_WIDTH 1u
#define ADC_INT_STATUS_EOSMP(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_EOSMP_SHIFT))&ADC_INT_STATUS_EOSMP_MASK)
#define ADC_INT_STATUS_ADRDY_MASK 0x1u
#define ADC_INT_STATUS_ADRDY_SHIFT 0u
#define ADC_INT_STATUS_ADRDY_WIDTH 1u
#define ADC_INT_STATUS_ADRDY(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_ADRDY_SHIFT))&ADC_INT_STATUS_ADRDY_MASK)
/* INT_STATUS Reg Mask */
#define ADC_INT_STATUS_MASK 0x0F0F61FFu
/* INT_ENABLE Bit Fields */
#define ADC_INT_ENABLE_TRGERR_IE_MASK 0x400u
#define ADC_INT_ENABLE_TRGERR_IE_SHIFT 10u
#define ADC_INT_ENABLE_TRGERR_IE_WIDTH 1u
#define ADC_INT_ENABLE_TRGERR_IE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_TRGERR_IE_SHIFT))&ADC_INT_ENABLE_TRGERR_IE_MASK)
#define ADC_INT_ENABLE_FIFO_RDY_IE_MASK 0x100u
#define ADC_INT_ENABLE_FIFO_RDY_IE_SHIFT 8u
#define ADC_INT_ENABLE_FIFO_RDY_IE_WIDTH 1u
#define ADC_INT_ENABLE_FIFO_RDY_IE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_FIFO_RDY_IE_SHIFT))&ADC_INT_ENABLE_FIFO_RDY_IE_MASK)
#define ADC_INT_ENABLE_ACMP_IE_MASK 0x80u
#define ADC_INT_ENABLE_ACMP_IE_SHIFT 7u
#define ADC_INT_ENABLE_ACMP_IE_WIDTH 1u
#define ADC_INT_ENABLE_ACMP_IE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_ACMP_IE_SHIFT))&ADC_INT_ENABLE_ACMP_IE_MASK)
#define ADC_INT_ENABLE_OVRIE_MASK 0x10u
#define ADC_INT_ENABLE_OVRIE_SHIFT 4u
#define ADC_INT_ENABLE_OVRIE_WIDTH 1u
#define ADC_INT_ENABLE_OVRIE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_OVRIE_SHIFT))&ADC_INT_ENABLE_OVRIE_MASK)
#define ADC_INT_ENABLE_EOSEQIE_MASK 0x8u
#define ADC_INT_ENABLE_EOSEQIE_SHIFT 3u
#define ADC_INT_ENABLE_EOSEQIE_WIDTH 1u
#define ADC_INT_ENABLE_EOSEQIE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_EOSEQIE_SHIFT))&ADC_INT_ENABLE_EOSEQIE_MASK)
#define ADC_INT_ENABLE_EOCIE_MASK 0x4u
#define ADC_INT_ENABLE_EOCIE_SHIFT 2u
#define ADC_INT_ENABLE_EOCIE_WIDTH 1u
#define ADC_INT_ENABLE_EOCIE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_EOCIE_SHIFT))&ADC_INT_ENABLE_EOCIE_MASK)
#define ADC_INT_ENABLE_EOSMPIE_MASK 0x2u
#define ADC_INT_ENABLE_EOSMPIE_SHIFT 1u
#define ADC_INT_ENABLE_EOSMPIE_WIDTH 1u
#define ADC_INT_ENABLE_EOSMPIE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_EOSMPIE_SHIFT))&ADC_INT_ENABLE_EOSMPIE_MASK)
#define ADC_INT_ENABLE_ADRDYIE_MASK 0x1u
#define ADC_INT_ENABLE_ADRDYIE_SHIFT 0u
#define ADC_INT_ENABLE_ADRDYIE_WIDTH 1u
#define ADC_INT_ENABLE_ADRDYIE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_ADRDYIE_SHIFT))&ADC_INT_ENABLE_ADRDYIE_MASK)
/* INT_ENABLE Reg Mask */
#define ADC_INT_ENABLE_MASK 0x0000059Fu
/* CONTROL Bit Fields */
#define ADC_CONTROL_ADRST_MASK 0x10u
#define ADC_CONTROL_ADRST_SHIFT 4u
#define ADC_CONTROL_ADRST_WIDTH 1u
#define ADC_CONTROL_ADRST(x) (((uint32_t)(((uint32_t)(x))<<ADC_CONTROL_ADRST_SHIFT))&ADC_CONTROL_ADRST_MASK)
#define ADC_CONTROL_ADSTP_MASK 0x8u
#define ADC_CONTROL_ADSTP_SHIFT 3u
#define ADC_CONTROL_ADSTP_WIDTH 1u
#define ADC_CONTROL_ADSTP(x) (((uint32_t)(((uint32_t)(x))<<ADC_CONTROL_ADSTP_SHIFT))&ADC_CONTROL_ADSTP_MASK)
#define ADC_CONTROL_ADSTART_MASK 0x4u
#define ADC_CONTROL_ADSTART_SHIFT 2u
#define ADC_CONTROL_ADSTART_WIDTH 1u
#define ADC_CONTROL_ADSTART(x) (((uint32_t)(((uint32_t)(x))<<ADC_CONTROL_ADSTART_SHIFT))&ADC_CONTROL_ADSTART_MASK)
#define ADC_CONTROL_ADDIS_MASK 0x2u
#define ADC_CONTROL_ADDIS_SHIFT 1u
#define ADC_CONTROL_ADDIS_WIDTH 1u
#define ADC_CONTROL_ADDIS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CONTROL_ADDIS_SHIFT))&ADC_CONTROL_ADDIS_MASK)
#define ADC_CONTROL_ADEN_MASK 0x1u
#define ADC_CONTROL_ADEN_SHIFT 0u
#define ADC_CONTROL_ADEN_WIDTH 1u
#define ADC_CONTROL_ADEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CONTROL_ADEN_SHIFT))&ADC_CONTROL_ADEN_MASK)
/* CONTROL Reg Mask */
#define ADC_CONTROL_MASK 0x0000001Fu
/* CFG1 Bit Fields */
#define ADC_CFG1_OVRMOD_MASK 0x40000000u
#define ADC_CFG1_OVRMOD_SHIFT 30u
#define ADC_CFG1_OVRMOD_WIDTH 1u
#define ADC_CFG1_OVRMOD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_OVRMOD_SHIFT))&ADC_CFG1_OVRMOD_MASK)
#define ADC_CFG1_SEQGP_EN_MASK 0x20000000u
#define ADC_CFG1_SEQGP_EN_SHIFT 29u
#define ADC_CFG1_SEQGP_EN_WIDTH 1u
#define ADC_CFG1_SEQGP_EN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_SEQGP_EN_SHIFT))&ADC_CFG1_SEQGP_EN_MASK)
#define ADC_CFG1_SEQ_LEN_MASK 0x1F000000u
#define ADC_CFG1_SEQ_LEN_SHIFT 24u
#define ADC_CFG1_SEQ_LEN_WIDTH 5u
#define ADC_CFG1_SEQ_LEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_SEQ_LEN_SHIFT))&ADC_CFG1_SEQ_LEN_MASK)
#define ADC_CFG1_SEQ_MOD_MASK 0xC00000u
#define ADC_CFG1_SEQ_MOD_SHIFT 22u
#define ADC_CFG1_SEQ_MOD_WIDTH 2u
#define ADC_CFG1_SEQ_MOD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_SEQ_MOD_SHIFT))&ADC_CFG1_SEQ_MOD_MASK)
#define ADC_CFG1_AUTO_DIS_MASK 0x200000u
#define ADC_CFG1_AUTO_DIS_SHIFT 21u
#define ADC_CFG1_AUTO_DIS_WIDTH 1u
#define ADC_CFG1_AUTO_DIS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_AUTO_DIS_SHIFT))&ADC_CFG1_AUTO_DIS_MASK)
#define ADC_CFG1_WAIT_MASK 0x100000u
#define ADC_CFG1_WAIT_SHIFT 20u
#define ADC_CFG1_WAIT_WIDTH 1u
#define ADC_CFG1_WAIT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_WAIT_SHIFT))&ADC_CFG1_WAIT_MASK)
#define ADC_CFG1_TRIGSRC_MASK 0x70000u
#define ADC_CFG1_TRIGSRC_SHIFT 16u
#define ADC_CFG1_TRIGSRC_WIDTH 3u
#define ADC_CFG1_TRIGSRC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_TRIGSRC_SHIFT))&ADC_CFG1_TRIGSRC_MASK)
#define ADC_CFG1_TRIGMODE_MASK 0x3800u
#define ADC_CFG1_TRIGMODE_SHIFT 11u
#define ADC_CFG1_TRIGMODE_WIDTH 3u
#define ADC_CFG1_TRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_TRIGMODE_SHIFT))&ADC_CFG1_TRIGMODE_MASK)
#define ADC_CFG1_ALIGN_MASK 0x400u
#define ADC_CFG1_ALIGN_SHIFT 10u
#define ADC_CFG1_ALIGN_WIDTH 1u
#define ADC_CFG1_ALIGN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ALIGN_SHIFT))&ADC_CFG1_ALIGN_MASK)
#define ADC_CFG1_RES_MASK 0x300u
#define ADC_CFG1_RES_SHIFT 8u
#define ADC_CFG1_RES_WIDTH 2u
#define ADC_CFG1_RES(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_RES_SHIFT))&ADC_CFG1_RES_MASK)
#define ADC_CFG1_DMAEN_MASK 0x1u
#define ADC_CFG1_DMAEN_SHIFT 0u
#define ADC_CFG1_DMAEN_WIDTH 1u
#define ADC_CFG1_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_DMAEN_SHIFT))&ADC_CFG1_DMAEN_MASK)
/* CFG1 Reg Mask */
#define ADC_CFG1_MASK 0x7FF73F01u
/* CFG2 Bit Fields */
#define ADC_CFG2_FWMARK_MASK 0x1F000000u
#define ADC_CFG2_FWMARK_SHIFT 24u
#define ADC_CFG2_FWMARK_WIDTH 5u
#define ADC_CFG2_FWMARK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_FWMARK_SHIFT))&ADC_CFG2_FWMARK_MASK)
#define ADC_CFG2_TRG_PRI_MASK 0x100000u
#define ADC_CFG2_TRG_PRI_SHIFT 20u
#define ADC_CFG2_TRG_PRI_WIDTH 1u
#define ADC_CFG2_TRG_PRI(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_TRG_PRI_SHIFT))&ADC_CFG2_TRG_PRI_MASK)
#define ADC_CFG2_TRG_CLR_MASK 0x80000u
#define ADC_CFG2_TRG_CLR_SHIFT 19u
#define ADC_CFG2_TRG_CLR_WIDTH 1u
#define ADC_CFG2_TRG_CLR(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_TRG_CLR_SHIFT))&ADC_CFG2_TRG_CLR_MASK)
#define ADC_CFG2_AVG_EN_MASK 0x40000u
#define ADC_CFG2_AVG_EN_SHIFT 18u
#define ADC_CFG2_AVG_EN_WIDTH 1u
#define ADC_CFG2_AVG_EN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_AVG_EN_SHIFT))&ADC_CFG2_AVG_EN_MASK)
#define ADC_CFG2_AVG_LEN_MASK 0x30000u
#define ADC_CFG2_AVG_LEN_SHIFT 16u
#define ADC_CFG2_AVG_LEN_WIDTH 2u
#define ADC_CFG2_AVG_LEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_AVG_LEN_SHIFT))&ADC_CFG2_AVG_LEN_MASK)
#define ADC_CFG2_CG_ACK_MASK 0x4000u
#define ADC_CFG2_CG_ACK_SHIFT 14u
#define ADC_CFG2_CG_ACK_WIDTH 1u
#define ADC_CFG2_CG_ACK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_CG_ACK_SHIFT))&ADC_CFG2_CG_ACK_MASK)
#define ADC_CFG2_CG_MASK 0x2000u
#define ADC_CFG2_CG_SHIFT 13u
#define ADC_CFG2_CG_WIDTH 1u
#define ADC_CFG2_CG(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_CG_SHIFT))&ADC_CFG2_CG_MASK)
#define ADC_CFG2_REF_EXT_MASK 0x1000u
#define ADC_CFG2_REF_EXT_SHIFT 12u
#define ADC_CFG2_REF_EXT_WIDTH 1u
#define ADC_CFG2_REF_EXT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_REF_EXT_SHIFT))&ADC_CFG2_REF_EXT_MASK)
#define ADC_CFG2_DIV_MASK 0x300u
#define ADC_CFG2_DIV_SHIFT 8u
#define ADC_CFG2_DIV_WIDTH 2u
#define ADC_CFG2_DIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_DIV_SHIFT))&ADC_CFG2_DIV_MASK)
#define ADC_CFG2_STCNT_MASK 0xFFu
#define ADC_CFG2_STCNT_SHIFT 0u
#define ADC_CFG2_STCNT_WIDTH 8u
#define ADC_CFG2_STCNT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_STCNT_SHIFT))&ADC_CFG2_STCNT_MASK)
/* CFG2 Reg Mask */
#define ADC_CFG2_MASK 0x1F1F73FFu
/* SMPR Bit Fields */
#define ADC_SMPR_SMP_OPT3_MASK 0xFF000000u
#define ADC_SMPR_SMP_OPT3_SHIFT 24u
#define ADC_SMPR_SMP_OPT3_WIDTH 8u
#define ADC_SMPR_SMP_OPT3(x) (((uint32_t)(((uint32_t)(x))<<ADC_SMPR_SMP_OPT3_SHIFT))&ADC_SMPR_SMP_OPT3_MASK)
#define ADC_SMPR_SMP_OPT2_MASK 0xFF0000u
#define ADC_SMPR_SMP_OPT2_SHIFT 16u
#define ADC_SMPR_SMP_OPT2_WIDTH 8u
#define ADC_SMPR_SMP_OPT2(x) (((uint32_t)(((uint32_t)(x))<<ADC_SMPR_SMP_OPT2_SHIFT))&ADC_SMPR_SMP_OPT2_MASK)
#define ADC_SMPR_SMP_OPT1_MASK 0xFF00u
#define ADC_SMPR_SMP_OPT1_SHIFT 8u
#define ADC_SMPR_SMP_OPT1_WIDTH 8u
#define ADC_SMPR_SMP_OPT1(x) (((uint32_t)(((uint32_t)(x))<<ADC_SMPR_SMP_OPT1_SHIFT))&ADC_SMPR_SMP_OPT1_MASK)
#define ADC_SMPR_SMP_OPT0_MASK 0xFFu
#define ADC_SMPR_SMP_OPT0_SHIFT 0u
#define ADC_SMPR_SMP_OPT0_WIDTH 8u
#define ADC_SMPR_SMP_OPT0(x) (((uint32_t)(((uint32_t)(x))<<ADC_SMPR_SMP_OPT0_SHIFT))&ADC_SMPR_SMP_OPT0_MASK)
/* SMPR Reg Mask */
#define ADC_SMPR_MASK 0xFFFFFFFFu
/* CMP_CTRL Bit Fields */
#define ADC_CMP_CTRL_ACMPEN_MASK 0x80u
#define ADC_CMP_CTRL_ACMPEN_SHIFT 7u
#define ADC_CMP_CTRL_ACMPEN_WIDTH 1u
#define ADC_CMP_CTRL_ACMPEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CMP_CTRL_ACMPEN_SHIFT))&ADC_CMP_CTRL_ACMPEN_MASK)
#define ADC_CMP_CTRL_ACMPSGL_MASK 0x40u
#define ADC_CMP_CTRL_ACMPSGL_SHIFT 6u
#define ADC_CMP_CTRL_ACMPSGL_WIDTH 1u
#define ADC_CMP_CTRL_ACMPSGL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CMP_CTRL_ACMPSGL_SHIFT))&ADC_CMP_CTRL_ACMPSGL_MASK)
#define ADC_CMP_CTRL_ACMPCH_MASK 0x3Fu
#define ADC_CMP_CTRL_ACMPCH_SHIFT 0u
#define ADC_CMP_CTRL_ACMPCH_WIDTH 6u
#define ADC_CMP_CTRL_ACMPCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_CMP_CTRL_ACMPCH_SHIFT))&ADC_CMP_CTRL_ACMPCH_MASK)
/* CMP_CTRL Reg Mask */
#define ADC_CMP_CTRL_MASK 0x000000FFu
/* CMP_TR Bit Fields */
#define ADC_CMP_TR_HT_MASK 0xFFF0000u
#define ADC_CMP_TR_HT_SHIFT 16u
#define ADC_CMP_TR_HT_WIDTH 12u
#define ADC_CMP_TR_HT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CMP_TR_HT_SHIFT))&ADC_CMP_TR_HT_MASK)
#define ADC_CMP_TR_LT_MASK 0xFFFu
#define ADC_CMP_TR_LT_SHIFT 0u
#define ADC_CMP_TR_LT_WIDTH 12u
#define ADC_CMP_TR_LT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CMP_TR_LT_SHIFT))&ADC_CMP_TR_LT_MASK)
/* CMP_TR Reg Mask */
#define ADC_CMP_TR_MASK 0x0FFF0FFFu
/* SGCSR Bit Fields */
#define ADC_SGCSR_EOSG_MASK 0x1000000u
#define ADC_SGCSR_EOSG_SHIFT 24u
#define ADC_SGCSR_EOSG_WIDTH 1u
#define ADC_SGCSR_EOSG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SGCSR_EOSG_SHIFT))&ADC_SGCSR_EOSG_MASK)
#define ADC_SGCSR_EOSGIE_MASK 0x10000u
#define ADC_SGCSR_EOSGIE_SHIFT 16u
#define ADC_SGCSR_EOSGIE_WIDTH 1u
#define ADC_SGCSR_EOSGIE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SGCSR_EOSGIE_SHIFT))&ADC_SGCSR_EOSGIE_MASK)
#define ADC_SGCSR_SG_END_MASK 0x1F00u
#define ADC_SGCSR_SG_END_SHIFT 8u
#define ADC_SGCSR_SG_END_WIDTH 5u
#define ADC_SGCSR_SG_END(x) (((uint32_t)(((uint32_t)(x))<<ADC_SGCSR_SG_END_SHIFT))&ADC_SGCSR_SG_END_MASK)
#define ADC_SGCSR_SG_START_MASK 0x1Fu
#define ADC_SGCSR_SG_START_SHIFT 0u
#define ADC_SGCSR_SG_START_WIDTH 5u
#define ADC_SGCSR_SG_START(x) (((uint32_t)(((uint32_t)(x))<<ADC_SGCSR_SG_START_SHIFT))&ADC_SGCSR_SG_START_MASK)
/* SGCSR0 Reg Mask */
#define ADC_SGCSR_MASK 0x01011F1Fu
/* CAL Bit Fields */
#define ADC_CAL_CAL_EN_MASK 0x80000000u
#define ADC_CAL_CAL_EN_SHIFT 31u
#define ADC_CAL_CAL_EN_WIDTH 1u
#define ADC_CAL_CAL_EN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CAL_CAL_EN_SHIFT))&ADC_CAL_CAL_EN_MASK)
#define ADC_CAL_OFFSET_MASK 0xFFF0000u
#define ADC_CAL_OFFSET_SHIFT 16u
#define ADC_CAL_OFFSET_WIDTH 12u
#define ADC_CAL_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ADC_CAL_OFFSET_SHIFT))&ADC_CAL_OFFSET_MASK)
#define ADC_CAL_GAIN_MASK 0x1FFFu
#define ADC_CAL_GAIN_SHIFT 0u
#define ADC_CAL_GAIN_WIDTH 13u
#define ADC_CAL_GAIN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CAL_GAIN_SHIFT))&ADC_CAL_GAIN_MASK)
/* CAL Reg Mask */
#define ADC_CAL_MASK 0x8FFF1FFFu
/* FIFO_DATA Bit Fields */
#define ADC_FIFO_DATA_FIFO_DATA_MASK 0xFFFFu
#define ADC_FIFO_DATA_FIFO_DATA_SHIFT 0u
#define ADC_FIFO_DATA_FIFO_DATA_WIDTH 16u
#define ADC_FIFO_DATA_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x))<<ADC_FIFO_DATA_FIFO_DATA_SHIFT))&ADC_FIFO_DATA_FIFO_DATA_MASK)
/* FIFO_DATA Reg Mask */
#define ADC_FIFO_DATA_MASK 0x0000FFFFu
/* SC Bit Fields */
#define ADC_SC_DIFF_MASK 0x400u
#define ADC_SC_DIFF_SHIFT 10u
#define ADC_SC_DIFF_WIDTH 1u
#define ADC_SC_DIFF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC_DIFF_SHIFT))&ADC_SC_DIFF_MASK)
#define ADC_SC_SMPSEL_MASK 0x300u
#define ADC_SC_SMPSEL_SHIFT 8u
#define ADC_SC_SMPSEL_WIDTH 2u
#define ADC_SC_SMPSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC_SMPSEL_SHIFT))&ADC_SC_SMPSEL_MASK)
#define ADC_SC_COCO_MASK 0x80u
#define ADC_SC_COCO_SHIFT 7u
#define ADC_SC_COCO_WIDTH 1u
#define ADC_SC_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC_COCO_SHIFT))&ADC_SC_COCO_MASK)
#define ADC_SC_AIEN_MASK 0x40u
#define ADC_SC_AIEN_SHIFT 6u
#define ADC_SC_AIEN_WIDTH 1u
#define ADC_SC_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC_AIEN_SHIFT))&ADC_SC_AIEN_MASK)
#define ADC_SC_CHS_MASK 0x3Fu
#define ADC_SC_CHS_SHIFT 0u
#define ADC_SC_CHS_WIDTH 6u
#define ADC_SC_CHS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC_CHS_SHIFT))&ADC_SC_CHS_MASK)
/* SC0 Reg Mask */
#define ADC_SC_MASK 0x000007FFu
/* RESULT Bit Fields */
#define ADC_RESULT_RESULT_MASK 0xFFFFu
#define ADC_RESULT_RESULT_SHIFT 0u
#define ADC_RESULT_RESULT_WIDTH 16u
#define ADC_RESULT_RESULT(x) (((uint32_t)(((uint32_t)(x))<<ADC_RESULT_RESULT_SHIFT))&ADC_RESULT_RESULT_MASK)
/* RESULT0 Reg Mask */
#define ADC_RESULT_MASK 0x0000FFFFu
/*!
* @}
*/ /* end of group ADC_Register_Masks */
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

805
fc/fc7240_ahb_overlay_regs.h Normal file
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@ -0,0 +1,805 @@
#ifndef _FC7240_AHB_OVERLAY_NU_Tztufn37_REGS_H_
#define _FC7240_AHB_OVERLAY_NU_Tztufn37_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- AHB_OVERLAY Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AHB_OVERLAY_Peripheral_Access_Layer AHB_OVERLAY Peripheral Access Layer
* @{
*/
/** AHB_OVERLAY - Size of Registers Arrays */
/** AHB_OVERLAY - Register Layout Typedef */
typedef struct {
__IO uint32_t REGION_0_SRC ; /* Region 0 Source Address Register, offset: 0x00 */
__IO uint32_t REGION_0_DST ; /* Region 0 Destination Address Register, offset: 0x04 */
__IO uint32_t REGION_0_SIZE ; /* Region 0 Size Register, offset: 0x08 */
__IO uint32_t REGION_0_EN ; /* Region 0 Enable Register, offset: 0x0C */
__IO uint32_t REGION_1_SRC ; /* Region 1 Source Address Register, offset: 0x10 */
__IO uint32_t REGION_1_DST ; /* Region 1 Destination Address Register, offset: 0x14 */
__IO uint32_t REGION_1_SIZE ; /* Region 1 Size Register, offset: 0x18 */
__IO uint32_t REGION_1_EN ; /* Region 1 Enable Register, offset: 0x1C */
__IO uint32_t REGION_2_SRC ; /* region 2 source address Register, offset: 0x20 */
__IO uint32_t REGION_2_DST ; /* Region 2 Destination Address Register, offset: 0x24 */
__IO uint32_t REGION_2_SIZE ; /* Region 2 Size Register, offset: 0x28 */
__IO uint32_t REGION_2_EN ; /* Region 2 Enable Register, offset: 0x2C */
uint8_t RESERVED_0[80];
__IO uint32_t GLOBAL_EN ; /* Enable of FAR and Overlay Register, offset: 0x80 */
__I uint32_t INTR_FLAG ; /* Flag of All Interrupt Register, offset: 0x84 */
__O uint32_t INTR_CLR ; /* Clear Bit of Interupt Register, offset: 0x88 */
__IO uint32_t INTR_EN ; /* Enable of Interrupt Register, offset: 0x8C */
__I uint32_t FAR_SRC ; /* Source of FAR Register, offset: 0x90 */
__IO uint32_t FAR_DST ; /* Sestination of FAR Register, offset: 0x94 */
__IO uint32_t FAR_SIZE ; /* Size of FAR Register, offset: 0x98 */
uint8_t RESERVED_1[4];
__I uint32_t REGION0_MASK ; /* Region 0 Mask Register, offset: 0xA0 */
__I uint32_t REGION1_MASK ; /* Region 1 Mask Register, offset: 0xA4 */
__I uint32_t REGION2_MASK ; /* Region 2 Mask Register, offset: 0xA8 */
} AHB_OVERLAY_Type, *AHB_OVERLAY_MemMapPtr;
/** Number of instances of the AHB_OVERLAY module. */
#define AHB_OVERLAY_INSTANCE_COUNT (1u)
/* AHB_OVERLAY - Peripheral instance base addresses */
/** Peripheral AHB_OVERLAY base address */
#define AHB_OVERLAY_BASE (0xE0081000u)
/** Peripheral AHB_OVERLAY base pointer */
#define AHB_OVERLAY ((AHB_OVERLAY_Type *)AHB_OVERLAY_BASE)
/** Array initializer of AHB_OVERLAY peripheral base addresses */
#define AHB_OVERLAY_BASE_ADDRS {AHB_OVERLAY_BASE}
/** Array initializer of AHB_OVERLAY peripheral base pointers */
#define AHB_OVERLAY_BASE_PTRS {AHB_OVERLAY}
// need fill by yourself
///** Number of interrupt vector arrays for the AHB_OVERLAY module. */
//#define AHB_OVERLAY_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the AHB_OVERLAY module. */
//#define AHB_OVERLAY_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the AHB_OVERLAY peripheral type */
//#define AHB_OVERLAY_IRQS {AHB_OVERLAY_IRQn}
/* ----------------------------------------------------------------------------
-- AHB_OVERLAY Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AHB_OVERLAY_Register_Masks AHB_OVERLAY Register Masks
* @{
*/
/* REGION_0_SRC Bit Fields */
#define AHB_OVERLAY_REGION_0_SRC_REGION0_SRC_MASK 0x1FFC00u
#define AHB_OVERLAY_REGION_0_SRC_REGION0_SRC_SHIFT 10u
#define AHB_OVERLAY_REGION_0_SRC_REGION0_SRC_WIDTH 11u
#define AHB_OVERLAY_REGION_0_SRC_REGION0_SRC(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_0_SRC_REGION0_SRC_MASK)
/* REGION_0_SRC Reg Mask */
#define AHB_OVERLAY_REGION_0_SRC_MASK 0x001FFC00u
/* REGION_0_DST Bit Fields */
#define AHB_OVERLAY_REGION_0_DST_REGION0_DST_MASK 0xFFFFFC00u
#define AHB_OVERLAY_REGION_0_DST_REGION0_DST_SHIFT 10u
#define AHB_OVERLAY_REGION_0_DST_REGION0_DST_WIDTH 22u
#define AHB_OVERLAY_REGION_0_DST_REGION0_DST(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_0_DST_REGION0_DST_MASK)
/* REGION_0_DST Reg Mask */
#define AHB_OVERLAY_REGION_0_DST_MASK 0xFFFFFC00u
/* REGION_0_SIZE Bit Fields */
#define AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_MASK 0x7Fu
#define AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_SHIFT 0u
#define AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_WIDTH 7u
#define AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_SHIFT))&AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_MASK)
/* REGION_0_SIZE Reg Mask */
#define AHB_OVERLAY_REGION_0_SIZE_MASK 0x0000007Fu
/* REGION_0_EN Bit Fields */
#define AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK 0x1u
#define AHB_OVERLAY_REGION_0_EN_REGION0_EN_SHIFT 0u
#define AHB_OVERLAY_REGION_0_EN_REGION0_EN_WIDTH 1u
#define AHB_OVERLAY_REGION_0_EN_REGION0_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_0_EN_REGION0_EN_SHIFT))&AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK)
/* REGION_0_EN Reg Mask */
#define AHB_OVERLAY_REGION_0_EN_MASK 0x00000001u
/* REGION_1_SRC Bit Fields */
#define AHB_OVERLAY_REGION_1_SRC_REGION1_SRC_MASK 0x1FFC00u
#define AHB_OVERLAY_REGION_1_SRC_REGION1_SRC_SHIFT 10u
#define AHB_OVERLAY_REGION_1_SRC_REGION1_SRC_WIDTH 11u
#define AHB_OVERLAY_REGION_1_SRC_REGION1_SRC(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_1_SRC_REGION1_SRC_MASK)
/* REGION_1_SRC Reg Mask */
#define AHB_OVERLAY_REGION_1_SRC_MASK 0x001FFC00u
/* REGION_1_DST Bit Fields */
#define AHB_OVERLAY_REGION_1_DST_REGION1_DST_MASK 0xFFFFFC00u
#define AHB_OVERLAY_REGION_1_DST_REGION1_DST_SHIFT 10u
#define AHB_OVERLAY_REGION_1_DST_REGION1_DST_WIDTH 22u
#define AHB_OVERLAY_REGION_1_DST_REGION1_DST(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_1_DST_REGION1_DST_MASK)
/* REGION_1_DST Reg Mask */
#define AHB_OVERLAY_REGION_1_DST_MASK 0xFFFFFC00u
/* REGION_1_SIZE Bit Fields */
#define AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_MASK 0x7Fu
#define AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_SHIFT 0u
#define AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_WIDTH 7u
#define AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_SHIFT))&AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_MASK)
/* REGION_1_SIZE Reg Mask */
#define AHB_OVERLAY_REGION_1_SIZE_MASK 0x0000007Fu
/* REGION_1_EN Bit Fields */
#define AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK 0x1u
#define AHB_OVERLAY_REGION_1_EN_REGION1_EN_SHIFT 0u
#define AHB_OVERLAY_REGION_1_EN_REGION1_EN_WIDTH 1u
#define AHB_OVERLAY_REGION_1_EN_REGION1_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_1_EN_REGION1_EN_SHIFT))&AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK)
/* REGION_1_EN Reg Mask */
#define AHB_OVERLAY_REGION_1_EN_MASK 0x00000001u
/* REGION_2_SRC Bit Fields */
#define AHB_OVERLAY_REGION_2_SRC_REGION2_SRC_MASK 0x1FFC00u
#define AHB_OVERLAY_REGION_2_SRC_REGION2_SRC_SHIFT 10u
#define AHB_OVERLAY_REGION_2_SRC_REGION2_SRC_WIDTH 11u
#define AHB_OVERLAY_REGION_2_SRC_REGION2_SRC(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_2_SRC_REGION2_SRC_MASK)
/* REGION_2_SRC Reg Mask */
#define AHB_OVERLAY_REGION_2_SRC_MASK 0x001FFC00u
/* REGION_2_DST Bit Fields */
#define AHB_OVERLAY_REGION_2_DST_REGION2_DST_MASK 0xFFFFFC00u
#define AHB_OVERLAY_REGION_2_DST_REGION2_DST_SHIFT 10u
#define AHB_OVERLAY_REGION_2_DST_REGION2_DST_WIDTH 22u
#define AHB_OVERLAY_REGION_2_DST_REGION2_DST(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_2_DST_REGION2_DST_MASK)
/* REGION_2_DST Reg Mask */
#define AHB_OVERLAY_REGION_2_DST_MASK 0xFFFFFC00u
/* REGION_2_SIZE Bit Fields */
#define AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_MASK 0x7Fu
#define AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_SHIFT 0u
#define AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_WIDTH 7u
#define AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_SHIFT))&AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_MASK)
/* REGION_2_SIZE Reg Mask */
#define AHB_OVERLAY_REGION_2_SIZE_MASK 0x0000007Fu
/* REGION_2_EN Bit Fields */
#define AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK 0x1u
#define AHB_OVERLAY_REGION_2_EN_REGION2_EN_SHIFT 0u
#define AHB_OVERLAY_REGION_2_EN_REGION2_EN_WIDTH 1u
#define AHB_OVERLAY_REGION_2_EN_REGION2_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_2_EN_REGION2_EN_SHIFT))&AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK)
/* REGION_2_EN Reg Mask */
#define AHB_OVERLAY_REGION_2_EN_MASK 0x00000001u
/* GLOBAL_EN Bit Fields */
#define AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK 0x2u
#define AHB_OVERLAY_GLOBAL_EN_FAR_EN_SHIFT 1u
#define AHB_OVERLAY_GLOBAL_EN_FAR_EN_WIDTH 1u
#define AHB_OVERLAY_GLOBAL_EN_FAR_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_GLOBAL_EN_FAR_EN_SHIFT))&AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK)
#define AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK 0x1u
#define AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_SHIFT 0u
#define AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_WIDTH 1u
#define AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_SHIFT))&AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK)
/* GLOBAL_EN Reg Mask */
#define AHB_OVERLAY_GLOBAL_EN_MASK 0x00000003u
/* INTR_FLAG Bit Fields */
#define AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_MASK 0x20000u
#define AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_SHIFT 17u
#define AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_MASK 0x10000u
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_SHIFT 16u
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_MASK 0x8000u
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_SHIFT 15u
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_MASK 0x4000u
#define AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_SHIFT 14u
#define AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_MASK 0x2000u
#define AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_SHIFT 13u
#define AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_MASK 0x1000u
#define AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_SHIFT 12u
#define AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_MASK 0x800u
#define AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_SHIFT 11u
#define AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_MASK 0x400u
#define AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_SHIFT 10u
#define AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_MASK 0x200u
#define AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_SHIFT 9u
#define AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_MASK 0x100u
#define AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_SHIFT 8u
#define AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_MASK 0x80u
#define AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_SHIFT 7u
#define AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_MASK 0x40u
#define AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_SHIFT 6u
#define AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_MASK 0x20u
#define AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_SHIFT 5u
#define AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_MASK 0x10u
#define AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_SHIFT 4u
#define AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_MASK 0x8u
#define AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_SHIFT 3u
#define AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_MASK 0x4u
#define AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_SHIFT 2u
#define AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_MASK 0x2u
#define AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_SHIFT 1u
#define AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_MASK)
#define AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_MASK 0x1u
#define AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_SHIFT 0u
#define AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_WIDTH 1u
#define AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_MASK)
/* INTR_FLAG Reg Mask */
#define AHB_OVERLAY_INTR_FLAG_MASK 0x0003FFFFu
/* INTR_CLR Bit Fields */
#define AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_MASK 0x20000u
#define AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_SHIFT 17u
#define AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_MASK 0x10000u
#define AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_SHIFT 16u
#define AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_MASK 0x8000u
#define AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_SHIFT 15u
#define AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_MASK 0x4000u
#define AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_SHIFT 14u
#define AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_MASK 0x2000u
#define AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_SHIFT 13u
#define AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_MASK 0x1000u
#define AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_SHIFT 12u
#define AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_MASK 0x800u
#define AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_SHIFT 11u
#define AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_MASK 0x400u
#define AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_SHIFT 10u
#define AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_MASK 0x200u
#define AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_SHIFT 9u
#define AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_MASK 0x100u
#define AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_SHIFT 8u
#define AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_MASK 0x80u
#define AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_SHIFT 7u
#define AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_MASK 0x40u
#define AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_SHIFT 6u
#define AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_MASK 0x20u
#define AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_SHIFT 5u
#define AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_MASK 0x10u
#define AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_SHIFT 4u
#define AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_MASK 0x8u
#define AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_SHIFT 3u
#define AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_MASK 0x4u
#define AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_SHIFT 2u
#define AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_MASK 0x2u
#define AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_SHIFT 1u
#define AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_MASK)
#define AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_MASK 0x1u
#define AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_SHIFT 0u
#define AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_WIDTH 1u
#define AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_MASK)
/* INTR_CLR Reg Mask */
#define AHB_OVERLAY_INTR_CLR_MASK 0x0003FFFFu
/* INTR_EN Bit Fields */
#define AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK 0x1u
#define AHB_OVERLAY_INTR_EN_INTR_ENABLE_SHIFT 0u
#define AHB_OVERLAY_INTR_EN_INTR_ENABLE_WIDTH 1u
#define AHB_OVERLAY_INTR_EN_INTR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_EN_INTR_ENABLE_SHIFT))&AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK)
/* INTR_EN Reg Mask */
#define AHB_OVERLAY_INTR_EN_MASK 0x00000001u
/* FAR_SRC Bit Fields */
#define AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR_MASK 0xFFFFFFFFu
#define AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR_SHIFT 0u
#define AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR_WIDTH 32u
#define AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR_MASK)
/* FAR_SRC Reg Mask */
#define AHB_OVERLAY_FAR_SRC_MASK 0xFFFFFFFFu
/* FAR_DST Bit Fields */
#define AHB_OVERLAY_FAR_DST_FAR_DST_ADDR_MASK 0xFFFF0000u
#define AHB_OVERLAY_FAR_DST_FAR_DST_ADDR_SHIFT 16u
#define AHB_OVERLAY_FAR_DST_FAR_DST_ADDR_WIDTH 16u
#define AHB_OVERLAY_FAR_DST_FAR_DST_ADDR(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_FAR_DST_FAR_DST_ADDR_MASK)
/* FAR_DST Reg Mask */
#define AHB_OVERLAY_FAR_DST_MASK 0xFFFF0000u
/* FAR_SIZE Bit Fields */
#define AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_MASK 0x1FFu
#define AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_SHIFT 0u
#define AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_WIDTH 9u
#define AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_SHIFT))&AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_MASK)
/* FAR_SIZE Reg Mask */
#define AHB_OVERLAY_FAR_SIZE_MASK 0x000001FFu
/* REGION0_MASK Bit Fields */
#define AHB_OVERLAY_REGION0_MASK_REGION0_MASK_MASK 0xFFFFFFFFu
#define AHB_OVERLAY_REGION0_MASK_REGION0_MASK_SHIFT 0u
#define AHB_OVERLAY_REGION0_MASK_REGION0_MASK_WIDTH 32u
#define AHB_OVERLAY_REGION0_MASK_REGION0_MASK(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION0_MASK_REGION0_MASK_SHIFT))&AHB_OVERLAY_REGION0_MASK_REGION0_MASK_MASK)
/* REGION0_MASK Reg Mask */
#define AHB_OVERLAY_REGION0_MASK_MASK 0xFFFFFFFFu
/* REGION1_MASK Bit Fields */
#define AHB_OVERLAY_REGION1_MASK_REGION1_MASK_MASK 0xFFFFFFFFu
#define AHB_OVERLAY_REGION1_MASK_REGION1_MASK_SHIFT 0u
#define AHB_OVERLAY_REGION1_MASK_REGION1_MASK_WIDTH 32u
#define AHB_OVERLAY_REGION1_MASK_REGION1_MASK(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION1_MASK_REGION1_MASK_SHIFT))&AHB_OVERLAY_REGION1_MASK_REGION1_MASK_MASK)
/* REGION1_MASK Reg Mask */
#define AHB_OVERLAY_REGION1_MASK_MASK 0xFFFFFFFFu
/* REGION2_MASK Bit Fields */
#define AHB_OVERLAY_REGION2_MASK_REGION2_MASK_MASK 0xFFFFFFFFu
#define AHB_OVERLAY_REGION2_MASK_REGION2_MASK_SHIFT 0u
#define AHB_OVERLAY_REGION2_MASK_REGION2_MASK_WIDTH 32u
#define AHB_OVERLAY_REGION2_MASK_REGION2_MASK(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION2_MASK_REGION2_MASK_SHIFT))&AHB_OVERLAY_REGION2_MASK_REGION2_MASK_MASK)
/* REGION2_MASK Reg Mask */
#define AHB_OVERLAY_REGION2_MASK_MASK 0xFFFFFFFFu
/*!
* @}
*/ /* end of group AHB_OVERLAY_Register_Masks */
/*!
* @}
*/ /* end of group AHB_OVERLAY_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_AONTIMER_NU_Tztufn16_REGS_H_
#define _FC7240_AONTIMER_NU_Tztufn16_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- AONTIMER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AONTIMER_Peripheral_Access_Layer AONTIMER Peripheral Access Layer
* @{
*/
/** AONTIMER - Size of Registers Arrays */
/** AONTIMER - Register Layout Typedef */
typedef struct {
__IO uint32_t CSR ; /* Control Status Register, offset: 0x0 */
__IO uint32_t PSR ; /* Prescale Register, offset: 0x4 */
__IO uint32_t CMR ; /* Compare Register, offset: 0x8 */
__IO uint32_t CNR ; /* Counter Register, offset: 0xC */
} AONTIMER_Type, *AONTIMER_MemMapPtr;
/** Number of instances of the AONTIMER module. */
#define AONTIMER_INSTANCE_COUNT (1u)
/* AONTIMER - Peripheral instance base addresses */
/** Peripheral AONTIMER base address */
#define AONTIMER_BASE (0x4002f000u)
/** Peripheral AONTIMER base pointer */
#define AONTIMER ((AONTIMER_Type *)AONTIMER_BASE)
/** Array initializer of AONTIMER peripheral base addresses */
#define AONTIMER_BASE_ADDRS {AONTIMER_BASE}
/** Array initializer of AONTIMER peripheral base pointers */
#define AONTIMER_BASE_PTRS {AONTIMER}
// need fill by yourself
///** Number of interrupt vector arrays for the AONTIMER module. */
//#define AONTIMER_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the AONTIMER module. */
//#define AONTIMER_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the AONTIMER peripheral type */
//#define AONTIMER_IRQS {AONTIMER_IRQn}
/* ----------------------------------------------------------------------------
-- AONTIMER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AONTIMER_Register_Masks AONTIMER Register Masks
* @{
*/
/* CSR Bit Fields */
#define AONTIMER_CSR_DBGEN_MASK 0x200u
#define AONTIMER_CSR_DBGEN_SHIFT 9u
#define AONTIMER_CSR_DBGEN_WIDTH 1u
#define AONTIMER_CSR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_DBGEN_SHIFT))&AONTIMER_CSR_DBGEN_MASK)
#define AONTIMER_CSR_TDRE_MASK 0x100u
#define AONTIMER_CSR_TDRE_SHIFT 8u
#define AONTIMER_CSR_TDRE_WIDTH 1u
#define AONTIMER_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TDRE_SHIFT))&AONTIMER_CSR_TDRE_MASK)
#define AONTIMER_CSR_TCF_MASK 0x80u
#define AONTIMER_CSR_TCF_SHIFT 7u
#define AONTIMER_CSR_TCF_WIDTH 1u
#define AONTIMER_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TCF_SHIFT))&AONTIMER_CSR_TCF_MASK)
#define AONTIMER_CSR_TIE_MASK 0x40u
#define AONTIMER_CSR_TIE_SHIFT 6u
#define AONTIMER_CSR_TIE_WIDTH 1u
#define AONTIMER_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TIE_SHIFT))&AONTIMER_CSR_TIE_MASK)
#define AONTIMER_CSR_TPS_MASK 0x30u
#define AONTIMER_CSR_TPS_SHIFT 4u
#define AONTIMER_CSR_TPS_WIDTH 2u
#define AONTIMER_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TPS_SHIFT))&AONTIMER_CSR_TPS_MASK)
#define AONTIMER_CSR_TPP_MASK 0x8u
#define AONTIMER_CSR_TPP_SHIFT 3u
#define AONTIMER_CSR_TPP_WIDTH 1u
#define AONTIMER_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TPP_SHIFT))&AONTIMER_CSR_TPP_MASK)
#define AONTIMER_CSR_TFC_MASK 0x4u
#define AONTIMER_CSR_TFC_SHIFT 2u
#define AONTIMER_CSR_TFC_WIDTH 1u
#define AONTIMER_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TFC_SHIFT))&AONTIMER_CSR_TFC_MASK)
#define AONTIMER_CSR_TMS_MASK 0x2u
#define AONTIMER_CSR_TMS_SHIFT 1u
#define AONTIMER_CSR_TMS_WIDTH 1u
#define AONTIMER_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TMS_SHIFT))&AONTIMER_CSR_TMS_MASK)
#define AONTIMER_CSR_TEN_MASK 0x1u
#define AONTIMER_CSR_TEN_SHIFT 0u
#define AONTIMER_CSR_TEN_WIDTH 1u
#define AONTIMER_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TEN_SHIFT))&AONTIMER_CSR_TEN_MASK)
/* CSR Reg Mask */
#define AONTIMER_CSR_MASK 0x000003FFu
/* PSR Bit Fields */
#define AONTIMER_PSR_PRESCALE_MASK 0x78u
#define AONTIMER_PSR_PRESCALE_SHIFT 3u
#define AONTIMER_PSR_PRESCALE_WIDTH 4u
#define AONTIMER_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_PSR_PRESCALE_SHIFT))&AONTIMER_PSR_PRESCALE_MASK)
#define AONTIMER_PSR_PBYP_MASK 0x4u
#define AONTIMER_PSR_PBYP_SHIFT 2u
#define AONTIMER_PSR_PBYP_WIDTH 1u
#define AONTIMER_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_PSR_PBYP_SHIFT))&AONTIMER_PSR_PBYP_MASK)
#define AONTIMER_PSR_PCS_MASK 0x3u
#define AONTIMER_PSR_PCS_SHIFT 0u
#define AONTIMER_PSR_PCS_WIDTH 2u
#define AONTIMER_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_PSR_PCS_SHIFT))&AONTIMER_PSR_PCS_MASK)
/* PSR Reg Mask */
#define AONTIMER_PSR_MASK 0x0000007Fu
/* CMR Bit Fields */
#define AONTIMER_CMR_COMPARE_MASK 0xFFFFu
#define AONTIMER_CMR_COMPARE_SHIFT 0u
#define AONTIMER_CMR_COMPARE_WIDTH 16u
#define AONTIMER_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CMR_COMPARE_SHIFT))&AONTIMER_CMR_COMPARE_MASK)
/* CMR Reg Mask */
#define AONTIMER_CMR_MASK 0x0000FFFFu
/* CNR Bit Fields */
#define AONTIMER_CNR_COUNTER_MASK 0xFFFFu
#define AONTIMER_CNR_COUNTER_SHIFT 0u
#define AONTIMER_CNR_COUNTER_WIDTH 16u
#define AONTIMER_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CNR_COUNTER_SHIFT))&AONTIMER_CNR_COUNTER_MASK)
/* CNR Reg Mask */
#define AONTIMER_CNR_MASK 0x0000FFFFu
/*!
* @}
*/ /* end of group AONTIMER_Register_Masks */
/*!
* @}
*/ /* end of group AONTIMER_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_CMP_NU_Tztufn27_REGS_H_
#define _FC7240_CMP_NU_Tztufn27_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- CMP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
* @{
*/
/** CMP - Size of Registers Arrays */
/** CMP - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[8];
__IO uint32_t CCR0 ; /* Comparator Control Register 0, offset: 0x8 */
__IO uint32_t CCR1 ; /* Comparator Control Register 1, offset: 0xC */
__IO uint32_t CCR2 ; /* Comparator Control Register 2, offset: 0x10 */
__IO uint32_t CCR3 ; /* Comparator Control Register 3, offset: 0x14 */
__IO uint32_t DCR ; /* Comparator DAC Control Register, offset: 0x18 */
__IO uint32_t IER ; /* Comparator Interrupt Enable Register, offset: 0x1C */
__IO uint32_t CSR ; /* Comparator Status Register, offset: 0x20 */
__IO uint32_t CSCR0 ; /* Channel Scan Control Register 0, offset: 0x24 */
__IO uint32_t CSCR1 ; /* Channel Scan Control Register 1, offset: 0x28 */
__IO uint32_t CSCSR ; /* Channel Scan Control and Status Register, offset: 0x2C */
__IO uint32_t CSSR ; /* Channel Scan Status Register, offset: 0x30 */
} CMP_Type, *CMP_MemMapPtr;
/** Number of instances of the CMP module. */
#define CMP_INSTANCE_COUNT (2u)
/* CMP - Peripheral instance base addresses */
/** Peripheral CMP0 base address */
#define CMP0_BASE (0x40040000u)
/** Peripheral CMP0 base pointer */
#define CMP0 ((CMP_Type *)CMP0_BASE)
/** Peripheral CMP1 base address */
#define CMP1_BASE (0x40041000u)
/** Peripheral CMP1 base pointer */
#define CMP1 ((CMP_Type *)CMP1_BASE)
/** Array initializer of CMP peripheral base addresses */
#define CMP_BASE_ADDRS {CMP0_BASE, CMP1_BASE}
/** Array initializer of CMP peripheral base pointers */
#define CMP_BASE_PTRS {CMP0, CMP1}
// need fill by yourself
///** Number of interrupt vector arrays for the CMP module. */
//#define CMP_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the CMP module. */
//#define CMP_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the CMP peripheral type */
//#define CMP_IRQS {CMP0_IRQn, CMP1_IRQn}
/* ----------------------------------------------------------------------------
-- CMP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
/* CCR0 Bit Fields */
#define CMP_CCR0_DACEN_SEL_MASK 0x4u
#define CMP_CCR0_DACEN_SEL_SHIFT 2u
#define CMP_CCR0_DACEN_SEL_WIDTH 1u
#define CMP_CCR0_DACEN_SEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR0_DACEN_SEL_SHIFT))&CMP_CCR0_DACEN_SEL_MASK)
#define CMP_CCR0_STOP_EN_MASK 0x2u
#define CMP_CCR0_STOP_EN_SHIFT 1u
#define CMP_CCR0_STOP_EN_WIDTH 1u
#define CMP_CCR0_STOP_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR0_STOP_EN_SHIFT))&CMP_CCR0_STOP_EN_MASK)
#define CMP_CCR0_EN_MASK 0x1u
#define CMP_CCR0_EN_SHIFT 0u
#define CMP_CCR0_EN_WIDTH 1u
#define CMP_CCR0_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR0_EN_SHIFT))&CMP_CCR0_EN_MASK)
/* CCR0 Reg Mask */
#define CMP_CCR0_MASK 0x00000007u
/* CCR1 Bit Fields */
#define CMP_CCR1_FILT_PER_MASK 0xFF000000u
#define CMP_CCR1_FILT_PER_SHIFT 24u
#define CMP_CCR1_FILT_PER_WIDTH 8u
#define CMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_FILT_PER_SHIFT))&CMP_CCR1_FILT_PER_MASK)
#define CMP_CCR1_FILT_CNT_MASK 0x70000u
#define CMP_CCR1_FILT_CNT_SHIFT 16u
#define CMP_CCR1_FILT_CNT_WIDTH 3u
#define CMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_FILT_CNT_SHIFT))&CMP_CCR1_FILT_CNT_MASK)
#define CMP_CCR1_EVT_SEL_MASK 0xC00u
#define CMP_CCR1_EVT_SEL_SHIFT 10u
#define CMP_CCR1_EVT_SEL_WIDTH 2u
#define CMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_EVT_SEL_SHIFT))&CMP_CCR1_EVT_SEL_MASK)
#define CMP_CCR1_WIN_CLS_MASK 0x200u
#define CMP_CCR1_WIN_CLS_SHIFT 9u
#define CMP_CCR1_WIN_CLS_WIDTH 1u
#define CMP_CCR1_WIN_CLS(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_WIN_CLS_SHIFT))&CMP_CCR1_WIN_CLS_MASK)
#define CMP_CCR1_WIN_INV_MASK 0x100u
#define CMP_CCR1_WIN_INV_SHIFT 8u
#define CMP_CCR1_WIN_INV_WIDTH 1u
#define CMP_CCR1_WIN_INV(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_WIN_INV_SHIFT))&CMP_CCR1_WIN_INV_MASK)
#define CMP_CCR1_CMPOUT_WIN_OW_MASK 0x80u
#define CMP_CCR1_CMPOUT_WIN_OW_SHIFT 7u
#define CMP_CCR1_CMPOUT_WIN_OW_WIDTH 1u
#define CMP_CCR1_CMPOUT_WIN_OW(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_CMPOUT_WIN_OW_SHIFT))&CMP_CCR1_CMPOUT_WIN_OW_MASK)
#define CMP_CCR1_CMPOUT_WIN_OWEN_MASK 0x40u
#define CMP_CCR1_CMPOUT_WIN_OWEN_SHIFT 6u
#define CMP_CCR1_CMPOUT_WIN_OWEN_WIDTH 1u
#define CMP_CCR1_CMPOUT_WIN_OWEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_CMPOUT_WIN_OWEN_SHIFT))&CMP_CCR1_CMPOUT_WIN_OWEN_MASK)
#define CMP_CCR1_CMPOUT_PEN_MASK 0x20u
#define CMP_CCR1_CMPOUT_PEN_SHIFT 5u
#define CMP_CCR1_CMPOUT_PEN_WIDTH 1u
#define CMP_CCR1_CMPOUT_PEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_CMPOUT_PEN_SHIFT))&CMP_CCR1_CMPOUT_PEN_MASK)
#define CMP_CCR1_CMPOUT_SEL_MASK 0x10u
#define CMP_CCR1_CMPOUT_SEL_SHIFT 4u
#define CMP_CCR1_CMPOUT_SEL_WIDTH 1u
#define CMP_CCR1_CMPOUT_SEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_CMPOUT_SEL_SHIFT))&CMP_CCR1_CMPOUT_SEL_MASK)
#define CMP_CCR1_CMPOUT_INV_MASK 0x8u
#define CMP_CCR1_CMPOUT_INV_SHIFT 3u
#define CMP_CCR1_CMPOUT_INV_WIDTH 1u
#define CMP_CCR1_CMPOUT_INV(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_CMPOUT_INV_SHIFT))&CMP_CCR1_CMPOUT_INV_MASK)
#define CMP_CCR1_DMA_EN_MASK 0x4u
#define CMP_CCR1_DMA_EN_SHIFT 2u
#define CMP_CCR1_DMA_EN_WIDTH 1u
#define CMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_DMA_EN_SHIFT))&CMP_CCR1_DMA_EN_MASK)
#define CMP_CCR1_SAMPLE_EN_MASK 0x2u
#define CMP_CCR1_SAMPLE_EN_SHIFT 1u
#define CMP_CCR1_SAMPLE_EN_WIDTH 1u
#define CMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_SAMPLE_EN_SHIFT))&CMP_CCR1_SAMPLE_EN_MASK)
#define CMP_CCR1_WIN_EN_MASK 0x1u
#define CMP_CCR1_WIN_EN_SHIFT 0u
#define CMP_CCR1_WIN_EN_WIDTH 1u
#define CMP_CCR1_WIN_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_WIN_EN_SHIFT))&CMP_CCR1_WIN_EN_MASK)
/* CCR1 Reg Mask */
#define CMP_CCR1_MASK 0xFF070FFFu
/* CCR2 Bit Fields */
#define CMP_CCR2_INMSEL_MASK 0x30000000u
#define CMP_CCR2_INMSEL_SHIFT 28u
#define CMP_CCR2_INMSEL_WIDTH 2u
#define CMP_CCR2_INMSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR2_INMSEL_SHIFT))&CMP_CCR2_INMSEL_MASK)
#define CMP_CCR2_INPSEL_MASK 0x3000000u
#define CMP_CCR2_INPSEL_SHIFT 24u
#define CMP_CCR2_INPSEL_WIDTH 2u
#define CMP_CCR2_INPSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR2_INPSEL_SHIFT))&CMP_CCR2_INPSEL_MASK)
#define CMP_CCR2_MSEL_MASK 0x700000u
#define CMP_CCR2_MSEL_SHIFT 20u
#define CMP_CCR2_MSEL_WIDTH 3u
#define CMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR2_MSEL_SHIFT))&CMP_CCR2_MSEL_MASK)
#define CMP_CCR2_PSEL_MASK 0x70000u
#define CMP_CCR2_PSEL_SHIFT 16u
#define CMP_CCR2_PSEL_WIDTH 3u
#define CMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR2_PSEL_SHIFT))&CMP_CCR2_PSEL_MASK)
#define CMP_CCR2_HYSTCTR_MASK 0x30u
#define CMP_CCR2_HYSTCTR_SHIFT 4u
#define CMP_CCR2_HYSTCTR_WIDTH 2u
#define CMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR2_HYSTCTR_SHIFT))&CMP_CCR2_HYSTCTR_MASK)
#define CMP_CCR2_HPMD_MASK 0x1u
#define CMP_CCR2_HPMD_SHIFT 0u
#define CMP_CCR2_HPMD_WIDTH 1u
#define CMP_CCR2_HPMD(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR2_HPMD_SHIFT))&CMP_CCR2_HPMD_MASK)
/* CCR2 Reg Mask */
#define CMP_CCR2_MASK 0x33770031u
/* CCR3 Bit Fields */
#define CMP_CCR3_DAC_RDY_CNT_MASK 0xFFC0u
#define CMP_CCR3_DAC_RDY_CNT_SHIFT 6u
#define CMP_CCR3_DAC_RDY_CNT_WIDTH 10u
#define CMP_CCR3_DAC_RDY_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR3_DAC_RDY_CNT_SHIFT))&CMP_CCR3_DAC_RDY_CNT_MASK)
#define CMP_CCR3_DAC_TRANS_BYP_MASK 0x1u
#define CMP_CCR3_DAC_TRANS_BYP_SHIFT 0u
#define CMP_CCR3_DAC_TRANS_BYP_WIDTH 1u
#define CMP_CCR3_DAC_TRANS_BYP(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR3_DAC_TRANS_BYP_SHIFT))&CMP_CCR3_DAC_TRANS_BYP_MASK)
/* CCR3 Reg Mask */
#define CMP_CCR3_MASK 0x0000FFC1u
/* DCR Bit Fields */
#define CMP_DCR_DAC_DATA_MASK 0xFF0000u
#define CMP_DCR_DAC_DATA_SHIFT 16u
#define CMP_DCR_DAC_DATA_WIDTH 8u
#define CMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x))<<CMP_DCR_DAC_DATA_SHIFT))&CMP_DCR_DAC_DATA_MASK)
#define CMP_DCR_VRSEL_MASK 0x100u
#define CMP_DCR_VRSEL_SHIFT 8u
#define CMP_DCR_VRSEL_WIDTH 1u
#define CMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_DCR_VRSEL_SHIFT))&CMP_DCR_VRSEL_MASK)
#define CMP_DCR_DAC_EN_MASK 0x1u
#define CMP_DCR_DAC_EN_SHIFT 0u
#define CMP_DCR_DAC_EN_WIDTH 1u
#define CMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_DCR_DAC_EN_SHIFT))&CMP_DCR_DAC_EN_MASK)
/* DCR Reg Mask */
#define CMP_DCR_MASK 0x00FF0101u
/* IER Bit Fields */
#define CMP_IER_CSF_IE_MASK 0x4u
#define CMP_IER_CSF_IE_SHIFT 2u
#define CMP_IER_CSF_IE_WIDTH 1u
#define CMP_IER_CSF_IE(x) (((uint32_t)(((uint32_t)(x))<<CMP_IER_CSF_IE_SHIFT))&CMP_IER_CSF_IE_MASK)
#define CMP_IER_CFF_IE_MASK 0x2u
#define CMP_IER_CFF_IE_SHIFT 1u
#define CMP_IER_CFF_IE_WIDTH 1u
#define CMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x))<<CMP_IER_CFF_IE_SHIFT))&CMP_IER_CFF_IE_MASK)
#define CMP_IER_CFR_IE_MASK 0x1u
#define CMP_IER_CFR_IE_SHIFT 0u
#define CMP_IER_CFR_IE_WIDTH 1u
#define CMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x))<<CMP_IER_CFR_IE_SHIFT))&CMP_IER_CFR_IE_MASK)
/* IER Reg Mask */
#define CMP_IER_MASK 0x00000007u
/* CSR Bit Fields */
#define CMP_CSR_CMPOUT_FILTER_MASK 0x100u
#define CMP_CSR_CMPOUT_FILTER_SHIFT 8u
#define CMP_CSR_CMPOUT_FILTER_WIDTH 1u
#define CMP_CSR_CMPOUT_FILTER(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSR_CMPOUT_FILTER_SHIFT))&CMP_CSR_CMPOUT_FILTER_MASK)
#define CMP_CSR_CSF_MASK 0x4u
#define CMP_CSR_CSF_SHIFT 2u
#define CMP_CSR_CSF_WIDTH 1u
#define CMP_CSR_CSF(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSR_CSF_SHIFT))&CMP_CSR_CSF_MASK)
#define CMP_CSR_CFF_MASK 0x2u
#define CMP_CSR_CFF_SHIFT 1u
#define CMP_CSR_CFF_WIDTH 1u
#define CMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSR_CFF_SHIFT))&CMP_CSR_CFF_MASK)
#define CMP_CSR_CFR_MASK 0x1u
#define CMP_CSR_CFR_SHIFT 0u
#define CMP_CSR_CFR_WIDTH 1u
#define CMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSR_CFR_SHIFT))&CMP_CSR_CFR_MASK)
/* CSR Reg Mask */
#define CMP_CSR_MASK 0x00000107u
/* CSCR0 Bit Fields */
#define CMP_CSCR0_CS_INITMOD_MASK 0x3F0000u
#define CMP_CSCR0_CS_INITMOD_SHIFT 16u
#define CMP_CSCR0_CS_INITMOD_WIDTH 6u
#define CMP_CSCR0_CS_INITMOD(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR0_CS_INITMOD_SHIFT))&CMP_CSCR0_CS_INITMOD_MASK)
#define CMP_CSCR0_CS_NSAM_MASK 0x300u
#define CMP_CSCR0_CS_NSAM_SHIFT 8u
#define CMP_CSCR0_CS_NSAM_WIDTH 2u
#define CMP_CSCR0_CS_NSAM(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR0_CS_NSAM_SHIFT))&CMP_CSCR0_CS_NSAM_MASK)
#define CMP_CSCR0_CS_EN_MASK 0x1u
#define CMP_CSCR0_CS_EN_SHIFT 0u
#define CMP_CSCR0_CS_EN_WIDTH 1u
#define CMP_CSCR0_CS_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR0_CS_EN_SHIFT))&CMP_CSCR0_CS_EN_MASK)
/* CSCR0 Reg Mask */
#define CMP_CSCR0_MASK 0x003F0301u
/* CSCR1 Bit Fields */
#define CMP_CSCR1_FIXCH_MASK 0x700000u
#define CMP_CSCR1_FIXCH_SHIFT 20u
#define CMP_CSCR1_FIXCH_WIDTH 3u
#define CMP_CSCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_FIXCH_SHIFT))&CMP_CSCR1_FIXCH_MASK)
#define CMP_CSCR1_FIXP_MASK 0x10000u
#define CMP_CSCR1_FIXP_SHIFT 16u
#define CMP_CSCR1_FIXP_WIDTH 1u
#define CMP_CSCR1_FIXP(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_FIXP_SHIFT))&CMP_CSCR1_FIXP_MASK)
#define CMP_CSCR1_CS_CH7EN_MASK 0x80u
#define CMP_CSCR1_CS_CH7EN_SHIFT 7u
#define CMP_CSCR1_CS_CH7EN_WIDTH 1u
#define CMP_CSCR1_CS_CH7EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH7EN_SHIFT))&CMP_CSCR1_CS_CH7EN_MASK)
#define CMP_CSCR1_CS_CH6EN_MASK 0x40u
#define CMP_CSCR1_CS_CH6EN_SHIFT 6u
#define CMP_CSCR1_CS_CH6EN_WIDTH 1u
#define CMP_CSCR1_CS_CH6EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH6EN_SHIFT))&CMP_CSCR1_CS_CH6EN_MASK)
#define CMP_CSCR1_CS_CH5EN_MASK 0x20u
#define CMP_CSCR1_CS_CH5EN_SHIFT 5u
#define CMP_CSCR1_CS_CH5EN_WIDTH 1u
#define CMP_CSCR1_CS_CH5EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH5EN_SHIFT))&CMP_CSCR1_CS_CH5EN_MASK)
#define CMP_CSCR1_CS_CH4EN_MASK 0x10u
#define CMP_CSCR1_CS_CH4EN_SHIFT 4u
#define CMP_CSCR1_CS_CH4EN_WIDTH 1u
#define CMP_CSCR1_CS_CH4EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH4EN_SHIFT))&CMP_CSCR1_CS_CH4EN_MASK)
#define CMP_CSCR1_CS_CH3EN_MASK 0x8u
#define CMP_CSCR1_CS_CH3EN_SHIFT 3u
#define CMP_CSCR1_CS_CH3EN_WIDTH 1u
#define CMP_CSCR1_CS_CH3EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH3EN_SHIFT))&CMP_CSCR1_CS_CH3EN_MASK)
#define CMP_CSCR1_CS_CH2EN_MASK 0x4u
#define CMP_CSCR1_CS_CH2EN_SHIFT 2u
#define CMP_CSCR1_CS_CH2EN_WIDTH 1u
#define CMP_CSCR1_CS_CH2EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH2EN_SHIFT))&CMP_CSCR1_CS_CH2EN_MASK)
#define CMP_CSCR1_CS_CH1EN_MASK 0x2u
#define CMP_CSCR1_CS_CH1EN_SHIFT 1u
#define CMP_CSCR1_CS_CH1EN_WIDTH 1u
#define CMP_CSCR1_CS_CH1EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH1EN_SHIFT))&CMP_CSCR1_CS_CH1EN_MASK)
#define CMP_CSCR1_CS_CH0EN_MASK 0x1u
#define CMP_CSCR1_CS_CH0EN_SHIFT 0u
#define CMP_CSCR1_CS_CH0EN_WIDTH 1u
#define CMP_CSCR1_CS_CH0EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH0EN_SHIFT))&CMP_CSCR1_CS_CH0EN_MASK)
/* CSCR1 Reg Mask */
#define CMP_CSCR1_MASK 0x007100FFu
/* CSCSR Bit Fields */
#define CMP_CSCSR_CS_SWCLR_MASK 0x20000u
#define CMP_CSCSR_CS_SWCLR_SHIFT 17u
#define CMP_CSCSR_CS_SWCLR_WIDTH 1u
#define CMP_CSCSR_CS_SWCLR(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_SWCLR_SHIFT))&CMP_CSCSR_CS_SWCLR_MASK)
#define CMP_CSCSR_CS_ACLR_MASK 0x10000u
#define CMP_CSCSR_CS_ACLR_SHIFT 16u
#define CMP_CSCSR_CS_ACLR_WIDTH 1u
#define CMP_CSCSR_CS_ACLR(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_ACLR_SHIFT))&CMP_CSCSR_CS_ACLR_MASK)
#define CMP_CSCSR_CS_CH7OUT_MASK 0x80u
#define CMP_CSCSR_CS_CH7OUT_SHIFT 7u
#define CMP_CSCSR_CS_CH7OUT_WIDTH 1u
#define CMP_CSCSR_CS_CH7OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH7OUT_SHIFT))&CMP_CSCSR_CS_CH7OUT_MASK)
#define CMP_CSCSR_CS_CH6OUT_MASK 0x40u
#define CMP_CSCSR_CS_CH6OUT_SHIFT 6u
#define CMP_CSCSR_CS_CH6OUT_WIDTH 1u
#define CMP_CSCSR_CS_CH6OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH6OUT_SHIFT))&CMP_CSCSR_CS_CH6OUT_MASK)
#define CMP_CSCSR_CS_CH5OUT_MASK 0x20u
#define CMP_CSCSR_CS_CH5OUT_SHIFT 5u
#define CMP_CSCSR_CS_CH5OUT_WIDTH 1u
#define CMP_CSCSR_CS_CH5OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH5OUT_SHIFT))&CMP_CSCSR_CS_CH5OUT_MASK)
#define CMP_CSCSR_CS_CH4OUT_MASK 0x10u
#define CMP_CSCSR_CS_CH4OUT_SHIFT 4u
#define CMP_CSCSR_CS_CH4OUT_WIDTH 1u
#define CMP_CSCSR_CS_CH4OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH4OUT_SHIFT))&CMP_CSCSR_CS_CH4OUT_MASK)
#define CMP_CSCSR_CS_CH3OUT_MASK 0x8u
#define CMP_CSCSR_CS_CH3OUT_SHIFT 3u
#define CMP_CSCSR_CS_CH3OUT_WIDTH 1u
#define CMP_CSCSR_CS_CH3OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH3OUT_SHIFT))&CMP_CSCSR_CS_CH3OUT_MASK)
#define CMP_CSCSR_CS_CH2OUT_MASK 0x4u
#define CMP_CSCSR_CS_CH2OUT_SHIFT 2u
#define CMP_CSCSR_CS_CH2OUT_WIDTH 1u
#define CMP_CSCSR_CS_CH2OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH2OUT_SHIFT))&CMP_CSCSR_CS_CH2OUT_MASK)
#define CMP_CSCSR_CS_CH1OUT_MASK 0x2u
#define CMP_CSCSR_CS_CH1OUT_SHIFT 1u
#define CMP_CSCSR_CS_CH1OUT_WIDTH 1u
#define CMP_CSCSR_CS_CH1OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH1OUT_SHIFT))&CMP_CSCSR_CS_CH1OUT_MASK)
#define CMP_CSCSR_CS_CH0OUT_MASK 0x1u
#define CMP_CSCSR_CS_CH0OUT_SHIFT 0u
#define CMP_CSCSR_CS_CH0OUT_WIDTH 1u
#define CMP_CSCSR_CS_CH0OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH0OUT_SHIFT))&CMP_CSCSR_CS_CH0OUT_MASK)
/* CSCSR Reg Mask */
#define CMP_CSCSR_MASK 0x000300FFu
/* CSSR Bit Fields */
#define CMP_CSSR_CS_ACTIVE_MASK 0x10000u
#define CMP_CSSR_CS_ACTIVE_SHIFT 16u
#define CMP_CSSR_CS_ACTIVE_WIDTH 1u
#define CMP_CSSR_CS_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_ACTIVE_SHIFT))&CMP_CSSR_CS_ACTIVE_MASK)
#define CMP_CSSR_CS_CH7F_MASK 0x80u
#define CMP_CSSR_CS_CH7F_SHIFT 7u
#define CMP_CSSR_CS_CH7F_WIDTH 1u
#define CMP_CSSR_CS_CH7F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH7F_SHIFT))&CMP_CSSR_CS_CH7F_MASK)
#define CMP_CSSR_CS_CH6F_MASK 0x40u
#define CMP_CSSR_CS_CH6F_SHIFT 6u
#define CMP_CSSR_CS_CH6F_WIDTH 1u
#define CMP_CSSR_CS_CH6F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH6F_SHIFT))&CMP_CSSR_CS_CH6F_MASK)
#define CMP_CSSR_CS_CH5F_MASK 0x20u
#define CMP_CSSR_CS_CH5F_SHIFT 5u
#define CMP_CSSR_CS_CH5F_WIDTH 1u
#define CMP_CSSR_CS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH5F_SHIFT))&CMP_CSSR_CS_CH5F_MASK)
#define CMP_CSSR_CS_CH4F_MASK 0x10u
#define CMP_CSSR_CS_CH4F_SHIFT 4u
#define CMP_CSSR_CS_CH4F_WIDTH 1u
#define CMP_CSSR_CS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH4F_SHIFT))&CMP_CSSR_CS_CH4F_MASK)
#define CMP_CSSR_CS_CH3F_MASK 0x8u
#define CMP_CSSR_CS_CH3F_SHIFT 3u
#define CMP_CSSR_CS_CH3F_WIDTH 1u
#define CMP_CSSR_CS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH3F_SHIFT))&CMP_CSSR_CS_CH3F_MASK)
#define CMP_CSSR_CS_CH2F_MASK 0x4u
#define CMP_CSSR_CS_CH2F_SHIFT 2u
#define CMP_CSSR_CS_CH2F_WIDTH 1u
#define CMP_CSSR_CS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH2F_SHIFT))&CMP_CSSR_CS_CH2F_MASK)
#define CMP_CSSR_CS_CH1F_MASK 0x2u
#define CMP_CSSR_CS_CH1F_SHIFT 1u
#define CMP_CSSR_CS_CH1F_WIDTH 1u
#define CMP_CSSR_CS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH1F_SHIFT))&CMP_CSSR_CS_CH1F_MASK)
#define CMP_CSSR_CS_CH0F_MASK 0x1u
#define CMP_CSSR_CS_CH0F_SHIFT 0u
#define CMP_CSSR_CS_CH0F_WIDTH 1u
#define CMP_CSSR_CS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH0F_SHIFT))&CMP_CSSR_CS_CH0F_MASK)
/* CSSR Reg Mask */
#define CMP_CSSR_MASK 0x000100FFu
/*!
* @}
*/ /* end of group CMP_Register_Masks */
/*!
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_CMU_NU_Tztufn2_REGS_H_
#define _FC7240_CMU_NU_Tztufn2_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- CMU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMU_Peripheral_Access_Layer CMU Peripheral Access Layer
* @{
*/
/** CMU - Size of Registers Arrays */
/** CMU - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[8];
__IO uint32_t CTRL ; /* Control Register, offset: 0x8 */
uint8_t RESERVED_1[4];
__IO uint32_t MIN ; /* Minimum Threshold Register, offset: 0x10 */
__IO uint32_t MAX ; /* Maximum Threshold Register, offset: 0x14 */
__IO uint32_t REF_WINDOW ; /* Reference Window Register, offset: 0x18 */
__I uint32_t MON_CNT ; /* Monitor Counter Register, offset: 0x1C */
__IO uint32_t ST ; /* Status Register, offset: 0x20 */
__IO uint32_t PERIOD ; /* Period Monitor Mode Configuration Register, offset: 0x24 */
} CMU_Type, *CMU_MemMapPtr;
/** Number of instances of the CMU module. */
#define CMU_INSTANCE_COUNT (5u)
/* CMU - Peripheral instance base addresses */
/** Peripheral CMU0 base address */
#define CMU0_BASE (0x40031000u)
/** Peripheral CMU0 base pointer */
#define CMU0 ((CMU_Type *)CMU0_BASE)
/** Peripheral CMU1 base address */
#define CMU1_BASE (0x40032000u)
/** Peripheral CMU1 base pointer */
#define CMU1 ((CMU_Type *)CMU1_BASE)
/** Peripheral CMU2 base address */
#define CMU2_BASE (0x40033000u)
/** Peripheral CMU2 base pointer */
#define CMU2 ((CMU_Type *)CMU2_BASE)
/** Peripheral CMU3 base address */
#define CMU3_BASE (0x40034000u)
/** Peripheral CMU3 base pointer */
#define CMU3 ((CMU_Type *)CMU3_BASE)
/** Peripheral CMU4 base address */
#define CMU4_BASE (0x40035000u)
/** Peripheral CMU4 base pointer */
#define CMU4 ((CMU_Type *)CMU4_BASE)
/** Array initializer of CMU peripheral base addresses */
#define CMU_BASE_ADDRS {CMU0_BASE, CMU1_BASE, CMU2_BASE, CMU3_BASE, CMU4_BASE}
/** Array initializer of CMU peripheral base pointers */
#define CMU_BASE_PTRS {CMU0, CMU1, CMU2, CMU3, CMU4}
// need fill by yourself
///** Number of interrupt vector arrays for the CMU module. */
//#define CMU_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the CMU module. */
//#define CMU_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the CMU peripheral type */
//#define CMU_IRQS {CMU0_IRQn, CMU1_IRQn, CMU2_IRQn, CMU3_IRQn, CMU4_IRQn}
/* ----------------------------------------------------------------------------
-- CMU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMU_Register_Masks CMU Register Masks
* @{
*/
/* CTRL Bit Fields */
#define CMU_CTRL_REF_DIV_MASK 0x70000u
#define CMU_CTRL_REF_DIV_SHIFT 16u
#define CMU_CTRL_REF_DIV_WIDTH 3u
#define CMU_CTRL_REF_DIV(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_REF_DIV_SHIFT))&CMU_CTRL_REF_DIV_MASK)
#define CMU_CTRL_IRQ_EN_MASK 0x40u
#define CMU_CTRL_IRQ_EN_SHIFT 6u
#define CMU_CTRL_IRQ_EN_WIDTH 1u
#define CMU_CTRL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_IRQ_EN_SHIFT))&CMU_CTRL_IRQ_EN_MASK)
#define CMU_CTRL_RESTART_EN_MASK 0x20u
#define CMU_CTRL_RESTART_EN_SHIFT 5u
#define CMU_CTRL_RESTART_EN_WIDTH 1u
#define CMU_CTRL_RESTART_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_RESTART_EN_SHIFT))&CMU_CTRL_RESTART_EN_MASK)
#define CMU_CTRL_LP_EN_MASK 0x10u
#define CMU_CTRL_LP_EN_SHIFT 4u
#define CMU_CTRL_LP_EN_WIDTH 1u
#define CMU_CTRL_LP_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_LP_EN_SHIFT))&CMU_CTRL_LP_EN_MASK)
#define CMU_CTRL_STOP_EN_MASK 0x8u
#define CMU_CTRL_STOP_EN_SHIFT 3u
#define CMU_CTRL_STOP_EN_WIDTH 1u
#define CMU_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_STOP_EN_SHIFT))&CMU_CTRL_STOP_EN_MASK)
#define CMU_CTRL_SW_RST_MASK 0x2u
#define CMU_CTRL_SW_RST_SHIFT 1u
#define CMU_CTRL_SW_RST_WIDTH 1u
#define CMU_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_SW_RST_SHIFT))&CMU_CTRL_SW_RST_MASK)
#define CMU_CTRL_ENABLE_MASK 0x1u
#define CMU_CTRL_ENABLE_SHIFT 0u
#define CMU_CTRL_ENABLE_WIDTH 1u
#define CMU_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_ENABLE_SHIFT))&CMU_CTRL_ENABLE_MASK)
/* CTRL Reg Mask */
#define CMU_CTRL_MASK 0x0007007Bu
/* MIN Bit Fields */
#define CMU_MIN_MIN_MASK 0xFFFFFFu
#define CMU_MIN_MIN_SHIFT 0u
#define CMU_MIN_MIN_WIDTH 24u
#define CMU_MIN_MIN(x) (((uint32_t)(((uint32_t)(x))<<CMU_MIN_MIN_SHIFT))&CMU_MIN_MIN_MASK)
/* MIN Reg Mask */
#define CMU_MIN_MASK 0x00FFFFFFu
/* MAX Bit Fields */
#define CMU_MAX_MAX_MASK 0xFFFFFFu
#define CMU_MAX_MAX_SHIFT 0u
#define CMU_MAX_MAX_WIDTH 24u
#define CMU_MAX_MAX(x) (((uint32_t)(((uint32_t)(x))<<CMU_MAX_MAX_SHIFT))&CMU_MAX_MAX_MASK)
/* MAX Reg Mask */
#define CMU_MAX_MASK 0x00FFFFFFu
/* REF_WINDOW Bit Fields */
#define CMU_REF_WINDOW_REF_WINDOW_MASK 0xFFFFFFu
#define CMU_REF_WINDOW_REF_WINDOW_SHIFT 0u
#define CMU_REF_WINDOW_REF_WINDOW_WIDTH 24u
#define CMU_REF_WINDOW_REF_WINDOW(x) (((uint32_t)(((uint32_t)(x))<<CMU_REF_WINDOW_REF_WINDOW_SHIFT))&CMU_REF_WINDOW_REF_WINDOW_MASK)
/* REF_WINDOW Reg Mask */
#define CMU_REF_WINDOW_MASK 0x00FFFFFFu
/* MON_CNT Bit Fields */
#define CMU_MON_CNT_MON_CNT_MASK 0xFFFFFFu
#define CMU_MON_CNT_MON_CNT_SHIFT 0u
#define CMU_MON_CNT_MON_CNT_WIDTH 24u
#define CMU_MON_CNT_MON_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMU_MON_CNT_MON_CNT_SHIFT))&CMU_MON_CNT_MON_CNT_MASK)
/* MON_CNT Reg Mask */
#define CMU_MON_CNT_MASK 0x00FFFFFFu
/* ST Bit Fields */
#define CMU_ST_LOC_MASK 0x8000u
#define CMU_ST_LOC_SHIFT 15u
#define CMU_ST_LOC_WIDTH 1u
#define CMU_ST_LOC(x) (((uint32_t)(((uint32_t)(x))<<CMU_ST_LOC_SHIFT))&CMU_ST_LOC_MASK)
#define CMU_ST_MIS_MASK 0x100u
#define CMU_ST_MIS_SHIFT 8u
#define CMU_ST_MIS_WIDTH 1u
#define CMU_ST_MIS(x) (((uint32_t)(((uint32_t)(x))<<CMU_ST_MIS_SHIFT))&CMU_ST_MIS_MASK)
/* ST Reg Mask */
#define CMU_ST_MASK 0x00008100u
/* PERIOD Bit Fields */
#define CMU_PERIOD_WINDOW_MASK 0xF0000u
#define CMU_PERIOD_WINDOW_SHIFT 16u
#define CMU_PERIOD_WINDOW_WIDTH 4u
#define CMU_PERIOD_WINDOW(x) (((uint32_t)(((uint32_t)(x))<<CMU_PERIOD_WINDOW_SHIFT))&CMU_PERIOD_WINDOW_MASK)
#define CMU_PERIOD_EN_MASK 0x1u
#define CMU_PERIOD_EN_SHIFT 0u
#define CMU_PERIOD_EN_WIDTH 1u
#define CMU_PERIOD_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_PERIOD_EN_SHIFT))&CMU_PERIOD_EN_MASK)
/* PERIOD Reg Mask */
#define CMU_PERIOD_MASK 0x000F0001u
/*!
* @}
*/ /* end of group CMU_Register_Masks */
/*!
* @}
*/ /* end of group CMU_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_CORDIC_NU_Tztufn44_REGS_H_
#define _FC7240_CORDIC_NU_Tztufn44_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- CORDIC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CORDIC_Peripheral_Access_Layer CORDIC Peripheral Access Layer
* @{
*/
/** CORDIC - Size of Registers Arrays */
/** CORDIC - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL ; /* Control Register, offset: 0x0 */
uint8_t RESERVED_0[12];
__IO uint32_t X_INPUT ; /* X-axis Input Data Register, offset: 0x10 */
__IO uint32_t Y_INPUT ; /* Y-axis Input Data Register, offset: 0x14 */
__IO uint32_t Z_INPUT ; /* Z-axis Input Data Register, offset: 0x18 */
uint8_t RESERVED_1[4];
__IO uint32_t STAT ; /* State Register, offset: 0x20 */
__I uint32_t X_OUTPUT ; /* X-axis Output Data Register, offset: 0x24 */
__I uint32_t Y_OUTPUT ; /* Y-axis Output Data Register, offset: 0x28 */
__I uint32_t Z_OUTPUT ; /* Z-axis Output Data Register, offset: 0x2C */
} CORDIC_Type, *CORDIC_MemMapPtr;
/** Number of instances of the CORDIC module. */
#define CORDIC_INSTANCE_COUNT (1u)
/* CORDIC - Peripheral instance base addresses */
/** Peripheral CORDIC base address */
#define CORDIC_BASE (0x4002b000u)
/** Peripheral CORDIC base pointer */
#define CORDIC ((CORDIC_Type *)CORDIC_BASE)
/** Array initializer of CORDIC peripheral base addresses */
#define CORDIC_BASE_ADDRS {CORDIC_BASE}
/** Array initializer of CORDIC peripheral base pointers */
#define CORDIC_BASE_PTRS {CORDIC}
// need fill by yourself
///** Number of interrupt vector arrays for the CORDIC module. */
//#define CORDIC_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the CORDIC module. */
//#define CORDIC_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the CORDIC peripheral type */
//#define CORDIC_IRQS {CORDIC_IRQn}
/* ----------------------------------------------------------------------------
-- CORDIC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CORDIC_Register_Masks CORDIC Register Masks
* @{
*/
/* CTRL Bit Fields */
#define CORDIC_CTRL_IE_MASK 0x80000000u
#define CORDIC_CTRL_IE_SHIFT 31u
#define CORDIC_CTRL_IE_WIDTH 1u
#define CORDIC_CTRL_IE(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_CTRL_IE_SHIFT))&CORDIC_CTRL_IE_MASK)
#define CORDIC_CTRL_SCALE_MASK 0x380u
#define CORDIC_CTRL_SCALE_SHIFT 7u
#define CORDIC_CTRL_SCALE_WIDTH 3u
#define CORDIC_CTRL_SCALE(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_CTRL_SCALE_SHIFT))&CORDIC_CTRL_SCALE_MASK)
#define CORDIC_CTRL_ITER_MASK 0x30u
#define CORDIC_CTRL_ITER_SHIFT 4u
#define CORDIC_CTRL_ITER_WIDTH 2u
#define CORDIC_CTRL_ITER(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_CTRL_ITER_SHIFT))&CORDIC_CTRL_ITER_MASK)
#define CORDIC_CTRL_OS_MASK 0xEu
#define CORDIC_CTRL_OS_SHIFT 1u
#define CORDIC_CTRL_OS_WIDTH 3u
#define CORDIC_CTRL_OS(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_CTRL_OS_SHIFT))&CORDIC_CTRL_OS_MASK)
#define CORDIC_CTRL_MODE_MASK 0x1u
#define CORDIC_CTRL_MODE_SHIFT 0u
#define CORDIC_CTRL_MODE_WIDTH 1u
#define CORDIC_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_CTRL_MODE_SHIFT))&CORDIC_CTRL_MODE_MASK)
/* CTRL Reg Mask */
#define CORDIC_CTRL_MASK 0x800003BFu
/* X_INPUT Bit Fields */
#define CORDIC_X_INPUT_DATA_MASK 0xFFFFFFFFu
#define CORDIC_X_INPUT_DATA_SHIFT 0u
#define CORDIC_X_INPUT_DATA_WIDTH 32u
#define CORDIC_X_INPUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_X_INPUT_DATA_SHIFT))&CORDIC_X_INPUT_DATA_MASK)
/* X_INPUT Reg Mask */
#define CORDIC_X_INPUT_MASK 0xFFFFFFFFu
/* Y_INPUT Bit Fields */
#define CORDIC_Y_INPUT_DATA_MASK 0xFFFFFFFFu
#define CORDIC_Y_INPUT_DATA_SHIFT 0u
#define CORDIC_Y_INPUT_DATA_WIDTH 32u
#define CORDIC_Y_INPUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_Y_INPUT_DATA_SHIFT))&CORDIC_Y_INPUT_DATA_MASK)
/* Y_INPUT Reg Mask */
#define CORDIC_Y_INPUT_MASK 0xFFFFFFFFu
/* Z_INPUT Bit Fields */
#define CORDIC_Z_INPUT_DATA_MASK 0xFFFFFFFFu
#define CORDIC_Z_INPUT_DATA_SHIFT 0u
#define CORDIC_Z_INPUT_DATA_WIDTH 32u
#define CORDIC_Z_INPUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_Z_INPUT_DATA_SHIFT))&CORDIC_Z_INPUT_DATA_MASK)
/* Z_INPUT Reg Mask */
#define CORDIC_Z_INPUT_MASK 0xFFFFFFFFu
/* STAT Bit Fields */
#define CORDIC_STAT_DONE_MASK 0x1u
#define CORDIC_STAT_DONE_SHIFT 0u
#define CORDIC_STAT_DONE_WIDTH 1u
#define CORDIC_STAT_DONE(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_STAT_DONE_SHIFT))&CORDIC_STAT_DONE_MASK)
/* STAT Reg Mask */
#define CORDIC_STAT_MASK 0x00000001u
/* X_OUTPUT Bit Fields */
#define CORDIC_X_OUTPUT_DATA_MASK 0xFFFFFFFFu
#define CORDIC_X_OUTPUT_DATA_SHIFT 0u
#define CORDIC_X_OUTPUT_DATA_WIDTH 32u
#define CORDIC_X_OUTPUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_X_OUTPUT_DATA_SHIFT))&CORDIC_X_OUTPUT_DATA_MASK)
/* X_OUTPUT Reg Mask */
#define CORDIC_X_OUTPUT_MASK 0xFFFFFFFFu
/* Y_OUTPUT Bit Fields */
#define CORDIC_Y_OUTPUT_DATA_MASK 0xFFFFFFFFu
#define CORDIC_Y_OUTPUT_DATA_SHIFT 0u
#define CORDIC_Y_OUTPUT_DATA_WIDTH 32u
#define CORDIC_Y_OUTPUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_Y_OUTPUT_DATA_SHIFT))&CORDIC_Y_OUTPUT_DATA_MASK)
/* Y_OUTPUT Reg Mask */
#define CORDIC_Y_OUTPUT_MASK 0xFFFFFFFFu
/* Z_OUTPUT Bit Fields */
#define CORDIC_Z_OUTPUT_DATA_MASK 0xFFFFFFFFu
#define CORDIC_Z_OUTPUT_DATA_SHIFT 0u
#define CORDIC_Z_OUTPUT_DATA_WIDTH 32u
#define CORDIC_Z_OUTPUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_Z_OUTPUT_DATA_SHIFT))&CORDIC_Z_OUTPUT_DATA_MASK)
/* Z_OUTPUT Reg Mask */
#define CORDIC_Z_OUTPUT_MASK 0xFFFFFFFFu
/*!
* @}
*/ /* end of group CORDIC_Register_Masks */
/*!
* @}
*/ /* end of group CORDIC_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_CPM_NU_Tztufn6_REGS_H_
#define _FC7240_CPM_NU_Tztufn6_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- CPM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CPM_Peripheral_Access_Layer CPM Peripheral Access Layer
* @{
*/
/** CPM - Size of Registers Arrays */
/** CPM - Register Layout Typedef */
typedef struct {
__IO uint32_t FISCR ; /* FPU Interrupt Status and Control Register, offset: 0x0 */
__IO uint32_t MISCR ; /* Miscellaneous Control Register, offset: 0x4 */
uint8_t RESERVED_0[24];
__IO uint32_t TCMRCR ; /* TCM Retry Control Register, offset: 0x20 */
} CPM_Type, *CPM_MemMapPtr;
/** Number of instances of the CPM module. */
#define CPM_INSTANCE_COUNT (1u)
/* CPM - Peripheral instance base addresses */
/** Peripheral CPM base address */
#define CPM_BASE (0xE0080000u)
/** Peripheral CPM base pointer */
#define CPM ((CPM_Type *)CPM_BASE)
/** Array initializer of CPM peripheral base addresses */
#define CPM_BASE_ADDRS {CPM_BASE}
/** Array initializer of CPM peripheral base pointers */
#define CPM_BASE_PTRS {CPM}
// need fill by yourself
///** Number of interrupt vector arrays for the CPM module. */
//#define CPM_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the CPM module. */
//#define CPM_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the CPM peripheral type */
//#define CPM_IRQS {CPM_IRQn}
/* ----------------------------------------------------------------------------
-- CPM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CPM_Register_Masks CPM Register Masks
* @{
*/
/* FISCR Bit Fields */
#define CPM_FISCR_FIXCE_MASK 0x200000u
#define CPM_FISCR_FIXCE_SHIFT 21u
#define CPM_FISCR_FIXCE_WIDTH 1u
#define CPM_FISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIXCE_SHIFT))&CPM_FISCR_FIXCE_MASK)
#define CPM_FISCR_FIDCE_MASK 0x100000u
#define CPM_FISCR_FIDCE_SHIFT 20u
#define CPM_FISCR_FIDCE_WIDTH 1u
#define CPM_FISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIDCE_SHIFT))&CPM_FISCR_FIDCE_MASK)
#define CPM_FISCR_FOFCE_MASK 0x80000u
#define CPM_FISCR_FOFCE_SHIFT 19u
#define CPM_FISCR_FOFCE_WIDTH 1u
#define CPM_FISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FOFCE_SHIFT))&CPM_FISCR_FOFCE_MASK)
#define CPM_FISCR_FUFCE_MASK 0x40000u
#define CPM_FISCR_FUFCE_SHIFT 18u
#define CPM_FISCR_FUFCE_WIDTH 1u
#define CPM_FISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FUFCE_SHIFT))&CPM_FISCR_FUFCE_MASK)
#define CPM_FISCR_FDZCE_MASK 0x20000u
#define CPM_FISCR_FDZCE_SHIFT 17u
#define CPM_FISCR_FDZCE_WIDTH 1u
#define CPM_FISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FDZCE_SHIFT))&CPM_FISCR_FDZCE_MASK)
#define CPM_FISCR_FIOCE_MASK 0x10000u
#define CPM_FISCR_FIOCE_SHIFT 16u
#define CPM_FISCR_FIOCE_WIDTH 1u
#define CPM_FISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIOCE_SHIFT))&CPM_FISCR_FIOCE_MASK)
#define CPM_FISCR_FIXC_MASK 0x20u
#define CPM_FISCR_FIXC_SHIFT 5u
#define CPM_FISCR_FIXC_WIDTH 1u
#define CPM_FISCR_FIXC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIXC_SHIFT))&CPM_FISCR_FIXC_MASK)
#define CPM_FISCR_FIDC_MASK 0x10u
#define CPM_FISCR_FIDC_SHIFT 4u
#define CPM_FISCR_FIDC_WIDTH 1u
#define CPM_FISCR_FIDC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIDC_SHIFT))&CPM_FISCR_FIDC_MASK)
#define CPM_FISCR_FOFC_MASK 0x8u
#define CPM_FISCR_FOFC_SHIFT 3u
#define CPM_FISCR_FOFC_WIDTH 1u
#define CPM_FISCR_FOFC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FOFC_SHIFT))&CPM_FISCR_FOFC_MASK)
#define CPM_FISCR_FUFC_MASK 0x4u
#define CPM_FISCR_FUFC_SHIFT 2u
#define CPM_FISCR_FUFC_WIDTH 1u
#define CPM_FISCR_FUFC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FUFC_SHIFT))&CPM_FISCR_FUFC_MASK)
#define CPM_FISCR_FDZC_MASK 0x2u
#define CPM_FISCR_FDZC_SHIFT 1u
#define CPM_FISCR_FDZC_WIDTH 1u
#define CPM_FISCR_FDZC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FDZC_SHIFT))&CPM_FISCR_FDZC_MASK)
#define CPM_FISCR_FIOC_MASK 0x1u
#define CPM_FISCR_FIOC_SHIFT 0u
#define CPM_FISCR_FIOC_WIDTH 1u
#define CPM_FISCR_FIOC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIOC_SHIFT))&CPM_FISCR_FIOC_MASK)
/* FISCR Reg Mask */
#define CPM_FISCR_MASK 0x003F003Fu
/* MISCR Bit Fields */
#define CPM_MISCR_AHBS_PRIORITY_MASK 0x1u
#define CPM_MISCR_AHBS_PRIORITY_SHIFT 0u
#define CPM_MISCR_AHBS_PRIORITY_WIDTH 1u
#define CPM_MISCR_AHBS_PRIORITY(x) (((uint32_t)(((uint32_t)(x))<<CPM_MISCR_AHBS_PRIORITY_SHIFT))&CPM_MISCR_AHBS_PRIORITY_MASK)
/* MISCR Reg Mask */
#define CPM_MISCR_MASK 0x00000001u
/* TCMRCR Bit Fields */
#define CPM_TCMRCR_D1RBCLR_MASK 0x4000u
#define CPM_TCMRCR_D1RBCLR_SHIFT 14u
#define CPM_TCMRCR_D1RBCLR_WIDTH 1u
#define CPM_TCMRCR_D1RBCLR(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D1RBCLR_SHIFT))&CPM_TCMRCR_D1RBCLR_MASK)
#define CPM_TCMRCR_D0RBCLR_MASK 0x2000u
#define CPM_TCMRCR_D0RBCLR_SHIFT 13u
#define CPM_TCMRCR_D0RBCLR_WIDTH 1u
#define CPM_TCMRCR_D0RBCLR(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D0RBCLR_SHIFT))&CPM_TCMRCR_D0RBCLR_MASK)
#define CPM_TCMRCR_IRBCLR_MASK 0x1000u
#define CPM_TCMRCR_IRBCLR_SHIFT 12u
#define CPM_TCMRCR_IRBCLR_WIDTH 1u
#define CPM_TCMRCR_IRBCLR(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_IRBCLR_SHIFT))&CPM_TCMRCR_IRBCLR_MASK)
#define CPM_TCMRCR_D1RBVLD_MASK 0x400u
#define CPM_TCMRCR_D1RBVLD_SHIFT 10u
#define CPM_TCMRCR_D1RBVLD_WIDTH 1u
#define CPM_TCMRCR_D1RBVLD(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D1RBVLD_SHIFT))&CPM_TCMRCR_D1RBVLD_MASK)
#define CPM_TCMRCR_D0RBVLD_MASK 0x200u
#define CPM_TCMRCR_D0RBVLD_SHIFT 9u
#define CPM_TCMRCR_D0RBVLD_WIDTH 1u
#define CPM_TCMRCR_D0RBVLD(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D0RBVLD_SHIFT))&CPM_TCMRCR_D0RBVLD_MASK)
#define CPM_TCMRCR_IRBVLD_MASK 0x100u
#define CPM_TCMRCR_IRBVLD_SHIFT 8u
#define CPM_TCMRCR_IRBVLD_WIDTH 1u
#define CPM_TCMRCR_IRBVLD(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_IRBVLD_SHIFT))&CPM_TCMRCR_IRBVLD_MASK)
#define CPM_TCMRCR_D1RBIE_MASK 0x40u
#define CPM_TCMRCR_D1RBIE_SHIFT 6u
#define CPM_TCMRCR_D1RBIE_WIDTH 1u
#define CPM_TCMRCR_D1RBIE(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D1RBIE_SHIFT))&CPM_TCMRCR_D1RBIE_MASK)
#define CPM_TCMRCR_D0RBIE_MASK 0x20u
#define CPM_TCMRCR_D0RBIE_SHIFT 5u
#define CPM_TCMRCR_D0RBIE_WIDTH 1u
#define CPM_TCMRCR_D0RBIE(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D0RBIE_SHIFT))&CPM_TCMRCR_D0RBIE_MASK)
#define CPM_TCMRCR_IRBIE_MASK 0x10u
#define CPM_TCMRCR_IRBIE_SHIFT 4u
#define CPM_TCMRCR_IRBIE_WIDTH 1u
#define CPM_TCMRCR_IRBIE(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_IRBIE_SHIFT))&CPM_TCMRCR_IRBIE_MASK)
#define CPM_TCMRCR_D1RBAC_MASK 0x4u
#define CPM_TCMRCR_D1RBAC_SHIFT 2u
#define CPM_TCMRCR_D1RBAC_WIDTH 1u
#define CPM_TCMRCR_D1RBAC(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D1RBAC_SHIFT))&CPM_TCMRCR_D1RBAC_MASK)
#define CPM_TCMRCR_D0RBAC_MASK 0x2u
#define CPM_TCMRCR_D0RBAC_SHIFT 1u
#define CPM_TCMRCR_D0RBAC_WIDTH 1u
#define CPM_TCMRCR_D0RBAC(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D0RBAC_SHIFT))&CPM_TCMRCR_D0RBAC_MASK)
#define CPM_TCMRCR_IRBAC_MASK 0x1u
#define CPM_TCMRCR_IRBAC_SHIFT 0u
#define CPM_TCMRCR_IRBAC_WIDTH 1u
#define CPM_TCMRCR_IRBAC(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_IRBAC_SHIFT))&CPM_TCMRCR_IRBAC_MASK)
/* TCMRCR Reg Mask */
#define CPM_TCMRCR_MASK 0x00007777u
/*!
* @}
*/ /* end of group CPM_Register_Masks */
/*!
* @}
*/ /* end of group CPM_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef DRIVER_CRC_H
#define DRIVER_CRC_H
/* ----------------------------------------------------------------------------
-- CRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
* @{
*/
/** CRC - Size of Registers Arrays */
/** CRC - Register Layout Typedef */
typedef struct {
union {
__IO uint32_t uDATA; /** CRC Data union */
struct {
__IO uint16_t L; /** CRC_DATAL register., offset: 0x0 */
__IO uint16_t H; /** CRC_DATAH register., offset: 0x2 */
} tDATA_16;
struct {
__IO uint8_t LL; /** CRC_DATALL register., offset: 0x0 */
__IO uint8_t LU; /** CRC_DATALU register., offset: 0x1 */
__IO uint8_t HL; /** CRC_DATAHL register., offset: 0x2 */
__IO uint8_t HU; /** CRC_DATAHU register., offset: 0x3 */
} tDATA_8;
} DATA;
__IO uint32_t POLY ; /* CRC Polynomial Register, offset: 0x4 */
__IO uint32_t CR ; /* CRC Control Register, offset: 0x8 */
__IO uint32_t SDAT ; /* CRC Data Bit Swap Register, offset: 0xC */
} CRC_Type, *CRC_MemMapPtr;
/** Number of instances of the CRC module. */
#define CRC_INSTANCE_COUNT (1u)
/* CRC - Peripheral instance base addresses */
/** Peripheral CRC base address */
#define CRC_BASE (0x4002a000u)
/** Peripheral CRC base pointer */
#define CRC ((CRC_Type *)CRC_BASE)
/** Array initializer of CRC peripheral base addresses */
#define CRC_BASE_ADDRS {CRC_BASE}
/** Array initializer of CRC peripheral base pointers */
#define CRC_BASE_PTRS {CRC}
/* ----------------------------------------------------------------------------
-- CRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CRC_Register_Masks CRC Register Masks
* @{
*/
/* DATA Bit Fields */
#define CRC_DATA_HU_MASK 0xFF000000u
#define CRC_DATA_HU_SHIFT 24u
#define CRC_DATA_HU_WIDTH 8u
#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
#define CRC_DATA_HL_MASK 0xFF0000u
#define CRC_DATA_HL_SHIFT 16u
#define CRC_DATA_HL_WIDTH 8u
#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
#define CRC_DATA_LU_MASK 0xFF00u
#define CRC_DATA_LU_SHIFT 8u
#define CRC_DATA_LU_WIDTH 8u
#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
#define CRC_DATA_LL_MASK 0xFFu
#define CRC_DATA_LL_SHIFT 0u
#define CRC_DATA_LL_WIDTH 8u
#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
/* DATA Reg Mask */
#define CRC_DATA_MASK 0xFFFFFFFFu
/* POLY Bit Fields */
#define CRC_POLY_HIGH_MASK 0xFFFF0000u
#define CRC_POLY_HIGH_SHIFT 16u
#define CRC_POLY_HIGH_WIDTH 16u
#define CRC_POLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_POLY_HIGH_SHIFT))&CRC_POLY_HIGH_MASK)
#define CRC_POLY_LOW_MASK 0xFFFFu
#define CRC_POLY_LOW_SHIFT 0u
#define CRC_POLY_LOW_WIDTH 16u
#define CRC_POLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_POLY_LOW_SHIFT))&CRC_POLY_LOW_MASK)
/* POLY Reg Mask */
#define CRC_POLY_MASK 0xFFFFFFFFu
/* CR Bit Fields */
#define CRC_CR_DSW_MASK 0xC0000000u
#define CRC_CR_DSW_SHIFT 30u
#define CRC_CR_DSW_WIDTH 2u
#define CRC_CR_DSW(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_DSW_SHIFT))&CRC_CR_DSW_MASK)
#define CRC_CR_DSR_MASK 0x30000000u
#define CRC_CR_DSR_SHIFT 28u
#define CRC_CR_DSR_WIDTH 2u
#define CRC_CR_DSR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_DSR_SHIFT))&CRC_CR_DSR_MASK)
#define CRC_CR_TCRC8_MASK 0x8000000u
#define CRC_CR_TCRC8_SHIFT 27u
#define CRC_CR_TCRC8_WIDTH 1u
#define CRC_CR_TCRC8(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_TCRC8_SHIFT))&CRC_CR_TCRC8_MASK)
#define CRC_CR_FXOR_MASK 0x4000000u
#define CRC_CR_FXOR_SHIFT 26u
#define CRC_CR_FXOR_WIDTH 1u
#define CRC_CR_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_FXOR_SHIFT))&CRC_CR_FXOR_MASK)
#define CRC_CR_WAS_MASK 0x2000000u
#define CRC_CR_WAS_SHIFT 25u
#define CRC_CR_WAS_WIDTH 1u
#define CRC_CR_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_WAS_SHIFT))&CRC_CR_WAS_MASK)
#define CRC_CR_TCRC_MASK 0x1000000u
#define CRC_CR_TCRC_SHIFT 24u
#define CRC_CR_TCRC_WIDTH 1u
#define CRC_CR_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_TCRC_SHIFT))&CRC_CR_TCRC_MASK)
/* CR Reg Mask */
#define CRC_CR_MASK 0xFF000000u
/* SDAT Bit Fields */
#define CRC_SDAT_HIGH_MASK 0xFFFF0000u
#define CRC_SDAT_HIGH_SHIFT 16u
#define CRC_SDAT_HIGH_WIDTH 16u
#define CRC_SDAT_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_SDAT_HIGH_SHIFT))&CRC_SDAT_HIGH_MASK)
#define CRC_SDAT_LOW_MASK 0xFFFFu
#define CRC_SDAT_LOW_SHIFT 0u
#define CRC_SDAT_LOW_WIDTH 16u
#define CRC_SDAT_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_SDAT_LOW_SHIFT))&CRC_SDAT_LOW_MASK)
/* SDAT Reg Mask */
#define CRC_SDAT_MASK 0xFFFFFFFFu
/*!
* @}
*/ /* end of group CRC_Register_Masks */
/*!
* @}
*/ /* end of group CRC_Peripheral_Access_Layer */
#endif

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#ifndef _FC7240_DMAMUX_NU_Tztufn36_REGS_H_
#define _FC7240_DMAMUX_NU_Tztufn36_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- DMAMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
* @{
*/
/** DMAMUX - Size of Registers Arrays */
/** DMAMUX - Register Layout Typedef */
#define DMAMUX_CHCFG_COUNT 16
#define DMAMUX_CHTRG_TRG_COUNT 4
typedef struct {
__IO uint8_t CHCFG[DMAMUX_CHCFG_COUNT] ; /* Channel N Configuration Register, offset: 0x0 */
uint8_t RESERVED_0[16];
__IO uint8_t CHTRG ; /* Channel N Trigger Register, offset: 0x20 */
} DMAMUX_Type, *DMAMUX_MemMapPtr;
/** Number of instances of the DMAMUX module. */
#define DMAMUX_INSTANCE_COUNT (1u)
/* DMAMUX - Peripheral instance base addresses */
/** Peripheral DMAMUX base address */
#define DMAMUX_BASE (0x4000a000u)
/** Peripheral DMAMUX base pointer */
#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
/** Array initializer of DMAMUX peripheral base addresses */
#define DMAMUX_BASE_ADDRS {DMAMUX_BASE}
/** Array initializer of DMAMUX peripheral base pointers */
#define DMAMUX_BASE_PTRS {DMAMUX}
// need fill by yourself
///** Number of interrupt vector arrays for the DMAMUX module. */
//#define DMAMUX_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the DMAMUX module. */
//#define DMAMUX_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the DMAMUX peripheral type */
//#define DMAMUX_IRQS {DMAMUX_IRQn}
/* ----------------------------------------------------------------------------
-- DMAMUX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
* @{
*/
/* CHCFG Bit Fields */
#define DMAMUX_CHCFG_ENBL_MASK 0x80u
#define DMAMUX_CHCFG_ENBL_SHIFT 7u
#define DMAMUX_CHCFG_ENBL_WIDTH 1u
#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
#define DMAMUX_CHCFG_SOURCE_MASK 0x7Fu
#define DMAMUX_CHCFG_SOURCE_SHIFT 0u
#define DMAMUX_CHCFG_SOURCE_WIDTH 7u
#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
/* CHCFG Reg Mask */
#define DMAMUX_CHCFG_MASK 0xFFu
/* CHTRG Bit Fields */
#define DMAMUX_CHTRG_TRIG_MASK 0x1u
#define DMAMUX_CHTRG_TRIG_SHIFT 0u
#define DMAMUX_CHTRG_TRIG_WIDTH 1u
#define DMAMUX_CHTRG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHTRG_TRIG_SHIFT))&DMAMUX_CHTRG_TRIG_MASK)
/* CHTRG Reg Mask */
#define DMAMUX_CHTRG_MASK 0x0Fu
/*!
* @}
*/ /* end of group DMAMUX_Register_Masks */
/*!
* @}
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_EIM_NU_Tztufn26_REGS_H_
#define _FC7240_EIM_NU_Tztufn26_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- EIM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer
* @{
*/
/** EIM - Size of Registers Arrays */
/** EIM - Register Layout Typedef */
#define EIM_CTRL_REG_COUNT 83
#define EIM_BUS_REG_COUNT 4
typedef struct {
__IO uint32_t CR ; /* Configuration Register, offset: 0x0 */
uint8_t RESERVED_0[12];
__IO uint32_t CTRL_REG[EIM_CTRL_REG_COUNT] ; /* Channel N Control Register, offset: 0x10 */
uint8_t RESERVED_1[676];
__IO uint32_t CPU0_LOCKSTEP ; /* CPU0 LOCKSTEP Error Injection Register, offset: 0x400 */
uint8_t RESERVED_2[4];
__IO uint32_t DMA0_LOCKSTEP ; /* DMA0 LOCKSTEP Error Injection Register, offset: 0x408 */
uint8_t RESERVED_3[1012];
__IO uint32_t BUS_REG[EIM_BUS_REG_COUNT] ; /* Bus Register, offset: 0x800 */
} EIM_Type, *EIM_MemMapPtr;
/** Number of instances of the EIM module. */
#define EIM_INSTANCE_COUNT (1u)
/* EIM - Peripheral instance base addresses */
/** Peripheral EIM base address */
#define EIM_BASE (0x40019000u)
/** Peripheral EIM base pointer */
#define EIM ((EIM_Type *)EIM_BASE)
/** Array initializer of EIM peripheral base addresses */
#define EIM_BASE_ADDRS {EIM_BASE}
/** Array initializer of EIM peripheral base pointers */
#define EIM_BASE_PTRS {EIM}
// need fill by yourself
///** Number of interrupt vector arrays for the EIM module. */
//#define EIM_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the EIM module. */
//#define EIM_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the EIM peripheral type */
//#define EIM_IRQS {EIM_IRQn}
/* ----------------------------------------------------------------------------
-- EIM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup EIM_Register_Masks EIM Register Masks
* @{
*/
/* CR Bit Fields */
#define EIM_CR_GEIEN_MASK 0x1u
#define EIM_CR_GEIEN_SHIFT 0u
#define EIM_CR_GEIEN_WIDTH 1u
#define EIM_CR_GEIEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CR_GEIEN_SHIFT))&EIM_CR_GEIEN_MASK)
/* CR Reg Mask */
#define EIM_CR_MASK 0x00000001u
/* CTRL_REG Bit Fields */
#define EIM_CTRL_REG_DWP_LOCK_MASK 0x80000000u
#define EIM_CTRL_REG_DWP_LOCK_SHIFT 31u
#define EIM_CTRL_REG_DWP_LOCK_WIDTH 1u
#define EIM_CTRL_REG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_DWP_LOCK_SHIFT))&EIM_CTRL_REG_DWP_LOCK_MASK)
#define EIM_CTRL_REG_DWP_MASK 0x70000000u
#define EIM_CTRL_REG_DWP_SHIFT 28u
#define EIM_CTRL_REG_DWP_WIDTH 3u
#define EIM_CTRL_REG_DWP(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_DWP_SHIFT))&EIM_CTRL_REG_DWP_MASK)
#define EIM_CTRL_REG_BUS_SEL_MASK 0x30u
#define EIM_CTRL_REG_BUS_SEL_SHIFT 4u
#define EIM_CTRL_REG_BUS_SEL_WIDTH 2u
#define EIM_CTRL_REG_BUS_SEL(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_BUS_SEL_SHIFT))&EIM_CTRL_REG_BUS_SEL_MASK)
#define EIM_CTRL_REG_ATTREIE_MASK 0x8u
#define EIM_CTRL_REG_ATTREIE_SHIFT 3u
#define EIM_CTRL_REG_ATTREIE_WIDTH 1u
#define EIM_CTRL_REG_ATTREIE(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_ATTREIE_SHIFT))&EIM_CTRL_REG_ATTREIE_MASK)
#define EIM_CTRL_REG_ADDREIE_MASK 0x4u
#define EIM_CTRL_REG_ADDREIE_SHIFT 2u
#define EIM_CTRL_REG_ADDREIE_WIDTH 1u
#define EIM_CTRL_REG_ADDREIE(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_ADDREIE_SHIFT))&EIM_CTRL_REG_ADDREIE_MASK)
#define EIM_CTRL_REG_DATA1EIE_MASK 0x2u
#define EIM_CTRL_REG_DATA1EIE_SHIFT 1u
#define EIM_CTRL_REG_DATA1EIE_WIDTH 1u
#define EIM_CTRL_REG_DATA1EIE(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_DATA1EIE_SHIFT))&EIM_CTRL_REG_DATA1EIE_MASK)
#define EIM_CTRL_REG_DATA0EIE_MASK 0x1u
#define EIM_CTRL_REG_DATA0EIE_SHIFT 0u
#define EIM_CTRL_REG_DATA0EIE_WIDTH 1u
#define EIM_CTRL_REG_DATA0EIE(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_DATA0EIE_SHIFT))&EIM_CTRL_REG_DATA0EIE_MASK)
/* CTRL_REG0 Reg Mask */
#define EIM_CTRL_REG_MASK 0xF000003Fu
/* CPU0_LOCKSTEP Bit Fields */
#define EIM_CPU0_LOCKSTEP_DWP_LOCK_MASK 0x80000000u
#define EIM_CPU0_LOCKSTEP_DWP_LOCK_SHIFT 31u
#define EIM_CPU0_LOCKSTEP_DWP_LOCK_WIDTH 1u
#define EIM_CPU0_LOCKSTEP_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_DWP_LOCK_SHIFT))&EIM_CPU0_LOCKSTEP_DWP_LOCK_MASK)
#define EIM_CPU0_LOCKSTEP_DWP_MASK 0x70000000u
#define EIM_CPU0_LOCKSTEP_DWP_SHIFT 28u
#define EIM_CPU0_LOCKSTEP_DWP_WIDTH 3u
#define EIM_CPU0_LOCKSTEP_DWP(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_DWP_SHIFT))&EIM_CPU0_LOCKSTEP_DWP_MASK)
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_MASK 0x8u
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_SHIFT 3u
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_WIDTH 1u
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_SHIFT))&EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_MASK)
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_MASK 0x4u
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_SHIFT 2u
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_WIDTH 1u
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_SHIFT))&EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_MASK)
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_MASK 0x2u
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_SHIFT 1u
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_WIDTH 1u
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_SHIFT))&EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_MASK)
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_MASK 0x1u
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_SHIFT 0u
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_WIDTH 1u
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_SHIFT))&EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_MASK)
/* CPU0_LOCKSTEP Reg Mask */
#define EIM_CPU0_LOCKSTEP_MASK 0xF000000Fu
/* DMA0_LOCKSTEP Bit Fields */
#define EIM_DMA0_LOCKSTEP_DWP_LOCK_MASK 0x80000000u
#define EIM_DMA0_LOCKSTEP_DWP_LOCK_SHIFT 31u
#define EIM_DMA0_LOCKSTEP_DWP_LOCK_WIDTH 1u
#define EIM_DMA0_LOCKSTEP_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_DWP_LOCK_SHIFT))&EIM_DMA0_LOCKSTEP_DWP_LOCK_MASK)
#define EIM_DMA0_LOCKSTEP_DWP_MASK 0x70000000u
#define EIM_DMA0_LOCKSTEP_DWP_SHIFT 28u
#define EIM_DMA0_LOCKSTEP_DWP_WIDTH 3u
#define EIM_DMA0_LOCKSTEP_DWP(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_DWP_SHIFT))&EIM_DMA0_LOCKSTEP_DWP_MASK)
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_MASK 0x8u
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_SHIFT 3u
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_WIDTH 1u
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_SHIFT))&EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_MASK)
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_MASK 0x4u
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_SHIFT 2u
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_WIDTH 1u
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_SHIFT))&EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_MASK)
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_MASK 0x2u
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_SHIFT 1u
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_WIDTH 1u
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_SHIFT))&EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_MASK)
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_MASK 0x1u
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_SHIFT 0u
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_WIDTH 1u
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_SHIFT))&EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_MASK)
/* DMA0_LOCKSTEP Reg Mask */
#define EIM_DMA0_LOCKSTEP_MASK 0xF000000Fu
/* BUS_REG Bit Fields */
#define EIM_BUS_REG_ATTR_MASK 0x1F000000u
#define EIM_BUS_REG_ATTR_SHIFT 24u
#define EIM_BUS_REG_ATTR_WIDTH 5u
#define EIM_BUS_REG_ATTR(x) (((uint32_t)(((uint32_t)(x))<<EIM_BUS_REG_ATTR_SHIFT))&EIM_BUS_REG_ATTR_MASK)
#define EIM_BUS_REG_ADDR_MASK 0x1F0000u
#define EIM_BUS_REG_ADDR_SHIFT 16u
#define EIM_BUS_REG_ADDR_WIDTH 5u
#define EIM_BUS_REG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<EIM_BUS_REG_ADDR_SHIFT))&EIM_BUS_REG_ADDR_MASK)
#define EIM_BUS_REG_DATA1_MASK 0x7F00u
#define EIM_BUS_REG_DATA1_SHIFT 8u
#define EIM_BUS_REG_DATA1_WIDTH 7u
#define EIM_BUS_REG_DATA1(x) (((uint32_t)(((uint32_t)(x))<<EIM_BUS_REG_DATA1_SHIFT))&EIM_BUS_REG_DATA1_MASK)
#define EIM_BUS_REG_DATA0_MASK 0x7Fu
#define EIM_BUS_REG_DATA0_SHIFT 0u
#define EIM_BUS_REG_DATA0_WIDTH 7u
#define EIM_BUS_REG_DATA0(x) (((uint32_t)(((uint32_t)(x))<<EIM_BUS_REG_DATA0_SHIFT))&EIM_BUS_REG_DATA0_MASK)
/* BUS_REG0 Reg Mask */
#define EIM_BUS_REG_MASK 0x1F1F7F7Fu
/*!
* @}
*/ /* end of group EIM_Register_Masks */
/*!
* @}
*/ /* end of group EIM_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7240_erm_regs.h Normal file
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fc/fc7240_fciic_regs.h Normal file
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fc/fc7240_fcpit_regs.h Normal file
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#ifndef _FC7240_FCPIT_NU_Tztufn30_REGS_H_
#define _FC7240_FCPIT_NU_Tztufn30_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- FCPIT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FCPIT_Peripheral_Access_Layer FCPIT Peripheral Access Layer
* @{
*/
/** FCPIT - Size of Registers Arrays */
#define FCPIT_CHANNEL_NUM 4u
/** FCPIT - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[8];
__IO uint32_t MCR ; /* Module Control Register, offset: 0x8 */
__IO uint32_t MSR ; /* Module Status Register, offset: 0xC */
__IO uint32_t MIER ; /* Module Interrupt Enable Register, offset: 0x10 */
__IO uint32_t SETTEN ; /* Set Timer Enable Register, offset: 0x14 */
__IO uint32_t CLRTEN ; /* Clear Timer Enable Register, offset: 0x18 */
uint8_t RESERVED_1[4];
struct
{
__IO uint32_t TVAL ; /* Timer Value Register, offset: 0x20 */
__I uint32_t CVAL ; /* Current Timer Value Register, offset: 0x24 */
__IO uint32_t TCTRL ; /* Timer Control Register, offset: 0x28 */
uint8_t RESERVED_2[4];
}CONTROLS[FCPIT_CHANNEL_NUM];
} FCPIT_Type, *FCPIT_MemMapPtr;
/** Number of instances of the FCPIT module. */
#define FCPIT_INSTANCE_COUNT (1u)
#define MAX_FCPIT_CHANNEL_NUM (4u)
/* FCPIT - Peripheral instance base addresses */
/** Peripheral FCPIT base address */
#define FCPIT_BASE (0x4002e000u)
/** Peripheral FCPIT base pointer */
#define FCPIT ((FCPIT_Type *)FCPIT_BASE)
/** Array initializer of FCPIT peripheral base addresses */
#define FCPIT_BASE_ADDRS {FCPIT_BASE}
/** Array initializer of FCPIT peripheral base pointers */
#define FCPIT_BASE_PTRS {FCPIT}
// need fill by yourself
///** Number of interrupt vector arrays for the FCPIT module. */
//#define FCPIT_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the FCPIT module. */
//#define FCPIT_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the FCPIT peripheral type */
//#define FCPIT_IRQS {FCPIT_IRQn}
/* ----------------------------------------------------------------------------
-- FCPIT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FCPIT_Register_Masks FCPIT Register Masks
* @{
*/
/* MCR Bit Fields */
#define FCPIT_MCR_DBG_EN_MASK 0x8u
#define FCPIT_MCR_DBG_EN_SHIFT 3u
#define FCPIT_MCR_DBG_EN_WIDTH 1u
#define FCPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MCR_DBG_EN_SHIFT))&FCPIT_MCR_DBG_EN_MASK)
#define FCPIT_MCR_LPM_EN_MASK 0x4u
#define FCPIT_MCR_LPM_EN_SHIFT 2u
#define FCPIT_MCR_LPM_EN_WIDTH 1u
#define FCPIT_MCR_LPM_EN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MCR_LPM_EN_SHIFT))&FCPIT_MCR_LPM_EN_MASK)
#define FCPIT_MCR_SW_RST_MASK 0x2u
#define FCPIT_MCR_SW_RST_SHIFT 1u
#define FCPIT_MCR_SW_RST_WIDTH 1u
#define FCPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MCR_SW_RST_SHIFT))&FCPIT_MCR_SW_RST_MASK)
#define FCPIT_MCR_M_CEN_MASK 0x1u
#define FCPIT_MCR_M_CEN_SHIFT 0u
#define FCPIT_MCR_M_CEN_WIDTH 1u
#define FCPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MCR_M_CEN_SHIFT))&FCPIT_MCR_M_CEN_MASK)
/* MCR Reg Mask */
#define FCPIT_MCR_MASK 0x0000000Fu
/* MSR Bit Fields */
#define FCPIT_MSR_TIF3_MASK 0x8u
#define FCPIT_MSR_TIF3_SHIFT 3u
#define FCPIT_MSR_TIF3_WIDTH 1u
#define FCPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MSR_TIF3_SHIFT))&FCPIT_MSR_TIF3_MASK)
#define FCPIT_MSR_TIF2_MASK 0x4u
#define FCPIT_MSR_TIF2_SHIFT 2u
#define FCPIT_MSR_TIF2_WIDTH 1u
#define FCPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MSR_TIF2_SHIFT))&FCPIT_MSR_TIF2_MASK)
#define FCPIT_MSR_TIF1_MASK 0x2u
#define FCPIT_MSR_TIF1_SHIFT 1u
#define FCPIT_MSR_TIF1_WIDTH 1u
#define FCPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MSR_TIF1_SHIFT))&FCPIT_MSR_TIF1_MASK)
#define FCPIT_MSR_TIF0_MASK 0x1u
#define FCPIT_MSR_TIF0_SHIFT 0u
#define FCPIT_MSR_TIF0_WIDTH 1u
#define FCPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MSR_TIF0_SHIFT))&FCPIT_MSR_TIF0_MASK)
/* MSR Reg Mask */
#define FCPIT_MSR_MASK 0x0000000Fu
/* MIER Bit Fields */
#define FCPIT_MIER_TIE3_MASK 0x8u
#define FCPIT_MIER_TIE3_SHIFT 3u
#define FCPIT_MIER_TIE3_WIDTH 1u
#define FCPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MIER_TIE3_SHIFT))&FCPIT_MIER_TIE3_MASK)
#define FCPIT_MIER_TIE2_MASK 0x4u
#define FCPIT_MIER_TIE2_SHIFT 2u
#define FCPIT_MIER_TIE2_WIDTH 1u
#define FCPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MIER_TIE2_SHIFT))&FCPIT_MIER_TIE2_MASK)
#define FCPIT_MIER_TIE1_MASK 0x2u
#define FCPIT_MIER_TIE1_SHIFT 1u
#define FCPIT_MIER_TIE1_WIDTH 1u
#define FCPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MIER_TIE1_SHIFT))&FCPIT_MIER_TIE1_MASK)
#define FCPIT_MIER_TIE0_MASK 0x1u
#define FCPIT_MIER_TIE0_SHIFT 0u
#define FCPIT_MIER_TIE0_WIDTH 1u
#define FCPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MIER_TIE0_SHIFT))&FCPIT_MIER_TIE0_MASK)
/* MIER Reg Mask */
#define FCPIT_MIER_MASK 0x0000000Fu
/* SETTEN Bit Fields */
#define FCPIT_SETTEN_SET_T_EN_3_MASK 0x8u
#define FCPIT_SETTEN_SET_T_EN_3_SHIFT 3u
#define FCPIT_SETTEN_SET_T_EN_3_WIDTH 1u
#define FCPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_SETTEN_SET_T_EN_3_SHIFT))&FCPIT_SETTEN_SET_T_EN_3_MASK)
#define FCPIT_SETTEN_SET_T_EN_2_MASK 0x4u
#define FCPIT_SETTEN_SET_T_EN_2_SHIFT 2u
#define FCPIT_SETTEN_SET_T_EN_2_WIDTH 1u
#define FCPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_SETTEN_SET_T_EN_2_SHIFT))&FCPIT_SETTEN_SET_T_EN_2_MASK)
#define FCPIT_SETTEN_SET_T_EN_1_MASK 0x2u
#define FCPIT_SETTEN_SET_T_EN_1_SHIFT 1u
#define FCPIT_SETTEN_SET_T_EN_1_WIDTH 1u
#define FCPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_SETTEN_SET_T_EN_1_SHIFT))&FCPIT_SETTEN_SET_T_EN_1_MASK)
#define FCPIT_SETTEN_SET_T_EN_0_MASK 0x1u
#define FCPIT_SETTEN_SET_T_EN_0_SHIFT 0u
#define FCPIT_SETTEN_SET_T_EN_0_WIDTH 1u
#define FCPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_SETTEN_SET_T_EN_0_SHIFT))&FCPIT_SETTEN_SET_T_EN_0_MASK)
/* SETTEN Reg Mask */
#define FCPIT_SETTEN_MASK 0x0000000Fu
/* CLRTEN Bit Fields */
#define FCPIT_CLRTEN_CLR_T_EN_3_MASK 0x8u
#define FCPIT_CLRTEN_CLR_T_EN_3_SHIFT 3u
#define FCPIT_CLRTEN_CLR_T_EN_3_WIDTH 1u
#define FCPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CLRTEN_CLR_T_EN_3_SHIFT))&FCPIT_CLRTEN_CLR_T_EN_3_MASK)
#define FCPIT_CLRTEN_CLR_T_EN_2_MASK 0x4u
#define FCPIT_CLRTEN_CLR_T_EN_2_SHIFT 2u
#define FCPIT_CLRTEN_CLR_T_EN_2_WIDTH 1u
#define FCPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CLRTEN_CLR_T_EN_2_SHIFT))&FCPIT_CLRTEN_CLR_T_EN_2_MASK)
#define FCPIT_CLRTEN_CLR_T_EN_1_MASK 0x2u
#define FCPIT_CLRTEN_CLR_T_EN_1_SHIFT 1u
#define FCPIT_CLRTEN_CLR_T_EN_1_WIDTH 1u
#define FCPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CLRTEN_CLR_T_EN_1_SHIFT))&FCPIT_CLRTEN_CLR_T_EN_1_MASK)
#define FCPIT_CLRTEN_CLR_T_EN_0_MASK 0x1u
#define FCPIT_CLRTEN_CLR_T_EN_0_SHIFT 0u
#define FCPIT_CLRTEN_CLR_T_EN_0_WIDTH 1u
#define FCPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CLRTEN_CLR_T_EN_0_SHIFT))&FCPIT_CLRTEN_CLR_T_EN_0_MASK)
/* CLRTEN Reg Mask */
#define FCPIT_CLRTEN_MASK 0x0000000Fu
/* TVAL Bit Fields */
#define FCPIT_TVAL_TMR_VAL_MASK 0xFFFFFFFFu
#define FCPIT_TVAL_TMR_VAL_SHIFT 0u
#define FCPIT_TVAL_TMR_VAL_WIDTH 32u
#define FCPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TVAL_TMR_VAL_SHIFT))&FCPIT_TVAL_TMR_VAL_MASK)
/* TVAL0 Reg Mask */
#define FCPIT_TVAL_MASK 0xFFFFFFFFu
/* CVAL Bit Fields */
#define FCPIT_CVAL_TMR_CUR_VAL_MASK 0xFFFFFFFFu
#define FCPIT_CVAL_TMR_CUR_VAL_SHIFT 0u
#define FCPIT_CVAL_TMR_CUR_VAL_WIDTH 32u
#define FCPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CVAL_TMR_CUR_VAL_SHIFT))&FCPIT_CVAL_TMR_CUR_VAL_MASK)
/* CVAL0 Reg Mask */
#define FCPIT_CVAL_MASK 0xFFFFFFFFu
/* TCTRL Bit Fields */
#define FCPIT_TCTRL_TRG_SEL_MASK 0xF000000u
#define FCPIT_TCTRL_TRG_SEL_SHIFT 24u
#define FCPIT_TCTRL_TRG_SEL_WIDTH 4u
#define FCPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TRG_SEL_SHIFT))&FCPIT_TCTRL_TRG_SEL_MASK)
#define FCPIT_TCTRL_TRG_SRC_MASK 0x800000u
#define FCPIT_TCTRL_TRG_SRC_SHIFT 23u
#define FCPIT_TCTRL_TRG_SRC_WIDTH 1u
#define FCPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TRG_SRC_SHIFT))&FCPIT_TCTRL_TRG_SRC_MASK)
#define FCPIT_TCTRL_TROT_MASK 0x40000u
#define FCPIT_TCTRL_TROT_SHIFT 18u
#define FCPIT_TCTRL_TROT_WIDTH 1u
#define FCPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TROT_SHIFT))&FCPIT_TCTRL_TROT_MASK)
#define FCPIT_TCTRL_TSOI_MASK 0x20000u
#define FCPIT_TCTRL_TSOI_SHIFT 17u
#define FCPIT_TCTRL_TSOI_WIDTH 1u
#define FCPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TSOI_SHIFT))&FCPIT_TCTRL_TSOI_MASK)
#define FCPIT_TCTRL_TSOT_MASK 0x10000u
#define FCPIT_TCTRL_TSOT_SHIFT 16u
#define FCPIT_TCTRL_TSOT_WIDTH 1u
#define FCPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TSOT_SHIFT))&FCPIT_TCTRL_TSOT_MASK)
#define FCPIT_TCTRL_MODE_MASK 0xCu
#define FCPIT_TCTRL_MODE_SHIFT 2u
#define FCPIT_TCTRL_MODE_WIDTH 2u
#define FCPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_MODE_SHIFT))&FCPIT_TCTRL_MODE_MASK)
#define FCPIT_TCTRL_CHAIN_MASK 0x2u
#define FCPIT_TCTRL_CHAIN_SHIFT 1u
#define FCPIT_TCTRL_CHAIN_WIDTH 1u
#define FCPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_CHAIN_SHIFT))&FCPIT_TCTRL_CHAIN_MASK)
#define FCPIT_TCTRL_T_EN_MASK 0x1u
#define FCPIT_TCTRL_T_EN_SHIFT 0u
#define FCPIT_TCTRL_T_EN_WIDTH 1u
#define FCPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_T_EN_SHIFT))&FCPIT_TCTRL_T_EN_MASK)
/* TCTRL0 Reg Mask */
#define FCPIT_TCTRL_MASK 0x0F87000Fu
/*!
* @}
*/ /* end of group FCPIT_Register_Masks */
/*!
* @}
*/ /* end of group FCPIT_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7240_fcsmu_regs.h Normal file
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#ifndef _FC7240_FCSMU_NU_Tztufn38_REGS_H_
#define _FC7240_FCSMU_NU_Tztufn38_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- FCSMU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FCSMU_Peripheral_Access_Layer FCSMU Peripheral Access Layer
* @{
*/
/** FCSMU - Size of Registers Arrays */
/** FCSMU - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL ; /* Control Register, offset: 0x0 */
__O uint32_t OPRK ; /* Operation Key Register, offset: 0x4 */
__IO uint32_t SOCTRL ; /* Status Output Control Register, offset: 0x8 */
__IO uint32_t FCCR0 ; /* Fault Clear Control Register 0, offset: 0xC */
uint8_t RESERVED_0[12];
__IO uint32_t FRST0 ; /* Fault Reset Control Register 0, offset: 0x1C */
uint8_t RESERVED_1[12];
__IO uint32_t FST0 ; /* Fault Status Register, offset: 0x2C */
uint8_t RESERVED_2[12];
__O uint32_t FST_UNLK ; /* Fault Status Register Unlock Register, offset: 0x3C */
__IO uint32_t FE0 ; /* Fault Enable Register, offset: 0x40 */
uint8_t RESERVED_3[12];
__IO uint32_t WARNING_EN0 ; /* Warning State Enable Register 0, offset: 0x50 */
uint8_t RESERVED_4[12];
__IO uint32_t WARNING_TO ; /* Warning Timeout Interval Register, offset: 0x60 */
__IO uint32_t CFG_TO ; /* Configuration State Timeout Interval Register, offset: 0x64 */
__IO uint32_t SOUT_DIAG ; /* SOUT Diagnostic Register, offset: 0x68 */
__I uint32_t STATUS ; /* Status Register, offset: 0x6C */
__I uint32_t NTW ; /* Normal to Warning Register, offset: 0x70 */
__I uint32_t WTF ; /* Warning to Fault Register, offset: 0x74 */
__I uint32_t NTF ; /* Normal to Fault Register, offset: 0x78 */
__I uint32_t FTW ; /* Fault to Warning Register, offset: 0x7C */
uint8_t RESERVED_5[4];
__O uint32_t INJECT ; /* Fault Injection Register, offset: 0x84 */
__IO uint32_t IRQ_STAT ; /* IRQ Status Register, offset: 0x88 */
__IO uint32_t IRQ_EN ; /* IRQ Enable Register, offset: 0x8C */
uint8_t RESERVED_6[4];
__O uint32_t TEMP_UNLK ; /* Temporary Configuration State Unlock Register, offset: 0x94 */
__O uint32_t PERMNT_LOCK ; /* Permanent Configuration State Lock Register, offset: 0x98 */
__IO uint32_t STMR ; /* SOUT Timer Interval Register, offset: 0x9C */
__IO uint32_t WARNING_IEN0 ; /* Warning State Interrupt Enable Register, offset: 0xA0 */
uint8_t RESERVED_7[12];
__IO uint32_t FAULT_IEN0 ; /* Fault State Interrupt Enable Register, offset: 0xB0 */
uint8_t RESERVED_8[12];
__IO uint32_t SOUT_EN0 ; /* SOUT Enable Register, offset: 0xC0 */
uint8_t RESERVED_9[12];
__I uint32_t WARNING_TMR ; /* Warning State Timer Register, offset: 0xD0 */
__I uint32_t SM_TMR ; /* Safe Mode State Timer Register, offset: 0xD4 */
__I uint32_t CFG_TMR ; /* Configuration State Timer Register, offset: 0xD8 */
__I uint32_t SOUT_TMR ; /* SOUT Timer Register, offset: 0xDC */
__IO uint32_t CRC_CTRL ; /* CRC Control Register, offset: 0xE0 */
__I uint32_t CRC_RES ; /* CRC Result Register, offset: 0xE4 */
} FCSMU_Type, *FCSMU_MemMapPtr;
/** Number of instances of the FCSMU module. */
#define FCSMU_INSTANCE_COUNT (1u)
/* FCSMU - Peripheral instance base addresses */
/** Peripheral FCSMU base address */
#define FCSMU_BASE (0x4000f000u)
/** Peripheral FCSMU base pointer */
#define FCSMU ((FCSMU_Type *)FCSMU_BASE)
/** Array initializer of FCSMU peripheral base addresses */
#define FCSMU_BASE_ADDRS {FCSMU_BASE}
/** Array initializer of FCSMU peripheral base pointers */
#define FCSMU_BASE_PTRS {FCSMU}
// need fill by yourself
///** Number of interrupt vector arrays for the FCSMU module. */
//#define FCSMU_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the FCSMU module. */
//#define FCSMU_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the FCSMU peripheral type */
//#define FCSMU_IRQS {FCSMU_IRQn}
/* ----------------------------------------------------------------------------
-- FCSMU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FCSMU_Register_Masks FCSMU Register Masks
* @{
*/
/* CTRL Bit Fields */
#define FCSMU_CTRL_DBGEN_MASK 0x200u
#define FCSMU_CTRL_DBGEN_SHIFT 9u
#define FCSMU_CTRL_DBGEN_WIDTH 1u
#define FCSMU_CTRL_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CTRL_DBGEN_SHIFT))&FCSMU_CTRL_DBGEN_MASK)
#define FCSMU_CTRL_OPS_MASK 0xC0u
#define FCSMU_CTRL_OPS_SHIFT 6u
#define FCSMU_CTRL_OPS_WIDTH 2u
#define FCSMU_CTRL_OPS(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CTRL_OPS_SHIFT))&FCSMU_CTRL_OPS_MASK)
#define FCSMU_CTRL_OPC_MASK 0x1Fu
#define FCSMU_CTRL_OPC_SHIFT 0u
#define FCSMU_CTRL_OPC_WIDTH 5u
#define FCSMU_CTRL_OPC(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CTRL_OPC_SHIFT))&FCSMU_CTRL_OPC_MASK)
/* CTRL Reg Mask */
#define FCSMU_CTRL_MASK 0x000002DFu
/* OPRK Bit Fields */
#define FCSMU_OPRK_OPKEY_MASK 0xFFFFFFFFu
#define FCSMU_OPRK_OPKEY_SHIFT 0u
#define FCSMU_OPRK_OPKEY_WIDTH 32u
#define FCSMU_OPRK_OPKEY(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_OPRK_OPKEY_SHIFT))&FCSMU_OPRK_OPKEY_MASK)
/* OPRK Reg Mask */
#define FCSMU_OPRK_MASK 0xFFFFFFFFu
/* SOCTRL Bit Fields */
#define FCSMU_SOCTRL_SOUT_PEN_MASK 0x2000000u
#define FCSMU_SOCTRL_SOUT_PEN_SHIFT 25u
#define FCSMU_SOCTRL_SOUT_PEN_WIDTH 1u
#define FCSMU_SOCTRL_SOUT_PEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_SOUT_PEN_SHIFT))&FCSMU_SOCTRL_SOUT_PEN_MASK)
#define FCSMU_SOCTRL_SOUT_CTRL_MASK 0x1800000u
#define FCSMU_SOCTRL_SOUT_CTRL_SHIFT 23u
#define FCSMU_SOCTRL_SOUT_CTRL_WIDTH 2u
#define FCSMU_SOCTRL_SOUT_CTRL(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_SOUT_CTRL_SHIFT))&FCSMU_SOCTRL_SOUT_CTRL_MASK)
#define FCSMU_SOCTRL_DIVEX_MASK 0x200000u
#define FCSMU_SOCTRL_DIVEX_SHIFT 21u
#define FCSMU_SOCTRL_DIVEX_WIDTH 1u
#define FCSMU_SOCTRL_DIVEX(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_DIVEX_SHIFT))&FCSMU_SOCTRL_DIVEX_MASK)
#define FCSMU_SOCTRL_SMRDT_MASK 0x1E0000u
#define FCSMU_SOCTRL_SMRDT_SHIFT 17u
#define FCSMU_SOCTRL_SMRDT_WIDTH 4u
#define FCSMU_SOCTRL_SMRDT(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_SMRDT_SHIFT))&FCSMU_SOCTRL_SMRDT_MASK)
#define FCSMU_SOCTRL_FASTEN_MASK 0x4000u
#define FCSMU_SOCTRL_FASTEN_SHIFT 14u
#define FCSMU_SOCTRL_FASTEN_WIDTH 1u
#define FCSMU_SOCTRL_FASTEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_FASTEN_SHIFT))&FCSMU_SOCTRL_FASTEN_MASK)
#define FCSMU_SOCTRL_POLSW_MASK 0x2000u
#define FCSMU_SOCTRL_POLSW_SHIFT 13u
#define FCSMU_SOCTRL_POLSW_WIDTH 1u
#define FCSMU_SOCTRL_POLSW(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_POLSW_SHIFT))&FCSMU_SOCTRL_POLSW_MASK)
#define FCSMU_SOCTRL_SOUT_PTC_MASK 0x1C00u
#define FCSMU_SOCTRL_SOUT_PTC_SHIFT 10u
#define FCSMU_SOCTRL_SOUT_PTC_WIDTH 3u
#define FCSMU_SOCTRL_SOUT_PTC(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_SOUT_PTC_SHIFT))&FCSMU_SOCTRL_SOUT_PTC_MASK)
#define FCSMU_SOCTRL_SOUT_DIV_MASK 0x3FFu
#define FCSMU_SOCTRL_SOUT_DIV_SHIFT 0u
#define FCSMU_SOCTRL_SOUT_DIV_WIDTH 10u
#define FCSMU_SOCTRL_SOUT_DIV(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_SOUT_DIV_SHIFT))&FCSMU_SOCTRL_SOUT_DIV_MASK)
/* SOCTRL Reg Mask */
#define FCSMU_SOCTRL_MASK 0x03BE7FFFu
/* FCCR0 Bit Fields */
#define FCSMU_FCCR0_FCC_MASK 0xFFFFFFFFu
#define FCSMU_FCCR0_FCC_SHIFT 0u
#define FCSMU_FCCR0_FCC_WIDTH 32u
#define FCSMU_FCCR0_FCC(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FCCR0_FCC_SHIFT))&FCSMU_FCCR0_FCC_MASK)
/* FCCR0 Reg Mask */
#define FCSMU_FCCR0_MASK 0xFFFFFFFFu
/* FRST0 Bit Fields */
#define FCSMU_FRST0_FRST_MASK 0xFFFFFFFFu
#define FCSMU_FRST0_FRST_SHIFT 0u
#define FCSMU_FRST0_FRST_WIDTH 32u
#define FCSMU_FRST0_FRST(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FRST0_FRST_SHIFT))&FCSMU_FRST0_FRST_MASK)
/* FRST0 Reg Mask */
#define FCSMU_FRST0_MASK 0xFFFFFFFFu
/* FST0 Bit Fields */
#define FCSMU_FST0_ST_MASK 0xFFFFFFFFu
#define FCSMU_FST0_ST_SHIFT 0u
#define FCSMU_FST0_ST_WIDTH 32u
#define FCSMU_FST0_ST(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FST0_ST_SHIFT))&FCSMU_FST0_ST_MASK)
/* FST0 Reg Mask */
#define FCSMU_FST0_MASK 0xFFFFFFFFu
/* FST_UNLK Bit Fields */
#define FCSMU_FST_UNLK_KEY_MASK 0xFFFFFFFFu
#define FCSMU_FST_UNLK_KEY_SHIFT 0u
#define FCSMU_FST_UNLK_KEY_WIDTH 32u
#define FCSMU_FST_UNLK_KEY(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FST_UNLK_KEY_SHIFT))&FCSMU_FST_UNLK_KEY_MASK)
/* FST_UNLK Reg Mask */
#define FCSMU_FST_UNLK_MASK 0xFFFFFFFFu
/* FE0 Bit Fields */
#define FCSMU_FE0_EN_MASK 0xFFFFFFFFu
#define FCSMU_FE0_EN_SHIFT 0u
#define FCSMU_FE0_EN_WIDTH 32u
#define FCSMU_FE0_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FE0_EN_SHIFT))&FCSMU_FE0_EN_MASK)
/* FE0 Reg Mask */
#define FCSMU_FE0_MASK 0xFFFFFFFFu
/* WARNING_EN0 Bit Fields */
#define FCSMU_WARNING_EN0_EN_MASK 0xFFFFFFFFu
#define FCSMU_WARNING_EN0_EN_SHIFT 0u
#define FCSMU_WARNING_EN0_EN_WIDTH 32u
#define FCSMU_WARNING_EN0_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_WARNING_EN0_EN_SHIFT))&FCSMU_WARNING_EN0_EN_MASK)
/* WARNING_EN0 Reg Mask */
#define FCSMU_WARNING_EN0_MASK 0xFFFFFFFFu
/* WARNING_TO Bit Fields */
#define FCSMU_WARNING_TO_TIME_MASK 0xFFFFFFFFu
#define FCSMU_WARNING_TO_TIME_SHIFT 0u
#define FCSMU_WARNING_TO_TIME_WIDTH 32u
#define FCSMU_WARNING_TO_TIME(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_WARNING_TO_TIME_SHIFT))&FCSMU_WARNING_TO_TIME_MASK)
/* WARNING_TO Reg Mask */
#define FCSMU_WARNING_TO_MASK 0xFFFFFFFFu
/* CFG_TO Bit Fields */
#define FCSMU_CFG_TO_TIME_MASK 0x7u
#define FCSMU_CFG_TO_TIME_SHIFT 0u
#define FCSMU_CFG_TO_TIME_WIDTH 3u
#define FCSMU_CFG_TO_TIME(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CFG_TO_TIME_SHIFT))&FCSMU_CFG_TO_TIME_MASK)
/* CFG_TO Reg Mask */
#define FCSMU_CFG_TO_MASK 0x00000007u
/* SOUT_DIAG Bit Fields */
#define FCSMU_SOUT_DIAG_SIN1_MASK 0x20u
#define FCSMU_SOUT_DIAG_SIN1_SHIFT 5u
#define FCSMU_SOUT_DIAG_SIN1_WIDTH 1u
#define FCSMU_SOUT_DIAG_SIN1(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOUT_DIAG_SIN1_SHIFT))&FCSMU_SOUT_DIAG_SIN1_MASK)
#define FCSMU_SOUT_DIAG_SIN0_MASK 0x10u
#define FCSMU_SOUT_DIAG_SIN0_SHIFT 4u
#define FCSMU_SOUT_DIAG_SIN0_WIDTH 1u
#define FCSMU_SOUT_DIAG_SIN0(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOUT_DIAG_SIN0_SHIFT))&FCSMU_SOUT_DIAG_SIN0_MASK)
#define FCSMU_SOUT_DIAG_SOUT1_MASK 0x2u
#define FCSMU_SOUT_DIAG_SOUT1_SHIFT 1u
#define FCSMU_SOUT_DIAG_SOUT1_WIDTH 1u
#define FCSMU_SOUT_DIAG_SOUT1(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOUT_DIAG_SOUT1_SHIFT))&FCSMU_SOUT_DIAG_SOUT1_MASK)
#define FCSMU_SOUT_DIAG_SOUT0_MASK 0x1u
#define FCSMU_SOUT_DIAG_SOUT0_SHIFT 0u
#define FCSMU_SOUT_DIAG_SOUT0_WIDTH 1u
#define FCSMU_SOUT_DIAG_SOUT0(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOUT_DIAG_SOUT0_SHIFT))&FCSMU_SOUT_DIAG_SOUT0_MASK)
/* SOUT_DIAG Reg Mask */
#define FCSMU_SOUT_DIAG_MASK 0x00000033u
/* STATUS Bit Fields */
#define FCSMU_STATUS_SOUTPIN_MASK 0x30u
#define FCSMU_STATUS_SOUTPIN_SHIFT 4u
#define FCSMU_STATUS_SOUTPIN_WIDTH 2u
#define FCSMU_STATUS_SOUTPIN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_STATUS_SOUTPIN_SHIFT))&FCSMU_STATUS_SOUTPIN_MASK)
#define FCSMU_STATUS_FIF_MASK 0x8u
#define FCSMU_STATUS_FIF_SHIFT 3u
#define FCSMU_STATUS_FIF_WIDTH 1u
#define FCSMU_STATUS_FIF(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_STATUS_FIF_SHIFT))&FCSMU_STATUS_FIF_MASK)
#define FCSMU_STATUS_STAT_MASK 0x7u
#define FCSMU_STATUS_STAT_SHIFT 0u
#define FCSMU_STATUS_STAT_WIDTH 3u
#define FCSMU_STATUS_STAT(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_STATUS_STAT_SHIFT))&FCSMU_STATUS_STAT_MASK)
/* STATUS Reg Mask */
#define FCSMU_STATUS_MASK 0x0000003Fu
/* NTW Bit Fields */
#define FCSMU_NTW_INDEX_MASK 0xFFu
#define FCSMU_NTW_INDEX_SHIFT 0u
#define FCSMU_NTW_INDEX_WIDTH 8u
#define FCSMU_NTW_INDEX(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_NTW_INDEX_SHIFT))&FCSMU_NTW_INDEX_MASK)
/* NTW Reg Mask */
#define FCSMU_NTW_MASK 0x000000FFu
/* WTF Bit Fields */
#define FCSMU_WTF_FLAG_MASK 0x200u
#define FCSMU_WTF_FLAG_SHIFT 9u
#define FCSMU_WTF_FLAG_WIDTH 1u
#define FCSMU_WTF_FLAG(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_WTF_FLAG_SHIFT))&FCSMU_WTF_FLAG_MASK)
#define FCSMU_WTF_INDEX_MASK 0xFFu
#define FCSMU_WTF_INDEX_SHIFT 0u
#define FCSMU_WTF_INDEX_WIDTH 8u
#define FCSMU_WTF_INDEX(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_WTF_INDEX_SHIFT))&FCSMU_WTF_INDEX_MASK)
/* WTF Reg Mask */
#define FCSMU_WTF_MASK 0x000002FFu
/* NTF Bit Fields */
#define FCSMU_NTF_FLAG_MASK 0x200u
#define FCSMU_NTF_FLAG_SHIFT 9u
#define FCSMU_NTF_FLAG_WIDTH 1u
#define FCSMU_NTF_FLAG(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_NTF_FLAG_SHIFT))&FCSMU_NTF_FLAG_MASK)
#define FCSMU_NTF_INDEX_MASK 0xFFu
#define FCSMU_NTF_INDEX_SHIFT 0u
#define FCSMU_NTF_INDEX_WIDTH 8u
#define FCSMU_NTF_INDEX(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_NTF_INDEX_SHIFT))&FCSMU_NTF_INDEX_MASK)
/* NTF Reg Mask */
#define FCSMU_NTF_MASK 0x000002FFu
/* FTW Bit Fields */
#define FCSMU_FTW_INDEX_MASK 0xFFu
#define FCSMU_FTW_INDEX_SHIFT 0u
#define FCSMU_FTW_INDEX_WIDTH 8u
#define FCSMU_FTW_INDEX(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FTW_INDEX_SHIFT))&FCSMU_FTW_INDEX_MASK)
/* FTW Reg Mask */
#define FCSMU_FTW_MASK 0x000000FFu
/* INJECT Bit Fields */
#define FCSMU_INJECT_INDEX_MASK 0x7Fu
#define FCSMU_INJECT_INDEX_SHIFT 0u
#define FCSMU_INJECT_INDEX_WIDTH 7u
#define FCSMU_INJECT_INDEX(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_INJECT_INDEX_SHIFT))&FCSMU_INJECT_INDEX_MASK)
/* INJECT Reg Mask */
#define FCSMU_INJECT_MASK 0x0000007Fu
/* IRQ_STAT Bit Fields */
#define FCSMU_IRQ_STAT_FAULT_IRQ_MASK 0x4u
#define FCSMU_IRQ_STAT_FAULT_IRQ_SHIFT 2u
#define FCSMU_IRQ_STAT_FAULT_IRQ_WIDTH 1u
#define FCSMU_IRQ_STAT_FAULT_IRQ(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_IRQ_STAT_FAULT_IRQ_SHIFT))&FCSMU_IRQ_STAT_FAULT_IRQ_MASK)
#define FCSMU_IRQ_STAT_WARNING_IRQ_MASK 0x2u
#define FCSMU_IRQ_STAT_WARNING_IRQ_SHIFT 1u
#define FCSMU_IRQ_STAT_WARNING_IRQ_WIDTH 1u
#define FCSMU_IRQ_STAT_WARNING_IRQ(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_IRQ_STAT_WARNING_IRQ_SHIFT))&FCSMU_IRQ_STAT_WARNING_IRQ_MASK)
#define FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK 0x1u
#define FCSMU_IRQ_STAT_CFG_TO_IRQ_SHIFT 0u
#define FCSMU_IRQ_STAT_CFG_TO_IRQ_WIDTH 1u
#define FCSMU_IRQ_STAT_CFG_TO_IRQ(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_IRQ_STAT_CFG_TO_IRQ_SHIFT))&FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK)
/* IRQ_STAT Reg Mask */
#define FCSMU_IRQ_STAT_MASK 0x00000007u
/* IRQ_EN Bit Fields */
#define FCSMU_IRQ_EN_CFG_TO_IEN_MASK 0x1u
#define FCSMU_IRQ_EN_CFG_TO_IEN_SHIFT 0u
#define FCSMU_IRQ_EN_CFG_TO_IEN_WIDTH 1u
#define FCSMU_IRQ_EN_CFG_TO_IEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_IRQ_EN_CFG_TO_IEN_SHIFT))&FCSMU_IRQ_EN_CFG_TO_IEN_MASK)
/* IRQ_EN Reg Mask */
#define FCSMU_IRQ_EN_MASK 0x00000001u
/* TEMP_UNLK Bit Fields */
#define FCSMU_TEMP_UNLK_KEY_MASK 0x1FFu
#define FCSMU_TEMP_UNLK_KEY_SHIFT 0u
#define FCSMU_TEMP_UNLK_KEY_WIDTH 9u
#define FCSMU_TEMP_UNLK_KEY(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_TEMP_UNLK_KEY_SHIFT))&FCSMU_TEMP_UNLK_KEY_MASK)
/* TEMP_UNLK Reg Mask */
#define FCSMU_TEMP_UNLK_MASK 0x000001FFu
/* PERMNT_LOCK Bit Fields */
#define FCSMU_PERMNT_LOCK_KEY_MASK 0x1FFu
#define FCSMU_PERMNT_LOCK_KEY_SHIFT 0u
#define FCSMU_PERMNT_LOCK_KEY_WIDTH 9u
#define FCSMU_PERMNT_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_PERMNT_LOCK_KEY_SHIFT))&FCSMU_PERMNT_LOCK_KEY_MASK)
/* PERMNT_LOCK Reg Mask */
#define FCSMU_PERMNT_LOCK_MASK 0x000001FFu
/* STMR Bit Fields */
#define FCSMU_STMR_FTTI_MASK 0xC0000000u
#define FCSMU_STMR_FTTI_SHIFT 30u
#define FCSMU_STMR_FTTI_WIDTH 2u
#define FCSMU_STMR_FTTI(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_STMR_FTTI_SHIFT))&FCSMU_STMR_FTTI_MASK)
#define FCSMU_STMR_MTE_MASK 0x4000u
#define FCSMU_STMR_MTE_SHIFT 14u
#define FCSMU_STMR_MTE_WIDTH 1u
#define FCSMU_STMR_MTE(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_STMR_MTE_SHIFT))&FCSMU_STMR_MTE_MASK)
#define FCSMU_STMR_MINI_TIME_MASK 0x3FFFu
#define FCSMU_STMR_MINI_TIME_SHIFT 0u
#define FCSMU_STMR_MINI_TIME_WIDTH 14u
#define FCSMU_STMR_MINI_TIME(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_STMR_MINI_TIME_SHIFT))&FCSMU_STMR_MINI_TIME_MASK)
/* STMR Reg Mask */
#define FCSMU_STMR_MASK 0xC0007FFFu
/* WARNING_IEN0 Bit Fields */
#define FCSMU_WARNING_IEN0_EN_MASK 0xFFFFFFFFu
#define FCSMU_WARNING_IEN0_EN_SHIFT 0u
#define FCSMU_WARNING_IEN0_EN_WIDTH 32u
#define FCSMU_WARNING_IEN0_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_WARNING_IEN0_EN_SHIFT))&FCSMU_WARNING_IEN0_EN_MASK)
/* WARNING_IEN0 Reg Mask */
#define FCSMU_WARNING_IEN0_MASK 0xFFFFFFFFu
/* FAULT_IEN0 Bit Fields */
#define FCSMU_FAULT_IEN0_EN_MASK 0xFFFFFFFFu
#define FCSMU_FAULT_IEN0_EN_SHIFT 0u
#define FCSMU_FAULT_IEN0_EN_WIDTH 32u
#define FCSMU_FAULT_IEN0_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FAULT_IEN0_EN_SHIFT))&FCSMU_FAULT_IEN0_EN_MASK)
/* FAULT_IEN0 Reg Mask */
#define FCSMU_FAULT_IEN0_MASK 0xFFFFFFFFu
/* SOUT_EN0 Bit Fields */
#define FCSMU_SOUT_EN0_EN_MASK 0xFFFFFFFFu
#define FCSMU_SOUT_EN0_EN_SHIFT 0u
#define FCSMU_SOUT_EN0_EN_WIDTH 32u
#define FCSMU_SOUT_EN0_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOUT_EN0_EN_SHIFT))&FCSMU_SOUT_EN0_EN_MASK)
/* SOUT_EN0 Reg Mask */
#define FCSMU_SOUT_EN0_MASK 0xFFFFFFFFu
/* WARNING_TMR Bit Fields */
#define FCSMU_WARNING_TMR_VAL_MASK 0xFFFFFFFFu
#define FCSMU_WARNING_TMR_VAL_SHIFT 0u
#define FCSMU_WARNING_TMR_VAL_WIDTH 32u
#define FCSMU_WARNING_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_WARNING_TMR_VAL_SHIFT))&FCSMU_WARNING_TMR_VAL_MASK)
/* WARNING_TMR Reg Mask */
#define FCSMU_WARNING_TMR_MASK 0xFFFFFFFFu
/* SM_TMR Bit Fields */
#define FCSMU_SM_TMR_VAL_MASK 0xFFFFu
#define FCSMU_SM_TMR_VAL_SHIFT 0u
#define FCSMU_SM_TMR_VAL_WIDTH 16u
#define FCSMU_SM_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SM_TMR_VAL_SHIFT))&FCSMU_SM_TMR_VAL_MASK)
/* SM_TMR Reg Mask */
#define FCSMU_SM_TMR_MASK 0x0000FFFFu
/* CFG_TMR Bit Fields */
#define FCSMU_CFG_TMR_VAL_MASK 0x1FFFFFu
#define FCSMU_CFG_TMR_VAL_SHIFT 0u
#define FCSMU_CFG_TMR_VAL_WIDTH 21u
#define FCSMU_CFG_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CFG_TMR_VAL_SHIFT))&FCSMU_CFG_TMR_VAL_MASK)
/* CFG_TMR Reg Mask */
#define FCSMU_CFG_TMR_MASK 0x001FFFFFu
/* SOUT_TMR Bit Fields */
#define FCSMU_SOUT_TMR_VAL_MASK 0x7FFFFFu
#define FCSMU_SOUT_TMR_VAL_SHIFT 0u
#define FCSMU_SOUT_TMR_VAL_WIDTH 23u
#define FCSMU_SOUT_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOUT_TMR_VAL_SHIFT))&FCSMU_SOUT_TMR_VAL_MASK)
/* SOUT_TMR Reg Mask */
#define FCSMU_SOUT_TMR_MASK 0x007FFFFFu
/* CRC_CTRL Bit Fields */
#define FCSMU_CRC_CTRL_DONE_MASK 0x40u
#define FCSMU_CRC_CTRL_DONE_SHIFT 6u
#define FCSMU_CRC_CTRL_DONE_WIDTH 1u
#define FCSMU_CRC_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_DONE_SHIFT))&FCSMU_CRC_CTRL_DONE_MASK)
#define FCSMU_CRC_CTRL_EF_MASK 0x20u
#define FCSMU_CRC_CTRL_EF_SHIFT 5u
#define FCSMU_CRC_CTRL_EF_WIDTH 1u
#define FCSMU_CRC_CTRL_EF(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_EF_SHIFT))&FCSMU_CRC_CTRL_EF_MASK)
#define FCSMU_CRC_CTRL_BUSY_MASK 0x10u
#define FCSMU_CRC_CTRL_BUSY_SHIFT 4u
#define FCSMU_CRC_CTRL_BUSY_WIDTH 1u
#define FCSMU_CRC_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_BUSY_SHIFT))&FCSMU_CRC_CTRL_BUSY_MASK)
#define FCSMU_CRC_CTRL_EOEN_MASK 0x8u
#define FCSMU_CRC_CTRL_EOEN_SHIFT 3u
#define FCSMU_CRC_CTRL_EOEN_WIDTH 1u
#define FCSMU_CRC_CTRL_EOEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_EOEN_SHIFT))&FCSMU_CRC_CTRL_EOEN_MASK)
#define FCSMU_CRC_CTRL_CHKEN_MASK 0x4u
#define FCSMU_CRC_CTRL_CHKEN_SHIFT 2u
#define FCSMU_CRC_CTRL_CHKEN_WIDTH 1u
#define FCSMU_CRC_CTRL_CHKEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_CHKEN_SHIFT))&FCSMU_CRC_CTRL_CHKEN_MASK)
#define FCSMU_CRC_CTRL_TRGEN_MASK 0x2u
#define FCSMU_CRC_CTRL_TRGEN_SHIFT 1u
#define FCSMU_CRC_CTRL_TRGEN_WIDTH 1u
#define FCSMU_CRC_CTRL_TRGEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_TRGEN_SHIFT))&FCSMU_CRC_CTRL_TRGEN_MASK)
#define FCSMU_CRC_CTRL_GEN_MASK 0x1u
#define FCSMU_CRC_CTRL_GEN_SHIFT 0u
#define FCSMU_CRC_CTRL_GEN_WIDTH 1u
#define FCSMU_CRC_CTRL_GEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_GEN_SHIFT))&FCSMU_CRC_CTRL_GEN_MASK)
/* CRC_CTRL Reg Mask */
#define FCSMU_CRC_CTRL_MASK 0x0000007Fu
/* CRC_RES Bit Fields */
#define FCSMU_CRC_RES_RESULT_MASK 0xFFFFFFFFu
#define FCSMU_CRC_RES_RESULT_SHIFT 0u
#define FCSMU_CRC_RES_RESULT_WIDTH 32u
#define FCSMU_CRC_RES_RESULT(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_RES_RESULT_SHIFT))&FCSMU_CRC_RES_RESULT_MASK)
/* CRC_RES Reg Mask */
#define FCSMU_CRC_RES_MASK 0xFFFFFFFFu
/*!
* @}
*/ /* end of group FCSMU_Register_Masks */
/*!
* @}
*/ /* end of group FCSMU_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

821
fc/fc7240_fcspi_regs.h Normal file
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#ifndef _FC7240_FCSPI_NU_Tztufn50_REGS_H_
#define _FC7240_FCSPI_NU_Tztufn50_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- FCSPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FCSPI_Peripheral_Access_Layer FCSPI Peripheral Access Layer
* @{
*/
/** FCSPI - Size of Registers Arrays */
/** FCSPI - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[16];
__IO uint32_t CTRL ; /* Control Register, offset: 0x10 */
__IO uint32_t STATUS ; /* Status Register, offset: 0x14 */
__IO uint32_t INT_EN ; /* Interrupt Enable Register, offset: 0x18 */
__IO uint32_t DMA_EN ; /* DMA Enable Register, offset: 0x1C */
__IO uint32_t CFG0 ; /* Configuration Register 0, offset: 0x20 */
__IO uint32_t CFG1 ; /* Configuration Register 1, offset: 0x24 */
uint8_t RESERVED_1[8];
__IO uint32_t DATA_MATCH0 ; /* Data Match Register 0, offset: 0x30 */
__IO uint32_t DATA_MATCH1 ; /* Data Match Register 1, offset: 0x34 */
uint8_t RESERVED_2[8];
__IO uint32_t CLK_CFG ; /* Clock Configuration Register, offset: 0x40 */
uint8_t RESERVED_3[20];
__IO uint32_t FIFO_WTM ; /* FIFO Water Mark Register, offset: 0x58 */
__I uint32_t FIFO_STATUS ; /* FIFO Status Register, offset: 0x5C */
__IO uint32_t TR_CTRL ; /* Transmit and Receive Control Register, offset: 0x60 */
__O uint32_t TX_DATA ; /* Transmit Data Register, offset: 0x64 */
uint8_t RESERVED_4[8];
__I uint32_t RX_STATUS ; /* Receive Status Register, offset: 0x70 */
__I uint32_t RX_DATA ; /* Receive Data Register, offset: 0x74 */
} FCSPI_Type, *FCSPI_MemMapPtr;
/** Number of instances of the FCSPI module. */
#define FCSPI_INSTANCE_COUNT (6u)
/* FCSPI - Peripheral instance base addresses */
/** Peripheral FCSPI0 base address */
#define FCSPI0_BASE (0x40062000u)
/** Peripheral FCSPI0 base pointer */
#define FCSPI0 ((FCSPI_Type *)FCSPI0_BASE)
/** Peripheral FCSPI1 base address */
#define FCSPI1_BASE (0x40063000u)
/** Peripheral FCSPI1 base pointer */
#define FCSPI1 ((FCSPI_Type *)FCSPI1_BASE)
/** Peripheral FCSPI2 base address */
#define FCSPI2_BASE (0x40064000u)
/** Peripheral FCSPI2 base pointer */
#define FCSPI2 ((FCSPI_Type *)FCSPI2_BASE)
/** Peripheral FCSPI3 base address */
#define FCSPI3_BASE (0x4043f000u)
/** Peripheral FCSPI3 base pointer */
#define FCSPI3 ((FCSPI_Type *)FCSPI3_BASE)
/** Peripheral FCSPI4 base address */
#define FCSPI4_BASE (0x40440000u)
/** Peripheral FCSPI4 base pointer */
#define FCSPI4 ((FCSPI_Type *)FCSPI4_BASE)
/** Peripheral FCSPI5 base address */
#define FCSPI5_BASE (0x40441000u)
/** Peripheral FCSPI5 base pointer */
#define FCSPI5 ((FCSPI_Type *)FCSPI5_BASE)
/** Array initializer of FCSPI peripheral base addresses */
#define FCSPI_BASE_ADDRS {FCSPI0_BASE, FCSPI1_BASE, FCSPI2_BASE, FCSPI3_BASE, FCSPI4_BASE, FCSPI5_BASE}
/** Array initializer of FCSPI peripheral base pointers */
#define FCSPI_BASE_PTRS {FCSPI0, FCSPI1, FCSPI2, FCSPI3, FCSPI4, FCSPI5}
// need fill by yourself
///** Number of interrupt vector arrays for the FCSPI module. */
//#define FCSPI_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the FCSPI module. */
//#define FCSPI_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the FCSPI peripheral type */
//#define FCSPI_IRQS {FCSPI0_IRQn, FCSPI1_IRQn, FCSPI2_IRQn, FCSPI3_IRQn, FCSPI4_IRQn, FCSPI5_IRQn}
/* ----------------------------------------------------------------------------
-- FCSPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FCSPI_Register_Masks FCSPI Register Masks
* @{
*/
/* CTRL Bit Fields */
#define FCSPI_CTRL_RST_RF_MASK 0x200u
#define FCSPI_CTRL_RST_RF_SHIFT 9u
#define FCSPI_CTRL_RST_RF_WIDTH 1u
#define FCSPI_CTRL_RST_RF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CTRL_RST_RF_SHIFT))&FCSPI_CTRL_RST_RF_MASK)
#define FCSPI_CTRL_RST_TF_MASK 0x100u
#define FCSPI_CTRL_RST_TF_SHIFT 8u
#define FCSPI_CTRL_RST_TF_WIDTH 1u
#define FCSPI_CTRL_RST_TF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CTRL_RST_TF_SHIFT))&FCSPI_CTRL_RST_TF_MASK)
#define FCSPI_CTRL_DBG_EN_MASK 0x8u
#define FCSPI_CTRL_DBG_EN_SHIFT 3u
#define FCSPI_CTRL_DBG_EN_WIDTH 1u
#define FCSPI_CTRL_DBG_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CTRL_DBG_EN_SHIFT))&FCSPI_CTRL_DBG_EN_MASK)
#define FCSPI_CTRL_WAIT_DIS_MASK 0x4u
#define FCSPI_CTRL_WAIT_DIS_SHIFT 2u
#define FCSPI_CTRL_WAIT_DIS_WIDTH 1u
#define FCSPI_CTRL_WAIT_DIS(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CTRL_WAIT_DIS_SHIFT))&FCSPI_CTRL_WAIT_DIS_MASK)
#define FCSPI_CTRL_SW_RST_MASK 0x2u
#define FCSPI_CTRL_SW_RST_SHIFT 1u
#define FCSPI_CTRL_SW_RST_WIDTH 1u
#define FCSPI_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CTRL_SW_RST_SHIFT))&FCSPI_CTRL_SW_RST_MASK)
#define FCSPI_CTRL_M_EN_MASK 0x1u
#define FCSPI_CTRL_M_EN_SHIFT 0u
#define FCSPI_CTRL_M_EN_WIDTH 1u
#define FCSPI_CTRL_M_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CTRL_M_EN_SHIFT))&FCSPI_CTRL_M_EN_MASK)
/* CTRL Reg Mask */
#define FCSPI_CTRL_MASK 0x0000030Fu
/* STATUS Bit Fields */
#define FCSPI_STATUS_BF_MASK 0x1000000u
#define FCSPI_STATUS_BF_SHIFT 24u
#define FCSPI_STATUS_BF_WIDTH 1u
#define FCSPI_STATUS_BF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_BF_SHIFT))&FCSPI_STATUS_BF_MASK)
#define FCSPI_STATUS_DMF_MASK 0x2000u
#define FCSPI_STATUS_DMF_SHIFT 13u
#define FCSPI_STATUS_DMF_WIDTH 1u
#define FCSPI_STATUS_DMF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_DMF_SHIFT))&FCSPI_STATUS_DMF_MASK)
#define FCSPI_STATUS_RX_FO_MASK 0x1000u
#define FCSPI_STATUS_RX_FO_SHIFT 12u
#define FCSPI_STATUS_RX_FO_WIDTH 1u
#define FCSPI_STATUS_RX_FO(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_RX_FO_SHIFT))&FCSPI_STATUS_RX_FO_MASK)
#define FCSPI_STATUS_TX_FU_MASK 0x800u
#define FCSPI_STATUS_TX_FU_SHIFT 11u
#define FCSPI_STATUS_TX_FU_WIDTH 1u
#define FCSPI_STATUS_TX_FU(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_TX_FU_SHIFT))&FCSPI_STATUS_TX_FU_MASK)
#define FCSPI_STATUS_TCF_MASK 0x400u
#define FCSPI_STATUS_TCF_SHIFT 10u
#define FCSPI_STATUS_TCF_WIDTH 1u
#define FCSPI_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_TCF_SHIFT))&FCSPI_STATUS_TCF_MASK)
#define FCSPI_STATUS_FEF_MASK 0x200u
#define FCSPI_STATUS_FEF_SHIFT 9u
#define FCSPI_STATUS_FEF_WIDTH 1u
#define FCSPI_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_FEF_SHIFT))&FCSPI_STATUS_FEF_MASK)
#define FCSPI_STATUS_RX_WF_MASK 0x100u
#define FCSPI_STATUS_RX_WF_SHIFT 8u
#define FCSPI_STATUS_RX_WF_WIDTH 1u
#define FCSPI_STATUS_RX_WF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_RX_WF_SHIFT))&FCSPI_STATUS_RX_WF_MASK)
#define FCSPI_STATUS_RX_FF_MASK 0x2u
#define FCSPI_STATUS_RX_FF_SHIFT 1u
#define FCSPI_STATUS_RX_FF_WIDTH 1u
#define FCSPI_STATUS_RX_FF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_RX_FF_SHIFT))&FCSPI_STATUS_RX_FF_MASK)
#define FCSPI_STATUS_TX_FF_MASK 0x1u
#define FCSPI_STATUS_TX_FF_SHIFT 0u
#define FCSPI_STATUS_TX_FF_WIDTH 1u
#define FCSPI_STATUS_TX_FF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_TX_FF_SHIFT))&FCSPI_STATUS_TX_FF_MASK)
/* STATUS Reg Mask */
#define FCSPI_STATUS_MASK 0x01003F03u
/* INT_EN Bit Fields */
#define FCSPI_INT_EN_DMIE_MASK 0x2000u
#define FCSPI_INT_EN_DMIE_SHIFT 13u
#define FCSPI_INT_EN_DMIE_WIDTH 1u
#define FCSPI_INT_EN_DMIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_DMIE_SHIFT))&FCSPI_INT_EN_DMIE_MASK)
#define FCSPI_INT_EN_RFOIE_MASK 0x1000u
#define FCSPI_INT_EN_RFOIE_SHIFT 12u
#define FCSPI_INT_EN_RFOIE_WIDTH 1u
#define FCSPI_INT_EN_RFOIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_RFOIE_SHIFT))&FCSPI_INT_EN_RFOIE_MASK)
#define FCSPI_INT_EN_TFUIE_MASK 0x800u
#define FCSPI_INT_EN_TFUIE_SHIFT 11u
#define FCSPI_INT_EN_TFUIE_WIDTH 1u
#define FCSPI_INT_EN_TFUIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_TFUIE_SHIFT))&FCSPI_INT_EN_TFUIE_MASK)
#define FCSPI_INT_EN_TCIE_MASK 0x400u
#define FCSPI_INT_EN_TCIE_SHIFT 10u
#define FCSPI_INT_EN_TCIE_WIDTH 1u
#define FCSPI_INT_EN_TCIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_TCIE_SHIFT))&FCSPI_INT_EN_TCIE_MASK)
#define FCSPI_INT_EN_FEIE_MASK 0x200u
#define FCSPI_INT_EN_FEIE_SHIFT 9u
#define FCSPI_INT_EN_FEIE_WIDTH 1u
#define FCSPI_INT_EN_FEIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_FEIE_SHIFT))&FCSPI_INT_EN_FEIE_MASK)
#define FCSPI_INT_EN_RWIE_MASK 0x100u
#define FCSPI_INT_EN_RWIE_SHIFT 8u
#define FCSPI_INT_EN_RWIE_WIDTH 1u
#define FCSPI_INT_EN_RWIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_RWIE_SHIFT))&FCSPI_INT_EN_RWIE_MASK)
#define FCSPI_INT_EN_RFIE_MASK 0x2u
#define FCSPI_INT_EN_RFIE_SHIFT 1u
#define FCSPI_INT_EN_RFIE_WIDTH 1u
#define FCSPI_INT_EN_RFIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_RFIE_SHIFT))&FCSPI_INT_EN_RFIE_MASK)
#define FCSPI_INT_EN_TFIE_MASK 0x1u
#define FCSPI_INT_EN_TFIE_SHIFT 0u
#define FCSPI_INT_EN_TFIE_WIDTH 1u
#define FCSPI_INT_EN_TFIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_TFIE_SHIFT))&FCSPI_INT_EN_TFIE_MASK)
/* INT_EN Reg Mask */
#define FCSPI_INT_EN_MASK 0x00003F03u
/* DMA_EN Bit Fields */
#define FCSPI_DMA_EN_RFDE_MASK 0x2u
#define FCSPI_DMA_EN_RFDE_SHIFT 1u
#define FCSPI_DMA_EN_RFDE_WIDTH 1u
#define FCSPI_DMA_EN_RFDE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_DMA_EN_RFDE_SHIFT))&FCSPI_DMA_EN_RFDE_MASK)
#define FCSPI_DMA_EN_TFDE_MASK 0x1u
#define FCSPI_DMA_EN_TFDE_SHIFT 0u
#define FCSPI_DMA_EN_TFDE_WIDTH 1u
#define FCSPI_DMA_EN_TFDE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_DMA_EN_TFDE_SHIFT))&FCSPI_DMA_EN_TFDE_MASK)
/* DMA_EN Reg Mask */
#define FCSPI_DMA_EN_MASK 0x00000003u
/* CFG0 Bit Fields */
#define FCSPI_CFG0_AKDS_MASK 0x400u
#define FCSPI_CFG0_AKDS_SHIFT 10u
#define FCSPI_CFG0_AKDS_WIDTH 1u
#define FCSPI_CFG0_AKDS(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG0_AKDS_SHIFT))&FCSPI_CFG0_AKDS_MASK)
#define FCSPI_CFG0_RDMO_MASK 0x200u
#define FCSPI_CFG0_RDMO_SHIFT 9u
#define FCSPI_CFG0_RDMO_WIDTH 1u
#define FCSPI_CFG0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG0_RDMO_SHIFT))&FCSPI_CFG0_RDMO_MASK)
#define FCSPI_CFG0_TRGEN_MASK 0x1u
#define FCSPI_CFG0_TRGEN_SHIFT 0u
#define FCSPI_CFG0_TRGEN_WIDTH 1u
#define FCSPI_CFG0_TRGEN(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG0_TRGEN_SHIFT))&FCSPI_CFG0_TRGEN_MASK)
/* CFG0 Reg Mask */
#define FCSPI_CFG0_MASK 0x00000601u
/* CFG1 Bit Fields */
#define FCSPI_CFG1_PCS_CFG_MASK 0x8000000u
#define FCSPI_CFG1_PCS_CFG_SHIFT 27u
#define FCSPI_CFG1_PCS_CFG_WIDTH 1u
#define FCSPI_CFG1_PCS_CFG(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_PCS_CFG_SHIFT))&FCSPI_CFG1_PCS_CFG_MASK)
#define FCSPI_CFG1_OUT_CFG_MASK 0x4000000u
#define FCSPI_CFG1_OUT_CFG_SHIFT 26u
#define FCSPI_CFG1_OUT_CFG_WIDTH 1u
#define FCSPI_CFG1_OUT_CFG(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_OUT_CFG_SHIFT))&FCSPI_CFG1_OUT_CFG_MASK)
#define FCSPI_CFG1_PIN_CFG_MASK 0x3000000u
#define FCSPI_CFG1_PIN_CFG_SHIFT 24u
#define FCSPI_CFG1_PIN_CFG_WIDTH 2u
#define FCSPI_CFG1_PIN_CFG(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_PIN_CFG_SHIFT))&FCSPI_CFG1_PIN_CFG_MASK)
#define FCSPI_CFG1_MAT_CFG_MASK 0x70000u
#define FCSPI_CFG1_MAT_CFG_SHIFT 16u
#define FCSPI_CFG1_MAT_CFG_WIDTH 3u
#define FCSPI_CFG1_MAT_CFG(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_MAT_CFG_SHIFT))&FCSPI_CFG1_MAT_CFG_MASK)
#define FCSPI_CFG1_PCS_POL_MASK 0xF00u
#define FCSPI_CFG1_PCS_POL_SHIFT 8u
#define FCSPI_CFG1_PCS_POL_WIDTH 4u
#define FCSPI_CFG1_PCS_POL(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_PCS_POL_SHIFT))&FCSPI_CFG1_PCS_POL_MASK)
#define FCSPI_CFG1_INT_PCS_MASK 0x4u
#define FCSPI_CFG1_INT_PCS_SHIFT 2u
#define FCSPI_CFG1_INT_PCS_WIDTH 1u
#define FCSPI_CFG1_INT_PCS(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_INT_PCS_SHIFT))&FCSPI_CFG1_INT_PCS_MASK)
#define FCSPI_CFG1_SCK_LB_MASK 0x2u
#define FCSPI_CFG1_SCK_LB_SHIFT 1u
#define FCSPI_CFG1_SCK_LB_WIDTH 1u
#define FCSPI_CFG1_SCK_LB(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_SCK_LB_SHIFT))&FCSPI_CFG1_SCK_LB_MASK)
#define FCSPI_CFG1_MASTER_MASK 0x1u
#define FCSPI_CFG1_MASTER_SHIFT 0u
#define FCSPI_CFG1_MASTER_WIDTH 1u
#define FCSPI_CFG1_MASTER(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_MASTER_SHIFT))&FCSPI_CFG1_MASTER_MASK)
/* CFG1 Reg Mask */
#define FCSPI_CFG1_MASK 0x0F070F07u
/* DATA_MATCH0 Bit Fields */
#define FCSPI_DATA_MATCH0_DATA0_MASK 0xFFFFFFFFu
#define FCSPI_DATA_MATCH0_DATA0_SHIFT 0u
#define FCSPI_DATA_MATCH0_DATA0_WIDTH 32u
#define FCSPI_DATA_MATCH0_DATA0(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_DATA_MATCH0_DATA0_SHIFT))&FCSPI_DATA_MATCH0_DATA0_MASK)
/* DATA_MATCH0 Reg Mask */
#define FCSPI_DATA_MATCH0_MASK 0xFFFFFFFFu
/* DATA_MATCH1 Bit Fields */
#define FCSPI_DATA_MATCH1_DATA1_MASK 0xFFFFFFFFu
#define FCSPI_DATA_MATCH1_DATA1_SHIFT 0u
#define FCSPI_DATA_MATCH1_DATA1_WIDTH 32u
#define FCSPI_DATA_MATCH1_DATA1(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_DATA_MATCH1_DATA1_SHIFT))&FCSPI_DATA_MATCH1_DATA1_MASK)
/* DATA_MATCH1 Reg Mask */
#define FCSPI_DATA_MATCH1_MASK 0xFFFFFFFFu
/* CLK_CFG Bit Fields */
#define FCSPI_CLK_CFG_SCKPCS_MASK 0xFF000000u
#define FCSPI_CLK_CFG_SCKPCS_SHIFT 24u
#define FCSPI_CLK_CFG_SCKPCS_WIDTH 8u
#define FCSPI_CLK_CFG_SCKPCS(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CLK_CFG_SCKPCS_SHIFT))&FCSPI_CLK_CFG_SCKPCS_MASK)
#define FCSPI_CLK_CFG_PCSSCK_MASK 0xFF0000u
#define FCSPI_CLK_CFG_PCSSCK_SHIFT 16u
#define FCSPI_CLK_CFG_PCSSCK_WIDTH 8u
#define FCSPI_CLK_CFG_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CLK_CFG_PCSSCK_SHIFT))&FCSPI_CLK_CFG_PCSSCK_MASK)
#define FCSPI_CLK_CFG_PCSPCS_MASK 0xFF00u
#define FCSPI_CLK_CFG_PCSPCS_SHIFT 8u
#define FCSPI_CLK_CFG_PCSPCS_WIDTH 8u
#define FCSPI_CLK_CFG_PCSPCS(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CLK_CFG_PCSPCS_SHIFT))&FCSPI_CLK_CFG_PCSPCS_MASK)
#define FCSPI_CLK_CFG_SCKDIV_MASK 0xFFu
#define FCSPI_CLK_CFG_SCKDIV_SHIFT 0u
#define FCSPI_CLK_CFG_SCKDIV_WIDTH 8u
#define FCSPI_CLK_CFG_SCKDIV(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CLK_CFG_SCKDIV_SHIFT))&FCSPI_CLK_CFG_SCKDIV_MASK)
/* CLK_CFG Reg Mask */
#define FCSPI_CLK_CFG_MASK 0xFFFFFFFFu
/* FIFO_WTM Bit Fields */
#define FCSPI_FIFO_WTM_RXWATER_MASK 0x70000u
#define FCSPI_FIFO_WTM_RXWATER_SHIFT 16u
#define FCSPI_FIFO_WTM_RXWATER_WIDTH 3u
#define FCSPI_FIFO_WTM_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_FIFO_WTM_RXWATER_SHIFT))&FCSPI_FIFO_WTM_RXWATER_MASK)
#define FCSPI_FIFO_WTM_TXWATER_MASK 0x7u
#define FCSPI_FIFO_WTM_TXWATER_SHIFT 0u
#define FCSPI_FIFO_WTM_TXWATER_WIDTH 3u
#define FCSPI_FIFO_WTM_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_FIFO_WTM_TXWATER_SHIFT))&FCSPI_FIFO_WTM_TXWATER_MASK)
/* FIFO_WTM Reg Mask */
#define FCSPI_FIFO_WTM_MASK 0x00070007u
/* FIFO_STATUS Bit Fields */
#define FCSPI_FIFO_STATUS_RXCNT_MASK 0xF0000u
#define FCSPI_FIFO_STATUS_RXCNT_SHIFT 16u
#define FCSPI_FIFO_STATUS_RXCNT_WIDTH 4u
#define FCSPI_FIFO_STATUS_RXCNT(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_FIFO_STATUS_RXCNT_SHIFT))&FCSPI_FIFO_STATUS_RXCNT_MASK)
#define FCSPI_FIFO_STATUS_TXCNT_MASK 0xFu
#define FCSPI_FIFO_STATUS_TXCNT_SHIFT 0u
#define FCSPI_FIFO_STATUS_TXCNT_WIDTH 4u
#define FCSPI_FIFO_STATUS_TXCNT(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_FIFO_STATUS_TXCNT_SHIFT))&FCSPI_FIFO_STATUS_TXCNT_MASK)
/* FIFO_STATUS Reg Mask */
#define FCSPI_FIFO_STATUS_MASK 0x000F000Fu
/* TR_CTRL Bit Fields */
#define FCSPI_TR_CTRL_SCK_POL_MASK 0x80000000u
#define FCSPI_TR_CTRL_SCK_POL_SHIFT 31u
#define FCSPI_TR_CTRL_SCK_POL_WIDTH 1u
#define FCSPI_TR_CTRL_SCK_POL(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_SCK_POL_SHIFT))&FCSPI_TR_CTRL_SCK_POL_MASK)
#define FCSPI_TR_CTRL_SCK_PHA_MASK 0x40000000u
#define FCSPI_TR_CTRL_SCK_PHA_SHIFT 30u
#define FCSPI_TR_CTRL_SCK_PHA_WIDTH 1u
#define FCSPI_TR_CTRL_SCK_PHA(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_SCK_PHA_SHIFT))&FCSPI_TR_CTRL_SCK_PHA_MASK)
#define FCSPI_TR_CTRL_PRESCALE_MASK 0x38000000u
#define FCSPI_TR_CTRL_PRESCALE_SHIFT 27u
#define FCSPI_TR_CTRL_PRESCALE_WIDTH 3u
#define FCSPI_TR_CTRL_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_PRESCALE_SHIFT))&FCSPI_TR_CTRL_PRESCALE_MASK)
#define FCSPI_TR_CTRL_PCS_MASK 0x3000000u
#define FCSPI_TR_CTRL_PCS_SHIFT 24u
#define FCSPI_TR_CTRL_PCS_WIDTH 2u
#define FCSPI_TR_CTRL_PCS(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_PCS_SHIFT))&FCSPI_TR_CTRL_PCS_MASK)
#define FCSPI_TR_CTRL_LSBF_MASK 0x800000u
#define FCSPI_TR_CTRL_LSBF_SHIFT 23u
#define FCSPI_TR_CTRL_LSBF_WIDTH 1u
#define FCSPI_TR_CTRL_LSBF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_LSBF_SHIFT))&FCSPI_TR_CTRL_LSBF_MASK)
#define FCSPI_TR_CTRL_BYSW_MASK 0x400000u
#define FCSPI_TR_CTRL_BYSW_SHIFT 22u
#define FCSPI_TR_CTRL_BYSW_WIDTH 1u
#define FCSPI_TR_CTRL_BYSW(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_BYSW_SHIFT))&FCSPI_TR_CTRL_BYSW_MASK)
#define FCSPI_TR_CTRL_CT_EN_MASK 0x200000u
#define FCSPI_TR_CTRL_CT_EN_SHIFT 21u
#define FCSPI_TR_CTRL_CT_EN_WIDTH 1u
#define FCSPI_TR_CTRL_CT_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_CT_EN_SHIFT))&FCSPI_TR_CTRL_CT_EN_MASK)
#define FCSPI_TR_CTRL_CT_GO_MASK 0x100000u
#define FCSPI_TR_CTRL_CT_GO_SHIFT 20u
#define FCSPI_TR_CTRL_CT_GO_WIDTH 1u
#define FCSPI_TR_CTRL_CT_GO(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_CT_GO_SHIFT))&FCSPI_TR_CTRL_CT_GO_MASK)
#define FCSPI_TR_CTRL_RX_MSK_MASK 0x80000u
#define FCSPI_TR_CTRL_RX_MSK_SHIFT 19u
#define FCSPI_TR_CTRL_RX_MSK_WIDTH 1u
#define FCSPI_TR_CTRL_RX_MSK(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_RX_MSK_SHIFT))&FCSPI_TR_CTRL_RX_MSK_MASK)
#define FCSPI_TR_CTRL_TX_MSK_MASK 0x40000u
#define FCSPI_TR_CTRL_TX_MSK_SHIFT 18u
#define FCSPI_TR_CTRL_TX_MSK_WIDTH 1u
#define FCSPI_TR_CTRL_TX_MSK(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_TX_MSK_SHIFT))&FCSPI_TR_CTRL_TX_MSK_MASK)
#define FCSPI_TR_CTRL_WIDTH_MASK 0x30000u
#define FCSPI_TR_CTRL_WIDTH_SHIFT 16u
#define FCSPI_TR_CTRL_WIDTH_WIDTH 2u
#define FCSPI_TR_CTRL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_WIDTH_SHIFT))&FCSPI_TR_CTRL_WIDTH_MASK)
#define FCSPI_TR_CTRL_FRM_SZ_MASK 0xFFFu
#define FCSPI_TR_CTRL_FRM_SZ_SHIFT 0u
#define FCSPI_TR_CTRL_FRM_SZ_WIDTH 12u
#define FCSPI_TR_CTRL_FRM_SZ(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_FRM_SZ_SHIFT))&FCSPI_TR_CTRL_FRM_SZ_MASK)
/* TR_CTRL Reg Mask */
#define FCSPI_TR_CTRL_MASK 0xFBFF0FFFu
/* TX_DATA Bit Fields */
#define FCSPI_TX_DATA_DATA_MASK 0xFFFFFFFFu
#define FCSPI_TX_DATA_DATA_SHIFT 0u
#define FCSPI_TX_DATA_DATA_WIDTH 32u
#define FCSPI_TX_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TX_DATA_DATA_SHIFT))&FCSPI_TX_DATA_DATA_MASK)
/* TX_DATA Reg Mask */
#define FCSPI_TX_DATA_MASK 0xFFFFFFFFu
/* RX_STATUS Bit Fields */
#define FCSPI_RX_STATUS_RX_EMPTY_MASK 0x2u
#define FCSPI_RX_STATUS_RX_EMPTY_SHIFT 1u
#define FCSPI_RX_STATUS_RX_EMPTY_WIDTH 1u
#define FCSPI_RX_STATUS_RX_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_RX_STATUS_RX_EMPTY_SHIFT))&FCSPI_RX_STATUS_RX_EMPTY_MASK)
#define FCSPI_RX_STATUS_FD_MASK 0x1u
#define FCSPI_RX_STATUS_FD_SHIFT 0u
#define FCSPI_RX_STATUS_FD_WIDTH 1u
#define FCSPI_RX_STATUS_FD(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_RX_STATUS_FD_SHIFT))&FCSPI_RX_STATUS_FD_MASK)
/* RX_STATUS Reg Mask */
#define FCSPI_RX_STATUS_MASK 0x00000003u
/* RX_DATA Bit Fields */
#define FCSPI_RX_DATA_RX_DATA_MASK 0xFFFFFFFFu
#define FCSPI_RX_DATA_RX_DATA_SHIFT 0u
#define FCSPI_RX_DATA_RX_DATA_WIDTH 32u
#define FCSPI_RX_DATA_RX_DATA(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_RX_DATA_RX_DATA_SHIFT))&FCSPI_RX_DATA_RX_DATA_MASK)
/* RX_DATA Reg Mask */
#define FCSPI_RX_DATA_MASK 0xFFFFFFFFu
/*!
* @}
*/ /* end of group FCSPI_Register_Masks */
/*!
* @}
*/ /* end of group FCSPI_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_FMC_NU_Tztufn25_REGS_H_
#define _FC7240_FMC_NU_Tztufn25_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- FMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
* @{
*/
/** FMC - Size of Registers Arrays */
/** FMC - Register Layout Typedef */
#define FMC_FB_FPELCK_COUNT 5
#define FMC_FB_CPELCK_COUNT 4
#define FMC_OTA_CTRL_COUNT 2
#define FMC_OTA_VER_LOC_COUNT 2
#define FMC_OTA_ACT_VER_COUNT 2
typedef struct {
__IO uint32_t FAPC0 ; /* Flash Access Port Control Register 0, offset: 0x0 */
__IO uint32_t FAPC1 ; /* Flash Access Port Control Register 1, offset: 0x4 */
__IO uint32_t FAPC2 ; /* Flash Access Port Control Register 2, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t FEEC ; /* Flash ECC Error Control Register, offset: 0x10 */
uint8_t RESERVED_1[4];
__IO uint32_t FEIPC ; /* Flash ECC Inject Position Control Register, offset: 0x18 */
uint8_t RESERVED_2[740];
__IO uint32_t FPESA_L ; /* Flash Program Erase Start Address Logical Register, offset: 0x300 */
__I uint32_t FPESA_P ; /* Flash Program Erase Start Address Physical Register, offset: 0x304 */
uint8_t RESERVED_3[56];
__IO uint32_t FB_FPELCK[FMC_FB_FPELCK_COUNT]; /* Flash Block n Fine Program Erase Lock Register, offset: 0x340 */
uint8_t RESERVED_4[4];
__IO uint32_t FN_FPELCK ; /* Flash NVR Fine Program Erase Lock Register, offset: 0x358 */
__IO uint32_t FB_CPELCK[FMC_FB_CPELCK_COUNT]; /* Flash Block n Coarse Program Erase Lock Register, offset: 0x35c */
uint8_t RESERVED_5[404];
__IO uint32_t OTA_CTRL[FMC_OTA_CTRL_COUNT] ; /* FLASH OTA Control Register, offset: 0x500 */
__I uint32_t OTA_VER_LOC[FMC_OTA_VER_LOC_COUNT]; /* FLASH OTA Version Location Register, offset: 0x508 */
__I uint32_t OTA_ACT_VER[FMC_OTA_ACT_VER_COUNT]; /* FLASH OTA Active Version Register, offset: 0x510 */
} FMC_Type, *FMC_MemMapPtr;
/** Number of instances of the FMC module. */
#define FMC_INSTANCE_COUNT (2u)
/* FMC - Peripheral instance base addresses */
/** Peripheral FMC1 base address */
#define FMC1_BASE (0x4001e000u)
/** Peripheral FMC1 base pointer */
#define FMC1 ((FMC_Type *)FMC1_BASE)
/** Peripheral FMC0 base address */
#define FMC0_BASE (0x4001f000u)
/** Peripheral FMC0 base pointer */
#define FMC0 ((FMC_Type *)FMC0_BASE)
/** Array initializer of FMC peripheral base addresses */
#define FMC_BASE_ADDRS {FMC0_BASE, FMC1_BASE}
/** Array initializer of FMC peripheral base pointers */
#define FMC_BASE_PTRS {FMC0, FMC1}
// need fill by yourself
///** Number of interrupt vector arrays for the FMC module. */
//#define FMC_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the FMC module. */
//#define FMC_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the FMC peripheral type */
//#define FMC_IRQS {FMC0_IRQn, FMC1_IRQn}
/* ----------------------------------------------------------------------------
-- FMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FMC_Register_Masks FMC Register Masks
* @{
*/
/* FAPC0 Bit Fields */
#define FMC_FAPC0_DBPEN_MASK 0x20u
#define FMC_FAPC0_DBPEN_SHIFT 5u
#define FMC_FAPC0_DBPEN_WIDTH 1u
#define FMC_FAPC0_DBPEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC0_DBPEN_SHIFT))&FMC_FAPC0_DBPEN_MASK)
#define FMC_FAPC0_CBPEN_MASK 0x10u
#define FMC_FAPC0_CBPEN_SHIFT 4u
#define FMC_FAPC0_CBPEN_WIDTH 1u
#define FMC_FAPC0_CBPEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC0_CBPEN_SHIFT))&FMC_FAPC0_CBPEN_MASK)
#define FMC_FAPC0_DBBEN_MASK 0x2u
#define FMC_FAPC0_DBBEN_SHIFT 1u
#define FMC_FAPC0_DBBEN_WIDTH 1u
#define FMC_FAPC0_DBBEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC0_DBBEN_SHIFT))&FMC_FAPC0_DBBEN_MASK)
#define FMC_FAPC0_CBBEN_MASK 0x1u
#define FMC_FAPC0_CBBEN_SHIFT 0u
#define FMC_FAPC0_CBBEN_WIDTH 1u
#define FMC_FAPC0_CBBEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC0_CBBEN_SHIFT))&FMC_FAPC0_CBBEN_MASK)
/* FAPC0 Reg Mask */
#define FMC_FAPC0_MASK 0x00000033u
/* FAPC1 Bit Fields */
#define FMC_FAPC1_DBPEN_MASK 0x20u
#define FMC_FAPC1_DBPEN_SHIFT 5u
#define FMC_FAPC1_DBPEN_WIDTH 1u
#define FMC_FAPC1_DBPEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC1_DBPEN_SHIFT))&FMC_FAPC1_DBPEN_MASK)
#define FMC_FAPC1_CBPEN_MASK 0x10u
#define FMC_FAPC1_CBPEN_SHIFT 4u
#define FMC_FAPC1_CBPEN_WIDTH 1u
#define FMC_FAPC1_CBPEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC1_CBPEN_SHIFT))&FMC_FAPC1_CBPEN_MASK)
#define FMC_FAPC1_DBBEN_MASK 0x2u
#define FMC_FAPC1_DBBEN_SHIFT 1u
#define FMC_FAPC1_DBBEN_WIDTH 1u
#define FMC_FAPC1_DBBEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC1_DBBEN_SHIFT))&FMC_FAPC1_DBBEN_MASK)
#define FMC_FAPC1_CBBEN_MASK 0x1u
#define FMC_FAPC1_CBBEN_SHIFT 0u
#define FMC_FAPC1_CBBEN_WIDTH 1u
#define FMC_FAPC1_CBBEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC1_CBBEN_SHIFT))&FMC_FAPC1_CBBEN_MASK)
/* FAPC1 Reg Mask */
#define FMC_FAPC1_MASK 0x00000033u
/* FAPC2 Bit Fields */
#define FMC_FAPC2_DBPEN_MASK 0x20u
#define FMC_FAPC2_DBPEN_SHIFT 5u
#define FMC_FAPC2_DBPEN_WIDTH 1u
#define FMC_FAPC2_DBPEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC2_DBPEN_SHIFT))&FMC_FAPC2_DBPEN_MASK)
#define FMC_FAPC2_CBPEN_MASK 0x10u
#define FMC_FAPC2_CBPEN_SHIFT 4u
#define FMC_FAPC2_CBPEN_WIDTH 1u
#define FMC_FAPC2_CBPEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC2_CBPEN_SHIFT))&FMC_FAPC2_CBPEN_MASK)
#define FMC_FAPC2_DBBEN_MASK 0x2u
#define FMC_FAPC2_DBBEN_SHIFT 1u
#define FMC_FAPC2_DBBEN_WIDTH 1u
#define FMC_FAPC2_DBBEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC2_DBBEN_SHIFT))&FMC_FAPC2_DBBEN_MASK)
#define FMC_FAPC2_CBBEN_MASK 0x1u
#define FMC_FAPC2_CBBEN_SHIFT 0u
#define FMC_FAPC2_CBBEN_WIDTH 1u
#define FMC_FAPC2_CBBEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC2_CBBEN_SHIFT))&FMC_FAPC2_CBBEN_MASK)
/* FAPC2 Reg Mask */
#define FMC_FAPC2_MASK 0x00000033u
/* FEEC Bit Fields */
#define FMC_FEEC_CEIE_SET_MASK 0xF0000000u
#define FMC_FEEC_CEIE_SET_SHIFT 28u
#define FMC_FEEC_CEIE_SET_WIDTH 4u
#define FMC_FEEC_CEIE_SET(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEEC_CEIE_SET_SHIFT))&FMC_FEEC_CEIE_SET_MASK)
#define FMC_FEEC_EIE_SET_MASK 0xF000000u
#define FMC_FEEC_EIE_SET_SHIFT 24u
#define FMC_FEEC_EIE_SET_WIDTH 4u
#define FMC_FEEC_EIE_SET(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEEC_EIE_SET_SHIFT))&FMC_FEEC_EIE_SET_MASK)
#define FMC_FEEC_EDATAC_POS2_MASK 0xF00000u
#define FMC_FEEC_EDATAC_POS2_SHIFT 20u
#define FMC_FEEC_EDATAC_POS2_WIDTH 4u
#define FMC_FEEC_EDATAC_POS2(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEEC_EDATAC_POS2_SHIFT))&FMC_FEEC_EDATAC_POS2_MASK)
#define FMC_FEEC_EDATAC_POS1_MASK 0xF0000u
#define FMC_FEEC_EDATAC_POS1_SHIFT 16u
#define FMC_FEEC_EDATAC_POS1_WIDTH 4u
#define FMC_FEEC_EDATAC_POS1(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEEC_EDATAC_POS1_SHIFT))&FMC_FEEC_EDATAC_POS1_MASK)
#define FMC_FEEC_DDBEE_MASK 0x80u
#define FMC_FEEC_DDBEE_SHIFT 7u
#define FMC_FEEC_DDBEE_WIDTH 1u
#define FMC_FEEC_DDBEE(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEEC_DDBEE_SHIFT))&FMC_FEEC_DDBEE_MASK)
#define FMC_FEEC_DES_MASK 0x1u
#define FMC_FEEC_DES_SHIFT 0u
#define FMC_FEEC_DES_WIDTH 1u
#define FMC_FEEC_DES(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEEC_DES_SHIFT))&FMC_FEEC_DES_MASK)
/* FEEC Reg Mask */
#define FMC_FEEC_MASK 0xFFFF0081u
/* FEIPC Bit Fields */
#define FMC_FEIPC_EDATA_POS1_MASK 0x1FFu
#define FMC_FEIPC_EDATA_POS1_SHIFT 0u
#define FMC_FEIPC_EDATA_POS1_WIDTH 9u
#define FMC_FEIPC_EDATA_POS1(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEIPC_EDATA_POS1_SHIFT))&FMC_FEIPC_EDATA_POS1_MASK)
#define FMC_FEIPC_EDATA_POS2_MASK 0x1FF0000u
#define FMC_FEIPC_EDATA_POS2_SHIFT 16u
#define FMC_FEIPC_EDATA_POS2_WIDTH 9u
#define FMC_FEIPC_EDATA_POS2(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEIPC_EDATA_POS2_SHIFT))&FMC_FEIPC_EDATA_POS2_MASK)
/* FEIPC Reg Mask */
#define FMC_FEIPC_MASK 0x01FF01FFu
/* FPESA_L Bit Fields */
#define FMC_FPESA_L_PESA_L_MASK 0xFFFFFFFFu
#define FMC_FPESA_L_PESA_L_SHIFT 0u
#define FMC_FPESA_L_PESA_L_WIDTH 32u
#define FMC_FPESA_L_PESA_L(x) (((uint32_t)(((uint32_t)(x))<<FMC_FPESA_L_PESA_L_SHIFT))&FMC_FPESA_L_PESA_L_MASK)
/* FPESA_L Reg Mask */
#define FMC_FPESA_L_MASK 0xFFFFFFFFu
/* FPESA_P Bit Fields */
#define FMC_FPESA_P_PESA_P_MASK 0xFFFFFFFFu
#define FMC_FPESA_P_PESA_P_SHIFT 0u
#define FMC_FPESA_P_PESA_P_WIDTH 32u
#define FMC_FPESA_P_PESA_P(x) (((uint32_t)(((uint32_t)(x))<<FMC_FPESA_P_PESA_P_SHIFT))&FMC_FPESA_P_PESA_P_MASK)
/* FPESA_P Reg Mask */
#define FMC_FPESA_P_MASK 0xFFFFFFFFu
/* FB_FPELCK Bit Fields */
#define FMC_FB_FPELCK_FPELCK_MASK 0xFFFFFFFFu
#define FMC_FB_FPELCK_FPELCK_SHIFT 0u
#define FMC_FB_FPELCK_FPELCK_WIDTH 32u
#define FMC_FB_FPELCK_FPELCK(x) (((uint32_t)(((uint32_t)(x))<<FMC_FB_FPELCK_FPELCK_SHIFT))&FMC_FB_FPELCK_FPELCK_MASK)
/* FB_FPELCK0 Reg Mask */
#define FMC_FB_FPELCK_MASK 0xFFFFFFFFu
/* FN_FPELCK Bit Fields */
#define FMC_FN_FPELCK_FPELCK_MASK 0x1u
#define FMC_FN_FPELCK_FPELCK_SHIFT 0u
#define FMC_FN_FPELCK_FPELCK_WIDTH 1u
#define FMC_FN_FPELCK_FPELCK(x) (((uint32_t)(((uint32_t)(x))<<FMC_FN_FPELCK_FPELCK_SHIFT))&FMC_FN_FPELCK_FPELCK_MASK)
/* FN_FPELCK Reg Mask */
#define FMC_FN_FPELCK_MASK 0x00000001u
/* FB_CPELCK Bit Fields */
#define FMC_FB_CPELCK_CPELCK_MASK 0xFFFFFFFFu
#define FMC_FB_CPELCK_CPELCK_SHIFT 0u
#define FMC_FB_CPELCK_CPELCK_WIDTH 32u
#define FMC_FB_CPELCK_CPELCK(x) (((uint32_t)(((uint32_t)(x))<<FMC_FB_CPELCK_CPELCK_SHIFT))&FMC_FB_CPELCK_CPELCK_MASK)
/* FB_CPELCK0 Reg Mask */
#define FMC_FB_CPELCK_MASK 0xFFFFFFFFu
/* OTA_CTRL Bit Fields */
#define FMC_OTA_CTRL_OTA_LOCK_MASK 0x40u
#define FMC_OTA_CTRL_OTA_LOCK_SHIFT 6u
#define FMC_OTA_CTRL_OTA_LOCK_WIDTH 1u
#define FMC_OTA_CTRL_OTA_LOCK(x) (((uint32_t)(((uint32_t)(x))<<FMC_OTA_CTRL_OTA_LOCK_SHIFT))&FMC_OTA_CTRL_OTA_LOCK_MASK)
#define FMC_OTA_CTRL_OTA_ACTIVE_MASK 0x20u
#define FMC_OTA_CTRL_OTA_ACTIVE_SHIFT 5u
#define FMC_OTA_CTRL_OTA_ACTIVE_WIDTH 1u
#define FMC_OTA_CTRL_OTA_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<FMC_OTA_CTRL_OTA_ACTIVE_SHIFT))&FMC_OTA_CTRL_OTA_ACTIVE_MASK)
#define FMC_OTA_CTRL_OTA_EN_MASK 0x1Fu
#define FMC_OTA_CTRL_OTA_EN_SHIFT 0u
#define FMC_OTA_CTRL_OTA_EN_WIDTH 5u
#define FMC_OTA_CTRL_OTA_EN(x) (((uint32_t)(((uint32_t)(x))<<FMC_OTA_CTRL_OTA_EN_SHIFT))&FMC_OTA_CTRL_OTA_EN_MASK)
/* OTA_CTRL0 Reg Mask */
#define FMC_OTA_CTRL_MASK 0x0000007Fu
/* OTA_VER_LOC Bit Fields */
#define FMC_OTA_VER_LOC_OTA_VER_LOC_MASK 0xFFFFFu
#define FMC_OTA_VER_LOC_OTA_VER_LOC_SHIFT 0u
#define FMC_OTA_VER_LOC_OTA_VER_LOC_WIDTH 20u
#define FMC_OTA_VER_LOC_OTA_VER_LOC(x) (((uint32_t)(((uint32_t)(x))<<FMC_OTA_VER_LOC_OTA_VER_LOC_SHIFT))&FMC_OTA_VER_LOC_OTA_VER_LOC_MASK)
/* OTA_VER_LOC0 Reg Mask */
#define FMC_OTA_VER_LOC_MASK 0x000FFFFFu
/* OTA_ACT_VER Bit Fields */
#define FMC_OTA_ACT_VER_OTA_ACT_VER_MASK 0xFFFFu
#define FMC_OTA_ACT_VER_OTA_ACT_VER_SHIFT 0u
#define FMC_OTA_ACT_VER_OTA_ACT_VER_WIDTH 16u
#define FMC_OTA_ACT_VER_OTA_ACT_VER(x) (((uint32_t)(((uint32_t)(x))<<FMC_OTA_ACT_VER_OTA_ACT_VER_SHIFT))&FMC_OTA_ACT_VER_OTA_ACT_VER_MASK)
/* OTA_ACT_VER0 Reg Mask */
#define FMC_OTA_ACT_VER_MASK 0x0000FFFFu
/*!
* @}
*/ /* end of group FMC_Register_Masks */
/*!
* @}
*/ /* end of group FMC_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_FREQM_NU_Tztufn8_REGS_H_
#define _FC7240_FREQM_NU_Tztufn8_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- FREQM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FREQM_Peripheral_Access_Layer FREQM Peripheral Access Layer
* @{
*/
/** FREQM - Size of Registers Arrays */
/** FREQM - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL ; /* Control Register, offset: 0x0 */
__IO uint32_t MES_CNT ; /* Measure Counter Register, offset: 0x4 */
__O uint32_t REF_CNT ; /* Reference Counter Register, offset: 0x8 */
__IO uint32_t MES_LENGTH ; /* Measure Counter Length Register, offset: 0xC */
__IO uint32_t REF_TIMEOUT ; /* Reference Counter Timeout Register, offset: 0x10 */
__IO uint32_t CNT_STATUS ; /* Counter Status Register, offset: 0x14 */
uint8_t RESERVED_0[4];
__I uint32_t REF_CNT_SAVE ; /* Saved Reference Counter Register, offset: 0x1C */
} FREQM_Type, *FREQM_MemMapPtr;
/** Number of instances of the FREQM module. */
#define FREQM_INSTANCE_COUNT (1u)
/* FREQM - Peripheral instance base addresses */
/** Peripheral FREQM base address */
#define FREQM_BASE (0x40078000u)
/** Peripheral FREQM base pointer */
#define FREQM ((FREQM_Type *)FREQM_BASE)
/** Array initializer of FREQM peripheral base addresses */
#define FREQM_BASE_ADDRS {FREQM_BASE}
/** Array initializer of FREQM peripheral base pointers */
#define FREQM_BASE_PTRS {FREQM}
// need fill by yourself
///** Number of interrupt vector arrays for the FREQM module. */
//#define FREQM_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the FREQM module. */
//#define FREQM_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the FREQM peripheral type */
//#define FREQM_IRQS {FREQM_IRQn}
/* ----------------------------------------------------------------------------
-- FREQM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FREQM_Register_Masks FREQM Register Masks
* @{
*/
/* CTRL Bit Fields */
#define FREQM_CTRL_CNT_EVENT_IE_MASK 0x4000u
#define FREQM_CTRL_CNT_EVENT_IE_SHIFT 14u
#define FREQM_CTRL_CNT_EVENT_IE_WIDTH 1u
#define FREQM_CTRL_CNT_EVENT_IE(x) (((uint32_t)(((uint32_t)(x))<<FREQM_CTRL_CNT_EVENT_IE_SHIFT))&FREQM_CTRL_CNT_EVENT_IE_MASK)
#define FREQM_CTRL_MES_CLK_SEL_MASK 0x3F00u
#define FREQM_CTRL_MES_CLK_SEL_SHIFT 8u
#define FREQM_CTRL_MES_CLK_SEL_WIDTH 6u
#define FREQM_CTRL_MES_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<FREQM_CTRL_MES_CLK_SEL_SHIFT))&FREQM_CTRL_MES_CLK_SEL_MASK)
#define FREQM_CTRL_MES_CLK_PREDIV_MASK 0xFFu
#define FREQM_CTRL_MES_CLK_PREDIV_SHIFT 0u
#define FREQM_CTRL_MES_CLK_PREDIV_WIDTH 8u
#define FREQM_CTRL_MES_CLK_PREDIV(x) (((uint32_t)(((uint32_t)(x))<<FREQM_CTRL_MES_CLK_PREDIV_SHIFT))&FREQM_CTRL_MES_CLK_PREDIV_MASK)
/* CTRL Reg Mask */
#define FREQM_CTRL_MASK 0x00007FFFu
/* MES_CNT Bit Fields */
#define FREQM_MES_CNT_MES_CNT_MASK 0xFFFFFFFFu
#define FREQM_MES_CNT_MES_CNT_SHIFT 0u
#define FREQM_MES_CNT_MES_CNT_WIDTH 32u
#define FREQM_MES_CNT_MES_CNT(x) (((uint32_t)(((uint32_t)(x))<<FREQM_MES_CNT_MES_CNT_SHIFT))&FREQM_MES_CNT_MES_CNT_MASK)
/* MES_CNT Reg Mask */
#define FREQM_MES_CNT_MASK 0xFFFFFFFFu
/* REF_CNT Bit Fields */
#define FREQM_REF_CNT_REF_CNT_MASK 0xFFFFFFFFu
#define FREQM_REF_CNT_REF_CNT_SHIFT 0u
#define FREQM_REF_CNT_REF_CNT_WIDTH 32u
#define FREQM_REF_CNT_REF_CNT(x) (((uint32_t)(((uint32_t)(x))<<FREQM_REF_CNT_REF_CNT_SHIFT))&FREQM_REF_CNT_REF_CNT_MASK)
/* REF_CNT Reg Mask */
#define FREQM_REF_CNT_MASK 0xFFFFFFFFu
/* MES_LENGTH Bit Fields */
#define FREQM_MES_LENGTH_MES_LENGTH_MASK 0xFFFFFFFFu
#define FREQM_MES_LENGTH_MES_LENGTH_SHIFT 0u
#define FREQM_MES_LENGTH_MES_LENGTH_WIDTH 32u
#define FREQM_MES_LENGTH_MES_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<FREQM_MES_LENGTH_MES_LENGTH_SHIFT))&FREQM_MES_LENGTH_MES_LENGTH_MASK)
/* MES_LENGTH Reg Mask */
#define FREQM_MES_LENGTH_MASK 0xFFFFFFFFu
/* REF_TIMEOUT Bit Fields */
#define FREQM_REF_TIMEOUT_REF_TIMEOUT_MASK 0xFFFFFFFFu
#define FREQM_REF_TIMEOUT_REF_TIMEOUT_SHIFT 0u
#define FREQM_REF_TIMEOUT_REF_TIMEOUT_WIDTH 32u
#define FREQM_REF_TIMEOUT_REF_TIMEOUT(x) (((uint32_t)(((uint32_t)(x))<<FREQM_REF_TIMEOUT_REF_TIMEOUT_SHIFT))&FREQM_REF_TIMEOUT_REF_TIMEOUT_MASK)
/* REF_TIMEOUT Reg Mask */
#define FREQM_REF_TIMEOUT_MASK 0xFFFFFFFFu
/* CNT_STATUS Bit Fields */
#define FREQM_CNT_STATUS_CNT_EVENT_MASK 0x80u
#define FREQM_CNT_STATUS_CNT_EVENT_SHIFT 7u
#define FREQM_CNT_STATUS_CNT_EVENT_WIDTH 1u
#define FREQM_CNT_STATUS_CNT_EVENT(x) (((uint32_t)(((uint32_t)(x))<<FREQM_CNT_STATUS_CNT_EVENT_SHIFT))&FREQM_CNT_STATUS_CNT_EVENT_MASK)
#define FREQM_CNT_STATUS_MES_CNT_START_MASK 0x4u
#define FREQM_CNT_STATUS_MES_CNT_START_SHIFT 2u
#define FREQM_CNT_STATUS_MES_CNT_START_WIDTH 1u
#define FREQM_CNT_STATUS_MES_CNT_START(x) (((uint32_t)(((uint32_t)(x))<<FREQM_CNT_STATUS_MES_CNT_START_SHIFT))&FREQM_CNT_STATUS_MES_CNT_START_MASK)
#define FREQM_CNT_STATUS_MES_CNT_STOP_MASK 0x2u
#define FREQM_CNT_STATUS_MES_CNT_STOP_SHIFT 1u
#define FREQM_CNT_STATUS_MES_CNT_STOP_WIDTH 1u
#define FREQM_CNT_STATUS_MES_CNT_STOP(x) (((uint32_t)(((uint32_t)(x))<<FREQM_CNT_STATUS_MES_CNT_STOP_SHIFT))&FREQM_CNT_STATUS_MES_CNT_STOP_MASK)
#define FREQM_CNT_STATUS_REF_CNT_STOP_MASK 0x1u
#define FREQM_CNT_STATUS_REF_CNT_STOP_SHIFT 0u
#define FREQM_CNT_STATUS_REF_CNT_STOP_WIDTH 1u
#define FREQM_CNT_STATUS_REF_CNT_STOP(x) (((uint32_t)(((uint32_t)(x))<<FREQM_CNT_STATUS_REF_CNT_STOP_SHIFT))&FREQM_CNT_STATUS_REF_CNT_STOP_MASK)
/* CNT_STATUS Reg Mask */
#define FREQM_CNT_STATUS_MASK 0x00000087u
/* REF_CNT_SAVE Bit Fields */
#define FREQM_REF_CNT_SAVE_REF_CNT_SAVE_MASK 0xFFFFFFFFu
#define FREQM_REF_CNT_SAVE_REF_CNT_SAVE_SHIFT 0u
#define FREQM_REF_CNT_SAVE_REF_CNT_SAVE_WIDTH 32u
#define FREQM_REF_CNT_SAVE_REF_CNT_SAVE(x) (((uint32_t)(((uint32_t)(x))<<FREQM_REF_CNT_SAVE_REF_CNT_SAVE_SHIFT))&FREQM_REF_CNT_SAVE_REF_CNT_SAVE_MASK)
/* REF_CNT_SAVE Reg Mask */
#define FREQM_REF_CNT_SAVE_MASK 0xFFFFFFFFu
/*!
* @}
*/ /* end of group FREQM_Register_Masks */
/*!
* @}
*/ /* end of group FREQM_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7240_ftu_regs.h Normal file
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283
fc/fc7240_gpio_regs.h Normal file
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#ifndef _FC7240_GPIO_NU_Tztufn42_REGS_H_
#define _FC7240_GPIO_NU_Tztufn42_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- GPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
* @{
*/
/** GPIO - Size of Registers Arrays */
/** GPIO - Register Layout Typedef */
typedef struct {
__IO uint32_t PDOR ; /* Port Data Output Register, offset: 0x0 */
__O uint32_t PSOR ; /* Port Set Output Register, offset: 0x4 */
__O uint32_t PCOR ; /* Port Clear Output Register, offset: 0x8 */
__O uint32_t PTOR ; /* Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR ; /* Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR ; /* Port Data Direction Register, offset: 0x14 */
__IO uint32_t PIDR ; /* Port Input Disable Register, offset: 0x18 */
} GPIO_Type, *GPIO_MemMapPtr;
/** Number of instances of the GPIO module. */
#define GPIO_INSTANCE_COUNT (5u)
/* GPIO - Peripheral instance base addresses */
/** Peripheral GPIOA base address */
#define GPIOA_BASE (0x41000000u)
/** Peripheral GPIOA base pointer */
#define GPIOA ((GPIO_Type *)GPIOA_BASE)
/** Peripheral GPIOB base address */
#define GPIOB_BASE (0x41000040u)
/** Peripheral GPIOB base pointer */
#define GPIOB ((GPIO_Type *)GPIOB_BASE)
/** Peripheral GPIOC base address */
#define GPIOC_BASE (0x41000080u)
/** Peripheral GPIOC base pointer */
#define GPIOC ((GPIO_Type *)GPIOC_BASE)
/** Peripheral GPIOD base address */
#define GPIOD_BASE (0x410000c0u)
/** Peripheral GPIOD base pointer */
#define GPIOD ((GPIO_Type *)GPIOD_BASE)
/** Peripheral GPIOE base address */
#define GPIOE_BASE (0x41000100u)
/** Peripheral GPIOE base pointer */
#define GPIOE ((GPIO_Type *)GPIOE_BASE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS {GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE}
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE}
// need fill by yourself
///** Number of interrupt vector arrays for the GPIO module. */
//#define GPIO_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the GPIO module. */
//#define GPIO_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the GPIO peripheral type */
//#define GPIO_IRQS {GPIOA_IRQn, GPIOB_IRQn, GPIOC_IRQn, GPIOD_IRQn, GPIOE_IRQn}
/* ----------------------------------------------------------------------------
-- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
/* PDOR Bit Fields */
#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
#define GPIO_PDOR_PDO_SHIFT 0u
#define GPIO_PDOR_PDO_WIDTH 32u
#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
/* PDOR Reg Mask */
#define GPIO_PDOR_MASK 0xFFFFFFFFu
/* PSOR Bit Fields */
#define GPIO_PSOR_PSO_MASK 0xFFFFFFFFu
#define GPIO_PSOR_PSO_SHIFT 0u
#define GPIO_PSOR_PSO_WIDTH 32u
#define GPIO_PSOR_PSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PSO_SHIFT))&GPIO_PSOR_PSO_MASK)
/* PSOR Reg Mask */
#define GPIO_PSOR_MASK 0xFFFFFFFFu
/* PCOR Bit Fields */
#define GPIO_PCOR_PCO_MASK 0xFFFFFFFFu
#define GPIO_PCOR_PCO_SHIFT 0u
#define GPIO_PCOR_PCO_WIDTH 32u
#define GPIO_PCOR_PCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PCO_SHIFT))&GPIO_PCOR_PCO_MASK)
/* PCOR Reg Mask */
#define GPIO_PCOR_MASK 0xFFFFFFFFu
/* PTOR Bit Fields */
#define GPIO_PTOR_PTO_MASK 0xFFFFFFFFu
#define GPIO_PTOR_PTO_SHIFT 0u
#define GPIO_PTOR_PTO_WIDTH 32u
#define GPIO_PTOR_PTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTO_SHIFT))&GPIO_PTOR_PTO_MASK)
/* PTOR Reg Mask */
#define GPIO_PTOR_MASK 0xFFFFFFFFu
/* PDIR Bit Fields */
#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
#define GPIO_PDIR_PDI_SHIFT 0u
#define GPIO_PDIR_PDI_WIDTH 32u
#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
/* PDIR Reg Mask */
#define GPIO_PDIR_MASK 0xFFFFFFFFu
/* PDDR Bit Fields */
#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
#define GPIO_PDDR_PDD_SHIFT 0u
#define GPIO_PDDR_PDD_WIDTH 32u
#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
/* PDDR Reg Mask */
#define GPIO_PDDR_MASK 0xFFFFFFFFu
/* PIDR Bit Fields */
#define GPIO_PIDR_PID_MASK 0xFFFFFFFFu
#define GPIO_PIDR_PID_SHIFT 0u
#define GPIO_PIDR_PID_WIDTH 32u
#define GPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PIDR_PID_SHIFT))&GPIO_PIDR_PID_MASK)
/* PIDR Reg Mask */
#define GPIO_PIDR_MASK 0xFFFFFFFFu
/*!
* @}
*/ /* end of group GPIO_Register_Masks */
/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_INTM_NU_Tztufn10_REGS_H_
#define _FC7240_INTM_NU_Tztufn10_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- INTM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup INTM_Peripheral_Access_Layer INTM Peripheral Access Layer
* @{
*/
/** INTM - Size of Registers Arrays */
/** INTM - Register Layout Typedef */
typedef struct {
__IO uint32_t ER ; /* Enable Register, offset: 0x0 */
__IO uint32_t IACKR ; /* Interrupt Acknowledge Register, offset: 0x4 */
__IO uint32_t IRQSELR0 ; /* Interrupt Request Select Register, offset: 0x8 */
__IO uint32_t LATR0 ; /* Latency Register, offset: 0xc */
__IO uint32_t TMR0 ; /* Timer Register, offset: 0x10 */
__I uint32_t SR0 ; /* Status Register, offset: 0x14 */
__IO uint32_t IRQSELR1 ; /* Interrupt Request Select Register, offset: 0x18 */
__IO uint32_t LATR1 ; /* Latency Register, offset: 0x1c */
__IO uint32_t TMR1 ; /* Timer Register, offset: 0x20 */
__I uint32_t SR1 ; /* Status Register, offset: 0x24 */
} INTM_Type, *INTM_MemMapPtr;
/** Number of instances of the INTM module. */
#define INTM_INSTANCE_COUNT (1u)
/* INTM - Peripheral instance base addresses */
/** Peripheral INTM base address */
#define INTM_BASE (0x4001a000u)
/** Peripheral INTM base pointer */
#define INTM ((INTM_Type *)INTM_BASE)
/** Array initializer of INTM peripheral base addresses */
#define INTM_BASE_ADDRS {INTM_BASE}
/** Array initializer of INTM peripheral base pointers */
#define INTM_BASE_PTRS {INTM}
// need fill by yourself
///** Number of interrupt vector arrays for the INTM module. */
//#define INTM_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the INTM module. */
//#define INTM_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the INTM peripheral type */
//#define INTM_IRQS {INTM_IRQn}
/* ----------------------------------------------------------------------------
-- INTM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup INTM_Register_Masks INTM Register Masks
* @{
*/
/* ER Bit Fields */
#define INTM_ER_EN_MASK 0x1u
#define INTM_ER_EN_SHIFT 0u
#define INTM_ER_EN_WIDTH 1u
#define INTM_ER_EN(x) (((uint32_t)(((uint32_t)(x))<<INTM_ER_EN_SHIFT))&INTM_ER_EN_MASK)
/* ER Reg Mask */
#define INTM_ER_MASK 0x00000001u
/* IACKR Bit Fields */
#define INTM_IACKR_IRQ_MASK 0x3FFu
#define INTM_IACKR_IRQ_SHIFT 0u
#define INTM_IACKR_IRQ_WIDTH 10u
#define INTM_IACKR_IRQ(x) (((uint32_t)(((uint32_t)(x))<<INTM_IACKR_IRQ_SHIFT))&INTM_IACKR_IRQ_MASK)
/* IACKR Reg Mask */
#define INTM_IACKR_MASK 0x000003FFu
/* IRQSELR Bit Fields */
#define INTM_IRQSELR_RSTE_MASK 0x80000000u
#define INTM_IRQSELR_RSTE_SHIFT 31u
#define INTM_IRQSELR_RSTE_WIDTH 1u
#define INTM_IRQSELR_RSTE(x) (((uint32_t)(((uint32_t)(x))<<INTM_IRQSELR_RSTE_SHIFT))&INTM_IRQSELR_RSTE_MASK)
#define INTM_IRQSELR_INTE_MASK 0x40000000u
#define INTM_IRQSELR_INTE_SHIFT 30u
#define INTM_IRQSELR_INTE_WIDTH 1u
#define INTM_IRQSELR_INTE(x) (((uint32_t)(((uint32_t)(x))<<INTM_IRQSELR_INTE_SHIFT))&INTM_IRQSELR_INTE_MASK)
#define INTM_IRQSELR_IACTE_MASK 0x20000000u
#define INTM_IRQSELR_IACTE_SHIFT 29u
#define INTM_IRQSELR_IACTE_WIDTH 1u
#define INTM_IRQSELR_IACTE(x) (((uint32_t)(((uint32_t)(x))<<INTM_IRQSELR_IACTE_SHIFT))&INTM_IRQSELR_IACTE_MASK)
#define INTM_IRQSELR_IACTST_MASK 0x10000u
#define INTM_IRQSELR_IACTST_SHIFT 16u
#define INTM_IRQSELR_IACTST_WIDTH 1u
#define INTM_IRQSELR_IACTST(x) (((uint32_t)(((uint32_t)(x))<<INTM_IRQSELR_IACTST_SHIFT))&INTM_IRQSELR_IACTST_MASK)
#define INTM_IRQSELR_IRQ_MASK 0x3FFu
#define INTM_IRQSELR_IRQ_SHIFT 0u
#define INTM_IRQSELR_IRQ_WIDTH 10u
#define INTM_IRQSELR_IRQ(x) (((uint32_t)(((uint32_t)(x))<<INTM_IRQSELR_IRQ_SHIFT))&INTM_IRQSELR_IRQ_MASK)
/* IRQSELR0 Reg Mask */
#define INTM_IRQSELR_MASK 0xE00103FFu
/* LATR Bit Fields */
#define INTM_LATR_LAT_MASK 0xFFFFFFu
#define INTM_LATR_LAT_SHIFT 0u
#define INTM_LATR_LAT_WIDTH 24u
#define INTM_LATR_LAT(x) (((uint32_t)(((uint32_t)(x))<<INTM_LATR_LAT_SHIFT))&INTM_LATR_LAT_MASK)
/* LATR0 Reg Mask */
#define INTM_LATR_MASK 0x00FFFFFFu
/* TMR Bit Fields */
#define INTM_TMR_TIMER_MASK 0xFFFFFFu
#define INTM_TMR_TIMER_SHIFT 0u
#define INTM_TMR_TIMER_WIDTH 24u
#define INTM_TMR_TIMER(x) (((uint32_t)(((uint32_t)(x))<<INTM_TMR_TIMER_SHIFT))&INTM_TMR_TIMER_MASK)
/* TMR0 Reg Mask */
#define INTM_TMR_MASK 0x00FFFFFFu
/* SR Bit Fields */
#define INTM_SR_STATUS_MASK 0x1u
#define INTM_SR_STATUS_SHIFT 0u
#define INTM_SR_STATUS_WIDTH 1u
#define INTM_SR_STATUS(x) (((uint32_t)(((uint32_t)(x))<<INTM_SR_STATUS_SHIFT))&INTM_SR_STATUS_MASK)
/* SR0 Reg Mask */
#define INTM_SR_MASK 0x00000001u
/*!
* @}
*/ /* end of group INTM_Register_Masks */
/*!
* @}
*/ /* end of group INTM_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_ISM_NU_Tztufn11_REGS_H_
#define _FC7240_ISM_NU_Tztufn11_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- ISM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ISM_Peripheral_Access_Layer ISM Peripheral Access Layer
* @{
*/
/** ISM - Size of Registers Arrays */
/** ISM - Register Layout Typedef */
typedef struct {
__I uint32_t PARAM ; /* Parameter Register, offset: 0x0 */
__IO uint32_t CTRL ; /* Control Register, offset: 0x4 */
__IO uint32_t E_STATUS ; /* Event Status Register, offset: 0x8 */
__IO uint32_t E_CTRL ; /* Event Control Register, offset: 0xC */
__IO uint32_t EC_CTRL ; /* Event Control Mode Control Register, offset: 0x10 */
uint8_t RESERVED_0[236];
__IO uint32_t FPC_STATUS0 ; /* FPC Status Register, offset: 0x100 */
__IO uint32_t FPC_CTRL0 ; /* FPC Control Register, offset: 0x104 */
__IO uint32_t FPC_CONFIG0 ; /* FPC Configuration Register, offset: 0x108 */
__IO uint32_t FPC_TIMER0 ; /* FPC Timer Register, offset: 0x10c */
__IO uint32_t FPC_STATUS1 ; /* FPC Status Register, offset: 0x110 */
__IO uint32_t FPC_CTRL1 ; /* FPC Control Register, offset: 0x114 */
__IO uint32_t FPC_CONFIG1 ; /* FPC Configuration Register, offset: 0x118 */
__IO uint32_t FPC_TIMER1 ; /* FPC Timer Register, offset: 0x11c */
__IO uint32_t FPC_STATUS2 ; /* FPC Status Register, offset: 0x120 */
__IO uint32_t FPC_CTRL2 ; /* FPC Control Register, offset: 0x124 */
__IO uint32_t FPC_CONFIG2 ; /* FPC Configuration Register, offset: 0x128 */
__IO uint32_t FPC_TIMER2 ; /* FPC Timer Register, offset: 0x12c */
__IO uint32_t FPC_STATUS3 ; /* FPC Status Register, offset: 0x130 */
__IO uint32_t FPC_CTRL3 ; /* FPC Control Register, offset: 0x134 */
__IO uint32_t FPC_CONFIG3 ; /* FPC Configuration Register, offset: 0x138 */
__IO uint32_t FPC_TIMER3 ; /* FPC Timer Register, offset: 0x13c */
__IO uint32_t FPC_STATUS4 ; /* FPC Status Register, offset: 0x140 */
__IO uint32_t FPC_CTRL4 ; /* FPC Control Register, offset: 0x144 */
__IO uint32_t FPC_CONFIG4 ; /* FPC Configuration Register, offset: 0x148 */
__IO uint32_t FPC_TIMER4 ; /* FPC Timer Register, offset: 0x14c */
__IO uint32_t FPC_STATUS5 ; /* FPC Status Register, offset: 0x150 */
__IO uint32_t FPC_CTRL5 ; /* FPC Control Register, offset: 0x154 */
__IO uint32_t FPC_CONFIG5 ; /* FPC Configuration Register, offset: 0x158 */
__IO uint32_t FPC_TIMER5 ; /* FPC Timer Register, offset: 0x15c */
__IO uint32_t FPC_STATUS6 ; /* FPC Status Register, offset: 0x160 */
__IO uint32_t FPC_CTRL6 ; /* FPC Control Register, offset: 0x164 */
__IO uint32_t FPC_CONFIG6 ; /* FPC Configuration Register, offset: 0x168 */
__IO uint32_t FPC_TIMER6 ; /* FPC Timer Register, offset: 0x16c */
__IO uint32_t FPC_STATUS7 ; /* FPC Status Register, offset: 0x170 */
__IO uint32_t FPC_CTRL7 ; /* FPC Control Register, offset: 0x174 */
__IO uint32_t FPC_CONFIG7 ; /* FPC Configuration Register, offset: 0x178 */
__IO uint32_t FPC_TIMER7 ; /* FPC Timer Register, offset: 0x17c */
__IO uint32_t FPC_STATUS8 ; /* FPC Status Register, offset: 0x180 */
__IO uint32_t FPC_CTRL8 ; /* FPC Control Register, offset: 0x184 */
__IO uint32_t FPC_CONFIG8 ; /* FPC Configuration Register, offset: 0x188 */
__IO uint32_t FPC_TIMER8 ; /* FPC Timer Register, offset: 0x18c */
__IO uint32_t FPC_STATUS9 ; /* FPC Status Register, offset: 0x190 */
__IO uint32_t FPC_CTRL9 ; /* FPC Control Register, offset: 0x194 */
__IO uint32_t FPC_CONFIG9 ; /* FPC Configuration Register, offset: 0x198 */
__IO uint32_t FPC_TIMER9 ; /* FPC Timer Register, offset: 0x19c */
__IO uint32_t FPC_STATUS10 ; /* FPC Status Register, offset: 0x1a0 */
__IO uint32_t FPC_CTRL10 ; /* FPC Control Register, offset: 0x1a4 */
__IO uint32_t FPC_CONFIG10 ; /* FPC Configuration Register, offset: 0x1a8 */
__IO uint32_t FPC_TIMER10 ; /* FPC Timer Register, offset: 0x1ac */
__IO uint32_t FPC_STATUS11 ; /* FPC Status Register, offset: 0x1b0 */
__IO uint32_t FPC_CTRL11 ; /* FPC Control Register, offset: 0x1b4 */
__IO uint32_t FPC_CONFIG11 ; /* FPC Configuration Register, offset: 0x1b8 */
__IO uint32_t FPC_TIMER11 ; /* FPC Timer Register, offset: 0x1bc */
__IO uint32_t FPC_STATUS12 ; /* FPC Status Register, offset: 0x1c0 */
__IO uint32_t FPC_CTRL12 ; /* FPC Control Register, offset: 0x1c4 */
__IO uint32_t FPC_CONFIG12 ; /* FPC Configuration Register, offset: 0x1c8 */
__IO uint32_t FPC_TIMER12 ; /* FPC Timer Register, offset: 0x1cc */
__IO uint32_t FPC_STATUS13 ; /* FPC Status Register, offset: 0x1d0 */
__IO uint32_t FPC_CTRL13 ; /* FPC Control Register, offset: 0x1d4 */
__IO uint32_t FPC_CONFIG13 ; /* FPC Configuration Register, offset: 0x1d8 */
__IO uint32_t FPC_TIMER13 ; /* FPC Timer Register, offset: 0x1dc */
__IO uint32_t FPC_STATUS14 ; /* FPC Status Register, offset: 0x1e0 */
__IO uint32_t FPC_CTRL14 ; /* FPC Control Register, offset: 0x1e4 */
__IO uint32_t FPC_CONFIG14 ; /* FPC Configuration Register, offset: 0x1e8 */
__IO uint32_t FPC_TIMER14 ; /* FPC Timer Register, offset: 0x1ec */
__IO uint32_t FPC_STATUS15 ; /* FPC Status Register, offset: 0x1f0 */
__IO uint32_t FPC_CTRL15 ; /* FPC Control Register, offset: 0x1f4 */
__IO uint32_t FPC_CONFIG15 ; /* FPC Configuration Register, offset: 0x1f8 */
__IO uint32_t FPC_TIMER15 ; /* FPC Timer Register, offset: 0x1fc */
uint8_t RESERVED_1[512];
__IO uint32_t LAM_STATUS0 ; /* LAM Status Register, offset: 0x400 */
__IO uint32_t LAM_CTRL0 ; /* LAM Control Register, offset: 0x404 */
__IO uint32_t LAM_CONFIG0 ; /* LAM Configuration Register, offset: 0x408 */
__IO uint32_t LAM_COUNTER0 ; /* LAM Counter Register, offset: 0x40c */
__IO uint32_t LAM_STATUS1 ; /* LAM Status Register, offset: 0x410 */
__IO uint32_t LAM_CTRL1 ; /* LAM Control Register, offset: 0x414 */
__IO uint32_t LAM_CONFIG1 ; /* LAM Configuration Register, offset: 0x418 */
__IO uint32_t LAM_COUNTER1 ; /* LAM Counter Register, offset: 0x41c */
__IO uint32_t LAM_STATUS2 ; /* LAM Status Register, offset: 0x420 */
__IO uint32_t LAM_CTRL2 ; /* LAM Control Register, offset: 0x424 */
__IO uint32_t LAM_CONFIG2 ; /* LAM Configuration Register, offset: 0x428 */
__IO uint32_t LAM_COUNTER2 ; /* LAM Counter Register, offset: 0x42c */
__IO uint32_t LAM_STATUS3 ; /* LAM Status Register, offset: 0x430 */
__IO uint32_t LAM_CTRL3 ; /* LAM Control Register, offset: 0x434 */
__IO uint32_t LAM_CONFIG3 ; /* LAM Configuration Register, offset: 0x438 */
__IO uint32_t LAM_COUNTER3 ; /* LAM Counter Register, offset: 0x43c */
__IO uint32_t LAM_STATUS4 ; /* LAM Status Register, offset: 0x440 */
__IO uint32_t LAM_CTRL4 ; /* LAM Control Register, offset: 0x444 */
__IO uint32_t LAM_CONFIG4 ; /* LAM Configuration Register, offset: 0x448 */
__IO uint32_t LAM_COUNTER4 ; /* LAM Counter Register, offset: 0x44c */
__IO uint32_t LAM_STATUS5 ; /* LAM Status Register, offset: 0x450 */
__IO uint32_t LAM_CTRL5 ; /* LAM Control Register, offset: 0x454 */
__IO uint32_t LAM_CONFIG5 ; /* LAM Configuration Register, offset: 0x458 */
__IO uint32_t LAM_COUNTER5 ; /* LAM Counter Register, offset: 0x45c */
__IO uint32_t LAM_STATUS6 ; /* LAM Status Register, offset: 0x460 */
__IO uint32_t LAM_CTRL6 ; /* LAM Control Register, offset: 0x464 */
__IO uint32_t LAM_CONFIG6 ; /* LAM Configuration Register, offset: 0x468 */
__IO uint32_t LAM_COUNTER6 ; /* LAM Counter Register, offset: 0x46c */
__IO uint32_t LAM_STATUS7 ; /* LAM Status Register, offset: 0x470 */
__IO uint32_t LAM_CTRL7 ; /* LAM Control Register, offset: 0x474 */
__IO uint32_t LAM_CONFIG7 ; /* LAM Configuration Register, offset: 0x478 */
__IO uint32_t LAM_COUNTER7 ; /* LAM Counter Register, offset: 0x47c */
__IO uint32_t LAM_STATUS8 ; /* LAM Status Register, offset: 0x480 */
__IO uint32_t LAM_CTRL8 ; /* LAM Control Register, offset: 0x484 */
__IO uint32_t LAM_CONFIG8 ; /* LAM Configuration Register, offset: 0x488 */
__IO uint32_t LAM_COUNTER8 ; /* LAM Counter Register, offset: 0x48c */
__IO uint32_t LAM_STATUS9 ; /* LAM Status Register, offset: 0x490 */
__IO uint32_t LAM_CTRL9 ; /* LAM Control Register, offset: 0x494 */
__IO uint32_t LAM_CONFIG9 ; /* LAM Configuration Register, offset: 0x498 */
__IO uint32_t LAM_COUNTER9 ; /* LAM Counter Register, offset: 0x49c */
__IO uint32_t LAM_STATUS10 ; /* LAM Status Register, offset: 0x4a0 */
__IO uint32_t LAM_CTRL10 ; /* LAM Control Register, offset: 0x4a4 */
__IO uint32_t LAM_CONFIG10 ; /* LAM Configuration Register, offset: 0x4a8 */
__IO uint32_t LAM_COUNTER10 ; /* LAM Counter Register, offset: 0x4ac */
__IO uint32_t LAM_STATUS11 ; /* LAM Status Register, offset: 0x4b0 */
__IO uint32_t LAM_CTRL11 ; /* LAM Control Register, offset: 0x4b4 */
__IO uint32_t LAM_CONFIG11 ; /* LAM Configuration Register, offset: 0x4b8 */
__IO uint32_t LAM_COUNTER11 ; /* LAM Counter Register, offset: 0x4bc */
__IO uint32_t LAM_STATUS12 ; /* LAM Status Register, offset: 0x4c0 */
__IO uint32_t LAM_CTRL12 ; /* LAM Control Register, offset: 0x4c4 */
__IO uint32_t LAM_CONFIG12 ; /* LAM Configuration Register, offset: 0x4c8 */
__IO uint32_t LAM_COUNTER12 ; /* LAM Counter Register, offset: 0x4cc */
__IO uint32_t LAM_STATUS13 ; /* LAM Status Register, offset: 0x4d0 */
__IO uint32_t LAM_CTRL13 ; /* LAM Control Register, offset: 0x4d4 */
__IO uint32_t LAM_CONFIG13 ; /* LAM Configuration Register, offset: 0x4d8 */
__IO uint32_t LAM_COUNTER13 ; /* LAM Counter Register, offset: 0x4dc */
__IO uint32_t LAM_STATUS14 ; /* LAM Status Register, offset: 0x4e0 */
__IO uint32_t LAM_CTRL14 ; /* LAM Control Register, offset: 0x4e4 */
__IO uint32_t LAM_CONFIG14 ; /* LAM Configuration Register, offset: 0x4e8 */
__IO uint32_t LAM_COUNTER14 ; /* LAM Counter Register, offset: 0x4ec */
__IO uint32_t LAM_STATUS15 ; /* LAM Status Register, offset: 0x4f0 */
__IO uint32_t LAM_CTRL15 ; /* LAM Control Register, offset: 0x4f4 */
__IO uint32_t LAM_CONFIG15 ; /* LAM Configuration Register, offset: 0x4f8 */
__IO uint32_t LAM_COUNTER15 ; /* LAM Counter Register, offset: 0x4fc */
} ISM_Type, *ISM_MemMapPtr;
/** Number of instances of the ISM module. */
#define ISM_INSTANCE_COUNT (1u)
/* ISM - Peripheral instance base addresses */
/** Peripheral ISM base address */
#define ISM_BASE (0x4001b000u)
/** Peripheral ISM base pointer */
#define ISM ((ISM_Type *)ISM_BASE)
/** Array initializer of ISM peripheral base addresses */
#define ISM_BASE_ADDRS {ISM_BASE}
/** Array initializer of ISM peripheral base pointers */
#define ISM_BASE_PTRS {ISM}
// need fill by yourself
///** Number of interrupt vector arrays for the ISM module. */
//#define ISM_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the ISM module. */
//#define ISM_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the ISM peripheral type */
//#define ISM_IRQS {ISM_IRQn}
/* ----------------------------------------------------------------------------
-- ISM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ISM_Register_Masks ISM Register Masks
* @{
*/
/* PARAM Bit Fields */
#define ISM_PARAM_LAM_MASK 0x1F000000u
#define ISM_PARAM_LAM_SHIFT 24u
#define ISM_PARAM_LAM_WIDTH 5u
#define ISM_PARAM_LAM(x) (((uint32_t)(((uint32_t)(x))<<ISM_PARAM_LAM_SHIFT))&ISM_PARAM_LAM_MASK)
#define ISM_PARAM_FPC_MASK 0x3F0000u
#define ISM_PARAM_FPC_SHIFT 16u
#define ISM_PARAM_FPC_WIDTH 6u
#define ISM_PARAM_FPC(x) (((uint32_t)(((uint32_t)(x))<<ISM_PARAM_FPC_SHIFT))&ISM_PARAM_FPC_MASK)
#define ISM_PARAM_ECMC_MASK 0xFu
#define ISM_PARAM_ECMC_SHIFT 0u
#define ISM_PARAM_ECMC_WIDTH 4u
#define ISM_PARAM_ECMC(x) (((uint32_t)(((uint32_t)(x))<<ISM_PARAM_ECMC_SHIFT))&ISM_PARAM_ECMC_MASK)
/* PARAM Reg Mask */
#define ISM_PARAM_MASK 0x1F3F000Fu
/* CTRL Bit Fields */
#define ISM_CTRL_EN_MASK 0x80000000u
#define ISM_CTRL_EN_SHIFT 31u
#define ISM_CTRL_EN_WIDTH 1u
#define ISM_CTRL_EN(x) (((uint32_t)(((uint32_t)(x))<<ISM_CTRL_EN_SHIFT))&ISM_CTRL_EN_MASK)
#define ISM_CTRL_IEN_MASK 0x1u
#define ISM_CTRL_IEN_SHIFT 0u
#define ISM_CTRL_IEN_WIDTH 1u
#define ISM_CTRL_IEN(x) (((uint32_t)(((uint32_t)(x))<<ISM_CTRL_IEN_SHIFT))&ISM_CTRL_IEN_MASK)
/* CTRL Reg Mask */
#define ISM_CTRL_MASK 0x80000001u
/* E_STATUS Bit Fields */
#define ISM_E_STATUS_ECS_MASK 0xF0000u
#define ISM_E_STATUS_ECS_SHIFT 16u
#define ISM_E_STATUS_ECS_WIDTH 4u
#define ISM_E_STATUS_ECS(x) (((uint32_t)(((uint32_t)(x))<<ISM_E_STATUS_ECS_SHIFT))&ISM_E_STATUS_ECS_MASK)
#define ISM_E_STATUS_ES_MASK 0xFFFFu
#define ISM_E_STATUS_ES_SHIFT 0u
#define ISM_E_STATUS_ES_WIDTH 16u
#define ISM_E_STATUS_ES(x) (((uint32_t)(((uint32_t)(x))<<ISM_E_STATUS_ES_SHIFT))&ISM_E_STATUS_ES_MASK)
/* E_STATUS Reg Mask */
#define ISM_E_STATUS_MASK 0x000FFFFFu
/* E_CTRL Bit Fields */
#define ISM_E_CTRL_ECE_MASK 0xF0000u
#define ISM_E_CTRL_ECE_SHIFT 16u
#define ISM_E_CTRL_ECE_WIDTH 4u
#define ISM_E_CTRL_ECE(x) (((uint32_t)(((uint32_t)(x))<<ISM_E_CTRL_ECE_SHIFT))&ISM_E_CTRL_ECE_MASK)
#define ISM_E_CTRL_EE_MASK 0xFFFFu
#define ISM_E_CTRL_EE_SHIFT 0u
#define ISM_E_CTRL_EE_WIDTH 16u
#define ISM_E_CTRL_EE(x) (((uint32_t)(((uint32_t)(x))<<ISM_E_CTRL_EE_SHIFT))&ISM_E_CTRL_EE_MASK)
/* E_CTRL Reg Mask */
#define ISM_E_CTRL_MASK 0x000FFFFFu
/* EC_CTRL Bit Fields */
#define ISM_EC_CTRL_THRL_3_MASK 0xF0000000u
#define ISM_EC_CTRL_THRL_3_SHIFT 28u
#define ISM_EC_CTRL_THRL_3_WIDTH 4u
#define ISM_EC_CTRL_THRL_3(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_THRL_3_SHIFT))&ISM_EC_CTRL_THRL_3_MASK)
#define ISM_EC_CTRL_SEL_3_MASK 0xF000000u
#define ISM_EC_CTRL_SEL_3_SHIFT 24u
#define ISM_EC_CTRL_SEL_3_WIDTH 4u
#define ISM_EC_CTRL_SEL_3(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_SEL_3_SHIFT))&ISM_EC_CTRL_SEL_3_MASK)
#define ISM_EC_CTRL_THRL_2_MASK 0xF00000u
#define ISM_EC_CTRL_THRL_2_SHIFT 20u
#define ISM_EC_CTRL_THRL_2_WIDTH 4u
#define ISM_EC_CTRL_THRL_2(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_THRL_2_SHIFT))&ISM_EC_CTRL_THRL_2_MASK)
#define ISM_EC_CTRL_SEL_2_MASK 0xF0000u
#define ISM_EC_CTRL_SEL_2_SHIFT 16u
#define ISM_EC_CTRL_SEL_2_WIDTH 4u
#define ISM_EC_CTRL_SEL_2(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_SEL_2_SHIFT))&ISM_EC_CTRL_SEL_2_MASK)
#define ISM_EC_CTRL_THRL_1_MASK 0xF000u
#define ISM_EC_CTRL_THRL_1_SHIFT 12u
#define ISM_EC_CTRL_THRL_1_WIDTH 4u
#define ISM_EC_CTRL_THRL_1(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_THRL_1_SHIFT))&ISM_EC_CTRL_THRL_1_MASK)
#define ISM_EC_CTRL_SEL_1_MASK 0xF00u
#define ISM_EC_CTRL_SEL_1_SHIFT 8u
#define ISM_EC_CTRL_SEL_1_WIDTH 4u
#define ISM_EC_CTRL_SEL_1(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_SEL_1_SHIFT))&ISM_EC_CTRL_SEL_1_MASK)
#define ISM_EC_CTRL_THRL_0_MASK 0xF0u
#define ISM_EC_CTRL_THRL_0_SHIFT 4u
#define ISM_EC_CTRL_THRL_0_WIDTH 4u
#define ISM_EC_CTRL_THRL_0(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_THRL_0_SHIFT))&ISM_EC_CTRL_THRL_0_MASK)
#define ISM_EC_CTRL_SEL_0_MASK 0xFu
#define ISM_EC_CTRL_SEL_0_SHIFT 0u
#define ISM_EC_CTRL_SEL_0_WIDTH 4u
#define ISM_EC_CTRL_SEL_0(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_SEL_0_SHIFT))&ISM_EC_CTRL_SEL_0_MASK)
/* EC_CTRL Reg Mask */
#define ISM_EC_CTRL_MASK 0xFFFFFFFFu
/* FPC_STATUS Bit Fields */
#define ISM_FPC_STATUS_RGD_MASK 0x2u
#define ISM_FPC_STATUS_RGD_SHIFT 1u
#define ISM_FPC_STATUS_RGD_WIDTH 1u
#define ISM_FPC_STATUS_RGD(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_STATUS_RGD_SHIFT))&ISM_FPC_STATUS_RGD_MASK)
#define ISM_FPC_STATUS_FGD_MASK 0x1u
#define ISM_FPC_STATUS_FGD_SHIFT 0u
#define ISM_FPC_STATUS_FGD_WIDTH 1u
#define ISM_FPC_STATUS_FGD(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_STATUS_FGD_SHIFT))&ISM_FPC_STATUS_FGD_MASK)
/* FPC_STATUS0 Reg Mask */
#define ISM_FPC_STATUS_MASK 0x00000003u
/* FPC_CTRL Bit Fields */
#define ISM_FPC_CTRL_IEN_MASK 0x2u
#define ISM_FPC_CTRL_IEN_SHIFT 1u
#define ISM_FPC_CTRL_IEN_WIDTH 1u
#define ISM_FPC_CTRL_IEN(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CTRL_IEN_SHIFT))&ISM_FPC_CTRL_IEN_MASK)
#define ISM_FPC_CTRL_EN_MASK 0x1u
#define ISM_FPC_CTRL_EN_SHIFT 0u
#define ISM_FPC_CTRL_EN_WIDTH 1u
#define ISM_FPC_CTRL_EN(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CTRL_EN_SHIFT))&ISM_FPC_CTRL_EN_MASK)
/* FPC_CTRL0 Reg Mask */
#define ISM_FPC_CTRL_MASK 0x00000003u
/* FPC_CONFIG Bit Fields */
#define ISM_FPC_CONFIG_FEG_MASK 0xC00000u
#define ISM_FPC_CONFIG_FEG_SHIFT 22u
#define ISM_FPC_CONFIG_FEG_WIDTH 2u
#define ISM_FPC_CONFIG_FEG(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CONFIG_FEG_SHIFT))&ISM_FPC_CONFIG_FEG_MASK)
#define ISM_FPC_CONFIG_FED_MASK 0x300000u
#define ISM_FPC_CONFIG_FED_SHIFT 20u
#define ISM_FPC_CONFIG_FED_WIDTH 2u
#define ISM_FPC_CONFIG_FED(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CONFIG_FED_SHIFT))&ISM_FPC_CONFIG_FED_MASK)
#define ISM_FPC_CONFIG_REG_MASK 0xC0000u
#define ISM_FPC_CONFIG_REG_SHIFT 18u
#define ISM_FPC_CONFIG_REG_WIDTH 2u
#define ISM_FPC_CONFIG_REG(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CONFIG_REG_SHIFT))&ISM_FPC_CONFIG_REG_MASK)
#define ISM_FPC_CONFIG_RED_MASK 0x30000u
#define ISM_FPC_CONFIG_RED_SHIFT 16u
#define ISM_FPC_CONFIG_RED_WIDTH 2u
#define ISM_FPC_CONFIG_RED(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CONFIG_RED_SHIFT))&ISM_FPC_CONFIG_RED_MASK)
#define ISM_FPC_CONFIG_CMP_MASK 0xFFFFu
#define ISM_FPC_CONFIG_CMP_SHIFT 0u
#define ISM_FPC_CONFIG_CMP_WIDTH 16u
#define ISM_FPC_CONFIG_CMP(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CONFIG_CMP_SHIFT))&ISM_FPC_CONFIG_CMP_MASK)
/* FPC_CONFIG0 Reg Mask */
#define ISM_FPC_CONFIG_MASK 0x00FFFFFFu
/* FPC_TIMER Bit Fields */
#define ISM_FPC_TIMER_TIM_MASK 0xFFFFu
#define ISM_FPC_TIMER_TIM_SHIFT 0u
#define ISM_FPC_TIMER_TIM_WIDTH 16u
#define ISM_FPC_TIMER_TIM(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_TIMER_TIM_SHIFT))&ISM_FPC_TIMER_TIM_MASK)
/* FPC_TIMER0 Reg Mask */
#define ISM_FPC_TIMER_MASK 0x0000FFFFu
/* LAM_STATUS Bit Fields */
#define ISM_LAM_STATUS_OVFL_MASK 0x80000000u
#define ISM_LAM_STATUS_OVFL_SHIFT 31u
#define ISM_LAM_STATUS_OVFL_WIDTH 1u
#define ISM_LAM_STATUS_OVFL(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_STATUS_OVFL_SHIFT))&ISM_LAM_STATUS_OVFL_MASK)
#define ISM_LAM_STATUS_COUNT_MASK 0xFFFFFFu
#define ISM_LAM_STATUS_COUNT_SHIFT 0u
#define ISM_LAM_STATUS_COUNT_WIDTH 24u
#define ISM_LAM_STATUS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_STATUS_COUNT_SHIFT))&ISM_LAM_STATUS_COUNT_MASK)
/* LAM_STATUS0 Reg Mask */
#define ISM_LAM_STATUS_MASK 0x80FFFFFFu
/* LAM_CTRL Bit Fields */
#define ISM_LAM_CTRL_IEN_MASK 0x2u
#define ISM_LAM_CTRL_IEN_SHIFT 1u
#define ISM_LAM_CTRL_IEN_WIDTH 1u
#define ISM_LAM_CTRL_IEN(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CTRL_IEN_SHIFT))&ISM_LAM_CTRL_IEN_MASK)
#define ISM_LAM_CTRL_EN_MASK 0x1u
#define ISM_LAM_CTRL_EN_SHIFT 0u
#define ISM_LAM_CTRL_EN_WIDTH 1u
#define ISM_LAM_CTRL_EN(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CTRL_EN_SHIFT))&ISM_LAM_CTRL_EN_MASK)
/* LAM_CTRL0 Reg Mask */
#define ISM_LAM_CTRL_MASK 0x00000003u
/* LAM_CONFIG Bit Fields */
#define ISM_LAM_CONFIG_RCS_MASK 0xF000000u
#define ISM_LAM_CONFIG_RCS_SHIFT 24u
#define ISM_LAM_CONFIG_RCS_WIDTH 4u
#define ISM_LAM_CONFIG_RCS(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_RCS_SHIFT))&ISM_LAM_CONFIG_RCS_MASK)
#define ISM_LAM_CONFIG_MCS_MASK 0xF0000u
#define ISM_LAM_CONFIG_MCS_SHIFT 16u
#define ISM_LAM_CONFIG_MCS_WIDTH 4u
#define ISM_LAM_CONFIG_MCS(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_MCS_SHIFT))&ISM_LAM_CONFIG_MCS_MASK)
#define ISM_LAM_CONFIG_IVW_MASK 0x1000u
#define ISM_LAM_CONFIG_IVW_SHIFT 12u
#define ISM_LAM_CONFIG_IVW_WIDTH 1u
#define ISM_LAM_CONFIG_IVW(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_IVW_SHIFT))&ISM_LAM_CONFIG_IVW_MASK)
#define ISM_LAM_CONFIG_EDS_MASK 0xF00u
#define ISM_LAM_CONFIG_EDS_SHIFT 8u
#define ISM_LAM_CONFIG_EDS_WIDTH 4u
#define ISM_LAM_CONFIG_EDS(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_EDS_SHIFT))&ISM_LAM_CONFIG_EDS_MASK)
#define ISM_LAM_CONFIG_EWS_MASK 0x10u
#define ISM_LAM_CONFIG_EWS_SHIFT 4u
#define ISM_LAM_CONFIG_EWS_WIDTH 1u
#define ISM_LAM_CONFIG_EWS(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_EWS_SHIFT))&ISM_LAM_CONFIG_EWS_MASK)
#define ISM_LAM_CONFIG_RMS_MASK 0x8u
#define ISM_LAM_CONFIG_RMS_SHIFT 3u
#define ISM_LAM_CONFIG_RMS_WIDTH 1u
#define ISM_LAM_CONFIG_RMS(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_RMS_SHIFT))&ISM_LAM_CONFIG_RMS_MASK)
#define ISM_LAM_CONFIG_MOS_MASK 0x4u
#define ISM_LAM_CONFIG_MOS_SHIFT 2u
#define ISM_LAM_CONFIG_MOS_WIDTH 1u
#define ISM_LAM_CONFIG_MOS(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_MOS_SHIFT))&ISM_LAM_CONFIG_MOS_MASK)
#define ISM_LAM_CONFIG_IVM_MASK 0x2u
#define ISM_LAM_CONFIG_IVM_SHIFT 1u
#define ISM_LAM_CONFIG_IVM_WIDTH 1u
#define ISM_LAM_CONFIG_IVM(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_IVM_SHIFT))&ISM_LAM_CONFIG_IVM_MASK)
#define ISM_LAM_CONFIG_IVR_MASK 0x1u
#define ISM_LAM_CONFIG_IVR_SHIFT 0u
#define ISM_LAM_CONFIG_IVR_WIDTH 1u
#define ISM_LAM_CONFIG_IVR(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_IVR_SHIFT))&ISM_LAM_CONFIG_IVR_MASK)
/* LAM_CONFIG0 Reg Mask */
#define ISM_LAM_CONFIG_MASK 0x0F0F1F1Fu
/* LAM_COUNTER Bit Fields */
#define ISM_LAM_COUNTER_CNT_MASK 0xFFFFFFu
#define ISM_LAM_COUNTER_CNT_SHIFT 0u
#define ISM_LAM_COUNTER_CNT_WIDTH 24u
#define ISM_LAM_COUNTER_CNT(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_COUNTER_CNT_SHIFT))&ISM_LAM_COUNTER_CNT_MASK)
/* LAM_COUNTER0 Reg Mask */
#define ISM_LAM_COUNTER_MASK 0x00FFFFFFu
/*!
* @}
*/ /* end of group ISM_Register_Masks */
/*!
* @}
*/ /* end of group ISM_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_LU_NU_Tztufn43_REGS_H_
#define _FC7240_LU_NU_Tztufn43_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- LU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LU_Peripheral_Access_Layer LU Peripheral Access Layer
* @{
*/
/** LU - Size of Registers Arrays */
/** LU - Register Layout Typedef */
#define LG_CNT 4
typedef struct {
struct {
__IO uint32_t AOI_0 ; /* AOI0 configuration, offset: 0x0+n*10h */
__IO uint32_t AOI_1 ; /* AOI1 configuration, offset: 0x4+n*10h */
__IO uint32_t CTRL ; /* lg configuration, offset: 0x8+n*10h */
__IO uint32_t FILT ; /* input filter, offset: 0xc+n*10h */
} LG[LG_CNT];
} LU_Type, *LU_MemMapPtr;
/** Number of instances of the LU module. */
#define LU_INSTANCE_COUNT (1u)
/* LU - Peripheral instance base addresses */
/** Peripheral LU base address */
#define LU_BASE (0x40070000u)
/** Peripheral LU base pointer */
#define LU ((LU_Type *)LU_BASE)
/** Array initializer of LU peripheral base addresses */
#define LU_BASE_ADDRS {LU_BASE}
/** Array initializer of LU peripheral base pointers */
#define LU_BASE_PTRS {LU}
// need fill by yourself
///** Number of interrupt vector arrays for the LU module. */
//#define LU_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the LU module. */
//#define LU_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the LU peripheral type */
//#define LU_IRQS {LU_IRQn}
/* ----------------------------------------------------------------------------
-- LU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LU_Register_Masks LU Register Masks
* @{
*/
/* AOI_0 Bit Fields */
#define LU_AOI_0_IN0A_CFG_MASK 0xC0000000u
#define LU_AOI_0_IN0A_CFG_SHIFT 30u
#define LU_AOI_0_IN0A_CFG_WIDTH 2u
#define LU_AOI_0_IN0A_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN0A_CFG_SHIFT))&LU_AOI_0_IN0A_CFG_MASK)
#define LU_AOI_0_IN0B_CFG_MASK 0x30000000u
#define LU_AOI_0_IN0B_CFG_SHIFT 28u
#define LU_AOI_0_IN0B_CFG_WIDTH 2u
#define LU_AOI_0_IN0B_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN0B_CFG_SHIFT))&LU_AOI_0_IN0B_CFG_MASK)
#define LU_AOI_0_IN0C_CFG_MASK 0xC000000u
#define LU_AOI_0_IN0C_CFG_SHIFT 26u
#define LU_AOI_0_IN0C_CFG_WIDTH 2u
#define LU_AOI_0_IN0C_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN0C_CFG_SHIFT))&LU_AOI_0_IN0C_CFG_MASK)
#define LU_AOI_0_IN0D_CFG_MASK 0x3000000u
#define LU_AOI_0_IN0D_CFG_SHIFT 24u
#define LU_AOI_0_IN0D_CFG_WIDTH 2u
#define LU_AOI_0_IN0D_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN0D_CFG_SHIFT))&LU_AOI_0_IN0D_CFG_MASK)
#define LU_AOI_0_IN1A_CFG_MASK 0xC00000u
#define LU_AOI_0_IN1A_CFG_SHIFT 22u
#define LU_AOI_0_IN1A_CFG_WIDTH 2u
#define LU_AOI_0_IN1A_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN1A_CFG_SHIFT))&LU_AOI_0_IN1A_CFG_MASK)
#define LU_AOI_0_IN1B_CFG_MASK 0x300000u
#define LU_AOI_0_IN1B_CFG_SHIFT 20u
#define LU_AOI_0_IN1B_CFG_WIDTH 2u
#define LU_AOI_0_IN1B_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN1B_CFG_SHIFT))&LU_AOI_0_IN1B_CFG_MASK)
#define LU_AOI_0_IN1C_CFG_MASK 0xC0000u
#define LU_AOI_0_IN1C_CFG_SHIFT 18u
#define LU_AOI_0_IN1C_CFG_WIDTH 2u
#define LU_AOI_0_IN1C_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN1C_CFG_SHIFT))&LU_AOI_0_IN1C_CFG_MASK)
#define LU_AOI_0_IN1D_CFG_MASK 0x30000u
#define LU_AOI_0_IN1D_CFG_SHIFT 16u
#define LU_AOI_0_IN1D_CFG_WIDTH 2u
#define LU_AOI_0_IN1D_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN1D_CFG_SHIFT))&LU_AOI_0_IN1D_CFG_MASK)
#define LU_AOI_0_IN2A_CFG_MASK 0xC000u
#define LU_AOI_0_IN2A_CFG_SHIFT 14u
#define LU_AOI_0_IN2A_CFG_WIDTH 2u
#define LU_AOI_0_IN2A_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN2A_CFG_SHIFT))&LU_AOI_0_IN2A_CFG_MASK)
#define LU_AOI_0_IN2B_CFG_MASK 0x3000u
#define LU_AOI_0_IN2B_CFG_SHIFT 12u
#define LU_AOI_0_IN2B_CFG_WIDTH 2u
#define LU_AOI_0_IN2B_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN2B_CFG_SHIFT))&LU_AOI_0_IN2B_CFG_MASK)
#define LU_AOI_0_IN2C_CFG_MASK 0xC00u
#define LU_AOI_0_IN2C_CFG_SHIFT 10u
#define LU_AOI_0_IN2C_CFG_WIDTH 2u
#define LU_AOI_0_IN2C_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN2C_CFG_SHIFT))&LU_AOI_0_IN2C_CFG_MASK)
#define LU_AOI_0_IN2D_CFG_MASK 0x300u
#define LU_AOI_0_IN2D_CFG_SHIFT 8u
#define LU_AOI_0_IN2D_CFG_WIDTH 2u
#define LU_AOI_0_IN2D_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN2D_CFG_SHIFT))&LU_AOI_0_IN2D_CFG_MASK)
#define LU_AOI_0_IN3A_CFG_MASK 0xC0u
#define LU_AOI_0_IN3A_CFG_SHIFT 6u
#define LU_AOI_0_IN3A_CFG_WIDTH 2u
#define LU_AOI_0_IN3A_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN3A_CFG_SHIFT))&LU_AOI_0_IN3A_CFG_MASK)
#define LU_AOI_0_IN3B_CFG_MASK 0x30u
#define LU_AOI_0_IN3B_CFG_SHIFT 4u
#define LU_AOI_0_IN3B_CFG_WIDTH 2u
#define LU_AOI_0_IN3B_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN3B_CFG_SHIFT))&LU_AOI_0_IN3B_CFG_MASK)
#define LU_AOI_0_IN3C_CFG_MASK 0xCu
#define LU_AOI_0_IN3C_CFG_SHIFT 2u
#define LU_AOI_0_IN3C_CFG_WIDTH 2u
#define LU_AOI_0_IN3C_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN3C_CFG_SHIFT))&LU_AOI_0_IN3C_CFG_MASK)
#define LU_AOI_0_IN3D_CFG_MASK 0x3u
#define LU_AOI_0_IN3D_CFG_SHIFT 0u
#define LU_AOI_0_IN3D_CFG_WIDTH 2u
#define LU_AOI_0_IN3D_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_0_IN3D_CFG_SHIFT))&LU_AOI_0_IN3D_CFG_MASK)
/* AOI_00 Reg Mask */
#define LU_AOI_0_MASK 0xFFFFFFFFu
/* AOI_1 Bit Fields */
#define LU_AOI_1_IN0A_CFG_MASK 0xC0000000u
#define LU_AOI_1_IN0A_CFG_SHIFT 30u
#define LU_AOI_1_IN0A_CFG_WIDTH 2u
#define LU_AOI_1_IN0A_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN0A_CFG_SHIFT))&LU_AOI_1_IN0A_CFG_MASK)
#define LU_AOI_1_IN0B_CFG_MASK 0x30000000u
#define LU_AOI_1_IN0B_CFG_SHIFT 28u
#define LU_AOI_1_IN0B_CFG_WIDTH 2u
#define LU_AOI_1_IN0B_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN0B_CFG_SHIFT))&LU_AOI_1_IN0B_CFG_MASK)
#define LU_AOI_1_IN0C_CFG_MASK 0xC000000u
#define LU_AOI_1_IN0C_CFG_SHIFT 26u
#define LU_AOI_1_IN0C_CFG_WIDTH 2u
#define LU_AOI_1_IN0C_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN0C_CFG_SHIFT))&LU_AOI_1_IN0C_CFG_MASK)
#define LU_AOI_1_IN0D_CFG_MASK 0x3000000u
#define LU_AOI_1_IN0D_CFG_SHIFT 24u
#define LU_AOI_1_IN0D_CFG_WIDTH 2u
#define LU_AOI_1_IN0D_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN0D_CFG_SHIFT))&LU_AOI_1_IN0D_CFG_MASK)
#define LU_AOI_1_IN1A_CFG_MASK 0xC00000u
#define LU_AOI_1_IN1A_CFG_SHIFT 22u
#define LU_AOI_1_IN1A_CFG_WIDTH 2u
#define LU_AOI_1_IN1A_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN1A_CFG_SHIFT))&LU_AOI_1_IN1A_CFG_MASK)
#define LU_AOI_1_IN1B_CFG_MASK 0x300000u
#define LU_AOI_1_IN1B_CFG_SHIFT 20u
#define LU_AOI_1_IN1B_CFG_WIDTH 2u
#define LU_AOI_1_IN1B_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN1B_CFG_SHIFT))&LU_AOI_1_IN1B_CFG_MASK)
#define LU_AOI_1_IN1C_CFG_MASK 0xC0000u
#define LU_AOI_1_IN1C_CFG_SHIFT 18u
#define LU_AOI_1_IN1C_CFG_WIDTH 2u
#define LU_AOI_1_IN1C_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN1C_CFG_SHIFT))&LU_AOI_1_IN1C_CFG_MASK)
#define LU_AOI_1_IN1D_CFG_MASK 0x30000u
#define LU_AOI_1_IN1D_CFG_SHIFT 16u
#define LU_AOI_1_IN1D_CFG_WIDTH 2u
#define LU_AOI_1_IN1D_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN1D_CFG_SHIFT))&LU_AOI_1_IN1D_CFG_MASK)
#define LU_AOI_1_IN2A_CFG_MASK 0xC000u
#define LU_AOI_1_IN2A_CFG_SHIFT 14u
#define LU_AOI_1_IN2A_CFG_WIDTH 2u
#define LU_AOI_1_IN2A_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN2A_CFG_SHIFT))&LU_AOI_1_IN2A_CFG_MASK)
#define LU_AOI_1_IN2B_CFG_MASK 0x3000u
#define LU_AOI_1_IN2B_CFG_SHIFT 12u
#define LU_AOI_1_IN2B_CFG_WIDTH 2u
#define LU_AOI_1_IN2B_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN2B_CFG_SHIFT))&LU_AOI_1_IN2B_CFG_MASK)
#define LU_AOI_1_IN2C_CFG_MASK 0xC00u
#define LU_AOI_1_IN2C_CFG_SHIFT 10u
#define LU_AOI_1_IN2C_CFG_WIDTH 2u
#define LU_AOI_1_IN2C_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN2C_CFG_SHIFT))&LU_AOI_1_IN2C_CFG_MASK)
#define LU_AOI_1_IN2D_CFG_MASK 0x300u
#define LU_AOI_1_IN2D_CFG_SHIFT 8u
#define LU_AOI_1_IN2D_CFG_WIDTH 2u
#define LU_AOI_1_IN2D_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN2D_CFG_SHIFT))&LU_AOI_1_IN2D_CFG_MASK)
#define LU_AOI_1_IN3A_CFG_MASK 0xC0u
#define LU_AOI_1_IN3A_CFG_SHIFT 6u
#define LU_AOI_1_IN3A_CFG_WIDTH 2u
#define LU_AOI_1_IN3A_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN3A_CFG_SHIFT))&LU_AOI_1_IN3A_CFG_MASK)
#define LU_AOI_1_IN3B_CFG_MASK 0x30u
#define LU_AOI_1_IN3B_CFG_SHIFT 4u
#define LU_AOI_1_IN3B_CFG_WIDTH 2u
#define LU_AOI_1_IN3B_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN3B_CFG_SHIFT))&LU_AOI_1_IN3B_CFG_MASK)
#define LU_AOI_1_IN3C_CFG_MASK 0xCu
#define LU_AOI_1_IN3C_CFG_SHIFT 2u
#define LU_AOI_1_IN3C_CFG_WIDTH 2u
#define LU_AOI_1_IN3C_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN3C_CFG_SHIFT))&LU_AOI_1_IN3C_CFG_MASK)
#define LU_AOI_1_IN3D_CFG_MASK 0x3u
#define LU_AOI_1_IN3D_CFG_SHIFT 0u
#define LU_AOI_1_IN3D_CFG_WIDTH 2u
#define LU_AOI_1_IN3D_CFG(x) (((uint32_t)(((uint32_t)(x))<<LU_AOI_1_IN3D_CFG_SHIFT))&LU_AOI_1_IN3D_CFG_MASK)
/* AOI_10 Reg Mask */
#define LU_AOI_1_MASK 0xFFFFFFFFu
/* CTRL Bit Fields */
#define LU_CTRL_BYPASS_MASK 0x3000u
#define LU_CTRL_BYPASS_SHIFT 12u
#define LU_CTRL_BYPASS_WIDTH 2u
#define LU_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x))<<LU_CTRL_BYPASS_SHIFT))&LU_CTRL_BYPASS_MASK)
#define LU_CTRL_SYNC_MASK 0xF00u
#define LU_CTRL_SYNC_SHIFT 8u
#define LU_CTRL_SYNC_WIDTH 4u
#define LU_CTRL_SYNC(x) (((uint32_t)(((uint32_t)(x))<<LU_CTRL_SYNC_SHIFT))&LU_CTRL_SYNC_MASK)
#define LU_CTRL_FB_OVRD_MASK 0xC0u
#define LU_CTRL_FB_OVRD_SHIFT 6u
#define LU_CTRL_FB_OVRD_WIDTH 2u
#define LU_CTRL_FB_OVRD(x) (((uint32_t)(((uint32_t)(x))<<LU_CTRL_FB_OVRD_SHIFT))&LU_CTRL_FB_OVRD_MASK)
#define LU_CTRL_MOD_MASK 0x1Cu
#define LU_CTRL_MOD_SHIFT 2u
#define LU_CTRL_MOD_WIDTH 3u
#define LU_CTRL_MOD(x) (((uint32_t)(((uint32_t)(x))<<LU_CTRL_MOD_SHIFT))&LU_CTRL_MOD_MASK)
#define LU_CTRL_INIT_EN_MASK 0x2u
#define LU_CTRL_INIT_EN_SHIFT 1u
#define LU_CTRL_INIT_EN_WIDTH 1u
#define LU_CTRL_INIT_EN(x) (((uint32_t)(((uint32_t)(x))<<LU_CTRL_INIT_EN_SHIFT))&LU_CTRL_INIT_EN_MASK)
#define LU_CTRL_FF_INIT_MASK 0x1u
#define LU_CTRL_FF_INIT_SHIFT 0u
#define LU_CTRL_FF_INIT_WIDTH 1u
#define LU_CTRL_FF_INIT(x) (((uint32_t)(((uint32_t)(x))<<LU_CTRL_FF_INIT_SHIFT))&LU_CTRL_FF_INIT_MASK)
/* CTRL0 Reg Mask */
#define LU_CTRL_MASK 0x00003FDFu
/* FILT Bit Fields */
#define LU_FILT_CNT0_MASK 0x7000000u
#define LU_FILT_CNT0_SHIFT 24u
#define LU_FILT_CNT0_WIDTH 3u
#define LU_FILT_CNT0(x) (((uint32_t)(((uint32_t)(x))<<LU_FILT_CNT0_SHIFT))&LU_FILT_CNT0_MASK)
#define LU_FILT_PRE0_MASK 0xFF0000u
#define LU_FILT_PRE0_SHIFT 16u
#define LU_FILT_PRE0_WIDTH 8u
#define LU_FILT_PRE0(x) (((uint32_t)(((uint32_t)(x))<<LU_FILT_PRE0_SHIFT))&LU_FILT_PRE0_MASK)
#define LU_FILT_CNT1_MASK 0x700u
#define LU_FILT_CNT1_SHIFT 8u
#define LU_FILT_CNT1_WIDTH 3u
#define LU_FILT_CNT1(x) (((uint32_t)(((uint32_t)(x))<<LU_FILT_CNT1_SHIFT))&LU_FILT_CNT1_MASK)
#define LU_FILT_PRE1_MASK 0xFFu
#define LU_FILT_PRE1_SHIFT 0u
#define LU_FILT_PRE1_WIDTH 8u
#define LU_FILT_PRE1(x) (((uint32_t)(((uint32_t)(x))<<LU_FILT_PRE1_SHIFT))&LU_FILT_PRE1_MASK)
/* FILT0 Reg Mask */
#define LU_FILT_MASK 0x07FF07FFu
/*!
* @}
*/ /* end of group LU_Register_Masks */
/*!
* @}
*/ /* end of group LU_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_MAM_NU_Tztufn19_REGS_H_
#define _FC7240_MAM_NU_Tztufn19_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- MAM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MAM_Peripheral_Access_Layer MAM Peripheral Access Layer
* @{
*/
/** MAM - Size of Registers Arrays */
/** MAM - Register Layout Typedef */
#define MAM_ACLR_COUNT 12
#define MAM_ACR_COUNT 188
typedef struct {
__IO uint32_t MAXCFG ; /* Matrix Configuration Register, offset: 0x000 */
__IO uint32_t BSTCR ; /* Burst Control Register, offset: 0x004 */
uint8_t RESERVED_0[248];
__IO uint32_t WDGCR ; /* Watchdog Control Register, offset: 0x100 */
__IO uint32_t TOCR ; /* Timeout Control Register, offset: 0x104 */
__IO uint32_t WDGDIV ; /* Watchdog Divider Register, offset: 0x108 */
uint8_t RESERVED_1[1524];
__IO uint32_t ACLR[MAM_ACLR_COUNT] ; /* Access Control Lock Register, offset: 0x700 */
uint8_t RESERVED_2[208];
__IO uint32_t ACR[MAM_ACR_COUNT] ; /* Access Control Register, offset: 0x800 */
} MAM_Type, *MAM_MemMapPtr;
/** Number of instances of the MAM module. */
#define MAM_INSTANCE_COUNT (1u)
/* MAM - Peripheral instance base addresses */
/** Peripheral MAM base address */
#define MAM_BASE (0x4040d000u)
/** Peripheral MAM base pointer */
#define MAM ((MAM_Type *)MAM_BASE)
/** Array initializer of MAM peripheral base addresses */
#define MAM_BASE_ADDRS {MAM_BASE}
/** Array initializer of MAM peripheral base pointers */
#define MAM_BASE_PTRS {MAM}
// need fill by yourself
///** Number of interrupt vector arrays for the MAM module. */
//#define MAM_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the MAM module. */
//#define MAM_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the MAM peripheral type */
//#define MAM_IRQS {MAM_IRQn}
/* ----------------------------------------------------------------------------
-- MAM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MAM_Register_Masks MAM Register Masks
* @{
*/
/* MAXCFG Bit Fields */
#define MAM_MAXCFG_MASTERNUM_MASK 0xFF000000u
#define MAM_MAXCFG_MASTERNUM_SHIFT 24u
#define MAM_MAXCFG_MASTERNUM_WIDTH 8u
#define MAM_MAXCFG_MASTERNUM(x) (((uint32_t)(((uint32_t)(x))<<MAM_MAXCFG_MASTERNUM_SHIFT))&MAM_MAXCFG_MASTERNUM_MASK)
#define MAM_MAXCFG_SLAVENUM_MASK 0xFF00u
#define MAM_MAXCFG_SLAVENUM_SHIFT 8u
#define MAM_MAXCFG_SLAVENUM_WIDTH 8u
#define MAM_MAXCFG_SLAVENUM(x) (((uint32_t)(((uint32_t)(x))<<MAM_MAXCFG_SLAVENUM_SHIFT))&MAM_MAXCFG_SLAVENUM_MASK)
/* MAXCFG Reg Mask */
#define MAM_MAXCFG_MASK 0xFF00FF00u
/* BSTCR Bit Fields */
#define MAM_BSTCR_INCRBREAK3_MASK 0xC0u
#define MAM_BSTCR_INCRBREAK3_SHIFT 6u
#define MAM_BSTCR_INCRBREAK3_WIDTH 2u
#define MAM_BSTCR_INCRBREAK3(x) (((uint32_t)(((uint32_t)(x))<<MAM_BSTCR_INCRBREAK3_SHIFT))&MAM_BSTCR_INCRBREAK3_MASK)
#define MAM_BSTCR_INCRBREAK2_MASK 0x30u
#define MAM_BSTCR_INCRBREAK2_SHIFT 4u
#define MAM_BSTCR_INCRBREAK2_WIDTH 2u
#define MAM_BSTCR_INCRBREAK2(x) (((uint32_t)(((uint32_t)(x))<<MAM_BSTCR_INCRBREAK2_SHIFT))&MAM_BSTCR_INCRBREAK2_MASK)
#define MAM_BSTCR_INCRBREAK1_MASK 0xCu
#define MAM_BSTCR_INCRBREAK1_SHIFT 2u
#define MAM_BSTCR_INCRBREAK1_WIDTH 2u
#define MAM_BSTCR_INCRBREAK1(x) (((uint32_t)(((uint32_t)(x))<<MAM_BSTCR_INCRBREAK1_SHIFT))&MAM_BSTCR_INCRBREAK1_MASK)
#define MAM_BSTCR_INCRBREAK0_MASK 0x3u
#define MAM_BSTCR_INCRBREAK0_SHIFT 0u
#define MAM_BSTCR_INCRBREAK0_WIDTH 2u
#define MAM_BSTCR_INCRBREAK0(x) (((uint32_t)(((uint32_t)(x))<<MAM_BSTCR_INCRBREAK0_SHIFT))&MAM_BSTCR_INCRBREAK0_MASK)
/* BSTCR Reg Mask */
#define MAM_BSTCR_MASK 0x000000FFu
/* WDGCR Bit Fields */
#define MAM_WDGCR_WDOGSTATUS3_MASK 0x80000u
#define MAM_WDGCR_WDOGSTATUS3_SHIFT 19u
#define MAM_WDGCR_WDOGSTATUS3_WIDTH 1u
#define MAM_WDGCR_WDOGSTATUS3(x) (((uint32_t)(((uint32_t)(x))<<MAM_WDGCR_WDOGSTATUS3_SHIFT))&MAM_WDGCR_WDOGSTATUS3_MASK)
#define MAM_WDGCR_WDOGSTATUS2_MASK 0x40000u
#define MAM_WDGCR_WDOGSTATUS2_SHIFT 18u
#define MAM_WDGCR_WDOGSTATUS2_WIDTH 1u
#define MAM_WDGCR_WDOGSTATUS2(x) (((uint32_t)(((uint32_t)(x))<<MAM_WDGCR_WDOGSTATUS2_SHIFT))&MAM_WDGCR_WDOGSTATUS2_MASK)
#define MAM_WDGCR_WDOGSTATUS1_MASK 0x20000u
#define MAM_WDGCR_WDOGSTATUS1_SHIFT 17u
#define MAM_WDGCR_WDOGSTATUS1_WIDTH 1u
#define MAM_WDGCR_WDOGSTATUS1(x) (((uint32_t)(((uint32_t)(x))<<MAM_WDGCR_WDOGSTATUS1_SHIFT))&MAM_WDGCR_WDOGSTATUS1_MASK)
#define MAM_WDGCR_WDOGSTATUS0_MASK 0x10000u
#define MAM_WDGCR_WDOGSTATUS0_SHIFT 16u
#define MAM_WDGCR_WDOGSTATUS0_WIDTH 1u
#define MAM_WDGCR_WDOGSTATUS0(x) (((uint32_t)(((uint32_t)(x))<<MAM_WDGCR_WDOGSTATUS0_SHIFT))&MAM_WDGCR_WDOGSTATUS0_MASK)
#define MAM_WDGCR_WDOGCTRL3_MASK 0x8u
#define MAM_WDGCR_WDOGCTRL3_SHIFT 3u
#define MAM_WDGCR_WDOGCTRL3_WIDTH 1u
#define MAM_WDGCR_WDOGCTRL3(x) (((uint32_t)(((uint32_t)(x))<<MAM_WDGCR_WDOGCTRL3_SHIFT))&MAM_WDGCR_WDOGCTRL3_MASK)
#define MAM_WDGCR_WDOGCTRL2_MASK 0x4u
#define MAM_WDGCR_WDOGCTRL2_SHIFT 2u
#define MAM_WDGCR_WDOGCTRL2_WIDTH 1u
#define MAM_WDGCR_WDOGCTRL2(x) (((uint32_t)(((uint32_t)(x))<<MAM_WDGCR_WDOGCTRL2_SHIFT))&MAM_WDGCR_WDOGCTRL2_MASK)
#define MAM_WDGCR_WDOGCTRL1_MASK 0x2u
#define MAM_WDGCR_WDOGCTRL1_SHIFT 1u
#define MAM_WDGCR_WDOGCTRL1_WIDTH 1u
#define MAM_WDGCR_WDOGCTRL1(x) (((uint32_t)(((uint32_t)(x))<<MAM_WDGCR_WDOGCTRL1_SHIFT))&MAM_WDGCR_WDOGCTRL1_MASK)
#define MAM_WDGCR_WDOGCTRL0_MASK 0x1u
#define MAM_WDGCR_WDOGCTRL0_SHIFT 0u
#define MAM_WDGCR_WDOGCTRL0_WIDTH 1u
#define MAM_WDGCR_WDOGCTRL0(x) (((uint32_t)(((uint32_t)(x))<<MAM_WDGCR_WDOGCTRL0_SHIFT))&MAM_WDGCR_WDOGCTRL0_MASK)
/* WDGCR Reg Mask */
#define MAM_WDGCR_MASK 0x000F000Fu
/* TOCR Bit Fields */
#define MAM_TOCR_TIMEOUTCTRL3_MASK 0xC0u
#define MAM_TOCR_TIMEOUTCTRL3_SHIFT 6u
#define MAM_TOCR_TIMEOUTCTRL3_WIDTH 2u
#define MAM_TOCR_TIMEOUTCTRL3(x) (((uint32_t)(((uint32_t)(x))<<MAM_TOCR_TIMEOUTCTRL3_SHIFT))&MAM_TOCR_TIMEOUTCTRL3_MASK)
#define MAM_TOCR_TIMEOUTCTRL2_MASK 0x30u
#define MAM_TOCR_TIMEOUTCTRL2_SHIFT 4u
#define MAM_TOCR_TIMEOUTCTRL2_WIDTH 2u
#define MAM_TOCR_TIMEOUTCTRL2(x) (((uint32_t)(((uint32_t)(x))<<MAM_TOCR_TIMEOUTCTRL2_SHIFT))&MAM_TOCR_TIMEOUTCTRL2_MASK)
#define MAM_TOCR_TIMEOUTCTRL1_MASK 0xCu
#define MAM_TOCR_TIMEOUTCTRL1_SHIFT 2u
#define MAM_TOCR_TIMEOUTCTRL1_WIDTH 2u
#define MAM_TOCR_TIMEOUTCTRL1(x) (((uint32_t)(((uint32_t)(x))<<MAM_TOCR_TIMEOUTCTRL1_SHIFT))&MAM_TOCR_TIMEOUTCTRL1_MASK)
#define MAM_TOCR_TIMEOUTCTRL0_MASK 0x3u
#define MAM_TOCR_TIMEOUTCTRL0_SHIFT 0u
#define MAM_TOCR_TIMEOUTCTRL0_WIDTH 2u
#define MAM_TOCR_TIMEOUTCTRL0(x) (((uint32_t)(((uint32_t)(x))<<MAM_TOCR_TIMEOUTCTRL0_SHIFT))&MAM_TOCR_TIMEOUTCTRL0_MASK)
/* TOCR Reg Mask */
#define MAM_TOCR_MASK 0x000000FFu
/* WDGDIV Bit Fields */
#define MAM_WDGDIV_WDGDIVCTRL3_MASK 0xF000u
#define MAM_WDGDIV_WDGDIVCTRL3_SHIFT 12u
#define MAM_WDGDIV_WDGDIVCTRL3_WIDTH 4u
#define MAM_WDGDIV_WDGDIVCTRL3(x) (((uint32_t)(((uint32_t)(x))<<MAM_WDGDIV_WDGDIVCTRL3_SHIFT))&MAM_WDGDIV_WDGDIVCTRL3_MASK)
#define MAM_WDGDIV_WDGDIVCTRL2_MASK 0xF00u
#define MAM_WDGDIV_WDGDIVCTRL2_SHIFT 8u
#define MAM_WDGDIV_WDGDIVCTRL2_WIDTH 4u
#define MAM_WDGDIV_WDGDIVCTRL2(x) (((uint32_t)(((uint32_t)(x))<<MAM_WDGDIV_WDGDIVCTRL2_SHIFT))&MAM_WDGDIV_WDGDIVCTRL2_MASK)
#define MAM_WDGDIV_WDGDIVCTRL1_MASK 0xF0u
#define MAM_WDGDIV_WDGDIVCTRL1_SHIFT 4u
#define MAM_WDGDIV_WDGDIVCTRL1_WIDTH 4u
#define MAM_WDGDIV_WDGDIVCTRL1(x) (((uint32_t)(((uint32_t)(x))<<MAM_WDGDIV_WDGDIVCTRL1_SHIFT))&MAM_WDGDIV_WDGDIVCTRL1_MASK)
#define MAM_WDGDIV_WDGDIVCTRL0_MASK 0xFu
#define MAM_WDGDIV_WDGDIVCTRL0_SHIFT 0u
#define MAM_WDGDIV_WDGDIVCTRL0_WIDTH 4u
#define MAM_WDGDIV_WDGDIVCTRL0(x) (((uint32_t)(((uint32_t)(x))<<MAM_WDGDIV_WDGDIVCTRL0_SHIFT))&MAM_WDGDIV_WDGDIVCTRL0_MASK)
/* WDGDIV Reg Mask */
#define MAM_WDGDIV_MASK 0x0000FFFFu
/* ACLR Bit Fields */
#define MAM_ACLR_LOCKBLOCK31_MASK 0x80000000u
#define MAM_ACLR_LOCKBLOCK31_SHIFT 31u
#define MAM_ACLR_LOCKBLOCK31_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK31(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK31_SHIFT))&MAM_ACLR_LOCKBLOCK31_MASK)
#define MAM_ACLR_LOCKBLOCK30_MASK 0x40000000u
#define MAM_ACLR_LOCKBLOCK30_SHIFT 30u
#define MAM_ACLR_LOCKBLOCK30_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK30(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK30_SHIFT))&MAM_ACLR_LOCKBLOCK30_MASK)
#define MAM_ACLR_LOCKBLOCK29_MASK 0x20000000u
#define MAM_ACLR_LOCKBLOCK29_SHIFT 29u
#define MAM_ACLR_LOCKBLOCK29_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK29(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK29_SHIFT))&MAM_ACLR_LOCKBLOCK29_MASK)
#define MAM_ACLR_LOCKBLOCK28_MASK 0x10000000u
#define MAM_ACLR_LOCKBLOCK28_SHIFT 28u
#define MAM_ACLR_LOCKBLOCK28_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK28(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK28_SHIFT))&MAM_ACLR_LOCKBLOCK28_MASK)
#define MAM_ACLR_LOCKBLOCK27_MASK 0x8000000u
#define MAM_ACLR_LOCKBLOCK27_SHIFT 27u
#define MAM_ACLR_LOCKBLOCK27_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK27(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK27_SHIFT))&MAM_ACLR_LOCKBLOCK27_MASK)
#define MAM_ACLR_LOCKBLOCK26_MASK 0x4000000u
#define MAM_ACLR_LOCKBLOCK26_SHIFT 26u
#define MAM_ACLR_LOCKBLOCK26_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK26(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK26_SHIFT))&MAM_ACLR_LOCKBLOCK26_MASK)
#define MAM_ACLR_LOCKBLOCK25_MASK 0x2000000u
#define MAM_ACLR_LOCKBLOCK25_SHIFT 25u
#define MAM_ACLR_LOCKBLOCK25_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK25(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK25_SHIFT))&MAM_ACLR_LOCKBLOCK25_MASK)
#define MAM_ACLR_LOCKBLOCK24_MASK 0x1000000u
#define MAM_ACLR_LOCKBLOCK24_SHIFT 24u
#define MAM_ACLR_LOCKBLOCK24_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK24(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK24_SHIFT))&MAM_ACLR_LOCKBLOCK24_MASK)
#define MAM_ACLR_LOCKBLOCK23_MASK 0x800000u
#define MAM_ACLR_LOCKBLOCK23_SHIFT 23u
#define MAM_ACLR_LOCKBLOCK23_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK23(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK23_SHIFT))&MAM_ACLR_LOCKBLOCK23_MASK)
#define MAM_ACLR_LOCKBLOCK22_MASK 0x400000u
#define MAM_ACLR_LOCKBLOCK22_SHIFT 22u
#define MAM_ACLR_LOCKBLOCK22_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK22(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK22_SHIFT))&MAM_ACLR_LOCKBLOCK22_MASK)
#define MAM_ACLR_LOCKBLOCK21_MASK 0x200000u
#define MAM_ACLR_LOCKBLOCK21_SHIFT 21u
#define MAM_ACLR_LOCKBLOCK21_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK21(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK21_SHIFT))&MAM_ACLR_LOCKBLOCK21_MASK)
#define MAM_ACLR_LOCKBLOCK20_MASK 0x100000u
#define MAM_ACLR_LOCKBLOCK20_SHIFT 20u
#define MAM_ACLR_LOCKBLOCK20_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK20(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK20_SHIFT))&MAM_ACLR_LOCKBLOCK20_MASK)
#define MAM_ACLR_LOCKBLOCK19_MASK 0x80000u
#define MAM_ACLR_LOCKBLOCK19_SHIFT 19u
#define MAM_ACLR_LOCKBLOCK19_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK19(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK19_SHIFT))&MAM_ACLR_LOCKBLOCK19_MASK)
#define MAM_ACLR_LOCKBLOCK18_MASK 0x40000u
#define MAM_ACLR_LOCKBLOCK18_SHIFT 18u
#define MAM_ACLR_LOCKBLOCK18_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK18(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK18_SHIFT))&MAM_ACLR_LOCKBLOCK18_MASK)
#define MAM_ACLR_LOCKBLOCK17_MASK 0x20000u
#define MAM_ACLR_LOCKBLOCK17_SHIFT 17u
#define MAM_ACLR_LOCKBLOCK17_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK17(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK17_SHIFT))&MAM_ACLR_LOCKBLOCK17_MASK)
#define MAM_ACLR_LOCKBLOCK16_MASK 0x10000u
#define MAM_ACLR_LOCKBLOCK16_SHIFT 16u
#define MAM_ACLR_LOCKBLOCK16_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK16(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK16_SHIFT))&MAM_ACLR_LOCKBLOCK16_MASK)
#define MAM_ACLR_LOCKBLOCK15_MASK 0x8000u
#define MAM_ACLR_LOCKBLOCK15_SHIFT 15u
#define MAM_ACLR_LOCKBLOCK15_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK15(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK15_SHIFT))&MAM_ACLR_LOCKBLOCK15_MASK)
#define MAM_ACLR_LOCKBLOCK14_MASK 0x4000u
#define MAM_ACLR_LOCKBLOCK14_SHIFT 14u
#define MAM_ACLR_LOCKBLOCK14_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK14(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK14_SHIFT))&MAM_ACLR_LOCKBLOCK14_MASK)
#define MAM_ACLR_LOCKBLOCK13_MASK 0x2000u
#define MAM_ACLR_LOCKBLOCK13_SHIFT 13u
#define MAM_ACLR_LOCKBLOCK13_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK13(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK13_SHIFT))&MAM_ACLR_LOCKBLOCK13_MASK)
#define MAM_ACLR_LOCKBLOCK12_MASK 0x1000u
#define MAM_ACLR_LOCKBLOCK12_SHIFT 12u
#define MAM_ACLR_LOCKBLOCK12_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK12(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK12_SHIFT))&MAM_ACLR_LOCKBLOCK12_MASK)
#define MAM_ACLR_LOCKBLOCK11_MASK 0x800u
#define MAM_ACLR_LOCKBLOCK11_SHIFT 11u
#define MAM_ACLR_LOCKBLOCK11_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK11(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK11_SHIFT))&MAM_ACLR_LOCKBLOCK11_MASK)
#define MAM_ACLR_LOCKBLOCK10_MASK 0x400u
#define MAM_ACLR_LOCKBLOCK10_SHIFT 10u
#define MAM_ACLR_LOCKBLOCK10_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK10(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK10_SHIFT))&MAM_ACLR_LOCKBLOCK10_MASK)
#define MAM_ACLR_LOCKBLOCK9_MASK 0x200u
#define MAM_ACLR_LOCKBLOCK9_SHIFT 9u
#define MAM_ACLR_LOCKBLOCK9_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK9(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK9_SHIFT))&MAM_ACLR_LOCKBLOCK9_MASK)
#define MAM_ACLR_LOCKBLOCK8_MASK 0x100u
#define MAM_ACLR_LOCKBLOCK8_SHIFT 8u
#define MAM_ACLR_LOCKBLOCK8_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK8(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK8_SHIFT))&MAM_ACLR_LOCKBLOCK8_MASK)
#define MAM_ACLR_LOCKBLOCK7_MASK 0x80u
#define MAM_ACLR_LOCKBLOCK7_SHIFT 7u
#define MAM_ACLR_LOCKBLOCK7_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK7(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK7_SHIFT))&MAM_ACLR_LOCKBLOCK7_MASK)
#define MAM_ACLR_LOCKBLOCK6_MASK 0x40u
#define MAM_ACLR_LOCKBLOCK6_SHIFT 6u
#define MAM_ACLR_LOCKBLOCK6_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK6(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK6_SHIFT))&MAM_ACLR_LOCKBLOCK6_MASK)
#define MAM_ACLR_LOCKBLOCK5_MASK 0x20u
#define MAM_ACLR_LOCKBLOCK5_SHIFT 5u
#define MAM_ACLR_LOCKBLOCK5_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK5(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK5_SHIFT))&MAM_ACLR_LOCKBLOCK5_MASK)
#define MAM_ACLR_LOCKBLOCK4_MASK 0x10u
#define MAM_ACLR_LOCKBLOCK4_SHIFT 4u
#define MAM_ACLR_LOCKBLOCK4_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK4(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK4_SHIFT))&MAM_ACLR_LOCKBLOCK4_MASK)
#define MAM_ACLR_LOCKBLOCK3_MASK 0x8u
#define MAM_ACLR_LOCKBLOCK3_SHIFT 3u
#define MAM_ACLR_LOCKBLOCK3_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK3(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK3_SHIFT))&MAM_ACLR_LOCKBLOCK3_MASK)
#define MAM_ACLR_LOCKBLOCK2_MASK 0x4u
#define MAM_ACLR_LOCKBLOCK2_SHIFT 2u
#define MAM_ACLR_LOCKBLOCK2_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK2(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK2_SHIFT))&MAM_ACLR_LOCKBLOCK2_MASK)
#define MAM_ACLR_LOCKBLOCK1_MASK 0x2u
#define MAM_ACLR_LOCKBLOCK1_SHIFT 1u
#define MAM_ACLR_LOCKBLOCK1_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK1(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK1_SHIFT))&MAM_ACLR_LOCKBLOCK1_MASK)
#define MAM_ACLR_LOCKBLOCK0_MASK 0x1u
#define MAM_ACLR_LOCKBLOCK0_SHIFT 0u
#define MAM_ACLR_LOCKBLOCK0_WIDTH 1u
#define MAM_ACLR_LOCKBLOCK0(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACLR_LOCKBLOCK0_SHIFT))&MAM_ACLR_LOCKBLOCK0_MASK)
/* ACLR0 Reg Mask */
#define MAM_ACLR_MASK 0xFFFFFFFFu
/* ACR Bit Fields */
#define MAM_ACR_ACCPOLICY7_MASK 0xF0000000u
#define MAM_ACR_ACCPOLICY7_SHIFT 28u
#define MAM_ACR_ACCPOLICY7_WIDTH 4u
#define MAM_ACR_ACCPOLICY7(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACR_ACCPOLICY7_SHIFT))&MAM_ACR_ACCPOLICY7_MASK)
#define MAM_ACR_ACCPOLICY6_MASK 0xF000000u
#define MAM_ACR_ACCPOLICY6_SHIFT 24u
#define MAM_ACR_ACCPOLICY6_WIDTH 4u
#define MAM_ACR_ACCPOLICY6(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACR_ACCPOLICY6_SHIFT))&MAM_ACR_ACCPOLICY6_MASK)
#define MAM_ACR_ACCPOLICY5_MASK 0xF00000u
#define MAM_ACR_ACCPOLICY5_SHIFT 20u
#define MAM_ACR_ACCPOLICY5_WIDTH 4u
#define MAM_ACR_ACCPOLICY5(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACR_ACCPOLICY5_SHIFT))&MAM_ACR_ACCPOLICY5_MASK)
#define MAM_ACR_ACCPOLICY4_MASK 0xF0000u
#define MAM_ACR_ACCPOLICY4_SHIFT 16u
#define MAM_ACR_ACCPOLICY4_WIDTH 4u
#define MAM_ACR_ACCPOLICY4(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACR_ACCPOLICY4_SHIFT))&MAM_ACR_ACCPOLICY4_MASK)
#define MAM_ACR_ACCPOLICY3_MASK 0xF000u
#define MAM_ACR_ACCPOLICY3_SHIFT 12u
#define MAM_ACR_ACCPOLICY3_WIDTH 4u
#define MAM_ACR_ACCPOLICY3(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACR_ACCPOLICY3_SHIFT))&MAM_ACR_ACCPOLICY3_MASK)
#define MAM_ACR_ACCPOLICY2_MASK 0xF00u
#define MAM_ACR_ACCPOLICY2_SHIFT 8u
#define MAM_ACR_ACCPOLICY2_WIDTH 4u
#define MAM_ACR_ACCPOLICY2(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACR_ACCPOLICY2_SHIFT))&MAM_ACR_ACCPOLICY2_MASK)
#define MAM_ACR_ACCPOLICY1_MASK 0xF0u
#define MAM_ACR_ACCPOLICY1_SHIFT 4u
#define MAM_ACR_ACCPOLICY1_WIDTH 4u
#define MAM_ACR_ACCPOLICY1(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACR_ACCPOLICY1_SHIFT))&MAM_ACR_ACCPOLICY1_MASK)
#define MAM_ACR_ACCPOLICY0_MASK 0xFu
#define MAM_ACR_ACCPOLICY0_SHIFT 0u
#define MAM_ACR_ACCPOLICY0_WIDTH 4u
#define MAM_ACR_ACCPOLICY0(x) (((uint32_t)(((uint32_t)(x))<<MAM_ACR_ACCPOLICY0_SHIFT))&MAM_ACR_ACCPOLICY0_MASK)
/* ACR0 Reg Mask */
#define MAM_ACR_MASK 0xFFFFFFFFu
/*!
* @}
*/ /* end of group MAM_Register_Masks */
/*!
* @}
*/ /* end of group MAM_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7240_mb_regs.h Normal file
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#ifndef _FC7240_MB_NU_Tztufn18_REGS_H_
#define _FC7240_MB_NU_Tztufn18_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- MB Peripheral Access Layer
---------------------------------------------------------------------------- */
#define MB_CHANNEL_CONFIG_COUNT 4
#define MB_INT_CONFIG_COUNT 2
/*!
* @addtogroup MB_Peripheral_Access_Layer MB Peripheral Access Layer
* @{
*/
/** MB - Size of Registers Arrays */
/** MB - Register Layout Typedef */
typedef struct {
struct
{
__I uint32_t MB_CCn_SEMA ; /* Communication Channel Smeaphore Register, offset: 0x0 */
__IO uint32_t MB_CCn_SEMA_UNLK ; /* Communication Channel Smeaphore Unlock Register, offset: 0x4 */
__O uint32_t MB_CCn_REQUEST ; /* Communication Channel Request Register, offset: 0x8 */
__IO uint32_t MB_CCn_DONE ; /* Communication Channel Done Register, offset: 0xc */
__IO uint32_t MB_CCn_DONE_MASK ; /* Communication Channel Done Mask Register, offset: 0x10 */
__IO uint32_t MB_CCn_DATA0 ; /* Communication Channel Data Register0, offset: 0x14 */
__IO uint32_t MB_CCn_DATA1 ; /* Communication Channel Data Register1, offset: 0x18 */
__I uint32_t MB_CCn_STAT ; /* Communication Channel Status Register, offset: 0x1c */
__O uint32_t MB_CCn_CLR ; /* Communication Channel Clear Register, offset: 0x20 */
uint8_t RESERVED_0[12];
} CHANNEL[MB_CHANNEL_CONFIG_COUNT];
uint8_t RESERVED_15[1856];
struct
{
__IO uint32_t MB_INTn_FLG ; /* Interrupt Channel Flag Register, offset: 0x800 */
__IO uint32_t MB_INTn_FLG_MASK ; /* Interrupt Channel Flag Mask Register, offset: 0x804 */
__IO uint32_t MB_INTn_INTEN ; /* Interrupt Channel Interrupt Enable Register, offset: 0x808 */
__I uint32_t MB_INTn_FLG_STAT ; /* Interrupt Channel Flag Status Register, offset: 0x80c */
__IO uint32_t MB_INTn_CTRL ; /* Interrupt Channel Control Register, offset: 0x810 */
uint8_t RESERVED_2[12];
} INTR[MB_INT_CONFIG_COUNT];
} MB_Type, *MB_MemMapPtr;
/** Number of instances of the MB module. */
#define MB_INSTANCE_COUNT (1u)
/* MB - Peripheral instance base addresses */
/** Peripheral MB base address */
#define MB_BASE (0x40058000u)
/** Peripheral MB base pointer */
#define MB ((MB_Type *)MB_BASE)
/** Array initializer of MB peripheral base addresses */
#define MB_BASE_ADDRS {MB_BASE}
/** Array initializer of MB peripheral base pointers */
#define MB_BASE_PTRS {MB}
// need fill by yourself
///** Number of interrupt vector arrays for the MB module. */
//#define MB_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the MB module. */
//#define MB_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the MB peripheral type */
//#define MB_IRQS {MB_IRQn}
/* ----------------------------------------------------------------------------
-- MB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MB_Register_Masks MB Register Masks
* @{
*/
/* CCn_SEMA Bit Fields */
#define MB_CCn_SEMA_LOCK_MASK 0x80000000u
#define MB_CCn_SEMA_LOCK_SHIFT 31u
#define MB_CCn_SEMA_LOCK_WIDTH 1u
#define MB_CCn_SEMA_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_LOCK_SHIFT))&MB_CCn_SEMA_LOCK_MASK)
#define MB_CCn_SEMA_LOCK_MASTER_ID_MASK 0xF0u
#define MB_CCn_SEMA_LOCK_MASTER_ID_SHIFT 4u
#define MB_CCn_SEMA_LOCK_MASTER_ID_WIDTH 4u
#define MB_CCn_SEMA_LOCK_MASTER_ID(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_LOCK_MASTER_ID_SHIFT))&MB_CCn_SEMA_LOCK_MASTER_ID_MASK)
#define MB_CCn_SEMA_LOCK_MASTER_SEC_MASK 0x2u
#define MB_CCn_SEMA_LOCK_MASTER_SEC_SHIFT 1u
#define MB_CCn_SEMA_LOCK_MASTER_SEC_WIDTH 1u
#define MB_CCn_SEMA_LOCK_MASTER_SEC(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_LOCK_MASTER_SEC_SHIFT))&MB_CCn_SEMA_LOCK_MASTER_SEC_MASK)
#define MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_MASK 0x1u
#define MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_SHIFT 0u
#define MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_WIDTH 1u
#define MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_SHIFT))&MB_CCn_SEMA_LOCK_MASTER_SUPERVISOR_MASK)
/* CC0_SEMA Reg Mask */
#define MB_CCn_SEMA_MASK 0x800000F3u
/* CCn_SEMA_UNLK Bit Fields */
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_MASK 0x3u
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_SHIFT 0u
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_WIDTH 2u
#define MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_SHIFT))&MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_MASK)
/* CCn_REQUEST Bit Fields */
#define MB_CCn_REQUEST_REQ_MASK 0x3u
#define MB_CCn_REQUEST_REQ_SHIFT 0u
#define MB_CCn_REQUEST_REQ_WIDTH 2u
#define MB_CCn_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_REQUEST_REQ_SHIFT))&MB_CCn_REQUEST_REQ_MASK)
/* CCn_DONE Bit Fields */
#define MB_CCn_DONE_DONE_MASK 0x3u
#define MB_CCn_DONE_DONE_SHIFT 0u
#define MB_CCn_DONE_DONE_WIDTH 2u
#define MB_CCn_DONE_DONE(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_DONE_SHIFT))&MB_CCn_DONE_DONE_MASK)
/* CCn_DONE_MASK Bit Fields */
#define MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK 0xF0000u
#define MB_CCn_DONE_MASK_DONE_MASTER_ID_SHIFT 16u
#define MB_CCn_DONE_MASK_DONE_MASTER_ID_WIDTH 4u
#define MB_CCn_DONE_MASK_DONE_MASTER_ID(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_MASK_DONE_MASTER_ID_SHIFT))&MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK)
#define MB_CCn_DONE_MASK_DONE_MASK_MASK 0x3u
#define MB_CCn_DONE_MASK_DONE_MASK_SHIFT 0u
#define MB_CCn_DONE_MASK_DONE_MASK_WIDTH 2u
#define MB_CCn_DONE_MASK_DONE_MASK(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DONE_MASK_DONE_MASK_SHIFT))&MB_CCn_DONE_MASK_DONE_MASK_MASK)
/* CC0_DONE_MASK Reg Mask */
#define MB_CCn_DONE_MASK_MASK 0x000F0003u
/* CCn_DATA0 Bit Fields */
#define MB_CCn_DATA0_DATA0_MASK 0xFFFFFFFFu
#define MB_CCn_DATA0_DATA0_SHIFT 0u
#define MB_CCn_DATA0_DATA0_WIDTH 32u
#define MB_CCn_DATA0_DATA0(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DATA0_DATA0_SHIFT))&MB_CCn_DATA0_DATA0_MASK)
/* CC0_DATA0 Reg Mask */
#define MB_CCn_DATA0_MASK 0xFFFFFFFFu
/* CCn_DATA1 Bit Fields */
#define MB_CCn_DATA1_DATA1_MASK 0xFFFFFFFFu
#define MB_CCn_DATA1_DATA1_SHIFT 0u
#define MB_CCn_DATA1_DATA1_WIDTH 32u
#define MB_CCn_DATA1_DATA1(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_DATA1_DATA1_SHIFT))&MB_CCn_DATA1_DATA1_MASK)
/* CC0_DATA1 Reg Mask */
#define MB_CCn_DATA1_MASK 0xFFFFFFFFu
/* CCn_STAT Bit Fields */
#define MB_CCn_STAT_CURRENT_LOCK_STATUS_MASK 0x80000000u
#define MB_CCn_STAT_CURRENT_LOCK_STATUS_SHIFT 31u
#define MB_CCn_STAT_CURRENT_LOCK_STATUS_WIDTH 1u
#define MB_CCn_STAT_CURRENT_LOCK_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_LOCK_STATUS_SHIFT))&MB_CCn_STAT_CURRENT_LOCK_STATUS_MASK)
#define MB_CCn_STAT_CURRENT_CPU_STATUS_MASK 0xFFFF00u
#define MB_CCn_STAT_CURRENT_CPU_STATUS_SHIFT 8u
#define MB_CCn_STAT_CURRENT_CPU_STATUS_WIDTH 16u
#define MB_CCn_STAT_CURRENT_CPU_STATUS(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_CPU_STATUS_SHIFT))&MB_CCn_STAT_CURRENT_CPU_STATUS_MASK)
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_MASK 0xF0u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_SHIFT 4u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_WIDTH 4u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_ID(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_SHIFT))&MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_MASK)
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_MASK 0x2u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_SHIFT 1u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_WIDTH 1u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_SHIFT))&MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_MASK)
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_MASK 0x1u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_SHIFT 0u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_WIDTH 1u
#define MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_SHIFT))&MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_MASK)
/* CC0_STAT Reg Mask */
#define MB_CCn_STAT_MASK 0x80FFFFF3u
/* CCn_CLR Bit Fields */
#define MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_MASK 0xFFFFFFFFu
#define MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_SHIFT 0u
#define MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_WIDTH 32u
#define MB_CCn_CLR_SOFTWARE_CLEAR_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_SHIFT))&MB_CCn_CLR_SOFTWARE_CLEAR_LOCK_MASK)
/* CC0_CLR Reg Mask */
#define MB_CCn_CLR_MASK 0xFFFFFFFFu
/* INTn_FLG Bit Fields */
#define MB_INTn_FLG_DONE_FLAG_MASK 0xF0000u
#define MB_INTn_FLG_DONE_FLAG_SHIFT 16u
#define MB_INTn_FLG_DONE_FLAG_WIDTH 4u
#define MB_INTn_FLG_DONE_FLAG(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_DONE_FLAG_SHIFT))&MB_INTn_FLG_DONE_FLAG_MASK)
#define MB_INTn_FLG_REQ_FLAG_MASK 0xFu
#define MB_INTn_FLG_REQ_FLAG_SHIFT 0u
#define MB_INTn_FLG_REQ_FLAG_WIDTH 4u
#define MB_INTn_FLG_REQ_FLAG(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_REQ_FLAG_SHIFT))&MB_INTn_FLG_REQ_FLAG_MASK)
/* INTn_FLG_MASK Bit Fields */
#define MB_INTn_FLG_MASK_DONE_FLAG_MASK_MASK 0xF0000u
#define MB_INTn_FLG_MASK_DONE_FLAG_MASK_SHIFT 16u
#define MB_INTn_FLG_MASK_DONE_FLAG_MASK_WIDTH 4u
#define MB_INTn_FLG_MASK_DONE_FLAG_MASK(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_MASK_DONE_FLAG_MASK_SHIFT))&MB_INTn_FLG_MASK_DONE_FLAG_MASK_MASK)
#define MB_INTn_FLG_MASK_REQ_FLAG_MASK_MASK 0xFu
#define MB_INTn_FLG_MASK_REQ_FLAG_MASK_SHIFT 0u
#define MB_INTn_FLG_MASK_REQ_FLAG_MASK_WIDTH 4u
#define MB_INTn_FLG_MASK_REQ_FLAG_MASK(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_MASK_REQ_FLAG_MASK_SHIFT))&MB_INTn_FLG_MASK_REQ_FLAG_MASK_MASK)
/* INT0_FLG_MASK Reg Mask */
#define MB_INTn_FLG_MASK_MASK 0x000F000Fu
/* INTn_INTEN Bit Fields */
#define MB_INTn_INTEN_DONE_INT_EN_MASK 0xF0000u
#define MB_INTn_INTEN_DONE_INT_EN_SHIFT 16u
#define MB_INTn_INTEN_DONE_INT_EN_WIDTH 4u
#define MB_INTn_INTEN_DONE_INT_EN(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_INTEN_DONE_INT_EN_SHIFT))&MB_INTn_INTEN_DONE_INT_EN_MASK)
#define MB_INTn_INTEN_REQ_INT_EN_MASK 0xFu
#define MB_INTn_INTEN_REQ_INT_EN_SHIFT 0u
#define MB_INTn_INTEN_REQ_INT_EN_WIDTH 4u
#define MB_INTn_INTEN_REQ_INT_EN(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_INTEN_REQ_INT_EN_SHIFT))&MB_INTn_INTEN_REQ_INT_EN_MASK)
/* INT0_INTEN Reg Mask */
#define MB_INTn_INTEN_MASK 0x000F000Fu
/* INTn_FLG_STAT Bit Fields */
#define MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_MASK 0xF0000u
#define MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_SHIFT 16u
#define MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_WIDTH 4u
#define MB_INTn_FLG_STAT_FLG_DONE_INT_STAT(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_SHIFT))&MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_MASK)
#define MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_MASK 0xFu
#define MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_SHIFT 0u
#define MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_WIDTH 4u
#define MB_INTn_FLG_STAT_FLG_REQ_INT_STAT(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_SHIFT))&MB_INTn_FLG_STAT_FLG_REQ_INT_STAT_MASK)
/* INT0_FLG_STAT Reg Mask */
#define MB_INTn_FLG_STAT_MASK 0x000F000Fu
/* INTn_CTRL Bit Fields */
#define MB_INTn_CTRL_INTEN_LOCK_MASK 0x4u
#define MB_INTn_CTRL_INTEN_LOCK_SHIFT 2u
#define MB_INTn_CTRL_INTEN_LOCK_WIDTH 1u
#define MB_INTn_CTRL_INTEN_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_CTRL_INTEN_LOCK_SHIFT))&MB_INTn_CTRL_INTEN_LOCK_MASK)
#define MB_INTn_CTRL_FLG_MASK_LOCK_MASK 0x2u
#define MB_INTn_CTRL_FLG_MASK_LOCK_SHIFT 1u
#define MB_INTn_CTRL_FLG_MASK_LOCK_WIDTH 1u
#define MB_INTn_CTRL_FLG_MASK_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_CTRL_FLG_MASK_LOCK_SHIFT))&MB_INTn_CTRL_FLG_MASK_LOCK_MASK)
#define MB_INTn_CTRL_FLG_LOCK_MASK 0x1u
#define MB_INTn_CTRL_FLG_LOCK_SHIFT 0u
#define MB_INTn_CTRL_FLG_LOCK_WIDTH 1u
#define MB_INTn_CTRL_FLG_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MB_INTn_CTRL_FLG_LOCK_SHIFT))&MB_INTn_CTRL_FLG_LOCK_MASK)
/* INT0_CTRL Reg Mask */
#define MB_INTn_CTRL_MASK 0x00000007u
/* Channel master done code */
#define MB_MASTER_DONE_CODE 0xFC730000u
/* force unlock channel */
#define MB_FORCE_UNLOCK_CODE 0xFC350000u
/*!
* @}
*/ /* end of group MB_Register_Masks */
/*!
* @}
*/ /* end of group MB_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_PMC_NU_Tztufn12_REGS_H_
#define _FC7240_PMC_NU_Tztufn12_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- PMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
* @{
*/
/** PMC - Size of Registers Arrays */
/** PMC - Register Layout Typedef */
typedef struct {
__IO uint32_t LVSCR ; /* Low Voltage Status and Control Register, offset: 0x0 */
__IO uint32_t CONFIG ; /* PMC Configuration Register, offset: 0x4 */
} PMC_Type, *PMC_MemMapPtr;
/** Number of instances of the PMC module. */
#define PMC_INSTANCE_COUNT (1u)
/* PMC - Peripheral instance base addresses */
/** Peripheral PMC base address */
#define PMC_BASE (0x40044000u)
/** Peripheral PMC base pointer */
#define PMC ((PMC_Type *)PMC_BASE)
/** Array initializer of PMC peripheral base addresses */
#define PMC_BASE_ADDRS {PMC_BASE}
/** Array initializer of PMC peripheral base pointers */
#define PMC_BASE_PTRS {PMC}
// need fill by yourself
///** Number of interrupt vector arrays for the PMC module. */
//#define PMC_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the PMC module. */
//#define PMC_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the PMC peripheral type */
//#define PMC_IRQS {PMC_IRQn}
/* ----------------------------------------------------------------------------
-- PMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PMC_Register_Masks PMC Register Masks
* @{
*/
/* LVSCR Bit Fields */
#define PMC_LVSCR_POR_FLAG_MASK 0x80000000u
#define PMC_LVSCR_POR_FLAG_SHIFT 31u
#define PMC_LVSCR_POR_FLAG_WIDTH 1u
#define PMC_LVSCR_POR_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_POR_FLAG_SHIFT))&PMC_LVSCR_POR_FLAG_MASK)
#define PMC_LVSCR_V15_STATUS_MASK 0xC000000u
#define PMC_LVSCR_V15_STATUS_SHIFT 26u
#define PMC_LVSCR_V15_STATUS_WIDTH 2u
#define PMC_LVSCR_V15_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_V15_STATUS_SHIFT))&PMC_LVSCR_V15_STATUS_MASK)
#define PMC_LVSCR_LVR1P1V_RPM_FLAG_MASK 0x800000u
#define PMC_LVSCR_LVR1P1V_RPM_FLAG_SHIFT 23u
#define PMC_LVSCR_LVR1P1V_RPM_FLAG_WIDTH 1u
#define PMC_LVSCR_LVR1P1V_RPM_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVR1P1V_RPM_FLAG_SHIFT))&PMC_LVSCR_LVR1P1V_RPM_FLAG_MASK)
#define PMC_LVSCR_LVR1P1V_FPM_FLAG_MASK 0x400000u
#define PMC_LVSCR_LVR1P1V_FPM_FLAG_SHIFT 22u
#define PMC_LVSCR_LVR1P1V_FPM_FLAG_WIDTH 1u
#define PMC_LVSCR_LVR1P1V_FPM_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVR1P1V_FPM_FLAG_SHIFT))&PMC_LVSCR_LVR1P1V_FPM_FLAG_MASK)
#define PMC_LVSCR_LVR2P5V_RPM_FLAG_MASK 0x200000u
#define PMC_LVSCR_LVR2P5V_RPM_FLAG_SHIFT 21u
#define PMC_LVSCR_LVR2P5V_RPM_FLAG_WIDTH 1u
#define PMC_LVSCR_LVR2P5V_RPM_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVR2P5V_RPM_FLAG_SHIFT))&PMC_LVSCR_LVR2P5V_RPM_FLAG_MASK)
#define PMC_LVSCR_LVR2P5V_FPM_FLAG_MASK 0x100000u
#define PMC_LVSCR_LVR2P5V_FPM_FLAG_SHIFT 20u
#define PMC_LVSCR_LVR2P5V_FPM_FLAG_WIDTH 1u
#define PMC_LVSCR_LVR2P5V_FPM_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVR2P5V_FPM_FLAG_SHIFT))&PMC_LVSCR_LVR2P5V_FPM_FLAG_MASK)
#define PMC_LVSCR_LVR5V_RPM_FLAG_MASK 0x20000u
#define PMC_LVSCR_LVR5V_RPM_FLAG_SHIFT 17u
#define PMC_LVSCR_LVR5V_RPM_FLAG_WIDTH 1u
#define PMC_LVSCR_LVR5V_RPM_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVR5V_RPM_FLAG_SHIFT))&PMC_LVSCR_LVR5V_RPM_FLAG_MASK)
#define PMC_LVSCR_LVR5V_FPM_FLAG_MASK 0x10000u
#define PMC_LVSCR_LVR5V_FPM_FLAG_SHIFT 16u
#define PMC_LVSCR_LVR5V_FPM_FLAG_WIDTH 1u
#define PMC_LVSCR_LVR5V_FPM_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVR5V_FPM_FLAG_SHIFT))&PMC_LVSCR_LVR5V_FPM_FLAG_MASK)
#define PMC_LVSCR_HVD1P5V_STATUS_MASK 0x4000u
#define PMC_LVSCR_HVD1P5V_STATUS_SHIFT 14u
#define PMC_LVSCR_HVD1P5V_STATUS_WIDTH 1u
#define PMC_LVSCR_HVD1P5V_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD1P5V_STATUS_SHIFT))&PMC_LVSCR_HVD1P5V_STATUS_MASK)
#define PMC_LVSCR_LVD1P5V_STATUS_MASK 0x2000u
#define PMC_LVSCR_LVD1P5V_STATUS_SHIFT 13u
#define PMC_LVSCR_LVD1P5V_STATUS_WIDTH 1u
#define PMC_LVSCR_LVD1P5V_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVD1P5V_STATUS_SHIFT))&PMC_LVSCR_LVD1P5V_STATUS_MASK)
#define PMC_LVSCR_LVD5V_STATUS_MASK 0x1000u
#define PMC_LVSCR_LVD5V_STATUS_SHIFT 12u
#define PMC_LVSCR_LVD5V_STATUS_WIDTH 1u
#define PMC_LVSCR_LVD5V_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVD5V_STATUS_SHIFT))&PMC_LVSCR_LVD5V_STATUS_MASK)
#define PMC_LVSCR_HVD1P1V_STATUS_MASK 0x800u
#define PMC_LVSCR_HVD1P1V_STATUS_SHIFT 11u
#define PMC_LVSCR_HVD1P1V_STATUS_WIDTH 1u
#define PMC_LVSCR_HVD1P1V_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD1P1V_STATUS_SHIFT))&PMC_LVSCR_HVD1P1V_STATUS_MASK)
#define PMC_LVSCR_HVD2P5V_STATUS_MASK 0x400u
#define PMC_LVSCR_HVD2P5V_STATUS_SHIFT 10u
#define PMC_LVSCR_HVD2P5V_STATUS_WIDTH 1u
#define PMC_LVSCR_HVD2P5V_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD2P5V_STATUS_SHIFT))&PMC_LVSCR_HVD2P5V_STATUS_MASK)
#define PMC_LVSCR_HVD5V_STATUS_MASK 0x100u
#define PMC_LVSCR_HVD5V_STATUS_SHIFT 8u
#define PMC_LVSCR_HVD5V_STATUS_WIDTH 1u
#define PMC_LVSCR_HVD5V_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD5V_STATUS_SHIFT))&PMC_LVSCR_HVD5V_STATUS_MASK)
#define PMC_LVSCR_HVD1P5V_FLAG_MASK 0x40u
#define PMC_LVSCR_HVD1P5V_FLAG_SHIFT 6u
#define PMC_LVSCR_HVD1P5V_FLAG_WIDTH 1u
#define PMC_LVSCR_HVD1P5V_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD1P5V_FLAG_SHIFT))&PMC_LVSCR_HVD1P5V_FLAG_MASK)
#define PMC_LVSCR_LVD1P5V_FLAG_MASK 0x20u
#define PMC_LVSCR_LVD1P5V_FLAG_SHIFT 5u
#define PMC_LVSCR_LVD1P5V_FLAG_WIDTH 1u
#define PMC_LVSCR_LVD1P5V_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVD1P5V_FLAG_SHIFT))&PMC_LVSCR_LVD1P5V_FLAG_MASK)
#define PMC_LVSCR_LVD5V_FLAG_MASK 0x10u
#define PMC_LVSCR_LVD5V_FLAG_SHIFT 4u
#define PMC_LVSCR_LVD5V_FLAG_WIDTH 1u
#define PMC_LVSCR_LVD5V_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_LVD5V_FLAG_SHIFT))&PMC_LVSCR_LVD5V_FLAG_MASK)
#define PMC_LVSCR_HVD1P1V_FLAG_MASK 0x8u
#define PMC_LVSCR_HVD1P1V_FLAG_SHIFT 3u
#define PMC_LVSCR_HVD1P1V_FLAG_WIDTH 1u
#define PMC_LVSCR_HVD1P1V_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD1P1V_FLAG_SHIFT))&PMC_LVSCR_HVD1P1V_FLAG_MASK)
#define PMC_LVSCR_HVD2P5V_FLAG_MASK 0x4u
#define PMC_LVSCR_HVD2P5V_FLAG_SHIFT 2u
#define PMC_LVSCR_HVD2P5V_FLAG_WIDTH 1u
#define PMC_LVSCR_HVD2P5V_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD2P5V_FLAG_SHIFT))&PMC_LVSCR_HVD2P5V_FLAG_MASK)
#define PMC_LVSCR_HVD5V_FLAG_MASK 0x1u
#define PMC_LVSCR_HVD5V_FLAG_SHIFT 0u
#define PMC_LVSCR_HVD5V_FLAG_WIDTH 1u
#define PMC_LVSCR_HVD5V_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PMC_LVSCR_HVD5V_FLAG_SHIFT))&PMC_LVSCR_HVD5V_FLAG_MASK)
/* LVSCR Reg Mask */
#define PMC_LVSCR_MASK 0x8CF37D7Du
/* CONFIG Bit Fields */
#define PMC_CONFIG_V15_LOCK_MASK 0x8000u
#define PMC_CONFIG_V15_LOCK_SHIFT 15u
#define PMC_CONFIG_V15_LOCK_WIDTH 1u
#define PMC_CONFIG_V15_LOCK(x) (((uint32_t)(((uint32_t)(x))<<PMC_CONFIG_V15_LOCK_SHIFT))&PMC_CONFIG_V15_LOCK_MASK)
#define PMC_CONFIG_LVD_IE_MASK 0x200u
#define PMC_CONFIG_LVD_IE_SHIFT 9u
#define PMC_CONFIG_LVD_IE_WIDTH 1u
#define PMC_CONFIG_LVD_IE(x) (((uint32_t)(((uint32_t)(x))<<PMC_CONFIG_LVD_IE_SHIFT))&PMC_CONFIG_LVD_IE_MASK)
#define PMC_CONFIG_HVD_IE_MASK 0x100u
#define PMC_CONFIG_HVD_IE_SHIFT 8u
#define PMC_CONFIG_HVD_IE_WIDTH 1u
#define PMC_CONFIG_HVD_IE(x) (((uint32_t)(((uint32_t)(x))<<PMC_CONFIG_HVD_IE_SHIFT))&PMC_CONFIG_HVD_IE_MASK)
#define PMC_CONFIG_V15_CTRL_EN_MASK 0x20u
#define PMC_CONFIG_V15_CTRL_EN_SHIFT 5u
#define PMC_CONFIG_V15_CTRL_EN_WIDTH 1u
#define PMC_CONFIG_V15_CTRL_EN(x) (((uint32_t)(((uint32_t)(x))<<PMC_CONFIG_V15_CTRL_EN_SHIFT))&PMC_CONFIG_V15_CTRL_EN_MASK)
#define PMC_CONFIG_V15_AUTOSW_MASK 0x10u
#define PMC_CONFIG_V15_AUTOSW_SHIFT 4u
#define PMC_CONFIG_V15_AUTOSW_WIDTH 1u
#define PMC_CONFIG_V15_AUTOSW(x) (((uint32_t)(((uint32_t)(x))<<PMC_CONFIG_V15_AUTOSW_SHIFT))&PMC_CONFIG_V15_AUTOSW_MASK)
#define PMC_CONFIG_RPM_VDD2P5_EN_MASK 0x8u
#define PMC_CONFIG_RPM_VDD2P5_EN_SHIFT 3u
#define PMC_CONFIG_RPM_VDD2P5_EN_WIDTH 1u
#define PMC_CONFIG_RPM_VDD2P5_EN(x) (((uint32_t)(((uint32_t)(x))<<PMC_CONFIG_RPM_VDD2P5_EN_SHIFT))&PMC_CONFIG_RPM_VDD2P5_EN_MASK)
/* CONFIG Reg Mask */
#define PMC_CONFIG_MASK 0x00008338u
/*!
* @}
*/ /* end of group PMC_Register_Masks */
/*!
* @}
*/ /* end of group PMC_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_PORT_NU_Tztufn47_REGS_H_
#define _FC7240_PORT_NU_Tztufn47_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- PORT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
* @{
*/
/** PORT - Size of Registers Arrays */
/** PORT - Register Layout Typedef */
#define PORT_PCR_COUNT 32
typedef struct {
__IO uint32_t PCR[PORT_PCR_COUNT] ; /* Port Control Register, offset: 0x0 */
__O uint32_t GPCLR ; /* Global Pin Control Low Register, offset: 0x80 */
__O uint32_t GPCHR ; /* Global Pin Control High Register, offset: 0x84 */
__O uint32_t GICLR ; /* Global Interrupt Control Low Register, offset: 0x88 */
__O uint32_t GICHR ; /* Global Interrupt Control High Register, offset: 0x8C */
uint8_t RESERVED_0[16];
__IO uint32_t ISFR ; /* Interrupt Status Flag Register, offset: 0xA0 */
uint8_t RESERVED_1[28];
__IO uint32_t DFER ; /* Digital Filter Enable Register, offset: 0xC0 */
__IO uint32_t DFCR ; /* Digital Filter Clock Register, offset: 0xC4 */
__IO uint32_t DFWR ; /* Digital Filter Width Register, offset: 0xC8 */
__IO uint32_t GLDWP ; /* Global Domain Write Protection Register, offset: 0xCC */
} PORT_Type, *PORT_MemMapPtr;
/** Number of instances of the PORT module. */
#define PORT_INSTANCE_COUNT (5u)
/* PORT - Peripheral instance base addresses */
/** Peripheral PORTA base address */
#define PORTA_BASE (0x40047000u)
/** Peripheral PORTA base pointer */
#define PORTA ((PORT_Type *)PORTA_BASE)
/** Peripheral PORTB base address */
#define PORTB_BASE (0x40048000u)
/** Peripheral PORTB base pointer */
#define PORTB ((PORT_Type *)PORTB_BASE)
/** Peripheral PORTC base address */
#define PORTC_BASE (0x40049000u)
/** Peripheral PORTC base pointer */
#define PORTC ((PORT_Type *)PORTC_BASE)
/** Peripheral PORTD base address */
#define PORTD_BASE (0x4004a000u)
/** Peripheral PORTD base pointer */
#define PORTD ((PORT_Type *)PORTD_BASE)
/** Peripheral PORTE base address */
#define PORTE_BASE (0x4004b000u)
/** Peripheral PORTE base pointer */
#define PORTE ((PORT_Type *)PORTE_BASE)
/** Array initializer of PORT peripheral base addresses */
#define PORT_BASE_ADDRS {PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE}
/** Array initializer of PORT peripheral base pointers */
#define PORT_BASE_PTRS {PORTA, PORTB, PORTC, PORTD, PORTE}
// need fill by yourself
///** Number of interrupt vector arrays for the PORT module. */
//#define PORT_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the PORT module. */
//#define PORT_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the PORT peripheral type */
//#define PORT_IRQS {PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn}
/* ----------------------------------------------------------------------------
-- PORT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PORT_Register_Masks PORT Register Masks
* @{
*/
/* PCR Bit Fields */
#define PORT_PCR_DWPLK_MASK 0x80000000u
#define PORT_PCR_DWPLK_SHIFT 31u
#define PORT_PCR_DWPLK_WIDTH 1u
#define PORT_PCR_DWPLK(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DWPLK_SHIFT))&PORT_PCR_DWPLK_MASK)
#define PORT_PCR_DWP_MASK 0x3E000000u
#define PORT_PCR_DWP_SHIFT 25u
#define PORT_PCR_DWP_WIDTH 5u
#define PORT_PCR_DWP(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DWP_SHIFT))&PORT_PCR_DWP_MASK)
#define PORT_PCR_ISF_MASK 0x1000000u
#define PORT_PCR_ISF_SHIFT 24u
#define PORT_PCR_ISF_WIDTH 1u
#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
#define PORT_PCR_ESTOP_MASK 0x200000u
#define PORT_PCR_ESTOP_SHIFT 21u
#define PORT_PCR_ESTOP_WIDTH 1u
#define PORT_PCR_ESTOP(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ESTOP_SHIFT))&PORT_PCR_ESTOP_MASK)
#define PORT_PCR_WKUDIS_MASK 0x100000u
#define PORT_PCR_WKUDIS_SHIFT 20u
#define PORT_PCR_WKUDIS_WIDTH 1u
#define PORT_PCR_WKUDIS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_WKUDIS_SHIFT))&PORT_PCR_WKUDIS_MASK)
#define PORT_PCR_IRQC_MASK 0xF0000u
#define PORT_PCR_IRQC_SHIFT 16u
#define PORT_PCR_IRQC_WIDTH 4u
#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
#define PORT_PCR_LK_MASK 0x8000u
#define PORT_PCR_LK_SHIFT 15u
#define PORT_PCR_LK_WIDTH 1u
#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
#define PORT_PCR_MUX_MASK 0x700u
#define PORT_PCR_MUX_SHIFT 8u
#define PORT_PCR_MUX_WIDTH 3u
#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
#define PORT_PCR_DSE1_MASK 0x80u
#define PORT_PCR_DSE1_SHIFT 7u
#define PORT_PCR_DSE1_WIDTH 1u
#define PORT_PCR_DSE1(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE1_SHIFT))&PORT_PCR_DSE1_MASK)
#define PORT_PCR_DSE0_MASK 0x40u
#define PORT_PCR_DSE0_SHIFT 6u
#define PORT_PCR_DSE0_WIDTH 1u
#define PORT_PCR_DSE0(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE0_SHIFT))&PORT_PCR_DSE0_MASK)
#define PORT_PCR_ODE_MASK 0x20u
#define PORT_PCR_ODE_SHIFT 5u
#define PORT_PCR_ODE_WIDTH 1u
#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
#define PORT_PCR_PFE_MASK 0x10u
#define PORT_PCR_PFE_SHIFT 4u
#define PORT_PCR_PFE_WIDTH 1u
#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
#define PORT_PCR_SRE_MASK 0x4u
#define PORT_PCR_SRE_SHIFT 2u
#define PORT_PCR_SRE_WIDTH 1u
#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
#define PORT_PCR_PE_MASK 0x2u
#define PORT_PCR_PE_SHIFT 1u
#define PORT_PCR_PE_WIDTH 1u
#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
#define PORT_PCR_PS_MASK 0x1u
#define PORT_PCR_PS_SHIFT 0u
#define PORT_PCR_PS_WIDTH 1u
#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
#define PORT_PCR_LOW_16BITS_MASK 0xFFFFU
#define PORT_PCR_HIGH_16BITS_MASK 0xFFFF0000U
/* PCR0 Reg Mask */
#define PORT_PCR_MASK 0xBF3F87F7u
/* GPCLR Bit Fields */
#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
#define PORT_GPCLR_GPWE_SHIFT 16u
#define PORT_GPCLR_GPWE_WIDTH 16u
#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
#define PORT_GPCLR_GPWD_MASK 0xFFFFu
#define PORT_GPCLR_GPWD_SHIFT 0u
#define PORT_GPCLR_GPWD_WIDTH 16u
#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
/* GPCLR Reg Mask */
#define PORT_GPCLR_MASK 0xFFFFFFFFu
/* GPCHR Bit Fields */
#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
#define PORT_GPCHR_GPWE_SHIFT 16u
#define PORT_GPCHR_GPWE_WIDTH 16u
#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
#define PORT_GPCHR_GPWD_MASK 0xFFFFu
#define PORT_GPCHR_GPWD_SHIFT 0u
#define PORT_GPCHR_GPWD_WIDTH 16u
#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
/* GPCHR Reg Mask */
#define PORT_GPCHR_MASK 0xFFFFFFFFu
/* GICLR Bit Fields */
#define PORT_GICLR_GIWD_MASK 0xFFFF0000u
#define PORT_GICLR_GIWD_SHIFT 16u
#define PORT_GICLR_GIWD_WIDTH 16u
#define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICLR_GIWD_SHIFT))&PORT_GICLR_GIWD_MASK)
#define PORT_GICLR_GIWE_MASK 0xFFFFu
#define PORT_GICLR_GIWE_SHIFT 0u
#define PORT_GICLR_GIWE_WIDTH 16u
#define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICLR_GIWE_SHIFT))&PORT_GICLR_GIWE_MASK)
/* GICLR Reg Mask */
#define PORT_GICLR_MASK 0xFFFFFFFFu
/* GICHR Bit Fields */
#define PORT_GICHR_GIWD_MASK 0xFFFF0000u
#define PORT_GICHR_GIWD_SHIFT 16u
#define PORT_GICHR_GIWD_WIDTH 16u
#define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICHR_GIWD_SHIFT))&PORT_GICHR_GIWD_MASK)
#define PORT_GICHR_GIWE_MASK 0xFFFFu
#define PORT_GICHR_GIWE_SHIFT 0u
#define PORT_GICHR_GIWE_WIDTH 16u
#define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICHR_GIWE_SHIFT))&PORT_GICHR_GIWE_MASK)
/* GICHR Reg Mask */
#define PORT_GICHR_MASK 0xFFFFFFFFu
/* ISFR Bit Fields */
#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
#define PORT_ISFR_ISF_SHIFT 0u
#define PORT_ISFR_ISF_WIDTH 32u
#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
/* ISFR Reg Mask */
#define PORT_ISFR_MASK 0xFFFFFFFFu
/* DFER Bit Fields */
#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
#define PORT_DFER_DFE_SHIFT 0u
#define PORT_DFER_DFE_WIDTH 32u
#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
/* DFER Reg Mask */
#define PORT_DFER_MASK 0xFFFFFFFFu
/* DFCR Bit Fields */
#define PORT_DFCR_CS_MASK 0x1u
#define PORT_DFCR_CS_SHIFT 0u
#define PORT_DFCR_CS_WIDTH 1u
#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
/* DFCR Reg Mask */
#define PORT_DFCR_MASK 0x00000001u
/* DFWR Bit Fields */
#define PORT_DFWR_FILT_MASK 0x1Fu
#define PORT_DFWR_FILT_SHIFT 0u
#define PORT_DFWR_FILT_WIDTH 5u
#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
/* DFWR Reg Mask */
#define PORT_DFWR_MASK 0x0000001Fu
/* GLDWP Bit Fields */
#define PORT_GLDWP_DWPLK_MASK 0x80000000u
#define PORT_GLDWP_DWPLK_SHIFT 31u
#define PORT_GLDWP_DWPLK_WIDTH 1u
#define PORT_GLDWP_DWPLK(x) (((uint32_t)(((uint32_t)(x))<<PORT_GLDWP_DWPLK_SHIFT))&PORT_GLDWP_DWPLK_MASK)
#define PORT_GLDWP_DWP_MASK 0x3E000000u
#define PORT_GLDWP_DWP_SHIFT 25u
#define PORT_GLDWP_DWP_WIDTH 5u
#define PORT_GLDWP_DWP(x) (((uint32_t)(((uint32_t)(x))<<PORT_GLDWP_DWP_SHIFT))&PORT_GLDWP_DWP_MASK)
/* GLDWP Reg Mask */
#define PORT_GLDWP_MASK 0xBE000000u
/*!
* @}
*/ /* end of group PORT_Register_Masks */
/*!
* @}
*/ /* end of group PORT_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7240_ptimer_regs.h Normal file
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#ifndef _FC7240_PTIMER_NU_Tztufn31_REGS_H_
#define _FC7240_PTIMER_NU_Tztufn31_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- PTIMER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PTIMER_Peripheral_Access_Layer PTIMER Peripheral Access Layer
* @{
*/
/** PTIMER - Size of Registers Arrays */
#define PTIMER_CH_CNT 4u
#define PTIMER_CH_DLY_CNT 8u
#define PTIMER_DLY_CNT (PTIMER_CH_CNT * PTIMER_CH_DLY_CNT)
/** PTIMER - Register Layout Typedef */
typedef struct {
__IO uint32_t STATUS_CTRL ; /* Status and Control Register, offset: 0x0 */
__IO uint32_t MAX_CNT ; /* Max Count Number Register, offset: 0x4 */
__IO uint32_t CNT ; /* Counter Register, offset: 0x8 */
__IO uint32_t INT_DLY ; /* Interrupt Delay Register, offset: 0xC */
struct{
__IO uint32_t CTRL ; /* Channel n Control register 1, array offset: 0x10, array step: 0x28 */
__IO uint32_t STATUS ; /* Channel n Status register, array offset: 0x14, array step: 0x28 */
__IO uint32_t DLY[PTIMER_CH_DLY_CNT] ; /* Channel n Delay 0 register..Channel n Delay 7 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
} CH[PTIMER_CH_CNT] ; /* Channel n registers, array offset: 0x10, array step: 0x28 */
uint8_t RESERVED_0[224];
__IO uint32_t POEN ; /* Pulse-Out Enable Register, offset: 0x190 */
__IO uint32_t PODLY ; /* Pulse-Out Delay Register, offset: 0x194 */
} PTIMER_Type, *PTIMER_MemMapPtr;
/** Number of instances of the PTIMER module. */
#define PTIMER_INSTANCE_COUNT (2u)
/* PTIMER - Peripheral instance base addresses */
/** Peripheral PTIMER0 base address */
#define PTIMER0_BASE (0x40037000u)
/** Peripheral PTIMER0 base pointer */
#define PTIMER0 ((PTIMER_Type *)PTIMER0_BASE)
/** Peripheral PTIMER1 base address */
#define PTIMER1_BASE (0x40038000u)
/** Peripheral PTIMER1 base pointer */
#define PTIMER1 ((PTIMER_Type *)PTIMER1_BASE)
/** Array initializer of PTIMER peripheral base addresses */
#define PTIMER_BASE_ADDRS {PTIMER0_BASE, PTIMER1_BASE}
/** Array initializer of PTIMER peripheral base pointers */
#define PTIMER_BASE_PTRS {PTIMER0, PTIMER1}
// need fill by yourself
///** Number of interrupt vector arrays for the PTIMER module. */
//#define PTIMER_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the PTIMER module. */
//#define PTIMER_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the PTIMER peripheral type */
//#define PTIMER_IRQS {PTIMER0_IRQn, PTIMER1_IRQn}
/* ----------------------------------------------------------------------------
-- PTIMER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PTIMER_Register_Masks PTIMER Register Masks
* @{
*/
/* STATUS_CTRL Bit Fields */
#define PTIMER_STATUS_CTRL_LDMODE_MASK 0xC0000u
#define PTIMER_STATUS_CTRL_LDMODE_SHIFT 18u
#define PTIMER_STATUS_CTRL_LDMODE_WIDTH 2u
#define PTIMER_STATUS_CTRL_LDMODE(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_LDMODE_SHIFT))&PTIMER_STATUS_CTRL_LDMODE_MASK)
#define PTIMER_STATUS_CTRL_SERR_INTEN_MASK 0x20000u
#define PTIMER_STATUS_CTRL_SERR_INTEN_SHIFT 17u
#define PTIMER_STATUS_CTRL_SERR_INTEN_WIDTH 1u
#define PTIMER_STATUS_CTRL_SERR_INTEN(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_SERR_INTEN_SHIFT))&PTIMER_STATUS_CTRL_SERR_INTEN_MASK)
#define PTIMER_STATUS_CTRL_SWTRG_MASK 0x10000u
#define PTIMER_STATUS_CTRL_SWTRG_SHIFT 16u
#define PTIMER_STATUS_CTRL_SWTRG_WIDTH 1u
#define PTIMER_STATUS_CTRL_SWTRG(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_SWTRG_SHIFT))&PTIMER_STATUS_CTRL_SWTRG_MASK)
#define PTIMER_STATUS_CTRL_DMAEN_MASK 0x8000u
#define PTIMER_STATUS_CTRL_DMAEN_SHIFT 15u
#define PTIMER_STATUS_CTRL_DMAEN_WIDTH 1u
#define PTIMER_STATUS_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_DMAEN_SHIFT))&PTIMER_STATUS_CTRL_DMAEN_MASK)
#define PTIMER_STATUS_CTRL_PRESCALER_MASK 0x7000u
#define PTIMER_STATUS_CTRL_PRESCALER_SHIFT 12u
#define PTIMER_STATUS_CTRL_PRESCALER_WIDTH 3u
#define PTIMER_STATUS_CTRL_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_PRESCALER_SHIFT))&PTIMER_STATUS_CTRL_PRESCALER_MASK)
#define PTIMER_STATUS_CTRL_TRGSEL_MASK 0xF00u
#define PTIMER_STATUS_CTRL_TRGSEL_SHIFT 8u
#define PTIMER_STATUS_CTRL_TRGSEL_WIDTH 4u
#define PTIMER_STATUS_CTRL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_TRGSEL_SHIFT))&PTIMER_STATUS_CTRL_TRGSEL_MASK)
#define PTIMER_STATUS_CTRL_ENABLE_MASK 0x80u
#define PTIMER_STATUS_CTRL_ENABLE_SHIFT 7u
#define PTIMER_STATUS_CTRL_ENABLE_WIDTH 1u
#define PTIMER_STATUS_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_ENABLE_SHIFT))&PTIMER_STATUS_CTRL_ENABLE_MASK)
#define PTIMER_STATUS_CTRL_INTFLAG_MASK 0x40u
#define PTIMER_STATUS_CTRL_INTFLAG_SHIFT 6u
#define PTIMER_STATUS_CTRL_INTFLAG_WIDTH 1u
#define PTIMER_STATUS_CTRL_INTFLAG(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_INTFLAG_SHIFT))&PTIMER_STATUS_CTRL_INTFLAG_MASK)
#define PTIMER_STATUS_CTRL_INTEN_MASK 0x20u
#define PTIMER_STATUS_CTRL_INTEN_SHIFT 5u
#define PTIMER_STATUS_CTRL_INTEN_WIDTH 1u
#define PTIMER_STATUS_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_INTEN_SHIFT))&PTIMER_STATUS_CTRL_INTEN_MASK)
#define PTIMER_STATUS_CTRL_MULT_MASK 0xCu
#define PTIMER_STATUS_CTRL_MULT_SHIFT 2u
#define PTIMER_STATUS_CTRL_MULT_WIDTH 2u
#define PTIMER_STATUS_CTRL_MULT(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_MULT_SHIFT))&PTIMER_STATUS_CTRL_MULT_MASK)
#define PTIMER_STATUS_CTRL_CONT_MASK 0x2u
#define PTIMER_STATUS_CTRL_CONT_SHIFT 1u
#define PTIMER_STATUS_CTRL_CONT_WIDTH 1u
#define PTIMER_STATUS_CTRL_CONT(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_CONT_SHIFT))&PTIMER_STATUS_CTRL_CONT_MASK)
#define PTIMER_STATUS_CTRL_LDOK_MASK 0x1u
#define PTIMER_STATUS_CTRL_LDOK_SHIFT 0u
#define PTIMER_STATUS_CTRL_LDOK_WIDTH 1u
#define PTIMER_STATUS_CTRL_LDOK(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CTRL_LDOK_SHIFT))&PTIMER_STATUS_CTRL_LDOK_MASK)
/* STATUS_CTRL Reg Mask */
#define PTIMER_STATUS_CTRL_MASK 0x000FFFEFu
/* MAX_CNT Bit Fields */
#define PTIMER_MAX_CNT_MAX_CNT_MASK 0xFFFFu
#define PTIMER_MAX_CNT_MAX_CNT_SHIFT 0u
#define PTIMER_MAX_CNT_MAX_CNT_WIDTH 16u
#define PTIMER_MAX_CNT_MAX_CNT(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_MAX_CNT_MAX_CNT_SHIFT))&PTIMER_MAX_CNT_MAX_CNT_MASK)
/* MAX_CNT Reg Mask */
#define PTIMER_MAX_CNT_MASK 0x0000FFFFu
/* CNT Bit Fields */
#define PTIMER_CNT_CNT_MASK 0xFFFFu
#define PTIMER_CNT_CNT_SHIFT 0u
#define PTIMER_CNT_CNT_WIDTH 16u
#define PTIMER_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_CNT_CNT_SHIFT))&PTIMER_CNT_CNT_MASK)
/* CNT Reg Mask */
#define PTIMER_CNT_MASK 0x0000FFFFu
/* INT_DLY Bit Fields */
#define PTIMER_INT_DLY_INT_DLY_MASK 0xFFFFu
#define PTIMER_INT_DLY_INT_DLY_SHIFT 0u
#define PTIMER_INT_DLY_INT_DLY_WIDTH 16u
#define PTIMER_INT_DLY_INT_DLY(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_INT_DLY_INT_DLY_SHIFT))&PTIMER_INT_DLY_INT_DLY_MASK)
/* INT_DLY Reg Mask */
#define PTIMER_INT_DLY_MASK 0x0000FFFFu
/* CTRL_CH Bit Fields */
#define PTIMER_CTRL_CH_BTB_MASK 0xFF0000u
#define PTIMER_CTRL_CH_BTB_SHIFT 16u
#define PTIMER_CTRL_CH_BTB_WIDTH 8u
#define PTIMER_CTRL_CH_BTB(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_CTRL_CH_BTB_SHIFT))&PTIMER_CTRL_CH_BTB_MASK)
#define PTIMER_CTRL_CH_PTOS_MASK 0xFF00u
#define PTIMER_CTRL_CH_PTOS_SHIFT 8u
#define PTIMER_CTRL_CH_PTOS_WIDTH 8u
#define PTIMER_CTRL_CH_PTOS(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_CTRL_CH_PTOS_SHIFT))&PTIMER_CTRL_CH_PTOS_MASK)
#define PTIMER_CTRL_CH_PTEN_MASK 0xFFu
#define PTIMER_CTRL_CH_PTEN_SHIFT 0u
#define PTIMER_CTRL_CH_PTEN_WIDTH 8u
#define PTIMER_CTRL_CH_PTEN(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_CTRL_CH_PTEN_SHIFT))&PTIMER_CTRL_CH_PTEN_MASK)
/* CTRL_CH Reg Mask */
#define PTIMER_CTRL_CH_MASK 0x00FFFFFFu
/* STATUS_CH Bit Fields */
#define PTIMER_STATUS_CH_CHN_FLAG_MASK 0xFF0000u
#define PTIMER_STATUS_CH_CHN_FLAG_SHIFT 16u
#define PTIMER_STATUS_CH_CHN_FLAG_WIDTH 8u
#define PTIMER_STATUS_CH_CHN_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CH_CHN_FLAG_SHIFT))&PTIMER_STATUS_CH_CHN_FLAG_MASK)
#define PTIMER_STATUS_CH_SERR_FLAG_MASK 0xFFu
#define PTIMER_STATUS_CH_SERR_FLAG_SHIFT 0u
#define PTIMER_STATUS_CH_SERR_FLAG_WIDTH 8u
#define PTIMER_STATUS_CH_SERR_FLAG(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_STATUS_CH_SERR_FLAG_SHIFT))&PTIMER_STATUS_CH_SERR_FLAG_MASK)
/* STATUS_CH Reg Mask */
#define PTIMER_STATUS_CH_MASK 0x00FF00FFu
/* DLYn_CHm Bit Fields */
#define PTIMER_DLY_CH_CHNDLY_MASK 0xFFFFu
#define PTIMER_DLY_CH_CHNDLY_SHIFT 0u
#define PTIMER_DLY_CH_CHNDLY_WIDTH 16u
#define PTIMER_DLY_CH_CHNDLY(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_DLY_CH_CHNDLY_SHIFT))&PTIMER_DLY_CH_CHNDLY_MASK)
/* DLYn_CHm Reg Mask */
#define PTIMER_DLY_CH_MASK 0x0000FFFFu
/* POEN Bit Fields */
#define PTIMER_POEN_POEN_MASK 0x1u
#define PTIMER_POEN_POEN_SHIFT 0u
#define PTIMER_POEN_POEN_WIDTH 1u
#define PTIMER_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_POEN_POEN_SHIFT))&PTIMER_POEN_POEN_MASK)
/* POEN Reg Mask */
#define PTIMER_POEN_MASK 0x00000001u
/* PODLY Bit Fields */
#define PTIMER_PODLY_DLY1_MASK 0xFFFF0000u
#define PTIMER_PODLY_DLY1_SHIFT 16u
#define PTIMER_PODLY_DLY1_WIDTH 16u
#define PTIMER_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_PODLY_DLY1_SHIFT))&PTIMER_PODLY_DLY1_MASK)
#define PTIMER_PODLY_DLY2_MASK 0xFFFFu
#define PTIMER_PODLY_DLY2_SHIFT 0u
#define PTIMER_PODLY_DLY2_WIDTH 16u
#define PTIMER_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PTIMER_PODLY_DLY2_SHIFT))&PTIMER_PODLY_DLY2_MASK)
/* PODLY Reg Mask */
#define PTIMER_PODLY_MASK 0xFFFFFFFFu
/*!
* @}
*/ /* end of group PTIMER_Register_Masks */
/*!
* @}
*/ /* end of group PTIMER_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7240_rgm_regs.h Normal file
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#ifndef _FC7240_RGM_NU_Tztufn9_REGS_H_
#define _FC7240_RGM_NU_Tztufn9_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- RGM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RGM_Peripheral_Access_Layer RGM Peripheral Access Layer
* @{
*/
/** RGM - Size of Registers Arrays */
/** RGM - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[8];
__IO uint32_t SRS ; /* System Reset Status Register, offset: 0x8 */
__IO uint32_t RSTFLT ; /* Reset Filter Control Register, offset: 0xC */
uint8_t RESERVED_1[8];
__IO uint32_t SSRS ; /* Sticky System Reset Status Register, offset: 0x18 */
__IO uint32_t SRIE ; /* System Reset Interrupt Enable Register, offset: 0x1C */
uint8_t RESERVED_2[224];
__IO uint32_t C0_CFG ; /* CPU0 Reset Configuration Register, offset: 0x100 */
__IO uint32_t C0_RST ; /* CPU0 Reset Register, offset: 0x104 */
__IO uint32_t C0_SRS ; /* CPU0 System Reset Status Register, offset: 0x108 */
uint8_t RESERVED_3[8];
__IO uint32_t C0_SSRS ; /* CPU0 Sticky System Reset Status Register, offset: 0x114 */
} RGM_Type, *RGM_MemMapPtr;
/** Number of instances of the RGM module. */
#define RGM_INSTANCE_COUNT (1u)
/* RGM - Peripheral instance base addresses */
/** Peripheral RGM base address */
#define RGM_BASE (0x40046000u)
/** Peripheral RGM base pointer */
#define RGM ((RGM_Type *)RGM_BASE)
/** Array initializer of RGM peripheral base addresses */
#define RGM_BASE_ADDRS {RGM_BASE}
/** Array initializer of RGM peripheral base pointers */
#define RGM_BASE_PTRS {RGM}
/* ----------------------------------------------------------------------------
-- RGM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RGM_Register_Masks RGM Register Masks
* @{
*/
/* SRS Bit Fields */
#define RGM_SRS_SYSRST_TOUT_MASK 0x80000000u
#define RGM_SRS_SYSRST_TOUT_SHIFT 31u
#define RGM_SRS_SYSRST_TOUT_WIDTH 1u
#define RGM_SRS_SYSRST_TOUT(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_SYSRST_TOUT_SHIFT))&RGM_SRS_SYSRST_TOUT_MASK)
#define RGM_SRS_PINRST_TOUT_MASK 0x40000000u
#define RGM_SRS_PINRST_TOUT_SHIFT 30u
#define RGM_SRS_PINRST_TOUT_WIDTH 1u
#define RGM_SRS_PINRST_TOUT(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_PINRST_TOUT_SHIFT))&RGM_SRS_PINRST_TOUT_MASK)
#define RGM_SRS_FSM_ERR_MASK 0x20000000u
#define RGM_SRS_FSM_ERR_SHIFT 29u
#define RGM_SRS_FSM_ERR_WIDTH 1u
#define RGM_SRS_FSM_ERR(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_FSM_ERR_SHIFT))&RGM_SRS_FSM_ERR_MASK)
#define RGM_SRS_LBIST_MASK 0x8000u
#define RGM_SRS_LBIST_SHIFT 15u
#define RGM_SRS_LBIST_WIDTH 1u
#define RGM_SRS_LBIST(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_LBIST_SHIFT))&RGM_SRS_LBIST_MASK)
#define RGM_SRS_CMU_MASK 0x4000u
#define RGM_SRS_CMU_SHIFT 14u
#define RGM_SRS_CMU_WIDTH 1u
#define RGM_SRS_CMU(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_CMU_SHIFT))&RGM_SRS_CMU_MASK)
#define RGM_SRS_SACKERR_MASK 0x2000u
#define RGM_SRS_SACKERR_SHIFT 13u
#define RGM_SRS_SACKERR_WIDTH 1u
#define RGM_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_SACKERR_SHIFT))&RGM_SRS_SACKERR_MASK)
#define RGM_SRS_WDOG1_MASK 0x1000u
#define RGM_SRS_WDOG1_SHIFT 12u
#define RGM_SRS_WDOG1_WIDTH 1u
#define RGM_SRS_WDOG1(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_WDOG1_SHIFT))&RGM_SRS_WDOG1_MASK)
#define RGM_SRS_SYSAP_MASK 0x800u
#define RGM_SRS_SYSAP_SHIFT 11u
#define RGM_SRS_SYSAP_WIDTH 1u
#define RGM_SRS_SYSAP(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_SYSAP_SHIFT))&RGM_SRS_SYSAP_MASK)
#define RGM_SRS_JTAG_MASK 0x100u
#define RGM_SRS_JTAG_SHIFT 8u
#define RGM_SRS_JTAG_WIDTH 1u
#define RGM_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_JTAG_SHIFT))&RGM_SRS_JTAG_MASK)
#define RGM_SRS_POR_MASK 0x80u
#define RGM_SRS_POR_SHIFT 7u
#define RGM_SRS_POR_WIDTH 1u
#define RGM_SRS_POR(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_POR_SHIFT))&RGM_SRS_POR_MASK)
#define RGM_SRS_PIN_MASK 0x40u
#define RGM_SRS_PIN_SHIFT 6u
#define RGM_SRS_PIN_WIDTH 1u
#define RGM_SRS_PIN(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_PIN_SHIFT))&RGM_SRS_PIN_MASK)
#define RGM_SRS_HSM_WDOG_MASK 0x20u
#define RGM_SRS_HSM_WDOG_SHIFT 5u
#define RGM_SRS_HSM_WDOG_WIDTH 1u
#define RGM_SRS_HSM_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_HSM_WDOG_SHIFT))&RGM_SRS_HSM_WDOG_MASK)
#define RGM_SRS_FCSMU_MASK 0x10u
#define RGM_SRS_FCSMU_SHIFT 4u
#define RGM_SRS_FCSMU_WIDTH 1u
#define RGM_SRS_FCSMU(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_FCSMU_SHIFT))&RGM_SRS_FCSMU_MASK)
#define RGM_SRS_CLKERR0_MASK 0x8u
#define RGM_SRS_CLKERR0_SHIFT 3u
#define RGM_SRS_CLKERR0_WIDTH 1u
#define RGM_SRS_CLKERR0(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_CLKERR0_SHIFT))&RGM_SRS_CLKERR0_MASK)
#define RGM_SRS_CLKERR1_MASK 0x4u
#define RGM_SRS_CLKERR1_SHIFT 2u
#define RGM_SRS_CLKERR1_WIDTH 1u
#define RGM_SRS_CLKERR1(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_CLKERR1_SHIFT))&RGM_SRS_CLKERR1_MASK)
#define RGM_SRS_LVR_MASK 0x2u
#define RGM_SRS_LVR_SHIFT 1u
#define RGM_SRS_LVR_WIDTH 1u
#define RGM_SRS_LVR(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_LVR_SHIFT))&RGM_SRS_LVR_MASK)
#define RGM_SRS_WAKEUP_MASK 0x1u
#define RGM_SRS_WAKEUP_SHIFT 0u
#define RGM_SRS_WAKEUP_WIDTH 1u
#define RGM_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRS_WAKEUP_SHIFT))&RGM_SRS_WAKEUP_MASK)
/* SRS Reg Mask */
#define RGM_SRS_MASK 0xE000F9FFu
/* RSTFLT Bit Fields */
#define RGM_RSTFLT_RSTFLT_BUSW_MASK 0x1F00u
#define RGM_RSTFLT_RSTFLT_BUSW_SHIFT 8u
#define RGM_RSTFLT_RSTFLT_BUSW_WIDTH 5u
#define RGM_RSTFLT_RSTFLT_BUSW(x) (((uint32_t)(((uint32_t)(x))<<RGM_RSTFLT_RSTFLT_BUSW_SHIFT))&RGM_RSTFLT_RSTFLT_BUSW_MASK)
#define RGM_RSTFLT_RSTFLT_AON_LP_MASK 0x4u
#define RGM_RSTFLT_RSTFLT_AON_LP_SHIFT 2u
#define RGM_RSTFLT_RSTFLT_AON_LP_WIDTH 1u
#define RGM_RSTFLT_RSTFLT_AON_LP(x) (((uint32_t)(((uint32_t)(x))<<RGM_RSTFLT_RSTFLT_AON_LP_SHIFT))&RGM_RSTFLT_RSTFLT_AON_LP_MASK)
#define RGM_RSTFLT_RSTFLT_AON_MASK 0x2u
#define RGM_RSTFLT_RSTFLT_AON_SHIFT 1u
#define RGM_RSTFLT_RSTFLT_AON_WIDTH 1u
#define RGM_RSTFLT_RSTFLT_AON(x) (((uint32_t)(((uint32_t)(x))<<RGM_RSTFLT_RSTFLT_AON_SHIFT))&RGM_RSTFLT_RSTFLT_AON_MASK)
#define RGM_RSTFLT_RSTFLT_BUS_MASK 0x1u
#define RGM_RSTFLT_RSTFLT_BUS_SHIFT 0u
#define RGM_RSTFLT_RSTFLT_BUS_WIDTH 1u
#define RGM_RSTFLT_RSTFLT_BUS(x) (((uint32_t)(((uint32_t)(x))<<RGM_RSTFLT_RSTFLT_BUS_SHIFT))&RGM_RSTFLT_RSTFLT_BUS_MASK)
/* RSTFLT Reg Mask */
#define RGM_RSTFLT_MASK 0x00001F07u
/* SSRS Bit Fields */
#define RGM_SSRS_SYSRST_TOUT_MASK 0x80000000u
#define RGM_SSRS_SYSRST_TOUT_SHIFT 31u
#define RGM_SSRS_SYSRST_TOUT_WIDTH 1u
#define RGM_SSRS_SYSRST_TOUT(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_SYSRST_TOUT_SHIFT))&RGM_SSRS_SYSRST_TOUT_MASK)
#define RGM_SSRS_PINRST_TOUT_MASK 0x40000000u
#define RGM_SSRS_PINRST_TOUT_SHIFT 30u
#define RGM_SSRS_PINRST_TOUT_WIDTH 1u
#define RGM_SSRS_PINRST_TOUT(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_PINRST_TOUT_SHIFT))&RGM_SSRS_PINRST_TOUT_MASK)
#define RGM_SSRS_FSM_ERR_MASK 0x20000000u
#define RGM_SSRS_FSM_ERR_SHIFT 29u
#define RGM_SSRS_FSM_ERR_WIDTH 1u
#define RGM_SSRS_FSM_ERR(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_FSM_ERR_SHIFT))&RGM_SSRS_FSM_ERR_MASK)
#define RGM_SSRS_LBIST_MASK 0x8000u
#define RGM_SSRS_LBIST_SHIFT 15u
#define RGM_SSRS_LBIST_WIDTH 1u
#define RGM_SSRS_LBIST(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_LBIST_SHIFT))&RGM_SSRS_LBIST_MASK)
#define RGM_SSRS_CMU_MASK 0x4000u
#define RGM_SSRS_CMU_SHIFT 14u
#define RGM_SSRS_CMU_WIDTH 1u
#define RGM_SSRS_CMU(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_CMU_SHIFT))&RGM_SSRS_CMU_MASK)
#define RGM_SSRS_SACKERR_ST_MASK 0x2000u
#define RGM_SSRS_SACKERR_ST_SHIFT 13u
#define RGM_SSRS_SACKERR_ST_WIDTH 1u
#define RGM_SSRS_SACKERR_ST(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_SACKERR_ST_SHIFT))&RGM_SSRS_SACKERR_ST_MASK)
#define RGM_SSRS_WDOG1_MASK 0x1000u
#define RGM_SSRS_WDOG1_SHIFT 12u
#define RGM_SSRS_WDOG1_WIDTH 1u
#define RGM_SSRS_WDOG1(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_WDOG1_SHIFT))&RGM_SSRS_WDOG1_MASK)
#define RGM_SSRS_SYSAP_ST_MASK 0x800u
#define RGM_SSRS_SYSAP_ST_SHIFT 11u
#define RGM_SSRS_SYSAP_ST_WIDTH 1u
#define RGM_SSRS_SYSAP_ST(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_SYSAP_ST_SHIFT))&RGM_SSRS_SYSAP_ST_MASK)
#define RGM_SSRS_JTAG_ST_MASK 0x100u
#define RGM_SSRS_JTAG_ST_SHIFT 8u
#define RGM_SSRS_JTAG_ST_WIDTH 1u
#define RGM_SSRS_JTAG_ST(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_JTAG_ST_SHIFT))&RGM_SSRS_JTAG_ST_MASK)
#define RGM_SSRS_POR_ST_MASK 0x80u
#define RGM_SSRS_POR_ST_SHIFT 7u
#define RGM_SSRS_POR_ST_WIDTH 1u
#define RGM_SSRS_POR_ST(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_POR_ST_SHIFT))&RGM_SSRS_POR_ST_MASK)
#define RGM_SSRS_PIN_ST_MASK 0x40u
#define RGM_SSRS_PIN_ST_SHIFT 6u
#define RGM_SSRS_PIN_ST_WIDTH 1u
#define RGM_SSRS_PIN_ST(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_PIN_ST_SHIFT))&RGM_SSRS_PIN_ST_MASK)
#define RGM_SSRS_HSMWDOG_ST_MASK 0x20u
#define RGM_SSRS_HSMWDOG_ST_SHIFT 5u
#define RGM_SSRS_HSMWDOG_ST_WIDTH 1u
#define RGM_SSRS_HSMWDOG_ST(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_HSMWDOG_ST_SHIFT))&RGM_SSRS_HSMWDOG_ST_MASK)
#define RGM_SSRS_FCSMU_ST_MASK 0x10u
#define RGM_SSRS_FCSMU_ST_SHIFT 4u
#define RGM_SSRS_FCSMU_ST_WIDTH 1u
#define RGM_SSRS_FCSMU_ST(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_FCSMU_ST_SHIFT))&RGM_SSRS_FCSMU_ST_MASK)
#define RGM_SSRS_CLKERR0_ST_MASK 0x8u
#define RGM_SSRS_CLKERR0_ST_SHIFT 3u
#define RGM_SSRS_CLKERR0_ST_WIDTH 1u
#define RGM_SSRS_CLKERR0_ST(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_CLKERR0_ST_SHIFT))&RGM_SSRS_CLKERR0_ST_MASK)
#define RGM_SSRS_CLKERR1_ST_MASK 0x4u
#define RGM_SSRS_CLKERR1_ST_SHIFT 2u
#define RGM_SSRS_CLKERR1_ST_WIDTH 1u
#define RGM_SSRS_CLKERR1_ST(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_CLKERR1_ST_SHIFT))&RGM_SSRS_CLKERR1_ST_MASK)
#define RGM_SSRS_LVR_MASK 0x2u
#define RGM_SSRS_LVR_SHIFT 1u
#define RGM_SSRS_LVR_WIDTH 1u
#define RGM_SSRS_LVR(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_LVR_SHIFT))&RGM_SSRS_LVR_MASK)
#define RGM_SSRS_WAKEUP_ST_MASK 0x1u
#define RGM_SSRS_WAKEUP_ST_SHIFT 0u
#define RGM_SSRS_WAKEUP_ST_WIDTH 1u
#define RGM_SSRS_WAKEUP_ST(x) (((uint32_t)(((uint32_t)(x))<<RGM_SSRS_WAKEUP_ST_SHIFT))&RGM_SSRS_WAKEUP_ST_MASK)
/* SSRS Reg Mask */
#define RGM_SSRS_MASK 0xE000F9FFu
/* SRIE Bit Fields */
#define RGM_SRIE_SACKERR_RIE_MASK 0x2000u
#define RGM_SRIE_SACKERR_RIE_SHIFT 13u
#define RGM_SRIE_SACKERR_RIE_WIDTH 1u
#define RGM_SRIE_SACKERR_RIE(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRIE_SACKERR_RIE_SHIFT))&RGM_SRIE_SACKERR_RIE_MASK)
#define RGM_SRIE_WDOG1_RIE_MASK 0x1000u
#define RGM_SRIE_WDOG1_RIE_SHIFT 12u
#define RGM_SRIE_WDOG1_RIE_WIDTH 1u
#define RGM_SRIE_WDOG1_RIE(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRIE_WDOG1_RIE_SHIFT))&RGM_SRIE_WDOG1_RIE_MASK)
#define RGM_SRIE_SYSAP_RIE_MASK 0x800u
#define RGM_SRIE_SYSAP_RIE_SHIFT 11u
#define RGM_SRIE_SYSAP_RIE_WIDTH 1u
#define RGM_SRIE_SYSAP_RIE(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRIE_SYSAP_RIE_SHIFT))&RGM_SRIE_SYSAP_RIE_MASK)
#define RGM_SRIE_SW_RIE_MASK 0x400u
#define RGM_SRIE_SW_RIE_SHIFT 10u
#define RGM_SRIE_SW_RIE_WIDTH 1u
#define RGM_SRIE_SW_RIE(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRIE_SW_RIE_SHIFT))&RGM_SRIE_SW_RIE_MASK)
#define RGM_SRIE_CPULOC_RIE_MASK 0x200u
#define RGM_SRIE_CPULOC_RIE_SHIFT 9u
#define RGM_SRIE_CPULOC_RIE_WIDTH 1u
#define RGM_SRIE_CPULOC_RIE(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRIE_CPULOC_RIE_SHIFT))&RGM_SRIE_CPULOC_RIE_MASK)
#define RGM_SRIE_JTAG_RIE_MASK 0x100u
#define RGM_SRIE_JTAG_RIE_SHIFT 8u
#define RGM_SRIE_JTAG_RIE_WIDTH 1u
#define RGM_SRIE_JTAG_RIE(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRIE_JTAG_RIE_SHIFT))&RGM_SRIE_JTAG_RIE_MASK)
#define RGM_SRIE_GLOBAL_RIE_MASK 0x80u
#define RGM_SRIE_GLOBAL_RIE_SHIFT 7u
#define RGM_SRIE_GLOBAL_RIE_WIDTH 1u
#define RGM_SRIE_GLOBAL_RIE(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRIE_GLOBAL_RIE_SHIFT))&RGM_SRIE_GLOBAL_RIE_MASK)
#define RGM_SRIE_PIN_RIE_MASK 0x40u
#define RGM_SRIE_PIN_RIE_SHIFT 6u
#define RGM_SRIE_PIN_RIE_WIDTH 1u
#define RGM_SRIE_PIN_RIE(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRIE_PIN_RIE_SHIFT))&RGM_SRIE_PIN_RIE_MASK)
#define RGM_SRIE_WDG_RIE_MASK 0x20u
#define RGM_SRIE_WDG_RIE_SHIFT 5u
#define RGM_SRIE_WDG_RIE_WIDTH 1u
#define RGM_SRIE_WDG_RIE(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRIE_WDG_RIE_SHIFT))&RGM_SRIE_WDG_RIE_MASK)
#define RGM_SRIE_CLKERR0_RIE_MASK 0x8u
#define RGM_SRIE_CLKERR0_RIE_SHIFT 3u
#define RGM_SRIE_CLKERR0_RIE_WIDTH 1u
#define RGM_SRIE_CLKERR0_RIE(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRIE_CLKERR0_RIE_SHIFT))&RGM_SRIE_CLKERR0_RIE_MASK)
#define RGM_SRIE_DELAY_MASK 0x3u
#define RGM_SRIE_DELAY_SHIFT 0u
#define RGM_SRIE_DELAY_WIDTH 2u
#define RGM_SRIE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<RGM_SRIE_DELAY_SHIFT))&RGM_SRIE_DELAY_MASK)
/* SRIE Reg Mask */
#define RGM_SRIE_MASK 0x00003FEBu
/* C0_CFG Bit Fields */
#define RGM_C0_CFG_C0_SWRST_EN_MASK 0x100000u
#define RGM_C0_CFG_C0_SWRST_EN_SHIFT 20u
#define RGM_C0_CFG_C0_SWRST_EN_WIDTH 1u
#define RGM_C0_CFG_C0_SWRST_EN(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_CFG_C0_SWRST_EN_SHIFT))&RGM_C0_CFG_C0_SWRST_EN_MASK)
#define RGM_C0_CFG_C0_INTM_EN_MASK 0x80000u
#define RGM_C0_CFG_C0_INTM_EN_SHIFT 19u
#define RGM_C0_CFG_C0_INTM_EN_WIDTH 1u
#define RGM_C0_CFG_C0_INTM_EN(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_CFG_C0_INTM_EN_SHIFT))&RGM_C0_CFG_C0_INTM_EN_MASK)
#define RGM_C0_CFG_C0_WDOG_EN_MASK 0x40000u
#define RGM_C0_CFG_C0_WDOG_EN_SHIFT 18u
#define RGM_C0_CFG_C0_WDOG_EN_WIDTH 1u
#define RGM_C0_CFG_C0_WDOG_EN(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_CFG_C0_WDOG_EN_SHIFT))&RGM_C0_CFG_C0_WDOG_EN_MASK)
#define RGM_C0_CFG_C0_SYSRST_EN_MASK 0x20000u
#define RGM_C0_CFG_C0_SYSRST_EN_SHIFT 17u
#define RGM_C0_CFG_C0_SYSRST_EN_WIDTH 1u
#define RGM_C0_CFG_C0_SYSRST_EN(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_CFG_C0_SYSRST_EN_SHIFT))&RGM_C0_CFG_C0_SYSRST_EN_MASK)
#define RGM_C0_CFG_C0_LOCKUP_EN_MASK 0x10000u
#define RGM_C0_CFG_C0_LOCKUP_EN_SHIFT 16u
#define RGM_C0_CFG_C0_LOCKUP_EN_WIDTH 1u
#define RGM_C0_CFG_C0_LOCKUP_EN(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_CFG_C0_LOCKUP_EN_SHIFT))&RGM_C0_CFG_C0_LOCKUP_EN_MASK)
#define RGM_C0_CFG_C0_SWRST_IE_MASK 0x10u
#define RGM_C0_CFG_C0_SWRST_IE_SHIFT 4u
#define RGM_C0_CFG_C0_SWRST_IE_WIDTH 1u
#define RGM_C0_CFG_C0_SWRST_IE(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_CFG_C0_SWRST_IE_SHIFT))&RGM_C0_CFG_C0_SWRST_IE_MASK)
#define RGM_C0_CFG_C0_INTM_IE_MASK 0x8u
#define RGM_C0_CFG_C0_INTM_IE_SHIFT 3u
#define RGM_C0_CFG_C0_INTM_IE_WIDTH 1u
#define RGM_C0_CFG_C0_INTM_IE(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_CFG_C0_INTM_IE_SHIFT))&RGM_C0_CFG_C0_INTM_IE_MASK)
#define RGM_C0_CFG_C0_WDOG_IE_MASK 0x4u
#define RGM_C0_CFG_C0_WDOG_IE_SHIFT 2u
#define RGM_C0_CFG_C0_WDOG_IE_WIDTH 1u
#define RGM_C0_CFG_C0_WDOG_IE(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_CFG_C0_WDOG_IE_SHIFT))&RGM_C0_CFG_C0_WDOG_IE_MASK)
#define RGM_C0_CFG_C0_SYSRST_IE_MASK 0x2u
#define RGM_C0_CFG_C0_SYSRST_IE_SHIFT 1u
#define RGM_C0_CFG_C0_SYSRST_IE_WIDTH 1u
#define RGM_C0_CFG_C0_SYSRST_IE(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_CFG_C0_SYSRST_IE_SHIFT))&RGM_C0_CFG_C0_SYSRST_IE_MASK)
#define RGM_C0_CFG_C0_LOCKUP_IE_MASK 0x1u
#define RGM_C0_CFG_C0_LOCKUP_IE_SHIFT 0u
#define RGM_C0_CFG_C0_LOCKUP_IE_WIDTH 1u
#define RGM_C0_CFG_C0_LOCKUP_IE(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_CFG_C0_LOCKUP_IE_SHIFT))&RGM_C0_CFG_C0_LOCKUP_IE_MASK)
/* C0_CFG Reg Mask */
#define RGM_C0_CFG_MASK 0x001F001Fu
/* C0_RST Bit Fields */
#define RGM_C0_RST_C0_OUT_OF_RST_MASK 0x2u
#define RGM_C0_RST_C0_OUT_OF_RST_SHIFT 1u
#define RGM_C0_RST_C0_OUT_OF_RST_WIDTH 1u
#define RGM_C0_RST_C0_OUT_OF_RST(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_RST_C0_OUT_OF_RST_SHIFT))&RGM_C0_RST_C0_OUT_OF_RST_MASK)
#define RGM_C0_RST_C0_SWRST_MASK 0x1u
#define RGM_C0_RST_C0_SWRST_SHIFT 0u
#define RGM_C0_RST_C0_SWRST_WIDTH 1u
#define RGM_C0_RST_C0_SWRST(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_RST_C0_SWRST_SHIFT))&RGM_C0_RST_C0_SWRST_MASK)
/* C0_RST Reg Mask */
#define RGM_C0_RST_MASK 0x00000003u
/* C0_SRS Bit Fields */
#define RGM_C0_SRS_SYSRST_TOUT_MASK 0x80000000u
#define RGM_C0_SRS_SYSRST_TOUT_SHIFT 31u
#define RGM_C0_SRS_SYSRST_TOUT_WIDTH 1u
#define RGM_C0_SRS_SYSRST_TOUT(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SRS_SYSRST_TOUT_SHIFT))&RGM_C0_SRS_SYSRST_TOUT_MASK)
#define RGM_C0_SRS_PINRST_TOUT_MASK 0x40000000u
#define RGM_C0_SRS_PINRST_TOUT_SHIFT 30u
#define RGM_C0_SRS_PINRST_TOUT_WIDTH 1u
#define RGM_C0_SRS_PINRST_TOUT(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SRS_PINRST_TOUT_SHIFT))&RGM_C0_SRS_PINRST_TOUT_MASK)
#define RGM_C0_SRS_FSM_ERR_MASK 0x20000000u
#define RGM_C0_SRS_FSM_ERR_SHIFT 29u
#define RGM_C0_SRS_FSM_ERR_WIDTH 1u
#define RGM_C0_SRS_FSM_ERR(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SRS_FSM_ERR_SHIFT))&RGM_C0_SRS_FSM_ERR_MASK)
#define RGM_C0_SRS_C0_SWRST_MASK 0x100000u
#define RGM_C0_SRS_C0_SWRST_SHIFT 20u
#define RGM_C0_SRS_C0_SWRST_WIDTH 1u
#define RGM_C0_SRS_C0_SWRST(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SRS_C0_SWRST_SHIFT))&RGM_C0_SRS_C0_SWRST_MASK)
#define RGM_C0_SRS_C0_INTM_MASK 0x80000u
#define RGM_C0_SRS_C0_INTM_SHIFT 19u
#define RGM_C0_SRS_C0_INTM_WIDTH 1u
#define RGM_C0_SRS_C0_INTM(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SRS_C0_INTM_SHIFT))&RGM_C0_SRS_C0_INTM_MASK)
#define RGM_C0_SRS_C0_WDOG_MASK 0x40000u
#define RGM_C0_SRS_C0_WDOG_SHIFT 18u
#define RGM_C0_SRS_C0_WDOG_WIDTH 1u
#define RGM_C0_SRS_C0_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SRS_C0_WDOG_SHIFT))&RGM_C0_SRS_C0_WDOG_MASK)
#define RGM_C0_SRS_C0_SYSRST_MASK 0x20000u
#define RGM_C0_SRS_C0_SYSRST_SHIFT 17u
#define RGM_C0_SRS_C0_SYSRST_WIDTH 1u
#define RGM_C0_SRS_C0_SYSRST(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SRS_C0_SYSRST_SHIFT))&RGM_C0_SRS_C0_SYSRST_MASK)
#define RGM_C0_SRS_C0_LOCKUP_MASK 0x10000u
#define RGM_C0_SRS_C0_LOCKUP_SHIFT 16u
#define RGM_C0_SRS_C0_LOCKUP_WIDTH 1u
#define RGM_C0_SRS_C0_LOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SRS_C0_LOCKUP_SHIFT))&RGM_C0_SRS_C0_LOCKUP_MASK)
#define RGM_C0_SRS_C0_SRS_MASK 0xFFFFu
#define RGM_C0_SRS_C0_SRS_SHIFT 0u
#define RGM_C0_SRS_C0_SRS_WIDTH 16u
#define RGM_C0_SRS_C0_SRS(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SRS_C0_SRS_SHIFT))&RGM_C0_SRS_C0_SRS_MASK)
/* C0_SRS Reg Mask */
#define RGM_C0_SRS_MASK 0xE01FFFFFu
/* C0_SSRS Bit Fields */
#define RGM_C0_SSRS_SYSRST_TOUT_MASK 0x80000000u
#define RGM_C0_SSRS_SYSRST_TOUT_SHIFT 31u
#define RGM_C0_SSRS_SYSRST_TOUT_WIDTH 1u
#define RGM_C0_SSRS_SYSRST_TOUT(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SSRS_SYSRST_TOUT_SHIFT))&RGM_C0_SSRS_SYSRST_TOUT_MASK)
#define RGM_C0_SSRS_PINRST_TOUT_MASK 0x40000000u
#define RGM_C0_SSRS_PINRST_TOUT_SHIFT 30u
#define RGM_C0_SSRS_PINRST_TOUT_WIDTH 1u
#define RGM_C0_SSRS_PINRST_TOUT(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SSRS_PINRST_TOUT_SHIFT))&RGM_C0_SSRS_PINRST_TOUT_MASK)
#define RGM_C0_SSRS_FSM_ERR_MASK 0x20000000u
#define RGM_C0_SSRS_FSM_ERR_SHIFT 29u
#define RGM_C0_SSRS_FSM_ERR_WIDTH 1u
#define RGM_C0_SSRS_FSM_ERR(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SSRS_FSM_ERR_SHIFT))&RGM_C0_SSRS_FSM_ERR_MASK)
#define RGM_C0_SSRS_C0_SWRST_MASK 0x100000u
#define RGM_C0_SSRS_C0_SWRST_SHIFT 20u
#define RGM_C0_SSRS_C0_SWRST_WIDTH 1u
#define RGM_C0_SSRS_C0_SWRST(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SSRS_C0_SWRST_SHIFT))&RGM_C0_SSRS_C0_SWRST_MASK)
#define RGM_C0_SSRS_C0_INTM_MASK 0x80000u
#define RGM_C0_SSRS_C0_INTM_SHIFT 19u
#define RGM_C0_SSRS_C0_INTM_WIDTH 1u
#define RGM_C0_SSRS_C0_INTM(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SSRS_C0_INTM_SHIFT))&RGM_C0_SSRS_C0_INTM_MASK)
#define RGM_C0_SSRS_C0_WDOG_MASK 0x40000u
#define RGM_C0_SSRS_C0_WDOG_SHIFT 18u
#define RGM_C0_SSRS_C0_WDOG_WIDTH 1u
#define RGM_C0_SSRS_C0_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SSRS_C0_WDOG_SHIFT))&RGM_C0_SSRS_C0_WDOG_MASK)
#define RGM_C0_SSRS_C0_SYSRST_MASK 0x20000u
#define RGM_C0_SSRS_C0_SYSRST_SHIFT 17u
#define RGM_C0_SSRS_C0_SYSRST_WIDTH 1u
#define RGM_C0_SSRS_C0_SYSRST(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SSRS_C0_SYSRST_SHIFT))&RGM_C0_SSRS_C0_SYSRST_MASK)
#define RGM_C0_SSRS_C0_LOCKUP_MASK 0x10000u
#define RGM_C0_SSRS_C0_LOCKUP_SHIFT 16u
#define RGM_C0_SSRS_C0_LOCKUP_WIDTH 1u
#define RGM_C0_SSRS_C0_LOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SSRS_C0_LOCKUP_SHIFT))&RGM_C0_SSRS_C0_LOCKUP_MASK)
#define RGM_C0_SSRS_SSRS_MASK 0xFFFFu
#define RGM_C0_SSRS_SSRS_SHIFT 0u
#define RGM_C0_SSRS_SSRS_WIDTH 16u
#define RGM_C0_SSRS_SSRS(x) (((uint32_t)(((uint32_t)(x))<<RGM_C0_SSRS_SSRS_SHIFT))&RGM_C0_SSRS_SSRS_MASK)
/* C0_SSRS Reg Mask */
#define RGM_C0_SSRS_MASK 0xE01FFFFFu
/*!
* @}
*/ /* end of group RGM_Register_Masks */
/*!
* @}
*/ /* end of group RGM_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7240_rtc_regs.h Normal file
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#ifndef _FC7240_RTC_NU_Tztufn39_REGS_H_
#define _FC7240_RTC_NU_Tztufn39_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- RTC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
* @{
*/
/** RTC - Size of Registers Arrays */
/** RTC - Register Layout Typedef */
typedef struct {
__IO uint32_t SR ; /* Seconds Register, offset: 0x0 */
__IO uint32_t PR ; /* Prescaler Register, offset: 0x4 */
__IO uint32_t AR ; /* Alarm Register, offset: 0x8 */
__IO uint32_t COMPR ; /* Compensation Register, offset: 0xC */
__IO uint32_t CR ; /* Control Register, offset: 0x10 */
__IO uint32_t STR ; /* Status Register, offset: 0x14 */
__IO uint32_t LR ; /* Lock Register, offset: 0x18 */
__IO uint32_t IER ; /* Interrupt Enable Register, offset: 0x1C */
} RTC_Type, *RTC_MemMapPtr;
/** Number of instances of the RTC module. */
#define RTC_INSTANCE_COUNT (1u)
/* RTC - Peripheral instance base addresses */
/** Peripheral RTC base address */
#define RTC_BASE (0x40030000u)
/** Peripheral RTC base pointer */
#define RTC ((RTC_Type *)RTC_BASE)
/** Array initializer of RTC peripheral base addresses */
#define RTC_BASE_ADDRS {RTC_BASE}
/** Array initializer of RTC peripheral base pointers */
#define RTC_BASE_PTRS {RTC}
// need fill by yourself
///** Number of interrupt vector arrays for the RTC module. */
//#define RTC_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the RTC module. */
//#define RTC_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the RTC peripheral type */
//#define RTC_IRQS {RTC_IRQn}
/* ----------------------------------------------------------------------------
-- RTC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTC_Register_Masks RTC Register Masks
* @{
*/
/* SR Bit Fields */
#define RTC_SR_TSR_MASK 0xFFFFFFFFu
#define RTC_SR_TSR_SHIFT 0u
#define RTC_SR_TSR_WIDTH 32u
#define RTC_SR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TSR_SHIFT))&RTC_SR_TSR_MASK)
/* SR Reg Mask */
#define RTC_SR_MASK 0xFFFFFFFFu
/* PR Bit Fields */
#define RTC_PR_TPR_MASK 0xFFFFu
#define RTC_PR_TPR_SHIFT 0u
#define RTC_PR_TPR_WIDTH 16u
#define RTC_PR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_PR_TPR_SHIFT))&RTC_PR_TPR_MASK)
/* PR Reg Mask */
#define RTC_PR_MASK 0x0000FFFFu
/* AR Bit Fields */
#define RTC_AR_TAR_MASK 0xFFFFFFFFu
#define RTC_AR_TAR_SHIFT 0u
#define RTC_AR_TAR_WIDTH 32u
#define RTC_AR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_AR_TAR_SHIFT))&RTC_AR_TAR_MASK)
/* AR Reg Mask */
#define RTC_AR_MASK 0xFFFFFFFFu
/* COMPR Bit Fields */
#define RTC_COMPR_CIC_MASK 0xFF000000u
#define RTC_COMPR_CIC_SHIFT 24u
#define RTC_COMPR_CIC_WIDTH 8u
#define RTC_COMPR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_COMPR_CIC_SHIFT))&RTC_COMPR_CIC_MASK)
#define RTC_COMPR_TCV_MASK 0xFF0000u
#define RTC_COMPR_TCV_SHIFT 16u
#define RTC_COMPR_TCV_WIDTH 8u
#define RTC_COMPR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_COMPR_TCV_SHIFT))&RTC_COMPR_TCV_MASK)
#define RTC_COMPR_CIR_MASK 0xFF00u
#define RTC_COMPR_CIR_SHIFT 8u
#define RTC_COMPR_CIR_WIDTH 8u
#define RTC_COMPR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_COMPR_CIR_SHIFT))&RTC_COMPR_CIR_MASK)
#define RTC_COMPR_TCR_MASK 0xFFu
#define RTC_COMPR_TCR_SHIFT 0u
#define RTC_COMPR_TCR_WIDTH 8u
#define RTC_COMPR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_COMPR_TCR_SHIFT))&RTC_COMPR_TCR_MASK)
/* COMPR Reg Mask */
#define RTC_COMPR_MASK 0xFFFFFFFFu
/* CR Bit Fields */
#define RTC_CR_CKO_MASK 0x200u
#define RTC_CR_CKO_SHIFT 9u
#define RTC_CR_CKO_WIDTH 1u
#define RTC_CR_CKO(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CKO_SHIFT))&RTC_CR_CKO_MASK)
#define RTC_CR_CKPS_MASK 0x20u
#define RTC_CR_CKPS_SHIFT 5u
#define RTC_CR_CKPS_WIDTH 1u
#define RTC_CR_CKPS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CKPS_SHIFT))&RTC_CR_CKPS_MASK)
#define RTC_CR_UM_MASK 0x8u
#define RTC_CR_UM_SHIFT 3u
#define RTC_CR_UM_WIDTH 1u
#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
#define RTC_CR_SWRST_MASK 0x1u
#define RTC_CR_SWRST_SHIFT 0u
#define RTC_CR_SWRST_WIDTH 1u
#define RTC_CR_SWRST(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWRST_SHIFT))&RTC_CR_SWRST_MASK)
/* CR Reg Mask */
#define RTC_CR_MASK 0x00000229u
/* STR Bit Fields */
#define RTC_STR_TCE_MASK 0x10u
#define RTC_STR_TCE_SHIFT 4u
#define RTC_STR_TCE_WIDTH 1u
#define RTC_STR_TCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_STR_TCE_SHIFT))&RTC_STR_TCE_MASK)
#define RTC_STR_TAF_MASK 0x4u
#define RTC_STR_TAF_SHIFT 2u
#define RTC_STR_TAF_WIDTH 1u
#define RTC_STR_TAF(x) (((uint32_t)(((uint32_t)(x))<<RTC_STR_TAF_SHIFT))&RTC_STR_TAF_MASK)
#define RTC_STR_TOF_MASK 0x2u
#define RTC_STR_TOF_SHIFT 1u
#define RTC_STR_TOF_WIDTH 1u
#define RTC_STR_TOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_STR_TOF_SHIFT))&RTC_STR_TOF_MASK)
/* STR Reg Mask */
#define RTC_STR_MASK 0x00000016u
/* LR Bit Fields */
#define RTC_LR_LRL_MASK 0x40u
#define RTC_LR_LRL_SHIFT 6u
#define RTC_LR_LRL_WIDTH 1u
#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
#define RTC_LR_STRL_MASK 0x20u
#define RTC_LR_STRL_SHIFT 5u
#define RTC_LR_STRL_WIDTH 1u
#define RTC_LR_STRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_STRL_SHIFT))&RTC_LR_STRL_MASK)
#define RTC_LR_CRL_MASK 0x10u
#define RTC_LR_CRL_SHIFT 4u
#define RTC_LR_CRL_WIDTH 1u
#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
#define RTC_LR_CPL_MASK 0x8u
#define RTC_LR_CPL_SHIFT 3u
#define RTC_LR_CPL_WIDTH 1u
#define RTC_LR_CPL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CPL_SHIFT))&RTC_LR_CPL_MASK)
/* LR Reg Mask */
#define RTC_LR_MASK 0x00000078u
/* IER Bit Fields */
#define RTC_IER_TSIC_MASK 0x70000u
#define RTC_IER_TSIC_SHIFT 16u
#define RTC_IER_TSIC_WIDTH 3u
#define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIC_SHIFT))&RTC_IER_TSIC_MASK)
#define RTC_IER_TSIE_MASK 0x10u
#define RTC_IER_TSIE_SHIFT 4u
#define RTC_IER_TSIE_WIDTH 1u
#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
#define RTC_IER_TAIE_MASK 0x4u
#define RTC_IER_TAIE_SHIFT 2u
#define RTC_IER_TAIE_WIDTH 1u
#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
#define RTC_IER_TOIE_MASK 0x2u
#define RTC_IER_TOIE_SHIFT 1u
#define RTC_IER_TOIE_WIDTH 1u
#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
/* IER Reg Mask */
#define RTC_IER_MASK 0x00070016u
/*!
* @}
*/ /* end of group RTC_Register_Masks */
/*!
* @}
*/ /* end of group RTC_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7240_scg_regs.h Normal file
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fc/fc7240_scm_regs.h Normal file
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fc/fc7240_sec_regs.h Normal file
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#ifndef _FC7240_SEC_NU_Tztufn17_REGS_H_
#define _FC7240_SEC_NU_Tztufn17_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- SEC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SEC_Peripheral_Access_Layer SEC Peripheral Access Layer
* @{
*/
/** SEC - Size of Registers Arrays */
/** SEC - Register Layout Typedef */
#define SEC_DEK_COUNT 4
typedef struct {
__IO uint32_t DEN ; /* Debug Enable Register, offset: 0x0 */
__I uint32_t FSEC0 ; /* System Security_Control Register0, offset: 0x4 */
__I uint32_t FSEC1 ; /* System Security_Control Register1, offset: 0x8 */
__IO uint32_t DCWOR ; /* Debug Control Write Once Register, offset: 0xC */
__O uint32_t DEK[SEC_DEK_COUNT] ; /* Debug Re-Enable Key Register, offset: 0x10 */
__IO uint32_t TME ; /* Test Mode Enable Register, offset: 0x20 */
__IO uint32_t TMEA ; /* Test Mode Re-Enable Allow Register, offset: 0x24 */
__O uint32_t TMEK ; /* Test Mode Re-Enable Key Register, offset: 0x28 */
uint8_t RESERVED_0[4];
__IO uint32_t FCR0 ; /* Flash Control Register0, offset: 0x30 */
uint8_t RESERVED_1[8];
__IO uint32_t NKRP ; /* NVR Key Read Protection, offset: 0x3C */
uint8_t RESERVED_2[32];
__I uint32_t BCS ; /* Boot Configuration Status Register, offset: 0x60 */
__I uint32_t UKAC ; /* User Key Access Configuration Register, offset: 0x64 */
__IO uint32_t BRC0 ; /* BootROM Configuration Register0, offset: 0x68 */
__I uint32_t BRC1 ; /* BootROM Configuration Register1, offset: 0x6C */
__IO uint32_t SW_CFG_ISP_FLG ; /* Software Configuration to Enter ISP Flag Register, offset: 0x70 */
__I uint32_t BRC2 ; /* BootROM Configuration Register2, offset: 0x74 */
__I uint32_t IMGEA ; /* Image Address Register, offset: 0x78 */
__IO uint32_t NVR_VER ; /* NVR Version Register, offset: 0x7C */
uint8_t RESERVED_3[8];
__I uint32_t LCSTAT ; /* Lifecycle Status Register, offset: 0x88 */
__IO uint32_t FAC ; /* Flash Access Control Register, offset: 0x8C */
uint8_t RESERVED_4[4];
__IO uint32_t FLEXCORE_EN ; /* FlexCore Enable Register, offset: 0x94 */
__IO uint32_t FLEX_CODE_ADDR ; /* Code Address for FlexCore Register, offset: 0x98 */
__IO uint32_t PFLASH_PRLLL_EN ; /* PFLASH Parallel Enable Register, offset: 0x9C */
} SEC_Type, *SEC_MemMapPtr;
/** Number of instances of the SEC module. */
#define SEC_INSTANCE_COUNT (1u)
/* SEC - Peripheral instance base addresses */
/** Peripheral SEC base address */
#define SEC_BASE (0x40014000u)
/** Peripheral SEC base pointer */
#define SEC ((SEC_Type *)SEC_BASE)
/** Array initializer of SEC peripheral base addresses */
#define SEC_BASE_ADDRS {SEC_BASE}
/** Array initializer of SEC peripheral base pointers */
#define SEC_BASE_PTRS {SEC}
// need fill by yourself
///** Number of interrupt vector arrays for the SEC module. */
//#define SEC_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the SEC module. */
//#define SEC_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the SEC peripheral type */
//#define SEC_IRQS {SEC_IRQn}
/* ----------------------------------------------------------------------------
-- SEC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SEC_Register_Masks SEC Register Masks
* @{
*/
/* DEN Bit Fields */
#define SEC_DEN_DEN_MASK 0xFu
#define SEC_DEN_DEN_SHIFT 0u
#define SEC_DEN_DEN_WIDTH 4u
#define SEC_DEN_DEN(x) (((uint32_t)(((uint32_t)(x))<<SEC_DEN_DEN_SHIFT))&SEC_DEN_DEN_MASK)
/* DEN Reg Mask */
#define SEC_DEN_MASK 0x0000000Fu
/* FSEC0 Bit Fields */
#define SEC_FSEC0_SSC0_MASK 0xFFFFu
#define SEC_FSEC0_SSC0_SHIFT 0u
#define SEC_FSEC0_SSC0_WIDTH 16u
#define SEC_FSEC0_SSC0(x) (((uint32_t)(((uint32_t)(x))<<SEC_FSEC0_SSC0_SHIFT))&SEC_FSEC0_SSC0_MASK)
/* FSEC0 Reg Mask */
#define SEC_FSEC0_MASK 0x0000FFFFu
/* FSEC1 Bit Fields */
#define SEC_FSEC1_SSC1_MASK 0xFFFFu
#define SEC_FSEC1_SSC1_SHIFT 0u
#define SEC_FSEC1_SSC1_WIDTH 16u
#define SEC_FSEC1_SSC1(x) (((uint32_t)(((uint32_t)(x))<<SEC_FSEC1_SSC1_SHIFT))&SEC_FSEC1_SSC1_MASK)
/* FSEC1 Reg Mask */
#define SEC_FSEC1_MASK 0x0000FFFFu
/* DCWOR Bit Fields */
#define SEC_DCWOR_DEA_MASK 0xFu
#define SEC_DCWOR_DEA_SHIFT 0u
#define SEC_DCWOR_DEA_WIDTH 4u
#define SEC_DCWOR_DEA(x) (((uint32_t)(((uint32_t)(x))<<SEC_DCWOR_DEA_SHIFT))&SEC_DCWOR_DEA_MASK)
#define SEC_DCWOR_RWL_MASK 0xF0u
#define SEC_DCWOR_RWL_SHIFT 4u
#define SEC_DCWOR_RWL_WIDTH 4u
#define SEC_DCWOR_RWL(x) (((uint32_t)(((uint32_t)(x))<<SEC_DCWOR_RWL_SHIFT))&SEC_DCWOR_RWL_MASK)
/* DCWOR Reg Mask */
#define SEC_DCWOR_MASK 0x000000FFu
/* DEK Bit Fields */
#define SEC_DEK_DEK_MASK 0xFFFFFFFFu
#define SEC_DEK_DEK_SHIFT 0u
#define SEC_DEK_DEK_WIDTH 32u
#define SEC_DEK_DEK(x) (((uint32_t)(((uint32_t)(x))<<SEC_DEK_DEK_SHIFT))&SEC_DEK_DEK_MASK)
/* DEK0 Reg Mask */
#define SEC_DEK_MASK 0xFFFFFFFFu
/* TME Bit Fields */
#define SEC_TME_TME_MASK 0xFu
#define SEC_TME_TME_SHIFT 0u
#define SEC_TME_TME_WIDTH 4u
#define SEC_TME_TME(x) (((uint32_t)(((uint32_t)(x))<<SEC_TME_TME_SHIFT))&SEC_TME_TME_MASK)
/* TME Reg Mask */
#define SEC_TME_MASK 0x0000000Fu
/* TMEA Bit Fields */
#define SEC_TMEA_TMEA_MASK 0xFu
#define SEC_TMEA_TMEA_SHIFT 0u
#define SEC_TMEA_TMEA_WIDTH 4u
#define SEC_TMEA_TMEA(x) (((uint32_t)(((uint32_t)(x))<<SEC_TMEA_TMEA_SHIFT))&SEC_TMEA_TMEA_MASK)
/* TMEA Reg Mask */
#define SEC_TMEA_MASK 0x0000000Fu
/* TMEK Bit Fields */
#define SEC_TMEK_TMEK_MASK 0xFFFFFFFFu
#define SEC_TMEK_TMEK_SHIFT 0u
#define SEC_TMEK_TMEK_WIDTH 32u
#define SEC_TMEK_TMEK(x) (((uint32_t)(((uint32_t)(x))<<SEC_TMEK_TMEK_SHIFT))&SEC_TMEK_TMEK_MASK)
/* TMEK Reg Mask */
#define SEC_TMEK_MASK 0xFFFFFFFFu
/* FCR0 Bit Fields */
#define SEC_FCR0_MED_MASK 0xFu
#define SEC_FCR0_MED_SHIFT 0u
#define SEC_FCR0_MED_WIDTH 4u
#define SEC_FCR0_MED(x) (((uint32_t)(((uint32_t)(x))<<SEC_FCR0_MED_SHIFT))&SEC_FCR0_MED_MASK)
#define SEC_FCR0_NWP_MASK 0xF00u
#define SEC_FCR0_NWP_SHIFT 8u
#define SEC_FCR0_NWP_WIDTH 4u
#define SEC_FCR0_NWP(x) (((uint32_t)(((uint32_t)(x))<<SEC_FCR0_NWP_SHIFT))&SEC_FCR0_NWP_MASK)
#define SEC_FCR0_NEP_MASK 0xF000u
#define SEC_FCR0_NEP_SHIFT 12u
#define SEC_FCR0_NEP_WIDTH 4u
#define SEC_FCR0_NEP(x) (((uint32_t)(((uint32_t)(x))<<SEC_FCR0_NEP_SHIFT))&SEC_FCR0_NEP_MASK)
/* FCR0 Reg Mask */
#define SEC_FCR0_MASK 0x0000FF0Fu
/* NKRP Bit Fields */
#define SEC_NKRP_NKRP_MASK 0xFu
#define SEC_NKRP_NKRP_SHIFT 0u
#define SEC_NKRP_NKRP_WIDTH 4u
#define SEC_NKRP_NKRP(x) (((uint32_t)(((uint32_t)(x))<<SEC_NKRP_NKRP_SHIFT))&SEC_NKRP_NKRP_MASK)
/* NKRP Reg Mask */
#define SEC_NKRP_MASK 0x0000000Fu
/* BCS Bit Fields */
#define SEC_BCS_FBS_MASK 0x1u
#define SEC_BCS_FBS_SHIFT 0u
#define SEC_BCS_FBS_WIDTH 1u
#define SEC_BCS_FBS(x) (((uint32_t)(((uint32_t)(x))<<SEC_BCS_FBS_SHIFT))&SEC_BCS_FBS_MASK)
#define SEC_BCS_NMIDIS_MASK 0x2u
#define SEC_BCS_NMIDIS_SHIFT 1u
#define SEC_BCS_NMIDIS_WIDTH 1u
#define SEC_BCS_NMIDIS(x) (((uint32_t)(((uint32_t)(x))<<SEC_BCS_NMIDIS_SHIFT))&SEC_BCS_NMIDIS_MASK)
#define SEC_BCS_BOOTROM_MASK 0x8u
#define SEC_BCS_BOOTROM_SHIFT 3u
#define SEC_BCS_BOOTROM_WIDTH 1u
#define SEC_BCS_BOOTROM(x) (((uint32_t)(((uint32_t)(x))<<SEC_BCS_BOOTROM_SHIFT))&SEC_BCS_BOOTROM_MASK)
#define SEC_BCS_ISPMODE_MASK 0x10u
#define SEC_BCS_ISPMODE_SHIFT 4u
#define SEC_BCS_ISPMODE_WIDTH 1u
#define SEC_BCS_ISPMODE(x) (((uint32_t)(((uint32_t)(x))<<SEC_BCS_ISPMODE_SHIFT))&SEC_BCS_ISPMODE_MASK)
#define SEC_BCS_PART_MODE_MASK 0x80u
#define SEC_BCS_PART_MODE_SHIFT 7u
#define SEC_BCS_PART_MODE_WIDTH 1u
#define SEC_BCS_PART_MODE(x) (((uint32_t)(((uint32_t)(x))<<SEC_BCS_PART_MODE_SHIFT))&SEC_BCS_PART_MODE_MASK)
#define SEC_BCS_PF_128BIT_MODE_MASK 0x100u
#define SEC_BCS_PF_128BIT_MODE_SHIFT 8u
#define SEC_BCS_PF_128BIT_MODE_WIDTH 1u
#define SEC_BCS_PF_128BIT_MODE(x) (((uint32_t)(((uint32_t)(x))<<SEC_BCS_PF_128BIT_MODE_SHIFT))&SEC_BCS_PF_128BIT_MODE_MASK)
/* BCS Reg Mask */
#define SEC_BCS_MASK 0x0000019Bu
/* UKAC Bit Fields */
#define SEC_UKAC_UKAE_MASK 0xFu
#define SEC_UKAC_UKAE_SHIFT 0u
#define SEC_UKAC_UKAE_WIDTH 4u
#define SEC_UKAC_UKAE(x) (((uint32_t)(((uint32_t)(x))<<SEC_UKAC_UKAE_SHIFT))&SEC_UKAC_UKAE_MASK)
/* UKAC Reg Mask */
#define SEC_UKAC_MASK 0x0000000Fu
/* BRC0 Bit Fields */
#define SEC_BRC0_SECURE_BOOT_DIS_MASK 0xFu
#define SEC_BRC0_SECURE_BOOT_DIS_SHIFT 0u
#define SEC_BRC0_SECURE_BOOT_DIS_WIDTH 4u
#define SEC_BRC0_SECURE_BOOT_DIS(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC0_SECURE_BOOT_DIS_SHIFT))&SEC_BRC0_SECURE_BOOT_DIS_MASK)
#define SEC_BRC0_DEBUG_AUTH_EN_MASK 0xF0u
#define SEC_BRC0_DEBUG_AUTH_EN_SHIFT 4u
#define SEC_BRC0_DEBUG_AUTH_EN_WIDTH 4u
#define SEC_BRC0_DEBUG_AUTH_EN(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC0_DEBUG_AUTH_EN_SHIFT))&SEC_BRC0_DEBUG_AUTH_EN_MASK)
#define SEC_BRC0_ISP_AUTH_EN_MASK 0xF00u
#define SEC_BRC0_ISP_AUTH_EN_SHIFT 8u
#define SEC_BRC0_ISP_AUTH_EN_WIDTH 4u
#define SEC_BRC0_ISP_AUTH_EN(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC0_ISP_AUTH_EN_SHIFT))&SEC_BRC0_ISP_AUTH_EN_MASK)
/* BRC0 Reg Mask */
#define SEC_BRC0_MASK 0x00000FFFu
/* BRC1 Bit Fields */
#define SEC_BRC1_UARTBR_MASK 0x30u
#define SEC_BRC1_UARTBR_SHIFT 4u
#define SEC_BRC1_UARTBR_WIDTH 2u
#define SEC_BRC1_UARTBR(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC1_UARTBR_SHIFT))&SEC_BRC1_UARTBR_MASK)
#define SEC_BRC1_CANBR_MASK 0xC0u
#define SEC_BRC1_CANBR_SHIFT 6u
#define SEC_BRC1_CANBR_WIDTH 2u
#define SEC_BRC1_CANBR(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC1_CANBR_SHIFT))&SEC_BRC1_CANBR_MASK)
#define SEC_BRC1_OSCFREQ_MASK 0x700u
#define SEC_BRC1_OSCFREQ_SHIFT 8u
#define SEC_BRC1_OSCFREQ_WIDTH 3u
#define SEC_BRC1_OSCFREQ(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC1_OSCFREQ_SHIFT))&SEC_BRC1_OSCFREQ_MASK)
#define SEC_BRC1_OSCA_MASK 0x800u
#define SEC_BRC1_OSCA_SHIFT 11u
#define SEC_BRC1_OSCA_WIDTH 1u
#define SEC_BRC1_OSCA(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC1_OSCA_SHIFT))&SEC_BRC1_OSCA_MASK)
#define SEC_BRC1_DBK_IN_EN_MASK 0xF000u
#define SEC_BRC1_DBK_IN_EN_SHIFT 12u
#define SEC_BRC1_DBK_IN_EN_WIDTH 4u
#define SEC_BRC1_DBK_IN_EN(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC1_DBK_IN_EN_SHIFT))&SEC_BRC1_DBK_IN_EN_MASK)
#define SEC_BRC1_NON_SEC_VERIF_EN_MASK 0x10000u
#define SEC_BRC1_NON_SEC_VERIF_EN_SHIFT 16u
#define SEC_BRC1_NON_SEC_VERIF_EN_WIDTH 1u
#define SEC_BRC1_NON_SEC_VERIF_EN(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC1_NON_SEC_VERIF_EN_SHIFT))&SEC_BRC1_NON_SEC_VERIF_EN_MASK)
#define SEC_BRC1_DBKEA_MASK 0xE0000u
#define SEC_BRC1_DBKEA_SHIFT 17u
#define SEC_BRC1_DBKEA_WIDTH 3u
#define SEC_BRC1_DBKEA(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC1_DBKEA_SHIFT))&SEC_BRC1_DBKEA_MASK)
#define SEC_BRC1_ISP_PIN_EN_MASK 0x100000u
#define SEC_BRC1_ISP_PIN_EN_SHIFT 20u
#define SEC_BRC1_ISP_PIN_EN_WIDTH 1u
#define SEC_BRC1_ISP_PIN_EN(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC1_ISP_PIN_EN_SHIFT))&SEC_BRC1_ISP_PIN_EN_MASK)
#define SEC_BRC1_ISPAIRM_MASK 0x200000u
#define SEC_BRC1_ISPAIRM_SHIFT 21u
#define SEC_BRC1_ISPAIRM_WIDTH 1u
#define SEC_BRC1_ISPAIRM(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC1_ISPAIRM_SHIFT))&SEC_BRC1_ISPAIRM_MASK)
#define SEC_BRC1_KEY_PROT_MASK 0x400000u
#define SEC_BRC1_KEY_PROT_SHIFT 22u
#define SEC_BRC1_KEY_PROT_WIDTH 1u
#define SEC_BRC1_KEY_PROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC1_KEY_PROT_SHIFT))&SEC_BRC1_KEY_PROT_MASK)
#define SEC_BRC1_ROM_LOOP_CTRL_MASK 0x800000u
#define SEC_BRC1_ROM_LOOP_CTRL_SHIFT 23u
#define SEC_BRC1_ROM_LOOP_CTRL_WIDTH 1u
#define SEC_BRC1_ROM_LOOP_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC1_ROM_LOOP_CTRL_SHIFT))&SEC_BRC1_ROM_LOOP_CTRL_MASK)
#define SEC_BRC1_SW_CFG_ISP_EN_MASK 0x1000000u
#define SEC_BRC1_SW_CFG_ISP_EN_SHIFT 24u
#define SEC_BRC1_SW_CFG_ISP_EN_WIDTH 1u
#define SEC_BRC1_SW_CFG_ISP_EN(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC1_SW_CFG_ISP_EN_SHIFT))&SEC_BRC1_SW_CFG_ISP_EN_MASK)
/* BRC1 Reg Mask */
#define SEC_BRC1_MASK 0x01FFFFF0u
/* SW_CFG_ISP_FLG Bit Fields */
#define SEC_SW_CFG_ISP_FLG_SW_CFG_ISP_FLG_MASK 0x1u
#define SEC_SW_CFG_ISP_FLG_SW_CFG_ISP_FLG_SHIFT 0u
#define SEC_SW_CFG_ISP_FLG_SW_CFG_ISP_FLG_WIDTH 1u
#define SEC_SW_CFG_ISP_FLG_SW_CFG_ISP_FLG(x) (((uint32_t)(((uint32_t)(x))<<SEC_SW_CFG_ISP_FLG_SW_CFG_ISP_FLG_SHIFT))&SEC_SW_CFG_ISP_FLG_SW_CFG_ISP_FLG_MASK)
/* SW_CFG_ISP_FLG Reg Mask */
#define SEC_SW_CFG_ISP_FLG_MASK 0x00000001u
/* BRC2 Bit Fields */
#define SEC_BRC2_USERCODE_VERIFY_MASK_MASK 0x1FFFFFFu
#define SEC_BRC2_USERCODE_VERIFY_MASK_SHIFT 0u
#define SEC_BRC2_USERCODE_VERIFY_MASK_WIDTH 25u
#define SEC_BRC2_USERCODE_VERIFY_MASK(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC2_USERCODE_VERIFY_MASK_SHIFT))&SEC_BRC2_USERCODE_VERIFY_MASK_MASK)
#define SEC_BRC2_ISP_INST_SEL_MASK 0xE000000u
#define SEC_BRC2_ISP_INST_SEL_SHIFT 25u
#define SEC_BRC2_ISP_INST_SEL_WIDTH 3u
#define SEC_BRC2_ISP_INST_SEL(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC2_ISP_INST_SEL_SHIFT))&SEC_BRC2_ISP_INST_SEL_MASK)
#define SEC_BRC2_USERCODE_VERIFICATION_ALG_MASK 0x70000000u
#define SEC_BRC2_USERCODE_VERIFICATION_ALG_SHIFT 28u
#define SEC_BRC2_USERCODE_VERIFICATION_ALG_WIDTH 3u
#define SEC_BRC2_USERCODE_VERIFICATION_ALG(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC2_USERCODE_VERIFICATION_ALG_SHIFT))&SEC_BRC2_USERCODE_VERIFICATION_ALG_MASK)
#define SEC_BRC2_DECRP_ALG_MASK 0x80000000u
#define SEC_BRC2_DECRP_ALG_SHIFT 31u
#define SEC_BRC2_DECRP_ALG_WIDTH 1u
#define SEC_BRC2_DECRP_ALG(x) (((uint32_t)(((uint32_t)(x))<<SEC_BRC2_DECRP_ALG_SHIFT))&SEC_BRC2_DECRP_ALG_MASK)
/* BRC2 Reg Mask */
#define SEC_BRC2_MASK 0xFFFFFFFFu
/* IMGEA Bit Fields */
#define SEC_IMGEA_IMAGE_ADDR_MASK 0xFFFFFFFFu
#define SEC_IMGEA_IMAGE_ADDR_SHIFT 0u
#define SEC_IMGEA_IMAGE_ADDR_WIDTH 32u
#define SEC_IMGEA_IMAGE_ADDR(x) (((uint32_t)(((uint32_t)(x))<<SEC_IMGEA_IMAGE_ADDR_SHIFT))&SEC_IMGEA_IMAGE_ADDR_MASK)
/* IMGEA Reg Mask */
#define SEC_IMGEA_MASK 0xFFFFFFFFu
/* NVR_VER Bit Fields */
#define SEC_NVR_VER_C_VER_MASK 0x3Fu
#define SEC_NVR_VER_C_VER_SHIFT 0u
#define SEC_NVR_VER_C_VER_WIDTH 6u
#define SEC_NVR_VER_C_VER(x) (((uint32_t)(((uint32_t)(x))<<SEC_NVR_VER_C_VER_SHIFT))&SEC_NVR_VER_C_VER_MASK)
#define SEC_NVR_VER_R_VER_MASK 0xFC0u
#define SEC_NVR_VER_R_VER_SHIFT 6u
#define SEC_NVR_VER_R_VER_WIDTH 6u
#define SEC_NVR_VER_R_VER(x) (((uint32_t)(((uint32_t)(x))<<SEC_NVR_VER_R_VER_SHIFT))&SEC_NVR_VER_R_VER_MASK)
#define SEC_NVR_VER_V_VER_MASK 0xF000u
#define SEC_NVR_VER_V_VER_SHIFT 12u
#define SEC_NVR_VER_V_VER_WIDTH 4u
#define SEC_NVR_VER_V_VER(x) (((uint32_t)(((uint32_t)(x))<<SEC_NVR_VER_V_VER_SHIFT))&SEC_NVR_VER_V_VER_MASK)
#define SEC_NVR_VER_CHIP_VER_MASK 0xFF0000u
#define SEC_NVR_VER_CHIP_VER_SHIFT 16u
#define SEC_NVR_VER_CHIP_VER_WIDTH 8u
#define SEC_NVR_VER_CHIP_VER(x) (((uint32_t)(((uint32_t)(x))<<SEC_NVR_VER_CHIP_VER_SHIFT))&SEC_NVR_VER_CHIP_VER_MASK)
/* NVR_VER Reg Mask */
#define SEC_NVR_VER_MASK 0x00FFFFFFu
/* LCSTAT Bit Fields */
#define SEC_LCSTAT_LIFECYCLE_OEM_DEV_MASK 0x1u
#define SEC_LCSTAT_LIFECYCLE_OEM_DEV_SHIFT 0u
#define SEC_LCSTAT_LIFECYCLE_OEM_DEV_WIDTH 1u
#define SEC_LCSTAT_LIFECYCLE_OEM_DEV(x) (((uint32_t)(((uint32_t)(x))<<SEC_LCSTAT_LIFECYCLE_OEM_DEV_SHIFT))&SEC_LCSTAT_LIFECYCLE_OEM_DEV_MASK)
#define SEC_LCSTAT_LIFECYCLE_OEM_PDT_MASK 0x2u
#define SEC_LCSTAT_LIFECYCLE_OEM_PDT_SHIFT 1u
#define SEC_LCSTAT_LIFECYCLE_OEM_PDT_WIDTH 1u
#define SEC_LCSTAT_LIFECYCLE_OEM_PDT(x) (((uint32_t)(((uint32_t)(x))<<SEC_LCSTAT_LIFECYCLE_OEM_PDT_SHIFT))&SEC_LCSTAT_LIFECYCLE_OEM_PDT_MASK)
#define SEC_LCSTAT_LIFECYCLE_IN_FIELD_MASK 0x4u
#define SEC_LCSTAT_LIFECYCLE_IN_FIELD_SHIFT 2u
#define SEC_LCSTAT_LIFECYCLE_IN_FIELD_WIDTH 1u
#define SEC_LCSTAT_LIFECYCLE_IN_FIELD(x) (((uint32_t)(((uint32_t)(x))<<SEC_LCSTAT_LIFECYCLE_IN_FIELD_SHIFT))&SEC_LCSTAT_LIFECYCLE_IN_FIELD_MASK)
#define SEC_LCSTAT_LIFECYCLE_SWFA_MASK 0x8u
#define SEC_LCSTAT_LIFECYCLE_SWFA_SHIFT 3u
#define SEC_LCSTAT_LIFECYCLE_SWFA_WIDTH 1u
#define SEC_LCSTAT_LIFECYCLE_SWFA(x) (((uint32_t)(((uint32_t)(x))<<SEC_LCSTAT_LIFECYCLE_SWFA_SHIFT))&SEC_LCSTAT_LIFECYCLE_SWFA_MASK)
#define SEC_LCSTAT_LIFECYCLE_HWFA_MASK 0x10u
#define SEC_LCSTAT_LIFECYCLE_HWFA_SHIFT 4u
#define SEC_LCSTAT_LIFECYCLE_HWFA_WIDTH 1u
#define SEC_LCSTAT_LIFECYCLE_HWFA(x) (((uint32_t)(((uint32_t)(x))<<SEC_LCSTAT_LIFECYCLE_HWFA_SHIFT))&SEC_LCSTAT_LIFECYCLE_HWFA_MASK)
/* LCSTAT Reg Mask */
#define SEC_LCSTAT_MASK 0x0000001Fu
/* FAC Bit Fields */
#define SEC_FAC_HOST_UKEY_RPROT_MASK 0x10000u
#define SEC_FAC_HOST_UKEY_RPROT_SHIFT 16u
#define SEC_FAC_HOST_UKEY_RPROT_WIDTH 1u
#define SEC_FAC_HOST_UKEY_RPROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_FAC_HOST_UKEY_RPROT_SHIFT))&SEC_FAC_HOST_UKEY_RPROT_MASK)
#define SEC_FAC_HOST_UKEY_WPROT_MASK 0x20000u
#define SEC_FAC_HOST_UKEY_WPROT_SHIFT 17u
#define SEC_FAC_HOST_UKEY_WPROT_WIDTH 1u
#define SEC_FAC_HOST_UKEY_WPROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_FAC_HOST_UKEY_WPROT_SHIFT))&SEC_FAC_HOST_UKEY_WPROT_MASK)
#define SEC_FAC_HOST_UKEY_EPROT_MASK 0x40000u
#define SEC_FAC_HOST_UKEY_EPROT_SHIFT 18u
#define SEC_FAC_HOST_UKEY_EPROT_WIDTH 1u
#define SEC_FAC_HOST_UKEY_EPROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_FAC_HOST_UKEY_EPROT_SHIFT))&SEC_FAC_HOST_UKEY_EPROT_MASK)
#define SEC_FAC_HOST_NVR_RPROT_MASK 0x80000u
#define SEC_FAC_HOST_NVR_RPROT_SHIFT 19u
#define SEC_FAC_HOST_NVR_RPROT_WIDTH 1u
#define SEC_FAC_HOST_NVR_RPROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_FAC_HOST_NVR_RPROT_SHIFT))&SEC_FAC_HOST_NVR_RPROT_MASK)
#define SEC_FAC_HOST_NVR_WPROT_MASK 0x100000u
#define SEC_FAC_HOST_NVR_WPROT_SHIFT 20u
#define SEC_FAC_HOST_NVR_WPROT_WIDTH 1u
#define SEC_FAC_HOST_NVR_WPROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_FAC_HOST_NVR_WPROT_SHIFT))&SEC_FAC_HOST_NVR_WPROT_MASK)
#define SEC_FAC_HOST_NVR_EPROT_MASK 0x200000u
#define SEC_FAC_HOST_NVR_EPROT_SHIFT 21u
#define SEC_FAC_HOST_NVR_EPROT_WIDTH 1u
#define SEC_FAC_HOST_NVR_EPROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_FAC_HOST_NVR_EPROT_SHIFT))&SEC_FAC_HOST_NVR_EPROT_MASK)
#define SEC_FAC_HSM_UKEY_RPROT_MASK 0x1000000u
#define SEC_FAC_HSM_UKEY_RPROT_SHIFT 24u
#define SEC_FAC_HSM_UKEY_RPROT_WIDTH 1u
#define SEC_FAC_HSM_UKEY_RPROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_FAC_HSM_UKEY_RPROT_SHIFT))&SEC_FAC_HSM_UKEY_RPROT_MASK)
#define SEC_FAC_HSM_UKEY_WPROT_MASK 0x2000000u
#define SEC_FAC_HSM_UKEY_WPROT_SHIFT 25u
#define SEC_FAC_HSM_UKEY_WPROT_WIDTH 1u
#define SEC_FAC_HSM_UKEY_WPROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_FAC_HSM_UKEY_WPROT_SHIFT))&SEC_FAC_HSM_UKEY_WPROT_MASK)
#define SEC_FAC_HSM_UKEY_EPROT_MASK 0x4000000u
#define SEC_FAC_HSM_UKEY_EPROT_SHIFT 26u
#define SEC_FAC_HSM_UKEY_EPROT_WIDTH 1u
#define SEC_FAC_HSM_UKEY_EPROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_FAC_HSM_UKEY_EPROT_SHIFT))&SEC_FAC_HSM_UKEY_EPROT_MASK)
#define SEC_FAC_HSM_NVR_RPROT_MASK 0x8000000u
#define SEC_FAC_HSM_NVR_RPROT_SHIFT 27u
#define SEC_FAC_HSM_NVR_RPROT_WIDTH 1u
#define SEC_FAC_HSM_NVR_RPROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_FAC_HSM_NVR_RPROT_SHIFT))&SEC_FAC_HSM_NVR_RPROT_MASK)
#define SEC_FAC_HSM_NVR_WPROT_MASK 0x10000000u
#define SEC_FAC_HSM_NVR_WPROT_SHIFT 28u
#define SEC_FAC_HSM_NVR_WPROT_WIDTH 1u
#define SEC_FAC_HSM_NVR_WPROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_FAC_HSM_NVR_WPROT_SHIFT))&SEC_FAC_HSM_NVR_WPROT_MASK)
#define SEC_FAC_HSM_NVR_EPROT_MASK 0x20000000u
#define SEC_FAC_HSM_NVR_EPROT_SHIFT 29u
#define SEC_FAC_HSM_NVR_EPROT_WIDTH 1u
#define SEC_FAC_HSM_NVR_EPROT(x) (((uint32_t)(((uint32_t)(x))<<SEC_FAC_HSM_NVR_EPROT_SHIFT))&SEC_FAC_HSM_NVR_EPROT_MASK)
/* FAC Reg Mask */
#define SEC_FAC_MASK 0x3F3F0000u
/* FLEXCORE_EN Bit Fields */
#define SEC_FLEXCORE_EN_FLEXCORE_EN_MASK 0xFu
#define SEC_FLEXCORE_EN_FLEXCORE_EN_SHIFT 0u
#define SEC_FLEXCORE_EN_FLEXCORE_EN_WIDTH 4u
#define SEC_FLEXCORE_EN_FLEXCORE_EN(x) (((uint32_t)(((uint32_t)(x))<<SEC_FLEXCORE_EN_FLEXCORE_EN_SHIFT))&SEC_FLEXCORE_EN_FLEXCORE_EN_MASK)
#define SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_MASK 0x10u
#define SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_SHIFT 4u
#define SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_WIDTH 1u
#define SEC_FLEXCORE_EN_FLEXCORE_DBG_EN(x) (((uint32_t)(((uint32_t)(x))<<SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_SHIFT))&SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_MASK)
/* FLEXCORE_EN Reg Mask */
#define SEC_FLEXCORE_EN_MASK 0x0000001Fu
/* FLEX_CODE_ADDR Bit Fields */
#define SEC_FLEX_CODE_ADDR_FLEX_CODE_ADDR_MASK 0x3FFFFFFFu
#define SEC_FLEX_CODE_ADDR_FLEX_CODE_ADDR_SHIFT 0u
#define SEC_FLEX_CODE_ADDR_FLEX_CODE_ADDR_WIDTH 30u
#define SEC_FLEX_CODE_ADDR_FLEX_CODE_ADDR(x) (((uint32_t)(((uint32_t)(x))<<SEC_FLEX_CODE_ADDR_FLEX_CODE_ADDR_SHIFT))&SEC_FLEX_CODE_ADDR_FLEX_CODE_ADDR_MASK)
/* FLEX_CODE_ADDR Reg Mask */
#define SEC_FLEX_CODE_ADDR_MASK 0x3FFFFFFFu
/* PFLASH_PRLLL_EN Bit Fields */
#define SEC_PFLASH_PRLLL_EN_PFLASH_PRLLL_EN_MASK 0xFu
#define SEC_PFLASH_PRLLL_EN_PFLASH_PRLLL_EN_SHIFT 0u
#define SEC_PFLASH_PRLLL_EN_PFLASH_PRLLL_EN_WIDTH 4u
#define SEC_PFLASH_PRLLL_EN_PFLASH_PRLLL_EN(x) (((uint32_t)(((uint32_t)(x))<<SEC_PFLASH_PRLLL_EN_PFLASH_PRLLL_EN_SHIFT))&SEC_PFLASH_PRLLL_EN_PFLASH_PRLLL_EN_MASK)
/* PFLASH_PRLLL_EN Reg Mask */
#define SEC_PFLASH_PRLLL_EN_MASK 0x0000000Fu
/*!
* @}
*/ /* end of group SEC_Register_Masks */
/*!
* @}
*/ /* end of group SEC_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_SMC_NU_Tztufn46_REGS_H_
#define _FC7240_SMC_NU_Tztufn46_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- SMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
* @{
*/
/** SMC - Size of Registers Arrays */
/** SMC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[12];
__IO uint32_t PMCTRL ; /* Power Mode Control Register, offset: 0xc */
__IO uint32_t STANDBY_CFG ; /* Standby Mode Configuration Register, offset: 0x10 */
} SMC_Type, *SMC_MemMapPtr;
/** Number of instances of the SMC module. */
#define SMC_INSTANCE_COUNT (1u)
/* SMC - Peripheral instance base addresses */
/** Peripheral SMC base address */
#define SMC_BASE (0x40045000u)
/** Peripheral SMC base pointer */
#define SMC ((SMC_Type *)SMC_BASE)
/** Array initializer of SMC peripheral base addresses */
#define SMC_BASE_ADDRS {SMC_BASE}
/** Array initializer of SMC peripheral base pointers */
#define SMC_BASE_PTRS {SMC}
// need fill by yourself
///** Number of interrupt vector arrays for the SMC module. */
//#define SMC_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the SMC module. */
//#define SMC_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the SMC peripheral type */
//#define SMC_IRQS {SMC_IRQn}
/* ----------------------------------------------------------------------------
-- SMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SMC_Register_Masks SMC Register Masks
* @{
*/
/* PMCTRL Bit Fields */
#define SMC_PMCTRL_STOP_MODE_MASK 0x7u
#define SMC_PMCTRL_STOP_MODE_SHIFT 0u
#define SMC_PMCTRL_STOP_MODE_WIDTH 3u
#define SMC_PMCTRL_STOP_MODE(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_STOP_MODE_SHIFT))&SMC_PMCTRL_STOP_MODE_MASK)
/* PMCTRL Reg Mask */
#define SMC_PMCTRL_MASK 0x00000007u
/* STANDBY_CFG Bit Fields */
#define SMC_STANDBY_CFG_OPTION_MASK 0x3u
#define SMC_STANDBY_CFG_OPTION_SHIFT 0u
#define SMC_STANDBY_CFG_OPTION_WIDTH 2u
#define SMC_STANDBY_CFG_OPTION(x) (((uint32_t)(((uint32_t)(x))<<SMC_STANDBY_CFG_OPTION_SHIFT))&SMC_STANDBY_CFG_OPTION_MASK)
/* STANDBY_CFG Reg Mask */
#define SMC_STANDBY_CFG_MASK 0x00000003u
/*!
* @}
*/ /* end of group SMC_Register_Masks */
/*!
* @}
*/ /* end of group SMC_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_TMU_NU_Tztufn28_REGS_H_
#define _FC7240_TMU_NU_Tztufn28_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- TMU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TMU_Peripheral_Access_Layer TMU Peripheral Access Layer
* @{
*/
/** TMU - Size of Registers Arrays */
/** TMU - Register Layout Typedef */
typedef struct {
__IO uint32_t UNLOCK ; /* Unlock Register, offset: 0x0 */
__IO uint32_t TF_CTRL ; /* Temperature Flag Control Register, offset: 0x4 */
__IO uint32_t TF_STATUS ; /* Temperature Flag Status Register, offset: 0x8 */
__IO uint32_t TV_CTRL ; /* Temperature Voltage Control Register, offset: 0xC */
__IO uint32_t TV_STATUS ; /* Temperature Voltage Status Register, offset: 0x10 */
uint8_t RESERVED_0[8];
__I uint32_t TV_TRIM ; /* Temperature Voltage Trim Register, offset: 0x1C */
} TMU_Type, *TMU_MemMapPtr;
/** Number of instances of the TMU module. */
#define TMU_INSTANCE_COUNT (1u)
/* TMU - Peripheral instance base addresses */
/** Peripheral TMU base address */
#define TMU_BASE (0x40043000u)
/** Peripheral TMU base pointer */
#define TMU ((TMU_Type *)TMU_BASE)
/** Array initializer of TMU peripheral base addresses */
#define TMU_BASE_ADDRS {TMU_BASE}
/** Array initializer of TMU peripheral base pointers */
#define TMU_BASE_PTRS {TMU}
// need fill by yourself
///** Number of interrupt vector arrays for the TMU module. */
//#define TMU_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the TMU module. */
//#define TMU_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the TMU peripheral type */
//#define TMU_IRQS {TMU_IRQn}
/* ----------------------------------------------------------------------------
-- TMU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TMU_Register_Masks TMU Register Masks
* @{
*/
/* UNLOCK Bit Fields */
#define TMU_UNLOCK_UNLOCK_MASK 0x1u
#define TMU_UNLOCK_UNLOCK_SHIFT 0u
#define TMU_UNLOCK_UNLOCK_WIDTH 1u
#define TMU_UNLOCK_UNLOCK(x) (((uint32_t)(((uint32_t)(x))<<TMU_UNLOCK_UNLOCK_SHIFT))&TMU_UNLOCK_UNLOCK_MASK)
/* UNLOCK Reg Mask */
#define TMU_UNLOCK_MASK 0x00000001u
/* TF_CTRL Bit Fields */
#define TMU_TF_CTRL_TF_150F_IE_MASK 0x8000000u
#define TMU_TF_CTRL_TF_150F_IE_SHIFT 27u
#define TMU_TF_CTRL_TF_150F_IE_WIDTH 1u
#define TMU_TF_CTRL_TF_150F_IE(x) (((uint32_t)(((uint32_t)(x))<<TMU_TF_CTRL_TF_150F_IE_SHIFT))&TMU_TF_CTRL_TF_150F_IE_MASK)
#define TMU_TF_CTRL_TF_125F_IE_MASK 0x4000000u
#define TMU_TF_CTRL_TF_125F_IE_SHIFT 26u
#define TMU_TF_CTRL_TF_125F_IE_WIDTH 1u
#define TMU_TF_CTRL_TF_125F_IE(x) (((uint32_t)(((uint32_t)(x))<<TMU_TF_CTRL_TF_125F_IE_SHIFT))&TMU_TF_CTRL_TF_125F_IE_MASK)
#define TMU_TF_CTRL_TF_RDYF_IE_MASK 0x1000000u
#define TMU_TF_CTRL_TF_RDYF_IE_SHIFT 24u
#define TMU_TF_CTRL_TF_RDYF_IE_WIDTH 1u
#define TMU_TF_CTRL_TF_RDYF_IE(x) (((uint32_t)(((uint32_t)(x))<<TMU_TF_CTRL_TF_RDYF_IE_SHIFT))&TMU_TF_CTRL_TF_RDYF_IE_MASK)
#define TMU_TF_CTRL_TF_HYSOFF_MASK 0x10000u
#define TMU_TF_CTRL_TF_HYSOFF_SHIFT 16u
#define TMU_TF_CTRL_TF_HYSOFF_WIDTH 1u
#define TMU_TF_CTRL_TF_HYSOFF(x) (((uint32_t)(((uint32_t)(x))<<TMU_TF_CTRL_TF_HYSOFF_SHIFT))&TMU_TF_CTRL_TF_HYSOFF_MASK)
#define TMU_TF_CTRL_TF_START_CNT_MASK 0xF00u
#define TMU_TF_CTRL_TF_START_CNT_SHIFT 8u
#define TMU_TF_CTRL_TF_START_CNT_WIDTH 4u
#define TMU_TF_CTRL_TF_START_CNT(x) (((uint32_t)(((uint32_t)(x))<<TMU_TF_CTRL_TF_START_CNT_SHIFT))&TMU_TF_CTRL_TF_START_CNT_MASK)
#define TMU_TF_CTRL_TF_FILT_BYP_MASK 0x2u
#define TMU_TF_CTRL_TF_FILT_BYP_SHIFT 1u
#define TMU_TF_CTRL_TF_FILT_BYP_WIDTH 1u
#define TMU_TF_CTRL_TF_FILT_BYP(x) (((uint32_t)(((uint32_t)(x))<<TMU_TF_CTRL_TF_FILT_BYP_SHIFT))&TMU_TF_CTRL_TF_FILT_BYP_MASK)
#define TMU_TF_CTRL_TF_EN_MASK 0x1u
#define TMU_TF_CTRL_TF_EN_SHIFT 0u
#define TMU_TF_CTRL_TF_EN_WIDTH 1u
#define TMU_TF_CTRL_TF_EN(x) (((uint32_t)(((uint32_t)(x))<<TMU_TF_CTRL_TF_EN_SHIFT))&TMU_TF_CTRL_TF_EN_MASK)
/* TF_CTRL Reg Mask */
#define TMU_TF_CTRL_MASK 0x0D010F03u
/* TF_STATUS Bit Fields */
#define TMU_TF_STATUS_TF_150_MASK 0x800u
#define TMU_TF_STATUS_TF_150_SHIFT 11u
#define TMU_TF_STATUS_TF_150_WIDTH 1u
#define TMU_TF_STATUS_TF_150(x) (((uint32_t)(((uint32_t)(x))<<TMU_TF_STATUS_TF_150_SHIFT))&TMU_TF_STATUS_TF_150_MASK)
#define TMU_TF_STATUS_TF_125_MASK 0x400u
#define TMU_TF_STATUS_TF_125_SHIFT 10u
#define TMU_TF_STATUS_TF_125_WIDTH 1u
#define TMU_TF_STATUS_TF_125(x) (((uint32_t)(((uint32_t)(x))<<TMU_TF_STATUS_TF_125_SHIFT))&TMU_TF_STATUS_TF_125_MASK)
#define TMU_TF_STATUS_TF_150F_MASK 0x8u
#define TMU_TF_STATUS_TF_150F_SHIFT 3u
#define TMU_TF_STATUS_TF_150F_WIDTH 1u
#define TMU_TF_STATUS_TF_150F(x) (((uint32_t)(((uint32_t)(x))<<TMU_TF_STATUS_TF_150F_SHIFT))&TMU_TF_STATUS_TF_150F_MASK)
#define TMU_TF_STATUS_TF_125F_MASK 0x4u
#define TMU_TF_STATUS_TF_125F_SHIFT 2u
#define TMU_TF_STATUS_TF_125F_WIDTH 1u
#define TMU_TF_STATUS_TF_125F(x) (((uint32_t)(((uint32_t)(x))<<TMU_TF_STATUS_TF_125F_SHIFT))&TMU_TF_STATUS_TF_125F_MASK)
#define TMU_TF_STATUS_TF_RDYF_MASK 0x1u
#define TMU_TF_STATUS_TF_RDYF_SHIFT 0u
#define TMU_TF_STATUS_TF_RDYF_WIDTH 1u
#define TMU_TF_STATUS_TF_RDYF(x) (((uint32_t)(((uint32_t)(x))<<TMU_TF_STATUS_TF_RDYF_SHIFT))&TMU_TF_STATUS_TF_RDYF_MASK)
/* TF_STATUS Reg Mask */
#define TMU_TF_STATUS_MASK 0x00000C0Du
/* TV_CTRL Bit Fields */
#define TMU_TV_CTRL_TV_RDYF_IE_MASK 0x1000000u
#define TMU_TV_CTRL_TV_RDYF_IE_SHIFT 24u
#define TMU_TV_CTRL_TV_RDYF_IE_WIDTH 1u
#define TMU_TV_CTRL_TV_RDYF_IE(x) (((uint32_t)(((uint32_t)(x))<<TMU_TV_CTRL_TV_RDYF_IE_SHIFT))&TMU_TV_CTRL_TV_RDYF_IE_MASK)
#define TMU_TV_CTRL_TV_START_CNT_MASK 0x700u
#define TMU_TV_CTRL_TV_START_CNT_SHIFT 8u
#define TMU_TV_CTRL_TV_START_CNT_WIDTH 3u
#define TMU_TV_CTRL_TV_START_CNT(x) (((uint32_t)(((uint32_t)(x))<<TMU_TV_CTRL_TV_START_CNT_SHIFT))&TMU_TV_CTRL_TV_START_CNT_MASK)
#define TMU_TV_CTRL_TV_EN_MASK 0x1u
#define TMU_TV_CTRL_TV_EN_SHIFT 0u
#define TMU_TV_CTRL_TV_EN_WIDTH 1u
#define TMU_TV_CTRL_TV_EN(x) (((uint32_t)(((uint32_t)(x))<<TMU_TV_CTRL_TV_EN_SHIFT))&TMU_TV_CTRL_TV_EN_MASK)
/* TV_CTRL Reg Mask */
#define TMU_TV_CTRL_MASK 0x01000701u
/* TV_STATUS Bit Fields */
#define TMU_TV_STATUS_TV_RDYF_MASK 0x1u
#define TMU_TV_STATUS_TV_RDYF_SHIFT 0u
#define TMU_TV_STATUS_TV_RDYF_WIDTH 1u
#define TMU_TV_STATUS_TV_RDYF(x) (((uint32_t)(((uint32_t)(x))<<TMU_TV_STATUS_TV_RDYF_SHIFT))&TMU_TV_STATUS_TV_RDYF_MASK)
/* TV_STATUS Reg Mask */
#define TMU_TV_STATUS_MASK 0x00000001u
/* TV_TRIM Bit Fields */
#define TMU_TV_TRIM_TV_TCODE_MASK 0xFFF0000u
#define TMU_TV_TRIM_TV_TCODE_SHIFT 16u
#define TMU_TV_TRIM_TV_TCODE_WIDTH 12u
#define TMU_TV_TRIM_TV_TCODE(x) (((uint32_t)(((uint32_t)(x))<<TMU_TV_TRIM_TV_TCODE_SHIFT))&TMU_TV_TRIM_TV_TCODE_MASK)
#define TMU_TV_TRIM_TV_SLOPE_MASK 0x1FFFu
#define TMU_TV_TRIM_TV_SLOPE_SHIFT 0u
#define TMU_TV_TRIM_TV_SLOPE_WIDTH 13u
#define TMU_TV_TRIM_TV_SLOPE(x) (((uint32_t)(((uint32_t)(x))<<TMU_TV_TRIM_TV_SLOPE_SHIFT))&TMU_TV_TRIM_TV_SLOPE_MASK)
/* TV_TRIM Reg Mask */
#define TMU_TV_TRIM_MASK 0x0FFF1FFFu
/*!
* @}
*/ /* end of group TMU_Register_Masks */
/*!
* @}
*/ /* end of group TMU_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7240_tpu_e_regs.h Normal file
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#ifndef _FC7240_TPU_H_NU_Tztufn35_REGS_H_
#define _FC7240_TPU_H_NU_Tztufn35_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- TPU_H Peripheral Access Layer
---------------------------------------------------------------------------- */
#define TPU_H_CH_COUNT 32
/*!
* @addtogroup TPU_H_Peripheral_Access_Layer TPU_H Peripheral Access Layer
* @{
*/
/** TPU_H - Size of Registers Arrays */
/** TPU_H - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[16];
__I uint32_t GCR_VSR ; /* Global Control Region -Visible Status Register, offset: 0x10 */
__I uint32_t GCR_VIR ; /* Global Control Region - Visible Input Status Register, offset: 0x14 */
__I uint32_t GCR_VOR ; /* Global Control Region - Visible Output Status Register, offset: 0x18 */
__I uint32_t GCR_VOBR ; /* Global Control Region - Visible Output Enable Status Register, offset: 0x1C */
__I uint32_t GCR_VM1R ; /* Global Control Region - Visible MRL1 Register, offset: 0x20 */
__I uint32_t GCR_VM2R ; /* Global Control Region -Visible MRL2 Register, offset: 0x24 */
__I uint32_t GCR_VT1R ; /* Global Control Region - Visible TDL1 Register, offset: 0x28 */
__I uint32_t GCR_VT2R ; /* Global Control Region - Visible TDL2 Register, offset: 0x2C */
__I uint32_t GCR_EM1R ; /* Global Control Region - Visible Event by MRL1 Register, offset: 0x30 */
__I uint32_t GCR_EM2R ; /* Global Control Region - Visible Event by MRL2 Register, offset: 0x34 */
__I uint32_t GCR_ET1R ; /* Global Control Region - Visible Event by TDL1 Register, offset: 0x38 */
__I uint32_t GCR_ET2R ; /* Global Control Region - Visible Event by TDL2 Register, offset: 0x3C */
__I uint32_t GCR_VHSR ; /* Global Control Region - Visible Host Acknowledge Register, offset: 0x40 */
uint8_t RESERVED_1[188];
__I uint32_t TBR_CR ; /* Time Bases Region - Control Register, offset: 0x100 */
__IO uint32_t TBR_T1R ; /* Time Base Region - TCR1 Value Register, offset: 0x104 */
__IO uint32_t TBR_T2R ; /* Time Base Region - TCR2 Value Register, offset: 0x108 */
uint8_t RESERVED_2[4];
__I uint32_t TBR_TPR ; /* Time Base Region - Tooth Program Register, offset: 0x110 */
__IO uint32_t TBR_TRR ; /* Time Base Region - Tick Rate Register, offset: 0x114 */
__IO uint32_t TBR_T1MR ; /* Time Base Region - TCR1 Maximum Register, offset: 0x118 */
__IO uint32_t TBR_T2MR ; /* Time Base Region - TCR2 Maximum Register, offset: 0x11C */
uint8_t RESERVED_3[1760];
struct{ /* offset: 0x800, array step: 0x40 */
__IO uint32_t CR ; /* Channel N Control Register, offset: 0x800 */
__I uint32_t SR ; /* Channel N Status Register, offset: 0x804 */
__IO uint32_t SCR ; /* Channel N Status Control Register, offset: 0x808 */
__I uint32_t EFR ; /* Channel N Event and Flag Register, offset: 0x80c */
uint8_t RESERVED_4[48];
} CH[TPU_H_CH_COUNT];
} TPU_H_Type, *TPU_H_MemMapPtr;
/** Number of instances of the TPU_H module. */
#define TPU_H_INSTANCE_COUNT (1u)
/* TPU_H - Peripheral instance base addresses */
/** Peripheral TPU_H base address */
#define TPU_H_BASE (0x40445000u)
/** Peripheral TPU_H base pointer */
#define TPU_H ((TPU_H_Type *)TPU_H_BASE)
/** Array initializer of TPU_H peripheral base addresses */
#define TPU_H_BASE_ADDRS {TPU_H_BASE}
/** Array initializer of TPU_H peripheral base pointers */
#define TPU_H_BASE_PTRS {TPU_H}
// need fill by yourself
///** Number of interrupt vector arrays for the TPU_H module. */
//#define TPU_H_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the TPU_H module. */
//#define TPU_H_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the TPU_H peripheral type */
//#define TPU_H_IRQS {TPU_H_IRQn}
/* ----------------------------------------------------------------------------
-- TPU_H Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TPU_H_Register_Masks TPU_H Register Masks
* @{
*/
/* GCR_VSR Bit Fields */
#define TPU_H_GCR_VSR_SR_MASK 0xFFFFFFFFu
#define TPU_H_GCR_VSR_SR_SHIFT 0u
#define TPU_H_GCR_VSR_SR_WIDTH 32u
#define TPU_H_GCR_VSR_SR(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_VSR_SR_SHIFT))&TPU_H_GCR_VSR_SR_MASK)
/* GCR_VSR Reg Mask */
#define TPU_H_GCR_VSR_MASK 0xFFFFFFFFu
/* GCR_VIR Bit Fields */
#define TPU_H_GCR_VIR_PSTI_MASK 0xFFFFFFFFu
#define TPU_H_GCR_VIR_PSTI_SHIFT 0u
#define TPU_H_GCR_VIR_PSTI_WIDTH 32u
#define TPU_H_GCR_VIR_PSTI(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_VIR_PSTI_SHIFT))&TPU_H_GCR_VIR_PSTI_MASK)
/* GCR_VIR Reg Mask */
#define TPU_H_GCR_VIR_MASK 0xFFFFFFFFu
/* GCR_VOR Bit Fields */
#define TPU_H_GCR_VOR_PSTO_MASK 0xFFFFFFFFu
#define TPU_H_GCR_VOR_PSTO_SHIFT 0u
#define TPU_H_GCR_VOR_PSTO_WIDTH 32u
#define TPU_H_GCR_VOR_PSTO(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_VOR_PSTO_SHIFT))&TPU_H_GCR_VOR_PSTO_MASK)
/* GCR_VOR Reg Mask */
#define TPU_H_GCR_VOR_MASK 0xFFFFFFFFu
/* GCR_VOBR Bit Fields */
#define TPU_H_GCR_VOBR_PSTOE_MASK 0xFFFFFFFFu
#define TPU_H_GCR_VOBR_PSTOE_SHIFT 0u
#define TPU_H_GCR_VOBR_PSTOE_WIDTH 32u
#define TPU_H_GCR_VOBR_PSTOE(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_VOBR_PSTOE_SHIFT))&TPU_H_GCR_VOBR_PSTOE_MASK)
/* GCR_VOBR Reg Mask */
#define TPU_H_GCR_VOBR_MASK 0xFFFFFFFFu
/* GCR_VM1R Bit Fields */
#define TPU_H_GCR_VM1R_M1R_MASK 0xFFFFFFFFu
#define TPU_H_GCR_VM1R_M1R_SHIFT 0u
#define TPU_H_GCR_VM1R_M1R_WIDTH 32u
#define TPU_H_GCR_VM1R_M1R(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_VM1R_M1R_SHIFT))&TPU_H_GCR_VM1R_M1R_MASK)
/* GCR_VM1R Reg Mask */
#define TPU_H_GCR_VM1R_MASK 0xFFFFFFFFu
/* GCR_VM2R Bit Fields */
#define TPU_H_GCR_VM2R_M2R_MASK 0xFFFFFFFFu
#define TPU_H_GCR_VM2R_M2R_SHIFT 0u
#define TPU_H_GCR_VM2R_M2R_WIDTH 32u
#define TPU_H_GCR_VM2R_M2R(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_VM2R_M2R_SHIFT))&TPU_H_GCR_VM2R_M2R_MASK)
/* GCR_VM2R Reg Mask */
#define TPU_H_GCR_VM2R_MASK 0xFFFFFFFFu
/* GCR_VT1R Bit Fields */
#define TPU_H_GCR_VT1R_T1R_MASK 0xFFFFFFFFu
#define TPU_H_GCR_VT1R_T1R_SHIFT 0u
#define TPU_H_GCR_VT1R_T1R_WIDTH 32u
#define TPU_H_GCR_VT1R_T1R(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_VT1R_T1R_SHIFT))&TPU_H_GCR_VT1R_T1R_MASK)
/* GCR_VT1R Reg Mask */
#define TPU_H_GCR_VT1R_MASK 0xFFFFFFFFu
/* GCR_VT2R Bit Fields */
#define TPU_H_GCR_VT2R_T2R_MASK 0xFFFFFFFFu
#define TPU_H_GCR_VT2R_T2R_SHIFT 0u
#define TPU_H_GCR_VT2R_T2R_WIDTH 32u
#define TPU_H_GCR_VT2R_T2R(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_VT2R_T2R_SHIFT))&TPU_H_GCR_VT2R_T2R_MASK)
/* GCR_VT2R Reg Mask */
#define TPU_H_GCR_VT2R_MASK 0xFFFFFFFFu
/* GCR_EM1R Bit Fields */
#define TPU_H_GCR_EM1R_EM1R_MASK 0xFFFFFFFFu
#define TPU_H_GCR_EM1R_EM1R_SHIFT 0u
#define TPU_H_GCR_EM1R_EM1R_WIDTH 32u
#define TPU_H_GCR_EM1R_EM1R(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_EM1R_EM1R_SHIFT))&TPU_H_GCR_EM1R_EM1R_MASK)
/* GCR_EM1R Reg Mask */
#define TPU_H_GCR_EM1R_MASK 0xFFFFFFFFu
/* GCR_EM2R Bit Fields */
#define TPU_H_GCR_EM2R_EM2R_MASK 0xFFFFFFFFu
#define TPU_H_GCR_EM2R_EM2R_SHIFT 0u
#define TPU_H_GCR_EM2R_EM2R_WIDTH 32u
#define TPU_H_GCR_EM2R_EM2R(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_EM2R_EM2R_SHIFT))&TPU_H_GCR_EM2R_EM2R_MASK)
/* GCR_EM2R Reg Mask */
#define TPU_H_GCR_EM2R_MASK 0xFFFFFFFFu
/* GCR_ET1R Bit Fields */
#define TPU_H_GCR_ET1R_ET1R_MASK 0xFFFFFFFFu
#define TPU_H_GCR_ET1R_ET1R_SHIFT 0u
#define TPU_H_GCR_ET1R_ET1R_WIDTH 32u
#define TPU_H_GCR_ET1R_ET1R(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_ET1R_ET1R_SHIFT))&TPU_H_GCR_ET1R_ET1R_MASK)
/* GCR_ET1R Reg Mask */
#define TPU_H_GCR_ET1R_MASK 0xFFFFFFFFu
/* GCR_ET2R Bit Fields */
#define TPU_H_GCR_ET2R_ET2R_MASK 0xFFFFFFFFu
#define TPU_H_GCR_ET2R_ET2R_SHIFT 0u
#define TPU_H_GCR_ET2R_ET2R_WIDTH 32u
#define TPU_H_GCR_ET2R_ET2R(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_ET2R_ET2R_SHIFT))&TPU_H_GCR_ET2R_ET2R_MASK)
/* GCR_ET2R Reg Mask */
#define TPU_H_GCR_ET2R_MASK 0xFFFFFFFFu
/* GCR_VHSR Bit Fields */
#define TPU_H_GCR_VHSR_HAS_MASK 0xFFFFFFFFu
#define TPU_H_GCR_VHSR_HAS_SHIFT 0u
#define TPU_H_GCR_VHSR_HAS_WIDTH 32u
#define TPU_H_GCR_VHSR_HAS(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_GCR_VHSR_HAS_SHIFT))&TPU_H_GCR_VHSR_HAS_MASK)
/* GCR_VHSR Reg Mask */
#define TPU_H_GCR_VHSR_MASK 0xFFFFFFFFu
/* TBR_CR Bit Fields */
#define TPU_H_TBR_CR_TCR1P_MASK 0xFF000000u
#define TPU_H_TBR_CR_TCR1P_SHIFT 24u
#define TPU_H_TBR_CR_TCR1P_WIDTH 8u
#define TPU_H_TBR_CR_TCR1P(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_CR_TCR1P_SHIFT))&TPU_H_TBR_CR_TCR1P_MASK)
#define TPU_H_TBR_CR_TCR1CTL_MASK 0x70000u
#define TPU_H_TBR_CR_TCR1CTL_SHIFT 16u
#define TPU_H_TBR_CR_TCR1CTL_WIDTH 3u
#define TPU_H_TBR_CR_TCR1CTL(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_CR_TCR1CTL_SHIFT))&TPU_H_TBR_CR_TCR1CTL_MASK)
#define TPU_H_TBR_CR_TCR2P_MASK 0xFC00u
#define TPU_H_TBR_CR_TCR2P_SHIFT 10u
#define TPU_H_TBR_CR_TCR2P_WIDTH 6u
#define TPU_H_TBR_CR_TCR2P(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_CR_TCR2P_SHIFT))&TPU_H_TBR_CR_TCR2P_MASK)
#define TPU_H_TBR_CR_ATGC_MASK 0x80u
#define TPU_H_TBR_CR_ATGC_SHIFT 7u
#define TPU_H_TBR_CR_ATGC_WIDTH 1u
#define TPU_H_TBR_CR_ATGC(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_CR_ATGC_SHIFT))&TPU_H_TBR_CR_ATGC_MASK)
#define TPU_H_TBR_CR_AM_MASK 0x60u
#define TPU_H_TBR_CR_AM_SHIFT 5u
#define TPU_H_TBR_CR_AM_WIDTH 2u
#define TPU_H_TBR_CR_AM(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_CR_AM_SHIFT))&TPU_H_TBR_CR_AM_MASK)
#define TPU_H_TBR_CR_TCRCF_MASK 0x18u
#define TPU_H_TBR_CR_TCRCF_SHIFT 3u
#define TPU_H_TBR_CR_TCRCF_WIDTH 2u
#define TPU_H_TBR_CR_TCRCF(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_CR_TCRCF_SHIFT))&TPU_H_TBR_CR_TCRCF_MASK)
#define TPU_H_TBR_CR_TCR2CTL_MASK 0x7u
#define TPU_H_TBR_CR_TCR2CTL_SHIFT 0u
#define TPU_H_TBR_CR_TCR2CTL_WIDTH 3u
#define TPU_H_TBR_CR_TCR2CTL(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_CR_TCR2CTL_SHIFT))&TPU_H_TBR_CR_TCR2CTL_MASK)
/* TBR_CR Reg Mask */
#define TPU_H_TBR_CR_MASK 0xFF07FCFFu
/* TBR_T1R Bit Fields */
#define TPU_H_TBR_T1R_TCR1_MASK 0xFFFFFFu
#define TPU_H_TBR_T1R_TCR1_SHIFT 0u
#define TPU_H_TBR_T1R_TCR1_WIDTH 24u
#define TPU_H_TBR_T1R_TCR1(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_T1R_TCR1_SHIFT))&TPU_H_TBR_T1R_TCR1_MASK)
/* TBR_T1R Reg Mask */
#define TPU_H_TBR_T1R_MASK 0x00FFFFFFu
/* TBR_T2R Bit Fields */
#define TPU_H_TBR_T2R_TCR2_MASK 0xFFFFFFu
#define TPU_H_TBR_T2R_TCR2_SHIFT 0u
#define TPU_H_TBR_T2R_TCR2_WIDTH 24u
#define TPU_H_TBR_T2R_TCR2(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_T2R_TCR2_SHIFT))&TPU_H_TBR_T2R_TCR2_MASK)
/* TBR_T2R Reg Mask */
#define TPU_H_TBR_T2R_MASK 0x00FFFFFFu
/* TBR_TPR Bit Fields */
#define TPU_H_TBR_TPR_LAST_MASK 0x8000u
#define TPU_H_TBR_TPR_LAST_SHIFT 15u
#define TPU_H_TBR_TPR_LAST_WIDTH 1u
#define TPU_H_TBR_TPR_LAST(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_TPR_LAST_SHIFT))&TPU_H_TBR_TPR_LAST_MASK)
#define TPU_H_TBR_TPR_MISSCNT_MASK 0x6000u
#define TPU_H_TBR_TPR_MISSCNT_SHIFT 13u
#define TPU_H_TBR_TPR_MISSCNT_WIDTH 2u
#define TPU_H_TBR_TPR_MISSCNT(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_TPR_MISSCNT_SHIFT))&TPU_H_TBR_TPR_MISSCNT_MASK)
#define TPU_H_TBR_TPR_IPH_MASK 0x1000u
#define TPU_H_TBR_TPR_IPH_SHIFT 12u
#define TPU_H_TBR_TPR_IPH_WIDTH 1u
#define TPU_H_TBR_TPR_IPH(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_TPR_IPH_SHIFT))&TPU_H_TBR_TPR_IPH_MASK)
#define TPU_H_TBR_TPR_HOLD_MASK 0x800u
#define TPU_H_TBR_TPR_HOLD_SHIFT 11u
#define TPU_H_TBR_TPR_HOLD_WIDTH 1u
#define TPU_H_TBR_TPR_HOLD(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_TPR_HOLD_SHIFT))&TPU_H_TBR_TPR_HOLD_MASK)
#define TPU_H_TBR_TPR_TPR10_MASK 0x400u
#define TPU_H_TBR_TPR_TPR10_SHIFT 10u
#define TPU_H_TBR_TPR_TPR10_WIDTH 1u
#define TPU_H_TBR_TPR_TPR10(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_TPR_TPR10_SHIFT))&TPU_H_TBR_TPR_TPR10_MASK)
#define TPU_H_TBR_TPR_TICKS_MASK 0x3FFu
#define TPU_H_TBR_TPR_TICKS_SHIFT 0u
#define TPU_H_TBR_TPR_TICKS_WIDTH 10u
#define TPU_H_TBR_TPR_TICKS(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_TPR_TICKS_SHIFT))&TPU_H_TBR_TPR_TICKS_MASK)
/* TBR_TPR Reg Mask */
#define TPU_H_TBR_TPR_MASK 0x0000FFFFu
/* TBR_TRR Bit Fields */
#define TPU_H_TBR_TRR_INTEGER_MASK 0xFFFE00u
#define TPU_H_TBR_TRR_INTEGER_SHIFT 9u
#define TPU_H_TBR_TRR_INTEGER_WIDTH 15u
#define TPU_H_TBR_TRR_INTEGER(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_TRR_INTEGER_SHIFT))&TPU_H_TBR_TRR_INTEGER_MASK)
#define TPU_H_TBR_TRR_FRACTION_MASK 0x1FFu
#define TPU_H_TBR_TRR_FRACTION_SHIFT 0u
#define TPU_H_TBR_TRR_FRACTION_WIDTH 9u
#define TPU_H_TBR_TRR_FRACTION(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_TRR_FRACTION_SHIFT))&TPU_H_TBR_TRR_FRACTION_MASK)
/* TBR_TRR Reg Mask */
#define TPU_H_TBR_TRR_MASK 0x00FFFFFFu
/* TBR_T1MR Bit Fields */
#define TPU_H_TBR_T1MR_OVF_MASK 0x80000000u
#define TPU_H_TBR_T1MR_OVF_SHIFT 31u
#define TPU_H_TBR_T1MR_OVF_WIDTH 1u
#define TPU_H_TBR_T1MR_OVF(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_T1MR_OVF_SHIFT))&TPU_H_TBR_T1MR_OVF_MASK)
#define TPU_H_TBR_T1MR_IRQ_EN_MASK 0x8000000u
#define TPU_H_TBR_T1MR_IRQ_EN_SHIFT 27u
#define TPU_H_TBR_T1MR_IRQ_EN_WIDTH 1u
#define TPU_H_TBR_T1MR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_T1MR_IRQ_EN_SHIFT))&TPU_H_TBR_T1MR_IRQ_EN_MASK)
#define TPU_H_TBR_T1MR_MAX_MASK 0xFFFFFFu
#define TPU_H_TBR_T1MR_MAX_SHIFT 0u
#define TPU_H_TBR_T1MR_MAX_WIDTH 24u
#define TPU_H_TBR_T1MR_MAX(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_T1MR_MAX_SHIFT))&TPU_H_TBR_T1MR_MAX_MASK)
/* TBR_T1MR Reg Mask */
#define TPU_H_TBR_T1MR_MASK 0x88FFFFFFu
/* TBR_T2MR Bit Fields */
#define TPU_H_TBR_T2MR_OVF_MASK 0x80000000u
#define TPU_H_TBR_T2MR_OVF_SHIFT 31u
#define TPU_H_TBR_T2MR_OVF_WIDTH 1u
#define TPU_H_TBR_T2MR_OVF(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_T2MR_OVF_SHIFT))&TPU_H_TBR_T2MR_OVF_MASK)
#define TPU_H_TBR_T2MR_IRQ_EN_MASK 0x8000000u
#define TPU_H_TBR_T2MR_IRQ_EN_SHIFT 27u
#define TPU_H_TBR_T2MR_IRQ_EN_WIDTH 1u
#define TPU_H_TBR_T2MR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_T2MR_IRQ_EN_SHIFT))&TPU_H_TBR_T2MR_IRQ_EN_MASK)
#define TPU_H_TBR_T2MR_MAX_MASK 0xFFFFFFu
#define TPU_H_TBR_T2MR_MAX_SHIFT 0u
#define TPU_H_TBR_T2MR_MAX_WIDTH 24u
#define TPU_H_TBR_T2MR_MAX(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_TBR_T2MR_MAX_SHIFT))&TPU_H_TBR_T2MR_MAX_MASK)
/* TBR_T2MR Reg Mask */
#define TPU_H_TBR_T2MR_MASK 0x88FFFFFFu
/* CHn_CR Bit Fields */
#define TPU_H_CHn_CR_CHAE_MASK 0x8000u
#define TPU_H_CHn_CR_CHAE_SHIFT 15u
#define TPU_H_CHn_CR_CHAE_WIDTH 1u
#define TPU_H_CHn_CR_CHAE(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_CR_CHAE_SHIFT))&TPU_H_CHn_CR_CHAE_MASK)
#define TPU_H_CHn_CR_CHDE_MASK 0x4000u
#define TPU_H_CHn_CR_CHDE_SHIFT 14u
#define TPU_H_CHn_CR_CHDE_WIDTH 1u
#define TPU_H_CHn_CR_CHDE(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_CR_CHDE_SHIFT))&TPU_H_CHn_CR_CHDE_MASK)
#define TPU_H_CHn_CR_CHEE_MASK 0x2000u
#define TPU_H_CHn_CR_CHEE_SHIFT 13u
#define TPU_H_CHn_CR_CHEE_WIDTH 1u
#define TPU_H_CHn_CR_CHEE(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_CR_CHEE_SHIFT))&TPU_H_CHn_CR_CHEE_MASK)
#define TPU_H_CHn_CR_CTC_MASK 0x1E00u
#define TPU_H_CHn_CR_CTC_SHIFT 9u
#define TPU_H_CHn_CR_CTC_WIDTH 4u
#define TPU_H_CHn_CR_CTC(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_CR_CTC_SHIFT))&TPU_H_CHn_CR_CTC_MASK)
#define TPU_H_CHn_CR_CDFD_MASK 0x100u
#define TPU_H_CHn_CR_CDFD_SHIFT 8u
#define TPU_H_CHn_CR_CDFD_WIDTH 1u
#define TPU_H_CHn_CR_CDFD(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_CR_CDFD_SHIFT))&TPU_H_CHn_CR_CDFD_MASK)
#define TPU_H_CHn_CR_CHSR_MASK 0x7u
#define TPU_H_CHn_CR_CHSR_SHIFT 0u
#define TPU_H_CHn_CR_CHSR_WIDTH 3u
#define TPU_H_CHn_CR_CHSR(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_CR_CHSR_SHIFT))&TPU_H_CHn_CR_CHSR_MASK)
/* CH0_CR Reg Mask */
#define TPU_H_CHn_CR_MASK 0x0000FF07u
/* CHn_SR Bit Fields */
#define TPU_H_CHn_SR_CIS_MASK 0x80000000u
#define TPU_H_CHn_SR_CIS_SHIFT 31u
#define TPU_H_CHn_SR_CIS_WIDTH 1u
#define TPU_H_CHn_SR_CIS(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_SR_CIS_SHIFT))&TPU_H_CHn_SR_CIS_MASK)
#define TPU_H_CHn_SR_CHRS_MASK 0x1000000u
#define TPU_H_CHn_SR_CHRS_SHIFT 24u
#define TPU_H_CHn_SR_CHRS_WIDTH 1u
#define TPU_H_CHn_SR_CHRS(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_SR_CHRS_SHIFT))&TPU_H_CHn_SR_CHRS_MASK)
#define TPU_H_CHn_SR_CHRI_MASK 0x70000u
#define TPU_H_CHn_SR_CHRI_SHIFT 16u
#define TPU_H_CHn_SR_CHRI_WIDTH 3u
#define TPU_H_CHn_SR_CHRI(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_SR_CHRI_SHIFT))&TPU_H_CHn_SR_CHRI_MASK)
#define TPU_H_CHn_SR_CEIS_MASK 0x8000u
#define TPU_H_CHn_SR_CEIS_SHIFT 15u
#define TPU_H_CHn_SR_CEIS_WIDTH 1u
#define TPU_H_CHn_SR_CEIS(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_SR_CEIS_SHIFT))&TPU_H_CHn_SR_CEIS_MASK)
#define TPU_H_CHn_SR_CHDS_MASK 0x4000u
#define TPU_H_CHn_SR_CHDS_SHIFT 14u
#define TPU_H_CHn_SR_CHDS_WIDTH 1u
#define TPU_H_CHn_SR_CHDS(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_SR_CHDS_SHIFT))&TPU_H_CHn_SR_CHDS_MASK)
#define TPU_H_CHn_SR_CTS_MASK 0x1000u
#define TPU_H_CHn_SR_CTS_SHIFT 12u
#define TPU_H_CHn_SR_CTS_WIDTH 1u
#define TPU_H_CHn_SR_CTS(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_SR_CTS_SHIFT))&TPU_H_CHn_SR_CTS_MASK)
#define TPU_H_CHn_SR_CHAS_MASK 0x100u
#define TPU_H_CHn_SR_CHAS_SHIFT 8u
#define TPU_H_CHn_SR_CHAS_WIDTH 1u
#define TPU_H_CHn_SR_CHAS(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_SR_CHAS_SHIFT))&TPU_H_CHn_SR_CHAS_MASK)
/* CH0_SR Reg Mask */
#define TPU_H_CHn_SR_MASK 0x8107D100u
/* CHn_SCR Bit Fields */
#define TPU_H_CHn_SCR_CEIC_MASK 0x8000u
#define TPU_H_CHn_SCR_CEIC_SHIFT 15u
#define TPU_H_CHn_SCR_CEIC_WIDTH 1u
#define TPU_H_CHn_SCR_CEIC(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_SCR_CEIC_SHIFT))&TPU_H_CHn_SCR_CEIC_MASK)
#define TPU_H_CHn_SCR_CHAC_MASK 0x100u
#define TPU_H_CHn_SCR_CHAC_SHIFT 8u
#define TPU_H_CHn_SCR_CHAC_WIDTH 1u
#define TPU_H_CHn_SCR_CHAC(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_SCR_CHAC_SHIFT))&TPU_H_CHn_SCR_CHAC_MASK)
#define TPU_H_CHn_SCR_CHRT_MASK 0x1u
#define TPU_H_CHn_SCR_CHRT_SHIFT 0u
#define TPU_H_CHn_SCR_CHRT_WIDTH 1u
#define TPU_H_CHn_SCR_CHRT(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_SCR_CHRT_SHIFT))&TPU_H_CHn_SCR_CHRT_MASK)
/* CH0_SCR Reg Mask */
#define TPU_H_CHn_SCR_MASK 0x00008101u
/* CHn_EFR Bit Fields */
#define TPU_H_CHn_EFR_CSR_MASK 0x80000000u
#define TPU_H_CHn_EFR_CSR_SHIFT 31u
#define TPU_H_CHn_EFR_CSR_WIDTH 1u
#define TPU_H_CHn_EFR_CSR(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_EFR_CSR_SHIFT))&TPU_H_CHn_EFR_CSR_MASK)
#define TPU_H_CHn_EFR_CHSR_MASK 0x40000000u
#define TPU_H_CHn_EFR_CHSR_SHIFT 30u
#define TPU_H_CHn_EFR_CHSR_WIDTH 1u
#define TPU_H_CHn_EFR_CHSR(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_EFR_CHSR_SHIFT))&TPU_H_CHn_EFR_CHSR_MASK)
#define TPU_H_CHn_EFR_EMRL1_MASK 0x200u
#define TPU_H_CHn_EFR_EMRL1_SHIFT 9u
#define TPU_H_CHn_EFR_EMRL1_WIDTH 1u
#define TPU_H_CHn_EFR_EMRL1(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_EFR_EMRL1_SHIFT))&TPU_H_CHn_EFR_EMRL1_MASK)
#define TPU_H_CHn_EFR_EMRL2_MASK 0x100u
#define TPU_H_CHn_EFR_EMRL2_SHIFT 8u
#define TPU_H_CHn_EFR_EMRL2_WIDTH 1u
#define TPU_H_CHn_EFR_EMRL2(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_EFR_EMRL2_SHIFT))&TPU_H_CHn_EFR_EMRL2_MASK)
#define TPU_H_CHn_EFR_ETDL1_MASK 0x80u
#define TPU_H_CHn_EFR_ETDL1_SHIFT 7u
#define TPU_H_CHn_EFR_ETDL1_WIDTH 1u
#define TPU_H_CHn_EFR_ETDL1(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_EFR_ETDL1_SHIFT))&TPU_H_CHn_EFR_ETDL1_MASK)
#define TPU_H_CHn_EFR_ETDL2_MASK 0x40u
#define TPU_H_CHn_EFR_ETDL2_SHIFT 6u
#define TPU_H_CHn_EFR_ETDL2_WIDTH 1u
#define TPU_H_CHn_EFR_ETDL2(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_EFR_ETDL2_SHIFT))&TPU_H_CHn_EFR_ETDL2_MASK)
#define TPU_H_CHn_EFR_MRLE1_MASK 0x20u
#define TPU_H_CHn_EFR_MRLE1_SHIFT 5u
#define TPU_H_CHn_EFR_MRLE1_WIDTH 1u
#define TPU_H_CHn_EFR_MRLE1(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_EFR_MRLE1_SHIFT))&TPU_H_CHn_EFR_MRLE1_MASK)
#define TPU_H_CHn_EFR_MRLE2_MASK 0x10u
#define TPU_H_CHn_EFR_MRLE2_SHIFT 4u
#define TPU_H_CHn_EFR_MRLE2_WIDTH 1u
#define TPU_H_CHn_EFR_MRLE2(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_EFR_MRLE2_SHIFT))&TPU_H_CHn_EFR_MRLE2_MASK)
#define TPU_H_CHn_EFR_MRL1_MASK 0x8u
#define TPU_H_CHn_EFR_MRL1_SHIFT 3u
#define TPU_H_CHn_EFR_MRL1_WIDTH 1u
#define TPU_H_CHn_EFR_MRL1(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_EFR_MRL1_SHIFT))&TPU_H_CHn_EFR_MRL1_MASK)
#define TPU_H_CHn_EFR_MRL2_MASK 0x4u
#define TPU_H_CHn_EFR_MRL2_SHIFT 2u
#define TPU_H_CHn_EFR_MRL2_WIDTH 1u
#define TPU_H_CHn_EFR_MRL2(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_EFR_MRL2_SHIFT))&TPU_H_CHn_EFR_MRL2_MASK)
#define TPU_H_CHn_EFR_TDL1_MASK 0x2u
#define TPU_H_CHn_EFR_TDL1_SHIFT 1u
#define TPU_H_CHn_EFR_TDL1_WIDTH 1u
#define TPU_H_CHn_EFR_TDL1(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_EFR_TDL1_SHIFT))&TPU_H_CHn_EFR_TDL1_MASK)
#define TPU_H_CHn_EFR_TDL2_MASK 0x1u
#define TPU_H_CHn_EFR_TDL2_SHIFT 0u
#define TPU_H_CHn_EFR_TDL2_WIDTH 1u
#define TPU_H_CHn_EFR_TDL2(x) (((uint32_t)(((uint32_t)(x))<<TPU_H_CHn_EFR_TDL2_SHIFT))&TPU_H_CHn_EFR_TDL2_MASK)
/* CH0_EFR Reg Mask */
#define TPU_H_CHn_EFR_MASK 0xC00003FFu
/*!
* @}
*/ /* end of group TPU_H_Register_Masks */
/*!
* @}
*/ /* end of group TPU_H_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_TRGSEL_NU_Tztufn48_REGS_H_
#define _FC7240_TRGSEL_NU_Tztufn48_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- TRGSEL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRGSEL_Peripheral_Access_Layer TRGSEL Peripheral Access Layer
* @{
*/
/** TRGSEL - Size of Registers Arrays */
/** TRGSEL - Register Layout Typedef */
#define TRGSEL_OUT_SEL_COUNT 32
typedef struct {
__IO uint32_t OUT_SEL[TRGSEL_OUT_SEL_COUNT] ; /* OUT SEL for N, offset: 0x0 */
} TRGSEL_Type, *TRGSEL_MemMapPtr;
/** Number of instances of the TRGSEL module. */
#define TRGSEL_INSTANCE_COUNT (6u)
/* TRGSEL - Peripheral instance base addresses */
/** Peripheral TRGSEL0 base address */
#define TRGSEL0_BASE (0x40026000u)
/** Peripheral TRGSEL0 base pointer */
#define TRGSEL0 ((TRGSEL_Type *)TRGSEL0_BASE)
/** Peripheral TRGSEL1 base address */
#define TRGSEL1_BASE (0x40027000u)
/** Peripheral TRGSEL1 base pointer */
#define TRGSEL1 ((TRGSEL_Type *)TRGSEL1_BASE)
/** Peripheral TRGSEL2 base address */
#define TRGSEL2_BASE (0x40028000u)
/** Peripheral TRGSEL2 base pointer */
#define TRGSEL2 ((TRGSEL_Type *)TRGSEL2_BASE)
/** Peripheral TRGSEL3 base address */
#define TRGSEL3_BASE (0x40029000u)
/** Peripheral TRGSEL3 base pointer */
#define TRGSEL3 ((TRGSEL_Type *)TRGSEL3_BASE)
/** Peripheral TRGSEL4 base address */
#define TRGSEL4_BASE (0x4043b000u)
/** Peripheral TRGSEL4 base pointer */
#define TRGSEL4 ((TRGSEL_Type *)TRGSEL4_BASE)
/** Peripheral TRGSEL5 base address */
#define TRGSEL5_BASE (0x4043c000u)
/** Peripheral TRGSEL5 base pointer */
#define TRGSEL5 ((TRGSEL_Type *)TRGSEL5_BASE)
/** Array initializer of TRGSEL peripheral base addresses */
#define TRGSEL_BASE_ADDRS {TRGSEL0_BASE, TRGSEL1_BASE, TRGSEL2_BASE, TRGSEL3_BASE, TRGSEL4_BASE, TRGSEL5_BASE}
/** Array initializer of TRGSEL peripheral base pointers */
#define TRGSEL_BASE_PTRS {TRGSEL0, TRGSEL1, TRGSEL2, TRGSEL3, TRGSEL4, TRGSEL5}
// need fill by yourself
///** Number of interrupt vector arrays for the TRGSEL module. */
//#define TRGSEL_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the TRGSEL module. */
//#define TRGSEL_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the TRGSEL peripheral type */
//#define TRGSEL_IRQS {TRGSEL0_IRQn, TRGSEL1_IRQn, TRGSEL2_IRQn, TRGSEL3_IRQn, TRGSEL4_IRQn, TRGSEL5_IRQn}
/* ----------------------------------------------------------------------------
-- TRGSEL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TRGSEL_Register_Masks TRGSEL Register Masks
* @{
*/
/* OUT_SEL Bit Fields */
#define TRGSEL_OUT_SEL_LOCK_MASK 0x80000000u
#define TRGSEL_OUT_SEL_LOCK_SHIFT 31u
#define TRGSEL_OUT_SEL_LOCK_WIDTH 1u
#define TRGSEL_OUT_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x))<<TRGSEL_OUT_SEL_LOCK_SHIFT))&TRGSEL_OUT_SEL_LOCK_MASK)
#define TRGSEL_OUT_SEL_SEL_3_MASK 0x7F000000u
#define TRGSEL_OUT_SEL_SEL_3_SHIFT 24u
#define TRGSEL_OUT_SEL_SEL_3_WIDTH 7u
#define TRGSEL_OUT_SEL_SEL_3(x) (((uint32_t)(((uint32_t)(x))<<TRGSEL_OUT_SEL_SEL_3_SHIFT))&TRGSEL_OUT_SEL_SEL_3_MASK)
#define TRGSEL_OUT_SEL_SEL_2_MASK 0x7F0000u
#define TRGSEL_OUT_SEL_SEL_2_SHIFT 16u
#define TRGSEL_OUT_SEL_SEL_2_WIDTH 7u
#define TRGSEL_OUT_SEL_SEL_2(x) (((uint32_t)(((uint32_t)(x))<<TRGSEL_OUT_SEL_SEL_2_SHIFT))&TRGSEL_OUT_SEL_SEL_2_MASK)
#define TRGSEL_OUT_SEL_SEL_1_MASK 0x7F00u
#define TRGSEL_OUT_SEL_SEL_1_SHIFT 8u
#define TRGSEL_OUT_SEL_SEL_1_WIDTH 7u
#define TRGSEL_OUT_SEL_SEL_1(x) (((uint32_t)(((uint32_t)(x))<<TRGSEL_OUT_SEL_SEL_1_SHIFT))&TRGSEL_OUT_SEL_SEL_1_MASK)
#define TRGSEL_OUT_SEL_SEL_0_MASK 0x7Fu
#define TRGSEL_OUT_SEL_SEL_0_SHIFT 0u
#define TRGSEL_OUT_SEL_SEL_0_WIDTH 7u
#define TRGSEL_OUT_SEL_SEL_0(x) (((uint32_t)(((uint32_t)(x))<<TRGSEL_OUT_SEL_SEL_0_SHIFT))&TRGSEL_OUT_SEL_SEL_0_MASK)
/* OUT_SEL0 Reg Mask */
#define TRGSEL_OUT_SEL_MASK 0xFF7F7F7Fu
/*!
* @}
*/ /* end of group TRGSEL_Register_Masks */
/*!
* @}
*/ /* end of group TRGSEL_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7240_tstmp_regs.h Normal file
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#ifndef _FC7240_TSTMP_NU_Tztufn45_REGS_H_
#define _FC7240_TSTMP_NU_Tztufn45_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- TSTMP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSTMP_Peripheral_Access_Layer TSTMP Peripheral Access Layer
* @{
*/
/** TSTMP - Size of Registers Arrays */
/** TSTMP - Register Layout Typedef */
typedef struct {
__I uint32_t VALL ; /* Low Value Register, offset: 0x0 */
__I uint32_t VALH ; /* High Value Register, offset: 0x4 */
__IO uint32_t MOD_INTEN ; /* Modulate Interrupt Enable Register, offset: 0x8 */
__IO uint32_t MOD_STATUS ; /* Modulate Status Register, offset: 0xC */
__IO uint32_t MOD0_SETVAL ; /* Modulate0 Set Value Register, offset: 0x10 */
__IO uint32_t MOD1_SETVAL ; /* Modulate1 Set Value Register, offset: 0x14 */
__IO uint32_t MOD2_SETVAL ; /* Modulate2 Set Value Register, offset: 0x18 */
__IO uint32_t MOD3_SETVAL ; /* Modulate3 Set Value Register, offset: 0x1C */
} TSTMP_Type, *TSTMP_MemMapPtr;
/** Number of instances of the TSTMP module. */
#define TSTMP_INSTANCE_COUNT (2u)
/** Number of modulate of each TSTMP module. */
#define TSTMP_MODULATE_COUNT (4u)
/* TSTMP - Peripheral instance base addresses */
/** Peripheral TSTMP0 base address */
#define TSTMP0_BASE (0x4002c000u)
/** Peripheral TSTMP0 base pointer */
#define TSTMP0 ((TSTMP_Type *)TSTMP0_BASE)
/** Peripheral TSTMP1 base address */
#define TSTMP1_BASE (0x4002d000u)
/** Peripheral TSTMP1 base pointer */
#define TSTMP1 ((TSTMP_Type *)TSTMP1_BASE)
/** Array initializer of TSTMP peripheral base addresses */
#define TSTMP_BASE_ADDRS {TSTMP0_BASE, TSTMP1_BASE}
/** Array initializer of TSTMP peripheral base pointers */
#define TSTMP_BASE_PTRS {TSTMP0, TSTMP1}
// need fill by yourself
///** Number of interrupt vector arrays for the TSTMP module. */
//#define TSTMP_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the TSTMP module. */
//#define TSTMP_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the TSTMP peripheral type */
//#define TSTMP_IRQS {TSTMP0_IRQn, TSTMP1_IRQn}
/* ----------------------------------------------------------------------------
-- TSTMP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TSTMP_Register_Masks TSTMP Register Masks
* @{
*/
/* VALL Bit Fields */
#define TSTMP_VALL_TVALL_MASK 0xFFFFFFFFu
#define TSTMP_VALL_TVALL_SHIFT 0u
#define TSTMP_VALL_TVALL_WIDTH 32u
#define TSTMP_VALL_TVALL(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_VALL_TVALL_SHIFT))&TSTMP_VALL_TVALL_MASK)
/* VALL Reg Mask */
#define TSTMP_VALL_MASK 0xFFFFFFFFu
/* VALH Bit Fields */
#define TSTMP_VALH_TVALH_MASK 0xFFFFFFu
#define TSTMP_VALH_TVALH_SHIFT 0u
#define TSTMP_VALH_TVALH_WIDTH 24u
#define TSTMP_VALH_TVALH(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_VALH_TVALH_SHIFT))&TSTMP_VALH_TVALH_MASK)
/* VALH Reg Mask */
#define TSTMP_VALH_MASK 0x00FFFFFFu
/* MOD_INTEN Bit Fields */
#define TSTMP_MOD_INTEN_MOD3_CLK_MASK 0x8000000u
#define TSTMP_MOD_INTEN_MOD3_CLK_SHIFT 27u
#define TSTMP_MOD_INTEN_MOD3_CLK_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD3_CLK(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD3_CLK_SHIFT))&TSTMP_MOD_INTEN_MOD3_CLK_MASK)
#define TSTMP_MOD_INTEN_MOD2_CLK_MASK 0x4000000u
#define TSTMP_MOD_INTEN_MOD2_CLK_SHIFT 26u
#define TSTMP_MOD_INTEN_MOD2_CLK_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD2_CLK(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD2_CLK_SHIFT))&TSTMP_MOD_INTEN_MOD2_CLK_MASK)
#define TSTMP_MOD_INTEN_MOD1_CLK_MASK 0x2000000u
#define TSTMP_MOD_INTEN_MOD1_CLK_SHIFT 25u
#define TSTMP_MOD_INTEN_MOD1_CLK_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD1_CLK(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD1_CLK_SHIFT))&TSTMP_MOD_INTEN_MOD1_CLK_MASK)
#define TSTMP_MOD_INTEN_MOD0_CLK_MASK 0x1000000u
#define TSTMP_MOD_INTEN_MOD0_CLK_SHIFT 24u
#define TSTMP_MOD_INTEN_MOD0_CLK_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD0_CLK(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD0_CLK_SHIFT))&TSTMP_MOD_INTEN_MOD0_CLK_MASK)
#define TSTMP_MOD_INTEN_MOD3_ENABLE_MASK 0x80000u
#define TSTMP_MOD_INTEN_MOD3_ENABLE_SHIFT 19u
#define TSTMP_MOD_INTEN_MOD3_ENABLE_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD3_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD3_ENABLE_SHIFT))&TSTMP_MOD_INTEN_MOD3_ENABLE_MASK)
#define TSTMP_MOD_INTEN_MOD2_ENABLE_MASK 0x40000u
#define TSTMP_MOD_INTEN_MOD2_ENABLE_SHIFT 18u
#define TSTMP_MOD_INTEN_MOD2_ENABLE_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD2_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD2_ENABLE_SHIFT))&TSTMP_MOD_INTEN_MOD2_ENABLE_MASK)
#define TSTMP_MOD_INTEN_MOD1_ENABLE_MASK 0x20000u
#define TSTMP_MOD_INTEN_MOD1_ENABLE_SHIFT 17u
#define TSTMP_MOD_INTEN_MOD1_ENABLE_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD1_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD1_ENABLE_SHIFT))&TSTMP_MOD_INTEN_MOD1_ENABLE_MASK)
#define TSTMP_MOD_INTEN_MOD0_ENABLE_MASK 0x10000u
#define TSTMP_MOD_INTEN_MOD0_ENABLE_SHIFT 16u
#define TSTMP_MOD_INTEN_MOD0_ENABLE_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD0_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD0_ENABLE_SHIFT))&TSTMP_MOD_INTEN_MOD0_ENABLE_MASK)
#define TSTMP_MOD_INTEN_MOD3_MODE_MASK 0x800u
#define TSTMP_MOD_INTEN_MOD3_MODE_SHIFT 11u
#define TSTMP_MOD_INTEN_MOD3_MODE_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD3_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD3_MODE_SHIFT))&TSTMP_MOD_INTEN_MOD3_MODE_MASK)
#define TSTMP_MOD_INTEN_MOD2_MODE_MASK 0x400u
#define TSTMP_MOD_INTEN_MOD2_MODE_SHIFT 10u
#define TSTMP_MOD_INTEN_MOD2_MODE_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD2_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD2_MODE_SHIFT))&TSTMP_MOD_INTEN_MOD2_MODE_MASK)
#define TSTMP_MOD_INTEN_MOD1_MODE_MASK 0x200u
#define TSTMP_MOD_INTEN_MOD1_MODE_SHIFT 9u
#define TSTMP_MOD_INTEN_MOD1_MODE_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD1_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD1_MODE_SHIFT))&TSTMP_MOD_INTEN_MOD1_MODE_MASK)
#define TSTMP_MOD_INTEN_MOD0_MODE_MASK 0x100u
#define TSTMP_MOD_INTEN_MOD0_MODE_SHIFT 8u
#define TSTMP_MOD_INTEN_MOD0_MODE_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD0_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD0_MODE_SHIFT))&TSTMP_MOD_INTEN_MOD0_MODE_MASK)
#define TSTMP_MOD_INTEN_MOD3_INTEN_MASK 0x8u
#define TSTMP_MOD_INTEN_MOD3_INTEN_SHIFT 3u
#define TSTMP_MOD_INTEN_MOD3_INTEN_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD3_INTEN(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD3_INTEN_SHIFT))&TSTMP_MOD_INTEN_MOD3_INTEN_MASK)
#define TSTMP_MOD_INTEN_MOD2_INTEN_MASK 0x4u
#define TSTMP_MOD_INTEN_MOD2_INTEN_SHIFT 2u
#define TSTMP_MOD_INTEN_MOD2_INTEN_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD2_INTEN(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD2_INTEN_SHIFT))&TSTMP_MOD_INTEN_MOD2_INTEN_MASK)
#define TSTMP_MOD_INTEN_MOD1_INTEN_MASK 0x2u
#define TSTMP_MOD_INTEN_MOD1_INTEN_SHIFT 1u
#define TSTMP_MOD_INTEN_MOD1_INTEN_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD1_INTEN(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD1_INTEN_SHIFT))&TSTMP_MOD_INTEN_MOD1_INTEN_MASK)
#define TSTMP_MOD_INTEN_MOD0_INTEN_MASK 0x1u
#define TSTMP_MOD_INTEN_MOD0_INTEN_SHIFT 0u
#define TSTMP_MOD_INTEN_MOD0_INTEN_WIDTH 1u
#define TSTMP_MOD_INTEN_MOD0_INTEN(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_INTEN_MOD0_INTEN_SHIFT))&TSTMP_MOD_INTEN_MOD0_INTEN_MASK)
/* MOD_INTEN Reg Mask */
#define TSTMP_MOD_INTEN_MASK 0x0F0F0F0Fu
/* MOD_STATUS Bit Fields */
#define TSTMP_MOD_STATUS_MOD3_MATCH_MASK 0x8u
#define TSTMP_MOD_STATUS_MOD3_MATCH_SHIFT 3u
#define TSTMP_MOD_STATUS_MOD3_MATCH_WIDTH 1u
#define TSTMP_MOD_STATUS_MOD3_MATCH(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_STATUS_MOD3_MATCH_SHIFT))&TSTMP_MOD_STATUS_MOD3_MATCH_MASK)
#define TSTMP_MOD_STATUS_MOD2_MATCH_MASK 0x4u
#define TSTMP_MOD_STATUS_MOD2_MATCH_SHIFT 2u
#define TSTMP_MOD_STATUS_MOD2_MATCH_WIDTH 1u
#define TSTMP_MOD_STATUS_MOD2_MATCH(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_STATUS_MOD2_MATCH_SHIFT))&TSTMP_MOD_STATUS_MOD2_MATCH_MASK)
#define TSTMP_MOD_STATUS_MOD1_MATCH_MASK 0x2u
#define TSTMP_MOD_STATUS_MOD1_MATCH_SHIFT 1u
#define TSTMP_MOD_STATUS_MOD1_MATCH_WIDTH 1u
#define TSTMP_MOD_STATUS_MOD1_MATCH(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_STATUS_MOD1_MATCH_SHIFT))&TSTMP_MOD_STATUS_MOD1_MATCH_MASK)
#define TSTMP_MOD_STATUS_MOD0_MATCH_MASK 0x1u
#define TSTMP_MOD_STATUS_MOD0_MATCH_SHIFT 0u
#define TSTMP_MOD_STATUS_MOD0_MATCH_WIDTH 1u
#define TSTMP_MOD_STATUS_MOD0_MATCH(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD_STATUS_MOD0_MATCH_SHIFT))&TSTMP_MOD_STATUS_MOD0_MATCH_MASK)
/* MOD_STATUS Reg Mask */
#define TSTMP_MOD_STATUS_MASK 0x0000000Fu
/* MOD0_SETVAL Bit Fields */
#define TSTMP_MOD0_SETVAL_MOD0_SETVAL_MASK 0xFFFFFFFFu
#define TSTMP_MOD0_SETVAL_MOD0_SETVAL_SHIFT 0u
#define TSTMP_MOD0_SETVAL_MOD0_SETVAL_WIDTH 32u
#define TSTMP_MOD0_SETVAL_MOD0_SETVAL(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD0_SETVAL_MOD0_SETVAL_SHIFT))&TSTMP_MOD0_SETVAL_MOD0_SETVAL_MASK)
/* MOD0_SETVAL Reg Mask */
#define TSTMP_MOD0_SETVAL_MASK 0xFFFFFFFFu
/* MOD1_SETVAL Bit Fields */
#define TSTMP_MOD1_SETVAL_MOD1_SETVAL_MASK 0xFFFFFFFFu
#define TSTMP_MOD1_SETVAL_MOD1_SETVAL_SHIFT 0u
#define TSTMP_MOD1_SETVAL_MOD1_SETVAL_WIDTH 32u
#define TSTMP_MOD1_SETVAL_MOD1_SETVAL(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD1_SETVAL_MOD1_SETVAL_SHIFT))&TSTMP_MOD1_SETVAL_MOD1_SETVAL_MASK)
/* MOD1_SETVAL Reg Mask */
#define TSTMP_MOD1_SETVAL_MASK 0xFFFFFFFFu
/* MOD2_SETVAL Bit Fields */
#define TSTMP_MOD2_SETVAL_MOD2_SETVAL_MASK 0xFFFFFFFFu
#define TSTMP_MOD2_SETVAL_MOD2_SETVAL_SHIFT 0u
#define TSTMP_MOD2_SETVAL_MOD2_SETVAL_WIDTH 32u
#define TSTMP_MOD2_SETVAL_MOD2_SETVAL(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD2_SETVAL_MOD2_SETVAL_SHIFT))&TSTMP_MOD2_SETVAL_MOD2_SETVAL_MASK)
/* MOD2_SETVAL Reg Mask */
#define TSTMP_MOD2_SETVAL_MASK 0xFFFFFFFFu
/* MOD3_SETVAL Bit Fields */
#define TSTMP_MOD3_SETVAL_MOD3_SETVAL_MASK 0xFFFFFFFFu
#define TSTMP_MOD3_SETVAL_MOD3_SETVAL_SHIFT 0u
#define TSTMP_MOD3_SETVAL_MOD3_SETVAL_WIDTH 32u
#define TSTMP_MOD3_SETVAL_MOD3_SETVAL(x) (((uint32_t)(((uint32_t)(x))<<TSTMP_MOD3_SETVAL_MOD3_SETVAL_SHIFT))&TSTMP_MOD3_SETVAL_MOD3_SETVAL_MASK)
/* MOD3_SETVAL Reg Mask */
#define TSTMP_MOD3_SETVAL_MASK 0xFFFFFFFFu
/*!
* @}
*/ /* end of group TSTMP_Register_Masks */
/*!
* @}
*/ /* end of group TSTMP_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7240_wdog_regs.h Normal file
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#ifndef _FC7240_WDOG_NU_Tztufn14_REGS_H_
#define _FC7240_WDOG_NU_Tztufn14_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- WDOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
* @{
*/
/** WDOG - Size of Registers Arrays */
/** WDOG - Register Layout Typedef */
typedef struct {
__IO uint32_t CS ; /* Watchdog Control and Status Register, offset: 0x0 */
__IO uint32_t COUNTER ; /* Watchdog Counter Register, offset: 0x4 */
__IO uint32_t TIMEOUT ; /* Watchdog Timeout Value Register, offset: 0x8 */
__IO uint32_t WINDOW ; /* Watchdog Window Register, offset: 0xC */
} WDOG_Type, *WDOG_MemMapPtr;
/** Number of instances of the WDOG module. */
#define WDOG_INSTANCE_COUNT (2u)
/* WDOG - Peripheral instance base addresses */
/** Peripheral WDOG0 base address */
#define WDOG0_BASE (0x40022000u)
/** Peripheral WDOG0 base pointer */
#define WDOG0 ((WDOG_Type *)WDOG0_BASE)
/** Peripheral WDOG1 base address */
#define WDOG1_BASE (0x40433000u)
/** Peripheral WDOG1 base pointer */
#define WDOG1 ((WDOG_Type *)WDOG1_BASE)
/** Array initializer of WDOG peripheral base addresses */
#define WDOG_BASE_ADDRS {WDOG0_BASE, WDOG1_BASE}
/** Array initializer of WDOG peripheral base pointers */
#define WDOG_BASE_PTRS {WDOG0, WDOG1}
// need fill by yourself
///** Number of interrupt vector arrays for the WDOG module. */
//#define WDOG_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the WDOG module. */
//#define WDOG_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the WDOG peripheral type */
//#define WDOG_IRQS {WDOG0_IRQn, WDOG1_IRQn}
/* ----------------------------------------------------------------------------
-- WDOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Register_Masks WDOG Register Masks
* @{
*/
/* CS Bit Fields */
#define WDOG_CS_DLY_CNT_MSB_MASK 0x30000u
#define WDOG_CS_DLY_CNT_MSB_SHIFT 16u
#define WDOG_CS_DLY_CNT_MSB_WIDTH 2u
#define WDOG_CS_DLY_CNT_MSB(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_DLY_CNT_MSB_SHIFT))&WDOG_CS_DLY_CNT_MSB_MASK)
#define WDOG_CS_WIN_MASK 0x8000u
#define WDOG_CS_WIN_SHIFT 15u
#define WDOG_CS_WIN_WIDTH 1u
#define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_WIN_SHIFT))&WDOG_CS_WIN_MASK)
#define WDOG_CS_FLAG_MASK 0x4000u
#define WDOG_CS_FLAG_SHIFT 14u
#define WDOG_CS_FLAG_WIDTH 1u
#define WDOG_CS_FLAG(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_FLAG_SHIFT))&WDOG_CS_FLAG_MASK)
#define WDOG_CS_PRESCALER_MASK 0x1000u
#define WDOG_CS_PRESCALER_SHIFT 12u
#define WDOG_CS_PRESCALER_WIDTH 1u
#define WDOG_CS_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_PRESCALER_SHIFT))&WDOG_CS_PRESCALER_MASK)
#define WDOG_CS_ULK_STAT_MASK 0x800u
#define WDOG_CS_ULK_STAT_SHIFT 11u
#define WDOG_CS_ULK_STAT_WIDTH 1u
#define WDOG_CS_ULK_STAT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_ULK_STAT_SHIFT))&WDOG_CS_ULK_STAT_MASK)
#define WDOG_CS_RECFG_STAT_MASK 0x400u
#define WDOG_CS_RECFG_STAT_SHIFT 10u
#define WDOG_CS_RECFG_STAT_WIDTH 1u
#define WDOG_CS_RECFG_STAT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_RECFG_STAT_SHIFT))&WDOG_CS_RECFG_STAT_MASK)
#define WDOG_CS_CLK_SEL_MASK 0x300u
#define WDOG_CS_CLK_SEL_SHIFT 8u
#define WDOG_CS_CLK_SEL_WIDTH 2u
#define WDOG_CS_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_CLK_SEL_SHIFT))&WDOG_CS_CLK_SEL_MASK)
#define WDOG_CS_ENABLE_MASK 0x80u
#define WDOG_CS_ENABLE_SHIFT 7u
#define WDOG_CS_ENABLE_WIDTH 1u
#define WDOG_CS_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_ENABLE_SHIFT))&WDOG_CS_ENABLE_MASK)
#define WDOG_CS_INT_MASK 0x40u
#define WDOG_CS_INT_SHIFT 6u
#define WDOG_CS_INT_WIDTH 1u
#define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_INT_SHIFT))&WDOG_CS_INT_MASK)
#define WDOG_CS_UPDATE_MASK 0x20u
#define WDOG_CS_UPDATE_SHIFT 5u
#define WDOG_CS_UPDATE_WIDTH 1u
#define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_UPDATE_SHIFT))&WDOG_CS_UPDATE_MASK)
#define WDOG_CS_TST_MASK 0x18u
#define WDOG_CS_TST_SHIFT 3u
#define WDOG_CS_TST_WIDTH 2u
#define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_TST_SHIFT))&WDOG_CS_TST_MASK)
#define WDOG_CS_DBG_MASK 0x4u
#define WDOG_CS_DBG_SHIFT 2u
#define WDOG_CS_DBG_WIDTH 1u
#define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_DBG_SHIFT))&WDOG_CS_DBG_MASK)
#define WDOG_CS_WAIT_MASK 0x2u
#define WDOG_CS_WAIT_SHIFT 1u
#define WDOG_CS_WAIT_WIDTH 1u
#define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_WAIT_SHIFT))&WDOG_CS_WAIT_MASK)
#define WDOG_CS_STOP_MASK 0x1u
#define WDOG_CS_STOP_SHIFT 0u
#define WDOG_CS_STOP_WIDTH 1u
#define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_STOP_SHIFT))&WDOG_CS_STOP_MASK)
/* CS Reg Mask */
#define WDOG_CS_MASK 0x0003DFFFu
/* COUNTER Bit Fields */
#define WDOG_COUNTER_CNTH_MASK 0xFF00u
#define WDOG_COUNTER_CNTH_SHIFT 8u
#define WDOG_COUNTER_CNTH_WIDTH 8u
#define WDOG_COUNTER_CNTH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_COUNTER_CNTH_SHIFT))&WDOG_COUNTER_CNTH_MASK)
#define WDOG_COUNTER_CNTL_MASK 0xFFu
#define WDOG_COUNTER_CNTL_SHIFT 0u
#define WDOG_COUNTER_CNTL_WIDTH 8u
#define WDOG_COUNTER_CNTL(x) (((uint32_t)(((uint32_t)(x))<<WDOG_COUNTER_CNTL_SHIFT))&WDOG_COUNTER_CNTL_MASK)
/* COUNTER Reg Mask */
#define WDOG_COUNTER_MASK 0x0000FFFFu
/* TIMEOUT Bit Fields */
#define WDOG_TIMEOUT_TIMEOUT_VALH_MASK 0xFF00u
#define WDOG_TIMEOUT_TIMEOUT_VALH_SHIFT 8u
#define WDOG_TIMEOUT_TIMEOUT_VALH_WIDTH 8u
#define WDOG_TIMEOUT_TIMEOUT_VALH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_TIMEOUT_TIMEOUT_VALH_SHIFT))&WDOG_TIMEOUT_TIMEOUT_VALH_MASK)
#define WDOG_TIMEOUT_TIMEOUT_VALL_MASK 0xFFu
#define WDOG_TIMEOUT_TIMEOUT_VALL_SHIFT 0u
#define WDOG_TIMEOUT_TIMEOUT_VALL_WIDTH 8u
#define WDOG_TIMEOUT_TIMEOUT_VALL(x) (((uint32_t)(((uint32_t)(x))<<WDOG_TIMEOUT_TIMEOUT_VALL_SHIFT))&WDOG_TIMEOUT_TIMEOUT_VALL_MASK)
/* TIMEOUT Reg Mask */
#define WDOG_TIMEOUT_MASK 0x0000FFFFu
/* WINDOW Bit Fields */
#define WDOG_WINDOW_WINDOW_HIGH_MASK 0xFF00u
#define WDOG_WINDOW_WINDOW_HIGH_SHIFT 8u
#define WDOG_WINDOW_WINDOW_HIGH_WIDTH 8u
#define WDOG_WINDOW_WINDOW_HIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_WINDOW_WINDOW_HIGH_SHIFT))&WDOG_WINDOW_WINDOW_HIGH_MASK)
#define WDOG_WINDOW_WINDOW_LOW_MASK 0xFFu
#define WDOG_WINDOW_WINDOW_LOW_SHIFT 0u
#define WDOG_WINDOW_WINDOW_LOW_WIDTH 8u
#define WDOG_WINDOW_WINDOW_LOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_WINDOW_WINDOW_LOW_SHIFT))&WDOG_WINDOW_WINDOW_LOW_MASK)
/* WINDOW Reg Mask */
#define WDOG_WINDOW_MASK 0x0000FFFFu
/*!
* @}
*/ /* end of group WDOG_Register_Masks */
/*!
* @}
*/ /* end of group WDOG_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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#ifndef _FC7240_WKU_NU_Tztufn29_REGS_H_
#define _FC7240_WKU_NU_Tztufn29_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* ----------------------------------------------------------------------------
-- WKU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup WKU_Peripheral_Access_Layer WKU Peripheral Access Layer
* @{
*/
/** WKU - Size of Registers Arrays */
/** WKU - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t MDC ; /* Module Delay Configuration Register0, offset: 0x04 */
__IO uint32_t MWER0 ; /* Module Wakeup Enable Register0, offset: 0x08 */
__IO uint32_t MWER1 ; /* Module Wakeup Enable Register1, offset: 0x0C */
__IO uint32_t MWER2 ; /* Module Wakeup Enable Register2, offset: 0x10 */
} WKU_Type, *WKU_MemMapPtr;
/** Number of instances of the WKU module. */
#define WKU_INSTANCE_COUNT (1u)
/* WKU - Peripheral instance base addresses */
/** Peripheral WKU base address */
#define WKU_BASE (0x4003f000u)
/** Peripheral WKU base pointer */
#define WKU ((WKU_Type *)WKU_BASE)
/** Array initializer of WKU peripheral base addresses */
#define WKU_BASE_ADDRS {WKU_BASE}
/** Array initializer of WKU peripheral base pointers */
#define WKU_BASE_PTRS {WKU}
// need fill by yourself
///** Number of interrupt vector arrays for the WKU module. */
//#define WKU_IRQS_ARR_COUNT (1u)
///** Number of interrupt channels for the WKU module. */
//#define WKU_IRQS_CH_COUNT (1u)
///** Interrupt vectors for the WKU peripheral type */
//#define WKU_IRQS {WKU_IRQn}
/* ----------------------------------------------------------------------------
-- WKU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup WKU_Register_Masks WKU Register Masks
* @{
*/
/* MDC Bit Fields */
#define WKU_MDC_DLYEN_MASK 0x80000000u
#define WKU_MDC_DLYEN_SHIFT 31u
#define WKU_MDC_DLYEN_WIDTH 1u
#define WKU_MDC_DLYEN(x) (((uint32_t)(((uint32_t)(x))<<WKU_MDC_DLYEN_SHIFT))&WKU_MDC_DLYEN_MASK)
#define WKU_MDC_DELAYTIME_MASK 0xFu
#define WKU_MDC_DELAYTIME_SHIFT 0u
#define WKU_MDC_DELAYTIME_WIDTH 4u
#define WKU_MDC_DELAYTIME(x) (((uint32_t)(((uint32_t)(x))<<WKU_MDC_DELAYTIME_SHIFT))&WKU_MDC_DELAYTIME_MASK)
/* MDC Reg Mask */
#define WKU_MDC_MASK 0x8000000Fu
/* MWER0 Bit Fields */
#define WKU_MWER0_MWE7_MASK 0x80u
#define WKU_MWER0_MWE7_SHIFT 7u
#define WKU_MWER0_MWE7_WIDTH 1u
#define WKU_MWER0_MWE7(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER0_MWE7_SHIFT))&WKU_MWER0_MWE7_MASK)
#define WKU_MWER0_MWE6_MASK 0x40u
#define WKU_MWER0_MWE6_SHIFT 6u
#define WKU_MWER0_MWE6_WIDTH 1u
#define WKU_MWER0_MWE6(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER0_MWE6_SHIFT))&WKU_MWER0_MWE6_MASK)
#define WKU_MWER0_MWE5_MASK 0x20u
#define WKU_MWER0_MWE5_SHIFT 5u
#define WKU_MWER0_MWE5_WIDTH 1u
#define WKU_MWER0_MWE5(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER0_MWE5_SHIFT))&WKU_MWER0_MWE5_MASK)
#define WKU_MWER0_MWE4_MASK 0x10u
#define WKU_MWER0_MWE4_SHIFT 4u
#define WKU_MWER0_MWE4_WIDTH 1u
#define WKU_MWER0_MWE4(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER0_MWE4_SHIFT))&WKU_MWER0_MWE4_MASK)
#define WKU_MWER0_MWE3_MASK 0x8u
#define WKU_MWER0_MWE3_SHIFT 3u
#define WKU_MWER0_MWE3_WIDTH 1u
#define WKU_MWER0_MWE3(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER0_MWE3_SHIFT))&WKU_MWER0_MWE3_MASK)
#define WKU_MWER0_MWE2_MASK 0x4u
#define WKU_MWER0_MWE2_SHIFT 2u
#define WKU_MWER0_MWE2_WIDTH 1u
#define WKU_MWER0_MWE2(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER0_MWE2_SHIFT))&WKU_MWER0_MWE2_MASK)
#define WKU_MWER0_MWE1_MASK 0x2u
#define WKU_MWER0_MWE1_SHIFT 1u
#define WKU_MWER0_MWE1_WIDTH 1u
#define WKU_MWER0_MWE1(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER0_MWE1_SHIFT))&WKU_MWER0_MWE1_MASK)
#define WKU_MWER0_MWE0_MASK 0x1u
#define WKU_MWER0_MWE0_SHIFT 0u
#define WKU_MWER0_MWE0_WIDTH 1u
#define WKU_MWER0_MWE0(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER0_MWE0_SHIFT))&WKU_MWER0_MWE0_MASK)
/* MWER0 Reg Mask */
#define WKU_MWER0_MASK 0x000000FFu
/* MWER1 Bit Fields */
#define WKU_MWER1_MWE15_MASK 0x80u
#define WKU_MWER1_MWE15_SHIFT 7u
#define WKU_MWER1_MWE15_WIDTH 1u
#define WKU_MWER1_MWE15(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER1_MWE15_SHIFT))&WKU_MWER1_MWE15_MASK)
#define WKU_MWER1_MWE14_MASK 0x40u
#define WKU_MWER1_MWE14_SHIFT 6u
#define WKU_MWER1_MWE14_WIDTH 1u
#define WKU_MWER1_MWE14(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER1_MWE14_SHIFT))&WKU_MWER1_MWE14_MASK)
#define WKU_MWER1_MWE13_MASK 0x20u
#define WKU_MWER1_MWE13_SHIFT 5u
#define WKU_MWER1_MWE13_WIDTH 1u
#define WKU_MWER1_MWE13(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER1_MWE13_SHIFT))&WKU_MWER1_MWE13_MASK)
#define WKU_MWER1_MWE12_MASK 0x10u
#define WKU_MWER1_MWE12_SHIFT 4u
#define WKU_MWER1_MWE12_WIDTH 1u
#define WKU_MWER1_MWE12(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER1_MWE12_SHIFT))&WKU_MWER1_MWE12_MASK)
#define WKU_MWER1_MWE11_MASK 0x8u
#define WKU_MWER1_MWE11_SHIFT 3u
#define WKU_MWER1_MWE11_WIDTH 1u
#define WKU_MWER1_MWE11(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER1_MWE11_SHIFT))&WKU_MWER1_MWE11_MASK)
#define WKU_MWER1_MWE10_MASK 0x4u
#define WKU_MWER1_MWE10_SHIFT 2u
#define WKU_MWER1_MWE10_WIDTH 1u
#define WKU_MWER1_MWE10(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER1_MWE10_SHIFT))&WKU_MWER1_MWE10_MASK)
#define WKU_MWER1_MWE9_MASK 0x2u
#define WKU_MWER1_MWE9_SHIFT 1u
#define WKU_MWER1_MWE9_WIDTH 1u
#define WKU_MWER1_MWE9(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER1_MWE9_SHIFT))&WKU_MWER1_MWE9_MASK)
#define WKU_MWER1_MWE8_MASK 0x1u
#define WKU_MWER1_MWE8_SHIFT 0u
#define WKU_MWER1_MWE8_WIDTH 1u
#define WKU_MWER1_MWE8(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER1_MWE8_SHIFT))&WKU_MWER1_MWE8_MASK)
/* MWER1 Reg Mask */
#define WKU_MWER1_MASK 0x000000FFu
/* MWER2 Bit Fields */
#define WKU_MWER2_MWE23_MASK 0x80u
#define WKU_MWER2_MWE23_SHIFT 7u
#define WKU_MWER2_MWE23_WIDTH 1u
#define WKU_MWER2_MWE23(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER2_MWE23_SHIFT))&WKU_MWER2_MWE23_MASK)
#define WKU_MWER2_MWE22_MASK 0x40u
#define WKU_MWER2_MWE22_SHIFT 6u
#define WKU_MWER2_MWE22_WIDTH 1u
#define WKU_MWER2_MWE22(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER2_MWE22_SHIFT))&WKU_MWER2_MWE22_MASK)
#define WKU_MWER2_MWE21_MASK 0x20u
#define WKU_MWER2_MWE21_SHIFT 5u
#define WKU_MWER2_MWE21_WIDTH 1u
#define WKU_MWER2_MWE21(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER2_MWE21_SHIFT))&WKU_MWER2_MWE21_MASK)
#define WKU_MWER2_MWE20_MASK 0x10u
#define WKU_MWER2_MWE20_SHIFT 4u
#define WKU_MWER2_MWE20_WIDTH 1u
#define WKU_MWER2_MWE20(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER2_MWE20_SHIFT))&WKU_MWER2_MWE20_MASK)
#define WKU_MWER2_MWE19_MASK 0x8u
#define WKU_MWER2_MWE19_SHIFT 3u
#define WKU_MWER2_MWE19_WIDTH 1u
#define WKU_MWER2_MWE19(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER2_MWE19_SHIFT))&WKU_MWER2_MWE19_MASK)
#define WKU_MWER2_MWE18_MASK 0x4u
#define WKU_MWER2_MWE18_SHIFT 2u
#define WKU_MWER2_MWE18_WIDTH 1u
#define WKU_MWER2_MWE18(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER2_MWE18_SHIFT))&WKU_MWER2_MWE18_MASK)
#define WKU_MWER2_MWE17_MASK 0x2u
#define WKU_MWER2_MWE17_SHIFT 1u
#define WKU_MWER2_MWE17_WIDTH 1u
#define WKU_MWER2_MWE17(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER2_MWE17_SHIFT))&WKU_MWER2_MWE17_MASK)
#define WKU_MWER2_MWE16_MASK 0x1u
#define WKU_MWER2_MWE16_SHIFT 0u
#define WKU_MWER2_MWE16_WIDTH 1u
#define WKU_MWER2_MWE16(x) (((uint32_t)(((uint32_t)(x))<<WKU_MWER2_MWE16_SHIFT))&WKU_MWER2_MWE16_MASK)
/* MWER2 Reg Mask */
#define WKU_MWER2_MASK 0x000000FFu
/*!
* @}
*/ /* end of group WKU_Register_Masks */
/*!
* @}
*/ /* end of group WKU_Peripheral_Access_Layer */
#ifdef __cplusplus
}
#endif
#endif

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fc/fc7xxx_scm_regs.h Normal file
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@echo off
rem 3 line, 3 column, saved as abc.png
set "PyPath=C:\ProgramInstalled\Python38"
set "PATH=%PyPath%;%PyPath%\Scripts;%PATH%"
rem python parseReg.py C:\_UserPartitions\Projects\Python\LoadRegister\FC100_header.h FC100_header
python Z_AddInclude.py
pause

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/**
* @file fc7xxx_fcfunc.c
* @author Flagchip
* @brief include fcfunc file
* @version 0.2.1
* @date 2022-02-20
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
#include "fcfunc.h"
/**
* \brief Personnal memcpy function,avoid building target file too large because of include <string.h>--memcpy()
*
* \param pDest pSource u32Count wdogTriggerFunc
*/
void* FCFUNC_FcOwnMemcpy(uint8_t *pDest, const uint8_t *pSource, uint32_t u32Count, void_functype wdogTriggerFunc )
{
uint8_t* plocalDest;
const uint8_t* plocalSource;
uint32_t u32Index;
/* Initialize variables */
plocalDest = (uint8_t*)pDest;
plocalSource = (uint8_t const *)pSource;
for (u32Index = 0u; u32Index < u32Count; u32Index++)
{
if ((u32Index & 0x3Fu) == 0u)
{
if(wdogTriggerFunc!=NULL)
{
(void)wdogTriggerFunc();
}
}
plocalDest[u32Index] = plocalSource[u32Index];
}
return pDest;
}
void* FC_OwnMemcpy(void *pDest, const void *pSource, uint32_t u32Count)
{
uint8_t* plocalDest;
const uint8_t* plocalSource;
uint32_t u32Index;
/* Initialize variables */
plocalDest = (uint8_t*)pDest;
plocalSource = (const uint8_t*)pSource;
for (u32Index = 0u; u32Index < u32Count; u32Index++)
{
plocalDest[u32Index] = plocalSource[u32Index];
}
return pDest;
}
void* FC_OwnMemcpyWithWdg(void *pDest, const void *pSource, uint32_t u32Count, void_functype wdogTriggerFunc, uint32_t u32CallBackCnt)
{
uint8_t* plocalDest;
const uint8_t* plocalSource;
uint32_t u32Index;
/* Initialize variables */
plocalDest = (uint8_t*)pDest;
plocalSource = (const uint8_t*)pSource;
for (u32Index = 0u; u32Index < u32Count; u32Index++)
{
if ((u32Index % u32CallBackCnt) == 0u)
{
if(wdogTriggerFunc!=NULL)
{
(void)wdogTriggerFunc();
}
}
plocalDest[u32Index] = plocalSource[u32Index];
}
return pDest;
}

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/**
* @file fc7xxx_fclib.h
* @author Flagchip
* @brief include fclib file
* @version 0.2.1
* @date 2022-02-20
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
#ifndef _DEVICE_FCLIB_FCFUNC_H_
#define _DEVICE_FCLIB_FCFUNC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "typedef.h"
#include "v_def.h"
void* FCFUNC_FcOwnMemcpy(uint8_t *pDest, const uint8_t *pSource, uint32_t u32Count, void_functype wdogTriggerFunc );
void* FC_OwnMemcpy(void *pDest, const void *pSource, uint32_t u32Count);
void* FC_OwnMemcpyWithWdg(void *pDest, const void *pSource, uint32_t u32Count, void_functype wdogTriggerFunc, uint32_t u32CallBackCnt );
#ifdef __cplusplus
}
#endif
#endif

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/**
* @file fc7xxx_fcmath.h
* @author Flagchip
* @brief include fcmath file
* @version 0.2.1
* @date 2022-02-20
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
#include "fcmath.h"
uint32_t Fc_Power(uint32_t num, uint32_t u8Power)
{
uint8_t u8Index;
uint32_t u32RetVal;
u32RetVal = 1;
for(u8Index=0;u8Index<u8Power;u8Index++)
{
u32RetVal *=num;
}
return u32RetVal;
}
uint32_t Fc_Max(uint32_t u32Val1, uint32_t u32Val2)
{
if(u32Val1>u32Val2)
return u32Val1;
else
return u32Val2;
}
uint32_t Fc_Min(uint32_t u32Val1, uint32_t u32Val2)
{
if(u32Val1>u32Val2)
return u32Val2;
else
return u32Val1;
}

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/**
* @file fc7xxx_fclib.h
* @author Flagchip
* @brief include fclib file
* @version 0.2.1
* @date 2022-02-20
*
* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd.
*
*/
#ifndef _DEVICE_FCLIB_FCMATH_H_
#define _DEVICE_FCLIB_FCMATH_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "typedef.h"
uint32_t Fc_Power(uint32_t num, uint32_t u8Power);
uint32_t Fc_Max(uint32_t u32Val1, uint32_t u32Val2);
uint32_t Fc_Min(uint32_t u32Val1, uint32_t u32Val2);
#ifdef __cplusplus
}
#endif
#endif

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/**
* @file interrupt_manager.c
* @author Flagchip
* @brief interrupt configuration
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
#include "interrupt_manager.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define FC7300_PERI_VECTOR_START 16U
#define FC7300_NVIC_PRIO_BITS 3U
#define __NVIC_PRIO_BITS 2U
/*******************************************************************************
* Code
******************************************************************************/
#if 0
/**
* \brief Initial the interrupt table and data and bss
*
*/
void IntMgr_Init(void)
{
#if defined ( __GNUC__ )
extern uint32 __isr0_vector[1];
SCB->VTOR = (uint32_t)__isr0_vector;
#elif defined (__ICCARM__)
extern uint32 __vector_table[1];
SCB->VTOR = (uint32_t)__vector_table;
#endif
}
#endif
/**
* \brief enable interrupt via interrupt number
*
* \param eIrqNumber is interrupt number
*/
void IntMgr_EnableInterrupt(IRQn_Type eIrqNumber)
{
if ((int32_t)(eIrqNumber) >= 0)
{
NVIC->ISER[(((uint32_t)eIrqNumber) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)eIrqNumber) & 0x1FUL));
}
}
/**
* \brief disable interrupt via interrupt number
*
* \param eIrqNumber is interrupt number
*/
void IntMgr_DisableInterrupt(IRQn_Type eIrqNumber)
{
if ((int32_t)(eIrqNumber) >= 0)
{
NVIC->ICER[(((uint32_t)eIrqNumber) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)eIrqNumber) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
* \brief enable global interrupt
*
*/
void IntMgr_EnableGlobalInterrupt(void)
{
/* Enable the global interrupt*/
__enable_irq();
}
/**
* \brief disable global interrupt
*
*/
void IntMgr_DisableGlobalInterrupt(void)
{
/* Disable the global interrupt */
__disable_irq();
}
/**
* \brief Set Priority group
*
* \param u32PriorityGroup is the group bits
*/
void IntMgr_SetGroupPriority(uint32_t u32PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (u32PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
/**
* \brief set the interrupt service Priority
*
* \param eIrqNumber is interrupt number
* \param u8Priority is u8Priority number
*/
void IntMgr_SetPriority(IRQn_Type eIrqNumber, uint8_t u8Priority)
{
if ((int32_t)(eIrqNumber) >= 0)
{
NVIC->IP[((uint32_t)eIrqNumber)] = (uint8_t)(((uint32_t)u8Priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFU);
}
else
{
SCB->SHPR[(((uint32_t)eIrqNumber) & 0xFUL) - 4UL] = (uint8_t)(((uint32_t)u8Priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFU);
}
}
/**
* \brief get the interrupt service Priority
*
* \param eIrqNumber is interrupt number
* \return the Priority
*/
uint8_t IntMgr_GetPriority(IRQn_Type eIrqNumber)
{
if ((int32_t)(eIrqNumber) >= 0)
{
return (((uint32_t)NVIC->IP[((uint32_t)eIrqNumber)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return (((uint32_t)SCB->SHPR[(((uint32_t)eIrqNumber) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
/*******************************************************************************
* EOF
******************************************************************************/

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/**
* @file interrupt_manager.h
* @author Flagchip
* @brief interrupt configuration
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
#if !defined(INTERRUPT_MANAGER_H)
#define INTERRUPT_MANAGER_H
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
#include "device_header.h"
typedef enum
{
/* Auxiliary constants */
NotAvail_IRQn = -128, /**< Not available device specific interrupt */
/* Core interrupts */
NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
/* FC100 Device specific interrupts */
DMA0_IRQn = 0U, /**< DMA channel 0 transfer complete */
DMA1_IRQn = 1U, /**< DMA channel 1 transfer complete */
DMA2_IRQn = 2U, /**< DMA channel 2 transfer complete */
DMA3_IRQn = 3U, /**< DMA channel 3 transfer complete */
DMA4_IRQn = 4U, /**< DMA channel 4 transfer complete */
DMA5_IRQn = 5U, /**< DMA channel 5 transfer complete */
DMA6_IRQn = 6U, /**< DMA channel 6 transfer complete */
DMA7_IRQn = 7U, /**< DMA channel 7 transfer complete */
DMA8_IRQn = 8U, /**< DMA channel 8 transfer complete */
DMA9_IRQn = 9U, /**< DMA channel 9 transfer complete */
DMA10_IRQn = 10U, /**< DMA channel 10 transfer complete */
DMA11_IRQn = 11U, /**< DMA channel 11 transfer complete */
DMA12_IRQn = 12U, /**< DMA channel 12 transfer complete */
DMA13_IRQn = 13U, /**< DMA channel 13 transfer complete */
DMA14_IRQn = 14U, /**< DMA channel 14 transfer complete */
DMA15_IRQn = 15U, /**< DMA channel 15 transfer complete */
DMA_Error_IRQn = 16U, /**< DMA error interrupt channels 0-63 */
CPM_IRQn = 17U, /**< FPU etc. interrupt */
FC_IRQn = 18U, /**< Flash Controller Command complete, time out etc. interrupt */
LVD_LVW_IRQn = 19U, /**< HVD/LVD etc. interrupt */
TMU_IRQn = 20U, /**< Temperature Monitor Unit interrupt */
WDOG0_IRQn = 21U, /**< Interrupt request out before wdg0 reset out */
WDOG1_IRQn = 22U, /**< Interrupt request out before wdg1 reset out */
FCSMU0_IRQn = 23U, /**< Fault Control and Safety Manage Unit */
STCU0_IRQn = 24U, /**< Safety Control Unit interrupt */
ERM_fault_IRQn = 25U, /**< ERM single- or double-bit error interrupt */
MAM0_IRQn = 26U, /**< Matrix Access Monitor interrupt */
RGM_Pre_IRQn = 27U, /**< RGM pre-reset Interrupt */
INTM0_IRQn = 28U, /**< INTM0 timeout interrupt */
ISM0_IRQn = 29U, /**< ISM0 interrupt */
MB_IRQn = 30U, /**< Mail Box interrupt */
SCG_IRQn = 31U, /**< SCG bus interrupt request */
CMU0_IRQn = 32U, /**< CMU0 interrupt */
CMU1_IRQn = 33U, /**< CMU1 interrupt */
CMU2_IRQn = 34U, /**< CMU2 interrupt */
CMU3_IRQn = 35U, /**< CMU3 interrupt */
CMU4_IRQn = 36U, /**< CMU4 interrupt */
TSTMP0_IRQn = 37U, /**< TimerStamp0 interrupt */
TSTMP1_IRQn = 38U, /**< TimerStamp1 interrupt */
CORDIC_IRQn = 39U, /**< CORDIC Accelerator interrupt */
HSM0_ERR_IRQn = 40U, /**< HSM error interrupt */
FCPIT0_IRQn = 41U, /**< FCPIT interrupt */
RTC_IRQn = 42U, /**< RTC alarm or seconds interrupt */
AONTIMER_IRQn = 43U, /**< AONTIMER interrupt request */
SWI_IRQn = 44U, /**< Software interrupt */
FREQM_IRQn = 45U, /**< FREQM interrupt */
ADC0_IRQn = 46U, /**< ADC0 interrupt request */
ADC1_IRQn = 47U, /**< ADC1 interrupt request */
PTIMER0_IRQn = 48U, /**< PTIMER0 interrupt */
PTIMER1_IRQn = 49U, /**< PTIMER1 interrupt */
FlexCAN0_IRQn = 50U, /**< FLEXCAN0 interrupt */
FlexCAN1_IRQn = 51U, /**< FLEXCAN1 interrupt */
FlexCAN2_IRQn = 52U, /**< FLEXCAN2 interrupt */
FlexCAN3_IRQn = 53U, /**< FLEXCAN3 interrupt */
FCIIC0_IRQn = 54U, /**< FCIIC0 Interrupt */
FCIIC1_IRQn = 55U, /**< FCIIC1 Interrupt */
FCSPI0_IRQn = 56U, /**< FCSPI0 Interrupt */
FCSPI1_IRQn = 57U, /**< FCSPI1 Interrupt */
FCSPI2_IRQn = 58U, /**< FCSPI2 Interrupt */
FCSPI3_IRQn = 59U, /**< FCSPI3 Interrupt */
FCSPI4_IRQn = 60U, /**< FCSPI4 Interrupt */
FCSPI5_IRQn = 61U, /**< FCSPI5 Interrupt */
FCUART0_IRQn = 62U, /**< FCUART0 Interrupt */
FCUART1_IRQn = 63U, /**< FCUART1 Interrupt */
FCUART2_IRQn = 64U, /**< FCUART2 Interrupt */
FCUART3_IRQn = 65U, /**< FCUART3 Interrupt */
FCUART4_IRQn = 66U, /**< FCUART4 Interrupt */
FCUART5_IRQn = 67U, /**< FCUART5 Interrupt */
FCUART6_IRQn = 68U, /**< FCUART6 Interrupt */
FCUART7_IRQn = 69U, /**< FCUART7 Interrupt */
FTU0_IRQn = 70U, /**< FTU0 all source interrupt */
FTU1_IRQn = 71U, /**< FTU1 all source interrupt */
FTU2_IRQn = 72U, /**< FTU2 all source interrupt */
FTU3_IRQn = 73U, /**< FTU3 all source interrupt */
FTU4_IRQn = 74U, /**< FTU4 all source interrupt */
FTU5_IRQn = 75U, /**< FTU5 all source interrupt */
FTU6_IRQn = 76U, /**< FTU6 all source interrupt */
FTU7_IRQn = 77U, /**< FTU7 all source interrupt */
CMP0_IRQn = 78U, /**< CMP0 all source interrupt */
CMP1_IRQn = 79U, /**< CMP1 all source interrupt */
PORTA_IRQn = 80U, /**< Port A pin detect interrupt */
PORTB_IRQn = 81U, /**< Port B pin detect interrupt */
PORTC_IRQn = 82U, /**< Port C pin detect interrupt */
PORTD_IRQn = 83U, /**< Port D pin detect interrupt */
PORTE_IRQn = 84U, /**< Port E pin detect interrupt */
MSC0_IRQn = 85U, /**< MSC Interrupt */
SENT0_IRQn = 86U, /**< SENT all interrupt (fast or slow) */
TPU0_CH0_7_IRQn = 87U, /**< TPU0 CH0-7 interrupt */
TPU0_CH8_15_IRQn = 88U, /**< TPU0 CH8-15 interrupt */
TPU0_CH16_23_IRQn = 89U, /**< TPU0 CH16-23 interrupt */
TPU0_CH24_31_IRQn = 90U, /**< TPU0 CH24-31 interrupt */
HSM0_IRQn = 91U, /**< HSM crypto interrupt */
IRQn_MAX = 92U
} IRQn_Type;
/**
* \brief enable interrupt via interrupt number
*
* \param eIrqNumber is interrupt number
*/
void IntMgr_EnableInterrupt(IRQn_Type eIrqNumber);
/**
* \brief disable interrupt via interrupt number
*
* \param eIrqNumber is interrupt number
*/
void IntMgr_DisableInterrupt(IRQn_Type eIrqNumber);
/**
* \brief enable global interrupt
*
*/
void IntMgr_EnableGlobalInterrupt(void);
/**
* \brief disable global interrupt
*
*/
void IntMgr_DisableGlobalInterrupt(void);
/**
* \brief Set Priority group
*
* \param u32PriorityGroup is the group bits
*/
void IntMgr_SetGroupPriority(uint32_t u32PriorityGroup);
/**
* \brief set the interrupt service priority
*
* \param eIrqNumber is interrupt number
* \param u8Priority is priority number
*/
void IntMgr_SetPriority(IRQn_Type eIrqNumber, uint8_t u8Priority);
/**
* \brief get the interrupt service priority
*
* \param eIrqNumber is interrupt number
* \return the priority
*/
uint8_t IntMgr_GetPriority(IRQn_Type eIrqNumber);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* INTERRUPT_MANAGER_H */
/*******************************************************************************
* EOF
******************************************************************************/

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modular.json Normal file
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{
"cmake": {
"inc_dirs": [
"./",
"./cm7",
"./fc",
"./fclib"
],
"srcs": [
"./**.c",
"./cm7/**.c",
"./fc/**.c",
"./fclib/**.c"
]
}
}

37
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/**
* @file typedef.h
* @author Flagchip
* @brief type defines
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
#ifndef DEVICE_TYPEDEF_H_
#define DEVICE_TYPEDEF_H_
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "compiler.h"
#define STD_ON 1
#define STD_OFF 0
#ifdef NDEBUG
#define DEV_ASSERT(x) ((void)0)
#else
#define DEV_ASSERT(x) do{}while((x) != 1)
#endif
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I const
#endif
#endif /* DEVICE_TYPEDEF_H_ */

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/**
* @file v_def.h
* @author Flagchip
* @brief variables type define
* @version 0.1.0
* @date 2024-01-12
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
#ifndef DEVICE_V_DEF_H_
#define DEVICE_V_DEF_H_
#ifndef TRUE
#define TRUE 1U
#endif
#ifndef FALSE
#define FALSE 0U
#endif
#ifndef NULL_PTR
#define NULL_PTR ((void*)0)
#endif
#ifndef int8
typedef signed char int8;
#endif
#ifndef int16
typedef signed short int16;
#endif
#ifndef int32
typedef signed int int32;
#endif
#ifndef uint8
typedef unsigned char uint8;
#endif
#ifndef uint16
typedef unsigned short uint16;
#endif
#ifndef uint32
typedef unsigned int uint32;
#endif
#ifndef boolean
typedef uint8_t boolean;
#endif
typedef void (*void_functype)(void);
#ifdef __GUNC__
#endif
#endif /* DEVICE_V_DEF_H_ */