806 lines
26 KiB
C
806 lines
26 KiB
C
#ifndef _FC7240_AHB_OVERLAY_NU_Tztufn37_REGS_H_
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#define _FC7240_AHB_OVERLAY_NU_Tztufn37_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- AHB_OVERLAY Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup AHB_OVERLAY_Peripheral_Access_Layer AHB_OVERLAY Peripheral Access Layer
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* @{
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*/
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/** AHB_OVERLAY - Size of Registers Arrays */
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/** AHB_OVERLAY - Register Layout Typedef */
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typedef struct {
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__IO uint32_t REGION_0_SRC ; /* Region 0 Source Address Register, offset: 0x00 */
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__IO uint32_t REGION_0_DST ; /* Region 0 Destination Address Register, offset: 0x04 */
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__IO uint32_t REGION_0_SIZE ; /* Region 0 Size Register, offset: 0x08 */
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__IO uint32_t REGION_0_EN ; /* Region 0 Enable Register, offset: 0x0C */
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__IO uint32_t REGION_1_SRC ; /* Region 1 Source Address Register, offset: 0x10 */
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__IO uint32_t REGION_1_DST ; /* Region 1 Destination Address Register, offset: 0x14 */
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__IO uint32_t REGION_1_SIZE ; /* Region 1 Size Register, offset: 0x18 */
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__IO uint32_t REGION_1_EN ; /* Region 1 Enable Register, offset: 0x1C */
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__IO uint32_t REGION_2_SRC ; /* region 2 source address Register, offset: 0x20 */
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__IO uint32_t REGION_2_DST ; /* Region 2 Destination Address Register, offset: 0x24 */
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__IO uint32_t REGION_2_SIZE ; /* Region 2 Size Register, offset: 0x28 */
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__IO uint32_t REGION_2_EN ; /* Region 2 Enable Register, offset: 0x2C */
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uint8_t RESERVED_0[80];
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__IO uint32_t GLOBAL_EN ; /* Enable of FAR and Overlay Register, offset: 0x80 */
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__I uint32_t INTR_FLAG ; /* Flag of All Interrupt Register, offset: 0x84 */
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__O uint32_t INTR_CLR ; /* Clear Bit of Interupt Register, offset: 0x88 */
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__IO uint32_t INTR_EN ; /* Enable of Interrupt Register, offset: 0x8C */
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__I uint32_t FAR_SRC ; /* Source of FAR Register, offset: 0x90 */
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__IO uint32_t FAR_DST ; /* Sestination of FAR Register, offset: 0x94 */
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__IO uint32_t FAR_SIZE ; /* Size of FAR Register, offset: 0x98 */
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uint8_t RESERVED_1[4];
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__I uint32_t REGION0_MASK ; /* Region 0 Mask Register, offset: 0xA0 */
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__I uint32_t REGION1_MASK ; /* Region 1 Mask Register, offset: 0xA4 */
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__I uint32_t REGION2_MASK ; /* Region 2 Mask Register, offset: 0xA8 */
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} AHB_OVERLAY_Type, *AHB_OVERLAY_MemMapPtr;
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/** Number of instances of the AHB_OVERLAY module. */
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#define AHB_OVERLAY_INSTANCE_COUNT (1u)
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/* AHB_OVERLAY - Peripheral instance base addresses */
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/** Peripheral AHB_OVERLAY base address */
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#define AHB_OVERLAY_BASE (0xE0081000u)
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/** Peripheral AHB_OVERLAY base pointer */
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#define AHB_OVERLAY ((AHB_OVERLAY_Type *)AHB_OVERLAY_BASE)
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/** Array initializer of AHB_OVERLAY peripheral base addresses */
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#define AHB_OVERLAY_BASE_ADDRS {AHB_OVERLAY_BASE}
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/** Array initializer of AHB_OVERLAY peripheral base pointers */
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#define AHB_OVERLAY_BASE_PTRS {AHB_OVERLAY}
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// need fill by yourself
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///** Number of interrupt vector arrays for the AHB_OVERLAY module. */
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//#define AHB_OVERLAY_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the AHB_OVERLAY module. */
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//#define AHB_OVERLAY_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the AHB_OVERLAY peripheral type */
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//#define AHB_OVERLAY_IRQS {AHB_OVERLAY_IRQn}
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/* ----------------------------------------------------------------------------
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-- AHB_OVERLAY Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup AHB_OVERLAY_Register_Masks AHB_OVERLAY Register Masks
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* @{
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*/
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/* REGION_0_SRC Bit Fields */
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#define AHB_OVERLAY_REGION_0_SRC_REGION0_SRC_MASK 0x1FFC00u
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#define AHB_OVERLAY_REGION_0_SRC_REGION0_SRC_SHIFT 10u
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#define AHB_OVERLAY_REGION_0_SRC_REGION0_SRC_WIDTH 11u
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#define AHB_OVERLAY_REGION_0_SRC_REGION0_SRC(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_0_SRC_REGION0_SRC_MASK)
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/* REGION_0_SRC Reg Mask */
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#define AHB_OVERLAY_REGION_0_SRC_MASK 0x001FFC00u
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/* REGION_0_DST Bit Fields */
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#define AHB_OVERLAY_REGION_0_DST_REGION0_DST_MASK 0xFFFFFC00u
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#define AHB_OVERLAY_REGION_0_DST_REGION0_DST_SHIFT 10u
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#define AHB_OVERLAY_REGION_0_DST_REGION0_DST_WIDTH 22u
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#define AHB_OVERLAY_REGION_0_DST_REGION0_DST(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_0_DST_REGION0_DST_MASK)
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/* REGION_0_DST Reg Mask */
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#define AHB_OVERLAY_REGION_0_DST_MASK 0xFFFFFC00u
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/* REGION_0_SIZE Bit Fields */
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#define AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_MASK 0x7Fu
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#define AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_SHIFT 0u
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#define AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_WIDTH 7u
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#define AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_SHIFT))&AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_MASK)
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/* REGION_0_SIZE Reg Mask */
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#define AHB_OVERLAY_REGION_0_SIZE_MASK 0x0000007Fu
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/* REGION_0_EN Bit Fields */
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#define AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK 0x1u
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#define AHB_OVERLAY_REGION_0_EN_REGION0_EN_SHIFT 0u
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#define AHB_OVERLAY_REGION_0_EN_REGION0_EN_WIDTH 1u
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#define AHB_OVERLAY_REGION_0_EN_REGION0_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_0_EN_REGION0_EN_SHIFT))&AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK)
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/* REGION_0_EN Reg Mask */
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#define AHB_OVERLAY_REGION_0_EN_MASK 0x00000001u
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/* REGION_1_SRC Bit Fields */
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#define AHB_OVERLAY_REGION_1_SRC_REGION1_SRC_MASK 0x1FFC00u
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#define AHB_OVERLAY_REGION_1_SRC_REGION1_SRC_SHIFT 10u
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#define AHB_OVERLAY_REGION_1_SRC_REGION1_SRC_WIDTH 11u
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#define AHB_OVERLAY_REGION_1_SRC_REGION1_SRC(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_1_SRC_REGION1_SRC_MASK)
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/* REGION_1_SRC Reg Mask */
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#define AHB_OVERLAY_REGION_1_SRC_MASK 0x001FFC00u
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/* REGION_1_DST Bit Fields */
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#define AHB_OVERLAY_REGION_1_DST_REGION1_DST_MASK 0xFFFFFC00u
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#define AHB_OVERLAY_REGION_1_DST_REGION1_DST_SHIFT 10u
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#define AHB_OVERLAY_REGION_1_DST_REGION1_DST_WIDTH 22u
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#define AHB_OVERLAY_REGION_1_DST_REGION1_DST(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_1_DST_REGION1_DST_MASK)
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/* REGION_1_DST Reg Mask */
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#define AHB_OVERLAY_REGION_1_DST_MASK 0xFFFFFC00u
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/* REGION_1_SIZE Bit Fields */
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#define AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_MASK 0x7Fu
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#define AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_SHIFT 0u
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#define AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_WIDTH 7u
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#define AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_SHIFT))&AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_MASK)
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/* REGION_1_SIZE Reg Mask */
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#define AHB_OVERLAY_REGION_1_SIZE_MASK 0x0000007Fu
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/* REGION_1_EN Bit Fields */
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#define AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK 0x1u
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#define AHB_OVERLAY_REGION_1_EN_REGION1_EN_SHIFT 0u
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#define AHB_OVERLAY_REGION_1_EN_REGION1_EN_WIDTH 1u
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#define AHB_OVERLAY_REGION_1_EN_REGION1_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_1_EN_REGION1_EN_SHIFT))&AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK)
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/* REGION_1_EN Reg Mask */
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#define AHB_OVERLAY_REGION_1_EN_MASK 0x00000001u
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/* REGION_2_SRC Bit Fields */
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#define AHB_OVERLAY_REGION_2_SRC_REGION2_SRC_MASK 0x1FFC00u
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#define AHB_OVERLAY_REGION_2_SRC_REGION2_SRC_SHIFT 10u
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#define AHB_OVERLAY_REGION_2_SRC_REGION2_SRC_WIDTH 11u
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#define AHB_OVERLAY_REGION_2_SRC_REGION2_SRC(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_2_SRC_REGION2_SRC_MASK)
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/* REGION_2_SRC Reg Mask */
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#define AHB_OVERLAY_REGION_2_SRC_MASK 0x001FFC00u
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/* REGION_2_DST Bit Fields */
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#define AHB_OVERLAY_REGION_2_DST_REGION2_DST_MASK 0xFFFFFC00u
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#define AHB_OVERLAY_REGION_2_DST_REGION2_DST_SHIFT 10u
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#define AHB_OVERLAY_REGION_2_DST_REGION2_DST_WIDTH 22u
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#define AHB_OVERLAY_REGION_2_DST_REGION2_DST(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_2_DST_REGION2_DST_MASK)
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/* REGION_2_DST Reg Mask */
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#define AHB_OVERLAY_REGION_2_DST_MASK 0xFFFFFC00u
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/* REGION_2_SIZE Bit Fields */
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#define AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_MASK 0x7Fu
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#define AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_SHIFT 0u
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#define AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_WIDTH 7u
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#define AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_SHIFT))&AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_MASK)
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/* REGION_2_SIZE Reg Mask */
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#define AHB_OVERLAY_REGION_2_SIZE_MASK 0x0000007Fu
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/* REGION_2_EN Bit Fields */
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#define AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK 0x1u
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#define AHB_OVERLAY_REGION_2_EN_REGION2_EN_SHIFT 0u
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#define AHB_OVERLAY_REGION_2_EN_REGION2_EN_WIDTH 1u
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#define AHB_OVERLAY_REGION_2_EN_REGION2_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_2_EN_REGION2_EN_SHIFT))&AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK)
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/* REGION_2_EN Reg Mask */
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#define AHB_OVERLAY_REGION_2_EN_MASK 0x00000001u
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/* GLOBAL_EN Bit Fields */
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#define AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK 0x2u
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#define AHB_OVERLAY_GLOBAL_EN_FAR_EN_SHIFT 1u
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#define AHB_OVERLAY_GLOBAL_EN_FAR_EN_WIDTH 1u
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#define AHB_OVERLAY_GLOBAL_EN_FAR_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_GLOBAL_EN_FAR_EN_SHIFT))&AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK)
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#define AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK 0x1u
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#define AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_SHIFT 0u
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#define AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_WIDTH 1u
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#define AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_SHIFT))&AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK)
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/* GLOBAL_EN Reg Mask */
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#define AHB_OVERLAY_GLOBAL_EN_MASK 0x00000003u
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/* INTR_FLAG Bit Fields */
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#define AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_MASK 0x20000u
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#define AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_SHIFT 17u
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#define AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_MASK 0x10000u
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#define AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_SHIFT 16u
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#define AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_MASK 0x8000u
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#define AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_SHIFT 15u
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#define AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_MASK 0x4000u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_SHIFT 14u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_MASK 0x2000u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_SHIFT 13u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_MASK 0x1000u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_SHIFT 12u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_MASK 0x800u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_SHIFT 11u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_MASK 0x400u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_SHIFT 10u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_MASK 0x200u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_SHIFT 9u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_MASK 0x100u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_SHIFT 8u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_MASK 0x80u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_SHIFT 7u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_MASK 0x40u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_SHIFT 6u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_MASK 0x20u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_SHIFT 5u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_MASK 0x10u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_SHIFT 4u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_MASK 0x8u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_SHIFT 3u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_MASK 0x4u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_SHIFT 2u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_MASK 0x2u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_SHIFT 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_MASK)
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#define AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_MASK 0x1u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_SHIFT 0u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_WIDTH 1u
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#define AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_MASK)
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/* INTR_FLAG Reg Mask */
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#define AHB_OVERLAY_INTR_FLAG_MASK 0x0003FFFFu
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/* INTR_CLR Bit Fields */
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#define AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_MASK 0x20000u
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#define AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_SHIFT 17u
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#define AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_MASK 0x10000u
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#define AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_SHIFT 16u
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#define AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_MASK 0x8000u
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#define AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_SHIFT 15u
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#define AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_MASK 0x4000u
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#define AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_SHIFT 14u
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#define AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_MASK 0x2000u
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#define AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_SHIFT 13u
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#define AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_MASK 0x1000u
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#define AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_SHIFT 12u
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#define AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_MASK 0x800u
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#define AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_SHIFT 11u
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#define AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_MASK 0x400u
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#define AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_SHIFT 10u
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#define AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_MASK 0x200u
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#define AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_SHIFT 9u
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#define AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_MASK 0x100u
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#define AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_SHIFT 8u
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#define AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_MASK 0x80u
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#define AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_SHIFT 7u
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#define AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_MASK 0x40u
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#define AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_SHIFT 6u
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#define AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_MASK 0x20u
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#define AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_SHIFT 5u
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#define AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_MASK 0x10u
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#define AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_SHIFT 4u
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#define AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_MASK 0x8u
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#define AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_SHIFT 3u
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#define AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_MASK 0x4u
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#define AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_SHIFT 2u
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#define AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_MASK 0x2u
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#define AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_SHIFT 1u
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#define AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_MASK)
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#define AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_MASK 0x1u
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#define AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_SHIFT 0u
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#define AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_WIDTH 1u
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#define AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_MASK)
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/* INTR_CLR Reg Mask */
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#define AHB_OVERLAY_INTR_CLR_MASK 0x0003FFFFu
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/* INTR_EN Bit Fields */
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#define AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK 0x1u
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#define AHB_OVERLAY_INTR_EN_INTR_ENABLE_SHIFT 0u
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#define AHB_OVERLAY_INTR_EN_INTR_ENABLE_WIDTH 1u
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#define AHB_OVERLAY_INTR_EN_INTR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_EN_INTR_ENABLE_SHIFT))&AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK)
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/* INTR_EN Reg Mask */
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#define AHB_OVERLAY_INTR_EN_MASK 0x00000001u
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/* FAR_SRC Bit Fields */
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#define AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR_MASK 0xFFFFFFFFu
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#define AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR_SHIFT 0u
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#define AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR_WIDTH 32u
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#define AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR_MASK)
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/* FAR_SRC Reg Mask */
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#define AHB_OVERLAY_FAR_SRC_MASK 0xFFFFFFFFu
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/* FAR_DST Bit Fields */
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#define AHB_OVERLAY_FAR_DST_FAR_DST_ADDR_MASK 0xFFFF0000u
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#define AHB_OVERLAY_FAR_DST_FAR_DST_ADDR_SHIFT 16u
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#define AHB_OVERLAY_FAR_DST_FAR_DST_ADDR_WIDTH 16u
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#define AHB_OVERLAY_FAR_DST_FAR_DST_ADDR(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_FAR_DST_FAR_DST_ADDR_MASK)
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/* FAR_DST Reg Mask */
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#define AHB_OVERLAY_FAR_DST_MASK 0xFFFF0000u
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/* FAR_SIZE Bit Fields */
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#define AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_MASK 0x1FFu
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#define AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_SHIFT 0u
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#define AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_WIDTH 9u
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#define AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_SHIFT))&AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_MASK)
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/* FAR_SIZE Reg Mask */
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#define AHB_OVERLAY_FAR_SIZE_MASK 0x000001FFu
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/* REGION0_MASK Bit Fields */
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#define AHB_OVERLAY_REGION0_MASK_REGION0_MASK_MASK 0xFFFFFFFFu
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#define AHB_OVERLAY_REGION0_MASK_REGION0_MASK_SHIFT 0u
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#define AHB_OVERLAY_REGION0_MASK_REGION0_MASK_WIDTH 32u
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#define AHB_OVERLAY_REGION0_MASK_REGION0_MASK(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION0_MASK_REGION0_MASK_SHIFT))&AHB_OVERLAY_REGION0_MASK_REGION0_MASK_MASK)
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/* REGION0_MASK Reg Mask */
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#define AHB_OVERLAY_REGION0_MASK_MASK 0xFFFFFFFFu
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/* REGION1_MASK Bit Fields */
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#define AHB_OVERLAY_REGION1_MASK_REGION1_MASK_MASK 0xFFFFFFFFu
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#define AHB_OVERLAY_REGION1_MASK_REGION1_MASK_SHIFT 0u
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#define AHB_OVERLAY_REGION1_MASK_REGION1_MASK_WIDTH 32u
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#define AHB_OVERLAY_REGION1_MASK_REGION1_MASK(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION1_MASK_REGION1_MASK_SHIFT))&AHB_OVERLAY_REGION1_MASK_REGION1_MASK_MASK)
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/* REGION1_MASK Reg Mask */
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#define AHB_OVERLAY_REGION1_MASK_MASK 0xFFFFFFFFu
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/* REGION2_MASK Bit Fields */
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#define AHB_OVERLAY_REGION2_MASK_REGION2_MASK_MASK 0xFFFFFFFFu
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#define AHB_OVERLAY_REGION2_MASK_REGION2_MASK_SHIFT 0u
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#define AHB_OVERLAY_REGION2_MASK_REGION2_MASK_WIDTH 32u
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#define AHB_OVERLAY_REGION2_MASK_REGION2_MASK(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION2_MASK_REGION2_MASK_SHIFT))&AHB_OVERLAY_REGION2_MASK_REGION2_MASK_MASK)
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/* REGION2_MASK Reg Mask */
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#define AHB_OVERLAY_REGION2_MASK_MASK 0xFFFFFFFFu
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/*!
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* @}
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*/ /* end of group AHB_OVERLAY_Register_Masks */
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/*!
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* @}
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*/ /* end of group AHB_OVERLAY_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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