278 lines
6.2 KiB
C
278 lines
6.2 KiB
C
#ifndef _FC7240_AONTIMER_NU_Tztufn16_REGS_H_
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#define _FC7240_AONTIMER_NU_Tztufn16_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- AONTIMER Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup AONTIMER_Peripheral_Access_Layer AONTIMER Peripheral Access Layer
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* @{
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*/
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/** AONTIMER - Size of Registers Arrays */
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/** AONTIMER - Register Layout Typedef */
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typedef struct {
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__IO uint32_t CSR ; /* Control Status Register, offset: 0x0 */
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__IO uint32_t PSR ; /* Prescale Register, offset: 0x4 */
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__IO uint32_t CMR ; /* Compare Register, offset: 0x8 */
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__IO uint32_t CNR ; /* Counter Register, offset: 0xC */
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} AONTIMER_Type, *AONTIMER_MemMapPtr;
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/** Number of instances of the AONTIMER module. */
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#define AONTIMER_INSTANCE_COUNT (1u)
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/* AONTIMER - Peripheral instance base addresses */
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/** Peripheral AONTIMER base address */
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#define AONTIMER_BASE (0x4002f000u)
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/** Peripheral AONTIMER base pointer */
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#define AONTIMER ((AONTIMER_Type *)AONTIMER_BASE)
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/** Array initializer of AONTIMER peripheral base addresses */
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#define AONTIMER_BASE_ADDRS {AONTIMER_BASE}
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/** Array initializer of AONTIMER peripheral base pointers */
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#define AONTIMER_BASE_PTRS {AONTIMER}
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// need fill by yourself
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///** Number of interrupt vector arrays for the AONTIMER module. */
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//#define AONTIMER_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the AONTIMER module. */
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//#define AONTIMER_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the AONTIMER peripheral type */
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//#define AONTIMER_IRQS {AONTIMER_IRQn}
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/* ----------------------------------------------------------------------------
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-- AONTIMER Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup AONTIMER_Register_Masks AONTIMER Register Masks
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* @{
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*/
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/* CSR Bit Fields */
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#define AONTIMER_CSR_DBGEN_MASK 0x200u
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#define AONTIMER_CSR_DBGEN_SHIFT 9u
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#define AONTIMER_CSR_DBGEN_WIDTH 1u
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#define AONTIMER_CSR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_DBGEN_SHIFT))&AONTIMER_CSR_DBGEN_MASK)
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#define AONTIMER_CSR_TDRE_MASK 0x100u
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#define AONTIMER_CSR_TDRE_SHIFT 8u
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#define AONTIMER_CSR_TDRE_WIDTH 1u
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#define AONTIMER_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TDRE_SHIFT))&AONTIMER_CSR_TDRE_MASK)
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#define AONTIMER_CSR_TCF_MASK 0x80u
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#define AONTIMER_CSR_TCF_SHIFT 7u
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#define AONTIMER_CSR_TCF_WIDTH 1u
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#define AONTIMER_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TCF_SHIFT))&AONTIMER_CSR_TCF_MASK)
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#define AONTIMER_CSR_TIE_MASK 0x40u
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#define AONTIMER_CSR_TIE_SHIFT 6u
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#define AONTIMER_CSR_TIE_WIDTH 1u
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#define AONTIMER_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TIE_SHIFT))&AONTIMER_CSR_TIE_MASK)
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#define AONTIMER_CSR_TPS_MASK 0x30u
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#define AONTIMER_CSR_TPS_SHIFT 4u
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#define AONTIMER_CSR_TPS_WIDTH 2u
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#define AONTIMER_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TPS_SHIFT))&AONTIMER_CSR_TPS_MASK)
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#define AONTIMER_CSR_TPP_MASK 0x8u
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#define AONTIMER_CSR_TPP_SHIFT 3u
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#define AONTIMER_CSR_TPP_WIDTH 1u
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#define AONTIMER_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TPP_SHIFT))&AONTIMER_CSR_TPP_MASK)
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#define AONTIMER_CSR_TFC_MASK 0x4u
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#define AONTIMER_CSR_TFC_SHIFT 2u
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#define AONTIMER_CSR_TFC_WIDTH 1u
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#define AONTIMER_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TFC_SHIFT))&AONTIMER_CSR_TFC_MASK)
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#define AONTIMER_CSR_TMS_MASK 0x2u
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#define AONTIMER_CSR_TMS_SHIFT 1u
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#define AONTIMER_CSR_TMS_WIDTH 1u
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#define AONTIMER_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TMS_SHIFT))&AONTIMER_CSR_TMS_MASK)
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#define AONTIMER_CSR_TEN_MASK 0x1u
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#define AONTIMER_CSR_TEN_SHIFT 0u
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#define AONTIMER_CSR_TEN_WIDTH 1u
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#define AONTIMER_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TEN_SHIFT))&AONTIMER_CSR_TEN_MASK)
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/* CSR Reg Mask */
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#define AONTIMER_CSR_MASK 0x000003FFu
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/* PSR Bit Fields */
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#define AONTIMER_PSR_PRESCALE_MASK 0x78u
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#define AONTIMER_PSR_PRESCALE_SHIFT 3u
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#define AONTIMER_PSR_PRESCALE_WIDTH 4u
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#define AONTIMER_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_PSR_PRESCALE_SHIFT))&AONTIMER_PSR_PRESCALE_MASK)
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#define AONTIMER_PSR_PBYP_MASK 0x4u
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#define AONTIMER_PSR_PBYP_SHIFT 2u
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#define AONTIMER_PSR_PBYP_WIDTH 1u
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#define AONTIMER_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_PSR_PBYP_SHIFT))&AONTIMER_PSR_PBYP_MASK)
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#define AONTIMER_PSR_PCS_MASK 0x3u
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#define AONTIMER_PSR_PCS_SHIFT 0u
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#define AONTIMER_PSR_PCS_WIDTH 2u
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#define AONTIMER_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_PSR_PCS_SHIFT))&AONTIMER_PSR_PCS_MASK)
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/* PSR Reg Mask */
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#define AONTIMER_PSR_MASK 0x0000007Fu
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/* CMR Bit Fields */
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#define AONTIMER_CMR_COMPARE_MASK 0xFFFFu
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#define AONTIMER_CMR_COMPARE_SHIFT 0u
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#define AONTIMER_CMR_COMPARE_WIDTH 16u
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#define AONTIMER_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CMR_COMPARE_SHIFT))&AONTIMER_CMR_COMPARE_MASK)
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/* CMR Reg Mask */
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#define AONTIMER_CMR_MASK 0x0000FFFFu
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/* CNR Bit Fields */
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#define AONTIMER_CNR_COUNTER_MASK 0xFFFFu
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#define AONTIMER_CNR_COUNTER_SHIFT 0u
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#define AONTIMER_CNR_COUNTER_WIDTH 16u
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#define AONTIMER_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CNR_COUNTER_SHIFT))&AONTIMER_CNR_COUNTER_MASK)
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/* CNR Reg Mask */
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#define AONTIMER_CNR_MASK 0x0000FFFFu
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/*!
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* @}
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*/ /* end of group AONTIMER_Register_Masks */
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/*!
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* @}
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*/ /* end of group AONTIMER_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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