828 lines
25 KiB
C
828 lines
25 KiB
C
#ifndef _FC7240_ISM_NU_Tztufn11_REGS_H_
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#define _FC7240_ISM_NU_Tztufn11_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- ISM Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup ISM_Peripheral_Access_Layer ISM Peripheral Access Layer
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* @{
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*/
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/** ISM - Size of Registers Arrays */
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/** ISM - Register Layout Typedef */
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typedef struct {
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__I uint32_t PARAM ; /* Parameter Register, offset: 0x0 */
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__IO uint32_t CTRL ; /* Control Register, offset: 0x4 */
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__IO uint32_t E_STATUS ; /* Event Status Register, offset: 0x8 */
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__IO uint32_t E_CTRL ; /* Event Control Register, offset: 0xC */
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__IO uint32_t EC_CTRL ; /* Event Control Mode Control Register, offset: 0x10 */
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uint8_t RESERVED_0[236];
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__IO uint32_t FPC_STATUS0 ; /* FPC Status Register, offset: 0x100 */
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__IO uint32_t FPC_CTRL0 ; /* FPC Control Register, offset: 0x104 */
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__IO uint32_t FPC_CONFIG0 ; /* FPC Configuration Register, offset: 0x108 */
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__IO uint32_t FPC_TIMER0 ; /* FPC Timer Register, offset: 0x10c */
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__IO uint32_t FPC_STATUS1 ; /* FPC Status Register, offset: 0x110 */
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__IO uint32_t FPC_CTRL1 ; /* FPC Control Register, offset: 0x114 */
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__IO uint32_t FPC_CONFIG1 ; /* FPC Configuration Register, offset: 0x118 */
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__IO uint32_t FPC_TIMER1 ; /* FPC Timer Register, offset: 0x11c */
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__IO uint32_t FPC_STATUS2 ; /* FPC Status Register, offset: 0x120 */
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__IO uint32_t FPC_CTRL2 ; /* FPC Control Register, offset: 0x124 */
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__IO uint32_t FPC_CONFIG2 ; /* FPC Configuration Register, offset: 0x128 */
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__IO uint32_t FPC_TIMER2 ; /* FPC Timer Register, offset: 0x12c */
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__IO uint32_t FPC_STATUS3 ; /* FPC Status Register, offset: 0x130 */
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__IO uint32_t FPC_CTRL3 ; /* FPC Control Register, offset: 0x134 */
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__IO uint32_t FPC_CONFIG3 ; /* FPC Configuration Register, offset: 0x138 */
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__IO uint32_t FPC_TIMER3 ; /* FPC Timer Register, offset: 0x13c */
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__IO uint32_t FPC_STATUS4 ; /* FPC Status Register, offset: 0x140 */
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__IO uint32_t FPC_CTRL4 ; /* FPC Control Register, offset: 0x144 */
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__IO uint32_t FPC_CONFIG4 ; /* FPC Configuration Register, offset: 0x148 */
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__IO uint32_t FPC_TIMER4 ; /* FPC Timer Register, offset: 0x14c */
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__IO uint32_t FPC_STATUS5 ; /* FPC Status Register, offset: 0x150 */
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__IO uint32_t FPC_CTRL5 ; /* FPC Control Register, offset: 0x154 */
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__IO uint32_t FPC_CONFIG5 ; /* FPC Configuration Register, offset: 0x158 */
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__IO uint32_t FPC_TIMER5 ; /* FPC Timer Register, offset: 0x15c */
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__IO uint32_t FPC_STATUS6 ; /* FPC Status Register, offset: 0x160 */
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__IO uint32_t FPC_CTRL6 ; /* FPC Control Register, offset: 0x164 */
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__IO uint32_t FPC_CONFIG6 ; /* FPC Configuration Register, offset: 0x168 */
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__IO uint32_t FPC_TIMER6 ; /* FPC Timer Register, offset: 0x16c */
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__IO uint32_t FPC_STATUS7 ; /* FPC Status Register, offset: 0x170 */
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__IO uint32_t FPC_CTRL7 ; /* FPC Control Register, offset: 0x174 */
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__IO uint32_t FPC_CONFIG7 ; /* FPC Configuration Register, offset: 0x178 */
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__IO uint32_t FPC_TIMER7 ; /* FPC Timer Register, offset: 0x17c */
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__IO uint32_t FPC_STATUS8 ; /* FPC Status Register, offset: 0x180 */
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__IO uint32_t FPC_CTRL8 ; /* FPC Control Register, offset: 0x184 */
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__IO uint32_t FPC_CONFIG8 ; /* FPC Configuration Register, offset: 0x188 */
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__IO uint32_t FPC_TIMER8 ; /* FPC Timer Register, offset: 0x18c */
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__IO uint32_t FPC_STATUS9 ; /* FPC Status Register, offset: 0x190 */
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__IO uint32_t FPC_CTRL9 ; /* FPC Control Register, offset: 0x194 */
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__IO uint32_t FPC_CONFIG9 ; /* FPC Configuration Register, offset: 0x198 */
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__IO uint32_t FPC_TIMER9 ; /* FPC Timer Register, offset: 0x19c */
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__IO uint32_t FPC_STATUS10 ; /* FPC Status Register, offset: 0x1a0 */
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__IO uint32_t FPC_CTRL10 ; /* FPC Control Register, offset: 0x1a4 */
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__IO uint32_t FPC_CONFIG10 ; /* FPC Configuration Register, offset: 0x1a8 */
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__IO uint32_t FPC_TIMER10 ; /* FPC Timer Register, offset: 0x1ac */
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__IO uint32_t FPC_STATUS11 ; /* FPC Status Register, offset: 0x1b0 */
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__IO uint32_t FPC_CTRL11 ; /* FPC Control Register, offset: 0x1b4 */
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__IO uint32_t FPC_CONFIG11 ; /* FPC Configuration Register, offset: 0x1b8 */
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__IO uint32_t FPC_TIMER11 ; /* FPC Timer Register, offset: 0x1bc */
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__IO uint32_t FPC_STATUS12 ; /* FPC Status Register, offset: 0x1c0 */
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__IO uint32_t FPC_CTRL12 ; /* FPC Control Register, offset: 0x1c4 */
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__IO uint32_t FPC_CONFIG12 ; /* FPC Configuration Register, offset: 0x1c8 */
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__IO uint32_t FPC_TIMER12 ; /* FPC Timer Register, offset: 0x1cc */
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__IO uint32_t FPC_STATUS13 ; /* FPC Status Register, offset: 0x1d0 */
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__IO uint32_t FPC_CTRL13 ; /* FPC Control Register, offset: 0x1d4 */
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__IO uint32_t FPC_CONFIG13 ; /* FPC Configuration Register, offset: 0x1d8 */
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__IO uint32_t FPC_TIMER13 ; /* FPC Timer Register, offset: 0x1dc */
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__IO uint32_t FPC_STATUS14 ; /* FPC Status Register, offset: 0x1e0 */
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__IO uint32_t FPC_CTRL14 ; /* FPC Control Register, offset: 0x1e4 */
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__IO uint32_t FPC_CONFIG14 ; /* FPC Configuration Register, offset: 0x1e8 */
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__IO uint32_t FPC_TIMER14 ; /* FPC Timer Register, offset: 0x1ec */
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__IO uint32_t FPC_STATUS15 ; /* FPC Status Register, offset: 0x1f0 */
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__IO uint32_t FPC_CTRL15 ; /* FPC Control Register, offset: 0x1f4 */
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__IO uint32_t FPC_CONFIG15 ; /* FPC Configuration Register, offset: 0x1f8 */
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__IO uint32_t FPC_TIMER15 ; /* FPC Timer Register, offset: 0x1fc */
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uint8_t RESERVED_1[512];
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__IO uint32_t LAM_STATUS0 ; /* LAM Status Register, offset: 0x400 */
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__IO uint32_t LAM_CTRL0 ; /* LAM Control Register, offset: 0x404 */
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__IO uint32_t LAM_CONFIG0 ; /* LAM Configuration Register, offset: 0x408 */
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__IO uint32_t LAM_COUNTER0 ; /* LAM Counter Register, offset: 0x40c */
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__IO uint32_t LAM_STATUS1 ; /* LAM Status Register, offset: 0x410 */
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__IO uint32_t LAM_CTRL1 ; /* LAM Control Register, offset: 0x414 */
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__IO uint32_t LAM_CONFIG1 ; /* LAM Configuration Register, offset: 0x418 */
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__IO uint32_t LAM_COUNTER1 ; /* LAM Counter Register, offset: 0x41c */
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__IO uint32_t LAM_STATUS2 ; /* LAM Status Register, offset: 0x420 */
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__IO uint32_t LAM_CTRL2 ; /* LAM Control Register, offset: 0x424 */
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__IO uint32_t LAM_CONFIG2 ; /* LAM Configuration Register, offset: 0x428 */
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__IO uint32_t LAM_COUNTER2 ; /* LAM Counter Register, offset: 0x42c */
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__IO uint32_t LAM_STATUS3 ; /* LAM Status Register, offset: 0x430 */
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__IO uint32_t LAM_CTRL3 ; /* LAM Control Register, offset: 0x434 */
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__IO uint32_t LAM_CONFIG3 ; /* LAM Configuration Register, offset: 0x438 */
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__IO uint32_t LAM_COUNTER3 ; /* LAM Counter Register, offset: 0x43c */
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__IO uint32_t LAM_STATUS4 ; /* LAM Status Register, offset: 0x440 */
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__IO uint32_t LAM_CTRL4 ; /* LAM Control Register, offset: 0x444 */
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__IO uint32_t LAM_CONFIG4 ; /* LAM Configuration Register, offset: 0x448 */
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__IO uint32_t LAM_COUNTER4 ; /* LAM Counter Register, offset: 0x44c */
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__IO uint32_t LAM_STATUS5 ; /* LAM Status Register, offset: 0x450 */
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__IO uint32_t LAM_CTRL5 ; /* LAM Control Register, offset: 0x454 */
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__IO uint32_t LAM_CONFIG5 ; /* LAM Configuration Register, offset: 0x458 */
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__IO uint32_t LAM_COUNTER5 ; /* LAM Counter Register, offset: 0x45c */
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__IO uint32_t LAM_STATUS6 ; /* LAM Status Register, offset: 0x460 */
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__IO uint32_t LAM_CTRL6 ; /* LAM Control Register, offset: 0x464 */
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__IO uint32_t LAM_CONFIG6 ; /* LAM Configuration Register, offset: 0x468 */
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__IO uint32_t LAM_COUNTER6 ; /* LAM Counter Register, offset: 0x46c */
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__IO uint32_t LAM_STATUS7 ; /* LAM Status Register, offset: 0x470 */
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__IO uint32_t LAM_CTRL7 ; /* LAM Control Register, offset: 0x474 */
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__IO uint32_t LAM_CONFIG7 ; /* LAM Configuration Register, offset: 0x478 */
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__IO uint32_t LAM_COUNTER7 ; /* LAM Counter Register, offset: 0x47c */
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__IO uint32_t LAM_STATUS8 ; /* LAM Status Register, offset: 0x480 */
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__IO uint32_t LAM_CTRL8 ; /* LAM Control Register, offset: 0x484 */
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__IO uint32_t LAM_CONFIG8 ; /* LAM Configuration Register, offset: 0x488 */
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__IO uint32_t LAM_COUNTER8 ; /* LAM Counter Register, offset: 0x48c */
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__IO uint32_t LAM_STATUS9 ; /* LAM Status Register, offset: 0x490 */
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__IO uint32_t LAM_CTRL9 ; /* LAM Control Register, offset: 0x494 */
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__IO uint32_t LAM_CONFIG9 ; /* LAM Configuration Register, offset: 0x498 */
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__IO uint32_t LAM_COUNTER9 ; /* LAM Counter Register, offset: 0x49c */
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__IO uint32_t LAM_STATUS10 ; /* LAM Status Register, offset: 0x4a0 */
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__IO uint32_t LAM_CTRL10 ; /* LAM Control Register, offset: 0x4a4 */
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__IO uint32_t LAM_CONFIG10 ; /* LAM Configuration Register, offset: 0x4a8 */
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__IO uint32_t LAM_COUNTER10 ; /* LAM Counter Register, offset: 0x4ac */
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__IO uint32_t LAM_STATUS11 ; /* LAM Status Register, offset: 0x4b0 */
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__IO uint32_t LAM_CTRL11 ; /* LAM Control Register, offset: 0x4b4 */
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__IO uint32_t LAM_CONFIG11 ; /* LAM Configuration Register, offset: 0x4b8 */
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__IO uint32_t LAM_COUNTER11 ; /* LAM Counter Register, offset: 0x4bc */
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__IO uint32_t LAM_STATUS12 ; /* LAM Status Register, offset: 0x4c0 */
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__IO uint32_t LAM_CTRL12 ; /* LAM Control Register, offset: 0x4c4 */
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__IO uint32_t LAM_CONFIG12 ; /* LAM Configuration Register, offset: 0x4c8 */
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__IO uint32_t LAM_COUNTER12 ; /* LAM Counter Register, offset: 0x4cc */
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__IO uint32_t LAM_STATUS13 ; /* LAM Status Register, offset: 0x4d0 */
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__IO uint32_t LAM_CTRL13 ; /* LAM Control Register, offset: 0x4d4 */
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__IO uint32_t LAM_CONFIG13 ; /* LAM Configuration Register, offset: 0x4d8 */
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__IO uint32_t LAM_COUNTER13 ; /* LAM Counter Register, offset: 0x4dc */
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__IO uint32_t LAM_STATUS14 ; /* LAM Status Register, offset: 0x4e0 */
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__IO uint32_t LAM_CTRL14 ; /* LAM Control Register, offset: 0x4e4 */
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__IO uint32_t LAM_CONFIG14 ; /* LAM Configuration Register, offset: 0x4e8 */
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__IO uint32_t LAM_COUNTER14 ; /* LAM Counter Register, offset: 0x4ec */
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__IO uint32_t LAM_STATUS15 ; /* LAM Status Register, offset: 0x4f0 */
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__IO uint32_t LAM_CTRL15 ; /* LAM Control Register, offset: 0x4f4 */
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__IO uint32_t LAM_CONFIG15 ; /* LAM Configuration Register, offset: 0x4f8 */
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__IO uint32_t LAM_COUNTER15 ; /* LAM Counter Register, offset: 0x4fc */
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} ISM_Type, *ISM_MemMapPtr;
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/** Number of instances of the ISM module. */
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#define ISM_INSTANCE_COUNT (1u)
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/* ISM - Peripheral instance base addresses */
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/** Peripheral ISM base address */
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#define ISM_BASE (0x4001b000u)
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/** Peripheral ISM base pointer */
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#define ISM ((ISM_Type *)ISM_BASE)
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/** Array initializer of ISM peripheral base addresses */
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#define ISM_BASE_ADDRS {ISM_BASE}
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/** Array initializer of ISM peripheral base pointers */
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#define ISM_BASE_PTRS {ISM}
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// need fill by yourself
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///** Number of interrupt vector arrays for the ISM module. */
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//#define ISM_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the ISM module. */
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//#define ISM_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the ISM peripheral type */
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//#define ISM_IRQS {ISM_IRQn}
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/* ----------------------------------------------------------------------------
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-- ISM Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup ISM_Register_Masks ISM Register Masks
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* @{
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*/
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/* PARAM Bit Fields */
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#define ISM_PARAM_LAM_MASK 0x1F000000u
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#define ISM_PARAM_LAM_SHIFT 24u
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#define ISM_PARAM_LAM_WIDTH 5u
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#define ISM_PARAM_LAM(x) (((uint32_t)(((uint32_t)(x))<<ISM_PARAM_LAM_SHIFT))&ISM_PARAM_LAM_MASK)
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#define ISM_PARAM_FPC_MASK 0x3F0000u
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#define ISM_PARAM_FPC_SHIFT 16u
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#define ISM_PARAM_FPC_WIDTH 6u
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#define ISM_PARAM_FPC(x) (((uint32_t)(((uint32_t)(x))<<ISM_PARAM_FPC_SHIFT))&ISM_PARAM_FPC_MASK)
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#define ISM_PARAM_ECMC_MASK 0xFu
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#define ISM_PARAM_ECMC_SHIFT 0u
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#define ISM_PARAM_ECMC_WIDTH 4u
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#define ISM_PARAM_ECMC(x) (((uint32_t)(((uint32_t)(x))<<ISM_PARAM_ECMC_SHIFT))&ISM_PARAM_ECMC_MASK)
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/* PARAM Reg Mask */
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#define ISM_PARAM_MASK 0x1F3F000Fu
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/* CTRL Bit Fields */
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#define ISM_CTRL_EN_MASK 0x80000000u
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#define ISM_CTRL_EN_SHIFT 31u
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#define ISM_CTRL_EN_WIDTH 1u
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#define ISM_CTRL_EN(x) (((uint32_t)(((uint32_t)(x))<<ISM_CTRL_EN_SHIFT))&ISM_CTRL_EN_MASK)
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#define ISM_CTRL_IEN_MASK 0x1u
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#define ISM_CTRL_IEN_SHIFT 0u
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#define ISM_CTRL_IEN_WIDTH 1u
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#define ISM_CTRL_IEN(x) (((uint32_t)(((uint32_t)(x))<<ISM_CTRL_IEN_SHIFT))&ISM_CTRL_IEN_MASK)
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/* CTRL Reg Mask */
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#define ISM_CTRL_MASK 0x80000001u
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/* E_STATUS Bit Fields */
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#define ISM_E_STATUS_ECS_MASK 0xF0000u
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#define ISM_E_STATUS_ECS_SHIFT 16u
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#define ISM_E_STATUS_ECS_WIDTH 4u
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#define ISM_E_STATUS_ECS(x) (((uint32_t)(((uint32_t)(x))<<ISM_E_STATUS_ECS_SHIFT))&ISM_E_STATUS_ECS_MASK)
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#define ISM_E_STATUS_ES_MASK 0xFFFFu
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#define ISM_E_STATUS_ES_SHIFT 0u
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#define ISM_E_STATUS_ES_WIDTH 16u
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#define ISM_E_STATUS_ES(x) (((uint32_t)(((uint32_t)(x))<<ISM_E_STATUS_ES_SHIFT))&ISM_E_STATUS_ES_MASK)
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/* E_STATUS Reg Mask */
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#define ISM_E_STATUS_MASK 0x000FFFFFu
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/* E_CTRL Bit Fields */
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#define ISM_E_CTRL_ECE_MASK 0xF0000u
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#define ISM_E_CTRL_ECE_SHIFT 16u
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#define ISM_E_CTRL_ECE_WIDTH 4u
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#define ISM_E_CTRL_ECE(x) (((uint32_t)(((uint32_t)(x))<<ISM_E_CTRL_ECE_SHIFT))&ISM_E_CTRL_ECE_MASK)
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#define ISM_E_CTRL_EE_MASK 0xFFFFu
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#define ISM_E_CTRL_EE_SHIFT 0u
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#define ISM_E_CTRL_EE_WIDTH 16u
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#define ISM_E_CTRL_EE(x) (((uint32_t)(((uint32_t)(x))<<ISM_E_CTRL_EE_SHIFT))&ISM_E_CTRL_EE_MASK)
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/* E_CTRL Reg Mask */
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#define ISM_E_CTRL_MASK 0x000FFFFFu
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/* EC_CTRL Bit Fields */
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#define ISM_EC_CTRL_THRL_3_MASK 0xF0000000u
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#define ISM_EC_CTRL_THRL_3_SHIFT 28u
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#define ISM_EC_CTRL_THRL_3_WIDTH 4u
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#define ISM_EC_CTRL_THRL_3(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_THRL_3_SHIFT))&ISM_EC_CTRL_THRL_3_MASK)
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#define ISM_EC_CTRL_SEL_3_MASK 0xF000000u
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#define ISM_EC_CTRL_SEL_3_SHIFT 24u
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#define ISM_EC_CTRL_SEL_3_WIDTH 4u
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#define ISM_EC_CTRL_SEL_3(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_SEL_3_SHIFT))&ISM_EC_CTRL_SEL_3_MASK)
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#define ISM_EC_CTRL_THRL_2_MASK 0xF00000u
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#define ISM_EC_CTRL_THRL_2_SHIFT 20u
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#define ISM_EC_CTRL_THRL_2_WIDTH 4u
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#define ISM_EC_CTRL_THRL_2(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_THRL_2_SHIFT))&ISM_EC_CTRL_THRL_2_MASK)
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#define ISM_EC_CTRL_SEL_2_MASK 0xF0000u
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#define ISM_EC_CTRL_SEL_2_SHIFT 16u
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#define ISM_EC_CTRL_SEL_2_WIDTH 4u
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#define ISM_EC_CTRL_SEL_2(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_SEL_2_SHIFT))&ISM_EC_CTRL_SEL_2_MASK)
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#define ISM_EC_CTRL_THRL_1_MASK 0xF000u
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#define ISM_EC_CTRL_THRL_1_SHIFT 12u
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#define ISM_EC_CTRL_THRL_1_WIDTH 4u
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#define ISM_EC_CTRL_THRL_1(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_THRL_1_SHIFT))&ISM_EC_CTRL_THRL_1_MASK)
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#define ISM_EC_CTRL_SEL_1_MASK 0xF00u
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#define ISM_EC_CTRL_SEL_1_SHIFT 8u
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#define ISM_EC_CTRL_SEL_1_WIDTH 4u
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#define ISM_EC_CTRL_SEL_1(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_SEL_1_SHIFT))&ISM_EC_CTRL_SEL_1_MASK)
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#define ISM_EC_CTRL_THRL_0_MASK 0xF0u
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#define ISM_EC_CTRL_THRL_0_SHIFT 4u
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#define ISM_EC_CTRL_THRL_0_WIDTH 4u
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#define ISM_EC_CTRL_THRL_0(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_THRL_0_SHIFT))&ISM_EC_CTRL_THRL_0_MASK)
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#define ISM_EC_CTRL_SEL_0_MASK 0xFu
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#define ISM_EC_CTRL_SEL_0_SHIFT 0u
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#define ISM_EC_CTRL_SEL_0_WIDTH 4u
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#define ISM_EC_CTRL_SEL_0(x) (((uint32_t)(((uint32_t)(x))<<ISM_EC_CTRL_SEL_0_SHIFT))&ISM_EC_CTRL_SEL_0_MASK)
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/* EC_CTRL Reg Mask */
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#define ISM_EC_CTRL_MASK 0xFFFFFFFFu
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/* FPC_STATUS Bit Fields */
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#define ISM_FPC_STATUS_RGD_MASK 0x2u
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#define ISM_FPC_STATUS_RGD_SHIFT 1u
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#define ISM_FPC_STATUS_RGD_WIDTH 1u
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#define ISM_FPC_STATUS_RGD(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_STATUS_RGD_SHIFT))&ISM_FPC_STATUS_RGD_MASK)
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#define ISM_FPC_STATUS_FGD_MASK 0x1u
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#define ISM_FPC_STATUS_FGD_SHIFT 0u
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#define ISM_FPC_STATUS_FGD_WIDTH 1u
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#define ISM_FPC_STATUS_FGD(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_STATUS_FGD_SHIFT))&ISM_FPC_STATUS_FGD_MASK)
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/* FPC_STATUS0 Reg Mask */
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#define ISM_FPC_STATUS_MASK 0x00000003u
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/* FPC_CTRL Bit Fields */
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#define ISM_FPC_CTRL_IEN_MASK 0x2u
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#define ISM_FPC_CTRL_IEN_SHIFT 1u
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#define ISM_FPC_CTRL_IEN_WIDTH 1u
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#define ISM_FPC_CTRL_IEN(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CTRL_IEN_SHIFT))&ISM_FPC_CTRL_IEN_MASK)
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#define ISM_FPC_CTRL_EN_MASK 0x1u
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#define ISM_FPC_CTRL_EN_SHIFT 0u
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#define ISM_FPC_CTRL_EN_WIDTH 1u
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#define ISM_FPC_CTRL_EN(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CTRL_EN_SHIFT))&ISM_FPC_CTRL_EN_MASK)
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/* FPC_CTRL0 Reg Mask */
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#define ISM_FPC_CTRL_MASK 0x00000003u
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/* FPC_CONFIG Bit Fields */
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#define ISM_FPC_CONFIG_FEG_MASK 0xC00000u
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#define ISM_FPC_CONFIG_FEG_SHIFT 22u
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#define ISM_FPC_CONFIG_FEG_WIDTH 2u
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#define ISM_FPC_CONFIG_FEG(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CONFIG_FEG_SHIFT))&ISM_FPC_CONFIG_FEG_MASK)
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#define ISM_FPC_CONFIG_FED_MASK 0x300000u
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#define ISM_FPC_CONFIG_FED_SHIFT 20u
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#define ISM_FPC_CONFIG_FED_WIDTH 2u
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#define ISM_FPC_CONFIG_FED(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CONFIG_FED_SHIFT))&ISM_FPC_CONFIG_FED_MASK)
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#define ISM_FPC_CONFIG_REG_MASK 0xC0000u
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#define ISM_FPC_CONFIG_REG_SHIFT 18u
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#define ISM_FPC_CONFIG_REG_WIDTH 2u
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#define ISM_FPC_CONFIG_REG(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CONFIG_REG_SHIFT))&ISM_FPC_CONFIG_REG_MASK)
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#define ISM_FPC_CONFIG_RED_MASK 0x30000u
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#define ISM_FPC_CONFIG_RED_SHIFT 16u
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#define ISM_FPC_CONFIG_RED_WIDTH 2u
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#define ISM_FPC_CONFIG_RED(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CONFIG_RED_SHIFT))&ISM_FPC_CONFIG_RED_MASK)
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#define ISM_FPC_CONFIG_CMP_MASK 0xFFFFu
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#define ISM_FPC_CONFIG_CMP_SHIFT 0u
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#define ISM_FPC_CONFIG_CMP_WIDTH 16u
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#define ISM_FPC_CONFIG_CMP(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_CONFIG_CMP_SHIFT))&ISM_FPC_CONFIG_CMP_MASK)
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/* FPC_CONFIG0 Reg Mask */
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#define ISM_FPC_CONFIG_MASK 0x00FFFFFFu
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/* FPC_TIMER Bit Fields */
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#define ISM_FPC_TIMER_TIM_MASK 0xFFFFu
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#define ISM_FPC_TIMER_TIM_SHIFT 0u
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#define ISM_FPC_TIMER_TIM_WIDTH 16u
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#define ISM_FPC_TIMER_TIM(x) (((uint32_t)(((uint32_t)(x))<<ISM_FPC_TIMER_TIM_SHIFT))&ISM_FPC_TIMER_TIM_MASK)
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/* FPC_TIMER0 Reg Mask */
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#define ISM_FPC_TIMER_MASK 0x0000FFFFu
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/* LAM_STATUS Bit Fields */
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#define ISM_LAM_STATUS_OVFL_MASK 0x80000000u
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#define ISM_LAM_STATUS_OVFL_SHIFT 31u
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#define ISM_LAM_STATUS_OVFL_WIDTH 1u
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#define ISM_LAM_STATUS_OVFL(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_STATUS_OVFL_SHIFT))&ISM_LAM_STATUS_OVFL_MASK)
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#define ISM_LAM_STATUS_COUNT_MASK 0xFFFFFFu
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#define ISM_LAM_STATUS_COUNT_SHIFT 0u
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#define ISM_LAM_STATUS_COUNT_WIDTH 24u
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#define ISM_LAM_STATUS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_STATUS_COUNT_SHIFT))&ISM_LAM_STATUS_COUNT_MASK)
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/* LAM_STATUS0 Reg Mask */
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#define ISM_LAM_STATUS_MASK 0x80FFFFFFu
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/* LAM_CTRL Bit Fields */
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#define ISM_LAM_CTRL_IEN_MASK 0x2u
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#define ISM_LAM_CTRL_IEN_SHIFT 1u
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#define ISM_LAM_CTRL_IEN_WIDTH 1u
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#define ISM_LAM_CTRL_IEN(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CTRL_IEN_SHIFT))&ISM_LAM_CTRL_IEN_MASK)
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#define ISM_LAM_CTRL_EN_MASK 0x1u
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#define ISM_LAM_CTRL_EN_SHIFT 0u
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#define ISM_LAM_CTRL_EN_WIDTH 1u
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#define ISM_LAM_CTRL_EN(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CTRL_EN_SHIFT))&ISM_LAM_CTRL_EN_MASK)
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/* LAM_CTRL0 Reg Mask */
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#define ISM_LAM_CTRL_MASK 0x00000003u
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/* LAM_CONFIG Bit Fields */
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#define ISM_LAM_CONFIG_RCS_MASK 0xF000000u
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#define ISM_LAM_CONFIG_RCS_SHIFT 24u
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#define ISM_LAM_CONFIG_RCS_WIDTH 4u
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#define ISM_LAM_CONFIG_RCS(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_RCS_SHIFT))&ISM_LAM_CONFIG_RCS_MASK)
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#define ISM_LAM_CONFIG_MCS_MASK 0xF0000u
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#define ISM_LAM_CONFIG_MCS_SHIFT 16u
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#define ISM_LAM_CONFIG_MCS_WIDTH 4u
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#define ISM_LAM_CONFIG_MCS(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_MCS_SHIFT))&ISM_LAM_CONFIG_MCS_MASK)
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#define ISM_LAM_CONFIG_IVW_MASK 0x1000u
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#define ISM_LAM_CONFIG_IVW_SHIFT 12u
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#define ISM_LAM_CONFIG_IVW_WIDTH 1u
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#define ISM_LAM_CONFIG_IVW(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_IVW_SHIFT))&ISM_LAM_CONFIG_IVW_MASK)
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#define ISM_LAM_CONFIG_EDS_MASK 0xF00u
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#define ISM_LAM_CONFIG_EDS_SHIFT 8u
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#define ISM_LAM_CONFIG_EDS_WIDTH 4u
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#define ISM_LAM_CONFIG_EDS(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_EDS_SHIFT))&ISM_LAM_CONFIG_EDS_MASK)
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#define ISM_LAM_CONFIG_EWS_MASK 0x10u
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#define ISM_LAM_CONFIG_EWS_SHIFT 4u
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#define ISM_LAM_CONFIG_EWS_WIDTH 1u
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#define ISM_LAM_CONFIG_EWS(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_EWS_SHIFT))&ISM_LAM_CONFIG_EWS_MASK)
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#define ISM_LAM_CONFIG_RMS_MASK 0x8u
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#define ISM_LAM_CONFIG_RMS_SHIFT 3u
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#define ISM_LAM_CONFIG_RMS_WIDTH 1u
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#define ISM_LAM_CONFIG_RMS(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_RMS_SHIFT))&ISM_LAM_CONFIG_RMS_MASK)
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#define ISM_LAM_CONFIG_MOS_MASK 0x4u
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#define ISM_LAM_CONFIG_MOS_SHIFT 2u
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#define ISM_LAM_CONFIG_MOS_WIDTH 1u
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#define ISM_LAM_CONFIG_MOS(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_MOS_SHIFT))&ISM_LAM_CONFIG_MOS_MASK)
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#define ISM_LAM_CONFIG_IVM_MASK 0x2u
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#define ISM_LAM_CONFIG_IVM_SHIFT 1u
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#define ISM_LAM_CONFIG_IVM_WIDTH 1u
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#define ISM_LAM_CONFIG_IVM(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_IVM_SHIFT))&ISM_LAM_CONFIG_IVM_MASK)
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#define ISM_LAM_CONFIG_IVR_MASK 0x1u
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#define ISM_LAM_CONFIG_IVR_SHIFT 0u
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#define ISM_LAM_CONFIG_IVR_WIDTH 1u
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#define ISM_LAM_CONFIG_IVR(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_CONFIG_IVR_SHIFT))&ISM_LAM_CONFIG_IVR_MASK)
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/* LAM_CONFIG0 Reg Mask */
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#define ISM_LAM_CONFIG_MASK 0x0F0F1F1Fu
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/* LAM_COUNTER Bit Fields */
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#define ISM_LAM_COUNTER_CNT_MASK 0xFFFFFFu
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#define ISM_LAM_COUNTER_CNT_SHIFT 0u
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#define ISM_LAM_COUNTER_CNT_WIDTH 24u
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#define ISM_LAM_COUNTER_CNT(x) (((uint32_t)(((uint32_t)(x))<<ISM_LAM_COUNTER_CNT_SHIFT))&ISM_LAM_COUNTER_CNT_MASK)
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/* LAM_COUNTER0 Reg Mask */
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#define ISM_LAM_COUNTER_MASK 0x00FFFFFFu
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/*!
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* @}
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*/ /* end of group ISM_Register_Masks */
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/*!
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* @}
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*/ /* end of group ISM_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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