526 lines
13 KiB
C
526 lines
13 KiB
C
#ifndef _FC7240_FMC_NU_Tztufn25_REGS_H_
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#define _FC7240_FMC_NU_Tztufn25_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------------------------------------------------------
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-- FMC Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
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* @{
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*/
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/** FMC - Size of Registers Arrays */
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/** FMC - Register Layout Typedef */
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#define FMC_FB_FPELCK_COUNT 5
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#define FMC_FB_CPELCK_COUNT 4
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#define FMC_OTA_CTRL_COUNT 2
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#define FMC_OTA_VER_LOC_COUNT 2
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#define FMC_OTA_ACT_VER_COUNT 2
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typedef struct {
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__IO uint32_t FAPC0 ; /* Flash Access Port Control Register 0, offset: 0x0 */
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__IO uint32_t FAPC1 ; /* Flash Access Port Control Register 1, offset: 0x4 */
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__IO uint32_t FAPC2 ; /* Flash Access Port Control Register 2, offset: 0x8 */
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uint8_t RESERVED_0[4];
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__IO uint32_t FEEC ; /* Flash ECC Error Control Register, offset: 0x10 */
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uint8_t RESERVED_1[4];
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__IO uint32_t FEIPC ; /* Flash ECC Inject Position Control Register, offset: 0x18 */
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uint8_t RESERVED_2[740];
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__IO uint32_t FPESA_L ; /* Flash Program Erase Start Address Logical Register, offset: 0x300 */
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__I uint32_t FPESA_P ; /* Flash Program Erase Start Address Physical Register, offset: 0x304 */
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uint8_t RESERVED_3[56];
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__IO uint32_t FB_FPELCK[FMC_FB_FPELCK_COUNT]; /* Flash Block n Fine Program Erase Lock Register, offset: 0x340 */
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uint8_t RESERVED_4[4];
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__IO uint32_t FN_FPELCK ; /* Flash NVR Fine Program Erase Lock Register, offset: 0x358 */
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__IO uint32_t FB_CPELCK[FMC_FB_CPELCK_COUNT]; /* Flash Block n Coarse Program Erase Lock Register, offset: 0x35c */
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uint8_t RESERVED_5[404];
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__IO uint32_t OTA_CTRL[FMC_OTA_CTRL_COUNT] ; /* FLASH OTA Control Register, offset: 0x500 */
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__I uint32_t OTA_VER_LOC[FMC_OTA_VER_LOC_COUNT]; /* FLASH OTA Version Location Register, offset: 0x508 */
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__I uint32_t OTA_ACT_VER[FMC_OTA_ACT_VER_COUNT]; /* FLASH OTA Active Version Register, offset: 0x510 */
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} FMC_Type, *FMC_MemMapPtr;
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/** Number of instances of the FMC module. */
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#define FMC_INSTANCE_COUNT (2u)
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/* FMC - Peripheral instance base addresses */
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/** Peripheral FMC1 base address */
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#define FMC1_BASE (0x4001e000u)
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/** Peripheral FMC1 base pointer */
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#define FMC1 ((FMC_Type *)FMC1_BASE)
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/** Peripheral FMC0 base address */
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#define FMC0_BASE (0x4001f000u)
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/** Peripheral FMC0 base pointer */
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#define FMC0 ((FMC_Type *)FMC0_BASE)
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/** Array initializer of FMC peripheral base addresses */
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#define FMC_BASE_ADDRS {FMC0_BASE, FMC1_BASE}
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/** Array initializer of FMC peripheral base pointers */
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#define FMC_BASE_PTRS {FMC0, FMC1}
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// need fill by yourself
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///** Number of interrupt vector arrays for the FMC module. */
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//#define FMC_IRQS_ARR_COUNT (1u)
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///** Number of interrupt channels for the FMC module. */
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//#define FMC_IRQS_CH_COUNT (1u)
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///** Interrupt vectors for the FMC peripheral type */
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//#define FMC_IRQS {FMC0_IRQn, FMC1_IRQn}
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/* ----------------------------------------------------------------------------
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-- FMC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup FMC_Register_Masks FMC Register Masks
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* @{
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*/
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/* FAPC0 Bit Fields */
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#define FMC_FAPC0_DBPEN_MASK 0x20u
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#define FMC_FAPC0_DBPEN_SHIFT 5u
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#define FMC_FAPC0_DBPEN_WIDTH 1u
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#define FMC_FAPC0_DBPEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC0_DBPEN_SHIFT))&FMC_FAPC0_DBPEN_MASK)
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#define FMC_FAPC0_CBPEN_MASK 0x10u
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#define FMC_FAPC0_CBPEN_SHIFT 4u
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#define FMC_FAPC0_CBPEN_WIDTH 1u
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#define FMC_FAPC0_CBPEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC0_CBPEN_SHIFT))&FMC_FAPC0_CBPEN_MASK)
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#define FMC_FAPC0_DBBEN_MASK 0x2u
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#define FMC_FAPC0_DBBEN_SHIFT 1u
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#define FMC_FAPC0_DBBEN_WIDTH 1u
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#define FMC_FAPC0_DBBEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC0_DBBEN_SHIFT))&FMC_FAPC0_DBBEN_MASK)
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#define FMC_FAPC0_CBBEN_MASK 0x1u
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#define FMC_FAPC0_CBBEN_SHIFT 0u
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#define FMC_FAPC0_CBBEN_WIDTH 1u
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#define FMC_FAPC0_CBBEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC0_CBBEN_SHIFT))&FMC_FAPC0_CBBEN_MASK)
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/* FAPC0 Reg Mask */
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#define FMC_FAPC0_MASK 0x00000033u
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/* FAPC1 Bit Fields */
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#define FMC_FAPC1_DBPEN_MASK 0x20u
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#define FMC_FAPC1_DBPEN_SHIFT 5u
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#define FMC_FAPC1_DBPEN_WIDTH 1u
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#define FMC_FAPC1_DBPEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC1_DBPEN_SHIFT))&FMC_FAPC1_DBPEN_MASK)
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#define FMC_FAPC1_CBPEN_MASK 0x10u
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#define FMC_FAPC1_CBPEN_SHIFT 4u
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#define FMC_FAPC1_CBPEN_WIDTH 1u
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#define FMC_FAPC1_CBPEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC1_CBPEN_SHIFT))&FMC_FAPC1_CBPEN_MASK)
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#define FMC_FAPC1_DBBEN_MASK 0x2u
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#define FMC_FAPC1_DBBEN_SHIFT 1u
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#define FMC_FAPC1_DBBEN_WIDTH 1u
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#define FMC_FAPC1_DBBEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC1_DBBEN_SHIFT))&FMC_FAPC1_DBBEN_MASK)
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#define FMC_FAPC1_CBBEN_MASK 0x1u
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#define FMC_FAPC1_CBBEN_SHIFT 0u
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#define FMC_FAPC1_CBBEN_WIDTH 1u
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#define FMC_FAPC1_CBBEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC1_CBBEN_SHIFT))&FMC_FAPC1_CBBEN_MASK)
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/* FAPC1 Reg Mask */
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#define FMC_FAPC1_MASK 0x00000033u
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/* FAPC2 Bit Fields */
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#define FMC_FAPC2_DBPEN_MASK 0x20u
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#define FMC_FAPC2_DBPEN_SHIFT 5u
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#define FMC_FAPC2_DBPEN_WIDTH 1u
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#define FMC_FAPC2_DBPEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC2_DBPEN_SHIFT))&FMC_FAPC2_DBPEN_MASK)
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#define FMC_FAPC2_CBPEN_MASK 0x10u
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#define FMC_FAPC2_CBPEN_SHIFT 4u
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#define FMC_FAPC2_CBPEN_WIDTH 1u
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#define FMC_FAPC2_CBPEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC2_CBPEN_SHIFT))&FMC_FAPC2_CBPEN_MASK)
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#define FMC_FAPC2_DBBEN_MASK 0x2u
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#define FMC_FAPC2_DBBEN_SHIFT 1u
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#define FMC_FAPC2_DBBEN_WIDTH 1u
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#define FMC_FAPC2_DBBEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC2_DBBEN_SHIFT))&FMC_FAPC2_DBBEN_MASK)
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#define FMC_FAPC2_CBBEN_MASK 0x1u
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#define FMC_FAPC2_CBBEN_SHIFT 0u
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#define FMC_FAPC2_CBBEN_WIDTH 1u
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#define FMC_FAPC2_CBBEN(x) (((uint32_t)(((uint32_t)(x))<<FMC_FAPC2_CBBEN_SHIFT))&FMC_FAPC2_CBBEN_MASK)
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/* FAPC2 Reg Mask */
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#define FMC_FAPC2_MASK 0x00000033u
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/* FEEC Bit Fields */
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#define FMC_FEEC_CEIE_SET_MASK 0xF0000000u
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#define FMC_FEEC_CEIE_SET_SHIFT 28u
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#define FMC_FEEC_CEIE_SET_WIDTH 4u
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#define FMC_FEEC_CEIE_SET(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEEC_CEIE_SET_SHIFT))&FMC_FEEC_CEIE_SET_MASK)
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#define FMC_FEEC_EIE_SET_MASK 0xF000000u
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#define FMC_FEEC_EIE_SET_SHIFT 24u
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#define FMC_FEEC_EIE_SET_WIDTH 4u
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#define FMC_FEEC_EIE_SET(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEEC_EIE_SET_SHIFT))&FMC_FEEC_EIE_SET_MASK)
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#define FMC_FEEC_EDATAC_POS2_MASK 0xF00000u
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#define FMC_FEEC_EDATAC_POS2_SHIFT 20u
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#define FMC_FEEC_EDATAC_POS2_WIDTH 4u
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#define FMC_FEEC_EDATAC_POS2(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEEC_EDATAC_POS2_SHIFT))&FMC_FEEC_EDATAC_POS2_MASK)
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#define FMC_FEEC_EDATAC_POS1_MASK 0xF0000u
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#define FMC_FEEC_EDATAC_POS1_SHIFT 16u
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#define FMC_FEEC_EDATAC_POS1_WIDTH 4u
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#define FMC_FEEC_EDATAC_POS1(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEEC_EDATAC_POS1_SHIFT))&FMC_FEEC_EDATAC_POS1_MASK)
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#define FMC_FEEC_DDBEE_MASK 0x80u
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#define FMC_FEEC_DDBEE_SHIFT 7u
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#define FMC_FEEC_DDBEE_WIDTH 1u
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#define FMC_FEEC_DDBEE(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEEC_DDBEE_SHIFT))&FMC_FEEC_DDBEE_MASK)
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#define FMC_FEEC_DES_MASK 0x1u
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#define FMC_FEEC_DES_SHIFT 0u
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#define FMC_FEEC_DES_WIDTH 1u
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#define FMC_FEEC_DES(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEEC_DES_SHIFT))&FMC_FEEC_DES_MASK)
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/* FEEC Reg Mask */
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#define FMC_FEEC_MASK 0xFFFF0081u
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/* FEIPC Bit Fields */
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#define FMC_FEIPC_EDATA_POS1_MASK 0x1FFu
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#define FMC_FEIPC_EDATA_POS1_SHIFT 0u
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#define FMC_FEIPC_EDATA_POS1_WIDTH 9u
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#define FMC_FEIPC_EDATA_POS1(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEIPC_EDATA_POS1_SHIFT))&FMC_FEIPC_EDATA_POS1_MASK)
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#define FMC_FEIPC_EDATA_POS2_MASK 0x1FF0000u
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#define FMC_FEIPC_EDATA_POS2_SHIFT 16u
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#define FMC_FEIPC_EDATA_POS2_WIDTH 9u
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#define FMC_FEIPC_EDATA_POS2(x) (((uint32_t)(((uint32_t)(x))<<FMC_FEIPC_EDATA_POS2_SHIFT))&FMC_FEIPC_EDATA_POS2_MASK)
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/* FEIPC Reg Mask */
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#define FMC_FEIPC_MASK 0x01FF01FFu
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/* FPESA_L Bit Fields */
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#define FMC_FPESA_L_PESA_L_MASK 0xFFFFFFFFu
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#define FMC_FPESA_L_PESA_L_SHIFT 0u
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#define FMC_FPESA_L_PESA_L_WIDTH 32u
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#define FMC_FPESA_L_PESA_L(x) (((uint32_t)(((uint32_t)(x))<<FMC_FPESA_L_PESA_L_SHIFT))&FMC_FPESA_L_PESA_L_MASK)
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/* FPESA_L Reg Mask */
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#define FMC_FPESA_L_MASK 0xFFFFFFFFu
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/* FPESA_P Bit Fields */
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#define FMC_FPESA_P_PESA_P_MASK 0xFFFFFFFFu
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#define FMC_FPESA_P_PESA_P_SHIFT 0u
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#define FMC_FPESA_P_PESA_P_WIDTH 32u
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#define FMC_FPESA_P_PESA_P(x) (((uint32_t)(((uint32_t)(x))<<FMC_FPESA_P_PESA_P_SHIFT))&FMC_FPESA_P_PESA_P_MASK)
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/* FPESA_P Reg Mask */
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#define FMC_FPESA_P_MASK 0xFFFFFFFFu
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/* FB_FPELCK Bit Fields */
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#define FMC_FB_FPELCK_FPELCK_MASK 0xFFFFFFFFu
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#define FMC_FB_FPELCK_FPELCK_SHIFT 0u
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#define FMC_FB_FPELCK_FPELCK_WIDTH 32u
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#define FMC_FB_FPELCK_FPELCK(x) (((uint32_t)(((uint32_t)(x))<<FMC_FB_FPELCK_FPELCK_SHIFT))&FMC_FB_FPELCK_FPELCK_MASK)
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/* FB_FPELCK0 Reg Mask */
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#define FMC_FB_FPELCK_MASK 0xFFFFFFFFu
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/* FN_FPELCK Bit Fields */
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#define FMC_FN_FPELCK_FPELCK_MASK 0x1u
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#define FMC_FN_FPELCK_FPELCK_SHIFT 0u
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#define FMC_FN_FPELCK_FPELCK_WIDTH 1u
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#define FMC_FN_FPELCK_FPELCK(x) (((uint32_t)(((uint32_t)(x))<<FMC_FN_FPELCK_FPELCK_SHIFT))&FMC_FN_FPELCK_FPELCK_MASK)
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/* FN_FPELCK Reg Mask */
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#define FMC_FN_FPELCK_MASK 0x00000001u
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/* FB_CPELCK Bit Fields */
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#define FMC_FB_CPELCK_CPELCK_MASK 0xFFFFFFFFu
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#define FMC_FB_CPELCK_CPELCK_SHIFT 0u
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#define FMC_FB_CPELCK_CPELCK_WIDTH 32u
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#define FMC_FB_CPELCK_CPELCK(x) (((uint32_t)(((uint32_t)(x))<<FMC_FB_CPELCK_CPELCK_SHIFT))&FMC_FB_CPELCK_CPELCK_MASK)
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/* FB_CPELCK0 Reg Mask */
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#define FMC_FB_CPELCK_MASK 0xFFFFFFFFu
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/* OTA_CTRL Bit Fields */
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#define FMC_OTA_CTRL_OTA_LOCK_MASK 0x40u
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#define FMC_OTA_CTRL_OTA_LOCK_SHIFT 6u
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#define FMC_OTA_CTRL_OTA_LOCK_WIDTH 1u
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#define FMC_OTA_CTRL_OTA_LOCK(x) (((uint32_t)(((uint32_t)(x))<<FMC_OTA_CTRL_OTA_LOCK_SHIFT))&FMC_OTA_CTRL_OTA_LOCK_MASK)
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#define FMC_OTA_CTRL_OTA_ACTIVE_MASK 0x20u
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#define FMC_OTA_CTRL_OTA_ACTIVE_SHIFT 5u
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#define FMC_OTA_CTRL_OTA_ACTIVE_WIDTH 1u
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#define FMC_OTA_CTRL_OTA_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<FMC_OTA_CTRL_OTA_ACTIVE_SHIFT))&FMC_OTA_CTRL_OTA_ACTIVE_MASK)
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#define FMC_OTA_CTRL_OTA_EN_MASK 0x1Fu
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#define FMC_OTA_CTRL_OTA_EN_SHIFT 0u
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#define FMC_OTA_CTRL_OTA_EN_WIDTH 5u
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#define FMC_OTA_CTRL_OTA_EN(x) (((uint32_t)(((uint32_t)(x))<<FMC_OTA_CTRL_OTA_EN_SHIFT))&FMC_OTA_CTRL_OTA_EN_MASK)
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/* OTA_CTRL0 Reg Mask */
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#define FMC_OTA_CTRL_MASK 0x0000007Fu
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/* OTA_VER_LOC Bit Fields */
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#define FMC_OTA_VER_LOC_OTA_VER_LOC_MASK 0xFFFFFu
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#define FMC_OTA_VER_LOC_OTA_VER_LOC_SHIFT 0u
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#define FMC_OTA_VER_LOC_OTA_VER_LOC_WIDTH 20u
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#define FMC_OTA_VER_LOC_OTA_VER_LOC(x) (((uint32_t)(((uint32_t)(x))<<FMC_OTA_VER_LOC_OTA_VER_LOC_SHIFT))&FMC_OTA_VER_LOC_OTA_VER_LOC_MASK)
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/* OTA_VER_LOC0 Reg Mask */
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#define FMC_OTA_VER_LOC_MASK 0x000FFFFFu
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/* OTA_ACT_VER Bit Fields */
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#define FMC_OTA_ACT_VER_OTA_ACT_VER_MASK 0xFFFFu
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#define FMC_OTA_ACT_VER_OTA_ACT_VER_SHIFT 0u
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#define FMC_OTA_ACT_VER_OTA_ACT_VER_WIDTH 16u
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#define FMC_OTA_ACT_VER_OTA_ACT_VER(x) (((uint32_t)(((uint32_t)(x))<<FMC_OTA_ACT_VER_OTA_ACT_VER_SHIFT))&FMC_OTA_ACT_VER_OTA_ACT_VER_MASK)
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/* OTA_ACT_VER0 Reg Mask */
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#define FMC_OTA_ACT_VER_MASK 0x0000FFFFu
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/*!
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* @}
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*/ /* end of group FMC_Register_Masks */
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/*!
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* @}
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*/ /* end of group FMC_Peripheral_Access_Layer */
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#ifdef __cplusplus
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}
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#endif
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#endif
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