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Inc/HwA_adc.h Normal file
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/**
* @file HwA_aontimer.h
* @author Flagchip
* @brief aontimer hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip076 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip076 N/A Change version and release
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_AONTIMER_H_
#define HWA_INCLUDE_HWA_AONTIMER_H_
#include "device_header.h"
#if AONTIMER_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_aontimer HwA_aontimer
* @ingroup module_driver_aontimer
* @{
*
*/
/********* Local typedef ************/
/**
* @brief The clock source of the pulse mode
*
*/
typedef enum
{
AONTIMER_CLK0_PIN = 0, /*!< select the Aontimer_clk0 pin as pulse sourse*/
AONTIMER_CLK1_PIN, /*!< select the Aontimer_clk1 pin as pulse sourse*/
AONTIMER_CLK2_PIN, /*!< select the Aontimer_clk2 pin as pulse sourse*/
AONTIMER_TRGSEL_OUTPUT, /*!< select the tresel as pulse sourse*/
} AONTIMER_PulseClkSrcType;
/**
* @brief Aontimer clock source, please refer to Reference Manual chapter8.Aontimer for details.
*
* */
typedef enum
{
AONTIMER_SIRC_1MHZ = 0U, /*!< AONTIMER SIRC 1mhz clock */
AONTIMER_RTC_CLK = 2U, /*!< AONTIMER RTC clock */
AONTIMER_IRC_CLK = 3U /*!< AONTIMER internal clock, which comes from PCC */
} AONTIMER_ClkSrcType;
/**
* @brief The polarity of pulse mode
*
* */
typedef enum
{
AONTIMER_PulsePolarityType_HIGH = 0, /*!< select the high polarity */
AONTIMER_PulsePolarityType_LOW /*!< select the low polarity */
} AONTIMER_PulsePolarityType;
/********* Local inline function ************/
/**
* @brief Configure AONTIMER module
*
* @param pAontimer the base address of the pAontimer instance.
* @param u32RegValue CSR register value
*/
LOCAL_INLINE void AONTIMER_HWA_ConfigModule(AONTIMER_Type *const pAontimer, uint32_t u32RegValue)
{
pAontimer->CSR = u32RegValue;
}
/**
* @brief Configure AONTIMER module prescale
*
* @param pAontimer the base address of the pAontimer instance.
* @param u32RegValue PSR register value
*/
LOCAL_INLINE void AONTIMER_HWA_ConfigModulePrescale(AONTIMER_Type *const pAontimer, uint32_t u32RegValue)
{
pAontimer->PSR = u32RegValue;
}
/**
* @brief Set AONTIMER compare value
*
* @param pAontimer the base address of the pAontimer instance.
* @param u32RegValue CMR register value
*/
LOCAL_INLINE void AONTIMER_HWA_SetModuleCompareValue(AONTIMER_Type *const pAontimer, uint32_t u32RegValue)
{
pAontimer->CMR = u32RegValue;
}
/**
* @brief Set AONTIMER current counter value
*
* @param pAontimer the base address of the pAontimer instance.
* @param u32RegValue CNR register value
*/
LOCAL_INLINE void AONTIMER_HWA_SetModuleCounterValue(AONTIMER_Type *const pAontimer, uint32_t u32RegValue)
{
pAontimer->CNR = u32RegValue;
}
/**
* @brief Set AONTIMER module running on debug mode
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_SetModuleRunOnDebug(AONTIMER_Type *const pAontimer)
{
uint32_t u32RegValue = pAontimer->CSR;
u32RegValue |= (uint32_t)AONTIMER_CSR_DBGEN_MASK;
u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK;
pAontimer->CSR = u32RegValue;
}
/**
* @brief Enable AONTIMER module interrupt
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_EnableModuleInterrupt(AONTIMER_Type *const pAontimer)
{
uint32_t u32RegValue = pAontimer->CSR;
u32RegValue |= (uint32_t)AONTIMER_CSR_TIE_MASK;
u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK;
pAontimer->CSR = u32RegValue;
}
/**
* @brief Select AONTIMER module external clock source when timer configured to pulse mode
*
* @param pAontimer the base address of the pAontimer instance.
* @param eClk Input counter clock source
*/
LOCAL_INLINE void AONTIMER_HWA_SelectClkSrcOnPulseMode(AONTIMER_Type *const pAontimer, AONTIMER_PulseClkSrcType eClk)
{
uint32_t u32RegValue = pAontimer->CSR;
u32RegValue |= (u32RegValue & ~(uint32_t)AONTIMER_CSR_TPS_MASK) | AONTIMER_CSR_TPS(eClk);
u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK;
pAontimer->CSR = u32RegValue;
}
/**
* @brief Clear AONTIMER interrupt flags
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_ClearInterruptFlag(AONTIMER_Type *const pAontimer)
{
pAontimer->CSR |= (uint32_t)AONTIMER_CSR_TCF_MASK;
}
/**
* @brief Set AONTIMER module polarity. Pulse counter input source is active-low, and the CNR increments on falling-edge.
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_SetModulePolarity(AONTIMER_Type *const pAontimer)
{
uint32_t u32RegValue = pAontimer->CSR;
u32RegValue |= (uint32_t)AONTIMER_CSR_TPP_MASK;
u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK;
pAontimer->CSR = u32RegValue;
}
/**
* @brief Configure AONTIMER module polarity. If ePol is 0:Pulse counter input source is active-high, and the CNR increments on rising-edge.
* If ePol is 1:Pulse counter input source is active-low, and the CNR increments on falling-edge.
*
* @param pAontimer the base address of the pAontimer instance.
* @param ePol Polarity enumeration
*/
LOCAL_INLINE void AONTIMER_HWA_ConfigModulePolarity(AONTIMER_Type *const pAontimer, AONTIMER_PulsePolarityType ePol)
{
uint32_t u32RegValue = pAontimer->CSR;
u32RegValue |= AONTIMER_CSR_TPP(ePol);
u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK;
pAontimer->CSR = u32RegValue;
}
/**
* @brief Enable AONTIMER module pulse mode
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_EnablePulseMode(AONTIMER_Type *const pAontimer)
{
uint32_t u32RegValue = pAontimer->CSR;
u32RegValue |= (uint32_t)AONTIMER_CSR_TMS_MASK;
u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK;
pAontimer->CSR = u32RegValue;
}
/**
* @brief Enable AONTIMER timer
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_EnableTimer(AONTIMER_Type *const pAontimer)
{
uint32_t u32RegValue = pAontimer->CSR;
u32RegValue |= (uint32_t)AONTIMER_CSR_TEN_MASK;
u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK;
pAontimer->CSR = u32RegValue;
}
/**
* @brief Set AONTIMER prescale
*
* @param pAontimer the base address of the pAontimer instance.
* @param u8PrescalerValue Prescaler value,the range of the input value is :0~15, and the range of prescaler is :2^1 ~ 2^16.
*/
LOCAL_INLINE void AONTIMER_HWA_SetPrescale(AONTIMER_Type *const pAontimer, uint8_t u8PrescalerValue)
{
uint32_t u32RegValue = pAontimer->PSR;
pAontimer->PSR = ((u32RegValue & ~(uint32_t)AONTIMER_PSR_PRESCALE_MASK) | AONTIMER_PSR_PRESCALE(u8PrescalerValue));
}
/**
* @brief If enable bypass mode, the timer will bypass the prescaler in timer counter mode or glitch filter in pulse mode
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_EnableBypassMode(AONTIMER_Type *const pAontimer)
{
pAontimer->PSR |= (uint32_t)AONTIMER_PSR_PBYP_MASK;
}
/**
* @brief Select AONTIMER mdoule clock source
*
* @param pAontimer the base address of the pAontimer instance.
* @param eClk Aontimer clock source
*/
LOCAL_INLINE void AONTIMER_HWA_SelectModuleClkSrc(AONTIMER_Type *const pAontimer, AONTIMER_ClkSrcType eClk)
{
uint32_t u32RegValue = pAontimer->PSR;
pAontimer->PSR = ((u32RegValue & ~(uint32_t)AONTIMER_PSR_PCS_MASK) | AONTIMER_PSR_PCS(eClk));
}
/**
* @brief Set AONTIMER module stop on debug mode
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_SetModuleStopOnDebug(AONTIMER_Type *const pAontimer)
{
pAontimer->CSR &= ~(uint32_t)(AONTIMER_CSR_DBGEN_MASK | AONTIMER_CSR_TCF_MASK);
}
/**
* @brief Disable AONTIMER module interrupt
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_DisableModuleInterrupt(AONTIMER_Type *const pAontimer)
{
pAontimer->CSR &= ~(uint32_t)(AONTIMER_CSR_TIE_MASK | AONTIMER_CSR_TCF_MASK);
}
/**
* @brief Clear AONTIMER module mode
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_ClearModuleMode(AONTIMER_Type *const pAontimer)
{
pAontimer->CSR &= ~(uint32_t)(AONTIMER_CSR_TPS_MASK | AONTIMER_CSR_TCF_MASK);
}
/**
* @brief Clear AONTIMER module polarity. Pulse counter input source is active-high, and the CNR increments on rising-edge.
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_ClearModulePolarity(AONTIMER_Type *const pAontimer)
{
pAontimer->CSR &= ~(uint32_t)(AONTIMER_CSR_TPP_MASK | AONTIMER_CSR_TCF_MASK);
}
/**
* @brief Disable AONTIEMR module pulse mode
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_DisablePulseMode(AONTIMER_Type *const pAontimer)
{
pAontimer->CSR &= ~(uint32_t)(AONTIMER_CSR_TMS_MASK | AONTIMER_CSR_TCF_MASK);
}
/**
* @brief Disable AONTIMER module timer
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_DisableTimer(AONTIMER_Type *const pAontimer)
{
pAontimer->CSR &= ~(uint32_t)(AONTIMER_CSR_TEN_MASK | AONTIMER_CSR_TCF_MASK);
}
/**
* @brief Clear AONTIMER module prescaler
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_ClearPrescale(AONTIMER_Type *const pAontimer)
{
pAontimer->PSR &= ~(uint32_t)AONTIMER_PSR_PRESCALE_MASK;
}
/**
* @brief If disable bypass mode, the timer will enable the prescaler in timer counter mode or glitch filter in pulse mode
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_DisableBypassMode(AONTIMER_Type *const pAontimer)
{
pAontimer->PSR &= ~(uint32_t)AONTIMER_PSR_PBYP_MASK;
}
/**
* @brief Clear AONTIMER module clock source
*
* @param pAontimer the base address of the pAontimer instance.
*/
LOCAL_INLINE void AONTIMER_HWA_ClearModuleClkSrc(AONTIMER_Type *const pAontimer)
{
pAontimer->PSR &= ~(uint32_t)AONTIMER_PSR_PCS_MASK;
}
/** @}*/ /* HwA_AONTIMER */
#endif /* #if AONTIMER_INSTANCE_COUNT > 0U */
#endif /* HWA_INCLUDE_HWA_AONTIMER_H_ */

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/**
* @file HwA_cm7.h
* @author Flagchip
* @brief cortex m4 hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
#ifndef _HWA_CM7_H_
#define _HWA_CM7_H_
#include "device_header.h"
/**
* @brief Enable deepsleep mode
*
*/
LOCAL_INLINE void CM7_HWA_EnableDeepSleep(void)
{
SCB->SCR |= (uint32_t)SCB_SCR_SLEEPDEEP_Msk;
}
/**
* @brief Disable deepsleep mode
*
*/
LOCAL_INLINE void CM7_HWA_DisableDeepSleep(void)
{
SCB->SCR &= ~(uint32_t)SCB_SCR_SLEEPDEEP_Msk;
}
#endif /* #ifndef _HWA_CM7_H_ */

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/**
* @file HwA_cmp.h
* @author Flagchip
* @brief CMP driver type definition and API
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip055 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip055 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_CMP_H_
#define _HWA_CMP_H_
#include "device_header.h"
#if CMP_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_cmp HwA_cmp
* @ingroup module_driver_cmp
* @{
*
*/
/********* Local typedef ************/
/**
* @brief The instance index of the CMP mode
*/
typedef enum
{
CMP_MODE_DISABLE = 0U, /*!< CMP function mode is disable */
CMP_MODE_CONTINUOUS = 1U, /*!< CMP function mode is continuous */
CMP_MODE_SAMPLE_NONFILTER_EXTCLK = 2U, /*!< CMP function mode is sampled,non-filtered mode 1*/
CMP_MODE_SAMPLE_NONFILTER_INTCLK = 3U, /*!< CMP function mode is sampled,non-filtered mode 2*/
CMP_MODE_SAMPLE_FILTER_EXTCLK = 4U, /*!< CMP function mode is sampled,filtered mode 1*/
CMP_MODE_SAMPLE_FILTER_INTCLK = 5U, /*!< CMP function mode is sampled,filtered mode 2*/
CMP_MODE_WINDOW = 6U, /*!< CMP function mode is windowed mode */
CMP_MODE_WINDOW_RESAMPLE = 7U, /*!< CMP function mode is windowed,re-sampled mode */
CMP_MODE_WINDOW_FILTER = 8U, /*!< CMP function mode is windowed,filtered mode */
#ifdef CMP_SUPPORT_CHANNELSCAN_MODE_FEATURE
CMP_MODE_CHANNEL_SCAN = 9U /*!< CMP channel scan mode */
#endif
} CMP_ModeSelType;
/**
* @brief The instance index of the CMP peripheral
*/
typedef enum
{
CMP_INSTANCE_0 = 0U, /*!< CMP instance 0 is selected */
CMP_INSTANCE_1 = 1U, /*!< CMP instance 1 is selected */
CMP_INSTANCE_2 = 2U /*!< CMP instance 2 is selected */
} CMP_InstanceType;
/**
* @brief The instance index of the CMP DAC enable select
*/
typedef enum
{
CMP_DACENABLE_DCR = 0U, /*!< CMP Dac is enabled by DCR[DAC_EN] */
CMP_DACENABLE_CCR0 = 1U /*!< CMP Dac is enabled by CCR0[EN] */
} CMP_DacEnableSrcType;
/**
* @brief The instance index of the CMP output invert
*/
typedef enum
{
CMP_NON_INVERT = 0U, /*!< CMP output do not Invert*/
CMP_INVERT = 1U /*!< CMP output Invert */
} CMP_InvertType;
/**
* @brief The instance index of the CMP output select
*/
typedef enum
{
CMP_FILTEROUT = 0U, /*!< CMP filter output */
CMP_UNFILTEROUT = 1U /*!< CMP Unfilter output */
} CMP_OutSelectType;
/**
* @brief The instance index of the CMP window level
*/
typedef enum
{
CMP_HOLD = 0U, /*!< CMP output hold when window close */
CMP_USERDEF = 1U /*!< CMP output userdefine when window close */
} CMP_OutWinLevelType;
/**
* @brief The instance index of the window output under userdefine CMP window level
*/
typedef enum
{
CMP_OUTWIN_0 = 0U, /*!< CMP window output is 0 */
CMP_OUTWIN_1 = 1U /*!< CMP window output is 1 */
} CMP_OutWinLevel_UserDefType;
/**
* @brief The instance index of the CMP Event caused window close
*/
typedef enum
{
CMP_RISINGEDGE = 0U, /*!< CMP output event RisingEdge causes window close */
CMP_FALLINGEDGE = 1U, /*!< CMP output event FallingEdge causes window close */
CMP_BOTHEDGES = 2U, /*!< CMP output event bothEdges causes window close */
} CMP_EventType;
/**
* @brief The instance index of the CMP filter count numbers
*/
typedef enum
{
CMP_FILTERCNT_0 = 0U, /*!< CMP filter is bypassed */
CMP_FILTERCNT_1 = 1U, /*!< CMP filter is 1 consecutive sample */
CMP_FILTERCNT_2 = 2U, /*!< CMP filter is 2 consecutive sample */
CMP_FILTERCNT_3 = 3U, /*!< CMP filter is 3 consecutive sample */
CMP_FILTERCNT_4 = 4U /*!< CMP filter is 4 consecutive sample */
} CMP_FilterCntType;
/**
* @brief The instance index of the CMP hysteresis control
*/
typedef enum
{
CMP_HYSTCTRL_0 = 0U, /*!< CMP 0 hysteresis internal */
CMP_HYSTCTRL_1 = 1U, /*!< CMP 1 hysteresis internal */
CMP_HYSTCTRL_2 = 2U, /*!< CMP 2 hysteresis internal */
CMP_HYSTCTRL_3 = 3U /*!< CMP 3 hysteresis internal */
} CMP_HystCtrlType;
#ifdef CMP_SUPPORT_CHANNELSCAN_MODE_FEATURE
/**
* @brief The fixed CMP port for reference in channel scan mode
*/
typedef enum
{
CMP_PORTSEL_MUX_P = 0U, /*!< CMP Positive Port */
CMP_PORTSEL_MUX_N = 1U /*!< CMP Negative Port */
} CMP_PortSelType;
#endif
/**
* @brief The source of the CMP input
*/
typedef enum
{
CMP_INSRCSEL_DAC = 0U, /*!< CMP input source is DAC */
CMP_INSRCSEL_MUX = 1U /*!< CMP input source is analog 1-8 mux */
} CMP_INSrcSelType;
/**
* @brief The instance index of the CMP input mux
*/
typedef enum
{
CMP_INSEL_MUX_IN0 = 0U, /*!< CMP input mux from IN0(CMP0,CMP1,CMP2) */
CMP_INSEL_MUX_IN1 = 1U, /*!< CMP input mux from IN1(CMP0,CMP1,CMP2) */
CMP_INSEL_MUX_IN2 = 2U, /*!< CMP input mux from IN2(CMP0,CMP1,CMP2) */
CMP_INSEL_MUX_IN3 = 3U, /*!< CMP input mux from IN3(CMP0,CMP1,CMP2) */
CMP_INSEL_MUX_IN4 = 4U, /*!< CMP input mux from IN4(CMP0,CMP1,CMP2) */
CMP_INSEL_MUX_IN5 = 5U, /*!< CMP input mux from IN5(CMP1,CMP2) */
CMP_INSEL_MUX_IN6 = 6U, /*!< CMP input mux from IN6(CMP1,CMP2) */
CMP_INSEL_MUX_IN7 = 7U /*!< CMP input mux from IN7(CMP1,CMP2) */
} CMP_MuxSelType;
/**
* @brief The instance index of high power mode select
*/
typedef enum
{
CMP_LOWSPEEDMODE = 0U, /*!< CMP low speed mode */
CMP_HIGHSPEEDMODE = 1U /*!< CMP high speed mode */
} CMP_SpeedModeSelType;
/**
* @brief Defines CMP out status
*/
typedef enum
{
CMP_OUT_FALLING_EDGE = 0U, /*!< CMP out detect falling edge */
CMP_OUT_RISING_EDGE = 1U, /*!< CMP out detect rising edge */
CMP_OUT_NONE = 2U /*!< CMP out detect none */
} CMP_OutStatus;
/********* Local inline function ************/
/**
* @brief set CMP enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetEn(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CCR0;
pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_EN_MASK)) | CMP_CCR0_EN(bEnable));
}
/**
* @brief STOP mode enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetEnLPMode(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CCR0;
pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_LP_EN_MASK)) | CMP_CCR0_LP_EN(bEnable));
}
/**
* @brief set DAC enable selection
*
* @param pCmp the CMP instance to use
* @param eType Dac enable source
*/
LOCAL_INLINE void CMP_HWA_SetDacEnableSrc(CMP_Type *const pCmp, CMP_DacEnableSrcType eType)
{
uint32_t u32RegVal = pCmp->CCR0;
pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_DACEN_SEL_MASK)) | CMP_CCR0_DACEN_SEL(eType));
}
/**
* @brief set CMP DMA enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetDma(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_DMA_EN_MASK)) | CMP_CCR1_DMA_EN(bEnable));
}
/**
* @brief set CMP mode
*
* @param pCmp the CMP instance to use
* @param eMod the CMP mode to use
* @param u8FilterPrd the CMP filter period
* @param eFilterCnt the CMP filter sample count
*/
LOCAL_INLINE void CMP_HWA_SetComparatorMode(CMP_Type *const pCmp, CMP_ModeSelType eMode, uint8_t u8FilterPrd, CMP_FilterCntType eFilterCnt)
{
uint32_t u32RegVal = pCmp->CCR1;
switch (eMode)
{
case CMP_MODE_DISABLE:
{
/* Nothing deal with */
}
break;
case CMP_MODE_CONTINUOUS:
{
u32RegVal &= ~CMP_CCR1_WIN_EN_MASK;
u32RegVal &= ~CMP_CCR1_SAMPLE_EN_MASK;
u32RegVal &= ~CMP_CCR1_FILT_PER_MASK;
u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK;
}
break;
case CMP_MODE_SAMPLE_NONFILTER_EXTCLK:
{
u32RegVal &= ~CMP_CCR1_WIN_EN_MASK;
u32RegVal |= CMP_CCR1_SAMPLE_EN(true);
u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK;
u32RegVal |= CMP_CCR1_FILT_CNT(0x01);
}
break;
case CMP_MODE_SAMPLE_NONFILTER_INTCLK:
{
u32RegVal &= ~CMP_CCR1_WIN_EN_MASK;
u32RegVal &= ~CMP_CCR1_SAMPLE_EN_MASK;
u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK;
u32RegVal &= ~CMP_CCR1_FILT_PER_MASK;
u32RegVal |= CMP_CCR1_FILT_CNT(0x01)|
CMP_CCR1_FILT_PER(u8FilterPrd);
}
break;
case CMP_MODE_SAMPLE_FILTER_EXTCLK:
{
u32RegVal &= ~CMP_CCR1_WIN_EN_MASK;
u32RegVal |= CMP_CCR1_SAMPLE_EN(true);
u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK;
u32RegVal |= CMP_CCR1_FILT_CNT(eFilterCnt);
}
break;
case CMP_MODE_SAMPLE_FILTER_INTCLK:
{
u32RegVal &= ~CMP_CCR1_WIN_EN_MASK;
u32RegVal &= ~CMP_CCR1_SAMPLE_EN_MASK;
u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK;
u32RegVal &= ~CMP_CCR1_FILT_PER_MASK;
u32RegVal |= CMP_CCR1_FILT_CNT(eFilterCnt)|
CMP_CCR1_FILT_PER(u8FilterPrd);
}
break;
case CMP_MODE_WINDOW:
{
u32RegVal |= CMP_CCR1_WIN_EN(true);
u32RegVal &= ~CMP_CCR1_SAMPLE_EN_MASK;
u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK;
u32RegVal &= ~CMP_CCR1_FILT_PER_MASK;
}
break;
case CMP_MODE_WINDOW_RESAMPLE:
{
u32RegVal |= CMP_CCR1_WIN_EN(true);
u32RegVal &= ~CMP_CCR1_SAMPLE_EN_MASK;
u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK;
u32RegVal &= ~CMP_CCR1_FILT_PER_MASK;
u32RegVal |= CMP_CCR1_FILT_CNT(0x01)|
CMP_CCR1_FILT_PER(u8FilterPrd);
}
break;
case CMP_MODE_WINDOW_FILTER:
{
u32RegVal |= CMP_CCR1_WIN_EN(true);
u32RegVal &= ~CMP_CCR1_SAMPLE_EN_MASK;
u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK;
u32RegVal &= ~CMP_CCR1_FILT_PER_MASK;
u32RegVal |= CMP_CCR1_FILT_CNT(eFilterCnt)|
CMP_CCR1_FILT_PER(u8FilterPrd);
}
break;
#ifdef CMP_SUPPORT_CHANNELSCAN_MODE_FEATURE
case CMP_MODE_CHANNEL_SCAN:
{
pCmp->CSCR0 |= CMP_CSCR0_CS_EN(true) ;
}
break;
#endif
default:
break;
}
pCmp->CCR1 = u32RegVal;
}
/**
* @brief set CPM output invert
*
* @param pCmp the CMP instance to use
* @param eType CPM output invert type
*/
LOCAL_INLINE void CMP_HWA_SetCmpOutInvert(CMP_Type *const pCmp, CMP_InvertType eType)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_INV_MASK)) | CMP_CCR1_CMPOUT_INV(eType));
}
/**
* @brief set CPM output filter/unfilter selection
*
* @param pCmp the CMP instance to use
* @param eType CPM output filter/unfilter type
*/
LOCAL_INLINE void CMP_HWA_SetCmpOutSel(CMP_Type *const pCmp, CMP_OutSelectType eType)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_SEL_MASK)) | CMP_CCR1_CMPOUT_SEL(eType));
}
/**
* @brief set comparator output pin enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetEnCmpOutPack(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_PEN_MASK)) | CMP_CCR1_CMPOUT_PEN(bEnable));
}
/**
* @brief set CMPOUT_WIN level, when window is closed
*
* @param pCmp the CMP instance to use
* @param eType CMPOUT_WIN level type
*/
LOCAL_INLINE void CMP_HWA_SetCmpOutWinLevel(CMP_Type *const pCmp, CMP_OutWinLevelType eType)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_WIN_OWEN_MASK)) | CMP_CCR1_CMPOUT_WIN_OWEN(eType));
}
/**
* @brief set CMPOUT_WIN level in user-define mode, when window is closed
*
* @param pCmp the CMP instance to use
* @param eType user-define CMPOUT_WIN level type
*/
LOCAL_INLINE void CMP_HWA_SetCmpOutWin(CMP_Type *const pCmp, CMP_OutWinLevel_UserDefType eType)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_WIN_OW_MASK)) | CMP_CCR1_CMPOUT_WIN_OW(eType));
}
/**
* @brief set invert the WINDOW/SAMPLE signal enable or not
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetEnWinSampleInvert(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_WIN_INV_MASK)) | CMP_CCR1_WIN_INV(bEnable));
}
/**
* @brief WINDOW signal can or not be closed by CMPO event when window mode
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetEnEventCloseWin(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_WIN_CLS_MASK)) | CMP_CCR1_WIN_CLS(bEnable));
}
/**
* @brief set which CMPO event causes window close
*
* @param pCmp the CMP instance to use
* @param eType CMPO event type
*/
LOCAL_INLINE void CMP_HWA_SetEventCloseWin(CMP_Type *const pCmp, CMP_EventType eType)
{
uint32_t u32RegVal = pCmp->CCR1;
pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_EVT_SEL_MASK)) | CMP_CCR1_EVT_SEL(eType));
}
/**
* @brief set CCR1 register
*
* @param pCmp the CMP instance to use
* @param u32RegVal Register value to set
*/
LOCAL_INLINE void CMP_HWA_SetCCR1(CMP_Type *const pCmp, uint32_t u32RegVal)
{
pCmp->CCR1 = u32RegVal;
}
/**
* @brief set CMP power mode select
*
* @param pCmp the CMP instance to use
* @param eMod CMP power mode
*/
LOCAL_INLINE void CMP_HWA_SetSpeedMode(CMP_Type *const pCmp, CMP_SpeedModeSelType eMode)
{
uint32_t u32RegVal = pCmp->CCR2;
pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_HPMD_MASK)) | CMP_CCR2_HPMD(eMode));
}
/**
* @brief set Comparator hard block hysteresis control
*
* @param pCmp the CMP instance to use
* @param eType CMP hysteresis control type
*/
LOCAL_INLINE void CMP_HWA_SetHystCtrl(CMP_Type *const pCmp, CMP_HystCtrlType eType)
{
uint32_t u32RegVal = pCmp->CCR2;
pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_HYSTCTR_MASK)) | CMP_CCR2_HYSTCTR(eType));
}
/**
* @brief set which input is selected for the positive mux
*
* @param pCmp the CMP instance to use
* @param eType CMP positive mux type
*/
LOCAL_INLINE void CMP_HWA_SetPSelMux(CMP_Type *const pCmp, CMP_MuxSelType eType)
{
uint32_t u32RegVal = pCmp->CCR2;
pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_PSEL_MASK)) | CMP_CCR2_PSEL(eType));
}
/**
* @brief set which input is selected for the negative mux
*
* @param pCmp the CMP instance to use
* @param eType CMP negative mux type
*/
LOCAL_INLINE void CMP_HWA_SetNSelMux(CMP_Type *const pCmp, CMP_MuxSelType eType)
{
uint32_t u32RegVal = pCmp->CCR2;
pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_MSEL_MASK)) | CMP_CCR2_MSEL(eType));
}
/**
* @brief set the input to the positive port of the comparator
*
* @param pCmp the CMP instance to use
* @param eType CMP positive input source type(analog mux,dac)
*/
LOCAL_INLINE void CMP_HWA_SetINPSel(CMP_Type *const pCmp, CMP_INSrcSelType eType)
{
uint32_t u32RegVal = pCmp->CCR2;
pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_INPSEL_MASK)) | CMP_CCR2_INPSEL(eType));
}
/**
* @brief set the input to the negative port of the comparator
*
* @param pCmp the CMP instance to use
* @param eType CMP negative input source type(analog mux,dac)
*/
LOCAL_INLINE void CMP_HWA_SetINNSel(CMP_Type *const pCmp, CMP_INSrcSelType eType)
{
uint32_t u32RegVal = pCmp->CCR2;
pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_INMSEL_MASK)) | CMP_CCR2_INMSEL(eType));
}
/**
* @brief set CCR2 register
*
* @param pCmp the CMP instance to use
* @param u32RegVal Register value to set
*/
LOCAL_INLINE void CMP_HWA_SetCCR2(CMP_Type *const pCmp, uint32_t u32RegVal)
{
pCmp->CCR2 = u32RegVal;
}
/**
* @brief set CMP DAC enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetEnDac(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->DCR;
pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_DAC_EN_MASK)) | CMP_DCR_DAC_EN(bEnable));
}
/**
* @brief set CMP Dac output
*
* @param pCmp the CMP instance to use
* @param u8Data the Dac data
* @note output = (VinRef / 256) * (u8Data + 1)
*/
LOCAL_INLINE void CMP_HWA_SetDacData(CMP_Type *const pCmp, uint8_t u8Data)
{
uint32_t u32RegVal = pCmp->DCR;
pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_DAC_DATA_MASK)) | CMP_DCR_DAC_DATA(u8Data));
}
/**
* @brief set DCR register
*
* @param pCmp the CMP instance to use
* @param u32RegVal Register value to set
*/
LOCAL_INLINE void CMP_HWA_SetDCR(CMP_Type *const pCmp, uint32_t u32RegVal)
{
pCmp->DCR = u32RegVal;
}
/**
* @brief set comparator rising interrupt enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetIntEn_Rising(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->IER;
pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CFR_IE_MASK)) | CMP_IER_CFR_IE(bEnable));
}
/**
* @brief get comparator rising interrupt enable status
*
* @param pCmp the CMP instance to use
* @return comparator rising interrupt status
*/
LOCAL_INLINE bool CMP_HWA_GetIntEn_Rising(CMP_Type *const pCmp)
{
bool RetStatus = false;
uint32_t u32RegVal = pCmp->IER;
RetStatus = (bool)((((u32RegVal & CMP_IER_CFR_IE_MASK) >> CMP_IER_CFR_IE_SHIFT) != 0U) ? true : false);
return RetStatus;
}
/**
* @brief set comparator falling interrupt enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetIntEn_Falling(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->IER;
pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CFF_IE_MASK)) | CMP_IER_CFF_IE(bEnable));
}
/**
* @brief get comparator falling interrupt enable status
*
* @param pCmp the CMP instance to use
* @return comparator falling interrupt status
*/
LOCAL_INLINE bool CMP_HWA_GetIntEn_Falling(CMP_Type *const pCmp)
{
bool bRetStatus = false;
uint32_t u32RegVal = pCmp->IER;
bRetStatus = (bool)((((u32RegVal & CMP_IER_CFF_IE_MASK) >> CMP_IER_CFF_IE_SHIFT) != 0U) ? true : false);
return bRetStatus;
}
/**
* @brief set IER register
*
* @param pCmp the CMP instance to use
* @param u32RegVal Register value to set
*/
LOCAL_INLINE void CMP_HWA_SetIER(CMP_Type *const pCmp, uint32_t u32RegVal)
{
pCmp->IER = u32RegVal;
}
/**
* @brief get CMP output rising edge status
*
* @param pCmp the CMP instance to use
* @return CMP rising edge status
*/
LOCAL_INLINE bool CMP_HWA_GetIntFlag_Rising(CMP_Type *const pCmp)
{
bool bRetStatus = false;
uint32_t u32RegVal = pCmp->CSR;
bRetStatus = (bool)((((u32RegVal & CMP_CSR_CFR_MASK) >> CMP_CSR_CFR_SHIFT) != 0U) ? true : false);
return bRetStatus;
}
/**
* @brief get CMP output falling edge status
*
* @param pCmp the CMP instance to use
* @return CMP falling edge status
*/
LOCAL_INLINE bool CMP_HWA_GetIntFlag_Falling(CMP_Type *const pCmp)
{
bool bRetStatus = false;
uint32_t u32RegVal = pCmp->CSR;
bRetStatus = (bool)((((u32RegVal & CMP_CSR_CFF_MASK) >> CMP_CSR_CFF_SHIFT) != 0U) ? true : false);
return bRetStatus;
}
/**
* @brief clear rising interrupt flag
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_ClearIntFlag_Rising(CMP_Type *const pCmp)
{
pCmp->CSR = CMP_CSR_CFR(true);
}
/**
* @brief clear falling interrupt flag
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_ClearIntFlag_Falling(CMP_Type *const pCmp)
{
pCmp->CSR = CMP_CSR_CFF(true);
}
/**
* @brief get CMP filtered output
*
* @param pCmp the CMP instance to use
* @return CMP filtered output
*/
LOCAL_INLINE uint32_t CMP_HWA_GetCmpOut(CMP_Type *const pCmp)
{
uint32_t u32RegVal = pCmp->CSR;
u32RegVal = (u32RegVal & CMP_CSR_CMPOUT_FILTER_MASK) >> CMP_CSR_CMPOUT_FILTER_SHIFT;
return u32RegVal;
}
/**
* @brief set CSR register
*
* @param pCmp the CMP instance to use
* @param u32RegVal Register value to set
*/
LOCAL_INLINE void CMP_HWA_SetCSR(CMP_Type *const pCmp, uint32_t u32RegVal)
{
pCmp->CSR = u32RegVal;
}
#ifdef CMP_SUPPORT_CHANNELSCAN_MODE_FEATURE
/**
* @brief set comparator channel scan interrupt enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetIntEn_ChannelScan(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->IER;
pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CSF_IE_MASK)) | CMP_IER_CSF_IE(bEnable));
}
/**
* @brief get comparator channel scan interrupt enable status
*
* @param pCmp the CMP instance to use
* @return comparator channel scan interrupt status
*/
LOCAL_INLINE bool CMP_HWA_GetIntEn_ChannelScan(CMP_Type *const pCmp)
{
bool bRetStatus = false;
uint32_t u32RegVal = pCmp->IER;
bRetStatus = (bool)((((u32RegVal & CMP_IER_CSF_IE_MASK) >> CMP_IER_CSF_IE_SHIFT) != 0U) ? true : false);
return bRetStatus;
}
/**
* @brief clear channel scan interrupt flag
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_ClearIntFlag_ChannelScan(CMP_Type *const pCmp)
{
pCmp->CSR = CMP_CSR_CSF(true);
}
/**
* @brief set CMP and DAC initialization delay modulus
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_SetCSInitModulus(CMP_Type *const pCmp, uint8_t u8Modulus)
{
uint32_t u32RegVal = pCmp->CSCR0;
pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_INITMOD_MASK)) | CMP_CSCR0_CS_INITMOD(u8Modulus));
}
/**
* @brief set number of clock cycles for sampling
*
* @param pCmp the CMP instance to use
* @param u8Nsam the sampling clocks value
*/
LOCAL_INLINE void CMP_HWA_SetCSNSAM(CMP_Type *const pCmp, uint8_t u8Nsam)
{
uint32_t u32RegVal = pCmp->CSCR0;
pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_NSAM_MASK)) | CMP_CSCR0_CS_NSAM(u8Nsam));
}
/**
* @brief set CMP channel scan enable
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetCSEn(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CSCR0;
pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_EN_MASK)) | CMP_CSCR0_CS_EN(bEnable));
}
/**
* @brief set CSCR0 register
*
* @param pCmp the CMP instance to use
* @param u32RegVal Register value to set
*/
LOCAL_INLINE void CMP_HWA_SetCSCR0(CMP_Type *const pCmp, uint32_t u32RegVal)
{
pCmp->CSCR0 = u32RegVal;
}
/**
* @brief set channel scan fixed channel
*
* @param pCmp the CMP instance to use
* @param eChannel the fixed channel
*/
LOCAL_INLINE void CMP_HWA_SetCSFixedChannel(CMP_Type *const pCmp, CMP_MuxSelType eChannel)
{
uint32_t u32RegVal = pCmp->CSCR1;
pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)CMP_CSCR1_FIXCH_MASK)) | CMP_CSCR1_FIXCH(eChannel));
}
/**
* @brief set channel scan fixed port
*
* @param pCmp the CMP instance to use
* @param ePort the fixed port
*/
LOCAL_INLINE void CMP_HWA_SetCSFixedPort(CMP_Type *const pCmp, CMP_PortSelType ePort)
{
uint32_t u32RegVal = pCmp->CSCR1;
pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)CMP_CSCR1_FIXP_MASK)) | CMP_CSCR1_FIXP(ePort));
}
/**
* @brief set channel scan channel enabled
*
* @param pCmp the CMP instance to use
* @param eChannel the enabled channel
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetCSChannelEn(CMP_Type *const pCmp, CMP_MuxSelType eChannel, bool bEnable)
{
uint32_t u32RegVal = pCmp->CSCR1;
pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)(1 << eChannel))) | (((uint32_t)bEnable) << eChannel));
}
/**
* @brief set CSCR1 register
*
* @param pCmp the CMP instance to use
* @param u32RegVal Register value to set
*/
LOCAL_INLINE void CMP_HWA_SetCSCR1(CMP_Type *const pCmp, uint32_t u32RegVal)
{
pCmp->CSCR1 = u32RegVal;
}
/**
* @brief get CMP output channel scan status
*
* @param pCmp the CMP instance to use
* @return CMP channel scan status
*/
LOCAL_INLINE bool CMP_HWA_GetIntFlag_ChannelScan(CMP_Type *const pCmp)
{
bool bRetStatus = false;
uint32_t u32RegVal = pCmp->CSR;
bRetStatus = (bool)((((u32RegVal & CMP_CSR_CSF_MASK) >> CMP_CSR_CSF_SHIFT) != 0U) ? true : false);
return bRetStatus;
}
/**
* @brief set channel scan channel enabled
*
* @param pCmp the CMP instance to use
* @param eChannel the enabled channel
* @param bPresetstate preset state for channel
*/
LOCAL_INLINE void CMP_HWA_SetCSChannelPresetstate(CMP_Type *const pCmp, CMP_MuxSelType eChannel, bool bPresetstate)
{
uint32_t u32RegVal = pCmp->CSCSR;
pCmp->CSCSR = ((u32RegVal & (~(uint32_t)(1 << eChannel))) | (((uint32_t)bPresetstate) << eChannel));
}
/**
* @brief get channel scan channel current state
*
* @param pCmp the CMP instance to use
* @param eChannel the channel that want to get state
*/
LOCAL_INLINE bool CMP_HWA_GetCSChannelOut(CMP_Type *const pCmp, CMP_MuxSelType eChannel)
{
bool OutFlag;
uint32_t u32RegVal = pCmp->CSCSR;
OutFlag = (bool)((u32RegVal & ((uint32_t)(1 << eChannel))) >> eChannel);
return OutFlag;
}
/**
* @brief software clear channel scan comparison results
*
* @param pCmp the CMP instance to use
*/
LOCAL_INLINE void CMP_HWA_ClearCSCompRes(CMP_Type *const pCmp)
{
uint32_t u32RegVal = pCmp->CSCSR;
pCmp->CSCSR = ((u32RegVal & (~(uint32_t)CMP_CSCSR_CS_SWCLR_MASK)) | CMP_CSCSR_CS_SWCLR(true));
}
/**
* @brief software clear channel scan comparison results
*
* @param pCmp the CMP instance to use
* @param bEnable enable/disable flag
*/
LOCAL_INLINE void CMP_HWA_SetCSCompareResultACEn(CMP_Type *const pCmp, bool bEnable)
{
uint32_t u32RegVal = pCmp->CSCSR;
pCmp->CSCSR = ((u32RegVal & (~(uint32_t)CMP_CSCSR_CS_ACLR_MASK)) | CMP_CSCSR_CS_ACLR(bEnable));
}
/**
* @brief set CSCSR register
*
* @param pCmp the CMP instance to use
* @param u32RegVal Register value to set
*/
LOCAL_INLINE void CMP_HWA_SetCSCSR(CMP_Type *const pCmp, uint32_t u32RegVal)
{
pCmp->CSCSR = u32RegVal;
}
/**
* @brief get channel scan active status
*
* @param pCmp the CMP instance to use
* @return status cmp channel whether is active
*/
LOCAL_INLINE bool CMP_HWA_GetCSActive(CMP_Type *const pCmp)
{
bool status;
uint32_t u32RegVal = pCmp->CSSR;
status = ((u32RegVal & ((uint32_t)CMP_CSSR_CS_ACTIVE_MASK)) >> CMP_CSSR_CS_ACTIVE_SHIFT) ? true : false;
return status;
}
/**
* @brief get channel scan comparison result changed flag
*
* @param pCmp the CMP instance to use
* @param eChannel the channel to get comparison result changed flag
* @return the comparison result changed flag for a given channel
*/
LOCAL_INLINE bool CMP_HWA_GetCSComparisonResultFlag(CMP_Type *const pCmp, CMP_MuxSelType eChannel)
{
uint32_t u32RegVal = pCmp->CSSR;
return ((u32RegVal & (1U << eChannel)) >> eChannel) ? true : false;
}
/**
* @brief set CSSR register
*
* @param pCmp the CMP instance to use
* @param u32RegVal Register value to set
*/
LOCAL_INLINE void CMP_HWA_SetCSSR(CMP_Type *const pCmp, uint32_t u32RegVal)
{
pCmp->CSSR = u32RegVal;
}
#endif
/** @}*/
#endif /* #if CMP_INSTANCE_COUNT > 0U */
#endif /* #ifndef _HWA_CMP_H_ */

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/**
* @file HwA_cmu.h
* @author Flagchip0100
* @brief CMU Module Register API
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright 2020-2024 Flagchip Semiconductors Co., Ltd.
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip100 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip100 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_CMU_H_
#define _HWA_CMU_H_
#include "device_header.h"
#if (CMU_INSTANCE_COUNT > 0U)
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @defgroup HwA_cmu HwA_cmu
* @ingroup module_driver_cmu
* @{
*/
/*******************************************************************************
* Local inline function
******************************************************************************/
/**
* @brief Set Reference Window value.
*
* @param pCmu CMU Instance.
* @param u32Temp Ref Window value.
*/
LOCAL_INLINE void CMU_HWA_SetRefWindow(CMU_Type *const pCmu, uint32_t u32Temp)
{
pCmu->REF_WINDOW = u32Temp;
}
/**
* @brief Set Minimun Counter value.
*
* @param pCmu CMU Instance.
* @param u32Temp Min Count value.
*/
LOCAL_INLINE void CMU_HWA_SetMinCnts(CMU_Type *const pCmu, uint32_t u32Temp)
{
pCmu->MIN = u32Temp;
}
/**
* @brief Get Minimun Counter value.
*
* @param pCmu CMU Instance.
* @return Min count value.
*/
LOCAL_INLINE uint32_t CMU_HWA_GetMinCnts(const CMU_Type *const pCmu)
{
return (pCmu->MIN & CMU_MIN_MIN_MASK) >> CMU_MIN_MIN_SHIFT;
}
/**
* @brief Set Maximun Counter value.
*
* @param pCmu CMU Instance.
* @param u32Temp Max count value.
*/
LOCAL_INLINE void CMU_HWA_SetMaxCnts(CMU_Type *const pCmu, uint32_t u32Temp)
{
pCmu->MAX = u32Temp;
}
/**
* @brief Get Maximun Counter value.
*
* @param pCmu CMU Instance.
* @return Max count value.
*/
LOCAL_INLINE uint32_t CMU_HWA_GetMaxCnts(const CMU_Type *const pCmu)
{
return (pCmu->MAX & CMU_MAX_MAX_MASK) >> CMU_MAX_MAX_SHIFT;
}
/**
* @brief Get Counter value.
*
* @param pCmu CMU Instance.
* @return Counter value.
*/
LOCAL_INLINE uint32_t CMU_HWA_GetCount(const CMU_Type *const pCmu)
{
return (pCmu->MON_CNT & CMU_MON_CNT_MON_CNT_MASK) >> CMU_MON_CNT_MON_CNT_SHIFT;
}
/**
* @brief Set period window Counter.
*
* @param pCmu CMU Instance.
* @param u32Temp Period value.
*/
LOCAL_INLINE void CMU_HWA_SetPeriodWindow(CMU_Type *const pCmu, uint32_t u32Temp)
{
pCmu->PERIOD = (pCmu->PERIOD & ~((uint32_t)CMU_PERIOD_WINDOW_MASK)) | CMU_PERIOD_WINDOW(u32Temp);
}
/**
* @brief Set period enble bit.
*
* @param pCmu CMU Instance.
* @param bEnable Set enable bit.
*/
LOCAL_INLINE void CMU_HWA_SetPeriodEnable(CMU_Type *const pCmu, bool bEnable)
{
pCmu->PERIOD = (pCmu->PERIOD & ~((uint32_t)CMU_PERIOD_EN_MASK)) | CMU_PERIOD_EN(bEnable);
}
/**
* @brief Get period enble bit.
*
* @param pCmu CMU Instance.
* @return Period mode enable bit.
*/
LOCAL_INLINE bool CMU_HWA_GetPeriodEnable(const CMU_Type *const pCmu)
{
return ((pCmu->PERIOD & CMU_PERIOD_EN_MASK) == CMU_PERIOD_EN_MASK) ? true : false;
}
/**
* @brief Set control register value.
*
* @param pCmu CMU Instance.
* @param u32Temp Control value.
*/
LOCAL_INLINE void CMU_HWA_SetCtrl(CMU_Type *const pCmu, uint32_t u32Temp)
{
pCmu->CTRL = u32Temp;
}
/**
* @brief Get control register value.
*
* @param pCmu CMU Instance.
* @return Control register value.
*/
LOCAL_INLINE uint32_t CMU_HWA_GetCtrl(const CMU_Type *const pCmu)
{
return pCmu->CTRL;
}
/**
* @brief Get status register value.
*
* @param pCmu CMU Instance.
* @return Status register value.
*/
LOCAL_INLINE uint32_t CMU_HWA_GetST(const CMU_Type *const pCmu)
{
return pCmu->ST;
}
/**
* @brief Clear clock monitor status.
*
* @param pCmu CMU Instance.
*/
LOCAL_INLINE void CMU_HWA_ClsST(CMU_Type *const pCmu)
{
pCmu->ST = CMU_ST_MIS_MASK | CMU_ST_LOC_MASK;
}
#ifdef CMU_CTRL_LP_SUPPORT
/**
* @brief Enable Standby mode.
*
* @param pCmu CMU Instance.
* @param bEnable Enable mode.
*/
LOCAL_INLINE void CMU_HWA_StanbyModeEnable(CMU_Type *const pCmu, bool bEnable)
{
pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_LP_EN_MASK)) | CMU_CTRL_LP_EN(bEnable);
}
#endif
/**
* @brief Enable Stop mode.
*
* @param pCmu CMU Instance.
* @param bEnable Enable mode.
*/
LOCAL_INLINE void CMU_HWA_StopModeEnable(CMU_Type *const pCmu, bool bEnable)
{
pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_STOP_EN_MASK)) | CMU_CTRL_STOP_EN(bEnable);
}
/**
* @brief Enable Softeare Reset.
*
* @param pCmu CMU Instance.
*/
LOCAL_INLINE void CMU_HWA_SoftwareRST(CMU_Type *const pCmu)
{
pCmu->CTRL |= CMU_CTRL_SW_RST_MASK;
}
/**
* @brief Enable Software Reset.
*
* @param pCmu CMU Instance.
* @return Software reset is done.
*/
LOCAL_INLINE bool CMU_HWA_GetSoftwareRST(const CMU_Type *const pCmu)
{
return ((pCmu->CTRL & CMU_CTRL_SW_RST_MASK) == CMU_CTRL_SW_RST_MASK) ? true : false;
}
/**
* @brief Enable low power restart mode.
*
* @param pCmu CMU Instance.
* @param bEnable Enable mode.
*/
LOCAL_INLINE void CMU_HWA_LPRestartEnable(CMU_Type *const pCmu, bool bEnable)
{
pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_RESTART_EN_MASK)) | CMU_CTRL_RESTART_EN(bEnable);
}
/** @}*/ /* HwA_cmu */
#if defined(__cplusplus)
}
#endif
#endif /* (CMU_INSTANCE_COUNT > 0U) */
#endif /* _HWA_CMU_H_ */

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/**
* @file HwA_cordic.h
* @author Flagchip
* @brief CORDIC hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip054 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip054 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_CORDIC_H_
#define _HWA_CORDIC_H_
#include "device_header.h"
#if CORDIC_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_cordic HwA_cordic
* @ingroup module_driver_cordic
* @{
*/
/**
* \brief CORDIC Iteration Type
*
* Defines the number of iterations for the CORDIC algorithm.
*/
typedef enum
{
CORDIC_Iteration_8 = 0,
CORDIC_Iteration_16,
CORDIC_Iteration_24
} CORDIC_IterationType;
/**
* \brief CORDIC System Type
*
* Specifies the system type for the CORDIC algorithm.
*/
typedef enum
{
CORDIC_Trigonometric = 0,
CORDIC_Hyperbolic,
CORDIC_Linear
} CORDIC_SystemType;
/**
* \brief CORDIC Mode Type
*
* Specifies the operation mode for the CORDIC algorithm.
*/
typedef enum
{
CORDIC_Rotate = 0,
CORDIC_Vector
} CORDIC_ModeType;
#if (DEVICE_NAME>FC7300FxMDxxxxxT1B_DEVICE_START) && (DEVICE_NAME<FC7300F8MDQ1A320T1B)
#define CORDIC_CTR_VAL(s,a,b,c,d) (CORDIC_CTRL_IE(a) | CORDIC_CTRL_ITER(b) | CORDIC_CTRL_OS(c) | CORDIC_CTRL_MODE(d))
#else
#define CORDIC_CTR_VAL(s,a,b,c,d) (CORDIC_CTRL_SCALE(s) | CORDIC_CTRL_IE(a) | CORDIC_CTRL_ITER(b) | CORDIC_CTRL_OS(c) | CORDIC_CTRL_MODE(d))
#endif
/**
* \brief Set CORDIC module Control register
*
* Sets the control register value of the CORDIC module.
*
* \param pCordic Pointer to the CORDIC module.
* \param u32Value Control register value to set.
*/
LOCAL_INLINE void Cordic_HWA_SetCtrl(CORDIC_Type* const pCordic, uint32_t u32Value)
{
pCordic->CTRL = u32Value;
}
/**
* \brief Read CORDIC module Control register
*
* Reads the control register value of the CORDIC module.
*
* \param pCordic Pointer to the CORDIC module.
* \return Control register value.
*/
LOCAL_INLINE uint32_t Cordic_HWA_GetCtrl(CORDIC_Type* const pCordic)
{
return (uint32_t)(pCordic->CTRL);
}
/**
* \brief Set CORDIC module X Input register
*
* Sets the X input register value of the CORDIC module.
*
* \param pCordic Pointer to the CORDIC module.
* \param u32Value X input register value to set.
*/
LOCAL_INLINE void Cordic_HWA_Set_XInput(CORDIC_Type* const pCordic, int32_t u32Value)
{
pCordic->X_INPUT = *((uint32_t *)&u32Value);
}
/**
* \brief Set CORDIC module Y Input register
*
* Sets the Y input register value of the CORDIC module.
*
* \param pCordic Pointer to the CORDIC module.
* \param u32Value Y input register value to set.
*/
LOCAL_INLINE void Cordic_HWA_Set_YInput(CORDIC_Type* const pCordic, int32_t u32Value)
{
pCordic->Y_INPUT = *((uint32_t *)&u32Value);
}
/**
* \brief Set CORDIC module Z Input register
*
* Sets the Z input register value of the CORDIC module.
*
* \param pCordic Pointer to the CORDIC module.
* \param u32Value Z input register value to set.
*/
LOCAL_INLINE void Cordic_HWA_Set_ZInput(CORDIC_Type* const pCordic, int32_t u32Value)
{
pCordic->Z_INPUT = *((uint32_t *)&u32Value);
}
/**
* \brief Read CORDIC module X Output register
*
* Reads the X output register value of the CORDIC module.
*
* \param pCordic Pointer to the CORDIC module.
* \return X output register value.
*/
LOCAL_INLINE int32_t Cordic_HWA_Get_XOutput(CORDIC_Type* const pCordic)
{
return (int32_t)(pCordic->X_OUTPUT);
}
/**
* \brief Read CORDIC module Y Output register
*
* Reads the Y output register value of the CORDIC module.
*
* \param pCordic Pointer to the CORDIC module.
* \return Y output register value.
*/
LOCAL_INLINE int32_t Cordic_HWA_Get_YOutput(CORDIC_Type* const pCordic)
{
return (int32_t)(pCordic->Y_OUTPUT);
}
/**
* \brief Read CORDIC module Z Output register
*
* Reads the Z output register value of the CORDIC module.
*
* \param pCordic Pointer to the CORDIC module.
* \return Z output register value.
*/
LOCAL_INLINE int32_t Cordic_HWA_Get_ZOutput(CORDIC_Type* const pCordic)
{
return (int32_t)(pCordic->Z_OUTPUT);
}
/**
* \brief Read CORDIC module State
*
* Reads the current state of the CORDIC module.
*
* \param pCordic Pointer to the CORDIC module.
* \return Current state of the CORDIC module.
*/
LOCAL_INLINE bool Cordic_HWA_Get_Stat(CORDIC_Type* const pCordic)
{
return (bool)(pCordic->STAT & CORDIC_STAT_DONE_MASK);
}
/**
* \brief Clear CORDIC module done Flag
*
* Reads the current state of the CORDIC module.
*
* \param pCordic Pointer to the CORDIC module.
*/
LOCAL_INLINE void Cordic_HWA_Clear_Stat(CORDIC_Type* const pCordic)
{
pCordic->STAT |= CORDIC_STAT_DONE_MASK;
}
/**
* @}
*/
#endif
#endif

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/**
* @file HwA_cpm.h
* @author Flagchip
* @brief CPM register API
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip120 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip120 N/A Change version and release
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_CPM_H_
#define HWA_INCLUDE_HWA_CPM_H_
#include "device_header.h"
#if CPM_INSTANCE_COUNT > 0U
/* ################################################################################## */
/* ####################################### Macro #################################### */
/** FPSCR Bit Fields */
#define FPSCR_IOC_MASK 0x00000001U
#define FPSCR_DZC_MASK 0x00000002U
#define FPSCR_OFC_MASK 0x00000004U
#define FPSCR_UFC_MASK 0x00000008U
#define FPSCR_IXC_MASK 0x00000010U
#define FPSCR_IDC_MASK 0x00000080U
#define CPM_FPU_INTFLAGMASK 0x0000003FU
/**
* @defgroup HwA_cpm HwA_cpm
* @ingroup module_driver_cpm
* @{
*/
/**
* @brief Get the value of CPM FISCR.
*
* This function returns FISCR value.
*
* @param pCpm the base address of the CPM instance.
* @return uint32_t the value of the FISCR register.
*/
LOCAL_INLINE uint32_t CPM_HWA_GetFiscr(CPM_Type *const pCpm)
{
uint32_t u32TmpVal = pCpm->FISCR;
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
return u32TmpVal;
}
/**
* @brief Return CPM_FISCR FIOC value
*
* @param pCpm the base address of the CPM instance.
* @return 0: No interrupt; 1: Interrupt occurred
*/
LOCAL_INLINE bool CPM_HWA_GetFpuFiocFlag(CPM_Type *const pCpm)
{
uint32_t u32TmpVal = pCpm->FISCR;
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
u32TmpVal = (u32TmpVal & CPM_FISCR_FIOC_MASK) >> CPM_FISCR_FIOC_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Return CPM_FISCR FDZC value
*
* @param pCpm the base address of the CPM instance.
* @return 0: No interrupt; 1: Interrupt occurred
*/
LOCAL_INLINE bool CPM_HWA_GetFpuFdzcFlag(CPM_Type *const pCpm)
{
uint32_t u32TmpVal = pCpm->FISCR;
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
u32TmpVal = (u32TmpVal & CPM_FISCR_FDZC_MASK) >> CPM_FISCR_FDZC_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Return CPM_FISCR FOFC value
*
* @param pCpm the base address of the CPM instance.
* @return 0: No interrupt; 1: Interrupt occurred
*/
LOCAL_INLINE bool CPM_HWA_GetFpuFofcFlag(CPM_Type *const pCpm)
{
uint32_t u32TmpVal = pCpm->FISCR;
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
u32TmpVal = (u32TmpVal & CPM_FISCR_FOFC_MASK) >> CPM_FISCR_FOFC_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Return CPM_FISCR FUFC value
*
* @param pCpm the base address of the CPM instance.
* @return 0: No interrupt; 1: Interrupt occurred
*/
LOCAL_INLINE bool CPM_HWA_GetFpuFufcFlag(CPM_Type *const pCpm)
{
uint32_t u32TmpVal = pCpm->FISCR;
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
u32TmpVal = (u32TmpVal & CPM_FISCR_FUFC_MASK) >> CPM_FISCR_FUFC_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Return CPM_FISCR FIXC value
*
* @param pCpm the base address of the CPM instance.
* @return 0: No interrupt; 1: Interrupt occurred
*/
LOCAL_INLINE bool CPM_HWA_GetFpuFixcFlag(CPM_Type *const pCpm)
{
uint32_t u32TmpVal = pCpm->FISCR;
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
u32TmpVal = (u32TmpVal & CPM_FISCR_FIXC_MASK) >> CPM_FISCR_FIXC_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Return CPM_FISCR FIDC value
*
* @param pCpm the base address of the CPM instance.
* @return 0: No interrupt; 1: Interrupt occurred
*/
LOCAL_INLINE bool CPM_HWA_GetFpuFidcFlag(CPM_Type *const pCpm)
{
uint32_t u32TmpVal = pCpm->FISCR;
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
u32TmpVal = (u32TmpVal & CPM_FISCR_FIDC_MASK) >> CPM_FISCR_FIDC_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set FIOCE interrupt
*
* @param pCpm the base address of the CPM instance.
* @param bEnable 1: enable interrupt 0: disable interrupt
*/
LOCAL_INLINE void CPM_HWA_SetFioceInt(CPM_Type *const pCpm, bool bEnable)
{
pCpm->FISCR = ((pCpm->FISCR & (~CPM_FISCR_FIOCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIOCE_SHIFT));
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
}
/**
* @brief Set FDZCE interrupt
*
* @param pCpm the base address of the CPM instance.
* @param bEnable 1: enable interrupt 0: disable interrupt
*/
LOCAL_INLINE void CPM_HWA_SetFdzceInt(CPM_Type *const pCpm, bool bEnable)
{
pCpm->FISCR = ((pCpm->FISCR & (~CPM_FISCR_FDZCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FDZCE_SHIFT));
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
}
/**
* @brief Set FOFCE interrupt
*
* @param pCpm the base address of the CPM instance.
* @param bEnable 1: enable interrupt 0: disable interrupt
*/
LOCAL_INLINE void CPM_HWA_SetFofceInt(CPM_Type *const pCpm, bool bEnable)
{
pCpm->FISCR = ((pCpm->FISCR & (~CPM_FISCR_FOFCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FOFCE_SHIFT));
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
}
/**
* @brief Set FUFCE interrupt
*
* @param pCpm the base address of the CPM instance.
* @param bEnable 1: enable interrupt 0: disable interrupt
*/
LOCAL_INLINE void CPM_HWA_SetFufceInt(CPM_Type *const pCpm, bool bEnable)
{
pCpm->FISCR = ((pCpm->FISCR & (~CPM_FISCR_FUFCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FUFCE_SHIFT));
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
}
/**
* @brief Set FIXCE interrupt
*
* @param pCpm the base address of the CPM instance.
* @param bEnable 1: enable interrupt 0: disable interrupt
*/
LOCAL_INLINE void CPM_HWA_SetFixceInt(CPM_Type *const pCpm, bool bEnable)
{
pCpm->FISCR = ((pCpm->FISCR & (~CPM_FISCR_FIXCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIXCE_SHIFT));
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
}
/**
* @brief Set FIDCE interrupt
*
* @param pCpm the base address of the CPM instance.
* @param bEnable 1: enable interrupt 0: disable interrupt
*/
LOCAL_INLINE void CPM_HWA_SetFidceInt(CPM_Type *const pCpm, bool bEnable)
{
pCpm->FISCR = ((pCpm->FISCR & (~CPM_FISCR_FIDCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIDCE_SHIFT));
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
}
/**
* @brief Set FISCR value
*
* @param pCpm the base address of the CPM instance.
* @param u32Val the value want to set the register
*/
LOCAL_INLINE void CPM_HWA_SetFiscr(CPM_Type *const pCpm, uint32_t u32Val)
{
pCpm->FISCR = u32Val;
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
}
#if (CPM_CONTAIN_CPUID == STD_ON)
/**
* @brief Return CPM_CoreID value
*
* @param pCpm the base address of the CPM instance.
* @return uint32_t the core ID value
*/
LOCAL_INLINE uint32_t CPM_HWA_GetCoreIDValve(CPM_Type *const pCpm)
{
uint32_t u32TmpVal = pCpm->MISCR;
#if (CPM_ERRATA == STD_ON)
__asm volatile(
"dmb \n"
"ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */
: : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory"
);
#endif
u32TmpVal = (u32TmpVal & CPM_MISCR_CPU_ID_MASK) >> CPM_MISCR_CPU_ID_SHIFT;
return (uint32_t)u32TmpVal;
}
#endif
/** @}*/
#endif
#endif /* HWA_INCLUDE_HWA_CPM_H_ */

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/**
* @file HwA_crc.h
* @author Flagchip
* @brief CRC hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip055 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip055 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_CRC_H_
#define _HWA_CRC_H_
#include "device_header.h"
#if CRC_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_crc HwA_crc
* @ingroup module_driver_crc
* @{
*/
/********* Local typedef ************/
/**
* @brief The data swap for write
*/
typedef enum{
WRITE_DATASWAP_NONE = 0U, /*!< none data swap for write */
WRITE_DATASWAP_BIT = 1U, /*!< only bits data swap for write */
WRITE_DATASWAP_BIT_BYTE = 2U, /*!< both bits and bytes data swap for write */
WRITE_DATASWAP_BYTE = 3U /*!< only bytes data swap for write */
} CRC_WriteDataSwapType;
/**
* @brief The data swap for read
*/
typedef enum{
READ_DATASWAP_NONE = 0U, /*!< none data swap for read */
READ_DATASWAP_BIT = 1U, /*!< only bits data swap for read */
READ_DATASWAP_BIT_BYTE = 2U, /*!< both bits and bytes data swap for read */
READ_DATASWAP_BYTE = 3U /*!< only bytes data swap for read */
} CRC_ReadDataSwapType;
/**
* @brief The complement of reading crc data
*/
typedef enum{
READ_DATA_NORMAL = 0U, /*!< none complement of reading crc data */
READ_DATA_FXOR = 1U /*!< Invert or complement with 0xFFFFFFFF or 0xFFFF of crc data */
} CRC_ReadDataFXORType;
/**
* @brief The command type of write crc data or seed value
*/
typedef enum{
WRITE_COMMAND_DATA = 0U, /*!< write crc data */
WRITE_COMMAND_SEED = 1U /*!< write seed value(used to initialization crc calculation) */
} CRC_WriteCommondType;
/**
* @brief The crc mode select
*/
typedef enum{
CRC_BIT_16 = 0U, /*!< crc 16 bit is selected */
CRC_BIT_32 = 1U, /*!< crc 32 bit is selected */
CRC_BIT_8 = 2U, /*!< crc 8 bit is selected */
CRC_BIT_INVALID = 3U
} CRC_BitWidthType;
/********* Local inline function ************/
/**
* @brief set CRC CR register for writing data or seed
*
* @param pCrc CRC instance
* @param u32Mod WAS mode
*/
LOCAL_INLINE void CRC_HWA_SetDataOrSeed(CRC_Type *const pCrc, CRC_WriteCommondType u32Mod)
{
uint32_t u32RegVal = pCrc->CR;
pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_WAS_MASK)) | CRC_CR_WAS(u32Mod));
}
/**
* @brief set polynomial value
*
* @param pCrc CRC instance
* @param u32Poly the polynomial value
*/
LOCAL_INLINE void CRC_HWA_SetPolyVal(CRC_Type *const pCrc, uint32_t u32Poly)
{
pCrc->POLY = u32Poly;
}
/**
* @brief set data register(32 bits)
*
* @param pCrc CRC instance
* @param u32Data data to be set
*/
LOCAL_INLINE void CRC_HWA_SetData_U32(CRC_Type *const pCrc, uint32_t u32Data)
{
pCrc->DATA.uDATA = u32Data;
}
/**
* @brief set data register(16 bits)
*
* @param pCrc CRC instance
* @param u16Data data to be set
*/
LOCAL_INLINE void CRC_HWA_SetData_U16(CRC_Type *const pCrc, uint16_t u16Data)
{
pCrc->DATA.tDATA_16.L = u16Data;
}
/**
* @brief set data register(low 8 bits)
*
* @param pCrc CRC instance
* @param u8Data data to be set
*/
LOCAL_INLINE void CRC_HWA_SetData_U8(CRC_Type *const pCrc, uint8_t u8Data)
{
pCrc->DATA.tDATA_8.LL = u8Data;
}
/**
* @brief get data register(32 bits)
*
* @param pCrc CRC instance
*
* @return 32-bit value
*/
LOCAL_INLINE uint32_t CRC_HWA_GetData_U32(CRC_Type *const pCrc)
{
return (pCrc->DATA.uDATA);
}
/**
* @brief get data register(high 16 bits)
*
* @param pCrc CRC instance
*
* @return high 16-bit value
*/
LOCAL_INLINE uint16_t CRC_HWA_GetData_U16_H(CRC_Type *const pCrc)
{
return (pCrc->DATA.tDATA_16.H);
}
/**
* @brief get data register(low 16 bits)
*
* @param pCrc CRC instance
*
* @return low 16-bit value
*/
LOCAL_INLINE uint16_t CRC_HWA_GetData_U16_L(CRC_Type *const pCrc)
{
return (pCrc->DATA.tDATA_16.L);
}
/**
* @brief set data swap for writes
*
* @param pCrc CRC instance
* @param eWrDataSwap the CRC_WriteDataSwapType type
*/
LOCAL_INLINE void CRC_HWA_SetWriteDataSwap(CRC_Type *const pCrc, CRC_WriteDataSwapType eWrDataSwap)
{
uint32_t u32RegVal = pCrc->CR;
pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_DSW_MASK)) | CRC_CR_DSW(eWrDataSwap));
}
/**
* @brief set data swap for read
*
* @param pCrc CRC instance
* @param eRdDataSwap the eRdDataSwap type
*/
LOCAL_INLINE void CRC_HWA_SetReadDataSwap(CRC_Type *const pCrc, CRC_ReadDataSwapType eRdDataSwap)
{
uint32_t u32RegVal = pCrc->CR;
pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_DSR_MASK)) | CRC_CR_DSR(eRdDataSwap));
}
/**
* @brief set complement read Of CRC data
*
* @param pCrc CRC instance
* @param eRdDataFXOR the CRC_ReadDataFXORType type
*/
LOCAL_INLINE void CRC_HWA_SetReadDataFXOR(CRC_Type *const pCrc, CRC_ReadDataFXORType eRdDataFXOR)
{
uint32_t u32RegVal = pCrc->CR;
pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_FXOR_MASK)) | CRC_CR_FXOR(eRdDataFXOR));
}
#if CRC_8_BIT_HARDWARE_SUPPORT
/**
* @brief set 8bit width of CRC protocol
*
* @param pCrc CRC instance
* @param eWidth the CRC_BitWidthType type
*/
LOCAL_INLINE void CRC_HWA_Set_8Bit_Width(CRC_Type *const pCrc, CRC_BitWidthType eWidth)
{
uint32_t u32RegVal = pCrc->CR;
pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_TCRC8_MASK)) | CRC_CR_TCRC8(eWidth));
}
/**
* @brief get 8-bit width of CRC protocol
*
* @param pCrc CRC instance
*/
LOCAL_INLINE CRC_BitWidthType CRC_HWA_Get8BitWidth(CRC_Type *const pCrc)
{
uint32_t u32TempVal = (pCrc->CR & ((uint32_t)CRC_CR_TCRC8_MASK)) >> CRC_CR_TCRC8_SHIFT;
return ((u32TempVal == 1U)?CRC_BIT_8:CRC_BIT_INVALID);
}
#endif
/**
* @brief set width of CRC protocol
*
* @param pCrc CRC instance
* @param eWidth the CRC_BitWidthType type
*/
LOCAL_INLINE void CRC_HWA_SetBitWidth(CRC_Type *const pCrc, CRC_BitWidthType eWidth)
{
uint32_t u32RegVal = pCrc->CR;
pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_TCRC_MASK)) | CRC_CR_TCRC(eWidth));
}
/**
* @brief get width of CRC protocol
*
* @param pCrc CRC instance
*/
LOCAL_INLINE CRC_BitWidthType CRC_HWA_GetBitWidth(CRC_Type *const pCrc)
{
uint32_t u32TempVal = (pCrc->CR & ((uint32_t)CRC_CR_TCRC_MASK)) >> CRC_CR_TCRC_SHIFT;
return ((u32TempVal == 0U)?CRC_BIT_16:CRC_BIT_32);
}
/**
* @brief get data swap type for read
*
* @param pCrc CRC instance
*/
LOCAL_INLINE CRC_ReadDataSwapType CRC_HWA_GetReadDataSwap(CRC_Type *const pCrc)
{
CRC_ReadDataSwapType eRet = READ_DATASWAP_NONE;
uint32_t u32TempVal;
u32TempVal = (pCrc->CR & ((uint32_t)CRC_CR_DSR_MASK))>>CRC_CR_DSR_SHIFT;
if (u32TempVal == 0U)
{
eRet = READ_DATASWAP_NONE;
}
else if (u32TempVal == 1U)
{
eRet = READ_DATASWAP_BIT;
}
else if (u32TempVal == 2U)
{
eRet = READ_DATASWAP_BIT_BYTE;
}
else if (u32TempVal == 3U)
{
eRet = READ_DATASWAP_BYTE;
}
else
{
/*Noting to do*/
}
return eRet;
}
/** @}*/
#endif /* #if CRC_INSTANCE_COUNT > 0U */
#endif /* #ifndef _HWA_CRC_H_ */

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/**
* @file HwA_crm.h
* @author Flagchip
* @brief CRM register API
* @version 2.5.0
* @date 2025-08-22
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2025 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 2.5.0 2025-8-22 Flagchip112 N/A Release version for FC7300FDDT1C
******************************************************************************** */
#ifndef _HWA_CRM_H_
#define _HWA_CRM_H_
#include "device_header.h"
#include "module_driver_flexcan.h"
#if CRM_INSTANCE_COUNT > 0U
/* ################################################################################## */
/* ####################################### Macro #################################### */
/**
* @brief CAN router interrupt type
*/
typedef enum
{
CRM_CANR_INT_MAP_MULTI, /* Multiple mapping interrupt */
CRM_CANR_INT_MAP_NONE, /* No mapping interrupt */
CRM_CANR_INT_MAP_DONE, /* Mapping done interrupt */
CRM_CANR_INT_BUSY, /* Busy interrupt */
CRM_CANR_INT_MAP_SELF /* Self mapping interrupt */
} CRM_IntType;
/**
* @brief Structure for CRM interrupt mask configuration
*
* Bitfield configuration matches CRM_CANR_IEN register layout:
* - MAP_MULTI_IE: Multiple mapping error flag interrupt enable (bit31)
* - MAP_NONE_IE: No mapping error flag interrupt enable (bit30)
* - MAP_DONE_IE: Mapping completion flag interrupt enable (bit24)
* - BUSY_IE: Busy state flag interrupt enable (bit8)
* - MAP_SELF_IE: Self-mapping flag interrupt enable (bit0)
*/
typedef struct
{
bool bMapMultiIE;
bool bMapNoneIE;
bool bMapDoneIE;
bool bBusyIE;
bool bMapSelfIE;
} CRM_IntMaskType;
/********* Local inline function ************/
/* ---------------------------- Channel Registers ----------------------------- */
/**
* @brief Set MATCH_ID0 register for specified channel
* @param ch Channel number (CRM_CH0-CRM_CH3)
* @param u32val Value to set
*/
LOCAL_INLINE void CRM_HWA_Set_CH_MATCH_ID0(CRM_ChannelIndex eChannel, FLEXCAN_IdType eIdType, uint32_t u32val)
{
uint32_t u32valtemp = 0;
if(FLEXCAN_ID_STD == eIdType)
{
u32valtemp = u32val << 18;
}else
{
u32valtemp = u32val;
}
switch (eChannel)
{
case CRM_CH0: CRM->CH0_MATCH_ID0 = u32valtemp; break;
case CRM_CH1: CRM->CH1_MATCH_ID0 = u32valtemp; break;
case CRM_CH2: CRM->CH2_MATCH_ID0 = u32valtemp; break;
case CRM_CH3: CRM->CH3_MATCH_ID0 = u32valtemp; break;
default: break;
}
}
/**
* @brief Set MATCH_ID1 register for specified channel
* @param ch Channel number (CRM_CH0-CRM_CH3)
* @param u32val Value to set
*/
LOCAL_INLINE void CRM_HWA_Set_CH_MATCH_ID1(CRM_ChannelIndex eChannel, FLEXCAN_IdType eIdType, uint32_t u32val)
{
uint32_t u32valtemp = 0;
if(FLEXCAN_ID_STD == eIdType)
{
u32valtemp = u32val << 18;
}else
{
u32valtemp = u32val;
}
switch (eChannel)
{
case CRM_CH0: CRM->CH0_MATCH_ID1 = u32valtemp; break;
case CRM_CH1: CRM->CH1_MATCH_ID1 = u32valtemp; break;
case CRM_CH2: CRM->CH2_MATCH_ID1 = u32valtemp; break;
case CRM_CH3: CRM->CH3_MATCH_ID1 = u32valtemp; break;
default: break;
}
}
/**
* @brief Set ROUTER_ID0 register for specified channel
* @param ch Channel number (CRM_CH0-CRM_CH3)
* @param u32val Value to set
*/
LOCAL_INLINE void CRM_HWA_Set_CH_ROUTER_ID0(CRM_ChannelIndex ch, FLEXCAN_IdType eIdType, uint32_t u32val)
{
uint32_t u32valtemp = 0;
if(FLEXCAN_ID_STD == eIdType)
{
u32valtemp = u32val << 18;
}else
{
u32valtemp = u32val;
}
switch (ch)
{
case CRM_CH0: CRM->CH0_ROUTER_ID0 = u32valtemp; break;
case CRM_CH1: CRM->CH1_ROUTER_ID0 = u32valtemp; break;
case CRM_CH2: CRM->CH2_ROUTER_ID0 = u32valtemp; break;
case CRM_CH3: CRM->CH3_ROUTER_ID0 = u32valtemp; break;
default: break;
}
}
/**
* @brief Set ROUTER_CS0 register for specified channel
* @param ch Channel number (CRM_CH0-CRM_CH3)
* @param u32val Value to set
*/
LOCAL_INLINE void CRM_HWA_Set_CH_ROUTER_CS0(CRM_ChannelIndex ch, uint32_t u32val)
{
switch (ch)
{
case CRM_CH0: CRM->CH0_ROUTER_CS0 = u32val; break;
case CRM_CH1: CRM->CH1_ROUTER_CS0 = u32val; break;
case CRM_CH2: CRM->CH2_ROUTER_CS0 = u32val; break;
case CRM_CH3: CRM->CH3_ROUTER_CS0 = u32val; break;
default: break;
}
}
/**
* @brief Set ROUTER_ID1 register for specified channel
* @param ch Channel number (CRM_CH0-CRM_CH3)
* @param u32val Value to set
*/
LOCAL_INLINE void CRM_HWA_Set_CH_ROUTER_ID1(CRM_ChannelIndex ch, FLEXCAN_IdType eIdType, uint32_t u32val)
{
uint32_t u32valtemp = 0;
if(FLEXCAN_ID_STD == eIdType)
{
u32valtemp = u32val << 18;
}else
{
u32valtemp = u32val;
}
switch (ch)
{
case CRM_CH0: CRM->CH0_ROUTER_ID1 = u32valtemp; break;
case CRM_CH1: CRM->CH1_ROUTER_ID1 = u32valtemp; break;
case CRM_CH2: CRM->CH2_ROUTER_ID1 = u32valtemp; break;
case CRM_CH3: CRM->CH3_ROUTER_ID1 = u32valtemp; break;
default: break;
}
}
/**
* @brief Set ROUTER_CS1 register for specified channel
* @param ch Channel number (CRM_CH0-CRM_CH3)
* @param u32val Value to set
*/
LOCAL_INLINE void CRM_HWA_Set_CH_ROUTER_CS1(CRM_ChannelIndex ch, uint32_t u32val)
{
switch (ch)
{
case CRM_CH0: CRM->CH0_ROUTER_CS1 = u32val; break;
case CRM_CH1: CRM->CH1_ROUTER_CS1 = u32val; break;
case CRM_CH2: CRM->CH2_ROUTER_CS1 = u32val; break;
case CRM_CH3: CRM->CH3_ROUTER_CS1 = u32val; break;
default: break;
}
}
/**
* @brief Set MATCH_MASK register for specified channel
* @param ch Channel number (CRM_CH0-CRM_CH3)
* @param u32val Value to set
*/
LOCAL_INLINE void CRM_HWA_Set_CH_MATCH_MASK(CRM_ChannelIndex ch, FLEXCAN_IdType eIdType, uint32_t u32val)
{
uint32_t u32valtemp = 0;
if(FLEXCAN_ID_STD == eIdType)
{
u32valtemp = u32val << 18;
}else
{
u32valtemp = u32val;
}
switch (ch)
{
case CRM_CH0: CRM->CH0_MATCH_MASK = u32valtemp; break;
case CRM_CH1: CRM->CH1_MATCH_MASK = u32valtemp; break;
case CRM_CH2: CRM->CH2_MATCH_MASK = u32valtemp; break;
case CRM_CH3: CRM->CH3_MATCH_MASK = u32valtemp; break;
default: break;
}
}
/**
* @brief Get MAP_CS register value for specified channel (read-only)
* @param ch Channel number (CRM_CH0-CRM_CH3)
* @return Register value
*/
LOCAL_INLINE uint32_t CRM_HWA_Get_CH_MAP_CS(CRM_ChannelIndex ch)
{
switch (ch)
{
case CRM_CH0: return CRM->CH0_MAP_CS;
case CRM_CH1: return CRM->CH1_MAP_CS;
case CRM_CH2: return CRM->CH2_MAP_CS;
case CRM_CH3: return CRM->CH3_MAP_CS;
default: return 0;
}
}
/**
* @brief Get MAP_ID register value for specified channel (read-only)
* @param ch Channel number (CRM_CH0-CRM_CH3)
* @return Register value
*/
LOCAL_INLINE uint32_t CRM_HWA_Get_CH_MAP_ID(CRM_ChannelIndex ch)
{
switch (ch)
{
case CRM_CH0: return CRM->CH0_MAP_ID;
case CRM_CH1: return CRM->CH1_MAP_ID;
case CRM_CH2: return CRM->CH2_MAP_ID;
case CRM_CH3: return CRM->CH3_MAP_ID;
default: return 0;
}
}
/* -------------------------- CAN Router Registers ---------------------------- */
/**
* @brief Enable specific CAN router interrupt
* @param eIntType Interrupt type to enable
* @param chMask Channel mask (only for channel-specific interrupts)
*/
LOCAL_INLINE void CRM_HWA_EnableCanrInt(CRM_ChannelIndex ch, CRM_IntMaskType chMask)
{
uint32_t u32RegVal = CRM->CANR_IEN;
u32RegVal |= CRM_CANR_STATUS_MAP_MULTI_FLAG(chMask.bMapMultiIE);
u32RegVal |= CRM_CANR_STATUS_MAP_NONE_FLAG(chMask.bMapNoneIE);
u32RegVal |= CRM_CANR_STATUS_MAP_DONE_FLAG((chMask.bMapDoneIE) << ch);
u32RegVal |= CRM_CANR_STATUS_BUSY_FLAG((chMask.bBusyIE) << ch);
u32RegVal |= CRM_CANR_STATUS_MAP_SELF_FLAG((chMask.bMapSelfIE) << ch);
CRM->CANR_IEN = u32RegVal;
}
/**
* @brief Disable specific CAN router interrupt
* @param eIntType Interrupt type to disable
* @param chMask Channel mask (only for channel-specific interrupts)
*/
LOCAL_INLINE void CRM_HWA_DisableCanrInt(CRM_ChannelIndex ch)
{
uint32_t u32RegVal = 0;
u32RegVal |= CRM_CANR_STATUS_MAP_MULTI_FLAG(1U);
u32RegVal |= CRM_CANR_STATUS_MAP_NONE_FLAG(1U);
u32RegVal |= CRM_CANR_STATUS_MAP_DONE_FLAG(1U << ch);
u32RegVal |= CRM_CANR_STATUS_BUSY_FLAG(1U << ch);
u32RegVal |= CRM_CANR_STATUS_MAP_SELF_FLAG(1U << ch);
CRM->CANR_IEN &= ~u32RegVal;
}
/**
* @brief Get CANR_STATUS register value
* @return Register value
*/
LOCAL_INLINE uint32_t CRM_HWA_Get_CANR_STATUS(void)
{
return CRM->CANR_STATUS;
}
/**
* @brief Clear specific status flag in CANR_STATUS
* @param eIntType Status flag type to clear
* @param chMask Channel mask (only for channel-specific flags)
*/
LOCAL_INLINE void CRM_HWA_ClearCanrStatus(CRM_IntType eIntType, uint8_t chMask)
{
uint32_t u32RegVal = CRM->CANR_STATUS;
switch (eIntType)
{
case CRM_CANR_INT_MAP_MULTI:
u32RegVal &= ~CRM_CANR_STATUS_MAP_MULTI_FLAG_MASK;
break;
case CRM_CANR_INT_MAP_NONE:
u32RegVal &= ~CRM_CANR_STATUS_MAP_NONE_FLAG_MASK;
break;
case CRM_CANR_INT_MAP_DONE:
u32RegVal &= ~(chMask << CRM_CANR_STATUS_MAP_DONE_FLAG_SHIFT);
break;
case CRM_CANR_INT_BUSY:
u32RegVal &= ~(chMask << CRM_CANR_STATUS_BUSY_FLAG_SHIFT);
break;
case CRM_CANR_INT_MAP_SELF:
u32RegVal &= ~(chMask << CRM_CANR_STATUS_MAP_SELF_FLAG_SHIFT);
break;
default:
break;
}
CRM->CANR_STATUS = u32RegVal;
}
/**
* @brief Set CANR_CTRL register value
* @param u32val Value to set
*/
LOCAL_INLINE void CRM_HWA_Set_CANR_CTRL(uint32_t u32val)
{
CRM->CANR_CTRL = u32val & CRM_CANR_CTRL_MASK;
}
/**
* @brief Get CANR_CTRL register value
* @return Register value
*/
LOCAL_INLINE uint32_t CRM_HWA_Get_CANR_CTRL(void)
{
return CRM->CANR_CTRL;
}
/**
* @brief Enable specific channel in CAN router
* @param ch Channel to enable
*/
LOCAL_INLINE void CRM_HWA_EnableChannel(CRM_ChannelIndex ch)
{
CRM->CANR_CTRL |= (1 << ch);
}
/**
* @brief Disable specific channel in CAN router
* @param ch Channel to disable
*/
LOCAL_INLINE void CRM_HWA_DisableChannel(CRM_ChannelIndex ch)
{
CRM->CANR_CTRL &= ~(1 << ch);
}
/** @}*/
#endif /* CRM_INSTANCE_COUNT > 0U */
#endif /* HWA_INCLUDE_HWA_crm_H_ */

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/**
* @file HwA_dmamux.h
* @author flagchip
* @brief Hardware access layer for DMAMUX
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip099 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_DMAMUX_H_
#define _HWA_DMAMUX_H_
#include "device_header.h"
#if DMAMUX_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_dmamux HwA_dmamux
* @ingroup module_driver_dma
* @{
*/
/**
* @brief Get whether DMAMUX is enabled for the specified DMA channel
*
* @param pDmamux the base address of the DMAMUX instance
* @param u8Channel the selected DMA channel
* @return true DMAMUX is enabled for the specified DMA channel
* @return false DMAMUX is disabled for the specified DMA channel
*/
LOCAL_INLINE bool DMAMUX_HWA_GetEnableFlag(const DMAMUX_Type *const pDmamux, uint8_t u8Channel)
{
uint8_t u8TmpVal = (pDmamux->CHCFG[u8Channel] & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT;
return (bool)((u8TmpVal != 0U) ? true : false);
}
/**
* @brief Get the request source for the specified DMA channel
*
* @param pDmamux the base address of the DMAMUX instance
* @param u8Channel the selected DMA channel
* @return DMA_RequestSourceType the request source of the specified DMA channel
*/
LOCAL_INLINE DMA_RequestSourceType DMAMUX_HWA_GetRequestSource(const DMAMUX_Type *const pDmamux, uint8_t u8Channel)
{
uint8_t u8TmpVal = (pDmamux->CHCFG[u8Channel] & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT;
return (DMA_RequestSourceType)u8TmpVal;
}
/**
* @brief Set the request source for the specified DMA channel
*
* @param pDmamux the base address of the DMAMUX instance
* @param u8Channel the selected DMA channel
* @param bEnable whether to enable DMAMUX for the specified DMA channel
* @param eReqSrc the request source to set for the specified DMA channel
*/
LOCAL_INLINE void DMAMUX_HWA_SetRequestSource(DMAMUX_Type *const pDmamux, uint8_t u8Channel, bool bEnable,
DMA_RequestSourceType eReqSrc)
{
pDmamux->CHCFG[u8Channel] = (uint8_t)((pDmamux->CHCFG[u8Channel] & ~(DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE_MASK)) |
DMAMUX_CHCFG_ENBL(bEnable) | DMAMUX_CHCFG_SOURCE(eReqSrc));
}
/**
* @brief Get whether periodic trig is enabled for the specified DMA channel
*
* @note Only DMA channel 0~3 supports periodic trig
*
* @param pDmamux the base address of the DMAMUX instance
* @param u8Channel the selected DMA channel
* @return true periodic trig is enabled for the specified DMA channel
* @return true periodic trig is disabled for the specified DMA channel
*/
LOCAL_INLINE bool DMAMUX_HWA_GetPeriodicTrigFlag(const DMAMUX_Type *const pDmamux, uint8_t u8Channel)
{
uint8_t u8TmpVal = (uint8_t)((pDmamux->CHTRG & (DMAMUX_CHTRG_TRIG0_MASK << u8Channel)) >> u8Channel);
return (bool)((u8TmpVal != 0U) ? true : false);
}
/**
* @brief Set whether to enable periodic trig for the specified DMA channel
*
* @note Only DMA channel 0~3 supports periodic trig
*
* @param pDmamux the base address of the DMAMUX instance
* @param u8Channel the selected DMA channel
* @param bEnable whether to enable periodic trig for the specified DMA channel
*/
LOCAL_INLINE void DMAMUX_HWA_SetPeriodicTrigFlag(DMAMUX_Type *const pDmamux, uint8_t u8Channel, bool bEnable)
{
pDmamux->CHTRG = (uint8_t)((pDmamux->CHTRG & ~(DMAMUX_CHTRG_TRIG0_MASK << u8Channel)) | (DMAMUX_CHTRG_TRIG0(bEnable) << u8Channel));
}
/** @}*/
#endif /* #if DMAMUX_INSTANCE_COUNT > 0U */
#endif /* _HWA_DMAMUX_H_ */

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/**
* @file HwA_eftu_ccm.h
* @author flagchip
* @brief Hardware access layer for EFTU CCM
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip099 N/A Change version and release
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_EFTU_CCM_H_
#define HWA_INCLUDE_HWA_EFTU_CCM_H_
#include "device_header.h"
#if EFTU_INSTANCE_COUNT > 0U
#define EFTU_CLUSTER_CLOCK_COUNT (8U)
#define EFTU_GTOM_CHANNEL_COUNT (16U)
#define EFTU_GTRIGGER_OUT_COUNT (8U)
#define EFTU_CMP_COUNT (2U)
#define EFTU_DMA_REQUEST_COUNT (6U)
#define EFTU_GTRIGGER_OUT_MASK_TOM1_CCU1_BIT0 (0x1<<0U)
#define EFTU_GTRIGGER_OUT_MASK_TOM0_CCU1_BIT1 (0x1<<1U)
#define EFTU_GTRIGGER_OUT_MASK_TOM1_CCU0_BIT2 (0x1<<2U)
#define EFTU_GTRIGGER_OUT_MASK_TOM0_CCU0_BIT3 (0x1<<3U)
#define EFTU_GTRIGGER_OUT_MASK_TIM_TRIG_BIT4 (0x1<<4U)
#define EFTU_TIM_ERROR_EN_BIT0 (0x1<<0U)
#define EFTU_TIM_ERROR_EN_BIT1 (0x1<<1U)
#define EFTU_TIM_ERROR_EN_BIT2 (0x1<<2U)
#define EFTU_TIM_ERROR_EN_BIT3 (0x1<<3U)
#define EFTU_TIM_ERROR_EN_BIT4 (0x1<<4U)
#define EFTU_TIM_ERROR_EN_BIT5 (0x1<<5U)
#define EFTU_TOM_SWAP_OUT_2_3_OUT_T_0_1_BIT0 (0x1<<0U)
#define EFTU_TOM_SWAP_OUT_6_7_OUT_T_4_5_BIT1 (0x1<<1U)
#define EFTU_TOM_SWAP_OUT_10_11_OUT_T_8_9_BIT2 (0x1<<2U)
#define EFTU_TOM_SWAP_OUT_14_15_OUT_T_12_13_BIT3 (0x1<<3U)
#define EFTU_TOM_SWAP_OUT_4_7_OUT_T_0_3_BIT4 (0x1<<4U)
#define EFTU_TOM_SWAP_OUT12_15_OUT_T_8_11_BIT5 (0x1<<5U)
typedef enum
{
EFTU_CLUSTER_CLOCK_CMU_CLK = 0U,
EFTU_CLUSTER_CLOCK_CMU_CLK8 = 1U,
EFTU_CLUSTER_CLOCK_EXT_CAPTURE = 2U,
} EFTU_CCM_ClusterCmuClkSelectType;
typedef enum
{
EFTU_DEBUG_RUN = 0U,
EFTU_DEBUG_TOM_HALT = 1U,
EFTU_DEBUG_OUT_FREEZEN = 2U,
EFTU_DEBUG_ALL_HALT = 3U,
} EFTU_CCM_DebugMode;
typedef enum
{
EFTU_TIM_AUXI_SRC_CH0 = 0U,
EFTU_TIM_AUXI_SRC_CH1 = 1U,
EFTU_TIM_AUXI_SRC_CH2 = 2U,
EFTU_TIM_AUXI_SRC_CH3 = 3U,
EFTU_TIM_AUXI_SRC_CH4 = 4U,
EFTU_TIM_AUXI_SRC_CH5 = 5U,
EFTU_TIM_AUXI_SRC_CH6 = 6U,
EFTU_TIM_AUXI_SRC_CH7 = 7U,
EFTU_TIM_AUXI_SRC_CH8 = 8U,
EFTU_TIM_AUXI_SRC_CH9 = 9U,
EFTU_TIM_AUXI_SRC_CH10 = 10U,
EFTU_TIM_AUXI_SRC_CH11 = 11U,
EFTU_TIM_AUXI_SRC_CH12 = 12U,
EFTU_TIM_AUXI_SRC_CH13 = 13U,
EFTU_TIM_AUXI_SRC_CH14 = 14U,
EFTU_TIM_AUXI_SRC_CH15 = 15U,
} EFTU_CCM_AuxInChlSrcType;
typedef enum
{
EFTU0_OUT0 = 0U,
EFTU1_OUT0 = 1U,
EFTU2_OUT0 = 2U,
EFTU0_OUT1 = 3U,
EFTU1_OUT2 = 4U,
EFTU2_OUT3 = 5U,
} EFTU_CCM_AuxInSrcType;
typedef enum
{
EFTU_TIM_PAD_IN = 0U,
EFTU_TIM_EXT_TRIGGER = 0U,
} EFTU_CCM_TimInSrcType;
typedef enum
{
EFTU_GTOM_MUX_SRC_EFTU2_OUT = 0U,
EFTU_GTOM_MUX_SRC_EFTU1_OUT = 1U,
EFTU_GTOM_MUX_SRC_EFTU0_OUT = 2U,
} EFTU_CCM_GtomOutSrc;
typedef enum
{
EFTU_GTRIGGER_OUT_SRC_DIS = 0U,
EFTU_GTRIGGER_OUT_SRC_EFTU0 = 1U,
EFTU_GTRIGGER_OUT_SRC_EFTU1 = 2U,
EFTU_GTRIGGER_OUT_SRC_EFTU2 = 3U,
} EFTU_CCM_GlobalTriggerOutType;
typedef enum
{
EFTU0_CMP0 = 0U,
EFTU0_CMP1 = 1U,
} EFTU_CCM_CmpInstance;
typedef enum
{
EFTU_CMP_X_Y_SEL_EFTU0_OUT_0_7 = 0x0U,
EFTU_CMP_X_Y_SEL_EFTU0_OUT_8_15 = 0x1U,
EFTU_CMP_X_Y_SEL_EFTU1_OUT_0_7 = 0x2U,
EFTU_CMP_X_Y_SEL_EFTU1_OUT_8_15 = 0x3U,
EFTU_CMP_X_Y_SEL_EFTU2_OUT_0_7 = 0x4U,
EFTU_CMP_X_Y_SEL_EFTU2_OUT_8_15 = 0x5U,
EFTU_CMP_X_Y_SEL_EFTU0_OUT_T_0_7 = 0x8U,
EFTU_CMP_X_Y_SEL_EFTU0_OUT_T_8_15 = 0x9U,
EFTU_CMP_X_Y_SEL_EFTU1_OUT_T_0_7 = 0xAU,
EFTU_CMP_X_Y_SEL_EFTU1_OUT_T_8_15 = 0xBU,
EFTU_CMP_X_Y_SEL_EFTU2_OUT_T_0_7 = 0xCU,
EFTU_CMP_X_Y_SEL_EFTU2_OUT_T_8_15 = 0xDU,
} EFTU_CCM_CmpSrcSelectType;
typedef enum
{
EFTU_HRPWM_SRC_OUT03_OUT_T03 = 0x0U,
EFTU_HRPWM_SRC_OUT47_OUT_T47 = 0x1U,
EFTU_HRPWM_SRC_OUT07 = 0x2U,
EFTU_HRPWM_SRC_OUT_T07 = 0x3U,
} EFTU_CCM_HrPwmSrcType;
typedef enum
{
EFTU_TOM0_CH0_TO_TOM1_CH0 = 0x1U,
EFTU_TOM0_CH7_TO_TOM1_CH0 = 0x2U,
} EFTU_CCM_TomChTrigInType;
typedef enum
{
EFTU_CLUSTER_CMU_CLK_0 = 0u,
EFTU_CLUSTER_CMU_CLK_1 = 1u,
EFTU_CLUSTER_CMU_CLK_2 = 2u,
EFTU_CLUSTER_CMU_CLK_3 = 3u,
EFTU_CLUSTER_CMU_CLK_4 = 4u,
EFTU_CLUSTER_CMU_CLK_5 = 5u,
EFTU_CLUSTER_CMU_CLK_6 = 6u,
EFTU_CLUSTER_CMU_CLK_7 = 7u,
} EFTU_CCM_ClusterCmuClkType;
typedef enum
{
EFTU_TIM_ERR_CH0 = 0U,
EFTU_TIM_ERR_CH1 = 1U,
EFTU_TIM_ERR_CH2 = 2U,
EFTU_TIM_ERR_CH3 = 3U,
EFTU_TIM_ERR_CH4 = 4U,
EFTU_TIM_ERR_CH5 = 5U,
EFTU_TIM_ERR_CH6 = 6U,
EFTU_TIM_ERR_CH7 = 7U,
} EFTU_CCM_TimErrChnType;
/*EFTU_CCM_PROT*/
LOCAL_INLINE void EFTU_CCM_HWA_EnableProtection(EFTU_CCM_Type *pCcm)
{
pCcm->PROT |= EFTU_CCM_PROT_CLS_PROT_MASK;
}
LOCAL_INLINE void EFTU_CCM_HWA_DisableProtection(EFTU_CCM_Type *pCcm)
{
pCcm->PROT &= ~EFTU_CCM_PROT_CLS_PROT_MASK;
}
LOCAL_INLINE void EFTU_CCM_HWA_ConfigDebugMode(EFTU_CCM_Type *pCcm, EFTU_CCM_DebugMode eDebugMode)
{
pCcm->PROT = (pCcm->PROT & ~EFTU_CCM_PROT_DBG_MODE_MASK) | EFTU_CCM_PROT_DBG_MODE(eDebugMode);
}
/*EFTU_CCM_CFG*/
LOCAL_INLINE void EFTU_CCM_HWA_EnableTim0(EFTU_CCM_Type *pCcm)
{
pCcm->CFG |= EFTU_CCM_CFG_EN_TIM_MASK;
}
LOCAL_INLINE void EFTU_CCM_HWA_EnableTom0(EFTU_CCM_Type *pCcm)
{
pCcm->CFG |= EFTU_CCM_CFG_EN_TOM0_MASK;
}
LOCAL_INLINE void EFTU_CCM_HWA_EnableTom1(EFTU_CCM_Type *pCcm)
{
pCcm->CFG |= EFTU_CCM_CFG_EN_TOM1_MASK;
}
LOCAL_INLINE void EFTU_CCM_HWA_DisableTim0(EFTU_CCM_Type *pCcm)
{
pCcm->CFG &= ~EFTU_CCM_CFG_EN_TIM_MASK;
}
LOCAL_INLINE void EFTU_CCM_HWA_DisableTom0(EFTU_CCM_Type *pCcm)
{
pCcm->CFG &= ~EFTU_CCM_CFG_EN_TOM0_MASK;
}
LOCAL_INLINE void EFTU_CCM_HWA_DisableTom1(EFTU_CCM_Type *pCcm)
{
pCcm->CFG &= ~EFTU_CCM_CFG_EN_TOM1_MASK;
}
/*EFTU_CCM_CMU_CLK_CFG*/
LOCAL_INLINE void EFTU_CCM_HWA_SetClusterCmuClkSrc(EFTU_CCM_Type *pCcm, EFTU_CCM_ClusterCmuClkType eCmuClk, EFTU_CCM_ClusterCmuClkSelectType eCmuClkSelect)
{
pCcm->CMU_CLK_CFG = ((uint32_t)pCcm->CMU_CLK_CFG & ~(uint32_t)(0x3U << (uint8_t)(4 * eCmuClk)))| ((uint32_t)((uint8_t)eCmuClkSelect << (uint8_t)(4 * eCmuClk)));
}
/*EFTU_CCM_TIM_IN_SRC /EFTU_CCM_TIM_IN_SRC0 /EFTU_CCM_TIM_IN_SRC1 */
LOCAL_INLINE void EFTU_CCM_HWA_SetTimInSrc(EFTU_CCM_Type *pCcm, uint8_t u8TimChannel, EFTU_CCM_TimInSrcType eTimSrcSelect)
{
pCcm->TIM_IN_SRC = ((uint32_t)pCcm->TIM_IN_SRC & ~(uint32_t)(0x1u << u8TimChannel)) | ((uint32_t)eTimSrcSelect << u8TimChannel);
}
LOCAL_INLINE void EFTU_CCM_HWA_SetAuxInSel0_3(EFTU_CCM_Type *pCcm, uint8_t u8TimAuxIn, EFTU_CCM_AuxInSrcType eAuxInSecSrc, EFTU_CCM_AuxInChlSrcType eAuxInSecChannel)
{
pCcm->TIM_IN_SRC0 = (pCcm->TIM_IN_SRC0 & ~(uint32_t)(0x7FU << (u8TimAuxIn * 8U)))|(eAuxInSecSrc * 16U + eAuxInSecChannel) << (u8TimAuxIn * 8U);
}
LOCAL_INLINE void EFTU_CCM_HWA_SetAuxInSel4_7(EFTU_CCM_Type *pCcm, uint8_t u8TimAuxIn, EFTU_CCM_AuxInSrcType eAuxInSecSrc, EFTU_CCM_AuxInChlSrcType eAuxInSecChannel)
{
pCcm->TIM_IN_SRC1 =(pCcm->TIM_IN_SRC1 & ~(uint32_t)(0x7FU << ((u8TimAuxIn - 4U) * 8U))) | (eAuxInSecSrc * 16U + eAuxInSecChannel) << ((u8TimAuxIn - 4U) * 8U);
}
/*EFTU_CCM_TOM_OUT*/
LOCAL_INLINE uint16_t EFTU_CCM_HWA_GetTomOutlevel(EFTU_CCM_Type *pCcm)
{
return pCcm->EFTU_OUT & EFTU_CCM_EFTU_OUT_EFTU_OUT_MASK ;
}
LOCAL_INLINE uint16_t EFTU_CCM_HWA_GetTomNOutlevel(EFTU_CCM_Type *pCcm)
{
return (pCcm->EFTU_OUT & EFTU_CCM_EFTU_OUT_EFTU_OUT_T_MASK) >> EFTU_CCM_EFTU_OUT_EFTU_OUT_T_SHIFT;
}
/*EFTU_CCM_GTOM_MUX_0/EFTU_CCM_GTOM_MUX_1/EFTU_CCM_GTOM_MUX_2/EFTU_CCM_GTOM_MUX_3,only for EFTU0*/
LOCAL_INLINE void EFTU_CCM_HWA_SetGtomMux0_3(EFTU_CCM_Type *pCcm, uint8_t u8GtomAuxIn, EFTU_CCM_GtomOutSrc eGtomSrc, uint8_t u8channel)
{
pCcm->GTOM_MUX_0 &= ~(uint32_t)(0x7FU << (u8GtomAuxIn * 8U));
pCcm->GTOM_MUX_0 |= (uint32_t)(eGtomSrc << 5U | u8channel) << (u8GtomAuxIn * 8U);
}
LOCAL_INLINE void EFTU_CCM_HWA_SetGtomMux4_7(EFTU_CCM_Type *pCcm, uint8_t u8GtomAuxIn, EFTU_CCM_GtomOutSrc eGtomSrc, uint8_t u8channel)
{
pCcm->GTOM_MUX_1 &= ~(uint32_t)(0x7FU << ((u8GtomAuxIn - 4U) * 8U));
pCcm->GTOM_MUX_1 |= (uint32_t)(eGtomSrc << 5U | u8channel) << ((u8GtomAuxIn - 4U) * 8U);
}
LOCAL_INLINE void EFTU_CCM_HWA_SetGtomMux8_11(EFTU_CCM_Type *pCcm, uint8_t u8GtomAuxIn, EFTU_CCM_GtomOutSrc eGtomSrc, uint8_t u8channel)
{
pCcm->GTOM_MUX_2 &= ~(uint32_t)(0x7FU << ((u8GtomAuxIn - 8U) * 8U));
pCcm->GTOM_MUX_2 |= (uint32_t)(eGtomSrc << 5U | u8channel) << ((u8GtomAuxIn - 8U) * 8U);
}
LOCAL_INLINE void EFTU_CCM_HWA_SetGtomMux12_15(EFTU_CCM_Type *pCcm, uint8_t u8GtomAuxIn, EFTU_CCM_GtomOutSrc eGtomSrc, uint8_t u8channel)
{
pCcm->GTOM_MUX_3 &= ~(uint32_t)(0x7FU << ((u8GtomAuxIn - 12U) * 8U));
pCcm->GTOM_MUX_3 |= (uint32_t)(eGtomSrc << 5U | u8channel) << ((u8GtomAuxIn - 12U) * 8U);
}
#if (EFTU_HRPWM_SUPPORT == STD_ON)
/*EFTU_CCM_HRPWM_MUX,only for EFTU0*/
LOCAL_INLINE void EFTU_CCM_HWA_SetHrPwmSrc(EFTU_CCM_Type *pCcm, EFTU_CCM_HrPwmSrcType eHrpwmSrcStatus)
{
pCcm->HRPWM_MUX = (pCcm->HRPWM_MUX & ~EFTU_CCM_HRPWM_MUX_SWAP_CTRL_MASK)|eHrpwmSrcStatus;
}
#endif
/*EFTU_CCM_TRG_MUX/EFTU_CCM_TRG_EN0/EFTU_CCM_TRG_EN1,only for EFTU0*/
/*
#define EFTU_GTRIGGER_OUT_MASK_TOM1_CCU1_BIT0 (0x1<<0U)
#define EFTU_GTRIGGER_OUT_MASK_TOM0_CCU1_BIT1 (0x1<<1U)
#define EFTU_GTRIGGER_OUT_MASK_TOM1_CCU0_BIT2 (0x1<<2U)
#define EFTU_GTRIGGER_OUT_MASK_TOM0_CCU0_BIT3 (0x1<<3U)
#define EFTU_GTRIGGER_OUT_MASK_TIM_TRIG_BIT4 (0x1<<4U)
* */
LOCAL_INLINE void EFTU_CCM_HWA_ConfigGtomTriggerSrc(EFTU_CCM_Type *pCcm, uint8_t u8TrgMux, EFTU_CCM_GlobalTriggerOutType eGtriggerSrc)
{
pCcm->TRG_MUX &= ~(uint32_t)(0x3U << (2U * u8TrgMux));
pCcm->TRG_MUX |= (uint32_t)eGtriggerSrc << (2U * u8TrgMux);
}
LOCAL_INLINE void EFTU_CCM_HWA_ConfigGtomTriggerMask0_3(EFTU_CCM_Type *pCcm, uint8_t u8TrgMux, uint8_t u8TriggerMask)
{
pCcm->TRG_EN0 &= ~(uint32_t)(0x1FU << (u8TrgMux * 8U));
pCcm->TRG_EN0 |= (uint32_t)u8TriggerMask << (u8TrgMux * 8U);
}
LOCAL_INLINE void EFTU_CCM_HWA_ConfigGtomTriggerMask4_7(EFTU_CCM_Type *pCcm, uint8_t u8TrgMux, uint8_t u8TriggerMask)
{
pCcm->TRG_EN1 &= ~(uint32_t)(0x1FU << ((u8TrgMux - 4U) * 8U));
pCcm->TRG_EN1 |= (uint32_t)u8TriggerMask << ((u8TrgMux - 4U) * 8U);
}
/*EFTU_CCM_CMP_MUX_SEL,only for EFTU0*/
LOCAL_INLINE void EFTU_CCM_HWA_ConfigCmpSrc(EFTU_CCM_Type *pCcm, EFTU_CCM_CmpInstance eCmpInstance, uint8_t Cmp_EnMask, EFTU_CCM_CmpSrcSelectType eCmpSrc_X,
EFTU_CCM_CmpSrcSelectType eCmpSrc_Y)
{
pCcm->CMP_MUX_SEL &= ~ ((uint32_t)(0xFFU << (8U * (eCmpInstance + 2u))) | (uint32_t)(0xFU << (eCmpInstance * 8U)) |(uint32_t)(0xFU << (eCmpInstance * 8U + 4u)));
pCcm->CMP_MUX_SEL |= (uint32_t)Cmp_EnMask << (8U * (eCmpInstance + 2u)) | ((uint32_t)eCmpSrc_X << (eCmpInstance * 8U)) | ((uint32_t)eCmpSrc_Y << (eCmpInstance * 8U + 4u));
}
/*EFTU_CCM_CMP Interrupt,only for EFTU0*/
LOCAL_INLINE bool EFTU_CCM_HWA_GetCmp0IrqFlag(EFTU_CCM_Type *pCcm)
{
return (((pCcm->EINT_ST & EFTU_CCM_EINT_ST_CMP0_ERR_MASK) != 0U) ? TRUE : FALSE);
}
LOCAL_INLINE bool EFTU_CCM_HWA_GetCmp1IrqFlag(EFTU_CCM_Type *pCcm)
{
return (((pCcm->EINT_ST & EFTU_CCM_EINT_ST_CMP1_ERR_MASK) != 0U) ? TRUE : FALSE);
}
LOCAL_INLINE void EFTU_CCM_HWA_ClearCmp0IrqFlag(EFTU_CCM_Type *pCcm)
{
pCcm->EINT_ST = EFTU_CCM_EINT_ST_CMP0_ERR_MASK;
}
LOCAL_INLINE void EFTU_CCM_HWA_ClearCmp1IrqFlag(EFTU_CCM_Type *pCcm)
{
pCcm->EINT_ST = EFTU_CCM_EINT_ST_CMP1_ERR_MASK;
}
LOCAL_INLINE bool EFTU_CCM_HWA_GetCmp0IrqEnable(EFTU_CCM_Type *pCcm)
{
return (((pCcm->EINT_EN & EFTU_CCM_EINT_EN_CMP0_ENABLE_MASK) != 0U) ? TRUE : FALSE);
}
LOCAL_INLINE bool EFTU_CCM_HWA_GetCmp1IrqEnable(EFTU_CCM_Type *pCcm)
{
return (((pCcm->EINT_EN & EFTU_CCM_EINT_EN_CMP1_ENABLE_MASK) != 0U) ? TRUE : FALSE);
}
LOCAL_INLINE void EFTU_CCM_HWA_EnCmpInterrupt(EFTU_CCM_Type *pCcm, EFTU_CCM_CmpInstance eCmpInstance)
{
pCcm->EINT_EN |= EFTU_CCM_EINT_EN_CMP0_ENABLE_MASK << eCmpInstance;
}
LOCAL_INLINE uint32 EFTU_CCM_HWA_GetErrIrqFlag(EFTU_CCM_Type *pCcm)
{
return ((pCcm->EINT_ST & EFTU_CCM_EINT_ST_TIM_ERR_MASK) >> EFTU_CCM_EINT_ST_TIM_ERR_SHIFT);
}
/*EFTU_CCM_TOM_MUX*/
/*
#define EFTU_TOM_SWAP_OUT_2_3_OUT_T_0_1_BIT0 (0x1<<0U)
#define EFTU_TOM_SWAP_OUT_6_7_OUT_T_4_5_BIT1 (0x1<<1U)
#define EFTU_TOM_SWAP_OUT_10_11_OUT_T_8_9_BIT2 (0x1<<2U)
#define EFTU_TOM_SWAP_OUT_14_15_OUT_T_12_13_BIT3 (0x1<<3U)
#define EFTU_TOM_SWAP_OUT_4_7_OUT_T_0_3_BIT4 (0x1<<4U)
#define EFTU_TOM_SWAP_OUT12_15_OUT_T_8_11_BIT5 (0x1<<5U)
* */
LOCAL_INLINE void EFTU_CCM_HWA_SwapTomOut(EFTU_CCM_Type *pCcm, uint8_t u8OutSwapMask)
{
pCcm->TOM_MUX = ( pCcm->TOM_MUX & ~EFTU_CCM_TOM_MUX_TOM_SWAP_MASK)|EFTU_CCM_TOM_MUX_TOM_SWAP(u8OutSwapMask);
}
LOCAL_INLINE void EFTU_CCM_HWA_SetTom0ch0TrigIn(EFTU_CCM_Type *pCcm, EFTU_CCM_TomChTrigInType eChSrc)
{
pCcm->TOM_MUX |= EFTU_CCM_TOM_MUX_TOM_MUX_CTRL(eChSrc);
}
/*EFTU_CCM_SPEC_LOCK,only for EFTU0*/
LOCAL_INLINE void EFTU_CCM_HWA_SpecUnLock(EFTU_CCM_Type *pCcm)
{
pCcm->SPEC_LOCK = 0xBEEFCAFE;
}
LOCAL_INLINE void EFTU_CCM_HWA_SpecLock(EFTU_CCM_Type *pCcm)
{
pCcm->SPEC_LOCK = 0x5AFECAFE;
}
/*EFTU_CCM_EINT_EN,EFTU_CCM_TIM_EINT_EN0/EFTU_CCM_TIM_EINT_EN2*/
/*
#define EFTU_TIM_ERROR_EN_BIT0 (0x1<<0U)
#define EFTU_TIM_ERROR_EN_BIT1 (0x1<<1U)
#define EFTU_TIM_ERROR_EN_BIT2 (0x1<<2U)
#define EFTU_TIM_ERROR_EN_BIT3 (0x1<<3U)
#define EFTU_TIM_ERROR_EN_BIT4 (0x1<<4U)
#define EFTU_TIM_ERROR_EN_BIT5 (0x1<<5U)
*/
LOCAL_INLINE void EFTU_CCM_HWA_EnTimChnErrInterupt0_3(EFTU_CCM_Type *pCcm, uint8_t u8TimChannel, uint8_t u8ErrEnMask)
{
pCcm->TIM_EINT_EN0 |= (uint32_t)u8ErrEnMask << (u8TimChannel * 8U);
}
LOCAL_INLINE void EFTU_CCM_HWA_EnTimChnErrInterupt4_7(EFTU_CCM_Type *pCcm, uint8_t u8TimChannel, uint8_t u8ErrEnMask)
{
pCcm->TIM_EINT_EN1 |= (uint32_t)u8ErrEnMask << ((u8TimChannel - 4U) * 8U);
}
LOCAL_INLINE uint32 EFTU_CCM_HWA_GetTimErrEnable0_3(EFTU_CCM_Type *pCcm)
{
return pCcm->TIM_EINT_EN0 & EFTU_CCM_TIM_EINT_EN0_MASK;
}
LOCAL_INLINE uint32 EFTU_CCM_HWA_GetTimErrEnable4_7(EFTU_CCM_Type *pCcm)
{
return pCcm->TIM_EINT_EN1 & EFTU_CCM_TIM_EINT_EN1_MASK;
}
LOCAL_INLINE uint32 EFTU_CCM_HWA_GetTimErrFlag0_3(EFTU_CCM_Type *pCcm)
{
return pCcm->TIM_EINT_ST0 & EFTU_CCM_TIM_EINT_ST0_MASK;
}
LOCAL_INLINE uint32 EFTU_CCM_HWA_GetTimErrFlag4_7(EFTU_CCM_Type *pCcm)
{
return pCcm->TIM_EINT_ST1 & EFTU_CCM_TIM_EINT_ST1_MASK;
}
LOCAL_INLINE void EFTU_CCM_HWA_ClearTimErrFlag0_3(EFTU_CCM_Type *pCcm, uint32 u32ErrMask)
{
pCcm->TIM_EINT_ST0 &= u32ErrMask;
}
LOCAL_INLINE void EFTU_CCM_HWA_ClearTimErrFlag4_7(EFTU_CCM_Type *pCcm, uint32 u32ErrMask)
{
pCcm->TIM_EINT_ST1 &= u32ErrMask;
}
#if (EFTU_CCM_DMA_REQ_ONE_INSTANCE == 6U)
/*EFTU_CCM_DMA_SRC01/EFTU_CCM_DMA_SRC23/EFTU_CCM_DMA_SRC45*/
LOCAL_INLINE void EFTU_CCM_HWA_ConfigDmaSrc0_1(EFTU_CCM_Type *pCcm, uint8_t u8DmaChannel, uint8_t u8DmaReqMask)
{
pCcm->DMA_SRC01 &= ~(uint32_t)(EFTU_CCM_DMA_SRC01_REQ_0_MASK << (u8DmaChannel * EFTU_CCM_DMA_SRC01_REQ_1_SHIFT));
pCcm->DMA_SRC01 |= (uint32_t)u8DmaReqMask << (u8DmaChannel * EFTU_CCM_DMA_SRC01_REQ_1_SHIFT);
}
LOCAL_INLINE void EFTU_CCM_HWA_ConfigDmaSrc2_3(EFTU_CCM_Type *pCcm, uint8_t u8DmaChannel, uint8_t u8DmaReqMask)
{
pCcm->DMA_SRC23 &= ~(uint32_t)(EFTU_CCM_DMA_SRC01_REQ_0_MASK << ((u8DmaChannel - 2U) * EFTU_CCM_DMA_SRC01_REQ_1_SHIFT));
pCcm->DMA_SRC23 |= (uint32_t)u8DmaReqMask << ((u8DmaChannel - 2U) * EFTU_CCM_DMA_SRC01_REQ_1_SHIFT);
}
LOCAL_INLINE void EFTU_CCM_HWA_ConfigDmaSrc4_5(EFTU_CCM_Type *pCcm, uint8_t u8DmaChannel, uint8_t u8DmaReqMask)
{
pCcm->DMA_SRC45 &= ~(uint32_t)(EFTU_CCM_DMA_SRC01_REQ_0_MASK << ((u8DmaChannel - 4U) * EFTU_CCM_DMA_SRC01_REQ_1_SHIFT));
pCcm->DMA_SRC45 |= (uint32_t)u8DmaReqMask << ((u8DmaChannel - 4U) * EFTU_CCM_DMA_SRC01_REQ_1_SHIFT);
}
#elif (EFTU_CCM_DMA_REQ_ONE_INSTANCE == 16U)
LOCAL_INLINE void EFTU_CCM_HWA_ConfigDmaSrc(EFTU_CCM_Type *pCcm, uint8_t u8DmaChannel, uint8_t u8DmaReqMask)
{
pCcm->DMA_SRC[(uint8_t)(u8DmaChannel>>1u)] = ((pCcm->DMA_SRC[(uint8_t)(u8DmaChannel>>1u)]) & ((~(uint32_t)(EFTU_CCM_DMA_SRC_REQ_0_MASK << (((uint8_t)u8DmaChannel&0x1U) * EFTU_CCM_DMA_SRC_REQ_1_SHIFT)))))|
(((uint32_t)u8DmaReqMask << ((u8DmaChannel&0x1U) * EFTU_CCM_DMA_SRC_REQ_1_SHIFT)));
}
#endif /*EFTU_CCM_DMA_REQ_ONE_INSTANCE*/
#endif /*EFTU_INSTANCE_COUNT*/
#endif /* HWA_INCLUDE_HWA_EFTU_CCM_H_ */

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/**
* @file HwA_eftu_cmu.h
* @author flagchip
* @brief Hardware access layer for EFTU CMU
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip099 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_EFTU_CMU_H_
#define _HWA_EFTU_CMU_H_
#include "device_header.h"
#if EFTU_INSTANCE_COUNT > 0U
/********* Local typedef ************/
/*
* @brief Clock source selection for CMU_CLK_x_CTRL
*/
typedef enum
{
CMU_GCLK_EN = 0u,
CMU_ECLK1_EN = 1U,
}EFTU_CMU_ClkCtrlSrcType;
typedef enum
{
CLUSTER_RES_CONST_1 = 0u,
CMU_ECLK0_EN = 1U,
}EFTU_CMU_Clk8CtrlSrcType;
typedef enum
{
EFTU_CMU_INSTANCE = 0U,
}EFTU_CMU_InstanceType;
/**
* @brief Cmu clock definition
*/
typedef enum
{
EFTU_CMU_CLK_0 = 0u,
EFTU_CMU_CLK_1 = 1u,
EFTU_CMU_CLK_2 = 2u,
EFTU_CMU_CLK_3 = 3u,
EFTU_CMU_CLK_4 = 4u,
EFTU_CMU_CLK_5 = 5u,
EFTU_CMU_CLK_6 = 6u,
EFTU_CMU_CLK_7 = 7u,
EFTU_ECLK_0 = 8u,
EFTU_ECLK_1 = 9u,
}EFTU_CMU_ClkSrcType;
/********* Local inline function ************/
/*
* @brief enable Cmu clock
*/
LOCAL_INLINE void EFTU_CMU_HWA_EnableClock(EFTU_CMU_Type *const pCmu ,EFTU_CMU_ClkSrcType eChannel)
{
pCmu->CLK_EN = (uint32_t)(0x2U << (uint8_t)(eChannel*2U));
}
/*
* @brief disable the Cmu clock
*/
LOCAL_INLINE void EFTU_CMU_HWA_DisableClock(EFTU_CMU_Type *const pCmu ,EFTU_CMU_ClkSrcType eChannel)
{
pCmu->CLK_EN = (uint32_t)(0x1u << (uint8_t)(eChannel*2U));
}
/*
* @brief set CMU Global Clock Control Numerator
*/
LOCAL_INLINE void EFTU_CMU_HWA_SetGclkNum(EFTU_CMU_Type *const pCmu ,uint8_t u8Num)
{
pCmu->GCLK_NUM = EFTU_CMU_GCLK_NUM_GCLK_NUM(u8Num);
}
/*
* @brief set CMU Global Clock Control Denominator
*/
LOCAL_INLINE void EFTU_CMU_HWA_SetGclkDen(EFTU_CMU_Type *const pCmu ,uint8_t u8Den)
{
pCmu->GCLK_DEN = EFTU_CMU_GCLK_DEN_GCLK_DEN(u8Den);
}
/*
* @brief set CMU Control for Clock Source CMU_CLK[n] n = 0~7
*/
LOCAL_INLINE void EFTU_CMU_HWA_SetCmuclkCnt(EFTU_CMU_Type *const pCmu ,uint32_t u32Cnt,EFTU_CMU_ClkSrcType eChannel)
{
pCmu->CLKn_CTRL[(uint8_t)eChannel] = EFTU_CMU_CLKn_CTRL_CLK_CNT(u32Cnt);
}
/*
* @brief set CMU ECLK0 Clock Control Numerator
*/
LOCAL_INLINE void EFTU_CMU_HWA_SetEclk0Num(EFTU_CMU_Type *const pCmu ,uint32_t u32Num)
{
pCmu->ECLK0_NUM = EFTU_CMU_ECLKn_NUM_ECLK_NUM(u32Num);
}
/*
* @brief set CMU ECLK0 Clock Control Denominator
*/
LOCAL_INLINE void EFTU_CMU_HWA_SetEclk0Den(EFTU_CMU_Type *const pCmu ,uint32_t u32Den)
{
pCmu->ECLK0_DEN = EFTU_CMU_ECLKn_DEN_ECLK_DEN(u32Den);
}
/*
* @brief set CMU ECLK1 Clock Control Numerator
*/
LOCAL_INLINE void EFTU_CMU_HWA_SetEclk1Num(EFTU_CMU_Type *const pCmu ,uint32_t u32Num)
{
pCmu->ECLK1_NUM = EFTU_CMU_ECLKn_NUM_ECLK_NUM(u32Num);
}
/*
* @brief set CMU ECLK1 Clock Control Denominator
*/
LOCAL_INLINE void EFTU_CMU_HWA_SetEclk1Den(EFTU_CMU_Type *const pCmu ,uint32_t u32Den)
{
pCmu->ECLK1_DEN = EFTU_CMU_ECLKn_DEN_ECLK_DEN(u32Den);
}
LOCAL_INLINE void EFTU_CMU_HWA_SetCmuClkSrc(EFTU_CMU_Type *const pCmu ,EFTU_CMU_ClkSrcType eChannel,EFTU_CMU_ClkCtrlSrcType eCtrl)
{
if (CMU_GCLK_EN == eCtrl)
{
pCmu->CLK_CTRL &= ~(1u<<(uint8_t)eChannel);
}
else
{
pCmu->CLK_CTRL |=(1u<<(uint8_t)eChannel);
}
}
LOCAL_INLINE void EFTU_CMU_HWA_SetCmuClk8Src(EFTU_CMU_Type *const pCmu ,EFTU_CMU_Clk8CtrlSrcType eCtrl)
{
if (CLUSTER_RES_CONST_1 == eCtrl)
{
pCmu->CLK_CTRL &= ~(1u<<(uint8_t)8U);
}
else
{
pCmu->CLK_CTRL |=(1u<<(uint8_t)8U);
}
}
#endif
#endif /*#ifndef _HWA_EFTU_CMU_H_*/

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/**
* @file HwA_eftu_dtm.h
* @author flagchip
* @brief Hardware access layer for EFTU DTM
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip070 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_EFTU_ATM_H_
#define _HWA_EFTU_ATM_H_
#include "device_header.h"
#if EFTU_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_eftu_tom HwA_eftu_dtm
* @ingroup module_driver_eftu_dtm
* @{
*/
/**
* @brief Clock Resolution Selection
*
*/
typedef enum
{
EFTU_DTM_CLOCK_SRC_SYS_CLK = 0u, /* CLS_CLK resolution selected (cluster clock) */
EFTU_DTM_CLOCK_SRC_CMU_CLK0, /* CCM_CLK_RES[0] resolution selected */
EFTU_DTM_CLOCK_SRC_CMU_CLK1, /* CCM_CLK_RES[1] resolution selected */
EFTU_DTM_CLOCK_SRC_CMU_CLK2, /* CCM_CLK_RES[2] resolution selected */
} EFTU_DTM_ClockSourceType;
/**
* @brief Selection of DTM Update and PSU_SHUT_OFF Reset Signal
*
*/
typedef enum
{
EFTU_DTM_SEL_FALLING_EDGE_ON_CURRENT = 0U, /* Select falling edge on current DTM channel 0 input */
EFTU_DTM_SEL_RISING_EDGE_ON_CURRENT, /* Select rising edge on current DTM channel 0 input */
EFTU_DTM_SEL_FALLING_EDGE_ON_PRECEDING, /* Select falling edge on preceding DTM channel 0 input */
EFTU_DTM_SEL_RISING_EDGE_ON_PRECEDING, /* Select rising edge on preceding DTM channel 0 input */
} EFTU_DTM_UpdateSourceType;
/**
* @brief Selection of Output 1
*
*/
typedef enum
{
EFTU_DTM_O1SEL_INV_DEAD_TIME_SIGNAL = 0U, /* Inverse dead time signal selected */
EFTU_DTM_O1SEL_SPECIAL_FUNTION /* Special function on output 1 selected (defined by
CH_CTRL1[O1F_0]) */
} EFTU_DTM_Output1SelectType;
/**
* @brief Selection of Input 1
*
*/
typedef enum
{
EFTU_DTM_I1SEL_PSU_SHIFT = 0U, /* Signal PSU_SHIFT[0] selected */
EFTU_DTM_I1SEL_PRE_DTM_COUT3_I, /* Signal DTM_COUT3_I from preceding DTM instance selected */
} EFTU_DTM_Input1SelectType;
/**
* @brief Selection of Output 0 Control
*
*/
typedef enum
{
EFTU_DTM_OC_FUNCTIONAL = 0U, /* Functional output */
EFTU_DTM_OC_CONSTANT, /* Constant output defined by CH_CTRL2[SL0_0] */
} EFTU_DTM_Output0ControlType;
/**
* @brief Selection of Signal Level on Output
*
*/
typedef enum
{
EFTU_DTM_SL_LOW = 0U, /* Set Signal Level to 0 */
EFTU_DTM_SL_HIGH /* Set Signal Level to 1 */
} EFTU_DTM_SignalLevelType;
/**
* @brief Selection of Combinational Input
*
*/
typedef enum
{
EFTU_DTM_CIS_DTM_IN = 0U, /* Select the input DTM_IN[N] or DTM_IN_T[N] of the instance
(CH_CTRL3[TSEL0_N] selects one of the two input signals) */
EFTU_DTM_CIS_EDGE_TRIGG /* Select internal signal EDGE_TRIGG_[N] */
} EFTU_DTM_CombInputSelectType;
/**
* @brief Input Selection for Dead Time / Edge Trigger Generation
*
*/
typedef enum
{
EFTU_DTM_EDGE_TRIG_SEL_DTM_IN = 0U, /* Use DTM_IN[N] of the instance as input for dead time / edge trigger
generation */
EFTU_DTM_EDGE_TRIG_SEL_DTM_IN_T /* Use DTM_IN_T[N] of the instance as input for dead time / edge
trigger generation */
} EFTU_DTM_EdgeTrigSelectType;
/**
* @brief Input Selection of Combinational Logic Path
*
*/
typedef enum
{
EFTU_DTM_COMB_INPUT_LOGIC_PATH_SEL_DTM_IN = 0U, /* Use DTM_IN[N] of the instance as input for combinational logic path */
EFTU_DTM_COMB_INPUT_LOGIC_PATH_SEL_DTM_IN_T /* Use DTM_IN_T[N] of the instance as input for combinational logic
path */
} EFTU_DTM_CombInputLogicPathSelectType;
/**
* @brief Selection of PSU Input
*
*/
typedef enum
{
EFTU_DTM_PSU_IN_TIM_CH_IN = 0u, /* TIM_CH_IN0 or TIM_CH_IN1 selected */
EFTU_DTM_PSU_IN_DTM_AUX_IN, /* DTM_AUX_IN selected */
} EFTU_DTM_PsuInputSelectType;
/**
* @brief Selection of input signal to be used as shutoff signal
*
*/
typedef enum
{
EFTU_DTM_SHUTOFF_SEL_TIM_CH_IN0 = 0U, /* TIM_CH_IN0 selected */
EFTU_DTM_SHUTOFF_SEL_TIM_CH_IN1, /* TIM_CH_IN1 selected */
EFTU_DTM_SHUTOFF_SEL_DTM_AUX_IN2, /* DTM_AUX_IN[2] of the instance selected (SoC special connection) */
EFTU_DTM_SHUTOFF_SEL_DTM_AUX_IN3, /* DTM_AUX_IN[3] of the instance selected (SoC special connection) */
EFTU_DTM_SHUTOFF_SEL_DTM_AUX_IN0, /* DTM_AUX_IN[0] of the instance selected (SoC special connection) */
EFTU_DTM_SHUTOFF_SEL_DTM_AUX_IN1, /* DTM_AUX_IN[1] of the instance selected (SoC special connection) */
EFTU_DTM_SHUTOFF_SEL_DTM_LOW, /* '0' selected */
EFTU_DTM_SHUTOFF_SEL_DTM_HIGH /* '1' selected*/
} EFTU_DTM_ShutOffSignalType;
/**
* @brief Selection of Shift
*
*/
typedef enum
{
EFTU_DTM_SHIFT_SELECT_CHANNEL1 = 0u, /* Trigger signal for reloading DOWN COUNTER is IN_EDGE[0] of
DTM channel [0]; PSU works on DTM channel 1*/
EFTU_DTM_SHIFT_SELECT_CHANNEL2, /* Trigger signal for reloading DOWN COUNTER is IN_EDGE[1] of
DTM channel [1]; PSU works on DTM channel 2*/
EFTU_DTM_SHIFT_SELECT_CHANNEL3, /* Trigger signal for reloading DOWN COUNTER is IN_EDGE[2] of
DTM channel [2]; PSU works on DTM channel 3*/
EFTU_DTM_SHIFT_SELECT_CHANNEL0 /* No loading of DOWN COUNTER (blanking window feature
deactivated); PSU works on DTM channel 0*/
} EFTU_DTM_ShiftSelectType;
/**
* @brief Selection of TIM Input
*
*/
typedef enum
{
EFTU_DTM_TIM_SEL_TIM_IN0 = 0u,
EFTU_DTM_TIM_SEL_TIM_IN1,
} EFTU_DTM_TimInputSelectType;
/**
* @brief Selection of Channel deadtime trigger
*
*/
typedef enum
{
EFTU_DTM_CHDTV_TRIG_BY_FALLING_EDGE = 0U, /* Update of CHn_DTV triggered by falling edge */
EFTU_DTM_CHDTV_TRIG_BY_RISING_EDGE /* Update of CHn_DTV triggered by rising edge */
} EFTU_DTM_DeadTimeTrigSelectType;
/**
* @brief Set the clock source for EFTU DTM
*
* @param pDtm Pointer to the base address of the EFTU DTM, used to access the DTM controller registers
* @param eClockSource The clock source type to be set, which is an enumerated value representing different clock source options
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetClockSource(EFTU_DTM_Type * const pDtm, EFTU_DTM_ClockSourceType eClockSource)
{
pDtm->CTRL = (pDtm->CTRL & (~(uint32_t)EFTU_DTM_CTRL_CLK_SEL_MASK)) | EFTU_DTM_CTRL_CLK_SEL(eClockSource);
}
/**
* @brief Set the DTM update signal source
*
* @param pDtm Pointer to the base address of the DTM module, used to access the DTM control register
* @param eSignal The specified update signal source, which is an enumerated value representing different signal sources
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetUpdateSignal(EFTU_DTM_Type * const pDtm, EFTU_DTM_UpdateSourceType eSignal)
{
pDtm->CTRL = (pDtm->CTRL & (~(uint32_t)EFTU_DTM_CTRL_DTM_SEL_MASK)) | EFTU_DTM_CTRL_DTM_SEL(eSignal);
}
/**
* @brief Set the update mode of the DTM
*
* @param pDtm Pointer to the base address of the DTM module, used to access and modify DTM registers
* @param u8UpdateMode The value of the update mode, which determines the operating mode of the DTM
* 000b - Asynchronous update
* 001b - Shutoff release by writing 1 to bit CTRL[SHUT_OFF_RST]
* 010b - Shutoff release by Select DTM Update and PSU_SHUT_OFF
* Reset Signal
* 011b - Shutoff release by shutoff signal PSU_SHUT_OFF
* 100b - Signal IN_EDGE[0] (from channel 0) used to trigger update of
* CH_CTRL2 with content of CH_CTRL2_SR
* 101b - Signal IN_EDGE[1] (from channel 1) used to trigger update of
* CH_CTRL2 with content of CH_CTRL2_SR
* 110b - Signal IN_EDGE[2] (from channel 2) used to trigger update of
* CH_CTRL2 with content of CH_CTRL2_SR
* 111b - Signal IN_EDGE[3] (from channel 3) used to trigger update of
* CH_CTRL2 with content of CH_CTRL2_SR
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetUpdateMode(EFTU_DTM_Type * const pDtm, uint8_t u8UpdateMode)
{
pDtm->CTRL = (pDtm->CTRL & (~(uint32_t)EFTU_DTM_CTRL_UPD_MODE_MASK)) | EFTU_DTM_CTRL_UPD_MODE(u8UpdateMode);
}
/**
* @brief Set Individual Shutoff Feature Enable
*
* This function modifies the CH_SHUTOFF_EN bit in the CTRL register of the EFTU_DTM controller to enable or disable the channel shut-off feature.
*
* @param pDtm Pointer to the base address of the EFTU_DTM module, used to access the module's registers
* @param bEnable Boolean value specifying whether to enable the Individual Shutoff Feature Enable. If true, the feature is enabled; if false, it is disabled
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetChannelShutOffEnable(EFTU_DTM_Type * const pDtm, bool bEnable)
{
pDtm->CTRL = (pDtm->CTRL & (~(uint32_t)EFTU_DTM_CTRL_CH_SHUTOFF_EN_MASK)) | EFTU_DTM_CTRL_CH_SHUTOFF_EN(bEnable);
}
/**
* @brief Set the shadow register update enable
*
* @param pDtm Base address pointer to the EFTU_DTM controller for accessing its registers
* @param bEnable Enable flag for shadow register updates, true to enable updates, false to disable updates
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetShadowRegisterUpdateEnable(EFTU_DTM_Type * const pDtm, bool bEnable)
{
pDtm->CTRL = (pDtm->CTRL & (~(uint32_t)EFTU_DTM_CTRL_SR_UPD_EN_MASK)) | EFTU_DTM_CTRL_SR_UPD_EN(bEnable);
}
/**
* @brief Shut off reset
*
* @param pDtm Base address pointer to the EFTU_DTM controller for accessing its registers
*/
LOCAL_INLINE void EFTU_DTM_HWA_ShutOffReset(EFTU_DTM_Type * const pDtm)
{
pDtm->CTRL |= EFTU_DTM_CTRL_SHUT_OFF_RST_MASK;
}
/**
* @brief Selects the output 1 source for EFTU DTM
*
* @param pDtm Pointer to the base address of the EFTU DTM, used to access its registers
* @param u8Channel Channel number, used to calculate the position of the control bits
* @param eSelect Output 1 selection value, specifying the new output source
*/
LOCAL_INLINE void EFTU_DTM_HWA_SelectOutput1(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_Output1SelectType eSelect)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL1 = (pDtm->CH_CTRL1 & (~(((uint32_t)EFTU_DTM_CH_CTRL1_O1SEL_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL1_O1SEL_0(eSelect) << u8Channel);
}
/**
* @brief Selects the input 1 for EFTU DTM
*
* @param pDtm Pointer to the base address of the EFTU DTM, used to access DTM registers
* @param u8Channel Channel number, used to calculate the bit position for the channel control
* @param eSelect Input 1 selection value, specifying the new input source
*/
LOCAL_INLINE void EFTU_DTM_HWA_SelectInput1(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_Input1SelectType eSelect)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL1 = (pDtm->CH_CTRL1 & (~(((uint32_t)EFTU_DTM_CH_CTRL1_I1SEL_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL1_I1SEL_0(eSelect) << u8Channel);
}
/**
* @brief Enable or disable the swap flag for a specific channel
*
* @param pDtm Pointer to the base address of the EFTU_DTM module, used to access the module's registers
* @param u8Channel Channel number, used to calculate the corresponding bit in the channel control register
* @param bEnable Boolean value indicating whether to enable the data swap feature
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetSwapEnable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL1 = (pDtm->CH_CTRL1 & (~(((uint32_t)EFTU_DTM_CH_CTRL1_SWAP_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL1_SWAP_0(bEnable) << u8Channel);
}
/**
* @brief Set the output 1 function for a specific channel of the EFTU DTM module
*
* @param pDtm Pointer to the EFTU_DTM_Type structure, representing the base address of the EFTU DTM module
* @param u8Channel The channel number to configure
* @param u8Function The output 1 function selection value
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetOutput1Function(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, uint8_t u8Function)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL1 = (pDtm->CH_CTRL1 & (~(((uint32_t)EFTU_DTM_CH_CTRL1_O1F_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL1_O1F_0(u8Function) << u8Channel);
}
/**
* @brief Enable or disable cross dead time
*
* @param pDtm Base address pointer of the DTM module
* @param u8Channel Channel number
* @param bEnable True to enable cross dead time, false to disable
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetCrossDeadTimeEnable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable)
{
u8Channel = ((u8Channel & 0x2) << 3U);
pDtm->CH_CTRL1 = (pDtm->CH_CTRL1 & (~(((uint32_t)EFTU_DTM_CH_CTRL1_XDT_EN_0_1_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL1_XDT_EN_0_1(bEnable) << u8Channel);
}
/**
* @brief Enable or disable shift function
*
* @param pDtm Base address pointer of the DTM module
* @param u8Channel Channel number, supports only channel 1
* @param bEnable True to enable shift function, false to disable
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetShiftEnable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable)
{
u8Channel = (uint8_t)((u8Channel - 1U) << 3U);
pDtm->CH_CTRL1 = (pDtm->CH_CTRL1 & (~(((uint32_t)EFTU_DTM_CH_CTRL1_SH_EN_1_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL1_SH_EN_1(bEnable) << u8Channel);
}
/**
* @brief Invert output 0 polarity
*
* @param pDtm Base address pointer of the DTM module
* @param u8Channel Channel number
* @param bInvert True to invert the polarity of output 0, false to not invert
*/
LOCAL_INLINE void EFTU_DTM_HWA_InvertOutput0(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bInvert)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_POL0_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_POL0_0(bInvert) << u8Channel);
}
/**
* @brief Set output 0 control mode
*
* @param pDtm Base address pointer of the DTM module
* @param u8Channel Channel number
* @param eCtrl Control mode for output 0
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetOutput0Ctrl(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_Output0ControlType eCtrl)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_OC0_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_OC0_0(eCtrl) << u8Channel);
}
/**
* @brief Set output 0 signal level
*
* @param pDtm Base address pointer of the DTM module
* @param u8Channel Channel number
* @param eLevel Signal level for output 0
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetOutput0SignalLevel(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_SignalLevelType eLevel)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SL0_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SL0_0(eLevel) << u8Channel);
}
/**
* @brief Enable or disable dead time 0
*
* @param pDtm Base address pointer of the DTM module
* @param u8Channel Channel number
* @param bEnable True to enable dead time 0, false to disable
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetDeadTime0Enable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_DT0_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_DT0_0(bEnable) << u8Channel);
}
/**
* @brief Inverts the output polarity of a specified channel.
*
* @param pDtm Pointer to the EFTU DTM module register base.
* @param u8Channel The channel number, indicating which channel's output polarity to invert.
* @param bInvert A boolean value, true to invert the output polarity, false to keep it unchanged.
*/
LOCAL_INLINE void EFTU_DTM_HWA_InvertOutput1(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bInvert)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_POL1_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_POL1_0(bInvert) << u8Channel);
}
/**
* @brief Sets the control mode for output 1 of a specified channel.
*
* @param pDtm Pointer to the EFTU DTM module register base.
* @param u8Channel The channel number, indicating which channel's output 1 control mode to set.
* @param eCtrl The control mode for output 1, specifying how the output should be controlled.
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetOutput1Ctrl(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_Output0ControlType eCtrl)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_OC1_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_OC1_0(eCtrl) << u8Channel);
}
/**
* @brief Sets the signal level for output 1 of a specified channel.
*
* @param pDtm Pointer to the EFTU DTM module register base.
* @param u8Channel The channel number, indicating which channel's output 1 signal level to set.
* @param eLevel The signal level for output 1, specifying the output signal level.
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetOutput1SignalLevel(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_SignalLevelType eLevel)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SL1_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SL1_0(eLevel) << u8Channel);
}
/**
* @brief Enables or disables dead time insertion for output 1 of a specified channel.
*
* @param pDtm Pointer to the EFTU DTM module register base.
* @param u8Channel The channel number, indicating which channel's output 1 dead time insertion to control.
* @param bEnable A boolean value, true to enable dead time insertion, false to disable it.
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetDeadTime1Enable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_DT1_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_DT1_0(bEnable) << u8Channel);
}
/**
* @brief Set the value of the Channel Control 2 register
*
* @param pDtm Base address pointer of the EFTU_DTM module
* @param u32Value Value to be written to the CH_CTRL2 register
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetCHCTRL2(EFTU_DTM_Type * const pDtm, uint32_t u32Value)
{
pDtm->CH_CTRL2 = u32Value;
}
/**
* @brief Get the value of the Channel Control 2 register
*
* @param pDtm Base address pointer of the EFTU_DTM module
* @return uint32_t Current value of the CH_CTRL2 register
*/
LOCAL_INLINE uint32_t EFTU_DTM_HWA_GetCHCTRL2(EFTU_DTM_Type * const pDtm)
{
return pDtm->CH_CTRL2;
}
/**
* @brief Invert the polarity of Output 0
*
* @param pDtm Base address pointer of the EFTU_DTM module
* @param u8Channel Channel number
* @param bInvert Whether to invert the output polarity, true for inversion, false for no inversion
*/
LOCAL_INLINE void EFTU_DTM_HWA_InvertOutput0Shadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bInvert)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_POL0_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_POL0_0_SR(bInvert) << u8Channel);
}
/**
* @brief Set the control mode of Output 0
*
* @param pDtm Base address pointer of the EFTU_DTM module
* @param u8Channel Channel number
* @param eCtrl Control mode of Output 0
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetOutput0CtrlShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_Output0ControlType eCtrl)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_OC0_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_OC0_0_SR(eCtrl) << u8Channel);
}
/**
* @brief Set the signal level of Output 0
*
* @param pDtm Base address pointer of the EFTU_DTM module
* @param u8Channel Channel number
* @param eLevel Signal level of Output 0
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetOutput0SignalLevelShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_SignalLevelType eLevel)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_SL0_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_SL0_0_SR(eLevel) << u8Channel);
}
/**
* @brief Set the enable state of Dead Time 0
*
* @param pDtm Base address pointer of the EFTU_DTM module
* @param u8Channel Channel number
* @param bEnable Enable state of Dead Time 0, true for enabled, false for disabled
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetDeadTime0EnableShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_DT0_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_DT0_0_SR(bEnable) << u8Channel);
}
/**
* @brief Invert the polarity of Output 1
*
* @param pDtm Base address pointer of the EFTU_DTM module
* @param u8Channel Channel number
* @param bInvert Whether to invert the output polarity, true for inversion, false for no inversion
*/
LOCAL_INLINE void EFTU_DTM_HWA_InvertOutput1Shadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bInvert)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_POL1_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_POL1_0_SR(bInvert) << u8Channel);
}
/**
* @brief Set the output 1 control shadow register for a DTM channel
*
* This function sets the output 1 control shadow register (CH_CTRL2_SR) bits for a specific DTM channel,
* controlling the behavior of the output signal.
*
* @param pDtm Pointer to the base address of the DTM module
* @param u8Channel Channel number to select the specific DTM channel
* @param eCtrl Output control selection, specifying the behavior of the output signal
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetOutput1CtrlShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_Output0ControlType eCtrl)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_OC1_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_OC1_0_SR(eCtrl) << u8Channel);
}
/**
* @brief Set the output 1 signal level shadow register for a DTM channel
*
* This function sets the output 1 signal level shadow register (CH_CTRL2_SR) bits for a specific DTM channel,
* defining the signal level of the output.
*
* @param pDtm Pointer to the base address of the DTM module
* @param u8Channel Channel number to select the specific DTM channel
* @param eLevel Signal level selection, specifying the level of the output signal
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetOutput1SignalLevelShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_SignalLevelType eLevel)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_SL1_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_SL1_0_SR(eLevel) << u8Channel);
}
/**
* @brief Set the dead time 1 enable shadow register for a DTM channel
*
* @param pDtm Pointer to the base address of the DTM module
* @param u8Channel Channel number to select the specific DTM channel
* @param bEnable Dead time enable selection, true to enable, false to disable
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetDeadTime1EnableShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_DT1_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_DT1_0_SR(bEnable) << u8Channel);
}
/**
* @brief Directly set the CH_CTRL2_SR register value for a DTM channel
*
* @param pDtm Pointer to the base address of the DTM module
* @param u32Value Value to set the CH_CTRL2_SR register
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetCTRL2SR(EFTU_DTM_Type * const pDtm, uint32_t u32Value)
{
pDtm->CH_CTRL2_SR = u32Value;
}
/**
* @brief Get the CH_CTRL2_SR register value for a DTM channel
*
* @param pDtm Pointer to the base address of the DTM module
* @return uint32_t Value of the CH_CTRL2_SR register
*/
LOCAL_INLINE uint32_t EFTU_DTM_HWA_GetCTRL2SR(EFTU_DTM_Type * const pDtm)
{
return pDtm->CH_CTRL2_SR;
}
/**
* @brief Set the polarity of the comb input signal for a DTM channel
*
* @param pDtm Pointer to the base address of the DTM module
* @param u8Channel Channel number to select the specific DTM channel
* @param bInvert Polarity selection, true to invert, false to not invert
*/
LOCAL_INLINE void EFTU_DTM_InvertCombInput(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bInvert)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL3 = (pDtm->CH_CTRL3 & (~(((uint32_t)EFTU_DTM_CH_CTRL3_CII0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL3_CII0(bInvert) << u8Channel);
}
/**
* @brief Select the comb input signal source for a DTM channel
*
* @param pDtm Pointer to the base address of the DTM module
* @param u8Channel Channel number to select the specific DTM channel
* @param eSelect Signal source selection, specifying the input signal to use
*/
LOCAL_INLINE void EFTU_DTM_SelectCombInput(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_CombInputSelectType eSelect)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL3 = (pDtm->CH_CTRL3 & (~(((uint32_t)EFTU_DTM_CH_CTRL3_CIS0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL3_CIS0(eSelect) << u8Channel);
}
/**
* @brief Select the edge trigger source for a DTM channel
*
* @param pDtm Pointer to the base address of the DTM module
* @param u8Channel Channel number to select the specific DTM channel
* @param eSelect Trigger source selection, specifying the source of the trigger event
*/
LOCAL_INLINE void EFTU_DTM_SelectEdgeTrigGen(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_EdgeTrigSelectType eSelect)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL3 = (pDtm->CH_CTRL3 & (~(((uint32_t)EFTU_DTM_CH_CTRL3_TSEL0_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL3_TSEL0_0(eSelect) << u8Channel);
}
/**
* @brief Select the comb input logic path for a DTM channel
*
* @param pDtm Pointer to the base address of the DTM module
* @param u8Channel Channel number to select the specific DTM channel
* @param eSelect Logic path selection, specifying the logical processing of the input signal
*/
LOCAL_INLINE void EFTU_DTM_SelectCombInputLogicPath(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_CombInputLogicPathSelectType eSelect)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CH_CTRL3 = (pDtm->CH_CTRL3 & (~(((uint32_t)EFTU_DTM_CH_CTRL3_TSEL1_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL3_TSEL1_0(eSelect) << u8Channel);
}
/**
* @brief Set the reload value for the DTM
*
* @param pDtm Pointer to the base address of the DTM module
* @param u16RelBlk Reload value, specifying the reload value of the counter
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetReloadValueBlkWin(EFTU_DTM_Type * const pDtm, uint16_t u16RelBlk)
{
pDtm->PS_CTRL = (pDtm->PS_CTRL & (~(uint32_t)EFTU_DTM_PS_CTRL_RELBLK_MASK)) | EFTU_DTM_PS_CTRL_RELBLK(u16RelBlk);
}
/**
* @brief Select the power supply input source for the DTM
*
* @param pDtm Pointer to the base address of the DTM module
* @param eSelection Power supply input source selection, specifying the power supply input to use
*/
LOCAL_INLINE void EFTU_DTM_HWA_SelectPsuInput(EFTU_DTM_Type * const pDtm, EFTU_DTM_PsuInputSelectType eSelection)
{
pDtm->PS_CTRL = (pDtm->PS_CTRL & (~(uint32_t)EFTU_DTM_PS_CTRL_PSU_IN_SEL_MASK)) | EFTU_DTM_PS_CTRL_PSU_IN_SEL(eSelection);
}
/**
* @brief Inverts the input polarity
*
* @param pDtm Base address pointer of the EFTU DTM
* @param bInvert Whether to invert the input polarity, true for inversion, false for no inversion
*/
LOCAL_INLINE void EFTU_DTM_InvertInputPolarity(EFTU_DTM_Type * const pDtm, bool bInvert)
{
pDtm->PS_CTRL = (pDtm->PS_CTRL & (~(uint32_t)EFTU_DTM_PS_CTRL_IN_POL_MASK)) | EFTU_DTM_PS_CTRL_IN_POL(bInvert);
}
/**
* @brief Selects the timer input
*
* @param pDtm Base address pointer of the EFTU DTM
* @param eSelect Timer input selection parameter, see EFTU_DTM_TimInputSelectType definition
*/
LOCAL_INLINE void EFTU_DTM_HWA_SelectTimInput(EFTU_DTM_Type * const pDtm, EFTU_DTM_TimInputSelectType eSelect)
{
pDtm->PS_CTRL = (pDtm->PS_CTRL & (~(uint32_t)EFTU_DTM_PS_CTRL_TIM_SEL_MASK)) | EFTU_DTM_PS_CTRL_TIM_SEL(eSelect);
}
/**
* @brief Selects the shift operation
*
* @param pDtm Base address pointer of the EFTU DTM
* @param eSelect Shift selection parameter, see EFTU_DTM_ShiftSelectType definition
*/
LOCAL_INLINE void EFTU_DTM_HWA_SelectShift(EFTU_DTM_Type * const pDtm, EFTU_DTM_ShiftSelectType eSelect)
{
pDtm->PS_CTRL = (pDtm->PS_CTRL & (~(uint32_t)EFTU_DTM_PS_CTRL_SHIFT_SEL_MASK)) | EFTU_DTM_PS_CTRL_SHIFT_SEL(eSelect);
}
/**
* @brief Sets the rising edge dead time
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param u16DeadTime Dead time value
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetRisingEdgeDeadTime(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, uint16_t u16DeadTime)
{
pDtm->CHn_DTV[u8Channel] = (pDtm->CHn_DTV[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_DT_RISE_MASK)) | EFTU_DTM_CHn_DTV_DT_RISE(u16DeadTime);
}
/**
* @brief Sets the falling edge dead time
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param u16DeadTime Dead time value
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetFallingEdgeDeadTime(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, uint16_t u16DeadTime)
{
pDtm->CHn_DTV[u8Channel] = (pDtm->CHn_DTV[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_DT_FALL_MASK)) | EFTU_DTM_CHn_DTV_DT_FALL(u16DeadTime);
}
#if defined(HRPWM_INSTANCE_COUNT) && (HRPWM_INSTANCE_COUNT > 0U)
/**
* @brief Sets the HRPWM mode
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param bEnable Whether to enable HRPWM mode, true for enable, false for disable
*/
LOCAL_INLINE void EFTU_DTM_SetHRPWM(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable)
{
pDtm->CHn_DTV[u8Channel] = (pDtm->CHn_DTV[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_HRES_MASK)) | EFTU_DTM_CHn_DTV_HRES(bEnable);
}
#endif
/**
* @brief Sets the output 0 signal level
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param eLevel Signal level, see EFTU_DTM_SignalLevelType definition
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetOutput0SignalLevelShadowShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_SignalLevelType eLevel)
{
u8Channel = (uint8_t)(u8Channel << 1U);
pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_SR_SL0_0_SR_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_SR_SL0_0_SR_SR(eLevel) << u8Channel);
}
/**
* @brief Sets the output 1 signal level
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param eLevel Signal level, see EFTU_DTM_SignalLevelType definition
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetOutput1SignalLevelShadowShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_SignalLevelType eLevel)
{
u8Channel = (uint8_t)(u8Channel << 1U);
pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_SR_SL1_0_SR_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_SR_SL1_0_SR_SR(eLevel) << u8Channel);
}
/**
* @brief Selects the shut-off signal
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param eSignal Shut-off signal selection parameter, see EFTU_DTM_ShutOffSignalType definition
*/
LOCAL_INLINE void EFTU_DTM_HWA_SelectShutOffSignal(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_ShutOffSignalType eSignal)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CTRL2 = (pDtm->CTRL2 & (~(((uint32_t)EFTU_DTM_CTRL2_SHUTOFF_SEL_0_MASK) << u8Channel))) | (EFTU_DTM_CTRL2_SHUTOFF_SEL_0(eSignal) << u8Channel);
}
/**
* @brief Inverts the shut-off signal
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param bInvert Whether to invert the shut-off signal polarity, true for inversion, false for no inversion
*/
LOCAL_INLINE void EFTU_DTM_HWA_InvertShutOffSignal(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bInvert)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CTRL2 = (pDtm->CTRL2 & (~(((uint32_t)EFTU_DTM_CTRL2_SHUTOFF_POL_0_MASK) << u8Channel))) | (EFTU_DTM_CTRL2_SHUTOFF_POL_0(bInvert) << u8Channel);
}
/**
* @brief Sets the update mode of the internal SHUTOFF_SYNC_N signal
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param u8UpdateMode Update mode value
* 00b - Internal signal SHUTOFF_SYNC_0 is cleared; a set is not possible
* 01b - Signal PSU_SHUT_OFF[0] sets internal signal SHUTOFF_SYNC_0;
* internal signal SHUTOFF_SYNC_0 is cleared depending on bit field
* CTRL2[SHUT_OFF_RST_0]
* 10b - Signal PSU_SHUT_OFF[0] sets internal signal SHUTOFF_SYNC_0;
* internal signal SHUTOFF_SYNC_0 is cleared by signal
* DTM_PREV_IN0_REDGE or DTM_PREV_IN0_FEDGE or DTM_IN_REDGE
* of channel 0 or DTM_IN_FEDGE of channel 0 defined by bit field
* CTRL[DTM_SEL]
* 11b - Signal PSU_SHUT_OFF[0] =1 sets internal signal
* SHUTOFF_SYNC_0; signal PSU_SHUT_OFF[0] =0 clears internal signal
* SHUTOFF_SYNC_0
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetShutOffSyncUpdateMode(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, uint8_t u8UpdateMode)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CTRL2 = (pDtm->CTRL2 & (~(((uint32_t)EFTU_DTM_CTRL2_UPD_MODE_0_MASK) << u8Channel))) | (EFTU_DTM_CTRL2_UPD_MODE_0(u8UpdateMode) << u8Channel);
}
/**
* @brief Clear of internal signal SHUTOFF_SYNC_
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
*/
LOCAL_INLINE void EFTU_DTM_HWA_ResetShutOffSync(EFTU_DTM_Type * const pDtm, uint8_t u8Channel)
{
pDtm->CTRL2 |= (EFTU_DTM_CTRL2_WR_EN_0_MASK | EFTU_DTM_CTRL2_SHUT_OFF_RST_0_MASK) << (u8Channel << 3U);
}
/**
* @brief Sets the write enable
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param bEnable Whether to enable write operations, true for enable, false for disable
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetWriteEnable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable)
{
u8Channel = (uint8_t)(u8Channel << 3U);
pDtm->CTRL2 = (pDtm->CTRL2 & (~(((uint32_t)EFTU_DTM_CTRL2_WR_EN_0_MASK) << u8Channel))) | (EFTU_DTM_CTRL2_WR_EN_0(bEnable) << u8Channel);
}
/**
* @brief Sets the CTRL2 register value
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u32Value Value to set for the CTRL2 register
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetCTRL2(EFTU_DTM_Type * const pDtm, uint32_t u32Value)
{
pDtm->CTRL2 = u32Value;
}
/**
* @brief Gets the CTRL2 register value
*
* @param pDtm Base address pointer of the EFTU DTM
* @return The value of the CTRL2 register
*/
LOCAL_INLINE uint32_t EFTU_DTM_HWA_GetCTRL2(EFTU_DTM_Type * const pDtm)
{
return pDtm->CTRL2;
}
/**
* @brief Sets the Shadow value for rising edge dead time
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param u16DeadTime Dead time value
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetRisingEdgeDeadTimeShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, uint16_t u16DeadTime)
{
pDtm->CHn_DTV_SR[u8Channel] = (pDtm->CHn_DTV_SR[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_SR_DT_RISE_SR_MASK)) | EFTU_DTM_CHn_DTV_SR_DT_RISE_SR(u16DeadTime);
}
/**
* @brief Selects the rising dead time trigger
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param eSelect Trigger selection parameter, see EFTU_DTM_DeadTimeTrigSelectType definition
*/
LOCAL_INLINE void EFTU_DTM_HWA_SelectRisingDeadTimeTrigger(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_DeadTimeTrigSelectType eSelect)
{
pDtm->CHn_DTV_SR[u8Channel] = (pDtm->CHn_DTV_SR[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_SR_DT_RISE_UPD_FE0RE1_MASK)) | EFTU_DTM_CHn_DTV_SR_DT_RISE_UPD_FE0RE1(eSelect);
}
/**
* @brief Sets the update rising dead time enable
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param bEnable Whether to enable the update, true for enable, false for disable
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetUpdateRisingDeadTimeEnable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable)
{
pDtm->CHn_DTV_SR[u8Channel] = (pDtm->CHn_DTV_SR[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_SR_DT_RISE_UPD_EN_MASK)) | EFTU_DTM_CHn_DTV_SR_DT_RISE_UPD_EN(bEnable);
}
/**
* @brief Sets the Shadow Value for Falling Edge Dead Time
*
* @param pDtm Base address pointer of the EFTU DTM
* @param u8Channel Channel number
* @param u16DeadTime Dead time value
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetFallingEdgeDeadTimeShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, uint16_t u16DeadTime)
{
pDtm->CHn_DTV_SR[u8Channel] = (pDtm->CHn_DTV_SR[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_SR_DT_FALL_SR_MASK)) | EFTU_DTM_CHn_DTV_SR_DT_FALL_SR(u16DeadTime);
}
/**
* @brief Select the falling edge dead time trigger
*
* @param pDtm Pointer to the base address of the DTM module
* @param u8Channel Channel number
* @param eSelect Trigger selection enum value
*/
LOCAL_INLINE void EFTU_DTM_HWA_SelectFallingDeadTimeTrigger(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_DeadTimeTrigSelectType eSelect)
{
pDtm->CHn_DTV_SR[u8Channel] = (pDtm->CHn_DTV_SR[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_SR_DT_FALL_UPD_FE0RE1_MASK)) | EFTU_DTM_CHn_DTV_SR_DT_FALL_UPD_FE0RE1(eSelect);
}
/**
* @brief Set the update enable for falling edge dead time
*
* @param pDtm Pointer to the base address of the DTM module
* @param u8Channel Channel number
* @param bEnable Boolean value to enable or disable the update
*/
LOCAL_INLINE void EFTU_DTM_HWA_SetUpdateFallingDeadTimeEnable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable)
{
pDtm->CHn_DTV_SR[u8Channel] = (pDtm->CHn_DTV_SR[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_SR_DT_FALL_UPD_EN_MASK)) | EFTU_DTM_CHn_DTV_SR_DT_FALL_UPD_EN(bEnable);
}
/** @}*/
#endif /* EFTU_INSTANCE_COUNT > 0U */
#endif /* _HWA_EFTU_ATM_H_ */

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/**
* @file HwA_eftu_tbu.h
* @author flagchip
* @brief Hardware access layer for EFTU TBU
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip099 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_EFTU_TBU_H_
#define _HWA_EFTU_TBU_H_
#include "device_header.h"
#if EFTU_INSTANCE_COUNT > 0U
/********* Local typedef ************/
/**
* @brief Select the EFTU TBU clock source.
*
*/
typedef enum
{
EFTU_TBU_CMU_CLK0 = 0U,
EFTU_TBU_CMU_CLK1,
EFTU_TBU_CMU_CLK2,
EFTU_TBU_CMU_CLK3,
EFTU_TBU_CMU_CLK4,
EFTU_TBU_CMU_CLK5,
EFTU_TBU_CMU_CLK6,
EFTU_TBU_CMU_CLK7
} EFTU_TBU_ClkSrcType;
/*
*@brief Select the EFTU channel_0 register resolution.
*/
typedef enum
{
EFTU_TBU_CNT0_0_23BIT = 0U,
EFTU_TBU_CNT0_3_26BIT
} EFTU_TBU_Ch0ResType;
/*
*@brief Select the EFTU channel x
*/
typedef enum
{
EFTU_TBU_CNT0 = 0U,
EFTU_TBU_CNT1,
EFTU_TBU_CNT2,
EFTU_TBU_CNT3,
EFTU_TBU_MAX
} EFTU_TBU_ChnCntType;
/*
*@brief Select the EFTU TBU CNT3 QD mode
*/
typedef enum
{
EFTU_TBU_QD_DIR_MODE = 0U,
EFTU_TBU_QD_PHA_MODE,
} EFTU_TBU_QDModeType;
typedef enum
{
EFTU_TBU_INSTANCE = 0U,
} EFTU_TBU_InstanceType;
/*
*@brief Channel selector for modulo counter. Only for channel 3
*/
typedef enum
{
EFTU0_CNT_TIM0_1 = 0U,
EFTU0_CNT_TIM2_3 = 1U,
} EFTU_TBU_QDInputSrcType;
/********* Local inline function ************/
/*
* @brief enable Tbu channel
*/
LOCAL_INLINE void EFTU_TBU_HWA_EnableChannel(EFTU_TBU_Type *const pTbu, EFTU_TBU_ChnCntType eChannel)
{
pTbu->CNTEN = (0x2U << (uint8_t)(eChannel * 2u));
}
/*
* @brief disable Tbu channel
*/
LOCAL_INLINE void EFTU_TBU_HWA_DisableChannel(EFTU_TBU_Type *const pTbu, EFTU_TBU_ChnCntType eChannel)
{
pTbu->CNTEN = (0x1U << (uint8_t)(eChannel * 2u));
}
/**
* @brief select the clock src of the channel 0
* */
LOCAL_INLINE void EFTU_TBU_HWA_SetTs0Src(EFTU_TBU_Type *const pTbu, EFTU_TBU_ClkSrcType eClkSrc)
{
pTbu->CNT0_CTRL |= EFTU_TBU_CNT0_CTRL_CNT_CLK_SRC(eClkSrc);
}
/**
* @brief select the clock src of the channel 0
* */
LOCAL_INLINE void EFTU_TBU_HWA_SetTs1Src(EFTU_TBU_Type *const pTbu, EFTU_TBU_ClkSrcType eClkSrc)
{
pTbu->CNT1_CTRL |= EFTU_TBU_CNT1_CTRL_CNT_CLK_SRC(eClkSrc);
}
/**
* @brief select the clock src of the channel 0
* */
LOCAL_INLINE void EFTU_TBU_HWA_SetTs2Src(EFTU_TBU_Type *const pTbu, EFTU_TBU_ClkSrcType eClkSrc)
{
pTbu->CNT2_CTRL |= EFTU_TBU_CNT2_CTRL_CNT_CLK_SRC(eClkSrc);
}
/**
* @brief select the time base register of the channel 0 provided to the sub module.
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetChannel0BaseReg(EFTU_TBU_Type *const pTbu, EFTU_TBU_Ch0ResType eTbuch0base)
{
pTbu->CNT0_CTRL |= EFTU_TBU_CNT0_CTRL_LOW_RES(eTbuch0base);
}
/**
* @brief get the TBU_TSx.
*/
LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetChannelTS0(const EFTU_TBU_Type *const pTbu)
{
return (uint32_t)(pTbu->CNT0_BASE & EFTU_TBU_CNT0_BASE_BASE_MASK);
}
/**
* @brief get the TBU_TSx.
*/
LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetChannelTS1(const EFTU_TBU_Type *const pTbu)
{
return (uint32_t)(pTbu->CNT1_BASE & EFTU_TBU_CNT1_BASE_BASE_MASK);
}
/**
* @brief get the TBU_TSx.
*/
LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetChannelTS2(const EFTU_TBU_Type *const pTbu)
{
return (uint32_t)(pTbu->CNT2_BASE & EFTU_TBU_CNT2_BASE_BASE_MASK);
}
/**
* @brief get the TBU_TSx.
*/
LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetChannelTS3(const EFTU_TBU_Type *const pTbu)
{
return (uint32_t)(pTbu->CNT3_BASE & EFTU_TBU_CNT3_BASE_BASE_MASK);
}
/**
* @brief Set the TBU_TS0 base
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetChannelTS0(EFTU_TBU_Type *const pTbu, uint32 u32TimeValue)
{
pTbu->CNT0_BASE = (pTbu->CNT0_BASE & ~EFTU_TBU_CNT0_BASE_BASE_MASK)|EFTU_TBU_CNT0_BASE_BASE(u32TimeValue);
}
/**
* @brief Set the TBU_TS1 base
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetChannelTS1(EFTU_TBU_Type *const pTbu, uint32 u32TimeValue)
{
pTbu->CNT1_BASE =(pTbu->CNT1_BASE & ~EFTU_TBU_CNT1_BASE_BASE_MASK) | EFTU_TBU_CNT1_BASE_BASE(u32TimeValue);
}
/**
* @brief Set the TBU_TS2 base
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetChannelTS2(EFTU_TBU_Type *const pTbu, uint32 u32TimeValue)
{
pTbu->CNT2_BASE =(pTbu->CNT2_BASE & ~EFTU_TBU_CNT2_BASE_BASE_MASK)|EFTU_TBU_CNT2_BASE_BASE(u32TimeValue);
}
/**
* @brief Set the TBU_TS3 base
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetChannelTS3(EFTU_TBU_Type *const pTbu, uint32 u32TimeValue)
{
pTbu->CNT3_BASE = (pTbu->CNT3_BASE & ~EFTU_TBU_CNT3_BASE_BASE_MASK)|EFTU_TBU_CNT3_BASE_BASE(u32TimeValue);
}
/**
* @brief configure channel 3 mode
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetChannel3Mode(EFTU_TBU_Type *const pTbu, EFTU_TBU_QDModeType eTbuch3Mode)
{
pTbu->CNT3_CTRL = (pTbu->CNT3_CTRL & ~EFTU_TBU_CNT3_CTRL_CNT_MODE_MASK)|EFTU_TBU_CNT3_CTRL_CNT_MODE(eTbuch3Mode);
}
/**
* @brief configure channel 3 src for modulo counter
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetChannel3Src(EFTU_TBU_Type *const pTbu, EFTU_TBU_QDInputSrcType eTbuch3CounterSrc)
{
pTbu->CNT3_CTRL =(pTbu->CNT3_CTRL & ~EFTU_TBU_CNT3_CTRL_USE_CNT2_MASK)|EFTU_TBU_CNT3_CTRL_USE_CNT2(eTbuch3CounterSrc);
}
/**
* @brief configure channel 3 Modulo value
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetChannel3MARK(EFTU_TBU_Type *const pTbu, uint32 u32mark)
{
pTbu->CNT3_MARK = (pTbu->CNT3_MARK & ~EFTU_TBU_CNT3_MARK_MARK_MASK)|EFTU_TBU_CNT3_MARK_MARK(u32mark);
}
/**
* @brief get channel 3 Modulo value
*/
LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetChannel3MARK(EFTU_TBU_Type *const pTbu)
{
return (uint32_t)pTbu->CNT3_MARK;
}
/**
* @brief get channel 3 capture value
*/
LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetChannel3Capture(EFTU_TBU_Type *const pTbu)
{
return (uint32_t)pTbu->CNT3_CAPTURE;
}
#if (EFTU_EAC_SUPPORT == STD_ON)
/**
* @brief Insert dummy physical tooth for exiting halt mode
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetIph(EFTU_TBU_Type *const pTbu)
{
pTbu->EAC_TPR |= EFTU_TBU_EAC_TPR_IPH_MASK;
}
/**
* @brief Force EAC halt
*/
LOCAL_INLINE void EFTU_TBU_HWA_HoldEac(EFTU_TBU_Type *const pTbu)
{
pTbu->EAC_TPR |= EFTU_TBU_EAC_TPR_HOLD_MASK;
}
/**
* @brief Last Tooth Indication
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetLast(EFTU_TBU_Type *const pTbu)
{
pTbu->EAC_TPR |= EFTU_TBU_EAC_TPR_LAST_MASK;
}
/**
* @brief Angle Ticks Number in the Current Tooth
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetTicks(EFTU_TBU_Type *const pTbu,uint32 u32Ticks)
{
pTbu->EAC_TPR |= EFTU_TBU_EAC_TPR_TICKS(u32Ticks);
}
/**
* @brief Misscnt Tooth Counter
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetMisscnt(EFTU_TBU_Type *const pTbu,uint32 u32MissCnt)
{
pTbu->EAC_TPR |= EFTU_TBU_EAC_TPR_MISSCNT(u32MissCnt);
}
/**
* @brief set EAC TRR value
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetTrr(EFTU_TBU_Type *const pTbu,uint32_t u32TrrValue)
{
pTbu->EAC_TRR = u32TrrValue;
}
/**
* @brief The value of the window start is used to determine the start of the
* window for the next tooth
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetStartWin(EFTU_TBU_Type *const pTbu,uint32_t u32StartWin)
{
pTbu->EAC_WINDOW_S = ((0x1U<<24)|u32StartWin);
}
/**
* @brief The value of the window start is used to determine the End of the
* window for the next tooth
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetEndWin(EFTU_TBU_Type *const pTbu,uint32_t u32EndWin)
{
pTbu->EAC_WINDOW_E = ((0x1U<<24)|u32EndWin);
}
/**
* @brief Set the EAC control register
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetCtrl(EFTU_TBU_Type *const pTbu,uint32_t u32CtrlValue)
{
pTbu->EAC_CTRL = u32CtrlValue;
}
/**
* @brief Clear the counter value to zero
*/
LOCAL_INLINE void EFTU_TBU_HWA_EacSwClearCnt(EFTU_TBU_Type *const pTbu)
{
pTbu->EAC_CTRL |= EFTU_TBU_EAC_CTRL_CNT_SW_CLR_MASK;
}
/**
* @brief EAC is halted until a physical tooth is detected
*/
LOCAL_INLINE void EFTU_TBU_HWA_HaltEac(EFTU_TBU_Type *const pTbu)
{
pTbu->EAC_CTRL |= EFTU_TBU_EAC_CTRL_HALT_ENABLE_MASK;
}
/**
* @brief Get the last measured time
*/
LOCAL_INLINE uint32 EFTU_TBU_HWA_GetLastMeasTime(EFTU_TBU_Type *const pTbu)
{
return (uint32_t)(pTbu->EAC_CNTS & 0xFFFFFF );
}
/**
* @brief Get the last last measured time
*/
LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetCnt(EFTU_TBU_Type *const pTbu)
{
return (uint32_t)(pTbu->EAC_CNT & 0xFFFFFF );
}
/**
* @brief Get the last last measured time
*/
LOCAL_INLINE uint8_t EFTU_TBU_HWA_GetDetectCounter(EFTU_TBU_Type *const pTbu)
{
return (uint8_t)((pTbu->EAC_CNTS & EFTU_TBU_EAC_CNTS_CH_CNTS_MASK) >> EFTU_TBU_EAC_CNTS_CH_CNTS_SHIFT) ;
}
/**
* @brief Set the last last measured time
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetCnts(EFTU_TBU_Type *const pTbu,uint32_t u32CntsValue)
{
pTbu->EAC_CNTS |= EFTU_TBU_EAC_CNTS_CH_CNTS_WE_SHIFT | EFTU_TBU_EAC_CNTS_CNTS(u32CntsValue);
}
/**
* @brief Set the detect counter
*/
LOCAL_INLINE void EFTU_TBU_HWA_SetCntsCounter(EFTU_TBU_Type *const pTbu,uint8_t u8Counter)
{
pTbu->EAC_CNTS |= EFTU_TBU_EAC_CNTS_CH_CNTS(u8Counter);
}
/**
* @brief Enable timeout interrupt
*/
LOCAL_INLINE void EFTU_TBU_HWA_EACEnTimeoutIRQ(EFTU_TBU_Type *const pTbu)
{
pTbu->EAC_IRQEN |= EFTU_TBU_EAC_IRQEN_TOOTH_TO_IEN_MASK;
}
/**
* @brief Enable error interrupt
*/
LOCAL_INLINE void EFTU_TBU_HWA_EACEnErrIRQ(EFTU_TBU_Type *const pTbu)
{
pTbu->EAC_IRQEN |= EFTU_TBU_EAC_IRQEN_TOOTH_ERR_IEN_MASK;
}
/**
* @brief Enable detect interrupt
*/
LOCAL_INLINE void EFTU_TBU_HWA_EACEnDetIRQ(EFTU_TBU_Type *const pTbu)
{
pTbu->EAC_IRQEN |= EFTU_TBU_EAC_STAT_TOOTH_DET_MASK;
}
/**
* @brief Disable timeout interrupt
*/
LOCAL_INLINE void EFTU_TBU_HWA_EACDisTimeoutIRQ(EFTU_TBU_Type *const pTbu)
{
pTbu->EAC_IRQEN &= ~EFTU_TBU_EAC_IRQEN_TOOTH_TO_IEN_MASK;
}
/**
* @brief Disable error interrupt
*/
LOCAL_INLINE void EFTU_TBU_HWA_EACDisErrIRQ(EFTU_TBU_Type *const pTbu)
{
pTbu->EAC_IRQEN &= ~EFTU_TBU_EAC_IRQEN_TOOTH_ERR_IEN_MASK;
}
/**
* @brief Disable detect interrupt
*/
LOCAL_INLINE void EFTU_TBU_HWA_EACDisDetIRQ(EFTU_TBU_Type *const pTbu)
{
pTbu->EAC_IRQEN &= ~EFTU_TBU_EAC_STAT_TOOTH_DET_MASK;
}
/**
* @brief get interrupt status
*/
LOCAL_INLINE uint32_t EFTU_TBU_HWA_EacGetIrqflag(EFTU_TBU_Type *const pTbu)
{
return (uint32_t)pTbu->EAC_STAT;
}
/**
* @brief get interrupt status
*/
LOCAL_INLINE void EFTU_TBU_HWA_EacClearIrqflag(EFTU_TBU_Type *const pTbu,uint32_t u32Mask)
{
pTbu->EAC_STAT = u32Mask;
}
#endif /* EFTU_EAC_SUPPORT */
#endif /* EFTU_INSTANCE_COUNT*/
#endif /*#ifndef _HWA_EFTU_TBU_H_*/

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/**
* @file HwA_eftu_tim.h
* @author flagchip
* @brief Hardware access layer for EFTU TIM
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip099 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_EFTU_TIM_H_
#define _HWA_EFTU_TIM_H_
#include "device_header.h"
#if EFTU_INSTANCE_COUNT > 0U
/********* Local typedef ************/
/**
* @get Tim Filter counter Frequency Selection.
*/
typedef enum
{
EFTU_TIM_FLT_CMUCLK0 = 0U,
EFTU_TIM_FLT_CMUCLK1 = 1U,
EFTU_TIM_FLT_CMUCLK6 = 2U,
EFTU_TIM_FLT_CMUCLK7 = 3U
}EFTU_TIM_FltSrcType;
typedef enum
{
EFTU_TIM_CMU_CLK0 = 0U,
EFTU_TIM_CMU_CLK1 = 1U,
EFTU_TIM_CMU_CLK2 = 2U,
EFTU_TIM_CMU_CLK3 = 3U,
EFTU_TIM_CMU_CLK4 = 4U,
EFTU_TIM_CMU_CLK5 = 5U,
EFTU_TIM_CMU_CLK6 = 6U,
EFTU_TIM_CMU_CLK7 = 7U,
}EFTU_TIM_ClockSrcType;
/*Tim Input Timeout EDGE*/
typedef enum
{
EFTU_TIM_TIMEOUT_DIS = 0U,
EFTU_TIM_TIMEOUT_RISING_EDGE = 1U,
EFTU_TIM_TIMEOUT_FALLING_EDGE = 2U,
EFTU_TIM_TIMEOUT_BOTH_EDGE = 3U,
}EFTU_TIM_TimeOutEdgeType;
typedef enum
{
EFTU_TO_CNT2_CLOCK_CMU_CLK = 0U,
EFTU_TO_CNT_CLOCK_SAMPLE_EVT = 1U,
}EFTU_TIM_TduCnt2ClkType;
typedef enum
{
EFTU_TO_CNT1_CLOCK_WORD_EVENT = 0U,
EFTU_TO_CNT1_CLOCK_TO_CNT = 1U,
}EFTU_TIM_TduCnt1ClkType;
typedef enum
{
EFTU_TDU_24BIT_OR_RESERVED = 0U,
EFTU_TDU_16BIT_8BIT_OR_16BIT = 1U,
EFTU_TDU_3_8BIT_OR_2_8BIT = 2U,
EFTU_TDU_2_8BIT_OR_2_8BIT = 3U
}EFTU_TIM_TduSlicType;
/**
*@brief TBU0_TS0 select bit
*/
typedef enum
{
EFTU_TIM_TBU_TS0_0_23BIT = 0U,
EFTU_TIM_TBU_TS0_3_26BIT = 1U
}EFTU_TIM_TbuTs0ResType;
typedef enum
{
EFTU_TIM_ACTIVE_FALLINGEDGE = 0U,
EFTU_TIM_ACTIVE_RISINGEDGE = 1U,
EFTU_TIM_ACTIVE_BOTHEDGE = 2U,/*just for TIEM TIPM mode*/
}EFTU_TIM_ActiveEdgeType;
/**
* @get Tim tdu counter timeout sensitive edge.
*/
typedef enum
{
EFTU_TIM_TDU_DISABLE = 0U,
EFTU_TIM_TDU_RISING_EDGE = 1U,
EFTU_TIM_TDU_FALLING_EDGE = 2U,
EFTU_TIM_TDU_BOTH_EDGE = 3U
}EFTU_TIM_TduEdgeType;
/**
* @brief Tim Channel Mode
*/
typedef enum
{
EFTU_TIM_MODE_PWMMEASUREMENT = 0U, /**< \brief TPWM */
EFTU_TIM_MODE_PULSEINTEGRATION = 1U, /**< \brief TPIM */
EFTU_TIM_MODE_INPUTEVENT = 2U, /**< \brief TIEM */
EFTU_TIM_MODE_PRESCALER = 3U, /**< \brief TIPM */
EFTU_TIM_MODE_BITCOMPRESSION = 4U, /**< \brief TBCM */
EFTU_TIM_MODE_PERIODICSAMPLING = 5U, /**< \brief TGPS */
EFTU_TIM_MODE_SERIALSHIFT = 6U /**< \brief TSSM */
}EFTU_TiM_ChannelModeType;
/**
* @brief GPR0 select mux
*/
typedef enum
{
EFTU_TIM_GPTSEL_TBUTS0 = 0U,
EFTU_TIM_GPTSEL_TBUTS1 = 1U,
EFTU_TIM_GPTSEL_TBUTS2 = 2U,
EFTU_TIM_GPTSEL_CNTS_OR_CNT = 3U, /*For GPR0 CNTS;For GPR1 CNT*/
EFTU_GPTSEL_CH_ECNT = 4U,
EFTU_GPTSEL_TIM_INP_VAL = 5U,
}EFTU_TIM_GprSrcType;
typedef enum
{
EFTU_TIM_CNTS_CNT = 0U,
EFTU_TIM_CNTS_TBUTS0 = 1u
}EFTU_TIM_CntsSrcType;
typedef enum
{
EFTU_TIM_TPWM_CNTRESET_ACTIVE_EDGE = 0U,
EFTU_TIM_TPWM_CNTRESET_EVERY_EDGE = 1U,
}EFTU_TIM_TpwmCntResType;
typedef enum
{
EFTU_TIM_IRQ_NEWVAL = 0X01U, /**< \brief new value irq mode */
EFTU_TIM_IRQ_ECNTOFL = 0X02U,
EFTU_TIM_IRQ_CNTOFL = 0X04U,
EFTU_TIM_IRQ_GPR0OFL = 0X08U,
EFTU_TIM_IRQ_TODET = 0X10U, /**< \brief Timeout irq mode */
EFTU_TIM_IRQ_GLITCHDET = 0X20U,
}EFTU_TIM_IrqSrcType;
typedef enum
{
EFTU_TIM_LUT_DISABLE = 0u,
EFTU_TIM_LUT_EXT_CAPTURE = 1u,
EFTU_TIM_LUT_FOUT_PREV = 2u,
EFTU_TIM_LUT_TSSM_OUT = 3u,
}EFTU_TIM_LutType;
/********* Local inline function ************/
LOCAL_INLINE void EFTU_TIM_HWA_EnIrq( EFTU_TIM_Type *const pTim,EFTU_TIM_IrqSrcType eirq ,uint8_t u8channel)
{
if(EFTU_TIM_IRQ_NEWVAL == eirq )
{
pTim->CONTROL[u8channel].CH_IRQ_EN |= EFTU_TIM_CHn_IRQ_EN_NEWVAL_IRQ_EN_MASK;
}
else if (EFTU_TIM_IRQ_ECNTOFL == eirq )
{
pTim->CONTROL[u8channel].CH_IRQ_EN |= EFTU_TIM_CHn_IRQ_EN_ECNTOFL_IRQ_EN_MASK;
}
else if (EFTU_TIM_IRQ_CNTOFL == eirq )
{
pTim->CONTROL[u8channel].CH_IRQ_EN |= EFTU_TIM_CHn_IRQ_EN_CNTOFL_IRQ_EN_MASK;
}
else if (EFTU_TIM_IRQ_GPR0OFL == eirq)
{
pTim->CONTROL[u8channel].CH_IRQ_EN |= EFTU_TIM_CHn_IRQ_EN_GPROFL_IRQ_EN_MASK;
}
else if (EFTU_TIM_IRQ_TODET == eirq)
{
pTim->CONTROL[u8channel].CH_IRQ_EN |= EFTU_TIM_CHn_IRQ_EN_TODET_IRQ_EN_MASK;
}
else if (EFTU_TIM_IRQ_GLITCHDET == eirq )
{
pTim->CONTROL[u8channel].CH_IRQ_EN |=EFTU_TIM_CHn_IRQ_EN_GLITCHDET_IRQ_EN_MASK;
}
else
{
}
}
LOCAL_INLINE void EFTU_TIM_HWA_DisIrq( EFTU_TIM_Type *const pTim,EFTU_TIM_IrqSrcType eirq ,uint8_t u8channel)
{
if(EFTU_TIM_IRQ_NEWVAL == eirq )
{
pTim->CONTROL[u8channel].CH_IRQ_EN &= ~EFTU_TIM_CHn_IRQ_EN_NEWVAL_IRQ_EN_MASK;
}
else if (EFTU_TIM_IRQ_ECNTOFL == eirq )
{
pTim->CONTROL[u8channel].CH_IRQ_EN &= ~EFTU_TIM_CHn_IRQ_EN_ECNTOFL_IRQ_EN_MASK;
}
else if (EFTU_TIM_IRQ_CNTOFL == eirq )
{
pTim->CONTROL[u8channel].CH_IRQ_EN &= ~EFTU_TIM_CHn_IRQ_EN_CNTOFL_IRQ_EN_MASK;
}
else if (EFTU_TIM_IRQ_GPR0OFL == eirq)
{
pTim->CONTROL[u8channel].CH_IRQ_EN &= ~EFTU_TIM_CHn_IRQ_EN_GPROFL_IRQ_EN_MASK;
}
else if (EFTU_TIM_IRQ_TODET == eirq)
{
pTim->CONTROL[u8channel].CH_IRQ_EN &= ~EFTU_TIM_CHn_IRQ_EN_TODET_IRQ_EN_MASK;
}
else if (EFTU_TIM_IRQ_GLITCHDET == eirq )
{
pTim->CONTROL[u8channel].CH_IRQ_EN &= ~EFTU_TIM_CHn_IRQ_EN_GLITCHDET_IRQ_EN_MASK;
}
else
{
}
}
LOCAL_INLINE boolean EFTU_TIM_HWA_GetGlitchEvent(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (pTim->CONTROL[u8channel].CH_IRQ_ST & EFTU_TIM_CHn_IRQ_ST_GLITCHDET_MASK) !=0U;
}
LOCAL_INLINE boolean EFTU_TIM_HWA_GetTimeOutEvent(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (pTim->CONTROL[u8channel].CH_IRQ_ST & EFTU_TIM_CHn_IRQ_ST_TODET_MASK) !=0U;
}
LOCAL_INLINE boolean EFTU_TIM_HWA_GetGprOverflowEvent(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (pTim->CONTROL[u8channel].CH_IRQ_ST & EFTU_TIM_CHn_IRQ_ST_GPROFL_MASK) !=0U;
}
LOCAL_INLINE boolean EFTU_TIM_HWA_GetCntOverflowEvent(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (pTim->CONTROL[u8channel].CH_IRQ_ST & EFTU_TIM_CHn_IRQ_ST_CNTOFL_MASK) !=0U;
}
LOCAL_INLINE boolean EFTU_TIM_HWA_GetNewValEvent(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (pTim->CONTROL[u8channel].CH_IRQ_ST & EFTU_TIM_CHn_IRQ_ST_NEWVAL_MASK) !=0U;
}
LOCAL_INLINE boolean EFTU_TIM_HWA_GetEcntEvent(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (pTim->CONTROL[u8channel].CH_IRQ_ST & EFTU_TIM_CHn_IRQ_ST_ECNTOFL_MASK) !=0U;
}
LOCAL_INLINE boolean EFTU_TIM_HWA_GetGlitchIrqEnable(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (pTim->CONTROL[u8channel].CH_IRQ_EN & EFTU_TIM_CHn_IRQ_EN_GLITCHDET_IRQ_EN_MASK) !=0U;
}
LOCAL_INLINE boolean EFTU_TIM_HWA_GetTimeOutIrqEnable(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (pTim->CONTROL[u8channel].CH_IRQ_EN & EFTU_TIM_CHn_IRQ_EN_TODET_IRQ_EN_MASK) !=0U;
}
LOCAL_INLINE boolean EFTU_TIM_HWA_GetGprOverflowIrqEnable(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (pTim->CONTROL[u8channel].CH_IRQ_EN & EFTU_TIM_CHn_IRQ_EN_GPROFL_IRQ_EN_MASK) !=0U;
}
LOCAL_INLINE boolean EFTU_TIM_HWA_GetCntOverflowIrqEnable(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (pTim->CONTROL[u8channel].CH_IRQ_EN & EFTU_TIM_CHn_IRQ_EN_CNTOFL_IRQ_EN_MASK) !=0U;
}
LOCAL_INLINE boolean EFTU_TIM_HWA_GetNewValIrqEnable(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (pTim->CONTROL[u8channel].CH_IRQ_EN & EFTU_TIM_CHn_IRQ_EN_NEWVAL_IRQ_EN_MASK) !=0U;
}
LOCAL_INLINE boolean EFTU_TIM_HWA_GetEcntIrqEnable(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (pTim->CONTROL[u8channel].CH_IRQ_EN & EFTU_TIM_CHn_IRQ_EN_ECNTOFL_IRQ_EN_MASK) !=0U;
}
LOCAL_INLINE void EFTU_TIM_HWA_ClearGlitchFlag( EFTU_TIM_Type * pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_IRQ_ST = EFTU_TIM_CHn_IRQ_ST_GLITCHDET_MASK;
}
LOCAL_INLINE void EFTU_TIM_HWA_ClearTimeOutFlag( EFTU_TIM_Type * pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_IRQ_ST = EFTU_TIM_CHn_IRQ_ST_TODET_MASK;
}
LOCAL_INLINE void EFTU_TIM_HWA_ClearGprOverflowFlag( EFTU_TIM_Type * pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_IRQ_ST = EFTU_TIM_CHn_IRQ_ST_GPROFL_MASK;
}
LOCAL_INLINE void EFTU_TIM_HWA_ClearCntOverflowFlag( EFTU_TIM_Type * pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_IRQ_ST = EFTU_TIM_CHn_IRQ_ST_CNTOFL_MASK;
}
LOCAL_INLINE void EFTU_TIM_HWA_ClearNewValFlag( EFTU_TIM_Type * pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_IRQ_ST = EFTU_TIM_CHn_IRQ_ST_NEWVAL_MASK;
}
LOCAL_INLINE void EFTU_TIM_HWA_ClearEcntFlag( EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_IRQ_ST = EFTU_TIM_CHn_IRQ_ST_ECNTOFL_MASK;
}
/**
* @get Tim channel x GPR0 value
*/
LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetChGPR0(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (uint32_t)(pTim->CONTROL[u8channel].CH_GPR0 & EFTU_TIM_CHn_GPR0_GPR0_MASK);
}
/**
* @get Tim channel x GPR0 Ecnt value
*/
LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetChGPR0Ecnt(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (uint32_t)((pTim->CONTROL[u8channel].CH_GPR0 & EFTU_TIM_CHn_GPR0_ECNT_MASK)>>EFTU_TIM_CHn_GPR0_ECNT_SHIFT);
}
/**
* @get Tim channel x GPR1 value
*/
LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetChGPR1(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (uint32_t)(pTim->CONTROL[u8channel].CH_GPR1 & EFTU_TIM_CHn_GPR1_GPR1_MASK);
}
/**
* @get Tim channel x Counter value
*/
LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetChCnt(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (uint32_t)(pTim->CONTROL[u8channel].CH_CNT & EFTU_TIM_CHn_CNT_CNT_MASK);
}
/**
* @get Tim channel0 Shadow Counter value
*/
LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetCntsCnt(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (uint32_t)(pTim->CONTROL[u8channel].CH_CNTS & EFTU_TIM_CHn_CNTS_CNTS_MASK);
}
/**
* @get Tim channel0 edge counter value
*/
LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetChECnt(const EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
return (uint32_t)(pTim->CONTROL[u8channel].CH_ECNT & EFTU_TIM_CHn_ECNT_ECNT_MASK);
}
/*******************FLT relate register *****************/
/**
* @get Set Value to be fed to Channel x
*/
LOCAL_INLINE void EFTU_TIM_HWA_SetVal(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
uint8_t u8shift = (uint8_t)(u8channel *4U);
pTim->IN_SRC = (uint32_t)(0x2<<u8shift);
}
/**
* @get clear Value to be fed to Channel x
*/
LOCAL_INLINE void EFTU_TIM_HWA_ClearVal(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
uint8_t u8shift = (uint8_t)(u8channel *4U);
pTim->IN_SRC =(uint32_t) (0x1<<u8shift);
}
/**
* @get Set channel AUX IN Source.
*/
LOCAL_INLINE void EFTU_TIM_HWA_SetAuxMode(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
uint8_t u8shift = (uint8_t)(u8channel *4U);
pTim->IN_SRC = (uint32_t)(0x8<<u8shift);
}
/**
* @get clear channel AUX IN Source.
*/
LOCAL_INLINE void EFTU_TIM_HWA_ClearAuxMode(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
uint8_t u8shift = (uint8_t)(u8channel *4U);
pTim->IN_SRC = (uint32_t)(0x4<<u8shift);
}
/**
* @brief CICTRL Channel Input Control Use signal TIM_IN(x-1) as input for channel x (or TIM_IN(m-1) if x is 0)
*
*
*/
LOCAL_INLINE void EFTU_TIM_HWA_SetchCicrl(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_CICTRL_MASK;
}
LOCAL_INLINE void EFTU_TIM_HWA_ClearchCicrl(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_CICTRL_MASK;
}
/**
* @brief config source for triggering the EXT_CAPTURE functionality
*/
LOCAL_INLINE void EFTU_TIM_HWA_ConfigchExtCapSrc(EFTU_TIM_Type *const pTim,uint8_t u8src,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_ECTRL =(pTim->CONTROL[u8channel].CH_ECTRL & ~EFTU_TIM_CHn_ECTRL_EXT_CAP_SRC_MASK) | EFTU_TIM_CHn_ECTRL_EXT_CAP_SRC(u8src);
}
LOCAL_INLINE void EFTU_TIM_HWA_ConfigLut( EFTU_TIM_Type *const pTim,EFTU_TIM_LutType elut ,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_ECTRL =(pTim->CONTROL[u8channel].CH_ECTRL & ~EFTU_TIM_CHn_ECTRL_USE_LUT_MASK)|EFTU_TIM_CHn_ECTRL_USE_LUT(elut);
}
/**
* @brief set Filter counter Src
*/
LOCAL_INLINE void EFTU_TIM_HWA_SetChFltSrc( EFTU_TIM_Type *const pTim, EFTU_TIM_FltSrcType eFltClkSrc,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL =(pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_FLT_CNT_FRQ_MASK) | EFTU_TIM_CHn_CTRL_FLT_CNT_FRQ(eFltClkSrc);
}
/**
* @brief set channel rising edge number
*/
LOCAL_INLINE void EFTU_TIM_HWA_SetChFltReValue( EFTU_TIM_Type *const pTim, uint8_t u8Recount,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_FLT_RE = u8Recount;
}
/**
* @brief set channel fall edge number
*/
LOCAL_INLINE void EFTU_TIM_HWA_SetChFltFeValue( EFTU_TIM_Type *const pTim, uint8_t u8Fecount,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_FLT_FE = u8Fecount;
}
/**
* @brief Enable the Filter mode for rising edge
*/
LOCAL_INLINE void EFTU_TIM_HWA_EnableChFltRe(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_FLT_MODE_RE_MASK;
}
/**
* @brief Disable the Filter mode for rising edge
*/
LOCAL_INLINE void EFTU_TIM_HWA_DisableChFltRe(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_FLT_MODE_RE_MASK;
}
/**
* @brief Enable the Filter mode for falling edge
*/
LOCAL_INLINE void EFTU_TIM_HWA_EnableChFltFe(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_FLT_MODE_FE_MASK;
}
/**
* @brief Disable the Filter mode for falling edge
*/
LOCAL_INLINE void EFTU_TIM_HWA_DisableChFltFe(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_FLT_MODE_FE_MASK;
}
/**
* @brief Enable the Filter counter mode for rising edge
*/
LOCAL_INLINE void EFTU_TIM_HWA_EnableChFltReCounter(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_FLT_CTR_RE_MASK;
}
/**
* @brief Disable the Filter mode for rising edge
*/
LOCAL_INLINE void EFTU_TIM_HWA_DisableChFltReCounter(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_FLT_CTR_RE_MASK;
}
/**
* @brief Enable the Filter counter mode for falling edge
*/
LOCAL_INLINE void EFTU_TIM_HWA_EnableChFltFeCounter(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_FLT_CTR_FE_MASK;
}
/**
* @brief Disable the Filter mode for falling edge
*/
LOCAL_INLINE void EFTU_TIM_HWA_DisableChFltFeCounter(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_FLT_CTR_FE_MASK;
}
/**
* @brief set extension of bit field FLT_CTR_RE
*/
LOCAL_INLINE void EFTU_TIM_HWA_EnableChFltReExbit(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_ECTRL |=EFTU_TIM_CHn_ECTRL_EFLT_CTR_RE_MASK;
}
/**
* @brief Disable extension of bit field FLT_CTR_RE
*/
LOCAL_INLINE void EFTU_TIM_HWA_DisableChFltReExbit(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_ECTRL &= ~EFTU_TIM_CHn_ECTRL_EFLT_CTR_RE_MASK;
}
/**
* @brief set extension of bit field FLT_CTR_FE
*/
LOCAL_INLINE void EFTU_TIM_HWA_EnableChFltFeExbit(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_ECTRL |=EFTU_TIM_CHn_ECTRL_EFLT_CTR_FE_MASK;
}
/**
* @brief Disable extension of bit field FLT_CTR_FE
*/
LOCAL_INLINE void EFTU_TIM_HWA_DisableChFltFeExbit(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_ECTRL &= ~EFTU_TIM_CHn_ECTRL_EFLT_CTR_FE_MASK;
}
LOCAL_INLINE void EFTU_TIM_HWA_EnableFlt(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_FLT_EN_MASK;
}
LOCAL_INLINE void EFTU_TIM_HWA_DisableFlt(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_FLT_EN_MASK;
}
/******************* End FLT relate register *****************/
/*but ECTRL related register has been changed*/
/******************* TDU relate register *****************/
/**
* @brief config Tov0 value.
*/
LOCAL_INLINE void EFTU_TOM_HWA_SetTduTov(EFTU_TIM_Type *const pTim,uint8_t u8Tov0Value, uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_EGV = (pTim->CONTROL[u8channel].CH_EGV & ~EFTU_TIM_CHn_EGV_TOV_MASK)|EFTU_TIM_CHn_EGV_TOV(u8Tov0Value);
}
/**
* @brief config Tov1 value.
*/
LOCAL_INLINE void EFTU_TOM_HWA_SetTduTov1(EFTU_TIM_Type *const pTim,uint8_t u8Tov1Value, uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_EGV = (pTim->CONTROL[u8channel].CH_EGV & ~EFTU_TIM_CHn_EGV_TOV1_MASK)|EFTU_TIM_CHn_EGV_TOV1(u8Tov1Value);
}
/**
* @brief config Tov2 value.
*/
LOCAL_INLINE void EFTU_TOM_HWA_SetTduTov2(EFTU_TIM_Type *const pTim,uint8_t u8Tov2Value, uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_EGV = (pTim->CONTROL[u8channel].CH_EGV & ~EFTU_TIM_CHn_EGV_TOV2_MASK)|EFTU_TIM_CHn_EGV_TOV2(u8Tov2Value);
}
LOCAL_INLINE void EFTU_TOM_HWA_SetimeoutValue(EFTU_TIM_Type *const pTim,uint32_t u32TimeoutValue, uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_EGV = (pTim->CONTROL[u8channel].CH_EGV & 0XFF000000)|(u32TimeoutValue & 0xFFFFFF);
}
/*
* @brief Config Tdu Clock
* */
LOCAL_INLINE void EFTU_TIM_HWA_SetTduClk(EFTU_TIM_Type *const pTim,EFTU_TIM_ClockSrcType eClk,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_EGV =(pTim->CONTROL[u8channel].CH_EGV & ~EFTU_TIM_CHn_EGV_TCS_MASK)|EFTU_TIM_CHn_EGV_TCS(eClk);
}
LOCAL_INLINE void EFTU_TIM_HWA_SetTimeoutEdge(EFTU_TIM_Type *const pTim,EFTU_TIM_TimeOutEdgeType pTimeOutSensitiveEgde, uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL =(pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_TOCTRL_MASK)| EFTU_TIM_CHn_CTRL_TOCTRL(pTimeOutSensitiveEgde);
}
LOCAL_INLINE void EFTU_TIM_HWA_ConfigTduCnt2Clk(EFTU_TIM_Type *const pTim,EFTU_TIM_TduCnt2ClkType eClk,uint8_t u8channel)
{
if(EFTU_TO_CNT2_CLOCK_CMU_CLK == eClk)
{
pTim->CONTROL[u8channel].CH_EGV &= ~EFTU_TIM_CHn_EGV_TCS_USE_SAMPLE_EVT_MASK;
}
else
{
pTim->CONTROL[u8channel].CH_EGV |= EFTU_TIM_CHn_EGV_TCS_USE_SAMPLE_EVT_MASK;
}
}
LOCAL_INLINE void EFTU_TIM_HWA_ConfigTduCnt1Clk(EFTU_TIM_Type *const pTim,EFTU_TIM_TduCnt1ClkType eClk,uint8_t u8channel)
{
if(EFTU_TO_CNT1_CLOCK_WORD_EVENT == eClk)
{
pTim->CONTROL[u8channel].CH_EGV &= ~EFTU_TIM_CHn_EGV_EG_SAME_CNT_CLK_MASK;
}
else
{
pTim->CONTROL[u8channel].CH_EGV |= EFTU_TIM_CHn_EGV_EG_SAME_CNT_CLK_MASK;
}
}
/**
* @brief confg tdu slic mode
*/
LOCAL_INLINE void EFTU_TIM_HWA_SetTduSlicing(EFTU_TIM_Type *const pTim,EFTU_TIM_TduSlicType eSlic,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_EGV = (pTim->CONTROL[u8channel].CH_EGV & ~EFTU_TIM_CHn_EGV_SLICING_MASK)| EFTU_TIM_CHn_EGV_SLICING(eSlic);
}
/******************* End TDU relate register *****************/
/**********channel related register*************/
LOCAL_INLINE void EFTU_TIM_HWA_SetChannelMode(EFTU_TIM_Type *const pTim,EFTU_TiM_ChannelModeType pTimMode,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL = (pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_TIM_MODE_MASK)|EFTU_TIM_CHn_CTRL_TIM_MODE(pTimMode);
}
LOCAL_INLINE void EFTU_TIM_HWA_SetChannelClockSrc(EFTU_TIM_Type *const pTim,EFTU_TIM_ClockSrcType pTimSrc,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL = (pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_CLK_SEL_MASK) | EFTU_TIM_CHn_CTRL_CLK_SEL(pTimSrc);
}
LOCAL_INLINE void EFTU_TIM_HWA_EnableChannel(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_TIM_EN_MASK;
}
LOCAL_INLINE void EFTU_TIM_HWA_DisableChannel(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_TIM_EN_MASK;
}
LOCAL_INLINE void EFTU_TIM_HWA_SetGPR0Sel(EFTU_TIM_Type *const pTim,EFTU_TIM_GprSrcType pTimGprser,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL = (pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_GPR0_SEL_MASK)|EFTU_TIM_CHn_CTRL_GPR0_SEL(pTimGprser);
}
LOCAL_INLINE void EFTU_TIM_HWA_SetGPR1Sel(EFTU_TIM_Type *const pTim,EFTU_TIM_GprSrcType pTimGprsel,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL = (pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_GPR1_SEL_MASK) | EFTU_TIM_CHn_CTRL_GPR1_SEL(pTimGprsel);
}
LOCAL_INLINE void EFTU_TIM_HWA_SetCntsSel(EFTU_TIM_Type *const pTim,EFTU_TIM_CntsSrcType pTimCntssel,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL = (pTim->CONTROL[u8channel].CH_CTRL & ~ EFTU_TIM_CHn_CTRL_CNTS_SEL_MASK)|EFTU_TIM_CHn_CTRL_CNTS_SEL(pTimCntssel);
}
LOCAL_INLINE void EFTU_TIM_HWA_SetTbu0BitFiled(EFTU_TIM_Type *const pTim,EFTU_TIM_TbuTs0ResType eTbu0Ts0,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CTRL =(pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_TBU0_SEL_MASK) | EFTU_TIM_CHn_CTRL_TBU0_SEL(eTbu0Ts0);
}
LOCAL_INLINE void EFTU_TIM_HWA_EnableExtCapture(EFTU_TIM_Type *const pTim,boolean bEn,uint8_t u8channel)
{
if(TRUE == bEn)
{
pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_EXT_CAP_EN_MASK;
}
else
{
pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_EXT_CAP_EN_MASK;
}
}
LOCAL_INLINE void EFTU_TIM_HWA_EnableSwCaputure(EFTU_TIM_Type *const pTim,boolean bEn,uint8_t u8channel)
{
if(TRUE == bEn)
{
pTim->CONTROL[u8channel].CH_ECTRL |= EFTU_TIM_CHn_ECTRL_SWAP_CAPTURE_MASK;
}
else
{
pTim->CONTROL[u8channel].CH_ECTRL &= ~EFTU_TIM_CHn_ECTRL_SWAP_CAPTURE_MASK;
}
}
LOCAL_INLINE void EFTU_TIM_HWA_ConfigActiveEdge(EFTU_TIM_Type *const pTim,EFTU_TIM_ActiveEdgeType eEdge ,uint8_t u8channel)
{
if(EFTU_TIM_ACTIVE_RISINGEDGE== eEdge)
{
pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_DSL_MASK;
}
else
{
pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_DSL_MASK;
}
}
LOCAL_INLINE void EFTU_TIM_HWA_ConfigTpwmCntmode(EFTU_TIM_Type *const pTim,EFTU_TIM_TpwmCntResType eResType ,uint8_t u8channel)
{
if(EFTU_TIM_TPWM_CNTRESET_EVERY_EDGE == eResType)
{
pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_ECNT_RESET_MASK;
}
else
{
pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_ECNT_RESET_MASK;
}
}
LOCAL_INLINE void EFTU_TIM_HWA_EnIngnoreEdge(EFTU_TIM_Type *const pTim,boolean bEn,uint8_t u8channel)
{
if(TRUE == bEn)
{
pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_ISL_MASK;
}
else
{
pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_ISL_MASK;
}
}
LOCAL_INLINE void EFTU_TIM_HWA_EnableImmStart(EFTU_TIM_Type *const pTim,boolean bEnable,uint8_t u8channel)
{
if(TRUE == bEnable)
{
pTim->CONTROL[u8channel].CH_ECTRL |=EFTU_TIM_CHn_ECTRL_IMM_START_MASK;
}
else
{
pTim->CONTROL[u8channel].CH_ECTRL &= ~EFTU_TIM_CHn_ECTRL_IMM_START_MASK;
}
}
LOCAL_INLINE void EFTU_TIM_HWA_SetCntsValue(EFTU_TIM_Type *const pTim,uint32 value,uint8_t u8channel)
{
pTim->CONTROL[u8channel].CH_CNTS = value;
}
LOCAL_INLINE void EFTU_TIM_HWA_TssmEnshiftRight(EFTU_TIM_Type *const pTim,boolean bShiftRight ,uint8_t u8channel)
{
if(TRUE== bShiftRight)
{
pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_DSL_MASK;
}
else
{
pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_DSL_MASK;
}
}
LOCAL_INLINE void EFTU_TIM_HWA_UnLock(EFTU_TIM_Type *const pTim)
{
pTim->TIM_SPEC_LOCK = 0xBEEFCAFE;
}
LOCAL_INLINE void EFTU_TIM_HWA_Lock(EFTU_TIM_Type *const pTim)
{
pTim->TIM_SPEC_LOCK = 0x5AFECAFE;
}
LOCAL_INLINE void EFTU_TIM_HWA_ResetChannel(EFTU_TIM_Type *const pTim,uint8_t u8channel)
{
pTim->RST |= 0x1U<<u8channel;
}
LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetInputLevel(EFTU_TIM_Type *const pTim)
{
return (uint32_t)(pTim->INP_VAL);
}
#endif
#endif /*#ifndef _HWA_EFTU_TIM_H_*/

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/**
* @file HwA_eim.h
* @author Flagchip0100
* @brief EIM Module Register API
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright 2020-2024 Flagchip Semiconductors Co., Ltd.
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip052 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip100 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_EIM_H_
#define _HWA_EIM_H_
#include "device_header.h"
#if (EIM_INSTANCE_COUNT > 0U)
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @defgroup HwA_eim HwA_eim
* @ingroup module_driver_eim
* @{
*/
/*******************************************************************************
* Local inline function
******************************************************************************/
/**
* @brief Enable EIM Global Error Injection.
*
* @param pEim EIM Instance.
*/
LOCAL_INLINE void EIM_HWA_EnableGlobalErrorInjection(EIM_Type *const pEim)
{
pEim->CR = EIM_CR_GEIEN(1U);
}
/**
* @brief Disable EIM Global Error Injection.
*
* @param pEim EIM Instance.
*/
LOCAL_INLINE void EIM_HWA_DisableGlobalErrorInjection(EIM_Type *const pEim)
{
pEim->CR = EIM_CR_GEIEN(0U);
}
/**
* @brief Get EIM channel N control register value.
*
* @param pEim EIM Instance.
* @param u8Idx Control register index.
* @return EIM channel N control register value.
*/
LOCAL_INLINE uint32_t EIM_HWA_GetCtrlRegn(const EIM_Type *const pEim, uint8_t u8Idx)
{
return pEim->CTRL_REG[u8Idx];
}
/**
* @brief Set EIM channel N control register value.
*
* @param pEim EIM Instance.
* @param u8Idx Control register index.
* @param u32Value Register value.
*/
LOCAL_INLINE void EIM_HWA_SetCtrlRegn(EIM_Type *const pEim, uint8_t u8Idx, uint32_t u32Value)
{
pEim->CTRL_REG[u8Idx] = u32Value;
}
/**
* @brief Get EIM_CTRL_REGn register DWP lock status.
*
* @param pEim EIM Instance.
* @param u8Idx Control register index.
* @return Lock status.
*/
LOCAL_INLINE bool EIM_HWA_GetCtrlRegnDwpLockStatus(const EIM_Type *const pEim, uint8_t u8Idx)
{
return ((pEim->CTRL_REG[u8Idx] & EIM_CTRL_REG_DWP_LOCK_MASK) != 0U) ? true : false;
}
/**
* @brief Set EIM_CTRL_REGn register DWP lock status.
*
* @param pEim EIM Instance.
* @param u8Idx Control register index.
* @param bEnable Enable or disable.
*/
LOCAL_INLINE void EIM_HWA_SetCtrlRegnDwpLock(EIM_Type *const pEim, uint8_t u8Idx, bool bEnable)
{
pEim->CTRL_REG[u8Idx] = (pEim->CTRL_REG[u8Idx] & ~((uint32_t)EIM_CTRL_REG_DWP_LOCK_MASK)) | EIM_CTRL_REG_DWP_LOCK(bEnable);
}
/**
* @brief Set EIM_CTRL_REGn register DWP mode.
*
* @param pEim EIM Instance.
* @param u8Idx Control register index.
* @param u8DwpMode DWP mode.
*/
LOCAL_INLINE void EIM_HWA_SetCtrlRegnDwpMode(EIM_Type *const pEim, uint8_t u8Idx, uint8_t u8DwpMode)
{
pEim->CTRL_REG[u8Idx] = (pEim->CTRL_REG[u8Idx] & ~((uint32_t)EIM_CTRL_REG_DWP_MASK)) | EIM_CTRL_REG_DWP(u8DwpMode);
}
/**
* @brief Set EIM LOCKSTEP error injection register.
*
* @param pEim EIM Instance.
* @param u8Idx Control register index.
* @param u32Value Register value.
*/
LOCAL_INLINE void EIM_HWA_SetLockstep(EIM_Type *const pEim, uint8_t u8Idx, uint32_t u32Value)
{
pEim->LOCKSTEP[u8Idx] = u32Value;
}
/**
* @brief Get EIM bus n register value.
*
* @param pEim EIM Instance.
* @param u8Idx Bus register index.
* @return Register value.
*/
LOCAL_INLINE uint32_t EIM_HWA_GetBusRegn(const EIM_Type *const pEim, uint8_t u8Idx)
{
return pEim->BUS_REG[u8Idx];
}
/**
* @brief Set EIM bus n register value.
*
* @param pEim EIM Instance.
* @param u8Idx Control register index.
* @param u32Value Register value.
*/
LOCAL_INLINE void EIM_HWA_SetBusRegn(EIM_Type *const pEim, uint8_t u8Idx, uint32_t u32Value)
{
pEim->BUS_REG[u8Idx] = u32Value;
}
/** @}*/
#if defined(__cplusplus)
}
#endif
#endif /* (EIM_INSTANCE_COUNT > 0U) */
#endif /* _HWA_EIM_H_ */

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/**
* @file HwA_erm.h
* @author Flagchip0100
* @brief ERM Module Register API
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright 2020-2024 Flagchip Semiconductors Co., Ltd.
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip052 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip100 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_ERM_H_
#define _HWA_ERM_H_
#include "device_header.h"
#if (ERM_INSTANCE_COUNT > 0U)
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @defgroup HwA_erm HwA_erm
* @ingroup module_driver_erm
* @{
*/
/*******************************************************************************
* Local inline function
******************************************************************************/
/**
* @brief set erm configuration register.
*
* @param pErm ERM Instance.
* @param u8Idx Control register index.
* @param u32RegValue access control value.
*/
LOCAL_INLINE void ERM_HWA_SetCRn(ERM_Type *const pErm, uint8_t u8Idx, uint32_t u32RegValue)
{
#ifdef ERM_CR4_SR4_SUPPORT
if (u8Idx == 4U)
{
pErm->CR4 = u32RegValue;
}
else
#endif
{
pErm->CR[u8Idx] = u32RegValue;
}
}
/**
* @brief get ERM configuration register.
*
* @param pErm ERM Instance.
* @param u8Idx Control register index.
* @return ERM CRn value.
*/
LOCAL_INLINE uint32_t ERM_HWA_GetCRn(const ERM_Type *const pErm, uint8_t u8Idx)
{
uint32_t u32Value = 0U;
#ifdef ERM_CR4_SR4_SUPPORT
if (u8Idx == 4U)
{
u32Value = pErm->CR4;
}
else
#endif
{
u32Value = pErm->CR[u8Idx];
}
return u32Value;
}
/**
* @brief set erm status register.
*
* @param pErm ERM Instance.
* @param u8Idx Status register index.
* @param u32RegValue access control value.
*/
LOCAL_INLINE void ERM_HWA_SetSRn(ERM_Type *const pErm, uint8_t u8Idx, uint32_t u32RegValue)
{
#ifdef ERM_CR4_SR4_SUPPORT
if (u8Idx == 4U)
{
pErm->SR4 = u32RegValue;
}
else
#endif
{
pErm->SR[u8Idx] = u32RegValue;
}
}
/**
* @brief get ERM status register.
*
* @param pErm ERM Instance.
* @param u8Idx Status register index.
* @return ERM SRn value.
*/
LOCAL_INLINE uint32_t ERM_HWA_GetSRn(const ERM_Type *const pErm, uint8_t u8Idx)
{
uint32_t u32Value = 0U;
#ifdef ERM_CR4_SR4_SUPPORT
if (u8Idx == 4U)
{
u32Value = pErm->SR4;
}
else
#endif
{
u32Value = pErm->SR[u8Idx];
}
return u32Value;;
}
/**
* @brief get ERM error address register.
*
* @param pErm ERM Instance.
* @param u8Idx Error address register index.
* @return ERM error address register value.
*/
LOCAL_INLINE uint32_t ERM_HWA_GetEARn(const ERM_Type *const pErm, uint8_t u8Idx)
{
return pErm->EAR[u8Idx].value;
}
#if defined(__cplusplus)
}
#endif
/** @}*/ /* HwA_erm */
#endif /* (ERM_INSTANCE_COUNT > 0U) */
#endif /* _HWA_ERM_H_ */

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/**
* @file HwA_fcpit.h
* @author Flagchip
* @brief FCPIT hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip071 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip071 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_FCPIT_H_
#define _HWA_FCPIT_H_
#include "device_header.h"
#if FCPIT_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_fcpit HwA_fcpit
* @ingroup module_driver_fcpit
* @{
*/
/********* Local typedef ************/
/** @brief Fcpit counter mode, the default mode is 32bit periodic count mode */
typedef enum
{
FCPIT_32PERIODIC_COUNTER = 0,
FCPIT_DUAL_16PERIODIC_COUNTER,
FCPIT_ACCUMULATOR,
FCPIT_INPUT_CAPTURE,
FCPIT_CHANNEL_NOMODE
} FCPIT_TimerModeType;
/** @brief Fcpit channel number */
typedef enum
{
FCPIT_CHANNEL_0 = 0U,
FCPIT_CHANNEL_1,
FCPIT_CHANNEL_2,
FCPIT_CHANNEL_3,
FCPIT_CHANNEL_MAX
} FCPIT_ChannelType;
/********* Local inline function ************/
/**
* @brief Set FCPIT channel value
*
* @param eChannel FCPIT channel number
* @param u32RegValue Timer value
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelValue(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint32_t u32RegValue)
{
pFcpit->CONTROLS[eChannel].TVAL = u32RegValue;
}
/**
* @brief Configure FCPIT channel
*
* @param eChannel FCPIT channel number
* @param u32RegValue TCTRL register value
*/
LOCAL_INLINE void FCPIT_HWA_ConfigChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint32_t u32RegValue)
{
pFcpit->CONTROLS[eChannel].TCTRL = u32RegValue;
}
/**
* @brief Configure FCPIT module
*
* @param u32RegValue MCR register value
*/
LOCAL_INLINE void FCPIT_HWA_ConfigModule(FCPIT_Type *pFcpit, uint32_t u32RegValue)
{
pFcpit->MCR = u32RegValue;
}
/**
* @brief Read FCPIT module enable
*
* @return MCR register with FCPIT_MCR_M_CEN_MASK
*/
LOCAL_INLINE uint32_t FCPIT_HWA_ReadModuleEnable(FCPIT_Type *pFcpit)
{
return (uint32_t)(pFcpit->MCR & FCPIT_MCR_M_CEN_MASK);
}
/**
* @brief Read FCPIT channel
*
* @param eChannel Channel number
* @return TCTRL register with FCPIT_TCTRL_T_EN_MASK
*/
LOCAL_INLINE uint32_t FCPIT_HWA_ReadChannelEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
return (uint32_t)(pFcpit->CONTROLS[eChannel].TCTRL & FCPIT_TCTRL_T_EN_MASK);
}
/**
* @brief Read FCPIT active interrupt flag
*
* @return FCPIT active interrupt flag
*/
LOCAL_INLINE uint32_t FCPIT_HWA_ReadInterruptFlag(FCPIT_Type *pFcpit)
{
return (pFcpit->MSR);
}
/**
* @brief Read FCPIT enable interrupt flag
*
* @return FCPIT enable interrupt flag
*/
LOCAL_INLINE uint32_t FCPIT_HWA_ReadEnableInterruptFlag(FCPIT_Type *pFcpit)
{
return (pFcpit->MIER);
}
/**
* @brief Set FCPIT channel running on debug mode
*
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelRunOnDebug(FCPIT_Type *pFcpit)
{
pFcpit->MCR |= FCPIT_MCR_DBG_EN_MASK;
}
/**
* @brief Set FCPIT channel running on low power mode
*
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelRunOnLpm(FCPIT_Type *pFcpit)
{
pFcpit->MCR |= FCPIT_MCR_LPM_EN_MASK;
}
/**
* @brief Enable FCPIT module
*
*/
LOCAL_INLINE void FCPIT_HWA_EnableModule(FCPIT_Type *pFcpit)
{
pFcpit->MCR |= FCPIT_MCR_M_CEN_MASK;
}
/**
* @brief Enable FCPIT channel(n) interrupt
*
* @param u32RegValue u32RegValue 0-3 bit indicate TIE0-TIE3
*/
LOCAL_INLINE void FCPIT_HWA_EnableChannelsInterrupt(FCPIT_Type *pFcpit, uint32_t u32RegValue)
{
pFcpit->MIER |= u32RegValue;
}
/**
* @brief Enable FCPIT channel
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_EnableChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_T_EN_MASK;
}
/**
* @brief Enable FCPIT channel
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_SetTimerEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->SETTEN |= (FCPIT_SETTEN_SET_T_EN_0_MASK << (uint32_t)eChannel);
}
/**
* @brief Disable FCPIT channel
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearTimerEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CLRTEN |= (FCPIT_CLRTEN_CLR_T_EN_0_MASK << (uint32_t)eChannel);
}
/**
* @brief Enable FCPIT channel(n) chain mode
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_EnableChannelChainMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_CHAIN_MASK;
}
/**
* @brief Configure FCPIT channel operation mode
*
* @param eChannel FCPIT channel number
* @param eMode FCPIT operation mode
*/
LOCAL_INLINE void FCPIT_HWA_ConfigChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, FCPIT_TimerModeType eMode)
{
uint32_t u32RegValue = pFcpit->CONTROLS[eChannel].TCTRL;
pFcpit->CONTROLS[eChannel].TCTRL = (u32RegValue & ~(uint32_t)FCPIT_TCTRL_MODE_MASK) | FCPIT_TCTRL_MODE(eMode);
}
/**
* @brief Set FCPIT channel start on trigger
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelStartOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TSOT_MASK;
}
/**
* @brief Set FCPIT channel stop on interrupt
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnInterrupt(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TSOI_MASK;
}
/**
* @brief Set FCPIT channel reload on trigger
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelReloadOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TROT_MASK;
}
/**
* @brief Set FCPIT channel trigger source
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelTriggerSrc(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TRG_SRC_MASK;
}
/**
* @brief Select FCPIT channel trigger
*
* @param eChannel FCPIT channel number
* @param u8SelChannel Select channel, range is 0-3
*/
LOCAL_INLINE void FCPIT_HWA_SelectChannelTrigger(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint8_t u8SelChannel)
{
uint32_t u32RegValue = pFcpit->CONTROLS[eChannel].TCTRL;
pFcpit->CONTROLS[eChannel].TCTRL = (u32RegValue & ~(uint32_t)FCPIT_TCTRL_TRG_SEL_MASK) |
FCPIT_TCTRL_TRG_SEL(u8SelChannel);
}
/**
* @brief Set FCPIT channel stop on debug mode
*
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnDebug(FCPIT_Type *pFcpit)
{
pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_DBG_EN_MASK;
}
/**
* @brief Set FCPIT channel stop on low power mode
*
*/
LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnLpm(FCPIT_Type *pFcpit)
{
pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_LPM_EN_MASK;
}
/**
* @brief Disable FCPIT module
*
*/
LOCAL_INLINE void FCPIT_HWA_DisableModule(FCPIT_Type *pFcpit)
{
pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_M_CEN_MASK;
}
/**
* @brief Clear FCPIT channel(n) interrupt flag
*
* @param u32RegValue 0-3 bit indicate TIF0-TIF3
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT_Type *pFcpit, uint32_t u32RegValue)
{
pFcpit->MSR = u32RegValue;
}
/**
* @brief Disable FCPIT channel(n) interrupt
*
* @param u32RegValue u32RegValue 0-3 bit indicate TIE0-TIE3
*/
LOCAL_INLINE void FCPIT_HWA_DisableChannelsInterrupt(FCPIT_Type *pFcpit, uint32_t u32RegValue)
{
pFcpit->MIER &= ~u32RegValue;
}
/**
* @brief Disable FCPIT channel
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_DisableChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_T_EN_MASK;
}
/**
* @brief Disable FCPIT channel chain mode
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_DisableChannelChainMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_CHAIN_MASK;
}
/**
* @brief Clear FCPIT channel operation mode
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_MODE_MASK;
}
/**
* @brief Clear FCPIT channel start on trigger
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelStartOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TSOT_MASK;
}
/**
* @brief Clear FCPIT channel stop on interrupt
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelStopOnInterrupt(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TSOI_MASK;
}
/**
* @brief Clear FCPIT channel reload on trigger
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelReloadOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TROT_MASK;
}
/**
* @brief Clear FCPIT channel trigger source
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelTriggerSrc(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TRG_SRC_MASK;
}
/**
* @brief Clear FCPIT channel trigger select
*
* @param eChannel FCPIT channel number
*/
LOCAL_INLINE void FCPIT_HWA_ClearChannelTriggerSelect(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel)
{
pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TRG_SEL_MASK;
}
/** @}*/
#endif /* #if FCPIT_INSTANCE_COUNT > 0U */
#endif /* #ifndef _HWA_FCPIT_H_ */

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@ -0,0 +1,708 @@
/**
* @file HwA_fcsmu.h
* @author Flagchip0100
* @brief FCSMU module register API
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright 2020-2024 Flagchip Semiconductors Co., Ltd.
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip052 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip100 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_FCSMU_H_
#define _HWA_FCSMU_H_
#include "device_header.h"
#if (FCSMU_INSTANCE_COUNT > 0U)
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @defgroup HwA_fcsmu HwA_fcsmu
* @ingroup module_driver_fcsmu
* @{
*/
/*******************************************************************************
* Local inline function
******************************************************************************/
/**
* @brief Set the fcsmu CTRL register
*
* @param pFcsmu FCSMU Instance
* @param u32Value The register value
*/
LOCAL_INLINE void FCSMU_HWA_SetCrtl(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->CTRL = u32Value;
}
/**
* @brief Get the fcsmu CTRL register
*
* @param pFcsmu FCSMU Instance
* @return CTRL register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetCtrl(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->CTRL;
}
/**
* @brief Get the fcsmu CTRL register OPS
*
* @param pFcsmu FCSMU Instance
* @return CTRL register OPS value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetCtrlOps(const FCSMU_Type *const pFcsmu)
{
return ((pFcsmu->CTRL & FCSMU_CTRL_OPS_MASK) >> FCSMU_CTRL_OPS_SHIFT);
}
/**
* @brief Set the fcsmu OPRK register
*
* @param pFcsmu FCSMU Instance
* @param u32Value The register value
*/
LOCAL_INLINE void FCSMU_HWA_SetOprk(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->OPRK = u32Value;
}
/**
* @brief Set the fcsmu SOCTRL register
*
* @param pFcsmu FCSMU Instance
* @param u32Value The register value
*/
LOCAL_INLINE void FCSMU_HWA_SetSoctrl(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->SOCTRL = u32Value;
}
/**
* @brief Get the fcsmu SOCTRL register
*
* @param pFcsmu FCSMU Instance
* @return SOCTRL register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetSoctrl(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->SOCTRL;
}
/**
* @brief Set the fcsmu FCCR0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value FCCR0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetFccr0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->FCCR0 = u32Value;
}
/**
* @brief Get the fcsmu FCCR0 register
*
* @param pFcsmu FCSMU Instance
* @return FCCR0 register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetFccr0(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->FCCR0;
}
/**
* @brief Set the fcsmu FRST0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value FRST0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetFrst0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->FRST0 = u32Value;
}
/**
* @brief Get the fcsmu FRST0 register
*
* @param pFcsmu FCSMU Instance
* @return FRST0 register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetFrst0(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->FRST0;
}
/**
* @brief Set the fcsmu FST0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value FST0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetFst0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->FST0 = u32Value;
}
/**
* @brief Get the fcsmu FST0 register
*
* @param pFcsmu FCSMU Instance
* @return FST0 register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetFst0(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->FST0;
}
/**
* @brief Set the fcsmu FST_UNLK register
*
* @param pFcsmu FCSMU Instance
* @param u32Value FST_UNLK register value
*/
LOCAL_INLINE void FCSMU_HWA_SetFstUnlk(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->FST_UNLK = u32Value;
}
/**
* @brief Set the fcsmu FE0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value FE0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetFe0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->FE0 = u32Value;
}
/**
* @brief Get the fcsmu FE0 register
*
* @param pFcsmu FCSMU Instance
* @return FE0 register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetFe0(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->FE0;
}
/**
* @brief Set the fcsmu WARNING_EN0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value WARNING_EN0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetWarningEn0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->WARNING_EN0 = u32Value;
}
/**
* @brief Get the fcsmu WARNING_EN0 register
*
* @param pFcsmu FCSMU Instance
* @return WARNING_EN0 register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetWarningEn0(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->WARNING_EN0;
}
/**
* @brief Set the fcsmu WARNING_TO register
*
* @param pFcsmu FCSMU Instance
* @param u32Value WARNING_TO register value
*/
LOCAL_INLINE void FCSMU_HWA_SetWarningTo(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->WARNING_TO = u32Value;
}
/**
* @brief Get the fcsmu WARNING_TO register
*
* @param pFcsmu FCSMU Instance
* @return WARNING_TO register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetWarningTo(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->WARNING_TO;
}
/**
* @brief Set the fcsmu CFG_TO register
*
* @param pFcsmu FCSMU Instance
* @param u32Value CFG_TO register value
*/
LOCAL_INLINE void FCSMU_HWA_SetCfgTo(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->CFG_TO = u32Value;
}
/**
* @brief Get the fcsmu CFG_TO register
*
* @param pFcsmu FCSMU Instance
* @return CFG_TO register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetCfgTo(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->CFG_TO;
}
/**
* @brief Set the fcsmu SOUT_DIAG register
*
* @param pFcsmu FCSMU Instance
* @param u32Value SOUT_DIAG register value
*/
LOCAL_INLINE void FCSMU_HWA_SetSoutDiag(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->SOUT_DIAG = u32Value;
}
/**
* @brief Get the fcsmu SOUT_DIAG register
*
* @param pFcsmu FCSMU Instance
* @return SOUT_DIAG register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetSoutDiag(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->SOUT_DIAG;
}
/**
* @brief Get the fcsmu STATUS register
*
* @param pFcsmu FCSMU Instance
* @return STATUS register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetStatus(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->STATUS;
}
/**
* @brief Get the fcsmu STATUS register FIF value
*
* @param pFcsmu FCSMU Instance
* @return STATUS register FIF value
*/
LOCAL_INLINE bool FCSMU_HWA_GetFaultState(const FCSMU_Type *const pFcsmu)
{
return ((pFcsmu->STATUS & FCSMU_STATUS_FIF_MASK) == FCSMU_STATUS_FIF_MASK) ? true : false;
}
/**
* @brief Get the fcsmu STATUS register STAT value
*
* @param pFcsmu FCSMU Instance
* @return STATUS register STAT value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetFcsmuState(const FCSMU_Type *const pFcsmu)
{
return ((pFcsmu->STATUS & FCSMU_STATUS_STAT_MASK) >> FCSMU_STATUS_STAT_SHIFT);
}
/**
* @brief Get the fcsmu NTW register
*
* @param pFcsmu FCSMU Instance
* @return NTW register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetNtw(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->NTW;
}
/**
* @brief Get the fcsmu WTF register
*
* @param pFcsmu FCSMU Instance
* @return WTF register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetWtf(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->WTF;
}
/**
* @brief Get the fcsmu NTF register
*
* @param pFcsmu FCSMU Instance
* @return NTF register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetNtf(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->NTF;
}
/**
* @brief Get the fcsmu FTW register
*
* @param pFcsmu FCSMU Instance
* @return FTW register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetFtw(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->FTW;
}
/**
* @brief Set the fcsmu INJECT register
*
* @param pFcsmu FCSMU Instance
* @param u32Value INJECT register value
*/
LOCAL_INLINE void FCSMU_HWA_SetInject(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->INJECT = u32Value;
}
/**
* @brief Get the fcsmu IRQ_STAT register
*
* @param pFcsmu FCSMU Instance
* @return IRQ_STAT register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetIrqStat(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->IRQ_STAT;
}
/**
* @brief Clear the fcsmu IRQ_STAT register
*
* @param pFcsmu FCSMU Instance
*/
LOCAL_INLINE void FCSMU_HWA_ClearCfgToIrq(FCSMU_Type *const pFcsmu)
{
pFcsmu->IRQ_STAT = FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK;
}
/**
* @brief Set the fcsmu IRQ_EN register
*
* @param pFcsmu FCSMU Instance
* @param bEnable IRQ_EN register value
*/
LOCAL_INLINE void FCSMU_HWA_EnableCfgToIrq(FCSMU_Type *const pFcsmu, bool bEnable)
{
pFcsmu->IRQ_EN = FCSMU_IRQ_EN_CFG_TO_IEN(bEnable);
}
/**
* @brief Set the fcsmu TEMP_UNLK register
*
* @param pFcsmu FCSMU Instance
* @param u32Value TEMP_UNLK register value
*/
LOCAL_INLINE void FCSMU_HWA_SetTempUnlk(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->TEMP_UNLK = u32Value;
}
/**
* @brief Set the fcsmu PERMNT_LOCK register
*
* @param pFcsmu FCSMU Instance
* @param u32Value PERMNT_LOCK register value
*/
LOCAL_INLINE void FCSMU_HWA_SetPermntLock(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->PERMNT_LOCK = u32Value;
}
/**
* @brief Set the fcsmu STMR register
*
* @param pFcsmu FCSMU Instance
* @param u32Value STMR register value
*/
LOCAL_INLINE void FCSMU_HWA_SetStmr(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->STMR = u32Value;
}
/**
* @brief Set the fcsmu WARNING_IEN0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value WARNING_IEN0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetWarningIen0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->WARNING_IEN0 = u32Value;
}
/**
* @brief Set the fcsmu FAULT_IEN0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value FAULT_IEN0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetFaultIen0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->FAULT_IEN0 = u32Value;
}
/**
* @brief Set the fcsmu SOUT_EN0 register
*
* @param pFcsmu FCSMU Instance
* @param u32Value SOUT_EN0 register value
*/
LOCAL_INLINE void FCSMU_HWA_SetSoutEn0(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->SOUT_EN0 = u32Value;
}
/**
* @brief Get the fcsmu WARNING_TMR register
*
* @param pFcsmu FCSMU Instance
* @return WARNING_TMR register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetWarningTmr(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->WARNING_TMR;
}
/**
* @brief Get the fcsmu SM_TMR register
*
* @param pFcsmu FCSMU Instance
* @return SM_TMR register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetSafeModeTmr(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->SM_TMR;
}
/**
* @brief Get the fcsmu CFG_TMR register
*
* @param pFcsmu FCSMU Instance
* @return CFG_TMR register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetCfgTmr(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->CFG_TMR;
}
/**
* @brief Get the fcsmu SOUT_TMR register
*
* @param pFcsmu FCSMU Instance
* @return SOUT_TMR register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetSoutTmr(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->SOUT_TMR;
}
/**
* @brief Set the fcsmu CRC_CTRL register
*
* @param pFcsmu FCSMU Instance
* @param u32Value CRC_CTRL register value
*/
LOCAL_INLINE void FCSMU_HWA_SetCrcCtrl(FCSMU_Type *const pFcsmu, uint32_t u32Value)
{
pFcsmu->CRC_CTRL = u32Value;
}
/**
* @brief Get the fcsmu CRC_CTRL register BUSY value
*
* @param pFcsmu FCSMU Instance
* @return BUSY value
*/
LOCAL_INLINE bool FCSMU_HWA_GetCrcBusy(const FCSMU_Type *const pFcsmu)
{
bool bRet = false;
#ifdef FCSMU_CRC_CTRL_DONE_SUPPORT
bRet = ((pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_DONE_MASK) == FCSMU_CRC_CTRL_DONE_MASK) ? false : true;
#else
bRet = ((pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_BUSY_MASK) == FCSMU_CRC_CTRL_BUSY_MASK) ? true : false;
#endif /* FCSMU_CRC_CTRL_DONE_SUPPORT */
return bRet;
}
/**
* @brief Get the fcsmu CRC_CTRL register EF value
*
* @param pFcsmu FCSMU Instance
* @return EF value
*/
LOCAL_INLINE bool FCSMU_HWA_GetCrcErrorFlag(const FCSMU_Type *const pFcsmu)
{
return ((pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_EF_MASK) == FCSMU_CRC_CTRL_EF_MASK) ? true : false;
}
/**
* @brief Clear the fcsmu CRC_CTRL register EF
*
* @param pFcsmu FCSMU Instance
*/
LOCAL_INLINE void FCSMU_HWA_ClearCrcErrorFlag(FCSMU_Type *const pFcsmu)
{
uint32_t u32RegValue = pFcsmu->CRC_CTRL;
/* Reserve RW bits */
u32RegValue = u32RegValue & (FCSMU_CRC_CTRL_EOEN_MASK |
FCSMU_CRC_CTRL_CHKEN_MASK |
FCSMU_CRC_CTRL_TRGEN_MASK);
u32RegValue = u32RegValue | FCSMU_CRC_CTRL_EF_MASK;
pFcsmu->CRC_CTRL = u32RegValue;
}
#ifdef FCSMU_CRC_CTRL_DONE_SUPPORT
/**
* @brief Clear the fcsmu CRC_CTRL register DONE
*
* @param pFcsmu FCSMU Instance
*/
LOCAL_INLINE void FCSMU_HWA_ClearCrcDoneFlag(FCSMU_Type *const pFcsmu)
{
uint32_t u32RegValue = pFcsmu->CRC_CTRL;
/* Reserve RW bits */
u32RegValue = u32RegValue & (FCSMU_CRC_CTRL_EOEN_MASK |
FCSMU_CRC_CTRL_CHKEN_MASK |
FCSMU_CRC_CTRL_TRGEN_MASK);
u32RegValue = u32RegValue | FCSMU_CRC_CTRL_DONE_MASK;
pFcsmu->CRC_CTRL = u32RegValue;
}
#endif
/**
* @brief Set the fcsmu CRC_CTRL register
*
* @param pFcsmu FCSMU Instance
* @param bEnable Enable or Disable CRC_CTRL register EOEN bit value
*/
LOCAL_INLINE void FCSMU_HWA_EnableErrorOutput(FCSMU_Type *const pFcsmu, bool bEnable)
{
uint32_t u32RegValue = pFcsmu->CRC_CTRL;
/* Reserve RW bits */
u32RegValue = u32RegValue & (FCSMU_CRC_CTRL_CHKEN_MASK |
FCSMU_CRC_CTRL_TRGEN_MASK);
u32RegValue = (u32RegValue & ~FCSMU_CRC_CTRL_EOEN_MASK) | FCSMU_CRC_CTRL_EOEN(bEnable);
pFcsmu->CRC_CTRL = u32RegValue;
}
/**
* @brief Get the fcsmu CRC_CTRL register EOEN value
*
* @param pFcsmu FCSMU Instance
* @return EOEN value
*/
LOCAL_INLINE bool FCSMU_HWA_GetCrcErrorOutputEnable(const FCSMU_Type *const pFcsmu)
{
return ((pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_EOEN_MASK) == FCSMU_CRC_CTRL_EOEN_MASK) ? true : false;
}
/**
* @brief Set the fcsmu CRC_CTRL register
*
* @param pFcsmu FCSMU Instance
* @param bEnable CRC_CTRL register value
*/
LOCAL_INLINE void FCSMU_HWA_EnableCrcChecker(FCSMU_Type *const pFcsmu, bool bEnable)
{
pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_CHKEN_MASK) | FCSMU_CRC_CTRL_CHKEN(bEnable);
}
/**
* @brief Get the fcsmu CRC_CTRL register CHKEN value
*
* @param pFcsmu FCSMU Instance
* @return CHKEN value
*/
LOCAL_INLINE bool FCSMU_HWA_GetCrcCheckerEnable(const FCSMU_Type *const pFcsmu)
{
return ((pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_CHKEN_MASK) == FCSMU_CRC_CTRL_CHKEN_MASK) ? true : false;
}
/**
* @brief Set the fcsmu CRC_CTRL register
*
* @param pFcsmu FCSMU Instance
* @param bEnable CRC_CTRL register value
*/
LOCAL_INLINE void FCSMU_HWA_EnableTrigger(FCSMU_Type *const pFcsmu, bool bEnable)
{
pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_TRGEN_MASK) | FCSMU_CRC_CTRL_TRGEN(bEnable);
}
/**
* @brief Get the fcsmu CRC_CTRL register TRGEN value
*
* @param pFcsmu FCSMU Instance
* @return TRGEN value
*/
LOCAL_INLINE bool FCSMU_HWA_GetTriggerEnable(const FCSMU_Type *const pFcsmu)
{
return ((pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_TRGEN_MASK) == FCSMU_CRC_CTRL_TRGEN_MASK) ? true : false;
}
/**
* @brief Set the fcsmu CRC_CTRL register
*
* @param pFcsmu FCSMU Instance
*/
LOCAL_INLINE void FCSMU_HWA_GenerateCrc(FCSMU_Type *const pFcsmu)
{
uint32_t u32RegValue = pFcsmu->CRC_CTRL;
/* Reserve RW bits */
u32RegValue = u32RegValue & (FCSMU_CRC_CTRL_EOEN_MASK |
FCSMU_CRC_CTRL_CHKEN_MASK |
FCSMU_CRC_CTRL_TRGEN_MASK);
u32RegValue = u32RegValue | FCSMU_CRC_CTRL_GEN(1U);
pFcsmu->CRC_CTRL = u32RegValue;
}
/**
* @brief Get the fcsmu CRC_RES register
*
* @param pFcsmu FCSMU Instance
* @return CRC_RES register value
*/
LOCAL_INLINE uint32_t FCSMU_HWA_GetCrcResult(const FCSMU_Type *const pFcsmu)
{
return pFcsmu->CRC_RES;
}
#if defined(__cplusplus)
}
#endif
/** @}*/
#endif /* (FCSMU_INSTANCE_COUNT > 0U) */
#endif /* _HWA_FCSMU_H_ */

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#ifndef _HWA_FCSPI_H_
#define _HWA_FCSPI_H_
#include "device_header.h"
#define FCSPI_SET_BIT(REG, BIT) ((REG) |= (BIT))
#define FCSPI_CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define FCSPI_READ_BIT(REG, BIT) ((REG) & (BIT))
#define FCSPI_CLEAR_REG(REG) ((REG) = (0x0))
#define FCSPI_WRITE_REG(REG, VAL) ((REG) = (VAL))
#define FCSPI_READ_REG(REG) ((REG))
#define FCSPI_MODIFY_REG(REG, CLEARMASK, SETMASK) FCSPI_WRITE_REG((REG), (((FCSPI_READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#if FCSPI_INSTANCE_COUNT > 0U
/**
* @brief FCSPI Mode type, master or slave.
*/
typedef enum {
FCSPI_MODE_SLAVE = 0,
FCSPI_MODE_MASTER = 1
} FCSPI_MasterSlaveModeType;
typedef enum {
FCSPI_PCS_0 = 0, /**< Transfer using pcs_0 */
FCSPI_PCS_1 = 1, /**< Transfer using pcs_1 */
FCSPI_PCS_2 = 2, /**< Transfer using pcs_2 */
FCSPI_PCS_3 = 3 /**< Transfer using pcs_3 */
} FCSPI_PcsSelType;
typedef enum {
FCSPI_PCS_ACTIVE_LOW = 0, /**< pcs use low level to select external device */
FCSPI_PCS_ACTIVE_HIGH = 1 /**< pcs use high level to select external device */
} FCSPI_PcsPolarityType;
typedef enum {
FCSPI_SIN_INPUT_SOUT_OUTPUT = 0, /**< SIN is configured as input pin and SOUT is configured as output pin */
FCSPI_SIN_INPUT_OUTPUT = 1, /**< SIN is configured as input and output pin */
FCSPI_SOUT_INPUT_OUTPUT = 2, /**< SOUT is configured as input and output pin */
FCSPI_SOUT_INPUT_SIN_OUTPUT = 3 /**< SOUT is configured as input pin and SIN is configured as output pin */
} FCSPI_PinConfigType;
typedef enum {
FCSPI_OUTPUT_RETAIN_LAST = 0, /**< SIN is configured as input pin and SOUT is configured as output pin */
FCSPI_OUTPUT_TRISTATE = 1
} FCSPI_OutputConfigType;
typedef enum {
FCSPI_TRANSFER_WIDTH_1_BIT = 0, /**< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */
FCSPI_TRANSFER_WIDTH_2_BIT = 1, /**< 2-bits shift out on SDO/SDI and in on SDO/SDI */
FCSPI_TRANSFER_WIDTH_4_BIT = 2 /**< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */
} FCSPI_TransferWidthType;
typedef enum
{
FCSPI_MSB_FIRST = 0, /**< most significant bit first handle, from msb to lsb */
FCSPI_LSB_FIRST = 1 /**< least significant bit first handle, from lsb to msb */
} FCSPI_DataFirstBitType;
typedef enum
{
FCSPI_PRESCALE_DIV_1 = 0, /**< most significant bit first handle, from msb to lsb */
FCSPI_PRESCALE_DIV_2 = 1,
FCSPI_PRESCALE_DIV_4 = 2,
FCSPI_PRESCALE_DIV_8 = 3,
FCSPI_PRESCALE_DIV_16 = 4,
FCSPI_PRESCALE_DIV_32 = 5,
FCSPI_PRESCALE_DIV_64 = 6,
FCSPI_PRESCALE_DIV_128 = 7
} FCSPI_PrescaleType;
typedef enum
{
FCSPI_SCK_SAMPLE_FIRST_EDGE = 0, /**< sample on first edge of sck active polarity, change on second */
FCSPI_SCK_SAMPLE_SECOND_EDGE = 1 /**< sample on second edge of sck active polarity, change on first */
} FCSPI_SckPhaseType;
typedef enum
{
FCSPI_SCK_IDLE_LOW = 0, /**< sck is high level when active (idles low). */
FCSPI_SCK_IDLE_HIGH = 1 /**< sck is low level when active (idles high). */
} FCSPI_SckPolarityType;
/********* Local inline function ************/
/**
* @brief Manipulate CTRL.M_EN to enable/disable FCSPI.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
*/
LOCAL_INLINE void FCSPI_HWA_EnableModule(FCSPI_Type *pFCSPI, bool enable)
{
enable ? FCSPI_WRITE_REG(pFCSPI->CTRL, 1) : FCSPI_WRITE_REG(pFCSPI->CTRL, 0);
}
LOCAL_INLINE void FCSPI_HWA_EnableDebugMode(FCSPI_Type *pFCSPI, bool enable)
{
enable ? FCSPI_SET_BIT(pFCSPI->CTRL, FCSPI_CTRL_DBG_EN_MASK) : FCSPI_CLEAR_BIT(pFCSPI->CTRL, FCSPI_CTRL_DBG_EN_MASK);
}
LOCAL_INLINE bool FCSPI_HWA_IsEnabled(FCSPI_Type *pFCSPI)
{
return FCSPI_READ_BIT(pFCSPI->CTRL, FCSPI_CTRL_M_EN_MASK);
}
LOCAL_INLINE void FCSPI_HWA_ResetRxFIFO(FCSPI_Type *pFCSPI)
{
FCSPI_SET_BIT(pFCSPI->CTRL, FCSPI_CTRL_RST_RF_MASK);
}
LOCAL_INLINE void FCSPI_HWA_ResetTxFIFO(FCSPI_Type *pFCSPI)
{
FCSPI_SET_BIT(pFCSPI->CTRL, FCSPI_CTRL_RST_TF_MASK);
}
/**
* @brief Set the FCSPI INT_EN register value for enable or disable some interrupts.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void FCSPI_HWA_EnableInterrupts(FCSPI_Type *pFCSPI, uint32_t IntsMask, bool enable)
{
if (true == enable)
{
FCSPI_SET_BIT(pFCSPI->INT_EN, IntsMask);
}
else
{
FCSPI_CLEAR_BIT(pFCSPI->INT_EN, IntsMask);
}
}
LOCAL_INLINE bool FCSPI_HWA_IsEnabledInterrupt(FCSPI_Type *pFCSPI, uint32_t IntMask)
{
return FCSPI_READ_BIT(pFCSPI->INT_EN, IntMask);
}
/**
* @brief Enable or disable the DMA feature by setting the FCSPI DMA_EN register value.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void FCSPI_HWA_EnableRxDMA(FCSPI_Type *pFCSPI, bool enable)
{
enable ? FCSPI_SET_BIT(pFCSPI->DMA_EN, FCSPI_DMA_EN_RFDE_MASK) : FCSPI_CLEAR_BIT(pFCSPI->DMA_EN, FCSPI_DMA_EN_RFDE_MASK);
}
LOCAL_INLINE bool FCSPI_HWA_IsEnabledRxDMA(FCSPI_Type *pFCSPI)
{
return FCSPI_READ_BIT(pFCSPI->DMA_EN, FCSPI_DMA_EN_RFDE_MASK);
}
LOCAL_INLINE void FCSPI_HWA_EnableTxDMA(FCSPI_Type *pFCSPI, bool enable)
{
enable ? FCSPI_SET_BIT(pFCSPI->DMA_EN, FCSPI_DMA_EN_TFDE_MASK) : FCSPI_CLEAR_BIT(pFCSPI->DMA_EN, FCSPI_DMA_EN_TFDE_MASK);
}
LOCAL_INLINE bool FCSPI_HWA_IsEnabledTxDMA(FCSPI_Type *pFCSPI)
{
return FCSPI_READ_BIT(pFCSPI->DMA_EN, FCSPI_DMA_EN_TFDE_MASK);
}
/**
* @brief Software reset FCSPI. This operation can be done regardless of whether the module is enabled or not(CTRL.M_EN).
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
*/
LOCAL_INLINE void FCSPI_HWA_SoftwareReset(FCSPI_Type *pFCSPI)
{
/* Disable DMA before software reset */
FCSPI_HWA_EnableRxDMA(pFCSPI, false);
FCSPI_HWA_EnableTxDMA(pFCSPI, false);
/* Disable all SPI interrupt before software reset */
FCSPI_HWA_EnableInterrupts(pFCSPI, FCSPI_INT_EN_MASK, false);
/* Disable module before software reset */
FCSPI_HWA_EnableModule(pFCSPI, false);
/* software reset */
FCSPI_SET_BIT(pFCSPI->CTRL, FCSPI_CTRL_SW_RST_MASK);
FCSPI_CLEAR_BIT(pFCSPI->CTRL, FCSPI_CTRL_SW_RST_MASK);
}
/**
* @brief Set the FCSPI to master mode.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
*/
LOCAL_INLINE void FCSPI_HWA_SetMasterMode(FCSPI_Type *pFCSPI)
{
FCSPI_SET_BIT(pFCSPI->CFG1, FCSPI_CFG1_MASTER_MASK);
}
/**
* @brief Set FCSPI to slave mode.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
*/
LOCAL_INLINE void FCSPI_HWA_SetSlaveMode(FCSPI_Type *pFCSPI)
{
FCSPI_CLEAR_BIT(pFCSPI->CFG1, FCSPI_CFG1_MASTER_MASK);
}
/**
* @brief Check the current mode status, master or slave.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @return the mode type of FCSPI, FCSPI_MODE_MASTER or FCSPI_MODE_SLAVE
*/
LOCAL_INLINE FCSPI_MasterSlaveModeType FCSPI_HWA_GetMode(FCSPI_Type *pFCSPI)
{
return (FCSPI_MasterSlaveModeType)(FCSPI_READ_BIT(pFCSPI->CFG1, FCSPI_CFG1_MASTER_MASK));
}
LOCAL_INLINE void FCSPI_HWA_ClearStatus(FCSPI_Type *pFCSPI, uint32_t u32StatusMask)
{
FCSPI_WRITE_REG(pFCSPI->STATUS, u32StatusMask);
}
/**
* @brief Clear FCSPI STATUS register for certain function.
*
* @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE uint32_t FCSPI_HWA_GetStatus(FCSPI_Type *pFCSPI, uint32_t u32FlagBitMask)
{
return FCSPI_READ_BIT(pFCSPI->STATUS, u32FlagBitMask);
}
LOCAL_INLINE void FCSPI_HWA_EnableSckLoopback(FCSPI_Type *pFCSPI, bool enable)
{
enable ? FCSPI_SET_BIT(pFCSPI->CFG1, FCSPI_CFG1_SCK_LB_MASK) : FCSPI_CLEAR_BIT(pFCSPI->CFG1, FCSPI_CFG1_SCK_LB_MASK);
}
LOCAL_INLINE void FCSPI_HWA_EnableInternalPcs(FCSPI_Type *pFCSPI, bool enable)
{
enable ? FCSPI_SET_BIT(pFCSPI->CFG1, FCSPI_CFG1_INT_PCS_MASK) : FCSPI_CLEAR_BIT(pFCSPI->CFG1, FCSPI_CFG1_INT_PCS_MASK);
}
LOCAL_INLINE void FCSPI_HWA_SetPcsPolarity(FCSPI_Type *pFCSPI, FCSPI_PcsSelType PCSn, FCSPI_PcsPolarityType PcsPolarity)
{
FCSPI_MODIFY_REG(pFCSPI->CFG1, FCSPI_CFG1_PCS_POL_MASK, (uint32_t)(PcsPolarity << PCSn) << FCSPI_CFG1_PCS_POL_SHIFT);
}
LOCAL_INLINE void FCSPI_HWA_SetPinConfig(FCSPI_Type *pFCSPI, FCSPI_PinConfigType PinCfg)
{
FCSPI_MODIFY_REG(pFCSPI->CFG1, FCSPI_CFG1_PIN_CFG_MASK, (uint32_t)PinCfg << FCSPI_CFG1_PIN_CFG_SHIFT);
}
LOCAL_INLINE void FCSPI_HWA_SetOutputConfig(FCSPI_Type *pFCSPI, FCSPI_OutputConfigType OutputCfg)
{
if (FCSPI_OUTPUT_RETAIN_LAST == OutputCfg) {
FCSPI_CLEAR_BIT(pFCSPI->CFG1, FCSPI_CFG1_OUT_CFG_MASK);
} else {
FCSPI_SET_BIT(pFCSPI->CFG1, FCSPI_CFG1_OUT_CFG_MASK);
}
}
LOCAL_INLINE void FCSPI_HWA_SetPcsConfig(FCSPI_Type *pFCSPI, bool Is4bitMode)
{
Is4bitMode ? FCSPI_SET_BIT(pFCSPI->CFG1, FCSPI_CFG1_PCS_CFG_MASK) : FCSPI_CLEAR_BIT(pFCSPI->CFG1, FCSPI_CFG1_PCS_CFG_MASK);
}
LOCAL_INLINE void FCSPI_HWA_SetSCKDIV(FCSPI_Type *pFCSPI, uint8 u8Value)
{
FCSPI_MODIFY_REG(pFCSPI->CLK_CFG, FCSPI_CLK_CFG_SCKDIV_MASK, (uint32_t)u8Value << FCSPI_CLK_CFG_SCKDIV_SHIFT);
}
LOCAL_INLINE void FCSPI_HWA_SetDelayPCSPCS(FCSPI_Type *pFCSPI, uint8 u8Value)
{
FCSPI_MODIFY_REG(pFCSPI->CLK_CFG, FCSPI_CLK_CFG_PCSPCS_MASK, (uint32_t)u8Value << FCSPI_CLK_CFG_PCSPCS_SHIFT);
}
LOCAL_INLINE void FCSPI_HWA_SetDelayPCSSCK(FCSPI_Type *pFCSPI, uint8 u8Value)
{
FCSPI_MODIFY_REG(pFCSPI->CLK_CFG, FCSPI_CLK_CFG_PCSSCK_MASK, (uint32_t)u8Value << FCSPI_CLK_CFG_PCSSCK_SHIFT);
}
LOCAL_INLINE void FCSPI_HWA_SetDelaySCKPCS(FCSPI_Type *pFCSPI, uint8 u8Value)
{
FCSPI_MODIFY_REG(pFCSPI->CLK_CFG, FCSPI_CLK_CFG_SCKPCS_MASK, (uint32_t)u8Value << FCSPI_CLK_CFG_SCKPCS_SHIFT);
}
LOCAL_INLINE void FCSPI_HWA_SetWatermarkTx(FCSPI_Type *pFCSPI, uint8 u8Value)
{
FCSPI_MODIFY_REG(pFCSPI->FIFO_WTM, FCSPI_FIFO_WTM_TXWATER_MASK, (uint32_t)u8Value & FCSPI_FIFO_WTM_TXWATER_MASK);
}
LOCAL_INLINE void FCSPI_HWA_SetWatermarkRx(FCSPI_Type *pFCSPI, uint8 u8Value)
{
FCSPI_MODIFY_REG(pFCSPI->FIFO_WTM, FCSPI_FIFO_WTM_RXWATER_MASK,
(uint32_t)(u8Value << FCSPI_FIFO_WTM_RXWATER_SHIFT) & FCSPI_FIFO_WTM_RXWATER_MASK);
}
LOCAL_INLINE uint32 FCSPI_HWA_GetTxFIFOCnt(FCSPI_Type *pFCSPI)
{
return (FCSPI_READ_BIT(pFCSPI->FIFO_STATUS, FCSPI_FIFO_STATUS_TXCNT_MASK));
}
LOCAL_INLINE uint32 FCSPI_HWA_GetRxFIFOCnt(FCSPI_Type *pFCSPI)
{
return (FCSPI_READ_BIT(pFCSPI->FIFO_STATUS, FCSPI_FIFO_STATUS_RXCNT_MASK) >> FCSPI_FIFO_STATUS_RXCNT_SHIFT);
}
LOCAL_INLINE void FCSPI_HWA_SetFrameSize(FCSPI_Type *pFCSPI, uint16 FrameSize)
{
FCSPI_MODIFY_REG(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_FRM_SZ_MASK, FrameSize - 1u);
}
LOCAL_INLINE void FCSPI_HWA_SetTransferWidth(FCSPI_Type *pFCSPI, FCSPI_TransferWidthType Width)
{
FCSPI_MODIFY_REG(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_WIDTH_MASK, ((uint32_t)Width << FCSPI_TR_CTRL_WIDTH_SHIFT) & FCSPI_TR_CTRL_WIDTH_MASK);
}
LOCAL_INLINE void FCSPI_HWA_EnableTxMask(FCSPI_Type *pFCSPI, bool enable)
{
enable ? FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_TX_MSK_MASK) : FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_TX_MSK_MASK);
}
LOCAL_INLINE void FCSPI_HWA_EnableRxMask(FCSPI_Type *pFCSPI, bool enable)
{
enable ? FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_RX_MSK_MASK) : FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_RX_MSK_MASK);
}
LOCAL_INLINE void FCSPI_HWA_EnableCTGO(FCSPI_Type *pFCSPI, bool enable)
{
enable ? FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_CT_GO_MASK) : FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_CT_GO_MASK);
}
LOCAL_INLINE void FCSPI_HWA_EnableCTEN(FCSPI_Type *pFCSPI, bool enable)
{
enable ? FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_CT_EN_MASK) : FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_CT_EN_MASK);
}
LOCAL_INLINE void FCSPI_HWA_EnableByteSwap(FCSPI_Type *pFCSPI, bool enable)
{
enable ? FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_BYSW_MASK) : FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_BYSW_MASK);
}
LOCAL_INLINE void FCSPI_HWA_SetDataFirstBit(FCSPI_Type *pFCSPI, FCSPI_DataFirstBitType eFirstBit)
{
if (FCSPI_MSB_FIRST == eFirstBit) {
FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_LSBF_MASK);
} else {
FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_LSBF_MASK);
}
}
LOCAL_INLINE void FCSPI_HWA_SelectPCS(FCSPI_Type *pFCSPI, FCSPI_PcsSelType PCSn)
{
FCSPI_MODIFY_REG(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_PCS_MASK, (uint32_t)PCSn << FCSPI_TR_CTRL_PCS_SHIFT);
}
LOCAL_INLINE void FCSPI_HWA_SetPrescale(FCSPI_Type *pFCSPI, FCSPI_PrescaleType PrescaleValue)
{
FCSPI_MODIFY_REG(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_PRESCALE_MASK, ((uint32_t)PrescaleValue << FCSPI_TR_CTRL_PRESCALE_SHIFT) & FCSPI_TR_CTRL_PRESCALE_MASK);
}
LOCAL_INLINE void FCSPI_HWA_SetSckPhase(FCSPI_Type *pFCSPI, FCSPI_SckPhaseType SckPhase)
{
if (FCSPI_SCK_SAMPLE_FIRST_EDGE == SckPhase) {
FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_SCK_PHA_MASK);
} else {
FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_SCK_PHA_MASK);
}
}
LOCAL_INLINE void FCSPI_HWA_SetSckPolarity(FCSPI_Type *pFCSPI, FCSPI_SckPolarityType SckPolarity)
{
if (FCSPI_SCK_IDLE_LOW == SckPolarity) {
FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_SCK_POL_MASK);
} else {
FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_SCK_POL_MASK);
}
}
LOCAL_INLINE void FCSPI_HWA_WriteTxData(FCSPI_Type *pFCSPI, uint32 TxData)
{
FCSPI_WRITE_REG(pFCSPI->TX_DATA, TxData);
}
LOCAL_INLINE bool FCSPI_HWA_GetFirstDataFlag(FCSPI_Type *pFCSPI)
{
return (bool)FCSPI_READ_BIT(pFCSPI->RX_STATUS, FCSPI_RX_STATUS_FD_MASK);
}
LOCAL_INLINE bool FCSPI_HWA_IsRxFIFOEmpty(FCSPI_Type *pFCSPI)
{
return (bool)(FCSPI_READ_BIT(pFCSPI->RX_STATUS, FCSPI_RX_STATUS_RX_EMPTY_MASK));
}
LOCAL_INLINE uint32 FCSPI_HWA_ReadRxData(FCSPI_Type *pFCSPI)
{
return FCSPI_READ_REG(pFCSPI->RX_DATA);
}
/** @}*/
#endif /* #if FCSPI_INSTANCE_COUNT > 0U */
#endif /* #ifndef _HWA_FCPIT_H_ */

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@ -0,0 +1,924 @@
/**
* @file HwA_fcuart.h
* @author Flagchip
* @brief FCUart register API
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip055 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip122 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_FCUART_H_
#define _HWA_FCUART_H_
#include "device_header.h"
#if FCUART_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_fcuart HwA_fcuart
* @ingroup module_driver_fcuart
* @{
*/
/********* Local typedef ************/
/**
* @brief UART STAT register flag
*
*/
typedef enum
{
FCUART_STAT_LBKDIF = FCUART_STAT_LBKDIF_MASK, /**< FCUART_STAT_LBKDIF LIN Break Detect Interrupt Flag, w1c */
FCUART_STAT_RPAEIF = FCUART_STAT_RPAEIF_MASK, /**< FCUART_STAT_RPAEIF RXD Pin Active Edge Interrupt Flag, w1c */
FCUART_STAT_MSBF = FCUART_STAT_MSBF_MASK, /**< FCUART_STAT_MSBF MSB First, RW */
FCUART_STAT_RXINV = FCUART_STAT_RXINV_MASK, /**< FCUART_STAT_RXINV Receive Data Inversion, RW */
FCUART_STAT_RWUID = FCUART_STAT_RWUID_MASK, /**< FCUART_STAT_RWUID Receive Wake Up Idle Detect, RW */
FCUART_STAT_BCGL = FCUART_STAT_BCGL_MASK, /**< FCUART_STAT_BCGL Break Character Generation Length, RW */
FCUART_STAT_LBKDE = FCUART_STAT_LBKDE_MASK, /**< FCUART_STAT_LBKDE LIN Break Detection Enable, RW */
FCUART_STAT_RAF = FCUART_STAT_RAF_MASK, /**< FCUART_STAT_RAF Receiver Active Flag, RO */
FCUART_STAT_TDREF = FCUART_STAT_TDREF_MASK, /**< FCUART_STAT_TDREF Transmit Data Register Empty Flag, RO */
FCUART_STAT_TCF = FCUART_STAT_TCF_MASK, /**< FCUART_STAT_TCF Transmission Complete Flag, RO */
FCUART_STAT_RDRFF = FCUART_STAT_RDRFF_MASK, /**< FCUART_STAT_RDRFF Receive Data Register Full Flag, RO */
FCUART_STAT_IDLEF = FCUART_STAT_IDLEF_MASK, /**< FCUART_STAT_IDLEF Idle Line Flag, w1c */
FCUART_STAT_RORF = FCUART_STAT_RORF_MASK, /**< FCUART_STAT_RORF Receiver Overrun Flag, w1c */
FCUART_STAT_NF = FCUART_STAT_NF_MASK, /**< FCUART_STAT_NF Noise Flag, w1c */
FCUART_STAT_FEF = FCUART_STAT_FEF_MASK, /**< FCUART_STAT_FEF Frame Error Flag, w1c */
FCUART_STAT_PEF = FCUART_STAT_PEF_MASK, /**< FCUART_STAT_PEF Parity Error Flag, w1c */
FCUART_STAT_M0F = FCUART_STAT_M0F_MASK, /**< FCUART_STAT_M0F Match address 0 Flag, w1c */
FCUART_STAT_M1F = FCUART_STAT_M1F_MASK, /**< FCUART_STAT_M1F Match address 1 Flag, w1c */
FCUART_STAT_RPEF = FCUART_STAT_RPEF_MASK, /**< FCUART_STAT_RPEF Receive Data Parity Error Flag, w1c */
FCUART_STAT_TPEF = FCUART_STAT_TPEF_MASK /**< FCUART_STAT_TPEF Transmit Data Parity Error Flag, w1c */
} FCUART_StatType;
/**
* @brief UART data bit length mode
*
*/
typedef enum
{
UART_BITMODE_8 = 0, /**< UART_BITMODE_8 */
UART_BITMODE_9 /**< UART_BITMODE_9 */
} FCUART_BitModeType;
/**
* @brief UART stop bits number
*
*/
typedef enum
{
UART_STOPBIT_NUM_1 = 0, /**< UART_STOPBIT_NUM_1 */
UART_STOPBIT_NUM_2 /**< UART_STOPBIT_NUM_2 */
} FCUART_StopBitNumType;
/**
* @brief UART parity check type
*
*/
typedef enum
{
UART_PARITY_EVEN = 0, /**< UART_PARITY_EVEN */
UART_PARITY_ODD /**< UART_PARITY_ODD */
} FCUART_ParityType;
/********* Local inline function ************/
/**
* @brief Get Stat Flag
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_SetSoftWareReset(FCUART_Type *pUart)
{
pUart->RST |= FCUART_RST_RST_MASK;
pUart->RST &= ~FCUART_RST_RST_MASK;
}
/**
* @brief Get Stat Flag
*
* @param pUart UART instance value
* @param eStatusType stat type
* @return FCUART STAT status flag
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetStatus(FCUART_Type *pUart, FCUART_StatType eStatusType)
{
return (pUart->STAT & (uint32_t)eStatusType);
}
/**
* @brief Clear Stat Flag
*
* @param pUart UART instance value
* @param u32StatusType stat type
*/
LOCAL_INLINE void FCUART_HWA_ClearStatus(FCUART_Type *pUart, uint32_t u32StatusType)
{
pUart->STAT = (u32StatusType | (pUart->STAT & FCUART_CHANGE_MASK));
}
/**
* @brief Enable Interrupt
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_EnableInterrupt(FCUART_Type *pUart, uint32 u32Value)
{
pUart->CTRL |= u32Value; /* Interrupt Enable */
}
/**
* @brief Disable Interrupt
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_DisableInterrupt(FCUART_Type *pUart, uint32 u32Value)
{
pUart->CTRL &= ~u32Value; /* Interrupt Disable */
}
/**
* @brief Enable Receive Interrupt
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_EnableReceiveInterrupt(FCUART_Type *pUart)
{
pUart->CTRL |= FCUART_CTRL_RIE_MASK; /* Receive Interrupt Enable */
}
/**
* @brief Disable Receive Interrupt
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_DisableReceiveInterrupt(FCUART_Type *pUart)
{
pUart->CTRL &= ~FCUART_CTRL_RIE_MASK; /* Receive Interrupt Enable */
}
/**
* @brief Enable Error Interrupt
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_EnableErrorInterrupt(FCUART_Type *pUart)
{
pUart->CTRL |= FCUART_CTRL_ORIE_MASK | /* Overrun Interrupt Enable */
FCUART_CTRL_NEIE_MASK | /* Noise Error Interrupt Enable */
FCUART_CTRL_FEIE_MASK | /* Frame Error Interrupt Enable */
FCUART_CTRL_PEIE_MASK; /* Parity Error Interrupt Enable */
}
/**
* @brief Disable Error Interrupt
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_DisableErrorInterrupt(FCUART_Type *pUart)
{
pUart->CTRL &= ~(FCUART_CTRL_ORIE_MASK | /* Overrun Interrupt Enable */
FCUART_CTRL_NEIE_MASK | /* Noise Error Interrupt Enable */
FCUART_CTRL_FEIE_MASK | /* Frame Error Interrupt Enable */
FCUART_CTRL_PEIE_MASK); /* Parity Error Interrupt Enable */
}
/**
* @brief Set FCUART Ctrl register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_SetCtrl(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->CTRL = u32Value;
}
/**
* @brief Get FCUART Ctrl register
*
* @param pUart UART instance value
* @return Register value
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetCtrl(FCUART_Type *pUart)
{
return pUart->CTRL;
}
/**
* @brief Attach FCUART Ctrl register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_AttachCtrl(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->CTRL |= u32Value;
}
/**
* @brief Set FCUART Baud register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_SetBaud(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->BAUD = u32Value;
}
/**
* @brief Get FCUART baud register
*
* @param pUart UART instance value
* @return Register value
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetBaud(FCUART_Type *pUart)
{
return pUart->BAUD;
}
/**
* @brief Attach FCUART Baud register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_AttachBaud(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->BAUD |= u32Value;
}
/**
* @brief Set FCUART Fifo register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_SetFifo(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->FIFO = u32Value;
}
/**
* @brief Get FCUART fifo register
*
* @param pUart UART instance value
* @return Register value
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetFifo(FCUART_Type *pUart)
{
return pUart->FIFO;
}
/**
* @brief Flush FCUART Tx Rx Fifo register
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_FlushTxRxFifo(FCUART_Type *pUart)
{
pUart->FIFO |= (FCUART_FIFO_TXFLUSH_MASK |
FCUART_FIFO_RXFLUSH_MASK);
}
/**
* @brief Get FCUART fifo register
*
* @param pUart UART instance value
* @return Register value
*/
LOCAL_INLINE bool FCUART_HWA_GetEnStatusRxFifo(FCUART_Type *pUart)
{
return ((((pUart->FIFO & FCUART_FIFO_RXFEN_MASK) >> FCUART_FIFO_RXFEN_SHIFT) == 1U) ? true: false);
}
/**
* @brief Get FCUART fifo register
*
* @param pUart UART instance value
* @return Register value
*/
LOCAL_INLINE bool FCUART_HWA_GetEnStatusTxFifo(FCUART_Type *pUart)
{
return ((((pUart->FIFO & FCUART_FIFO_TXFEN_MASK) >> FCUART_FIFO_TXFEN_SHIFT) == 1U) ? true: false);
}
/**
* @brief Attach FCUART Fifo register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_AttachFifo(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->FIFO |= u32Value;
}
/**
* @brief Set FCUART WaterMark register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_SetWaterMark(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->WATERMARK = u32Value;
}
/**
* @brief Get FCUART Rx WaterMark
*
* @param pUart UART instance value
* @return Rxcount value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetRxWaterMark(FCUART_Type *pUart)
{
return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_RXWATER_MASK) >> FCUART_WATERMARK_RXWATER_SHIFT));
}
/**
* @brief Get FCUART Tx WaterMark
*
* @param pUart UART instance value
* @return Rxcount value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetTxWaterMark(FCUART_Type *pUart)
{
return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_TXWATER_MASK) >> FCUART_WATERMARK_TXWATER_SHIFT));
}
/**
* @brief Get FCUART WaterMark Rxcount
*
* @param pUart UART instance value
* @return Rxcount value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetFifoRxCount(FCUART_Type *pUart)
{
return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_RXCOUNT_MASK) >> FCUART_WATERMARK_RXCOUNT_SHIFT));
}
/**
* @brief Get FCUART WaterMark Txcount
*
* @param pUart UART instance value
* @return Rxcount value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetFifoTxCount(FCUART_Type *pUart)
{
return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_TXCOUNT_MASK) >> FCUART_WATERMARK_TXCOUNT_SHIFT));
}
/**
* @brief Attach FCUART WaterMark register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_AttachWaterMark(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->WATERMARK |= u32Value;
}
/**
* @brief Set FCUART Match register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_SetMatch(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->MATCH = u32Value;
}
/**
* @brief Attach FCUART Match register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_AttachMatch(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->MATCH |= u32Value;
}
/**
* @brief Get FCUART Match register
*
* @param pUart UART instance value
* @return Register value
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetMatch(FCUART_Type *pUart)
{
return pUart->MATCH;
}
/**
* @brief Read FCUART STAT register
*
* @param pUart UART instance value
* @return STAT read value
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetSTAT(FCUART_Type *pUart)
{
return pUart->STAT;
}
/**
* @brief Write 1 Clear FCUART STAT register
*
* @param pUart UART instance value
* @param u32Value written value
*/
LOCAL_INLINE void FCUART_HWA_WriteClearSTAT(FCUART_Type *pUart, uint32_t u32Value)
{
pUart->STAT = ((pUart->STAT & FCUART_CHANGE_MASK) | u32Value);
}
/**
* @brief Set Bit Mode and Parity
*
* @param pUart UART instance value
* @param eBitMode is bit mode, 8 or 9 bits
*/
LOCAL_INLINE void FCUART_HWA_SetBitMode(FCUART_Type *pUart, FCUART_BitModeType eBitMode)
{
uint32_t u32RegVal = pUart->CTRL;
pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_BMSEL_MASK)) | FCUART_CTRL_BMSEL(eBitMode));
}
/**
* @brief Set Bit Mode and Parity
*
* @param pUart UART instance value
* @param bParityEnable If enable Parity, set 1U, or set 0U
* @param eParityType Parity type, odd-even
*/
LOCAL_INLINE void FCUART_HWA_SetParity(FCUART_Type *pUart, FCUART_ParityType eParityType, bool bParityEnable)
{
uint32_t u32RegVal = pUart->CTRL;
pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_PE_MASK | FCUART_CTRL_PT_MASK)) |
FCUART_CTRL_PE(bParityEnable) |
FCUART_CTRL_PT(eParityType) );
}
/**
* @brief Set Bit Mode and Parity
*
* @param pUart UART instance value
* @param eStopBit stop bits number 1 or 2 bits
*/
LOCAL_INLINE void FCUART_HWA_SetStopBit(FCUART_Type *pUart, FCUART_StopBitNumType eStopBit)
{
uint32_t u32RegVal = pUart->BAUD;
pUart->BAUD = ((u32RegVal & (~ FCUART_BAUD_SBNS_MASK)) | FCUART_BAUD_SBNS(eStopBit));
}
/**
* @brief Enable Receive DMA
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_EnableReceiveDMA(FCUART_Type *pUart)
{
pUart->BAUD |= FCUART_BAUD_RDMAEN_MASK;
}
/**
* @brief Disable Receive DMA
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_DisableReceiveDMA(FCUART_Type *pUart)
{
pUart->BAUD &= ~FCUART_BAUD_RDMAEN_MASK;
}
/**
* @brief Enable Receive FIFO
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_EnableReceiveFIFO(FCUART_Type *pUart)
{
pUart->FIFO |= FCUART_FIFO_RXFEN_MASK;
}
/**
* @brief Disable Receive FIFO
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_DisableReceiveFIFO(FCUART_Type *pUart)
{
pUart->FIFO &= ~FCUART_FIFO_RXFEN_MASK;
}
/**
* @brief Clear Fifo Overflow/Underflow flag
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_ClearFIFOErrorFlag(FCUART_Type *pUart)
{
pUart->FIFO |= FCUART_FIFO_TXOF_MASK | FCUART_FIFO_RXUF_MASK;
}
/**
* @brief Set FCUART Tx WaterMark
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_SetTxWaterMark(FCUART_Type *pUart, uint8_t u8Value)
{
uint32_t u32Value = 0;
u32Value = pUart->WATERMARK & (~(uint32_t)FCUART_WATERMARK_TXWATER_MASK);
u32Value |= FCUART_WATERMARK_TXWATER(u8Value);
pUart->WATERMARK = u32Value;
}
/**
* @brief Set FCUART Rx WaterMark
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_SetRxWaterMark(FCUART_Type *pUart, uint8_t u8Value)
{
uint32_t u32Value = 0;
u32Value = pUart->WATERMARK & (~(uint32_t)FCUART_WATERMARK_RXWATER_MASK);
u32Value |= FCUART_WATERMARK_RXWATER(u8Value);
pUart->WATERMARK = u32Value;
}
/**
* @brief Set Data Value
*
* @param pUart UART instance value
* @param u32Data Set data
*/
LOCAL_INLINE void FCUART_HWA_SetData(FCUART_Type *pUart, uint32_t u32Data)
{
pUart->DATA = u32Data; /* data 32 bit */
}
/**
* @brief Get Data Value
*
* @param pUart UART instance value
* @return the data value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetData(FCUART_Type *pUart)
{
uint8_t u8Data;
u8Data = *((volatile uint8_t *)&pUart->DATA); /* data 32 bit */
return u8Data;
}
/**
* @brief Get Data Value with check frame error flag
*
* @param pUart UART instance value
* @param data Received data
* @return the frame error exist or not
*/
LOCAL_INLINE bool FCUART_HWA_GetDataWithFef(FCUART_Type *pUart, uint8_t *data)
{
uint32_t u32Val;
u32Val = pUart->DATA;
*data = (uint8_t)u32Val;
return ((u32Val & FCUART_DATA_FETSC_MASK) == FCUART_DATA_FETSC_MASK) ? true : false;
}
/**
* @brief Set R8T9 bit
*
* @param pUart UART instance value
* @return the data value
*/
LOCAL_INLINE void FCUART_HWA_SetR8T9(FCUART_Type *pUart, uint8_t u8Data)
{
uint32_t u32RegVal = pUart->CTRL;
pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_R8T9_MASK)) | FCUART_CTRL_R8T9(u8Data));
}
/**
* @brief Get R8T9 bit
*
* @param pUart UART instance value
* @return the data value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetR8T9(FCUART_Type *pUart)
{
return (uint8_t)((pUart->CTRL & FCUART_CTRL_R8T9_MASK) >> FCUART_CTRL_R8T9_SHIFT);
}
/**
* @brief Set R9T8 bit
*
* @param pUart UART instance value
* @return the data value
*/
LOCAL_INLINE void FCUART_HWA_SetR9T8(FCUART_Type *pUart, uint8_t u8Data)
{
uint32_t u32RegVal = pUart->CTRL;
pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_R9T8_MASK)) | FCUART_CTRL_R9T8(u8Data));
}
/**
* @brief Get R9T8 bit
*
* @param pUart UART instance value
* @return the data value
*/
LOCAL_INLINE uint8_t FCUART_HWA_GetR9T8(FCUART_Type *pUart)
{
return (uint8_t)((pUart->CTRL & FCUART_CTRL_R9T8_MASK) >> FCUART_CTRL_R9T8_SHIFT);
}
/**
* @brief Reset the instance by software.
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_SoftwareReset(FCUART_Type *pUart)
{
pUart->RST |= FCUART_RST_RST_MASK;
pUart->RST &= ~FCUART_RST_RST_MASK;
}
/**
* @brief Set fcuart TX Transfer enable or disable.
*
* @param pUart UART instance value
* @param bEnable Enable cmd, false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetTxTransfer(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->CTRL |= FCUART_CTRL_TE_MASK;
}
else
{
pUart->CTRL &= ~FCUART_CTRL_TE_MASK;
}
}
/**
* \brief Start transmit
*
* \param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_StartTransmit(FCUART_Type *pUart)
{
pUart->CTRL |= FCUART_CTRL_TE_MASK; /* start transmit */
}
/**
* @brief Set fcuart RX Transfer enable or disable.
*
* @param pUart UART instance value
* @param bEnable Enable cmd, false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetRxTransfer(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->CTRL |= FCUART_CTRL_RE_MASK;
}
else
{
pUart->CTRL &= ~FCUART_CTRL_RE_MASK;
}
}
/**
* @brief Set fcuart start transfer.
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_StartTransfer(FCUART_Type *pUart)
{
pUart->CTRL |= (uint32_t)(FCUART_CTRL_TE_MASK | FCUART_CTRL_RE_MASK);
}
/**
* @brief Set fcuart stop transfer.
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_StopTransfer(FCUART_Type *pUart)
{
pUart->CTRL &= ~(uint32_t)(FCUART_CTRL_TE_MASK | FCUART_CTRL_RE_MASK);
}
/**
* @brief Set lin break detect interrupt.
*
* @param pUart UART instance value
* @param bEnable Enable cmd, false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetLinBreakDetectInterrupt(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->BAUD |= FCUART_BAUD_LBKDIE_MASK;
}
else
{
pUart->BAUD &= ~FCUART_BAUD_LBKDIE_MASK;
}
}
/**
* @brief Set lin break detect feature enable.
*
* @param pUart UART instance value
* @param bEnable Enable cmd, false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetLinBreakDetectEnable(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->STAT = ((FCUART_STAT_LBKDE_MASK | FCUART_STAT_BCGL_MASK)|(pUart->STAT & FCUART_CHANGE_MASK));
}
else
{
pUart->STAT &= ((~(FCUART_STAT_LBKDE_MASK | FCUART_STAT_BCGL_MASK))&FCUART_CHANGE_MASK);
}
}
/**
* @brief Send a lin break field.
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_SendBreakField(FCUART_Type *pUart)
{
pUart->DATA = FCUART_DATA_FETSC_MASK;
}
/**
* @brief Set uart receive active interrupt.
*
* @param pUart UART instance value
* @param bEnable Enable cmd, false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetReceiveActiveInterrupt(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->BAUD |= FCUART_BAUD_RIAEIE_MASK;
}
else
{
pUart->BAUD &= ~FCUART_BAUD_RIAEIE_MASK;
}
}
/**
* @brief Set uart receive active interrupt.
*
* @param pUart UART instance value
* @param return false for disable, true for enable.
*/
LOCAL_INLINE bool FCUART_HWA_GetReceiveActiveInterrupt(FCUART_Type *pUart)
{
bool bRetVal = false;
if (0U != (pUart->BAUD & FCUART_BAUD_RIAEIE_MASK))
{
bRetVal = true;
}
return bRetVal;
}
/**
* @brief Set FCUART inverse feature.
*
* @param pUart UART instance value
* @param bEnable false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetReceiveDataInverse(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->STAT = (FCUART_STAT_RXINV_MASK | (pUart->STAT & FCUART_CHANGE_MASK));
}
else
{
pUart->STAT &= ((~FCUART_STAT_RXINV_MASK)&FCUART_CHANGE_MASK);
}
}
/**
* @brief Get the FCUART inverse bit value.
*
* @param pUart UART instance value
* @param return false for disable, true for enable.
*/
LOCAL_INLINE bool FCUART_HWA_GetReceiveDataInverse(FCUART_Type *pUart)
{
bool bRetVal = false;
if (0U != (pUart->STAT & FCUART_STAT_RXINV_MASK))
{
bRetVal = true;
}
return bRetVal;
}
/**
* @brief Set the FCUART frame error interrupt.
*
* @param pUart UART instance value
* @param bEnable false for disable, true for enable.
*/
LOCAL_INLINE void FCUART_HWA_SetFrameErrorInterrupt(FCUART_Type *pUart, bool bEnable)
{
if (true == bEnable)
{
pUart->CTRL |= FCUART_CTRL_FEIE_MASK;
}
else
{
pUart->CTRL &= ~FCUART_CTRL_FEIE_MASK;
}
}
/**
* @brief Enable the FCUART loop mode.
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_EnableLoopMode(FCUART_Type *pUart)
{
pUart->CTRL |= FCUART_CTRL_LOOPMS_MASK;
}
/**
* @brief Disable the FCUART loop mode.
*
* @param pUart UART instance value
*/
LOCAL_INLINE void FCUART_HWA_DisableLoopMode(FCUART_Type *pUart)
{
pUart->CTRL &= ~FCUART_CTRL_LOOPMS_MASK;
}
/**
* \brief Set FCUART MODIR value
*
* \param pUart UART instance value
* \param u32Data Set data
*/
LOCAL_INLINE void FCUART_HWA_SetModir(FCUART_Type *pUart, uint32_t u32Data)
{
pUart->HFCR = u32Data; /* data 32 bit */
}
/**
* \brief Get FCUART MODIR value
*
* \param pUart UART instance value
* \param u32Data Get data
*/
LOCAL_INLINE uint32_t FCUART_HWA_GetModir(FCUART_Type *pUart)
{
return pUart->HFCR ;
}
/** @}*/
#endif
#endif /* end for #ifndef _HWA_FCUART_H_ */

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/**
* @file HwA_freqm.h
* @author Flagchip0100
* @brief FREQM Module Register API
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright 2020-2024 Flagchip Semiconductors Co., Ltd.
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip087 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip100 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_FREQM_H_
#define _HWA_FREQM_H_
#include "device_header.h"
#if (FREQM_INSTANCE_COUNT > 0U)
/**
* @defgroup HwA_freqm HwA_freqm
* @ingroup module_driver_freqm
* @{
*/
#if defined(__cplusplus)
extern "C" {
#endif
/**
* @defgroup HwA_freqm
* @{
*/
/*******************************************************************************
* Local inline function
******************************************************************************/
/**
* @brief Set the measured clock selection.
*
* @param pFreqm the base address of the FREQM.
* @param u8ClkSel the clock selection index.
*/
LOCAL_INLINE void FREQM_HWA_MesClkSel(FREQM_Type *const pFreqm, uint8_t u8ClkSel)
{
pFreqm->CTRL = (pFreqm->CTRL & ~((uint32_t)FREQM_CTRL_MES_CLK_SEL_MASK)) | FREQM_CTRL_MES_CLK_SEL(u8ClkSel);
}
/**
* @brief Set the clock selection.
*
* @param pFreqm the base address of the FREQM.
* @param u8PredivVal the measure clock prediv value.
*/
LOCAL_INLINE void FREQM_HWA_MesClk_PreDiv(FREQM_Type *const pFreqm, uint8_t u8PredivVal)
{
pFreqm->CTRL = (pFreqm->CTRL & ~((uint32_t)FREQM_CTRL_MES_CLK_PREDIV_MASK)) | FREQM_CTRL_MES_CLK_PREDIV(u8PredivVal);
}
/**
* @brief Enable count event interrupt.
*
* @param pFreqm the base address of the FREQM.
*/
LOCAL_INLINE void FREQM_HWA_EnableCntEventInterrupt(FREQM_Type *const pFreqm)
{
pFreqm->CTRL |= FREQM_CTRL_CNT_EVENT_IE_MASK;
}
/**
* @brief Disable count event interrupt.
*
* @param pFreqm the base address of the FREQM.
*/
LOCAL_INLINE void FREQM_HWA_DisableCntEventInterrupt(FREQM_Type *const pFreqm)
{
pFreqm->CTRL &= ~((uint32_t)FREQM_CTRL_CNT_EVENT_IE_MASK);
}
/**
* @brief Set counting length of measure counter.
*
* @param pFreqm the base address of the FREQM.
* @param u32MesLen counting length of measure counter.
*/
LOCAL_INLINE void FREQM_HWA_SetMesLength(FREQM_Type *const pFreqm, uint32_t u32MesLen)
{
pFreqm->MES_LENGTH = u32MesLen;
}
/**
* @brief Set timeout value of reference counter.
*
* @param pFreqm the base address of the FREQM.
* @param u32RefTo timeout value of reference counter.
*/
LOCAL_INLINE void FREQM_HWA_SetRefTimeout(FREQM_Type *const pFreqm, uint32_t u32RefTo)
{
pFreqm->REF_TIMEOUT = u32RefTo;
}
/**
* @brief Set value of reference counter.
*
* @param pFreqm the base address of the FREQM.
* @param u32RefCnt value of reference counter.
*/
LOCAL_INLINE void FREQM_HWA_SetRefCnt(FREQM_Type *const pFreqm, uint32_t u32RefCnt)
{
pFreqm->REF_CNT = u32RefCnt;
}
/**
* @brief Clear counter event interrupt flag.
*
* @param pFreqm the base address of the FREQM.
*/
LOCAL_INLINE void FREQM_HWA_ClearInterruptFlag(FREQM_Type *const pFreqm)
{
pFreqm->CNT_STATUS = FREQM_CNT_STATUS_CNT_EVENT_MASK;
}
/**
* @brief Get counter event interrupt flag
*
* @param pFreqm the base address of the FREQM
* @return false for disable, true for enable.
*/
LOCAL_INLINE bool FREQM_HWA_GetInterruptFlag(const FREQM_Type *const pFreqm)
{
return ((pFreqm->CNT_STATUS & FREQM_CNT_STATUS_CNT_EVENT_MASK) == FREQM_CNT_STATUS_CNT_EVENT_MASK) ? true : false;
}
/**
* @brief Get counter status
*
* @param pFreqm the base address of the FREQM
* @return Counter status.
*/
LOCAL_INLINE uint32_t FREQM_HWA_GetCntStatus(const FREQM_Type *const pFreqm)
{
return (pFreqm->CNT_STATUS & (FREQM_CNT_STATUS_MES_CNT_START_MASK | FREQM_CNT_STATUS_MES_CNT_STOP_MASK | FREQM_CNT_STATUS_REF_CNT_STOP_MASK));
}
/**
* @brief Set value of measure counter.
*
* @param pFreqm the base address of the FREQM.
* @param u32MesCnt value of measure counter.
*/
LOCAL_INLINE void FREQM_HWA_SetMesCnt(FREQM_Type *const pFreqm, uint32_t u32MesCnt)
{
pFreqm->MES_CNT = u32MesCnt;
}
/**
* @brief Get saved reference counter value.
*
* @param pFreqm the base address of the FREQM.
* @return saved reference counter value.
*/
LOCAL_INLINE uint32_t FREQM_HWA_GetRefCntSave(const FREQM_Type *const pFreqm)
{
return pFreqm->REF_CNT_SAVE;
}
/** @}*/ /* HwA_freqm */
#if defined(__cplusplus)
}
#endif
/** @}*/
#endif /* (FREQM_INSTANCE_COUNT > 0U) */
#endif /* _HWA_FREQM_H_ */

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/**
* @file HwA_gpio.h
* @author Flagchip
* @brief GPIO hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip071 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip071 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_GPIO_H_
#define _HWA_GPIO_H_
#include "device_header.h"
#if GPIO_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_gpio HwA_gpio
* @ingroup module_driver_gpio
* @{
*/
/**
* @brief Set port output to 1
*
* @param pGpio Gpio instance
* @param u32Pins Pin numbers
*/
LOCAL_INLINE void GPIO_HWA_SetPortOutput(GPIO_Type *pGpio, uint32_t u32Pins)
{
pGpio->PSOR = u32Pins;
}
/**
* @brief Set port output to 0
*
* @param pGpio Gpio instance
* @param u32Pins Pin numbers
*/
LOCAL_INLINE void GPIO_HWA_ClearPortOutput(GPIO_Type *pGpio, uint32_t u32Pins)
{
pGpio->PCOR = u32Pins;
}
/**
* @brief Toggle port output
*
* @param pGpio Gpio instance
* @param u32Pins Pin numbers
*/
LOCAL_INLINE void GPIO_HWA_TogglePort(GPIO_Type *pGpio, uint32_t u32Pins)
{
pGpio->PTOR = u32Pins;
}
/**
* @brief Set port direction Input
*
* @param pGpio Gpio instance
* @param u32Pins Pin numbers
*/
LOCAL_INLINE void GPIO_HWA_SetPortDirectionInput(GPIO_Type *pGpio, uint32_t u32Pins)
{
pGpio->PDDR &= (~u32Pins);
}
/**
* @brief Set port direction output
*
* @param pGpio Gpio instance
* @param u32Pins Pin numbers
*/
LOCAL_INLINE void GPIO_HWA_SetPortDirectionOutput(GPIO_Type *pGpio, uint32_t u32Pins)
{
pGpio->PDDR |= u32Pins;
}
/**
* @brief Read port data input, this register indicate data on pad.
*
* @param pGpio Gpio instance
* @return PDIR register value
*/
LOCAL_INLINE uint32_t GPIO_HWA_ReadPortDataInput(GPIO_Type *pGpio)
{
return pGpio->PDIR;
}
/**
* @brief Set pin output to 1
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_SetPinOutput(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PSOR = (uint32_t)1 << u8Pin;
}
/**
* @brief Set pin output to 0
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_ClearPinOutput(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PCOR = (uint32_t)1 << u8Pin;
}
/**
* @brief Set pin direction
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_SetPinDirection(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PDDR |= (uint32_t)1 << u8Pin;
}
/**
* @brief Clear pin direction
*
* @param pGpio Gpio instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void GPIO_HWA_ClearPinDirection(GPIO_Type *pGpio, uint8_t u8Pin)
{
pGpio->PDDR &= ~((uint32_t)1 << u8Pin);
}
/** @}*/
#endif
#endif /* #ifndef _HWA_GPIO_H_ */

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/**
* @file HwA_hrpwm.h
* @author Flagchip
* @brief HRPWM hardware access layer
* @version 2.0.0
* @date 2024-11-06
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip070 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip070 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_HRPWM_H_
#define _HWA_HRPWM_H_
#include "device_header.h"
#if defined(HRPWM_INSTANCE_COUNT) && (HRPWM_INSTANCE_COUNT > 0U)
/**
* @defgroup HwA_hrpwm HwA_hrpwm
* @ingroup module_driver_hrpwm
* @{
*/
/* Define the unlock write code for the HRPWM module, used to unlock HRPWM registers for configuration */
#define HRPWM_UNLOCK_WRITE_CODE 0x10248888U
/* Define the lock write code for the HRPWM module, used to lock HRPWM registers to protect configuration */
#define HRPWM_LOCK_WRITE_CODE 0x1024CAFEU
/**
* @brief Enable or disable an HRPWM channel
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param u8Channel The HRPWM channel number to control
* @param bEnable True to enable the channel, False to disable the channel
*/
LOCAL_INLINE void HRPWM_HWA_SetChannelEnable(HRPWM_Type * const pHrpwm, uint8_t u8Channel, bool bEnable)
{
pHrpwm->EN_CTRL = (pHrpwm->EN_CTRL & (~(1U << u8Channel))) | ((uint32_t)bEnable << u8Channel);
}
/**
* @brief Set bypass mode for an HRPWM channel
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param u8Channel The HRPWM channel number to control
* @param bBypass True to enable bypass mode, False to disable bypass mode
*/
LOCAL_INLINE void HRPWM_HWA_SetChannelBypass(HRPWM_Type * const pHrpwm, uint8_t u8Channel, bool bBypass)
{
pHrpwm->BYPASS_CTRL = (pHrpwm->BYPASS_CTRL & (~(1U << u8Channel))) | ((uint32_t)bBypass << u8Channel);
}
/**
* @brief Set Fault bypass enable for an HRPWM channel
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param u8Channel The HRPWM channel number to control
* @param bBypass True to enable HRPWM fault, False to disable HRPWM fault
*/
LOCAL_INLINE void HRPWM_HWA_SetChannelFaultEnable(HRPWM_Type * const pHrpwm, uint8_t u8Channel, bool bBypass)
{
pHrpwm->FAULT_BYPASS_CTRL = (pHrpwm->FAULT_BYPASS_CTRL & (~(1U << u8Channel))) | ((uint32_t)bBypass << u8Channel);
}
/**
* @brief Enable or disable the internal LDO
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param bEnable True to enable the internal LDO, False to disable the internal LDO
*/
LOCAL_INLINE void HRPWM_HWA_SetInternalLDOEnable(HRPWM_Type * const pHrpwm, bool bEnable)
{
pHrpwm->ANA_CTRL = (pHrpwm->ANA_CTRL & (~HRPWM_ANA_CTRL_PH_LDOEN_MASK)) | HRPWM_ANA_CTRL_PH_LDOEN(bEnable);
}
/**
* @brief Set bypass mode for the internal LDO
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param bEnable True to enable LDO bypass mode, False to disable LDO bypass mode
*/
LOCAL_INLINE void HRPWM_HWA_SetInternalLDOBypass(HRPWM_Type * const pHrpwm, bool bEnable)
{
pHrpwm->ANA_CTRL = (pHrpwm->ANA_CTRL & (~HRPWM_ANA_CTRL_PH_LDOBYPASSEN_MASK)) | HRPWM_ANA_CTRL_PH_LDOBYPASSEN(bEnable);
}
/**
* @brief Enable or disable phase generation
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param bEnable True to enable phase generation, False to disable phase generation
*/
LOCAL_INLINE void HRPWM_HWA_SetPhaseGeneration(HRPWM_Type * const pHrpwm, bool bEnable)
{
pHrpwm->ANA_CTRL = (pHrpwm->ANA_CTRL & (~HRPWM_ANA_CTRL_PH_EN_MASK)) | HRPWM_ANA_CTRL_PH_EN(bEnable);
}
/**
* @brief Set the value of the ANA_CTRL register
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param u32Value The value to set for the ANA_CTRL register
*/
LOCAL_INLINE void HRPWM_HWA_SetANACtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value)
{
pHrpwm->ANA_CTRL = u32Value;
}
/**
* @brief Get the value of the ANA_CTRL register
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @return uint32_t The value of the ANA_CTRL register
*/
LOCAL_INLINE uint32_t HRPWM_HWA_GetANACtrl(HRPWM_Type * const pHrpwm)
{
return pHrpwm->ANA_CTRL;
}
/**
* @brief Check if the analog power is OK
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @return true If the analog power is OK, otherwise false
*/
LOCAL_INLINE bool HRPWM_HWA_GetAnolagPowerOK(HRPWM_Type * const pHrpwm)
{
return (bool)((pHrpwm->ANA_CTRL & HRPWM_ANA_CTRL_ANA_POWER_OK_MASK) >> HRPWM_ANA_CTRL_ANA_POWER_OK_SHIFT);
}
/**
* @brief Check if phase generation is locked
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @return true If phase generation is locked, otherwise false
*/
LOCAL_INLINE bool HRPWM_HWA_GetPhaseGenLock(HRPWM_Type * const pHrpwm)
{
return (bool)pHrpwm->ANA_CTRL & HRPWM_ANA_CTRL_PH_LOCK_MASK;
}
/**
* @brief Unlock HRPWM registers for write operations
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
*/
LOCAL_INLINE void HRPWM_HWA_UnlockRegisterWrite(HRPWM_Type * const pHrpwm)
{
pHrpwm->LOCK_CTRL = HRPWM_UNLOCK_WRITE_CODE;
}
/**
* @brief Lock HRPWM registers to prevent write operations
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
*/
LOCAL_INLINE void HRPWM_HWA_LockRegisterWrite(HRPWM_Type * const pHrpwm)
{
pHrpwm->LOCK_CTRL = HRPWM_LOCK_WRITE_CODE;
}
/**
* @brief Set fault software release mode
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param u8Channel The HRPWM channel number to configure
* @param bSwRelease True: fault release by writing FAULT_STATUS, False: fault release without software
*/
LOCAL_INLINE void HRPWM_HWA_SetSWFaultRelease(HRPWM_Type * const pHrpwm, uint8_t u8Channel, bool bSwRelease)
{
pHrpwm->FAULT_SW_CTRL_EN = (pHrpwm->FAULT_SW_CTRL_EN & (~(1U << u8Channel))) | ((uint32_t)bSwRelease << u8Channel);
}
/**
* @brief Get fault status
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @return uint8_t The current fault status
*/
LOCAL_INLINE uint8_t HRPWM_HWA_GetFaultStatus(HRPWM_Type * const pHrpwm)
{
return (uint8_t)(pHrpwm->FAULT_STATUS & HRPWM_FAULT_STATUS_MASK);
}
/**
* @brief Clear fault status
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param u8Mask The fault status mask to clear
*/
LOCAL_INLINE void HRPWM_HWA_ClearFaultStatus(HRPWM_Type * const pHrpwm, uint8_t u8Mask)
{
pHrpwm->FAULT_STATUS = (uint32_t)u8Mask;
}
/**
* @brief Set the value of the EN_CTRL register
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param u32Value The value to set for the EN_CTRL register
*/
LOCAL_INLINE void HRPWM_HWA_SetENCtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value)
{
pHrpwm->EN_CTRL = u32Value;
}
/**
* @brief Set the value of the BYPASS_CTRL register
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param u32Value The value to set for the BYPASS_CTRL register
*/
LOCAL_INLINE void HRPWM_HWA_SetBypassCtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value)
{
pHrpwm->BYPASS_CTRL = u32Value;
}
/**
* @brief Set the value of the FAULT_BYPASS_CTRL register
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param u32Value The value to set for the FAULT_BYPASS_CTRL register
*/
LOCAL_INLINE void HRPWM_HWA_SetFltBypassCtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value)
{
pHrpwm->FAULT_BYPASS_CTRL = u32Value;
}
/**
* @brief Set the value of the FAULT_SW_CTRL_EN register
*
* @param pHrpwm Base address pointer of the HRPWM peripheral
* @param u32Value The value to set for the FAULT_SW_CTRL_EN register
*/
LOCAL_INLINE void HRPWM_HWA_SetFltSWCtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value)
{
pHrpwm->FAULT_SW_CTRL_EN = u32Value;
}
/** @}*/
#endif /* defined(HRPWM_INSTANCE_COUNT) && (HRPWM_INSTANCE_COUNT > 0U) */
#endif /* _HWA_HRPWM_H_ */

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/**
* @file HwA_intm.h
* @author flagchip
* @brief Interrupt monitor
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip084 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_INTM_H_
#define _HWA_INTM_H_
#include "device_header.h"
#if INTM_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_fciic HwA_fciic
* @ingroup module_driver_fciic
* @{
*/
typedef struct
{
__IO uint32_t IRQSELR; /**< INTM Interrupt Request Select Register*/
__IO uint32_t LATR; /**< INTM Latency Register */
__IO uint32_t TMR; /**< INTM Timer Register */
__I uint32_t SR; /**< INTM Status Register */
} INTM_MonitorType, *INTM_MonitorMemMapPtr;
/**
* @brief Enable the INTM.
* @param pIntm INTM instance. INTM instance.
* @param bEnable Enable the ITNM.
*/
LOCAL_INLINE void INTM_HWA_Enable(INTM_Type *const pIntm, bool bEnable)
{
if (bEnable)
{
pIntm->ER = INTM_ER_EN_MASK;
}
else
{
pIntm->ER = 0U;
}
}
/**
* @brief Get the instance of interrupt monitor.
* @param pIntm INTM instance.
* @param u8IrqMonitorIndex Interrupt monitor index.
* @return Monitor Instance.
*/
LOCAL_INLINE INTM_MonitorType *INTM_HWA_GetIrqMonitor(INTM_Type *const pIntm, uint8_t u8IrqMonitorIndex)
{
return (INTM_MonitorType *)((uint32_t) & (pIntm->IRQSELR0) + (uint32_t)u8IrqMonitorIndex * 0x10U);
}
/**
* @brief Set the interrupt acknowledge.
* @param pIntm INTM instance.
* @param u16IrqNum Interrupt number to be monitored.
*/
LOCAL_INLINE void INTM_HWA_SetIACKR(INTM_Type *const pIntm, uint16_t u16IrqNum)
{
pIntm->IACKR = u16IrqNum;
}
/**
* @brief Set which interrupt to be monoterd.
* @param pIrqMon Interrupt monitor instance.
* @param u16IrqNum Interrupt number to be monitored.
*/
LOCAL_INLINE void INTM_HWA_SetIRQReqNum(INTM_MonitorType *const pIrqMon, uint16_t u16IrqNum)
{
pIrqMon->IRQSELR = u16IrqNum;
}
/**
* @brief Enable reset when interrupt delays overtime.
* @param pIrqMon Interrupt monitor instance.
* @param bEnable Enable reset.
*/
LOCAL_INLINE void INTM_HWA_EnableReset(INTM_MonitorType *const pIrqMon, bool bEnable)
{
pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_RSTE_MASK) | INTM_IRQSELR_RSTE(bEnable);
}
/**
* @brief Enable interrupt when monitored interrupt delays overtime.
* @param pIrqMon Interrupt monitor instance.
* @param bEnable Enabel the interrupt.
*/
LOCAL_INLINE void INTM_HWA_EnableInterrupt(INTM_MonitorType *const pIrqMon, bool bEnable)
{
pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_INTE_MASK) | INTM_IRQSELR_INTE(bEnable);
}
/**
* @brief Enable inactive mode.
* @param pIrqMon Interrupt monitor instance.
* @param bEnable Enable inactive mode.
*/
LOCAL_INLINE void INTM_HWA_EnableInactiveMode(INTM_MonitorType *const pIrqMon, bool bEnable)
{
pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_IACTE_MASK) | INTM_IRQSELR_IACTE(bEnable);
}
/**
* @brief Start the inactive mode.
* @param pIrqMon Interrupt monitor instance.
*/
LOCAL_INLINE void INTM_HWA_StartInactiveMode(INTM_MonitorType *const pIrqMon)
{
pIrqMon->IRQSELR |= INTM_IRQSELR_IACTST_MASK;
__asm volatile(
"dmb \n"
"ldr r8, [%[IRQSELR]] \n"/* Must Read IRQSELR after set. */
: : [IRQSELR] "r"(&pIrqMon->IRQSELR) : "r8", "memory"
);
}
/**
* @brief Stop the inactive mode.
* @param pIrqMon Interrupt monitor instance.
*/
LOCAL_INLINE void INTM_HWA_StopInactiveMode(INTM_MonitorType *const pIrqMon)
{
pIrqMon->IRQSELR &= ~INTM_IRQSELR_IACTST_MASK;
}
/**
* @brief Set the timeout value of interrupt.
* @param pIrqMon Interrupt monitor instance.
* @param u32Latency the timeout value of interrupt monitor.
*/
LOCAL_INLINE void INTM_HWA_SetLatency(INTM_MonitorType *const pIrqMon, uint32_t u32Latency)
{
pIrqMon->LATR = u32Latency;
}
/**
* @brief Get the value of timer.
* @param pIrqMon Interrupt monitor instance.
* @return Timer value
*/
LOCAL_INLINE uint32_t INTM_HWA_GetTimerCounter(INTM_MonitorType *const pIrqMon)
{
return pIrqMon->TMR;
}
/**
* @brief Set the value of timer.
* @param pIrqMon Interrupt monitor instance.
* @param u32Value The value to be set.
*/
LOCAL_INLINE void INTM_HWA_SetTimerCounter(INTM_MonitorType *const pIrqMon, uint32_t u32Value)
{
pIrqMon->TMR = u32Value;
}
/**
* @brief Read interrupt status.
* @param pIrqMon Interrupt monitor instance.
* @return Interrupt status.
*/
LOCAL_INLINE bool INTM_HWA_ReadStatus(INTM_MonitorType *const pIrqMon)
{
return (pIrqMon->SR & INTM_SR_MASK) == INTM_SR_MASK ? true : false;
}
/** @}*/
#endif /* #if INTM_INSTANCE_COUNT > 0U */
#endif /*#ifndef _HWA_INTM_H_*/

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/**
* @file HwA_ism.h
* @author flagchip
* @brief ISM hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip084 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_ISM_H_
#define _HWA_ISM_H_
#include "device_header.h"
#if ISM_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_ism HwA_ism
* @ingroup module_driver_ism
* @{
*/
/********* macros ************/
/********* Local typedef ************/
typedef struct
{
__IO uint32_t FPC_STATUS;
__IO uint32_t FPC_CTRL;
__IO uint32_t FPC_CONFIG;
__IO uint32_t FPC_TIMER;
} FPC_Type, *FPC_MemMapPtr;
typedef struct
{
__IO uint32_t LAM_STATUS;
__IO uint32_t LAM_CTRL;
__IO uint32_t LAM_CONFIG;
__IO uint32_t LAM_CONTER;
} LAM_Type, *LAM_MemMapPtr;
typedef enum
{
ISM_FPC_DETECT_NO_FILTER = 0U, /**< No filter mode. Copy input to SOUT directly, which is LAM input.*/
ISM_FPC_DETECT_IMMI_FILTER = 1U, /**< Immediate filter mode.*/
ISM_FPC_DETECT_DELAY_MODE = 2U, /**< Delay mode.*/
ISM_FPC_DETECT_PRESCALER_MODE = 3U /**< Prescaler mode.*/
} ISM_FPC_EdgeDetectModeType;
typedef enum
{
ISM_FPC_DELAY_FIXED0 = 0U, /**< Fixed delay mode.*/
ISM_FPC_DELAY_FIXED1 = 1U, /**< Fixed delay mode.*/
ISM_FPC_DELAY_SMART_DELAY0 = 2U, /**< Smart delay mode. The counter is decremented when a glitch happens.*/
ISM_FPC_DELAY_SMART_DELAY1 = 3U /**< Smart delay mode. The counter is reset when a glitch happens.*/
} ISM_FPC_EdgeDelayModeType;
typedef enum
{
ISM_LAM_EVT_WIN_NON_INVERT = 0U, /**< Event window non-inverted.*/
ISM_LAM_EVT_WIN_INVERT = 1U /**< Event window inverted.*/
} ISM_LAM_InvertEventWindowType;
typedef enum
{
ISM_LAM_NTR_CLEAR_NTR_GATE = 0U, /**< Neither edge used to clear the event window counter. Neither edge used to gate event generation.*/
ISM_LAM_POS_CLEAR_NTR_GATE = 1U, /**< Positive edge used to clear the event window counter. Neither edge used to gate event generation.*/
ISM_LAM_NEG_CLEAR_NTR_GATE = 2U, /**< Negative edge used to clear the event window counter. Neither edge used to gate event generation.*/
ISM_LAM_ETR_CLEAR_NTR_GATE = 3U, /**< Either edge used to clear the event window counter. Neither edge used to gate event generation.*/
ISM_LAM_NTR_CLEAR_POS_GATE = 4U, /**< Neither edge used to clear the event window counter. Positive edge used to gate event generation.*/
ISM_LAM_POS_CLEAR_POS_GATE = 5U, /**< Positive edge used to clear the event window counter. Positive edge used to gate event generation.*/
ISM_LAM_NEG_CLEAR_POS_GATE = 6U, /**< Negative edge used to clear the event window counter. Positive edge used to gate event generation.*/
ISM_LAM_ETR_CLEAR_POS_GATE = 7U, /**< Either edge used to clear the event window counter. Positive edge used to gate event generation.*/
ISM_LAM_NTR_CLEAR_NEG_GATE = 8U, /**< Neither edge used to clear the event window counter. Negative edge used to gate event generation.*/
ISM_LAM_POS_CLEAR_NEG_GATE = 9U, /**< Positive edge used to clear the event window counter. Negative edge used to gate event generation.*/
ISM_LAM_NEG_CLEAR_NEG_GATE = 10U, /**< Negative edge used to clear the event window counter. Negative edge used to gate event generation.*/
ISM_LAM_ETR_CLEAR_NEG_GATE = 11U, /**< Either edge used to clear the event window counter. Negative edge used to gate event generation.*/
ISM_LAM_NTR_CLEAR_ETR_GATE = 12U, /**< Neither edge used to clear the event window counter. Either edge used to gate event generation.*/
ISM_LAM_POS_CLEAR_ETR_GATE = 13U, /**< Positive edge used to clear the event window counter. Either edge used to gate event generation.*/
ISM_LAM_NEG_CLEAR_ETR_GATE = 14U, /**< Negative edge used to clear the event window counter. Either edge used to gate event generation.*/
ISM_LAM_ETR_CLEAR_ETR_GATE = 15U /**< Either edge used to clear the event window counter. Either edge used to gate event generation.*/
} ISM_LAM_EventWindowEdgeType;
typedef enum
{
ISM_LAM_EVT_WIN_SEL_REF = 0U, /**< Event window generation is determined from the reference signal.*/
ISM_LAM_EVT_WIN_SEL_MON = 1U /**< Event window generation is determined from the monitor signal.*/
} ISM_LAM_EventWindowSelectType;
typedef enum
{
ISM_LAM_RUN_FREE = 0U, /**< Event window generation is free-running.*/
ISM_LAM_RUN_GATED = 1U /**< Event window generation is gated with the monitor or reference signal.*/
} ISM_LAM_RunModeSelectType;
typedef enum
{
ISM_LAM_SRC_FPC_MON = 0U, /**< Monitor signal is sourced directly from FPC monitor channel.*/
ISM_LAM_SRC_EXORD_FPC_REF = 1U /**< Monitor signal is EXOR'd with FPC reference channel.*/
} ISM_LAM_MonitorSourceType;
typedef enum
{
ISM_LAM_FPC_MON_NON_INVERT = 0U, /**< Do not invert the monitor signal from FPC.*/
ISM_LAM_FPC_MON_INVERT = 1U /**< Invert the monitor signal from FPC.*/
} ISM_LAM_InvertMonitorType;
typedef enum
{
ISM_LAM_FPC_REF_NON_INVERT = 0U, /**< Do not invert the reference signal from FPC.*/
ISM_LAM_FPC_REF_INVERT = 1U /**< Invert the reference signal from FPC.*/
} ISM_LAM_InvertReferenceType;
/********* Local inline function ************/
/********* ISM Register interface ************/
/**
* @brief Get ISM ECM count
*
* @param pIsm ISM Instance
* @return ECM count
*/
LOCAL_INLINE uint8_t ISM_HWA_PARAM_ECMC(ISM_Type *const pIsm)
{
return (uint8_t)((pIsm->PARAM & ISM_PARAM_ECMC_MASK) >> ISM_PARAM_ECMC_SHIFT);
}
/**
* @brief Get ISM FPC count
*
* @param pIsm ISM Instance
* @return FPC count
*/
LOCAL_INLINE uint8_t ISM_HWA_PARAM_FPC(ISM_Type *const pIsm)
{
return (uint8_t)((pIsm->PARAM & ISM_PARAM_FPC_MASK) >> ISM_PARAM_FPC_SHIFT);
}
/**
* @brief Get ISM LAM count
*
* @param pIsm ISM Instance
* @return LAM count
*/
LOCAL_INLINE uint8_t ISM_HWA_PARAM_LAM(ISM_Type *const pIsm)
{
return (uint8_t)((pIsm->PARAM & ISM_PARAM_LAM_MASK) >> ISM_PARAM_LAM_SHIFT);
}
/**
* @brief Enable ISM
*
* @param pIsm ISM Instance
* @param bEnable EN value
*/
LOCAL_INLINE void ISM_HWA_Enable(ISM_Type *const pIsm, bool bEnable)
{
pIsm->CTRL = (pIsm->CTRL & ~ISM_CTRL_EN_MASK) | ISM_CTRL_EN(bEnable);
}
/**
* @brief Enable ISM Interrupt
*
* @param pIsm ISM Instance
* @param bEnable IEN value
*/
LOCAL_INLINE void ISM_HWA_InterruptEnable(ISM_Type *const pIsm, bool bEnable)
{
pIsm->CTRL = (pIsm->CTRL & ~ISM_CTRL_IEN_MASK) | ISM_CTRL_IEN(bEnable);
}
/**
* @brief Get ECS of ISM_E_STATUS register
*
* @param pIsm ISM Instance
* @return ECS value
*/
LOCAL_INLINE uint8_t ISM_HWA_GetEcs(ISM_Type *const pIsm)
{
return (uint8_t)((pIsm->E_STATUS & ISM_E_STATUS_ECS_MASK) >> ISM_E_STATUS_ECS_SHIFT);
}
/**
* @brief Clear ECS of ISM_E_STATUS register
*
* @param pIsm ISM Instance
* @param u32Channels ECM channels
*/
LOCAL_INLINE void ISM_HWA_ClearEcs(ISM_Type *const pIsm, uint32_t u32Channels)
{
pIsm->E_STATUS = (u32Channels << ISM_E_STATUS_ECS_SHIFT) & ISM_E_STATUS_ECS_MASK;
}
/**
* @brief Get ES of ISM_E_STATUS register
*
* @param pIsm ISM Instance
* @return ES value
*/
LOCAL_INLINE uint16_t ISM_HWA_GetEs(ISM_Type *const pIsm)
{
return (uint16_t)((pIsm->E_STATUS & ISM_E_STATUS_ES_MASK) >> ISM_E_STATUS_ES_SHIFT);
}
/**
* @brief Clear ES of ISM_E_STATUS register
*
* @param pIsm ISM Instance
* @param u32Channels ECM channels
*/
LOCAL_INLINE void ISM_HWA_ClearEs(ISM_Type *const pIsm, uint32_t u32Channels)
{
pIsm->E_STATUS = (u32Channels << ISM_E_STATUS_ES_SHIFT) & ISM_E_STATUS_ES_MASK;
}
/**
* @brief Enable ISM ECM channels system event
*
* @param pIsm ISM Instance
* @param u32Channels ECM Channels
* @param bEnable enable value
*/
LOCAL_INLINE void ISM_HWA_EnableEcmSystemEvent(ISM_Type *const pIsm, uint32_t u32Channels, bool bEnable)
{
if (bEnable)
{
pIsm->E_CTRL = pIsm->E_CTRL | (u32Channels << ISM_E_CTRL_ECE_SHIFT);
}
else
{
pIsm->E_CTRL = pIsm->E_CTRL & ~(u32Channels << ISM_E_CTRL_ECE_SHIFT);
}
}
/**
* @brief Get Enabled ISM ECM channels system event
*
* @param pIsm ISM Instance
* @return Enabled ECM event
*/
LOCAL_INLINE uint8_t ISM_HWA_GetEnabledEcmSystemEvent(ISM_Type *const pIsm)
{
return (uint8_t)((pIsm->E_CTRL & ISM_E_CTRL_ECE_MASK) >> ISM_E_CTRL_ECE_SHIFT);
}
/**
* @brief Enable ISM LAM channels system event
*
* @param pIsm ISM Instance
* @param u32Channels LAM Channels
* @param bEnable enable value
*/
LOCAL_INLINE void ISM_HWA_EnableLamSystemEvent(ISM_Type *const pIsm, uint32_t u32Channels, bool bEnable)
{
if (bEnable)
{
pIsm->E_CTRL = pIsm->E_CTRL | (u32Channels << ISM_E_CTRL_EE_SHIFT);
}
else
{
pIsm->E_CTRL = pIsm->E_CTRL & ~(u32Channels << ISM_E_CTRL_EE_SHIFT);
}
}
/**
* @brief Get Enabled ISM LAM channels system event
*
* @param pIsm ISM Instance
* @return Enabled LAM event
*/
LOCAL_INLINE uint16_t ISM_HWA_GetEnabledLamSystemEvent(ISM_Type *const pIsm)
{
return (uint16_t)((pIsm->E_CTRL & ISM_E_CTRL_EE_MASK) >> ISM_E_CTRL_EE_SHIFT);
}
/**
* @brief Set the EC_CTRL register
*
* @param pIsm ISM Instance
* @param u32Value register Value
*/
LOCAL_INLINE void ISM_HWA_SetEcCtrl(ISM_Type *const pIsm, uint32_t u32Value)
{
pIsm->EC_CTRL = u32Value;
}
/**
* @brief Set THRL and LAM channel of ECM0
*
* @param pIsm ISM Instance
* @param u32Value THRL value
* @param u32LamChannel Lam channel
*/
LOCAL_INLINE void ISM_HWA_SetEcm0EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel)
{
uint32_t u32TempValue = pIsm->EC_CTRL;
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_0_MASK) | ISM_EC_CTRL_SEL_0(u32LamChannel);
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_0_MASK) | ISM_EC_CTRL_THRL_0(u32Value);
pIsm->EC_CTRL = u32TempValue;
}
/**
* @brief Set THRL and LAM channel of ECM1
*
* @param pIsm ISM Instance
* @param u32Value THRL value
* @param u32LamChannel Lam channel
*/
LOCAL_INLINE void ISM_HWA_SetEcm1EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel)
{
uint32_t u32TempValue = pIsm->EC_CTRL;
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_1_MASK) | ISM_EC_CTRL_SEL_1(u32LamChannel);
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_1_MASK) | ISM_EC_CTRL_THRL_1(u32Value);
pIsm->EC_CTRL = u32TempValue;
}
/**
* @brief Set THRL and LAM channel of ECM2
*
* @param pIsm ISM Instance
* @param u32Value THRL value
* @param u32LamChannel Lam channel
*/
LOCAL_INLINE void ISM_HWA_SetEcm2EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel)
{
uint32_t u32TempValue = pIsm->EC_CTRL;
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_2_MASK) | ISM_EC_CTRL_SEL_2(u32LamChannel);
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_2_MASK) | ISM_EC_CTRL_THRL_2(u32Value);
pIsm->EC_CTRL = u32TempValue;
}
/**
* @brief Set THRL and LAM channel of ECM3
*
* @param pIsm ISM Instance
* @param u32Value THRL value
* @param u32LamChannel Lam channel
*/
LOCAL_INLINE void ISM_HWA_SetEcm3EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel)
{
uint32_t u32TempValue = pIsm->EC_CTRL;
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_3_MASK) | ISM_EC_CTRL_SEL_3(u32LamChannel);
u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_3_MASK) | ISM_EC_CTRL_THRL_3(u32Value);
pIsm->EC_CTRL = u32TempValue;
}
/**
* @brief Get the RGD value of FPC_STATUS
*
* @param pFpc FPC Instance
* @return RGD value
*/
LOCAL_INLINE bool ISM_HWA_GetFpcRgd(FPC_Type *const pFpc)
{
return (pFpc->FPC_STATUS & ISM_FPC_STATUS_RGD_MASK) == ISM_FPC_STATUS_RGD_MASK ? true : false;
}
/**
* @brief Clear the RGD value of FPC_STATUS
*
* @param pFpc FPC Instance
*/
LOCAL_INLINE void ISM_HWA_ClearFpcRgd(FPC_Type *const pFpc)
{
pFpc->FPC_STATUS = ISM_FPC_STATUS_RGD_MASK;
}
/**
* @brief Get the FGD value of FPC_STATUS
*
* @param pFpc FPC Instance
* @return FGD value
*/
LOCAL_INLINE bool ISM_HWA_GetFpcFgd(FPC_Type *const pFpc)
{
return (pFpc->FPC_STATUS & ISM_FPC_STATUS_FGD_MASK) == ISM_FPC_STATUS_FGD_MASK ? true : false;
}
/**
* @brief Clear the FGD value of FPC_STATUS
*
* @param pFpc FPC Instance
*/
LOCAL_INLINE void ISM_HWA_ClearFpcFgd(FPC_Type *const pFpc)
{
pFpc->FPC_STATUS = ISM_FPC_STATUS_FGD_MASK;
}
/**
* @brief Set the EN of FPC_CTRL
*
* @param pFpc FPC Instance
* @param bEnable EN value
*/
LOCAL_INLINE void ISM_HWA_SetFpcCtrlEn(FPC_Type *const pFpc, bool bEnable)
{
pFpc->FPC_CTRL = (pFpc->FPC_CTRL & ~ISM_FPC_CTRL_EN_MASK) | ISM_FPC_CTRL_EN(bEnable);
}
/**
* @brief Set the IEN of FPC_CTRL
*
* @param pFpc FPC Instance
* @param bEnable IEN value
*/
LOCAL_INLINE void ISM_HWA_SetFpcCtrlIen(FPC_Type *const pFpc, bool bEnable)
{
pFpc->FPC_CTRL = (pFpc->FPC_CTRL & ~ISM_FPC_CTRL_IEN_MASK) | ISM_FPC_CTRL_IEN(bEnable);
}
/**
* @brief Get the IEN of FPC_CTRL
*
* @param pFpc FPC Instance
* @return Interrupt enable bit
*/
LOCAL_INLINE bool ISM_HWA_GetFpcCtrlIen(FPC_Type *const pFpc)
{
return (pFpc->FPC_CTRL & ISM_FPC_CTRL_IEN_MASK) == ISM_FPC_CTRL_IEN_MASK ? true : false;
}
/**
* @brief Set the FEG of FPC_CONFIG
*
* @param pFpc FPC Instance
* @param eMode FEG mode
*/
LOCAL_INLINE void ISM_HWA_SetFpcFallingDetectMode(FPC_Type *const pFpc, ISM_FPC_EdgeDetectModeType eMode)
{
pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_FEG_MASK) | ISM_FPC_CONFIG_FEG(eMode);
}
/**
* @brief Set the FED of FPC_CONFIG
*
* @param pFpc FPC Instance
* @param eMode FED mode
*/
LOCAL_INLINE void ISM_HWA_SetFpcFallingDelayMode(FPC_Type *const pFpc, ISM_FPC_EdgeDelayModeType eMode)
{
pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_FED_MASK) | ISM_FPC_CONFIG_FED(eMode);
}
/**
* @brief Set the REG of FPC_CONFIG
*
* @param pFpc FPC Instance
* @param eMode REG mode
*/
LOCAL_INLINE void ISM_HWA_SetFpcRisingDetectMode(FPC_Type *const pFpc, ISM_FPC_EdgeDetectModeType eMode)
{
pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_REG_MASK) | ISM_FPC_CONFIG_REG(eMode);
}
/**
* @brief Set the RED of FPC_CONFIG
*
* @param pFpc FPC Instance
* @param eMode RED mode
*/
LOCAL_INLINE void ISM_HWA_SetFpcRisingDelayMode(FPC_Type *const pFpc, ISM_FPC_EdgeDelayModeType eMode)
{
pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_RED_MASK) | ISM_FPC_CONFIG_RED(eMode);
}
/**
* @brief Set the CMP of FPC_CONFIG
*
* @param pFpc FPC Instance
* @param u32Value FPC threshold value that is compared with the 16-bit timer.
*/
LOCAL_INLINE void ISM_HWA_SetFpcConfigCmp(FPC_Type *const pFpc, uint32_t u32Value)
{
pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_CMP_MASK) | ISM_FPC_CONFIG_CMP(u32Value);
}
/**
* @brief Set the value of FPC_CONFIG
*
* @param pFpc FPC Instance
* @param u32Value Register value
*/
LOCAL_INLINE void ISM_HWA_SetFpcConfig(FPC_Type *const pFpc, uint32_t u32Value)
{
pFpc->FPC_CONFIG = u32Value;
}
/**
* @brief Get the TIM of FPC_TIMER
*
* @param pFpc FPC Instance
* @return TIM value
*/
LOCAL_INLINE uint16_t ISM_HWA_GetFpcTimer(FPC_Type *const pFpc)
{
return (uint16_t)((pFpc->FPC_TIMER & ISM_FPC_TIMER_TIM_MASK) >> ISM_FPC_TIMER_TIM_SHIFT);
}
/**
* @brief Clear the TIM of FPC_TIMER
*
* @param pFpc FPC Instance
*/
LOCAL_INLINE void ISM_HWA_ClearFpcTimer(FPC_Type *const pFpc)
{
pFpc->FPC_TIMER = ISM_FPC_TIMER_TIM_MASK;
}
/**
* @brief Get the COUNT of LAM_STATUS
*
* @param pLam LAM Instance
* @return COUNT value
*/
LOCAL_INLINE uint32_t ISM_HWA_GetLamStatusCounter(LAM_Type *const pLam)
{
return (pLam->LAM_STATUS & ISM_LAM_STATUS_COUNT_MASK) >> ISM_LAM_STATUS_COUNT_SHIFT;
}
/**
* @brief Clear the COUNT of LAM_STATUS
*
* @param pLam LAM Instance
*/
LOCAL_INLINE void ISM_HWA_ClearLamStatusCounter(LAM_Type *const pLam)
{
pLam->LAM_STATUS = ISM_LAM_STATUS_COUNT_MASK;
}
/**
* @brief Get the OVFL of LAM_STATUS
*
* @param pLam LAM Instance
* @return OVFL value
*/
LOCAL_INLINE bool ISM_HWA_GetLamStatusOvfl(LAM_Type *const pLam)
{
return (pLam->LAM_STATUS & ISM_LAM_STATUS_OVFL_MASK) == ISM_LAM_STATUS_OVFL_MASK ? true : false;
}
/**
* @brief Clear the OVFL of LAM_STATUS
*
* @param pLam LAM Instance
*/
LOCAL_INLINE void ISM_HWA_ClearLamStatusOvfl(LAM_Type *const pLam)
{
pLam->LAM_STATUS = ISM_LAM_STATUS_OVFL_MASK;
}
/**
* @brief Set the IEN of LAM_CTRL
*
* @param pLam LAM Instance
* @param bEnable IEN value, LAM Channel Overflow Interrupt Enable
*/
LOCAL_INLINE void ISM_HWA_SetLamCtrIen(LAM_Type *const pLam, bool bEnable)
{
pLam->LAM_CTRL = (pLam->LAM_CTRL & ~ISM_LAM_CTRL_IEN_MASK) | ISM_LAM_CTRL_IEN(bEnable);
}
/**
* @brief Get the IEN of LAM_CTRL
*
* @param pLam LAM Instance
* @return LAM Channel Overflow Interrupt Enable bit
*/
LOCAL_INLINE bool ISM_HWA_GetLamCtrIen(LAM_Type *const pLam)
{
return (pLam->LAM_CTRL & ISM_LAM_CTRL_IEN_MASK) == ISM_LAM_CTRL_IEN_MASK ? true : false;
}
/**
* @brief Set the EN of LAM_CTRL
*
* @param pLam LAM Instance
* @param bEnable EN value, LAM Channel Enable
*/
LOCAL_INLINE void ISM_HWA_SetLamCtrEn(LAM_Type *const pLam, bool bEnable)
{
pLam->LAM_CTRL = (pLam->LAM_CTRL & ~ISM_LAM_CTRL_EN_MASK) | ISM_LAM_CTRL_EN(bEnable);
}
/**
* @brief Set the value of LAM_CONFIG
*
* @param pLam LAM Instance
* @param u32Value Reigster value
*/
LOCAL_INLINE void ISM_HWA_SetLamConfig(LAM_Type *const pLam, uint32_t u32Value)
{
pLam->LAM_CONFIG = u32Value;
}
/**
* @brief Set the value of LAM_COUNTER
*
* @param pLam LAM Instance
* @param u32Value Reigster value
*/
LOCAL_INLINE void ISM_HWA_SetLamCounter(LAM_Type *const pLam, uint32_t u32Value)
{
pLam->LAM_CONTER = u32Value;
}
/**
* @brief Get the FPC instance.
* @param pIsm ISM Instance
* @param u8FpcIndex FPC index
* @return FPC Instance
*/
LOCAL_INLINE FPC_Type *ISM_HWA_GetFpc(ISM_Type *const pIsm, uint8_t u8FpcIndex)
{
return (FPC_Type *)((uint32_t) & (pIsm->FPC_STATUS0) + (uint32_t)u8FpcIndex * 0x10U);
}
/**
* @brief Get the LAM instance.
* @param pIsm ISM Instance
* @param u8FpcIndex LAM index
* @return LAM Instance
*/
LOCAL_INLINE LAM_Type *ISM_HWA_GetLam(ISM_Type *const pIsm, uint8_t u8LamIndex)
{
return (LAM_Type *)((uint32_t) & (pIsm->LAM_STATUS0) + (uint32_t)u8LamIndex * 0x10U);
}
/** @}*/ /* HwA_ism */
#endif /* #if ISM_INSTANCE_COUNT > 0U */
#endif /* #ifndef _HWA_ISM_H_ */

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/**
* @file HwA_ldi.h
* @author Flagchip
* @brief LDI hardware access layer
* @version 2.0.0
* @date 2025-06-18
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2025-06-18 Flagchip0121 N/A Init version
******************************************************************************** */
#ifndef _HWA_LDI_H_
#define _HWA_LDI_H_
#include "device_header.h"
#if LDI_INSTANCE_COUNT > 0U
#define LDI_SET_BIT(REG, BIT) ((REG) |= (BIT))
#define LDI_CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define LDI_READ_BIT(REG, BIT) ((REG) & (BIT))
#define LDI_CLEAR_REG(REG) ((REG) = (0x0U))
#define LDI_WRITE_REG(REG, VAL) ((REG) = (VAL))
#define LDI_READ_REG(REG) ((REG))
#define LDI_MODIFY_REG(REG, CLEARMASK, SETMASK) LDI_WRITE_REG((REG), (((LDI_READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/**
* @defgroup HwA_ldi HwA_ldi
* @ingroup module_driver_ldi
* @{
*/
/********* Local inline function ************/
/**
* @brief Ldi clear all FIFO
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_ClearFIFO(LDI_Type *pLdi)
{
LDI_SET_BIT(pLdi->CTRL, LDI_CTRL_CLR_FIFO3_MASK|LDI_CTRL_CLR_FIFO2_MASK|LDI_CTRL_CLR_FIFO1_MASK|LDI_CTRL_CLR_FIFO0_MASK);
}
/**
* @brief Ldi clear all FIFO Status
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_ClearFIFOStatus(LDI_Type *pLdi)
{
LDI_SET_BIT(pLdi->FSR, LDI_FSR_FF3_MASK|LDI_FSR_FU3_MASK|LDI_FSR_FF2_MASK|LDI_FSR_FU2_MASK|
LDI_FSR_FF1_MASK|LDI_FSR_FU1_MASK|LDI_FSR_FF0_MASK|LDI_FSR_FU0_MASK);
}
/**
* @brief Ldi Set DDR Mode
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_SetDdrMode(LDI_Type *pLdi)
{
LDI_CLEAR_BIT(pLdi->CTRL, LDI_CTRL_DDR_MASK);
}
/**
* @brief Ldi Set SDR Mode
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_SetSdrMode(LDI_Type *pLdi)
{
LDI_CLEAR_BIT(pLdi->CTRL, LDI_CTRL_DDR_MASK);
}
/**
* @brief Ldi Set DDR delay
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_SetDdrDelay(LDI_Type *pLdi)
{
LDI_SET_BIT(pLdi->CTRL, LDI_CTRL_DDRT_MASK);
}
/**
* @brief Ldi Set SDR delay
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_SetSdrDelay(LDI_Type *pLdi)
{
LDI_SET_BIT(pLdi->CTRL, LDI_CTRL_DCLK_INV_MASK);
}
/**
* @brief Ldi config Ctrl register
*
* @param pLdi Ldi instance
* @param u32LdiCtrlReg Register value
*/
LOCAL_INLINE void LDI_HWA_CfgCtrl(LDI_Type *pLdi, uint32_t u32LdiCtrlReg)
{
LDI_WRITE_REG(pLdi->CTRL, u32LdiCtrlReg);
}
/**
* @brief Ldi config clock Ctrl register
*
* @param pLdi Ldi instance
* @param u32LdiClkCtrlReg Register value
*/
LOCAL_INLINE void LDI_HWA_CfgClkCtrl(LDI_Type *pLdi, uint32_t u32LdiClkCtrlReg)
{
LDI_WRITE_REG(pLdi->CTRL, u32LdiClkCtrlReg);
}
/**
* @brief Ldi enable function clock reference
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_EnFuncClkRef(LDI_Type *pLdi)
{
LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_FCRE_MASK);
}
/**
* @brief Ldi enable clock
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_EnableClk(LDI_Type *pLdi)
{
LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_FCE_MASK);
}
/**
* @brief Ldi set DDR/SDR Prediv
*
* @param pLdi Ldi instance
* @param u32DclkDivValue Dclk prediv
*/
LOCAL_INLINE void LDI_HWA_DdrSdrPrediv(LDI_Type *pLdi, uint32_t u32DclkDivValue)
{
LDI_SET_BIT(pLdi->CLK_CTRL, u32DclkDivValue);
}
/**
* @brief Ldi set gclk Prediv
*
* @param pLdi Ldi instance
* @param u32DclkDivValue Gclk prediv
*/
LOCAL_INLINE void LDI_HWA_GCLKPrediv(LDI_Type *pLdi, uint32_t u32GclkDivValue)
{
LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_GCLKDIV(u32GclkDivValue));
}
/**
* @brief Ldi set gclk source
*
* @param pLdi Ldi instance
* @param u32GclkSrc Gclk source
*/
LOCAL_INLINE void LDI_HWA_GCLKSrc(LDI_Type *pLdi, uint32_t u32GclkSrc)
{
LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_GCLKMUX(u32GclkSrc));
}
/**
* @brief Ldi set Spread Spectrum Mode
*
* @param pLdi Ldi instance
* @param u32SpreadMode Spread Spectrum Mode
*/
LOCAL_INLINE void LDI_HWA_SetSpreadMode(LDI_Type *pLdi, uint32_t u32SpreadMode)
{
LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_SSM(u32SpreadMode));
}
/**
* @brief Ldi set Spread Spectrum Direction
*
* @param pLdi Ldi instance
* @param u32SpreadDirction Spread direction Mode
*/
LOCAL_INLINE void LDI_HWA_SetSpreadDirection(LDI_Type *pLdi, uint32_t u32SpreadDirction)
{
LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_SSD(u32SpreadDirction));
}
/**
* @brief Ldi set clock config
*
* @param pLdi Ldi instance
* @param u32Clkcfg Spread direction Mode
*/
LOCAL_INLINE void LDI_HWA_SetClkcfg(LDI_Type *pLdi, uint32_t u32Clkcfg)
{
LDI_SET_BIT(pLdi->CLK_CTRL, u32Clkcfg);
}
/**
* @brief Ldi Enable Fut
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_EnableFut(LDI_Type *pLdi)
{
LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_FUT_MASK);
}
/**
* @brief Ldi config px ctrl register
*
* @param pLdi Ldi instance
* @param u32LdiPxCtrlReg Px ctlr register value
*/
LOCAL_INLINE void LDI_HWA_CfgPxCtrl(LDI_Type *pLdi, uint32_t u32LdiPxCtrlReg)
{
LDI_WRITE_REG(pLdi->PX_CTRL, u32LdiPxCtrlReg);
}
/**
* @brief Ldi config px ctrl2 register
*
* @param pLdi Ldi instance
* @param u32LdiPxCtrl2Reg Px ctlr register value
*/
LOCAL_INLINE void LDI_HWA_CfgPxCtrl2(LDI_Type *pLdi, uint32_t u32LdiPxCtrl2Reg)
{
LDI_WRITE_REG(pLdi->PX_CTRL2, u32LdiPxCtrl2Reg);
}
/**
* @brief Ldi config px status register
*
* @param pLdi Ldi instance
* @param u32LdiPxStatusReg Px ctlr register value
*/
LOCAL_INLINE void LDI_HWA_CfgPxStatus(LDI_Type *pLdi, uint32_t u32LdiPxStatusReg)
{
LDI_WRITE_REG(pLdi->PX_CTRL2, u32LdiPxStatusReg);
}
/**
* @brief Ldi claer Tr size
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_ClearTrSize(LDI_Type *pLdi)
{
LDI_SET_BIT(pLdi->PX_STATUS, LDI_PX_STATUS_TR_SIZE_MASK);
}
/**
* @brief Ldi Enable channel
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_EnableChannel(LDI_Type *pLdi, uint32_t u32PinsMaskValue)
{
LDI_SET_BIT(pLdi->PX_CTRL2, LDI_PX_CTRL2_PINS(u32PinsMaskValue));
}
/**
* @brief Ldi enable interrupt
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_EnableInterrupt(LDI_Type *pLdi)
{
LDI_WRITE_REG(pLdi->IRQ_EN, LDI_IRQ_EN_PX_UPDT_MASK);
}
/**
* @brief Ldi disable interrupt
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_DisableInterrupt(LDI_Type *pLdi)
{
LDI_CLEAR_BIT(pLdi->IRQ_EN, LDI_IRQ_EN_PX_UPDT_MASK | LDI_IRQ_EN_PX_DISP_MASK);
}
/**
* @brief Ldi clear interrupt flag
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_ClearInterruptFlag(LDI_Type *pLdi)
{
LDI_WRITE_REG(pLdi->IRQ_ST, LDI_IRQ_EN_PX_UPDT_MASK | LDI_IRQ_EN_PX_DISP_MASK);
}
/**
* @brief Ldi config pixel display row configuration register
*
* @param pLdi Ldi instance
* @param u32PxdRcfgReg Register value
*/
LOCAL_INLINE void LDI_HWA_CfgPxdRcfg(LDI_Type *pLdi, uint32_t u32PxdRcfgReg)
{
LDI_WRITE_REG(pLdi->PXD_RCFG, u32PxdRcfgReg);
}
/**
* @brief Ldi config pixel display gclk configuration register
*
* @param pLdi Ldi instance
* @param u32PxdGcfgReg Register value
*/
LOCAL_INLINE void LDI_HWA_CfgPxdGcfg(LDI_Type *pLdi, uint32_t u32PxdGcfgReg)
{
LDI_WRITE_REG(pLdi->PXD_GCFG, u32PxdGcfgReg);
}
/**
* @brief Ldi config pixel display SOE configuration register
*
* @param pLdi Ldi instance
* @param u32PxdScfgReg Register value
*/
LOCAL_INLINE void LDI_HWA_CfgPxdScfg(LDI_Type *pLdi, uint32_t u32PxdScfgReg)
{
LDI_WRITE_REG(pLdi->PXD_SCFG, u32PxdScfgReg);
}
/**
* @brief Ldi config pixel display DOE configuration register
*
* @param pLdi Ldi instance
* @param u32PxdDcfgReg Register value
*/
LOCAL_INLINE void LDI_HWA_CfgPxdDcfg(LDI_Type *pLdi, uint32_t u32PxdDcfgReg)
{
LDI_WRITE_REG(pLdi->PXD_DCFG, u32PxdDcfgReg);
}
/**
* @brief Ldi config pixel display SDI configuration register
*
* @param pLdi Ldi instance
* @param u32PxdIcfgReg Register value
*/
LOCAL_INLINE void LDI_HWA_CfgPxdIcfg(LDI_Type *pLdi, uint32_t u32PxdIcfgReg)
{
LDI_WRITE_REG(pLdi->PXD_ICFG, u32PxdIcfgReg);
}
/**
* @brief Ldi config Fcr0 register
*
* @param pLdi Ldi instance
* @param u32Fcr0Reg Register value
*/
LOCAL_INLINE void LDI_HWA_CfgFcr0(LDI_Type *pLdi, uint32_t u32Fcr0Reg)
{
LDI_WRITE_REG(pLdi->FCR0, u32Fcr0Reg);
}
/**
* @brief Ldi config Fcr1 register
*
* @param pLdi Ldi instance
* @param u32Fcr1Reg Register value
*/
LOCAL_INLINE void LDI_HWA_CfgFcr1(LDI_Type *pLdi, uint32_t u32Fcr1Reg)
{
LDI_WRITE_REG(pLdi->FCR1, u32Fcr1Reg);
}
/**
* @brief Ldi config Fcr2 register
*
* @param pLdi Ldi instance
* @param u32Fcr2Reg Register value
*/
LOCAL_INLINE void LDI_HWA_CfgFcr2(LDI_Type *pLdi, uint32_t u32Fcr2Reg)
{
LDI_WRITE_REG(pLdi->FCR2, u32Fcr2Reg);
}
/**
* @brief Ldi config Fcr3 register
*
* @param pLdi Ldi instance
* @param u32Fcr3Reg Register value
*/
LOCAL_INLINE void LDI_HWA_CfgFcr3(LDI_Type *pLdi, uint32_t u32Fcr3Reg)
{
LDI_WRITE_REG(pLdi->FCR3, u32Fcr3Reg);
}
/**
* @brief Ldi set Tr size
*
* @param pLdi Ldi instance
* @param u32TrSize Tr size
*/
LOCAL_INLINE void LDI_HWA_SetTrSize(LDI_Type *pLdi, uint32_t u32TrSize)
{
LDI_WRITE_REG(pLdi->PX_STATUS, LDI_PX_STATUS_TR_SIZE(u32TrSize));
}
/**
* @brief Ldi start update
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_UpdateStart(LDI_Type *pLdi)
{
LDI_SET_BIT(pLdi->PX_STATUS, LDI_PX_STATUS_UP_START_MASK);
}
/**
* @brief Ldi get update flag
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE uint32_t LDI_HWA_GetUpdateFlag(LDI_Type *pLdi)
{
return(LDI_READ_BIT(pLdi->IRQ_ST, LDI_IRQ_ST_PX_UPDT_MASK) >> LDI_IRQ_ST_PX_UPDT_SHIFT);
}
/**
* @brief Ldi get fifo 0 filling level
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE uint32_t LDI_HWA_GetCh0FifoFillLevel(LDI_Type *pLdi)
{
return (LDI_READ_BIT(pLdi->FCR0, LDI_FCR0_FL_MASK ) >> LDI_FCR0_FL_SHIFT);
}
/**
* @brief Ldi enable dma mode
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_EnableDma(LDI_Type *pLdi)
{
LDI_SET_BIT(pLdi->CTRL, LDI_CTRL_EDME_MASK );
}
/**
* @brief Ldi disable dma mode
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_DisableDma(LDI_Type *pLdi)
{
LDI_CLEAR_BIT(pLdi->CTRL, LDI_CTRL_EDME_MASK );
}
/**
* @brief Ldi config display
*
* @param pLdi Ldi instance
*/
LOCAL_INLINE void LDI_HWA_CfgDisplay(LDI_Type *pLdi)
{
LDI_SET_BIT(pLdi->PX_STATUS, LDI_PX_STATUS_DISP_START_MASK);
}
/** @}*/
#endif
#endif /* #ifndef _HWA_LDI_H_ */

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/**
* @file HwA_lu.h
* @author Flagchip
* @brief LU hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip084 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_LU_H_
#define _HWA_LU_H_
#include "device_header.h"
#if LU_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_lu HwA_lu
* @ingroup module_driver_lu
* @{
*/
/********* Local typedef ************/
/** @brief LU LG instance */
typedef enum
{
LU_LG_0 = 0U,
LU_LG_1,
LU_LG_2,
LU_LG_3
} LU_LgType;
/** @brief LU AOI mode */
typedef enum
{
LU_NO_BYPASS = 0U,
LU_AOI0_BYPASS,
LU_AOI1_BYPASS,
LU_AOI0_AOI1_BYPASS
} LU_BypassModeType;
/** @brief LU FF mode */
typedef enum
{
LU_BYPASS_MODE0 = 0U,
LU_RS_MODE,
LU_TFF_MODE,
LU_DFF_MODE,
LU_JKFF_MODE,
LU_LATCH_MODE
} LU_ConfigModeType;
/** @brief LU Input(n) type */
typedef enum
{
LU_INPUT_N_A = 0U,
LU_INPUT_N_B,
LU_INPUT_N_C,
LU_INPUT_N_D
} LU_InputNType;
/********* Local inline function ************/
/**
* @brief Configure LU LG(n) AOI0 configuration
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32RegValue AOI0 register value
*/
LOCAL_INLINE void LU_HWA_ConfigAOI0(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue)
{
pLu->LG[eLg].AOI_0 = u32RegValue;
}
/**
* @brief Configure LU LG(n) AOI1 configuration
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32RegValue AOI1 register value
*/
LOCAL_INLINE void LU_HWA_ConfigAOI1(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue)
{
pLu->LG[eLg].AOI_1 = u32RegValue;
}
/**
* @brief Configure LU LG(n) contrl configuration
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32RegValue CTRL register value
*/
LOCAL_INLINE void LU_HWA_ConfigCtrl(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue)
{
pLu->LG[eLg].CTRL = u32RegValue;
}
/**
* @brief Configure LU LG(n) filter configuration
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32RegValue FILT register value
*/
LOCAL_INLINE void LU_HWA_ConfigFilter(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue)
{
pLu->LG[eLg].FILT = u32RegValue;
}
/**
* @brief Set LG bypass control
*
* @param pLu LU instance
* @param eLg LG instance
* @param eMode LG bypass control mode
*/
LOCAL_INLINE void LU_HWA_SetLgBypassControl(LU_Type* pLu, LU_LgType eLg, LU_BypassModeType eMode)
{
uint32_t u32TempRegValue = pLu->LG[eLg].CTRL;
pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_BYPASS_MASK) | LU_CTRL_BYPASS(eMode));
}
/**
* @brief Set LG Flip-Flop mode
*
* @param pLu LU instance
* @param eLg LG instance
* @param eMode Flip-Flop mode
*/
LOCAL_INLINE void LU_HWA_SetLgFlipFlopMode(LU_Type* pLu, LU_LgType eLg, LU_ConfigModeType eMode)
{
uint32_t u32TempRegValue = pLu->LG[eLg].CTRL;
pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_MOD_MASK) | LU_CTRL_MOD(eMode));
}
/**
* @brief Set LG inputs synchronous control
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32Value LG input bit,0-3 bit indicate INPUT(n)A/INPUT(n)B/INPUT(n)C/INPUT(n)D
*/
LOCAL_INLINE void LU_HWA_SetLgInputsSyncCtrl(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value)
{
uint32_t u32TempRegValue = pLu->LG[eLg].CTRL;
pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_SYNC_MASK) | LU_CTRL_SYNC(u32Value));
}
/**
* @brief Set LG output feedback override control
*
* @param pLu LU instance
* @param eLg LG instance
* @param eInput Feedback to LG input
*/
LOCAL_INLINE void LU_HWA_SetLgFeedbackOverrideCtrl(LU_Type* pLu, LU_LgType eLg, LU_InputNType eInput)
{
uint32_t u32TempRegValue = pLu->LG[eLg].CTRL;
pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_FB_OVRD_MASK) | LU_CTRL_FB_OVRD(eInput));
}
/**
* @brief Configure the output of flip-flop as "1"
*
* @param pLu LU instance
* @param eLg LG instance
*/
LOCAL_INLINE void LU_HWA_ConfigFlipFlopTo1(LU_Type* pLu, LU_LgType eLg)
{
pLu->LG[eLg].CTRL |= (uint32_t)LU_CTRL_FF_INIT_MASK;
}
/**
* @brief Generate enable pulse
*
* @param pLu LU instance
* @param eLg LG instance
*/
LOCAL_INLINE void LU_HWA_EnableControlFlipFlopInitOutput(LU_Type* pLu, LU_LgType eLg)
{
pLu->LG[eLg].CTRL |= (uint32_t)LU_CTRL_INIT_EN_MASK;
}
/**
* @brief Input filter sample count for AOI0
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32Value Sample count value
*/
LOCAL_INLINE void LU_HWA_SetAOI0InputFilterSampleCount(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value)
{
uint32_t u32TempRegValue = pLu->LG[eLg].FILT;
pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_CNT0_MASK) | LU_FILT_CNT0(u32Value));
}
/**
* @brief Input filter sample period for AOI0
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32Value Sample period value
*/
LOCAL_INLINE void LU_HWA_SetAOI0InputFilterSamplePeriod(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value)
{
uint32_t u32TempRegValue = pLu->LG[eLg].FILT;
pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_PRE0_MASK) | LU_FILT_PRE0(u32Value));
}
/**
* @brief Input filter sample count for AOI1
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32Value Sample count value
*/
LOCAL_INLINE void LU_HWA_SetAOI1InputFilterSampleCount(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value)
{
uint32_t u32TempRegValue = pLu->LG[eLg].FILT;
pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_CNT1_MASK) | LU_FILT_CNT1(u32Value));
}
/**
* @brief Input filter sample period for AOI1
*
* @param pLu LU instance
* @param eLg LG instance
* @param u32Value Sample period value
*/
LOCAL_INLINE void LU_HWA_SetAOI1InputFilterSamplePeriod(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value)
{
uint32_t u32TempRegValue = pLu->LG[eLg].FILT;
pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_PRE1_MASK) | LU_FILT_PRE1(u32Value));
}
/**
* @brief Configure the output of flip-flop as "0"
*
* @param pLu LU instance
* @param eLg LG instance
*/
LOCAL_INLINE void LU_HWA_ConfigFlipFlopTo0(LU_Type* pLu, LU_LgType eLg)
{
pLu->LG[eLg].CTRL &= ~(uint32_t)LU_CTRL_FF_INIT_MASK;
}
/** @}*/
#endif /* #if LU_INSTANCE_COUNT > 0U */
#endif /* #ifndef _HWA_LU_H_ */

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/**
* @file HwA_mam.h
* @author Flagchip
* @brief Hardware access layer for MAM
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip054 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip054 N/A Change version and release
* 2.5.0 2025-08-20 Flagchip0100 N/A Add FC7300F4MDDxxxT1C support
******************************************************************************** */
#ifndef _HWA_MAM_H_
#define _HWA_MAM_H_
#include "device_header.h"
#if MAM_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_mam HwA_mam
* @ingroup module_driver_mam
* @{
*/
/**
* @brief Set Mam module Matrix Configure register
*
* @param1 MAM base pointer
*
* @param2 u32Value Matrix Configure register value
*/
LOCAL_INLINE void Mam_HWA_SetMatrixCfg(MAM_Type *MAM, uint32_t u32Value)
{
MAM->MAXCFG = u32Value;
}
/**
* @brief Read Mam module Ctrl register
*
* @param MAM base pointer
*
* @return Matrix Configure register value
*/
LOCAL_INLINE uint32_t Mam_HWA_GetMatrixCfg(MAM_Type *MAM)
{
return (uint32_t)(MAM->MAXCFG);
}
/**
* @brief Set Mam module Wdgctr register
*
* @param1 MAM base pointer
*
* @param2 u32Value Wdgctr register value
*/
LOCAL_INLINE void Mam_HWA_SetWdgCr(MAM_Type *MAM, uint32_t u32Value)
{
MAM->WDGCR = u32Value;
}
/**
* @brief Read Mam module Wdgctr register
*
* @param MAM base pointer
*
* @return Wdgctr register value
*/
LOCAL_INLINE uint32 Mam_HWA_GetWdgCr(MAM_Type *MAM)
{
return MAM->WDGCR;
}
/**
* @brief Set Mam module timeout control register
*
* @param1 MAM base pointer
*
* @param2 u32Value timeout control register value
*/
LOCAL_INLINE void Mam_HWA_SetWdgToCr(MAM_Type *MAM, uint32_t u32Value)
{
MAM->TOCR = u32Value;
}
/**
* @brief Read Mam module timeout control register
*
* @param MAM base pointer
*
* @return timeout control register value
*/
LOCAL_INLINE uint32 Mam_HWA_GetWdgToCr(MAM_Type *MAM)
{
return MAM->TOCR;
}
#ifdef MAM_WDOG_DIV_SUPPORT
/**
* @brief Set Mam module watchdog div register
*
* @param1 MAM base pointer
*
* @param2 u32Value watchdog div register value
*/
LOCAL_INLINE void Mam_HWA_SetWdgDiv(MAM_Type *MAM, uint32_t u32Value)
{
MAM->WDGDIV = u32Value;
}
/**
* @brief Read Mam module watchdog div register
*
* @param MAM base pointer
*
* @return watchdog div register value
*/
LOCAL_INLINE uint32 Mam_HWA_GetWdgDiv(MAM_Type *MAM)
{
return MAM->WDGDIV;
}
#endif
/**
* @brief Set Mam module ACR register
*
* @param1 MAM base pointer
*
* @param2 idx ACR register index
*
* @param3 u32Value ACR register value
*/
LOCAL_INLINE void Mam_HWA_Set_ACR(MAM_Type *MAM, uint32_t idx, uint32_t u32Value)
{
MAM->ACR[idx] = u32Value;
}
/**
* @brief Read Mam module ACR register
*
* @param1 MAM base pointer
*
* @param2 idx ACR register index
*
* @return ACR register value
*/
LOCAL_INLINE uint32_t Mam_HWA_Get_ACR(MAM_Type *MAM, uint32_t idx)
{
return MAM->ACR[idx];
}
/**
* @brief Set Mam module ACLR register
*
* @param1 MAM base pointer
*
* @param2 idx ACLR register index
*
* @param3 u32Value ACLR register value
*/
LOCAL_INLINE void Mam_HWA_Set_ACLR(MAM_Type *MAM, uint32_t idx, uint32_t u32Value)
{
MAM->ACLR[idx] = u32Value;
}
/**
* @brief Read Mam module ACLR register
*
* @param1 MAM base pointer
*
* @param2 idx ACLR register index
*
* @return ACLR register value
*/
LOCAL_INLINE uint32_t Mam_HWA_Get_ACLR(MAM_Type *MAM, uint32_t idx)
{
return MAM->ACLR[idx];
}
#ifdef MAM_PORT_MONITOR_SUPPORT
/**
* @brief Set the Check Control Register (CCLR) value
*
* @param MAM Pointer to the MAM peripheral register structure
* @param u32Value Value to write to the CCLR register
* - Each bit corresponds to a monitor port (0-31)
* - Setting a bit enables monitoring for that port
* - Clearing a bit disables monitoring for that port
*/
LOCAL_INLINE void Mam_HWA_Set_CCLR(MAM_Type *MAM, uint32_t u32Value)
{
MAM->CCLR = u32Value;
}
/**
* @brief Get the current Check Control Register (CCLR) value
*
* @param MAM Pointer to the MAM peripheral register structure
* @return uint32_t Current CCLR register value
* - Each bit represents the enabled state of a monitor port (0-31)
* - Bit set to 1: monitoring enabled for that port
* - Bit set to 0: monitoring disabled for that port
*/
LOCAL_INLINE uint32_t Mam_HWA_Get_CCLR(MAM_Type *MAM)
{
return MAM->CCLR;
}
#endif
#ifdef MAM_SLAVE_PRIORITY_SUPPORT
/**
* @brief Set the Priority Enable Register (PRI_EN) value
*
* @param MAM Pointer to the MAM peripheral register structure
* @param u32Value Priority enable configuration value
* - Each bit (0-31) enables/disables priority arbitration for a slave
* - Bit set to 1: priority arbitration enabled for corresponding slave
* - Bit set to 0: round-robin arbitration used for corresponding slave
*/
LOCAL_INLINE void Mam_HWA_Set_PRI_EN(MAM_Type *MAM, uint32_t u32Value)
{
MAM->PRI_EN = MAM_PRIORITY_EN_KEY;
MAM->PRI_EN = u32Value;
}
/**
* @brief Get the current Priority Enable Register (PRI_EN) value
*
* @param MAM Pointer to the MAM peripheral register structure
* @return uint32_t Current PRI_EN register value
* - Each bit (0-31) represents priority enable state for a slave
* - Bit set to 1: priority arbitration enabled for corresponding slave
* - Bit set to 0: round-robin arbitration used for corresponding slave
*/
LOCAL_INLINE uint32_t Mam_HWA_Get_PRI_EN(MAM_Type *MAM)
{
return MAM->PRI_EN;
}
/**
* @brief Set Priority ID for Slave Group 0 (slaves 0-7)
*
* @param MAM Pointer to the MAM peripheral register structure
* @param u32Value Priority configuration value
* - Bits [3:0]: Priority master for slave 0
* - Bits [7:4]: Priority master for slave 1
* - ... up to Bits [31:28]: Priority master for slave 7
*/
LOCAL_INLINE void Mam_HWA_Set_PRI_ID_SLVGRP0(MAM_Type *MAM, uint32_t u32Value)
{
MAM->PRI_ID_SLVGRP0 = u32Value;
}
/**
* @brief Get current Priority ID for Slave Group 0 (slaves 0-7)
*
* @param MAM Pointer to the MAM peripheral register structure
* @return uint32_t Current priority configuration for slaves 0-7
*/
LOCAL_INLINE uint32_t Mam_HWA_Get_PRI_ID_SLVGRP0(MAM_Type *MAM)
{
return MAM->PRI_ID_SLVGRP0;
}
/**
* @brief Set Priority ID for Slave Group 1 (slaves 8-15)
*
* @param MAM Pointer to the MAM peripheral register structure
* @param u32Value Priority configuration value
* - Byte 0: Priority master for slave 8 (bits [7:0])
* - Byte 1: Priority master for slave 9 (bits [15:8])
* - ... up to Byte 7: Priority master for slave 15 (bits [63:56])
*/
LOCAL_INLINE void Mam_HWA_Set_PRI_ID_SLVGRP1(MAM_Type *MAM, uint32_t u32Value)
{
MAM->PRI_ID_SLVGRP1 = u32Value;
}
/**
* @brief Get current Priority ID for Slave Group 1 (slaves 8-15)
*
* @param MAM Pointer to the MAM peripheral register structure
* @return uint32_t Current priority configuration for slaves 8-15
*/
LOCAL_INLINE uint32_t Mam_HWA_Get_PRI_ID_SLVGRP1(MAM_Type *MAM)
{
return MAM->PRI_ID_SLVGRP1;
}
#endif
/** @}*/
#endif /* #if MAM_INSTANCE_COUNT > 0U */
#endif

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/**
* @file HwA_mb.h
* @author flagchip
* @brief Mailbox hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip070 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip070 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_MAILBOX_H_
#define _HWA_MAILBOX_H_
#include "device_header.h"
#if MB_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_mb HwA_mb
* @ingroup module_driver_mb
* @{
*/
/**
* @brief The definition of mask all events
*
*/
#define MB_EVENT_NONE 0u
/**
* @brief The definition of receiving all events
*
*/
#define MB_EVENT_ALL 0xFFFFFFFFu
/**
* @brief The definition of receiving all request events
*
*/
#define MB_EVENT_ALL_REQ 0x0000FFFFu
/**
* @brief The definition of receiving all done events
*
*/
#define MB_EVENT_ALL_DONE 0xFFFF0000u
/**
* @brief The definition of request events on ch
*
*/
#define MB_EVENT_REQ(ch) (uint32_t)((uint32_t)1u << (ch))
/**
* @brief The definition of done events on ch
*
*/
#define MB_EVENT_DONE(ch) (uint32_t)((uint32_t)1u << ((ch) + MB_INTn_FLG_MASK_DONE_FLAG_MASK_SHIFT))
/**
* @brief The definition of issue to no core
*
*/
#define MB_CORE_MASK_CORE_NONE 0u
/**
* @brief The definition of issue to core 0
*
*/
#define MB_CORE_MASK_CORE_0 1u
/**
* @brief The definition of issue to core 1
*
*/
#define MB_CORE_MASK_CORE_1 2u
/**
* @brief The definition of issue to core 2
*
*/
#define MB_CORE_MASK_CORE_2 4u
/**
* @brief The definition of issue to HSM
*
*/
#define MB_CORE_MASK_HSM 8u
/**
* @brief The definition of issue to all cores
*
*/
#define MB_CORE_MASK_ALL 0xFu
/**
* @brief The definition of issue to core
*
*/
#define MB_CORE_MASK(core) (uint32_t)(1ul << (core))
/**
* @brief Lock the MB_INTn registers
*
* @param u8CoreIndex the index of the core
* @param u32Mask the lock bits
*/
LOCAL_INLINE void MB_HWA_LockIntrReg(uint8_t u8CoreIndex, uint32_t u32Mask)
{
MB->INTR[u8CoreIndex].CCn_CTRL |= u32Mask;
}
/**
* @brief Unlock the MB_INTn registers
*
* @param u8CoreIndex the index of the core
* @param u32Mask the unlock bits
*/
LOCAL_INLINE void MB_HWA_UnlockIntrReg(uint8_t u8CoreIndex, uint32_t u32Mask)
{
MB->INTR[u8CoreIndex].CCn_CTRL &= ~u32Mask;
}
/**
* @brief Lock the MB_INTn_FLG
*
* @param u8CoreIndex the index of the core
*/
LOCAL_INLINE void MB_HWA_LockFlag(uint8_t u8CoreIndex)
{
MB->INTR[u8CoreIndex].CCn_CTRL |= MB_INTn_CTRL_FLG_LOCK_MASK;
}
/**
* @brief Unlock the MB_INTn_FLG
*
* @param u8CoreIndex the index of the core
*/
LOCAL_INLINE void MB_HWA_UnlockFlag(uint8_t u8CoreIndex)
{
MB->INTR[u8CoreIndex].CCn_CTRL &= ~MB_INTn_CTRL_FLG_LOCK_MASK;
}
/**
* @brief Lock the MB_INTn_FLG_MASK
*
* @param u8CoreIndex the index of the core
*/
LOCAL_INLINE void MB_HWA_LockFlagMask(uint8_t u8CoreIndex)
{
MB->INTR[u8CoreIndex].CCn_CTRL |= MB_INTn_CTRL_FLG_MASK_LOCK_MASK;
}
/**
* @brief Unlock the MB_INTn_FLG_MASK
*
* @param u8CoreIndex the index of the core
*/
LOCAL_INLINE void MB_HWA_UnlockFlagMask(uint8_t u8CoreIndex)
{
MB->INTR[u8CoreIndex].CCn_CTRL &= ~MB_INTn_CTRL_FLG_MASK_LOCK_MASK;
}
/**
* @brief Lock the MB_INTn_INTEN
*
* @param u8CoreIndex the index of the core
*/
LOCAL_INLINE void MB_HWA_LockInten(uint8_t u8CoreIndex)
{
MB->INTR[u8CoreIndex].CCn_CTRL |= MB_INTn_CTRL_INTEN_LOCK_MASK;
}
/**
* @brief Unlock the MB_INTn_INTEN
*
* @param u8CoreIndex the index of the core
*/
LOCAL_INLINE void MB_HWA_UnlockInten(uint8_t u8CoreIndex)
{
MB->INTR[u8CoreIndex].CCn_CTRL &= ~MB_INTn_CTRL_INTEN_LOCK_MASK;
}
/**
* @brief Configure receive events of mailbox interrupt channel
*
* @param u8CoreIndex the index of the core
* @param u32Mask configuration for receiving events
*/
LOCAL_INLINE void MB_HWA_ConfigFlagMask(uint8_t u8CoreIndex, uint32_t u32Mask)
{
MB->INTR[u8CoreIndex].CCn_FLG_MASK = u32Mask;
}
/**
* @brief Enable receive events of mailbox interrupt channel
*
* @param u8CoreIndex the index of the core
* @param u32Mask indicates the events to be enabled
*/
LOCAL_INLINE void MB_HWA_EnableEvent(uint8_t u8CoreIndex, uint32_t u32Mask)
{
MB->INTR[u8CoreIndex].CCn_FLG_MASK |= u32Mask;
}
/**
* @brief Disable receive events of mailbox interrupt channel
*
* @param u8CoreIndex the index of the core
* @param u32Mask indicates the events to be enabled
*/
LOCAL_INLINE void MB_HWA_DisableEvent(uint8_t u8CoreIndex, uint32_t u32Mask)
{
MB->INTR[u8CoreIndex].CCn_FLG_MASK &= ~u32Mask;
}
/**
* @brief Configure the interrupt of mailbox interrupt channel
*
* @param u8CoreIndex the index of the core
* @param u32Mask configuration for interrupts
*/
LOCAL_INLINE void MB_HWA_ConfigIntrEnable(uint8_t u8CoreIndex, uint32_t u32Mask)
{
MB->INTR[u8CoreIndex].CCn_INTEN = u32Mask;
}
/**
* @brief Enable the interrupt of mailbox interrupt channel
*
* @param u8CoreIndex the index of the core
* @param u32Mask indicates the interrupts to be enabled
*/
LOCAL_INLINE void MB_HWA_EnableIntr(uint8_t u8CoreIndex, uint32_t u32Mask)
{
MB->INTR[u8CoreIndex].CCn_INTEN |= u32Mask;
}
/**
* @brief Disable the interrupt of mailbox interrupt channel
*
* @param u8CoreIndex the index of the core
* @param u32Mask indicates the interrupts to be disabled
*/
LOCAL_INLINE void MB_HWA_DisableIntr(uint8_t u8CoreIndex, uint32_t u32Mask)
{
MB->INTR[u8CoreIndex].CCn_INTEN &= ~u32Mask;
}
/**
* @brief Clear the flag of mailbox interrupt channel
*
* @param u8CoreIndex the index of the core
* @param u32Mask indicates the flags to be cleared
*/
LOCAL_INLINE void MB_HWA_ClearFlag(uint8_t u8CoreIndex, uint32_t u32Mask)
{
MB->INTR[u8CoreIndex].CCn_FLG = u32Mask;
}
/**
* @brief Get the flag masks of mailbox interrupt channel
*
* @param u8CoreIndex the index of the core
* @param u32Mask the mask to get
* @return the flag masks of the mailbox interrupt channel
*/
LOCAL_INLINE uint32_t MB_HWA_GetFlagMask(uint8_t u8CoreIndex, uint32_t u32Mask)
{
return MB->INTR[u8CoreIndex].CCn_FLG_MASK & u32Mask;
}
/**
* @brief Get the flags of mailbox interrupt channel
*
* @param u8CoreIndex the index of the core
* @param u32Mask the mask to get
* @return the flags of the mailbox interrupt channel
*/
LOCAL_INLINE uint32_t MB_HWA_GetFlag(uint8_t u8CoreIndex, uint32_t u32Mask)
{
return MB->INTR[u8CoreIndex].CCn_FLG & u32Mask;
}
/**
* @brief Get the result of flag & inten of mailbox interrupt channel
*
* @param u8CoreIndex the index of the core
* @param u32Mask the mask to get
* @return the result of flag & inten of the mailbox interrupt channel
*/
LOCAL_INLINE uint32_t MB_HWA_GetFlagStat(uint8_t u8CoreIndex, uint32_t u32Mask)
{
return MB->INTR[u8CoreIndex].CCn_FLG_STAT & u32Mask;
}
/**
* @brief Get the master ID of the currently obtained channel
*
* @param u32Channel the index of the channel
* @return the master ID
*/
LOCAL_INLINE uint32_t MB_HWA_GetMasterID(uint32_t u32Channel)
{
return (MB->CHANNEL[u32Channel].CCn_STAT & MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_MASK) >> MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_SHIFT;
}
/**
* @brief Send data to the mailbox channel
*
* @param u32Channel the index of the channel
* @param pData the buffer to be written
*/
LOCAL_INLINE void MB_HWA_WriteData(uint32_t u32Channel, uint32_t *pData)
{
MB->CHANNEL[u32Channel].CCn_DATA0 = pData[0];
MB->CHANNEL[u32Channel].CCn_DATA1 = pData[1];
}
/**
* @brief Receive data from the mailbox channel
*
* @param u32Channel the index of the channel
* @param pData the buffer to receive data
*/
LOCAL_INLINE void MB_HWA_GetData(uint32_t u32Channel, uint32_t *pData)
{
pData[0] = MB->CHANNEL[u32Channel].CCn_DATA0;
pData[1] = MB->CHANNEL[u32Channel].CCn_DATA1;
}
/**
* @brief Get the automatically clear status of the mailbox channel
*
* @param u32Channel the index of the channel
* @param u8CoreIndex the index of the core
* @return automatically clear the channel lock enable bit
*/
LOCAL_INLINE uint32_t MB_HWA_GetAutoClear(uint32_t u32Channel, uint8_t u8CoreIndex)
{
return MB->CHANNEL[u32Channel].CCn_SEMA_UNLK & ((uint32_t)1u << u8CoreIndex);
}
/**
* @brief Release the mailbox channel
*
* @param u32Channel the index of the channel
*/
LOCAL_INLINE void MB_HWA_ReleaseChannel(uint32_t u32Channel)
{
MB->CHANNEL[u32Channel].CCn_DONE = MB_MASTER_DONE_CODE;
}
/**
* @brief Software clears channel lock
*
* @param u32Channel the index of the channel
*/
LOCAL_INLINE void MB_HWA_UnlockChannel(uint32_t u32Channel)
{
MB->CHANNEL[u32Channel].CCn_CLR = MB_FORCE_UNLOCK_CODE;
}
/**
* @brief Issue a done event
*
* @param u32Channel the index of the channel
* @param u32DoneMask the cores to issue
*/
LOCAL_INLINE void MB_HWA_SetDone(uint32_t u32Channel, uint32_t u32DoneMask)
{
MB->CHANNEL[u32Channel].CCn_DONE |= (u32DoneMask & MB_CCn_DONE_MASK);
}
/**
* @brief Get the Communication Channel Semaphore Register
*
* @param u32Channel the index of the channel
* @return Channel Lock Acquisition
*/
LOCAL_INLINE uint32_t MB_HWA_GetSemaphore(uint32_t u32Channel, uint32_t u32Mask)
{
return MB->CHANNEL[u32Channel].CCn_SEMA & u32Mask;
}
/**
* @brief Configure the master ID of the core that generates a done event
*
* @param u32Channel the index of the channel
* @param u32MasterId master ID
*/
LOCAL_INLINE void MB_HWA_ConfigDoneMasterId(uint32_t u32Channel, uint32_t u32MasterId)
{
MB->CHANNEL[u32Channel].CCn_DONE_MASK = (MB->CHANNEL[u32Channel].CCn_DONE_MASK & (~MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK)) \
| MB_CCn_DONE_MASK_DONE_MASTER_ID(u32MasterId);
}
/**
* @brief Get the master ID of the core that generates a done event
*
* @param u32Channel the index of the channel
* @return the master ID
*/
LOCAL_INLINE uint32_t MB_HWA_GetDoneMasterId(uint32_t u32Channel)
{
return (MB->CHANNEL[u32Channel].CCn_DONE_MASK & MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK) \
>> MB_CCn_DONE_MASK_DONE_MASTER_ID_SHIFT;
}
/**
* @brief Configure the mask of the done events
*
* @param u32Channel the index of the channel
* @param u32DoneMask the cores to issue
*/
LOCAL_INLINE void MB_HWA_ConfigDoneMask(uint32_t u32Channel, uint32_t u32DoneMask)
{
MB->CHANNEL[u32Channel].CCn_DONE_MASK = (MB->CHANNEL[u32Channel].CCn_DONE_MASK & (~MB_CCn_DONE_MASK)) | \
(u32DoneMask & MB_CCn_DONE_MASK);
}
/**
* @brief Get the mask of the done events
*
* @param u32Channel the index of the channel
* @return the mask of the done events
*/
LOCAL_INLINE uint32_t MB_HWA_GetDoneMask(uint32_t u32Channel)
{
return MB->CHANNEL[u32Channel].CCn_DONE_MASK & MB_CCn_DONE_MASK;
}
/**
* @brief Configure the automatically clear of the lock enable bit
*
* @param u32Channel the index of the channel
* @param u32AutoUnlockMask the automatically clear of the lock enable bit
*/
LOCAL_INLINE void MB_HWA_ConfigAutoUnlock(uint32_t u32Channel, uint32_t u32AutoUnlockMask)
{
MB->CHANNEL[u32Channel].CCn_SEMA_UNLK = u32AutoUnlockMask & MB_CCn_SEMA_UNLK_MASK;
}
/**
* @brief Issue request events
*
* @param u32Channel the index of the channel
* @param u32RequestMask the cores to issue
*/
LOCAL_INLINE void MB_HWA_ConfigRequest(uint32_t u32Channel, uint32_t u32RequestMask)
{
MB->CHANNEL[u32Channel].CCn_REQUEST = u32RequestMask & MB_CCn_REQUEST_MASK;
}
#ifdef MB_SEMA_EXSIST
/**
* @brief Function to get the semaphore status
*
* This function retrieves the status of a semaphore specified by the identifier u32Sema.
* It accesses the SEMAn_STATUS array of a predefined MB object, which contains the status values of all semaphores.
*
* @param u32Sema Semaphore identifier used to specify the semaphore whose status is to be retrieved.
* @return uint32_t Returns the status value of the specified semaphore.
*
*/
LOCAL_INLINE uint32_t MB_HWA_GetSemaStatus(uint32_t u32Sema)
{
return MB->SEMAn_STATUS[u32Sema];
}
/**
* @brief Get semaphore lock status
*
* @param u32Sema Semaphore identifier
*
* @return bool Returns the semaphore lock status
*
* @note This function checks the specific bit in the SEMAn_STATUS register to determine if the semaphore is locked
*/
LOCAL_INLINE bool MB_HWA_GetSemaLock(uint32_t u32Sema)
{
return (bool)(MB->SEMAn_STATUS[u32Sema] & MB_SEMAn_STATUS_SEMA_FLG_MASK);
}
/**
* @brief Get the master ID of a semaphore
*
* @param u32Sema Semaphore identifier used to select the specific semaphore status register
* @return uint8_t The master ID of the semaphore
*/
LOCAL_INLINE uint8_t MB_HWA_GetSemaMasterID(uint32_t u32Sema)
{
return (uint8_t)((MB->SEMAn_STATUS[u32Sema] & MB_SEMAn_STATUS_SEMA_MID_MASK) >> MB_SEMAn_STATUS_SEMA_MID_SHIFT);
}
/**
* @brief Get Semaphore Resource ID
*
* @param u32Sema Semaphore index, indicating which semaphore register to use.
* @return uint8_t Semaphore resource ID.
*/
LOCAL_INLINE uint8_t MB_HWA_GetSemaResourceID(uint32_t u32Sema)
{
return (uint8_t)((MB->SEMAn_STATUS[u32Sema] & MB_SEMAn_STATUS_SEMA_RSRC_ID_MASK) >> MB_SEMAn_STATUS_SEMA_RSRC_ID_SHIFT);
}
/**
* @brief Get the global semaphore status
*
* @return uint16_t The current global semaphore status value
*/
LOCAL_INLINE uint16_t MB_HWA_GetSemaGlobalStatus(void)
{
return (uint16_t)(MB->SEMA_GLOBAL_STATUS & MB_SEMA_GLOBAL_STATUS_MASK);
}
/**
* @brief Enable semaphore lock protection
*
*/
LOCAL_INLINE void MB_HWA_EnableSemaLockProtect(void)
{
MB->SEMA_CTRL &= ~MB_SEMA_CTRL_MASK;
}
/**
* @brief Disable semaphore lock protection
*
*/
LOCAL_INLINE void MB_HWA_DisableSemaLockProtect(void)
{
MB->SEMA_CTRL |= MB_SEMA_CTRL_MASK;
}
/**
* @brief Get the SEMA error status register value
*
* @return uint32_t The current value of the SEMA error status register
*/
LOCAL_INLINE uint32_t MB_HWA_ReadSemaErrorStatus(void)
{
return MB->SEMA_ERROR_STATUS;
}
/**
* @brief Get Semaphore Error Resource ID
*
* @return uint8_t The value of the semaphore error resource ID
*/
LOCAL_INLINE uint8_t MB_HWA_GetSemaErrorResourceID(void)
{
return (uint8_t)((MB->SEMA_ERROR_STATUS & MB_SEMA_ERROR_STATUS_SEMA_ERR_RSRC_ID_MASK) >> MB_SEMA_ERROR_STATUS_SEMA_ERR_RSRC_ID_SHIFT);
}
/**
* @brief Get Semaphore Master ID
*
* @return uint8_t The value of the semaphore error master ID
*/
LOCAL_INLINE uint8_t MB_HWA_GetSemaErrorMasterID(void)
{
return (uint8_t)((MB->SEMA_ERROR_STATUS & MB_SEMA_ERROR_STATUS_SEMA_ERR_MID_MASK) >> MB_SEMA_ERROR_STATUS_SEMA_ERR_MID_SHIFT);
}
/**
* @brief Get Semaphore Error Status
*
* @return uint8_t The value of the semaphore error status
*/
LOCAL_INLINE uint32_t MB_HWA_GetSemaErrorStatus(void)
{
return MB->SEMA_ERROR_STATUS;
}
/**
* @brief Sets the software reset signal for the MB module
*
*/
LOCAL_INLINE void MB_HWA_SoftwareResetSema(void)
{
MB->SEMA_SW_RESET = MB_SEMA_KEY_SW_RESET;
}
/**
* @brief Release all semaphores
*
* @param u8MasterId The Master Index used to identify the resource to be acquired, the value should be 0~4
*/
LOCAL_INLINE void MB_HWA_ReleaseAllSema(uint8_t u8MasterIdx)
{
MB->SEMA_RELEASE = MB_SEMA_KEY_RELEASE_ALL | (uint32_t)(u8MasterIdx & 0x7u);
}
/**
* @brief Acquire a resource by its ID
*
* @param u32ResourceID The resource ID used to identify the resource to be acquired
*/
LOCAL_INLINE uint32_t MB_HWA_GetResource(uint32_t u32ResourceID)
{
return MB->SEMA_RSRC[u32ResourceID];
}
/**
* @brief Unlocks the specified resource
*
* This function unlocks the resource identified by u32ResourceID by setting the associated semaphore key to an unlocked state.
*
* @param u32ResourceID The resource identifier used to specify the resource to unlock
*/
LOCAL_INLINE void MB_HWA_UnlockResource(uint32_t u32ResourceID)
{
MB->SEMA_RSRC[u32ResourceID] = MB_SEMA_KEY_UNLOCK;
}
LOCAL_INLINE void MB_HWA_ReleaseResource(uint32_t u32ResourceID)
{
MB->SEMA_RSRC[u32ResourceID] = MB_SEMA_KEY_RELEASE;
}
/**
* @brief Clear error status function
*
* Sets the status flag for the specified resource ID to the key value that clears the error status.
*
*/
LOCAL_INLINE void MB_HWA_ClearErrorStatus(void)
{
MB->SEMA_ERROR_STATUS = MB_SEMA_KEY_CLEAR_ERROR;
}
#endif
/** @}*/
#endif /* #if MB_INSTANCE_COUNT > 0U */
#endif

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@ -0,0 +1,710 @@
/**
* @file HwA_msc.h
* @author flagchip
* @brief MSC hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip084 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_MSC_H_
#define _HWA_MSC_H_
#include "device_header.h"
#if MSC_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_msc HwA_msc
* @ingroup module_driver_msc
* @{
*/
/********* macros ************/
typedef enum
{
MSC_RSV_SUCCESS = 0x0U, /*!< MSC receive status is successful. */
MSC_RSV_PARITY_ERROR = 0x1U, /*!< MSC receive has parity error. */
MSC_RSV_STOP_ERROR = 0x2U, /*!< MSC receive has stop error. */
MSC_RSV_ERROR = 0x4U, /*!< MSC receive status is not successful. */
} MSC_ReceiveStatusType;
/********* Local typedef ************/
/********* Local inline function ************/
/********* xxx Register interface ************/
/**
* @brief Get the msc TCCTR register
*
* @param pMsc MSCInstance
* @param u32Value TCCTR register value
*/
LOCAL_INLINE void MSC_HWA_SetTcctr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCCTR = u32Value;
}
/**
* @brief Get the msc TCCTR register DTS bit
*
* @param pMsc MSCInstance
* @return DTS value
*/
LOCAL_INLINE bool MSC_HWA_GetDataNeedSend(MSC_Type *const pMsc)
{
return (pMsc->TCCTR & MSC_TCCTR_DTS_MASK) == MSC_TCCTR_DTS_MASK ? true : false;
}
/**
* @brief Set the msc TCCTR register DTS bit
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_SetDataNeedSend(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_SDTS_MASK;
}
/**
* @brief Get the msc TCCTR register CTS bit
*
* @param pMsc MSCInstance
* @return CTS value
*/
LOCAL_INLINE bool MSC_HWA_GetCmdNeedSend(MSC_Type *const pMsc)
{
return (pMsc->TCCTR & MSC_TCCTR_CTS_MASK) == MSC_TCCTR_CTS_MASK ? true : false;
}
/**
* @brief Get the CFB value of TCSTR register
*
* @param pMsc MSCInstance
* @return CFB value
*/
LOCAL_INLINE bool MSC_HWA_GetCfb(MSC_Type *const pMsc)
{
return (bool)(((pMsc->TCSTR & (uint32_t)MSC_TCSTR_CFB_MASK) != 0U) ? true : false);
}
/**
* @brief Get the DFB value of TCSTR register
*
* @param pMsc MSCInstance
* @return DFB value
*/
LOCAL_INLINE bool MSC_HWA_GetDfb(MSC_Type *const pMsc)
{
return ((pMsc->TCSTR & (uint32_t)MSC_TCSTR_DFB_MASK) != 0U) ? true : false;
}
/**
* @brief Set the NP value of TCSTR register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_SetNp(MSC_Type *const pMsc, uint8_t u8Np)
{
pMsc->TCSTR = (pMsc->TCSTR & ~MSC_TCSTR_NP_MASK) | MSC_TCSTR_NP(u8Np);
}
/**
* @brief Get the NP value of TCSTR register
*
* @param pMsc MSCInstance
* @return NP value
*/
LOCAL_INLINE uint32_t MSC_HWA_GetNp(MSC_Type *const pMsc)
{
return ((pMsc->TCSTR & (uint32_t)MSC_TCSTR_NP_MASK)) >> MSC_TCSTR_NP_SHIFT;
}
/**
* @brief Set the msc TCDAR register
*
* @param pMsc MSCInstance
* @param u32Value TCDAR value
*/
LOCAL_INLINE void MSC_HWA_SetTcdar(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCDAR = u32Value;
}
/**
* @brief Set the TDH of TCDAR register
*
* @param pMsc MSCInstance
* @param u16Value TDH value
*/
LOCAL_INLINE void MSC_HWA_SetTcdarTdh(MSC_Type *const pMsc, uint16_t u16Value)
{
pMsc->TCDAR = (pMsc->TCDAR & ~MSC_TCDAR_TDH_MASK) | MSC_TCDAR_TDH(u16Value);
}
/**
* @brief Set the TDL of TCDAR register
*
* @param pMsc MSCInstance
* @param u16Value TDL value
*/
LOCAL_INLINE void MSC_HWA_SetTcdarTdl(MSC_Type *const pMsc, uint16_t u16Value)
{
pMsc->TCDAR = (pMsc->TCDAR & ~MSC_TCDAR_TDL_MASK) | MSC_TCDAR_TDL(u16Value);
}
/**
* @brief Set the TCCOR register
*
* @param pMsc MSCInstance
* @param u32Value TCCOR value
*/
LOCAL_INLINE void MSC_HWA_SetTccor(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCCOR = u32Value;
}
/**
* @brief Set the TCH of TCCOR register
*
* @param pMsc MSCInstance
* @param u16Value TCH value
*/
LOCAL_INLINE void MSC_HWA_SetTccorTch(MSC_Type *const pMsc, uint16_t u16Value)
{
pMsc->TCCOR = (pMsc->TCCOR & ~MSC_TCCOR_TCH_MASK) | MSC_TCCOR_TCH(u16Value);
}
/**
* @brief Set the TCL of TCCOR register
*
* @param pMsc MSCInstance
* @param u16Value TCL value
*/
LOCAL_INLINE void MSC_HWA_SetTccorTcl(MSC_Type *const pMsc, uint16_t u16Value)
{
pMsc->TCCOR = (pMsc->TCCOR & ~MSC_TCCOR_TCL_MASK) | MSC_TCCOR_TCL(u16Value);
}
/**
* @brief Set the TCSLR register
*
* @param pMsc MSCInstance
* @param u32Value TCSLR value
*/
LOCAL_INLINE void MSC_HWA_SetTcslr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCSLR = u32Value;
}
/**
* @brief Set the TCSHR register
*
* @param pMsc MSCInstance
* @param u32Value TCSHR value
*/
LOCAL_INLINE void MSC_HWA_SetTcshr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCSHR = u32Value;
}
/**
* @brief Set the TCELR register
*
* @param pMsc MSCInstance
* @param u32Value TCELR value
*/
LOCAL_INLINE void MSC_HWA_SetTcelr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCELR = u32Value;
}
/**
* @brief Set the IOCR register
*
* @param pMsc MSCInstance
* @param u32Value IOCR value
*/
LOCAL_INLINE void MSC_HWA_SetIocr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->IOCR = u32Value;
}
/**
* @brief Set the ISCR register
*
* @param pMsc MSCInstance
* @param u32Value ISCR value
*/
LOCAL_INLINE void MSC_HWA_SetIscr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->ISCR = u32Value;
}
/**
* @brief Set the msc TCDIS
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_SetTcdis(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_SDIS_MASK;
}
/**
* @brief Clear the msc TCDIS
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearTcdis(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_CDIS_MASK;
}
/**
* @brief Clear the msc CRFI
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearCrfi(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_CRFI_MASK;
}
/**
* @brief Clear the msc CTFI
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearCtfi(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_CTFI_MASK;
}
/**
* @brief Clear the msc CCFI
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearCcfi(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_CCFI_MASK;
}
/**
* @brief Clear the msc CDFI
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearCdfi(MSC_Type *const pMsc)
{
pMsc->ISCR = MSC_ISCR_CDFI_MASK;
}
/**
* @brief Get the msc INSR register
*
* @param pMsc MSCInstance
* @return INSR register value
*/
LOCAL_INLINE uint32_t MSC_HWA_GetInsr(MSC_Type *const pMsc)
{
return pMsc->INSR & (uint32_t)MSC_INSR_MASK;
}
/**
* @brief Set the INCR register
*
* @param pMsc MSCInstance
* @param u32Value INCR value
*/
LOCAL_INLINE void MSC_HWA_SetIncr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->INCR = u32Value;
}
/**
* @brief Get the msc INCR register
*
* @param pMsc MSCInstance
* @return INCR register value
*/
LOCAL_INLINE uint32_t MSC_HWA_GetIncr(MSC_Type *const pMsc)
{
return pMsc->INCR;
}
/**
* @brief Get the msc RCCSR register
*
* @param pMsc MSCInstance
* @return RCCSR register value
*/
LOCAL_INLINE uint32_t MSC_HWA_GetRccsr(MSC_Type *const pMsc)
{
return pMsc->RCCSR;
}
/**
* @brief Set the RCCSR register
*
* @param pMsc MSCInstance
* @param u32Value RCCSR value
*/
LOCAL_INLINE void MSC_HWA_SetRccsr(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->RCCSR = u32Value;
}
/**
* @brief Get the DATA of RDR0 register
*
* @param pMsc MSCInstance
* @return RDATA value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr0Data(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR0 & MSC_RDR0_RDATA_MASK) >> MSC_RDR0_RDATA_SHIFT);
}
/**
* @brief Get the LAF of RDR0 register
*
* @param pMsc MSCInstance
* @return LAF value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr0Addr(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR0 & MSC_RDR0_LAF_MASK) >> MSC_RDR0_LAF_SHIFT);
}
/**
* @brief Get the VLD of RDR0 register
*
* @param pMsc MSCInstance
* @return VLD value
*/
LOCAL_INLINE bool MSC_HWA_GetRdr0Vld(MSC_Type *const pMsc)
{
return (pMsc->RDR0 & MSC_RDR0_VLD_MASK) == MSC_RDR0_VLD_MASK ? true : false;
}
/**
* @brief Get the RERR of RDR0 register
*
* @param pMsc MSCInstance
* @return RERR value
*/
LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr0Rerr(MSC_Type *const pMsc)
{
uint32_t u32Tempvalue = (pMsc->RDR0 & MSC_RDR0_RERR_MASK) >> MSC_RDR0_RERR_SHIFT;
return (MSC_ReceiveStatusType)u32Tempvalue;
}
/**
* @brief Clear the VLD of register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearRdr0Vld(MSC_Type *const pMsc)
{
pMsc->RDR0 |= MSC_RDR0_CLR_MASK;
}
/**
* @brief Get the DATA of RDR1 register
*
* @param pMsc MSCInstance
* @return RDATA value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr1Data(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR1 & MSC_RDR1_RDATA_MASK) >> MSC_RDR1_RDATA_SHIFT);
}
/**
* @brief Get the LAF of RDR1 register
*
* @param pMsc MSCInstance
* @return LAF value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr1Addr(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR1 & MSC_RDR1_LAF_MASK) >> MSC_RDR1_LAF_SHIFT);
}
/**
* @brief Get the VLD of RDR1 register
*
* @param pMsc MSCInstance
* @return VLD value
*/
LOCAL_INLINE bool MSC_HWA_GetRdr1Vld(MSC_Type *const pMsc)
{
return (pMsc->RDR1 & MSC_RDR1_VLD_MASK) == MSC_RDR1_VLD_MASK ? true : false;
}
/**
* @brief Get the RERR of RDR1 register
*
* @param pMsc MSCInstance
* @return RERR value
*/
LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr1Rerr(MSC_Type *const pMsc)
{
uint32_t u32Tempvalue = (pMsc->RDR1 & MSC_RDR1_RERR_MASK) >> MSC_RDR1_RERR_SHIFT;
return (MSC_ReceiveStatusType)u32Tempvalue ;
}
/**
* @brief Clear the VLD of register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearRdr1Vld(MSC_Type *const pMsc)
{
pMsc->RDR1 |= MSC_RDR1_CLR_MASK;
}
/**
* @brief Get the DATA of RDR2 register
*
* @param pMsc MSCInstance
* @return RDATA value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr2Data(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR2 & MSC_RDR2_RDATA_MASK) >> MSC_RDR2_RDATA_SHIFT);
}
/**
* @brief Get the LAF of RDR2 register
*
* @param pMsc MSCInstance
* @return LAF value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr2Addr(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR2 & MSC_RDR2_LAF_MASK) >> MSC_RDR2_LAF_SHIFT);
}
/**
* @brief Get the VLD of RDR2 register
*
* @param pMsc MSCInstance
* @return VLD value
*/
LOCAL_INLINE bool MSC_HWA_GetRdr2Vld(MSC_Type *const pMsc)
{
return (pMsc->RDR2 & MSC_RDR2_VLD_MASK) == MSC_RDR2_VLD_MASK ? true : false;
}
/**
* @brief Get the RERR of RDR2 register
*
* @param pMsc MSCInstance
* @return RERR value
*/
LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr2Rerr(MSC_Type *const pMsc)
{
uint32_t u32Tempvalue = (pMsc->RDR2 & MSC_RDR2_RERR_MASK) >> MSC_RDR2_RERR_SHIFT;
return (MSC_ReceiveStatusType)u32Tempvalue;
}
/**
* @brief Clear the VLD of register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearRdr2Vld(MSC_Type *const pMsc)
{
pMsc->RDR2 |= MSC_RDR2_CLR_MASK;
}
/**
* @brief Get the DATA of RDR3 register
*
* @param pMsc MSCInstance
* @return RDATA value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr3Data(MSC_Type *const pMsc)
{
return (uint8_t)(pMsc->RDR3 & MSC_RDR3_RDATA_MASK) >> MSC_RDR3_RDATA_SHIFT;
}
/**
* @brief Get the LAF of RDR3 register
*
* @param pMsc MSCInstance
* @return LAF value
*/
LOCAL_INLINE uint8_t MSC_HWA_GetRdr3Addr(MSC_Type *const pMsc)
{
return (uint8_t)((pMsc->RDR3 & MSC_RDR3_LAF_MASK) >> MSC_RDR3_LAF_SHIFT);
}
/**
* @brief Get the VLD of RDR3 register
*
* @param pMsc MSCInstance
* @return VLD value
*/
LOCAL_INLINE bool MSC_HWA_GetRdr3Vld(MSC_Type *const pMsc)
{
return (pMsc->RDR3 & MSC_RDR3_VLD_MASK) == MSC_RDR3_VLD_MASK ? true : false;
}
/**
* @brief Get the RERR of RDR3 register
*
* @param pMsc MSCInstance
* @return RERR value
*/
LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr3Rerr(MSC_Type *const pMsc)
{
uint32_t u32Tempvalue = (pMsc->RDR3 & MSC_RDR3_RERR_MASK) >> MSC_RDR3_RERR_SHIFT;
return (MSC_ReceiveStatusType)u32Tempvalue;
}
/**
* @brief Clear the VLD of register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearRdr3Vld(MSC_Type *const pMsc)
{
pMsc->RDR3 |= MSC_RDR3_CLR_MASK;
}
/**
* @brief Reset the msc
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_SetMsrRst(MSC_Type *const pMsc)
{
pMsc->MSR |= MSC_MSR_RST_MASK;
}
/**
* @brief Get the reset status
*
* @param pMsc MSCInstance
* @return reset status
*/
LOCAL_INLINE bool MSC_HWA_GetMsrRdone(MSC_Type *const pMsc)
{
return (bool)(((pMsc->MSR & MSC_MSR_RDONE_MASK) != 0U) ? true : false);
}
/**
* @brief clear reset status
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_ClearMsrDone(MSC_Type *const pMsc)
{
pMsc->SRCR = MSC_SRCR_RCLR_MASK;
}
/**
* @brief Get the msc RTOR register
*
* @param pMsc MSCInstance
* @return RTOR register value
*/
LOCAL_INLINE uint32_t MSC_HWA_GetRtor(MSC_Type *const pMsc)
{
return pMsc->RTOR;
}
/**
* @brief Set the msc RTOR register
*
* @param pMsc MSCInstance
* @param u32Value RTOR value
*/
LOCAL_INLINE void MSC_HWA_SetRtor(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->RTOR = u32Value;
}
/**
* @brief Get the msc TCCTR1 register
*
* @param pMsc MSCInstance
* @return TCCTR1 register value
*/
LOCAL_INLINE uint32_t MSC_HWA_GetTcctr1(MSC_Type *const pMsc)
{
return pMsc->TCCTR1;
}
/**
* @brief Set the msc TCCTR1 register
*
* @param pMsc MSCInstance
* @param u32Value TCCTR1 value
*/
LOCAL_INLINE void MSC_HWA_SetTcctr1(MSC_Type *const pMsc, uint32_t u32Value)
{
pMsc->TCCTR1 = u32Value;
}
/**
* @brief Set the EN msc GCR register
*
* @param pMsc MSCInstance
* @param bEnable EN value
*/
LOCAL_INLINE void MSC_HWA_SetMscEnable(MSC_Type *const pMsc, bool bEnable)
{
pMsc->GCR = (pMsc->GCR & ~MSC_GCR_EN_MASK) | MSC_GCR_EN(bEnable);
}
/**
* @brief Set the WP_EN of msc GCR register
*
* @param pMsc MSCInstance
* @param bEnable WP_EN value
*/
LOCAL_INLINE void MSC_HWA_SetMscWriteProtection(MSC_Type *const pMsc, bool bEnable)
{
pMsc->GCR = (pMsc->GCR & ~MSC_GCR_WP_EN_MASK) | MSC_GCR_WP_EN(bEnable);
}
/**
* @brief Unlock the msc CCULR register
*
* @param pMsc MSCInstance
*/
LOCAL_INLINE void MSC_HWA_Unlock(MSC_Type *const pMsc)
{
pMsc->CCULR = 0x10248888U;
}
/** @}*/ /* HwA_msc */
#endif /* #if MSC_INSTANCE_COUNT > 0U */
#endif /* #ifndef _HWA_MSC_H_ */

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/**
* @file HwA_ospi.h
* @author Flagchip
* @brief ospi hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip087 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip087 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_OSPI_H_
#define _HWA_OSPI_H_
#include "device_header.h"
#if OSPI_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_ospi HwA_ospi
* @ingroup module_driver_ospi
* @{
*/
typedef enum
{
DQS_INTER_LOOPBACK = 0,
DQS_PAD_LOOPBACK,
DQS_EXTERNAL_PADINPUT
}OSPI_DqsSrcSelType;
typedef enum
{
OSPI_CLOCK_DIV_1 = 0U,
OSPI_CLOCK_DIV_2 = 1U,
OSPI_CLOCK_DIV_3 = 2U,
OSPI_CLOCK_DIV_4 = 3U,
OSPI_CLOCK_DIV_5 = 4U,
OSPI_CLOCK_DIV_6 = 5U,
OSPI_CLOCK_DIV_7 = 6U,
OSPI_CLOCK_DIV_8 = 7U
}OSPI_ClockDivideType;
typedef enum
{
OSPI_MUX_PLL0 = 0,
OSPI_MUX_FIRC,
OSPI_MUX_PLL1
}OSPI_ClockMuxType;
typedef enum
{
OSPI_BIG_ENDIAN = 0,
OSPI_LITTLE_ENDIAN,
}OSPI_EndianType;
#define CTRL_RST_VALUE 0x34000
/********* Local inline function ************/
#ifdef OSPI_CTRL_SWRST
/**
* @brief Generate a software reset of OSPI hardware.
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_SW_Reset(OSPI_Type *pOSPI)
{
pOSPI->CTRL |= OSPI_CTRL_SWRST(1);
pOSPI->CTRL &= ~OSPI_CTRL_SWRST(1);
}
#endif
/**
* @brief OSPI DIO3 Default High
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_Dio3DefHigh(OSPI_Type *pOSPI)
{
pOSPI->CTRL |= OSPI_CTRL_DSDIO3_MASK;
}
/**
* @brief OSPI DIO3 Default Low
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_Dio3DefLow(OSPI_Type *pOSPI)
{
pOSPI->CTRL &= ~OSPI_CTRL_DSDIO3_MASK;
}
/**
* @brief OSPI DIO2 Default High
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_Dio2DefHigh(OSPI_Type *pOSPI)
{
pOSPI->CTRL |= OSPI_CTRL_DSDIO2_MASK;
}
/**
* @brief OSPI DIO2 Default Low
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_Dio2DefLow(OSPI_Type *pOSPI)
{
pOSPI->CTRL &= ~OSPI_CTRL_DSDIO2_MASK;
}
/**
* @brief OSPI Module Enable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_ModuleEnable(OSPI_Type *pOSPI)
{
pOSPI->CTRL &= ~OSPI_CTRL_MDIS_MASK;
}
/**
* @brief OSPI Module Disable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_ModuleDisable(OSPI_Type *pOSPI)
{
pOSPI->CTRL |= OSPI_CTRL_MDIS_MASK;
}
/**
* @brief OSPI Clear Tx fifo
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_ClearTxFifo(OSPI_Type *pOSPI)
{
pOSPI->CTRL |= OSPI_CTRL_CLR_TF_MASK;
}
/**
* @brief OSPI Clear Rx fifo
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_ClearRxFifo(OSPI_Type *pOSPI)
{
pOSPI->CTRL |= OSPI_CTRL_CLR_RF_MASK;
}
/**
* @brief OSPI DDR Mode Enable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_DdrModeEnable(OSPI_Type *pOSPI)
{
pOSPI->CTRL |= OSPI_CTRL_DDR_EN_MASK;
}
/**
* @brief OSPI DDR Mode Disable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_DdrModeDisable(OSPI_Type *pOSPI)
{
pOSPI->CTRL &= ~OSPI_CTRL_DDR_EN_MASK;
}
/**
* @brief OSPI DQS Mode Enable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_DqsModeEnable(OSPI_Type *pOSPI)
{
pOSPI->CTRL |= OSPI_CTRL_RWDS_EN_MASK;
}
/**
* @brief OSPI DQS Mode Disable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_DqsModeDisable(OSPI_Type *pOSPI)
{
pOSPI->CTRL &= ~OSPI_CTRL_RWDS_EN_MASK;
}
/**
* @brief OSPI DQS Lantency Enable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_DqsLatEnable(OSPI_Type *pOSPI)
{
pOSPI->CTRL |= OSPI_CTRL_RWDS_LAT_MASK;
}
/**
* @brief OSPI DQS Lantency Disable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_DqsLatDisable(OSPI_Type *pOSPI)
{
pOSPI->CTRL &= ~OSPI_CTRL_RWDS_LAT_MASK;
}
/**
* @brief OSPI DQS Out Enable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_DqsOutEnable(OSPI_Type *pOSPI)
{
pOSPI->CTRL |= OSPI_CTRL_RWDS_OUT_MASK;
}
/**
* @brief OSPI DQS Out Disable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_DqsOutDisable(OSPI_Type *pOSPI)
{
pOSPI->CTRL &= ~OSPI_CTRL_RWDS_OUT_MASK;
}
/**
* @brief Set OSPI Endian value.
*
* @param pOSPI the base address of the OSPI.
* @param eEndian Endian select value.
*/
LOCAL_INLINE void OSPI_HWA_EndianSelect(OSPI_Type *pOSPI,OSPI_EndianType eEndian)
{
pOSPI->CTRL &= ~OSPI_CTRL_ENDIAN_MASK;
pOSPI->CTRL |= OSPI_CTRL_ENDIAN(eEndian);
}
/**
* @brief Set OSPI CTRL value, users should write the whole value to this register.
*
* @param pOSPI the base address of the OSPI.
* @param u32Value the value which will be written to the CTRL register.
*/
LOCAL_INLINE void OSPI_HWA_SetCtrlValue(OSPI_Type *pOSPI, uint32_t u32Value)
{
pOSPI->CTRL = u32Value;
}
/**
* @brief Read the OSPI CTRL register value for all.
*
* @param pOSPI pOSPI the base address of the OSPI.
* @return OSPI CTRL regsiter value.
*/
LOCAL_INLINE uint32_t OSPI_HWA_GetCtrlValue(OSPI_Type *pOSPI)
{
return pOSPI->CTRL;
}
/**
* @brief Set CMD ID.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value Pointers of current CMD stored in LUT registers.
*/
LOCAL_INLINE void OSPI_HWA_SetCmdId(OSPI_Type *pOSPI, uint16_t u16Value)
{
pOSPI->CMDC &= ~OSPI_CMDC_CMD_ID_MASK;
pOSPI->CMDC |= OSPI_CMDC_CMD_ID(u16Value);
}
/**
* @brief Set CMD SIZE.
*
* @param pOSPI the base address of the OSPI.
* @param u16Value Transfer sizes of current CMD.
*/
LOCAL_INLINE void OSPI_HWA_SetCmdSize(OSPI_Type *pOSPI, uint16_t u16Value)
{
pOSPI->CMDC &= ~OSPI_CMDC_CMD_SIZE_MASK;
pOSPI->CMDC |= OSPI_CMDC_CMD_SIZE(u16Value);
}
/**
* @brief Set CMD id and size.
*
* @param pOSPI the base address of the OSPI.
* @param u8SeqId Pointers of current CMD stored in LUT registers.
* @param u16Size Transfer sizes of current CMD.
*/
LOCAL_INLINE void OSPI_HWA_SetCmdIdSize(OSPI_Type *pOSPI,uint8_t u8SeqId,uint16_t u16Size)
{
pOSPI->CMDC = OSPI_CMDC_CMD_ID(u8SeqId)|OSPI_CMDC_CMD_SIZE(u16Size);
}
/**
* @brief Read the OSPI CMDC register value for all.
*
* @param pOSPI pOSPI the base address of the OSPI.
* @return OSPI CMDC regsiter value.
*/
LOCAL_INLINE uint32_t OSPI_HWA_GetCmdcValue(OSPI_Type *pOSPI)
{
return pOSPI->CMDC;
}
/**
* @brief Set Data Hold Time,This bit should only be valid in DDR mode.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value Data Hold Time.
*/
LOCAL_INLINE void OSPI_HWA_SetDataHoldTime(OSPI_Type *pOSPI, uint8_t u8Value)
{
pOSPI->FLS_CFG &= ~OSPI_FLS_CFG_TDH_MASK;
pOSPI->FLS_CFG |= OSPI_FLS_CFG_TDH(u8Value);
}
/**
* @brief Set CS Hold Time.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value CS Hold Time.
*/
LOCAL_INLINE void OSPI_HWA_SetCsHoldTime(OSPI_Type *pOSPI, uint8_t u8Value)
{
pOSPI->FLS_CFG &= ~OSPI_FLS_CFG_TCSH_MASK;
pOSPI->FLS_CFG |= OSPI_FLS_CFG_TCSH(u8Value);
}
/**
* @brief Set CS Setup Time.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value CS Setup Time.
*/
LOCAL_INLINE void OSPI_HWA_SetCsSetupTime(OSPI_Type *pOSPI, uint8_t u8Value)
{
pOSPI->FLS_CFG &= ~OSPI_FLS_CFG_TCSS_MASK;
pOSPI->FLS_CFG |= OSPI_FLS_CFG_TCSS(u8Value);
}
/**
* @brief Read the OSPI CMDC register value for all.
*
* @param pOSPI pOSPI the base address of the OSPI.
* @return OSPI CMDC regsiter value.
*/
LOCAL_INLINE uint32_t OSPI_HWA_GetFlashCfgValue(OSPI_Type *pOSPI)
{
return pOSPI->FLS_CFG;
}
/**
* @brief OSPI Enable internal reference clock
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_InternalRefclkEnable(OSPI_Type *pOSPI)
{
pOSPI->SOC_CFG |= OSPI_SOC_CFG_CLK_EN_MASK;
}
/**
* @brief OSPI Disable internal reference clock
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_InternalRefclkDisable(OSPI_Type *pOSPI)
{
pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_CLK_EN_MASK;
}
/**
* @brief OSPI Set Internal Reference Clock Divider.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value Internal Reference Clock Divider.
*/
LOCAL_INLINE void OSPI_HWA_InternalRefclkDiv(OSPI_Type *pOSPI, OSPI_ClockDivideType eClkDiv)
{
pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_CLK_DIV_MASK;
pOSPI->SOC_CFG |= OSPI_SOC_CFG_CLK_DIV(eClkDiv);
}
/**
* @brief OSPI PAD IBE Enable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_PadIbeEnable(OSPI_Type *pOSPI)
{
pOSPI->SOC_CFG |= OSPI_SOC_CFG_IBE_EN_MASK;
}
/**
* @brief OSPI PAD IBE Disable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_PadIbeDisable(OSPI_Type *pOSPI)
{
pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_IBE_EN_MASK;
}
/**
* @brief OSPI Select Internal Reference Clock Source.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value Internal Reference Clock Source.
*/
LOCAL_INLINE void OSPI_HWA_InternalRefclkSource(OSPI_Type *pOSPI, OSPI_ClockMuxType u8Value)
{
pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_CLK_MUX_MASK;
pOSPI->SOC_CFG |= OSPI_SOC_CFG_CLK_MUX(u8Value);
}
/**
* @brief OSPI Use inverted DQS
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_DqsInvertedEnable(OSPI_Type *pOSPI)
{
pOSPI->SOC_CFG |= OSPI_SOC_CFG_RWDS_INV_MASK;
}
/**
* @brief OSPI Not use inverted DQS
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_DqsInvertedDisable(OSPI_Type *pOSPI)
{
pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_RWDS_INV_MASK;
}
/**
* @brief OSPI Select DQS Source.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value DQS Source.
*/
LOCAL_INLINE void OSPI_HWA_DqsSource(OSPI_Type *pOSPI, OSPI_DqsSrcSelType u8Value)
{
pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_RWDS_INV_MASK;
pOSPI->SOC_CFG |= OSPI_SOC_CFG_RWDS_MUX(u8Value);
}
/**
* @brief OSPI OBE timing relax enable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_ObeTimRelaxEnable(OSPI_Type *pOSPI)
{
pOSPI->SOC_CFG |= OSPI_SOC_CFG_OBE_RELAX_MASK;
}
/**
* @brief OSPI OBE timing relax disable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_ObeTimRelaxDisable(OSPI_Type *pOSPI)
{
pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_OBE_RELAX_MASK;
}
/**
* @brief OSPI DDR Clock Enable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_DdrClkEnable(OSPI_Type *pOSPI)
{
pOSPI->SOC_CFG |= OSPI_SOC_CFG_DDR_EN_MASK;
}
/**
* @brief OSPI DDR Clock Disable
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_DdrClkDisable(OSPI_Type *pOSPI)
{
pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_DDR_EN_MASK;
}
/**
* @brief OSPI Switch Delay Line into DQS for timing. DQS will delay for DLLINE_CFG * Tcell.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value DQS Delay Line Cfg Value.
*/
LOCAL_INLINE void OSPI_HWA_CfgDelayLine(OSPI_Type *pOSPI, uint8_t u8Value)
{
pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_DLLINE_CFG_MASK;
pOSPI->SOC_CFG |= OSPI_SOC_CFG_DLLINE_CFG(u8Value);
}
/**
* @brief Write the OSPI SOC CFG register.
*
* @param pOSPI pOSPI the base address of the OSPI.
* @param u32Value the value to be writen.
*/
LOCAL_INLINE void OSPI_HWA_SetSocCfgValue(OSPI_Type *pOSPI, uint32_t u32Value)
{
pOSPI->SOC_CFG = u32Value;
}
/**
* @brief Read the OSPI SOC CFG register value for all.
*
* @param pOSPI pOSPI the base address of the OSPI.
* @return OSPI SOC_CFG regsiter value.
*/
LOCAL_INLINE uint32_t OSPI_HWA_GetSocCfgValue(OSPI_Type *pOSPI)
{
return pOSPI->SOC_CFG;
}
/**
* @brief Set flash address, users should write the whole value to this register.
*
* @param pOSPI the base address of the OSPI.
* @param u32Value the value which will be written to the FLS_AR register.
*/
LOCAL_INLINE void OSPI_HWA_SetFlashAddr(OSPI_Type *pOSPI, uint32_t u32Value)
{
pOSPI->FLS_AR = u32Value;
}
/**
* @brief Set flash addressable mode.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value the value of addressable mode.
*/
LOCAL_INLINE void OSPI_HWA_SetFlashAddrMode(OSPI_Type *pOSPI, uint8_t u8Value)
{
pOSPI->FLS_CAR &= ~OSPI_FLS_CAR_WA_MASK;
pOSPI->FLS_CAR |= OSPI_FLS_CAR_WA(u8Value);
}
/**
* @brief Set Column Address Space.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value the value of Column Address Space.
*/
LOCAL_INLINE void OSPI_HWA_SetColAddrSpace(OSPI_Type *pOSPI, uint8_t u8Value)
{
pOSPI->FLS_CAR &= ~OSPI_FLS_CAR_CAS_MASK;
pOSPI->FLS_CAR |= OSPI_FLS_CAR_CAS(u8Value);
}
/**
* @brief Set Sample delay clock cycle.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value the value of Sample Delay clock cycle.
*/
LOCAL_INLINE void OSPI_HWA_SetSampleDlyClkCycle(OSPI_Type *pOSPI, uint8_t u8Value)
{
pOSPI->SAMP_CTRL &= ~OSPI_SAMP_CTRL_DLY_MASK;
pOSPI->SAMP_CTRL |= OSPI_SAMP_CTRL_DLY(u8Value);
}
/**
* @brief Selects reference clock edge for valid sampling phase.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value the value of reference clock edge.
*/
LOCAL_INLINE void OSPI_HWA_SelectRefClkEdge(OSPI_Type *pOSPI, uint8_t u8Value)
{
pOSPI->SAMP_CTRL &= ~OSPI_SAMP_CTRL_PHS_MASK;
pOSPI->SAMP_CTRL |= OSPI_SAMP_CTRL_PHS(u8Value);
}
/**
* @brief Read RX FIFO Counter,Indicates the current RX FIFO read pointer;
* Automatically increases when RX FIFO pops an event.
*
* @param pOSPI pOSPI the base address of the OSPI.
* @return RX FIFO Counter.
*/
LOCAL_INLINE uint16_t OSPI_HWA_GetRxFifoCnt(OSPI_Type *pOSPI)
{
return (uint16_t)((pOSPI->RFSR&OSPI_RFSR_RFCTR_MASK)>>OSPI_RFSR_RFCTR_SHIFT);
}
/**
* @brief Read RX FIFO Fill Level,Indicates how many words are available in RX FIFO.
*
* @param pOSPI pOSPI the base address of the OSPI.
* @return RX FIFO Fill Level.
*/
LOCAL_INLINE uint8_t OSPI_HWA_GetRxFifoFillLevel(OSPI_Type *pOSPI)
{
return (uint8_t)((pOSPI->RFSR&OSPI_RFSR_RFFL_MASK)>>OSPI_RFSR_RFFL_SHIFT);
}
/**
* @brief Set RX FIFO Watermark,
* Indicates how many valid entries will trigger a readout action.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value the value of RX FIFO Watermark.
*/
LOCAL_INLINE void OSPI_HWA_SetRxFifoWaterMark(OSPI_Type *pOSPI, uint8_t u8Value)
{
pOSPI->RF_CFG &= ~OSPI_RF_CFG_WMRK_MASK;
pOSPI->RF_CFG |= OSPI_RF_CFG_WMRK(u8Value);
}
/**
* @brief Read TX FIFO Counter,Indicates the current TX FIFO stored data pointer;
* Automatically increases when TX FIFO pops an event.
*
* @param pOSPI pOSPI the base address of the OSPI.
* @return TX FIFO Counter.
*/
LOCAL_INLINE uint16_t OSPI_HWA_GetTxFifoCnt(OSPI_Type *pOSPI)
{
return (uint16_t)((pOSPI->TFSR&OSPI_TFSR_TFCTR_MASK)>>OSPI_TFSR_TFCTR_SHIFT);
}
/**
* @brief Read TX FIFO Fill Level,Indicates how many words are available in TX FIFO.
*
* @param pOSPI pOSPI the base address of the OSPI.
* @return TX FIFO Fill Level.
*/
LOCAL_INLINE uint8_t OSPI_HWA_GetTxFifoFillLevel(OSPI_Type *pOSPI)
{
return (uint8_t)((pOSPI->TFSR&OSPI_TFSR_TFFL_MASK)>>OSPI_TFSR_TFFL_SHIFT);
}
/**
* @brief Get transmit fifo register address.
*
* @param pOSPI the base address of the OSPI.
* @return Transmit fifo register address.
*/
LOCAL_INLINE uint32_t OSPI_HWA_GetTFDRAddr(OSPI_Type *pOSPI)
{
return (uint32_t)&pOSPI->TFDR;
}
/**
* @brief Writing this register will trigger data entry of TX FIFO.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value the value of tx data.
*/
LOCAL_INLINE void OSPI_HWA_WriteTxData(OSPI_Type *pOSPI, uint32_t u32Value)
{
pOSPI->TFDR = u32Value;
}
/**
* @brief Set TX FIFO Watermark,
* Indicates how many valid entries will trigger a transmit action.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value the value of TX FIFO Watermark.
*/
LOCAL_INLINE void OSPI_HWA_SetTxFifoWaterMark(OSPI_Type *pOSPI, uint8_t u8Value)
{
pOSPI->TF_CFG &= ~OSPI_TF_CFG_WMRK_MASK;
pOSPI->TF_CFG |= OSPI_TF_CFG_WMRK(u8Value);
}
/**
* @brief Read status register.
*
* @param pOSPI pOSPI the base address of the OSPI.
* @return Status register.
*/
LOCAL_INLINE uint32_t OSPI_HWA_GetStatus(OSPI_Type *pOSPI)
{
return pOSPI->STATUS&OSPI_STATUS_MASK;
}
/**
* @brief Read flag register.
*
* @param pOSPI pOSPI the base address of the OSPI.
* @return flag register.
*/
LOCAL_INLINE uint32_t OSPI_HWA_GetFlag(OSPI_Type *pOSPI)
{
return pOSPI->FLAG&OSPI_FLAG_MASK;
}
/**
* @brief Writing this register will clear ospi flag.
*
* @param pOSPI the base address of the OSPI.
* @param u8Value the value of flag to be cleared.
*/
LOCAL_INLINE void OSPI_HWA_ClearFlag(OSPI_Type *pOSPI, uint32_t u32Value)
{
pOSPI->FLAG = (u32Value&OSPI_FLAG_MASK);
}
/**
* @brief Set the OSPI IND_EN register value for enable or disable interrupts&DMA.
*
* @param pOSPI the base address of the OSPI.
* @param u32Value the value write to the register.
*/
LOCAL_INLINE void OSPI_HWA_SetIntDmasEnableReg(OSPI_Type *pOSPI, uint32_t u32Value)
{
pOSPI->IND_EN = (u32Value&OSPI_IND_EN_MASK);
}
/**
* @brief Set the OSPI Rx DMA mode.
*
* @param pOSPI the base address of the OSPI.
* @param u8Enable open or close rx dma mode.
*/
LOCAL_INLINE void OSPI_HWA_SetRxDMA(OSPI_Type *pOSPI, uint8_t u8Enable)
{
if (u8Enable)
{
pOSPI->IND_EN |= OSPI_IND_EN_RFDDRE_MASK;
}
else
{
pOSPI->IND_EN &= ~OSPI_IND_EN_RFDDRE_MASK;
}
}
/**
* @brief Set the OSPI Tx DMA mode.
*
* @param pOSPI the base address of the OSPI.
* @param u8Enable open or close tx dma mode.
*/
LOCAL_INLINE void OSPI_HWA_SetTxDMA(OSPI_Type *pOSPI, uint8_t u8Enable)
{
if (u8Enable)
{
pOSPI->IND_EN |= OSPI_IND_EN_TFFDRE_MASK;
}
else
{
pOSPI->IND_EN &= ~OSPI_IND_EN_TFFDRE_MASK;
}
}
/**
* @brief Set flash top address register.
*
* @param pOSPI the base address of the OSPI.
* @param Top Address of Flash Device.
*/
LOCAL_INLINE void OSPI_HWA_SetFlashTopAddr(OSPI_Type *pOSPI, uint32_t u32Value)
{
pOSPI->FLS_TAR = (u32Value&OSPI_FLS_TAR_MASK);
}
/**
* @brief Get receive fifo register address.
*
* @param pOSPI the base address of the OSPI.
* @return Receive fifo register address.
*/
LOCAL_INLINE uint32_t OSPI_HWA_GetRFDRAddr(OSPI_Type *pOSPI)
{
return (uint32_t)pOSPI->RFDR;
}
/**
* @brief Read receive fifo data register.
*
* @param pOSPI the base address of the OSPI.
* @param u8Idx Fifo index to be read.
* @return Receive fifo data register.
*/
LOCAL_INLINE uint32_t OSPI_HWA_ReadRcvFifoReg(OSPI_Type *pOSPI,uint8_t u8Idx)
{
return pOSPI->RFDR[u8Idx];
}
/**
* @brief Read secondary receive fifo data register.
*
* @param pOSPI the base address of the OSPI.
* @return Secondary receive fifo data register.
*/
LOCAL_INLINE uint32_t OSPI_HWA_ReadSecondaryRcvFifoReg(OSPI_Type *pOSPI)
{
return pOSPI->RFD2R;
}
/**
* @brief Write LUT Key register.
*
* @param pOSPI the base address of the OSPI.
* @param u32Value LUT Key Value to be writed.
*/
LOCAL_INLINE void OSPI_HWA_WriteLutKey(OSPI_Type *pOSPI, uint32_t u32Value)
{
pOSPI->LUT_KEY = u32Value;
}
/**
* @brief Read LUT Key register.
*
* @param pOSPI the base address of the OSPI.
* @return LUT Key Value.
*/
LOCAL_INLINE uint32_t OSPI_HWA_ReadLutKey(OSPI_Type *pOSPI)
{
return pOSPI->LUT_KEY;
}
/**
* @brief Lock the LUT.
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_LockLut(OSPI_Type *pOSPI)
{
pOSPI->LUT_CFG = OSPI_LUT_CFG_LOCK_MASK;
}
/**
* @brief Unlock the LUT.
*
* @param pOSPI the base address of the OSPI.
*/
LOCAL_INLINE void OSPI_HWA_UnlockLut(OSPI_Type *pOSPI)
{
pOSPI->LUT_CFG = OSPI_LUT_CFG_UNLOCK_MASK;
}
/**
* @brief Write lookup table register.
*
* @param pOSPI the base address of the OSPI.
* @param u8Idx Index of LUT.
* @param u32Value LUT Value to be writed.
*/
LOCAL_INLINE void OSPI_HWA_WriteLut(OSPI_Type *pOSPI, uint8_t u8Idx, uint32_t u32Value)
{
pOSPI->LUT[u8Idx] = u32Value;
}
#endif /* #if OSPI_INSTANCE_COUNT > 0U */
#endif /* #ifndef _HWA_OSPI_H_ */

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/**
* @file HwA_overlay.h
* @author Flagchip
* @brief FC4xxx Overlay hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip038 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip038 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_OVERLAY_H_
#define _HWA_OVERLAY_H_
#include "device_header.h"
#if AHB_OVERLAY_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_overlay HwA_overlay
* @ingroup module_driver_overlay
* @{
*/
/** @brief Overlay Region Count */
#define OVERLYA_REGION_CNT 3U
/** @brief FAR source address */
#define OVERLAY_FAR_SRC 0x08000000U
/** @brief FAR max size */
#define OVERLAY_FAR_SIZE_MAX 0x2000000U
/** @brief FAR size align */
#define OVERLAY_FAR_SIZE_ALIGN 0x10000U
/** @brief FAR size max mask **/
#define OVERLAY_FAR_SIZE_MASK 0xFFFFU
#if AHB_OVERLAY_EN_UNLOCK == STD_ON
#define OVERLAY_EN_UNLOCK_KEY 0xECFEAA55
#endif
/**
* @brief FAR Size
*
*/
typedef enum
{
OVERLAY_FARUINTSIZE_64KB = 0x10000, /**< OVERLAY_FARUINTSIZE_64KB, remapping far uint size to 64KB */
}OVERLAY_FARSizeType;
/**
* @brief enable overlay global switch
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayEnable(void)
{
#if AHB_OVERLAY_EN_UNLOCK == STD_ON
AHB_OVERLAY->GLOBAL_EN = OVERLAY_EN_UNLOCK_KEY;
#endif
AHB_OVERLAY->GLOBAL_EN |= AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK;
}
/**
* @brief disable overlay global switch
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayDisable(void)
{
#if AHB_OVERLAY_EN_UNLOCK == STD_ON
AHB_OVERLAY->GLOBAL_EN = OVERLAY_EN_UNLOCK_KEY;
#endif
AHB_OVERLAY->GLOBAL_EN &= ~((uint32_t)AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK);
}
/**
* @brief enable far global switch
*
*/
LOCAL_INLINE void OVERLAY_HWA_FAREnable(void)
{
#if AHB_OVERLAY_EN_UNLOCK == STD_ON
AHB_OVERLAY->GLOBAL_EN = OVERLAY_EN_UNLOCK_KEY;
#endif
AHB_OVERLAY->GLOBAL_EN |= AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK;
}
/**
* @brief disable far global switch
*
*/
LOCAL_INLINE void OVERLAY_HWA_FARDisable(void)
{
#if AHB_OVERLAY_EN_UNLOCK == STD_ON
AHB_OVERLAY->GLOBAL_EN = OVERLAY_EN_UNLOCK_KEY;
#endif
AHB_OVERLAY->GLOBAL_EN &= ~((uint32_t)AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK);
}
/**
* @brief enable overlay region 0
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayRegion0Enable(void)
{
AHB_OVERLAY->REGION_0_EN |= AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK;
}
/**
* @brief disable overlay region 0
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayRegion0Disable(void)
{
AHB_OVERLAY->REGION_0_EN &= ~((uint32_t)AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK);
}
/**
* @brief Set Overlay Region 0 Source
*
* @param u32Src Source address
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Src(uint32_t u32Src)
{
AHB_OVERLAY->REGION_0_SRC = AHB_OVERLAY_REGION_0_SRC_REGION0_SRC(u32Src);
}
/**
* @brief Set Overlay Region 0 Destination
*
* @param u32Dst Destination address
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Dst(uint32_t u32Dst)
{
AHB_OVERLAY->REGION_0_DST = AHB_OVERLAY_REGION_0_DST_REGION0_DST(u32Dst);
}
/**
* @brief Set Overlay Region 0 Size
*
* @param eSize size
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Size(OVERLAY_OverlaySizeType eSize)
{
AHB_OVERLAY->REGION_0_SIZE = AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE((uint32_t)eSize);
}
/**
* @brief enable overlay region 1
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayRegion1Enable(void)
{
AHB_OVERLAY->REGION_1_EN |= AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK;
}
/**
* @brief disable overlay region 1
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayRegion1Disable(void)
{
AHB_OVERLAY->REGION_1_EN &= ~((uint32_t)AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK);
}
/**
* @brief Set Overlay Region 1 Source
*
* @param u32Src Source address
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Src(uint32_t u32Src)
{
AHB_OVERLAY->REGION_1_SRC = AHB_OVERLAY_REGION_1_SRC_REGION1_SRC(u32Src);
}
/**
* @brief Set Overlay Region 1 Destination
*
* @param u32Dst Destination address
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Dst(uint32_t u32Dst)
{
AHB_OVERLAY->REGION_1_DST = AHB_OVERLAY_REGION_1_DST_REGION1_DST(u32Dst);
}
/**
* @brief Set Overlay Region 1 Size
*
* @param eSize size
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Size(OVERLAY_OverlaySizeType eSize)
{
AHB_OVERLAY->REGION_1_SIZE = AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE((uint32_t)eSize);
}
/**
* @brief enable overlay region 2
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayRegion2Enable(void)
{
AHB_OVERLAY->REGION_2_EN |= AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK;
}
/**
* @brief disable overlay region 2
*
*/
LOCAL_INLINE void OVERLAY_HWA_OverlayRegion2Disable(void)
{
AHB_OVERLAY->REGION_2_EN &= ~((uint32_t)AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK);
}
/**
* @brief Set Overlay Region 2 Source
*
* @param u32Src Source address
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Src(uint32_t u32Src)
{
AHB_OVERLAY->REGION_2_SRC = AHB_OVERLAY_REGION_2_SRC_REGION2_SRC(u32Src);
}
/**
* @brief Set Overlay Region 2 Destination
*
* @param u32Dst Destination address
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Dst(uint32_t u32Dst)
{
AHB_OVERLAY->REGION_2_DST = AHB_OVERLAY_REGION_2_DST_REGION2_DST(u32Dst);
}
/**
* @brief Set Overlay Region 2 Size
*
* @param eSize size
*/
LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Size(OVERLAY_OverlaySizeType eSize)
{
AHB_OVERLAY->REGION_2_SIZE = AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE((uint32_t)eSize);
}
/**
* @brief Set Far Destination
*
* @param u32Dst Destination address, must pflash
*/
LOCAL_INLINE void OVERLAY_HWA_SetFarDst(uint32_t u32Dst)
{
AHB_OVERLAY->FAR_DST = AHB_OVERLAY_FAR_DST_FAR_DST_ADDR(u32Dst);
}
/**
* @brief Set Far Size
*
* @param u32Size size=(u32Size+1)*64KB
*/
LOCAL_INLINE void OVERLAY_HWA_SetFarSize(uint32_t u32Size)
{
AHB_OVERLAY->FAR_SIZE = AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL(u32Size);
}
/**
* @brief enable error interrupt
*
*/
LOCAL_INLINE void OVERLAY_HWA_ErrorInterruptEnable(void)
{
AHB_OVERLAY->INTR_EN |= AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK;
}
/**
* @brief disable error interrupt
*
*/
LOCAL_INLINE void OVERLAY_HWA_ErrorInterruptDisable(void)
{
AHB_OVERLAY->INTR_EN &= ~((uint32_t)AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK);
}
/**
* @brief get error flag
*
*/
LOCAL_INLINE uint32 OVERLAY_HWA_GetErrorFlag(void)
{
return (AHB_OVERLAY->INTR_FLAG & AHB_OVERLAY_INTR_FLAG_MASK);
}
/**
* @brief clear error flag
*
*/
LOCAL_INLINE uint32 OVERLAY_HWA_ClrErrorFlag(uint32_t u32ClrBits)
{
return AHB_OVERLAY->INTR_CLR |= AHB_OVERLAY_INTR_FLAG_MASK & u32ClrBits;
}
/** @}*/
#endif /* #if AHB_OVERLAY_INSTANCE_COUNT > 0U */
#endif /* _HWA_OVERLAY_H_ */

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/**
* @file HwA_pmc.h
* @author flagchip
* @brief PMC register API
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip095 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip095 N/A Change version and release
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_PMC_H_
#define HWA_INCLUDE_HWA_PMC_H_
#include "device_header.h"
#if PMC_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_pmc
* @ingroup module_driver_pmc
* @{
*/
/**
* @brief get PMC LVCSR register
*
* @return uint32_t LVCSR register value
*/
LOCAL_INLINE uint32_t PMC_HWA_GetLVSCR(void)
{
return (uint32)(PMC->LVSCR);
}
/**
* @brief set PMC LVCSR register.
*
* This function configures the PMC LVCSR registe.
*
* @param u32Val Set PMC LVCSR register value.
*/
LOCAL_INLINE void PMC_HWA_SetLVSCR(uint32_t u32Val)
{
PMC->LVSCR = u32Val;
}
/**
* @brief get PMC CONFIG register
*
* @return uint32_t CONFIG register value
*/
LOCAL_INLINE uint32_t PMC_HWA_GetCONFIG(void)
{
return (uint32)(PMC->CONFIG);
}
/**
* @brief set PMC CONFIG register.
*
* This function configures the PMC CONFIG registe.
*
* @param u32LVSCRValue Set PMC CONFIG register value.
*/
LOCAL_INLINE void PMC_HWA_SetCONFIG(uint32_t u32Val)
{
PMC->CONFIG = u32Val;
}
/**
* @brief HWA Disable PMC interrupt
*
* @param the parameter of interrupt flag
*/
LOCAL_INLINE void PMC_HWA_DisableInterrupt(uint32 u32Val)
{
PMC->CONFIG &= (~u32Val);
}
/**
* @brief HWA Enable PMC interrupt
*
* @param the parameter of interrupt flag
*/
LOCAL_INLINE void Pmc_HWA_EnableInterrupt(uint32 u32Val)
{
PMC->CONFIG |= u32Val;
}
/**
* @brief Return Low Voltage Detect Interrupt Enable Flag
*
* @return 0: Low Voltage Detect Interrupt Disabled; 1: Low Voltage Detect Interrupt Enabled
*/
LOCAL_INLINE bool PMC_ReadLVDInterruptFlag(void)
{
return (bool) ((PMC->CONFIG & PMC_CONFIG_LVD_IE_MASK) >> PMC_CONFIG_LVD_IE_SHIFT);
}
/**
* @brief Return High Voltage Detect Interrupt Enable Flag
*
* @return 0: High Voltage Detect Interrupt Disabled; 1: High Voltage Detect Interrupt Enabled
*/
LOCAL_INLINE bool PMC_ReadHVDInterruptFlag(void)
{
return (bool) ((PMC->CONFIG & PMC_CONFIG_HVD_IE_MASK) >> PMC_CONFIG_HVD_IE_SHIFT);
}
/** @}*/
#endif /* #if PMC_INSTANCE_COUNT > 0U */
#endif /* HWA_INCLUDE_HWA_PMC_H_ */

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/**
* @file HwA_port.h
* @author Flagchip
* @brief PORT hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip071 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip071 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_PORT_H_
#define _HWA_PORT_H_
#include "device_header.h"
#if PORT_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_port HwA_port
* @ingroup module_driver_port
* @{
*/
/********* Local inline function ************/
/**
* @brief Configure pin
*
* @param pPort Port instance
* @param u8Pin Pin number
* @param u32PcrReg Pin PCR register value
*/
LOCAL_INLINE void PORT_HWA_ConfigPin(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32PcrReg)
{
pPort->PCR[u8Pin] = u32PcrReg;
}
/**
* @brief Read pin interrupt flag
*
* @param pPort Port instance
* @param u8Pin Pin number
* @return interrupt flag value
*/
LOCAL_INLINE uint32_t PORT_HWA_ReadPinInterruptFlag(PORT_Type *pPort, uint8_t u8Pin)
{
return pPort->PCR[u8Pin] & (uint32_t)PORT_PCR_ISF_MASK;
}
/**
* @brief Set pin multiplexing
*
* @param pPort Port instance
* @param u8Pin Pin number
* @param Port_PinMuxType Pin MXU configuration value
*/
LOCAL_INLINE void PORT_HWA_SetPinMux(PORT_Type *pPort, uint8_t u8Pin, Port_PinMuxType u32PinMux)
{
uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]);
pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_MUX_MASK) | PORT_PCR_MUX(u32PinMux.u32PortPinMode));
}
/**
* @brief Set Pin Emergency Stop
*
* @param pPort Port instance
* @param u8Pin Pin number
* @param bEnable Enable or Disable Emergency Stop of this Pin
*/
LOCAL_INLINE void PORT_HWA_SetPinEmgcyStop(PORT_Type *pPort, uint8_t u8Pin, bool bEnable)
{
uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]);
pPort->PCR[u8Pin] = (u32TempRegVal & (~ (uint32_t)PORT_PCR_ESTOP_MASK)) | PORT_PCR_ESTOP(bEnable);
}
/**
* @brief Set pin interrupt mode
*
* @param pPort Port instance
* @param u8Pin Pin number
* @param u32PinIrqc Pin IRQC configuration value
*/
LOCAL_INLINE void PORT_HWA_SetPinInterruptMode(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32PinIrqc)
{
uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]);
pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(u32PinIrqc));
}
/**
* @brief Set pin pull enable
*
* @param pPort Port instance
* @param u8Pin Pin number
* @param u8PeValue Pin PE configuration value(1/0)
*/
LOCAL_INLINE void PORT_HWA_SetPinPullEnable(PORT_Type *pPort, uint8_t u8Pin, uint8_t u8PeValue)
{
if (u8PeValue)
{
pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_PE_MASK;
}
else
{
pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_PE_MASK;
}
}
/**
* @brief Set pin pull mode
*
* @param pPort Port instance
* @param u8Pin Pin number
* @param u8PsValue Pin PS configuration value(1/0)
*/
LOCAL_INLINE void PORT_HWA_SetPinPullMode(PORT_Type *pPort, uint8_t u8Pin, uint8_t u8PsValue)
{
if (u8PsValue)
{
pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_PS_MASK;
}
else
{
pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_PS_MASK;
}
}
/**
* @brief Set pin drive strength
*
* @param pPort Port instance
* @param u8Pin Pin number
* @note only hs PAD use this bit
*/
LOCAL_INLINE void PORT_HWA_SetPinDriveStrength(PORT_Type *pPort, uint8_t u8Pin)
{
pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_DSE0_MASK;
}
/**
* @brief Set pin passive filter enable
*
* @param pPort Port instance
* @param u8Pin Pin number
* @param u8PfeValue Pin PFE configuration value(1/0)
*/
LOCAL_INLINE void PORT_HWA_SetPinPassiveFilterEnable(PORT_Type *pPort, uint8_t u8Pin, uint8_t u8PfeValue)
{
if (u8PfeValue)
{
pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_PFE_MASK;
}
else
{
pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_PFE_MASK;
}
}
/**
* @brief Configure port digital filter
*
* @param pPort Port instance
* @param u32RegValue Enable bit,0-31 bit indicate pin 0-31
*/
LOCAL_INLINE void PORT_HWA_ConfigDigitalFilter(PORT_Type *pPort, uint32_t u32RegValue)
{
pPort->DFER = u32RegValue;
}
/**
* @brief Set port digital filter enable
*
* @param pPort Port instance
* @param u8RegBit DFER register bit
*/
LOCAL_INLINE void PORT_HWA_SetDigitalFilterEnable(PORT_Type *pPort, uint8_t u8RegBit)
{
pPort->DFER |= (uint32_t)1 << u8RegBit;
}
/**
* @brief Set port digital filter clock source
*
* @param pPort Port instance
* @param eClkSrc Digital filter clock source
*/
LOCAL_INLINE void PORT_HWA_SetDigitalFilterClkSrc(PORT_Type *pPort)
{
pPort->DFCR |= 1U;
}
/**
* @brief Configure digital filter width
* @param pPort Port instance
* @param u32FilterWidth Digital filter length value,range:0-31
*/
LOCAL_INLINE void PORT_HWA_ConfigDigitalFilterWidth(PORT_Type *pPort, uint32_t u32FilterWidth)
{
pPort->DFWR = PORT_DFWR_FILT(u32FilterWidth);
}
/**
* @brief Clear pin interrupt mode
*
* @param pPort Port instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void PORT_HWA_ClearPinInterruptMode(PORT_Type *pPort, uint8_t u8Pin)
{
pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_IRQC_MASK;
}
/**
* @brief Clear pin interrupt flag
*
* @param pPort Port instance
* @param u8Pin Pin number
*/
LOCAL_INLINE void PORT_HWA_ClearPinInterruptFlag(PORT_Type *pPort, uint8_t u8Pin)
{
pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_ISF_MASK;
}
/**
* @brief CLear port digital filter enable
*
* @param pPort Port instance
*/
LOCAL_INLINE void PORT_HWA_ClearDigitalFilterEnable(PORT_Type *pPort)
{
pPort->DFER = (uint32_t)0U;
}
/**
* @brief Clear port digital filter enable for specific pin
*
* @param pPort Port instance
* @param u8RegBit DFER register bit
*/
LOCAL_INLINE void PORT_HWA_ClearDigitalFilterPin(PORT_Type *pPort, uint8_t u8RegBit)
{
pPort->DFER &= (uint32_t)~((uint32_t)1 << u8RegBit);
}
/**
* @brief Clear port digital filter clock source
*
* @param pPort Port instance
*/
LOCAL_INLINE void PORT_HWA_ClearDigitalFilterClkSrc(PORT_Type *pPort)
{
pPort->DFCR &= ~(uint32_t)PORT_DFCR_CS_MASK;
}
/**
* @brief Clear port digital filter width
*
* @param pPort Port instance
*/
LOCAL_INLINE void PORT_HWA_ClearDigitalFilterWidth(PORT_Type *pPort)
{
pPort->DFWR &= ~(uint32_t)PORT_DFWR_FILT_MASK;
}
/** @}*/
#endif
#endif /* #ifndef _HWA_PORT_H_ */

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/**
* @file HwA_ptimer.h
* @author flagchip
* @brief Hardware access layer for PTIMER
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip030 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_PTIMER_H_
#define _HWA_PTIMER_H_
#include "device_header.h"
#if PTIMER_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_ptimer HwA_ptimer
* @ingroup module_driver_ptimer
* @{
*/
/**
* @brief Ptimer value load mode
*
* Some Ptimer registers are buffered and will only take effect after called
* PTIMER_LoadValue() function, and this option selects when the buffered configurations
* will tack effect after PTIMER_LoadValue() is called.
*
*/
typedef enum
{
PTIMER_LOAD_VAL_IMMEDIATELY = 0U,
/*!< Loaded immediately after load operation. */
PTIMER_LOAD_VAL_AT_MODULO_COUNTER = 1U,
/*!< Loaded when counter hits the max count after load operation. */
PTIMER_LOAD_VAL_AT_NEXT_TRIGGER = 2U,
/*!< Loaded when detecting an input trigger after load operation. */
PTIMER_LOAD_VAL_AT_MODULO_COUNTER_OR_NEXT_TRIGGER = 3U
/*!< Loaded when counter hits the max count or detecting an input trigger after load operation. */
} PTIMER_LoadValueModeType;
/**
* @brief Ptimer clock pre-divider factor
*
* The Ptimer clock source is from core clock and the divider is a multiplication of
* PTIMER_ClockPreDividerType and PTIMER_ClockPreDivMultiplyFactorType, and thus:
* Freq = Core_Freq / (PTIMER_ClockPreDividerType * PTIMER_ClockPreDivMultiplyFactorType)
*
*/
typedef enum
{
PTIMER_PRE_DIVIDE_BY_1 = 0U,
PTIMER_PRE_DIVIDE_BY_2 = 1U,
PTIMER_PRE_DIVIDE_BY_4 = 2U,
PTIMER_PRE_DIVIDE_BY_8 = 3U,
PTIMER_PRE_DIVIDE_BY_16 = 4U,
PTIMER_PRE_DIVIDE_BY_32 = 5U,
PTIMER_PRE_DIVIDE_BY_64 = 6U,
PTIMER_PRE_DIVIDE_BY_128 = 7U
} PTIMER_ClockPreDividerType;
/**
* @brief Ptimer clock divider multiplication factor
*
* The Ptimer clock source is from core clock and the divider is a multiplication of
* PTIMER_ClockPreDividerType and PTIMER_ClockPreDivMultiplyFactorType, and thus:
* Freq = Core_Freq / (PTIMER_ClockPreDividerType * PTIMER_ClockPreDivMultiplyFactorType)
*
*/
typedef enum
{
PTIMER_PRE_DIVIDER_MULTIPLY_BY_1 = 0U,
PTIMER_PRE_DIVIDER_MULTIPLY_BY_10 = 1U,
PTIMER_PRE_DIVIDER_MULTIPLY_BY_20 = 2U,
PTIMER_PRE_DIVIDER_MULTIPLY_BY_40 = 3U
} PTIMER_ClockPreDivMultiplyFactorType;
/**
* @brief Ptimer trigger source
*
*/
typedef enum
{
PTIMER_TRGSRC_TRGSEL = 0x00U, /*!< Ptimer trigger source from TrgSel */
PTIMER_TRGSRC_SW = 0x0FU /*!< Ptimer trigger source from software trigger*/
} PTIMER_TrgSrcType;
#if PTIMER_SUPPORT_DEBUG_MODE
/**
* @brief Disable debug mode of Ptimer
*
* @param pPtimer the base address of the pPtimer instance
* @param disable true. disable debug mode fasle enable debug mode
*/
LOCAL_INLINE void PTIMER_HWA_DisableDebugMode(PTIMER_Type *pPtimer, bool disable)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & (~PTIMER_STATUS_CTRL_DBG_DISEN_MASK)) | PTIMER_STATUS_CTRL_DBG_DISEN(disable);
}
#endif
/**
* @brief Get the STATUS_CTRL register value
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE uint32_t PTIMER_HWA_GetStatusCtrl(const PTIMER_Type *const pPtimer)
{
return pPtimer->STATUS_CTRL;
}
/**
* @brief Set the STATUS_CTRL register value
*
* @param pPtimer the base address of the Ptimer instance
* @param u32CfgValue the register value to set
*/
LOCAL_INLINE void PTIMER_HWA_SetStatusCtrl(PTIMER_Type *const pPtimer, uint32_t u32CfgValue)
{
pPtimer->STATUS_CTRL = u32CfgValue;
}
/**
* @brief Get the load mode of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @return PTIMER_LoadValueModeType the load mode of the Ptimer instance
*/
LOCAL_INLINE PTIMER_LoadValueModeType PTIMER_HWA_GetLoadMode(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_LDMODE_MASK) >> PTIMER_STATUS_CTRL_LDMODE_SHIFT;
return (PTIMER_LoadValueModeType)u32TmpVal;
}
/**
* @brief Set the load mode of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param eLoadMode the load mode of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetLoadMode(PTIMER_Type *const pPtimer, PTIMER_LoadValueModeType eLoadMode)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_LDMODE_MASK) | PTIMER_STATUS_CTRL_LDMODE(eLoadMode);
}
/**
* @brief Get whether sequence error interrupt is enabled
*
* @param pPtimer the base address of the Ptimer instance
* @return true sequence error interrupt is enabled
* @return false sequence error interrupt is disabled
*/
LOCAL_INLINE bool PTIMER_HWA_GetSeqErrIntEnableFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_SERR_INTEN_MASK) >> PTIMER_STATUS_CTRL_SERR_INTEN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set whether to enable sequence error interrupt
*
* @param pPtimer the base address of the Ptimer instance
* @param bEnable whether to enable sequence error interrupt
*/
LOCAL_INLINE void PTIMER_HWA_SetSeqErrIntEnableFlag(PTIMER_Type *const pPtimer, bool bEnable)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_SERR_INTEN_MASK) | PTIMER_STATUS_CTRL_SERR_INTEN(
bEnable ? 1U : 0U);
}
/**
* @brief Generate software trigger signal for Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_GenerateSwTrigger(PTIMER_Type *const pPtimer)
{
pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_SWTRG_MASK;
}
/**
* @brief Get whether DMA is enabled for the Ptimer insstance
*
* @param pPtimer the base address of the Ptimer instance
* @return true DMA is enabled
* @return false DMA is disabled
*/
LOCAL_INLINE bool PTIMER_HWA_GetDMAEnableFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_DMAEN_MASK) >> PTIMER_STATUS_CTRL_DMAEN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set whether to enable Ptimer DMA
*
* @param pPtimer the base address of the Ptimer instance
* @param bEnable whether to enable DMA for the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetDMAEnableFlag(PTIMER_Type *const pPtimer, bool bEnable)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_DMAEN_MASK) | PTIMER_STATUS_CTRL_DMAEN(bEnable ? 1U : 0U);
}
/**
* @brief Get the predivider value of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @return PTIMER_ClockPreDividerType the predivider of the Ptimer instance
*/
LOCAL_INLINE PTIMER_ClockPreDividerType PTIMER_HWA_GetDivPrescaler(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_PRESCALER_MASK) >> PTIMER_STATUS_CTRL_PRESCALER_SHIFT;
return (PTIMER_ClockPreDividerType)u32TmpVal;
}
/**
* @brief Set the predivider value of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param eDivPrescaler the predivider of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetDivPrescaler(PTIMER_Type *const pPtimer, PTIMER_ClockPreDividerType eDivPrescaler)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_PRESCALER_MASK) | PTIMER_STATUS_CTRL_PRESCALER(
eDivPrescaler);
}
/**
* @brief Get the trigger source of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @return PTIMER_TRGSRC_TRGSEL the trigger source is from TrgSel
* @return PTIMER_TRGSRC_SW the trigger source is from software
*/
LOCAL_INLINE PTIMER_TrgSrcType PTIMER_HWA_GetTriggerSource(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_TRGSEL_MASK) >> PTIMER_STATUS_CTRL_TRGSEL_SHIFT;
return (PTIMER_TrgSrcType)u32TmpVal;
}
/**
* @brief Set the trigger source of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param eTriggerSource the trigger source of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetTriggerSource(PTIMER_Type *const pPtimer, PTIMER_TrgSrcType eTriggerSource)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_TRGSEL_MASK) | PTIMER_STATUS_CTRL_TRGSEL(
eTriggerSource);
}
/**
* @brief Get whether the Ptimer instance is enabled
*
* @param pPtimer the base address of the Ptimer instance
* @return true the Ptimer instance is enabled
* @return false the Ptimer instance is disabled
*/
LOCAL_INLINE bool PTIMER_HWA_GetEnableFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_ENABLE_MASK) >> PTIMER_STATUS_CTRL_ENABLE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Enable the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_Enable(PTIMER_Type *const pPtimer)
{
pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_ENABLE_MASK;
}
/**
* @brief Disable the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_Disable(PTIMER_Type *const pPtimer)
{
pPtimer->STATUS_CTRL &= ~PTIMER_STATUS_CTRL_ENABLE_MASK;
}
/**
* @brief Get the delay interrupt flag of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @return true the delay interrupt flag of the Ptimer instance is generated
* @return false the delay interrupt flag of the Ptimer instance is not generated
*/
LOCAL_INLINE bool PTIMER_HWA_GetInterruptFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_INTFLAG_MASK) >> PTIMER_STATUS_CTRL_INTFLAG_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the delay interrupt flag of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_ClearInterruptFlag(PTIMER_Type *const pPtimer)
{
pPtimer->STATUS_CTRL &= ~PTIMER_STATUS_CTRL_INTFLAG_MASK;
}
/**
* @brief Get whether delay interrupt is enabled for the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE bool PTIMER_HWA_GetInterruptEnableFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_INTEN_MASK) >> PTIMER_STATUS_CTRL_INTEN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set whether to enable delay interrupt for the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param bEnable whether to enable delay interrupt for the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetInterruptEnableFlag(PTIMER_Type *const pPtimer, bool bEnable)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_INTEN_MASK) | PTIMER_STATUS_CTRL_INTEN(bEnable ? 1U : 0U);
}
/**
* @brief Get the multiply factor of the predivider of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @return PTIMER_ClockPreDivMultiplyFactorType the multiply factor of the Ptimer instance
*/
LOCAL_INLINE PTIMER_ClockPreDivMultiplyFactorType PTIMER_HWA_GetDivMultiply(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_MULT_MASK) >> PTIMER_STATUS_CTRL_MULT_SHIFT;
return (PTIMER_ClockPreDivMultiplyFactorType)u32TmpVal;
}
/**
* @brief Set the multiply factor of the predivider of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param eMultFactor the multiply factor of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetDivMultiply(PTIMER_Type *const pPtimer,
PTIMER_ClockPreDivMultiplyFactorType eMultFactor)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_MULT_MASK) | PTIMER_STATUS_CTRL_MULT(eMultFactor);
}
/**
* @brief Get whether continuous mode is enabled for the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @return true continuous mode is enabled for the Ptimer instance
* @return false continuous mode is disabled for the Ptimer instance
*/
LOCAL_INLINE bool PTIMER_HWA_GetContinuoiusModeFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_CONT_MASK) >> PTIMER_STATUS_CTRL_CONT_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set whether to enable continuous mode for the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param bEnable whether to enable continuous mode for the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_SetContinuoiusModeFlag(PTIMER_Type *const pPtimer, bool bEnable)
{
pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_CONT_MASK) | PTIMER_STATUS_CTRL_CONT(bEnable ? 1U : 0U);
}
/**
* @brief Get the config value loading status
*
* @param pPtimer the base address of the Ptimer instance
* @return true the config values are in loading status
* @return false the config values are loaded
*/
LOCAL_INLINE bool PTIMER_HWA_GetValueLoadStatus(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_LDOK_MASK) >> PTIMER_STATUS_CTRL_LDOK_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Load the buffered values into register
*
* @note Some Ptimer registers are buffered and will only take effect after called
* this function
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_LoadValue(PTIMER_Type *const pPtimer)
{
pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_LDOK_MASK;
}
/**
* @brief Get the Ptimer max counter period
* When the Ptimer counter reaches the period, it will return to zero
*
* @param pPtimer the base address of the Ptimer instance
* @return uint16_t the Ptimer max count
*/
LOCAL_INLINE uint16_t PTIMER_HWA_GetMaxCount(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->MAX_CNT & PTIMER_MAX_CNT_MAX_CNT_MASK) >> PTIMER_MAX_CNT_MAX_CNT_SHIFT;
return (uint16_t)u32TmpVal;
}
/**
* @brief Set the Ptimer max counter period
* When the Ptimer counter reaches the period, it will return to zero
*
* @note the period parameter is buffered and will take effect only after called PTIMER_LoadValue()
* function.
*
* @param pPtimer the base address of the Ptimer instance
* @param u16MaxCnt the Ptimer max count
*/
LOCAL_INLINE void PTIMER_HWA_SetMaxCount(PTIMER_Type *const pPtimer, uint16_t u16MaxCnt)
{
pPtimer->MAX_CNT = PTIMER_MAX_CNT_MAX_CNT(u16MaxCnt);
}
/**
* @brief Get the Ptimer current count value
*
* @param pPtimer the base address of the Ptimer instance
* @return uint16_t the Ptimer current count value
*/
LOCAL_INLINE uint16_t PTIMER_HWA_GetCounterValue(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->CNT & PTIMER_CNT_CNT_MASK) >> PTIMER_CNT_CNT_SHIFT;
return (uint16_t)u32TmpVal;
}
/**
* @brief Get the ptimer interrupt period
*
* @param pPtimer the base address of the Ptimer instance
* @return uint16_t the Ptimer interrupt period
*/
LOCAL_INLINE uint16_t PTIMER_HWA_GetInterruptDelay(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->INT_DLY & PTIMER_INT_DLY_INT_DLY_MASK) >> PTIMER_INT_DLY_INT_DLY_SHIFT;
return (uint16_t)u32TmpVal;
}
/**
* @brief Set the ptimer interrupt period
*
* @param pPtimer the base address of the Ptimer instance
* @param u16InterruptDelay the Ptimer interrupt period
*/
LOCAL_INLINE void PTIMER_HWA_SetInterruptDelay(PTIMER_Type *const pPtimer, uint16_t u16InterruptDelay)
{
pPtimer->INT_DLY = PTIMER_INT_DLY_INT_DLY(u16InterruptDelay);
}
/**
* @brief Get whether back to back trigger is enbaled for the Ptimer channel
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @return true back to back trigger is enbaled for the Ptimer channel
* @return false back to back trigger is disabled for the Ptimer channel
*/
LOCAL_INLINE bool PTIMER_HWA_GetChannelBackToBackFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerCtrlIdx = u8Channel % 8U;
uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_BTB(1UL << u8PtimerCtrlIdx)) >>
(PTIMER_CTRL_CH_BTB_SHIFT + u8PtimerCtrlIdx);
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get whether pre-trigger output is enbaled for the Ptimer channel
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @return true pre-trigger output is enbaled for the Ptimer channel
* @return false pre-trigger output is disabled for the Ptimer channel
*/
LOCAL_INLINE bool PTIMER_HWA_GetChannelPretriggerOutputFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerCtrlIdx = u8Channel % 8U;
uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_PTOS(1UL << u8PtimerCtrlIdx)) >>
(PTIMER_CTRL_CH_PTOS_SHIFT + u8PtimerCtrlIdx);
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get whether pre-trigger is enbaled for the Ptimer channel
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @return true pre-trigger is enbaled for the Ptimer channel
* @return false pre-trigger is disabled for the Ptimer channel
*/
LOCAL_INLINE bool PTIMER_HWA_GetChannelPretriggerEnableFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerCtrlIdx = u8Channel % 8U;
uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_PTEN(1UL << u8PtimerCtrlIdx)) >>
(PTIMER_CTRL_CH_PTEN_SHIFT + u8PtimerCtrlIdx);
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Ptimer channel control flags
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @param bEnablePretrigger whether to enable pre-trigger
* @param bEnablePretriggerOutput whether to enable pre-trigger output
* @param bEnableBackToBack whether to enable back to back trigger
*/
LOCAL_INLINE void PTIMER_HWA_SetChannelControl(PTIMER_Type *const pPtimer, uint8_t u8Channel, bool bEnablePretrigger,
bool bEnablePretriggerOutput, bool bEnableBackToBack)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerCtrlIdx = u8Channel % 8U;
uint32_t u32CtrlMask = PTIMER_CTRL_CH_PTEN(1UL << u8PtimerCtrlIdx) |
PTIMER_CTRL_CH_PTOS(1UL << u8PtimerCtrlIdx) |
PTIMER_CTRL_CH_BTB(1UL << u8PtimerCtrlIdx);
pPtimer->CH[u8PtimerChannelIdx].CTRL = (pPtimer->CH[u8PtimerChannelIdx].CTRL & ~u32CtrlMask) |
PTIMER_CTRL_CH_PTEN((bEnablePretrigger ? 1UL : 0UL) << u8PtimerCtrlIdx) |
PTIMER_CTRL_CH_PTOS((bEnablePretriggerOutput ? 1UL : 0UL) << u8PtimerCtrlIdx) |
PTIMER_CTRL_CH_BTB((bEnableBackToBack ? 1UL : 0UL) << u8PtimerCtrlIdx);
}
/**
* @brief Get whether the Ptimer counter matches the channel counter
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @return true the Ptimer counter matches the channel counter
* @return false the Ptimer counter has not reached the channel counter
*/
LOCAL_INLINE bool PTIMER_HWA_GetChannelCounterFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerStatusIdx = u8Channel % 8U;
uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].STATUS & PTIMER_STATUS_CH_CHN_FLAG(1UL << u8PtimerStatusIdx)) >>
(PTIMER_STATUS_CH_CHN_FLAG_SHIFT + u8PtimerStatusIdx);
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the Ptimer channel counter match flag
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
*/
LOCAL_INLINE void PTIMER_HWA_ClearChannelCounterFlag(PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerStatusIdx = u8Channel % 8U;
pPtimer->CH[u8PtimerChannelIdx].STATUS &= ~PTIMER_STATUS_CH_CHN_FLAG(1UL << u8PtimerStatusIdx);
}
/**
* @brief Get the sequence error status of the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the channel related to the sequence error
* @return true the selected channel has sequence error
* @return false the selected channel does not have sequence error
*/
LOCAL_INLINE bool PTIMER_HWA_GetChannelSequenceErrorFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerStatusIdx = u8Channel % 8U;
uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].STATUS & PTIMER_STATUS_CH_SERR_FLAG(1UL << u8PtimerStatusIdx)) >>
(PTIMER_STATUS_CH_SERR_FLAG_SHIFT + u8PtimerStatusIdx);
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the sequence error flag of the selected Ptimer channel
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel to clear the sequence error flag
*/
LOCAL_INLINE void PTIMER_HWA_ClearChannelSequenceErrorFlag(PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / 8U;
uint8_t u8PtimerStatusIdx = u8Channel % 8U;
pPtimer->CH[u8PtimerChannelIdx].STATUS &= ~PTIMER_STATUS_CH_SERR_FLAG(1UL << u8PtimerStatusIdx);
}
/**
* @brief Get the channel delay value
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @return uint16_t the channel delay value
*/
LOCAL_INLINE uint16_t PTIMER_HWA_GetChannelDelay(const PTIMER_Type *const pPtimer, uint8_t u8Channel)
{
uint8_t u8PtimerChannelIdx = u8Channel / PTIMER_CH_DLY_CNT;
uint8_t u8PtimerDelayIdx = u8Channel % PTIMER_CH_DLY_CNT;
uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].DLY[u8PtimerDelayIdx] & PTIMER_DLY0_CH_CHNDLY_MASK) >>
PTIMER_DLY0_CH_CHNDLY_SHIFT;
return (uint16_t)u32TmpVal;
}
/**
* @brief Set the channel delay value
*
* @param pPtimer the base address of the Ptimer instance
* @param u8Channel the Ptimer channel
* @param u16Delay the channel delay value
*/
LOCAL_INLINE void PTIMER_HWA_SetChannelDelay(PTIMER_Type *const pPtimer, uint8_t u8Channel, uint16_t u16Delay)
{
uint8_t u8PtimerChannelIdx = u8Channel / PTIMER_CH_DLY_CNT;
uint8_t u8PtimerDelayIdx = u8Channel % PTIMER_CH_DLY_CNT;
pPtimer->CH[u8PtimerChannelIdx].DLY[u8PtimerDelayIdx] = PTIMER_DLY0_CH_CHNDLY(u16Delay);
}
/**
* @brief Get whether pulse-out is enabled
*
* @param pPtimer the base address of the Ptimer instance
* @return true pulse-out is enabled
* @return false pulse-out is disabled
*/
LOCAL_INLINE bool PTIMER_HWA_GetPulseOutEnableFlag(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->POEN & PTIMER_POEN_POEN_MASK) >> PTIMER_POEN_POEN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Enable pulse-out for the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_EnablePulseOut(PTIMER_Type *const pPtimer)
{
pPtimer->POEN |= PTIMER_POEN_POEN_MASK;
}
/**
* @brief Disable pulse-out for the Ptimer instance
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE void PTIMER_HWA_DisablePulseOut(PTIMER_Type *const pPtimer)
{
pPtimer->POEN &= ~PTIMER_POEN_POEN_MASK;
}
/**
* @brief Get the delay high value for the pulse-out function
* When the Ptimer counter reach the delay high value, the pulse output goes high
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE uint16_t PTIMER_HWA_GetPulseOutDelayHigh(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->PODLY & PTIMER_PODLY_DLY1_MASK) >> PTIMER_PODLY_DLY1_SHIFT;
return (uint16_t)u32TmpVal;
}
/**
* @brief Get the delay low value for the pulse-out function
* When the Ptimer counter reach the delay low value, the pulse output goes low
*
* @param pPtimer the base address of the Ptimer instance
*/
LOCAL_INLINE uint16_t PTIMER_HWA_GetPulseOutDelayLow(const PTIMER_Type *const pPtimer)
{
uint32_t u32TmpVal = (pPtimer->PODLY & PTIMER_PODLY_DLY2_MASK) >> PTIMER_PODLY_DLY2_SHIFT;
return (uint16_t)u32TmpVal;
}
/**
* @brief Set the pulse out delay value
* When the Ptimer counter reach the delay high value, the pulse output goes high
* When the Ptimer counter reach the delay low value, the pulse output goes low
* The delay high value can be either greater or less than the delay low value
*
* @param pPtimer the base address of the Ptimer instance
* @param u16DelayHigh the delay high value
* @param u16DelayLow the delay low value
*/
LOCAL_INLINE void PTIMER_HWA_SetPulseOutDelay(PTIMER_Type *const pPtimer, uint16_t u16DelayHigh, uint16_t u16DelayLow)
{
pPtimer->PODLY = PTIMER_PODLY_DLY1(u16DelayHigh) | PTIMER_PODLY_DLY2(u16DelayLow);
}
/** @}*/
#endif /* #if PTIMER_INSTANCE_COUNT > 0U */
#endif /* _HWA_PTIMER_H_ */

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/**
* @file HwA_rtc.h
* @author Flagchip
* @brief rtc hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip076 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip120 N/A Change version and release
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_RTC_H_
#define HWA_INCLUDE_HWA_RTC_H_
#include "device_header.h"
#if RTC_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_rtc HwA_rtc
* @ingroup module_driver_rtc
* @{
*/
/********* Local typedef ************/
/**
* @brief in the second interrupt mode, this type indicates the interrupt frequency.
* in the clkout mode , this type indicates the clkout frequency .
*
* */
typedef enum
{
RTC_FREQ_1HZ = 0, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 1Hz */
RTC_FREQ_2HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 2Hz */
RTC_FREQ_4HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 4Hz */
RTC_FREQ_8HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 8Hz */
RTC_FREQ_16HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 16Hz */
RTC_FREQ_32hZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 32Hz */
RTC_FREQ_64HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 64Hz */
RTC_FREQ_128HZ /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 128Hz */
} RTC_ClkoutSecIntFreqType;
/********* Local inline function ************/
/**
* @brief Read second value
*
* @param pRtc the base address of the pRtc instance.
* @return Second value
*/
LOCAL_INLINE uint32_t RTC_HWA_ReadSecondValue(RTC_Type *const pRtc)
{
uint32_t u32SecondValue0, u32SecondValue1;
do
{
u32SecondValue0 = pRtc->SR;
u32SecondValue1 = pRtc->SR;
}while (u32SecondValue0 != u32SecondValue1);
return u32SecondValue0;
}
/**
* @brief Read RTC SR overflow flag
*
* @param pRtc the base address of the pRtc instance.
* @return true means Overflow flag is 1 ;false means Overflow flag is 0.
*/
LOCAL_INLINE bool RTC_HWA_ReadOverflowFlag(RTC_Type *const pRtc)
{
return (bool)(((pRtc->STR & (uint32_t)RTC_STR_TOF_MASK)!=0u)? true:false);
}
/**
* @brief Read RTC IER overflow enable bit
*
* @param pRtc the base address of the pRtc instance.
* @return true means enable Overflow Interrupt ;false means disable Overflow Interrupt
*/
LOCAL_INLINE bool RTC_HWA_ReadOverflowEnable(RTC_Type *const pRtc)
{
return (bool)(((pRtc->IER & (uint32_t)RTC_IER_TOIE_MASK)!=0u) ? true:false);
}
/**
* @brief Read RTC alarm flag
*
* @param pRtc the base address of the pRtc instance.
* @return true means alarm flag is 1 ;false means alarm flag is 0.
*/
LOCAL_INLINE bool RTC_HWA_ReadAlarmFlag(RTC_Type *const pRtc)
{
return (bool)(((pRtc->STR & (uint32_t)RTC_STR_TAF_MASK)!=0u)?true:false);
}
/**
* @brief Read RTC alarm Enable
*
* @param pRtc the base address of the pRtc instance.
* @return true means enable alarm Interrupt ;false means disable alarm Interrupt
*/
LOCAL_INLINE bool RTC_HWA_ReadAlarmEnable(RTC_Type *const pRtc)
{
return (bool)(((pRtc->IER & (uint32_t)RTC_IER_TAIE_MASK)!=0u)?true:false);
}
/**
* @brief Read RTC second interrupt Enable
*
* @param pRtc the base address of the pRtc instance.
* @return true means enable second Interrupt ;false means disable second Interrupt
*/
LOCAL_INLINE bool RTC_HWA_ReadSecondEnable(RTC_Type *const pRtc)
{
return (bool)(((pRtc->IER & (uint32_t)RTC_IER_TSIE_MASK)!=0u)?true:false);
}
/**
* @brief Read RTC Compensation Interbal
*
* @param pRtc the base address of the pRtc instance.
* @return Compensation Interbal
*/
LOCAL_INLINE uint8_t RTC_HWA_ReadCompInterval(RTC_Type *const pRtc)
{
return (uint8_t)((pRtc->COMPR & (uint32_t)RTC_COMPR_CIC_MASK) >> RTC_COMPR_CIC_SHIFT);
}
/**
* @brief Read RTC Compensation Value
*
* @param pRtc the base address of the pRtc instance.
* @return Compensation Value
*/
LOCAL_INLINE uint8_t RTC_HWA_ReadCompValue(RTC_Type *const pRtc)
{
return (uint8_t)((pRtc->COMPR & (uint32_t)RTC_COMPR_TCV_MASK) >> RTC_COMPR_TCV_SHIFT);
}
/**
* @brief Sets the RTC compare interval.
*
* @param pRtc the base address of the pRtc instance.
* @param u8Interval The compare interval reload value, in seconds.
*/
LOCAL_INLINE void RTC_HWA_SetCompInterval(RTC_Type *const pRtc, uint8_t u8Interval)
{
pRtc->COMPR = ((pRtc->COMPR & ~RTC_COMPR_CIR_MASK) | (uint32_t)(u8Interval << RTC_COMPR_CIR_SHIFT));
}
/**
* @brief Sets the RTC compare value.
*
* @param pRtc the base address of the pRtc instance.
* @param u8Value The compare value, in ticks.
*/
LOCAL_INLINE void RTC_HWA_SetCompValue(RTC_Type *const pRtc, uint8_t u8Value)
{
pRtc->COMPR = ((pRtc->COMPR & ~RTC_COMPR_TCR_MASK) | (uint32_t)(u8Value << RTC_COMPR_TCR_SHIFT));
}
/**
* @brief Set RTC prescaler register
*
* @param pRtc the base address of the pRtc instance.
* @param u16Value PR register value
*/
LOCAL_INLINE void RTC_HWA_SetPrescalerCounterValue(RTC_Type *const pRtc, uint16_t u16Value)
{
pRtc->PR = (uint32_t)u16Value;
pRtc->PR = (uint32_t)u16Value;
}
/**
* @brief Set RTC seconds register
*
* @param pRtc the base address of the pRtc instance.
* @param u32Value SR register value
*/
LOCAL_INLINE void RTC_HWA_SetSecondCounterValue(RTC_Type *const pRtc, uint32_t u32Value)
{
pRtc->SR = u32Value;
}
/**
* @brief Set RTC alarm value
*
* @param pRtc the base address of the pRtc instance.
* @param u32Value TAR register value
*/
LOCAL_INLINE void RTC_HWA_SetAlarmCounterValue(RTC_Type *const pRtc, uint32_t u32Value)
{
pRtc->AR = u32Value;
}
/**
* @brief Set RTC interrupt value
*
* @param pRtc the base address of the pRtc instance.
* @param u32Value IER register value
*/
LOCAL_INLINE void RTC_HWA_SetInterruptValue(RTC_Type *const pRtc, uint32_t u32Value)
{
pRtc->IER = u32Value;
}
/**
* @brief Configure control register
*
* @param pRtc the base address of the pRtc instance.
* @param u32Value Control value
*/
LOCAL_INLINE void RTC_HWA_ConfigControl(RTC_Type *const pRtc, uint32_t u32Value)
{
pRtc->CR = u32Value;
}
/**
* @brief Enable RTC time counter
*
* @param pRtc the base address of the pRtc instance.
*/
LOCAL_INLINE void RTC_HWA_EnableRtcCounter(RTC_Type *const pRtc)
{
uint32_t u32RegValue = pRtc->STR;
u32RegValue |= (uint32_t)RTC_STR_TCE_MASK;
u32RegValue &= ~(uint32_t)0x8u;
pRtc->STR = u32RegValue;
}
/**
* @brief Set RTC_CLKOUT is from the 32.768 khz clock
*
* @param pRtc the base address of the pRtc instance.
*/
LOCAL_INLINE void RTC_HWA_SetClkoutFreqStable(RTC_Type *const pRtc)
{
pRtc->CR |= (uint32_t)RTC_CR_CKPS_MASK;
}
/**
* @brief Enable alarm interrupt
*
* @param pRtc the base address of the pRtc instance.
* @param bEnable Indicates whether to enable the interrupt. true: Enable interrupt, false: Disable interrupt.
*/
LOCAL_INLINE void RTC_HWA_EnableAlarmInterrupt(RTC_Type *const pRtc, bool bEnable)
{
pRtc->IER = (pRtc->IER & ~(uint32_t)RTC_IER_TAIE_MASK) | RTC_IER_TAIE(bEnable);
}
/**
* @brief Enable second interrupt
*
* @param pRtc the base address of the pRtc instance.
* @param bEnable A boolean indicating whether to enable (true) or disable (false) the interrupt.
*/
LOCAL_INLINE void RTC_HWA_EnableSecondInterrupt(RTC_Type *const pRtc, bool bEnable)
{
pRtc->IER = (pRtc->IER & ~(uint32_t)RTC_IER_TSIE_MASK) | RTC_IER_TSIE(bEnable);
}
/**
* @brief Enable overflow interrupt
*
* @param pRtc the base address of the pRtc instance.
* @param bEnable Boolean value indicating whether to enable (true) or disable (false) the interrupt.
*/
LOCAL_INLINE void RTC_HWA_EnableOverflowInterrupt(RTC_Type *const pRtc, bool bEnable)
{
pRtc->IER = (pRtc->IER & ~(uint32_t)RTC_IER_TOIE_MASK) | RTC_IER_TOIE(bEnable);
}
/**
* @brief Unlock lock/status/control/compensation register
*
* @param pRtc the base address of the pRtc instance.
*/
LOCAL_INLINE void RTC_HWA_UnlockStatusControlCompensationReg(RTC_Type *const pRtc)
{
pRtc->LR |= (uint32_t)(RTC_LR_LRL_MASK | RTC_LR_STRL_MASK | RTC_LR_CRL_MASK | RTC_LR_CPL_MASK);
}
/**
* @brief Set second interrupt and RTC_CLKOUT frequency
*
* @param pRtc the base address of the pRtc instance.
* @param eFreq Frequency value
*/
LOCAL_INLINE void RTC_HWA_SetSecondAndClkoutFreq(RTC_Type *const pRtc, RTC_ClkoutSecIntFreqType eFreq)
{
uint32_t u32RegValue = pRtc->IER;
pRtc->IER &= ~(uint32_t)RTC_IER_TSIE_MASK;
pRtc->IER = (u32RegValue & ~(uint32_t)RTC_IER_TSIC_MASK) | RTC_IER_TSIC(eFreq);
}
/**
* @brief Disable RTC time counter
*
* @param pRtc the base address of the pRtc instance.
*/
LOCAL_INLINE void RTC_HWA_DisableRtcCounter(RTC_Type *const pRtc)
{
pRtc->STR &= ~(uint32_t)(RTC_STR_TCE_MASK | 0x8u);
}
/**
* @brief Set RTC_CLKOUT is from the prescaler output clock selected by IER[TSIC]
*
* @param pRtc the base address of the pRtc instance.
*/
LOCAL_INLINE void RTC_HWA_SetClkoutFromSelectFreq(RTC_Type *const pRtc)
{
pRtc->CR &= ~(uint32_t)RTC_CR_CKPS_MASK;
}
/**
* @brief Disable alarm interrupt
*
* @param pRtc the base address of the pRtc instance.
*/
LOCAL_INLINE void RTC_HWA_DisableAlarmInterrupt(RTC_Type *const pRtc)
{
pRtc->IER &= ~(uint32_t)RTC_IER_TAIE_MASK;
}
/**
* @brief Disable second interrupt
*
* @param pRtc the base address of the pRtc instance.
*/
LOCAL_INLINE void RTC_HWA_DisableSecondInterrupt(RTC_Type *const pRtc)
{
pRtc->IER &= ~(uint32_t)RTC_IER_TSIE_MASK;
}
/**
* @brief Disable overflow interrupt
*
* @param pRtc the base address of the pRtc instance.
*/
LOCAL_INLINE void RTC_HWA_DisableOverflowInterrupt(RTC_Type *const pRtc)
{
pRtc->IER &= ~(uint32_t)RTC_IER_TOIE_MASK;
}
#endif
/** @}*/ /* HwA_RTC */
#endif /* HWA_INCLUDE_HWA_RTC_H_ */

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/**
* @file HwA_scm.h
* @author flagchip
* @brief Hardware access layer for SCM
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip055 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip055 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_SCM_H_
#define _HWA_SCM_H_
#include "device_header.h"
#if SCM_INSTANCE_COUNT > 0U
/**
* @brief SCM adc trigger selection
*/
typedef enum
{
SCM_ADC_INSTANCE_0 = 0U,
SCM_ADC_INSTANCE_1 = 1U,
SCM_ADC_INSTANCE_2 = 2U,
SCM_ADC_INSTANCE_3 = 3U,
SCM_ADC_INSTANCE_4 = 4U,
SCM_ADC_INSTANCE_5 = 5U,
} SCM_AdcInstance;
/**
* @brief SCM adc trigger selection
*/
typedef enum
{
SCM_ADC_TRIGGER_PTIMER = 0U,
SCM_ADC_TRIGGER_TRGSEL = 1U,
} SCM_AdcTriggerSel;
/**
* @brief SCM adc pre-trigger selection
*/
typedef enum
{
SCM_ADC_PRE_TRIGGER_PTIMER = 0U,
SCM_ADC_PRE_TRIGGER_TRGSEL = 1U,
SCM_ADC_PRE_TRIGGER_SCM_SOFTWARE_PRE_TRIGGER = 2U,
} SCM_AdcPreTriggerSel;
/**
* @brief SCM software trigger source
*/
typedef enum
{
SCM_SOFTWARE_PRE_TRIGGER_0 = 0U, /*!< SCM software pre-trigger 0 */
SCM_SOFTWARE_PRE_TRIGGER_1 = 1U, /*!< SCM software pre-trigger 1 */
SCM_SOFTWARE_PRE_TRIGGER_2 = 2U, /*!< SCM software pre-trigger 2 */
SCM_SOFTWARE_PRE_TRIGGER_3 = 3U, /*!< SCM software pre-trigger 3 */
} SCM_SoftwarePreTrigger;
/**
* @defgroup HwA_scm HwA_scm
* @ingroup module_driver_scm
* @{
*/
/********* Local typedef ************/
/********* Local inline function ************/
/**
* @brief Get UIDL data(Unique identification for the chip. Loaded from NVR)
*
* @return return value
*/
LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDL(void)
{
return SCM->UIDL;
}
/**
* @brief Get UIDML data(Unique identification for the chip. Loaded from NVR)
*
* @return return value
*/
LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDML(void)
{
return SCM->UIDML;
}
/**
* @brief Get UIDMH data(Unique identification for the chip. Loaded from NVR)
*
* @return return value
*/
LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDMH(void)
{
return SCM->UIDMH;
}
/**
* @brief Get UIDH data(Unique identification for the chip. Loaded from NVR)
*
* @return return value
*/
LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDH(void)
{
return SCM->UIDH;
}
/**
* @brief Get Family Identification
*
* @return return value
*/
LOCAL_INLINE uint8_t SCM_HWA_GetData_FamilyID(void)
{
return (uint8_t)((SCM->PARTID0 & (uint32_t)SCM_PARTID0_FAM_ID_MASK) >> (uint32_t)SCM_PARTID0_FAM_ID_SHIFT);
}
/**
* @brief Get Revision Identification
*
* @return return value
*/
LOCAL_INLINE uint8_t SCM_HWA_GetData_RevID(void)
{
return (uint8_t)((SCM->PARTID0 & (uint32_t)SCM_PARTID0_REVID_MASK));
}
/**
* @brief Set the ISM_ROUTING register value
*
* @param u32Val value to be set
*/
LOCAL_INLINE void SCM_HWA_Set_ISM_ROUTING(uint32_t u32Val)
{
SCM->ISM_ROUTING = u32Val;
}
/**
* @brief Get CHIPCFG0 register status
*
* @return return value
*/
LOCAL_INLINE uint32_t SCM_HWA_Get_CHIPCFG0(void)
{
return SCM->CHIPCFG0;
}
/**
* @brief Set the SOCMISC register value
*
* @param u32Val value to be set
*/
LOCAL_INLINE void SCM_HWA_Set_SOCMISC(uint32_t u32Val)
{
SCM->SOCMISC = u32Val;
}
/**
* @brief Get the SOCMISC register status
*
* @return Lock status
*/
LOCAL_INLINE uint32_t SCM_HWA_Get_SOCMISC(void)
{
return SCM->SOCMISC;
}
#if SCM_GET_DEVICEID_SUPPORT
/**
* @brief Get device ID
*
* @return return value
*/
LOCAL_INLINE uint32_t SCM_HWA_GetData_DeviceID(void)
{
return ((SCM->CHIPCFG1 & (uint32_t)SCM_CHIPCFG1_DEVICE_ID_MASK) >> (uint32_t)SCM_CHIPCFG1_DEVICE_ID_SHIFT);
}
#endif
/**
* @brief Get SYSAP_CTRL register status
*
* @return Register status
*/
LOCAL_INLINE uint32_t SCM_HWA_Get_SYSAP_CTRL(void)
{
return SCM->SYSAP_CTRL;
}
#if SCM_CRC_SUPPORT
/**
* @brief Set the CRCCSR register value
*
* @param u32Val value to be set
*/
LOCAL_INLINE void SCM_HWA_Set_CRCCSR(uint32_t u32Val)
{
SCM->CRCCSR = u32Val;
}
/**
* @brief Get CRCCSR register status
*
* @return Register status
*/
LOCAL_INLINE uint32_t SCM_HWA_Get_CRCCSR(void)
{
return SCM->CRCCSR;
}
/**
* @brief Set CRC check enable/disable
*
* @param bEnable Enable/Disable
*/
LOCAL_INLINE void SCM_HWA_SetCrcCheckEnable(bool bEnable)
{
SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_CHKEN_MASK))) | SCM_CRCCSR_CHKEN(bEnable);
}
/**
* @brief Set CRC trigger enable/disable
*
* @param bEnable Enable/Disable
*/
LOCAL_INLINE void SCM_HWA_SetCrcTriggerEnable(bool bEnable)
{
SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_TRGEN_MASK))) | SCM_CRCCSR_TRGEN(bEnable);
}
/**
* @brief Set CRC error out enable/disable
*
* @param bEnable Enable/Disable
*/
LOCAL_INLINE void SCM_HWA_SetCrcErrorOutEnable(bool bEnable)
{
SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_EOEN_MASK))) | SCM_CRCCSR_EOEN(bEnable);
}
/**
* @brief Clear CRC error flag
*/
LOCAL_INLINE void SCM_HWA_ClearCrcErrorFlag(void)
{
SCM->CRCCSR |= SCM_CRCCSR_ERR_MASK;
}
/**
* @brief Get CRC Done Flag
*
* @return CRC Done Flag
*/
LOCAL_INLINE bool SCM_HWA_GetCrcDoneFlag(void)
{
return ((SCM->CRCCSR & SCM_CRCCSR_BUY_MASK) == SCM_CRCCSR_BUY_MASK) ? false : true;
}
/**
* @brief Set CRC software generate enable/disable
*
* @param bEnable Enable/Disable
*/
LOCAL_INLINE void SCM_HWA_SetCrcGenerateEnable(bool bEnable)
{
SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_GEN_MASK))) | SCM_CRCCSR_GEN(bEnable);
}
/**
* @brief Get CRC result
*
* @return CRC result
*/
LOCAL_INLINE uint32_t SCM_HWA_GetCrcResult(void)
{
return SCM->CRCRES;
}
#endif
/**
* @brief Set the FTU_GTBC register value
*
* @param u32Val value to be set
*/
LOCAL_INLINE void SCM_HWA_Set_FTU_GTBC(uint32_t u32Val)
{
#if defined (SCM_FTU_GTBC_FTU_GTBC_MASK)
SCM->FTU_GTBC = u32Val;
#elif defined (SCM_FTU_GTBC_FTU0_GTBC_MASK)
SCM->FTU_GTBC = u32Val;
#else
#error "No valid SCM_FTU_GTB*_FTU*_GTBC_MASK definition"
#endif
}
#if defined(SCM_GTBC_TPU_SELECT_SUPPORT) && (SCM_GTBC_TPU_SELECT_SUPPORT)
/**
* @brief Configure TPU global time base control selection
*
* @param bEn Enable or disable TPU Global Time Base
*/
LOCAL_INLINE void SCM_HWA_ConfigTpuGTBSelect(bool bEn)
{
#if defined(SCM_FTU_GTBC_ETPU_GTBC_MASK)
SCM->FTU_GTBC &= ~(uint32_t)SCM_FTU_GTBC_ETPU_GTBC_MASK;
SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_ETPU_GTBC(bEn);
#elif defined(SCM_FTU_GTBC_TPU_GTBC_MASK)
SCM->FTU_GTBC &= ~(uint32_t)SCM_FTU_GTBC_TPU_GTBC_MASK;
SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_TPU_GTBC(bEn);
#else
#error "No valid SCM_FTU_GTBC_*TPU definition"
#endif
}
#endif
/**
* @brief Set TPU clock enable/disable
*
* @param bEnable Enable/Disable
*/
LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_TPUClock(bool bEnable)
{
#if defined(SCM_SUBSYSPCC_SUPPORT) && defined(SCM_SUBSYSPCC_SUPPORT)
SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_CLKEN_TPU_MASK)) |
SCM_SUBSYS_PCC_CLKEN_TPU(bEnable));
#elif (SCM_TPUPCC_SUPPORT && SCM_TPUPCC_SUPPORT)
SCM->TPU_PCC = ((SCM->TPU_PCC & (~(uint32_t)SCM_TPU_PCC_CLKEN_TPU_MASK)) |
SCM_TPU_PCC_CLKEN_TPU(bEnable));
#else
PROCESS_UNUSED_VAR(bEnable);
#endif
}
/**
* @brief Set SubSystem clock enable/disable
*
* @param bEnable Enable/Disable
*/
LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_SubSystemClock(bool bEnable)
{
#if (SCM_FLEXHSM_PCC_SUPPORT && SCM_FLEXHSM_PCC_SUPPORT)
SCM->FLEXHSM_PCC = ((SCM->FLEXHSM_PCC & (~(uint32_t)SCM_FLEXHSM_PCC_CLKEN_FLEXHSM_MASK)) |
SCM_FLEXHSM_PCC_CLKEN_FLEXHSM(bEnable));
#elif (SCM_SUBSYSPCC_SUPPORT && SCM_SUBSYSPCC_SUPPORT)
SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_CLKEN_SUBSYS_MASK)) |
SCM_SUBSYS_PCC_CLKEN_SUBSYS(bEnable));
#else
PROCESS_UNUSED_VAR(bEnable);
#endif
}
#if defined(SCM_GTBC_FTU_SELECT_SUPPORT) && (SCM_GTBC_FTU_SELECT_SUPPORT)
/**
* @brief Set FTU global time base control selection
*
* @param u32SelectedFtu The GTBC mask of Selected Ftu instance,it is the or value of SCM_FTUGTBCtrlType.
* eg.u32SelectedFtu == 1 means FTU0 selected, u32SelectedFtu == 5 means FTU0 and FTU2 selected.
*/
LOCAL_INLINE void SCM_HWA_SetFtuGTBSelect(uint32_t u32SelectedFtu)
{
SCM->FTU_GTBC |= (u32SelectedFtu & 0xFFu) << SCM_FTU_GTBC_FTU0_GTBC_SHIFT;
}
/**
* @brief Clear FTU global time base control selection
*
* @param u32SelectedFtu The GTBC mask of Selected Ftu instance,it is the or value of SCM_FTUGTBCtrlType.
* eg.u32SelectedFtu == 1 means FTU0 selected, u32SelectedFtu == 5 means FTU0 and FTU2 selected.
*/
LOCAL_INLINE void SCM_HWA_ClearFtuGTBSelect(uint32_t u32SelectedFtu)
{
SCM->FTU_GTBC &= ~(uint32_t)((u32SelectedFtu & 0xFFu) << SCM_FTU_GTBC_FTU0_GTBC_SHIFT);
}
#endif
#if defined(SCM_FTU_GTBC_TSTMP_TRIG_SUPPORT) && (SCM_FTU_GTBC_TSTMP_TRIG_SUPPORT)
/**
* @brief Configure FTU Global Time Base Control Mask Register
*
* @param u8FtuIndex The selected FTU instance (must be 0 ~ 7)
* @param u32Value Value to be set (must be 0 ~ 15)
*/
LOCAL_INLINE void SCM_HWA_ConfigFtuGTBMask(uint8_t u8FtuIndex, uint32_t u32Value)
{
#if defined(SCM_FTU_GTBEM_FTU0_GTBEM_MASK)
SCM->FTU_GTBEM = (SCM->FTU_GTBEM & (~((uint32_t)SCM_FTU_GTBEM_FTU0_GTBEM_MASK << (SCM_FTU_GTBEM_FTU0_GTBEM_WIDTH * u8FtuIndex))))
| (((uint32_t)u32Value & SCM_FTU_GTBEM_FTU0_GTBEM_MASK) << (SCM_FTU_GTBEM_FTU0_GTBEM_WIDTH * u8FtuIndex));
#elif defined(SCM_FTU_GTBCM_FTU0_GTBCM_MASK)
SCM->FTU_GTBCM = (SCM->FTU_GTBCM & (~((uint32_t)SCM_FTU_GTBCM_FTU0_GTBCM_MASK << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex))))
| (((uint32_t)u32Value & SCM_FTU_GTBCM_FTU0_GTBCM_MASK) << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex));
#else
#error "No valid SCM_FTU_GTB*M_FTU*_GTB*M definition"
#endif
}
/**
* @brief Clear FTU Global Time Base Control Mask Register
*
* @param u8FtuIndex The selected FTU instance (must be 0 ~ 7)
*/
LOCAL_INLINE void SCM_HWA_ClearFtuGTBMask(uint8_t u8FtuIndex)
{
#if defined(SCM_FTU_GTBEM_FTU0_GTBEM_MASK)
SCM->FTU_GTBEM &= ~ ((uint32_t)SCM_FTU_GTBEM_FTU0_GTBEM_MASK << (SCM_FTU_GTBEM_FTU0_GTBEM_WIDTH * u8FtuIndex));
#elif defined(SCM_FTU_GTBCM_FTU0_GTBCM_MASK)
SCM->FTU_GTBCM &= ~ ((uint32_t)SCM_FTU_GTBCM_FTU0_GTBCM_MASK << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex));
#else
#error "No valid SCM_FTU_GTB*M_FTU*_GTB*M definition"
#endif
}
#endif
#if SCM_PTIMER_CHANNEL_SELECTION_SUPPORT
/**
* @brief Set the ADC_ROUTING2 register value
*
* @param u32Val value to be set
*/
LOCAL_INLINE void SCM_HWA_Set_ADC_ROUTING2(uint32_t u32Val)
{
SCM->ADC_ROUTING2 = u32Val;
}
/**
* @brief Get the ADC_ROUTING2 register status
*
* @return Lock status
*/
LOCAL_INLINE uint32_t SCM_HWA_Get_ADC_ROUTING2(void)
{
return SCM->ADC_ROUTING2;
}
#endif
#ifdef SCM_CPU1VTOR_CPU1_INIT_VECTOR_MASK
/**
* @brief Set the CPU1VTOR register value
*
* @param u32Val value to be set
*/
LOCAL_INLINE void SCM_HWA_Set_CPU1VTOR(uint32_t u32Val)
{
SCM->CPU1VTOR = u32Val;
}
/**
* @brief Get the CPU1VTOR register status
*
* @return Lock status
*/
LOCAL_INLINE uint32_t SCM_HWA_Get_CPU1VTOR(void)
{
return SCM->CPU1VTOR;
}
/**
* @brief Set CPU1 Vector Table Register vector initial vector
*
* @param u32Value value to be set
*/
LOCAL_INLINE void SCM_HWA_CPU1VTOR_SetVector(uint32_t u32Value)
{
uint32_t u32RegVal = SCM->CPU1VTOR;
SCM->CPU1VTOR = ((u32RegVal & (~(uint32_t)SCM_CPU1VTOR_CPU1_INIT_VECTOR_MASK)) | SCM_CPU1VTOR_CPU1_INIT_VECTOR(u32Value));
}
#endif
#ifdef SCM_CPU2VTOR_CPU2_INIT_VECTOR_MASK
/**
* @brief Set the CPU2VTOR register value
*
* @param u32Val value to be set
*/
LOCAL_INLINE void SCM_HWA_Set_CPU2VTOR(uint32_t u32Val)
{
SCM->CPU2VTOR = u32Val;
}
/**
* @brief Get the CPU2VTOR register status
*
* @return Lock status
*/
LOCAL_INLINE uint32_t SCM_HWA_Get_CPU2VTOR(void)
{
return SCM->CPU2VTOR;
}
/**
* @brief Set Core Hold Register vector initial vector
*
* @param u32Value value to be set
*/
LOCAL_INLINE void SCM_HWA_CPU2VTOR_SetVector(uint32_t u32Value)
{
uint32_t u32RegVal = SCM->CPU2VTOR;
SCM->CPU2VTOR = ((u32RegVal & (~(uint32_t)SCM_CPU2VTOR_CPU2_INIT_VECTOR_MASK)) | SCM_CPU2VTOR_CPU2_INIT_VECTOR(u32Value));
}
#endif
#ifdef SCM_CPU3VTOR_CPU3_INIT_VECTOR_MASK
/**
* @brief Set the CPU3VTOR register value
*
* @param u32Val value to be set
*/
LOCAL_INLINE void SCM_HWA_Set_CPU3VTOR(uint32_t u32Val)
{
SCM->CPU3VTOR = u32Val;
}
/**
* @brief Get the CPU3VTOR register status
*
* @return Lock status
*/
LOCAL_INLINE uint32_t SCM_HWA_Get_CPU3VTOR(void)
{
return SCM->CPU3VTOR;
}
/**
* @brief Set Core Hold Register vector initial vector
*
* @param u32Value value to be set
*/
LOCAL_INLINE void SCM_HWA_CPU3VTOR_SetVector(uint32_t u32Value)
{
uint32_t u32RegVal = SCM->CPU3VTOR;
SCM->CPU3VTOR = ((u32RegVal & (~(uint32_t)SCM_CPU3VTOR_CPU3_INIT_VECTOR_MASK)) | SCM_CPU3VTOR_CPU3_INIT_VECTOR(u32Value));
}
#endif
#ifdef SCM_CORE_HOLD_CPU1_CORE_HOLD_MASK
/**
* @brief Set cpu1 hold enable status
*
* @param bEnable Enable/Disable status
*/
LOCAL_INLINE void SCM_HWA_SetCOREHOLD_Cpu1Hold(bool bEnable)
{
if (true == bEnable)
{
SCM->CORE_HOLD |= (uint32_t)SCM_CORE_HOLD_CPU1_CORE_HOLD_MASK;
}
else
{
SCM->CORE_HOLD &= ~(uint32_t)SCM_CORE_HOLD_CPU1_CORE_HOLD_MASK;
}
}
#endif
#ifdef SCM_CORE_HOLD_CPU2_CORE_HOLD_MASK
/**
* @brief Set cpu2 hold enable status
*
* @param bEnable Enable/Disable status
*/
LOCAL_INLINE void SCM_HWA_SetCOREHOLD_Cpu2Hold(bool bEnable)
{
if (true == bEnable)
{
SCM->CORE_HOLD |= (uint32_t)SCM_CORE_HOLD_CPU2_CORE_HOLD_MASK;
}
else
{
SCM->CORE_HOLD &= ~(uint32_t)SCM_CORE_HOLD_CPU2_CORE_HOLD_MASK;
}
}
#endif
#ifdef SCM_CORE_HOLD_CPU3_CORE_HOLD_MASK
/**
* @brief Set cpu3 hold enable status
*
* @param bEnable Enable/Disable status
*/
LOCAL_INLINE void SCM_HWA_SetCOREHOLD_Cpu3Hold(bool bEnable)
{
if (true == bEnable)
{
SCM->CORE_HOLD |= (uint32_t)SCM_CORE_HOLD_CPU3_CORE_HOLD_MASK;
}
else
{
SCM->CORE_HOLD &= ~(uint32_t)SCM_CORE_HOLD_CPU3_CORE_HOLD_MASK;
}
}
#endif
#if SCM_ADC_PRE_TRIGGER_SEL_SUPPORT
LOCAL_INLINE void SCM_HWA_SetAdcPretriggerSel(SCM_AdcInstance eInstance, SCM_AdcPreTriggerSel ePreTriggerSel)
{
#if ADC_INSTANCE_COUNT > 5U
if (eInstance == SCM_ADC_INSTANCE_5)
{
SCM->ADC_ROUTING1 = (SCM->ADC_ROUTING1 & ~SCM_ADC_ROUTING1_ADC5_PRETRGSEL_MASK) |
SCM_ADC_ROUTING1_ADC5_PRETRGSEL(ePreTriggerSel);
}
else
#endif
#if ADC_INSTANCE_COUNT > 4U
if (eInstance == SCM_ADC_INSTANCE_4)
{
SCM->ADC_ROUTING1 = (SCM->ADC_ROUTING1 & ~SCM_ADC_ROUTING1_ADC4_PRETRGSEL_MASK) |
SCM_ADC_ROUTING1_ADC4_PRETRGSEL(ePreTriggerSel);
}
else
#endif
#if ADC_INSTANCE_COUNT > 3U
if (eInstance == SCM_ADC_INSTANCE_3)
{
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC3_PRETRGSEL_MASK) |
SCM_ADC_ROUTING_ADC3_PRETRGSEL(ePreTriggerSel);
}
else
#endif
#if ADC_INSTANCE_COUNT > 2U
if (eInstance == SCM_ADC_INSTANCE_2)
{
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC2_PRETRGSEL_MASK) |
SCM_ADC_ROUTING_ADC2_PRETRGSEL(ePreTriggerSel);
}
else
#endif
#if ADC_INSTANCE_COUNT > 1U
if (eInstance == SCM_ADC_INSTANCE_1)
{
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC1_PRETRGSEL_MASK) |
SCM_ADC_ROUTING_ADC1_PRETRGSEL(ePreTriggerSel);
}
else
#endif
#if ADC_INSTANCE_COUNT > 0U
if (eInstance == SCM_ADC_INSTANCE_0)
{
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC0_PRETRGSEL_MASK) |
SCM_ADC_ROUTING_ADC0_PRETRGSEL(ePreTriggerSel);
}
#endif
}
#endif
#if SCM_ADC_TRIGGER_SEL_SUPPORT
LOCAL_INLINE void SCM_HWA_SetAdcTriggerSel(SCM_AdcInstance eInstance, SCM_AdcTriggerSel eTriggerSel)
{
#if ADC_INSTANCE_COUNT > 5U
if (eInstance == SCM_ADC_INSTANCE_5)
{
SCM->ADC_ROUTING1 = (SCM->ADC_ROUTING1 & ~SCM_ADC_ROUTING1_ADC5_TRGSEL_MASK) |
SCM_ADC_ROUTING1_ADC5_TRGSEL(eTriggerSel);
}
else
#endif
#if ADC_INSTANCE_COUNT > 4U
if (eInstance == SCM_ADC_INSTANCE_4)
{
SCM->ADC_ROUTING1 = (SCM->ADC_ROUTING1 & ~SCM_ADC_ROUTING1_ADC4_TRGSEL_MASK) |
SCM_ADC_ROUTING1_ADC4_TRGSEL(eTriggerSel);
}
else
#endif
#if ADC_INSTANCE_COUNT > 3U
if (eInstance == SCM_ADC_INSTANCE_3)
{
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC3_TRGSEL_MASK) |
SCM_ADC_ROUTING_ADC3_TRGSEL(eTriggerSel);
}
else
#endif
#if ADC_INSTANCE_COUNT > 2U
if (eInstance == SCM_ADC_INSTANCE_2)
{
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC2_TRGSEL_MASK) |
SCM_ADC_ROUTING_ADC2_TRGSEL(eTriggerSel);
}
else
#endif
#if ADC_INSTANCE_COUNT > 1U
if (eInstance == SCM_ADC_INSTANCE_1)
{
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC1_TRGSEL_MASK) |
SCM_ADC_ROUTING_ADC1_TRGSEL(eTriggerSel);
}
else
#endif
#if ADC_INSTANCE_COUNT > 0U
if (eInstance == SCM_ADC_INSTANCE_0)
{
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC0_TRGSEL_MASK) |
SCM_ADC_ROUTING_ADC0_TRGSEL(eTriggerSel);
}
#endif
}
#endif
#if SCM_HSADC_BIAS_FORCE_ENABLE_SUPPORT
LOCAL_INLINE void SCM_HWA_SetHsadcBiasForceEnable(void)
{
SCM->ADC_CFG = SCM->ADC_CFG | (1U << 31U);
}
#endif
/** @}*/
#endif /* #if SCM_INSTANCE_COUNT > 0U */
#endif /*#ifndef _HWA_SCM_H_ */

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/**
* @file HwA_sec.h
* @author Flagchip
* @brief sec hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip120 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip120 N/A Change version and release
******************************************************************************** */
#ifndef HWA_INCLUDE_HWA_SEC_H_
#define HWA_INCLUDE_HWA_SEC_H_
#include "device_header.h"
#if SEC_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_sec HwA_sec
* @ingroup module_driver_sec
* @{
*/
/* DEN Bit Fields */
/**
* @brief Enable the debug module
*
* @param pSec A pointer to the SEC registers.
*/
LOCAL_INLINE void SEC_HWA_EnDebug(SEC_Type *const pSec)
{
pSec->DEN = SEC_DEN_DEN(0X5) ;
}
/* FSEC0 Bit Fields */
/**
* @brief Get the system security KEY0
*
* @param pSec A pointer to the SEC registers.
* */
LOCAL_INLINE uint16_t SEC_HWA_GetSScontrol0(SEC_Type *const pSec)
{
return (uint16_t)((pSec->FSEC0) & (SEC_FSEC0_SSC0_MASK));
}
/* FSEC1 Bit Fields */
/**
* @brief Get the system security KEY1
*
* @param pSec A pointer to the SEC registers.
* */
LOCAL_INLINE uint16_t SEC_HWA_GetSScontrol1(SEC_Type *const pSec)
{
return (uint16_t)((pSec->FSEC1) & (SEC_FSEC1_SSC1_MASK));
}
/* DCWOR Bit Fields */
/**
* @brief Re-enable the Debug mode.
* @note This register can only be write once. startup_fc4150.s has lock the register.
*
* @param pSec A pointer to the SEC registers.
* */
LOCAL_INLINE void SEC_HWA_ReEnDebug(SEC_Type *const pSec)
{
pSec->DCWOR = ((pSec->DCWOR & (~SEC_DCWOR_DEA_MASK)) | SEC_DCWOR_DEA(0X5));
}
/**
* @brief Get the Re-enable Debug permission.
*
* @param pSec A pointer to the SEC registers.
* */
LOCAL_INLINE bool SEC_HWA_GetReEnDebug(SEC_Type *const pSec)
{
bool ret = false;
uint8_t dea = (uint8_t)((pSec->DCWOR & (SEC_DCWOR_DEA_MASK)) >> SEC_DCWOR_DEA_SHIFT);
if (dea == 0x5U)
{
ret = true;
}
return ret;
}
/**
* @brief Enable the write operation for SEC register.
* @note This register can only be write once. startup_fc4150.s has lock the register.
*
* @param pSec A pointer to the SEC registers.
* */
LOCAL_INLINE void SEC_HWA_WriteUnlock(SEC_Type *const pSec)
{
pSec->DCWOR = ((pSec->DCWOR & (~SEC_DCWOR_RWL_MASK)) | SEC_DCWOR_RWL(0X5));
}
/**
* @brief Get the sec write permission
*
* @param pSec A pointer to the SEC registers.
* @return true means allow write. false means forbid write.
*/
LOCAL_INLINE bool SEC_HWA_GetWritePer(SEC_Type *const pSec)
{
bool ret = false;
uint8_t rwl = (uint8_t)((pSec->DCWOR & (SEC_DCWOR_RWL_MASK)) >> SEC_DCWOR_RWL_SHIFT);
if ((rwl == 0x5U) || (rwl == 0xFU))
{
ret = true;
}
return ret;
}
/* DEK Bit Fields */
/**
* @brief Enable the write operation for SEC register.
*
* @param pSec A pointer to the SEC registers.
* @param count Counter indicating the number of encryption executions
* @param key New encryption key to be written
* */
LOCAL_INLINE void SEC_HWA_WriteReEnKeyn(SEC_Type *const pSec, uint8_t count, uint32_t key)
{
if (count < 4u)
{
pSec->DEN = key;
}
}
/* TME Bit Fields */
/**
* @brief Enable the Test module
*
* @param pSec A pointer to the SEC registers.
* */
LOCAL_INLINE void SEC_HWA_EnTest(SEC_Type *const pSec)
{
pSec->TME = SEC_TME_TME(0X5) ;
}
/* TMEA Bit Fields */
/**
* @brief Re-Enable Test mode
*
* @param pSec A pointer to the SEC registers.
* */
LOCAL_INLINE void SEC_HWA_ReEnTest(SEC_Type *const pSec)
{
pSec->TMEA = SEC_TMEA_TMEA(0X5) ;
}
/**
* @brief Get the Re-enable Test permission.
*
* @param pSec A pointer to the SEC registers.
* */
LOCAL_INLINE bool SEC_HWA_GetReEnTest(SEC_Type *const pSec)
{
bool ret = false;
uint8_t tmea = (uint8_t)((pSec->TMEA & (SEC_TMEA_TMEA_MASK)) >> SEC_TMEA_TMEA_SHIFT);
if ((tmea == 0x5U) || (tmea == 0xFU))
{
ret = true;
}
return ret;
}
/* TMEK Bit Fields */
/**
* @brief write Test re-enable mode key
*
* @param pSec A pointer to the SEC registers.
* @param testkey The test key value to be reloaded into the TMEK register.
*/
LOCAL_INLINE void SEC_HWA_ReEnTestKey(SEC_Type *const pSec, uint32_t testkey)
{
pSec->TMEK = SEC_TMEK_TMEK(testkey) ;
}
/* FCR0 Bit Fields */
/**
* @brief Enable the Mass Erase
*
* @param pSec A pointer to the SEC registers.
*/
LOCAL_INLINE void SEC_HWA_EnME(SEC_Type *const pSec)
{
pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_MED_MASK)) | SEC_FCR0_MED(0x5));
}
#if SEC_FCR0_NRP_MASK
/**
* @brief Enable the Block 0 NVR read .
*
* @param pSec A pointer to the SEC registers.
*/
LOCAL_INLINE void SEC_HWA_EnReadB0NVR(SEC_Type *const pSec)
{
pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_NRP_MASK)) | SEC_FCR0_NRP(0x5)) ;
}
/**
* @brief Disable the Block 0 NVR read .
*
* @param pSec A pointer to the SEC registers.
*/
LOCAL_INLINE void SEC_HWA_DisReadB0NVR(SEC_Type *const pSec)
{
pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_NRP_MASK)) | SEC_FCR0_NRP(0xA)) ;
}
#endif
#if SEC_NKRP_NKRP_MASK
/**
* @brief Enable the Block 0 NVR key read .
*
* @param pSec A pointer to the SEC registers.
*/
LOCAL_INLINE void SEC_HWA_EnReadB0NVRKey(SEC_Type *const pSec)
{
pSec->NKRP = ((pSec->NKRP & (~SEC_NKRP_NKRP_MASK)) | SEC_NKRP_NKRP(0x5)) ;
}
/**
* @brief Disable the Block 0 NVR Key read .
*
* @param pSec A pointer to the SEC registers.
*/
LOCAL_INLINE void SEC_HWA_DisReadB0NVRKey(SEC_Type *const pSec)
{
pSec->NKRP = ((pSec->NKRP & (~SEC_NKRP_NKRP_MASK)) | SEC_NKRP_NKRP(0xA)) ;
}
#endif
/**
* @brief Enable the Block 0 NVR write .
*
* @param pSec A pointer to the SEC registers.
*/
LOCAL_INLINE void SEC_HWA_EnWriteB0NVR(SEC_Type *const pSec)
{
pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_NWP_MASK)) | SEC_FCR0_NWP(0x5)) ;
}
/**
* @brief Disable the Block 0 NVR write .
*
* @param pSec A pointer to the SEC registers.
*/
LOCAL_INLINE void SEC_HWA_DisWriteB0NVR(SEC_Type *const pSec)
{
pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_NWP_MASK)) | SEC_FCR0_NWP(0xA)) ;
}
/**
* @brief Enable the Block 0 NVR erase .
*
* @param pSec A pointer to the SEC registers.
*/
LOCAL_INLINE void SEC_HWA_EnEraseB0NVR(SEC_Type *const pSec)
{
pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_NEP_MASK)) | SEC_FCR0_NEP(0x5)) ;
}
/**
* @brief Disable the Block 0 NVR erase .
*
* @param pSec A pointer to the SEC registers.
*/
LOCAL_INLINE void SEC_HWA_DisEraseB0NVR(SEC_Type *const pSec)
{
pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_NEP_MASK)) | SEC_FCR0_NEP(0xA)) ;
}
/* BCS Bit Fields */
/**
* @brief Get the Fast Boot Select.
*
* @param pSec A pointer to the SEC registers.
* @return 0b - Select PLL0 as the core clock source; the core clock is 300MHz
* 1b - Select FIRC as the core clock source; the core clock is 96MHz.
* */
LOCAL_INLINE uint8_t SEC_HWA_GetFastBootClock(SEC_Type *const pSec)
{
return (uint8_t)((pSec->BCS & SEC_BCS_FBS_MASK) >> SEC_BCS_FBS_SHIFT);
}
/**
* @brief NMI Function Enable/Disable
*
* @param pSec A pointer to the SEC registers.
* @return false - NMI pin function is disabled after reset.
* true - NMI pin function is enabled
* */
LOCAL_INLINE bool SEC_HWA_GetNmiPin(SEC_Type *const pSec)
{
return (bool)((pSec->BCS & SEC_BCS_NMIDIS_MASK) >> SEC_BCS_NMIDIS_SHIFT);
}
#if SEC_BCS_ISPDIS_MASK
/**
* @brief ISP Function Enable/Disable
*
* @param pSec A pointer to the SEC registers.
* @return false - ISP pin function is disabled after reset.
* true - ISP pin function is enabled.
* */
LOCAL_INLINE bool SEC_HWA_GetIspEn(SEC_Type *const pSec)
{
return (bool)((pSec->BCS & SEC_BCS_ISPDIS_MASK) >> SEC_BCS_ISPDIS_SHIFT);
}
#endif
/**
* @brief Boot Rom Configuration
*
* @param pSec A pointer to the SEC registers.
* @return false - Boot from GPR defined address (except ROM).
* true - Boot from ROM.
* */
LOCAL_INLINE bool SEC_HWA_GetBootRom(SEC_Type *const pSec)
{
return (bool)((pSec->BCS & SEC_BCS_BOOTROM_MASK) >> SEC_BCS_BOOTROM_SHIFT);
}
/**
* @brief ISP Mode Status
*
* @param pSec A pointer to the SEC registers.
* @return false - ISP mode is inactive.
* true - ISP mode is active.
* */
LOCAL_INLINE bool SEC_HWA_GetIspStatus(SEC_Type *const pSec)
{
return (bool)((pSec->BCS & SEC_BCS_ISPMODE_MASK) >> SEC_BCS_ISPMODE_SHIFT);
}
/* UKAC Bit Fields */
/**
* @brief User Key Access Enable. Only valid under non-secure boot
*
* @param pSec A pointer to the SEC registers.
* @return true means User key can be read/programmed/erased by host CPU ,false means User key is not available for host cpu
* */
LOCAL_INLINE bool SEC_HWA_GetUKAS(SEC_Type *const pSec)
{
bool ret = false;
uint8_t uake =(uint8_t)((pSec->UKAC & SEC_UKAC_UKAE_MASK) >> SEC_UKAC_UKAE_SHIFT);
if ((uake == 0x5U) || (uake == 0xFU))
{
ret = true;
}
return ret;
}
/* BRC0 Bit Fields */
/**
* @brief Secure Boot Disable (Value loaded from NVR sector)
*
* @param pSec A pointer to the SEC registers.
* @return true means Secure boot mode , false means Non secure boot mode.
*/
LOCAL_INLINE bool SEC_HWA_GetSB(SEC_Type *const pSec)
{
bool ret = false;
#if SEC_BRC0_SECURE_BOOT_DIS_MASK
uint8_t sbdis = (uint8_t)((pSec->BRC0 & SEC_BRC0_SECURE_BOOT_DIS_MASK) >> SEC_BRC0_SECURE_BOOT_DIS_SHIFT);
if (sbdis == 0x0u)
{
ret = true;
}
#elif defined SEC_BRC0_SB_LC_EN_MASK
uint8_t sbdis = (uint8_t)((pSec->BRC0 & SEC_BRC0_SB_LC_EN_MASK) >> SEC_BRC0_SB_LC_EN_SHIFT);
if (sbdis == 0x0u)
{
ret = true;
}
#else
#endif
return ret;
}
/**
* @brief Host Debug Auth Enable. Only valid in secure boot. (Value loaded from NVR sector)
*
* @param pSec A pointer to the SEC registers.
* @return true means Host debug authentication enable. false means Host debug authentication disable.
*/
LOCAL_INLINE bool SEC_HWA_GetDEAUEn(SEC_Type *const pSec)
{
bool ret = false;
uint8_t dean = (uint8_t)((pSec->BRC0 & SEC_BRC0_DEBUG_AUTH_EN_MASK) >> SEC_BRC0_DEBUG_AUTH_EN_SHIFT);
if ((dean == 0x5u) || (dean == 0xFu))
{
ret = true;
}
return ret;
}
/**
* @brief ISP Auth Enable. Only valid in secure boot. (Value loaded from NVR sector)
*
* @param pSec A pointer to the SEC registers.
* @return true means ISP authentication enable, false means ISP authentication disable.
*/
LOCAL_INLINE bool SEC_HWA_GetISPAU(SEC_Type *const pSec)
{
bool ret = false;
uint8_t isp = (uint8_t)((pSec->BRC0 & SEC_BRC0_ISP_AUTH_EN_MASK) >> SEC_BRC0_ISP_AUTH_EN_SHIFT);
if ((isp == 0x5u) || (isp == 0xFu))
{
ret = true;
}
return ret;
}
#if SEC_BRC0_FW_READ_DIS_MASK
/**
* @brief Firmware Read Disable/Enable. (Value loaded from NVR sector)
*
* @param pSec A pointer to the SEC registers.
* @return true means Host core read access to firmware read is disabled, false means - Host core read access to firmware read is enabled.
*/
LOCAL_INLINE bool SEC_HWA_GetFWRE(SEC_Type *const pSec)
{
bool ret = false;
uint8_t fwre = (uint8_t)((pSec->BRC0 & SEC_BRC0_FW_READ_DIS_MASK) >> SEC_BRC0_FW_READ_DIS_SHIFT);
if ((fwre == 0x5u) || (fwre == 0xFu))
{
ret = true;
}
return ret;
}
#endif
#if SEC_BRC1_FW_VALID_MASK
/* BRC1 Bit Fields */
/**
* @brief Get whether Flash Firmware is valid.
*
* @param pSec A pointer to the SEC registers.
* @return true means Flash Firmware is valid. false means Flash Firmware is invalid
* */
LOCAL_INLINE bool SEC_HWA_GetFwValid(SEC_Type *const pSec)
{
bool ret = false;
uint8_t fw = (uint8_t)((pSec->BRC1 & SEC_BRC1_FW_VALID_MASK) >> SEC_BRC1_FW_VALID_SHIFT);
if (fw != 0xFU)
{
ret = true;
}
return ret;
}
#endif
/**
* @brief Get the FCUART Baud Rate for ISP
*
* @param pSec A pointer to the SEC registers.
* @return FCUART Baud Rate for ISP
* */
LOCAL_INLINE uint8_t SEC_HWA_GetUartBR(SEC_Type *const pSec)
{
return (uint8_t)((pSec->BRC1 & SEC_BRC1_UARTBR_MASK) >> SEC_BRC1_UARTBR_SHIFT);
}
/**
* @brief Get CAN Baud Rate for ISP
*
* @param pSec A pointer to the SEC registers.
* @return CAN Baud Rate for ISP
* */
LOCAL_INLINE uint8_t SEC_HWA_GetCanBR(SEC_Type *const pSec)
{
return (uint8_t)((pSec->BRC1 & SEC_BRC1_CANBR_MASK) >> SEC_BRC1_CANBR_SHIFT);
}
/**
* @brief Get OSC Frequency
*
* @param pSec A pointer to the SEC registers.
* @return OSC Frequency
* */
LOCAL_INLINE uint8_t SEC_HWA_GetOSCFre(SEC_Type *const pSec)
{
return (uint8_t)((pSec->BRC1 & SEC_BRC1_OSCFREQ_MASK) >> SEC_BRC1_OSCFREQ_SHIFT);
}
/**
* @brief Get whether OSC Available.
*
* @param pSec A pointer to the SEC registers.
* @return true means OSC is available. false means -OSC is not available
* */
LOCAL_INLINE bool SEC_HWA_GetOSCAvail(SEC_Type *const pSec)
{
bool ret = false;
uint8_t osc = (uint8_t)((pSec->BRC1 & SEC_BRC1_OSCA_MASK) >> SEC_BRC1_OSCA_SHIFT);
if (osc == 0x0U)
{
ret = true;
}
return ret;
}
/**
* @brief Get whether Debug Mailbox Backdoor Key Enable.
*
* @param pSec A pointer to the SEC registers.
* @return true means user can enable debug by writing debug backdoor key, false means user can not enable debug
* */
LOCAL_INLINE bool SEC_HWA_GetMBBKEN(SEC_Type *const pSec)
{
bool ret = false;
#if SEC_BRC1_DBG_MB_BKD_EN_MASK
uint8_t mbbk = (uint8_t)((pSec->BRC1 & SEC_BRC1_DBG_MB_BKD_EN_MASK) >> SEC_BRC1_DBG_MB_BKD_EN_SHIFT);
if (mbbk == 0x5U)
#elif SEC_BRC1_DBK_IN_EN_MASK
uint8_t mbbk = (uint8_t)((pSec->BRC1 & SEC_BRC1_DBK_IN_EN_MASK) >> SEC_BRC1_DBK_IN_EN_SHIFT);
if((mbbk == 0x3U) || (mbbk == 0xFU))
#else
#endif
{
ret = true;
}
return ret;
}
#if SEC_FWA_MASK
/* FWA Bit Fields */
/**
* @brief Get the HSM Firmware Address.
*
* @param pSec A pointer to the SEC registers.
* @return the HSM Firmware Address.
* */
LOCAL_INLINE uint32_t SEC_HWA_GetHsmAddr(SEC_Type *const pSec)
{
return (uint32_t)(pSec->FWA & SEC_FWA_HSM_FW_ADDR_MASK);
}
#endif
/* BRC2 Bit Fields */
/**
* @brief Get Bootloader Verification Mask
*
* @param pSec A pointer to the SEC registers.
* @return Bootloader Verification Mask.
* */
LOCAL_INLINE uint32_t SEC_HWA_GetBLMask(SEC_Type *const pSec)
{
#if SEC_BRC2_USERCODE_VERIFY_MASK_MASK
return (uint32_t)((pSec->BRC2 & SEC_BRC2_USERCODE_VERIFY_MASK_MASK) >> SEC_BRC2_USERCODE_VERIFY_MASK_SHIFT);
#elif SEC_BRC2_IMG_VERIFY_MASK_MASK
return (uint32_t)((pSec->BRC2 & SEC_BRC2_IMG_VERIFY_MASK_MASK) >> SEC_BRC2_IMG_VERIFY_MASK_SHIFT);
#else
#endif
}
/**
* @brief Get the ISP Instance Select.
*
* @param pSec A pointer to the SEC registers.
* @return ISP Instance Select
* */
LOCAL_INLINE uint8_t SEC_HWA_GetIspIns(SEC_Type *const pSec)
{
return (uint8_t)((pSec->BRC2 & SEC_BRC2_ISP_INST_SEL_MASK) >> SEC_BRC2_ISP_INST_SEL_SHIFT);
}
/**
* @brief Get Bootloader Verification Algorithm
*
* @param pSec A pointer to the SEC registers.
* @return Bootloader Verification Algorithm
* */
LOCAL_INLINE uint8_t SEC_HWA_GetBLVer(SEC_Type *const pSec)
{
#if SEC_BRC2_USERCODE_VERIFICATION_ALG_MASK
return (uint8_t)((pSec->BRC2 & SEC_BRC2_USERCODE_VERIFICATION_ALG_MASK) >> SEC_BRC2_USERCODE_VERIFICATION_ALG_SHIFT);
#elif SEC_BRC2_IMG_VERIF_ALG_MASK
return (uint8_t)((pSec->BRC2 & SEC_BRC2_IMG_VERIF_ALG_MASK) >> SEC_BRC2_IMG_VERIF_ALG_SHIFT);
#else
#endif
}
#if SEC_BRC2_DECRP_ALG_MASK
/**
* @brief Get Debug/ISP/PREFA Authentication and USRK decryption algorithm
*
* @param pSec A pointer to the SEC registers.
* @return 1b - SM2, 0b - ECC256
* */
LOCAL_INLINE uint8_t SEC_HWA_GetDecrypt(SEC_Type *const pSec)
{
return (uint8_t)((pSec->BRC2 & SEC_BRC2_DECRP_ALG_MASK) >> SEC_BRC2_DECRP_ALG_SHIFT);
}
#endif
/* BTLA Bit Fields */
/**
* @brief Get the bootloader address.
*
* @param pSec A pointer to the SEC registers.
* @return Bootloader Address.
* */
LOCAL_INLINE uint32_t SEC_HWA_GetBLAddr(SEC_Type *const pSec)
{
return (uint32_t)((pSec->IMGEA & SEC_IMGEA_IMAGE_ADDR_MASK) >> SEC_IMGEA_IMAGE_ADDR_SHIFT);
}
/* LCSTAT Bit Fields */
/**
* @brief Get the life cycle status of the chip.
*
* @param pSec A pointer to the SEC registers.
* @return The lifecycle status
* */
LOCAL_INLINE uint8_t SEC_HWA_GetLCStaus(SEC_Type *const pSec)
{
return (uint8_t)(pSec->LCSTAT & 0XFFU);
}
/* FAC Bit Fields */
/**
* @brief Get the Host User Key Read Protection
*
* @param pSec A pointer to the SEC registers.
* @return true - Host read access to User Key region is enabled
* false - Host read access to User Key region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHUKRead(SEC_Type *const pSec)
{
return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_UKEY_RPROT_MASK) >> SEC_FAC_HOST_UKEY_RPROT_SHIFT));
}
/**
* @brief Get the Host User Key write Protection
*
* @param pSec A pointer to the SEC registers.
* @return true - Host write access to User Key region is enabled
* false - Host write access to User Key region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHUKWrite(SEC_Type *const pSec)
{
return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_UKEY_WPROT_MASK) >> SEC_FAC_HOST_UKEY_WPROT_SHIFT));
}
/**
* @brief Get the Host User Key erase Protection
*
* @param pSec A pointer to the SEC registers.
* @return true - Host erase access to User Key region is enabled
* false - Host erase access to User Key region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHUKErase(SEC_Type *const pSec)
{
return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_UKEY_EPROT_MASK) >> SEC_FAC_HOST_UKEY_EPROT_SHIFT));
}
/**
* @brief Get the Host NVR Read Protection
*
* @param pSec A pointer to the SEC registers.
* @return true - Host read access to NVR region is enabled
* false - Host read access to NVR region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHostNvrRead(SEC_Type *const pSec)
{
return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_NVR_RPROT_MASK) >> SEC_FAC_HOST_NVR_RPROT_SHIFT));
}
/**
* @brief Get the Host NVR write Protection
*
* @param pSec A pointer to the SEC registers.
* @return true - Host write access to NVR region is enabled
* false - Host write access to NVR region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHostNvrWrite(SEC_Type *const pSec)
{
return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_NVR_WPROT_MASK) >> SEC_FAC_HOST_NVR_WPROT_SHIFT));
}
/**
* @brief Get the Host NVR erase Protection
*
* @param pSec A pointer to the SEC registers.
* @return true - Host erase access to NVR region is enabled
* false - Host erase access to NVR region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHostNvrErase(SEC_Type *const pSec)
{
return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_NVR_EPROT_MASK) >> SEC_FAC_HOST_NVR_EPROT_SHIFT));
}
/**
* @brief Get the HSM User Key Erase Protection
*
* @param pSec A pointer to the SEC registers.
* @return true - HSM erase access to User Key region is enabled
* false -HSM erase access to User Key region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHsmUKErase(SEC_Type *const pSec)
{
#if SEC_FAC_HSM_UKEY_EPROT_MASK
return (bool)(~(((pSec->FAC) & SEC_FAC_HSM_UKEY_EPROT_MASK) >> SEC_FAC_HSM_UKEY_EPROT_SHIFT));
#elif SEC_FAC_HOST_EUKEY_EPROT_MASK
return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_EUKEY_EPROT_MASK) >> SEC_FAC_HOST_EUKEY_EPROT_SHIFT));
#else
#endif
}
/**
* @brief Get the HSM NVR Erase Protection
*
* @param pSec A pointer to the SEC registers.
* @return true - HSM erase access to NVR region is enabled
* false -HSM erase access to NVR region is disabled
* */
LOCAL_INLINE bool SEC_HWA_GetHsmNvrErase(SEC_Type *const pSec)
{
return (bool)(~(((pSec->FAC) & SEC_FAC_HSM_NVR_EPROT_MASK) >> SEC_FAC_HSM_NVR_EPROT_SHIFT));
}
/** @}*/ /* HwA_SEC */
#endif /* #if SEC_INSTANCE_COUNT > 0U */
#endif /* HWA_INCLUDE_HWA_SEC_H_ */

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/**
* @file HwA_ssi.h
* @author flagchip
* @brief ssi hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 2.0.0 2023-12-12 Flagchip054 N/A First version for FC7300
******************************************************************************** */
#ifndef _HWA_SSI_H_
#define _HWA_SSI_H_
#include "device_header.h"
#if SSI_INSTANCE_COUNT > 0U
/**
* @brief Enable Function Clock
*
* @param SSI instance value
*/
LOCAL_INLINE void SSI_HWA_Func_Enable(SSI_Type *pSsi)
{
pSsi->GCR |= SSI_GCR_FUNC_EN_MASK;
}
/**
* @brief Disable Function Clock
*
* @param SSI Pointer to the SSI_Type structure representing the SSI peripheral instance
*/
LOCAL_INLINE void SSI_HWA_Func_Disable(SSI_Type *pSsi)
{
pSsi->GCR &= ~SSI_GCR_FUNC_EN_MASK;
}
/**
* @brief Set Function Clock Divider
*
* @param SSI Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u32Value devider
*/
LOCAL_INLINE void SSI_HWA_SetFuncDev(SSI_Type *pSsi, uint32_t u32Value)
{
pSsi->GCR = (pSsi->GCR & ~SSI_GCR_FUNC_DIV_MASK) | SSI_GCR_FUNC_DIV(u32Value);
}
/**
* @brief Get the value of the Global Status Register (GSR)
*
* This function reads the value of the Global Status Register (GSR) for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @return The value of the Global Status Register (GSR)
*/
LOCAL_INLINE uint32_t SSI_HWA_GetGlobalStatus(SSI_Type *pSsi)
{
return pSsi->GSR;
}
/**
* @brief Get the value of the Global Error Status
*
* This function reads the value of the Global Error Status for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @return The value of the Global Error Status
*/
LOCAL_INLINE uint32_t SSI_HWA_GetGlobalErrStatus(SSI_Type *pSsi)
{
uint32_t u32ErrStatus;
u32ErrStatus = pSsi->GSR & ~SSI_GSR_SPC_VLD_MASK;
return u32ErrStatus;
}
/**
* @brief Get the value of the SpcVld Status
*
* This function reads the value of the SpcVld Status for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @return The value of the SpcVld Status
*/
LOCAL_INLINE uint32_t SSI_HWA_GetSpcVldStatus(SSI_Type *pSsi)
{
return ((pSsi->GSR & SSI_GSR_SPC_VLD_MASK) >> SSI_GSR_SPC_VLD_SHIFT);
}
/**
* @brief Get the value of the Wheel Stop Status
*
* This function reads the value of the Wheel Stop Status for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @return The value of the SpcVld
*/
LOCAL_INLINE uint32_t SSI_HWA_GetWhlStopStatus(SSI_Type *pSsi)
{
return ((pSsi->GSR & SSI_GSR_WHL_STOP_MASK) >> SSI_GSR_WHL_STOP_WIDTH);
}
/**
* @brief Get the value of the Sensor Protocol Counter Timeout Status
*
* This function reads the value of the SPC Timeout Status for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @return The value of the SpcTimeout Status
*/
LOCAL_INLINE uint32_t SSI_HWA_GetSpcTimeoutStatus(SSI_Type *pSsi)
{
return ((pSsi->GSR & SSI_GSR_SPC_TIMEOUT_MASK) >> SSI_GSR_SPC_TIMEOUT_SHIFT);
}
/**
* @brief Get the value of SPC Range Status
*
* This function reads the value of the SPC Range Status for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @return The value of the SPC Range Status
*/
LOCAL_INLINE uint32_t SSI_HWA_GetSpcRangeErrStatus(SSI_Type *pSsi)
{
return ((pSsi->GSR & SSI_GSR_SPC_RANGE_ERR_MASK) >> SSI_GSR_SPC_RANGE_ERR_SHIFT);
}
/**
* @brief Get the value of Protocol Decoder Status
*
* This function reads the value of the Protocol Decoder Status for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @return The value of the Protocol Decoder Status
*/
LOCAL_INLINE uint32_t SSI_HWA_GetDecodeErrStatus(SSI_Type *pSsi)
{
return ((pSsi->GSR & SSI_GSR_DECODE_ERR_MASK) >> SSI_GSR_DECODE_ERR_SHIFT);
}
/**
* @brief Get the value of Protocol Interval Status
*
* This function reads the value of the Protocol Interval Status for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @return The value of the Protocol Interval Status
*/
LOCAL_INLINE uint32_t SSI_HWA_GetIntervalErrStatus(SSI_Type *pSsi)
{
return ((pSsi->GSR & SSI_GSR_INTERVAL_ERR_MASK) >> SSI_GSR_INTERVAL_ERR_SHIFT);
}
/**
* @brief Get the value of Pulse Width Status
*
* This function reads the value of the Pulse Width Status for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @return The value of the Pulse Width Status
*/
LOCAL_INLINE uint32_t SSI_HWA_GetPulseWdhErrStatus(SSI_Type *pSsi)
{
return ((pSsi->GSR & SSI_GSR_PULSE_WIDTH_ERR_MASK) >> SSI_GSR_PULSE_WIDTH_ERR_SHIFT);
}
/**
* @brief Get the value of Protocol Status
*
* This function reads the value of the Protocol Status for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @return The value of Protocol Status
*/
LOCAL_INLINE uint32_t SSI_HWA_GetProtErrStatus(SSI_Type *pSsi)
{
return ((pSsi->GSR & SSI_GSR_PROTOC_ERR_MASK) >> SSI_GSR_PROTOC_ERR_SHIFT);
}
/**
* @brief Set the Lower Part of the Global Counter Window Register (GCWLR)
*
* This function sets the lower part of the Global Counter Window Register (GCWLR) for the specified
* SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u32Value The value to set in the lower part of the GCWLR register
*/
LOCAL_INLINE void SSI_HWA_SetGlobalCounterWindowsL(SSI_Type *pSsi, uint32_t u32Value)
{
pSsi->GCWLR = (u32Value & SSI_GCWLR_WIN_L_MASK);
}
/**
* @brief Set the High Part of the Global Counter Window Register (GCWHR)
*
* This function sets the High part of the Global Counter Window Register (GCWHR) for the specified
* SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u32Value The value to set in the High part of the GCWHR register
*/
LOCAL_INLINE void SSI_HWA_SetGlobalCounterWindowsH(SSI_Type *pSsi, uint32_t u32Value)
{
pSsi->GCWHR = (u32Value & SSI_GCWHR_WIN_H_MASK);
}
/**
* @brief Set the Global Protocol Configuration Register (GPCR)
*
* This function sets the Global Protocol Configuration Register (GPCR) for the specified SSI
* peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u32Value The value to set in the GPCR register
*/
LOCAL_INLINE void SSI_HWA_SetGlobalProCfg(SSI_Type *pSsi, uint32_t u32Value)
{
pSsi->GPCR = u32Value;
}
/**
* @brief Set the AK Interrupt Error Threshold Configuration
*
* This function sets the AK Interrupt Error Threshold configuration in the Global Protocol
* Configuration Register (GPCR) for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u32Value The value to set for the AK Interrupt Error Threshold
*/
LOCAL_INLINE void SSI_HWA_SetAKIntErrThrCfg(SSI_Type *pSsi, uint32_t u32Value)
{
pSsi->GPCR = (pSsi->GPCR &= ~SSI_GPCR_AK_IETH_MASK) | SSI_GPCR_AK_IETH(u32Value);
}
/**
* @brief Set the AK Period Error Threshold Configuration
*
* This function sets the AK Period Error Threshold configuration in the Global Protocol
* Configuration Register (GPCR) for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u32Value The value to set for the AK Period Error Threshold
*/
LOCAL_INLINE void SSI_HWA_SetAKPerErrThrCfg(SSI_Type *pSsi, uint32_t u32Value)
{
pSsi->GPCR = (pSsi->GPCR &= ~SSI_GPCR_AK_PETH_MASK) | SSI_GPCR_AK_PETH(u32Value);
}
/**
* @brief Set the PWM Period Error Threshold Configuration
*
* This function sets the PWM Period Error Threshold configuration in the Global Protocol
* Configuration Register (GPCR) for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u32Value The value to set for the PWM Period Error Threshold
*/
LOCAL_INLINE void SSI_HWA_SetPwmPerErrThrCfg(SSI_Type *pSsi, uint32_t u32Value)
{
pSsi->GPCR = (pSsi->GPCR &= ~SSI_GPCR_PWM_PETH_MASK) | SSI_GPCR_PWM_PETH(u32Value);
}
/**
* @brief Set the PWM Reference Pulse Width
*
* This function sets the PWM Reference Pulse Width configuration in the Global Protocol
* Configuration Register (GPCR) for the specified SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u32Value The value to set for the PWM Reference Pulse Width
*/
LOCAL_INLINE void SSI_HWA_SetPwmRefPulseWidth(SSI_Type *pSsi, uint32_t u32Value)
{
pSsi->GPCR = (pSsi->GPCR &= ~SSI_GPCR_REF_WIDTH_MASK) | SSI_GPCR_REF_WIDTH(u32Value);
}
/**
* @brief Set the Sub-instance Control Register
*
* This function sets the Sub-instance Control Register (ICR) for a specified sub-instance index
* in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to configure
* @param u32Value The value to set for the Sub-instance Control Register
*/
LOCAL_INLINE void SSI_HWA_SetSubinsCtr(SSI_Type *pSsi, uint8_t u8IcrIdx, uint32_t u32Value)
{
pSsi->SUB_INS[u8IcrIdx].ICR = u32Value;
}
/**
* @brief Enable the Sub-instance
*
* This function enables the sub-instance by setting the enable bit in the Sub-instance Control
* Register (ICR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to enable
*/
LOCAL_INLINE void SSI_HWA_Subins_Enable(SSI_Type *pSsi, uint8_t u8IcrIdx)
{
pSsi->SUB_INS[u8IcrIdx].ICR |= SSI_ICR_SSI_EN_MASK;
}
/**
* @brief Disable the Sub-instance
*
* This function Disable the sub-instance by setting the enable bit in the Sub-instance Control
* Register (ICR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to enable
*/
LOCAL_INLINE void SSI_HWA_Subins_Disable(SSI_Type *pSsi, uint8_t u8IcrIdx)
{
pSsi->SUB_INS[u8IcrIdx].ICR &= ~SSI_ICR_SSI_EN_MASK;
}
/**
* @brief Set the Sub-instance Channel Switch
*
* This function sets the channel switch configuration in the Sub-instance Control Register (ICR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to configure
* @param u32Value The value to set for the channel switch configuration
*/
LOCAL_INLINE void SSI_HWA_SetSubinsChlSwitch(SSI_Type *pSsi, uint8_t u8IcrIdx, uint32_t u32Value)
{
uint32_t u32RegVal = pSsi->SUB_INS[u8IcrIdx].ICR;
pSsi->SUB_INS[u8IcrIdx].ICR = (u32RegVal & ~SSI_ICR_CHL_SW_MASK) | SSI_ICR_CHL_SW(u32Value);
}
/**
* @brief Enable Window Range Check for Sub-instance
*
* This function enables the window range check feature in the Sub-instance Control Register (ICR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsWinRangChk_Enable(SSI_Type *pSsi, uint8_t u8IcrIdx)
{
pSsi->SUB_INS[u8IcrIdx].ICR |= SSI_ICR_RANG_CHK_EN_MASK;
}
/**
* @brief Disable Window Range Check for Sub-instance
*
* This function Disable the window range check feature in the Sub-instance Control Register (ICR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsWinRangChk_Disable(SSI_Type *pSsi, uint8_t u8IcrIdx)
{
pSsi->SUB_INS[u8IcrIdx].ICR &= ~SSI_ICR_RANG_CHK_EN_MASK;
}
/**
* @brief Set the Sub-instance Channel Selection
*
* This function sets the channel selection configuration in the Sub-instance Control Register (ICR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to configure
* @param u32Value The value to set for the channel selection configuration
*/
LOCAL_INLINE void SSI_HWA_SetSubinsChlSel(SSI_Type *pSsi, uint8_t u8IcrIdx, uint8_t u8Value)
{
uint32_t u32RegVal = pSsi->SUB_INS[u8IcrIdx].ICR;
pSsi->SUB_INS[u8IcrIdx].ICR = (u32RegVal & ~SSI_ICR_CHL_SEL_MASK) | SSI_ICR_CHL_SEL(u8Value);
}
/**
* @brief Set the Sub-instance Protocol Selection
*
* This function sets the Protocol selection configuration in the Sub-instance Control Register
* (ICR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to configure
* @param u32Value The value to set for the Protocol selection configuration
*/
LOCAL_INLINE void SSI_HWA_SetSubinsProtSel(SSI_Type *pSsi, uint8_t u8IcrIdx, uint32_t u32Value)
{
uint32_t u32RegVal = pSsi->SUB_INS[u8IcrIdx].ICR;
pSsi->SUB_INS[u8IcrIdx].ICR = (u32RegVal & ~SSI_ICR_PROT_SEL_MASK) | SSI_ICR_PROT_SEL(u32Value);
}
/**
* @brief Get the Sub-instance Protocol Selection
*
* This function Gets the Protocol selection configuration in the Sub-instance Control Register
* (ICR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to configure
* @return The value of the Sub-instance Protocol Selection
*/
LOCAL_INLINE uint32_t SSI_HWA_GetSubinsProtSel(SSI_Type *pSsi, uint8_t u8IcrIdx)
{
return ((pSsi->SUB_INS[u8IcrIdx].ICR & SSI_ICR_PROT_SEL_MASK) >> SSI_ICR_PROT_SEL_SHIFT);
}
#if SSI_INTERNAL_CMP_SUPPORT == STD_ON
/**
* @brief Enable internal cmp for Sub-instance
*
* This function enables the internal cmp in the Sub-instance Control Register (ICR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsIntCmp_Enable(SSI_Type *pSsi, uint8_t u8IcrIdx)
{
pSsi->SUB_INS[u8IcrIdx].ICR |= SSI_ICR_CMP_EN_MASK;
}
/**
* @brief Disable internal cmp for Sub-instance
*
* This function Disable the internal cmp in the Sub-instance Control Register (ICR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsIntCmp_Disable(SSI_Type *pSsi, uint8_t u8IcrIdx)
{
pSsi->SUB_INS[u8IcrIdx].ICR &= ~SSI_ICR_CMP_EN_MASK;
}
/**
* @brief Set the Sub-instance Resistance Select
*
* This function sets resistance select configuration in the Sub-instance Control Register (ICR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to configure
* @param u32Value The value to set for the resource selection configuration
*/
LOCAL_INLINE void SSI_HWA_SetSubinsResSel(SSI_Type *pSsi, uint8_t u8IcrIdx, uint32_t u32Value)
{
uint32_t u32RegVal = pSsi->SUB_INS[u8IcrIdx].ICR;
pSsi->SUB_INS[u8IcrIdx].ICR = (u32RegVal & ~SSI_ICR_RES_SEL_MASK) | SSI_ICR_RES_SEL(u32Value);
}
#endif
/**
* @brief Set the Sub-instance GPWM Polarity
*
* This function sets the GPWM polarity configuration in the Sub-instance Control Register (ICR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to configure
* @param u32Value The value to set for the GPWM polarity configuration
*/
LOCAL_INLINE void SSI_HWA_SetSubinsGpwmPola(SSI_Type *pSsi, uint8_t u8IcrIdx, uint32_t u32Value)
{
uint32_t u32RegVal = pSsi->SUB_INS[u8IcrIdx].ICR;
pSsi->SUB_INS[u8IcrIdx].ICR = (u32RegVal & ~SSI_ICR_GPWM_INV_MASK) | SSI_ICR_GPWM_INV(u32Value);
}
/**
* @brief Set the Sub-instance GPWM Time Counter
*
* This function sets the GPWM time counter configuration in the Sub-instance Control Register (ICR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IcrIdx The index of the sub-instance control register to configure
* @param u32Value The value to set for the GPWM time counter configuration
*/
LOCAL_INLINE void SSI_HWA_SetSubinsGpwmTimeCnt(SSI_Type *pSsi, uint8_t u8IcrIdx, uint32_t u32Value)
{
uint32_t u32RegVal = pSsi->SUB_INS[u8IcrIdx].ICR;
pSsi->SUB_INS[u8IcrIdx].ICR = (u32RegVal & ~SSI_ICR_GPWM_TOC_MASK) | SSI_ICR_GPWM_TOC(u32Value);
}
/**
* @brief Enable the Sub-instance Filter
*
* This function enables the filter in the Sub-instance Filter Register (IFR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IfrIdx The index of the sub-instance filter register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsFilter_Enable(SSI_Type *pSsi, uint8_t u8IfrIdx)
{
pSsi->SUB_INS[u8IfrIdx].IFR |= SSI_IFR_FLT_EN_MASK;
}
/**
* @brief Disable the Sub-instance Filter
*
* This function disable the filter in the Sub-instance Filter Register (IFR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IfrIdx The index of the sub-instance filter register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsFilter_Disable(SSI_Type *pSsi, uint8_t u8IfrIdx)
{
pSsi->SUB_INS[u8IfrIdx].IFR &= ~SSI_IFR_FLT_EN_MASK;
}
/**
* @brief Set the Sub-instance Filter Width
*
* This function sets the filter width configuration in the Sub-instance Filter Register (IFR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IfrIdx The index of the sub-instance filter register to configure
* @param u32Value The value to set for the filter width configuration
*/
LOCAL_INLINE void SSI_HWA_SetSubinsFilterWidth(SSI_Type *pSsi, uint8_t u8IfrIdx, uint32_t u32Value)
{
uint32_t u32RegVal = pSsi->SUB_INS[u8IfrIdx].IFR;
pSsi->SUB_INS[u8IfrIdx].IFR = (u32RegVal & ~SSI_IFR_FLT_WIDTH_MASK) |
SSI_IFR_FLT_WIDTH(u32Value);
}
/**
* @brief Set the Sub-instance Interrupt Configuration
*
* This function sets the interrupt configuration in the Sub-instance Interrupt Control Register
* (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
* @param u32Value The value to set for the interrupt configuration
*/
LOCAL_INLINE void SSI_HWA_SetSubinsIntCfg(SSI_Type *pSsi, uint8_t u8IntcrIdx, uint32_t u32Value)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR = u32Value;
}
/**
* @brief Set the Sub-instance Interrupt Configuration
*
* This function sets the interrupt configuration in the Sub-instance Interrupt Control Register
* (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
* @param u32Value The value to set for the interrupt configuration
*/
LOCAL_INLINE void SSI_HWA_SubinsErrInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR |= 0xDE;
}
/**
* @brief Enable Valid Interrupt in Sub-instance
*
* This function enables the valid interrupt in the Sub-instance Interrupt Control Register (INTCR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsValidInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_VLD_INT_EN_MASK;
}
/**
* @brief Disable Valid Interrupt in Sub-instance
*
* This function disables the valid interrupt in the Sub-instance Interrupt Control Register (INTCR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsValidInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_VLD_INT_EN_MASK;
}
/**
* @brief Enable Stop Interrupt in Sub-instance
*
* This function enables the Stop interrupt in the Sub-instance Interrupt Control Register (INTCR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsStopInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_STOP_INT_EN_MASK;
}
/**
* @brief Disable Stop Interrupt in Sub-instance
*
* This function disables the Stop interrupt in the Sub-instance Interrupt Control Register (INTCR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsStopInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_STOP_INT_EN_MASK;
}
/**
* @brief Enable Timeout Interrupt in Sub-instance
*
* This function enables the timeout interrupt in the Sub-instance Interrupt Control Register
* (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsFTimeoutInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_TIMEOUT_INT_EN_MASK;
}
/**
* @brief Disable Timeout Interrupt in Sub-instance
*
* This function disables the timeout interrupt in the Sub-instance Interrupt Control Register
* (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsFTimeoutInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_TIMEOUT_INT_EN_MASK;
}
/**
* @brief Enable Range Error Interrupt in Sub-instance
*
* This function enables the Range Error interrupt in the Sub-instance Interrupt Control Register
* (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsRangeErrInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_RANGE_ERR_EN_MASK;
}
/**
* @brief Disable Range Error Interrupt in Sub-instance
*
* This function disables the Range Error interrupt in the Sub-instance Interrupt Control Register
* (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsRangeErrInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_RANGE_ERR_EN_MASK;
}
/**
* @brief Enable Decode Error Interrupt in Sub-instance
*
* This function enables the Decode Error interrupt in the Sub-instance Interrupt Control Register
* (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsDecodeErrInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_DECODE_ERR_EN_MASK;
}
/**
* @brief Disable Decode Error Interrupt in Sub-instance
*
* This function disables the Decode Error interrupt in the Sub-instance Interrupt Control Register
* (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsDecodeErrInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_DECODE_ERR_EN_MASK;
}
/**
* @brief Enable Interval Error Interrupt in Sub-instance
*
* This function enables the Interval Error interrupt in the Sub-instance Interrupt Control Register
* (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsIntervalErrInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_INTERVAL_ERR_EN_MASK;
}
/**
* @brief Disable Interval Error Interrupt in Sub-instance
*
* This function disables the Interval Error interrupt in the Sub-instance Interrupt Control
* Register (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsIntervalErrInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_INTERVAL_ERR_EN_MASK;
}
/**
* @brief Enable Pulse Width Error Interrupt in Sub-instance
*
* This function enables the Pulse Width Error interrupt in the Sub-instance Interrupt Control
* Register (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsPulseWidthErrInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_PULSE_WIDTH_ERR_EN_MASK;
}
/**
* @brief Disable Pulse Width Error Interrupt in Sub-instance
*
* This function disables the Pulse Width Error interrupt in the Sub-instance Interrupt Control
* Register (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsPulseWidthErrInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_PULSE_WIDTH_ERR_EN_MASK;
}
/**
* @brief Enable Protocol Error Interrupt in Sub-instance
*
* This function enables the Protocol Error interrupt in the Sub-instance Interrupt Control Register
* (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsProtErrInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_PROTOC_ERR_INT_EN_MASK;
}
/**
* @brief Disable Protocol Error Interrupt in Sub-instance
*
* This function disables the Protocol Error interrupt in the Sub-instance Interrupt Control
* Register (INTCR) for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8IntcrIdx The index of the sub-instance interrupt control register to configure
*/
LOCAL_INLINE void SSI_HWA_SubinsProtErrInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx)
{
pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_PROTOC_ERR_INT_EN_MASK;
}
/**
* @brief Get Sensor Protocol Counter Value
*
* This function retrieves the counter value from the Sensor Protocol Control Register (SPCR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8SpcrIdx The index of the sensor protocol control register to read
* @return The counter value from the specified sensor protocol control register
*/
LOCAL_INLINE uint32_t SSI_HWA_GetSensorProtocolCnt(SSI_Type *pSsi, uint8_t u8SpcrIdx)
{
return (pSsi->SUB_INS[u8SpcrIdx].SPCR & SSI_SPCR_CNT_MASK);
}
/**
* @brief Get High Pulse Counter Value
*
* This function retrieves the high pulse counter value from the High Pulse Control Register (HPCR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8HpcrIdx The index of the high pulse control register to read
* @return The high pulse counter value from the specified high pulse control register
*/
LOCAL_INLINE uint32_t SSI_HWA_GetHighPulseCnt(SSI_Type *pSsi, uint8_t u8HpcrIdx)
{
return (pSsi->SUB_INS[u8HpcrIdx].HPCR & SSI_HPCR_HPULSE_MASK);
}
/**
* @brief Get AK Manchester Code Value
*
* This function retrieves the AK man Manchester value from the AK Protocol Register (AKPR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8AkprIdx The index of the AK Protocol register to read
* @return The AK Manchester code value from the specified AK Protocol register
*/
LOCAL_INLINE uint32_t SSI_HWA_GetAkMancodeVal(SSI_Type *pSsi, uint8_t u8AkprIdx)
{
return (pSsi->SUB_INS[u8AkprIdx].AKPR & SSI_AKPR_MCODE_MASK);
}
/**
* @brief Get AK Manchester Decode Counter Value
*
* This function retrieves the AK Manchester decode counter value from the AK Protocol Register
* (AKPR) for a specified sub-instance index in the SSI peripheral. The counter value is extracted
* and right-shifted by the appropriate number of bits to align it correctly.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8AkprIdx The index of the AK Protocol register to read
* @return The AK Manchester decode counter value from the specified AK Protocol register
*/
LOCAL_INLINE uint32_t SSI_HWA_GetAkManDecodeCnt(SSI_Type *pSsi, uint8_t u8AkprIdx)
{
return ((pSsi->SUB_INS[u8AkprIdx].AKPR & SSI_AKPR_MCODE_CNT_MASK) >> SSI_AKPR_MCODE_CNT_SHIFT);
}
/**
* @brief Get PWM Decode Value
*
* This function retrieves the PWM decode value from the PWM Protocol Register (PWMPR)
* for a specified sub-instance index in the SSI peripheral.
*
* @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance
* @param u8PwmprIdx The index of the PWM Protocol register to read
* @return The PWM decode value from the specified PWM Protocol register
*/
LOCAL_INLINE uint32_t SSI_HWA_GetPwmDecodeVal(SSI_Type *pSsi, uint8_t u8PwmprIdx)
{
return (pSsi->SUB_INS[u8PwmprIdx].PWMPR & SSI_PWMPR_PCODE_MASK);
}
/**
* @brief Unlock the MB_INTn registers
*
* @param u8CoreIndex the index of the core
* @param u32Mask the unlock bits
*/
LOCAL_INLINE uint32_t SSI_HWA_GetStatusVal(SSI_Type *pSsi, uint8_t u8IsrIdx)
{
uint32 u32Status = SSI_ISR_PROTOC_ERR(1) | SSI_ISR_PULSE_WIDTH_ERR(1) | SSI_ISR_INTERVAL_ERR(1) |
SSI_ISR_DECODE_ERR(1) | SSI_ISR_SPC_RANGE_ERR(1) | SSI_ISR_SPC_TIMEOUT_ERR(1) |
SSI_ISR_WHL_STOP(1) | SSI_ISR_SPC_VLD(1);
return (pSsi->SUB_INS[u8IsrIdx].ISR & u32Status);
}
/**
* @brief Unlock the MB_INTn registers
*
* @param u8CoreIndex the index of the core
* @param u32Mask the unlock bits
*/
LOCAL_INLINE uint32_t SSI_HWA_GetIntCmpStatus(SSI_Type *pSsi, uint8_t u8IsrIdx)
{
return ((pSsi->SUB_INS[u8IsrIdx].ISR & SSI_ISR_CMP_IOK_MASK) >> SSI_ISR_CMP_IOK_SHIFT);
}
/**
* @brief Unlock the MB_INTn registers
*
* @param u8CoreIndex the index of the core
* @param u32Mask the unlock bits
*/
LOCAL_INLINE void SSI_HWA_ClearSubStatus(SSI_Type *pSsi, uint8_t u8IsrIdx)
{
uint32 u32Val = SSI_ISR_PROTOC_ERR(1) | SSI_ISR_PULSE_WIDTH_ERR(1) | SSI_ISR_INTERVAL_ERR(1) |
SSI_ISR_DECODE_ERR(1) | SSI_ISR_SPC_RANGE_ERR(1) | SSI_ISR_SPC_TIMEOUT_ERR(1) |
SSI_ISR_WHL_STOP(1) | SSI_ISR_SPC_VLD(1);
pSsi->SUB_INS[u8IsrIdx].ISR |= u32Val;
}
/**
* @brief Unlock the MB_INTn registers
*
* @param u8CoreIndex the index of the core
* @param u32Mask the unlock bits
*/
LOCAL_INLINE void SSI_HWA_ClearSpcVldStatus(SSI_Type *pSsi, uint8_t u8IsrIdx)
{
pSsi->SUB_INS[u8IsrIdx].ISR = SSI_ISR_SPC_VLD(1);
}
#endif /* #if SSI_INSTANCE_COUNT > 0U */
#endif

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/**
* @file HwA_stcu.h
* @author Flagchip
* @brief Safety Test and Control Unit
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip038 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip038 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_STCU_H_
#define _HWA_STCU_H_
#include "device_header.h"
#if STCU_INSTANCE_COUNT > 0U
/**
* \brief Get Self Test Status
*
* \return Status, maybe more than one status, refer to "STCU_SelfTestStatusType"
*/
LOCAL_INLINE uint32_t STCU_HWA_GetSelfTestStatus(void)
{
return STCU->SELF_TEST_STATUS;
}
/**
* \brief Clear all Self Test Status
*/
LOCAL_INLINE void STCU_HWA_ClearSelfTestStatus(void)
{
STCU->SELF_TEST_STATUS = 0x0UL;
}
/**
* \brief Mbist select for self-test
*
* \param u32MbistSel maybe more than one
*/
LOCAL_INLINE void STCU_HWA_MbistSelect(uint32_t u32MbistSel)
{
STCU->MBIST_SEL = u32MbistSel;
}
/**
* \brief Get Mbist Done Flag
*
* \return All Mbist Done flags, refer to "STCU_MbistDoneType"
*/
LOCAL_INLINE uint32_t STCU_GetMbistDone(void)
{
return STCU->MBIST_DONE_STATUS;
}
/**
* \brief Get Mbist Fail Flag
*
* \return All Mbist Fail flags "STCU_MbistFailedType"
*/
LOCAL_INLINE uint32_t STCU_GetMbistFail(void)
{
return STCU->MBIST_FAIL_STATUS;
}
/**
* \brief Check Lbist execution failed status
*
* \return LBIST status, refer to "STCU_LbistStatusType"
*/
LOCAL_INLINE uint32_t STCU_HWA_CheckLbistStatus(void)
{
return STCU->LBIST_STATUS;
}
/**
* \brief Get STCU Hardware Ram Initial Status
*
* \return Initial Status, refer to "STCU_HardwareInitRamStatusType"
*/
LOCAL_INLINE uint32_t STCU_HWA_GetHardwareRamInitStatus(void)
{
return STCU->SRAM_INI_STATUS;
}
/**
* \brief STCU RAM Init Mode set, can select more than one, for example: STCU_INIT_RAM_TYPE_SRAM0 | STCU_INIT_RAM_TYPE_SRAM1
*
* \param u32InitRamType Init Mode
*/
LOCAL_INLINE void STCU_HWA_SetRamInitType(uint32_t u32InitRamType)
{
STCU->SRAM_INI_SEL = u32InitRamType;
}
/**
* \brief Set STCU Interrupt
*
* \param bIntEn Normal interrupt enable
* \param bSequenceErrorIntEn Sequence error interrupt enable
* \param bSizeErrorIntEn Size error interrupt enable
*/
LOCAL_INLINE void STCU_HWA_SetInterrupt(uint8_t bIntEn, uint8_t bSequenceErrorIntEn, uint8_t bSizeErrorIntEn)
{
STCU->IRQ = STCU_IRQ_EN(bIntEn) | STCU_IRQ_SEQ_ERR(bSequenceErrorIntEn) | STCU_IRQ_SIZE_ERR(bSizeErrorIntEn);
}
/**
* \brief STCU Ram Initial Start
*
* \param eInitRamMode Initial mode
* \param bEnable Enable Initial
* \param bLock Lock after initial
*/
LOCAL_INLINE void STCU_HWA_StartRamInit(uint8_t eInitRamMode, uint8_t bLock)
{
STCU->SRAM_INI_CTRL = STCU_SRAM_INI_CTRL_MODE(eInitRamMode) | STCU_SRAM_INI_CTRL_EN_MASK | STCU_SRAM_INI_CTRL_LOCK(bLock) ;
}
/**
* \brief Get Ram Initial Done flag
*
* \return All Done flag, maybe more than one flag, refer to "STCU_InitRamDoneType"
*/
LOCAL_INLINE uint32_t STCU_HWA_GetRamInitDone(void)
{
return STCU->SRAM_INI_DONE_STATUS;
}
/**
* \brief Get Ram Initial status
*
* \return All Done flag, maybe more than one flag, refer to "STCU_HardwareInitRamStatusType"
*/
LOCAL_INLINE uint32_t STCU_HWA_GetRamInitStatus(void)
{
return STCU->SRAM_INI_STATUS;
}
/**
* \brief Set the LBIST pattern amount control value N.
*
* \param u32Amount LBIST pattern amount control value N. (pattern amount = N * 256)
*/
LOCAL_INLINE void STCU_HWA_SetLBISTPatternAmount(uint32_t u32Amount)
{
STCU->LBIST_PAT_CTRL = u32Amount;
}
/**
* \brief Set the MBIST algorithm for SW trigger self-test
*
* \param bFullTest Enable Full test for MBIST.
* \param bSRAMInit Enable SRAM initialization at the end of software trigger self-test.
*/
LOCAL_INLINE void STCU_HWA_SetMBISTSWAlg(bool bFullTest, bool bSRAMInit)
{
STCU->MBIST_ALG = (STCU->MBIST_ALG & ~(STCU_MBIST_ALG_TRIG_ALG_SEL_MASK | STCU_MBIST_ALG_TRIG_INI_EN_MASK)) | \
(STCU_MBIST_ALG_TRIG_ALG_SEL(bFullTest?0X1FU:0x19U) | STCU_MBIST_ALG_TRIG_INI_EN(bSRAMInit?0x1U:0x0U));
}
/**
* \brief Set safety key
*
* \param u32Key Safety Key.
*/
LOCAL_INLINE void STCU_HWA_SetSafetyKey(uint32_t u32Key)
{
STCU->SELF_TEST_KEY = u32Key;
}
/**
* \brief Enable A self-test software trigger.
*/
LOCAL_INLINE void STCU_HWA_SwTriggerA(void)
{
STCU->SELF_TEST_TRIG_A = STCU_SELF_TEST_TRIG_A_MASK;
}
/**
* \brief Enable B self-test software trigger.
*/
LOCAL_INLINE void STCU_HWA_SwTriggerB(void)
{
STCU->SELF_TEST_TRIG_B = STCU_SELF_TEST_TRIG_B_MASK;
}
/**
* \brief Set self test ctrl register
*
* \param u32Reg Register value.
*/
LOCAL_INLINE void STCU_HWA_SetSelfTestCTRL(uint32_t u32Reg)
{
STCU->SELF_TEST_CTRL = u32Reg;
}
/**
* \brief Enable interrupt
*/
LOCAL_INLINE void STCU_HWA_EnableInterrupt(void)
{
STCU->IRQ |= STCU_IRQ_EN_MASK;
}
/**
* \brief Disable interrupt
*/
LOCAL_INLINE void STCU_HWA_DisableInterrupt(void)
{
STCU->IRQ &= ~STCU_IRQ_EN_MASK;
}
/**
* \brief Get STCU interrupt flags
*
* \return Status, maybe more than one status, refer to "STCU_InterruptFlagType"
*/
LOCAL_INLINE uint32_t STCU_HWA_GetInterruptFlag(void)
{
return ((STCU->IRQ) & (STCU_IRQ_SEQ_ERR_MASK | STCU_IRQ_SIZE_ERR_MASK));
}
/**
* \brief Clear STCU interrupt flags
*/
LOCAL_INLINE void STCU_HWA_ClearInterruptFlag(void)
{
STCU->IRQ &= ~(STCU_IRQ_SEQ_ERR_MASK | STCU_IRQ_SIZE_ERR_MASK);
}
/**
* \brief Set STCU LBIST expected misr value
*/
LOCAL_INLINE void STCU_HWA_SetExpectedMisr(uint32_t u32Misr)
{
STCU->LBIST_EXP_MISR = STCU_LBIST_EXP_MISR_MISR(u32Misr);
}
/**
* \brief Get STCU LBIST expected misr value
*/
LOCAL_INLINE uint32_t STCU_HWA_GetExpectedMisr(void)
{
return STCU->LBIST_EXP_MISR;
}
/**
* \brief Get STCU LBIST actual misr value
*/
LOCAL_INLINE uint32_t STCU_HWA_GetActualMisr(void)
{
return STCU->LBIST_ACT_MISR;
}
/** @}*/
#endif /* #if STCU_INSTANCE_COUNT > 0U */
#endif /*#ifndef _HWA_STCU_H_*/

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/**
* @file HwA_tmu.h
* @author Flagchip
* @brief Hardware access layer for TMU
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip074 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip074 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_TMU_H
#define _HWA_TMU_H
#include "device_header.h"
#if TMU_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_tmu HwA_tmu
* @ingroup module_driver_tmu
* @{
*/
/**
* @brief Select the TF_CTRL and TV_CTRL register is lock or not
*
*/
typedef enum
{
TMU_TF_TV_LOCK = 0U, /*!< TF_CTRL and TV_CTRL register is lock*/
TMU_TF_TV_UNLOCK = 1U /*!< TF_CTRL and TV_CTRL register is unlock*/
}TMU_LockType;
/**
* @brief Select the Flag-based temperature sensor hysteresis control
*
*/
typedef enum
{
TMU_TF_HYSOFF_ON = 0U, /*!< Flag-based temperature sensor hysteresis is on*/
TMU_TF_HYSOFF_OFF = 1U /*!< Flag-based temperature sensor hysteresis is off*/
}TMU_HysteresisType;
/**
* @brief Select the Flag-based temperature sensor filter control
*
*/
typedef enum
{
TMU_TF_FILT_BYP_BYPASSED = 0U, /*!< Flag-based temperature sensor filter is bypassed*/
TMU_TF_FILT_BYP_ENABLED = 1U /*!< Flag-based temperature sensor filter is enabled*/
}TMU_bypassType;
/**
* @brief Get the status of whether the temperature sensor register is locked
*
* @param pTmu the base address of the TMU instance
* @return true Temperature register is locked(CTRL)
* @return false Temperature register is unlocked(CTRL)
*/
LOCAL_INLINE TMU_LockType TMU_HWA_GetTemperatureLockStatus(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->UNLOCK & TMU_UNLOCK_UNLOCK_MASK) >> TMU_UNLOCK_UNLOCK_SHIFT;
return (TMU_LockType)u32TmpVal;
}
/**
* @brief Set the status of whether the temperature sensor register is locked or not
*
* @param pTmu the base address of the TMU instance
* @param eLockStatus Select the TF_CTRL and TV_CTRL register is lock or not
*/
LOCAL_INLINE void TMU_HWA_SetTemperatureLockStatus(TMU_Type *const pTmu,TMU_LockType eLockStatus)
{
if((bool)eLockStatus)
{
pTmu->UNLOCK = 0xA5A50000U | TMU_UNLOCK_UNLOCK(eLockStatus);
}else
{
pTmu->UNLOCK = TMU_UNLOCK_UNLOCK(eLockStatus);
}
}
#if !TMU_SUPPORT_TV_ECMP
/**
* @brief Get the Flag-based temperature sensor over 150 Celsius interrupt flag
*
* @param pTmu the base address of the TMU instance
* @return true Temperature over 150 Celsius interrupt is enabled
* @return false Temperature over 150 Celsius interrupt is disabled
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperature150InterruptFlag(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_150F_IE_MASK) >> TMU_TF_CTRL_TF_150F_IE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Flag-based temperature sensor over 150 Celsius interrupt flag
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether to enable the temperature over 150 Celsius interrupt
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperature150InterruptFlag(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_150F_IE_MASK) | TMU_TF_CTRL_TF_150F_IE(bEnable);
}
/**
* @brief Get the Flag-based temperature sensor over 125 Celsius interrupt flag
*
* @param pTmu the base address of the TMU instance
* @return true Temperature over 125 Celsius interrupt is enabled
* @return false Temperature over 125 Celsius interrupt is disabled
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperature125InterruptFlag(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_125F_IE_MASK) >> TMU_TF_CTRL_TF_125F_IE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Flag-based temperature sensor over 125 Celsius interrupt flag
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether to enable the temperature over 125 Celsius interrupt
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperature125InterruptFlag(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_125F_IE_MASK) | TMU_TF_CTRL_TF_125F_IE(bEnable);
}
/**
* @brief Get the Flag-based temperature sensor ready interrupt flag
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor ready interrupt is enabled
* @return false Temperature sensor ready interrupt is disabled
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureReadyInterruptFlag(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_RDYF_IE_MASK) >> TMU_TF_CTRL_TF_RDYF_IE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Flag-based temperature sensor over ready interrupt flag
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether to enable the temperature sensor ready interrupt
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperatureReadyInterruptFlag(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_RDYF_IE_MASK) | TMU_TF_CTRL_TF_RDYF_IE(bEnable);
}
/**
* @brief Get the Flag-based temperature sensor hysteresis control status
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor Hysteresis is off
* @return false Temperature sensor Hysteresis is on
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureHysteresisStatus(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_HYSOFF_MASK) >> TMU_TF_CTRL_TF_HYSOFF_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Flag-based temperature sensor hysteresis control status
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether to off(1)/on(0) the temperature sensor hysteresis
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperatureHysteresisStatus(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_HYSOFF_MASK) | TMU_TF_CTRL_TF_HYSOFF(bEnable);
}
/**
* @brief Get the Flag-based temperature sensor startup counter
*
* @param pTmu the base address of the TMU instance
* @return u32TmpVal count of the startup
*/
LOCAL_INLINE uint8_t TMU_HWA_GetFlagTemperatureCounter(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_START_CNT_MASK) >> TMU_TF_CTRL_TF_START_CNT_SHIFT;
return (uint8_t)u32TmpVal;
}
/**
* @brief Set the Flag-based temperature sensor startup counter
*
* @param pTmu the base address of the TMU instance
* @param u8Counter the startup counter
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperatureCounter(TMU_Type *const pTmu,uint8_t u8Counter)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_START_CNT_MASK) | TMU_TF_CTRL_TF_START_CNT(u8Counter);
}
#ifdef TMU_SUPPORT_STOP
/**
* @brief Configure the stop mode of the Flag-based temperature sensor
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether the Flag-based temperature sensor is run in stop mode
*/
LOCAL_INLINE void TMU_HWA_ConfigFlagTemperatureStopMode(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_STOP_EN_MASK) | TMU_TF_CTRL_TF_STOP_EN(bEnable);
}
#endif
/**
* @brief Get the Flag-based temperature sensor filter bypass control status
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor Filter is enabled
* @return false Temperature sensor Filter is bypassed
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureFilterBypassStatus(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_FILT_BYP_MASK) >> TMU_TF_CTRL_TF_FILT_BYP_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Flag-based temperature sensor filter bypass control status
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether the temperature sensor filter is enabled(1) or bypassed(0)
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperatureFilterBypassStatus(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_FILT_BYP_MASK) | TMU_TF_CTRL_TF_FILT_BYP(bEnable);
}
/**
* @brief Get the Flag-based temperature sensor enable status
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor is on
* @return false Temperature sensor is off
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureEnableStatus(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_EN_MASK) >> TMU_TF_CTRL_TF_EN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Flag-based temperature sensor enable status
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether the temperature sensor is on(1) or off(0)
*/
LOCAL_INLINE void TMU_HWA_SetFlagTemperatureEnableStatus(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_EN_MASK) | TMU_TF_CTRL_TF_EN(bEnable);
}
/**
* @brief Check whether the temperature is over 150 Celsius
*
* @param pTmu the base address of the TMU instance
* @return true the temperature is over 150 Celsius
* @return false the temperature is not over 150 Celsius
*/
LOCAL_INLINE bool TMU_HWA_Get150Status(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TF_STATUS;
u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_150_MASK) >> TMU_TF_STATUS_TF_150_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Check whether the temperature is over 125 Celsius
*
* @param pTmu the base address of the TMU instance
* @return true the temperature is over 125 Celsius
* @return false the temperature is not over 125 Celsius
*/
LOCAL_INLINE bool TMU_HWA_Get125Status(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TF_STATUS;
u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_125_MASK) >> TMU_TF_STATUS_TF_125_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Check whether the flag for temperature over 150 Celsius is set
*
* @param pTmu the base address of the TMU instance
* @return true the temperature has exceeded 150 Celsius since last time W1C
* @return false the temperature has not exceeded 150 Celsius since TF is ready
*/
LOCAL_INLINE bool TMU_HWA_Get150Flag(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TF_STATUS;
u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_150F_MASK) >> TMU_TF_STATUS_TF_150F_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the temperature over 150 Celsius flag
*
* @param pTmu the base address of the TMU instance
*/
LOCAL_INLINE void TMU_HWA_Clear150Flag(TMU_Type *const pTmu)
{
pTmu->TF_STATUS = TMU_TF_STATUS_TF_150F(1U);
}
/**
* @brief Check whether the flag for temperature over 125 Celsius is set
*
* @param pTmu the base address of the TMU instance
* @return true the temperature has exceeded 125 Celsius since last time W1C
* @return false the temperature has not exceeded 125 Celsius since TF is ready
*/
LOCAL_INLINE bool TMU_HWA_Get125Flag(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TF_STATUS;
u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_125F_MASK) >> TMU_TF_STATUS_TF_125F_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the temperature over 125 Celsius flag
*
* @param pTmu the base address of the TMU instance
*/
LOCAL_INLINE void TMU_HWA_Clear125Flag(TMU_Type *const pTmu)
{
pTmu->TF_STATUS = TMU_TF_STATUS_TF_125F(1U);
}
/**
* @brief Check whether the Flag-based temperature sensor is ready
*
* @param pTmu the base address of the TMU instance
* @return true the Flag-based temperature sensor is ready
* @return false the Flag-based temperature sensor is not ready
*/
LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureReady(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TF_STATUS;
u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_RDYF_MASK) >> TMU_TF_STATUS_TF_RDYF_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the Flag-based temperature sensor ready flag
*
* @param pTmu the base address of the TMU instance
*/
LOCAL_INLINE void TMU_HWA_ClearFlagTemperatureReady(TMU_Type *const pTmu)
{
pTmu->TF_STATUS = TMU_TF_STATUS_TF_RDYF(1U);
}
/**
* @brief Get the Vlotage-based temperature sensor ready interrupt flag
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor ready interrupt is enabled
* @return false Temperature sensor ready interrupt is disabled
*/
LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureReadyInterruptFlag(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_RDYF_IE_MASK) >> TMU_TV_CTRL_TV_RDYF_IE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Voltage-based temperature sensor over ready interrupt flag
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether to enable the temperature sensor ready interrupt
*/
LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureReadyInterruptFlag(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_RDYF_IE_MASK) | TMU_TV_CTRL_TV_RDYF_IE(bEnable);
}
/**
* @brief Get the Voltage-based temperature sensor startup counter
*
* @param pTmu the base address of the TMU instance
* @return u32TmpVal count of the startup
*/
LOCAL_INLINE uint8_t TMU_HWA_GetVoltageTemperatureCounter(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_START_CNT_MASK) >> TMU_TV_CTRL_TV_START_CNT_SHIFT;
return (uint8_t)u32TmpVal;
}
/**
* @brief Set the Voltage-based temperature sensor startup counter
*
* @param pTmu the base address of the TMU instance
* @param u8Counter the startup counter
*/
LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureCounter(TMU_Type *const pTmu,uint8_t u8Counter)
{
pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_START_CNT_MASK) | TMU_TV_CTRL_TV_START_CNT(u8Counter);
}
#endif
#if TMU_SUPPORT_TV_ECMP
/**
* @brief Get the Vlotage-based temperature sensor compare flag 1 interrupt enable status
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor compare flag 1 interrupt is enabled
* @return false Temperature sensor compare flag 1 interrupt is disabled
*/
LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureCompare1InterruptEnableStatus(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_CMP1F_IE_MASK) >> TMU_TV_CTRL_TV_CMP1F_IE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get the Vlotage-based temperature sensor compare flag 0 interrupt enable status
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor compare flag 0 interrupt is enabled
* @return false Temperature sensor compare flag 0 interrupt is disabled
*/
LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureCompare0InterruptEnableStatus(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_CMP0F_IE_MASK) >> TMU_TV_CTRL_TV_CMP0F_IE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Voltage-based temperature sensor compare flag 1 interrupt enable status
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether to enable the temperature sensor compare flag 1 interrupt
*/
LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureCompare1InterruptEnableStatus(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_CMP1F_IE_MASK) | TMU_TV_CTRL_TV_CMP1F_IE(bEnable);
}
/**
* @brief Set the Voltage-based temperature sensor compare flag 0 interrupt enable status
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether to enable the temperature sensor compare flag 0 interrupt
*/
LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureCompare0InterruptEnableStatus(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_CMP0F_IE_MASK) | TMU_TV_CTRL_TV_CMP0F_IE(bEnable);
}
#endif
#ifdef TMU_SUPPORT_STOP
/**
* @brief Configure the stop mode of the Voltage-based temperature sensor
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether the Voltage-based temperature sensor is run in stop mode
*/
LOCAL_INLINE void TMU_HWA_ConfigVoltageTemperatureStopMode(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_STOP_EN_MASK) | TMU_TV_CTRL_TV_STOP_EN(bEnable);
}
#endif
/**
* @brief Get the Voltage-based temperature sensor enable status
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor is on
* @return false Temperature sensor is off
*/
LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureEnableStatus(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_EN_MASK) >> TMU_TV_CTRL_TV_EN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set the Voltage-based temperature sensor enable status
*
* @param pTmu the base address of the TMU instance
* @param bEnable whether the temperature sensor is on(1) or off(0)
*/
LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureEnableStatus(TMU_Type *const pTmu,bool bEnable)
{
pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_EN_MASK) | TMU_TV_CTRL_TV_EN(bEnable);
}
/**
* @brief Check whether the Voltage-based temperature sensor is ready
*
* @param pTmu the base address of the TMU instance
* @return true the Voltage-based temperature sensor is ready
* @return false the Voltage-based temperature sensor is not ready
*/
LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureReady(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TV_STATUS;
u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_RDYF_MASK) >> TMU_TV_STATUS_TV_RDYF_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
#if TMU_SUPPORT_TV_ECMP
/**
* @brief Get the Voltage-based temperature sensor compare status 1
*
* @param pTmu the base address of the TMU instance
* @return true the real time status of ADC compare result 1 is assert
* @return false the real time status of ADC compare result 1 is de-assert
*/
LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureCompareStatus1(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TV_STATUS;
u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_CMP1_MASK) >> TMU_TV_STATUS_TV_CMP1_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get the Voltage-based temperature sensor compare status 0
*
* @param pTmu the base address of the TMU instance
* @return true the real time status of ADC compare result 0 is assert
* @return false the real time status of ADC compare result 0 is de-assert
*/
LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureCompareStatus0(TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TV_STATUS;
u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_CMP0_MASK) >> TMU_TV_STATUS_TV_CMP0_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get the Vlotage-based temperature sensor compare flag 1
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor compare flag 1 is asserted
* @return false Temperature sensor compare flag 1 is not asserted
*/
LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureCompareFlag1(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TV_STATUS;
u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_CMP1F_MASK) >> TMU_TV_STATUS_TV_CMP1F_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get the Vlotage-based temperature sensor compare flag 0
*
* @param pTmu the base address of the TMU instance
* @return true Temperature sensor compare flag 0 is asserted
* @return false Temperature sensor compare flag 0 is not asserted
*/
LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureCompareFlag0(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TV_STATUS;
u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_CMP0F_MASK) >> TMU_TV_STATUS_TV_CMP0F_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear the Vlotage-based temperature sensor compare flag 1
*
* @param pTmu the base address of the TMU instance
*/
LOCAL_INLINE void TMU_HWA_ClearVoltageTemperatureCompareFlag1(TMU_Type *const pTmu)
{
pTmu->TV_STATUS = TMU_TV_STATUS_TV_CMP1F(1U);
}
/**
* @brief Clear the Vlotage-based temperature sensor compare flag 0
*
* @param pTmu the base address of the TMU instance
*/
LOCAL_INLINE void TMU_HWA_ClearVoltageTemperatureCompareFlag0(TMU_Type *const pTmu)
{
pTmu->TV_STATUS = TMU_TV_STATUS_TV_CMP0F(1U);
}
#endif
#if !TMU_SUPPORT_TV_ECMP
/**
* @brief Clear the Voltage-based temperature sensor ready flag
*
* @param pTmu the base address of the TMU instance
*/
LOCAL_INLINE void TMU_HWA_ClearVoltageTemperatureReady(TMU_Type *const pTmu)
{
pTmu->TV_STATUS = TMU_TV_STATUS_TV_RDYF(1U);
}
/**
* @brief Get the TMU_TF_CTRL config
*
* @param pTmu the base address of the TMU instance
* @return uint32_t the TMU_TF_CTRL config
*/
LOCAL_INLINE uint32_t TMU_HWA_GetFlagTempCtrl(const TMU_Type *const pTmu)
{
return pTmu->TF_CTRL;
}
/**
* @brief Set the TMU_TF_CTRL config
*
* @param pTmu the base address of the TMU instance
* @param u32Config the TMU_TF_CTRL config
*/
LOCAL_INLINE void TMU_HWA_SetFlagTempCtrl(TMU_Type *const pTmu, uint32_t u32Config)
{
pTmu->TF_CTRL = u32Config;
}
#endif
/**
* @brief Get the TMU_TV_CTRL config
*
* @param pTmu the base address of the TMU instance
* @return uint32_t the TMU_TV_CTRL config
*/
LOCAL_INLINE uint32_t TMU_HWA_GetVoltageTempCtrl(const TMU_Type *const pTmu)
{
return pTmu->TV_CTRL;
}
/**
* @brief Set the TMU_TV_CTRL config
*
* @param pTmu the base address of the TMU instance
* @param u32Config the TMU_TV_CTRL config
*/
LOCAL_INLINE void TMU_HWA_SetVoltageTempCtrl(TMU_Type *const pTmu, uint32_t u32Config)
{
pTmu->TV_CTRL = u32Config;
}
#ifdef TMU_SUPPORT_TRIM
/**
* @brief Get the TV_TRIM_TV_TCODE value
*
* @param pTmu the base address of the TMU instance
* @return uint32_t the TV_TRIM_TV_TCODE value
*/
LOCAL_INLINE uint32_t TMU_HWA_GetTemperatureCode(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TV_TRIM;
u32TmpVal = (u32TmpVal & TMU_TV_TRIM_TV_TCODE_MASK) >> TMU_TV_TRIM_TV_TCODE_SHIFT;
return u32TmpVal;
}
/**
* @brief Get the TV_TRIM_TV_SLOPE value
*
* @param pTmu the base address of the TMU instance
* @return uint32_t the TV_TRIM_TV_SLOPE value
*/
LOCAL_INLINE uint32_t TMU_HWA_GetSlopeFactor(const TMU_Type *const pTmu)
{
uint32_t u32TmpVal = pTmu->TV_TRIM;
u32TmpVal = (u32TmpVal & TMU_TV_TRIM_TV_SLOPE_MASK) >> TMU_TV_TRIM_TV_SLOPE_SHIFT;
return u32TmpVal;
}
#endif
/** @}*/
#endif /* #if TMU_INSTANCE_COUNT > 0U */
#endif /* _HWA_TMU_H_ */

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/**
* @file HwA_tpuh.h
* @author Flagchip
* @brief FC7xxx TPUH hardware access layer
* @version 2.0.0
* @date 2024-1-12
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip084 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_TPUH_H_
#define _HWA_TPUH_H_
#include "device_header.h"
#if TPU_INSTANCE_COUNT > 0U
/********* Local typedef ************/
/** @brief TPU TCR1 clock control mode type */
typedef enum
{
TPUH_CLK_SRC_TCRCLK = 0U,
UTPUH_PDOWN_CNT_MODE = 3U,
TPUH_CLK_SRC_TPUCLKDIV2 = 4U,
TPUH_CLK_SRC_TPUCLK = 5U
} TPUH_TCR1ClkCtrlModeType;
/** @brief TPU angle tick gen clk type */
typedef enum
{
TPUH_TCR1_PRESCAL_OUTPUT = 0U,
TPUH_TCR2_PRESCAL_OUTPUT = 1U
} TPUH_AngleTickGenClkType;
/** @brief TPU Angle Mode Selection type */
typedef enum
{
TPUH_TCR2_TIMEBASE_EAC_DISABLE = 0U,
TPUH_TOOTHSIGNAL_AS_TCRCLK_TOOTH_CH_0 = 1U,
TPUH_TOOTHSIGNAL_AS_CH1INPUT_TOOTH_CH_1 = 2U,
TPUH_TOOTHSIGNAL_AS_CH2INPUT_TOOTH_CH_2 = 3U
} TPUH_AngleModeSel;
/** @brief TPU Angle Mode Selection type */
typedef enum
{
TPUH_TWO_SAMPLE_MODE_TPU_CLK_DIV2 = 0U,
TPUH_TWO_SAMPLE_MODE_CH_CLK = 1U,
TPUH_INTEGRATOR_MODE_TPU_CLK_DIV2 = 2U,
TPUH_INTEGRATOR_MODE_CH_CLK = 3U
} TPUH_TCRClkFilterType;
/** @brief TPU TCR2 clock control mode0 type */
typedef enum
{
TPUH_GATED_DIV8_CLK = 0U,
TPUH_RISE_TRANSITION_INCREMENT_TCR2_PRESCALER = 1U,
TPUH_FALL_TRANSITION_INCREMENT_TCR2_PRESCALER = 2U,
TPUH_DIV8_CLK = 4U,
TPUH_UPDOWN_CNT_MODE = 5U,
TPUH_FROZEN = 7U
} TPUH_TCR1ClkCtrlMode0Type;
typedef enum
{
TPUH_RSING_EDGE = 1U,
TPUH_FALLING_EDGE = 2U,
TPUH_BOTH_EDGES = 3U,
TPUH_NO_EDGE = 6U,
} TPUH_TCR1ClkCtrlMode1Type;
/** @brief Missing Tooth Counter */
typedef enum
{
TPUH_NOT_A_MISSING_TOOTH = 0U,
TPUH_ONE_MISSING_TOOTH = 1U,
TPUH_TWO_MISSING_TOOTH = 2U,
TPUH_THREE_MISSING_TOOTH = 3U,
} TPUH_MissToothCntType;
/** @brief Channel Trigger Configuration */
typedef enum
{
TPUH_DISABLED = 0U,
TPUH_ANY_EVENT_GATED_BY_MSRTSR = 2U,
TPUH_HSA_EVENT_ON_FLEXCORE_MODE = 3U,
TPUH_MRL1_EVENT_NOT_GATED_BY_MSR = 4U,
TPUH_MRL2_EVENT_NOT_GATED_BY_MSR = 5U,
TPUH_MRL1_OR_MRL2_EVENT_NOT_GATED_BY_MSR = 6U,
TPUH_MRL1_AND_MRL2_EVENT_NOT_GATED_BY_MSR = 7U,
TPUH_TDL1_OR_TDL2_EVENT_NOT_GATED_BY_TSR = 8U,
TPUH_TDL1_AND_TDL2_EVENT_NOT_GATED_BY_TSR = 9U,
TPUH_EVENT_EQUAL_TO_CH_DO_LEVEL = 10U,
TPUH_EVENT_NEGATIVE_TO_CH_DO_LEVEL = 11U,
TPUH_EVENT_EQUAL_TO_CH_DO_PART1_LEVEL = 12U,
TPUH_EVENT_EQUAL_TO_CH_DO_PART2_LEVEL = 13U,
TPUH_EVENT_EQUAL_TO_CH_IND_LEVEL = 14U,
TPUH_EVENT_EQUAL_TO_CH_IND_LATCH_LEVEL = 15U,
} TPUH_ChTrigCFGType;
/********* Local inline function ************/
/**
* @brief Get service request status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetSRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VSR & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get pin input status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetInputStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VIR & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get pin output status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetoutputStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VOR & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get pin output enable status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetoutputEnStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VOBR & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get MRL1 status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetMRL1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VM1R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get MRL2 status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetMRL2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VM2R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TDL1 status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetTDL1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VT1R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TDL2 status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetTDL2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VT2R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get MRL1 event status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetMRL1EventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_EM1R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get MRL2 event status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetMRL2EventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_EM2R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TDL1 event status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetTDL1eventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_ET1R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TDL2 event status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetTDL2eventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_ET2R & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get HAS status of specific channel
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetHASStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->GCR_VHSR & (1U << u8Channel)) >> u8Channel;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TCR1 prescaler.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1Prescaler(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR1P_MASK) >> TPU_H_TBR_CR_TCR1P_SHIFT;
return u32TmpVal;
}
/**
* @brief Get TCR1 clock control.
*
*/
LOCAL_INLINE TPUH_TCR1ClkCtrlModeType TPU_H_HWA_GetTCR1ClkControl(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR1CTL_MASK) >> TPU_H_TBR_CR_TCR1CTL_SHIFT;
return (TPUH_TCR1ClkCtrlModeType)u32TmpVal;
}
/**
* @brief Get TCR2 prescaler.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2Prescaler(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2P_MASK) >> TPU_H_TBR_CR_TCR2P_SHIFT;
return u32TmpVal;
}
/**
* @brief Get Angle tick generator clock.
*
*/
LOCAL_INLINE TPUH_AngleTickGenClkType TPU_H_HWA_GetATGC(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_ATGC_MASK) >> TPU_H_TBR_CR_ATGC_SHIFT;
return (TPUH_AngleTickGenClkType)u32TmpVal;
}
/**
* @brief Get Angle Mode Selection.
*
*/
LOCAL_INLINE TPUH_AngleModeSel TPU_H_HWA_GetAM(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_AM_MASK) >> TPU_H_TBR_CR_AM_SHIFT;
return (TPUH_AngleModeSel)u32TmpVal;
}
/**
* @brief Get TCRCLK signal Filter Control.
*
*/
LOCAL_INLINE TPUH_TCRClkFilterType TPU_H_HWA_GetTCRClkFilter(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCRCF_MASK) >> TPU_H_TBR_CR_TCRCF_SHIFT;
return (TPUH_TCRClkFilterType)u32TmpVal;
}
/**
* @brief Get TCR2 clock control.
*
*/
LOCAL_INLINE TPUH_TCR1ClkCtrlMode0Type TPU_H_HWA_GetTCR2ClkControlAM0(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2CTL_MASK) >> TPU_H_TBR_CR_TCR2CTL_SHIFT;
return (TPUH_TCR1ClkCtrlMode0Type)u32TmpVal;
}
/**
* @brief Get TCR2 clock control.
*
*/
LOCAL_INLINE TPUH_TCR1ClkCtrlMode1Type TPU_H_HWA_GetTCR2ClkControlAM1(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2CTL_MASK) >> TPU_H_TBR_CR_TCR2CTL_SHIFT;
return (TPUH_TCR1ClkCtrlMode1Type)u32TmpVal;
}
/**
* @brief Get TCR1 cnt value.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1CntVal(const TPU_H_Type *const pTPUH)
{
return pTPUH->TBR_T1R;
}
/**
* @brief Get TCR2 cnt value.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2CntVal(const TPU_H_Type *const pTPUH)
{
return pTPUH->TBR_T2R;
}
/**
* @brief Get last tooth indication.
*
*/
LOCAL_INLINE bool TPU_H_HWA_NotLastTooth(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_LAST_MASK) >> TPU_H_TBR_TPR_LAST_SHIFT;
return (bool)((u32TmpVal == 0U) ? true : false);
}
/**
* @brief Get missing tooth counter.
*
*/
LOCAL_INLINE TPUH_MissToothCntType TPU_H_HWA_GetMissingTooth(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_MISSCNT_MASK) >> TPU_H_TBR_TPR_MISSCNT_SHIFT;
return (TPUH_MissToothCntType)u32TmpVal;
}
/**
* @brief Get last tooth indication.
*
*/
LOCAL_INLINE bool TPU_H_HWA_NoInsertTooth(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_IPH_MASK) >> TPU_H_TBR_TPR_IPH_SHIFT;
return (bool)((u32TmpVal == 0U) ? true : false);
}
/**
* @brief Get last tooth indication.
*
*/
LOCAL_INLINE bool TPU_H_HWA_NoForceEACHalt(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_HOLD_MASK) >> TPU_H_TBR_TPR_HOLD_SHIFT;
return (bool)((u32TmpVal == 0U) ? true : false);
}
/**
* @brief Get angle ticks number.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetAngleTicksVal(const TPU_H_Type *const pTPUH)
{
return (pTPUH->TBR_TPR & TPU_H_TBR_TPR_TICKS_MASK) >> TPU_H_TBR_TPR_TICKS_SHIFT;
}
/**
* @brief Get the integer part of TCR1 clocks in one Angle tick.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetIntergerPerAngleTick(const TPU_H_Type *const pTPUH)
{
return (pTPUH->TBR_TRR & TPU_H_TBR_TRR_INTEGER_MASK) >> TPU_H_TBR_TRR_INTEGER_SHIFT;
}
/**
* @brief Get the fraction part of TCR1 clocks in one Angle tick.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetFractionPerAngleTick(const TPU_H_Type *const pTPUH)
{
return (pTPUH->TBR_TRR & TPU_H_TBR_TRR_FRACTION_MASK) >> TPU_H_TBR_TRR_FRACTION_SHIFT;
}
/**
* @brief Get TCR1 overflow flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetTCR1Overflow(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_OVF_MASK) >> TPU_H_TBR_T1MR_OVF_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TCR1 IRQ enable flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_TCR1IRQEnable(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_IRQ_EN_MASK) >> TPU_H_TBR_T1MR_IRQ_EN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get the maximum value of TCR1 counter in TCR1 updown mode.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1MaxCnt(const TPU_H_Type *const pTPUH)
{
return (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_MAX_MASK) >> TPU_H_TBR_T1MR_MAX_SHIFT;
}
/**
* @brief Get TCR2 overflow flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_TCR2Overflow(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_OVF_MASK) >> TPU_H_TBR_T2MR_OVF_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get TCR2 IRQ enable flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_TCR2IRQEnable(const TPU_H_Type *const pTPUH)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_IRQ_EN_MASK) >> TPU_H_TBR_T2MR_IRQ_EN_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get the maximum value of TCR2 counter in TCR1 updown mode.
*
*/
LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2MaxCnt(const TPU_H_Type *const pTPUH)
{
return (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_MAX_MASK) >> TPU_H_TBR_T2MR_MAX_SHIFT;
}
/**
* @brief Get channel HSA enable flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChHSAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHAE_MASK) >> TPU_H_CHn_CR_CHAE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set channel HSA enable or disable.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChHSA(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHAE_MASK) | TPU_H_CHn_CR_CHAE(benable));
}
/**
* @brief Set channel event trigger dma enable or disable.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChEventDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CDFD_MASK) | TPU_H_CHn_CR_CDFD(benable));
}
/**
* @brief Set channel request Dma enable or disable.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChReqDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHDE_MASK) | TPU_H_CHn_CR_CHDE(benable));
}
/**
* @brief Get channel HSR Dma request enable flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChDMAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHDE_MASK) >> TPU_H_CHn_CR_CHDE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set channel Sync isr from flexcore enable or disable.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChSyncISR(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHEE_MASK) | TPU_H_CHn_CR_CHEE(benable));
}
/**
* @brief Get channel HSR event as interrupt enable flag.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChHSRISREnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHEE_MASK) >> TPU_H_CHn_CR_CHEE_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get channel trigger configuration.
*
*/
LOCAL_INLINE TPUH_ChTrigCFGType TPU_H_HWA_GetChTrigCondition(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CTC_MASK) >> TPU_H_CHn_CR_CTC_SHIFT;
return (TPUH_ChTrigCFGType)u32TmpVal;
}
/**
* @brief Set channel trigger configuration.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChTrig(TPU_H_Type *const pTPUH, uint8_t u8Channel, TPUH_ChTrigCFGType etrgcfg)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CTC_MASK) | TPU_H_CHn_CR_CTC(etrgcfg));
}
/**
* @brief Get channel trigger DMA enable.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChTrigDMAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CDFD_MASK) >> TPU_H_CHn_CR_CDFD_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Set channel trigger DMA enable.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChTrigDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CDFD_MASK) | TPU_H_CHn_CR_CDFD(benable));
}
/**
* @brief Get channel HSR index.
*
*/
LOCAL_INLINE uint8 TPU_H_HWA_GetChHSRIdx(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHSR_MASK) >> TPU_H_CHn_CR_CHSR_SHIFT;
return (uint8)u32TmpVal;
}
/**
* @brief Get channel HSR index.
*
*/
LOCAL_INLINE void TPU_H_HWA_SetChHSRIdx(TPU_H_Type *const pTPUH, uint8_t u8Channel, uint8_t u8HSRIdx)
{
pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHSR_MASK) | TPU_H_CHn_CR_CHSR(u8HSRIdx));
}
/**
* @brief Get channel event trigger interrupt status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChEventTrigISRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CIS_MASK) >> TPU_H_CHn_SR_CIS_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get channel host service request (HSR) status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChHSRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (uint32_t)((pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHRS_MASK) >> TPU_H_CHn_SR_CHRS_SHIFT);
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get HSA.
*
*/
LOCAL_INLINE uint8 TPU_H_HWA_GetChHSAIdx(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHRI_MASK) >> TPU_H_CHn_SR_CHRI_SHIFT;
return (uint8_t)u32TmpVal;
}
/**
* @brief Get channel event as interrupt status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChDMAReq(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHDS_MASK) >> TPU_H_CHn_SR_CHDS_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get channel trigger status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChTrigStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CTS_MASK) >> TPU_H_CHn_SR_CTS_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get channel host service acknowledge (HSA) interrupt status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChHSAReqStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHAS_MASK) >> TPU_H_CHn_SR_CHAS_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Clear channel interrupt by event.
*
*/
LOCAL_INLINE void TPU_H_HWA_ClearChEventISRFlg(TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CEIC_MASK;
}
/**
* @brief Clear channel HSA.
*
*/
LOCAL_INLINE void TPU_H_HWA_ClearChHSA(TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CHAC_MASK;
}
/**
* @brief Clear channel HSR.
*
*/
LOCAL_INLINE void TPU_H_HWA_ClearChHSR(TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CHRT_MASK;
}
/**
* @brief Get channel service request.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChServiceReq(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_CSR_MASK) >> TPU_H_CHn_EFR_CSR_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get channel service request to HOST.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChServiceReqToHost(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_CHSR_MASK) >> TPU_H_CHn_EFR_CHSR_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get match recognition latch 1 event status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_EMRL1_MASK) >> TPU_H_CHn_EFR_EMRL1_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get match recognition latch 2 event status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_EMRL2_MASK) >> TPU_H_CHn_EFR_EMRL2_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get transition detect latch 1 event status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch1Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_ETDL1_MASK) >> TPU_H_CHn_EFR_ETDL1_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get transition detect latch 2 event status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch2Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_ETDL2_MASK) >> TPU_H_CHn_EFR_ETDL2_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get match recognition latch 1 enable status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1En(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRLE1_MASK) >> TPU_H_CHn_EFR_MRLE1_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get match recognition latch 2 enable status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2En(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRLE2_MASK) >> TPU_H_CHn_EFR_MRLE2_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get match recognition latch 1 enable status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRL1_MASK) >> TPU_H_CHn_EFR_MRL1_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get match recognition latch 2 enable status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRL2_MASK) >> TPU_H_CHn_EFR_MRL2_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get Transition Detect latch 1 enable status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_TDL1_MASK) >> TPU_H_CHn_EFR_TDL1_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
/**
* @brief Get Transition Detect latch 2 enable status.
*
*/
LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel)
{
uint32_t u32TmpVal;
u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_TDL2_MASK) >> TPU_H_CHn_EFR_TDL2_SHIFT;
return (bool)((u32TmpVal != 0U) ? true : false);
}
#endif
#endif /* #ifndef _HWA_TPUH_H_ */

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Inc/HwA_trgsel.h Normal file
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@ -0,0 +1,164 @@
/**
* @file HwA_trgsel.h
* @author flagchip
* @brief Hardware access layer for TrgSel
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip030 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_TRGSEL_H_
#define _HWA_TRGSEL_H_
#include "device_header.h"
#if TRGSEL_INSTANCE_COUNT > 0U
#define TRGSEL_REGSIZE 4U
/**
* @defgroup HwA_trgsel HwA_trgsel
* @ingroup module_driver_trgsel
* @{
*/
/**
* @brief Get the trigger source of the selected trigger target
*
* @param pTrgsel the base address of the TrgSel instance
* @param u32TargetIndex the trigger target to get the trigger source
* @return uint32_t the trigger source of the selected trigger target
*/
LOCAL_INLINE uint32_t TRGSEL_HWA_GetTargetTriggerSource(const TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex)
{
uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE;
uint32_t u32SelIdx = u32TargetIndex % TRGSEL_REGSIZE;
uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx];
switch (u32SelIdx)
{
case 0U:
{
u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_0_MASK) >> TRGSEL_OUT_SEL_SEL_0_SHIFT;
break;
}
case 1U:
{
u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_1_MASK) >> TRGSEL_OUT_SEL_SEL_1_SHIFT;
break;
}
case 2U:
{
u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_2_MASK) >> TRGSEL_OUT_SEL_SEL_2_SHIFT;
break;
}
case 3U:
{
u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_3_MASK) >> TRGSEL_OUT_SEL_SEL_3_SHIFT;
break;
}
default:
break;
}
return (uint32_t)u32Tmp;
}
/**
* @brief Set the trigger source of the selected trigger target
*
* @param pTrgsel the base address of the TrgSel instance
* @param u32TargetIndex the trigger target to set the trigger source
* @param u32SourceIndex the selected trigger source to trig the target
*/
LOCAL_INLINE void TRGSEL_HWA_SetTargetTriggerSource(TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex,
uint32_t u32SourceIndex)
{
uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE;
uint32_t u32SelIdx = u32TargetIndex % TRGSEL_REGSIZE;
uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx];
switch (u32SelIdx)
{
case 0U:
{
u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_0_MASK) | TRGSEL_OUT_SEL_SEL_0(u32SourceIndex);
break;
}
case 1U:
{
u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_1_MASK) | TRGSEL_OUT_SEL_SEL_1(u32SourceIndex);
break;
}
case 2U:
{
u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_2_MASK) | TRGSEL_OUT_SEL_SEL_2(u32SourceIndex);
break;
}
case 3U:
{
u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_3_MASK) | TRGSEL_OUT_SEL_SEL_3(u32SourceIndex);
break;
}
default:
break;
}
pTrgsel->OUT_SEL[u32RegIdx] = u32Tmp;
}
/**
* @brief Get wether the trigger source of the selected target is locked
*
* @param pTrgsel the base address of the TrgSel instance
* @param u32TargetIndex the trigger target to get the lock status
* @return true the trigger source of the selected target cannot be modified
* @return false the trigger source of the selected target can be modified
*/
LOCAL_INLINE bool TRGSEL_HWA_GetTargetLockStatus(const TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex)
{
uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE;
uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx];
u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_LOCK_MASK) >> TRGSEL_OUT_SEL_LOCK_SHIFT;
return (bool)((u32Tmp != 0U) ? true : false);
}
/**
* @brief Lock the trigger source of the selected target
*
* @note The trigger target is grouped by four, so if you lock the trigger source of one target, the
* adjacent three trigger targets in the same register group are also be locked. So please ensure the
* trigger sources are not to be modified before lock the trigger target.
*
* @param pTrgsel the base address of the TrgSel instance
* @param u32TargetIndex the trigger target to lock the trigger source
*/
LOCAL_INLINE void TRGSEL_HWA_LockTargetTriggerSource(TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex)
{
uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE;
pTrgsel->OUT_SEL[u32RegIdx] |= TRGSEL_OUT_SEL_LOCK_MASK;
}
/** @}*/
#endif /* #if TRGSEL_INSTANCE_COUNT > 0U */
#endif /* _HWA_TRGSEL_H_ */

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/**
* @file HwA_tstmp.h
* @author Flagchip
* @brief TSTMP hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip084 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_TSTMP_H_
#define _HWA_TSTMP_H_
#include "device_header.h"
#if TSTMP_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_tstmp HwA_tstmp
* @ingroup module_driver_tstmp
* @{
*/
/********* Local typedef ************/
/** @brief Tstmp modulate number */
typedef enum
{
TSTMP_MODChn0 = 0U,
TSTMP_MODChn1,
TSTMP_MODChn2,
TSTMP_MODChn3
} TSTMP_ModChannelType;
#if (TSTMP_SUPPORT_MODULATE_SUPPOT == STD_ON)
/** @brief TSTMP counter mode
* (available on FC7300F1M_B only)*/
typedef enum
{
TSTMP_MODE_ALWAYS_RUNNING = 0U,
TSTMP_MODE_PERIOD_RUNNING = 1U
} TSTMP_ModeCounterRunningMode;
#endif
/********* Local inline function ************/
/**
* @brief Read TSTMP value
*
* @param pTstmp TSTMP instance
* @return TSTMP value
*/
LOCAL_INLINE uint64_t TSTMP_HWA_ReadTstmpValue(TSTMP_Type *pTstmp)
{
uint32_t u32TstmpL, u32TstmpH;
uint64_t u64TempValue = 0U;
u32TstmpL = pTstmp->VALL;
u32TstmpH = pTstmp->VALH;
u64TempValue = u32TstmpH;
u64TempValue = (u64TempValue << 32) + u32TstmpL;
return u64TempValue;
}
/**
* @brief Read TSTMP interrupt enable bits
*
* @param pTstmp TSTMP instance
* @return TSTMP interrupt enable bits
*/
LOCAL_INLINE uint32_t TSTMP_HWA_ReadTstmpInterruptEnable(TSTMP_Type *pTstmp)
{
return (uint32_t)pTstmp->MOD_INTEN;
}
/**
* @brief Read TSTMP all MOD match flag
*
* @param pTstmp TSTMP instance
* @return TSTMP all MOD match flag
*/
LOCAL_INLINE uint32_t TSTMP_HWA_ReadModMatchFlag(TSTMP_Type *pTstmp)
{
return ((uint32_t)(pTstmp->MOD_STATUS) & (uint32_t)(TSTMP_MOD_STATUS_MOD0_MATCH_MASK | TSTMP_MOD_STATUS_MOD1_MATCH_MASK
| TSTMP_MOD_STATUS_MOD2_MATCH_MASK | TSTMP_MOD_STATUS_MOD3_MATCH_MASK));
}
/**
* @brief Clear TSTMP MOD match flag
*
* @param pTstmp TSTMP instance
*/
LOCAL_INLINE void TSTMP_HWA_ClearModMatchFlag(TSTMP_Type *pTstmp,TSTMP_ModChannelType eMod)
{
pTstmp->MOD_STATUS = ((uint32_t)1U << (uint32_t)eMod);
}
/**
* @brief Set MOD match value
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
* @param u32ModValue MOD value
*/
LOCAL_INLINE void TSTMP_HWA_SetModMatchValue(TSTMP_Type *pTstmp, TSTMP_ModChannelType eMod, uint32_t u32ModValue)
{
switch(eMod)
{
case TSTMP_MODChn0:
pTstmp->MOD0_SETVAL = u32ModValue;
break;
case TSTMP_MODChn1:
pTstmp->MOD1_SETVAL = u32ModValue;
break;
case TSTMP_MODChn2:
pTstmp->MOD2_SETVAL = u32ModValue;
break;
case TSTMP_MODChn3:
pTstmp->MOD3_SETVAL = u32ModValue;
break;
default:
break;
}
}
/**
* @brief Enable TSTMP MOD(n) match interrupt
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
*/
LOCAL_INLINE void TSTMP_HWA_EnableModMatchInterrupt(TSTMP_Type *pTstmp, TSTMP_ModChannelType eMod)
{
pTstmp->MOD_INTEN |= ((uint32_t)1U << (uint32_t)eMod);
}
/**
* @brief Disable TSTMP MOD(n) match interrupt
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
*/
LOCAL_INLINE void TSTMP_HWA_DisableModMatchInterrupt(TSTMP_Type *pTstmp, TSTMP_ModChannelType eMod)
{
pTstmp->MOD_INTEN &= ~((uint32_t)1U << (uint32_t)eMod);
}
#if (TSTMP_SUPPORT_MODULATE_SUPPOT == STD_ON)
/**
* @brief Set the counting modes of TSTMP MOD(n)
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
* @param eCounterMode Counting mode set
*/
LOCAL_INLINE void TSTMP_HWA_SetModCounterMode(TSTMP_Type *pTstmp, TSTMP_ModChannelType eMod, TSTMP_ModeCounterRunningMode eCounterMode)
{
pTstmp->MOD_INTEN = (pTstmp->MOD_INTEN & ~((uint32_t)0x100U << (uint32_t)eMod)) |
(((uint32_t)eCounterMode << 8U) << (uint32_t)eMod);
}
/**
* @brief Enable TSTMP MOD(n) counter
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
*/
LOCAL_INLINE void TSTMP_HWA_EnableModCounter(TSTMP_Type *pTstmp, TSTMP_ModChannelType eMod)
{
pTstmp->MOD_INTEN |= ((uint32_t)0x10000U << (uint32_t)eMod);
}
/**
* @brief Disable TSTMP MOD(n) counter
*
* @param pTstmp TSTMP instance
* @param eMod MOD number
*/
LOCAL_INLINE void TSTMP_HWA_DisableModCounter(TSTMP_Type *pTstmp, TSTMP_ModChannelType eMod)
{
pTstmp->MOD_INTEN &= ~((uint32_t)0x10000U << (uint32_t)eMod);
}
#endif
/** @}*/
#endif /* #if TSTMP_INSTANCE_COUNT > 0U */
#endif /* #ifndef _HWA_TSTMP_H_ */

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/**
* @file HwA_WDOG.h
* @author flagchip
* @brief Wdog hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip031 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip031 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_WDOG_H_
#define _HWA_WDOG_H_
#include "device_header.h"
#if WDOG_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_wdog HwA_wdog
* @ingroup module_driver_wdog
* @{
*/
/********* Local typedef ************/
/********* Local inline function ************/
/********* Wdog Register interface ************/
/**
* @brief Set CS register value, for Wdog working mode configuration.
*
* @param WDOG_Type *pWdog. point to wdog instance base register address.
* @param uint32_t u32Cs. configured register value
*/
LOCAL_INLINE void WDOG_HWA_SetCs(WDOG_Type *pWdog, uint32_t u32Cs)
{
pWdog->CS = u32Cs;
}
/**
* @brief Get CS register value, for WDOG working mode configuration.
* @return uint32_t CS register value.
*/
LOCAL_INLINE uint32_t WDOG_HWA_GetCs(WDOG_Type *pWdog)
{
uint32_t u32Temp = 0U;
u32Temp = pWdog->CS;
return u32Temp;
}
/**
* @brief Clear Wdog interrupt flag.
*
* @param WDOG_Type *pWdog. point to wdog instance base register address.
*/
LOCAL_INLINE void WDOG_HWA_ClearInterruptFlag(WDOG_Type *pWdog)
{
pWdog->CS |= WDOG_CS_FLAG_MASK;
}
/**
* @brief Get WDOG unlock status, if locked, register can't be written.
* @return bool. true as unlocked. false as locked.
*/
LOCAL_INLINE bool WDOG_HWA_GetUnlockStatus(WDOG_Type *pWdog)
{
return (bool)((((uint32_t)pWdog->CS & (uint32_t)WDOG_CS_ULK_STAT_MASK) != 0U) ? true : false);
}
/**
* @brief Set COUNTER register value. for Wdog unlock and refresh usage.
*
* @param pWdog. point to wdog instance base register address.
*
* @param u32Counter. configured register value
*/
LOCAL_INLINE void WDOG_HWA_SetCounter(WDOG_Type *pWdog, uint32_t u32Counter)
{
pWdog->COUNTER = u32Counter;
}
/**
* @brief Set TIMEOUT register value. for WDOG timeout value
*
* @param WDOG_Type *pWdog. point to wdog instance base register address.
*
* @param uint16_t u16Timeout configured register value
*/
LOCAL_INLINE void WDOG_HWA_SetTimeout(WDOG_Type *pWdog, uint16_t u16Timeout)
{
pWdog->TIMEOUT = u16Timeout;
}
/**
* @brief Set WINDOW register value. for windowed WDOG low threshold value.
*
* @param WDOG_Type *pWdog. point to wdog instance base register address.
*
* @param uint16_t u16Window. configured register value
*/
LOCAL_INLINE void WDOG_HWA_SetWindow(WDOG_Type *pWdog, uint16_t u16Window)
{
pWdog->WINDOW = u16Window;
}
#if WDOG_SUPPORT_FASTCFG
/**
* @brief Set Fast Configuration Control.
*
* @param pWdog. point to wdog instance base register address.
*
* @param u32Value. configured register value
*/
LOCAL_INLINE void WDOG_HWA_SetFastCfgState(WDOG_Type *pWdog, uint32_t u32Value)
{
pWdog->FASTCFG = u32Value;
}
/** @}*/ /* HwA_WODG */
#endif
#endif
#endif /* #ifndef _HWA_WDOG_H_ */

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/**
* @file HwA_wku.h
* @author Flagchip
* @brief WKU hardware access layer
* @version 2.0.0
* @date 2024-08-20
*
* SDK Version: 2.6.0
*
* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
*
* @details
*/
/* ********************************************************************************
* Revision History:
*
* Version Date Initials CR# Descriptions
* --------- ---------- ------------ ---------- ---------------
* 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300
* 2.0.0 2024-10-12 Flagchip084 N/A Change version and release
******************************************************************************** */
#ifndef _HWA_WKU_H_
#define _HWA_WKU_H_
#include "device_header.h"
#if WKU_INSTANCE_COUNT > 0U
/**
* @defgroup HwA_wku HwA_wku
* @ingroup module_driver_wku
* @{
*/
/********* Local typedef ************/
#define WKU_MWR0 0x0000100U
#define WKU_MWR1 0x0010000U
#define WKU_MWR2 0x1000000U
/** @brief Wku input */
typedef enum
{
#if (WKU_GPIO_TYPE_0_SUPPORT || WKU_GPIO_TYPE_1_SUPPORT)
WKU_INPUT_FCSPI0 = 0x000040U,
WKU_INPUT_FCUART = 0x000080U,
WKU_INPUT_CMP0 = 0x000400U,
WKU_INPUT_CMP1 = 0x000800U,
WKU_INPUT_TSTMP0 = 0x002000U,
WKU_INPUT_RTC_ALARM = 0x004000U,
WKU_INPUT_RTC_SECONDS = 0x008000U,
WKU_INPUT_FCPIT0 = 0x010000U,
WKU_INPUT_CMU0 = 0x020000U,
WKU_INPUT_AONTIMER = 0x040000U,
WKU_INPUT_GPIOA = 0x080000U,
#if WKU_GPIO_TYPE_0_SUPPORT
WKU_INPUT_GPIOC = 0x100000U,
WKU_INPUT_GPIOE = 0x200000U,
WKU_INPUT_GPIOF = 0x400000U,
WKU_INPUT_GPIOG = 0x800000U,
#else
WKU_INPUT_GPIOC = 0x200000U,
WKU_INPUT_GPIOD = 0x400000U,
WKU_INPUT_GPIOE = 0x800000U,
#endif /* WKU_GPIO_TYPE_0_SUPPORT */
#elif WKU_GPIO_TYPE_2_SUPPORT
WKU_INPUT_GPIOB = 0x000001U,
WKU_INPUT_GPIOD = 0x000002U,
WKU_INPUT_GPIOF = 0x000004U,
WKU_INPUT_GPIOG = 0x000008U,
WKU_INPUT_GPIOH = 0x000010U,
WKU_INPUT_GPIOI = 0x000020U,
#if WKU_GPIO_TYPE_2_ADC2_SUPPORT
WKU_INPUT_ADC1_LPWAKE = 0x000100U,
WKU_INPUT_ADC2_LPWAKE = 0x000200U,
#else
WKU_INPUT_ADC0_LPWAKE = 0x000100U,
WKU_INPUT_ADC1_LPWAKE = 0x000200U,
#endif /* WKU_GPIO_TYPE_2_ADC2_SUPPORT */
#if WKU_GPIO_TYPE_2_CMP0_SUPPORT
WKU_INPUT_CMP0 = 0x000400U,
#endif /* WKU_GPIO_TYPE_2_CMP0_SUPPORT */
WKU_INPUT_TSTMP0 = 0x002000U,
WKU_INPUT_RTC_ALARM = 0x004000U,
WKU_INPUT_RTC_SECONDS = 0x008000U,
WKU_INPUT_AONTIMER0 = 0x040000U,
WKU_INPUT_GPIOA = 0x080000U,
WKU_INPUT_GPIOC = 0x100000U,
WKU_INPUT_GPIOE = 0x200000U,
#else
/* More supoort */
#endif /* (WKU_GPIO_TYPE_0_SUPPORT || WKU_GPIO_TYPE_1_SUPPORT) */
WKU_INPUT_MAX = 0xFFFFFFU
} WKU_WakeupInputType;
/********* Local inline function ************/
/**
* @brief Enable wakeup source
*
* @param eWakeup Wakeup source type
*/
LOCAL_INLINE void WKU_HWA_EnableWakeupSource(const WKU_WakeupInputType eWakeup)
{
if (eWakeup < WKU_MWR0)
{
WKU->MWER0 |= (uint32_t)eWakeup;
}
else if ((eWakeup < WKU_MWR1) && (eWakeup >= WKU_MWR0))
{
WKU->MWER1 |= ((uint32_t)eWakeup >> 8U);
}
else
{
WKU->MWER2 |= ((uint32_t)eWakeup >> 16U);
}
}
/**
* @brief Disable wakeup source
*
* @param eWakeup Wakeup source type
*/
LOCAL_INLINE void WKU_HWA_DisableWakeupSource(const WKU_WakeupInputType eWakeup)
{
if (eWakeup < WKU_MWR0)
{
WKU->MWER0 &= ((~((uint32_t)eWakeup)) & (uint32_t)0xFF);
}
else if ((eWakeup < WKU_MWR1) && (eWakeup >= WKU_MWR0))
{
WKU->MWER1 &= ((~(uint32_t)((uint32_t)eWakeup >> 8U)) & (uint32_t)0xFF);
}
else
{
WKU->MWER2 &= ((~(uint32_t)((uint32_t)eWakeup >> 16U)) & (uint32_t)0xFF);
}
}
/**
* @brief Read WKU wakeup source
*
* @return WKU wakeup source value
*/
LOCAL_INLINE uint32_t WKU_HWA_ReadWakeupSource(void)
{
uint32_t u32WakeupSource = 0U;
u32WakeupSource = (uint32_t)(WKU->MWER0);
u32WakeupSource |= (uint32_t)((uint32_t)(WKU->MWER1) << 8U);
u32WakeupSource |= (uint32_t)((uint32_t)(WKU->MWER2) << 16U);
return u32WakeupSource;
}
#if WKU_GPIO_TYPE_2_SUPPORT
/**
* @brief Get wakeup flag
*
* @param eWakeup
* @return
*/
LOCAL_INLINE bool WKU_HWA_CheckWakeupFlag(const WKU_WakeupInputType eWakeup)
{
uint32_t u32WakeupFlag = 0U;
if (eWakeup < WKU_MWR0)
{
u32WakeupFlag = WKU->MWFR0 & (((uint32_t)eWakeup) & (uint32_t)0xFF);
}
else if ((eWakeup < WKU_MWR1) && (eWakeup >= WKU_MWR0))
{
u32WakeupFlag = WKU->MWFR1 & (((uint32_t)((uint32_t)eWakeup >> 8U)) & (uint32_t)0xFF);
}
else
{
u32WakeupFlag = WKU->MWFR2 & (((uint32_t)((uint32_t)eWakeup >> 16U)) & (uint32_t)0xFF);
}
if (u32WakeupFlag != 0U)
{
return true;
}
else
{
return false;
}
}
/**
* @brief Get all wakeup flag
*
* @param void
* @return
*/
LOCAL_INLINE uint32_t WKU_HWA_GetAllWakeupFlag(void)
{
uint32_t u32WakeupFlag = 0U;
u32WakeupFlag = (uint32_t)(WKU->MWFR0);
u32WakeupFlag |= (uint32_t)((uint32_t)(WKU->MWFR1) << 8U);
u32WakeupFlag |= (uint32_t)((uint32_t)(WKU->MWFR2) << 16U);
return u32WakeupFlag;
}
#endif /* WKU_GPIO_TYPE_2_SUPPORT */
/** @}*/
#endif /* #if WKU_INSTANCE_COUNT > 0U */
#endif /* #ifndef _HWA_WKU_H_ */

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/*
* Hwa_eftu_spe.h
*
* Created on: 2025年12月3日
* Author: qxw0076
*/
#ifndef TEMPLATE_HWA_INCLUDE_HWA_EFTU_SPE_H_
#define TEMPLATE_HWA_INCLUDE_HWA_EFTU_SPE_H_
#include "device_header.h"
#if (EFTU_INSTANCE_COUNT > 0U) && (EFTU_SPE_SUPPORT == STD_ON) && defined(EFTU_SPE_SUPPORT)
typedef enum
{
EFTU_SPE_INSTANCE_0 = 0U,
EFTU_SPE_INSTANCE_1 = 1U,
} EFTU_SPE_InstanceType;
typedef enum
{
EFTU_SPE_UPDATETRIGGER_NIPD = 0U,
EFTU_SPE_UPDATETRIGGER_TOM = 1U,
EFTU_SPE_UPDATETRIGGER_NIPD_DELAY = 2U,
EFTU_SPE_UPDATETRIGGER_TOM_DELAY = 3U,
} EFTU_SPE_UpdateTriggerType;
typedef enum
{
EFTU_SPE_EXUPDATETRIGGER_CH6_CM0 = 0U,
EFTU_SPE_EXUPDATETRIGGER_CH7_CM0 = 1U,
EFTU_SPE_EXUPDATETRIGGER_CH4_CM0 = 2U,
EFTU_SPE_EXUPDATETRIGGER_CH5_CM0 = 3U,
} EFTU_SPE_UpdateExTriggerType;
typedef enum
{
EFTU_SPE_REFTYPE_00 = 0U,
EFTU_SPE_REFTYPE_01 = 1U,
EFTU_SPE_REFTYPE_10 = 2U,
EFTU_SPE_REFTYPE_11 = 3U,
} EFTU_SPE_RefSelectType;
typedef enum
{
EFTU_SPE_OUT_REF_H = 0U,
EFTU_SPE_OUT_REF_L = 1U,
EFTU_SPE_OUT_CONST_0 = 2U,
EFTU_SPE_OUT_CONST_1 = 3U,
} EFTU_SPE_PwmOutSelect;
typedef enum
{
EFTU_SPE_HALL_INPUT_0 = 0u,
EFTU_SPE_HALL_INPUT_1 = 1u,
} EFTU_SPE_HallLevel;
typedef struct
{
EFTU_SPE_HallLevel eHallA_level;
EFTU_SPE_HallLevel eHallB_level;
EFTU_SPE_HallLevel eHallC_level;
uint8 u8SpePtr;
uint8 u8SpePtrBwd;
} EFTU_SPE_HallPattern;
typedef struct
{
EFTU_SPE_PwmOutSelect ePwmoutpattern0;
EFTU_SPE_PwmOutSelect ePwmoutpattern1;
EFTU_SPE_PwmOutSelect ePwmoutpattern2;
EFTU_SPE_PwmOutSelect ePwmoutpattern3;
EFTU_SPE_PwmOutSelect ePwmoutpattern4;
EFTU_SPE_PwmOutSelect ePwmoutpattern5;
} EFTU_SPE_OutPattern;
typedef enum
{
CCM_CLK_RES_0 = 0U,
CCM_CLK_RES_1 = 1U,
CCM_CLK_RES_2 = 2U,
CCM_CLK_RES_3 = 3U,
CCM_CLK_RES_4 = 4U,
CCM_CLK_RES_5 = 5U,
CCM_CLK_RES_6 = 6U,
CCM_CLK_RES_7 = 7U,
} EFTU_SPE_DelayClockSrc;
typedef enum
{
DTM_AUX_IN0 = 0U,
DTM_AUX_IN1 = 1U,
DTM_AUX_IN2 = 2U,
DTM_AUX_IN3 = 3U,
DTM_AUX_IN4 = 4U,
DTM_AUX_IN5 = 5U,
DTM_AUX_IN6 = 6U,
DTM_AUX_IN7 = 7U,
} EFTU_SPE_FastShutSrc;
typedef enum
{
EFTU_SPE_PAT0 = 0U,
EFTU_SPE_PAT1 = 1U,
EFTU_SPE_PAT2 = 2U,
EFTU_SPE_PAT3 = 3U,
EFTU_SPE_PAT4 = 4U,
EFTU_SPE_PAT5 = 5U,
EFTU_SPE_PAT6 = 6U,
EFTU_SPE_PAT7 = 7U,
} EFTU_SPE_OutPatternType;
typedef enum
{
EFTU_SPE_OUT_PAT_PTR = 0U,
EFTU_SPE_OUT_PPAT_PTR_BWD = 1U,
EFTU_SPE_OUT_PAT_6 = 2U,
EFTU_SPE_OUT_PAT_7 = 3U,
} EFTU_SPE_ControlCmd;
LOCAL_INLINE void EFTU_SPE_ConfigPAT(EFTU_SPE_Type *const pSpe, uint32 u32HallPta)
{
pSpe->HALL_IN_PAT = u32HallPta;
}
LOCAL_INLINE void EFTU_SPE_ConfigOutPwm(EFTU_SPE_Type *const pSpe, uint32 u32OutPwm, uint8 u8Channel)
{
pSpe->PWM_OUT_PAT[u8Channel] = u32OutPwm;
}
LOCAL_INLINE void EFTU_SPE_ConfigOutputDirect(EFTU_SPE_Type *const pSpe, uint32 u32Outpattern)
{
pSpe->PWM_OUT_CTRL = u32Outpattern;
}
LOCAL_INLINE void EFTU_SPE_ConfigNewInputIrq(EFTU_SPE_Type *const pSpe, boolean bEnable)
{
if (bEnable == true)
{
pSpe->IRQ_EN |= EFTU_SPE_IRQ_EN_NIPD_EN_MASK;
}
else
{
pSpe->IRQ_EN &= ~EFTU_SPE_IRQ_EN_NIPD_EN_MASK;
}
}
LOCAL_INLINE void EFTU_SPE_ConfigDircIrq(EFTU_SPE_Type *const pSpe, boolean bEnable)
{
if (bEnable == true)
{
pSpe->IRQ_EN |= EFTU_SPE_IRQ_EN_DCHG_EN_MASK;
}
else
{
pSpe->IRQ_EN &= ~EFTU_SPE_IRQ_EN_DCHG_EN_MASK;
}
}
LOCAL_INLINE void EFTU_SPE_ConfigEipdIrq(EFTU_SPE_Type *const pSpe, boolean bEnable)
{
if (bEnable == true)
{
pSpe->IRQ_EN |= EFTU_SPE_IRQ_EN_EIPD_EN_MASK;
}
else
{
pSpe->IRQ_EN &= ~EFTU_SPE_IRQ_EN_EIPD_EN_MASK;
}
}
LOCAL_INLINE void EFTU_SPE_ConfigBieIrq(EFTU_SPE_Type *const pSpe, boolean bEnable)
{
if (bEnable == true)
{
pSpe->IRQ_EN |= EFTU_SPE_IRQ_EN_BIE_EN_MASK;
}
else
{
pSpe->IRQ_EN &= ~EFTU_SPE_IRQ_EN_BIE_EN_MASK;
}
}
LOCAL_INLINE void EFTU_SPE_ConfigRcmpIrq(EFTU_SPE_Type *const pSpe, boolean bEnable)
{
if (bEnable == true)
{
pSpe->IRQ_EN |= EFTU_SPE_IRQ_EN_RCMP_EN_MASK;
}
else
{
pSpe->IRQ_EN &= ~EFTU_SPE_IRQ_EN_RCMP_EN_MASK;
}
}
LOCAL_INLINE uint8 EFTU_SPE_GetIrqFlag(EFTU_SPE_Type *const pSpe)
{
return (uint8)((pSpe->IRQ_ST & EFTU_SPE_IRQ_ST_MASK));
}
LOCAL_INLINE uint8 EFTU_SPE_GetIrqnbleBit(EFTU_SPE_Type *const pSpe)
{
return (uint8)((pSpe->IRQ_EN & EFTU_SPE_IRQ_EN_MASK));
}
LOCAL_INLINE void EFTU_SPE_ClearIrqMask(EFTU_SPE_Type *const pSpe, uint32 u32IrqMask)
{
pSpe->IRQ_ST = u32IrqMask;
}
LOCAL_INLINE void EFTU_SPE_SetCmpcntValue(EFTU_SPE_Type *const pSpe, uint32 u32CmpValue)
{
pSpe->REV_CMP = u32CmpValue;
}
LOCAL_INLINE void EFTU_SPE_SetIputcntValue(EFTU_SPE_Type *const pSpe, uint32 u32RevValue)
{
pSpe->REV_CNT = u32RevValue;
}
LOCAL_INLINE void EFTU_SPE_SoftWareTrigger(EFTU_SPE_Type *const pSpe)
{
pSpe->CMD |= EFTU_SPE_CMD_SW_UPD_TRG_MASK;
}
LOCAL_INLINE void EFTU_SPE_SetCmd(EFTU_SPE_Type *const pSpe, EFTU_SPE_ControlCmd eControlcmd)
{
pSpe->CMD = ((pSpe->CMD & ~EFTU_SPE_CMD_CTRL_CMD_MASK) | (uint32)eControlcmd);
}
LOCAL_INLINE void EFTU_SPE_SetFastshutSrc(EFTU_SPE_Type *const pSpe, EFTU_SPE_FastShutSrc eFastShut)
{
pSpe->CTRL2 = ((pSpe->CTRL2 & ~EFTU_SPE_CTRL2_FSOI_SEL_MASK) | EFTU_SPE_CTRL2_FSOI_SEL(eFastShut));
}
LOCAL_INLINE void EFTU_SPE_SetDelayClkSrc(EFTU_SPE_Type *const pSpe, EFTU_SPE_DelayClockSrc eClockSrc)
{
pSpe->CTRL2 = ((pSpe->CTRL2 & ~EFTU_SPE_CTRL2_DTRG_CLK_SEL_MASK) |
EFTU_SPE_CTRL2_DTRG_CLK_SEL(eClockSrc));
}
LOCAL_INLINE void EFTU_SPE_SetDelaycount(EFTU_SPE_Type *const pSpe, uint8 u8cnt)
{
pSpe->CTRL2 = ((pSpe->CTRL2 & ~EFTU_SPE_CTRL2_DTRG_VAL_MASK) | EFTU_SPE_CTRL2_DTRG_VAL(u8cnt));
}
LOCAL_INLINE void EFTU_SPE_SetPatPtrBwd(EFTU_SPE_Type *const pSpe, EFTU_SPE_OutPatternType ePtrBwd)
{
pSpe->CTRL2 = ((pSpe->CTRL2 & ~EFTU_SPE_CTRL2_PTR_BWD_MASK) | EFTU_SPE_CTRL2_PTR_BWD(ePtrBwd));
}
LOCAL_INLINE void EFTU_SPE_Enable(EFTU_SPE_Type *const pSpe)
{
pSpe->CTRL |= EFTU_SPE_CTRL_EN_MASK;
}
LOCAL_INLINE void EFTU_SPE_Disable(EFTU_SPE_Type *const pSpe)
{
pSpe->CTRL &= ~EFTU_SPE_CTRL_EN_MASK;
}
LOCAL_INLINE void EFTU_SPE_EnableHallInput(EFTU_SPE_Type *const pSpe)
{
pSpe->CTRL |= EFTU_SPE_CTRL_SIE_MASK;
}
LOCAL_INLINE void EFTU_SPE_DisableHallInput(EFTU_SPE_Type *const pSpe)
{
pSpe->CTRL &= ~EFTU_SPE_CTRL_SIE_MASK;
}
LOCAL_INLINE void EFTU_SPE_SetUpdateTrigger(EFTU_SPE_Type *const pSpe,
EFTU_SPE_UpdateTriggerType eUpdateTrigger)
{
pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_TRG_SEL_MASK) | EFTU_SPE_CTRL_TRG_SEL(eUpdateTrigger));
}
LOCAL_INLINE void EFTU_SPE_SetExUpdateTrigger(EFTU_SPE_Type *const pSpe,
EFTU_SPE_UpdateExTriggerType eExUpdateTrigger)
{
pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_TRG_ESEL_MASK) |
EFTU_SPE_CTRL_TRG_ESEL(eExUpdateTrigger));
}
LOCAL_INLINE void EFTU_SPE_SetPatPtr(EFTU_SPE_Type *const pSpe, EFTU_SPE_OutPatternType ePtr)
{
pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_PAT_PTR_MASK) | EFTU_SPE_CTRL_PAT_PTR(ePtr));
}
LOCAL_INLINE void EFTU_SPE_EnableFastShut(EFTU_SPE_Type *const pSpe)
{
pSpe->CTRL |= EFTU_SPE_CTRL_FSOM_MASK;
}
LOCAL_INLINE void EFTU_SPE_DisableFastShut(EFTU_SPE_Type *const pSpe)
{
pSpe->CTRL &= ~EFTU_SPE_CTRL_FSOM_MASK;
}
LOCAL_INLINE void EFTU_SPE_ConfigAip(EFTU_SPE_Type *const pSpe, uint8 u8Aip)
{
pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_AIP_MASK) | EFTU_SPE_CTRL_AIP(u8Aip));
}
LOCAL_INLINE void EFTU_SPE_ConfigPip(EFTU_SPE_Type *const pSpe, uint8 u8Pip)
{
pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_PIP_MASK) | EFTU_SPE_CTRL_PIP(u8Pip));
}
LOCAL_INLINE void EFTU_SPE_ConfigRefSel(EFTU_SPE_Type *const pSpe, EFTU_SPE_RefSelectType eRefSel)
{
pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_PIP_MASK) | EFTU_SPE_CTRL_REF_SEL(eRefSel));
}
LOCAL_INLINE void EFTU_SPE_ConfigShutoffLevel(EFTU_SPE_Type *const pSpe, uint8 u8Shutlevel)
{
pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_FSOL_MASK) | EFTU_SPE_CTRL_FSOL(u8Shutlevel));
}
LOCAL_INLINE uint8 EFTU_SPE_GetNip(EFTU_SPE_Type *const pSpe)
{
return (uint8)((pSpe->CTRL & EFTU_SPE_CTRL_NIP_MASK) >> EFTU_SPE_CTRL_NIP_SHIFT);
}
LOCAL_INLINE uint32 EFTU_SPE_GetHallPattern(EFTU_SPE_Type *const pSpe)
{
return pSpe->HALL_IN_PAT;
}
#endif /* (EFTU_INSTANCE_COUNT > 0U) && (EFTU_SPE_SUPPORT == STD_ON) && defined(EFTU_SPE_SUPPORT)*/
#endif /* TEMPLATE_HWA_INCLUDE_HWA_EFTU_SPE_H_ */

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{
"cmake": {
"inc_dirs": [
"./Inc"
]
}
}