875 lines
20 KiB
C
875 lines
20 KiB
C
/**
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* @file HwA_ospi.h
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* @author Flagchip
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* @brief ospi hardware access layer
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* @version 2.0.0
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* @date 2024-08-20
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*
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* SDK Version: 2.6.0
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*
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* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
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*
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* @details
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2023-12-15 Flagchip087 N/A First version for FC7300
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* 2.0.0 2024-10-12 Flagchip087 N/A Change version and release
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******************************************************************************** */
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#ifndef _HWA_OSPI_H_
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#define _HWA_OSPI_H_
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#include "device_header.h"
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#if OSPI_INSTANCE_COUNT > 0U
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/**
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* @defgroup HwA_ospi HwA_ospi
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* @ingroup module_driver_ospi
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* @{
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*/
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typedef enum
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{
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DQS_INTER_LOOPBACK = 0,
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DQS_PAD_LOOPBACK,
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DQS_EXTERNAL_PADINPUT
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}OSPI_DqsSrcSelType;
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typedef enum
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{
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OSPI_CLOCK_DIV_1 = 0U,
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OSPI_CLOCK_DIV_2 = 1U,
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OSPI_CLOCK_DIV_3 = 2U,
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OSPI_CLOCK_DIV_4 = 3U,
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OSPI_CLOCK_DIV_5 = 4U,
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OSPI_CLOCK_DIV_6 = 5U,
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OSPI_CLOCK_DIV_7 = 6U,
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OSPI_CLOCK_DIV_8 = 7U
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}OSPI_ClockDivideType;
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typedef enum
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{
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OSPI_MUX_PLL0 = 0,
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OSPI_MUX_FIRC,
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OSPI_MUX_PLL1
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}OSPI_ClockMuxType;
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typedef enum
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{
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OSPI_BIG_ENDIAN = 0,
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OSPI_LITTLE_ENDIAN,
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}OSPI_EndianType;
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#define CTRL_RST_VALUE 0x34000
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/********* Local inline function ************/
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#ifdef OSPI_CTRL_SWRST
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/**
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* @brief Generate a software reset of OSPI hardware.
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_SW_Reset(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL |= OSPI_CTRL_SWRST(1);
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pOSPI->CTRL &= ~OSPI_CTRL_SWRST(1);
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}
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#endif
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/**
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* @brief OSPI DIO3 Default High
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_Dio3DefHigh(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL |= OSPI_CTRL_DSDIO3_MASK;
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}
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/**
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* @brief OSPI DIO3 Default Low
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_Dio3DefLow(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL &= ~OSPI_CTRL_DSDIO3_MASK;
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}
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/**
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* @brief OSPI DIO2 Default High
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_Dio2DefHigh(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL |= OSPI_CTRL_DSDIO2_MASK;
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}
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/**
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* @brief OSPI DIO2 Default Low
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_Dio2DefLow(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL &= ~OSPI_CTRL_DSDIO2_MASK;
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}
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/**
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* @brief OSPI Module Enable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_ModuleEnable(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL &= ~OSPI_CTRL_MDIS_MASK;
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}
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/**
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* @brief OSPI Module Disable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_ModuleDisable(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL |= OSPI_CTRL_MDIS_MASK;
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}
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/**
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* @brief OSPI Clear Tx fifo
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_ClearTxFifo(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL |= OSPI_CTRL_CLR_TF_MASK;
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}
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/**
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* @brief OSPI Clear Rx fifo
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_ClearRxFifo(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL |= OSPI_CTRL_CLR_RF_MASK;
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}
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/**
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* @brief OSPI DDR Mode Enable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_DdrModeEnable(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL |= OSPI_CTRL_DDR_EN_MASK;
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}
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/**
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* @brief OSPI DDR Mode Disable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_DdrModeDisable(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL &= ~OSPI_CTRL_DDR_EN_MASK;
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}
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/**
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* @brief OSPI DQS Mode Enable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_DqsModeEnable(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL |= OSPI_CTRL_RWDS_EN_MASK;
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}
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/**
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* @brief OSPI DQS Mode Disable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_DqsModeDisable(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL &= ~OSPI_CTRL_RWDS_EN_MASK;
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}
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/**
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* @brief OSPI DQS Lantency Enable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_DqsLatEnable(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL |= OSPI_CTRL_RWDS_LAT_MASK;
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}
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/**
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* @brief OSPI DQS Lantency Disable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_DqsLatDisable(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL &= ~OSPI_CTRL_RWDS_LAT_MASK;
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}
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/**
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* @brief OSPI DQS Out Enable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_DqsOutEnable(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL |= OSPI_CTRL_RWDS_OUT_MASK;
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}
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/**
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* @brief OSPI DQS Out Disable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_DqsOutDisable(OSPI_Type *pOSPI)
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{
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pOSPI->CTRL &= ~OSPI_CTRL_RWDS_OUT_MASK;
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}
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/**
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* @brief Set OSPI Endian value.
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*
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* @param pOSPI the base address of the OSPI.
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* @param eEndian Endian select value.
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*/
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LOCAL_INLINE void OSPI_HWA_EndianSelect(OSPI_Type *pOSPI,OSPI_EndianType eEndian)
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{
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pOSPI->CTRL &= ~OSPI_CTRL_ENDIAN_MASK;
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pOSPI->CTRL |= OSPI_CTRL_ENDIAN(eEndian);
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}
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/**
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* @brief Set OSPI CTRL value, users should write the whole value to this register.
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*
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* @param pOSPI the base address of the OSPI.
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* @param u32Value the value which will be written to the CTRL register.
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*/
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LOCAL_INLINE void OSPI_HWA_SetCtrlValue(OSPI_Type *pOSPI, uint32_t u32Value)
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{
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pOSPI->CTRL = u32Value;
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}
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/**
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* @brief Read the OSPI CTRL register value for all.
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*
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* @param pOSPI pOSPI the base address of the OSPI.
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* @return OSPI CTRL regsiter value.
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*/
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LOCAL_INLINE uint32_t OSPI_HWA_GetCtrlValue(OSPI_Type *pOSPI)
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{
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return pOSPI->CTRL;
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}
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/**
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* @brief Set CMD ID.
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*
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* @param pOSPI the base address of the OSPI.
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* @param u8Value Pointers of current CMD stored in LUT registers.
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*/
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LOCAL_INLINE void OSPI_HWA_SetCmdId(OSPI_Type *pOSPI, uint16_t u16Value)
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{
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pOSPI->CMDC &= ~OSPI_CMDC_CMD_ID_MASK;
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pOSPI->CMDC |= OSPI_CMDC_CMD_ID(u16Value);
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}
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/**
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* @brief Set CMD SIZE.
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*
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* @param pOSPI the base address of the OSPI.
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* @param u16Value Transfer sizes of current CMD.
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*/
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LOCAL_INLINE void OSPI_HWA_SetCmdSize(OSPI_Type *pOSPI, uint16_t u16Value)
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{
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pOSPI->CMDC &= ~OSPI_CMDC_CMD_SIZE_MASK;
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pOSPI->CMDC |= OSPI_CMDC_CMD_SIZE(u16Value);
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}
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/**
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* @brief Set CMD id and size.
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*
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* @param pOSPI the base address of the OSPI.
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* @param u8SeqId Pointers of current CMD stored in LUT registers.
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* @param u16Size Transfer sizes of current CMD.
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*/
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LOCAL_INLINE void OSPI_HWA_SetCmdIdSize(OSPI_Type *pOSPI,uint8_t u8SeqId,uint16_t u16Size)
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{
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pOSPI->CMDC = OSPI_CMDC_CMD_ID(u8SeqId)|OSPI_CMDC_CMD_SIZE(u16Size);
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}
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/**
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* @brief Read the OSPI CMDC register value for all.
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*
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* @param pOSPI pOSPI the base address of the OSPI.
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* @return OSPI CMDC regsiter value.
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*/
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LOCAL_INLINE uint32_t OSPI_HWA_GetCmdcValue(OSPI_Type *pOSPI)
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{
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return pOSPI->CMDC;
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}
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/**
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* @brief Set Data Hold Time,This bit should only be valid in DDR mode.
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*
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* @param pOSPI the base address of the OSPI.
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* @param u8Value Data Hold Time.
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*/
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LOCAL_INLINE void OSPI_HWA_SetDataHoldTime(OSPI_Type *pOSPI, uint8_t u8Value)
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{
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pOSPI->FLS_CFG &= ~OSPI_FLS_CFG_TDH_MASK;
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pOSPI->FLS_CFG |= OSPI_FLS_CFG_TDH(u8Value);
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}
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/**
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* @brief Set CS Hold Time.
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*
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* @param pOSPI the base address of the OSPI.
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* @param u8Value CS Hold Time.
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*/
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LOCAL_INLINE void OSPI_HWA_SetCsHoldTime(OSPI_Type *pOSPI, uint8_t u8Value)
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{
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pOSPI->FLS_CFG &= ~OSPI_FLS_CFG_TCSH_MASK;
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pOSPI->FLS_CFG |= OSPI_FLS_CFG_TCSH(u8Value);
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}
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/**
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* @brief Set CS Setup Time.
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*
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* @param pOSPI the base address of the OSPI.
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* @param u8Value CS Setup Time.
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*/
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LOCAL_INLINE void OSPI_HWA_SetCsSetupTime(OSPI_Type *pOSPI, uint8_t u8Value)
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{
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pOSPI->FLS_CFG &= ~OSPI_FLS_CFG_TCSS_MASK;
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pOSPI->FLS_CFG |= OSPI_FLS_CFG_TCSS(u8Value);
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}
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/**
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* @brief Read the OSPI CMDC register value for all.
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*
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* @param pOSPI pOSPI the base address of the OSPI.
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* @return OSPI CMDC regsiter value.
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*/
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LOCAL_INLINE uint32_t OSPI_HWA_GetFlashCfgValue(OSPI_Type *pOSPI)
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{
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return pOSPI->FLS_CFG;
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}
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/**
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* @brief OSPI Enable internal reference clock
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_InternalRefclkEnable(OSPI_Type *pOSPI)
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{
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pOSPI->SOC_CFG |= OSPI_SOC_CFG_CLK_EN_MASK;
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}
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/**
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* @brief OSPI Disable internal reference clock
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_InternalRefclkDisable(OSPI_Type *pOSPI)
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{
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pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_CLK_EN_MASK;
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}
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/**
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* @brief OSPI Set Internal Reference Clock Divider.
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*
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* @param pOSPI the base address of the OSPI.
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* @param u8Value Internal Reference Clock Divider.
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*/
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LOCAL_INLINE void OSPI_HWA_InternalRefclkDiv(OSPI_Type *pOSPI, OSPI_ClockDivideType eClkDiv)
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{
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pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_CLK_DIV_MASK;
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pOSPI->SOC_CFG |= OSPI_SOC_CFG_CLK_DIV(eClkDiv);
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}
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/**
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* @brief OSPI PAD IBE Enable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_PadIbeEnable(OSPI_Type *pOSPI)
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{
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pOSPI->SOC_CFG |= OSPI_SOC_CFG_IBE_EN_MASK;
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}
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/**
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* @brief OSPI PAD IBE Disable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_PadIbeDisable(OSPI_Type *pOSPI)
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{
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pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_IBE_EN_MASK;
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}
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/**
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* @brief OSPI Select Internal Reference Clock Source.
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*
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* @param pOSPI the base address of the OSPI.
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* @param u8Value Internal Reference Clock Source.
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*/
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LOCAL_INLINE void OSPI_HWA_InternalRefclkSource(OSPI_Type *pOSPI, OSPI_ClockMuxType u8Value)
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{
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pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_CLK_MUX_MASK;
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pOSPI->SOC_CFG |= OSPI_SOC_CFG_CLK_MUX(u8Value);
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}
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/**
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* @brief OSPI Use inverted DQS
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_DqsInvertedEnable(OSPI_Type *pOSPI)
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{
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pOSPI->SOC_CFG |= OSPI_SOC_CFG_RWDS_INV_MASK;
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}
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/**
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* @brief OSPI Not use inverted DQS
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_DqsInvertedDisable(OSPI_Type *pOSPI)
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{
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pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_RWDS_INV_MASK;
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}
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/**
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* @brief OSPI Select DQS Source.
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*
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* @param pOSPI the base address of the OSPI.
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* @param u8Value DQS Source.
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*/
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LOCAL_INLINE void OSPI_HWA_DqsSource(OSPI_Type *pOSPI, OSPI_DqsSrcSelType u8Value)
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{
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pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_RWDS_INV_MASK;
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pOSPI->SOC_CFG |= OSPI_SOC_CFG_RWDS_MUX(u8Value);
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}
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/**
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* @brief OSPI OBE timing relax enable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_ObeTimRelaxEnable(OSPI_Type *pOSPI)
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{
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pOSPI->SOC_CFG |= OSPI_SOC_CFG_OBE_RELAX_MASK;
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}
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/**
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* @brief OSPI OBE timing relax disable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_ObeTimRelaxDisable(OSPI_Type *pOSPI)
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{
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pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_OBE_RELAX_MASK;
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}
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/**
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* @brief OSPI DDR Clock Enable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_DdrClkEnable(OSPI_Type *pOSPI)
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{
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pOSPI->SOC_CFG |= OSPI_SOC_CFG_DDR_EN_MASK;
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}
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/**
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* @brief OSPI DDR Clock Disable
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*
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* @param pOSPI the base address of the OSPI.
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*/
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LOCAL_INLINE void OSPI_HWA_DdrClkDisable(OSPI_Type *pOSPI)
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{
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pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_DDR_EN_MASK;
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}
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/**
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* @brief OSPI Switch Delay Line into DQS for timing. DQS will delay for DLLINE_CFG * Tcell.
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*
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* @param pOSPI the base address of the OSPI.
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* @param u8Value DQS Delay Line Cfg Value.
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*/
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LOCAL_INLINE void OSPI_HWA_CfgDelayLine(OSPI_Type *pOSPI, uint8_t u8Value)
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{
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pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_DLLINE_CFG_MASK;
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pOSPI->SOC_CFG |= OSPI_SOC_CFG_DLLINE_CFG(u8Value);
|
|
}
|
|
|
|
/**
|
|
* @brief Write the OSPI SOC CFG register.
|
|
*
|
|
* @param pOSPI pOSPI the base address of the OSPI.
|
|
* @param u32Value the value to be writen.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_SetSocCfgValue(OSPI_Type *pOSPI, uint32_t u32Value)
|
|
{
|
|
pOSPI->SOC_CFG = u32Value;
|
|
}
|
|
|
|
/**
|
|
* @brief Read the OSPI SOC CFG register value for all.
|
|
*
|
|
* @param pOSPI pOSPI the base address of the OSPI.
|
|
* @return OSPI SOC_CFG regsiter value.
|
|
*/
|
|
LOCAL_INLINE uint32_t OSPI_HWA_GetSocCfgValue(OSPI_Type *pOSPI)
|
|
{
|
|
return pOSPI->SOC_CFG;
|
|
}
|
|
|
|
/**
|
|
* @brief Set flash address, users should write the whole value to this register.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u32Value the value which will be written to the FLS_AR register.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_SetFlashAddr(OSPI_Type *pOSPI, uint32_t u32Value)
|
|
{
|
|
pOSPI->FLS_AR = u32Value;
|
|
}
|
|
|
|
/**
|
|
* @brief Set flash addressable mode.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u8Value the value of addressable mode.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_SetFlashAddrMode(OSPI_Type *pOSPI, uint8_t u8Value)
|
|
{
|
|
pOSPI->FLS_CAR &= ~OSPI_FLS_CAR_WA_MASK;
|
|
pOSPI->FLS_CAR |= OSPI_FLS_CAR_WA(u8Value);
|
|
}
|
|
|
|
/**
|
|
* @brief Set Column Address Space.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u8Value the value of Column Address Space.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_SetColAddrSpace(OSPI_Type *pOSPI, uint8_t u8Value)
|
|
{
|
|
pOSPI->FLS_CAR &= ~OSPI_FLS_CAR_CAS_MASK;
|
|
pOSPI->FLS_CAR |= OSPI_FLS_CAR_CAS(u8Value);
|
|
}
|
|
|
|
/**
|
|
* @brief Set Sample delay clock cycle.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u8Value the value of Sample Delay clock cycle.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_SetSampleDlyClkCycle(OSPI_Type *pOSPI, uint8_t u8Value)
|
|
{
|
|
pOSPI->SAMP_CTRL &= ~OSPI_SAMP_CTRL_DLY_MASK;
|
|
pOSPI->SAMP_CTRL |= OSPI_SAMP_CTRL_DLY(u8Value);
|
|
}
|
|
|
|
/**
|
|
* @brief Selects reference clock edge for valid sampling phase.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u8Value the value of reference clock edge.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_SelectRefClkEdge(OSPI_Type *pOSPI, uint8_t u8Value)
|
|
{
|
|
pOSPI->SAMP_CTRL &= ~OSPI_SAMP_CTRL_PHS_MASK;
|
|
pOSPI->SAMP_CTRL |= OSPI_SAMP_CTRL_PHS(u8Value);
|
|
}
|
|
|
|
/**
|
|
* @brief Read RX FIFO Counter,Indicates the current RX FIFO read pointer;
|
|
* Automatically increases when RX FIFO pops an event.
|
|
*
|
|
* @param pOSPI pOSPI the base address of the OSPI.
|
|
* @return RX FIFO Counter.
|
|
*/
|
|
LOCAL_INLINE uint16_t OSPI_HWA_GetRxFifoCnt(OSPI_Type *pOSPI)
|
|
{
|
|
return (uint16_t)((pOSPI->RFSR&OSPI_RFSR_RFCTR_MASK)>>OSPI_RFSR_RFCTR_SHIFT);
|
|
}
|
|
|
|
/**
|
|
* @brief Read RX FIFO Fill Level,Indicates how many words are available in RX FIFO.
|
|
*
|
|
* @param pOSPI pOSPI the base address of the OSPI.
|
|
* @return RX FIFO Fill Level.
|
|
*/
|
|
LOCAL_INLINE uint8_t OSPI_HWA_GetRxFifoFillLevel(OSPI_Type *pOSPI)
|
|
{
|
|
return (uint8_t)((pOSPI->RFSR&OSPI_RFSR_RFFL_MASK)>>OSPI_RFSR_RFFL_SHIFT);
|
|
}
|
|
|
|
/**
|
|
* @brief Set RX FIFO Watermark,
|
|
* Indicates how many valid entries will trigger a readout action.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u8Value the value of RX FIFO Watermark.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_SetRxFifoWaterMark(OSPI_Type *pOSPI, uint8_t u8Value)
|
|
{
|
|
pOSPI->RF_CFG &= ~OSPI_RF_CFG_WMRK_MASK;
|
|
pOSPI->RF_CFG |= OSPI_RF_CFG_WMRK(u8Value);
|
|
}
|
|
|
|
/**
|
|
* @brief Read TX FIFO Counter,Indicates the current TX FIFO stored data pointer;
|
|
* Automatically increases when TX FIFO pops an event.
|
|
*
|
|
* @param pOSPI pOSPI the base address of the OSPI.
|
|
* @return TX FIFO Counter.
|
|
*/
|
|
LOCAL_INLINE uint16_t OSPI_HWA_GetTxFifoCnt(OSPI_Type *pOSPI)
|
|
{
|
|
return (uint16_t)((pOSPI->TFSR&OSPI_TFSR_TFCTR_MASK)>>OSPI_TFSR_TFCTR_SHIFT);
|
|
}
|
|
|
|
/**
|
|
* @brief Read TX FIFO Fill Level,Indicates how many words are available in TX FIFO.
|
|
*
|
|
* @param pOSPI pOSPI the base address of the OSPI.
|
|
* @return TX FIFO Fill Level.
|
|
*/
|
|
LOCAL_INLINE uint8_t OSPI_HWA_GetTxFifoFillLevel(OSPI_Type *pOSPI)
|
|
{
|
|
return (uint8_t)((pOSPI->TFSR&OSPI_TFSR_TFFL_MASK)>>OSPI_TFSR_TFFL_SHIFT);
|
|
}
|
|
|
|
/**
|
|
* @brief Get transmit fifo register address.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @return Transmit fifo register address.
|
|
*/
|
|
LOCAL_INLINE uint32_t OSPI_HWA_GetTFDRAddr(OSPI_Type *pOSPI)
|
|
{
|
|
return (uint32_t)&pOSPI->TFDR;
|
|
}
|
|
|
|
/**
|
|
* @brief Writing this register will trigger data entry of TX FIFO.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u8Value the value of tx data.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_WriteTxData(OSPI_Type *pOSPI, uint32_t u32Value)
|
|
{
|
|
pOSPI->TFDR = u32Value;
|
|
}
|
|
|
|
/**
|
|
* @brief Set TX FIFO Watermark,
|
|
* Indicates how many valid entries will trigger a transmit action.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u8Value the value of TX FIFO Watermark.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_SetTxFifoWaterMark(OSPI_Type *pOSPI, uint8_t u8Value)
|
|
{
|
|
pOSPI->TF_CFG &= ~OSPI_TF_CFG_WMRK_MASK;
|
|
pOSPI->TF_CFG |= OSPI_TF_CFG_WMRK(u8Value);
|
|
}
|
|
|
|
/**
|
|
* @brief Read status register.
|
|
*
|
|
* @param pOSPI pOSPI the base address of the OSPI.
|
|
* @return Status register.
|
|
*/
|
|
LOCAL_INLINE uint32_t OSPI_HWA_GetStatus(OSPI_Type *pOSPI)
|
|
{
|
|
return pOSPI->STATUS&OSPI_STATUS_MASK;
|
|
}
|
|
|
|
/**
|
|
* @brief Read flag register.
|
|
*
|
|
* @param pOSPI pOSPI the base address of the OSPI.
|
|
* @return flag register.
|
|
*/
|
|
LOCAL_INLINE uint32_t OSPI_HWA_GetFlag(OSPI_Type *pOSPI)
|
|
{
|
|
return pOSPI->FLAG&OSPI_FLAG_MASK;
|
|
}
|
|
|
|
/**
|
|
* @brief Writing this register will clear ospi flag.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u8Value the value of flag to be cleared.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_ClearFlag(OSPI_Type *pOSPI, uint32_t u32Value)
|
|
{
|
|
pOSPI->FLAG = (u32Value&OSPI_FLAG_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Set the OSPI IND_EN register value for enable or disable interrupts&DMA.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u32Value the value write to the register.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_SetIntDmasEnableReg(OSPI_Type *pOSPI, uint32_t u32Value)
|
|
{
|
|
pOSPI->IND_EN = (u32Value&OSPI_IND_EN_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Set the OSPI Rx DMA mode.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u8Enable open or close rx dma mode.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_SetRxDMA(OSPI_Type *pOSPI, uint8_t u8Enable)
|
|
{
|
|
if (u8Enable)
|
|
{
|
|
pOSPI->IND_EN |= OSPI_IND_EN_RFDDRE_MASK;
|
|
}
|
|
else
|
|
{
|
|
pOSPI->IND_EN &= ~OSPI_IND_EN_RFDDRE_MASK;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Set the OSPI Tx DMA mode.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u8Enable open or close tx dma mode.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_SetTxDMA(OSPI_Type *pOSPI, uint8_t u8Enable)
|
|
{
|
|
if (u8Enable)
|
|
{
|
|
pOSPI->IND_EN |= OSPI_IND_EN_TFFDRE_MASK;
|
|
}
|
|
else
|
|
{
|
|
pOSPI->IND_EN &= ~OSPI_IND_EN_TFFDRE_MASK;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Set flash top address register.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param Top Address of Flash Device.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_SetFlashTopAddr(OSPI_Type *pOSPI, uint32_t u32Value)
|
|
{
|
|
pOSPI->FLS_TAR = (u32Value&OSPI_FLS_TAR_MASK);
|
|
}
|
|
|
|
/**
|
|
* @brief Get receive fifo register address.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @return Receive fifo register address.
|
|
*/
|
|
LOCAL_INLINE uint32_t OSPI_HWA_GetRFDRAddr(OSPI_Type *pOSPI)
|
|
{
|
|
return (uint32_t)pOSPI->RFDR;
|
|
}
|
|
|
|
/**
|
|
* @brief Read receive fifo data register.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u8Idx Fifo index to be read.
|
|
* @return Receive fifo data register.
|
|
*/
|
|
LOCAL_INLINE uint32_t OSPI_HWA_ReadRcvFifoReg(OSPI_Type *pOSPI,uint8_t u8Idx)
|
|
{
|
|
return pOSPI->RFDR[u8Idx];
|
|
}
|
|
|
|
/**
|
|
* @brief Read secondary receive fifo data register.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @return Secondary receive fifo data register.
|
|
*/
|
|
LOCAL_INLINE uint32_t OSPI_HWA_ReadSecondaryRcvFifoReg(OSPI_Type *pOSPI)
|
|
{
|
|
return pOSPI->RFD2R;
|
|
}
|
|
|
|
/**
|
|
* @brief Write LUT Key register.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u32Value LUT Key Value to be writed.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_WriteLutKey(OSPI_Type *pOSPI, uint32_t u32Value)
|
|
{
|
|
pOSPI->LUT_KEY = u32Value;
|
|
}
|
|
|
|
/**
|
|
* @brief Read LUT Key register.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @return LUT Key Value.
|
|
*/
|
|
LOCAL_INLINE uint32_t OSPI_HWA_ReadLutKey(OSPI_Type *pOSPI)
|
|
{
|
|
return pOSPI->LUT_KEY;
|
|
}
|
|
|
|
/**
|
|
* @brief Lock the LUT.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_LockLut(OSPI_Type *pOSPI)
|
|
{
|
|
pOSPI->LUT_CFG = OSPI_LUT_CFG_LOCK_MASK;
|
|
}
|
|
|
|
/**
|
|
* @brief Unlock the LUT.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_UnlockLut(OSPI_Type *pOSPI)
|
|
{
|
|
pOSPI->LUT_CFG = OSPI_LUT_CFG_UNLOCK_MASK;
|
|
}
|
|
|
|
/**
|
|
* @brief Write lookup table register.
|
|
*
|
|
* @param pOSPI the base address of the OSPI.
|
|
* @param u8Idx Index of LUT.
|
|
* @param u32Value LUT Value to be writed.
|
|
*/
|
|
LOCAL_INLINE void OSPI_HWA_WriteLut(OSPI_Type *pOSPI, uint8_t u8Idx, uint32_t u32Value)
|
|
{
|
|
pOSPI->LUT[u8Idx] = u32Value;
|
|
}
|
|
|
|
#endif /* #if OSPI_INSTANCE_COUNT > 0U */
|
|
|
|
#endif /* #ifndef _HWA_OSPI_H_ */
|