From 089add0ade5f56476eea2c7942ea587aec38ec45 Mon Sep 17 00:00:00 2001 From: cfif Date: Tue, 9 Jun 2026 13:41:49 +0300 Subject: [PATCH] =?UTF-8?q?=D0=9D=D0=BE=D0=B2=D1=8B=D0=B9=20SDK?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Inc/HwA_adc.h | 2408 ++++++++ Inc/HwA_aontimer.h | 352 ++ Inc/HwA_cm7.h | 42 + Inc/HwA_cmp.h | 988 ++++ Inc/HwA_cmu.h | 249 + Inc/HwA_cordic.h | 210 + Inc/HwA_cpm.h | 340 ++ Inc/HwA_crc.h | 303 + Inc/HwA_crm.h | 377 ++ Inc/HwA_csc.h | 1294 +++++ Inc/HwA_dma.h | 1605 ++++++ Inc/HwA_dmamux.h | 112 + Inc/HwA_eftu_ccm.h | 485 ++ Inc/HwA_eftu_cmu.h | 166 + Inc/HwA_eftu_dtm.h | 952 ++++ Inc/HwA_eftu_tbu.h | 451 ++ Inc/HwA_eftu_tim.h | 840 +++ Inc/HwA_eftu_tom.h | 1161 ++++ Inc/HwA_eim.h | 167 + Inc/HwA_elu.h | 1143 ++++ Inc/HwA_enet.h | 13240 +++++++++++++++++++++++++++++++++++++++++++ Inc/HwA_erm.h | 153 + Inc/HwA_fciic.h | 1071 ++++ Inc/HwA_fcpit.h | 409 ++ Inc/HwA_fcsmu.h | 708 +++ Inc/HwA_fcspi.h | 412 ++ Inc/HwA_fcuart.h | 924 +++ Inc/HwA_flexcan.h | 2096 +++++++ Inc/HwA_freqm.h | 187 + Inc/HwA_ftu.h | 1955 +++++++ Inc/HwA_gpio.h | 151 + Inc/HwA_hrpwm.h | 256 + Inc/HwA_hsadc.h | 2069 +++++++ Inc/HwA_intm.h | 189 + Inc/HwA_ism.h | 654 +++ Inc/HwA_ldi.h | 490 ++ Inc/HwA_lu.h | 265 + Inc/HwA_mam.h | 306 + Inc/HwA_mb.h | 638 +++ Inc/HwA_msc.h | 710 +++ Inc/HwA_ospi.h | 874 +++ Inc/HwA_overlay.h | 324 ++ Inc/HwA_pmc.h | 122 + Inc/HwA_port.h | 282 + Inc/HwA_ptimer.h | 722 +++ Inc/HwA_qdt.h | 1858 ++++++ Inc/HwA_rgm.h | 1095 ++++ Inc/HwA_rtc.h | 362 ++ Inc/HwA_scg.h | 1101 ++++ Inc/HwA_scm.h | 724 +++ Inc/HwA_sdadc.h | 5698 +++++++++++++++++++ Inc/HwA_sddf.h | 2420 ++++++++ Inc/HwA_sec.h | 753 +++ Inc/HwA_sent.h | 1443 +++++ Inc/HwA_smc.h | 1502 +++++ Inc/HwA_ssi.h | 929 +++ Inc/HwA_stcu.h | 274 + Inc/HwA_tmu.h | 702 +++ Inc/HwA_tpue.h | 2076 +++++++ Inc/HwA_tpuh.h | 906 +++ Inc/HwA_trgsel.h | 164 + Inc/HwA_tstmp.h | 206 + Inc/HwA_wdog.h | 135 + Inc/HwA_wku.h | 216 + Inc/Hwa_eftu_spe.h | 333 ++ modular.json | 7 + 66 files changed, 65756 insertions(+) create mode 100644 Inc/HwA_adc.h create mode 100644 Inc/HwA_aontimer.h create mode 100644 Inc/HwA_cm7.h create mode 100644 Inc/HwA_cmp.h create mode 100644 Inc/HwA_cmu.h create mode 100644 Inc/HwA_cordic.h create mode 100644 Inc/HwA_cpm.h create mode 100644 Inc/HwA_crc.h create mode 100644 Inc/HwA_crm.h create mode 100644 Inc/HwA_csc.h create mode 100644 Inc/HwA_dma.h create mode 100644 Inc/HwA_dmamux.h create mode 100644 Inc/HwA_eftu_ccm.h create mode 100644 Inc/HwA_eftu_cmu.h create mode 100644 Inc/HwA_eftu_dtm.h create mode 100644 Inc/HwA_eftu_tbu.h create mode 100644 Inc/HwA_eftu_tim.h create mode 100644 Inc/HwA_eftu_tom.h create mode 100644 Inc/HwA_eim.h create mode 100644 Inc/HwA_elu.h create mode 100644 Inc/HwA_enet.h create mode 100644 Inc/HwA_erm.h create mode 100644 Inc/HwA_fciic.h create mode 100644 Inc/HwA_fcpit.h create mode 100644 Inc/HwA_fcsmu.h create mode 100644 Inc/HwA_fcspi.h create mode 100644 Inc/HwA_fcuart.h create mode 100644 Inc/HwA_flexcan.h create mode 100644 Inc/HwA_freqm.h create mode 100644 Inc/HwA_ftu.h create mode 100644 Inc/HwA_gpio.h create mode 100644 Inc/HwA_hrpwm.h create mode 100644 Inc/HwA_hsadc.h create mode 100644 Inc/HwA_intm.h create mode 100644 Inc/HwA_ism.h create mode 100644 Inc/HwA_ldi.h create mode 100644 Inc/HwA_lu.h create mode 100644 Inc/HwA_mam.h create mode 100644 Inc/HwA_mb.h create mode 100644 Inc/HwA_msc.h create mode 100644 Inc/HwA_ospi.h create mode 100644 Inc/HwA_overlay.h create mode 100644 Inc/HwA_pmc.h create mode 100644 Inc/HwA_port.h create mode 100644 Inc/HwA_ptimer.h create mode 100644 Inc/HwA_qdt.h create mode 100644 Inc/HwA_rgm.h create mode 100644 Inc/HwA_rtc.h create mode 100644 Inc/HwA_scg.h create mode 100644 Inc/HwA_scm.h create mode 100644 Inc/HwA_sdadc.h create mode 100644 Inc/HwA_sddf.h create mode 100644 Inc/HwA_sec.h create mode 100644 Inc/HwA_sent.h create mode 100644 Inc/HwA_smc.h create mode 100644 Inc/HwA_ssi.h create mode 100644 Inc/HwA_stcu.h create mode 100644 Inc/HwA_tmu.h create mode 100644 Inc/HwA_tpue.h create mode 100644 Inc/HwA_tpuh.h create mode 100644 Inc/HwA_trgsel.h create mode 100644 Inc/HwA_tstmp.h create mode 100644 Inc/HwA_wdog.h create mode 100644 Inc/HwA_wku.h create mode 100644 Inc/Hwa_eftu_spe.h create mode 100644 modular.json diff --git a/Inc/HwA_adc.h b/Inc/HwA_adc.h new file mode 100644 index 0000000..3efe2d1 --- /dev/null +++ b/Inc/HwA_adc.h @@ -0,0 +1,2408 @@ +/** + * @file HwA_adc.h + * @author flagchip + * @brief Hardware access layer for ADC + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip030 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_ADC_H_ +#define _HWA_ADC_H_ + +#include "device_header.h" + +#if ADC_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_adc HwA_adc + * @ingroup module_driver_adc + * @{ + */ + +/** + * @brief Select the ADC Resolution + * + */ +typedef enum +{ + ADC_RESOLUTION_12_BIT = 0U, /*!< 12 bit resolution */ + ADC_RESOLUTION_10_BIT = 1U, /*!< 10 bit resolution */ + ADC_RESOLUTION_8_BIT = 2U /*!< 8 bit resolution */ +} ADC_ResolutionType; + +/** + * @brief Select the ADC result alignment + * + */ +typedef enum +{ + ADC_ALIGN_RIGHT = 0U, /*!< ADC result is aligned in right */ + ADC_ALIGN_LEFT = 1U /*!< ADC result is aligned in left */ +} ADC_AlignType; + +/** + * @brief Select the ADC trigger mode + * + * @note This option is only valid in ADC single sequence mode and ADC continuous mode. + * In ADC discontinuous mode, the ADC trigger mode is fixed as ADC_TRIGMODE_RISING_EDGE + * + */ +typedef enum +{ + ADC_TRGMODE_SW = 0U, /*!< ADC is triggered by software */ + ADC_TRGMODE_RISING_EDGE = 1U, /*!< ADC is triggered by hardware trigger on rising edge */ + ADC_TRGMODE_FALLING_EDGE = 2U, /*!< ADC is triggered by hardware trigger on falling edge */ + ADC_TRGMODE_BOTH_EDGE = 3U, /*!< ADC is triggered by hardware trigger on both edges */ + ADC_TRGMODE_HIGH_VOLTAGE = 4U, /*!< ADC is triggered when hardware trigger is high voltage */ + ADC_TRGMODE_LOW_VOLTAGE = 5U, /*!< ADC is triggered when hardware trigger is low voltage */ + #if ADC_SUPPORT_INTERNAL_PERIODIC_TRG + ADC_TRGMODE_INTERNAL_PERIODIC = 6U /*!< ADC is triggered by internal generated periodic trigger */ + #endif +} ADC_TrgModeType; + +/** + * @brief Select the ADC sequence mode + * + */ +typedef enum +{ + ADC_SEQMODE_SINGLE = 0U, /*!< ADC single sequence mode */ + ADC_SEQMODE_CONTINUOUS = 1U, /*!< ADC continuous mode */ + ADC_SEQMODE_DISCONTINUOUS_0 = 2U, /*!< ADC discontinuous 0 mode */ + ADC_SEQMODE_DISCONTINUOUS_1 = 3U, /*!< ADC discontinuous 1 mode */ +#if ADC_SUPPORT_SG_MODE + ADC_SEQMODE_GROUP = 4U /*!< ADC sequence group mode */ +#endif +} ADC_SeqModeType; + +/** + * @brief Select the ADC overrun management mode + * + * To select whether the old data are preserved or overwritten by the new data when ADC + * is overrun (The FIFO is full when new convertion result comes) + * + */ +typedef enum +{ + ADC_OVERRUN_MODE_PRESERVE = 0U, /*!< old data are preserved when ADC is overrun */ + ADC_OVERRUN_MODE_OVERWRITE = 1U /*!< old data are overwritten when ADC is overrun */ +} ADC_OverrunModeType; + +#if ADC_SUPPORT_INTERNAL_REFERENCE +/** + * @brief Select the ADC voltage reference source + * + */ +typedef enum +{ + ADC_REF_INTERNAL = 0U, /*!< select the internal voltage reference */ + ADC_REF_EXTERNAL = 1U /*!< select the external voltage reference */ +} ADC_RefType; +#endif + +#if ADC_SUPPORT_SG_MODE +/** + * @brief Select the priority of Trigger Latch Unit + * + */ +typedef enum +{ + ADC_TRG_LATCH_UNIT_PRI_ROUND_ROBIN = 0U, /*!< select the round robin scheduling priority */ + ADC_TRG_LATCH_UNIT_PRI_FIX = 1U /*!< select the fixed priority(0>1>2>3) */ +} ADC_TrgLatchUnitPri; +#endif + +/** + * @brief Select the ADC hardware average samples + * + */ +typedef enum +{ + ADC_AVERAGE_LEN_4 = 0U, /*!< result average by 4 samples */ + ADC_AVERAGE_LEN_8 = 1U, /*!< result average by 8 samples */ + ADC_AVERAGE_LEN_16 = 2U, /*!< result average by 16 samples */ + ADC_AVERAGE_LEN_32 = 3U /*!< result average by 32 samples */ +} ADC_AverageLenType; + +/** + * @brief Set the ADC clock divider + * + * @note ADC clock divider is not available in FC7300F512K + * + */ +typedef enum +{ + ADC_CLOCK_DIV_1 = 0U, + ADC_CLOCK_DIV_2 = 1U, + ADC_CLOCK_DIV_4 = 2U, + ADC_CLOCK_DIV_8 = 3U +} ADC_ClockDivideType; + +/** + * @brief The trigger source of the ADC instance + * + * @note In ADC discontinuous 1 mode, the trigger source is from Ptimer + * In ADC single and continuous mode, if hardware trigger is enabled, the trigger + * source is from TRGSEL + * + */ +typedef enum +{ + ADC_TRGSRC_PTIMER = 0U, /**< Trigger source from PTIMER/TRGSEL with Ptimer */ + ADC_TRGSRC_TRGSEL = 2U, /**< Trigger source from TRGSEL */ +#if ADC_SUPPORT_SG_MODE + ADC_TRGSRC_TRG_LATCH_UNIT = 3U /**< Trigger source from Trigger Latch Unit */ +#endif +} ADC_TrgSrcType; + +/** + * @brief Select the channel compare mode + * + * Select whether the channel compare is enabled on all channels or on the single + * selected channel + * + */ +typedef enum +{ + ADC_CMP_CHANNEL_ALL = 0U, /*!< Compare enabled in all channels */ + ADC_CMP_CHANNEL_SINGLE = 1U /*!< Compare enabled in the specified channel */ +} ADC_CmpChannelType; + +/** + * @brief Select the enhanced compare option + * + */ +typedef enum +{ + ADC_ECMP_NOT_BETWEEN = 0U, + ADC_ECMP_OVER_HIGN = 1U, + ADC_ECMP_UNDER_LOW = 2U, + ADC_ECMP_BETWEEN = 3U +} ADC_ECMPOption; + +#if ADC_SUPPORT_ENHANCED_CMP_BLOCK +/** + * @brief The ADC enhanced compare block Index + * + */ +typedef enum +{ + ADC_ECMP0 = 0U, + ADC_ECMP1 = 1U, +} ADC_ECMPIndex; +#endif + +#if ADC_SUPPORT_FAST_CMP_BLOCK +typedef enum +{ + ADC_FCMP_REFMODE_SW = 0U, + ADC_FCMP_REFMODE_RAMP = 1U, + ADC_FCMP_REFMODE_ALT = 2U +} ADC_FCmpRefMode; + +typedef enum +{ + ADC_FCMP_RAMPDIR_UP = 0U, + ADC_FCMP_RAMPDIR_DOWN = 1U +} ADC_FCmpRampDir; + +typedef enum +{ + ADC_FCMP_RAMPTRGMODE_SW_AUTO = 0U, + ADC_FCMP_RAMPTRGMODE_SW_EXT = 1U, + ADC_FCMP_RAMPTRGMODE_EXT_AUTO = 2U +} ADC_FCmpRampTrgMode; + + +typedef enum +{ + ADC_FCMP_RAMPTRGPOL_RISING_OR_HIGH = 0U, + ADC_FCMP_RAMPTRGPOL_FALLING_OR_LOW = 1U, +} ADC_FCmpRampTrgPolarity; + +typedef enum +{ + ADC_FCMP_BFA_A1B0 = 0U, + ADC_FCMP_BFA_A0B1 = 1U, +} ADC_FCmpBFLAction; +#endif + +/** + * @brief Select the channel compare mode + * + * Select whether the channel compare is enabled on all channels or on the single + * selected channel + * + */ +typedef enum +{ + ADC_ECMP_CHANNEL_ALL = 0U, /*!< Compare enabled in all channels */ + ADC_ECMP_CHANNEL_SINGLE = 1U /*!< Compare enabled in the specified channel */ +} ADC_ECmpChannelType; + +#if ADC_SUPPORT_FAST_CMP_BLOCK +/** + * @brief Check whether detect fast compare falling edge + * + * @param pAdc the base address of the ADC instance + * @return true detect fast compare falling edge + * @return false not detect fast compare falling edge + */ +LOCAL_INLINE bool ADC_HWA_GetFCRFFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_FCR_F_MASK) >> ADC_INT_STATUS_FCR_F_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the fast compare falling edge flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearFCRFFlag(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_FCR_F(1U); +} + +/** + * @brief Check whether detect fast compare rising edge + * + * @param pAdc the base address of the ADC instance + * @return true detect fast compare rising edge + * @return false not detect fast compare rising edge + */ +LOCAL_INLINE bool ADC_HWA_GetFCRRFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_FCR_R_MASK) >> ADC_INT_STATUS_FCR_R_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the fast compare rising edge flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearFCRRFlag(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_FCR_R(1U); +} + +#endif + +/** + * @brief Check whether the data quantity in the FIFO is greater than watermark + * + * @param pAdc the base address of the ADC instance + * @return true the ADC FIFO is ready + * @return false the ADC FIFO is unready + */ +LOCAL_INLINE bool ADC_HWA_GetFIFOReadyFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_FIFO_RDY_MASK) >> ADC_INT_STATUS_FIFO_RDY_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the conversion result is in the comparing range + * + * @param pAdc the base address of the ADC instance + * @return true the conversion result is in the comparing range + * @return false the conversion result is not in the comparing range + */ +LOCAL_INLINE bool ADC_HWA_GetCmpFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_ACMP_MASK) >> ADC_INT_STATUS_ACMP_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the compare flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearCmpFlag(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_ACMP(1U); +} + +/** + * @brief Check whether the ADC FIFO is empty + * + * @param pAdc the base address of the ADC instance + * @return true the ADC FIFO is empty + * @return false the ADC FIFO is not empty + */ +LOCAL_INLINE bool ADC_HWA_GetFIFOEmptyFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_EMPTY_MASK) >> ADC_INT_STATUS_EMPTY_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the ADC FIFO is full + * + * @param pAdc the base address of the ADC instance + * @return true the ADC FIFO is full + * @return false the ADC FIFO is not full + */ +LOCAL_INLINE bool ADC_HWA_GetFIFOFullFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_FULL_MASK) >> ADC_INT_STATUS_FULL_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the overrrun status of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return true the ADC is in overrun status + * @return false the ADC is not overrun + */ +LOCAL_INLINE bool ADC_HWA_GetOverrunFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_OVR_MASK) >> ADC_INT_STATUS_OVR_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the overrun flag of the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearOverrunFlag(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_OVR(1U); +} + +/** + * @brief Check whether the ADC conversion sequence is finished + * + * @param pAdc the base address of the ADC instance + * @return true the ADC conversion sequence is finished + * @return false the ADC conversion sequence is unfinished + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSequenceFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_EOSEQ_MASK) >> ADC_INT_STATUS_EOSEQ_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ADC conversion sequence complete flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearEndOfSequenceFlag(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_EOSEQ(1U); +} + +/** + * @brief Check whether the current ADC conversion is finished + * + * @param pAdc the base address of the ADC instance + * @return true the current ADC conversion is finished + * @return false the current ADC conversion is unfinished + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfConversionFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_EOC_MASK) >> ADC_INT_STATUS_EOC_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ADC single conversion complete flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearEndOfConversionFlag(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_EOC(1U); +} + +/** + * @brief Check whether the sampling phase of the current ADC conversion is finished + * + * @param pAdc the base address of the ADC instance + * @return true the sampling phase of the ADC conversion is finished + * @return false the sampling phase of the ADC conversion is unfinished + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSampleFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_EOSMP_MASK) >> ADC_INT_STATUS_EOSMP_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ADC sampling complete flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearEndOfSampleFlag(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_EOSMP(1U); +} + +/** + * @brief Check whether the ADC instance is ready to operate + * + * @param pAdc the base address of the ADC instance + * @return true the ADC instance is ready for a new conversion + * @return false the ADC instance is unready + */ +LOCAL_INLINE bool ADC_HWA_GetADCReadyFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_ADRDY_MASK) >> ADC_INT_STATUS_ADRDY_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ready flag of the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearADCReadyFlag(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_ADRDY(1U); +} + +/** + * @brief Clear the ready flag of the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearFlags(ADC_Type *const pAdc, uint32_t u32Flags) +{ + pAdc->INT_STATUS = u32Flags; +} + +#if ADC_SUPPORT_FAST_CMP_BLOCK +/** + * @brief Get the fast compare falling edge interrupt + * If enabled, ADC interrupt is generated when detect fast compare falling edge + * @param pAdc the base address of the ADC instance + * @return true fast compare falling interrupt is enabled + * @return false fast compare falling interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetFCRFIntEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_FCR_F_IE_MASK) >> ADC_INT_ENABLE_FCR_F_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the fast compare falling edge interrupt + * If enabled, ADC interrupt is generated when detect fast compare falling edge + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the fast compare falling interrupt + */ +LOCAL_INLINE void ADC_HWA_SetFCRFIntEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_FCR_F_IE_MASK) | ADC_INT_ENABLE_FCR_F_IE(bEnable); +} + +/** + * @brief Get the fast compare rising edge interrupt + * If enabled, ADC interrupt is generated when detect fast compare rising edge + * @param pAdc the base address of the ADC instance + * @return true fast compare rising interrupt is enabled + * @return false fast compare rising interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetFCRRIntEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_FCR_R_IE_MASK) >> ADC_INT_ENABLE_FCR_R_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the fast compare rising edge interrupt + * If enabled, ADC interrupt is generated when detect fast compare rising edge + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the fast compare rising interrupt + */ +LOCAL_INLINE void ADC_HWA_SetFCRRIntEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_FCR_R_IE_MASK) | ADC_INT_ENABLE_FCR_R_IE(bEnable); +} +#endif + +/** + * @brief Get the FIFO Ready interrupt flag + * If enabled, ADC interrupt is generated when the FIFO water mark is greater than FWMARK + * @param pAdc the base address of the ADC instance + * @return true ADC FIFO Ready interrupt is enabled + * @return false ADC FIFO Ready interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetFIFOReadyIntEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_FIFO_RDY_IE_MASK) >> ADC_INT_ENABLE_FIFO_RDY_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the FIFO Ready interrupt flag + * If enabled, ADC interrupt is generated when the FIFO water mark is greater than FWMARK + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC FIFO Ready interrupt + */ +LOCAL_INLINE void ADC_HWA_SetFIFOReadyIntEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_FIFO_RDY_IE_MASK) | ADC_INT_ENABLE_FIFO_RDY_IE(bEnable); +} + +/** + * @brief Get the Compare interrupt flag + * If enabled, ADC interrupt is generated when the ADC conversion result is not within the compare threshold + * @param pAdc the base address of the ADC instance + * @return true ADC Compare interrupt is enabled + * @return false ADC Compare interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetCmpIntEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_ACMP_IE_MASK) >> ADC_INT_ENABLE_ACMP_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Compare interrupt flag + * If enabled, ADC interrupt is generated when the ADC conversion result is not within the compare threshold + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC Compare interrupt + */ +LOCAL_INLINE void ADC_HWA_SetCmpIntEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_ACMP_IE_MASK) | ADC_INT_ENABLE_ACMP_IE(bEnable); +} + +/** + * @brief Get the Overrun interrupt flag + * If enabled, ADC interrupt is generated when the ADC instance is overrun + * @param pAdc the base address of the ADC instance + * @return true ADC Overrun interrupt is enabled + * @return false ADC Overrun interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetOverrunIntEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_OVRIE_MASK) >> ADC_INT_ENABLE_OVRIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Overrun interrupt flag + * If enabled, ADC interrupt is generated when the ADC instance is overrun + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC Overrun interrupt + */ +LOCAL_INLINE void ADC_HWA_SetOverrunIntEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_OVRIE_MASK) | ADC_INT_ENABLE_OVRIE(bEnable); +} + +/** + * @brief Get the End of Sequence interrupt enable flag + * If enabled, ADC interrupt is generated when the ADC sequence conversion is completed + * @param pAdc the base address of the ADC instance + * @return true ADC End of Sequence interrupt is enabled + * @return false ADC End of Sequence interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSequenceIntEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_EOSEQIE_MASK) >> ADC_INT_ENABLE_EOSEQIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the End of Sequence interrupt enable flag + * If enabled, ADC interrupt is generated when the ADC sequence conversion is completed + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC End of Sequence interrupt + */ +LOCAL_INLINE void ADC_HWA_SetEndOfSequenceIntEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_EOSEQIE_MASK) | ADC_INT_ENABLE_EOSEQIE(bEnable); +} + +/** + * @brief Get the conversion complete interrupt enable flag + * If enabled, ADC interrupt is generated when each ADC conversion is completed + * @param pAdc the base address of the ADC instance + * @return true the ADC End of Conversion interrupt is enabled + * @return false the ADC End of Conversion interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWAGetEndOfConversionIntEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_EOCIE_MASK) >> ADC_INT_ENABLE_EOCIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the conversion complete interrupt enable flag + * If enabled, ADC interrupt is generated when each ADC conversion is completed + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the conversion complete interrupt + */ +LOCAL_INLINE void ADC_HWA_SetEndOfConversionIntEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_EOCIE_MASK) | ADC_INT_ENABLE_EOCIE(bEnable); +} + +/** + * @brief Get the sample complete interrupt enable flag + * If enabled, ADC interrupt is generated when each ADC conversion finished the sampling phase + * @param pAdc the base address of the ADC instance + * @return true the sample complete interrupt is enabled + * @return false the sample complete interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSampleIntEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_EOSMPIE_MASK) >> ADC_INT_ENABLE_EOSMPIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the sample complete interrupt enable flag + * If enabled, ADC interrupt is generated when each ADC conversion finished the sampling phase + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the sample complete interrupt + */ +LOCAL_INLINE void ADC_HWA_SetEndOfSampleIntEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_EOSMPIE_MASK) | ADC_INT_ENABLE_EOSMPIE(bEnable); +} + +/** + * @brief Get the ADC ready interrupt enable flag + * If enabled, ADC interrupt is generated when the ADC module is ready for conversion + * @param pAdc the base address of the ADC instance + * @return true the ADC ready interrupt is enabled + * @return false the ADC ready interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetADCReadyIntEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_ADRDYIE_MASK) >> ADC_INT_ENABLE_ADRDYIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the ADC ready interrupt enable flag + * If enabled, ADC interrupt is generated when the ADC module is ready for conversion + * @param pAdc the base address of the ADC instance + * @param bEnable Whether to enable the ADC ready interrupt + */ +LOCAL_INLINE void ADC_HWA_SetADCReadyIntEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_ADRDYIE_MASK) | ADC_INT_ENABLE_ADRDYIE(bEnable); +} + +/** + * @brief Get the interrupt enable config + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the interrupt enable config + */ +LOCAL_INLINE uint32_t ADC_HWA_GetIntEnable(const ADC_Type *const pAdc) +{ + return pAdc->INT_ENABLE; +} + +/** + * @brief Set the interrupt enable + * + * @param pAdc adc address point + * @param u32IntCfg the interrupt enable config + */ +LOCAL_INLINE void ADC_HWA_SetIntEnable(ADC_Type *const pAdc, uint32_t u32IntCfg) +{ + pAdc->INT_ENABLE = u32IntCfg; +} + +/** + * @brief Reset the ADC hardware + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Reset(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADRST(1U); + pAdc->CONTROL = 0U; +} + +/** + * @brief Get whether ADC is in stopping status + * + * @param pAdc the base address of the ADC instance + * @return true the ADC instance is stopping + * @return false the ADC instance is not in stopping status + */ +LOCAL_INLINE bool ADC_HWA_GetStop(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CONTROL; + u32TmpVal = (u32TmpVal & ADC_CONTROL_ADSTP_MASK) >> ADC_CONTROL_ADSTP_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Stop the ADC conversion + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Stop(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADSTP(1U); +} + +/** + * @brief Get the conversion start status of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return true the conversion of the ADC instance is started + * @return false the conversion of the ADC instance has not been started + */ +LOCAL_INLINE bool ADC_HWA_GetStart(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CONTROL; + u32TmpVal = (u32TmpVal & ADC_CONTROL_ADSTART_MASK) >> ADC_CONTROL_ADSTART_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Start the ADC conversion + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Start(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADSTART(1U); +} + +/** + * @brief Get whether the ADC instance is in disable status + * + * @param pAdc the base address of the ADC instance + * @return true the ADC instance is in disable status + * @return false the ADC instance is not in disable status + */ +LOCAL_INLINE bool ADC_HWA_GetDisable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CONTROL; + u32TmpVal = (u32TmpVal & ADC_CONTROL_ADDIS_MASK) >> ADC_CONTROL_ADDIS_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Disable the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Disable(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADDIS(1U); +} + +/** + * @brief Get the enable status of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return true the ADC instance is enabled + * @return false the ADC instance has not been enabled + */ +LOCAL_INLINE bool ADC_HWA_GetEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CONTROL; + u32TmpVal = (u32TmpVal & ADC_CONTROL_ADEN_MASK) >> ADC_CONTROL_ADEN_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Enable(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADEN(1U); +} + +#if ADC_SUPPORT_INSTANCE_DIFFMODE_SET +/** + * @brief Get whether the ADC is in differential mode + * + * @note Differential mode is only available in FC7300F2M + * + * @param pAdc the base address of the ADC instance + * @return true the ADC is in differential mode + * @return false the ADC is not in differential mode + */ +LOCAL_INLINE bool ADC_HWA_GetInstanceDiffModeEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_DIFF_MASK) >> ADC_CFG1_DIFF_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable the ADC differential mode + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC differential mode + */ +LOCAL_INLINE void ADC_HWA_SetInstanceDiffModeEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_DIFF_MASK) | ADC_CFG1_DIFF(bEnable); +} +#endif + +/** + * @brief Get the overrun management mode + * + * @param pAdc the base address of the ADC instance + * @return ADC_OVERRUN_MODE_PRESERVE the conversion data is preserved when ADC is overrun + * @return ADC_OVERRUN_MODE_OVERWRITE the conversion data is overwritten when ADC is overrun + */ +LOCAL_INLINE ADC_OverrunModeType ADC_HWA_GetOverrunManagementMode(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_OVRMOD_MASK) >> ADC_CFG1_OVRMOD_SHIFT; + return (ADC_OverrunModeType)u32TmpVal; +} + +/** + * @brief Set the overrun management mode + * + * @param pAdc the base address of the ADC instance + * @param eMode the overrun management for the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetOverrunManagementMode(ADC_Type *const pAdc, ADC_OverrunModeType eMode) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_OVRMOD_MASK) | ADC_CFG1_OVRMOD(eMode); +} + +#if ADC_SUPPORT_SG_MODE +/** + * @brief Get the sequence group mode state + * + * @param pAdc the base address of the ADC instance + * @return the sequence group mode state + */ +LOCAL_INLINE bool ADC_HWA_GetSGEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_SEQGP_EN_MASK) >> ADC_CFG1_SEQGP_EN_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the sequence group mode state + * + * @param pAdc the base address of the ADC instance + * @param the sequence group mode state + */ +LOCAL_INLINE void ADC_HWA_SetSGEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_SEQGP_EN_MASK) | ADC_CFG1_SEQGP_EN(bEnable); +} +#endif + +/** + * @brief Get the sequence length of the ADC conversion sequence + * + * @param pAdc the base address of the ADC instance + * @return uint8_t the sequence length of the ADC conversion sequence + */ +LOCAL_INLINE uint8_t ADC_HWA_GetSequenceLength(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_SEQ_LEN_MASK) >> ADC_CFG1_SEQ_LEN_SHIFT; + + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the sequence length of the ADC conversion sequence + * + * @param pAdc the base address of the ADC instance + * @param u8SequenceLength the sequence length of the ADC conversion sequence + */ +LOCAL_INLINE void ADC_HWA_SetSequenceLength(ADC_Type *const pAdc, uint8_t u8SequenceLength) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_SEQ_LEN_MASK) | ADC_CFG1_SEQ_LEN(u8SequenceLength); +} + +/** + * @brief Get the ADC sequence mode + * + * @param pAdc the base address of the ADC instance + * @return ADC_SeqModeType the sequence mode the the ADC instance + */ +LOCAL_INLINE ADC_SeqModeType ADC_HWA_GetSequenceMode(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_SEQ_MOD_MASK) >> ADC_CFG1_SEQ_MOD_SHIFT; + + return (ADC_SeqModeType)u32TmpVal; +} + +/** + * @brief Set the ADC sequence mode + * + * @param pAdc the base address of the ADC instance + * @param eSequenceMode the sequence mode the the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetSequenceMode(ADC_Type *const pAdc, ADC_SeqModeType eSequenceMode) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_SEQ_MOD_MASK) | ADC_CFG1_SEQ_MOD(eSequenceMode); +} + +/** + * @brief Get whether auto disable is enabled + * + * @note Auto disable mode is only available in FC7300F2M + * + * @param pAdc the base address of the ADC instance + * @return true auto disable mode is enabled + * @return false auto disable mode is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetAutoDisableModeEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_AUTO_DIS_MASK) >> ADC_CFG1_AUTO_DIS_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable auto disable mode + * + * @note Auto disable mode is only available in FC7300F2M + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable auto disable mode + */ +LOCAL_INLINE void ADC_HWA_SetAutoDisableModeEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_AUTO_DIS_MASK) | ADC_CFG1_AUTO_DIS(bEnable); +} + +/** + * @brief Get whether the wait conversion mode is enabled + * + * @param pAdc the base address of the ADC instance + * @return true the wait conversion mode is enabled + * @return false the wait conversion mode is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetWaitConversionModeEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_WAIT_MASK) >> ADC_CFG1_WAIT_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the wait conversion mode + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the wait conversion mode + */ +LOCAL_INLINE void ADC_HWA_SetWaitConversionModeEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_WAIT_MASK) | ADC_CFG1_WAIT(bEnable); +} + +/** + * @brief Get the trigger source the the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return ADC_TrigSrcType the trigger source of the ADC instance + */ +LOCAL_INLINE ADC_TrgSrcType ADC_HWA_GetTriggerSource(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_TRIGSRC_MASK) >> ADC_CFG1_TRIGSRC_SHIFT; + + return (ADC_TrgSrcType)u32TmpVal; +} + +/** + * @brief Set the trigger source the the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param eTriggerSource the trigger source of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetTriggerSource(ADC_Type *const pAdc, ADC_TrgSrcType eTrgSource) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_TRIGSRC_MASK) | ADC_CFG1_TRIGSRC(eTrgSource); +} + +/** + * @brief Get the trigger mode of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return ADC_TrigModeType the trigger mode if the ADC instance + */ +LOCAL_INLINE ADC_TrgModeType ADC_HWA_GetTriggerMode(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_TRIGMODE_MASK) >> ADC_CFG1_TRIGMODE_SHIFT; + + return (ADC_TrgModeType)u32TmpVal; +} + +/** + * @brief Set the trigger mode of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param eTriggerMode the trigger mode if the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetTriggerMode(ADC_Type *const pAdc, ADC_TrgModeType eTrgMode) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_TRIGMODE_MASK) | ADC_CFG1_TRIGMODE(eTrgMode); +} + +/** + * @brief Get the data align mode + * + * @param pAdc the base address of the ADC instance + * @return ADC_ALIGN_RIGHT the conversion data is aligned right + * @return ADC_ALIGN_LEFT the conversion is aligned left + */ +LOCAL_INLINE ADC_AlignType ADC_HWA_GetDataAlignment(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_ALIGN_MASK) >> ADC_CFG1_ALIGN_SHIFT; + return (ADC_AlignType)u32TmpVal; +} + +/** + * @brief Set the data align mode + * + * @param pAdc the base address of the ADC instance + * @param eAlign the data align mode + */ +LOCAL_INLINE void ADC_HWA_SetDataAlignment(ADC_Type *const pAdc, ADC_AlignType eAlign) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_ALIGN_MASK) | ADC_CFG1_ALIGN(eAlign); +} + +/** + * @brief Get the ADC resolution of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return ADC_ResolutionType the resolution of the ADC instance + */ +LOCAL_INLINE ADC_ResolutionType ADC_HWA_GetDataResolution(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_RES_MASK) >> ADC_CFG1_RES_SHIFT; + return (ADC_ResolutionType)u32TmpVal; +} + +/** + * @brief Set the resolution of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param eResolution the resolution of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetDataResolution(ADC_Type *const pAdc, ADC_ResolutionType eResolution) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_RES_MASK) | ADC_CFG1_RES(eResolution); +} + +/** + * @brief Get whether DMA for the ADC instance is enabled + * + * @param pAdc the base address of the ADC instance + * @return true DMA is enabled for the ADC instance + * @return false DMA is disabled for the ADC instance + */ +LOCAL_INLINE bool ADC_HWA_GetDMAEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_DMAEN_MASK) >> ADC_CFG1_DMAEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable or disable the DMA for the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the DMA for the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetDMAEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_DMAEN_MASK) | ADC_CFG1_DMAEN(bEnable); +} + +/** + * @brief Get the ADC_CFG1 config + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the ADC_CFG1 config + */ +LOCAL_INLINE uint32_t ADC_HWA_GetConfig1(const ADC_Type *const pAdc) +{ + return pAdc->CFG1; +} + +/** + * @brief Set the ADC_CFG1 config + * + * @param pAdc the base address of the ADC instance + * @param u32Config the ADC_CFG1 config + */ +LOCAL_INLINE void ADC_HWA_SetConfig1(ADC_Type *const pAdc, uint32_t u32Config) +{ + pAdc->CFG1 = u32Config; +} + +/** + * @brief Get the FIFO water mark settings for the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return uint8_t the ADC FIFO water mark setting + */ +LOCAL_INLINE uint8_t ADC_HWA_GetFIFOWaterMark(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_FWMARK_MASK) >> ADC_CFG2_FWMARK_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the FIFO water mark for the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param u8WaterMark the ADC FIFO water mark setting + */ +LOCAL_INLINE void ADC_HWA_SetFIFOWaterMark(ADC_Type *const pAdc, uint8_t u8WaterMark) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_FWMARK_MASK) | ADC_CFG2_FWMARK(u8WaterMark); +} + +#if ADC_SUPPORT_SG_MODE +/** + * @brief Get the priority of Trigger Latch + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE uint8_t ADC_HWA_GetTriggerLatchUnitPriority(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_TRG_PRI_MASK) >> ADC_CFG2_TRG_PRI_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the priority of Trigger Latch + * + * @param pAdc the base address of the ADC instance + * @param eTrgLatchUnitPri the priority of Trigger Latch Unit setting + */ +LOCAL_INLINE void ADC_HWA_SetTriggerLatchUnitPriority(ADC_Type *const pAdc, ADC_TrgLatchUnitPri eTrgLatchUnitPri) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_TRG_CLR_MASK) | ADC_CFG2_TRG_CLR(eTrgLatchUnitPri); +} + +/** + * @brief Clear Latch Trigger in Trigger Latch Unit + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearLatchTrigger(ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG2; + pAdc->CFG2 = u32TmpVal | ADC_CFG2_TRG_CLR(1); +} +#endif + +/** + * @brief Get whether hardware average is enabled + * + * @param pAdc the base address of the ADC instance + * @return true hardware average is enabled + * @return false hardware average is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetAverageEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_AVG_EN_MASK) >> ADC_CFG2_AVG_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable or disable hardware average for the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC hardware average + */ +LOCAL_INLINE void ADC_HWA_SetAverageEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_AVG_EN_MASK) | ADC_CFG2_AVG_EN(bEnable); +} + +/** + * @brief Get the hardware average number + * + * @param pAdc the base address of the ADC instance + * @return ADC_AverageType the hardware average number + */ +LOCAL_INLINE ADC_AverageLenType ADC_HWA_GetAverageNumber(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_AVG_LEN_MASK) >> ADC_CFG2_AVG_LEN_SHIFT; + return (ADC_AverageLenType)u32TmpVal; +} + +/** + * @brief Set the hardware average number + * + * @param pAdc the base address of the ADC instance + * @param eAverageNumber the hardware average number to set + */ +LOCAL_INLINE void ADC_HWA_SetAverageNumber(ADC_Type *const pAdc, ADC_AverageLenType eAverageNumber) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_AVG_LEN_MASK) | ADC_CFG2_AVG_LEN(eAverageNumber); +} +/** + * @brief Whether clock gating is acknowledged + * + * @note This feature is only available in FC7300F2M + * + * @param pAdc the base address of the ADC instance + * @return true ADC clock source is off after setting Clock Gating Enable Flag + * @return false ADC clock source is on after clearing Clock Gating Enable Flag + */ +LOCAL_INLINE bool ADC_HWA_GetClockGatingAck(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_CG_ACK_MASK) >> ADC_CFG2_CG_ACK_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether clock gating is enabled + * + * @note This feature is only available in FC7300F2M + * + * @param pAdc the base address of the ADC instance + * @return true Clock gating is enabled, ADC clock is off + * @return false Clock gating is disabled, ADC clock is on + */ +LOCAL_INLINE bool ADC_HWA_GetClockGatingEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_CG_MASK) >> ADC_CFG2_CG_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable ADC clock gating + * + * @note This feature is only available in FC7300F2M + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable ADC clock gating + */ +LOCAL_INLINE void ADC_HWA_SetClockGatingEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_CG_MASK) | ADC_CFG2_CG(bEnable); +} + +#if ADC_SUPPORT_INTERNAL_REFERENCE +/** + * @brief Get the voltage reference of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return ADC_REF_INTERNAL the ADC instance uses internal voltage reference + * @return ADC_REF_EXTERNAL the ADC instance uses external voltage reference + */ +LOCAL_INLINE ADC_RefType ADC_HWA_GetVoltageReference(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_REF_EXT_MASK) >> ADC_CFG2_REF_EXT_SHIFT; + return (ADC_RefType)u32TmpVal; +} + +/** + * @brief Set the voltage reference of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param eRefSel the voltage reference of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetVoltageReference(ADC_Type *const pAdc, ADC_RefType eRefSel) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_REF_EXT_MASK) | ADC_CFG2_REF_EXT(eRefSel); +} +#endif + +/** + * @brief Get the ADC clock divider + * + * @note This feature is only available in FC7300F2M + * + * @param pAdc the base address of the ADC instance + * @return ADC_ClockDivideType the ADC clock divider + */ +LOCAL_INLINE ADC_ClockDivideType ADC_HWA_GetClockDivider(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_DIV_MASK) >> ADC_CFG2_DIV_SHIFT; + return (ADC_ClockDivideType)u32TmpVal; +} + +/** + * @brief Set the ADC clock divider + * + * @note Before configuring DIV, must set CG and wait for CG_ACK=1. + * After configuring DIV, must clear CG and wait for CG_ACK=0. + * @note This feature is only available in FC7300F2M + * + * @param pAdc the base address of the ADC instance + * @param eDivider the ADC clock divider to set + */ +LOCAL_INLINE void ADC_HWA_SetClockDivider(ADC_Type *const pAdc, ADC_ClockDivideType eDivider) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_DIV_MASK) | ADC_CFG2_DIV(eDivider); +} + +/** + * @brief Get the ADC start up count + * + * @param pAdc the base address of the ADC instance + * @return uint8_t the start count of the ADC instance + */ +LOCAL_INLINE uint8_t ADC_HWA_GetStartupCnt(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_STCNT_MASK) >> ADC_CFG2_STCNT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the ADC start up count + * + * @param pAdc the base address of the ADC instance + * @param u8StartupCnt the start count of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetStartupCnt(ADC_Type *const pAdc, uint8_t u8StartupCnt) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_STCNT_MASK) | ADC_CFG2_STCNT(u8StartupCnt); +} + +/** + * @brief Get the ADC_CFG2 config + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the ADC_CFG2 config + */ +LOCAL_INLINE uint32_t ADC_HWA_GetConfig2(const ADC_Type *const pAdc) +{ + return pAdc->CFG2; +} + +/** + * @brief Set the ADC_CFG2 config + * + * @param pAdc the base address of the ADC instance + * @param u32Config the ADC_CFG2 config + */ +LOCAL_INLINE void ADC_HWA_SetConfig2(ADC_Type *const pAdc, uint32_t u32Config) +{ + pAdc->CFG2 = u32Config; +} + +/** + * @brief Get the sample time of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param u8Selection the sample time index, range 0~3 + * @return uint8_t the sample time of the selected index + */ +LOCAL_INLINE uint8_t ADC_HWA_GetSampleTime(ADC_Type *const pAdc, uint8_t u8Selection) +{ + uint32_t ret; + ret = (pAdc->SMPR & (ADC_SMPR_SMP_OPT0_MASK << (8U * u8Selection))) >> (8U * u8Selection); + return (uint8_t)ret; +} + +/** + * @brief Set the sample time of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param u8Selection the sample time index, range 0~3 + * @param u8SampleTime the sample time of the selected index + */ +LOCAL_INLINE void ADC_HWA_SetSampleTime(ADC_Type *const pAdc, uint8_t u8Selection, uint8_t u8SampleTime) +{ + DEV_ASSERT(u8Selection < ADC_SAMPLE_TIME_OPTION_CNT); + pAdc->SMPR = (pAdc->SMPR & ~(ADC_SMPR_SMP_OPT0_MASK << (8U * u8Selection))) | + (ADC_SMPR_SMP_OPT0(u8SampleTime) << (8U * u8Selection)); +} + +/** + * @brief Set the ADC hardware compare channel + * + * @param pAdc the base address of the ADC instance + * @param eChannelType whether the hardware compare enabled on single channel or all channels + * @param u8ChannalNum if hardware compare is enabled on single channel, this specifies the channel number + */ +LOCAL_INLINE void ADC_HWA_SetCmpChannel(ADC_Type *const pAdc, ADC_CmpChannelType eChannelType, + uint8_t u8ChannalNum) +{ + pAdc->CMP_CTRL = (pAdc->CMP_CTRL & (~ADC_CMP_CTRL_ACMPSGL_MASK) & (~ADC_CMP_CTRL_ACMPCH_MASK)) | + ADC_CMP_CTRL_ACMPSGL(eChannelType) | ADC_CMP_CTRL_ACMPCH(u8ChannalNum); +} + +/** + * @brief Get whether hardware compare is enabled + * + * @param pAdc the base address of the ADC instance + * @return true hardware compare is enabled + * @return false hardware compare is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetCmpEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CMP_CTRL & ADC_CMP_CTRL_ACMPEN_MASK) >> ADC_CMP_CTRL_ACMPEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set to enable or disable the hardware compare + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether the ADC hardware compare is enabled + */ +LOCAL_INLINE void ADC_HWA_SetCmpEnable(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CMP_CTRL = (pAdc->CMP_CTRL & ~ADC_CMP_CTRL_ACMPEN_MASK) | ADC_CMP_CTRL_ACMPEN(bEnable); +} + +/** + * @brief Set the ADC hardware compare threshold + * + * @param pAdc the base address of the ADC instance + * @param u16LowThres the lower threshold + * @param u16HighThres the higher threshold + */ +LOCAL_INLINE void ADC_HWA_SetCmpThreshold(ADC_Type *const pAdc, uint16_t u16LowThres, uint16_t u16HighThres) +{ + pAdc->CMP_TR = ADC_CMP_TR_LT(u16LowThres) | ADC_CMP_TR_HT(u16HighThres); +} + +#if ADC_SUPPORT_PERIOD_TRIGGER + +/** + * @brief Get the ADC period trigger interval + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the ADC period trigger interval + */ +LOCAL_INLINE uint16_t ADC_HWA_GetPeriodTriggerInterval(const ADC_Type *const pAdc) +{ + return ((pAdc->CFG3 & ADC_CFG3_PTRGIV_MASK) >> ADC_CFG3_PTRGIV_SHIFT); +} + +/** + * @brief Set the ADC period trigger interval + * + * @param pAdc the base address of the ADC instance + * @param u16Interval the ADC period trigger interval + */ +LOCAL_INLINE void ADC_HWA_SetPeriodTriggerInterval(ADC_Type *const pAdc, uint16_t u16Interval) +{ + pAdc->CFG3 = (pAdc->CFG3 & ~ADC_CFG3_PTRGIV_MASK) | ADC_CFG3_PTRGIV(u16Interval); +} + +#endif + +#if ADC_SUPPORT_SG_MODE +/** + * @brief Get the end of sequence group flag + * + * @param pAdc the base address of the ADC instance + * @param u8SGIndex the index of the sequence group + * @param bool the sequence group interrupt flag + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSGFlag(ADC_Type *const pAdc, const uint8_t u8SGIndex) +{ + uint32_t u32TmpVal = (pAdc->SGCSR[u8SGIndex] & ADC_SGCSR_EOSG_MASK) >> ADC_SGCSR_EOSG_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Clear the end of sequence group flag + * + * @param pAdc the base address of the ADC instance + * @param u8SGIndex the index of the sequence group + */ +LOCAL_INLINE void ADC_HWA_ClearEndOfSGFlag(ADC_Type *const pAdc, const uint8_t u8SGIndex) +{ + uint32_t u32TmpVal = pAdc->SGCSR[u8SGIndex]; + pAdc->SGCSR[u8SGIndex] = (u32TmpVal & ~ADC_SGCSR_EOSG_MASK) | ADC_SGCSR_EOSG(1U); +} + +/** + * @brief Set the sequence group end of sequence interrupt enable + * + * @param pAdc the base address of the ADC instance + * @param u8SGIndex the index of the sequence group + * @param bEnable the sequence group interrupt enable or disable + */ +LOCAL_INLINE void ADC_HWA_SetEndOfSGIntEnable(ADC_Type *const pAdc, const uint8_t u8SGIndex, const bool bEnable) +{ + uint32_t u32TmpVal = pAdc->SGCSR[u8SGIndex]; + pAdc->SGCSR[u8SGIndex] = (u32TmpVal & ~ADC_SGCSR_EOSGIE_MASK) | ADC_SGCSR_EOSGIE(bEnable); +} + +/** + * @brief Get the sequence group end of sequence interrupt enable + * + * @param pAdc the base address of the ADC instance + * @param u8SGIndex the index of the sequence group + * @param bEnable the sequence group interrupt enable or disable + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSGIntEnable(ADC_Type *const pAdc, const uint8_t u8SGIndex) +{ + uint32_t u32TmpVal = pAdc->SGCSR[u8SGIndex]; + u32TmpVal = (u32TmpVal & ADC_SGCSR_EOSGIE_MASK) >> ADC_SGCSR_EOSGIE_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Get the sequence group start point + * + * @param pAdc the base address of the ADC instance + * @param u8SGIndex the index of the sequence group + */ +LOCAL_INLINE uint8_t ADC_HWA_GetSGStartPoint(ADC_Type *const pAdc, const uint8_t u8SGIndex) +{ + return (uint8_t)((pAdc->SGCSR[u8SGIndex] & ADC_SGCSR_SG_START_MASK) >> ADC_SGCSR_SG_START_SHIFT); +} + +/** + * @brief Get the sequence group end point + * + * @param pAdc the base address of the ADC instance + * @param u8SGIndex the index of the sequence group + */ +LOCAL_INLINE uint8_t ADC_HWA_GetSGEndPoint(ADC_Type *const pAdc, const uint8_t u8SGIndex) +{ + return (uint8_t)((pAdc->SGCSR[u8SGIndex] & ADC_SGCSR_SG_END_MASK) >> ADC_SGCSR_SG_END_SHIFT); +} + +/** + * @brief Set the sequence group start point & end point + * + * @param pAdc the base address of the ADC instance + * @param u8SGIndex the index of the sequence group + * @param u8Start the sequence group start point + * @param u8End the sequence group end point + */ +LOCAL_INLINE void ADC_HWA_SetSGStartEndPoint(ADC_Type *const pAdc, const uint8_t u8SGIndex, const uint8_t u8Start, const uint8_t u8End) +{ + uint32_t u32TmpVal = pAdc->SGCSR[u8SGIndex]; + u32TmpVal = (u32TmpVal & ~ADC_SGCSR_SG_END_MASK) | ADC_SGCSR_SG_END(u8End); + u32TmpVal = (u32TmpVal & ~ADC_SGCSR_SG_START_MASK) | ADC_SGCSR_SG_START(u8Start); + pAdc->SGCSR[u8SGIndex] = u32TmpVal; +} +#endif + +#if ADC_SUPPORT_GAIN_AND_OFFSET_CALIBRATION +/** + * @brief Set the ADC_CAL config + * + * @param pAdc the base address of the ADC instance + * @param u32Cal the ADC_CAL config + */ +LOCAL_INLINE void ADC_HWA_SetCal(ADC_Type *const pAdc, uint32_t u32Cal) +{ + pAdc->CAL = u32Cal; +} +#endif + +/** + * @brief Get the conversion result FIFO data of the ADC instance + * + * @note only reslut data of ADC single mode and continuous mode will be stored + * in FIFO register. + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the ADC conversion result + */ +LOCAL_INLINE uint32_t ADC_HWA_GetFIFOData(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->FIFO_DATA; + u32TmpVal = (u32TmpVal & ADC_FIFO_DATA_FIFO_DATA_MASK) >> ADC_FIFO_DATA_FIFO_DATA_SHIFT; + return (uint32_t)u32TmpVal; +} + +#if ADC_SUPPORT_CHANNEL_DIFFMODE_SET +/** + * @brief Get the differential mode state of the ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return bool the state of diff mode for ADC channel + */ +LOCAL_INLINE bool ADC_HWA_GetChannelDiffModeEnable(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = (pAdc->SC[u8ChnIdx] & ADC_SC_DIFF_MASK) >> ADC_SC_DIFF_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the differential mode state of the ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @param bEnable the state of diff mode for ADC channel + */ +LOCAL_INLINE void ADC_HWA_SetChannelDiffModeEnable(ADC_Type *const pAdc, const uint8_t u8ChnIdx, const bool bEnable) +{ + pAdc->SC[u8ChnIdx] = (pAdc->SC[u8ChnIdx] & ~ADC_SC_DIFF_MASK) | ADC_SC_DIFF(bEnable); +} +#endif + +/** + * @brief Get the sample time index of the ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return uint8_t the sample time index of the ADC channel + */ +LOCAL_INLINE uint8_t ADC_HWA_GetChannelSampleTimeIndex(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = (pAdc->SC[u8ChnIdx] & ADC_SC_SMPSEL_MASK) >> ADC_SC_SMPSEL_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the sample time index of the ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @param u8SmpSel the sample time index of the ADC channel + */ +LOCAL_INLINE void ADC_HWA_SetChannelSampleTimeIndex(ADC_Type *const pAdc, const uint8_t u8ChnIdx, uint8_t u8SmpSel) +{ + pAdc->SC[u8ChnIdx] = (pAdc->SC[u8ChnIdx] & ~ADC_SC_SMPSEL_MASK) | ADC_SC_SMPSEL(u8SmpSel); +} + +/** + * @brief Get the channel conversion complete status of the ADC instance + * + * @note this function is used only in ADC discontinuous mode to get the channel complete + * status + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return true the ADC conversion on the selected channel is completed + * @return false the ADC conversion on the selected channel is not completed + */ +LOCAL_INLINE bool ADC_HWA_GetChannelCoCoFlag(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pAdc->SC[u8ChnIdx]; + u32TmpVal = (u32TmpVal & ADC_SC_COCO_MASK) >> ADC_SC_COCO_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether interrupt is enabled on the selected ADC channel + * + * @note this function is used only in ADC discontinuous mode to get the channel interrupt + * settings + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return true interrupt is enabled on the selected channel + * @return false interrupt is disabled on the selected channel + */ +LOCAL_INLINE bool ADC_HWA_GetChannelCoCoIntEnable(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pAdc->SC[u8ChnIdx]; + u32TmpVal = (u32TmpVal & ADC_SC_AIEN_MASK) >> ADC_SC_AIEN_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set to enable or disable interrupt on the selected ADC channel + * + * @note this function is used only in ADC discontinuous mode to get the channel interrupt + * settings + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @param bEnable whether to enable interrupt on the selected ADC channel + */ +LOCAL_INLINE void ADC_HWA_SetChannelCoCoIntEnable(ADC_Type *const pAdc, const uint8_t u8ChnIdx, bool bEnable) +{ + pAdc->SC[u8ChnIdx] = (pAdc->SC[u8ChnIdx] & ~ADC_SC_AIEN_MASK) | ADC_SC_AIEN(bEnable); +} + +/** + * @brief Get the input channel of the selected ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return uint8_t the hardware input channel + */ +LOCAL_INLINE uint8_t ADC_HWA_GetChannelInput(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = (pAdc->SC[u8ChnIdx] & ADC_SC_CHS_MASK) >> ADC_SC_CHS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the input channel to the selected ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @param u8InputChannel the hardware input channel + */ +LOCAL_INLINE void ADC_HWA_SetChannelInput(ADC_Type *const pAdc, const uint8_t u8ChnIdx, uint8_t u8InputChannel) +{ + pAdc->SC[u8ChnIdx] = (pAdc->SC[u8ChnIdx] & ~ADC_SC_CHS_MASK) | ADC_SC_CHS(u8InputChannel); +} + +/** + * @brief Get the conversion result data of the ADC instance + * + * @note only result data of ADC discontinuous mode will be stored in RESULTn register. + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the ADC channel + * @return uint32_t the ADC conversion result + */ +LOCAL_INLINE uint32_t ADC_HWA_GetChannelData(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pAdc->RESULT[u8ChnIdx]; + u32TmpVal = (u32TmpVal & ADC_RESULT_RESULT_MASK) >> ADC_RESULT_RESULT_SHIFT; + + return (uint32_t)u32TmpVal; +} + +#if ADC_SUPPORT_ENHANCED_CMP_BLOCK +/** + * @brief Set the enhanced comparator option + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @param eOption the option of the enhanced comparator + * @return non + */ +LOCAL_INLINE void ADC_HWA_SetECMPOption(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index, ADC_ECMPOption eOption) +{ + uint32_t u32TmpVal = pAdc->ECMP_CTRL[u8Index]; + u32TmpVal = (u32TmpVal & ~ADC_ECMP_CTRL_CMPOPT_MASK) | ADC_ECMP_CTRL_CMPOPT(eOption); + pAdc->ECMP_CTRL[u8Index] = u32TmpVal; +} + +/** + * @brief Enabld/disable the enhanced comparator + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @param bEnable the option of the enhanced comparator + * @return non + */ +LOCAL_INLINE void ADC_HWA_SetECMPEnable(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index, bool bEnable) +{ + uint32_t u32TmpVal = pAdc->ECMP_CTRL[u8Index]; + u32TmpVal = (u32TmpVal & ~ADC_ECMP_CTRL_CMPEN_MASK) | ADC_ECMP_CTRL_CMPEN(bEnable); + pAdc->ECMP_CTRL[u8Index] = u32TmpVal; +} + +/** + * @brief Set the enhanced comparator channel type selection + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @param eType the selection of channel type selection + * @return non + */ +LOCAL_INLINE void ADC_HWA_SetECMPSGL(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index, ADC_ECmpChannelType eType) +{ + uint32_t u32TmpVal = pAdc->ECMP_CTRL[u8Index]; + u32TmpVal = (u32TmpVal & ~ADC_ECMP_CTRL_CMPSGL_MASK) | ADC_ECMP_CTRL_CMPSGL(eType); + pAdc->ECMP_CTRL[u8Index] = u32TmpVal; +} + +/** + * @brief Set the enhanced comparator channel selection + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @param u8Channel the selection of channel + * @return non + */ +LOCAL_INLINE void ADC_HWA_SetECMPChannel(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index, uint8_t u8Channel) +{ + uint32_t u32TmpVal = pAdc->ECMP_CTRL[u8Index]; + u32TmpVal = (u32TmpVal & ~ADC_ECMP_CTRL_CMPCH_MASK) | ADC_ECMP_CTRL_CMPCH(u8Channel); + pAdc->ECMP_CTRL[u8Index] = u32TmpVal; +} + +/** + * @brief Get the enhanced comparator high flag + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @return bool the flag of enhanced comparator high + */ +LOCAL_INLINE bool ADC_HWA_GetECMPHighFlag(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index) +{ + uint32_t u32TmpVal = pAdc->ECMP_STATUS; + if (u8Index == ADC_ECMP0) + u32TmpVal = (u32TmpVal & ADC_ECMP_STATUS_CMPH0_MASK); + else if (u8Index == ADC_ECMP1) + u32TmpVal = (u32TmpVal & ADC_ECMP_STATUS_CMPH1_MASK); + return u32TmpVal ? true : false; +} + +/** + * @brief Get the enhanced comparator low flag + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @return bool the flag of enhanced comparator low + */ +LOCAL_INLINE bool ADC_HWA_GetECMPLowFlag(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index) +{ + uint32_t u32TmpVal = pAdc->ECMP_STATUS; + if (u8Index == ADC_ECMP0) + u32TmpVal = (u32TmpVal & ADC_ECMP_STATUS_CMPL0_MASK); + else if (u8Index == ADC_ECMP1) + u32TmpVal = (u32TmpVal & ADC_ECMP_STATUS_CMPL1_MASK); + return u32TmpVal ? true : false; +} + +/** + * @brief Get the enhanced comparator window flag + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @return bool the flag of enhanced comparator window + */ +LOCAL_INLINE bool ADC_HWA_GetECMPWinFlag(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index) +{ + uint32_t u32TmpVal = pAdc->ECMP_STATUS; + if (u8Index == ADC_ECMP0) + u32TmpVal = (u32TmpVal & ADC_ECMP_STATUS_CMPW0_MASK); + else if (u8Index == ADC_ECMP1) + u32TmpVal = (u32TmpVal & ADC_ECMP_STATUS_CMPW1_MASK); + return u32TmpVal ? true : false; +} + +/** + * @brief Clear the enhanced comparator high flag + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @return non + */ +LOCAL_INLINE void ADC_HWA_ClearECMPHighFlag(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index) +{ + if (u8Index == ADC_ECMP0) + pAdc->ECMP_STATUS = ADC_ECMP_STATUS_CMPH0_MASK; + else if (u8Index == ADC_ECMP1) + pAdc->ECMP_STATUS = ADC_ECMP_STATUS_CMPH1_MASK; +} + +/** + * @brief Clear the enhanced comparator low flag + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @return non + */ +LOCAL_INLINE void ADC_HWA_ClearECMPLowFlag(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index) +{ + if (u8Index == ADC_ECMP0) + pAdc->ECMP_STATUS = ADC_ECMP_STATUS_CMPL0_MASK; + else if (u8Index == ADC_ECMP1) + pAdc->ECMP_STATUS = ADC_ECMP_STATUS_CMPL1_MASK; +} + +/** + * @brief Clear the enhanced comparator window flag + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @return non + */ +LOCAL_INLINE void ADC_HWA_ClearECMPWinFlag(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index) +{ + if (u8Index == ADC_ECMP0) + pAdc->ECMP_STATUS = ADC_ECMP_STATUS_CMPW0_MASK; + else if (u8Index == ADC_ECMP1) + pAdc->ECMP_STATUS = ADC_ECMP_STATUS_CMPW1_MASK; +} + +/** + * @brief Set the enhanced comparator high interrupt enable + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @param bEnable the enable status of enhanced comparator high interrupt + */ +LOCAL_INLINE void ADC_HWA_SetECMPHighIntEnable(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index, bool bEnable) +{ + uint32_t u32TmpVal = pAdc->ECMP_INT_EN; + if (u8Index == ADC_ECMP0) + u32TmpVal = (u32TmpVal & ~ADC_ECMP_INT_EN_CMPH_IE0_MASK) | ADC_ECMP_INT_EN_CMPH_IE0(bEnable); + else if (u8Index == ADC_ECMP1) + u32TmpVal = (u32TmpVal & ~ADC_ECMP_INT_EN_CMPH_IE1_MASK) | ADC_ECMP_INT_EN_CMPH_IE1(bEnable); + pAdc->ECMP_INT_EN = u32TmpVal; +} + +/** + * @brief Get the enhanced comparator high interrupt enable status + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @return bool the enable status of enhanced comparator high interrupt + */ +LOCAL_INLINE bool ADC_HWA_GetECMPHighIntEnable(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index) +{ + uint32_t u32TmpVal = pAdc->ECMP_INT_EN; + if (u8Index == ADC_ECMP0) + u32TmpVal = u32TmpVal & ADC_ECMP_INT_EN_CMPH_IE0_MASK; + else if (u8Index == ADC_ECMP1) + u32TmpVal = u32TmpVal & ADC_ECMP_INT_EN_CMPH_IE1_MASK; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the enhanced comparator low interrupt enable + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @param bEnable the enable status of enhanced comparator low interrupt + */ +LOCAL_INLINE void ADC_HWA_SetECMPLowIntEnable(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index, bool bEnable) +{ + uint32_t u32TmpVal = pAdc->ECMP_INT_EN; + if (u8Index == ADC_ECMP0) + u32TmpVal = (u32TmpVal & ~ADC_ECMP_INT_EN_CMPL_IE0_MASK) | ADC_ECMP_INT_EN_CMPL_IE0(bEnable); + else if (u8Index == ADC_ECMP1) + u32TmpVal = (u32TmpVal & ~ADC_ECMP_INT_EN_CMPL_IE1_MASK) | ADC_ECMP_INT_EN_CMPL_IE1(bEnable); + pAdc->ECMP_INT_EN = u32TmpVal; +} + +/** + * @brief Get the enhanced comparator low interrupt enable status + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @return bool the enable status of enhanced comparator low interrupt + */ +LOCAL_INLINE bool ADC_HWA_GetECMPLowIntEnable(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index) +{ + uint32_t u32TmpVal = pAdc->ECMP_INT_EN; + if (u8Index == ADC_ECMP0) + u32TmpVal = u32TmpVal & ADC_ECMP_INT_EN_CMPL_IE0_MASK; + else if (u8Index == ADC_ECMP1) + u32TmpVal = u32TmpVal & ADC_ECMP_INT_EN_CMPL_IE1_MASK; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the enhanced comparator window interrupt enable + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @param bEnable the enable status of enhanced comparator window interrupt + */ +LOCAL_INLINE void ADC_HWA_SetECMPWinIntEnable(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index, bool bEnable) +{ + uint32_t u32TmpVal = pAdc->ECMP_INT_EN; + if (u8Index == ADC_ECMP0) + u32TmpVal = (u32TmpVal & ~ADC_ECMP_INT_EN_CMPW_IE0_MASK) | ADC_ECMP_INT_EN_CMPW_IE0(bEnable); + else if (u8Index == ADC_ECMP1) + u32TmpVal = (u32TmpVal & ~ADC_ECMP_INT_EN_CMPW_IE1_MASK) | ADC_ECMP_INT_EN_CMPW_IE1(bEnable); + pAdc->ECMP_INT_EN = u32TmpVal; +} + +/** + * @brief Get the enhanced comparator window interrupt enable status + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @return bool the enable status of enhanced comparator window interrupt + */ +LOCAL_INLINE bool ADC_HWA_GetECMPWinIntEnable(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index) +{ + uint32_t u32TmpVal = pAdc->ECMP_INT_EN; + if (u8Index == ADC_ECMP0) + u32TmpVal = u32TmpVal & ADC_ECMP_INT_EN_CMPW_IE0_MASK; + else if (u8Index == ADC_ECMP1) + u32TmpVal = u32TmpVal & ADC_ECMP_INT_EN_CMPW_IE1_MASK; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the enhanced comparator threshold + * + * @param pAdc the base address of the ADC instance + * @param u8Index the index of the enhanced comparator block + * @param u16LowThres the low threshold of the enhanced comparator + * @param u16HighThres the high threshold of the enhanced comparator + */ +LOCAL_INLINE void ADC_HWA_SetECMPThreshold(ADC_Type *const pAdc, const ADC_ECMPIndex u8Index, uint16_t u16LowThres, uint16_t u16HighThres) +{ + uint32_t u32TmpVal = pAdc->ECMP_TR[u8Index]; + u32TmpVal = ADC_ECMP_TR_HT(u16HighThres) | ADC_ECMP_TR_LT(u16LowThres); + pAdc->ECMP_TR[u8Index] = u32TmpVal; +} +#endif + +#if ADC_SUPPORT_FAST_CMP_BLOCK +/** + * @brief Get the fast compare enable + * + * @note + * + * @param pAdc the base address of the ADC instance + * @return bool whether the ADC fast compare enable + */ +LOCAL_INLINE bool ADC_HWA_GetFCEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->FCMP_CTRL & ADC_FCMP_CTRL_FC_EN_MASK) >> ADC_FCMP_CTRL_FC_EN_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the fast compare reference of the ADC instance + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param enable whether the ADC fast compare enable + * @return none + */ +LOCAL_INLINE void ADC_HWA_SetFCEnable(ADC_Type *const pAdc, bool enable) +{ + pAdc->FCMP_CTRL = (pAdc->FCMP_CTRL & ~ADC_FCMP_CTRL_FC_EN_MASK) | ADC_FCMP_CTRL_FC_EN(enable); +} + +/** + * @brief Set the fast compare control register + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param value control register value + * @return none + */ +LOCAL_INLINE void ADC_HWA_SetFCCtrl(ADC_Type *const pAdc, uint32_t value) +{ + pAdc->FCMP_CTRL = value; +} + +/** + * @brief Get the fast compare reference of the ADC instance + * + * @note + * + * @param pAdc the base address of the ADC instance + * @return int16_t the ADC fast compare reference + */ +LOCAL_INLINE int16_t ADC_HWA_GetFCRef(const ADC_Type *const pAdc) +{ + return (pAdc->FCREF & ADC_FCREF_FCREF_MASK) >> ADC_FCREF_FCREF_SHIFT; +} + +/** + * @brief Set the fast compare reference of the ADC instance + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param ref the index of the ADC channel + * @return none + */ +LOCAL_INLINE void ADC_HWA_SetFCRef(ADC_Type *const pAdc, uint16_t ref) +{ + pAdc->FCREF = (pAdc->FCREF & ~ADC_FCREF_FCREF_MASK) | ADC_FCREF_FCREF(ref); +} + +/** + * @brief Get the fast compare ramp reference A of the ADC instance + * + * @note + * + * @param pAdc the base address of the ADC instance + * @return int16_t the ADC fast compare ramp reference A + */ +LOCAL_INLINE int16_t ADC_HWA_GetFCRampRefA(const ADC_Type *const pAdc) +{ + return (pAdc->FCRAMP0 & ADC_FCRAMP0_FCREF_A_MASK) >> ADC_FCRAMP0_FCREF_A_SHIFT; +} + +/** + * @brief Set the fast compare ramp reference A of the ADC instance + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param ref the ADC fast compare ramp reference A + * @return none + */ +LOCAL_INLINE void ADC_HWA_SetFCRampRefA(ADC_Type *const pAdc, uint16_t ref) +{ + pAdc->FCRAMP0 = (pAdc->FCRAMP0 & ~ADC_FCRAMP0_FCREF_A_MASK) | ADC_FCRAMP0_FCREF_A(ref); +} + +/** + * @brief Get the fast compare ramp step of the ADC instance + * + * @note + * + * @param pAdc the base address of the ADC instance + * @return uint8_t the ADC fast compare ramp step + */ +LOCAL_INLINE uint8_t ADC_HWA_GetFCRampStep(const ADC_Type *const pAdc) +{ + return (pAdc->FCRAMP0 & ADC_FCRAMP0_RPSTEP_MASK) >> ADC_FCRAMP0_RPSTEP_SHIFT; +} + +/** + * @brief Set the fast compare ramp step + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param step the ADC fast compare ramp step + * @return none + */ +LOCAL_INLINE void ADC_HWA_SetFCRampStep(ADC_Type *const pAdc, uint16_t step) +{ + pAdc->FCRAMP0 = (pAdc->FCRAMP0 & ~ADC_FCRAMP0_RPSTEP_MASK) | ADC_FCRAMP0_RPSTEP(step); +} + +/** + * @brief Set the fast compare ramp0 register + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param value the ADC fast compare ramp0 register value + * @return none + */ +LOCAL_INLINE void ADC_HWA_SetFCRamp0(ADC_Type *const pAdc, uint32_t value) +{ + pAdc->FCRAMP0 = value; +} + +/** + * @brief Get the fast compare ramp reference B of the ADC instance + * + * @note + * + * @param pAdc the base address of the ADC instance + * @return int16_t the ADC fast compare ramp reference B + */ +LOCAL_INLINE int16_t ADC_HWA_GetFCRampRefB(const ADC_Type *const pAdc) +{ + return (pAdc->FCRAMP1 & ADC_FCRAMP1_FCREF_B_MASK) >> ADC_FCRAMP1_FCREF_B_SHIFT; +} + +/** + * @brief Set the fast compare ramp reference B of the ADC instance + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param ref the ADC fast compare ramp reference B + * @return none + */ +LOCAL_INLINE void ADC_HWA_SetFCRampRefB(ADC_Type *const pAdc, uint16_t ref) +{ + pAdc->FCRAMP1 = (pAdc->FCRAMP1 & ~ADC_FCRAMP1_FCREF_B_MASK) | ADC_FCRAMP1_FCREF_B(ref); +} + +/** + * @brief Get the fast compare ramp dir + * + * @note + * + * @param pAdc the base address of the ADC instance + * @return ADC_FCmpRampDir the ADC fast compare ramp dir + */ +LOCAL_INLINE ADC_FCmpRampDir ADC_HWA_GetFCRampDir(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->FCRAMP1 & ADC_FCRAMP1_RPDIR_MASK) >> ADC_FCRAMP1_RPDIR_SHIFT; + return u32TmpVal ? ADC_FCMP_RAMPDIR_DOWN : ADC_FCMP_RAMPDIR_UP; +} + +/** + * @brief Set the fast compare ramp dir + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param dir the ADC fast compare ramp dir + * @return none + */ +LOCAL_INLINE void ADC_HWA_SetFCRampDir(ADC_Type *const pAdc, ADC_FCmpRampDir dir) +{ + pAdc->FCRAMP1 = (pAdc->FCRAMP1 & ~ADC_FCRAMP1_RPDIR_MASK) | ADC_FCRAMP1_RPDIR(dir); +} + +/** + * @brief Set the fast compare ramp1 register + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param value the ADC fast compare ramp1 register value + * @return none + */ +LOCAL_INLINE void ADC_HWA_SetFCRamp1(ADC_Type *const pAdc, uint32_t value) +{ + pAdc->FCRAMP1 = value; +} + +/** + * @brief Get the fast compare reference upper delta + * + * @note + * + * @param pAdc the base address of the ADC instance + * @return uint16_t the ADC fast compare ref upper delta + */ +LOCAL_INLINE uint16_t ADC_HWA_GetFCRefDeltaP(const ADC_Type *const pAdc) +{ + return (pAdc->FCHYST & ADC_FCHYST_DELTAP_MASK) >> ADC_FCHYST_DELTAP_SHIFT; +} + +/** + * @brief Set the fast compare reference upper delta + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param delta the ADC fast compare ref upper delta + * @return none + */ +LOCAL_INLINE void ADC_HWA_SetFCRefDeltaP(ADC_Type *const pAdc, uint16_t delta) +{ + pAdc->FCHYST = (pAdc->FCHYST & ~ADC_FCHYST_DELTAP_MASK) | ADC_FCHYST_DELTAP(delta); +} + +/** + * @brief Get the fast compare reference lower delta + * + * @note + * + * @param pAdc the base address of the ADC instance + * @return uint16_t the ADC fast compare ref lower delta + */ +LOCAL_INLINE uint16_t ADC_HWA_GetFCRefDeltaN(const ADC_Type *const pAdc) +{ + return (pAdc->FCHYST & ADC_FCHYST_DELTAN_MASK) >> ADC_FCHYST_DELTAN_SHIFT; +} + +/** + * @brief Set the fast compare reference lower delta + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param delta the ADC fast compare ref lower delta + * @return none + */ +LOCAL_INLINE void ADC_HWA_SetFCRefDeltaN(ADC_Type *const pAdc, uint16_t delta) +{ + pAdc->FCHYST = (pAdc->FCHYST & ~ADC_FCHYST_DELTAN_MASK) | ADC_FCHYST_DELTAN(delta); +} + +/** + * @brief Set the fast compare reference hysteresis + * + * @note + * + * @param pAdc the base address of the ADC instance + * @param u32Hyst the ADC fast compare reference hysteresis + * @return none + */ +LOCAL_INLINE void ADC_HWA_SetFCHysteresis(ADC_Type *const pAdc, uint32_t u32Hyst) +{ + pAdc->FCHYST = u32Hyst; +} + +/** + * @brief Get the fast compare result + * + * @note + * + * @param pAdc the base address of the ADC instance + * @return bool fast compare result + */ +LOCAL_INLINE bool ADC_HWA_GetFCResult(ADC_Type *const pAdc) +{ + return (bool)((pAdc->FCBFR & ADC_FCBFR_FCR_MASK) >> ADC_FCBFR_FCR_SHIFT); +} + +/** + * @brief Get the fast compare boundary flag + * + * @note + * + * @param pAdc the base address of the ADC instance + * @return bool fast compare boundary flag + */ +LOCAL_INLINE bool ADC_HWA_GetFCBoundaryFlag(ADC_Type *const pAdc) +{ + return (bool)((pAdc->FCBFR & ADC_FCBFR_BFL_MASK) >> ADC_FCBFR_BFL_SHIFT); +} +#endif /* ADC_SUPPORT_FAST_CMP_BLOCK */ + +#if ADC_SUPPORT_GROUP_INJECTION +/** + * @brief Trigger sequence group 0 injection + * + * @note + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_TriggerSG0Injection(ADC_Type *const pAdc) +{ + pAdc->CFG2 = pAdc->CFG2 | ADC_CFG2_STRIG_INJT_MASK; +} +#endif + +/** @}*/ + +#endif /* #if ADC_INSTANCE_COUNT > 0U */ + +#endif /* _HWA_ADC_H_ */ diff --git a/Inc/HwA_aontimer.h b/Inc/HwA_aontimer.h new file mode 100644 index 0000000..1475870 --- /dev/null +++ b/Inc/HwA_aontimer.h @@ -0,0 +1,352 @@ +/** + * @file HwA_aontimer.h + * @author Flagchip + * @brief aontimer hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip076 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip076 N/A Change version and release + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_AONTIMER_H_ +#define HWA_INCLUDE_HWA_AONTIMER_H_ + +#include "device_header.h" + +#if AONTIMER_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_aontimer HwA_aontimer + * @ingroup module_driver_aontimer + * @{ + * + */ + +/********* Local typedef ************/ +/** + * @brief The clock source of the pulse mode + * + */ +typedef enum +{ + + AONTIMER_CLK0_PIN = 0, /*!< select the Aontimer_clk0 pin as pulse sourse*/ + AONTIMER_CLK1_PIN, /*!< select the Aontimer_clk1 pin as pulse sourse*/ + AONTIMER_CLK2_PIN, /*!< select the Aontimer_clk2 pin as pulse sourse*/ + AONTIMER_TRGSEL_OUTPUT, /*!< select the tresel as pulse sourse*/ + +} AONTIMER_PulseClkSrcType; + +/** + * @brief Aontimer clock source, please refer to Reference Manual chapter8.Aontimer for details. + * + * */ +typedef enum +{ + AONTIMER_SIRC_1MHZ = 0U, /*!< AONTIMER SIRC 1mhz clock */ + AONTIMER_RTC_CLK = 2U, /*!< AONTIMER RTC clock */ + AONTIMER_IRC_CLK = 3U /*!< AONTIMER internal clock, which comes from PCC */ +} AONTIMER_ClkSrcType; + +/** + * @brief The polarity of pulse mode + * + * */ +typedef enum +{ + AONTIMER_PulsePolarityType_HIGH = 0, /*!< select the high polarity */ + AONTIMER_PulsePolarityType_LOW /*!< select the low polarity */ +} AONTIMER_PulsePolarityType; + +/********* Local inline function ************/ +/** + * @brief Configure AONTIMER module + * + * @param pAontimer the base address of the pAontimer instance. + * @param u32RegValue CSR register value + */ +LOCAL_INLINE void AONTIMER_HWA_ConfigModule(AONTIMER_Type *const pAontimer, uint32_t u32RegValue) +{ + pAontimer->CSR = u32RegValue; +} + +/** + * @brief Configure AONTIMER module prescale + * + * @param pAontimer the base address of the pAontimer instance. + * @param u32RegValue PSR register value + */ +LOCAL_INLINE void AONTIMER_HWA_ConfigModulePrescale(AONTIMER_Type *const pAontimer, uint32_t u32RegValue) +{ + pAontimer->PSR = u32RegValue; +} + +/** + * @brief Set AONTIMER compare value + * + * @param pAontimer the base address of the pAontimer instance. + * @param u32RegValue CMR register value + */ +LOCAL_INLINE void AONTIMER_HWA_SetModuleCompareValue(AONTIMER_Type *const pAontimer, uint32_t u32RegValue) +{ + pAontimer->CMR = u32RegValue; +} + +/** + * @brief Set AONTIMER current counter value + * + * @param pAontimer the base address of the pAontimer instance. + * @param u32RegValue CNR register value + */ +LOCAL_INLINE void AONTIMER_HWA_SetModuleCounterValue(AONTIMER_Type *const pAontimer, uint32_t u32RegValue) +{ + pAontimer->CNR = u32RegValue; +} + +/** + * @brief Set AONTIMER module running on debug mode + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_SetModuleRunOnDebug(AONTIMER_Type *const pAontimer) +{ + uint32_t u32RegValue = pAontimer->CSR; + u32RegValue |= (uint32_t)AONTIMER_CSR_DBGEN_MASK; + u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK; + pAontimer->CSR = u32RegValue; +} + +/** + * @brief Enable AONTIMER module interrupt + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_EnableModuleInterrupt(AONTIMER_Type *const pAontimer) +{ + uint32_t u32RegValue = pAontimer->CSR; + u32RegValue |= (uint32_t)AONTIMER_CSR_TIE_MASK; + u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK; + pAontimer->CSR = u32RegValue; +} + +/** + * @brief Select AONTIMER module external clock source when timer configured to pulse mode + * + * @param pAontimer the base address of the pAontimer instance. + * @param eClk Input counter clock source + */ +LOCAL_INLINE void AONTIMER_HWA_SelectClkSrcOnPulseMode(AONTIMER_Type *const pAontimer, AONTIMER_PulseClkSrcType eClk) +{ + uint32_t u32RegValue = pAontimer->CSR; + u32RegValue |= (u32RegValue & ~(uint32_t)AONTIMER_CSR_TPS_MASK) | AONTIMER_CSR_TPS(eClk); + u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK; + pAontimer->CSR = u32RegValue; +} + +/** + * @brief Clear AONTIMER interrupt flags + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_ClearInterruptFlag(AONTIMER_Type *const pAontimer) +{ + pAontimer->CSR |= (uint32_t)AONTIMER_CSR_TCF_MASK; +} + +/** + * @brief Set AONTIMER module polarity. Pulse counter input source is active-low, and the CNR increments on falling-edge. + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_SetModulePolarity(AONTIMER_Type *const pAontimer) +{ + uint32_t u32RegValue = pAontimer->CSR; + u32RegValue |= (uint32_t)AONTIMER_CSR_TPP_MASK; + u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK; + pAontimer->CSR = u32RegValue; +} + +/** + * @brief Configure AONTIMER module polarity. If ePol is 0:Pulse counter input source is active-high, and the CNR increments on rising-edge. + * If ePol is 1:Pulse counter input source is active-low, and the CNR increments on falling-edge. + * + * @param pAontimer the base address of the pAontimer instance. + * @param ePol Polarity enumeration + */ +LOCAL_INLINE void AONTIMER_HWA_ConfigModulePolarity(AONTIMER_Type *const pAontimer, AONTIMER_PulsePolarityType ePol) +{ + uint32_t u32RegValue = pAontimer->CSR; + u32RegValue |= AONTIMER_CSR_TPP(ePol); + u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK; + pAontimer->CSR = u32RegValue; +} + +/** + * @brief Enable AONTIMER module pulse mode + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_EnablePulseMode(AONTIMER_Type *const pAontimer) +{ + uint32_t u32RegValue = pAontimer->CSR; + u32RegValue |= (uint32_t)AONTIMER_CSR_TMS_MASK; + u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK; + pAontimer->CSR = u32RegValue; +} + +/** + * @brief Enable AONTIMER timer + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_EnableTimer(AONTIMER_Type *const pAontimer) +{ + uint32_t u32RegValue = pAontimer->CSR; + u32RegValue |= (uint32_t)AONTIMER_CSR_TEN_MASK; + u32RegValue &= ~(uint32_t)AONTIMER_CSR_TCF_MASK; + pAontimer->CSR = u32RegValue; +} + +/** + * @brief Set AONTIMER prescale + * + * @param pAontimer the base address of the pAontimer instance. + * @param u8PrescalerValue Prescaler value,the range of the input value is :0~15, and the range of prescaler is :2^1 ~ 2^16. + */ +LOCAL_INLINE void AONTIMER_HWA_SetPrescale(AONTIMER_Type *const pAontimer, uint8_t u8PrescalerValue) +{ + uint32_t u32RegValue = pAontimer->PSR; + pAontimer->PSR = ((u32RegValue & ~(uint32_t)AONTIMER_PSR_PRESCALE_MASK) | AONTIMER_PSR_PRESCALE(u8PrescalerValue)); +} + +/** + * @brief If enable bypass mode, the timer will bypass the prescaler in timer counter mode or glitch filter in pulse mode + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_EnableBypassMode(AONTIMER_Type *const pAontimer) +{ + pAontimer->PSR |= (uint32_t)AONTIMER_PSR_PBYP_MASK; +} + +/** + * @brief Select AONTIMER mdoule clock source + * + * @param pAontimer the base address of the pAontimer instance. + * @param eClk Aontimer clock source + */ +LOCAL_INLINE void AONTIMER_HWA_SelectModuleClkSrc(AONTIMER_Type *const pAontimer, AONTIMER_ClkSrcType eClk) +{ + uint32_t u32RegValue = pAontimer->PSR; + pAontimer->PSR = ((u32RegValue & ~(uint32_t)AONTIMER_PSR_PCS_MASK) | AONTIMER_PSR_PCS(eClk)); +} + +/** + * @brief Set AONTIMER module stop on debug mode + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_SetModuleStopOnDebug(AONTIMER_Type *const pAontimer) +{ + pAontimer->CSR &= ~(uint32_t)(AONTIMER_CSR_DBGEN_MASK | AONTIMER_CSR_TCF_MASK); +} + + +/** + * @brief Disable AONTIMER module interrupt + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_DisableModuleInterrupt(AONTIMER_Type *const pAontimer) +{ + pAontimer->CSR &= ~(uint32_t)(AONTIMER_CSR_TIE_MASK | AONTIMER_CSR_TCF_MASK); +} + +/** + * @brief Clear AONTIMER module mode + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_ClearModuleMode(AONTIMER_Type *const pAontimer) +{ + pAontimer->CSR &= ~(uint32_t)(AONTIMER_CSR_TPS_MASK | AONTIMER_CSR_TCF_MASK); +} + +/** + * @brief Clear AONTIMER module polarity. Pulse counter input source is active-high, and the CNR increments on rising-edge. + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_ClearModulePolarity(AONTIMER_Type *const pAontimer) +{ + pAontimer->CSR &= ~(uint32_t)(AONTIMER_CSR_TPP_MASK | AONTIMER_CSR_TCF_MASK); +} + +/** + * @brief Disable AONTIEMR module pulse mode + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_DisablePulseMode(AONTIMER_Type *const pAontimer) +{ + pAontimer->CSR &= ~(uint32_t)(AONTIMER_CSR_TMS_MASK | AONTIMER_CSR_TCF_MASK); +} + +/** + * @brief Disable AONTIMER module timer + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_DisableTimer(AONTIMER_Type *const pAontimer) +{ + pAontimer->CSR &= ~(uint32_t)(AONTIMER_CSR_TEN_MASK | AONTIMER_CSR_TCF_MASK); +} + +/** + * @brief Clear AONTIMER module prescaler + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_ClearPrescale(AONTIMER_Type *const pAontimer) +{ + pAontimer->PSR &= ~(uint32_t)AONTIMER_PSR_PRESCALE_MASK; +} + +/** + * @brief If disable bypass mode, the timer will enable the prescaler in timer counter mode or glitch filter in pulse mode + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_DisableBypassMode(AONTIMER_Type *const pAontimer) +{ + pAontimer->PSR &= ~(uint32_t)AONTIMER_PSR_PBYP_MASK; +} + +/** + * @brief Clear AONTIMER module clock source + * + * @param pAontimer the base address of the pAontimer instance. + */ +LOCAL_INLINE void AONTIMER_HWA_ClearModuleClkSrc(AONTIMER_Type *const pAontimer) +{ + pAontimer->PSR &= ~(uint32_t)AONTIMER_PSR_PCS_MASK; +} + +/** @}*/ /* HwA_AONTIMER */ + +#endif /* #if AONTIMER_INSTANCE_COUNT > 0U */ + +#endif /* HWA_INCLUDE_HWA_AONTIMER_H_ */ diff --git a/Inc/HwA_cm7.h b/Inc/HwA_cm7.h new file mode 100644 index 0000000..8f20a38 --- /dev/null +++ b/Inc/HwA_cm7.h @@ -0,0 +1,42 @@ +/** + * @file HwA_cm7.h + * @author Flagchip + * @brief cortex m4 hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +#ifndef _HWA_CM7_H_ +#define _HWA_CM7_H_ + +#include "device_header.h" + +/** + * @brief Enable deepsleep mode + * + */ +LOCAL_INLINE void CM7_HWA_EnableDeepSleep(void) +{ + SCB->SCR |= (uint32_t)SCB_SCR_SLEEPDEEP_Msk; +} + +/** + * @brief Disable deepsleep mode + * + */ +LOCAL_INLINE void CM7_HWA_DisableDeepSleep(void) +{ + SCB->SCR &= ~(uint32_t)SCB_SCR_SLEEPDEEP_Msk; +} + + + + +#endif /* #ifndef _HWA_CM7_H_ */ diff --git a/Inc/HwA_cmp.h b/Inc/HwA_cmp.h new file mode 100644 index 0000000..1941127 --- /dev/null +++ b/Inc/HwA_cmp.h @@ -0,0 +1,988 @@ +/** + * @file HwA_cmp.h + * @author Flagchip + * @brief CMP driver type definition and API + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip055 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip055 N/A Change version and release + ******************************************************************************** */ + + +#ifndef _HWA_CMP_H_ +#define _HWA_CMP_H_ + +#include "device_header.h" + +#if CMP_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_cmp HwA_cmp + * @ingroup module_driver_cmp + * @{ + * + */ + +/********* Local typedef ************/ + +/** + * @brief The instance index of the CMP mode + */ +typedef enum +{ + CMP_MODE_DISABLE = 0U, /*!< CMP function mode is disable */ + CMP_MODE_CONTINUOUS = 1U, /*!< CMP function mode is continuous */ + CMP_MODE_SAMPLE_NONFILTER_EXTCLK = 2U, /*!< CMP function mode is sampled,non-filtered mode 1*/ + CMP_MODE_SAMPLE_NONFILTER_INTCLK = 3U, /*!< CMP function mode is sampled,non-filtered mode 2*/ + CMP_MODE_SAMPLE_FILTER_EXTCLK = 4U, /*!< CMP function mode is sampled,filtered mode 1*/ + CMP_MODE_SAMPLE_FILTER_INTCLK = 5U, /*!< CMP function mode is sampled,filtered mode 2*/ + CMP_MODE_WINDOW = 6U, /*!< CMP function mode is windowed mode */ + CMP_MODE_WINDOW_RESAMPLE = 7U, /*!< CMP function mode is windowed,re-sampled mode */ + CMP_MODE_WINDOW_FILTER = 8U, /*!< CMP function mode is windowed,filtered mode */ +#ifdef CMP_SUPPORT_CHANNELSCAN_MODE_FEATURE + CMP_MODE_CHANNEL_SCAN = 9U /*!< CMP channel scan mode */ +#endif +} CMP_ModeSelType; + +/** + * @brief The instance index of the CMP peripheral + */ +typedef enum +{ + CMP_INSTANCE_0 = 0U, /*!< CMP instance 0 is selected */ + CMP_INSTANCE_1 = 1U, /*!< CMP instance 1 is selected */ + CMP_INSTANCE_2 = 2U /*!< CMP instance 2 is selected */ +} CMP_InstanceType; + +/** + * @brief The instance index of the CMP DAC enable select + */ +typedef enum +{ + CMP_DACENABLE_DCR = 0U, /*!< CMP Dac is enabled by DCR[DAC_EN] */ + CMP_DACENABLE_CCR0 = 1U /*!< CMP Dac is enabled by CCR0[EN] */ +} CMP_DacEnableSrcType; + +/** + * @brief The instance index of the CMP output invert + */ +typedef enum +{ + CMP_NON_INVERT = 0U, /*!< CMP output do not Invert*/ + CMP_INVERT = 1U /*!< CMP output Invert */ +} CMP_InvertType; + +/** + * @brief The instance index of the CMP output select + */ +typedef enum +{ + CMP_FILTEROUT = 0U, /*!< CMP filter output */ + CMP_UNFILTEROUT = 1U /*!< CMP Unfilter output */ +} CMP_OutSelectType; + +/** + * @brief The instance index of the CMP window level + */ +typedef enum +{ + CMP_HOLD = 0U, /*!< CMP output hold when window close */ + CMP_USERDEF = 1U /*!< CMP output userdefine when window close */ +} CMP_OutWinLevelType; + +/** + * @brief The instance index of the window output under userdefine CMP window level + */ +typedef enum +{ + CMP_OUTWIN_0 = 0U, /*!< CMP window output is 0 */ + CMP_OUTWIN_1 = 1U /*!< CMP window output is 1 */ +} CMP_OutWinLevel_UserDefType; + + +/** + * @brief The instance index of the CMP Event caused window close + */ +typedef enum +{ + CMP_RISINGEDGE = 0U, /*!< CMP output event RisingEdge causes window close */ + CMP_FALLINGEDGE = 1U, /*!< CMP output event FallingEdge causes window close */ + CMP_BOTHEDGES = 2U, /*!< CMP output event bothEdges causes window close */ +} CMP_EventType; + +/** + * @brief The instance index of the CMP filter count numbers + */ +typedef enum +{ + CMP_FILTERCNT_0 = 0U, /*!< CMP filter is bypassed */ + CMP_FILTERCNT_1 = 1U, /*!< CMP filter is 1 consecutive sample */ + CMP_FILTERCNT_2 = 2U, /*!< CMP filter is 2 consecutive sample */ + CMP_FILTERCNT_3 = 3U, /*!< CMP filter is 3 consecutive sample */ + CMP_FILTERCNT_4 = 4U /*!< CMP filter is 4 consecutive sample */ +} CMP_FilterCntType; + +/** + * @brief The instance index of the CMP hysteresis control + */ +typedef enum +{ + CMP_HYSTCTRL_0 = 0U, /*!< CMP 0 hysteresis internal */ + CMP_HYSTCTRL_1 = 1U, /*!< CMP 1 hysteresis internal */ + CMP_HYSTCTRL_2 = 2U, /*!< CMP 2 hysteresis internal */ + CMP_HYSTCTRL_3 = 3U /*!< CMP 3 hysteresis internal */ +} CMP_HystCtrlType; + +#ifdef CMP_SUPPORT_CHANNELSCAN_MODE_FEATURE +/** + * @brief The fixed CMP port for reference in channel scan mode + */ +typedef enum +{ + CMP_PORTSEL_MUX_P = 0U, /*!< CMP Positive Port */ + CMP_PORTSEL_MUX_N = 1U /*!< CMP Negative Port */ +} CMP_PortSelType; +#endif + +/** + * @brief The source of the CMP input + */ +typedef enum +{ + CMP_INSRCSEL_DAC = 0U, /*!< CMP input source is DAC */ + CMP_INSRCSEL_MUX = 1U /*!< CMP input source is analog 1-8 mux */ +} CMP_INSrcSelType; + +/** + * @brief The instance index of the CMP input mux + */ +typedef enum +{ + CMP_INSEL_MUX_IN0 = 0U, /*!< CMP input mux from IN0(CMP0,CMP1,CMP2) */ + CMP_INSEL_MUX_IN1 = 1U, /*!< CMP input mux from IN1(CMP0,CMP1,CMP2) */ + CMP_INSEL_MUX_IN2 = 2U, /*!< CMP input mux from IN2(CMP0,CMP1,CMP2) */ + CMP_INSEL_MUX_IN3 = 3U, /*!< CMP input mux from IN3(CMP0,CMP1,CMP2) */ + CMP_INSEL_MUX_IN4 = 4U, /*!< CMP input mux from IN4(CMP0,CMP1,CMP2) */ + CMP_INSEL_MUX_IN5 = 5U, /*!< CMP input mux from IN5(CMP1,CMP2) */ + CMP_INSEL_MUX_IN6 = 6U, /*!< CMP input mux from IN6(CMP1,CMP2) */ + CMP_INSEL_MUX_IN7 = 7U /*!< CMP input mux from IN7(CMP1,CMP2) */ +} CMP_MuxSelType; + +/** + * @brief The instance index of high power mode select + */ +typedef enum +{ + CMP_LOWSPEEDMODE = 0U, /*!< CMP low speed mode */ + CMP_HIGHSPEEDMODE = 1U /*!< CMP high speed mode */ +} CMP_SpeedModeSelType; + +/** + * @brief Defines CMP out status + */ +typedef enum +{ + CMP_OUT_FALLING_EDGE = 0U, /*!< CMP out detect falling edge */ + CMP_OUT_RISING_EDGE = 1U, /*!< CMP out detect rising edge */ + CMP_OUT_NONE = 2U /*!< CMP out detect none */ +} CMP_OutStatus; + + +/********* Local inline function ************/ + +/** + * @brief set CMP enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEn(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR0; + pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_EN_MASK)) | CMP_CCR0_EN(bEnable)); +} + +/** + * @brief STOP mode enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnLPMode(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR0; + pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_LP_EN_MASK)) | CMP_CCR0_LP_EN(bEnable)); +} + +/** + * @brief set DAC enable selection + * + * @param pCmp the CMP instance to use + * @param eType Dac enable source + */ +LOCAL_INLINE void CMP_HWA_SetDacEnableSrc(CMP_Type *const pCmp, CMP_DacEnableSrcType eType) +{ + uint32_t u32RegVal = pCmp->CCR0; + pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_DACEN_SEL_MASK)) | CMP_CCR0_DACEN_SEL(eType)); +} + +/** + * @brief set CMP DMA enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetDma(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_DMA_EN_MASK)) | CMP_CCR1_DMA_EN(bEnable)); +} + +/** + * @brief set CMP mode + * + * @param pCmp the CMP instance to use + * @param eMod the CMP mode to use + * @param u8FilterPrd the CMP filter period + * @param eFilterCnt the CMP filter sample count + */ +LOCAL_INLINE void CMP_HWA_SetComparatorMode(CMP_Type *const pCmp, CMP_ModeSelType eMode, uint8_t u8FilterPrd, CMP_FilterCntType eFilterCnt) +{ + uint32_t u32RegVal = pCmp->CCR1; + + switch (eMode) + { + case CMP_MODE_DISABLE: + { + /* Nothing deal with */ + } + break; + + case CMP_MODE_CONTINUOUS: + { + u32RegVal &= ~CMP_CCR1_WIN_EN_MASK; + u32RegVal &= ~CMP_CCR1_SAMPLE_EN_MASK; + u32RegVal &= ~CMP_CCR1_FILT_PER_MASK; + u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK; + } + break; + + case CMP_MODE_SAMPLE_NONFILTER_EXTCLK: + { + u32RegVal &= ~CMP_CCR1_WIN_EN_MASK; + u32RegVal |= CMP_CCR1_SAMPLE_EN(true); + u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK; + u32RegVal |= CMP_CCR1_FILT_CNT(0x01); + } + break; + + case CMP_MODE_SAMPLE_NONFILTER_INTCLK: + { + u32RegVal &= ~CMP_CCR1_WIN_EN_MASK; + u32RegVal &= ~CMP_CCR1_SAMPLE_EN_MASK; + u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK; + u32RegVal &= ~CMP_CCR1_FILT_PER_MASK; + u32RegVal |= CMP_CCR1_FILT_CNT(0x01)| + CMP_CCR1_FILT_PER(u8FilterPrd); + } + break; + + case CMP_MODE_SAMPLE_FILTER_EXTCLK: + { + u32RegVal &= ~CMP_CCR1_WIN_EN_MASK; + u32RegVal |= CMP_CCR1_SAMPLE_EN(true); + u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK; + u32RegVal |= CMP_CCR1_FILT_CNT(eFilterCnt); + } + break; + + case CMP_MODE_SAMPLE_FILTER_INTCLK: + { + u32RegVal &= ~CMP_CCR1_WIN_EN_MASK; + u32RegVal &= ~CMP_CCR1_SAMPLE_EN_MASK; + u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK; + u32RegVal &= ~CMP_CCR1_FILT_PER_MASK; + u32RegVal |= CMP_CCR1_FILT_CNT(eFilterCnt)| + CMP_CCR1_FILT_PER(u8FilterPrd); + } + break; + + case CMP_MODE_WINDOW: + { + u32RegVal |= CMP_CCR1_WIN_EN(true); + u32RegVal &= ~CMP_CCR1_SAMPLE_EN_MASK; + u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK; + u32RegVal &= ~CMP_CCR1_FILT_PER_MASK; + } + break; + + case CMP_MODE_WINDOW_RESAMPLE: + { + u32RegVal |= CMP_CCR1_WIN_EN(true); + u32RegVal &= ~CMP_CCR1_SAMPLE_EN_MASK; + u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK; + u32RegVal &= ~CMP_CCR1_FILT_PER_MASK; + u32RegVal |= CMP_CCR1_FILT_CNT(0x01)| + CMP_CCR1_FILT_PER(u8FilterPrd); + } + break; + + case CMP_MODE_WINDOW_FILTER: + { + u32RegVal |= CMP_CCR1_WIN_EN(true); + u32RegVal &= ~CMP_CCR1_SAMPLE_EN_MASK; + u32RegVal &= ~CMP_CCR1_FILT_CNT_MASK; + u32RegVal &= ~CMP_CCR1_FILT_PER_MASK; + u32RegVal |= CMP_CCR1_FILT_CNT(eFilterCnt)| + CMP_CCR1_FILT_PER(u8FilterPrd); + } + break; + +#ifdef CMP_SUPPORT_CHANNELSCAN_MODE_FEATURE + case CMP_MODE_CHANNEL_SCAN: + { + pCmp->CSCR0 |= CMP_CSCR0_CS_EN(true) ; + } + break; +#endif + + default: + break; + } + + pCmp->CCR1 = u32RegVal; +} + +/** + * @brief set CPM output invert + * + * @param pCmp the CMP instance to use + * @param eType CPM output invert type + */ +LOCAL_INLINE void CMP_HWA_SetCmpOutInvert(CMP_Type *const pCmp, CMP_InvertType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_INV_MASK)) | CMP_CCR1_CMPOUT_INV(eType)); +} + +/** + * @brief set CPM output filter/unfilter selection + * + * @param pCmp the CMP instance to use + * @param eType CPM output filter/unfilter type + */ +LOCAL_INLINE void CMP_HWA_SetCmpOutSel(CMP_Type *const pCmp, CMP_OutSelectType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_SEL_MASK)) | CMP_CCR1_CMPOUT_SEL(eType)); +} + +/** + * @brief set comparator output pin enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnCmpOutPack(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_PEN_MASK)) | CMP_CCR1_CMPOUT_PEN(bEnable)); +} + +/** + * @brief set CMPOUT_WIN level, when window is closed + * + * @param pCmp the CMP instance to use + * @param eType CMPOUT_WIN level type + */ +LOCAL_INLINE void CMP_HWA_SetCmpOutWinLevel(CMP_Type *const pCmp, CMP_OutWinLevelType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_WIN_OWEN_MASK)) | CMP_CCR1_CMPOUT_WIN_OWEN(eType)); +} + +/** + * @brief set CMPOUT_WIN level in user-define mode, when window is closed + * + * @param pCmp the CMP instance to use + * @param eType user-define CMPOUT_WIN level type + */ +LOCAL_INLINE void CMP_HWA_SetCmpOutWin(CMP_Type *const pCmp, CMP_OutWinLevel_UserDefType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_WIN_OW_MASK)) | CMP_CCR1_CMPOUT_WIN_OW(eType)); +} + +/** + * @brief set invert the WINDOW/SAMPLE signal enable or not + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnWinSampleInvert(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_WIN_INV_MASK)) | CMP_CCR1_WIN_INV(bEnable)); +} + +/** + * @brief WINDOW signal can or not be closed by CMPO event when window mode + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnEventCloseWin(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_WIN_CLS_MASK)) | CMP_CCR1_WIN_CLS(bEnable)); +} + +/** + * @brief set which CMPO event causes window close + * + * @param pCmp the CMP instance to use + * @param eType CMPO event type + */ +LOCAL_INLINE void CMP_HWA_SetEventCloseWin(CMP_Type *const pCmp, CMP_EventType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_EVT_SEL_MASK)) | CMP_CCR1_EVT_SEL(eType)); +} + +/** + * @brief set CCR1 register + * + * @param pCmp the CMP instance to use + * @param u32RegVal Register value to set + */ +LOCAL_INLINE void CMP_HWA_SetCCR1(CMP_Type *const pCmp, uint32_t u32RegVal) +{ + pCmp->CCR1 = u32RegVal; +} + +/** + * @brief set CMP power mode select + * + * @param pCmp the CMP instance to use + * @param eMod CMP power mode + */ +LOCAL_INLINE void CMP_HWA_SetSpeedMode(CMP_Type *const pCmp, CMP_SpeedModeSelType eMode) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_HPMD_MASK)) | CMP_CCR2_HPMD(eMode)); +} + +/** + * @brief set Comparator hard block hysteresis control + * + * @param pCmp the CMP instance to use + * @param eType CMP hysteresis control type + */ +LOCAL_INLINE void CMP_HWA_SetHystCtrl(CMP_Type *const pCmp, CMP_HystCtrlType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_HYSTCTR_MASK)) | CMP_CCR2_HYSTCTR(eType)); +} + +/** + * @brief set which input is selected for the positive mux + * + * @param pCmp the CMP instance to use + * @param eType CMP positive mux type + */ +LOCAL_INLINE void CMP_HWA_SetPSelMux(CMP_Type *const pCmp, CMP_MuxSelType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_PSEL_MASK)) | CMP_CCR2_PSEL(eType)); +} + +/** + * @brief set which input is selected for the negative mux + * + * @param pCmp the CMP instance to use + * @param eType CMP negative mux type + */ +LOCAL_INLINE void CMP_HWA_SetNSelMux(CMP_Type *const pCmp, CMP_MuxSelType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_MSEL_MASK)) | CMP_CCR2_MSEL(eType)); +} + +/** + * @brief set the input to the positive port of the comparator + * + * @param pCmp the CMP instance to use + * @param eType CMP positive input source type(analog mux,dac) + */ +LOCAL_INLINE void CMP_HWA_SetINPSel(CMP_Type *const pCmp, CMP_INSrcSelType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_INPSEL_MASK)) | CMP_CCR2_INPSEL(eType)); +} + +/** + * @brief set the input to the negative port of the comparator + * + * @param pCmp the CMP instance to use + * @param eType CMP negative input source type(analog mux,dac) + */ +LOCAL_INLINE void CMP_HWA_SetINNSel(CMP_Type *const pCmp, CMP_INSrcSelType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_INMSEL_MASK)) | CMP_CCR2_INMSEL(eType)); +} + +/** + * @brief set CCR2 register + * + * @param pCmp the CMP instance to use + * @param u32RegVal Register value to set + */ +LOCAL_INLINE void CMP_HWA_SetCCR2(CMP_Type *const pCmp, uint32_t u32RegVal) +{ + pCmp->CCR2 = u32RegVal; +} + +/** + * @brief set CMP DAC enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnDac(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->DCR; + pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_DAC_EN_MASK)) | CMP_DCR_DAC_EN(bEnable)); +} + +/** + * @brief set CMP Dac output + * + * @param pCmp the CMP instance to use + * @param u8Data the Dac data + * @note output = (VinRef / 256) * (u8Data + 1) + */ +LOCAL_INLINE void CMP_HWA_SetDacData(CMP_Type *const pCmp, uint8_t u8Data) +{ + uint32_t u32RegVal = pCmp->DCR; + pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_DAC_DATA_MASK)) | CMP_DCR_DAC_DATA(u8Data)); +} + +/** + * @brief set DCR register + * + * @param pCmp the CMP instance to use + * @param u32RegVal Register value to set + */ +LOCAL_INLINE void CMP_HWA_SetDCR(CMP_Type *const pCmp, uint32_t u32RegVal) +{ + pCmp->DCR = u32RegVal; +} + +/** + * @brief set comparator rising interrupt enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetIntEn_Rising(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->IER; + pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CFR_IE_MASK)) | CMP_IER_CFR_IE(bEnable)); +} + +/** + * @brief get comparator rising interrupt enable status + * + * @param pCmp the CMP instance to use + * @return comparator rising interrupt status + */ +LOCAL_INLINE bool CMP_HWA_GetIntEn_Rising(CMP_Type *const pCmp) +{ + bool RetStatus = false; + uint32_t u32RegVal = pCmp->IER; + + RetStatus = (bool)((((u32RegVal & CMP_IER_CFR_IE_MASK) >> CMP_IER_CFR_IE_SHIFT) != 0U) ? true : false); + return RetStatus; +} + +/** + * @brief set comparator falling interrupt enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetIntEn_Falling(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->IER; + pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CFF_IE_MASK)) | CMP_IER_CFF_IE(bEnable)); +} + +/** + * @brief get comparator falling interrupt enable status + * + * @param pCmp the CMP instance to use + * @return comparator falling interrupt status + */ +LOCAL_INLINE bool CMP_HWA_GetIntEn_Falling(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->IER; + + bRetStatus = (bool)((((u32RegVal & CMP_IER_CFF_IE_MASK) >> CMP_IER_CFF_IE_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief set IER register + * + * @param pCmp the CMP instance to use + * @param u32RegVal Register value to set + */ +LOCAL_INLINE void CMP_HWA_SetIER(CMP_Type *const pCmp, uint32_t u32RegVal) +{ + pCmp->IER = u32RegVal; +} + +/** + * @brief get CMP output rising edge status + * + * @param pCmp the CMP instance to use + * @return CMP rising edge status + */ +LOCAL_INLINE bool CMP_HWA_GetIntFlag_Rising(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->CSR; + + bRetStatus = (bool)((((u32RegVal & CMP_CSR_CFR_MASK) >> CMP_CSR_CFR_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief get CMP output falling edge status + * + * @param pCmp the CMP instance to use + * @return CMP falling edge status + */ +LOCAL_INLINE bool CMP_HWA_GetIntFlag_Falling(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->CSR; + + bRetStatus = (bool)((((u32RegVal & CMP_CSR_CFF_MASK) >> CMP_CSR_CFF_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief clear rising interrupt flag + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_ClearIntFlag_Rising(CMP_Type *const pCmp) +{ + pCmp->CSR = CMP_CSR_CFR(true); +} + +/** + * @brief clear falling interrupt flag + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_ClearIntFlag_Falling(CMP_Type *const pCmp) +{ + pCmp->CSR = CMP_CSR_CFF(true); +} + +/** + * @brief get CMP filtered output + * + * @param pCmp the CMP instance to use + * @return CMP filtered output + */ +LOCAL_INLINE uint32_t CMP_HWA_GetCmpOut(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSR; + u32RegVal = (u32RegVal & CMP_CSR_CMPOUT_FILTER_MASK) >> CMP_CSR_CMPOUT_FILTER_SHIFT; + return u32RegVal; +} + +/** + * @brief set CSR register + * + * @param pCmp the CMP instance to use + * @param u32RegVal Register value to set + */ +LOCAL_INLINE void CMP_HWA_SetCSR(CMP_Type *const pCmp, uint32_t u32RegVal) +{ + pCmp->CSR = u32RegVal; +} + +#ifdef CMP_SUPPORT_CHANNELSCAN_MODE_FEATURE + +/** + * @brief set comparator channel scan interrupt enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetIntEn_ChannelScan(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->IER; + pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CSF_IE_MASK)) | CMP_IER_CSF_IE(bEnable)); +} + +/** + * @brief get comparator channel scan interrupt enable status + * + * @param pCmp the CMP instance to use + * @return comparator channel scan interrupt status + */ +LOCAL_INLINE bool CMP_HWA_GetIntEn_ChannelScan(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->IER; + + bRetStatus = (bool)((((u32RegVal & CMP_IER_CSF_IE_MASK) >> CMP_IER_CSF_IE_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief clear channel scan interrupt flag + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_ClearIntFlag_ChannelScan(CMP_Type *const pCmp) +{ + pCmp->CSR = CMP_CSR_CSF(true); +} + +/** + * @brief set CMP and DAC initialization delay modulus + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_SetCSInitModulus(CMP_Type *const pCmp, uint8_t u8Modulus) +{ + uint32_t u32RegVal = pCmp->CSCR0; + pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_INITMOD_MASK)) | CMP_CSCR0_CS_INITMOD(u8Modulus)); +} + +/** + * @brief set number of clock cycles for sampling + * + * @param pCmp the CMP instance to use + * @param u8Nsam the sampling clocks value + */ +LOCAL_INLINE void CMP_HWA_SetCSNSAM(CMP_Type *const pCmp, uint8_t u8Nsam) +{ + uint32_t u32RegVal = pCmp->CSCR0; + pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_NSAM_MASK)) | CMP_CSCR0_CS_NSAM(u8Nsam)); +} + +/** + * @brief set CMP channel scan enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetCSEn(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CSCR0; + pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_EN_MASK)) | CMP_CSCR0_CS_EN(bEnable)); +} + +/** + * @brief set CSCR0 register + * + * @param pCmp the CMP instance to use + * @param u32RegVal Register value to set + */ +LOCAL_INLINE void CMP_HWA_SetCSCR0(CMP_Type *const pCmp, uint32_t u32RegVal) +{ + pCmp->CSCR0 = u32RegVal; +} + +/** + * @brief set channel scan fixed channel + * + * @param pCmp the CMP instance to use + * @param eChannel the fixed channel + */ +LOCAL_INLINE void CMP_HWA_SetCSFixedChannel(CMP_Type *const pCmp, CMP_MuxSelType eChannel) +{ + uint32_t u32RegVal = pCmp->CSCR1; + pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)CMP_CSCR1_FIXCH_MASK)) | CMP_CSCR1_FIXCH(eChannel)); +} + +/** + * @brief set channel scan fixed port + * + * @param pCmp the CMP instance to use + * @param ePort the fixed port + */ +LOCAL_INLINE void CMP_HWA_SetCSFixedPort(CMP_Type *const pCmp, CMP_PortSelType ePort) +{ + uint32_t u32RegVal = pCmp->CSCR1; + pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)CMP_CSCR1_FIXP_MASK)) | CMP_CSCR1_FIXP(ePort)); +} + +/** + * @brief set channel scan channel enabled + * + * @param pCmp the CMP instance to use + * @param eChannel the enabled channel + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetCSChannelEn(CMP_Type *const pCmp, CMP_MuxSelType eChannel, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CSCR1; + pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)(1 << eChannel))) | (((uint32_t)bEnable) << eChannel)); +} + +/** + * @brief set CSCR1 register + * + * @param pCmp the CMP instance to use + * @param u32RegVal Register value to set + */ +LOCAL_INLINE void CMP_HWA_SetCSCR1(CMP_Type *const pCmp, uint32_t u32RegVal) +{ + pCmp->CSCR1 = u32RegVal; +} + +/** + * @brief get CMP output channel scan status + * + * @param pCmp the CMP instance to use + * @return CMP channel scan status + */ +LOCAL_INLINE bool CMP_HWA_GetIntFlag_ChannelScan(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->CSR; + + bRetStatus = (bool)((((u32RegVal & CMP_CSR_CSF_MASK) >> CMP_CSR_CSF_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief set channel scan channel enabled + * + * @param pCmp the CMP instance to use + * @param eChannel the enabled channel + * @param bPresetstate preset state for channel + */ +LOCAL_INLINE void CMP_HWA_SetCSChannelPresetstate(CMP_Type *const pCmp, CMP_MuxSelType eChannel, bool bPresetstate) +{ + uint32_t u32RegVal = pCmp->CSCSR; + pCmp->CSCSR = ((u32RegVal & (~(uint32_t)(1 << eChannel))) | (((uint32_t)bPresetstate) << eChannel)); +} + +/** + * @brief get channel scan channel current state + * + * @param pCmp the CMP instance to use + * @param eChannel the channel that want to get state + */ +LOCAL_INLINE bool CMP_HWA_GetCSChannelOut(CMP_Type *const pCmp, CMP_MuxSelType eChannel) +{ + bool OutFlag; + uint32_t u32RegVal = pCmp->CSCSR; + OutFlag = (bool)((u32RegVal & ((uint32_t)(1 << eChannel))) >> eChannel); + + return OutFlag; +} + +/** + * @brief software clear channel scan comparison results + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_ClearCSCompRes(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSCSR; + pCmp->CSCSR = ((u32RegVal & (~(uint32_t)CMP_CSCSR_CS_SWCLR_MASK)) | CMP_CSCSR_CS_SWCLR(true)); +} + +/** + * @brief software clear channel scan comparison results + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetCSCompareResultACEn(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CSCSR; + pCmp->CSCSR = ((u32RegVal & (~(uint32_t)CMP_CSCSR_CS_ACLR_MASK)) | CMP_CSCSR_CS_ACLR(bEnable)); +} + +/** + * @brief set CSCSR register + * + * @param pCmp the CMP instance to use + * @param u32RegVal Register value to set + */ +LOCAL_INLINE void CMP_HWA_SetCSCSR(CMP_Type *const pCmp, uint32_t u32RegVal) +{ + pCmp->CSCSR = u32RegVal; +} + +/** + * @brief get channel scan active status + * + * @param pCmp the CMP instance to use + * @return status cmp channel whether is active + */ +LOCAL_INLINE bool CMP_HWA_GetCSActive(CMP_Type *const pCmp) +{ + bool status; + uint32_t u32RegVal = pCmp->CSSR; + status = ((u32RegVal & ((uint32_t)CMP_CSSR_CS_ACTIVE_MASK)) >> CMP_CSSR_CS_ACTIVE_SHIFT) ? true : false; + return status; +} + +/** + * @brief get channel scan comparison result changed flag + * + * @param pCmp the CMP instance to use + * @param eChannel the channel to get comparison result changed flag + * @return the comparison result changed flag for a given channel + */ +LOCAL_INLINE bool CMP_HWA_GetCSComparisonResultFlag(CMP_Type *const pCmp, CMP_MuxSelType eChannel) +{ + uint32_t u32RegVal = pCmp->CSSR; + return ((u32RegVal & (1U << eChannel)) >> eChannel) ? true : false; +} + +/** + * @brief set CSSR register + * + * @param pCmp the CMP instance to use + * @param u32RegVal Register value to set + */ +LOCAL_INLINE void CMP_HWA_SetCSSR(CMP_Type *const pCmp, uint32_t u32RegVal) +{ + pCmp->CSSR = u32RegVal; +} + +#endif + +/** @}*/ + +#endif /* #if CMP_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_CMP_H_ */ diff --git a/Inc/HwA_cmu.h b/Inc/HwA_cmu.h new file mode 100644 index 0000000..804cd49 --- /dev/null +++ b/Inc/HwA_cmu.h @@ -0,0 +1,249 @@ +/** + * @file HwA_cmu.h + * @author Flagchip0100 + * @brief CMU Module Register API + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright 2020-2024 Flagchip Semiconductors Co., Ltd. + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip100 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip100 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_CMU_H_ +#define _HWA_CMU_H_ + +#include "device_header.h" + +#if (CMU_INSTANCE_COUNT > 0U) + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @defgroup HwA_cmu HwA_cmu + * @ingroup module_driver_cmu + * @{ + */ + +/******************************************************************************* + * Local inline function + ******************************************************************************/ +/** + * @brief Set Reference Window value. + * + * @param pCmu CMU Instance. + * @param u32Temp Ref Window value. + */ +LOCAL_INLINE void CMU_HWA_SetRefWindow(CMU_Type *const pCmu, uint32_t u32Temp) +{ + pCmu->REF_WINDOW = u32Temp; +} + +/** + * @brief Set Minimun Counter value. + * + * @param pCmu CMU Instance. + * @param u32Temp Min Count value. + */ +LOCAL_INLINE void CMU_HWA_SetMinCnts(CMU_Type *const pCmu, uint32_t u32Temp) +{ + pCmu->MIN = u32Temp; +} + +/** + * @brief Get Minimun Counter value. + * + * @param pCmu CMU Instance. + * @return Min count value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetMinCnts(const CMU_Type *const pCmu) +{ + return (pCmu->MIN & CMU_MIN_MIN_MASK) >> CMU_MIN_MIN_SHIFT; +} + +/** + * @brief Set Maximun Counter value. + * + * @param pCmu CMU Instance. + * @param u32Temp Max count value. + */ +LOCAL_INLINE void CMU_HWA_SetMaxCnts(CMU_Type *const pCmu, uint32_t u32Temp) +{ + pCmu->MAX = u32Temp; +} + +/** + * @brief Get Maximun Counter value. + * + * @param pCmu CMU Instance. + * @return Max count value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetMaxCnts(const CMU_Type *const pCmu) +{ + return (pCmu->MAX & CMU_MAX_MAX_MASK) >> CMU_MAX_MAX_SHIFT; +} + +/** + * @brief Get Counter value. + * + * @param pCmu CMU Instance. + * @return Counter value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetCount(const CMU_Type *const pCmu) +{ + return (pCmu->MON_CNT & CMU_MON_CNT_MON_CNT_MASK) >> CMU_MON_CNT_MON_CNT_SHIFT; +} + +/** + * @brief Set period window Counter. + * + * @param pCmu CMU Instance. + * @param u32Temp Period value. + */ +LOCAL_INLINE void CMU_HWA_SetPeriodWindow(CMU_Type *const pCmu, uint32_t u32Temp) +{ + pCmu->PERIOD = (pCmu->PERIOD & ~((uint32_t)CMU_PERIOD_WINDOW_MASK)) | CMU_PERIOD_WINDOW(u32Temp); +} + +/** + * @brief Set period enble bit. + * + * @param pCmu CMU Instance. + * @param bEnable Set enable bit. + */ +LOCAL_INLINE void CMU_HWA_SetPeriodEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->PERIOD = (pCmu->PERIOD & ~((uint32_t)CMU_PERIOD_EN_MASK)) | CMU_PERIOD_EN(bEnable); +} + +/** + * @brief Get period enble bit. + * + * @param pCmu CMU Instance. + * @return Period mode enable bit. + */ +LOCAL_INLINE bool CMU_HWA_GetPeriodEnable(const CMU_Type *const pCmu) +{ + return ((pCmu->PERIOD & CMU_PERIOD_EN_MASK) == CMU_PERIOD_EN_MASK) ? true : false; +} + +/** + * @brief Set control register value. + * + * @param pCmu CMU Instance. + * @param u32Temp Control value. + */ +LOCAL_INLINE void CMU_HWA_SetCtrl(CMU_Type *const pCmu, uint32_t u32Temp) +{ + pCmu->CTRL = u32Temp; +} + +/** + * @brief Get control register value. + * + * @param pCmu CMU Instance. + * @return Control register value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetCtrl(const CMU_Type *const pCmu) +{ + return pCmu->CTRL; +} + +/** + * @brief Get status register value. + * + * @param pCmu CMU Instance. + * @return Status register value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetST(const CMU_Type *const pCmu) +{ + return pCmu->ST; +} + +/** + * @brief Clear clock monitor status. + * + * @param pCmu CMU Instance. + */ +LOCAL_INLINE void CMU_HWA_ClsST(CMU_Type *const pCmu) +{ + pCmu->ST = CMU_ST_MIS_MASK | CMU_ST_LOC_MASK; +} + +#ifdef CMU_CTRL_LP_SUPPORT +/** + * @brief Enable Standby mode. + * + * @param pCmu CMU Instance. + * @param bEnable Enable mode. + */ +LOCAL_INLINE void CMU_HWA_StanbyModeEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_LP_EN_MASK)) | CMU_CTRL_LP_EN(bEnable); +} +#endif + +/** + * @brief Enable Stop mode. + * + * @param pCmu CMU Instance. + * @param bEnable Enable mode. + */ +LOCAL_INLINE void CMU_HWA_StopModeEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_STOP_EN_MASK)) | CMU_CTRL_STOP_EN(bEnable); +} + +/** + * @brief Enable Softeare Reset. + * + * @param pCmu CMU Instance. + */ +LOCAL_INLINE void CMU_HWA_SoftwareRST(CMU_Type *const pCmu) +{ + pCmu->CTRL |= CMU_CTRL_SW_RST_MASK; +} + +/** + * @brief Enable Software Reset. + * + * @param pCmu CMU Instance. + * @return Software reset is done. + */ +LOCAL_INLINE bool CMU_HWA_GetSoftwareRST(const CMU_Type *const pCmu) +{ + return ((pCmu->CTRL & CMU_CTRL_SW_RST_MASK) == CMU_CTRL_SW_RST_MASK) ? true : false; +} + +/** + * @brief Enable low power restart mode. + * + * @param pCmu CMU Instance. + * @param bEnable Enable mode. + */ +LOCAL_INLINE void CMU_HWA_LPRestartEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_RESTART_EN_MASK)) | CMU_CTRL_RESTART_EN(bEnable); +} + +/** @}*/ /* HwA_cmu */ + +#if defined(__cplusplus) +} +#endif + +#endif /* (CMU_INSTANCE_COUNT > 0U) */ + +#endif /* _HWA_CMU_H_ */ diff --git a/Inc/HwA_cordic.h b/Inc/HwA_cordic.h new file mode 100644 index 0000000..87774ed --- /dev/null +++ b/Inc/HwA_cordic.h @@ -0,0 +1,210 @@ +/** + * @file HwA_cordic.h + * @author Flagchip + * @brief CORDIC hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip054 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip054 N/A Change version and release + ******************************************************************************** */ +#ifndef _HWA_CORDIC_H_ +#define _HWA_CORDIC_H_ +#include "device_header.h" + +#if CORDIC_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_cordic HwA_cordic + * @ingroup module_driver_cordic + * @{ + */ + +/** + * \brief CORDIC Iteration Type + * + * Defines the number of iterations for the CORDIC algorithm. + */ +typedef enum +{ + CORDIC_Iteration_8 = 0, + CORDIC_Iteration_16, + CORDIC_Iteration_24 +} CORDIC_IterationType; + +/** + * \brief CORDIC System Type + * + * Specifies the system type for the CORDIC algorithm. + */ +typedef enum +{ + CORDIC_Trigonometric = 0, + CORDIC_Hyperbolic, + CORDIC_Linear +} CORDIC_SystemType; + +/** + * \brief CORDIC Mode Type + * + * Specifies the operation mode for the CORDIC algorithm. + */ +typedef enum +{ + CORDIC_Rotate = 0, + CORDIC_Vector +} CORDIC_ModeType; + +#if (DEVICE_NAME>FC7300FxMDxxxxxT1B_DEVICE_START) && (DEVICE_NAMECTRL = u32Value; +} + +/** + * \brief Read CORDIC module Control register + * + * Reads the control register value of the CORDIC module. + * + * \param pCordic Pointer to the CORDIC module. + * \return Control register value. + */ +LOCAL_INLINE uint32_t Cordic_HWA_GetCtrl(CORDIC_Type* const pCordic) +{ + return (uint32_t)(pCordic->CTRL); +} + +/** + * \brief Set CORDIC module X Input register + * + * Sets the X input register value of the CORDIC module. + * + * \param pCordic Pointer to the CORDIC module. + * \param u32Value X input register value to set. + */ +LOCAL_INLINE void Cordic_HWA_Set_XInput(CORDIC_Type* const pCordic, int32_t u32Value) +{ + pCordic->X_INPUT = *((uint32_t *)&u32Value); +} + +/** + * \brief Set CORDIC module Y Input register + * + * Sets the Y input register value of the CORDIC module. + * + * \param pCordic Pointer to the CORDIC module. + * \param u32Value Y input register value to set. + */ +LOCAL_INLINE void Cordic_HWA_Set_YInput(CORDIC_Type* const pCordic, int32_t u32Value) +{ + pCordic->Y_INPUT = *((uint32_t *)&u32Value); +} + +/** + * \brief Set CORDIC module Z Input register + * + * Sets the Z input register value of the CORDIC module. + * + * \param pCordic Pointer to the CORDIC module. + * \param u32Value Z input register value to set. + */ +LOCAL_INLINE void Cordic_HWA_Set_ZInput(CORDIC_Type* const pCordic, int32_t u32Value) +{ + pCordic->Z_INPUT = *((uint32_t *)&u32Value); +} + +/** + * \brief Read CORDIC module X Output register + * + * Reads the X output register value of the CORDIC module. + * + * \param pCordic Pointer to the CORDIC module. + * \return X output register value. + */ +LOCAL_INLINE int32_t Cordic_HWA_Get_XOutput(CORDIC_Type* const pCordic) +{ + return (int32_t)(pCordic->X_OUTPUT); +} + +/** + * \brief Read CORDIC module Y Output register + * + * Reads the Y output register value of the CORDIC module. + * + * \param pCordic Pointer to the CORDIC module. + * \return Y output register value. + */ +LOCAL_INLINE int32_t Cordic_HWA_Get_YOutput(CORDIC_Type* const pCordic) +{ + return (int32_t)(pCordic->Y_OUTPUT); +} + +/** + * \brief Read CORDIC module Z Output register + * + * Reads the Z output register value of the CORDIC module. + * + * \param pCordic Pointer to the CORDIC module. + * \return Z output register value. + */ +LOCAL_INLINE int32_t Cordic_HWA_Get_ZOutput(CORDIC_Type* const pCordic) +{ + return (int32_t)(pCordic->Z_OUTPUT); +} + +/** + * \brief Read CORDIC module State + * + * Reads the current state of the CORDIC module. + * + * \param pCordic Pointer to the CORDIC module. + * \return Current state of the CORDIC module. + */ +LOCAL_INLINE bool Cordic_HWA_Get_Stat(CORDIC_Type* const pCordic) +{ + return (bool)(pCordic->STAT & CORDIC_STAT_DONE_MASK); +} + +/** + * \brief Clear CORDIC module done Flag + * + * Reads the current state of the CORDIC module. + * + * \param pCordic Pointer to the CORDIC module. + */ +LOCAL_INLINE void Cordic_HWA_Clear_Stat(CORDIC_Type* const pCordic) +{ + pCordic->STAT |= CORDIC_STAT_DONE_MASK; +} + +/** + * @} + */ + +#endif + +#endif diff --git a/Inc/HwA_cpm.h b/Inc/HwA_cpm.h new file mode 100644 index 0000000..8213f17 --- /dev/null +++ b/Inc/HwA_cpm.h @@ -0,0 +1,340 @@ +/** + * @file HwA_cpm.h + * @author Flagchip + * @brief CPM register API + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip120 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip120 N/A Change version and release + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_CPM_H_ +#define HWA_INCLUDE_HWA_CPM_H_ +#include "device_header.h" + +#if CPM_INSTANCE_COUNT > 0U + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + +/** FPSCR Bit Fields */ +#define FPSCR_IOC_MASK 0x00000001U +#define FPSCR_DZC_MASK 0x00000002U +#define FPSCR_OFC_MASK 0x00000004U +#define FPSCR_UFC_MASK 0x00000008U +#define FPSCR_IXC_MASK 0x00000010U +#define FPSCR_IDC_MASK 0x00000080U +#define CPM_FPU_INTFLAGMASK 0x0000003FU + +/** + * @defgroup HwA_cpm HwA_cpm + * @ingroup module_driver_cpm + * @{ + */ + +/** + * @brief Get the value of CPM FISCR. + * + * This function returns FISCR value. + * + * @param pCpm the base address of the CPM instance. + * @return uint32_t the value of the FISCR register. + */ +LOCAL_INLINE uint32_t CPM_HWA_GetFiscr(CPM_Type *const pCpm) +{ + uint32_t u32TmpVal = pCpm->FISCR; +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif + return u32TmpVal; +} + +/** + * @brief Return CPM_FISCR FIOC value + * + * @param pCpm the base address of the CPM instance. + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFiocFlag(CPM_Type *const pCpm) +{ + uint32_t u32TmpVal = pCpm->FISCR; +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif + u32TmpVal = (u32TmpVal & CPM_FISCR_FIOC_MASK) >> CPM_FISCR_FIOC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FDZC value + * + * @param pCpm the base address of the CPM instance. + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFdzcFlag(CPM_Type *const pCpm) +{ + uint32_t u32TmpVal = pCpm->FISCR; +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif + u32TmpVal = (u32TmpVal & CPM_FISCR_FDZC_MASK) >> CPM_FISCR_FDZC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FOFC value + * + * @param pCpm the base address of the CPM instance. + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFofcFlag(CPM_Type *const pCpm) +{ + uint32_t u32TmpVal = pCpm->FISCR; +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif + u32TmpVal = (u32TmpVal & CPM_FISCR_FOFC_MASK) >> CPM_FISCR_FOFC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FUFC value + * + * @param pCpm the base address of the CPM instance. + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFufcFlag(CPM_Type *const pCpm) +{ + uint32_t u32TmpVal = pCpm->FISCR; +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif + u32TmpVal = (u32TmpVal & CPM_FISCR_FUFC_MASK) >> CPM_FISCR_FUFC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FIXC value + * + * @param pCpm the base address of the CPM instance. + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFixcFlag(CPM_Type *const pCpm) +{ + uint32_t u32TmpVal = pCpm->FISCR; +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif + u32TmpVal = (u32TmpVal & CPM_FISCR_FIXC_MASK) >> CPM_FISCR_FIXC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FIDC value + * + * @param pCpm the base address of the CPM instance. + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFidcFlag(CPM_Type *const pCpm) +{ + uint32_t u32TmpVal = pCpm->FISCR; +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif + u32TmpVal = (u32TmpVal & CPM_FISCR_FIDC_MASK) >> CPM_FISCR_FIDC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set FIOCE interrupt + * + * @param pCpm the base address of the CPM instance. + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFioceInt(CPM_Type *const pCpm, bool bEnable) +{ + pCpm->FISCR = ((pCpm->FISCR & (~CPM_FISCR_FIOCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIOCE_SHIFT)); +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif +} + +/** + * @brief Set FDZCE interrupt + * + * @param pCpm the base address of the CPM instance. + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFdzceInt(CPM_Type *const pCpm, bool bEnable) +{ + pCpm->FISCR = ((pCpm->FISCR & (~CPM_FISCR_FDZCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FDZCE_SHIFT)); +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif +} + +/** + * @brief Set FOFCE interrupt + * + * @param pCpm the base address of the CPM instance. + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFofceInt(CPM_Type *const pCpm, bool bEnable) +{ + pCpm->FISCR = ((pCpm->FISCR & (~CPM_FISCR_FOFCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FOFCE_SHIFT)); +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif +} + +/** + * @brief Set FUFCE interrupt + * + * @param pCpm the base address of the CPM instance. + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFufceInt(CPM_Type *const pCpm, bool bEnable) +{ + pCpm->FISCR = ((pCpm->FISCR & (~CPM_FISCR_FUFCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FUFCE_SHIFT)); +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif +} + +/** + * @brief Set FIXCE interrupt + * + * @param pCpm the base address of the CPM instance. + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFixceInt(CPM_Type *const pCpm, bool bEnable) +{ + pCpm->FISCR = ((pCpm->FISCR & (~CPM_FISCR_FIXCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIXCE_SHIFT)); +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif +} + +/** + * @brief Set FIDCE interrupt + * + * @param pCpm the base address of the CPM instance. + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFidceInt(CPM_Type *const pCpm, bool bEnable) +{ + pCpm->FISCR = ((pCpm->FISCR & (~CPM_FISCR_FIDCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIDCE_SHIFT)); +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif +} + +/** + * @brief Set FISCR value + * + * @param pCpm the base address of the CPM instance. + * @param u32Val the value want to set the register + */ +LOCAL_INLINE void CPM_HWA_SetFiscr(CPM_Type *const pCpm, uint32_t u32Val) +{ + pCpm->FISCR = u32Val; +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif +} + +#if (CPM_CONTAIN_CPUID == STD_ON) +/** + * @brief Return CPM_CoreID value + * + * @param pCpm the base address of the CPM instance. + * @return uint32_t the core ID value + */ +LOCAL_INLINE uint32_t CPM_HWA_GetCoreIDValve(CPM_Type *const pCpm) +{ + uint32_t u32TmpVal = pCpm->MISCR; +#if (CPM_ERRATA == STD_ON) + __asm volatile( + "dmb \n" + "ldr r8, [%[TCMRCR]] \n"/* Must Read 0xE0080020 after set or read CPM register. */ + : : [TCMRCR] "r"(&pCpm->TCMRCR) : "r8", "memory" + ); +#endif + u32TmpVal = (u32TmpVal & CPM_MISCR_CPU_ID_MASK) >> CPM_MISCR_CPU_ID_SHIFT; + return (uint32_t)u32TmpVal; +} +#endif + +/** @}*/ + +#endif + +#endif /* HWA_INCLUDE_HWA_CPM_H_ */ diff --git a/Inc/HwA_crc.h b/Inc/HwA_crc.h new file mode 100644 index 0000000..7e9615e --- /dev/null +++ b/Inc/HwA_crc.h @@ -0,0 +1,303 @@ +/** + * @file HwA_crc.h + * @author Flagchip + * @brief CRC hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip055 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip055 N/A Change version and release + ******************************************************************************** */ + + +#ifndef _HWA_CRC_H_ +#define _HWA_CRC_H_ + +#include "device_header.h" + +#if CRC_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_crc HwA_crc + * @ingroup module_driver_crc + * @{ + */ + +/********* Local typedef ************/ + +/** + * @brief The data swap for write + */ +typedef enum{ + WRITE_DATASWAP_NONE = 0U, /*!< none data swap for write */ + WRITE_DATASWAP_BIT = 1U, /*!< only bits data swap for write */ + WRITE_DATASWAP_BIT_BYTE = 2U, /*!< both bits and bytes data swap for write */ + WRITE_DATASWAP_BYTE = 3U /*!< only bytes data swap for write */ +} CRC_WriteDataSwapType; + +/** + * @brief The data swap for read + */ +typedef enum{ + READ_DATASWAP_NONE = 0U, /*!< none data swap for read */ + READ_DATASWAP_BIT = 1U, /*!< only bits data swap for read */ + READ_DATASWAP_BIT_BYTE = 2U, /*!< both bits and bytes data swap for read */ + READ_DATASWAP_BYTE = 3U /*!< only bytes data swap for read */ +} CRC_ReadDataSwapType; + +/** + * @brief The complement of reading crc data + */ +typedef enum{ + READ_DATA_NORMAL = 0U, /*!< none complement of reading crc data */ + READ_DATA_FXOR = 1U /*!< Invert or complement with 0xFFFFFFFF or 0xFFFF of crc data */ +} CRC_ReadDataFXORType; + +/** + * @brief The command type of write crc data or seed value + */ +typedef enum{ + WRITE_COMMAND_DATA = 0U, /*!< write crc data */ + WRITE_COMMAND_SEED = 1U /*!< write seed value(used to initialization crc calculation) */ +} CRC_WriteCommondType; + +/** + * @brief The crc mode select + */ +typedef enum{ + CRC_BIT_16 = 0U, /*!< crc 16 bit is selected */ + CRC_BIT_32 = 1U, /*!< crc 32 bit is selected */ + CRC_BIT_8 = 2U, /*!< crc 8 bit is selected */ + CRC_BIT_INVALID = 3U +} CRC_BitWidthType; + + +/********* Local inline function ************/ + +/** + * @brief set CRC CR register for writing data or seed + * + * @param pCrc CRC instance + * @param u32Mod WAS mode + */ +LOCAL_INLINE void CRC_HWA_SetDataOrSeed(CRC_Type *const pCrc, CRC_WriteCommondType u32Mod) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_WAS_MASK)) | CRC_CR_WAS(u32Mod)); +} + +/** + * @brief set polynomial value + * + * @param pCrc CRC instance + * @param u32Poly the polynomial value + */ +LOCAL_INLINE void CRC_HWA_SetPolyVal(CRC_Type *const pCrc, uint32_t u32Poly) +{ + pCrc->POLY = u32Poly; +} + +/** + * @brief set data register(32 bits) + * + * @param pCrc CRC instance + * @param u32Data data to be set + */ +LOCAL_INLINE void CRC_HWA_SetData_U32(CRC_Type *const pCrc, uint32_t u32Data) +{ + pCrc->DATA.uDATA = u32Data; +} + +/** + * @brief set data register(16 bits) + * + * @param pCrc CRC instance + * @param u16Data data to be set + */ +LOCAL_INLINE void CRC_HWA_SetData_U16(CRC_Type *const pCrc, uint16_t u16Data) +{ + pCrc->DATA.tDATA_16.L = u16Data; +} + +/** + * @brief set data register(low 8 bits) + * + * @param pCrc CRC instance + * @param u8Data data to be set + */ +LOCAL_INLINE void CRC_HWA_SetData_U8(CRC_Type *const pCrc, uint8_t u8Data) +{ + pCrc->DATA.tDATA_8.LL = u8Data; +} + +/** + * @brief get data register(32 bits) + * + * @param pCrc CRC instance + * + * @return 32-bit value + */ +LOCAL_INLINE uint32_t CRC_HWA_GetData_U32(CRC_Type *const pCrc) +{ + return (pCrc->DATA.uDATA); +} + +/** + * @brief get data register(high 16 bits) + * + * @param pCrc CRC instance + * + * @return high 16-bit value + */ +LOCAL_INLINE uint16_t CRC_HWA_GetData_U16_H(CRC_Type *const pCrc) +{ + return (pCrc->DATA.tDATA_16.H); +} + +/** + * @brief get data register(low 16 bits) + * + * @param pCrc CRC instance + * + * @return low 16-bit value + */ +LOCAL_INLINE uint16_t CRC_HWA_GetData_U16_L(CRC_Type *const pCrc) +{ + return (pCrc->DATA.tDATA_16.L); +} + +/** + * @brief set data swap for writes + * + * @param pCrc CRC instance + * @param eWrDataSwap the CRC_WriteDataSwapType type + */ +LOCAL_INLINE void CRC_HWA_SetWriteDataSwap(CRC_Type *const pCrc, CRC_WriteDataSwapType eWrDataSwap) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_DSW_MASK)) | CRC_CR_DSW(eWrDataSwap)); +} + +/** + * @brief set data swap for read + * + * @param pCrc CRC instance + * @param eRdDataSwap the eRdDataSwap type + */ +LOCAL_INLINE void CRC_HWA_SetReadDataSwap(CRC_Type *const pCrc, CRC_ReadDataSwapType eRdDataSwap) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_DSR_MASK)) | CRC_CR_DSR(eRdDataSwap)); +} + +/** + * @brief set complement read Of CRC data + * + * @param pCrc CRC instance + * @param eRdDataFXOR the CRC_ReadDataFXORType type + */ +LOCAL_INLINE void CRC_HWA_SetReadDataFXOR(CRC_Type *const pCrc, CRC_ReadDataFXORType eRdDataFXOR) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_FXOR_MASK)) | CRC_CR_FXOR(eRdDataFXOR)); +} + +#if CRC_8_BIT_HARDWARE_SUPPORT +/** + * @brief set 8bit width of CRC protocol + * + * @param pCrc CRC instance + * @param eWidth the CRC_BitWidthType type + */ +LOCAL_INLINE void CRC_HWA_Set_8Bit_Width(CRC_Type *const pCrc, CRC_BitWidthType eWidth) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_TCRC8_MASK)) | CRC_CR_TCRC8(eWidth)); +} + +/** + * @brief get 8-bit width of CRC protocol + * + * @param pCrc CRC instance + */ +LOCAL_INLINE CRC_BitWidthType CRC_HWA_Get8BitWidth(CRC_Type *const pCrc) +{ + uint32_t u32TempVal = (pCrc->CR & ((uint32_t)CRC_CR_TCRC8_MASK)) >> CRC_CR_TCRC8_SHIFT; + return ((u32TempVal == 1U)?CRC_BIT_8:CRC_BIT_INVALID); +} +#endif + +/** + * @brief set width of CRC protocol + * + * @param pCrc CRC instance + * @param eWidth the CRC_BitWidthType type + */ +LOCAL_INLINE void CRC_HWA_SetBitWidth(CRC_Type *const pCrc, CRC_BitWidthType eWidth) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_TCRC_MASK)) | CRC_CR_TCRC(eWidth)); +} + +/** + * @brief get width of CRC protocol + * + * @param pCrc CRC instance + */ +LOCAL_INLINE CRC_BitWidthType CRC_HWA_GetBitWidth(CRC_Type *const pCrc) +{ + uint32_t u32TempVal = (pCrc->CR & ((uint32_t)CRC_CR_TCRC_MASK)) >> CRC_CR_TCRC_SHIFT; + return ((u32TempVal == 0U)?CRC_BIT_16:CRC_BIT_32); +} + +/** + * @brief get data swap type for read + * + * @param pCrc CRC instance + */ +LOCAL_INLINE CRC_ReadDataSwapType CRC_HWA_GetReadDataSwap(CRC_Type *const pCrc) +{ + CRC_ReadDataSwapType eRet = READ_DATASWAP_NONE; + uint32_t u32TempVal; + + u32TempVal = (pCrc->CR & ((uint32_t)CRC_CR_DSR_MASK))>>CRC_CR_DSR_SHIFT; + if (u32TempVal == 0U) + { + eRet = READ_DATASWAP_NONE; + } + else if (u32TempVal == 1U) + { + eRet = READ_DATASWAP_BIT; + } + else if (u32TempVal == 2U) + { + eRet = READ_DATASWAP_BIT_BYTE; + } + else if (u32TempVal == 3U) + { + eRet = READ_DATASWAP_BYTE; + } + else + { + /*Noting to do*/ + } + return eRet; +} + +/** @}*/ + +#endif /* #if CRC_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_CRC_H_ */ diff --git a/Inc/HwA_crm.h b/Inc/HwA_crm.h new file mode 100644 index 0000000..34c803f --- /dev/null +++ b/Inc/HwA_crm.h @@ -0,0 +1,377 @@ +/** + * @file HwA_crm.h + * @author Flagchip + * @brief CRM register API + * @version 2.5.0 + * @date 2025-08-22 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2025 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 2.5.0 2025-8-22 Flagchip112 N/A Release version for FC7300FDDT1C + ******************************************************************************** */ + +#ifndef _HWA_CRM_H_ +#define _HWA_CRM_H_ +#include "device_header.h" +#include "module_driver_flexcan.h" +#if CRM_INSTANCE_COUNT > 0U + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + +/** + * @brief CAN router interrupt type + */ +typedef enum +{ + CRM_CANR_INT_MAP_MULTI, /* Multiple mapping interrupt */ + CRM_CANR_INT_MAP_NONE, /* No mapping interrupt */ + CRM_CANR_INT_MAP_DONE, /* Mapping done interrupt */ + CRM_CANR_INT_BUSY, /* Busy interrupt */ + CRM_CANR_INT_MAP_SELF /* Self mapping interrupt */ +} CRM_IntType; + +/** + * @brief Structure for CRM interrupt mask configuration + * + * Bitfield configuration matches CRM_CANR_IEN register layout: + * - MAP_MULTI_IE: Multiple mapping error flag interrupt enable (bit31) + * - MAP_NONE_IE: No mapping error flag interrupt enable (bit30) + * - MAP_DONE_IE: Mapping completion flag interrupt enable (bit24) + * - BUSY_IE: Busy state flag interrupt enable (bit8) + * - MAP_SELF_IE: Self-mapping flag interrupt enable (bit0) + */ +typedef struct +{ + bool bMapMultiIE; + bool bMapNoneIE; + bool bMapDoneIE; + bool bBusyIE; + bool bMapSelfIE; +} CRM_IntMaskType; + +/********* Local inline function ************/ +/* ---------------------------- Channel Registers ----------------------------- */ +/** + * @brief Set MATCH_ID0 register for specified channel + * @param ch Channel number (CRM_CH0-CRM_CH3) + * @param u32val Value to set + */ +LOCAL_INLINE void CRM_HWA_Set_CH_MATCH_ID0(CRM_ChannelIndex eChannel, FLEXCAN_IdType eIdType, uint32_t u32val) +{ + uint32_t u32valtemp = 0; + if(FLEXCAN_ID_STD == eIdType) + { + u32valtemp = u32val << 18; + }else + { + u32valtemp = u32val; + } + switch (eChannel) + { + case CRM_CH0: CRM->CH0_MATCH_ID0 = u32valtemp; break; + case CRM_CH1: CRM->CH1_MATCH_ID0 = u32valtemp; break; + case CRM_CH2: CRM->CH2_MATCH_ID0 = u32valtemp; break; + case CRM_CH3: CRM->CH3_MATCH_ID0 = u32valtemp; break; + default: break; + } +} + +/** + * @brief Set MATCH_ID1 register for specified channel + * @param ch Channel number (CRM_CH0-CRM_CH3) + * @param u32val Value to set + */ +LOCAL_INLINE void CRM_HWA_Set_CH_MATCH_ID1(CRM_ChannelIndex eChannel, FLEXCAN_IdType eIdType, uint32_t u32val) +{ + uint32_t u32valtemp = 0; + if(FLEXCAN_ID_STD == eIdType) + { + u32valtemp = u32val << 18; + }else + { + u32valtemp = u32val; + } + switch (eChannel) + { + case CRM_CH0: CRM->CH0_MATCH_ID1 = u32valtemp; break; + case CRM_CH1: CRM->CH1_MATCH_ID1 = u32valtemp; break; + case CRM_CH2: CRM->CH2_MATCH_ID1 = u32valtemp; break; + case CRM_CH3: CRM->CH3_MATCH_ID1 = u32valtemp; break; + default: break; + } +} + +/** + * @brief Set ROUTER_ID0 register for specified channel + * @param ch Channel number (CRM_CH0-CRM_CH3) + * @param u32val Value to set + */ +LOCAL_INLINE void CRM_HWA_Set_CH_ROUTER_ID0(CRM_ChannelIndex ch, FLEXCAN_IdType eIdType, uint32_t u32val) +{ + uint32_t u32valtemp = 0; + if(FLEXCAN_ID_STD == eIdType) + { + u32valtemp = u32val << 18; + }else + { + u32valtemp = u32val; + } + switch (ch) + { + case CRM_CH0: CRM->CH0_ROUTER_ID0 = u32valtemp; break; + case CRM_CH1: CRM->CH1_ROUTER_ID0 = u32valtemp; break; + case CRM_CH2: CRM->CH2_ROUTER_ID0 = u32valtemp; break; + case CRM_CH3: CRM->CH3_ROUTER_ID0 = u32valtemp; break; + default: break; + } +} + +/** + * @brief Set ROUTER_CS0 register for specified channel + * @param ch Channel number (CRM_CH0-CRM_CH3) + * @param u32val Value to set + */ +LOCAL_INLINE void CRM_HWA_Set_CH_ROUTER_CS0(CRM_ChannelIndex ch, uint32_t u32val) +{ + switch (ch) + { + case CRM_CH0: CRM->CH0_ROUTER_CS0 = u32val; break; + case CRM_CH1: CRM->CH1_ROUTER_CS0 = u32val; break; + case CRM_CH2: CRM->CH2_ROUTER_CS0 = u32val; break; + case CRM_CH3: CRM->CH3_ROUTER_CS0 = u32val; break; + default: break; + } +} + +/** + * @brief Set ROUTER_ID1 register for specified channel + * @param ch Channel number (CRM_CH0-CRM_CH3) + * @param u32val Value to set + */ +LOCAL_INLINE void CRM_HWA_Set_CH_ROUTER_ID1(CRM_ChannelIndex ch, FLEXCAN_IdType eIdType, uint32_t u32val) +{ + uint32_t u32valtemp = 0; + if(FLEXCAN_ID_STD == eIdType) + { + u32valtemp = u32val << 18; + }else + { + u32valtemp = u32val; + } + switch (ch) + { + case CRM_CH0: CRM->CH0_ROUTER_ID1 = u32valtemp; break; + case CRM_CH1: CRM->CH1_ROUTER_ID1 = u32valtemp; break; + case CRM_CH2: CRM->CH2_ROUTER_ID1 = u32valtemp; break; + case CRM_CH3: CRM->CH3_ROUTER_ID1 = u32valtemp; break; + default: break; + } +} + +/** + * @brief Set ROUTER_CS1 register for specified channel + * @param ch Channel number (CRM_CH0-CRM_CH3) + * @param u32val Value to set + */ +LOCAL_INLINE void CRM_HWA_Set_CH_ROUTER_CS1(CRM_ChannelIndex ch, uint32_t u32val) +{ + switch (ch) + { + case CRM_CH0: CRM->CH0_ROUTER_CS1 = u32val; break; + case CRM_CH1: CRM->CH1_ROUTER_CS1 = u32val; break; + case CRM_CH2: CRM->CH2_ROUTER_CS1 = u32val; break; + case CRM_CH3: CRM->CH3_ROUTER_CS1 = u32val; break; + default: break; + } +} + +/** + * @brief Set MATCH_MASK register for specified channel + * @param ch Channel number (CRM_CH0-CRM_CH3) + * @param u32val Value to set + */ +LOCAL_INLINE void CRM_HWA_Set_CH_MATCH_MASK(CRM_ChannelIndex ch, FLEXCAN_IdType eIdType, uint32_t u32val) +{ + uint32_t u32valtemp = 0; + if(FLEXCAN_ID_STD == eIdType) + { + u32valtemp = u32val << 18; + }else + { + u32valtemp = u32val; + } + switch (ch) + { + case CRM_CH0: CRM->CH0_MATCH_MASK = u32valtemp; break; + case CRM_CH1: CRM->CH1_MATCH_MASK = u32valtemp; break; + case CRM_CH2: CRM->CH2_MATCH_MASK = u32valtemp; break; + case CRM_CH3: CRM->CH3_MATCH_MASK = u32valtemp; break; + default: break; + } +} + +/** + * @brief Get MAP_CS register value for specified channel (read-only) + * @param ch Channel number (CRM_CH0-CRM_CH3) + * @return Register value + */ +LOCAL_INLINE uint32_t CRM_HWA_Get_CH_MAP_CS(CRM_ChannelIndex ch) +{ + switch (ch) + { + case CRM_CH0: return CRM->CH0_MAP_CS; + case CRM_CH1: return CRM->CH1_MAP_CS; + case CRM_CH2: return CRM->CH2_MAP_CS; + case CRM_CH3: return CRM->CH3_MAP_CS; + default: return 0; + } +} + +/** + * @brief Get MAP_ID register value for specified channel (read-only) + * @param ch Channel number (CRM_CH0-CRM_CH3) + * @return Register value + */ +LOCAL_INLINE uint32_t CRM_HWA_Get_CH_MAP_ID(CRM_ChannelIndex ch) +{ + switch (ch) + { + case CRM_CH0: return CRM->CH0_MAP_ID; + case CRM_CH1: return CRM->CH1_MAP_ID; + case CRM_CH2: return CRM->CH2_MAP_ID; + case CRM_CH3: return CRM->CH3_MAP_ID; + default: return 0; + } +} + +/* -------------------------- CAN Router Registers ---------------------------- */ +/** + * @brief Enable specific CAN router interrupt + * @param eIntType Interrupt type to enable + * @param chMask Channel mask (only for channel-specific interrupts) + */ +LOCAL_INLINE void CRM_HWA_EnableCanrInt(CRM_ChannelIndex ch, CRM_IntMaskType chMask) +{ + uint32_t u32RegVal = CRM->CANR_IEN; + u32RegVal |= CRM_CANR_STATUS_MAP_MULTI_FLAG(chMask.bMapMultiIE); + u32RegVal |= CRM_CANR_STATUS_MAP_NONE_FLAG(chMask.bMapNoneIE); + u32RegVal |= CRM_CANR_STATUS_MAP_DONE_FLAG((chMask.bMapDoneIE) << ch); + u32RegVal |= CRM_CANR_STATUS_BUSY_FLAG((chMask.bBusyIE) << ch); + u32RegVal |= CRM_CANR_STATUS_MAP_SELF_FLAG((chMask.bMapSelfIE) << ch); + CRM->CANR_IEN = u32RegVal; +} + +/** + * @brief Disable specific CAN router interrupt + * @param eIntType Interrupt type to disable + * @param chMask Channel mask (only for channel-specific interrupts) + */ +LOCAL_INLINE void CRM_HWA_DisableCanrInt(CRM_ChannelIndex ch) +{ + uint32_t u32RegVal = 0; + u32RegVal |= CRM_CANR_STATUS_MAP_MULTI_FLAG(1U); + u32RegVal |= CRM_CANR_STATUS_MAP_NONE_FLAG(1U); + u32RegVal |= CRM_CANR_STATUS_MAP_DONE_FLAG(1U << ch); + u32RegVal |= CRM_CANR_STATUS_BUSY_FLAG(1U << ch); + u32RegVal |= CRM_CANR_STATUS_MAP_SELF_FLAG(1U << ch); + CRM->CANR_IEN &= ~u32RegVal; +} + +/** + * @brief Get CANR_STATUS register value + * @return Register value + */ +LOCAL_INLINE uint32_t CRM_HWA_Get_CANR_STATUS(void) +{ + return CRM->CANR_STATUS; +} + +/** + * @brief Clear specific status flag in CANR_STATUS + * @param eIntType Status flag type to clear + * @param chMask Channel mask (only for channel-specific flags) + */ +LOCAL_INLINE void CRM_HWA_ClearCanrStatus(CRM_IntType eIntType, uint8_t chMask) +{ + uint32_t u32RegVal = CRM->CANR_STATUS; + + switch (eIntType) + { + case CRM_CANR_INT_MAP_MULTI: + u32RegVal &= ~CRM_CANR_STATUS_MAP_MULTI_FLAG_MASK; + break; + + case CRM_CANR_INT_MAP_NONE: + u32RegVal &= ~CRM_CANR_STATUS_MAP_NONE_FLAG_MASK; + break; + + case CRM_CANR_INT_MAP_DONE: + u32RegVal &= ~(chMask << CRM_CANR_STATUS_MAP_DONE_FLAG_SHIFT); + break; + + case CRM_CANR_INT_BUSY: + u32RegVal &= ~(chMask << CRM_CANR_STATUS_BUSY_FLAG_SHIFT); + break; + + case CRM_CANR_INT_MAP_SELF: + u32RegVal &= ~(chMask << CRM_CANR_STATUS_MAP_SELF_FLAG_SHIFT); + break; + + default: + break; + } + + CRM->CANR_STATUS = u32RegVal; +} + +/** + * @brief Set CANR_CTRL register value + * @param u32val Value to set + */ +LOCAL_INLINE void CRM_HWA_Set_CANR_CTRL(uint32_t u32val) +{ + CRM->CANR_CTRL = u32val & CRM_CANR_CTRL_MASK; +} + +/** + * @brief Get CANR_CTRL register value + * @return Register value + */ +LOCAL_INLINE uint32_t CRM_HWA_Get_CANR_CTRL(void) +{ + return CRM->CANR_CTRL; +} + +/** + * @brief Enable specific channel in CAN router + * @param ch Channel to enable + */ +LOCAL_INLINE void CRM_HWA_EnableChannel(CRM_ChannelIndex ch) +{ + CRM->CANR_CTRL |= (1 << ch); +} + +/** + * @brief Disable specific channel in CAN router + * @param ch Channel to disable + */ +LOCAL_INLINE void CRM_HWA_DisableChannel(CRM_ChannelIndex ch) +{ + CRM->CANR_CTRL &= ~(1 << ch); +} + +/** @}*/ + +#endif /* CRM_INSTANCE_COUNT > 0U */ + +#endif /* HWA_INCLUDE_HWA_crm_H_ */ diff --git a/Inc/HwA_csc.h b/Inc/HwA_csc.h new file mode 100644 index 0000000..5555ac1 --- /dev/null +++ b/Inc/HwA_csc.h @@ -0,0 +1,1294 @@ +/** + * @file HwA_csc.h + * @author flagchip + * @brief Hardware access layer for CSC + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip055 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip055 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_CSC_H_ +#define _HWA_CSC_H_ + +#include "device_header.h" + +#if CSC0_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_csc HwA_csc + * @ingroup module_driver_csc + * @{ + */ + +/********* Local typedef ************/ +/** + * @brief CSC0 clock out divide ratio type + * + */ +typedef enum +{ + CSC0_CLKOUT_DIV_BY1 = 0U, /*!< Divided by 1 */ + CSC0_CLKOUT_DIV_BY2 = 1U, /*!< Divided by 2 */ + CSC0_CLKOUT_DIV_BY3 = 2U, /*!< Divided by 3 */ + CSC0_CLKOUT_DIV_BY4 = 3U, /*!< Divided by 4 */ + CSC0_CLKOUT_DIV_BY5 = 4U, /*!< Divided by 5 */ + CSC0_CLKOUT_DIV_BY6 = 5U, /*!< Divided by 6 */ + CSC0_CLKOUT_DIV_BY7 = 6U, /*!< Divided by 7 */ + CSC0_CLKOUT_DIV_BY8 = 7U /*!< Divided by 8 */ +} CSC0_ClockOutDivType; + +/** + * @brief CSC0 clock out source type + * + */ +typedef enum +{ + CSC0_CLKOUT_SCG_CLKOUT = 0U, /*!< SCG CLKOUT */ + CSC0_CLKOUT_FOSC_DIVM_CLK = 2U, /*!< FOSC DIVM CLK */ + CSC0_CLKOUT_SLOW_CLK = 3U, /*!< SLOW CLK */ + CSC0_CLKOUT_SIRC_DIVM_CLK = 4U, /*!< SIRC DIVM CLK */ + CSC0_CLKOUT_PLL1_DIVM_CLK = 5U, /*!< PLL1 DIVM CLK */ + CSC0_CLKOUT_FIRC_DIVM_CLK = 6U, /*!< FIRC DIVM CLK */ + CSC0_CLKOUT_CORE_CLK = 7U, /*!< CORE CLK */ + CSC0_CLKOUT_PLL0_DIVM_CLK = 8U, /*!< PLL0 DIVM CLK */ + CSC0_CLKOUT_BUS_CLK = 9U, /*!< BUS CLK */ + CSC0_CLKOUT_SIRC_128K_CLK = 10U, /*!< SIRC 128K CLK */ + CSC0_CLKOUT_AON_CLK = 12U, /*!< AON CLK */ + CSC0_CLKOUT_RTC_CLK = 14U /*!< AON32K CLK */ +} CSC0_ClockOutSrcType; + +/** + * @brief Data type for CSC0_AONCLKSR[32KAONCLKSEL], set AON32KCLK source clock + * + */ +typedef enum +{ + CSC0_AON32K_SIRCDIV_32K_CLK = 1U, /*!< CSC0_AONCLKSR[32KAONCLKSEL], SIRCDIV_32K */ + CSC0_AON32K_SOSC32K_CLK = 2U, /*!< CSC0_AONCLKSR[32KAONCLKSEL], SOSC32K */ + CSC0_AON32K_SIRC32K_CLK = 3U /*!< CSC0_AONCLKSR[32KAONCLKSEL], SIRC32K */ +} CSC0_AON32KClkSrcType; + +/** + * @brief Data type for CSC0_RTCCLKSEL[RTCCLKSEL], set RTCCLK source clock + * + */ +typedef enum +{ + CSC0_RTC_FOSCDIVL_CLK = 0U, /*!< CSC0_RTCCLKSEL[RTCCLKSEL], FOSC_DIVL */ + CSC0_RTC_SIRCDIV_32K_CLK = 1U, /*!< CSC0_RTCCLKSEL[RTCCLKSEL], SIRC_DIV */ + CSC0_RTC_SOSC_CLK = 2U, /*!< CSC0_RTCCLKSEL[RTCCLKSEL], SOSC */ + CSC0_RTC_SIRC32K_CLK = 3U /*!< CSC0_RTCCLKSEL[RTCCLKSEL], SIRC_32K */ +} CSC0_RTCClkSrcType; + +/** + * @brief Data type for CSC0_AONCLKSEL[AONCLKSEL], set AONCLK source clock + * + */ +typedef enum +{ + CSC0_AON_SIRCDIV_128K_CLK = 0U, /*!< CSC0_AONCLKSEL[AONCLKSEL], SIRCDIV_128K */ + CSC0_AON_SIRC32K_CLK = 1U, /*!< CSC0_AONCLKSEL[AONCLKSEL], SIRC32K */ + CSC0_AON_SIRCDIV_32K_CLK = 2U, /*!< CSC0_AONCLKSEL[AONCLKSEL], SIRCDIV_32K */ + CSC0_AON_SIRC32_1K_CLK = 3U /*!< CSC0_AONCLKSEL[AONCLKSEL], SIRC32_1K */ +} CSC0_AONClkSrcType; + +#endif /* #if CSC0_INSTANCE_COUNT > 0U */ + +/********* Local inline function ************/ +/****** Operation on CSC0_xxxRegister0 ******/ +#if CSC0_INSTANCE_COUNT > 0U +/** + * @brief Set stop mode register 0 + * + */ +LOCAL_INLINE void CSC0_HWA_Set_STOP_MODER0(uint32_t u32val) +{ + CSC0->STOP_MODER0 = u32val; +} + +/** + * @brief Get stop mode register 0 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_STOP_MODER0(void) +{ + return CSC0->STOP_MODER0; +} + +/** + * @brief Set stop request register 0 + * + */ +LOCAL_INLINE void CSC0_HWA_Set_STOP_REQR0(uint32_t u32val) +{ + CSC0->STOP_REQR0 = u32val; +} + +/** + * @brief Get stop request register 0 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_STOP_REQR0(void) +{ + return CSC0->STOP_REQR0; +} + +/** + * @brief Get stop ack status in register 0 + * + * @return Register ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_STOP_ACKR0(void) +{ + return CSC0->STOP_ACKR0; +} + +/****** Operation on CSC0_xxxRegister1 ******/ +/** + * @brief Set stop mode register 1 + * + */ +LOCAL_INLINE void CSC0_HWA_Set_STOP_MODER1(uint32_t u32val) +{ + CSC0->STOP_MODER1 = u32val; +} + +/** + * @brief Get stop mode register 1 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_STOP_MODER1(void) +{ + return CSC0->STOP_MODER1; +} + +/** + * @brief Set stop request register 1 + * + */ +LOCAL_INLINE void CSC0_HWA_Set_STOP_REQR1(uint32_t u32val) +{ + CSC0->STOP_REQR1 = u32val; +} + +/** + * @brief Get stop request register 1 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_STOP_REQR1(void) +{ + return CSC0->STOP_REQR1; +} + +/** + * @brief Get stop ack status in register 1 + * + * @return Register ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_STOP_ACKR1(void) +{ + return CSC0->STOP_ACKR1; +} + +/****** Operation on CSC0_xxxRegister2 ******/ +/** + * @brief Set stop mode register 2 + * + */ +LOCAL_INLINE void CSC0_HWA_Set_STOP_MODER2(uint32_t u32val) +{ + CSC0->STOP_MODER2 = u32val; +} + +/** + * @brief Get stop mode register 2 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_STOP_MODER2(void) +{ + return CSC0->STOP_MODER2; +} + +/** + * @brief Set stop request register 2 + * + */ +LOCAL_INLINE void CSC0_HWA_Set_STOP_REQR2(uint32_t u32val) +{ + CSC0->STOP_REQR2 = u32val; +} + +/** + * @brief Get stop request register 2 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_STOP_REQR2(void) +{ + return CSC0->STOP_REQR2; +} + +/** + * @brief Get stop ack status in register 2 + * + * @return Register ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_STOP_ACKR2(void) +{ + return CSC0->STOP_ACKR2; +} + +/** + * @brief Set CCM0 configure register + * + */ +LOCAL_INLINE void CSC0_HWA_Set_CCM0_CFG(uint32_t u32val) +{ + CSC0->CCM0_CFG = u32val; +} + +/** + * @brief Get CCM0 configure + * @return Register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_CCM0_CFG(void) +{ + return CSC0->CCM0_CFG; +} + +/** + * @brief Set SCG MAM stall request register + * + */ +LOCAL_INLINE void CSC0_HWA_Set_SCG_MAM_STALL(uint32_t u32val) +{ + CSC0->SCG_MAM_STALL = u32val; +} + +/** + * @brief Get SCG MAM stall request register + * @return Register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_SCG_MAM_STALL(void) +{ + return CSC0->SCG_MAM_STALL; +} + +/** + * @brief Set cpu0 software interrupt register + * + */ +LOCAL_INLINE void CSC0_HWA_Set_CPU0_INT(uint32_t u32val) +{ + CSC0->CPU0_INT = u32val; +} + +/** + * @brief Get cpu0 software interrupt register + * @return Register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_CPU0_INT(void) +{ + return CSC0->CPU0_INT; +} + +/** + * @brief Enable cpu0 software interrupt + * + */ +LOCAL_INLINE void CSC0_HWA_EnableCpu0SWInterrupt(void) +{ + CSC0->CPU0_INT |= (uint32_t)CSC0_CPU0_INT_SW_INT_MASK; +} + +/** + * @brief Disable cpu0 software interrupt + * + */ +LOCAL_INLINE void CSC0_HWA_DisableCpu0SWInterrupt(void) +{ + CSC0->CPU0_INT &= ~(uint32_t)CSC0_CPU0_INT_SW_INT_MASK; +} + +#if CSC0_CLOCKCONFIG_SUPPORT +/** + * @brief Set clock out control register + * + */ +LOCAL_INLINE void CSC0_HWA_Set_CLKOUT_CTRL(uint32_t u32val) +{ + CSC0->CLKOUT_CTRL = u32val; +} + +/** + * @brief Get clock out control register + * @return Register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_CLKOUT_CTRL(void) +{ + return CSC0->CLKOUT_CTRL; +} + +/** + * @brief Enable CSC0 clock out + * + */ +LOCAL_INLINE void CSC0_HWA_EnableClockOut(void) +{ + CSC0->CLKOUT_CTRL |= (uint32_t)CSC0_CLKOUT_CTRL_CLKOUT_EN_MASK; +} + +/** + * @brief Disable CSC0 clock out + * + */ +LOCAL_INLINE void CSC0_HWA_DisableClockOut(void) +{ + CSC0->CLKOUT_CTRL &= ~(uint32_t)CSC0_CLKOUT_CTRL_CLKOUT_EN_MASK; +} + +/** + * @brief Get CLKOUT source Select + * + * @return CSC0_ClockOutSrcType CSC0 clock out source + */ +LOCAL_INLINE CSC0_ClockOutSrcType CSC0_HWA_GetClkOutSel(void) +{ + uint32_t u32RegVal = (CSC0->CLKOUT_CTRL & CSC0_CLKOUT_CTRL_CLKOUT_SEL_MASK) >> CSC0_CLKOUT_CTRL_CLKOUT_SEL_SHIFT; + return (CSC0_ClockOutSrcType)u32RegVal; +} + +/** + * @brief Get CLKOUT CSC0 clock out divider + * + * @return CSC0_ClockOutDivType CSC0 clock out divider + */ +LOCAL_INLINE CSC0_ClockOutDivType CSC0_HWA_GetClkOutDiv(void) +{ + uint32_t u32RegVal = (CSC0->CLKOUT_CTRL & CSC0_CLKOUT_CTRL_CLKOUT_DIV_MASK) >> CSC0_CLKOUT_CTRL_CLKOUT_DIV_SHIFT; + return (CSC0_ClockOutDivType)u32RegVal; +} + +/** + * @brief Set CLKOUTDIV + * + * @param eDivType CSC0 clock out devide ratio type + */ +LOCAL_INLINE void CSC0_HWA_SetClkOutDiv(CSC0_ClockOutDivType eDivType) +{ + uint32_t u32RegVal = CSC0->CLKOUT_CTRL; + CSC0->CLKOUT_CTRL = ((u32RegVal & (~(uint32_t)CSC0_CLKOUT_CTRL_CLKOUT_DIV_MASK)) | CSC0_CLKOUT_CTRL_CLKOUT_DIV(eDivType)); +} + +/** + * @brief Set CLKOUT Select + * + * @param eClkSrcType CSC0 clock out devide ratio type + */ +LOCAL_INLINE void CSC0_HWA_SetClkOutSel(CSC0_ClockOutSrcType eClkSrcType) +{ + uint32_t u32RegVal = CSC0->CLKOUT_CTRL; + CSC0->CLKOUT_CTRL = ((u32RegVal & (~(uint32_t)CSC0_CLKOUT_CTRL_CLKOUT_SEL_MASK)) | CSC0_CLKOUT_CTRL_CLKOUT_SEL(eClkSrcType)); +} + +/** + * @brief Lock CSC0_CLKOUT_CTRL register + * + */ +LOCAL_INLINE void CSC0_HWA_LockCLKOUT_CTRL(void) +{ + CSC0->CLKOUT_CTRL |= (uint32_t)CSC0_CLKOUT_CTRL_LOCK_MASK; +} + +/** + * @brief Unlock CSC0_CLKOUT_CTRL register + * + */ +LOCAL_INLINE void CSC0_HWA_UnlockCLKOUT_CTRL(void) +{ + CSC0->CLKOUT_CTRL &= ~(uint32_t)CSC0_CLKOUT_CTRL_LOCK_MASK; +} + +/** + * @brief Get CSC0_CLKOUT_CTRL register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_CLKOUT_CTRL_GetLockStatus(void) +{ + return (CSC0->CLKOUT_CTRL & (uint32_t)CSC0_CLKOUT_CTRL_LOCK_MASK); +} + +/** + * @brief Set AONCLKSR register + * + */ +LOCAL_INLINE void CSC0_HWA_Set_AONCLKSR(uint32_t u32val) +{ + CSC0->AONCLKSR = u32val; +} + +/** + * @brief Get AONCLKSR register status + * + * @return AONCLKSR register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_AONCLKSR(void) +{ + return CSC0->AONCLKSR; +} + +/** + * @brief Set CSC0_AON32KCLK source clock + * + * @param CSC0_AON32KClkSrcType CSC0_AON32KCLK source type + */ +LOCAL_INLINE void CSC0_HWA_SetAON32kClkSrc(CSC0_AON32KClkSrcType eClkSrcType) +{ + uint32_t u32RegVal = CSC0->AONCLKSR; + CSC0->AONCLKSR = ((u32RegVal & (~(uint32_t)CSC0_AONCLKSR_AON32KCLKSEL_MASK)) | CSC0_AONCLKSR_AON32KCLKSEL(eClkSrcType)); +} + +/** + * @brief Set CSC0_RTCCLK source clock + * + * @param CSC0_RTCClkSrcType CSC0_RTCCLK source type + */ +LOCAL_INLINE void CSC0_HWA_SetRTCClkSrc(CSC0_RTCClkSrcType eClkSrcType) +{ + uint32_t u32RegVal = CSC0->AONCLKSR; + CSC0->AONCLKSR = ((u32RegVal & (~(uint32_t)CSC0_AONCLKSR_RTCCLKSEL_MASK)) | CSC0_AONCLKSR_RTCCLKSEL(eClkSrcType)); +} + +/** + * @brief Set CSC0_AONCLK source clock + * + * @param CSC0_AONClkSrcType CSC0_AONCLK source type + */ +LOCAL_INLINE void CSC0_HWA_SetAONClkSrc(CSC0_AONClkSrcType eClkSrcType) +{ + uint32_t u32RegVal = CSC0->AONCLKSR; + CSC0->AONCLKSR = ((u32RegVal & (~(uint32_t)CSC0_AONCLKSR_AONCLKSEL_MASK)) | CSC0_AONCLKSR_AONCLKSEL(eClkSrcType)); +} + +/** + * @brief Enable CSC0_SIRCDIV32K clock out + * + */ +LOCAL_INLINE void CSC0_HWA_EnableSIRCDIV_32KClkOut(void) +{ + CSC0->AONCLKSR |= (uint32_t)CSC0_AONCLKSR_SIRCDIV32KEN_MASK; +} + +/** + * @brief Disable CSC0_SIRCDIV32K clock out + * + */ +LOCAL_INLINE void CSC0_HWA_DisableSIRCDIV_32KClkOut(void) +{ + CSC0->AONCLKSR &= ~(uint32_t)CSC0_AONCLKSR_SIRCDIV32KEN_MASK; +} + +/** + * @brief Enable CSC0_SIRC32_1K clock out + * + */ +LOCAL_INLINE void CSC0_HWA_EnableSIRC32_1KClkOut(void) +{ + CSC0->AONCLKSR |= (uint32_t)CSC0_AONCLKSR_AON1KCLKEN_MASK; +} + +/** + * @brief Disable CSC0_SIRC32_1K clock out + * + */ +LOCAL_INLINE void CSC0_HWA_DisableSIRC32_1KClkOut(void) +{ + CSC0->AONCLKSR &= ~(uint32_t)CSC0_AONCLKSR_AON1KCLKEN_MASK; +} + +/** + * @brief Lock CSC0_AONCLKSR register + * + */ +LOCAL_INLINE void CSC0_HWA_LockAONCLKSR(void) +{ + CSC0->AONCLKSR |= (uint32_t)CSC0_AONCLKSR_LOCK_MASK; +} + +/** + * @brief Unlock CSC0_AONCLKSR register + * + */ +LOCAL_INLINE void CSC0_HWA_UnlockAONCLKSR(void) +{ + CSC0->AONCLKSR &= ~(uint32_t)CSC0_AONCLKSR_LOCK_MASK; +} + +/** + * @brief Get CSC0_AONCLKSR register status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_AONCLKSR_GetLockStaus(void) +{ + return (CSC0->AONCLKSR & (uint32_t)CSC0_AONCLKSR_LOCK_MASK); +} + +/** + * @brief Set PCU control register + * + */ +LOCAL_INLINE void CSC0_HWA_Set_PCU_CTRL(uint32_t u32val) +{ + CSC0->PCU_CTRL = u32val; +} + +/** + * @brief Get PCU control register + * @return Register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_PCU_CTRL(void) +{ + return CSC0->PCU_CTRL; +} + +/** + * @brief Get count of reduce power mode exit + * + * @return count be got + */ +LOCAL_INLINE uint8_t CSC0_HWA_GetRpmExitCount(void) +{ + return (uint8_t)((CSC0->PCU_CTRL & (uint32_t)CSC0_PCU_CTRL_RPM_EXIT_CNT_MASK)>>CSC0_PCU_CTRL_RPM_EXIT_CNT_SHIFT); +} + +/** + * @brief Set CSC_CMU control group register + * + * @param u32Value Value to be set + */ +LOCAL_INLINE void CSC0_HWA_Set_CMU_CTRL(uint32_t u32Value) +{ + CSC0->CMU_CTRL = u32Value; +} + +/** + * @brief Get CSC_CMU control group register status + * + * @return register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_CMU_CTRL(void) +{ + return CSC0->CMU_CTRL; +} +#endif + +/** + * @brief Set multi CSC_SMU control group 0 + * + * @param u32Value Value to be set + */ +LOCAL_INLINE void CSC0_HWA_Set_SMU_CTRL0(uint32_t u32Value) +{ + CSC0->SMU_CTRL0 = u32Value; +} + +/** + * @brief Get CSC0_SMU_CTRL0 register status + * + * @return register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_SMU_CTRL0(void) +{ + return CSC0->SMU_CTRL0; +} + +/** + * @brief Set multi CSC_SMU control group 1 + * + * @param u32Value Value to be set + */ +LOCAL_INLINE void CSC0_HWA_Set_SMU_CTRL1(uint32_t u32Value) +{ + CSC0->SMU_CTRL1 = u32Value; +} + +/** + * @brief Get CSC0_SMU_CTRL1 register status + * + * @return register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_SMU_CTRL1(void) +{ + return CSC0->SMU_CTRL1; +} + +/** + * @brief Set multi CSC_SMU control group 4 + * + * @param u32Value Value to be set + */ +LOCAL_INLINE void CSC0_HWA_Set_SMU_CTRL4(uint32_t u32Value) +{ + CSC0->SMU_CTRL4 = u32Value; +} + +/** + * @brief Get CSC0_SMU_CTRL4 register status + * + * @return register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_SMU_CTRL4(void) +{ + return CSC0->SMU_CTRL4; +} + +#if CSC0_SMU_CTRL5_SUPPORT +/** + * @brief Set multi CSC_SMU control group 5 + * + * @param u32Value Value to be set + */ +LOCAL_INLINE void CSC0_HWA_Set_SMU_CTRL5(uint32_t u32Value) +{ + CSC0->SMU_CTRL5 = u32Value; +} + +/** + * @brief Get CSC0_SMU_CTRL5 register status + * + * @return register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_SMU_CTRL5(void) +{ + return CSC0->SMU_CTRL5; +} +#endif /* CSC0_SMU_CTRL5_SUPPORT */ + +#if CSC0_LP_WAKEUP_SUPPORT +/** + * @brief Set LP_WAKEUP register + * + * @param u32Value Value to be set + */ +LOCAL_INLINE void CSC0_HWA_Set_LP_WAKEUP(uint32_t u32Value) +{ + CSC0->LP_WAKEUP = u32Value; +} + +/** + * @brief Get LP_WAKEUP register status + * + * @return register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_Get_LP_WAKEUP(void) +{ + return CSC0->LP_WAKEUP; +} +#endif /* CSC0_LP_WAKEUP_SUPPORT */ + +#endif /* CSC0_INSTANCE_COUNT > 0U */ + +#if CSC1_INSTANCE_COUNT > 0U +/****** Operation on CSC1_xxxRegister0 ******/ +/** @brief Set stop mode register 0 + * + */ +LOCAL_INLINE void CSC1_HWA_Set_STOP_MODER0(uint32_t u32val) +{ + CSC1->STOP_MODER0 = u32val; +} + +/** + * @brief Get stop mode register 0 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC1_HWA_Get_STOP_MODER0(void) +{ + return CSC1->STOP_MODER0; +} + +/** + * @brief Set stop request register 0 + * + */ +LOCAL_INLINE void CSC1_HWA_Set_STOP_REQR0(uint32_t u32val) +{ + CSC1->STOP_REQR0 = u32val; +} + +/** + * @brief Get stop request register 0 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC1_HWA_Get_STOP_REQR0(void) +{ + return CSC1->STOP_REQR0; +} + +/** + * @brief Get stop ack status in register 0 + * + * @return Register ack status + */ +LOCAL_INLINE uint32_t CSC1_HWA_Get_STOP_ACKR0(void) +{ + return CSC1->STOP_ACKR0; +} + +/****** Operation on CSC1_xxxRegister1 ******/ +/** + * @brief Set stop mode register 1 + * + */ +LOCAL_INLINE void CSC1_HWA_Set_STOP_MODER1(uint32_t u32val) +{ + CSC1->STOP_MODER1 = u32val; +} + +/** + * @brief Get stop mode register 1 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC1_HWA_Get_STOP_MODER1(void) +{ + return CSC1->STOP_MODER1; +} + +/** + * @brief Set stop request register 1 + * + */ +LOCAL_INLINE void CSC1_HWA_Set_STOP_REQR1(uint32_t u32val) +{ + CSC1->STOP_REQR1 = u32val; +} + +/** + * @brief Get stop request register 1 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC1_HWA_Get_STOP_REQR1(void) +{ + return CSC1->STOP_REQR1; +} + +/** + * @brief Get stop ack status in register 1 + * + * @return Register ack status + */ +LOCAL_INLINE uint32_t CSC1_HWA_Get_STOP_ACKR1(void) +{ + return CSC1->STOP_ACKR1; +} + +/****** Operation on CSC1_xxxRegister2 ******/ +/** + * @brief Set stop mode register 2 + * + */ +LOCAL_INLINE void CSC1_HWA_Set_STOP_MODER2(uint32_t u32val) +{ + CSC1->STOP_MODER2 = u32val; +} + +/** + * @brief Get stop mode register 2 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC1_HWA_Get_STOP_MODER2(void) +{ + return CSC1->STOP_MODER2; +} + +/** + * @brief Set stop request register 2 + * + */ +LOCAL_INLINE void CSC1_HWA_Set_STOP_REQR2(uint32_t u32val) +{ + CSC1->STOP_REQR2 = u32val; +} + +/** + * @brief Get stop request register 2 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC1_HWA_Get_STOP_REQR2(void) +{ + return CSC1->STOP_REQR2; +} + +/** + * @brief Get stop ack status in register 2 + * + * @return Register ack status + */ +LOCAL_INLINE uint32_t CSC1_HWA_Get_STOP_ACKR2(void) +{ + return CSC1->STOP_ACKR2; +} + +/** + * @brief Set CCM0 configure register + * + */ +LOCAL_INLINE void CSC1_HWA_Set_CCM1_CFG(uint32_t u32val) +{ + CSC1->CCM1_CFG = u32val; +} + +/** + * @brief Get CCM0 configure + * @return Register status + */ +LOCAL_INLINE uint32_t CSC1_HWA_Get_CCM1_CFG(void) +{ + return CSC1->CCM1_CFG; +} + +/** + * @brief Set cpu0 software interrupt register + * + */ +LOCAL_INLINE void CSC1_HWA_Set_CPU1_INT(uint32_t u32val) +{ + CSC1->CPU1_INT = u32val; +} + +/** + * @brief Get cpu1 software interrupt register + * @return Register status + */ +LOCAL_INLINE uint32_t CSC1_HWA_Get_CPU1_INT(void) +{ + return CSC1->CPU1_INT; +} + +/** + * @brief Enable cpu1 software interrupt + * + */ +LOCAL_INLINE void CSC1_HWA_EnableCpu1SWInterrupt(void) +{ + CSC1->CPU1_INT |= (uint32_t)CSC1_CPU1_INT_SW_INT_MASK; +} + +/** + * @brief Disable cpu1 software interrupt + * + */ +LOCAL_INLINE void CSC1_HWA_DisableCpu1SWInterrupt(void) +{ + CSC1->CPU1_INT &= ~(uint32_t)CSC1_CPU1_INT_SW_INT_MASK; +} +#endif /* CSC1_INSTANCE_COUNT > 0U */ + +#if CSC2_INSTANCE_COUNT > 0U +/****** Operation on CSC2_xxxRegister0 ******/ +/** @brief Set stop mode register 0 + * + */ +LOCAL_INLINE void CSC2_HWA_Set_STOP_MODER0(uint32_t u32val) +{ + CSC2->STOP_MODER0 = u32val; +} + +/** + * @brief Get stop mode register 0 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC2_HWA_Get_STOP_MODER0(void) +{ + return CSC2->STOP_MODER0; +} + +/** + * @brief Set stop request register 0 + * + */ +LOCAL_INLINE void CSC2_HWA_Set_STOP_REQR0(uint32_t u32val) +{ + CSC2->STOP_REQR0 = u32val; +} + +/** + * @brief Get stop request register 0 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC2_HWA_Get_STOP_REQR0(void) +{ + return CSC2->STOP_REQR0; +} + +/** + * @brief Get stop ack status in register 0 + * + * @return Register ack status + */ +LOCAL_INLINE uint32_t CSC2_HWA_Get_STOP_ACKR0(void) +{ + return CSC2->STOP_ACKR0; +} + +/****** Operation on CSC2_xxxRegister1 ******/ +/** + * @brief Set stop mode register 1 + * + */ +LOCAL_INLINE void CSC2_HWA_Set_STOP_MODER1(uint32_t u32val) +{ + CSC2->STOP_MODER1 = u32val; +} + +/** + * @brief Get stop mode register 1 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC2_HWA_Get_STOP_MODER1(void) +{ + return CSC2->STOP_MODER1; +} + +/** + * @brief Set stop request register 1 + * + */ +LOCAL_INLINE void CSC2_HWA_Set_STOP_REQR1(uint32_t u32val) +{ + CSC2->STOP_REQR1 = u32val; +} + +/** + * @brief Get stop request register 1 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC2_HWA_Get_STOP_REQR1(void) +{ + return CSC2->STOP_REQR1; +} + +/** + * @brief Get stop ack status in register 1 + * + * @return Register ack status + */ +LOCAL_INLINE uint32_t CSC2_HWA_Get_STOP_ACKR1(void) +{ + return CSC2->STOP_ACKR1; +} + +/****** Operation on CSC2_xxxRegister2 ******/ +/** + * @brief Set stop mode register 2 + * + */ +LOCAL_INLINE void CSC2_HWA_Set_STOP_MODER2(uint32_t u32val) +{ + CSC2->STOP_MODER2 = u32val; +} + +/** + * @brief Get stop mode register 2 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC2_HWA_Get_STOP_MODER2(void) +{ + return CSC2->STOP_MODER2; +} + +/** + * @brief Set stop request register 2 + * + */ +LOCAL_INLINE void CSC2_HWA_Set_STOP_REQR2(uint32_t u32val) +{ + CSC2->STOP_REQR2 = u32val; +} + +/** + * @brief Get stop request register 2 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC2_HWA_Get_STOP_REQR2(void) +{ + return CSC2->STOP_REQR2; +} + +/** + * @brief Get stop ack status in register 2 + * + * @return Register ack status + */ +LOCAL_INLINE uint32_t CSC2_HWA_Get_STOP_ACKR2(void) +{ + return CSC2->STOP_ACKR2; +} + +/** + * @brief Set CCM0 configure register + * + */ +LOCAL_INLINE void CSC2_HWA_Set_CCM2_CFG(uint32_t u32val) +{ + CSC2->CCM2_CFG = u32val; +} + +/** + * @brief Get CCM0 configure + * @return Register status + */ +LOCAL_INLINE uint32_t CSC2_HWA_Get_CCM2_CFG(void) +{ + return CSC2->CCM2_CFG; +} + +/** + * @brief Set cpu0 software interrupt register + * + */ +LOCAL_INLINE void CSC2_HWA_Set_CPU2_INT(uint32_t u32val) +{ + CSC2->CPU2_INT = u32val; +} + +/** + * @brief Get cpu0 software interrupt register + * @return Register status + */ +LOCAL_INLINE uint32_t CSC2_HWA_Get_CPU2_INT(void) +{ + return CSC2->CPU2_INT; +} + +/** + * @brief Enable cpu0 software interrupt + * + */ +LOCAL_INLINE void CSC2_HWA_EnableCpu2SWInterrupt(void) +{ + CSC2->CPU2_INT |= (uint32_t)CSC2_CPU2_INT_SW_INT_MASK; +} + +/** + * @brief Disable cpu0 software interrupt + * + */ +LOCAL_INLINE void CSC2_HWA_DisableCpu2SWInterrupt(void) +{ + CSC2->CPU2_INT &= ~(uint32_t)CSC2_CPU2_INT_SW_INT_MASK; +} +#endif /* CSC2_INSTANCE_COUNT > 0U */ + +/** @}*/ +#if CSC3_INSTANCE_COUNT > 0U +/****** Operation on CSC3_xxxRegister0 ******/ +/** + * @brief Set stop mode register 0 + * + */ +LOCAL_INLINE void CSC3_HWA_Set_STOP_MODER0(uint32_t u32val) +{ + CSC3->STOP_MODER0 = u32val; +} + +/** + * @brief Get stop mode register 0 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC3_HWA_Get_STOP_MODER0(void) +{ + return CSC2->STOP_MODER0; +} + +/** + * @brief Set stop request register 0 + * + */ +LOCAL_INLINE void CSC3_HWA_Set_STOP_REQR0(uint32_t u32val) +{ + CSC3->STOP_REQR0 = u32val; +} + +/** + * @brief Get stop request register 0 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC3_HWA_Get_STOP_REQR0(void) +{ + return CSC3->STOP_REQR0; +} + +/** + * @brief Get stop ack status in register 0 + * + * @return Register ack status + */ +LOCAL_INLINE uint32_t CSC3_HWA_Get_STOP_ACKR0(void) +{ + return CSC3->STOP_ACKR0; +} + +/** + * @brief Set stop mode register 1 + * + */ +LOCAL_INLINE void CSC3_HWA_Set_STOP_MODER1(uint32_t u32val) +{ + CSC3->STOP_MODER1 = u32val; +} + +/** + * @brief Get stop mode register 1 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC3_HWA_Get_STOP_MODER1(void) +{ + return CSC3->STOP_MODER1; +} + +/** + * @brief Set stop request register 1 + * + */ +LOCAL_INLINE void CSC3_HWA_Set_STOP_REQR1(uint32_t u32val) +{ + CSC3->STOP_REQR1 = u32val; +} + +/** + * @brief Get stop request register 1 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC3_HWA_Get_STOP_REQR1(void) +{ + return CSC3->STOP_REQR1; +} + +/** + * @brief Get stop ack status in register 1 + * + * @return Register ack status + */ +LOCAL_INLINE uint32_t CSC3_HWA_Get_STOP_ACKR1(void) +{ + return CSC3->STOP_ACKR1; +} + +/** + * @brief Set stop mode register 2 + * + */ +LOCAL_INLINE void CSC3_HWA_Set_STOP_MODER2(uint32_t u32val) +{ + CSC3->STOP_MODER2 = u32val; +} + +/** + * @brief Get stop mode register 2 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC3_HWA_Get_STOP_MODER2(void) +{ + return CSC2->STOP_MODER2; +} + +/** + * @brief Set stop request register 2 + * + */ +LOCAL_INLINE void CSC3_HWA_Set_STOP_REQR2(uint32_t u32val) +{ + CSC3->STOP_REQR2 = u32val; +} + +/** + * @brief Get stop request register 2 + * @return Register status + */ +LOCAL_INLINE uint32_t CSC3_HWA_Get_STOP_REQR2(void) +{ + return CSC3->STOP_REQR2; +} + +/** + * @brief Get stop ack status in register 2 + * + * @return Register ack status + */ +LOCAL_INLINE uint32_t CSC3_HWA_Get_STOP_ACKR2(void) +{ + return CSC3->STOP_ACKR2; +} + +/** + * @brief Set CCM3 configure register + * + */ +LOCAL_INLINE void CSC3_HWA_Set_CCM3_CFG(uint32_t u32val) +{ + CSC3->CCM3_CFG = u32val; +} + +/** + * @brief Get CCM3 configure + * @return Register status + */ +LOCAL_INLINE uint32_t CSC3_HWA_Get_CCM3_CFG(void) +{ + return CSC3->CCM3_CFG; +} + +/** + * @brief Set cpu0 software interrupt register + * + */ +LOCAL_INLINE void CSC2_HWA_Set_CPU3_INT(uint32_t u32val) +{ + CSC3->CPU3_INT = u32val; +} + +/** + * @brief Get cpu0 software interrupt register + * @return Register status + */ +LOCAL_INLINE uint32_t CSC2_HWA_Get_CPU3_INT(void) +{ + return CSC3->CPU3_INT; +} + +/** + * @brief Enable cpu0 software interrupt + * + */ +LOCAL_INLINE void CSC2_HWA_EnableCpu3SWInterrupt(void) +{ + CSC3->CPU3_INT |= (uint32_t)CSC3_CPU3_INT_SW_INT_MASK; +} + +/** + * @brief Disable cpu0 software interrupt + * + */ +LOCAL_INLINE void CSC2_HWA_DisableCpu3SWInterrupt(void) +{ + CSC3->CPU3_INT &= ~(uint32_t)CSC3_CPU3_INT_SW_INT_MASK; +} +#endif + + +#endif /*#ifndef _HWA_CSC_H_*/ diff --git a/Inc/HwA_dma.h b/Inc/HwA_dma.h new file mode 100644 index 0000000..708a9f6 --- /dev/null +++ b/Inc/HwA_dma.h @@ -0,0 +1,1605 @@ +/** + * @file HwA_dma.h + * @author flagchip + * @brief Hardware access layer for DMA + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip099 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_DMA_H_ +#define _HWA_DMA_H_ + +#include "device_header.h" + +#if DMA_INSTANCE_COUNT > 0U + +#define DMA_CH_TO_DCHPRI(x) ((x) ^ 3U) + +/** + * @defgroup HwA_dma HwA_dma + * @ingroup module_driver_dma + * @{ + */ + +/** + * @brief DMA running status + * + */ +typedef enum +{ + DMA_RUNNING_STATUS_IDLE = 0x0U, /*!< The DMA engine is idle */ + DMA_RUNNING_STATUS_ACTIVE = 0x1U /*!< The DMA engine is transferring data */ +} DMA_RunningStatusType; + +/** + * @brief DMA channel arbitration algorithm used in the channel arbitration phase + * + */ +typedef enum +{ + DMA_ARBITRATION_ALGORITHM_FIXED_PRIORITY = 0U, /*!< Use the fixed priority for arbitration */ + DMA_ARBITRATION_ALGORITHM_ROUND_ROBIN = 1U /*!< Use the channel number for arbitration, + higher channel number has higher priority */ +} DMA_ArbitrationAlgorithmType; + +/** + * @brief Defines the size of data in one transfer + * + * One transfer can contain multiple block, and one block may contain multiple + * data, this parameter specifies the size of data which the DMA engine will + * access one time in the memory. + * + */ +typedef enum +{ + + DMA_TRANSFER_SIZE_1B = 0x0U, + DMA_TRANSFER_SIZE_2B = 0x1U, + DMA_TRANSFER_SIZE_4B = 0x2U, + DMA_TRANSFER_SIZE_8B = 0x3U, + DMA_TRANSFER_SIZE_32B = 0x5U +} DMA_TransferSizeType; + +#ifdef DMA_CR_ACTIVE_MASK +/** + * @brief Get active status of the DMA instance + * + * @param pDma the base address of the DMA instance + * @return DMA_RUNNING_STATUS_ACTIVE DMA is executing a channel + * @return DMA_RUNNING_STATUS_IDLE DMA is idle + */ +LOCAL_INLINE DMA_RunningStatusType DMA_HWA_GetStatus(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_ACTIVE_MASK) >> DMA_CR_ACTIVE_SHIFT; + return (DMA_RunningStatusType)u32TmpVal; +} +#endif + +/** + * @brief Get whether the DMA instance is cancelling + * + * @param pDma the base address of the DMA instance + * @return true cancel operation is requested and has not been finished + * @return false DMA is under normal operation + */ +LOCAL_INLINE bool DMA_HWA_GetCancelTransferStatus(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_CX_MASK) >> DMA_CR_CX_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Cancel the remaining transfer of the DMA + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_CancelTransfer(DMA_Type *const pDma) +{ + pDma->CR |= DMA_CR_CX_MASK; +} + +/** + * @brief Get whether the DMA instance is cancelling with error + * + * @param pDma the base address of the DMA instance + * @return true cancel operation is requested and has not been finished + * @return false DMA is under normal operation + */ +LOCAL_INLINE bool DMA_HWA_GetErrorCancelTransferStatus(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_ECX_MASK) >> DMA_CR_ECX_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +#ifdef DMA_HAVE_GPR +/** + * @brief Set Channel Group 0 Priority and clear Group 1 Priority + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_SetGPR0PRIClearGPR1PRI(DMA_Type *const pDma) +{ + pDma->CR = (pDma->CR & ~(DMA_CR_GRP1PRI_MASK | DMA_CR_GPR0PRI_MASK)) | DMA_CR_GPR0PRI_MASK; +} + +/** + * @brief Set Channel Group 1 Priority and clear Group 0 Priority + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_SetGPR1PRIClearGPR0PRI(DMA_Type *const pDma) +{ + pDma->CR = (pDma->CR & ~(DMA_CR_GRP1PRI_MASK | DMA_CR_GPR0PRI_MASK)) | DMA_CR_GRP1PRI_MASK; +} +#endif + +/** + * @brief Cancel the remaining transfer of the DMA and generate an error after finished cancelling + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ErrorCancelTransfer(DMA_Type *const pDma) +{ + pDma->CR |= DMA_CR_ECX_MASK; +} + +/** + * @brief Get whether inner loop mapping is enabled + * + * @param pDma the base address of the DMA instance + * @return true inner loop mapping is enabled + * @return false inner loop mapping is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetInnerLoopMappingEnableFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_EILM_MASK) >> DMA_CR_EILM_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable inner loop mapping + * + * @note Only after enabling inner loop mapping, you can apply an offset to the source + * and/or destination address after the inner loop finishes. + * + * @param pDma the base address of the DMA instance + * @param bEnable whether to enable the inner loop mapping + */ +LOCAL_INLINE void DMA_HWA_SetInnerLoopMappingEnableFlag(DMA_Type *const pDma, bool bEnable) +{ + pDma->CR = (pDma->CR & ~DMA_CR_EILM_MASK) | DMA_CR_EILM(bEnable); +} + +/** + * @brief Get whether the continuous trig mode is enabled + * When continuous trig mode is enabled, channel arbitration is not used for a inner loop + * channel trig before being activated again. Upon inner loop completion, the channel + * activates again if that channel has a inner loop channel trig enabled and the trig + * channel is itself. This effectively applies the inner loop offsets and restarts the next + * inner loop. + * + * @param pDma the base address of the DMA instance + * @return true continuous trig mode is enabled + * @return false continuous trig mode is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetContinuousTrigModeEnableFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_CTM_MASK) >> DMA_CR_CTM_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable the continuous trig mode + * + * @param pDma the base address of the DMA instance + * @param bEnable whether to enable the continuous trig mode + */ +LOCAL_INLINE void DMA_HWA_SetContinuousTrigModeEnableFlag(DMA_Type *const pDma, bool bEnable) +{ + pDma->CR = (pDma->CR & ~DMA_CR_CTM_MASK) | DMA_CR_CTM(bEnable); +} + +/** + * @brief Get whether the DMA is halted + * When the DMA is halted, it will ignore all service requests + * @param pDma the base address of the DMA instance + * @return true the DMA is halted + * @return true the DMA is not halted + */ +LOCAL_INLINE bool DMA_HWA_GetHatlStatus(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_HALT_MASK) >> DMA_CR_HALT_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Halt the DMA operations + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_HaltOperations(DMA_Type *const pDma) +{ + pDma->CR |= DMA_CR_HALT_MASK; +} + +/** + * @brief Clear the halt flag of the DMA instance + * After HALT is cleared, the DMA could continue to operate + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearHaltFlag(DMA_Type *const pDma) +{ + pDma->CR &= ~DMA_CR_HALT_MASK; +} + +/** + * @brief Get whether halt on error is enabled on the DMA instance + * + * @param pDma the base address of the DMA instance + * @return true halt on error is enabled, any error will cause HALT flag to be set + * @return false halt on error is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetHaltOnErrorFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_HOE_MASK) >> DMA_CR_HOE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable halt on error on the DMA instance + * + * @note Ff halt on error is enabled, any error will cause HALT flag to be set + * + * @param pDma the base address of the DMA instance + * @param bEnable whether to enable halt on error + */ +LOCAL_INLINE void DMA_HWA_SetHaltOnErrorFlag(DMA_Type *const pDma, bool bEnable) +{ + pDma->CR = (pDma->CR & ~DMA_CR_HOE_MASK) | DMA_CR_HOE(bEnable); +} + +/** + * @brief Get the DMA arbitration algorithm + * + * @param pDma the base address of the DMA instance + * @return DMA_ArbitrationAlgorithmType the DMA arbitration algorithm + */ +LOCAL_INLINE DMA_ArbitrationAlgorithmType DMA_HWA_GetArbitrationAlgorithm(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_ERCA_MASK) >> DMA_CR_ERCA_SHIFT; + return (DMA_ArbitrationAlgorithmType)u32TmpVal; +} + +/** + * @brief Set the DMA arbitration algorithm + * + * @param pDma the base address of the DMA instance + * @param eAlgorithm the DMA arbitration algorithm + */ +LOCAL_INLINE void DMA_HWA_SetArbitrationAlgorithm(DMA_Type *const pDma, DMA_ArbitrationAlgorithmType eAlgorithm) +{ + pDma->CR = (pDma->CR & ~DMA_CR_ERCA_MASK) | DMA_CR_ERCA(eAlgorithm); +} + +/** + * @brief Get whether the DMA is configured to stop under debug mode + * + * @param pDma the base address of the DMA instance + * @return true the DMA is will stop under debug mode + * @return true the DMA is will continue to operate under debug mode + */ +LOCAL_INLINE bool DMA_HWA_GetDebugModeStopFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_DBGS_MASK) >> DMA_CR_DBGS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the control register of the DMA instance + * + * @param pDma the base address of the DMA instance + * @return uint32_t the control register settings + */ +LOCAL_INLINE uint32_t DMA_HWA_GetControlRegister(const DMA_Type *const pDma) +{ + return pDma->CR; +} + +/** + * @brief Set the control register of the DMA instance + * + * @param pDma the base address of the DMA instance + * @param u32Settings the settings of the DMA control register + */ +LOCAL_INLINE void DMA_HWA_SetControlRegister(DMA_Type *const pDma, uint32_t u32Settings) +{ + pDma->CR = u32Settings; +} + +/** + * @brief Set whether to stop DMA under debug mode + * + * @param pDma the base address of the DMA instance + * @param bEnable whether to stop DMA under debug mode + */ +LOCAL_INLINE void DMA_HWA_SetDebugModeStopFlag(DMA_Type *const pDma, bool bEnable) +{ + pDma->CR = (pDma->CR & ~DMA_CR_DBGS_MASK) | DMA_CR_DBGS(bEnable); +} + +/** + * @brief Get the DMA error status + * + * @param pDma the base address of the DMA instance + * @return uint32_t the DMA error status + */ +LOCAL_INLINE uint32_t DMA_HWA_GetErrorStatus(const DMA_Type *const pDma) +{ + return pDma->ES; +} + +/** + * @brief Get whether there is error occured on the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true there is error on the specified channel + * @return false there is no error on the specified channel + */ +LOCAL_INLINE bool DMA_HWA_GetChannelErrorFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pDma->ERR & (1UL << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the channel error status, each bit represents a channel + * + * @param pDma the base address of the DMA instance + * @return uint16_t the channel error status + */ +LOCAL_INLINE uint16_t DMA_HWA_GetAllChannelErrorFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = pDma->ERR; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get whether error interrupt is enabled on the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true error interrupt is enabled on the specified channel + * @return false error interrupt is disabled on the specified channel + */ +LOCAL_INLINE bool DMA_HWA_GetChannelErrorInterruptEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pDma->EEI & (1UL << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel error interrupt enable status + * + * @param pDma the base address of the DMA instance + * @return uint16_t the channel error interrupt enable status + */ +LOCAL_INLINE uint16_t DMA_HWA_GetAllChannelErrorInterruptEnableFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = pDma->EEI; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Enable error interrupt for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_EnableChannelErrorInterrupt(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->SEEI = DMA_SEEI_SEEI(u8Channel); +} + +/** + * @brief Enable error interrupt for all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_EnableAllChannelErrorInterrupt(DMA_Type *const pDma) +{ + pDma->SEEI = DMA_SEEI_SAEE_MASK; +} + +/** + * @brief Disable error interrupt for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_DisableChannelErrorInterrupt(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CEEI = DMA_CEEI_CEEI(u8Channel); +} + +/** + * @brief Disable error interrupt for all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_DisableAllChannelErrorInterrupt(DMA_Type *const pDma) +{ + pDma->CEEI = DMA_CEEI_CAEE_MASK; +} + +/** + * @brief Enable channel request for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_EnableChannelRequest(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->SERQ = DMA_SERQ_SERQ(u8Channel); +} + +/** + * @brief Enable channel request for all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_EnableAllChannelRequest(DMA_Type *const pDma) +{ + pDma->SERQ = DMA_SERQ_SAER_MASK; +} + +/** + * @brief Disable channel request for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_DisableChannelRequest(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CERQ = DMA_CERQ_CERQ(u8Channel); +} + +/** + * @brief Disable channel request for all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_DisableAllChannelRequest(DMA_Type *const pDma) +{ + pDma->CERQ = DMA_CERQ_CAER_MASK; +} + +/** + * @brief Clear DONE bit for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_ClearChannelDoneStatus(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CDNE = DMA_CDNE_CDNE(u8Channel); +} + +/** + * @brief Clear DONE bit for the all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearAllChannelDoneStatus(DMA_Type *const pDma) +{ + pDma->CDNE = DMA_CDNE_CADN_MASK; +} + +/** + * @brief Clear ERR bit for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_ClearChannelErrorFlag(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CERR = DMA_CERR_CERR(u8Channel); +} + +/** + * @brief Clear ERR bit for the all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearAllChannelErrorFlag(DMA_Type *const pDma) +{ + pDma->CERR = DMA_CERR_CAEI_MASK; +} + +/** + * @brief Clear interrupt flag for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_ClearChannelInterruptFlag(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CINT = DMA_CINT_CINT(u8Channel); +} + +/** + * @brief Clear interrupt flag for the all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearAllChannelInterruptFlag(DMA_Type *const pDma) +{ + pDma->CINT = DMA_CINT_CAIR_MASK; +} + +/** + * @brief Set start for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_SetChannelStart(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->SSRT = DMA_SSRT_SSRT(u8Channel); +} + +/** + * @brief Set start for the all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_SetAllChannelStart(DMA_Type *const pDma) +{ + pDma->SSRT = DMA_SSRT_SAST_MASK; +} + +/** + * @brief Get whether source unalign modulo is enabled for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE bool DMA_HWA_GetSrcUnalignModuloEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ +#if (DMA_UME_COUNT == 2U) + uint32_t u32TmpVal = (pDma->UME[u8Channel/16U] & ((uint32_t)DMA_UME_SUME0_MASK << (2U * (u8Channel % 16U)))) >> + (DMA_UME_SUME0_SHIFT + 2U * (u8Channel % 16U)); +#elif (DMA_UME_COUNT == 1U) + uint32_t u32TmpVal = (pDma->UME[u8Channel/16U] & ((uint32_t)DMA_UME_SUME0_MASK << (2U * (u8Channel % 16U)))) >> + (DMA_UME_SUME0_SHIFT + 2U * (u8Channel % 16U)); +#endif + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether destination unalign modulo is enabled for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE bool DMA_HWA_GetDestUnalignModuloEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ +#if (DMA_UME_COUNT == 2U) + uint32_t u32TmpVal = (pDma->UME[u8Channel/16U] & ((uint32_t)DMA_UME_DUME0_MASK << (2U * (u8Channel % 16U)))) >> + (DMA_UME_DUME0_SHIFT + 2U * (u8Channel % 16U)); +#elif (DMA_UME_COUNT == 1U) + uint32_t u32TmpVal = (pDma->UME[u8Channel/16U] & ((uint32_t)DMA_UME_DUME0_MASK << (2U * (u8Channel % 16U)))) >> + (DMA_UME_DUME0_SHIFT + 2U * (u8Channel % 16U)); +#endif + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether to enable unalign modulo for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnableSrcModulo whether source unalign modulo is to be enabled + * @param bEnableDestModulo whether destination unalign modulo is to be enabled + */ +LOCAL_INLINE void DMA_HWA_SetUnalignModuloEnableFlag(DMA_Type *const pDma, uint8_t u8Channel, + bool bEnableSrcModulo, bool bEnableDestModulo) +{ +#if (DMA_UME_COUNT == 2U) + pDma->UME[u8Channel/16U] = (pDma->UME[u8Channel/16U] & ~((DMA_UME_DUME0_MASK | DMA_UME_SUME0_MASK) << (2U * (u8Channel % 16U)))) | + ((DMA_UME_DUME0(bEnableDestModulo) | DMA_UME_SUME0(bEnableSrcModulo)) << (2U * (u8Channel % 16U))); +#elif (DMA_UME_COUNT == 1U) + pDma->UME[u8Channel / 16U] = (pDma->UME[u8Channel / 16U] & ~((uint32_t)(DMA_UME_DUME0_MASK | DMA_UME_SUME0_MASK) << (2U * (u8Channel % 16U)))) | + ((DMA_UME_DUME0(bEnableDestModulo) | DMA_UME_SUME0(bEnableSrcModulo)) << (2U * (u8Channel % 16U))); +#endif +} + +/** + * @brief Get the source unalign modulo of the index + * + * @param pDma the base address of the DMA instance + * @param u8Selection the index of the unalign modulo + * @return uint16_t the source unalign modulo + */ +LOCAL_INLINE uint16_t DMA_HWA_GetSrcUnalignModulo(const DMA_Type *const pDma, uint8_t u8Selection) +{ +#if (DMA_UME_COUNT == 2U) + uint32_t u32TmpVal = (pDma->UMO[u8Selection] & DMA_UMO_SUMO_MASK) >> DMA_UMO_SUMO_SHIFT; +#elif (DMA_UME_COUNT == 1U) + uint32_t u32TmpVal = (pDma->UMO[u8Selection] & DMA_UMO_SUMO_MASK) >> DMA_UMO_SUMO_SHIFT; +#endif + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get the destination unalign modulo of the index + * + * @param pDma the base address of the DMA instance + * @param u8Selection the index of the unalign modulo + * @return uint16_t the destination unalign modulo + */ +LOCAL_INLINE uint16_t DMA_HWA_GetDestUnalignModulo(const DMA_Type *const pDma, uint8_t u8Selection) +{ +#if (DMA_UME_COUNT == 2U) + uint32_t u32TmpVal = (pDma->UMO[u8Selection] & DMA_UMO_DUMO_MASK) >> DMA_UMO_DUMO_SHIFT; +#elif (DMA_UME_COUNT == 1U) + uint32_t u32TmpVal = (pDma->UMO[u8Selection] & DMA_UMO_DUMO_MASK) >> DMA_UMO_DUMO_SHIFT; +#endif + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set unalign modulo of the index + * + * @param pDma the base address of the DMA instance + * @param u8Selection the index of the unalign modulo + * @param u16SrcModulo the source unalign modulo + * @param u16DestModulo the destination unalign modulo + */ +LOCAL_INLINE void DMA_HWA_SetUnalignModulo(DMA_Type *const pDma, uint8_t u8Selection, + uint16_t u16SrcModulo, uint16_t u16DestModulo) +{ +#if (DMA_UME_COUNT == 2U) + pDma->UMO[u8Selection] = DMA_UMO_SUMO(u16SrcModulo) | DMA_UMO_DUMO(u16DestModulo); +#elif (DMA_UME_COUNT == 1U) + pDma->UMO[u8Selection] = DMA_UMO_SUMO(u16SrcModulo) | DMA_UMO_DUMO(u16DestModulo); +#endif +} + +/** + * @brief Get priority of the channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the priority of the channel + */ +LOCAL_INLINE uint8_t DMA_HWA_GetPriority(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint8_t u8TmpVal = pDma->CHPRI[DMA_CH_TO_DCHPRI(u8Channel)]; + return u8TmpVal; +} + +/** + * @brief Set priority of the channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8Priority the priority of the channel + */ +LOCAL_INLINE void DMA_HWA_SetPriority(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8Priority) +{ + pDma->CHPRI[DMA_CH_TO_DCHPRI(u8Channel)] = u8Priority; +} + +/** + * @brief Get the source address of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint32_t the source address of the DMA channel + */ +LOCAL_INLINE uint32_t DMA_HWA_GetSrcAddr(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return pDma->CFG[u8Channel].SADDR; +} + +/** + * @brief Set the source address of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u32SrcAddr the source address of the DMA channel + */ +LOCAL_INLINE void DMA_HWA_SetSrcAddr(DMA_Type *const pDma, uint8_t u8Channel, uint32_t u32SrcAddr) +{ + pDma->CFG[u8Channel].SADDR = u32SrcAddr; +} + +/** + * @brief Get the destination address of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint32_t the destination address of the DMA channel + */ +LOCAL_INLINE uint32_t DMA_HWA_GetDestAddr(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return pDma->CFG[u8Channel].DADDR; +} + +/** + * @brief Set the destination address of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u32DestAddr the destination address of the DMA channel + */ +LOCAL_INLINE void DMA_HWA_SetDestAddr(DMA_Type *const pDma, uint8_t u8Channel, uint32_t u32DestAddr) +{ + pDma->CFG[u8Channel].DADDR = u32DestAddr; +} + +/** + * @brief Get source data offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int16_t the source data offset + */ +LOCAL_INLINE int16_t DMA_HWA_GetSrcOffset(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return (int16_t)pDma->CFG[u8Channel].SOFF; +} + +/** + * @brief Set source data offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param s16Offset the source data offset + */ +LOCAL_INLINE void DMA_HWA_SetSrcOffset(DMA_Type *const pDma, uint8_t u8Channel, int16_t s16Offset) +{ + pDma->CFG[u8Channel].SOFF = (uint16_t)s16Offset; +} + +/** + * @brief Get destination data offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int16_t the destination data offset + */ +LOCAL_INLINE int16_t DMA_HWA_GetDestOffset(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return (int16_t)pDma->CFG[u8Channel].DOFF; +} + +/** + * @brief Set destination data offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param s16Offset the destination data offset + */ +LOCAL_INLINE void DMA_HWA_SetDestOffset(DMA_Type *const pDma, uint8_t u8Channel, int16_t s16Offset) +{ + pDma->CFG[u8Channel].DOFF = (uint16_t)s16Offset; +} + +/** + * @brief Get the source data size of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return DMA_TransferSizeType the source data size of the DMA channel + */ +LOCAL_INLINE DMA_TransferSizeType DMA_HWA_GetSrcDataSize(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].ATTR & DMA_CFG_ATTR_SSIZE_MASK) >> DMA_CFG_ATTR_SSIZE_SHIFT; + return (DMA_TransferSizeType)u16TmpVal; +} + +/** + * @brief Set the source data size of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param eDataSize the source data size of the DMA channel + */ +LOCAL_INLINE void DMA_HWA_SetSrcDataSize(DMA_Type *const pDma, uint8_t u8Channel, DMA_TransferSizeType eDataSize) +{ + pDma->CFG[u8Channel].ATTR = (uint16_t)((pDma->CFG[u8Channel].ATTR & ~DMA_CFG_ATTR_SSIZE_MASK) | DMA_CFG_ATTR_SSIZE(eDataSize)); +} + +/** + * @brief Get the destination data size of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return DMA_TransferSizeType the destination data size of the DMA channel + */ +LOCAL_INLINE DMA_TransferSizeType DMA_HWA_GetDestDataSize(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].ATTR & DMA_CFG_ATTR_DSIZE_MASK) >> DMA_CFG_ATTR_DSIZE_SHIFT; + return (DMA_TransferSizeType)u16TmpVal; +} + +/** + * @brief Set the destination data size of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param eDataSize the destination data size of the DMA channel + */ +LOCAL_INLINE void DMA_HWA_SetDestDataSize(DMA_Type *const pDma, uint8_t u8Channel, DMA_TransferSizeType eDataSize) +{ + pDma->CFG[u8Channel].ATTR = (uint16_t)((pDma->CFG[u8Channel].ATTR & ~DMA_CFG_ATTR_DSIZE_MASK) | DMA_CFG_ATTR_DSIZE(eDataSize)); +} + +/** + * @brief Get the source address aligned modulo of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the source address aligned modulo + */ +LOCAL_INLINE uint8_t DMA_HWA_GetSrcModulo(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].ATTR & DMA_CFG_ATTR_SMOD_MASK) >> DMA_CFG_ATTR_SMOD_SHIFT; + return (uint8_t)u16TmpVal; +} + +/** + * @brief Set the source address aligned modulo of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8SrcModulo the source address aligned modulo + */ +LOCAL_INLINE void DMA_HWA_SetSrcModulo(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8SrcModulo) +{ + pDma->CFG[u8Channel].ATTR = (uint16_t)((pDma->CFG[u8Channel].ATTR & ~DMA_CFG_ATTR_SMOD_MASK) | DMA_CFG_ATTR_SMOD(u8SrcModulo)); +} + +/** + * @brief Get the destination address aligned modulo of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the destination address aligned modulo + */ +LOCAL_INLINE uint8_t DMA_HWA_GetDestModulo(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].ATTR & DMA_CFG_ATTR_DMOD_MASK) >> DMA_CFG_ATTR_DMOD_SHIFT; + return (uint8_t)u16TmpVal; +} + +/** + * @brief Set the destination address aligned modulo of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8DestModulo the destination address aligned modulo + */ +LOCAL_INLINE void DMA_HWA_SetDestModulo(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8DestModulo) +{ + pDma->CFG[u8Channel].ATTR = (uint16_t)((pDma->CFG[u8Channel].ATTR & ~DMA_CFG_ATTR_DMOD_MASK) | DMA_CFG_ATTR_DMOD(u8DestModulo)); +} + +/** + * @brief Get the address adjustment applied to the source address after major loop finished + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int32_t the address adjustment applied to the source address after major loop finished + */ +LOCAL_INLINE int32_t DMA_HWA_GetSrcLastAddrAdjustment(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return (int32_t)pDma->CFG[u8Channel].SLAST; +} + +/** + * @brief Set the address adjustment applied to the source address after major loop finished + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param s32LastAdj the address adjustment applied to the source address after major loop finished + */ +LOCAL_INLINE void DMA_HWA_SetSrcLastAddrAdjustment(DMA_Type *const pDma, uint8_t u8Channel, int32_t s32LastAdj) +{ + pDma->CFG[u8Channel].SLAST = (uint32_t)s32LastAdj; +} + +/** + * @brief Get the address adjustment applied to the destination address after major loop finished + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int32_t the address adjustment applied to the destination address after major loop finished + */ +LOCAL_INLINE int32_t DMA_HWA_GetDestLastAddrAdjustment(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return (int32_t)pDma->CFG[u8Channel].DLAST; +} + +/** + * @brief Set the address adjustment applied to the destination address after major loop finished + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param s32LastAdj the address adjustment applied to the destination address after major loop finished + */ +LOCAL_INLINE void DMA_HWA_SetDestLastAddrAdjustment(DMA_Type *const pDma, uint8_t u8Channel, int32_t s32LastAdj) +{ + pDma->CFG[u8Channel].DLAST = (uint32_t)s32LastAdj; +} + +/** + * @brief Get whether source address inner loop offset is enabled + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true source address inner loop offset is enabled + * @return false source address inner loop offset is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + u32TmpVal = 0U; + } + else + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFNO & DMA_CFG_NBYTES_ILOFFNO_SILOE_MASK) >> + DMA_CFG_NBYTES_ILOFFNO_SILOE_SHIFT; + } + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether destination address inner loop offset is enabled + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true destination address inner loop offset is enabled + * @return false destination address inner loop offset is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetInnerLoopDestOffsetEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + u32TmpVal = 0U; + } + else + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFNO & DMA_CFG_NBYTES_ILOFFNO_DILOE_MASK) >> + DMA_CFG_NBYTES_ILOFFNO_DILOE_SHIFT; + } + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the inner loop offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int32_t the signed inner loop offset + */ +LOCAL_INLINE int32_t DMA_HWA_GetInnerLoopOffset(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + u32TmpVal = 0U; + } + else + { + bool bDmaInnerLoopSrcOffsetEnable = DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(pDma, u8Channel); + bool bDmaInnerLoopDestOffsetEnable = DMA_HWA_GetInnerLoopDestOffsetEnableFlag(pDma, u8Channel); + if ((bDmaInnerLoopSrcOffsetEnable == false) && (bDmaInnerLoopDestOffsetEnable == false)) + { + u32TmpVal = 0U; + } + else + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFYES & DMA_CFG_NBYTES_ILOFFYES_ILOFF_MASK) >> + DMA_CFG_NBYTES_ILOFFYES_ILOFF_SHIFT; + } + } + /* Convert sign-extended 20bit value to signed 32bit value */ + if ((u32TmpVal & (1U << 19U)) != 0U) + { + u32TmpVal |= 0xFFF00000U; + } + return (int32_t)u32TmpVal; +} + +/** + * @brief Get the transfer data size of the inner loop + * @note if inner loop mapping is disabled, the range is 0~2^31-1 + * if inner loop mapping is enabled and inner loop offset is disabled, the range is 0~2^30-1 + * if inner loop mapping is enabled and inner loop offset is enabled, the range is 0~2^10-1 + * 0 means 2^32 + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint32_t the transfer data size of the inner loop + */ +LOCAL_INLINE uint32_t DMA_HWA_GetInnerLoopSize(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + u32TmpVal = pDma->CFG[u8Channel].NBYTES.ILNO; + } + else + { + bool bDmaInnerLoopSrcOffsetEnable = DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(pDma, u8Channel); + bool bDmaInnerLoopDestOffsetEnable = DMA_HWA_GetInnerLoopDestOffsetEnableFlag(pDma, u8Channel); + if ((bDmaInnerLoopSrcOffsetEnable == false) && (bDmaInnerLoopDestOffsetEnable == false)) + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFNO & DMA_CFG_NBYTES_ILOFFNO_NBYTES_MASK) >> + DMA_CFG_NBYTES_ILOFFNO_NBYTES_SHIFT; + } + else + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFYES & DMA_CFG_NBYTES_ILOFFYES_NBYTES_MASK) >> + DMA_CFG_NBYTES_ILOFFYES_NBYTES_SHIFT; + } + } + return u32TmpVal; +} + +/** + * @brief Set the inner loop offset of the DMA channel + * + * @note the inner loop offset can only be enabled when inner loop mapping is enabled + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnableSrcOffset whether to enable source address inner loop offset + * @param bEnableDestOffset whether to enable destination address inner loop offset + * @param s32Offset the inner loop offset + */ +LOCAL_INLINE void DMA_HWA_SetInnerLoopOffset(DMA_Type *const pDma, uint8_t u8Channel, bool bEnableSrcOffset, + bool bEnableDestOffset, int32_t s32Offset) +{ + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + //ignore the action + } + else + { + if ((bEnableSrcOffset == false) && (bEnableDestOffset == false)) + { + bool bDmaInnerLoopSrcOffsetEnable = DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(pDma, u8Channel); + bool bDmaInnerLoopDestOffsetEnable = DMA_HWA_GetInnerLoopDestOffsetEnableFlag(pDma, u8Channel); + /* If inner loop offset is enabled, to disable inner loop offset, we should clear the inner + loop offset enable bit and meanwhile the inner loop offset bits */ + if ((bDmaInnerLoopSrcOffsetEnable == true) || (bDmaInnerLoopDestOffsetEnable == true)) + { + pDma->CFG[u8Channel].NBYTES.ILOFFNO &= ~(DMA_CFG_NBYTES_ILOFFNO_SILOE_MASK | DMA_CFG_NBYTES_ILOFFNO_DILOE_MASK | + DMA_CFG_NBYTES_ILOFFYES_ILOFF_MASK); + } + } + else + { + pDma->CFG[u8Channel].NBYTES.ILOFFYES = (pDma->CFG[u8Channel].NBYTES.ILOFFYES & ~(DMA_CFG_NBYTES_ILOFFYES_SILOE_MASK | + DMA_CFG_NBYTES_ILOFFYES_DILOE_MASK | DMA_CFG_NBYTES_ILOFFYES_ILOFF_MASK)) | + DMA_CFG_NBYTES_ILOFFYES_SILOE(bEnableSrcOffset) | + DMA_CFG_NBYTES_ILOFFYES_DILOE(bEnableDestOffset) | + DMA_CFG_NBYTES_ILOFFYES_ILOFF(s32Offset); + } + } +} + +/** + * @brief Set the transfer data size of the inner loop + * @note if inner loop mapping is disabled, the range is 0~2^31-1 + * if inner loop mapping is enabled and inner loop offset is disabled, the range is 0~2^30-1 + * if inner loop mapping is enabled and inner loop offset is enabled, the range is 0~2^10-1 + * 0 means 2^32 + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u32Size the transfer data size of the inner loop + */ +LOCAL_INLINE void DMA_HWA_SetInnerLoopSize(DMA_Type *const pDma, uint8_t u8Channel, uint32_t u32Size) +{ + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + pDma->CFG[u8Channel].NBYTES.ILNO = DMA_CFG_NBYTES_ILNO_NBYTES(u32Size); + } + else + { + bool bDmaInnerLoopSrcOffsetEnable = DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(pDma, u8Channel); + bool bDmaInnerLoopDestOffsetEnable = DMA_HWA_GetInnerLoopDestOffsetEnableFlag(pDma, u8Channel); + if ((bDmaInnerLoopSrcOffsetEnable == false) && (bDmaInnerLoopDestOffsetEnable == false)) + { + pDma->CFG[u8Channel].NBYTES.ILOFFNO = (pDma->CFG[u8Channel].NBYTES.ILOFFNO & ~DMA_CFG_NBYTES_ILOFFNO_NBYTES_MASK) | + DMA_CFG_NBYTES_ILOFFNO_NBYTES(u32Size); + } + else + { + pDma->CFG[u8Channel].NBYTES.ILOFFYES = (pDma->CFG[u8Channel].NBYTES.ILOFFYES & ~DMA_CFG_NBYTES_ILOFFYES_NBYTES_MASK) | + DMA_CFG_NBYTES_ILOFFYES_NBYTES(u32Size); + } + } +} + +/** + * @brief Get whether current channel to channel trig is enabled when inner loop complete + * @note this field shall always be same with the beginning channel to channel trig enable flag + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true channel to channel trig is enabled when inner loop complete + * @return false channel to channel trig is disabled when inner loop complete + */ +LOCAL_INLINE bool DMA_HWA_GetCurrentChannelToChannelTrigEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CLC.CHTRGENNO & DMA_CFG_CLC_CHTRGENNO_CHTRGEN_MASK) >> + DMA_CFG_CLC_CHTRGENNO_CHTRGEN_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the target channel when current channel to channel trig is enabled + * @note this field shall always be same with the beginning traget channel trig field + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the target channel + */ +LOCAL_INLINE uint8_t DMA_HWA_GetCurrentChannelToChannelTrigChannel(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal; + if (DMA_HWA_GetCurrentChannelToChannelTrigEnableFlag(pDma, u8Channel) == true) + { + u16TmpVal = (pDma->CFG[u8Channel].CLC.CHTRGENYES & DMA_CFG_CLC_CHTRGENYES_TRGCH_MASK) >> + DMA_CFG_CLC_CHTRGENYES_TRGCH_SHIFT; + } + else + { + u16TmpVal = 0U; + } + return (uint8_t)u16TmpVal; +} + +/** + * @brief Get the current loop count + * The current loop count is the same as the beginning loop count initially, and it will decrement + * each time a inner loop finishes + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint16_t the current loop count + */ +LOCAL_INLINE uint16_t DMA_HWA_GetCurrentLoopCount(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal; + if (DMA_HWA_GetCurrentChannelToChannelTrigEnableFlag(pDma, u8Channel) == false) + { + u16TmpVal = (pDma->CFG[u8Channel].CLC.CHTRGENNO & DMA_CFG_CLC_CHTRGENNO_CLC_MASK) >> DMA_CFG_CLC_CHTRGENNO_CLC_SHIFT; + } + else + { + u16TmpVal = (pDma->CFG[u8Channel].CLC.CHTRGENYES & DMA_CFG_CLC_CHTRGENYES_CLC_MASK) >> DMA_CFG_CLC_CHTRGENYES_CLC_SHIFT; + } + return u16TmpVal; +} + +/** + * @brief Get whether beginning channel to channel trig is enabled when inner loop complete + * @note this field shall always be same with the current channel to channel trig enable flag + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true channel to channel trig is enabled when inner loop complete + * @return false channel to channel trig is disabled when inner loop complete + */ +LOCAL_INLINE bool DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].BLC.CHTRGENNO & DMA_CFG_BLC_CHTRGENNO_CHTRGEN_MASK) >> + DMA_CFG_BLC_CHTRGENNO_CHTRGEN_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the target channel when beginning channel to channel trig is enabled + * @note this field shall always be same with the current traget channel trig field + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the target channel + */ +LOCAL_INLINE uint8_t DMA_HWA_GetBeginningChannelToChannelTrigChannel(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal; + if (DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(pDma, u8Channel) == true) + { + u16TmpVal = (pDma->CFG[u8Channel].BLC.CHTRGENYES & DMA_CFG_BLC_CHTRGENYES_TRGCH_MASK) >> + DMA_CFG_BLC_CHTRGENYES_TRGCH_SHIFT; + } + else + { + u16TmpVal = 0U; + } + return (uint8_t)u16TmpVal; +} + +/** + * @brief Get the beginning loop count + * This field specifies how many inner loops will be executed in a DMA transfer + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint16_t the beginning loop count + */ +LOCAL_INLINE uint16_t DMA_HWA_GetBeginningLoopCount(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal; + if (DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(pDma, u8Channel) == false) + { + u16TmpVal = (pDma->CFG[u8Channel].BLC.CHTRGENNO & DMA_CFG_BLC_CHTRGENNO_BLC_MASK) >> DMA_CFG_BLC_CHTRGENNO_BLC_SHIFT; + } + else + { + u16TmpVal = (pDma->CFG[u8Channel].BLC.CHTRGENYES & DMA_CFG_BLC_CHTRGENYES_BLC_MASK) >> DMA_CFG_BLC_CHTRGENYES_BLC_SHIFT; + } + return u16TmpVal; +} + +/** + * @brief Set channel to channel trig when inner loop complete + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnable whether to enbable channel to channel trig when inner loop complete + * @param u8TrigChannel the target channel + */ +LOCAL_INLINE void DMA_HWA_SetChannelToChannelTrig(DMA_Type *const pDma, uint8_t u8Channel, bool bEnable, + uint8_t u8TrigChannel) +{ + if (bEnable == false) + { + if (DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(pDma, u8Channel) == true) + { + pDma->CFG[u8Channel].BLC.CHTRGENNO &= (uint16_t)~(DMA_CFG_BLC_CHTRGENNO_CHTRGEN_MASK); + pDma->CFG[u8Channel].CLC.CHTRGENNO &= (uint16_t)~(DMA_CFG_CLC_CHTRGENNO_CHTRGEN_MASK); + } + } + else + { + pDma->CFG[u8Channel].BLC.CHTRGENYES = (uint16_t)((pDma->CFG[u8Channel].BLC.CHTRGENYES & + ~(DMA_CFG_BLC_CHTRGENYES_CHTRGEN_MASK | DMA_CFG_BLC_CHTRGENYES_TRGCH_MASK)) | + DMA_CFG_BLC_CHTRGENYES_CHTRGEN(bEnable) | DMA_CFG_BLC_CHTRGENYES_TRGCH(u8TrigChannel)); + pDma->CFG[u8Channel].CLC.CHTRGENYES = (uint16_t)((pDma->CFG[u8Channel].CLC.CHTRGENYES & + ~(DMA_CFG_CLC_CHTRGENYES_CHTRGEN_MASK | DMA_CFG_CLC_CHTRGENYES_TRGCH_MASK)) | + DMA_CFG_CLC_CHTRGENYES_CHTRGEN(bEnable) | DMA_CFG_CLC_CHTRGENYES_TRGCH(u8TrigChannel)); + } +} + +/** + * @brief Set the loop count of the DMA transfer + * This field specifies how many inner loops will be executed in a DMA transfer + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u16LoopCnt the inner loop count in a DMA transfer + */ +LOCAL_INLINE void DMA_HWA_SetLoopCount(DMA_Type *const pDma, uint8_t u8Channel, uint16_t u16LoopCnt) +{ + if (DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(pDma, u8Channel) == false) + { + pDma->CFG[u8Channel].BLC.CHTRGENNO = (uint16_t)((pDma->CFG[u8Channel].BLC.CHTRGENNO & ~DMA_CFG_BLC_CHTRGENNO_BLC_MASK) | + DMA_CFG_BLC_CHTRGENNO_BLC(u16LoopCnt)); + pDma->CFG[u8Channel].CLC.CHTRGENNO = (uint16_t)((pDma->CFG[u8Channel].CLC.CHTRGENNO & ~DMA_CFG_CLC_CHTRGENNO_CLC_MASK) | + DMA_CFG_CLC_CHTRGENNO_CLC(u16LoopCnt)); + } + else + { + pDma->CFG[u8Channel].BLC.CHTRGENYES = (uint16_t)((pDma->CFG[u8Channel].BLC.CHTRGENYES & ~DMA_CFG_BLC_CHTRGENYES_BLC_MASK) | + DMA_CFG_BLC_CHTRGENYES_BLC(u16LoopCnt)); + pDma->CFG[u8Channel].CLC.CHTRGENYES = (uint16_t)((pDma->CFG[u8Channel].CLC.CHTRGENYES & ~DMA_CFG_CLC_CHTRGENYES_CLC_MASK) | + DMA_CFG_CLC_CHTRGENYES_CLC(u16LoopCnt)); + } +} + +/** + * @brief Get the unalign modulo index selection + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the unalign modulo index selection + */ +LOCAL_INLINE uint8_t DMA_HWA_GetUnalignModuloSel(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_UMS_MASK) >> DMA_CFG_CSR_UMS_SHIFT; + return (uint8_t)u16TmpVal; +} + +/** + * @brief Set the unalign modulo index selection + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8UnalignModuloSel the unalign modulo index selection + */ +LOCAL_INLINE void DMA_HWA_SetUnalignModuloSel(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8UnalignModuloSel) +{ + pDma->CFG[u8Channel].CSR = (uint16_t)((pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_UMS_MASK) | DMA_CFG_CSR_UMS(u8UnalignModuloSel)); +} + +/** + * @brief Get the target channel to trig when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the target channel + */ +LOCAL_INLINE uint8_t DMA_HWA_GetOuterLoopTrigChannel(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_OTRGCH_MASK) >> DMA_CFG_CSR_OTRGCH_SHIFT; + return (uint8_t)u16TmpVal; +} + +/** + * @brief Set the target channel to trig when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8TrigChannel the target channel + */ +LOCAL_INLINE void DMA_HWA_SetOuterLoopTrigChannel(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8TrigChannel) +{ + pDma->CFG[u8Channel].CSR = (uint16_t)((pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_OTRGCH_MASK) | DMA_CFG_CSR_OTRGCH(u8TrigChannel)); +} + +/** + * @brief Get whether the transfer is done on the selected channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true the transfer is done + * @return false the transfer has not done + */ +LOCAL_INLINE bool DMA_HWA_GetChannelDoneStatus(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_DONE_MASK) >> DMA_CFG_CSR_DONE_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the active status of the DMA channel + * This flag signals the channel is currently in execution. It is set when channel service begins, + * and is cleared by the DMA as the inner loop completes or when any error condition is detected + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true the channel is in execution + * @return false the channel is idle + */ +LOCAL_INLINE DMA_RunningStatusType DMA_HWA_GetChannelActiveStatus(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_ACTIVE_MASK) >> DMA_CFG_CSR_ACTIVE_SHIFT; + return (DMA_RunningStatusType)u16TmpVal; +} + +/** + * @brief Get channel to channel trig is enabled when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true the target channel will be trigged when outer loop is completed + * @return false the channel to channel trig when outer loop is completed is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetOuterLoopTrigEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_OCHTRGEN_MASK) >> DMA_CFG_CSR_OCHTRGEN_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable channel to channel trig when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnable whether to enable channel to channel trig when outer loop is completed + */ +LOCAL_INLINE void DMA_HWA_SetOuterLoopTrigEnableFlag(DMA_Type *const pDma, uint8_t u8Channel, bool bEnable) +{ + pDma->CFG[u8Channel].CSR = (uint16_t)((pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_OCHTRGEN_MASK) | DMA_CFG_CSR_OCHTRGEN(bEnable)); +} + +/** + * @brief Get whether DMA request will be disabled automatically when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true DMA request will be disabled automatically when outer loop is completed + * @return false DMA request will not be cleared when outer loop is completed + */ +LOCAL_INLINE bool DMA_HWA_GetAutoDisableReuqestEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_DREQ_MASK) >> DMA_CFG_CSR_DREQ_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to disable DMA request automatically when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnable whether to disable DMA request automatically when outer loop is completed + */ +LOCAL_INLINE void DMA_HWA_SetAutoDisableReuqestEnableFlag(DMA_Type *const pDma, uint8_t u8Channel, bool bEnable) +{ + pDma->CFG[u8Channel].CSR = (uint16_t)((pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_DREQ_MASK) | DMA_CFG_CSR_DREQ(bEnable)); +} + +/** + * @brief Get whether DMA interrupt wiil be generated when the outer loop is half done + * @note When outer loop count is 1, do not enable half complete interrupt + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true DMA will generate interrupt when outer loop is half done + * @return true DMA will not generate interrupt when outer loop is half done + */ +LOCAL_INLINE bool DMA_HWA_GetHalfCompleteInterruptEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_INTHALF_MASK) >> DMA_CFG_CSR_INTHALF_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable DMA interrupt when the outer loop is half done + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnable whether to enable DMA interrupt when the outer loop is half done + */ +LOCAL_INLINE void DMA_HWA_SetHalfCompleteInterruptEnableFlag(DMA_Type *const pDma, uint8_t u8Channel, bool bEnable) +{ + pDma->CFG[u8Channel].CSR = (uint16_t)((pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_INTHALF_MASK) | DMA_CFG_CSR_INTHALF(bEnable)); +} + +/** + * @brief Get whether DMA interrupt is enabled when DMA transfer is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true DMA will generate interrupt when outer loop is completed + * @return false DMA will not generate interrupt when outer loop is completed + */ +LOCAL_INLINE bool DMA_HWA_GetTransferCompleteInterruptEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_INTOUTER_MASK) >> DMA_CFG_CSR_INTOUTER_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable DMA transfer complete interrupt + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_EnableTransferCompleteInterrupt(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CFG[u8Channel].CSR |= DMA_CFG_CSR_INTOUTER_MASK; +} + +/** + * @brief Disable DMA transfer complete interrupt + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_DisableTransferCompleteInterrupt(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CFG[u8Channel].CSR &= (uint16_t)~DMA_CFG_CSR_INTOUTER_MASK; +} + +/** + * @brief Get whether the DMA start is requested but has not been executed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true the DMA start is requested but has not been executed + * @return false the DMA start is not requested or it has started execution + */ +LOCAL_INLINE bool DMA_HWA_GetWaitStartFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_START_MASK) >> DMA_CFG_CSR_START_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Get DMA channel control and status + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint16_t control and status of the selected channel + */ +LOCAL_INLINE uint16_t DMA_HWA_GetChannelControlStatus(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return pDma->CFG[u8Channel].CSR; +} + +/** + * @brief Set DMA channel control and status + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u16Setting control settings of the selected channel + */ +LOCAL_INLINE void DMA_HWA_SetChannelControlStatus(DMA_Type *const pDma, uint8_t u8Channel, uint16_t u16Setting) +{ + pDma->CFG[u8Channel].CSR = u16Setting; +} + +#ifdef DMA_HAVE_MONCHK +/** + * @brief Enable DMA Monitor Checker + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_EnableMonitorChecker(DMA_Type *const pDma) +{ + pDma->MON_CTRL |= DMA_MON_CTRL_MON_CHK_EN_MASK; +} + +/** + * @brief Disable DMA Monitor Checker + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_DisableMonitorChecker(DMA_Type *const pDma) +{ + pDma->MON_CTRL &= ~DMA_MON_CTRL_MON_CHK_EN_MASK; +} + +/** + * @brief Get DMA Monitor Checker error status + * + * @param pDma the base address of the DMA instance + * @return uint32_t status of the DMA Monitor Checker + */ +LOCAL_INLINE uint32_t DMA_HWA_GetMonitorCheckerErrStatus(DMA_Type *const pDma) +{ + return pDma->MON_ERR_STATUS; +} + +/** + * @brief Clear DMA Monitor Checker all error status + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearMonitorCheckerAllError(DMA_Type *const pDma) +{ + pDma->MON_CTRL |= DMA_MON_CTRL_ERR_CLR_MASK; +} +/** @}*/ +#endif + +#endif /* #if DMA_INSTANCE_COUNT > 0U */ + +#endif /* _HWA_DMA_H_ */ diff --git a/Inc/HwA_dmamux.h b/Inc/HwA_dmamux.h new file mode 100644 index 0000000..744f596 --- /dev/null +++ b/Inc/HwA_dmamux.h @@ -0,0 +1,112 @@ +/** + * @file HwA_dmamux.h + * @author flagchip + * @brief Hardware access layer for DMAMUX + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip099 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_DMAMUX_H_ +#define _HWA_DMAMUX_H_ + +#include "device_header.h" + +#if DMAMUX_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_dmamux HwA_dmamux + * @ingroup module_driver_dma + * @{ + */ + +/** + * @brief Get whether DMAMUX is enabled for the specified DMA channel + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @return true DMAMUX is enabled for the specified DMA channel + * @return false DMAMUX is disabled for the specified DMA channel + */ +LOCAL_INLINE bool DMAMUX_HWA_GetEnableFlag(const DMAMUX_Type *const pDmamux, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pDmamux->CHCFG[u8Channel] & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT; + return (bool)((u8TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the request source for the specified DMA channel + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @return DMA_RequestSourceType the request source of the specified DMA channel + */ +LOCAL_INLINE DMA_RequestSourceType DMAMUX_HWA_GetRequestSource(const DMAMUX_Type *const pDmamux, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pDmamux->CHCFG[u8Channel] & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT; + return (DMA_RequestSourceType)u8TmpVal; +} + +/** + * @brief Set the request source for the specified DMA channel + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @param bEnable whether to enable DMAMUX for the specified DMA channel + * @param eReqSrc the request source to set for the specified DMA channel + */ +LOCAL_INLINE void DMAMUX_HWA_SetRequestSource(DMAMUX_Type *const pDmamux, uint8_t u8Channel, bool bEnable, + DMA_RequestSourceType eReqSrc) +{ + pDmamux->CHCFG[u8Channel] = (uint8_t)((pDmamux->CHCFG[u8Channel] & ~(DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE_MASK)) | + DMAMUX_CHCFG_ENBL(bEnable) | DMAMUX_CHCFG_SOURCE(eReqSrc)); +} + +/** + * @brief Get whether periodic trig is enabled for the specified DMA channel + * + * @note Only DMA channel 0~3 supports periodic trig + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @return true periodic trig is enabled for the specified DMA channel + * @return true periodic trig is disabled for the specified DMA channel + */ +LOCAL_INLINE bool DMAMUX_HWA_GetPeriodicTrigFlag(const DMAMUX_Type *const pDmamux, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (uint8_t)((pDmamux->CHTRG & (DMAMUX_CHTRG_TRIG0_MASK << u8Channel)) >> u8Channel); + return (bool)((u8TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable periodic trig for the specified DMA channel + * + * @note Only DMA channel 0~3 supports periodic trig + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @param bEnable whether to enable periodic trig for the specified DMA channel + */ +LOCAL_INLINE void DMAMUX_HWA_SetPeriodicTrigFlag(DMAMUX_Type *const pDmamux, uint8_t u8Channel, bool bEnable) +{ + pDmamux->CHTRG = (uint8_t)((pDmamux->CHTRG & ~(DMAMUX_CHTRG_TRIG0_MASK << u8Channel)) | (DMAMUX_CHTRG_TRIG0(bEnable) << u8Channel)); +} + +/** @}*/ + +#endif /* #if DMAMUX_INSTANCE_COUNT > 0U */ + +#endif /* _HWA_DMAMUX_H_ */ diff --git a/Inc/HwA_eftu_ccm.h b/Inc/HwA_eftu_ccm.h new file mode 100644 index 0000000..d9f1c46 --- /dev/null +++ b/Inc/HwA_eftu_ccm.h @@ -0,0 +1,485 @@ +/** + * @file HwA_eftu_ccm.h + * @author flagchip + * @brief Hardware access layer for EFTU CCM + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip099 N/A Change version and release + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_EFTU_CCM_H_ +#define HWA_INCLUDE_HWA_EFTU_CCM_H_ +#include "device_header.h" + +#if EFTU_INSTANCE_COUNT > 0U + +#define EFTU_CLUSTER_CLOCK_COUNT (8U) + +#define EFTU_GTOM_CHANNEL_COUNT (16U) +#define EFTU_GTRIGGER_OUT_COUNT (8U) +#define EFTU_CMP_COUNT (2U) +#define EFTU_DMA_REQUEST_COUNT (6U) + +#define EFTU_GTRIGGER_OUT_MASK_TOM1_CCU1_BIT0 (0x1<<0U) +#define EFTU_GTRIGGER_OUT_MASK_TOM0_CCU1_BIT1 (0x1<<1U) +#define EFTU_GTRIGGER_OUT_MASK_TOM1_CCU0_BIT2 (0x1<<2U) +#define EFTU_GTRIGGER_OUT_MASK_TOM0_CCU0_BIT3 (0x1<<3U) +#define EFTU_GTRIGGER_OUT_MASK_TIM_TRIG_BIT4 (0x1<<4U) + +#define EFTU_TIM_ERROR_EN_BIT0 (0x1<<0U) +#define EFTU_TIM_ERROR_EN_BIT1 (0x1<<1U) +#define EFTU_TIM_ERROR_EN_BIT2 (0x1<<2U) +#define EFTU_TIM_ERROR_EN_BIT3 (0x1<<3U) +#define EFTU_TIM_ERROR_EN_BIT4 (0x1<<4U) +#define EFTU_TIM_ERROR_EN_BIT5 (0x1<<5U) + + +#define EFTU_TOM_SWAP_OUT_2_3_OUT_T_0_1_BIT0 (0x1<<0U) +#define EFTU_TOM_SWAP_OUT_6_7_OUT_T_4_5_BIT1 (0x1<<1U) +#define EFTU_TOM_SWAP_OUT_10_11_OUT_T_8_9_BIT2 (0x1<<2U) +#define EFTU_TOM_SWAP_OUT_14_15_OUT_T_12_13_BIT3 (0x1<<3U) +#define EFTU_TOM_SWAP_OUT_4_7_OUT_T_0_3_BIT4 (0x1<<4U) +#define EFTU_TOM_SWAP_OUT12_15_OUT_T_8_11_BIT5 (0x1<<5U) + + +typedef enum +{ + EFTU_CLUSTER_CLOCK_CMU_CLK = 0U, + EFTU_CLUSTER_CLOCK_CMU_CLK8 = 1U, + EFTU_CLUSTER_CLOCK_EXT_CAPTURE = 2U, +} EFTU_CCM_ClusterCmuClkSelectType; + +typedef enum +{ + EFTU_DEBUG_RUN = 0U, + EFTU_DEBUG_TOM_HALT = 1U, + EFTU_DEBUG_OUT_FREEZEN = 2U, + EFTU_DEBUG_ALL_HALT = 3U, +} EFTU_CCM_DebugMode; + +typedef enum +{ + EFTU_TIM_AUXI_SRC_CH0 = 0U, + EFTU_TIM_AUXI_SRC_CH1 = 1U, + EFTU_TIM_AUXI_SRC_CH2 = 2U, + EFTU_TIM_AUXI_SRC_CH3 = 3U, + EFTU_TIM_AUXI_SRC_CH4 = 4U, + EFTU_TIM_AUXI_SRC_CH5 = 5U, + EFTU_TIM_AUXI_SRC_CH6 = 6U, + EFTU_TIM_AUXI_SRC_CH7 = 7U, + EFTU_TIM_AUXI_SRC_CH8 = 8U, + EFTU_TIM_AUXI_SRC_CH9 = 9U, + EFTU_TIM_AUXI_SRC_CH10 = 10U, + EFTU_TIM_AUXI_SRC_CH11 = 11U, + EFTU_TIM_AUXI_SRC_CH12 = 12U, + EFTU_TIM_AUXI_SRC_CH13 = 13U, + EFTU_TIM_AUXI_SRC_CH14 = 14U, + EFTU_TIM_AUXI_SRC_CH15 = 15U, +} EFTU_CCM_AuxInChlSrcType; + +typedef enum +{ + EFTU0_OUT0 = 0U, + EFTU1_OUT0 = 1U, + EFTU2_OUT0 = 2U, + EFTU0_OUT1 = 3U, + EFTU1_OUT2 = 4U, + EFTU2_OUT3 = 5U, +} EFTU_CCM_AuxInSrcType; + +typedef enum +{ + EFTU_TIM_PAD_IN = 0U, + EFTU_TIM_EXT_TRIGGER = 0U, +} EFTU_CCM_TimInSrcType; + +typedef enum +{ + EFTU_GTOM_MUX_SRC_EFTU2_OUT = 0U, + EFTU_GTOM_MUX_SRC_EFTU1_OUT = 1U, + EFTU_GTOM_MUX_SRC_EFTU0_OUT = 2U, +} EFTU_CCM_GtomOutSrc; + +typedef enum +{ + EFTU_GTRIGGER_OUT_SRC_DIS = 0U, + EFTU_GTRIGGER_OUT_SRC_EFTU0 = 1U, + EFTU_GTRIGGER_OUT_SRC_EFTU1 = 2U, + EFTU_GTRIGGER_OUT_SRC_EFTU2 = 3U, +} EFTU_CCM_GlobalTriggerOutType; + +typedef enum +{ + EFTU0_CMP0 = 0U, + EFTU0_CMP1 = 1U, +} EFTU_CCM_CmpInstance; + +typedef enum +{ + EFTU_CMP_X_Y_SEL_EFTU0_OUT_0_7 = 0x0U, + EFTU_CMP_X_Y_SEL_EFTU0_OUT_8_15 = 0x1U, + EFTU_CMP_X_Y_SEL_EFTU1_OUT_0_7 = 0x2U, + EFTU_CMP_X_Y_SEL_EFTU1_OUT_8_15 = 0x3U, + EFTU_CMP_X_Y_SEL_EFTU2_OUT_0_7 = 0x4U, + EFTU_CMP_X_Y_SEL_EFTU2_OUT_8_15 = 0x5U, + + EFTU_CMP_X_Y_SEL_EFTU0_OUT_T_0_7 = 0x8U, + EFTU_CMP_X_Y_SEL_EFTU0_OUT_T_8_15 = 0x9U, + EFTU_CMP_X_Y_SEL_EFTU1_OUT_T_0_7 = 0xAU, + EFTU_CMP_X_Y_SEL_EFTU1_OUT_T_8_15 = 0xBU, + EFTU_CMP_X_Y_SEL_EFTU2_OUT_T_0_7 = 0xCU, + EFTU_CMP_X_Y_SEL_EFTU2_OUT_T_8_15 = 0xDU, +} EFTU_CCM_CmpSrcSelectType; + +typedef enum +{ + EFTU_HRPWM_SRC_OUT03_OUT_T03 = 0x0U, + EFTU_HRPWM_SRC_OUT47_OUT_T47 = 0x1U, + EFTU_HRPWM_SRC_OUT07 = 0x2U, + EFTU_HRPWM_SRC_OUT_T07 = 0x3U, +} EFTU_CCM_HrPwmSrcType; + + +typedef enum +{ + EFTU_TOM0_CH0_TO_TOM1_CH0 = 0x1U, + EFTU_TOM0_CH7_TO_TOM1_CH0 = 0x2U, +} EFTU_CCM_TomChTrigInType; + +typedef enum +{ + EFTU_CLUSTER_CMU_CLK_0 = 0u, + EFTU_CLUSTER_CMU_CLK_1 = 1u, + EFTU_CLUSTER_CMU_CLK_2 = 2u, + EFTU_CLUSTER_CMU_CLK_3 = 3u, + EFTU_CLUSTER_CMU_CLK_4 = 4u, + EFTU_CLUSTER_CMU_CLK_5 = 5u, + EFTU_CLUSTER_CMU_CLK_6 = 6u, + EFTU_CLUSTER_CMU_CLK_7 = 7u, +} EFTU_CCM_ClusterCmuClkType; + +typedef enum +{ + EFTU_TIM_ERR_CH0 = 0U, + EFTU_TIM_ERR_CH1 = 1U, + EFTU_TIM_ERR_CH2 = 2U, + EFTU_TIM_ERR_CH3 = 3U, + EFTU_TIM_ERR_CH4 = 4U, + EFTU_TIM_ERR_CH5 = 5U, + EFTU_TIM_ERR_CH6 = 6U, + EFTU_TIM_ERR_CH7 = 7U, +} EFTU_CCM_TimErrChnType; +/*EFTU_CCM_PROT*/ +LOCAL_INLINE void EFTU_CCM_HWA_EnableProtection(EFTU_CCM_Type *pCcm) +{ + pCcm->PROT |= EFTU_CCM_PROT_CLS_PROT_MASK; +} + +LOCAL_INLINE void EFTU_CCM_HWA_DisableProtection(EFTU_CCM_Type *pCcm) +{ + pCcm->PROT &= ~EFTU_CCM_PROT_CLS_PROT_MASK; +} + +LOCAL_INLINE void EFTU_CCM_HWA_ConfigDebugMode(EFTU_CCM_Type *pCcm, EFTU_CCM_DebugMode eDebugMode) +{ + pCcm->PROT = (pCcm->PROT & ~EFTU_CCM_PROT_DBG_MODE_MASK) | EFTU_CCM_PROT_DBG_MODE(eDebugMode); +} + + +/*EFTU_CCM_CFG*/ +LOCAL_INLINE void EFTU_CCM_HWA_EnableTim0(EFTU_CCM_Type *pCcm) +{ + pCcm->CFG |= EFTU_CCM_CFG_EN_TIM_MASK; +} + +LOCAL_INLINE void EFTU_CCM_HWA_EnableTom0(EFTU_CCM_Type *pCcm) +{ + pCcm->CFG |= EFTU_CCM_CFG_EN_TOM0_MASK; +} + +LOCAL_INLINE void EFTU_CCM_HWA_EnableTom1(EFTU_CCM_Type *pCcm) +{ + pCcm->CFG |= EFTU_CCM_CFG_EN_TOM1_MASK; +} + +LOCAL_INLINE void EFTU_CCM_HWA_DisableTim0(EFTU_CCM_Type *pCcm) +{ + pCcm->CFG &= ~EFTU_CCM_CFG_EN_TIM_MASK; +} + +LOCAL_INLINE void EFTU_CCM_HWA_DisableTom0(EFTU_CCM_Type *pCcm) +{ + pCcm->CFG &= ~EFTU_CCM_CFG_EN_TOM0_MASK; +} + +LOCAL_INLINE void EFTU_CCM_HWA_DisableTom1(EFTU_CCM_Type *pCcm) +{ + pCcm->CFG &= ~EFTU_CCM_CFG_EN_TOM1_MASK; +} + + +/*EFTU_CCM_CMU_CLK_CFG*/ +LOCAL_INLINE void EFTU_CCM_HWA_SetClusterCmuClkSrc(EFTU_CCM_Type *pCcm, EFTU_CCM_ClusterCmuClkType eCmuClk, EFTU_CCM_ClusterCmuClkSelectType eCmuClkSelect) +{ + pCcm->CMU_CLK_CFG = ((uint32_t)pCcm->CMU_CLK_CFG & ~(uint32_t)(0x3U << (uint8_t)(4 * eCmuClk)))| ((uint32_t)((uint8_t)eCmuClkSelect << (uint8_t)(4 * eCmuClk))); +} + + +/*EFTU_CCM_TIM_IN_SRC /EFTU_CCM_TIM_IN_SRC0 /EFTU_CCM_TIM_IN_SRC1 */ +LOCAL_INLINE void EFTU_CCM_HWA_SetTimInSrc(EFTU_CCM_Type *pCcm, uint8_t u8TimChannel, EFTU_CCM_TimInSrcType eTimSrcSelect) +{ + pCcm->TIM_IN_SRC = ((uint32_t)pCcm->TIM_IN_SRC & ~(uint32_t)(0x1u << u8TimChannel)) | ((uint32_t)eTimSrcSelect << u8TimChannel); +} + + +LOCAL_INLINE void EFTU_CCM_HWA_SetAuxInSel0_3(EFTU_CCM_Type *pCcm, uint8_t u8TimAuxIn, EFTU_CCM_AuxInSrcType eAuxInSecSrc, EFTU_CCM_AuxInChlSrcType eAuxInSecChannel) +{ + pCcm->TIM_IN_SRC0 = (pCcm->TIM_IN_SRC0 & ~(uint32_t)(0x7FU << (u8TimAuxIn * 8U)))|(eAuxInSecSrc * 16U + eAuxInSecChannel) << (u8TimAuxIn * 8U); +} + +LOCAL_INLINE void EFTU_CCM_HWA_SetAuxInSel4_7(EFTU_CCM_Type *pCcm, uint8_t u8TimAuxIn, EFTU_CCM_AuxInSrcType eAuxInSecSrc, EFTU_CCM_AuxInChlSrcType eAuxInSecChannel) +{ + pCcm->TIM_IN_SRC1 =(pCcm->TIM_IN_SRC1 & ~(uint32_t)(0x7FU << ((u8TimAuxIn - 4U) * 8U))) | (eAuxInSecSrc * 16U + eAuxInSecChannel) << ((u8TimAuxIn - 4U) * 8U); +} + + +/*EFTU_CCM_TOM_OUT*/ +LOCAL_INLINE uint16_t EFTU_CCM_HWA_GetTomOutlevel(EFTU_CCM_Type *pCcm) +{ + return pCcm->EFTU_OUT & EFTU_CCM_EFTU_OUT_EFTU_OUT_MASK ; +} + +LOCAL_INLINE uint16_t EFTU_CCM_HWA_GetTomNOutlevel(EFTU_CCM_Type *pCcm) +{ + return (pCcm->EFTU_OUT & EFTU_CCM_EFTU_OUT_EFTU_OUT_T_MASK) >> EFTU_CCM_EFTU_OUT_EFTU_OUT_T_SHIFT; +} + + +/*EFTU_CCM_GTOM_MUX_0/EFTU_CCM_GTOM_MUX_1/EFTU_CCM_GTOM_MUX_2/EFTU_CCM_GTOM_MUX_3,only for EFTU0*/ +LOCAL_INLINE void EFTU_CCM_HWA_SetGtomMux0_3(EFTU_CCM_Type *pCcm, uint8_t u8GtomAuxIn, EFTU_CCM_GtomOutSrc eGtomSrc, uint8_t u8channel) +{ + pCcm->GTOM_MUX_0 &= ~(uint32_t)(0x7FU << (u8GtomAuxIn * 8U)); + pCcm->GTOM_MUX_0 |= (uint32_t)(eGtomSrc << 5U | u8channel) << (u8GtomAuxIn * 8U); +} +LOCAL_INLINE void EFTU_CCM_HWA_SetGtomMux4_7(EFTU_CCM_Type *pCcm, uint8_t u8GtomAuxIn, EFTU_CCM_GtomOutSrc eGtomSrc, uint8_t u8channel) +{ + pCcm->GTOM_MUX_1 &= ~(uint32_t)(0x7FU << ((u8GtomAuxIn - 4U) * 8U)); + pCcm->GTOM_MUX_1 |= (uint32_t)(eGtomSrc << 5U | u8channel) << ((u8GtomAuxIn - 4U) * 8U); +} +LOCAL_INLINE void EFTU_CCM_HWA_SetGtomMux8_11(EFTU_CCM_Type *pCcm, uint8_t u8GtomAuxIn, EFTU_CCM_GtomOutSrc eGtomSrc, uint8_t u8channel) +{ + pCcm->GTOM_MUX_2 &= ~(uint32_t)(0x7FU << ((u8GtomAuxIn - 8U) * 8U)); + pCcm->GTOM_MUX_2 |= (uint32_t)(eGtomSrc << 5U | u8channel) << ((u8GtomAuxIn - 8U) * 8U); +} + +LOCAL_INLINE void EFTU_CCM_HWA_SetGtomMux12_15(EFTU_CCM_Type *pCcm, uint8_t u8GtomAuxIn, EFTU_CCM_GtomOutSrc eGtomSrc, uint8_t u8channel) +{ + pCcm->GTOM_MUX_3 &= ~(uint32_t)(0x7FU << ((u8GtomAuxIn - 12U) * 8U)); + pCcm->GTOM_MUX_3 |= (uint32_t)(eGtomSrc << 5U | u8channel) << ((u8GtomAuxIn - 12U) * 8U); +} + +#if (EFTU_HRPWM_SUPPORT == STD_ON) +/*EFTU_CCM_HRPWM_MUX,only for EFTU0*/ +LOCAL_INLINE void EFTU_CCM_HWA_SetHrPwmSrc(EFTU_CCM_Type *pCcm, EFTU_CCM_HrPwmSrcType eHrpwmSrcStatus) +{ + pCcm->HRPWM_MUX = (pCcm->HRPWM_MUX & ~EFTU_CCM_HRPWM_MUX_SWAP_CTRL_MASK)|eHrpwmSrcStatus; +} +#endif +/*EFTU_CCM_TRG_MUX/EFTU_CCM_TRG_EN0/EFTU_CCM_TRG_EN1,only for EFTU0*/ +/* +#define EFTU_GTRIGGER_OUT_MASK_TOM1_CCU1_BIT0 (0x1<<0U) +#define EFTU_GTRIGGER_OUT_MASK_TOM0_CCU1_BIT1 (0x1<<1U) +#define EFTU_GTRIGGER_OUT_MASK_TOM1_CCU0_BIT2 (0x1<<2U) +#define EFTU_GTRIGGER_OUT_MASK_TOM0_CCU0_BIT3 (0x1<<3U) +#define EFTU_GTRIGGER_OUT_MASK_TIM_TRIG_BIT4 (0x1<<4U) + * */ +LOCAL_INLINE void EFTU_CCM_HWA_ConfigGtomTriggerSrc(EFTU_CCM_Type *pCcm, uint8_t u8TrgMux, EFTU_CCM_GlobalTriggerOutType eGtriggerSrc) +{ + pCcm->TRG_MUX &= ~(uint32_t)(0x3U << (2U * u8TrgMux)); + pCcm->TRG_MUX |= (uint32_t)eGtriggerSrc << (2U * u8TrgMux); +} + +LOCAL_INLINE void EFTU_CCM_HWA_ConfigGtomTriggerMask0_3(EFTU_CCM_Type *pCcm, uint8_t u8TrgMux, uint8_t u8TriggerMask) +{ + pCcm->TRG_EN0 &= ~(uint32_t)(0x1FU << (u8TrgMux * 8U)); + pCcm->TRG_EN0 |= (uint32_t)u8TriggerMask << (u8TrgMux * 8U); +} + +LOCAL_INLINE void EFTU_CCM_HWA_ConfigGtomTriggerMask4_7(EFTU_CCM_Type *pCcm, uint8_t u8TrgMux, uint8_t u8TriggerMask) +{ + pCcm->TRG_EN1 &= ~(uint32_t)(0x1FU << ((u8TrgMux - 4U) * 8U)); + pCcm->TRG_EN1 |= (uint32_t)u8TriggerMask << ((u8TrgMux - 4U) * 8U); +} + +/*EFTU_CCM_CMP_MUX_SEL,only for EFTU0*/ +LOCAL_INLINE void EFTU_CCM_HWA_ConfigCmpSrc(EFTU_CCM_Type *pCcm, EFTU_CCM_CmpInstance eCmpInstance, uint8_t Cmp_EnMask, EFTU_CCM_CmpSrcSelectType eCmpSrc_X, + EFTU_CCM_CmpSrcSelectType eCmpSrc_Y) +{ + + pCcm->CMP_MUX_SEL &= ~ ((uint32_t)(0xFFU << (8U * (eCmpInstance + 2u))) | (uint32_t)(0xFU << (eCmpInstance * 8U)) |(uint32_t)(0xFU << (eCmpInstance * 8U + 4u))); + pCcm->CMP_MUX_SEL |= (uint32_t)Cmp_EnMask << (8U * (eCmpInstance + 2u)) | ((uint32_t)eCmpSrc_X << (eCmpInstance * 8U)) | ((uint32_t)eCmpSrc_Y << (eCmpInstance * 8U + 4u)); +} +/*EFTU_CCM_CMP Interrupt,only for EFTU0*/ +LOCAL_INLINE bool EFTU_CCM_HWA_GetCmp0IrqFlag(EFTU_CCM_Type *pCcm) +{ + return (((pCcm->EINT_ST & EFTU_CCM_EINT_ST_CMP0_ERR_MASK) != 0U) ? TRUE : FALSE); +} + +LOCAL_INLINE bool EFTU_CCM_HWA_GetCmp1IrqFlag(EFTU_CCM_Type *pCcm) +{ + return (((pCcm->EINT_ST & EFTU_CCM_EINT_ST_CMP1_ERR_MASK) != 0U) ? TRUE : FALSE); +} +LOCAL_INLINE void EFTU_CCM_HWA_ClearCmp0IrqFlag(EFTU_CCM_Type *pCcm) +{ + pCcm->EINT_ST = EFTU_CCM_EINT_ST_CMP0_ERR_MASK; +} +LOCAL_INLINE void EFTU_CCM_HWA_ClearCmp1IrqFlag(EFTU_CCM_Type *pCcm) +{ + pCcm->EINT_ST = EFTU_CCM_EINT_ST_CMP1_ERR_MASK; +} + +LOCAL_INLINE bool EFTU_CCM_HWA_GetCmp0IrqEnable(EFTU_CCM_Type *pCcm) +{ + return (((pCcm->EINT_EN & EFTU_CCM_EINT_EN_CMP0_ENABLE_MASK) != 0U) ? TRUE : FALSE); +} + +LOCAL_INLINE bool EFTU_CCM_HWA_GetCmp1IrqEnable(EFTU_CCM_Type *pCcm) +{ + return (((pCcm->EINT_EN & EFTU_CCM_EINT_EN_CMP1_ENABLE_MASK) != 0U) ? TRUE : FALSE); +} + +LOCAL_INLINE void EFTU_CCM_HWA_EnCmpInterrupt(EFTU_CCM_Type *pCcm, EFTU_CCM_CmpInstance eCmpInstance) +{ + pCcm->EINT_EN |= EFTU_CCM_EINT_EN_CMP0_ENABLE_MASK << eCmpInstance; +} + + +LOCAL_INLINE uint32 EFTU_CCM_HWA_GetErrIrqFlag(EFTU_CCM_Type *pCcm) +{ + return ((pCcm->EINT_ST & EFTU_CCM_EINT_ST_TIM_ERR_MASK) >> EFTU_CCM_EINT_ST_TIM_ERR_SHIFT); +} + + +/*EFTU_CCM_TOM_MUX*/ +/* +#define EFTU_TOM_SWAP_OUT_2_3_OUT_T_0_1_BIT0 (0x1<<0U) +#define EFTU_TOM_SWAP_OUT_6_7_OUT_T_4_5_BIT1 (0x1<<1U) +#define EFTU_TOM_SWAP_OUT_10_11_OUT_T_8_9_BIT2 (0x1<<2U) +#define EFTU_TOM_SWAP_OUT_14_15_OUT_T_12_13_BIT3 (0x1<<3U) +#define EFTU_TOM_SWAP_OUT_4_7_OUT_T_0_3_BIT4 (0x1<<4U) +#define EFTU_TOM_SWAP_OUT12_15_OUT_T_8_11_BIT5 (0x1<<5U) + * */ +LOCAL_INLINE void EFTU_CCM_HWA_SwapTomOut(EFTU_CCM_Type *pCcm, uint8_t u8OutSwapMask) +{ + pCcm->TOM_MUX = ( pCcm->TOM_MUX & ~EFTU_CCM_TOM_MUX_TOM_SWAP_MASK)|EFTU_CCM_TOM_MUX_TOM_SWAP(u8OutSwapMask); +} + +LOCAL_INLINE void EFTU_CCM_HWA_SetTom0ch0TrigIn(EFTU_CCM_Type *pCcm, EFTU_CCM_TomChTrigInType eChSrc) +{ + pCcm->TOM_MUX |= EFTU_CCM_TOM_MUX_TOM_MUX_CTRL(eChSrc); +} + +/*EFTU_CCM_SPEC_LOCK,only for EFTU0*/ +LOCAL_INLINE void EFTU_CCM_HWA_SpecUnLock(EFTU_CCM_Type *pCcm) +{ + pCcm->SPEC_LOCK = 0xBEEFCAFE; +} +LOCAL_INLINE void EFTU_CCM_HWA_SpecLock(EFTU_CCM_Type *pCcm) +{ + pCcm->SPEC_LOCK = 0x5AFECAFE; +} + +/*EFTU_CCM_EINT_EN,EFTU_CCM_TIM_EINT_EN0/EFTU_CCM_TIM_EINT_EN2*/ +/* +#define EFTU_TIM_ERROR_EN_BIT0 (0x1<<0U) +#define EFTU_TIM_ERROR_EN_BIT1 (0x1<<1U) +#define EFTU_TIM_ERROR_EN_BIT2 (0x1<<2U) +#define EFTU_TIM_ERROR_EN_BIT3 (0x1<<3U) +#define EFTU_TIM_ERROR_EN_BIT4 (0x1<<4U) +#define EFTU_TIM_ERROR_EN_BIT5 (0x1<<5U) +*/ + + +LOCAL_INLINE void EFTU_CCM_HWA_EnTimChnErrInterupt0_3(EFTU_CCM_Type *pCcm, uint8_t u8TimChannel, uint8_t u8ErrEnMask) +{ + pCcm->TIM_EINT_EN0 |= (uint32_t)u8ErrEnMask << (u8TimChannel * 8U); +} +LOCAL_INLINE void EFTU_CCM_HWA_EnTimChnErrInterupt4_7(EFTU_CCM_Type *pCcm, uint8_t u8TimChannel, uint8_t u8ErrEnMask) +{ + pCcm->TIM_EINT_EN1 |= (uint32_t)u8ErrEnMask << ((u8TimChannel - 4U) * 8U); +} + +LOCAL_INLINE uint32 EFTU_CCM_HWA_GetTimErrEnable0_3(EFTU_CCM_Type *pCcm) +{ + return pCcm->TIM_EINT_EN0 & EFTU_CCM_TIM_EINT_EN0_MASK; +} + +LOCAL_INLINE uint32 EFTU_CCM_HWA_GetTimErrEnable4_7(EFTU_CCM_Type *pCcm) +{ + return pCcm->TIM_EINT_EN1 & EFTU_CCM_TIM_EINT_EN1_MASK; +} + +LOCAL_INLINE uint32 EFTU_CCM_HWA_GetTimErrFlag0_3(EFTU_CCM_Type *pCcm) +{ + return pCcm->TIM_EINT_ST0 & EFTU_CCM_TIM_EINT_ST0_MASK; +} + +LOCAL_INLINE uint32 EFTU_CCM_HWA_GetTimErrFlag4_7(EFTU_CCM_Type *pCcm) +{ + return pCcm->TIM_EINT_ST1 & EFTU_CCM_TIM_EINT_ST1_MASK; +} + +LOCAL_INLINE void EFTU_CCM_HWA_ClearTimErrFlag0_3(EFTU_CCM_Type *pCcm, uint32 u32ErrMask) +{ + pCcm->TIM_EINT_ST0 &= u32ErrMask; +} + +LOCAL_INLINE void EFTU_CCM_HWA_ClearTimErrFlag4_7(EFTU_CCM_Type *pCcm, uint32 u32ErrMask) +{ + pCcm->TIM_EINT_ST1 &= u32ErrMask; +} + +#if (EFTU_CCM_DMA_REQ_ONE_INSTANCE == 6U) +/*EFTU_CCM_DMA_SRC01/EFTU_CCM_DMA_SRC23/EFTU_CCM_DMA_SRC45*/ +LOCAL_INLINE void EFTU_CCM_HWA_ConfigDmaSrc0_1(EFTU_CCM_Type *pCcm, uint8_t u8DmaChannel, uint8_t u8DmaReqMask) +{ + pCcm->DMA_SRC01 &= ~(uint32_t)(EFTU_CCM_DMA_SRC01_REQ_0_MASK << (u8DmaChannel * EFTU_CCM_DMA_SRC01_REQ_1_SHIFT)); + pCcm->DMA_SRC01 |= (uint32_t)u8DmaReqMask << (u8DmaChannel * EFTU_CCM_DMA_SRC01_REQ_1_SHIFT); +} + +LOCAL_INLINE void EFTU_CCM_HWA_ConfigDmaSrc2_3(EFTU_CCM_Type *pCcm, uint8_t u8DmaChannel, uint8_t u8DmaReqMask) +{ + pCcm->DMA_SRC23 &= ~(uint32_t)(EFTU_CCM_DMA_SRC01_REQ_0_MASK << ((u8DmaChannel - 2U) * EFTU_CCM_DMA_SRC01_REQ_1_SHIFT)); + pCcm->DMA_SRC23 |= (uint32_t)u8DmaReqMask << ((u8DmaChannel - 2U) * EFTU_CCM_DMA_SRC01_REQ_1_SHIFT); +} + +LOCAL_INLINE void EFTU_CCM_HWA_ConfigDmaSrc4_5(EFTU_CCM_Type *pCcm, uint8_t u8DmaChannel, uint8_t u8DmaReqMask) +{ + pCcm->DMA_SRC45 &= ~(uint32_t)(EFTU_CCM_DMA_SRC01_REQ_0_MASK << ((u8DmaChannel - 4U) * EFTU_CCM_DMA_SRC01_REQ_1_SHIFT)); + pCcm->DMA_SRC45 |= (uint32_t)u8DmaReqMask << ((u8DmaChannel - 4U) * EFTU_CCM_DMA_SRC01_REQ_1_SHIFT); +} + +#elif (EFTU_CCM_DMA_REQ_ONE_INSTANCE == 16U) + +LOCAL_INLINE void EFTU_CCM_HWA_ConfigDmaSrc(EFTU_CCM_Type *pCcm, uint8_t u8DmaChannel, uint8_t u8DmaReqMask) +{ + pCcm->DMA_SRC[(uint8_t)(u8DmaChannel>>1u)] = ((pCcm->DMA_SRC[(uint8_t)(u8DmaChannel>>1u)]) & ((~(uint32_t)(EFTU_CCM_DMA_SRC_REQ_0_MASK << (((uint8_t)u8DmaChannel&0x1U) * EFTU_CCM_DMA_SRC_REQ_1_SHIFT)))))| + (((uint32_t)u8DmaReqMask << ((u8DmaChannel&0x1U) * EFTU_CCM_DMA_SRC_REQ_1_SHIFT))); +} +#endif /*EFTU_CCM_DMA_REQ_ONE_INSTANCE*/ + +#endif /*EFTU_INSTANCE_COUNT*/ +#endif /* HWA_INCLUDE_HWA_EFTU_CCM_H_ */ diff --git a/Inc/HwA_eftu_cmu.h b/Inc/HwA_eftu_cmu.h new file mode 100644 index 0000000..a3e79a4 --- /dev/null +++ b/Inc/HwA_eftu_cmu.h @@ -0,0 +1,166 @@ +/** + * @file HwA_eftu_cmu.h + * @author flagchip + * @brief Hardware access layer for EFTU CMU + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip099 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_EFTU_CMU_H_ +#define _HWA_EFTU_CMU_H_ +#include "device_header.h" + +#if EFTU_INSTANCE_COUNT > 0U + +/********* Local typedef ************/ +/* + * @brief Clock source selection for CMU_CLK_x_CTRL +*/ +typedef enum +{ + CMU_GCLK_EN = 0u, + CMU_ECLK1_EN = 1U, +}EFTU_CMU_ClkCtrlSrcType; + +typedef enum +{ + CLUSTER_RES_CONST_1 = 0u, + CMU_ECLK0_EN = 1U, +}EFTU_CMU_Clk8CtrlSrcType; + +typedef enum +{ + EFTU_CMU_INSTANCE = 0U, +}EFTU_CMU_InstanceType; + +/** + * @brief Cmu clock definition +*/ +typedef enum +{ + EFTU_CMU_CLK_0 = 0u, + EFTU_CMU_CLK_1 = 1u, + EFTU_CMU_CLK_2 = 2u, + EFTU_CMU_CLK_3 = 3u, + EFTU_CMU_CLK_4 = 4u, + EFTU_CMU_CLK_5 = 5u, + EFTU_CMU_CLK_6 = 6u, + EFTU_CMU_CLK_7 = 7u, + EFTU_ECLK_0 = 8u, + EFTU_ECLK_1 = 9u, +}EFTU_CMU_ClkSrcType; + + +/********* Local inline function ************/ +/* + * @brief enable Cmu clock +*/ +LOCAL_INLINE void EFTU_CMU_HWA_EnableClock(EFTU_CMU_Type *const pCmu ,EFTU_CMU_ClkSrcType eChannel) +{ + pCmu->CLK_EN = (uint32_t)(0x2U << (uint8_t)(eChannel*2U)); +} + +/* + * @brief disable the Cmu clock +*/ +LOCAL_INLINE void EFTU_CMU_HWA_DisableClock(EFTU_CMU_Type *const pCmu ,EFTU_CMU_ClkSrcType eChannel) +{ + pCmu->CLK_EN = (uint32_t)(0x1u << (uint8_t)(eChannel*2U)); +} + +/* + * @brief set CMU Global Clock Control Numerator +*/ +LOCAL_INLINE void EFTU_CMU_HWA_SetGclkNum(EFTU_CMU_Type *const pCmu ,uint8_t u8Num) +{ + pCmu->GCLK_NUM = EFTU_CMU_GCLK_NUM_GCLK_NUM(u8Num); +} + +/* + * @brief set CMU Global Clock Control Denominator +*/ +LOCAL_INLINE void EFTU_CMU_HWA_SetGclkDen(EFTU_CMU_Type *const pCmu ,uint8_t u8Den) +{ + pCmu->GCLK_DEN = EFTU_CMU_GCLK_DEN_GCLK_DEN(u8Den); +} + +/* + * @brief set CMU Control for Clock Source CMU_CLK[n] n = 0~7 +*/ +LOCAL_INLINE void EFTU_CMU_HWA_SetCmuclkCnt(EFTU_CMU_Type *const pCmu ,uint32_t u32Cnt,EFTU_CMU_ClkSrcType eChannel) +{ + pCmu->CLKn_CTRL[(uint8_t)eChannel] = EFTU_CMU_CLKn_CTRL_CLK_CNT(u32Cnt); +} + +/* + * @brief set CMU ECLK0 Clock Control Numerator +*/ +LOCAL_INLINE void EFTU_CMU_HWA_SetEclk0Num(EFTU_CMU_Type *const pCmu ,uint32_t u32Num) +{ + pCmu->ECLK0_NUM = EFTU_CMU_ECLKn_NUM_ECLK_NUM(u32Num); +} + +/* + * @brief set CMU ECLK0 Clock Control Denominator +*/ +LOCAL_INLINE void EFTU_CMU_HWA_SetEclk0Den(EFTU_CMU_Type *const pCmu ,uint32_t u32Den) +{ + pCmu->ECLK0_DEN = EFTU_CMU_ECLKn_DEN_ECLK_DEN(u32Den); +} +/* + * @brief set CMU ECLK1 Clock Control Numerator +*/ +LOCAL_INLINE void EFTU_CMU_HWA_SetEclk1Num(EFTU_CMU_Type *const pCmu ,uint32_t u32Num) +{ + pCmu->ECLK1_NUM = EFTU_CMU_ECLKn_NUM_ECLK_NUM(u32Num); +} +/* + * @brief set CMU ECLK1 Clock Control Denominator +*/ +LOCAL_INLINE void EFTU_CMU_HWA_SetEclk1Den(EFTU_CMU_Type *const pCmu ,uint32_t u32Den) +{ + pCmu->ECLK1_DEN = EFTU_CMU_ECLKn_DEN_ECLK_DEN(u32Den); +} + + +LOCAL_INLINE void EFTU_CMU_HWA_SetCmuClkSrc(EFTU_CMU_Type *const pCmu ,EFTU_CMU_ClkSrcType eChannel,EFTU_CMU_ClkCtrlSrcType eCtrl) +{ + if (CMU_GCLK_EN == eCtrl) + { + pCmu->CLK_CTRL &= ~(1u<<(uint8_t)eChannel); + } + else + { + pCmu->CLK_CTRL |=(1u<<(uint8_t)eChannel); + } +} + +LOCAL_INLINE void EFTU_CMU_HWA_SetCmuClk8Src(EFTU_CMU_Type *const pCmu ,EFTU_CMU_Clk8CtrlSrcType eCtrl) +{ + if (CLUSTER_RES_CONST_1 == eCtrl) + { + pCmu->CLK_CTRL &= ~(1u<<(uint8_t)8U); + } + else + { + pCmu->CLK_CTRL |=(1u<<(uint8_t)8U); + } +} + +#endif + +#endif /*#ifndef _HWA_EFTU_CMU_H_*/ diff --git a/Inc/HwA_eftu_dtm.h b/Inc/HwA_eftu_dtm.h new file mode 100644 index 0000000..35e2355 --- /dev/null +++ b/Inc/HwA_eftu_dtm.h @@ -0,0 +1,952 @@ +/** + * @file HwA_eftu_dtm.h + * @author flagchip + * @brief Hardware access layer for EFTU DTM + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip070 N/A Change version and release + ******************************************************************************** */ + + +#ifndef _HWA_EFTU_ATM_H_ +#define _HWA_EFTU_ATM_H_ +#include "device_header.h" + +#if EFTU_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_eftu_tom HwA_eftu_dtm + * @ingroup module_driver_eftu_dtm + * @{ + */ + +/** + * @brief Clock Resolution Selection + * + */ +typedef enum +{ + EFTU_DTM_CLOCK_SRC_SYS_CLK = 0u, /* CLS_CLK resolution selected (cluster clock) */ + EFTU_DTM_CLOCK_SRC_CMU_CLK0, /* CCM_CLK_RES[0] resolution selected */ + EFTU_DTM_CLOCK_SRC_CMU_CLK1, /* CCM_CLK_RES[1] resolution selected */ + EFTU_DTM_CLOCK_SRC_CMU_CLK2, /* CCM_CLK_RES[2] resolution selected */ +} EFTU_DTM_ClockSourceType; + +/** + * @brief Selection of DTM Update and PSU_SHUT_OFF Reset Signal + * + */ +typedef enum +{ + EFTU_DTM_SEL_FALLING_EDGE_ON_CURRENT = 0U, /* Select falling edge on current DTM channel 0 input */ + EFTU_DTM_SEL_RISING_EDGE_ON_CURRENT, /* Select rising edge on current DTM channel 0 input */ + EFTU_DTM_SEL_FALLING_EDGE_ON_PRECEDING, /* Select falling edge on preceding DTM channel 0 input */ + EFTU_DTM_SEL_RISING_EDGE_ON_PRECEDING, /* Select rising edge on preceding DTM channel 0 input */ +} EFTU_DTM_UpdateSourceType; + +/** + * @brief Selection of Output 1 + * + */ +typedef enum +{ + EFTU_DTM_O1SEL_INV_DEAD_TIME_SIGNAL = 0U, /* Inverse dead time signal selected */ + EFTU_DTM_O1SEL_SPECIAL_FUNTION /* Special function on output 1 selected (defined by + CH_CTRL1[O1F_0]) */ +} EFTU_DTM_Output1SelectType; + +/** + * @brief Selection of Input 1 + * + */ +typedef enum +{ + EFTU_DTM_I1SEL_PSU_SHIFT = 0U, /* Signal PSU_SHIFT[0] selected */ + EFTU_DTM_I1SEL_PRE_DTM_COUT3_I, /* Signal DTM_COUT3_I from preceding DTM instance selected */ +} EFTU_DTM_Input1SelectType; + +/** + * @brief Selection of Output 0 Control + * + */ +typedef enum +{ + EFTU_DTM_OC_FUNCTIONAL = 0U, /* Functional output */ + EFTU_DTM_OC_CONSTANT, /* Constant output defined by CH_CTRL2[SL0_0] */ +} EFTU_DTM_Output0ControlType; + +/** + * @brief Selection of Signal Level on Output + * + */ +typedef enum +{ + EFTU_DTM_SL_LOW = 0U, /* Set Signal Level to 0 */ + EFTU_DTM_SL_HIGH /* Set Signal Level to 1 */ +} EFTU_DTM_SignalLevelType; + +/** + * @brief Selection of Combinational Input + * + */ +typedef enum +{ + EFTU_DTM_CIS_DTM_IN = 0U, /* Select the input DTM_IN[N] or DTM_IN_T[N] of the instance + (CH_CTRL3[TSEL0_N] selects one of the two input signals) */ + EFTU_DTM_CIS_EDGE_TRIGG /* Select internal signal EDGE_TRIGG_[N] */ +} EFTU_DTM_CombInputSelectType; + +/** + * @brief Input Selection for Dead Time / Edge Trigger Generation + * + */ +typedef enum +{ + EFTU_DTM_EDGE_TRIG_SEL_DTM_IN = 0U, /* Use DTM_IN[N] of the instance as input for dead time / edge trigger + generation */ + EFTU_DTM_EDGE_TRIG_SEL_DTM_IN_T /* Use DTM_IN_T[N] of the instance as input for dead time / edge + trigger generation */ +} EFTU_DTM_EdgeTrigSelectType; + +/** + * @brief Input Selection of Combinational Logic Path + * + */ +typedef enum +{ + EFTU_DTM_COMB_INPUT_LOGIC_PATH_SEL_DTM_IN = 0U, /* Use DTM_IN[N] of the instance as input for combinational logic path */ + EFTU_DTM_COMB_INPUT_LOGIC_PATH_SEL_DTM_IN_T /* Use DTM_IN_T[N] of the instance as input for combinational logic + path */ +} EFTU_DTM_CombInputLogicPathSelectType; + +/** + * @brief Selection of PSU Input + * + */ +typedef enum +{ + EFTU_DTM_PSU_IN_TIM_CH_IN = 0u, /* TIM_CH_IN0 or TIM_CH_IN1 selected */ + EFTU_DTM_PSU_IN_DTM_AUX_IN, /* DTM_AUX_IN selected */ +} EFTU_DTM_PsuInputSelectType; + +/** + * @brief Selection of input signal to be used as shutoff signal + * + */ +typedef enum +{ + EFTU_DTM_SHUTOFF_SEL_TIM_CH_IN0 = 0U, /* TIM_CH_IN0 selected */ + EFTU_DTM_SHUTOFF_SEL_TIM_CH_IN1, /* TIM_CH_IN1 selected */ + EFTU_DTM_SHUTOFF_SEL_DTM_AUX_IN2, /* DTM_AUX_IN[2] of the instance selected (SoC special connection) */ + EFTU_DTM_SHUTOFF_SEL_DTM_AUX_IN3, /* DTM_AUX_IN[3] of the instance selected (SoC special connection) */ + EFTU_DTM_SHUTOFF_SEL_DTM_AUX_IN0, /* DTM_AUX_IN[0] of the instance selected (SoC special connection) */ + EFTU_DTM_SHUTOFF_SEL_DTM_AUX_IN1, /* DTM_AUX_IN[1] of the instance selected (SoC special connection) */ + EFTU_DTM_SHUTOFF_SEL_DTM_LOW, /* '0' selected */ + EFTU_DTM_SHUTOFF_SEL_DTM_HIGH /* '1' selected*/ +} EFTU_DTM_ShutOffSignalType; + +/** + * @brief Selection of Shift + * + */ +typedef enum +{ + EFTU_DTM_SHIFT_SELECT_CHANNEL1 = 0u, /* Trigger signal for reloading DOWN COUNTER is IN_EDGE[0] of + DTM channel [0]; PSU works on DTM channel 1*/ + EFTU_DTM_SHIFT_SELECT_CHANNEL2, /* Trigger signal for reloading DOWN COUNTER is IN_EDGE[1] of + DTM channel [1]; PSU works on DTM channel 2*/ + EFTU_DTM_SHIFT_SELECT_CHANNEL3, /* Trigger signal for reloading DOWN COUNTER is IN_EDGE[2] of + DTM channel [2]; PSU works on DTM channel 3*/ + EFTU_DTM_SHIFT_SELECT_CHANNEL0 /* No loading of DOWN COUNTER (blanking window feature + deactivated); PSU works on DTM channel 0*/ +} EFTU_DTM_ShiftSelectType; + +/** + * @brief Selection of TIM Input + * + */ +typedef enum +{ + EFTU_DTM_TIM_SEL_TIM_IN0 = 0u, + EFTU_DTM_TIM_SEL_TIM_IN1, +} EFTU_DTM_TimInputSelectType; + +/** + * @brief Selection of Channel deadtime trigger + * + */ +typedef enum +{ + EFTU_DTM_CHDTV_TRIG_BY_FALLING_EDGE = 0U, /* Update of CHn_DTV triggered by falling edge */ + EFTU_DTM_CHDTV_TRIG_BY_RISING_EDGE /* Update of CHn_DTV triggered by rising edge */ +} EFTU_DTM_DeadTimeTrigSelectType; + +/** + * @brief Set the clock source for EFTU DTM + * + * @param pDtm Pointer to the base address of the EFTU DTM, used to access the DTM controller registers + * @param eClockSource The clock source type to be set, which is an enumerated value representing different clock source options + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetClockSource(EFTU_DTM_Type * const pDtm, EFTU_DTM_ClockSourceType eClockSource) +{ + pDtm->CTRL = (pDtm->CTRL & (~(uint32_t)EFTU_DTM_CTRL_CLK_SEL_MASK)) | EFTU_DTM_CTRL_CLK_SEL(eClockSource); +} + +/** + * @brief Set the DTM update signal source + * + * @param pDtm Pointer to the base address of the DTM module, used to access the DTM control register + * @param eSignal The specified update signal source, which is an enumerated value representing different signal sources + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetUpdateSignal(EFTU_DTM_Type * const pDtm, EFTU_DTM_UpdateSourceType eSignal) +{ + pDtm->CTRL = (pDtm->CTRL & (~(uint32_t)EFTU_DTM_CTRL_DTM_SEL_MASK)) | EFTU_DTM_CTRL_DTM_SEL(eSignal); +} + +/** + * @brief Set the update mode of the DTM + * + * @param pDtm Pointer to the base address of the DTM module, used to access and modify DTM registers + * @param u8UpdateMode The value of the update mode, which determines the operating mode of the DTM + * 000b - Asynchronous update + * 001b - Shutoff release by writing 1 to bit CTRL[SHUT_OFF_RST] + * 010b - Shutoff release by Select DTM Update and PSU_SHUT_OFF + * Reset Signal + * 011b - Shutoff release by shutoff signal PSU_SHUT_OFF + * 100b - Signal IN_EDGE[0] (from channel 0) used to trigger update of + * CH_CTRL2 with content of CH_CTRL2_SR + * 101b - Signal IN_EDGE[1] (from channel 1) used to trigger update of + * CH_CTRL2 with content of CH_CTRL2_SR + * 110b - Signal IN_EDGE[2] (from channel 2) used to trigger update of + * CH_CTRL2 with content of CH_CTRL2_SR + * 111b - Signal IN_EDGE[3] (from channel 3) used to trigger update of + * CH_CTRL2 with content of CH_CTRL2_SR + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetUpdateMode(EFTU_DTM_Type * const pDtm, uint8_t u8UpdateMode) +{ + pDtm->CTRL = (pDtm->CTRL & (~(uint32_t)EFTU_DTM_CTRL_UPD_MODE_MASK)) | EFTU_DTM_CTRL_UPD_MODE(u8UpdateMode); +} + +/** + * @brief Set Individual Shutoff Feature Enable + * + * This function modifies the CH_SHUTOFF_EN bit in the CTRL register of the EFTU_DTM controller to enable or disable the channel shut-off feature. + * + * @param pDtm Pointer to the base address of the EFTU_DTM module, used to access the module's registers + * @param bEnable Boolean value specifying whether to enable the Individual Shutoff Feature Enable. If true, the feature is enabled; if false, it is disabled + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetChannelShutOffEnable(EFTU_DTM_Type * const pDtm, bool bEnable) +{ + pDtm->CTRL = (pDtm->CTRL & (~(uint32_t)EFTU_DTM_CTRL_CH_SHUTOFF_EN_MASK)) | EFTU_DTM_CTRL_CH_SHUTOFF_EN(bEnable); +} + +/** + * @brief Set the shadow register update enable + * + * @param pDtm Base address pointer to the EFTU_DTM controller for accessing its registers + * @param bEnable Enable flag for shadow register updates, true to enable updates, false to disable updates + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetShadowRegisterUpdateEnable(EFTU_DTM_Type * const pDtm, bool bEnable) +{ + pDtm->CTRL = (pDtm->CTRL & (~(uint32_t)EFTU_DTM_CTRL_SR_UPD_EN_MASK)) | EFTU_DTM_CTRL_SR_UPD_EN(bEnable); +} + +/** + * @brief Shut off reset + * + * @param pDtm Base address pointer to the EFTU_DTM controller for accessing its registers + */ +LOCAL_INLINE void EFTU_DTM_HWA_ShutOffReset(EFTU_DTM_Type * const pDtm) +{ + pDtm->CTRL |= EFTU_DTM_CTRL_SHUT_OFF_RST_MASK; +} + +/** + * @brief Selects the output 1 source for EFTU DTM + * + * @param pDtm Pointer to the base address of the EFTU DTM, used to access its registers + * @param u8Channel Channel number, used to calculate the position of the control bits + * @param eSelect Output 1 selection value, specifying the new output source + */ +LOCAL_INLINE void EFTU_DTM_HWA_SelectOutput1(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_Output1SelectType eSelect) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL1 = (pDtm->CH_CTRL1 & (~(((uint32_t)EFTU_DTM_CH_CTRL1_O1SEL_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL1_O1SEL_0(eSelect) << u8Channel); +} + +/** + * @brief Selects the input 1 for EFTU DTM + * + * @param pDtm Pointer to the base address of the EFTU DTM, used to access DTM registers + * @param u8Channel Channel number, used to calculate the bit position for the channel control + * @param eSelect Input 1 selection value, specifying the new input source + */ +LOCAL_INLINE void EFTU_DTM_HWA_SelectInput1(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_Input1SelectType eSelect) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL1 = (pDtm->CH_CTRL1 & (~(((uint32_t)EFTU_DTM_CH_CTRL1_I1SEL_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL1_I1SEL_0(eSelect) << u8Channel); +} + +/** + * @brief Enable or disable the swap flag for a specific channel + * + * @param pDtm Pointer to the base address of the EFTU_DTM module, used to access the module's registers + * @param u8Channel Channel number, used to calculate the corresponding bit in the channel control register + * @param bEnable Boolean value indicating whether to enable the data swap feature + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetSwapEnable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL1 = (pDtm->CH_CTRL1 & (~(((uint32_t)EFTU_DTM_CH_CTRL1_SWAP_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL1_SWAP_0(bEnable) << u8Channel); +} + +/** + * @brief Set the output 1 function for a specific channel of the EFTU DTM module + * + * @param pDtm Pointer to the EFTU_DTM_Type structure, representing the base address of the EFTU DTM module + * @param u8Channel The channel number to configure + * @param u8Function The output 1 function selection value + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetOutput1Function(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, uint8_t u8Function) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL1 = (pDtm->CH_CTRL1 & (~(((uint32_t)EFTU_DTM_CH_CTRL1_O1F_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL1_O1F_0(u8Function) << u8Channel); +} + +/** + * @brief Enable or disable cross dead time + * + * @param pDtm Base address pointer of the DTM module + * @param u8Channel Channel number + * @param bEnable True to enable cross dead time, false to disable + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetCrossDeadTimeEnable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable) +{ + u8Channel = ((u8Channel & 0x2) << 3U); + pDtm->CH_CTRL1 = (pDtm->CH_CTRL1 & (~(((uint32_t)EFTU_DTM_CH_CTRL1_XDT_EN_0_1_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL1_XDT_EN_0_1(bEnable) << u8Channel); +} + +/** + * @brief Enable or disable shift function + * + * @param pDtm Base address pointer of the DTM module + * @param u8Channel Channel number, supports only channel 1 + * @param bEnable True to enable shift function, false to disable + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetShiftEnable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable) +{ + u8Channel = (uint8_t)((u8Channel - 1U) << 3U); + pDtm->CH_CTRL1 = (pDtm->CH_CTRL1 & (~(((uint32_t)EFTU_DTM_CH_CTRL1_SH_EN_1_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL1_SH_EN_1(bEnable) << u8Channel); +} + +/** + * @brief Invert output 0 polarity + * + * @param pDtm Base address pointer of the DTM module + * @param u8Channel Channel number + * @param bInvert True to invert the polarity of output 0, false to not invert + */ +LOCAL_INLINE void EFTU_DTM_HWA_InvertOutput0(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bInvert) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_POL0_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_POL0_0(bInvert) << u8Channel); +} + +/** + * @brief Set output 0 control mode + * + * @param pDtm Base address pointer of the DTM module + * @param u8Channel Channel number + * @param eCtrl Control mode for output 0 + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetOutput0Ctrl(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_Output0ControlType eCtrl) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_OC0_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_OC0_0(eCtrl) << u8Channel); +} + +/** + * @brief Set output 0 signal level + * + * @param pDtm Base address pointer of the DTM module + * @param u8Channel Channel number + * @param eLevel Signal level for output 0 + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetOutput0SignalLevel(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_SignalLevelType eLevel) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SL0_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SL0_0(eLevel) << u8Channel); +} + +/** + * @brief Enable or disable dead time 0 + * + * @param pDtm Base address pointer of the DTM module + * @param u8Channel Channel number + * @param bEnable True to enable dead time 0, false to disable + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetDeadTime0Enable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_DT0_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_DT0_0(bEnable) << u8Channel); +} + +/** + * @brief Inverts the output polarity of a specified channel. + * + * @param pDtm Pointer to the EFTU DTM module register base. + * @param u8Channel The channel number, indicating which channel's output polarity to invert. + * @param bInvert A boolean value, true to invert the output polarity, false to keep it unchanged. + */ +LOCAL_INLINE void EFTU_DTM_HWA_InvertOutput1(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bInvert) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_POL1_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_POL1_0(bInvert) << u8Channel); +} + +/** + * @brief Sets the control mode for output 1 of a specified channel. + * + * @param pDtm Pointer to the EFTU DTM module register base. + * @param u8Channel The channel number, indicating which channel's output 1 control mode to set. + * @param eCtrl The control mode for output 1, specifying how the output should be controlled. + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetOutput1Ctrl(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_Output0ControlType eCtrl) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_OC1_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_OC1_0(eCtrl) << u8Channel); +} + +/** + * @brief Sets the signal level for output 1 of a specified channel. + * + * @param pDtm Pointer to the EFTU DTM module register base. + * @param u8Channel The channel number, indicating which channel's output 1 signal level to set. + * @param eLevel The signal level for output 1, specifying the output signal level. + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetOutput1SignalLevel(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_SignalLevelType eLevel) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SL1_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SL1_0(eLevel) << u8Channel); +} + +/** + * @brief Enables or disables dead time insertion for output 1 of a specified channel. + * + * @param pDtm Pointer to the EFTU DTM module register base. + * @param u8Channel The channel number, indicating which channel's output 1 dead time insertion to control. + * @param bEnable A boolean value, true to enable dead time insertion, false to disable it. + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetDeadTime1Enable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2 = (pDtm->CH_CTRL2 & (~(((uint32_t)EFTU_DTM_CH_CTRL2_DT1_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_DT1_0(bEnable) << u8Channel); +} + +/** + * @brief Set the value of the Channel Control 2 register + * + * @param pDtm Base address pointer of the EFTU_DTM module + * @param u32Value Value to be written to the CH_CTRL2 register + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetCHCTRL2(EFTU_DTM_Type * const pDtm, uint32_t u32Value) +{ + pDtm->CH_CTRL2 = u32Value; +} + +/** + * @brief Get the value of the Channel Control 2 register + * + * @param pDtm Base address pointer of the EFTU_DTM module + * @return uint32_t Current value of the CH_CTRL2 register + */ +LOCAL_INLINE uint32_t EFTU_DTM_HWA_GetCHCTRL2(EFTU_DTM_Type * const pDtm) +{ + return pDtm->CH_CTRL2; +} + +/** + * @brief Invert the polarity of Output 0 + * + * @param pDtm Base address pointer of the EFTU_DTM module + * @param u8Channel Channel number + * @param bInvert Whether to invert the output polarity, true for inversion, false for no inversion + */ +LOCAL_INLINE void EFTU_DTM_HWA_InvertOutput0Shadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bInvert) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_POL0_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_POL0_0_SR(bInvert) << u8Channel); +} + +/** + * @brief Set the control mode of Output 0 + * + * @param pDtm Base address pointer of the EFTU_DTM module + * @param u8Channel Channel number + * @param eCtrl Control mode of Output 0 + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetOutput0CtrlShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_Output0ControlType eCtrl) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_OC0_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_OC0_0_SR(eCtrl) << u8Channel); +} + +/** + * @brief Set the signal level of Output 0 + * + * @param pDtm Base address pointer of the EFTU_DTM module + * @param u8Channel Channel number + * @param eLevel Signal level of Output 0 + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetOutput0SignalLevelShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_SignalLevelType eLevel) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_SL0_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_SL0_0_SR(eLevel) << u8Channel); +} + +/** + * @brief Set the enable state of Dead Time 0 + * + * @param pDtm Base address pointer of the EFTU_DTM module + * @param u8Channel Channel number + * @param bEnable Enable state of Dead Time 0, true for enabled, false for disabled + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetDeadTime0EnableShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_DT0_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_DT0_0_SR(bEnable) << u8Channel); +} + +/** + * @brief Invert the polarity of Output 1 + * + * @param pDtm Base address pointer of the EFTU_DTM module + * @param u8Channel Channel number + * @param bInvert Whether to invert the output polarity, true for inversion, false for no inversion + */ +LOCAL_INLINE void EFTU_DTM_HWA_InvertOutput1Shadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bInvert) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_POL1_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_POL1_0_SR(bInvert) << u8Channel); +} + +/** + * @brief Set the output 1 control shadow register for a DTM channel + * + * This function sets the output 1 control shadow register (CH_CTRL2_SR) bits for a specific DTM channel, + * controlling the behavior of the output signal. + * + * @param pDtm Pointer to the base address of the DTM module + * @param u8Channel Channel number to select the specific DTM channel + * @param eCtrl Output control selection, specifying the behavior of the output signal + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetOutput1CtrlShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_Output0ControlType eCtrl) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_OC1_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_OC1_0_SR(eCtrl) << u8Channel); +} + +/** + * @brief Set the output 1 signal level shadow register for a DTM channel + * + * This function sets the output 1 signal level shadow register (CH_CTRL2_SR) bits for a specific DTM channel, + * defining the signal level of the output. + * + * @param pDtm Pointer to the base address of the DTM module + * @param u8Channel Channel number to select the specific DTM channel + * @param eLevel Signal level selection, specifying the level of the output signal + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetOutput1SignalLevelShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_SignalLevelType eLevel) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_SL1_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_SL1_0_SR(eLevel) << u8Channel); +} + +/** + * @brief Set the dead time 1 enable shadow register for a DTM channel + * + * @param pDtm Pointer to the base address of the DTM module + * @param u8Channel Channel number to select the specific DTM channel + * @param bEnable Dead time enable selection, true to enable, false to disable + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetDeadTime1EnableShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_CTRL2_SR_DT1_0_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL2_SR_DT1_0_SR(bEnable) << u8Channel); +} + +/** + * @brief Directly set the CH_CTRL2_SR register value for a DTM channel + * + * @param pDtm Pointer to the base address of the DTM module + * @param u32Value Value to set the CH_CTRL2_SR register + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetCTRL2SR(EFTU_DTM_Type * const pDtm, uint32_t u32Value) +{ + pDtm->CH_CTRL2_SR = u32Value; +} + +/** + * @brief Get the CH_CTRL2_SR register value for a DTM channel + * + * @param pDtm Pointer to the base address of the DTM module + * @return uint32_t Value of the CH_CTRL2_SR register + */ +LOCAL_INLINE uint32_t EFTU_DTM_HWA_GetCTRL2SR(EFTU_DTM_Type * const pDtm) +{ + return pDtm->CH_CTRL2_SR; +} + +/** + * @brief Set the polarity of the comb input signal for a DTM channel + * + * @param pDtm Pointer to the base address of the DTM module + * @param u8Channel Channel number to select the specific DTM channel + * @param bInvert Polarity selection, true to invert, false to not invert + */ +LOCAL_INLINE void EFTU_DTM_InvertCombInput(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bInvert) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL3 = (pDtm->CH_CTRL3 & (~(((uint32_t)EFTU_DTM_CH_CTRL3_CII0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL3_CII0(bInvert) << u8Channel); +} + +/** + * @brief Select the comb input signal source for a DTM channel + * + * @param pDtm Pointer to the base address of the DTM module + * @param u8Channel Channel number to select the specific DTM channel + * @param eSelect Signal source selection, specifying the input signal to use + */ +LOCAL_INLINE void EFTU_DTM_SelectCombInput(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_CombInputSelectType eSelect) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL3 = (pDtm->CH_CTRL3 & (~(((uint32_t)EFTU_DTM_CH_CTRL3_CIS0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL3_CIS0(eSelect) << u8Channel); +} + +/** + * @brief Select the edge trigger source for a DTM channel + * + * @param pDtm Pointer to the base address of the DTM module + * @param u8Channel Channel number to select the specific DTM channel + * @param eSelect Trigger source selection, specifying the source of the trigger event + */ +LOCAL_INLINE void EFTU_DTM_SelectEdgeTrigGen(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_EdgeTrigSelectType eSelect) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL3 = (pDtm->CH_CTRL3 & (~(((uint32_t)EFTU_DTM_CH_CTRL3_TSEL0_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL3_TSEL0_0(eSelect) << u8Channel); +} + +/** + * @brief Select the comb input logic path for a DTM channel + * + * @param pDtm Pointer to the base address of the DTM module + * @param u8Channel Channel number to select the specific DTM channel + * @param eSelect Logic path selection, specifying the logical processing of the input signal + */ +LOCAL_INLINE void EFTU_DTM_SelectCombInputLogicPath(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_CombInputLogicPathSelectType eSelect) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CH_CTRL3 = (pDtm->CH_CTRL3 & (~(((uint32_t)EFTU_DTM_CH_CTRL3_TSEL1_0_MASK) << u8Channel))) | (EFTU_DTM_CH_CTRL3_TSEL1_0(eSelect) << u8Channel); +} + +/** + * @brief Set the reload value for the DTM + * + * @param pDtm Pointer to the base address of the DTM module + * @param u16RelBlk Reload value, specifying the reload value of the counter + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetReloadValueBlkWin(EFTU_DTM_Type * const pDtm, uint16_t u16RelBlk) +{ + pDtm->PS_CTRL = (pDtm->PS_CTRL & (~(uint32_t)EFTU_DTM_PS_CTRL_RELBLK_MASK)) | EFTU_DTM_PS_CTRL_RELBLK(u16RelBlk); +} + +/** + * @brief Select the power supply input source for the DTM + * + * @param pDtm Pointer to the base address of the DTM module + * @param eSelection Power supply input source selection, specifying the power supply input to use + */ +LOCAL_INLINE void EFTU_DTM_HWA_SelectPsuInput(EFTU_DTM_Type * const pDtm, EFTU_DTM_PsuInputSelectType eSelection) +{ + pDtm->PS_CTRL = (pDtm->PS_CTRL & (~(uint32_t)EFTU_DTM_PS_CTRL_PSU_IN_SEL_MASK)) | EFTU_DTM_PS_CTRL_PSU_IN_SEL(eSelection); +} + +/** + * @brief Inverts the input polarity + * + * @param pDtm Base address pointer of the EFTU DTM + * @param bInvert Whether to invert the input polarity, true for inversion, false for no inversion + */ +LOCAL_INLINE void EFTU_DTM_InvertInputPolarity(EFTU_DTM_Type * const pDtm, bool bInvert) +{ + pDtm->PS_CTRL = (pDtm->PS_CTRL & (~(uint32_t)EFTU_DTM_PS_CTRL_IN_POL_MASK)) | EFTU_DTM_PS_CTRL_IN_POL(bInvert); +} + +/** + * @brief Selects the timer input + * + * @param pDtm Base address pointer of the EFTU DTM + * @param eSelect Timer input selection parameter, see EFTU_DTM_TimInputSelectType definition + */ +LOCAL_INLINE void EFTU_DTM_HWA_SelectTimInput(EFTU_DTM_Type * const pDtm, EFTU_DTM_TimInputSelectType eSelect) +{ + pDtm->PS_CTRL = (pDtm->PS_CTRL & (~(uint32_t)EFTU_DTM_PS_CTRL_TIM_SEL_MASK)) | EFTU_DTM_PS_CTRL_TIM_SEL(eSelect); +} + +/** + * @brief Selects the shift operation + * + * @param pDtm Base address pointer of the EFTU DTM + * @param eSelect Shift selection parameter, see EFTU_DTM_ShiftSelectType definition + */ +LOCAL_INLINE void EFTU_DTM_HWA_SelectShift(EFTU_DTM_Type * const pDtm, EFTU_DTM_ShiftSelectType eSelect) +{ + pDtm->PS_CTRL = (pDtm->PS_CTRL & (~(uint32_t)EFTU_DTM_PS_CTRL_SHIFT_SEL_MASK)) | EFTU_DTM_PS_CTRL_SHIFT_SEL(eSelect); +} + +/** + * @brief Sets the rising edge dead time + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param u16DeadTime Dead time value + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetRisingEdgeDeadTime(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, uint16_t u16DeadTime) +{ + pDtm->CHn_DTV[u8Channel] = (pDtm->CHn_DTV[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_DT_RISE_MASK)) | EFTU_DTM_CHn_DTV_DT_RISE(u16DeadTime); +} + +/** + * @brief Sets the falling edge dead time + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param u16DeadTime Dead time value + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetFallingEdgeDeadTime(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, uint16_t u16DeadTime) +{ + pDtm->CHn_DTV[u8Channel] = (pDtm->CHn_DTV[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_DT_FALL_MASK)) | EFTU_DTM_CHn_DTV_DT_FALL(u16DeadTime); +} +#if defined(HRPWM_INSTANCE_COUNT) && (HRPWM_INSTANCE_COUNT > 0U) +/** + * @brief Sets the HRPWM mode + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param bEnable Whether to enable HRPWM mode, true for enable, false for disable + */ +LOCAL_INLINE void EFTU_DTM_SetHRPWM(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable) +{ + pDtm->CHn_DTV[u8Channel] = (pDtm->CHn_DTV[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_HRES_MASK)) | EFTU_DTM_CHn_DTV_HRES(bEnable); +} +#endif +/** + * @brief Sets the output 0 signal level + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param eLevel Signal level, see EFTU_DTM_SignalLevelType definition + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetOutput0SignalLevelShadowShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_SignalLevelType eLevel) +{ + u8Channel = (uint8_t)(u8Channel << 1U); + pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_SR_SL0_0_SR_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_SR_SL0_0_SR_SR(eLevel) << u8Channel); +} + +/** + * @brief Sets the output 1 signal level + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param eLevel Signal level, see EFTU_DTM_SignalLevelType definition + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetOutput1SignalLevelShadowShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_SignalLevelType eLevel) +{ + u8Channel = (uint8_t)(u8Channel << 1U); + pDtm->CH_CTRL2_SR = (pDtm->CH_CTRL2_SR & (~(((uint32_t)EFTU_DTM_CH_SR_SL1_0_SR_SR_MASK) << u8Channel))) | (EFTU_DTM_CH_SR_SL1_0_SR_SR(eLevel) << u8Channel); +} + +/** + * @brief Selects the shut-off signal + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param eSignal Shut-off signal selection parameter, see EFTU_DTM_ShutOffSignalType definition + */ +LOCAL_INLINE void EFTU_DTM_HWA_SelectShutOffSignal(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_ShutOffSignalType eSignal) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CTRL2 = (pDtm->CTRL2 & (~(((uint32_t)EFTU_DTM_CTRL2_SHUTOFF_SEL_0_MASK) << u8Channel))) | (EFTU_DTM_CTRL2_SHUTOFF_SEL_0(eSignal) << u8Channel); +} + +/** + * @brief Inverts the shut-off signal + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param bInvert Whether to invert the shut-off signal polarity, true for inversion, false for no inversion + */ +LOCAL_INLINE void EFTU_DTM_HWA_InvertShutOffSignal(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bInvert) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CTRL2 = (pDtm->CTRL2 & (~(((uint32_t)EFTU_DTM_CTRL2_SHUTOFF_POL_0_MASK) << u8Channel))) | (EFTU_DTM_CTRL2_SHUTOFF_POL_0(bInvert) << u8Channel); +} + +/** + * @brief Sets the update mode of the internal SHUTOFF_SYNC_N signal + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param u8UpdateMode Update mode value + * 00b - Internal signal SHUTOFF_SYNC_0 is cleared; a set is not possible + * 01b - Signal PSU_SHUT_OFF[0] sets internal signal SHUTOFF_SYNC_0; + * internal signal SHUTOFF_SYNC_0 is cleared depending on bit field + * CTRL2[SHUT_OFF_RST_0] + * 10b - Signal PSU_SHUT_OFF[0] sets internal signal SHUTOFF_SYNC_0; + * internal signal SHUTOFF_SYNC_0 is cleared by signal + * DTM_PREV_IN0_REDGE or DTM_PREV_IN0_FEDGE or DTM_IN_REDGE + * of channel 0 or DTM_IN_FEDGE of channel 0 defined by bit field + * CTRL[DTM_SEL] + * 11b - Signal PSU_SHUT_OFF[0] =1 sets internal signal + * SHUTOFF_SYNC_0; signal PSU_SHUT_OFF[0] =0 clears internal signal + * SHUTOFF_SYNC_0 + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetShutOffSyncUpdateMode(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, uint8_t u8UpdateMode) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CTRL2 = (pDtm->CTRL2 & (~(((uint32_t)EFTU_DTM_CTRL2_UPD_MODE_0_MASK) << u8Channel))) | (EFTU_DTM_CTRL2_UPD_MODE_0(u8UpdateMode) << u8Channel); +} + +/** + * @brief Clear of internal signal SHUTOFF_SYNC_ + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + */ +LOCAL_INLINE void EFTU_DTM_HWA_ResetShutOffSync(EFTU_DTM_Type * const pDtm, uint8_t u8Channel) +{ + pDtm->CTRL2 |= (EFTU_DTM_CTRL2_WR_EN_0_MASK | EFTU_DTM_CTRL2_SHUT_OFF_RST_0_MASK) << (u8Channel << 3U); +} + +/** + * @brief Sets the write enable + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param bEnable Whether to enable write operations, true for enable, false for disable + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetWriteEnable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable) +{ + u8Channel = (uint8_t)(u8Channel << 3U); + pDtm->CTRL2 = (pDtm->CTRL2 & (~(((uint32_t)EFTU_DTM_CTRL2_WR_EN_0_MASK) << u8Channel))) | (EFTU_DTM_CTRL2_WR_EN_0(bEnable) << u8Channel); +} + +/** + * @brief Sets the CTRL2 register value + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u32Value Value to set for the CTRL2 register + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetCTRL2(EFTU_DTM_Type * const pDtm, uint32_t u32Value) +{ + pDtm->CTRL2 = u32Value; +} + +/** + * @brief Gets the CTRL2 register value + * + * @param pDtm Base address pointer of the EFTU DTM + * @return The value of the CTRL2 register + */ +LOCAL_INLINE uint32_t EFTU_DTM_HWA_GetCTRL2(EFTU_DTM_Type * const pDtm) +{ + return pDtm->CTRL2; +} + +/** + * @brief Sets the Shadow value for rising edge dead time + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param u16DeadTime Dead time value + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetRisingEdgeDeadTimeShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, uint16_t u16DeadTime) +{ + pDtm->CHn_DTV_SR[u8Channel] = (pDtm->CHn_DTV_SR[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_SR_DT_RISE_SR_MASK)) | EFTU_DTM_CHn_DTV_SR_DT_RISE_SR(u16DeadTime); +} + +/** + * @brief Selects the rising dead time trigger + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param eSelect Trigger selection parameter, see EFTU_DTM_DeadTimeTrigSelectType definition + */ +LOCAL_INLINE void EFTU_DTM_HWA_SelectRisingDeadTimeTrigger(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_DeadTimeTrigSelectType eSelect) +{ + pDtm->CHn_DTV_SR[u8Channel] = (pDtm->CHn_DTV_SR[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_SR_DT_RISE_UPD_FE0RE1_MASK)) | EFTU_DTM_CHn_DTV_SR_DT_RISE_UPD_FE0RE1(eSelect); +} + +/** + * @brief Sets the update rising dead time enable + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param bEnable Whether to enable the update, true for enable, false for disable + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetUpdateRisingDeadTimeEnable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable) +{ + pDtm->CHn_DTV_SR[u8Channel] = (pDtm->CHn_DTV_SR[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_SR_DT_RISE_UPD_EN_MASK)) | EFTU_DTM_CHn_DTV_SR_DT_RISE_UPD_EN(bEnable); +} + +/** + * @brief Sets the Shadow Value for Falling Edge Dead Time + * + * @param pDtm Base address pointer of the EFTU DTM + * @param u8Channel Channel number + * @param u16DeadTime Dead time value + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetFallingEdgeDeadTimeShadow(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, uint16_t u16DeadTime) +{ + pDtm->CHn_DTV_SR[u8Channel] = (pDtm->CHn_DTV_SR[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_SR_DT_FALL_SR_MASK)) | EFTU_DTM_CHn_DTV_SR_DT_FALL_SR(u16DeadTime); +} + +/** + * @brief Select the falling edge dead time trigger + * + * @param pDtm Pointer to the base address of the DTM module + * @param u8Channel Channel number + * @param eSelect Trigger selection enum value + */ +LOCAL_INLINE void EFTU_DTM_HWA_SelectFallingDeadTimeTrigger(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, EFTU_DTM_DeadTimeTrigSelectType eSelect) +{ + pDtm->CHn_DTV_SR[u8Channel] = (pDtm->CHn_DTV_SR[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_SR_DT_FALL_UPD_FE0RE1_MASK)) | EFTU_DTM_CHn_DTV_SR_DT_FALL_UPD_FE0RE1(eSelect); +} + +/** + * @brief Set the update enable for falling edge dead time + * + * @param pDtm Pointer to the base address of the DTM module + * @param u8Channel Channel number + * @param bEnable Boolean value to enable or disable the update + */ +LOCAL_INLINE void EFTU_DTM_HWA_SetUpdateFallingDeadTimeEnable(EFTU_DTM_Type * const pDtm, uint8_t u8Channel, bool bEnable) +{ + pDtm->CHn_DTV_SR[u8Channel] = (pDtm->CHn_DTV_SR[u8Channel] & (~(uint32_t)EFTU_DTM_CHn_DTV_SR_DT_FALL_UPD_EN_MASK)) | EFTU_DTM_CHn_DTV_SR_DT_FALL_UPD_EN(bEnable); +} +/** @}*/ +#endif /* EFTU_INSTANCE_COUNT > 0U */ +#endif /* _HWA_EFTU_ATM_H_ */ diff --git a/Inc/HwA_eftu_tbu.h b/Inc/HwA_eftu_tbu.h new file mode 100644 index 0000000..8cddbf8 --- /dev/null +++ b/Inc/HwA_eftu_tbu.h @@ -0,0 +1,451 @@ +/** + * @file HwA_eftu_tbu.h + * @author flagchip + * @brief Hardware access layer for EFTU TBU + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip099 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_EFTU_TBU_H_ +#define _HWA_EFTU_TBU_H_ +#include "device_header.h" + +#if EFTU_INSTANCE_COUNT > 0U +/********* Local typedef ************/ +/** + * @brief Select the EFTU TBU clock source. + * + */ +typedef enum +{ + EFTU_TBU_CMU_CLK0 = 0U, + EFTU_TBU_CMU_CLK1, + EFTU_TBU_CMU_CLK2, + EFTU_TBU_CMU_CLK3, + EFTU_TBU_CMU_CLK4, + EFTU_TBU_CMU_CLK5, + EFTU_TBU_CMU_CLK6, + EFTU_TBU_CMU_CLK7 +} EFTU_TBU_ClkSrcType; + +/* +*@brief Select the EFTU channel_0 register resolution. +*/ +typedef enum +{ + EFTU_TBU_CNT0_0_23BIT = 0U, + EFTU_TBU_CNT0_3_26BIT +} EFTU_TBU_Ch0ResType; + +/* +*@brief Select the EFTU channel x +*/ +typedef enum +{ + EFTU_TBU_CNT0 = 0U, + EFTU_TBU_CNT1, + EFTU_TBU_CNT2, + EFTU_TBU_CNT3, + EFTU_TBU_MAX +} EFTU_TBU_ChnCntType; + +/* +*@brief Select the EFTU TBU CNT3 QD mode +*/ +typedef enum +{ + EFTU_TBU_QD_DIR_MODE = 0U, + EFTU_TBU_QD_PHA_MODE, +} EFTU_TBU_QDModeType; + +typedef enum +{ + EFTU_TBU_INSTANCE = 0U, +} EFTU_TBU_InstanceType; + +/* +*@brief Channel selector for modulo counter. Only for channel 3 +*/ +typedef enum +{ + EFTU0_CNT_TIM0_1 = 0U, + EFTU0_CNT_TIM2_3 = 1U, +} EFTU_TBU_QDInputSrcType; + +/********* Local inline function ************/ +/* + * @brief enable Tbu channel +*/ +LOCAL_INLINE void EFTU_TBU_HWA_EnableChannel(EFTU_TBU_Type *const pTbu, EFTU_TBU_ChnCntType eChannel) +{ + pTbu->CNTEN = (0x2U << (uint8_t)(eChannel * 2u)); +} + +/* + * @brief disable Tbu channel +*/ +LOCAL_INLINE void EFTU_TBU_HWA_DisableChannel(EFTU_TBU_Type *const pTbu, EFTU_TBU_ChnCntType eChannel) +{ + pTbu->CNTEN = (0x1U << (uint8_t)(eChannel * 2u)); +} + +/** + * @brief select the clock src of the channel 0 + * */ +LOCAL_INLINE void EFTU_TBU_HWA_SetTs0Src(EFTU_TBU_Type *const pTbu, EFTU_TBU_ClkSrcType eClkSrc) +{ + pTbu->CNT0_CTRL |= EFTU_TBU_CNT0_CTRL_CNT_CLK_SRC(eClkSrc); +} + +/** + * @brief select the clock src of the channel 0 + * */ +LOCAL_INLINE void EFTU_TBU_HWA_SetTs1Src(EFTU_TBU_Type *const pTbu, EFTU_TBU_ClkSrcType eClkSrc) +{ + pTbu->CNT1_CTRL |= EFTU_TBU_CNT1_CTRL_CNT_CLK_SRC(eClkSrc); +} + +/** + * @brief select the clock src of the channel 0 + * */ +LOCAL_INLINE void EFTU_TBU_HWA_SetTs2Src(EFTU_TBU_Type *const pTbu, EFTU_TBU_ClkSrcType eClkSrc) +{ + pTbu->CNT2_CTRL |= EFTU_TBU_CNT2_CTRL_CNT_CLK_SRC(eClkSrc); +} + + +/** + * @brief select the time base register of the channel 0 provided to the sub module. +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetChannel0BaseReg(EFTU_TBU_Type *const pTbu, EFTU_TBU_Ch0ResType eTbuch0base) +{ + pTbu->CNT0_CTRL |= EFTU_TBU_CNT0_CTRL_LOW_RES(eTbuch0base); +} + +/** + * @brief get the TBU_TSx. + */ +LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetChannelTS0(const EFTU_TBU_Type *const pTbu) +{ + return (uint32_t)(pTbu->CNT0_BASE & EFTU_TBU_CNT0_BASE_BASE_MASK); +} + +/** + * @brief get the TBU_TSx. + */ +LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetChannelTS1(const EFTU_TBU_Type *const pTbu) +{ + + return (uint32_t)(pTbu->CNT1_BASE & EFTU_TBU_CNT1_BASE_BASE_MASK); + +} +/** + * @brief get the TBU_TSx. + */ +LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetChannelTS2(const EFTU_TBU_Type *const pTbu) +{ + + return (uint32_t)(pTbu->CNT2_BASE & EFTU_TBU_CNT2_BASE_BASE_MASK); + +} +/** + * @brief get the TBU_TSx. + */ +LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetChannelTS3(const EFTU_TBU_Type *const pTbu) +{ + return (uint32_t)(pTbu->CNT3_BASE & EFTU_TBU_CNT3_BASE_BASE_MASK); +} +/** + * @brief Set the TBU_TS0 base +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetChannelTS0(EFTU_TBU_Type *const pTbu, uint32 u32TimeValue) +{ + pTbu->CNT0_BASE = (pTbu->CNT0_BASE & ~EFTU_TBU_CNT0_BASE_BASE_MASK)|EFTU_TBU_CNT0_BASE_BASE(u32TimeValue); +} + +/** + * @brief Set the TBU_TS1 base +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetChannelTS1(EFTU_TBU_Type *const pTbu, uint32 u32TimeValue) +{ + pTbu->CNT1_BASE =(pTbu->CNT1_BASE & ~EFTU_TBU_CNT1_BASE_BASE_MASK) | EFTU_TBU_CNT1_BASE_BASE(u32TimeValue); +} +/** + * @brief Set the TBU_TS2 base +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetChannelTS2(EFTU_TBU_Type *const pTbu, uint32 u32TimeValue) +{ + pTbu->CNT2_BASE =(pTbu->CNT2_BASE & ~EFTU_TBU_CNT2_BASE_BASE_MASK)|EFTU_TBU_CNT2_BASE_BASE(u32TimeValue); +} +/** + * @brief Set the TBU_TS3 base +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetChannelTS3(EFTU_TBU_Type *const pTbu, uint32 u32TimeValue) +{ + pTbu->CNT3_BASE = (pTbu->CNT3_BASE & ~EFTU_TBU_CNT3_BASE_BASE_MASK)|EFTU_TBU_CNT3_BASE_BASE(u32TimeValue); +} + +/** + * @brief configure channel 3 mode +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetChannel3Mode(EFTU_TBU_Type *const pTbu, EFTU_TBU_QDModeType eTbuch3Mode) +{ + pTbu->CNT3_CTRL = (pTbu->CNT3_CTRL & ~EFTU_TBU_CNT3_CTRL_CNT_MODE_MASK)|EFTU_TBU_CNT3_CTRL_CNT_MODE(eTbuch3Mode); +} + +/** + * @brief configure channel 3 src for modulo counter +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetChannel3Src(EFTU_TBU_Type *const pTbu, EFTU_TBU_QDInputSrcType eTbuch3CounterSrc) +{ + pTbu->CNT3_CTRL =(pTbu->CNT3_CTRL & ~EFTU_TBU_CNT3_CTRL_USE_CNT2_MASK)|EFTU_TBU_CNT3_CTRL_USE_CNT2(eTbuch3CounterSrc); +} + +/** + * @brief configure channel 3 Modulo value +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetChannel3MARK(EFTU_TBU_Type *const pTbu, uint32 u32mark) +{ + pTbu->CNT3_MARK = (pTbu->CNT3_MARK & ~EFTU_TBU_CNT3_MARK_MARK_MASK)|EFTU_TBU_CNT3_MARK_MARK(u32mark); +} + +/** + * @brief get channel 3 Modulo value +*/ +LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetChannel3MARK(EFTU_TBU_Type *const pTbu) +{ + return (uint32_t)pTbu->CNT3_MARK; +} + +/** + * @brief get channel 3 capture value +*/ +LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetChannel3Capture(EFTU_TBU_Type *const pTbu) +{ + return (uint32_t)pTbu->CNT3_CAPTURE; +} + +#if (EFTU_EAC_SUPPORT == STD_ON) + +/** + * @brief Insert dummy physical tooth for exiting halt mode +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetIph(EFTU_TBU_Type *const pTbu) +{ + pTbu->EAC_TPR |= EFTU_TBU_EAC_TPR_IPH_MASK; +} + +/** + * @brief Force EAC halt +*/ +LOCAL_INLINE void EFTU_TBU_HWA_HoldEac(EFTU_TBU_Type *const pTbu) +{ + pTbu->EAC_TPR |= EFTU_TBU_EAC_TPR_HOLD_MASK; +} + +/** + * @brief Last Tooth Indication +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetLast(EFTU_TBU_Type *const pTbu) +{ + pTbu->EAC_TPR |= EFTU_TBU_EAC_TPR_LAST_MASK; +} + +/** + * @brief Angle Ticks Number in the Current Tooth +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetTicks(EFTU_TBU_Type *const pTbu,uint32 u32Ticks) +{ + pTbu->EAC_TPR |= EFTU_TBU_EAC_TPR_TICKS(u32Ticks); +} + +/** + * @brief Misscnt Tooth Counter +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetMisscnt(EFTU_TBU_Type *const pTbu,uint32 u32MissCnt) +{ + pTbu->EAC_TPR |= EFTU_TBU_EAC_TPR_MISSCNT(u32MissCnt); +} + +/** + * @brief set EAC TRR value +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetTrr(EFTU_TBU_Type *const pTbu,uint32_t u32TrrValue) +{ + pTbu->EAC_TRR = u32TrrValue; +} + + +/** + * @brief The value of the window start is used to determine the start of the + * window for the next tooth +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetStartWin(EFTU_TBU_Type *const pTbu,uint32_t u32StartWin) +{ + pTbu->EAC_WINDOW_S = ((0x1U<<24)|u32StartWin); +} + +/** + * @brief The value of the window start is used to determine the End of the + * window for the next tooth +*/ +LOCAL_INLINE void EFTU_TBU_HWA_SetEndWin(EFTU_TBU_Type *const pTbu,uint32_t u32EndWin) +{ + pTbu->EAC_WINDOW_E = ((0x1U<<24)|u32EndWin); +} + + + +/** + * @brief Set the EAC control register + */ +LOCAL_INLINE void EFTU_TBU_HWA_SetCtrl(EFTU_TBU_Type *const pTbu,uint32_t u32CtrlValue) +{ + pTbu->EAC_CTRL = u32CtrlValue; +} + + +/** + * @brief Clear the counter value to zero + */ +LOCAL_INLINE void EFTU_TBU_HWA_EacSwClearCnt(EFTU_TBU_Type *const pTbu) +{ + pTbu->EAC_CTRL |= EFTU_TBU_EAC_CTRL_CNT_SW_CLR_MASK; +} + +/** + * @brief EAC is halted until a physical tooth is detected + */ +LOCAL_INLINE void EFTU_TBU_HWA_HaltEac(EFTU_TBU_Type *const pTbu) +{ + pTbu->EAC_CTRL |= EFTU_TBU_EAC_CTRL_HALT_ENABLE_MASK; +} + +/** + * @brief Get the last measured time + */ +LOCAL_INLINE uint32 EFTU_TBU_HWA_GetLastMeasTime(EFTU_TBU_Type *const pTbu) +{ + return (uint32_t)(pTbu->EAC_CNTS & 0xFFFFFF ); +} + +/** + * @brief Get the last last measured time + */ +LOCAL_INLINE uint32_t EFTU_TBU_HWA_GetCnt(EFTU_TBU_Type *const pTbu) +{ + return (uint32_t)(pTbu->EAC_CNT & 0xFFFFFF ); +} + +/** + * @brief Get the last last measured time + */ +LOCAL_INLINE uint8_t EFTU_TBU_HWA_GetDetectCounter(EFTU_TBU_Type *const pTbu) +{ + return (uint8_t)((pTbu->EAC_CNTS & EFTU_TBU_EAC_CNTS_CH_CNTS_MASK) >> EFTU_TBU_EAC_CNTS_CH_CNTS_SHIFT) ; +} + +/** + * @brief Set the last last measured time + */ +LOCAL_INLINE void EFTU_TBU_HWA_SetCnts(EFTU_TBU_Type *const pTbu,uint32_t u32CntsValue) +{ + pTbu->EAC_CNTS |= EFTU_TBU_EAC_CNTS_CH_CNTS_WE_SHIFT | EFTU_TBU_EAC_CNTS_CNTS(u32CntsValue); +} + + +/** + * @brief Set the detect counter + */ +LOCAL_INLINE void EFTU_TBU_HWA_SetCntsCounter(EFTU_TBU_Type *const pTbu,uint8_t u8Counter) +{ + pTbu->EAC_CNTS |= EFTU_TBU_EAC_CNTS_CH_CNTS(u8Counter); +} + + +/** + * @brief Enable timeout interrupt + */ +LOCAL_INLINE void EFTU_TBU_HWA_EACEnTimeoutIRQ(EFTU_TBU_Type *const pTbu) +{ + pTbu->EAC_IRQEN |= EFTU_TBU_EAC_IRQEN_TOOTH_TO_IEN_MASK; +} + +/** + * @brief Enable error interrupt + */ +LOCAL_INLINE void EFTU_TBU_HWA_EACEnErrIRQ(EFTU_TBU_Type *const pTbu) +{ + pTbu->EAC_IRQEN |= EFTU_TBU_EAC_IRQEN_TOOTH_ERR_IEN_MASK; +} + +/** + * @brief Enable detect interrupt + */ +LOCAL_INLINE void EFTU_TBU_HWA_EACEnDetIRQ(EFTU_TBU_Type *const pTbu) +{ + pTbu->EAC_IRQEN |= EFTU_TBU_EAC_STAT_TOOTH_DET_MASK; +} + + +/** + * @brief Disable timeout interrupt + */ +LOCAL_INLINE void EFTU_TBU_HWA_EACDisTimeoutIRQ(EFTU_TBU_Type *const pTbu) +{ + pTbu->EAC_IRQEN &= ~EFTU_TBU_EAC_IRQEN_TOOTH_TO_IEN_MASK; +} + +/** + * @brief Disable error interrupt + */ +LOCAL_INLINE void EFTU_TBU_HWA_EACDisErrIRQ(EFTU_TBU_Type *const pTbu) +{ + pTbu->EAC_IRQEN &= ~EFTU_TBU_EAC_IRQEN_TOOTH_ERR_IEN_MASK; +} + +/** + * @brief Disable detect interrupt + */ +LOCAL_INLINE void EFTU_TBU_HWA_EACDisDetIRQ(EFTU_TBU_Type *const pTbu) +{ + pTbu->EAC_IRQEN &= ~EFTU_TBU_EAC_STAT_TOOTH_DET_MASK; +} + +/** + * @brief get interrupt status + */ + +LOCAL_INLINE uint32_t EFTU_TBU_HWA_EacGetIrqflag(EFTU_TBU_Type *const pTbu) +{ + return (uint32_t)pTbu->EAC_STAT; +} + +/** + * @brief get interrupt status + */ + +LOCAL_INLINE void EFTU_TBU_HWA_EacClearIrqflag(EFTU_TBU_Type *const pTbu,uint32_t u32Mask) +{ + pTbu->EAC_STAT = u32Mask; +} + +#endif /* EFTU_EAC_SUPPORT */ + +#endif /* EFTU_INSTANCE_COUNT*/ + +#endif /*#ifndef _HWA_EFTU_TBU_H_*/ diff --git a/Inc/HwA_eftu_tim.h b/Inc/HwA_eftu_tim.h new file mode 100644 index 0000000..6c222ae --- /dev/null +++ b/Inc/HwA_eftu_tim.h @@ -0,0 +1,840 @@ +/** + * @file HwA_eftu_tim.h + * @author flagchip + * @brief Hardware access layer for EFTU TIM + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip099 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_EFTU_TIM_H_ +#define _HWA_EFTU_TIM_H_ +#include "device_header.h" + +#if EFTU_INSTANCE_COUNT > 0U + +/********* Local typedef ************/ +/** + * @get Tim Filter counter Frequency Selection. +*/ +typedef enum +{ + EFTU_TIM_FLT_CMUCLK0 = 0U, + EFTU_TIM_FLT_CMUCLK1 = 1U, + EFTU_TIM_FLT_CMUCLK6 = 2U, + EFTU_TIM_FLT_CMUCLK7 = 3U +}EFTU_TIM_FltSrcType; + +typedef enum +{ + EFTU_TIM_CMU_CLK0 = 0U, + EFTU_TIM_CMU_CLK1 = 1U, + EFTU_TIM_CMU_CLK2 = 2U, + EFTU_TIM_CMU_CLK3 = 3U, + EFTU_TIM_CMU_CLK4 = 4U, + EFTU_TIM_CMU_CLK5 = 5U, + EFTU_TIM_CMU_CLK6 = 6U, + EFTU_TIM_CMU_CLK7 = 7U, +}EFTU_TIM_ClockSrcType; + + +/*Tim Input Timeout EDGE*/ +typedef enum +{ + EFTU_TIM_TIMEOUT_DIS = 0U, + EFTU_TIM_TIMEOUT_RISING_EDGE = 1U, + EFTU_TIM_TIMEOUT_FALLING_EDGE = 2U, + EFTU_TIM_TIMEOUT_BOTH_EDGE = 3U, + +}EFTU_TIM_TimeOutEdgeType; + + +typedef enum +{ + EFTU_TO_CNT2_CLOCK_CMU_CLK = 0U, + EFTU_TO_CNT_CLOCK_SAMPLE_EVT = 1U, +}EFTU_TIM_TduCnt2ClkType; + +typedef enum +{ + EFTU_TO_CNT1_CLOCK_WORD_EVENT = 0U, + EFTU_TO_CNT1_CLOCK_TO_CNT = 1U, +}EFTU_TIM_TduCnt1ClkType; + +typedef enum +{ + EFTU_TDU_24BIT_OR_RESERVED = 0U, + EFTU_TDU_16BIT_8BIT_OR_16BIT = 1U, + EFTU_TDU_3_8BIT_OR_2_8BIT = 2U, + EFTU_TDU_2_8BIT_OR_2_8BIT = 3U +}EFTU_TIM_TduSlicType; + +/** + *@brief TBU0_TS0 select bit +*/ +typedef enum +{ + EFTU_TIM_TBU_TS0_0_23BIT = 0U, + EFTU_TIM_TBU_TS0_3_26BIT = 1U +}EFTU_TIM_TbuTs0ResType; + +typedef enum +{ + EFTU_TIM_ACTIVE_FALLINGEDGE = 0U, + EFTU_TIM_ACTIVE_RISINGEDGE = 1U, + EFTU_TIM_ACTIVE_BOTHEDGE = 2U,/*just for TIEM TIPM mode*/ +}EFTU_TIM_ActiveEdgeType; + +/** + * @get Tim tdu counter timeout sensitive edge. +*/ +typedef enum +{ + EFTU_TIM_TDU_DISABLE = 0U, + EFTU_TIM_TDU_RISING_EDGE = 1U, + EFTU_TIM_TDU_FALLING_EDGE = 2U, + EFTU_TIM_TDU_BOTH_EDGE = 3U +}EFTU_TIM_TduEdgeType; + +/** + * @brief Tim Channel Mode +*/ +typedef enum +{ + EFTU_TIM_MODE_PWMMEASUREMENT = 0U, /**< \brief TPWM */ + EFTU_TIM_MODE_PULSEINTEGRATION = 1U, /**< \brief TPIM */ + EFTU_TIM_MODE_INPUTEVENT = 2U, /**< \brief TIEM */ + EFTU_TIM_MODE_PRESCALER = 3U, /**< \brief TIPM */ + EFTU_TIM_MODE_BITCOMPRESSION = 4U, /**< \brief TBCM */ + EFTU_TIM_MODE_PERIODICSAMPLING = 5U, /**< \brief TGPS */ + EFTU_TIM_MODE_SERIALSHIFT = 6U /**< \brief TSSM */ +}EFTU_TiM_ChannelModeType; + +/** + * @brief GPR0 select mux +*/ +typedef enum +{ + EFTU_TIM_GPTSEL_TBUTS0 = 0U, + EFTU_TIM_GPTSEL_TBUTS1 = 1U, + EFTU_TIM_GPTSEL_TBUTS2 = 2U, + EFTU_TIM_GPTSEL_CNTS_OR_CNT = 3U, /*For GPR0 CNTS;For GPR1 CNT*/ + EFTU_GPTSEL_CH_ECNT = 4U, + EFTU_GPTSEL_TIM_INP_VAL = 5U, +}EFTU_TIM_GprSrcType; + + + +typedef enum +{ + EFTU_TIM_CNTS_CNT = 0U, + EFTU_TIM_CNTS_TBUTS0 = 1u +}EFTU_TIM_CntsSrcType; + + +typedef enum +{ + EFTU_TIM_TPWM_CNTRESET_ACTIVE_EDGE = 0U, + EFTU_TIM_TPWM_CNTRESET_EVERY_EDGE = 1U, +}EFTU_TIM_TpwmCntResType; + +typedef enum +{ + EFTU_TIM_IRQ_NEWVAL = 0X01U, /**< \brief new value irq mode */ + EFTU_TIM_IRQ_ECNTOFL = 0X02U, + EFTU_TIM_IRQ_CNTOFL = 0X04U, + EFTU_TIM_IRQ_GPR0OFL = 0X08U, + EFTU_TIM_IRQ_TODET = 0X10U, /**< \brief Timeout irq mode */ + EFTU_TIM_IRQ_GLITCHDET = 0X20U, +}EFTU_TIM_IrqSrcType; + +typedef enum +{ + EFTU_TIM_LUT_DISABLE = 0u, + EFTU_TIM_LUT_EXT_CAPTURE = 1u, + EFTU_TIM_LUT_FOUT_PREV = 2u, + EFTU_TIM_LUT_TSSM_OUT = 3u, +}EFTU_TIM_LutType; + +/********* Local inline function ************/ +LOCAL_INLINE void EFTU_TIM_HWA_EnIrq( EFTU_TIM_Type *const pTim,EFTU_TIM_IrqSrcType eirq ,uint8_t u8channel) +{ + if(EFTU_TIM_IRQ_NEWVAL == eirq ) + { + pTim->CONTROL[u8channel].CH_IRQ_EN |= EFTU_TIM_CHn_IRQ_EN_NEWVAL_IRQ_EN_MASK; + } + else if (EFTU_TIM_IRQ_ECNTOFL == eirq ) + { + pTim->CONTROL[u8channel].CH_IRQ_EN |= EFTU_TIM_CHn_IRQ_EN_ECNTOFL_IRQ_EN_MASK; + } + else if (EFTU_TIM_IRQ_CNTOFL == eirq ) + { + pTim->CONTROL[u8channel].CH_IRQ_EN |= EFTU_TIM_CHn_IRQ_EN_CNTOFL_IRQ_EN_MASK; + } + else if (EFTU_TIM_IRQ_GPR0OFL == eirq) + { + pTim->CONTROL[u8channel].CH_IRQ_EN |= EFTU_TIM_CHn_IRQ_EN_GPROFL_IRQ_EN_MASK; + } + else if (EFTU_TIM_IRQ_TODET == eirq) + { + pTim->CONTROL[u8channel].CH_IRQ_EN |= EFTU_TIM_CHn_IRQ_EN_TODET_IRQ_EN_MASK; + } + else if (EFTU_TIM_IRQ_GLITCHDET == eirq ) + { + pTim->CONTROL[u8channel].CH_IRQ_EN |=EFTU_TIM_CHn_IRQ_EN_GLITCHDET_IRQ_EN_MASK; + } + else + { + + } +} + +LOCAL_INLINE void EFTU_TIM_HWA_DisIrq( EFTU_TIM_Type *const pTim,EFTU_TIM_IrqSrcType eirq ,uint8_t u8channel) +{ + if(EFTU_TIM_IRQ_NEWVAL == eirq ) + { + pTim->CONTROL[u8channel].CH_IRQ_EN &= ~EFTU_TIM_CHn_IRQ_EN_NEWVAL_IRQ_EN_MASK; + } + else if (EFTU_TIM_IRQ_ECNTOFL == eirq ) + { + pTim->CONTROL[u8channel].CH_IRQ_EN &= ~EFTU_TIM_CHn_IRQ_EN_ECNTOFL_IRQ_EN_MASK; + } + else if (EFTU_TIM_IRQ_CNTOFL == eirq ) + { + pTim->CONTROL[u8channel].CH_IRQ_EN &= ~EFTU_TIM_CHn_IRQ_EN_CNTOFL_IRQ_EN_MASK; + } + else if (EFTU_TIM_IRQ_GPR0OFL == eirq) + { + pTim->CONTROL[u8channel].CH_IRQ_EN &= ~EFTU_TIM_CHn_IRQ_EN_GPROFL_IRQ_EN_MASK; + } + else if (EFTU_TIM_IRQ_TODET == eirq) + { + pTim->CONTROL[u8channel].CH_IRQ_EN &= ~EFTU_TIM_CHn_IRQ_EN_TODET_IRQ_EN_MASK; + } + else if (EFTU_TIM_IRQ_GLITCHDET == eirq ) + { + pTim->CONTROL[u8channel].CH_IRQ_EN &= ~EFTU_TIM_CHn_IRQ_EN_GLITCHDET_IRQ_EN_MASK; + } + else + { + + } +} + +LOCAL_INLINE boolean EFTU_TIM_HWA_GetGlitchEvent(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (pTim->CONTROL[u8channel].CH_IRQ_ST & EFTU_TIM_CHn_IRQ_ST_GLITCHDET_MASK) !=0U; +} + +LOCAL_INLINE boolean EFTU_TIM_HWA_GetTimeOutEvent(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (pTim->CONTROL[u8channel].CH_IRQ_ST & EFTU_TIM_CHn_IRQ_ST_TODET_MASK) !=0U; +} + +LOCAL_INLINE boolean EFTU_TIM_HWA_GetGprOverflowEvent(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (pTim->CONTROL[u8channel].CH_IRQ_ST & EFTU_TIM_CHn_IRQ_ST_GPROFL_MASK) !=0U; +} + +LOCAL_INLINE boolean EFTU_TIM_HWA_GetCntOverflowEvent(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (pTim->CONTROL[u8channel].CH_IRQ_ST & EFTU_TIM_CHn_IRQ_ST_CNTOFL_MASK) !=0U; +} + +LOCAL_INLINE boolean EFTU_TIM_HWA_GetNewValEvent(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (pTim->CONTROL[u8channel].CH_IRQ_ST & EFTU_TIM_CHn_IRQ_ST_NEWVAL_MASK) !=0U; +} + +LOCAL_INLINE boolean EFTU_TIM_HWA_GetEcntEvent(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (pTim->CONTROL[u8channel].CH_IRQ_ST & EFTU_TIM_CHn_IRQ_ST_ECNTOFL_MASK) !=0U; +} + + + +LOCAL_INLINE boolean EFTU_TIM_HWA_GetGlitchIrqEnable(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (pTim->CONTROL[u8channel].CH_IRQ_EN & EFTU_TIM_CHn_IRQ_EN_GLITCHDET_IRQ_EN_MASK) !=0U; +} + +LOCAL_INLINE boolean EFTU_TIM_HWA_GetTimeOutIrqEnable(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (pTim->CONTROL[u8channel].CH_IRQ_EN & EFTU_TIM_CHn_IRQ_EN_TODET_IRQ_EN_MASK) !=0U; +} + +LOCAL_INLINE boolean EFTU_TIM_HWA_GetGprOverflowIrqEnable(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (pTim->CONTROL[u8channel].CH_IRQ_EN & EFTU_TIM_CHn_IRQ_EN_GPROFL_IRQ_EN_MASK) !=0U; +} + +LOCAL_INLINE boolean EFTU_TIM_HWA_GetCntOverflowIrqEnable(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (pTim->CONTROL[u8channel].CH_IRQ_EN & EFTU_TIM_CHn_IRQ_EN_CNTOFL_IRQ_EN_MASK) !=0U; +} + +LOCAL_INLINE boolean EFTU_TIM_HWA_GetNewValIrqEnable(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (pTim->CONTROL[u8channel].CH_IRQ_EN & EFTU_TIM_CHn_IRQ_EN_NEWVAL_IRQ_EN_MASK) !=0U; +} + +LOCAL_INLINE boolean EFTU_TIM_HWA_GetEcntIrqEnable(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (pTim->CONTROL[u8channel].CH_IRQ_EN & EFTU_TIM_CHn_IRQ_EN_ECNTOFL_IRQ_EN_MASK) !=0U; +} + + + + + + +LOCAL_INLINE void EFTU_TIM_HWA_ClearGlitchFlag( EFTU_TIM_Type * pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_IRQ_ST = EFTU_TIM_CHn_IRQ_ST_GLITCHDET_MASK; +} + +LOCAL_INLINE void EFTU_TIM_HWA_ClearTimeOutFlag( EFTU_TIM_Type * pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_IRQ_ST = EFTU_TIM_CHn_IRQ_ST_TODET_MASK; +} + +LOCAL_INLINE void EFTU_TIM_HWA_ClearGprOverflowFlag( EFTU_TIM_Type * pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_IRQ_ST = EFTU_TIM_CHn_IRQ_ST_GPROFL_MASK; +} + +LOCAL_INLINE void EFTU_TIM_HWA_ClearCntOverflowFlag( EFTU_TIM_Type * pTim,uint8_t u8channel) +{ +pTim->CONTROL[u8channel].CH_IRQ_ST = EFTU_TIM_CHn_IRQ_ST_CNTOFL_MASK; +} + +LOCAL_INLINE void EFTU_TIM_HWA_ClearNewValFlag( EFTU_TIM_Type * pTim,uint8_t u8channel) +{ +pTim->CONTROL[u8channel].CH_IRQ_ST = EFTU_TIM_CHn_IRQ_ST_NEWVAL_MASK; +} + +LOCAL_INLINE void EFTU_TIM_HWA_ClearEcntFlag( EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ +pTim->CONTROL[u8channel].CH_IRQ_ST = EFTU_TIM_CHn_IRQ_ST_ECNTOFL_MASK; +} + + +/** + * @get Tim channel x GPR0 value +*/ +LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetChGPR0(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (uint32_t)(pTim->CONTROL[u8channel].CH_GPR0 & EFTU_TIM_CHn_GPR0_GPR0_MASK); +} + +/** + * @get Tim channel x GPR0 Ecnt value +*/ +LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetChGPR0Ecnt(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (uint32_t)((pTim->CONTROL[u8channel].CH_GPR0 & EFTU_TIM_CHn_GPR0_ECNT_MASK)>>EFTU_TIM_CHn_GPR0_ECNT_SHIFT); +} + +/** + * @get Tim channel x GPR1 value +*/ +LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetChGPR1(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (uint32_t)(pTim->CONTROL[u8channel].CH_GPR1 & EFTU_TIM_CHn_GPR1_GPR1_MASK); +} + +/** + * @get Tim channel x Counter value +*/ +LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetChCnt(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (uint32_t)(pTim->CONTROL[u8channel].CH_CNT & EFTU_TIM_CHn_CNT_CNT_MASK); +} + +/** + * @get Tim channel0 Shadow Counter value +*/ +LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetCntsCnt(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (uint32_t)(pTim->CONTROL[u8channel].CH_CNTS & EFTU_TIM_CHn_CNTS_CNTS_MASK); +} + +/** + * @get Tim channel0 edge counter value +*/ +LOCAL_INLINE uint32_t EFTU_TIM_HWA_GetChECnt(const EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + return (uint32_t)(pTim->CONTROL[u8channel].CH_ECNT & EFTU_TIM_CHn_ECNT_ECNT_MASK); +} + + +/*******************FLT relate register *****************/ +/** + * @get Set Value to be fed to Channel x +*/ +LOCAL_INLINE void EFTU_TIM_HWA_SetVal(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + uint8_t u8shift = (uint8_t)(u8channel *4U); + pTim->IN_SRC = (uint32_t)(0x2<IN_SRC =(uint32_t) (0x1<IN_SRC = (uint32_t)(0x8<IN_SRC = (uint32_t)(0x4<CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_CICTRL_MASK; +} + +LOCAL_INLINE void EFTU_TIM_HWA_ClearchCicrl(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_CICTRL_MASK; +} + +/** + * @brief config source for triggering the EXT_CAPTURE functionality + */ +LOCAL_INLINE void EFTU_TIM_HWA_ConfigchExtCapSrc(EFTU_TIM_Type *const pTim,uint8_t u8src,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_ECTRL =(pTim->CONTROL[u8channel].CH_ECTRL & ~EFTU_TIM_CHn_ECTRL_EXT_CAP_SRC_MASK) | EFTU_TIM_CHn_ECTRL_EXT_CAP_SRC(u8src); +} + + +LOCAL_INLINE void EFTU_TIM_HWA_ConfigLut( EFTU_TIM_Type *const pTim,EFTU_TIM_LutType elut ,uint8_t u8channel) +{ + + pTim->CONTROL[u8channel].CH_ECTRL =(pTim->CONTROL[u8channel].CH_ECTRL & ~EFTU_TIM_CHn_ECTRL_USE_LUT_MASK)|EFTU_TIM_CHn_ECTRL_USE_LUT(elut); +} + + +/** + * @brief set Filter counter Src +*/ +LOCAL_INLINE void EFTU_TIM_HWA_SetChFltSrc( EFTU_TIM_Type *const pTim, EFTU_TIM_FltSrcType eFltClkSrc,uint8_t u8channel) +{ + + pTim->CONTROL[u8channel].CH_CTRL =(pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_FLT_CNT_FRQ_MASK) | EFTU_TIM_CHn_CTRL_FLT_CNT_FRQ(eFltClkSrc); +} + +/** + * @brief set channel rising edge number +*/ +LOCAL_INLINE void EFTU_TIM_HWA_SetChFltReValue( EFTU_TIM_Type *const pTim, uint8_t u8Recount,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_FLT_RE = u8Recount; +} + +/** + * @brief set channel fall edge number +*/ +LOCAL_INLINE void EFTU_TIM_HWA_SetChFltFeValue( EFTU_TIM_Type *const pTim, uint8_t u8Fecount,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_FLT_FE = u8Fecount; +} + + +/** + * @brief Enable the Filter mode for rising edge +*/ +LOCAL_INLINE void EFTU_TIM_HWA_EnableChFltRe(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_FLT_MODE_RE_MASK; +} + +/** + * @brief Disable the Filter mode for rising edge +*/ +LOCAL_INLINE void EFTU_TIM_HWA_DisableChFltRe(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_FLT_MODE_RE_MASK; +} + +/** + * @brief Enable the Filter mode for falling edge +*/ +LOCAL_INLINE void EFTU_TIM_HWA_EnableChFltFe(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_FLT_MODE_FE_MASK; +} + +/** + * @brief Disable the Filter mode for falling edge +*/ +LOCAL_INLINE void EFTU_TIM_HWA_DisableChFltFe(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_FLT_MODE_FE_MASK; +} + +/** + * @brief Enable the Filter counter mode for rising edge +*/ +LOCAL_INLINE void EFTU_TIM_HWA_EnableChFltReCounter(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_FLT_CTR_RE_MASK; +} + +/** + * @brief Disable the Filter mode for rising edge +*/ +LOCAL_INLINE void EFTU_TIM_HWA_DisableChFltReCounter(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_FLT_CTR_RE_MASK; +} + +/** + * @brief Enable the Filter counter mode for falling edge +*/ +LOCAL_INLINE void EFTU_TIM_HWA_EnableChFltFeCounter(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_FLT_CTR_FE_MASK; +} + +/** + * @brief Disable the Filter mode for falling edge +*/ +LOCAL_INLINE void EFTU_TIM_HWA_DisableChFltFeCounter(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_FLT_CTR_FE_MASK; +} + +/** + * @brief set extension of bit field FLT_CTR_RE +*/ +LOCAL_INLINE void EFTU_TIM_HWA_EnableChFltReExbit(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_ECTRL |=EFTU_TIM_CHn_ECTRL_EFLT_CTR_RE_MASK; +} + +/** + * @brief Disable extension of bit field FLT_CTR_RE +*/ +LOCAL_INLINE void EFTU_TIM_HWA_DisableChFltReExbit(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_ECTRL &= ~EFTU_TIM_CHn_ECTRL_EFLT_CTR_RE_MASK; +} + +/** + * @brief set extension of bit field FLT_CTR_FE +*/ +LOCAL_INLINE void EFTU_TIM_HWA_EnableChFltFeExbit(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_ECTRL |=EFTU_TIM_CHn_ECTRL_EFLT_CTR_FE_MASK; +} + +/** + * @brief Disable extension of bit field FLT_CTR_FE +*/ +LOCAL_INLINE void EFTU_TIM_HWA_DisableChFltFeExbit(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_ECTRL &= ~EFTU_TIM_CHn_ECTRL_EFLT_CTR_FE_MASK; +} + + +LOCAL_INLINE void EFTU_TIM_HWA_EnableFlt(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_FLT_EN_MASK; +} + +LOCAL_INLINE void EFTU_TIM_HWA_DisableFlt(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_FLT_EN_MASK; +} + +/******************* End FLT relate register *****************/ +/*but ECTRL related register has been changed*/ + +/******************* TDU relate register *****************/ + +/** + * @brief config Tov0 value. +*/ +LOCAL_INLINE void EFTU_TOM_HWA_SetTduTov(EFTU_TIM_Type *const pTim,uint8_t u8Tov0Value, uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_EGV = (pTim->CONTROL[u8channel].CH_EGV & ~EFTU_TIM_CHn_EGV_TOV_MASK)|EFTU_TIM_CHn_EGV_TOV(u8Tov0Value); +} + +/** + * @brief config Tov1 value. +*/ +LOCAL_INLINE void EFTU_TOM_HWA_SetTduTov1(EFTU_TIM_Type *const pTim,uint8_t u8Tov1Value, uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_EGV = (pTim->CONTROL[u8channel].CH_EGV & ~EFTU_TIM_CHn_EGV_TOV1_MASK)|EFTU_TIM_CHn_EGV_TOV1(u8Tov1Value); +} + +/** + * @brief config Tov2 value. +*/ +LOCAL_INLINE void EFTU_TOM_HWA_SetTduTov2(EFTU_TIM_Type *const pTim,uint8_t u8Tov2Value, uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_EGV = (pTim->CONTROL[u8channel].CH_EGV & ~EFTU_TIM_CHn_EGV_TOV2_MASK)|EFTU_TIM_CHn_EGV_TOV2(u8Tov2Value); +} + +LOCAL_INLINE void EFTU_TOM_HWA_SetimeoutValue(EFTU_TIM_Type *const pTim,uint32_t u32TimeoutValue, uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_EGV = (pTim->CONTROL[u8channel].CH_EGV & 0XFF000000)|(u32TimeoutValue & 0xFFFFFF); +} + + +/* + * @brief Config Tdu Clock + * */ +LOCAL_INLINE void EFTU_TIM_HWA_SetTduClk(EFTU_TIM_Type *const pTim,EFTU_TIM_ClockSrcType eClk,uint8_t u8channel) +{ + + pTim->CONTROL[u8channel].CH_EGV =(pTim->CONTROL[u8channel].CH_EGV & ~EFTU_TIM_CHn_EGV_TCS_MASK)|EFTU_TIM_CHn_EGV_TCS(eClk); +} + +LOCAL_INLINE void EFTU_TIM_HWA_SetTimeoutEdge(EFTU_TIM_Type *const pTim,EFTU_TIM_TimeOutEdgeType pTimeOutSensitiveEgde, uint8_t u8channel) +{ + + pTim->CONTROL[u8channel].CH_CTRL =(pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_TOCTRL_MASK)| EFTU_TIM_CHn_CTRL_TOCTRL(pTimeOutSensitiveEgde); +} + + + +LOCAL_INLINE void EFTU_TIM_HWA_ConfigTduCnt2Clk(EFTU_TIM_Type *const pTim,EFTU_TIM_TduCnt2ClkType eClk,uint8_t u8channel) +{ + if(EFTU_TO_CNT2_CLOCK_CMU_CLK == eClk) + { + pTim->CONTROL[u8channel].CH_EGV &= ~EFTU_TIM_CHn_EGV_TCS_USE_SAMPLE_EVT_MASK; + } + else + { + pTim->CONTROL[u8channel].CH_EGV |= EFTU_TIM_CHn_EGV_TCS_USE_SAMPLE_EVT_MASK; + } +} + + + +LOCAL_INLINE void EFTU_TIM_HWA_ConfigTduCnt1Clk(EFTU_TIM_Type *const pTim,EFTU_TIM_TduCnt1ClkType eClk,uint8_t u8channel) +{ + + if(EFTU_TO_CNT1_CLOCK_WORD_EVENT == eClk) + { + pTim->CONTROL[u8channel].CH_EGV &= ~EFTU_TIM_CHn_EGV_EG_SAME_CNT_CLK_MASK; + } + else + { + pTim->CONTROL[u8channel].CH_EGV |= EFTU_TIM_CHn_EGV_EG_SAME_CNT_CLK_MASK; + } +} + +/** + * @brief confg tdu slic mode +*/ +LOCAL_INLINE void EFTU_TIM_HWA_SetTduSlicing(EFTU_TIM_Type *const pTim,EFTU_TIM_TduSlicType eSlic,uint8_t u8channel) +{ + + pTim->CONTROL[u8channel].CH_EGV = (pTim->CONTROL[u8channel].CH_EGV & ~EFTU_TIM_CHn_EGV_SLICING_MASK)| EFTU_TIM_CHn_EGV_SLICING(eSlic); +} + +/******************* End TDU relate register *****************/ + + + +/**********channel related register*************/ +LOCAL_INLINE void EFTU_TIM_HWA_SetChannelMode(EFTU_TIM_Type *const pTim,EFTU_TiM_ChannelModeType pTimMode,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL = (pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_TIM_MODE_MASK)|EFTU_TIM_CHn_CTRL_TIM_MODE(pTimMode); +} + + +LOCAL_INLINE void EFTU_TIM_HWA_SetChannelClockSrc(EFTU_TIM_Type *const pTim,EFTU_TIM_ClockSrcType pTimSrc,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL = (pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_CLK_SEL_MASK) | EFTU_TIM_CHn_CTRL_CLK_SEL(pTimSrc); +} + +LOCAL_INLINE void EFTU_TIM_HWA_EnableChannel(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_TIM_EN_MASK; +} + +LOCAL_INLINE void EFTU_TIM_HWA_DisableChannel(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_TIM_EN_MASK; +} + +LOCAL_INLINE void EFTU_TIM_HWA_SetGPR0Sel(EFTU_TIM_Type *const pTim,EFTU_TIM_GprSrcType pTimGprser,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL = (pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_GPR0_SEL_MASK)|EFTU_TIM_CHn_CTRL_GPR0_SEL(pTimGprser); +} + +LOCAL_INLINE void EFTU_TIM_HWA_SetGPR1Sel(EFTU_TIM_Type *const pTim,EFTU_TIM_GprSrcType pTimGprsel,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CTRL = (pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_GPR1_SEL_MASK) | EFTU_TIM_CHn_CTRL_GPR1_SEL(pTimGprsel); +} + +LOCAL_INLINE void EFTU_TIM_HWA_SetCntsSel(EFTU_TIM_Type *const pTim,EFTU_TIM_CntsSrcType pTimCntssel,uint8_t u8channel) +{ + + pTim->CONTROL[u8channel].CH_CTRL = (pTim->CONTROL[u8channel].CH_CTRL & ~ EFTU_TIM_CHn_CTRL_CNTS_SEL_MASK)|EFTU_TIM_CHn_CTRL_CNTS_SEL(pTimCntssel); +} + +LOCAL_INLINE void EFTU_TIM_HWA_SetTbu0BitFiled(EFTU_TIM_Type *const pTim,EFTU_TIM_TbuTs0ResType eTbu0Ts0,uint8_t u8channel) +{ + + pTim->CONTROL[u8channel].CH_CTRL =(pTim->CONTROL[u8channel].CH_CTRL & ~EFTU_TIM_CHn_CTRL_TBU0_SEL_MASK) | EFTU_TIM_CHn_CTRL_TBU0_SEL(eTbu0Ts0); +} + + +LOCAL_INLINE void EFTU_TIM_HWA_EnableExtCapture(EFTU_TIM_Type *const pTim,boolean bEn,uint8_t u8channel) +{ + if(TRUE == bEn) + { + pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_EXT_CAP_EN_MASK; + } + else + { + pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_EXT_CAP_EN_MASK; + } +} + +LOCAL_INLINE void EFTU_TIM_HWA_EnableSwCaputure(EFTU_TIM_Type *const pTim,boolean bEn,uint8_t u8channel) +{ + if(TRUE == bEn) + { + pTim->CONTROL[u8channel].CH_ECTRL |= EFTU_TIM_CHn_ECTRL_SWAP_CAPTURE_MASK; + } + else + { + pTim->CONTROL[u8channel].CH_ECTRL &= ~EFTU_TIM_CHn_ECTRL_SWAP_CAPTURE_MASK; + } +} + + +LOCAL_INLINE void EFTU_TIM_HWA_ConfigActiveEdge(EFTU_TIM_Type *const pTim,EFTU_TIM_ActiveEdgeType eEdge ,uint8_t u8channel) +{ + if(EFTU_TIM_ACTIVE_RISINGEDGE== eEdge) + { + pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_DSL_MASK; + } + else + { + pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_DSL_MASK; + } +} + + + +LOCAL_INLINE void EFTU_TIM_HWA_ConfigTpwmCntmode(EFTU_TIM_Type *const pTim,EFTU_TIM_TpwmCntResType eResType ,uint8_t u8channel) +{ + + if(EFTU_TIM_TPWM_CNTRESET_EVERY_EDGE == eResType) + { + pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_ECNT_RESET_MASK; + } + else + { + pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_ECNT_RESET_MASK; + } +} + +LOCAL_INLINE void EFTU_TIM_HWA_EnIngnoreEdge(EFTU_TIM_Type *const pTim,boolean bEn,uint8_t u8channel) +{ + if(TRUE == bEn) + { + pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_ISL_MASK; + } + else + { + pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_ISL_MASK; + } +} + + +LOCAL_INLINE void EFTU_TIM_HWA_EnableImmStart(EFTU_TIM_Type *const pTim,boolean bEnable,uint8_t u8channel) +{ + if(TRUE == bEnable) + { + pTim->CONTROL[u8channel].CH_ECTRL |=EFTU_TIM_CHn_ECTRL_IMM_START_MASK; + } + else + { + pTim->CONTROL[u8channel].CH_ECTRL &= ~EFTU_TIM_CHn_ECTRL_IMM_START_MASK; + } +} + +LOCAL_INLINE void EFTU_TIM_HWA_SetCntsValue(EFTU_TIM_Type *const pTim,uint32 value,uint8_t u8channel) +{ + pTim->CONTROL[u8channel].CH_CNTS = value; +} + + +LOCAL_INLINE void EFTU_TIM_HWA_TssmEnshiftRight(EFTU_TIM_Type *const pTim,boolean bShiftRight ,uint8_t u8channel) +{ + if(TRUE== bShiftRight) + { + pTim->CONTROL[u8channel].CH_CTRL |= EFTU_TIM_CHn_CTRL_DSL_MASK; + } + else + { + pTim->CONTROL[u8channel].CH_CTRL &= ~EFTU_TIM_CHn_CTRL_DSL_MASK; + } +} + +LOCAL_INLINE void EFTU_TIM_HWA_UnLock(EFTU_TIM_Type *const pTim) +{ + pTim->TIM_SPEC_LOCK = 0xBEEFCAFE; +} + +LOCAL_INLINE void EFTU_TIM_HWA_Lock(EFTU_TIM_Type *const pTim) +{ + pTim->TIM_SPEC_LOCK = 0x5AFECAFE; +} + +LOCAL_INLINE void EFTU_TIM_HWA_ResetChannel(EFTU_TIM_Type *const pTim,uint8_t u8channel) +{ + pTim->RST |= 0x1U<INP_VAL); +} + + +#endif + +#endif /*#ifndef _HWA_EFTU_TIM_H_*/ diff --git a/Inc/HwA_eftu_tom.h b/Inc/HwA_eftu_tom.h new file mode 100644 index 0000000..ed992d1 --- /dev/null +++ b/Inc/HwA_eftu_tom.h @@ -0,0 +1,1161 @@ +/** + * @file HwA_eftu_tom.h + * @author flagchip + * @brief Hardware access layer for EFTU TOM + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip099 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_EFTU_TOM_H_ +#define _HWA_EFTU_TOM_H_ +#include "device_header.h" + +#if defined(EFTU_INSTANCE_COUNT) && (EFTU_INSTANCE_COUNT > 0U) + +/** + * @defgroup HwA_eftu_tom HwA_eftu_tom + * @ingroup module_driver_eftu_tom + * @{ + */ + +/** + * @brief Selection of Time Base Used for Comparison + * + */ +typedef enum +{ + EFTU_TOM_TBU_SEL_TS0 = 0u, /* TBU_TS0 selected */ + EFTU_TOM_TBU_SEL_TS1 = 1u, /* TBU_TS1 selected */ + EFTU_TOM_TBU_SEL_TS2 = 2u /* TBU_TS2 selected */ +} EFTU_TOM_TimeBaseSelectionType; + +/** + * @brief TOM Channel Mode Select + * + */ +typedef enum +{ + EFTU_TOM_CHANNEL_MODE_IMMEDIATE = 0u, + EFTU_TOM_CHANNEL_MODE_COMPARE = 1u, + EFTU_TOM_CHANNEL_MODE_PWM = 2u, + EFTU_TOM_CHANNEL_MODE_SERIAL = 3u, + EFTU_TOM_CHANNEL_MODE_BUFFERD_COMPARE = 4u, +} EFTU_TOM_ChannelModeType; + +/** + * @brief Initial Signal Level + * + */ +typedef enum +{ + EFTU_TOM_SIGNAL_LEVEL_LOW = 0u, /* Low signal level */ + EFTU_TOM_SIGNAL_LEVEL_HIGH = 1u /* High signal level */ +} EFTU_TOM_SignalLevelType; + +/** + * @brief Enumeration for Trigger Pulse Types + * + */ +typedef enum +{ + EFTU_TOM_TRIG_PULSE_SUSTAINED = 0u, /* Output on TOM_OUT_T is '1' as long as CN0=SR0 */ + EFTU_TOM_TRIG_PULSE_ONE_CLUSTER_CLK = 1u, /* Output on TOM_OUT_T is '1' for only one cluster clock period if CN0=SR0 */ +} EFTU_TOM_TriggerPulseType; + +/** + * @brief Up/down Counter Mode + * + * This enumeration type EFTU_TOM_UpDownModeType defines the different up-down counting modes for the EFTU counter. + * Each value represents a specific counting update condition, including counting only upwards, counting both up and down, and specific update conditions. + */ +typedef enum +{ + EFTU_TOM_UP_MODE = 0u, /* up/down counter mode disabled: CN0 counts always up */ + EFTU_TOM_UP_DOWN_MODE_UPDATE_CN0_REACH_0 = 1u, /* up/down counter mode enabled: CN0 counts up and down, + CM0, CM1, CTRL[SL] and CTRL[CLK_SRC] are updated if CN0 is 0 (i.e. + the counting direction changes from down to up). */ + EFTU_TOM_UP_DOWN_MODE_UPDATE_CN0_REACH_CM0 = 2u, /* up/down counter mode enabled: CN0 counts up and down, + CM0, CM1, CTRL[SL] and CTRL[CLK_SRC] are updated if CN0 reaches + CM0-1 or the channel receives the trigger signal and the counting + direction changes from up to down */ + EFTU_TOM_UP_DOWN_MODE_UPDATE_CN0_REACH_0_OR_CM0 = 3u, /* up/down counter mode enabled: CN0 counts up and down, + CM0, CM1, CTRL[SL] and CTRL[CLK_SRC] are updated if CN0 is 0 or + reaches CM0-1 or the channel receives the trigger signal and the + counting direction changes from up to down*/ +} EFTU_TOM_UpDownModeType; + +/** + * @brief Reset Source of CCU0 + * + */ +typedef enum +{ + EFTU_TOM_RESET_CN0_ON_MATCHING_CM0 = 0u, /* Reset counter register CN0 to 0 on matching comparison with + CM0 */ + EFTU_TOM_RESET_CN0_ON_TRIGGER = 1u, /* Reset counter register CN0 to 0 when has trigger in + (internal/external) */ +} EFTU_TOM_CCO0ResetSourceType; + +/** + * @brief Select time base value from TBU_CNT1 and TBU_CNT2. + * + */ +typedef enum +{ + EFTU_TOM_SEL_TBU_TS1 = 0u, /* TBU_CNT1 selected */ + EFTU_TOM_SEL_TBU_TS2 = 1u, /* TBU_CNT2 selected */ +} EFTU_TOM_TBValueSelectionType; + +/** + * @brief Trigger output selection (output signal TOM_CH_TRIGOUT) of TOMchannel N + * + */ +typedef enum +{ + EFTU_TOM_TRIG_OUT_BYPASS_TRIG_IN = 0U, /* Bypass trigger in (from the preceding channel, selected by + TRIG_OUT_USE_EXT) to trigger out (to following channel) */ + EFTU_TOM_TRIG_OUT_USE_TRIG_CCU0, /* Use TRIG_CCU0 (generated by the current channel) to trigger out + (to following channel) */ +} EFTU_TOM_TrigOutSelectionType; + +/** + * @brief Trigger request signal + * @note This field is controlled by EFTU_TOM_TGC_SPEC_LOCK. + * + * Trigger request signal (see TGC) to update the register + * TGC_ENDIS_STAT and TGC_OUTEN_STAT, and trigger a force update + * when enable force update. + * + * @param pTOM Pointer to the base address of the EFTU_TOM type, used to access hardware registers + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetHostTriggerRequest(EFTU_TOM_Type * const pTOM) +{ + pTOM->TGC_GLB_CTRL |= EFTU_TOM_TGC_GLB_CTRL_HOST_TRIG_MASK; +} + +/** + * @brief Disable the global time base + * @note This field is controlled by EFTU_TOM_TGC_SPEC_LOCK. + * + * @param pTOM Base address pointer to the EFTU_TOM module, used to access the module's registers + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableGlobalTimeBase(EFTU_TOM_Type * const pTOM) +{ + pTOM->TGC_GLB_CTRL |= EFTU_TOM_TGC_GLB_CTRL_GLBEN_BYPASS_MASK; +} + +/** + * @brief Enable the global time base + * @note This field is controlled by EFTU_TOM_TGC_SPEC_LOCK. + * + * @param pTOM Base address pointer to the EFTU_TOM module, used to access the module's registers + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableGlobalTimeBase(EFTU_TOM_Type * const pTOM) +{ + pTOM->TGC_GLB_CTRL &= ~(uint32_t)EFTU_TOM_TGC_GLB_CTRL_GLBEN_BYPASS_MASK; +} + +/** + * @brief Reset specific channels of the EFTU TOM module + * + * This function is used to reset specific channels within the EFTU TOM module. + * It performs the reset operation by setting the corresponding bits in the TGC_GLB_CTRL register + * according to the provided channel mask. + * + * @param pTOM Pointer to the EFTU TOM module type structure, which should point to the memory-mapped address of the TOM module + * @param u8ChannelMask Channel mask, used to specify which channels need to be reset. Each bit in the mask corresponds to a channel. + */ +LOCAL_INLINE void EFTU_TOM_HWA_ResetChannel(EFTU_TOM_Type * const pTOM, uint8_t u8ChannelMask) +{ + pTOM->TGC_GLB_CTRL |= EFTU_TOM_TGC_GLB_CTRL_RST_CH(u8ChannelMask); +} + +/** + * @brief Enable EFTU TOM Channel Update + * + * Enable TOM Channel update of registers CM0, CM1, CTRL[SL] and CTRL[CLK_SRC], SR0, SR1, CTRL_SR[SL_SR] and + * CTRL_SR[CLK_SRC_SR]. + * + * @param pTOM Pointer to the base address of the EFTU TOM module, used to access registers + * @param u8Channel The channel number to enable for updates + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableChannelUpdate(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_GLB_CTRL = (pTOM->TGC_GLB_CTRL & (~(((uint32_t)EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL0_MASK) << ((uint32_t)u8Channel << 1U)))) + | ((uint32_t)EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL0(2u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * @brief Disable EFTU TOM Channel Update + * + * Disable TOM Channel update of registers CM0, CM1, CTRL[SL] and CTRL[CLK_SRC], SR0, SR1, CTRL_SR[SL_SR] and + * CTRL_SR[CLK_SRC_SR]. + * + * @param pTOM Pointer to the base address of the EFTU TOM module, used to access registers + * @param u8Channel The channel number to enable for updates + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableChannelUpdate(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_GLB_CTRL = (pTOM->TGC_GLB_CTRL & (~(((uint32_t)EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL0_MASK) << ((uint32_t)u8Channel << 1U)))) + | ((uint32_t)EFTU_TOM_TGC_GLB_CTRL_UPEN_CTRL0(1u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * @brief Get the value of the TGC global control register + * + * @param pTOM Pointer to the EFTU_TOM module, which contains the global control register + * @return uint32_t The current value of the TGC global control register + */ +LOCAL_INLINE uint32_t EFTU_TOM_HWA_GetGlobalControl(EFTU_TOM_Type * const pTOM) +{ + return pTOM->TGC_GLB_CTRL; +} + +/** + * @brief Set the value of the TGC global control register + * + * @param pTOM Base address pointer to the EFTU TOM module, used to access the module's registers + * @param u32Value Value to be written to the global control register, used to configure the module + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetGlobalControl(EFTU_TOM_Type * const pTOM, uint32_t u32Value) +{ + pTOM->TGC_GLB_CTRL = u32Value; +} + +/** + * Enable channel on an update trigger + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral to access its registers. + * @param u8Channel The channel number to enable. + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableChannelOnUpdateTrig(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_ENDIS_CTRL = (pTOM->TGC_ENDIS_CTRL & (~((uint32_t)EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL0_MASK << ((uint32_t)u8Channel << 1U)))) + | ((uint32_t)EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL0(2u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * Disable channel on an update trigger + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral to access its registers. + * @param u8Channel The channel number to disable. + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableChannelOnUpdateTrig(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_ENDIS_CTRL = (pTOM->TGC_ENDIS_CTRL & (~((uint32_t)EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL0_MASK << ((uint32_t)u8Channel << 1U)))) + | ((uint32_t)EFTU_TOM_TGC_ENDIS_CTRL_ENDIS_CTRL0(1u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * Enable channel + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral to access its registers. + * @param u8Channel The channel number to enable. + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableChannel(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_ENDIS_STAT = (pTOM->TGC_ENDIS_STAT & (~((uint32_t)EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT0_MASK << ((uint32_t)u8Channel << 1U)))) + | ((uint32_t)EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT0(2u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * Disable channel + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral to access its registers. + * @param u8Channel The channel number to disable. + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableChannel(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_ENDIS_STAT = (pTOM->TGC_ENDIS_STAT & (~((uint32_t)EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT0_MASK << ((uint32_t)u8Channel << 1U)))) + | ((uint32_t)EFTU_TOM_TGC_ENDIS_STAT_ENDIS_STAT0(1u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * Set the action Time Base value + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral to access its registers. + * @param u8Channel The time base value to be set + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetTimeBaseValue(EFTU_TOM_Type * const pTOM, uint32_t u32Value) +{ + pTOM->TGC_ACT_TB = (pTOM->TGC_ACT_TB & ~EFTU_TOM_TGC_ACT_TB_ACT_TB_MASK) | (u32Value & EFTU_TOM_TGC_ACT_TB_ACT_TB_MASK); +} + +/** + * Set time base trigger request + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral to access its registers. + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetTimeBaseTrigger(EFTU_TOM_Type * const pTOM) +{ + pTOM->TGC_ACT_TB |= EFTU_TOM_TGC_ACT_TB_TB_TRIG_MASK; +} + +/** + * @brief Selects the time base for Comparison + * + * @param pTOM Base address pointer of the EFTU TOM module, used to access the module's registers + * @param eSelection The selection value for the time base, determining which time base to use + */ +LOCAL_INLINE void EFTU_TOM_HWA_SelectTimeBase(EFTU_TOM_Type * const pTOM, EFTU_TOM_TimeBaseSelectionType eSelection) +{ + pTOM->TGC_ACT_TB = (pTOM->TGC_ACT_TB & ~EFTU_TOM_TGC_ACT_TB_TBU_SEL_MASK) | EFTU_TOM_TGC_ACT_TB_TBU_SEL(eSelection); +} + +/** + * Enable the output of an EFTU_TOM channel on update trigger. + * + * @param pTOM Pointer to the base address of the EFTU_TOM module, used to access the module's registers. + * @param u8Channel The channel number to enable output. + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableChannelOutputOnUpdateTrig(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_OUTEN_CTRL = (pTOM->TGC_OUTEN_CTRL & (~(((uint32_t)EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL0_MASK) << ((uint32_t)u8Channel << 1U)))) + | (EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL0(2u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * Disable the output of an EFTU_TOM channel on update trigger. + * + * @param pTOM Pointer to the base address of the EFTU_TOM module, used to access the module's registers. + * @param u8Channel The channel number to disable output. + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableChannelOutputOnUpdateTrig(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_OUTEN_CTRL = (pTOM->TGC_OUTEN_CTRL & (~(((uint32_t)EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL0_MASK) << ((uint32_t)u8Channel << 1U)))) + | (EFTU_TOM_TGC_OUTEN_CTRL_OUTEN_CTRL0(1u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * Enable the output of an EFTU_TOM channel. + * + * @param pTOM Pointer to the base address of the EFTU_TOM module, used to access the module's registers. + * @param u8Channel The channel number to enable output. + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableChannelOutput(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_OUTEN_STAT = (pTOM->TGC_OUTEN_STAT & (~(((uint32_t)EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT0_MASK) << ((uint32_t)u8Channel << 1U)))) + | (EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT0(2u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * Disable the output of an EFTU_TOM channel. + * + * @param pTOM Pointer to the base address of the EFTU_TOM module, used to access the module's registers. + * @param u8Channel The channel number to enable output. + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableChannelOutput(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_OUTEN_STAT = (pTOM->TGC_OUTEN_STAT & (~(((uint32_t)EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT0_MASK) << ((uint32_t)u8Channel << 1U)))) + | (EFTU_TOM_TGC_OUTEN_STAT_OUTEN_STAT0(1u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * Enable the force update of an EFTU_TOM channel. + * + * @param pTOM Pointer to the base address of the EFTU_TOM module, used to access the module's registers. + * @param u8Channel The channel number to enable force update. + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableForceUpdate(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_FUPD_CTRL = (pTOM->TGC_FUPD_CTRL & (~(((uint32_t)EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL0_MASK) << ((uint32_t)u8Channel << 1U)))) + | (EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL0(2u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * Disable the force update of an EFTU_TOM channel. + * + * @param pTOM Pointer to the base address of the EFTU_TOM module, used to access the module's registers. + * @param u8Channel The channel number to disable force update. + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableForceUpdate(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_FUPD_CTRL = (pTOM->TGC_FUPD_CTRL & (~(((uint32_t)EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL0_MASK) << ((uint32_t)u8Channel << 1U)))) + | (EFTU_TOM_TGC_FUPD_CTRL_FUPD_CTRL0(1u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * Enable the reset CN0 of channel n on force update event + * + * @param pTOM Pointer to the base address of the EFTU_TOM module, used to access the module's registers. + * @param u8Channel The channel number to enable the reset CN0 on force update event. + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableForceUpdateResetCN0(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_FUPD_CTRL = (pTOM->TGC_FUPD_CTRL & (~(((uint32_t)EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH0_MASK) << ((uint32_t)u8Channel << 1U)))) + | (EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH0(2u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * Disable the reset CN0 of channel n on force update event + * + * @param pTOM Pointer to the base address of the EFTU_TOM module, used to access the module's registers. + * @param u8Channel The channel number to disable the reset CN0 on force update event. + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableForceUpdateResetCN0(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_FUPD_CTRL = (pTOM->TGC_FUPD_CTRL & (~(((uint32_t)EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH0_MASK) << ((uint32_t)u8Channel << 1U)))) + | (EFTU_TOM_TGC_FUPD_CTRL_RSTCN0_CH0(1u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * @brief Enable the input signal TOM_CH_TRIGOUT as a trigger source + * + * @param pTOM Base address pointer to the EFTU_TOM module, used to access the module's registers + * @param u8Channel Channel number of the EFTU_TOM module, specifying which channel to configure + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableInternalTrigger(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_INT_TRIG = (pTOM->TGC_INT_TRIG & (~(((uint32_t)EFTU_TOM_TGC_INT_TRIG_INT_TRIG0_MASK) << ((uint32_t)u8Channel << 1U)))) + | (EFTU_TOM_TGC_INT_TRIG_INT_TRIG0(2u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * @brief Disable the input signal TOM_CH_TRIGOUT as a trigger source + * + * @param pTOM Base address pointer to the EFTU_TOM module, used to access the module's registers + * @param u8Channel Channel number of the EFTU_TOM module, specifying which channel to configure + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableInternalTrigger(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->TGC_INT_TRIG = (pTOM->TGC_INT_TRIG & (~(((uint32_t)EFTU_TOM_TGC_INT_TRIG_INT_TRIG0_MASK) << ((uint32_t)u8Channel << 1U)))) + | (EFTU_TOM_TGC_INT_TRIG_INT_TRIG0(1u) << ((uint32_t)u8Channel << 1U)); +} + +/** + * @brief Lock the special lock in the EFTU TOM module + * + * @param pTOM Pointer to the base address of the EFTU TOM module, used to access registers within the module. + */ +LOCAL_INLINE void EFTU_TOM_HWA_LockSpecialLock(EFTU_TOM_Type * const pTOM) +{ + pTOM->TGC_SPEC_LOCK = 0x5AFECAFEu; +} + +/** + * @brief Unlock the special lock in the EFTU TOM module + * + * @param pTOM Pointer to the base address of the EFTU TOM module, used to access registers within the module. + */ +LOCAL_INLINE void EFTU_TOM_HWA_UnlockSpecialLock(EFTU_TOM_Type * const pTOM) +{ + pTOM->TGC_SPEC_LOCK = 0xBEEFCAFEu; +} + +/** + * @brief Set the channel mode for EFTU TOM + * + * @param pTOM Pointer to the base address of the EFTU TOM module, used to access the module's registers + * @param u8Channel The channel number to set the mode for + * @param eChannelMode The new channel mode, which is an enumerated type defining the different modes the channel can operate in + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetChannelMode(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, EFTU_TOM_ChannelModeType eChannelMode) +{ + pTOM->Channel[u8Channel].CH_CTRL = (pTOM->Channel[u8Channel].CH_CTRL & (~(uint32_t)EFTU_TOM_CHn_CTRL_MODE_MASK)) + | EFTU_TOM_CHn_CTRL_MODE(eChannelMode); +} + +/** + * @brief Set the TOM channel control mode + * + * @param pTOM Pointer to the base address of the EFTU TOM module, used to access the module's registers + * @param u8Channel The channel number to set the mode for + * @param u8TomModeCtrl TOM mode control value + * SOMI Mode: + * TMCB[0]: + * 0b - Set output to the inverse value of CTRL[SL] + * 1b - Set output to CTRL[SL] + * TMCB[4:1]: Reserved + * SOMC Mode: + * TMCB[1:0]: Signal level control + * 00b - No signal level change at output (exception TMCB[4:2] = 0b001) + * 01b - Set output signal level to 1 when CTRL[SL] = 0 else output + * signal level to 0 (exception TMCB[4 :2] = 0b001). + * 10b - Set output signal level to 0 when CTRL[SL] = 0 else output + * signal level to 1 (exception TMCB[4 :2] = 0b001) + * 11b - Toggle output signal level (exception TMCB[4:2] = 0b001) + * TMCB[4:2]: Compare strategy + * 000b - Compare in CCU0 and CCU1 in parallel, disable the CCUx on a + * compare match on either of compare units. Use TBU_CNT0 in CCU0 + * and TBU_CNT1 or TBU_CNT2 in CCU1. + * 001b - Compare in CCU0 and CCU1 in parallel, disable the + * CCU0/CCU1 on a compare match on either compare units. Use + * TBU_CNT0 in CCU0 and TBU_CNT1 or TBU_CNT2 in CCU1. + * 010b - Compare in CCU0 only against TBU_CNT0. + * 011b - Compare in CCU1 only against TBU_CNT1 or TBU_CNT2. + * 100b - Compare first in CCU0 and then in CCU1. Use TBU_CNT0. + * 101b - Compare first in CCU0 and then in CCU1. Use TBU_CNT1 or + * TBU_CNT2. + * 110b - Compare first in CCU0 and then in CCU1. Use TBU_CNT0 in + * CCU0 and TBU_CNT1 or TBU_CNT2 in CCU1. + * 111b - Cancel pending compare events. + * SOMP Mode + * TMCB[1:0]: Reserved + * TMCB[2]: PCM mode enable (only able with odd channel and UDMODE == 0 ) + * 0b - disabled + * 1b - enabled + * TMCB[3]: SR0_TRIG, SR0 used for TOM_OUT_T (need RST_CCU0 == 0) + * 0b - SR0 is used as a shadow register for register CM0. + * 1b - SR0 is not used as a shadow register for register CM0. SR0 is + * compared with CN0 and if both are equal, a trigger pulse is generated + * at output TOM_OUT_T + * TMCB[4]: Reserved + * SOMS Mode + * TMCB[0]: Shift direction + * 0b - Right shift of data is started from bit CM1[0]. + * 1b - Left shift of data is started from bit CM1[23]. + * TMCB[2:1]: Reserved + * TMCB[3]: Double shift output + * 0b - CM1 is used as a 24-bit shift register. + * 1b - CM1 is split into two 12-bit shift register. + * TMCB[4]: Reserved + * SOMB Mode + * TMCB[1:0]: Signal level control + * 00b - No signal level change at output . + * 01b - Set output signal level to 1 when CTRL[SL] = 0 else output + * signal level to 0. + * 10b - Set output signal level to 0 when CTRL[SL] = 0 else output + * signal level to 1. + * 11b - Toggle output signal level + * TMCB[4:2]: Compare strategy + * 000b - Reserved. Has no effect. + * 001b - Reserved. Has no effect. + * 010b - Compare in CCU0 only against TBU_CNT0. + * 011b - Compare in CCU1 only against TBU_CNT1 or TBU_CNT2. + * 100b - Compare first in CCU0 and then in CCU1. Use TBU_CNT0. + * 101b - Compare first in CCU0 and then in CCU1. Use TBU_CNT1 or + * TBU_CNT2. + * 110b - Compare first in CCU0 and then in CCU1. Use TBU_CNT0 in + * CCU0 and TBU_CNT1 or TBU_CNT2 in CCU1. + * 111b - Cancel pending comparisons + * + * + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetTomModeCtrl(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, uint8_t u8TomModeCtrl) +{ + pTOM->Channel[u8Channel].CH_CTRL = (pTOM->Channel[u8Channel].CH_CTRL & (~(uint32_t)EFTU_TOM_CHn_CTRL_TMCB_MASK)) + | EFTU_TOM_CHn_CTRL_TMCB(u8TomModeCtrl); +} + +/** + * @brief Enable Extended Update Mode + * + * SOMI Mode: Reserved + * SOMC Mode + * 0b - No extended update of CM0 and CM1 via AFCB + * 1b - Extended update mode in case of compare strategy 'serve last': + * CM1 after CCU0 compare match possible via AFCB. + * SOMP Mode: Reserved + * SOMS Mode: Reserved + * SOMB Mode + * 0b - No extended update of CM0 and CM1 via AFCB + * 1b - Extended update mode in case of compare strategy 'serve last': + * CM1 after CCU0 compare match possible via AFCB. + * @param pTOM Pointer to the EFTU_TOM module, used to access the module's registers + * @param u8Channel The channel number to configure, specifying which channel to enable the extended update mode for + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableExtendUpdateMode(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_CTRL |= EFTU_TOM_CHn_CTRL_EUPM_MASK; +} + +/** + * @brief Disable Extended Update Mode + * + * SOMI Mode: Reserved + * SOMC Mode + * 0b - No extended update of CM0 and CM1 via AFCB + * 1b - Extended update mode in case of compare strategy 'serve last': + * CM1 after CCU0 compare match possible via AFCB. + * SOMP Mode: Reserved + * SOMS Mode: Reserved + * SOMB Mode + * 0b - No extended update of CM0 and CM1 via AFCB + * 1b - Extended update mode in case of compare strategy 'serve last': + * CM1 after CCU0 compare match possible via AFCB. + * + * @param pTOM Pointer to the EFTU_TOM module, used to access the module's registers + * @param u8Channel The channel number to configure, specifying which channel to disable the extended update mode for + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableExtendUpdateMode(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_CTRL &= ~EFTU_TOM_CHn_CTRL_EUPM_MASK; +} + +/** + * @brief Set the initial signal level for an EFTU TOM channel + * + * @param pTOM Pointer to the base address of the EFTU TOM module + * @param u8Channel The channel number to be configured + * @param eInitialSignalLevel The initial signal level as an enumerated value + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetInitialSignalLevel(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, EFTU_TOM_SignalLevelType eInitialSignalLevel) +{ + pTOM->Channel[u8Channel].CH_CTRL = (pTOM->Channel[u8Channel].CH_CTRL & (~(uint32_t)EFTU_TOM_CHn_CTRL_SL_MASK)) + | EFTU_TOM_CHn_CTRL_SL(eInitialSignalLevel); +} + +/** + * @brief Set the clock source for an EFTU TOM channel + * @note It has different usage for different TOM channel modes. + * + * @param pTOM Pointer to the EFTU TOM module + * @param u8Channel The channel number in the TOM module + * @param u8ClockSrc The clock source value to be set + * -> SOMI Mode: Reserved + * -> SOMC Mode: Reserved + * -> SOMP Mode + * 0000b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[0] resolution is selected + * 0001b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[1] resolution is selected + * 0010b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[2] resolution is selected + * 0011b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[3] resolution is selected + * 0100b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[4] resolution is selected + * 0101b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[5] resolution is selected + * 0110b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[6] resolution is selected + * 0111b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[7] resolution is selected + * 1000b - Reserved + * 1001b - Reserved + * 1010b - Reserved + * 1011b - Reserved + * 1100b - Functional operation stopped, clock resolution tied to zero. + * 1101b - Reserved + * 1110b - Reserved + * 1111b - Reserved + * -> SOMS Mode + * 0000b - CCM_CLK_RES[0] resolution is selected + * 0001b - CCM_CLK_RES[1] resolution is selected + * 0010b - CCM_CLK_RES[2] resolution is selected + * 0011b - CCM_CLK_RES[3] resolution is selected + * 0100b - CCM_CLK_RES[4] resolution is selected + * 0101b - CCM_CLK_RES[5] resolution is selected + * 0110b - CCM_CLK_RES[6] resolution is selected + * 0111b - CCM_CLK_RES[7] resolution is selected + * 1000b - Reserved + * 1001b - Reserved + * 1010b - Reserved + * 1011b - Reserved + * 1100b - Functional operation stopped, clock resolution tied to zero. + * 1101b - Reserved + * 1110b - Reserved + * 1111b - Reserved + * -> SOMB Mode: Reserved + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetClockSource(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, uint8_t u8ClockSrc) +{ + pTOM->Channel[u8Channel].CH_CTRL = (pTOM->Channel[u8Channel].CH_CTRL & (~(uint32_t)EFTU_TOM_CHn_CTRL_CLK_SRC_MASK)) + | EFTU_TOM_CHn_CTRL_CLK_SRC(u8ClockSrc); +} + +/** + * @brief Set the trigger pulse type for a specific channel of the EFTU_TOM module + * + * @param pTOM Pointer to the base address of the EFTU_TOM module, used to access the module's registers + * @param u8Channel The channel number to configure + * @param eTrigPulse The trigger pulse type, an enumerated value representing different trigger pulse configurations + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetTriggerPulse(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, EFTU_TOM_TriggerPulseType eTrigPulse) +{ + pTOM->Channel[u8Channel].CH_CTRL = (pTOM->Channel[u8Channel].CH_CTRL & (~(uint32_t)EFTU_TOM_CHn_CTRL_TRIG_PULSE_MASK)) + | EFTU_TOM_CHn_CTRL_TRIG_PULSE(eTrigPulse); +} + +/** + * @brief Set the up-down mode for an EFTU TOM channel + * + * @param pTOM Pointer to the EFTU TOM module + * @param u8Channel Channel number specifying which channel to configure + * @param eUpDownMode Desired up-down mode, of type EFTU_TOM_UpDownModeType + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetUpDownMode(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, EFTU_TOM_UpDownModeType eUpDownMode) +{ + pTOM->Channel[u8Channel].CH_CTRL = (pTOM->Channel[u8Channel].CH_CTRL & (~(uint32_t)EFTU_TOM_CHn_CTRL_UDMODE_MASK)) + | EFTU_TOM_CHn_CTRL_UDMODE(eUpDownMode); +} + +/** + * @brief Set the CCU0 reset source for a specific channel. + * + * @param pTOM Pointer to the base address of the EFTU TOM module, used to access the module's registers. + * @param u8Channel The channel number to be configured, determining which channel's settings will be changed. + * @param eResetSource The type of CCU0 reset source, an enumeration value that determines the conditions under which CCU0 is reset. + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetCCU0ResetSource(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, EFTU_TOM_CCO0ResetSourceType eResetSource) +{ + pTOM->Channel[u8Channel].CH_CTRL = (pTOM->Channel[u8Channel].CH_CTRL & (~(uint32_t)EFTU_TOM_CHn_CTRL_RST_CCU0_MASK)) + | EFTU_TOM_CHn_CTRL_RST_CCU0(eResetSource); +} + +/** + * @brief Enable trigger of one-shot pulse by trigger signal. + * + * This function enables the one-shot pulse mode by setting the corresponding bit in the channel control register. + * In this mode, the channel will generate a single pulse after a trigger event. + * + * @param pTOM Pointer to the base address of the EFTU TOM module + * @param u8Channel The channel number to configure + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableOneShotPulse(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_CTRL |= EFTU_TOM_CHn_CTRL_OSM_TRIG_MASK; +} + +/** + * @brief Disable trigger of one-shot pulse by trigger signal. + * + * This function enables the one-shot pulse mode by setting the corresponding bit in the channel control register. + * In this mode, the channel will generate a single pulse after a trigger event. + * + * @param pTOM Pointer to the base address of the EFTU TOM module + * @param u8Channel The channel number to configure + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableOneShotPulse(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_CTRL &= ~EFTU_TOM_CHn_CTRL_OSM_TRIG_MASK; +} + +/** + * @brief Set the trigger output selection for an EFTU TOM channel + * + * @param pTOM Pointer to the base address of the EFTU TOM module + * @param u8Channel The channel number to be configured + * @param eSelection The trigger output selection type + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetTriggerOut(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, EFTU_TOM_TrigOutSelectionType eSelection) +{ + pTOM->Channel[u8Channel].CH_CTRL = (pTOM->Channel[u8Channel].CH_CTRL & (~(uint32_t)EFTU_TOM_CHn_CTRL_TRIGOUT_MASK)) + | EFTU_TOM_CHn_CTRL_TRIGOUT(eSelection); +} + +#if (EFTU_HRPWM_SUPPORT == STD_ON) + +/** + * @brief Allow HRPWM_MUX counter to following channel + * @note Only TOM0 of EFTU0 has this bit. + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral to access its registers + * @param u8Channel The channel number to operate on + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableHRPWMMux(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_CTRL |= EFTU_TOM_CHn_CTRL_HRPWM_MUX_MASK; +} + +/** + * @brief Disable HRPWM_MUX counter to following channel + * @note Only TOM0 of EFTU0 has this bit. + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral to access its registers + * @param u8Channel The channel number to operate on + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableHRPWMMux(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_CTRL &= ~EFTU_TOM_CHn_CTRL_HRPWM_MUX_MASK; +} +#endif +/** + * @brief Select EXT_TRIGIN as trigger signal + * + * if RST_CCU0=1 or OSM_TRIG=1, external trigger is selected as + * trigger to reset CN0 or to start single pulse generation + * + * @param pTOM Pointer to the EFTU_TOM peripheral base address + * @param u8Channel Channel number specifying which channel will have the external trigger source enabled + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableTrigInUseExt(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_CTRL |= EFTU_TOM_CHn_CTRL_TRIG_IN_USE_EXT_MASK; +} + +/** + * @brief Select EXT_TRIGIN as trigger signal + * + * if RST_CCU0=1 or OSM_TRIG=1, internal trigger is selected as + * trigger to reset CN0 or to start single pulse generation. + * + * @param pTOM Pointer to the EFTU_TOM peripheral base address + * @param u8Channel Channel number specifying which channel will have the external trigger source enabled + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableTrigInUseExt(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_CTRL &= ~EFTU_TOM_CHn_CTRL_TRIG_IN_USE_EXT_MASK; +} + +/** + * @brief Select EXT_TRIGIN as potential output signal TOM_CH_TRIGOUT of + * TOM channel N when TRIG_OUT == 0. + * + * Bypass external trigger in (from the preceding channel) to trigger + * out (to the following channel) + * + * @param pTOM Pointer to the EFTU_TOM peripheral base address + * @param u8Channel Channel number specifying which channel will have the external trigger source enabled + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableTrigOutUseExt(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_CTRL |= EFTU_TOM_CHn_CTRL_TRIG_OUT_USE_EXT_MASK; +} + +/** + * @brief Select EXT_TRIGIN as potential output signal TOM_CH_TRIGOUT of + * TOM channel N when TRIG_OUT == 0. + * + * Bypass internal trigger in (from the preceding channel) to trigger + * out (to the following channel) + * + * @param pTOM Pointer to the EFTU_TOM peripheral base address + * @param u8Channel Channel number specifying which channel will have the external trigger source enabled + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableTrigOutUseExt(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_CTRL &= ~EFTU_TOM_CHn_CTRL_TRIG_OUT_USE_EXT_MASK; +} + +/** + * @brief Set the external forced update signal for an EFTU TOM channel + * @note It has different usage for different TOM channel modes. + * + * @param pTOM Base address pointer of the EFTU TOM module, used to access the TOM module registers + * @param u8Channel Channel number of the EFTU TOM, used to select the channel to configure + * @param u8ExtForcedUpdate Value of the external forced update signal to be written to the channel control register + * -> SOMI Mode: Reserved + * 0b - use signal from TGC to force update + * 1b - use external trigger to force update + * -> SOMC Mode: Reserved + * -> SOMP Mode: + * 0b - use signal from TGC to force update + * 1b - use external trigger to force update + * -> SOMS Mode: Reserved + * 0b - use signal from TGC to force update + * 1b - use external trigger to force update + * -> SOMB Mode: Reserved + * 0b - use signal from TGC to force update + * 1b - use external trigger to force update + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetExtForcedUpdate(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, uint8_t u8ExtForcedUpdate) +{ + pTOM->Channel[u8Channel].CH_CTRL = (pTOM->Channel[u8Channel].CH_CTRL & (~(uint32_t)EFTU_TOM_CHn_CTRL_EXT_FUPD_MASK)) | EFTU_TOM_CHn_CTRL_EXT_FUPD(u8ExtForcedUpdate); +} + +/** + * @brief Select the time base value for the EFTU TOM module + * + * @param pTOM Base address pointer of the EFTU TOM module + * @param u8Channel Channel number indicating which TOM channel to configure + * @param eTimeBaseSel Enum type indicating the time base value to select + */ + +LOCAL_INLINE void EFTU_TOM_HWA_SelectTimeBaseValue(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, EFTU_TOM_TBValueSelectionType eTimeBaseSel) +{ + pTOM->Channel[u8Channel].CH_CTRL = (pTOM->Channel[u8Channel].CH_CTRL & (~(uint32_t)EFTU_TOM_CHn_CTRL_TB12_SEL_MASK)) + | EFTU_TOM_CHn_CTRL_TB12_SEL(eTimeBaseSel); +} + +/** + * @brief Set the shadow initial signal level for an EFTU TOM channel + * + * @param pTOM Pointer to the base address of the EFTU TOM module + * @param u8Channel The channel number to be configured + * @param eInitialSignalLevel The initial signal level as an enumerated value + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetShadowInitialSignalLevel(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, EFTU_TOM_SignalLevelType eInitialSignalLevel) +{ + pTOM->Channel[u8Channel].CH_CTRL_SR = (pTOM->Channel[u8Channel].CH_CTRL_SR & (~(uint32_t)EFTU_TOM_CHn_CTRL_SR_SL_SR_MASK)) + | EFTU_TOM_CHn_CTRL_SR_SL_SR(eInitialSignalLevel); +} + +/** + * @brief Set the shadow clock source for an EFTU TOM channel + * @note It has different usage for different TOM channel modes. + * + * @param pTOM Pointer to the EFTU TOM module + * @param u8Channel The channel number in the TOM module + * @param u8ClockSrc The clock source value to be set + * -> SOMI Mode: Reserved + * -> SOMC Mode: Reserved + * -> SOMP Mode + * 0000b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[0] resolution is selected + * 0001b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[1] resolution is selected + * 0010b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[2] resolution is selected + * 0011b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[3] resolution is selected + * 0100b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[4] resolution is selected + * 0101b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[5] resolution is selected + * 0110b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[6] resolution is selected + * 0111b - After its first update from the shadow register CLK_SRC_SR, + * CCM_CLK_RES[7] resolution is selected + * 1000b - Reserved + * 1001b - Reserved + * 1010b - Reserved + * 1011b - Reserved + * 1100b - Functional operation stopped, clock resolution tied to zero. + * 1101b - Reserved + * 1110b - Reserved + * 1111b - Reserved + * -> SOMS Mode + * 0000b - CCM_CLK_RES[0] resolution is selected + * 0001b - CCM_CLK_RES[1] resolution is selected + * 0010b - CCM_CLK_RES[2] resolution is selected + * 0011b - CCM_CLK_RES[3] resolution is selected + * 0100b - CCM_CLK_RES[4] resolution is selected + * 0101b - CCM_CLK_RES[5] resolution is selected + * 0110b - CCM_CLK_RES[6] resolution is selected + * 0111b - CCM_CLK_RES[7] resolution is selected + * 1000b - Reserved + * 1001b - Reserved + * 1010b - Reserved + * 1011b - Reserved + * 1100b - Functional operation stopped, clock resolution tied to zero. + * 1101b - Reserved + * 1110b - Reserved + * 1111b - Reserved + * -> SOMB Mode: Reserved + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetShadowClockSource(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, uint8_t u8ClockSrc) +{ + pTOM->Channel[u8Channel].CH_CTRL_SR = (pTOM->Channel[u8Channel].CH_CTRL_SR & (~(uint32_t)EFTU_TOM_CHn_CTRL_SR_CLK_SRC_SR_MASK)) + | EFTU_TOM_CHn_CTRL_SR_CLK_SRC_SR(u8ClockSrc); +} + + +#if defined(HRPWM_INSTANCE_COUNT) && (HRPWM_INSTANCE_COUNT > 0U) +/** + * @brief Set TOM high resolution support for a specific channel in the EFTU_TOM module + * + * @param pTOM Base address pointer of the EFTU_TOM module, used to access the module's registers + * @param u8Channel The channel number to configure, determines which CH_CTRL2 register to modify + * @param bSupport A boolean value indicating whether to enable HRPWM support. True to enable, False to disable + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetHRPWMSupport(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, bool bSupport) +{ + pTOM->Channel[u8Channel].CH_CTRL2 = (pTOM->Channel[u8Channel].CH_CTRL2 & ~(EFTU_TOM_CHn_CTRL2_HRPWM_MASK)) + | EFTU_TOM_CHn_CTRL2_HRPWM(bSupport); +} +#endif +/** + * @brief Get the output level of an EFTU TOM channel + * + * @param pTOM Pointer to the base address of the EFTU TOM module, used to access the module's registers + * @param u8Channel The channel number to read the output level from + * @return uint8_t The current output level of the specified channel, 0 for low level, 1 for high level + */ +LOCAL_INLINE uint8_t EFTU_TOM_HWA_GetOutputLevel(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + return (uint8_t)(pTOM->Channel[u8Channel].CH_STAT & EFTU_TOM_CHn_STAT_OL_MASK); +} + +/** + * @brief Get the CCU match status + * + * @param pTOM Base address pointer of the EFTU TOM module, used to access the module's registers + * @param u8Channel Channel number, specifying the particular channel to query + * @return uint8_t The CCU match status value + */ +LOCAL_INLINE uint8_t EFTU_TOM_HWA_GetCcuMatch(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + return (uint8_t)((pTOM->Channel[u8Channel].CH_STAT & EFTU_TOM_CHn_STAT_CCU_MATCH_MASK) >> EFTU_TOM_CHn_STAT_CCU_MATCH_SHIFT); +} + +/** + * @brief Get the One-shot Mode Retrigger Failure Flag + * + * @param pTOM Base address pointer of the EFTU TOM module, used to access the module's registers + * @param u8Channel Channel number, specifying the particular channel to query + * @return uint8_t The One-shot Mode Retrigger Failure Flag + */ +LOCAL_INLINE uint8_t EFUT_TOM_HWA_GetOSMRetrigFailed(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + return (uint8_t)((pTOM->Channel[u8Channel].CH_STAT & EFTU_TOM_CHn_STAT_OSM_RTF_MASK) >> EFTU_TOM_CHn_STAT_OSM_RTF_SHIFT); +} + +/** + * Clear OSM Retrigger Failed Status + * + * @param pTOM Pointer to the EFTU_TOM_Type structure, representing the base address of the TOM module + * @param u8Channel Channel number (uint8_t) specifying the channel whose status needs to be cleared + */ +LOCAL_INLINE void EFUT_TOM_HWA_ClearOSMRetrigFailed(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_STAT = EFTU_TOM_CHn_STAT_OSM_RTF_MASK; +} + +/** + * @brief Get the current value of the CCU0 counter + * + * @param pTOM Base address pointer of the EFTU_TOM module, used to access the module's registers + * @param u8Channel Channel number, used to select the specific counter channel + * @return uint32_t The current value of the CCU0 counter + */ +LOCAL_INLINE uint32_t EFTU_TOM_HWA_GetCCU0Counter(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + return pTOM->Channel[u8Channel].CH_CN0 & EFTU_TOM_CHn_CN0_CN0_MASK; +} + +/** + * @brief Set the current count value of the CCU0 counter + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral, used to access the peripheral's registers + * @param u8Channel Channel number, specifying which channel's counter needs to be set + * @param u32Value The count value to be set, this value will be written to the counter register + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetCCU0Counter(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, uint32_t u32Value) +{ + pTOM->Channel[u8Channel].CH_CN0 = u32Value & EFTU_TOM_CHn_CN0_CN0_MASK; +} + +/** + * @brief Set the CCU0 compare value + * + * @param pTOM Base address pointer of the EFTU TOM module, used to access the module's registers + * @param u8Channel Channel number, indicating the channel for which the compare value needs to be set + * @param u32Value Compare value, the value to be set in the compare register + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetCCU0Compare(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, uint32_t u32Value) +{ + pTOM->Channel[u8Channel].CH_CM0 = u32Value & EFTU_TOM_CHn_CM0_CM0_MASK; +} + +/** + * @brief Set the value of Shadow Register 0 for a specific channel in the EFTU_TOM module + * + * @param pTOM Base address pointer of the EFTU_TOM module, used to access the module's registers + * @param u8Channel Channel number of the EFTU_TOM module, used to select the specific channel to operate on + * @param u32Value Value to be set in the Shadow Register 0, which determines the compare or capture behavior of the channel + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetShadowValue0(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, uint32_t u32Value) +{ + pTOM->Channel[u8Channel].CH_SR0 = u32Value & EFTU_TOM_CHn_SR0_SR0_MASK; +} + +/** + * @brief Set TOM CCU1 Compare Register + * + * @param pTOM Pointer to the base address of the EFTU_TOM module, used to access the module's registers + * @param u8Channel Channel number, which determines the specific CCU1 counter of the channel + * @param u32Value The counter value to be set, this is a 32-bit value + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetCCU1Counter(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, uint32_t u32Value) +{ + pTOM->Channel[u8Channel].CH_CM1 = u32Value & EFTU_TOM_CHn_CM1_CM1_MASK; +} + +/** + * @brief Set the value of Shadow Register 1 for a specific channel in the EFTU_TOM module + * + * @param pTOM Base address pointer of the EFTU_TOM module, used to access the module's registers + * @param u8Channel Channel number of the EFTU_TOM module, used to select the specific channel to operate on + * @param u32Value Value to be set in the Shadow Register 1, which determines the compare or capture behavior of the channel + */ +LOCAL_INLINE void EFTU_TOM_HWA_SetShadowValue1(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, uint32_t u32Value) +{ + pTOM->Channel[u8Channel].CH_SR1 = u32Value & EFTU_TOM_CHn_SR1_SR1_MASK; +} + +/** + * @brief Get the interrupt flag for a specific channel of the EFTU TOM module. + * + * @param pTOM Base address pointer to the EFTU TOM module registers. + * @param u8Channel The channel number to select the specific channel interrupt status. + * @return uint32_t The interrupt status flag of the selected channel. + */ +LOCAL_INLINE uint32_t EFTU_TOM_HWA_GetInterruptFlag(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + return pTOM->Channel[u8Channel].CH_IRQ_ST; +} + +/** + * @brief Clear the interrupt flag for a specific EFTU TOM channel + * + * @param pTOM Pointer to the EFTU_TOM peripheral structure, used to access and modify the peripheral registers + * @param u8Channel The channel number of the EFTU TOM, specifying the exact channel whose interrupt flag needs to be cleared + * @param u32Flag The interrupt flag to be cleared, written to the interrupt status register to clear the flag + */ +LOCAL_INLINE void EFTU_TOM_HWA_ClearInterruptFlag(EFTU_TOM_Type * const pTOM, uint8_t u8Channel, uint32_t u32Flag) +{ + pTOM->Channel[u8Channel].CH_IRQ_ST = u32Flag; +} + +/** + * @brief Enable CCU0 Interrupt + * + * This function enables the CCU0 interrupt by setting the corresponding interrupt enable bit for a specific channel. + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral to access its registers + * @param u8Channel The channel number for which the CCU0 interrupt is to be enabled + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableCCU0Interrupt(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_IRQ_EN |= EFTU_TOM_CHn_IRQ_EN_CCU0_TC_IRQ_EN_MASK; +} + +/** + * @brief Disable CCU0 Interrupt + * + * This function enables the CCU0 interrupt by setting the corresponding interrupt enable bit for a specific channel. + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral to access its registers + * @param u8Channel The channel number for which the CCU0 interrupt is to be disable + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableCCU0Interrupt(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_IRQ_EN &= ~EFTU_TOM_CHn_IRQ_EN_CCU0_TC_IRQ_EN_MASK; +} + +/** + * @brief Enable CCU1 Interrupt + * + * This function enables the CCU1 interrupt by setting the corresponding interrupt enable bit for a specific channel. + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral to access its registers + * @param u8Channel The channel number for which the CCU1 interrupt is to be enabled + */ +LOCAL_INLINE void EFTU_TOM_HWA_EnableCCU1Interrupt(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_IRQ_EN |= EFTU_TOM_CHn_IRQ_EN_CCU1_TC_IRQ_EN_MASK; +} + +/** + * @brief Disable CCU1 Interrupt + * + * This function enables the CCU1 interrupt by setting the corresponding interrupt enable bit for a specific channel. + * + * @param pTOM Base address pointer of the EFTU_TOM peripheral to access its registers + * @param u8Channel The channel number for which the CCU1 interrupt is to be disable + */ +LOCAL_INLINE void EFTU_TOM_HWA_DisableCCU1Interrupt(EFTU_TOM_Type * const pTOM, uint8_t u8Channel) +{ + pTOM->Channel[u8Channel].CH_IRQ_EN &= ~EFTU_TOM_CHn_IRQ_EN_CCU1_TC_IRQ_EN_MASK; +} + +/** @}*/ + +#endif /* EFTU_INSTANCE_COUNT > 0U */ + +#endif /* _HWA_EFTU_TOM_H_ */ diff --git a/Inc/HwA_eim.h b/Inc/HwA_eim.h new file mode 100644 index 0000000..bd2cf23 --- /dev/null +++ b/Inc/HwA_eim.h @@ -0,0 +1,167 @@ +/** + * @file HwA_eim.h + * @author Flagchip0100 + * @brief EIM Module Register API + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright 2020-2024 Flagchip Semiconductors Co., Ltd. + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip052 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip100 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_EIM_H_ +#define _HWA_EIM_H_ + +#include "device_header.h" + +#if (EIM_INSTANCE_COUNT > 0U) + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @defgroup HwA_eim HwA_eim + * @ingroup module_driver_eim + * @{ + */ + +/******************************************************************************* + * Local inline function + ******************************************************************************/ +/** + * @brief Enable EIM Global Error Injection. + * + * @param pEim EIM Instance. + */ +LOCAL_INLINE void EIM_HWA_EnableGlobalErrorInjection(EIM_Type *const pEim) +{ + pEim->CR = EIM_CR_GEIEN(1U); +} + +/** + * @brief Disable EIM Global Error Injection. + * + * @param pEim EIM Instance. + */ +LOCAL_INLINE void EIM_HWA_DisableGlobalErrorInjection(EIM_Type *const pEim) +{ + pEim->CR = EIM_CR_GEIEN(0U); +} + +/** + * @brief Get EIM channel N control register value. + * + * @param pEim EIM Instance. + * @param u8Idx Control register index. + * @return EIM channel N control register value. + */ +LOCAL_INLINE uint32_t EIM_HWA_GetCtrlRegn(const EIM_Type *const pEim, uint8_t u8Idx) +{ + return pEim->CTRL_REG[u8Idx]; +} + +/** + * @brief Set EIM channel N control register value. + * + * @param pEim EIM Instance. + * @param u8Idx Control register index. + * @param u32Value Register value. + */ +LOCAL_INLINE void EIM_HWA_SetCtrlRegn(EIM_Type *const pEim, uint8_t u8Idx, uint32_t u32Value) +{ + pEim->CTRL_REG[u8Idx] = u32Value; +} + +/** + * @brief Get EIM_CTRL_REGn register DWP lock status. + * + * @param pEim EIM Instance. + * @param u8Idx Control register index. + * @return Lock status. + */ +LOCAL_INLINE bool EIM_HWA_GetCtrlRegnDwpLockStatus(const EIM_Type *const pEim, uint8_t u8Idx) +{ + return ((pEim->CTRL_REG[u8Idx] & EIM_CTRL_REG_DWP_LOCK_MASK) != 0U) ? true : false; +} + +/** + * @brief Set EIM_CTRL_REGn register DWP lock status. + * + * @param pEim EIM Instance. + * @param u8Idx Control register index. + * @param bEnable Enable or disable. + */ +LOCAL_INLINE void EIM_HWA_SetCtrlRegnDwpLock(EIM_Type *const pEim, uint8_t u8Idx, bool bEnable) +{ + pEim->CTRL_REG[u8Idx] = (pEim->CTRL_REG[u8Idx] & ~((uint32_t)EIM_CTRL_REG_DWP_LOCK_MASK)) | EIM_CTRL_REG_DWP_LOCK(bEnable); +} + +/** + * @brief Set EIM_CTRL_REGn register DWP mode. + * + * @param pEim EIM Instance. + * @param u8Idx Control register index. + * @param u8DwpMode DWP mode. + */ +LOCAL_INLINE void EIM_HWA_SetCtrlRegnDwpMode(EIM_Type *const pEim, uint8_t u8Idx, uint8_t u8DwpMode) +{ + pEim->CTRL_REG[u8Idx] = (pEim->CTRL_REG[u8Idx] & ~((uint32_t)EIM_CTRL_REG_DWP_MASK)) | EIM_CTRL_REG_DWP(u8DwpMode); +} + +/** + * @brief Set EIM LOCKSTEP error injection register. + * + * @param pEim EIM Instance. + * @param u8Idx Control register index. + * @param u32Value Register value. + */ +LOCAL_INLINE void EIM_HWA_SetLockstep(EIM_Type *const pEim, uint8_t u8Idx, uint32_t u32Value) +{ + pEim->LOCKSTEP[u8Idx] = u32Value; +} + +/** + * @brief Get EIM bus n register value. + * + * @param pEim EIM Instance. + * @param u8Idx Bus register index. + * @return Register value. + */ +LOCAL_INLINE uint32_t EIM_HWA_GetBusRegn(const EIM_Type *const pEim, uint8_t u8Idx) +{ + return pEim->BUS_REG[u8Idx]; +} + +/** + * @brief Set EIM bus n register value. + * + * @param pEim EIM Instance. + * @param u8Idx Control register index. + * @param u32Value Register value. + */ +LOCAL_INLINE void EIM_HWA_SetBusRegn(EIM_Type *const pEim, uint8_t u8Idx, uint32_t u32Value) +{ + pEim->BUS_REG[u8Idx] = u32Value; +} + +/** @}*/ + +#if defined(__cplusplus) +} +#endif + +#endif /* (EIM_INSTANCE_COUNT > 0U) */ + +#endif /* _HWA_EIM_H_ */ diff --git a/Inc/HwA_elu.h b/Inc/HwA_elu.h new file mode 100644 index 0000000..d8cb912 --- /dev/null +++ b/Inc/HwA_elu.h @@ -0,0 +1,1143 @@ +/** + * @file HwA_elu.h + * @author Flagchip + * @brief esLU hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_ELU_H_ +#define _HWA_ELU_H_ + +#include "device_header.h" + +#if ELU_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_lu HwA_lu + * @ingroup module_driver_lu + * @{ + */ + +/********* Local typedef ************/ +/** @brief LU LG instance */ +typedef enum +{ + LU_LG_0 = 0U, + LU_LG_1, + LU_LG_2, + LU_LG_3 +} LU_LG_Type; + +/** @brief LU AOI mode */ +typedef enum +{ + LU_NO_BYPASS = 0U, + LU_LUT0_BYPASS, + LU_LUT1_BYPASS, + LU_LUT0_LUT1_BYPASS +} LU_LG_BypassModeType; + +/** @brief LU FF mode */ +typedef enum +{ + LU_BYPASS_MODE0 = 0U, + LU_RS_MODE, + LU_TFF_MODE, + LU_DFF_MODE, + LU_JKFF_MODE, + LU_LATCH_MODE, + LU_NORMAL0_MODE, + LU_NORMAL1_MODE +} LU_LG_ConfigModeType; + +/** @brief LU Input(n) type */ +typedef enum +{ + LU_INPUT_N_A = 0U, + LU_INPUT_N_B, + LU_INPUT_N_C, + LU_INPUT_N_D +} LU_LG_InputNType; + +typedef enum +{ + LU_INPUT_LU = 0U, + LU_INPUT_DU_OUTA, + LU_INPUT_DU_OUTB, + LU_INPUT_DU_OUTC +} LU_InputDType; + +typedef enum +{ + LU_OUTPUT_LG = 0U, + LU_OUTPUT_DU_OUTA, + LU_OUTPUT_DU_OUTB, + LU_OUTPUT_DU_OUTC, +} LU_OutputDType; + +typedef enum +{ + LU_PRESCALER_DIV_0 = 0, + LU_PRESCALER_DIV_2, + LU_PRESCALER_DIV_3, + LU_PRESCALER_DIV_8, + LU_PRESCALER_DIV_16, + LU_PRESCALER_DIV_32, + LU_PRESCALER_DIV_64, + LU_PRESCALER_DIV_128 +} LU_PrescalerType; + +typedef enum +{ + LU_FLEX_SAMP_EVEN_EDGES = 0, /** 00b - Sampling on even edges.*/ + LU_FLEX_SAMP_ODD_EDGES , /** 01b - Sampling on odd edges.*/ + LU_FLEX_SAMP_SEND_EVEN_EDGES, /** 10b - Sending on even edges.*/ + LU_FLEX_SAMP_SEND_ODD_EDGES /** 11b - Sending on odd edges.*/ +} LU_FlexSampType; + +typedef enum +{ + LU_OPC_NONE = 0, + LU_OPC_INCR , /** 0001b - INCR.*/ + LU_OPC_DECR , /** 0010b - DECR.*/ + LU_OPC_INCR_WRAP , /** 0011b - INCR_Wrap.*/ + LU_OPC_DECR_WRAP , /** 0100b - DECR_Wrap.*/ + LU_OPC_INCR_DECR , /** 0101b - INCR_DECR.*/ + LU_OPC_INCR_DECR_WRAP , /** 0110b - INCR_DECR_Wrap.*/ + LU_OPC_INCR_WRAP_MODE1 , /** 0111b - INCR_Wrap_Mode1.*/ + LU_OPC_INCR_DECR_WRAP_MODE1 , /** 1000b - INCR_DECR_Wrap_Mode1.*/ + LU_OPC_SHIFT_IN_LEFT , /** 1001b - Shift In Left.*/ + LU_OPC_SHIFT_IN_RIGHT , /** 1010b - Shift In Right.*/ + LU_OPC_SHIFT_OUT_LEFT , /** 1011b - Shift Out Left.*/ + LU_OPC_SHIFT_OUT_RIGHT , /** 1100b - Shift Out Right.*/ + LU_OPC_FLEX, /** 1101b - FLEX.*/ + LU_OPC_DATA_MATCH /** 1110b - Data Match.*/ +} LU_DU_OpcType; + +typedef enum +{ + INPUTAMUX_VSS = 0, + INPUTAMUX_VDD , + INPUTAMUX_LG0_LUT0_OUT , + INPUTAMUX_LG0_LUT1_OUT , + INPUTAMUX_LG1_LUT0_OUT , + INPUTAMUX_LG1_LUT1_OUT , + INPUTAMUX_LG2_LUT0_OUT , + INPUTAMUX_LG2_LUT1_OUT , + INPUTAMUX_LG3_LUT0_OUT , + INPUTAMUX_LG3_LUT1_OUT , + INPUTAMUX_LU_DATA_UNIT_OUTA , + INPUTAMUX_LU_DATA_UNIT_OUTB , + INPUTAMUX_LU_DATA_UNIT_OUTC +} LU_DU_InputMuxType; + +typedef enum +{ + LU_DU_CAPTURE_NONE = 0, /**< do not use capture*/ + LU_DU_CAPTURE_POS_EDGE , + LU_DU_CAPTURE_NEG_EDGE , + LU_DU_CAPTURE_BOTH_EDGE +}LU_DU_CaptureModeType; + +/********* Local inline function ************/ +/** + * @brief Configure LU LG(n) configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue LUT register value + */ +LOCAL_INLINE void LU_HWA_ConfigCfg(LU_Type *pLu, LU_LG_Type eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].LG_CFG = u32RegValue; +} + +/** + * @brief Configure LU LG(n) configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue LUT0 register value + */ +LOCAL_INLINE void LU_HWA_SetConfigCfgLut0(LU_Type *pLu, LU_LG_Type eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].LG_CFG |= LU_LG_CFG_LUT0_CTRL(u32RegValue); +} + +/** + * @brief Configure LU LG(n) configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue LUT1 register value + */ +LOCAL_INLINE void LU_HWA_SetConfigCfgLut1(LU_Type *pLu, LU_LG_Type eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].LG_CFG |= LU_LG_CFG_LUT1_CTRL(u32RegValue); +} + +/** + * @brief Configure LU LG(n) contrl configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue CTRL register value + */ +LOCAL_INLINE void LU_HWA_ConfigCtrl(LU_Type *pLu, LU_LG_Type eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].LG_CTRL = u32RegValue; +} + +/** + * @brief Configure LU LG(n) filter configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue FILT register value + */ +LOCAL_INLINE void LU_HWA_ConfigFilter(LU_Type *pLu, LU_LG_Type eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].LG_FILT = u32RegValue; +} + +/** + * @brief Configures the DMA selection. + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_ConfigDmaSel(LU_Type *pLu, LU_LG_Type eLg) +{ + pLu->LG[eLg].LG_CTRL |= (uint32_t)LU_DU_CTRL_DMASEL_MASK; +} + +/** + * @brief Configures the Interrupt selection. + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_ConfigIntSel(LU_Type *pLu, LU_LG_Type eLg) +{ + pLu->LG[eLg].LG_CTRL |= (uint32_t)LU_DU_CTRL_INTSEL_MASK; +} + +/** + * @brief Configures the input selection. + * + * @param pLu Pointer to the LU instance. + * @param eLg LG instance. + * @param eInput Input selection. + */ +LOCAL_INLINE void LU_HWA_ConfigInuptSelToA(LU_Type *pLu, LU_LG_Type eLg, LU_InputDType eInput) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].LG_CTRL; + pLu->LG[eLg].LG_CTRL = ((u32TempRegValue & ~(uint32_t)LU_LG_CTRL_INPUTASEL_MASK) | LU_LG_CTRL_INPUTASEL(eInput)); +} + +/** + * @brief Configures the input selection. + * + * @param pLu Pointer to the LU instance. + * @param eLg LG instance. + * @param eInput Input selection. + */ +LOCAL_INLINE void LU_HWA_ConfigInuptSelToB(LU_Type *pLu, LU_LG_Type eLg, LU_InputDType eInput) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].LG_CTRL; + pLu->LG[eLg].LG_CTRL = ((u32TempRegValue & ~(uint32_t)LU_LG_CTRL_INPUTBSEL_MASK) | LU_LG_CTRL_INPUTBSEL(eInput)); +} + +/** + * @brief Configures the input selection. + * + * @param pLu Pointer to the LU instance. + * @param eLg LG instance. + * @param eInput Input selection. + */ +LOCAL_INLINE void LU_HWA_ConfigInuptSelToC(LU_Type *pLu, LU_LG_Type eLg, LU_InputDType eInput) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].LG_CTRL; + pLu->LG[eLg].LG_CTRL = ((u32TempRegValue & ~(uint32_t)LU_LG_CTRL_INPUTCSEL_MASK) | LU_LG_CTRL_INPUTCSEL(eInput)); +} + +/** + * @brief Configures the input selection. + * + * @param pLu Pointer to the LU instance. + * @param eLg LG instance. + * @param eInput Input selection. + */ +LOCAL_INLINE void LU_HWA_ConfigInuptSelToD(LU_Type *pLu, LU_LG_Type eLg, LU_InputDType eInput) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].LG_CTRL; + pLu->LG[eLg].LG_CTRL = ((u32TempRegValue & ~(uint32_t)LU_LG_CTRL_INPUTDSEL_MASK) | LU_LG_CTRL_INPUTDSEL(eInput)); +} + +/** + * @brief Set LG bypass control + * + * @param pLu LU instance + * @param eLg LG instance + * @param eMode LG bypass control mode + */ +LOCAL_INLINE void LU_HWA_SetLgBypassControl(LU_Type *pLu, LU_LG_Type eLg, LU_LG_BypassModeType eMode) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].LG_CTRL; + pLu->LG[eLg].LG_CTRL = ((u32TempRegValue & ~(uint32_t)LU_LG_CTRL_BYPASS_MASK) | LU_LG_CTRL_BYPASS(eMode)); +} + +/** + * @brief Set LG inputs synchronous control + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value LG input bit,0-3 bit indicate INPUT(n)A/INPUT(n)B/INPUT(n)C/INPUT(n)D + */ +LOCAL_INLINE void LU_HWA_SetLgInputsSyncCtrl(LU_Type *pLu, LU_LG_Type eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].LG_CTRL; + pLu->LG[eLg].LG_CTRL = ((u32TempRegValue & ~(uint32_t)LU_LG_CTRL_SYNC_MASK) | LU_LG_CTRL_SYNC(u32Value)); +} + +/** + * @brief Set LG output feedback override control + * + * @param pLu LU instance + * @param eLg LG instance + * @param eInput Feedback to LG input + */ +LOCAL_INLINE void LU_HWA_SetLgFeedbackOverrideCtrl(LU_Type *pLu, LU_LG_Type eLg, LU_LG_InputNType eInput) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].LG_CTRL; + pLu->LG[eLg].LG_CTRL = ((u32TempRegValue & ~(uint32_t)LU_LG_CTRL_FB_OVRD_MASK) | LU_LG_CTRL_FB_OVRD(eInput)); +} + +/** + * @brief Set LG Flip-Flop mode + * + * @param pLu LU instance + * @param eLg LG instance + * @param eMode Flip-Flop mode + */ +LOCAL_INLINE void LU_HWA_SetLgFlipFlopMode(LU_Type *pLu, LU_LG_Type eLg, LU_LG_ConfigModeType eMode) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].LG_CTRL; + pLu->LG[eLg].LG_CTRL = ((u32TempRegValue & ~(uint32_t)LU_LG_CTRL_MOD_MASK) | LU_LG_CTRL_MOD(eMode)); +} + +/** + * @brief Generate enable pulse + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_EnableControlFlipFlopInitOutput(LU_Type *pLu, LU_LG_Type eLg) +{ + pLu->LG[eLg].LG_CTRL |= (uint32_t)LU_LG_CTRL_INIT_EN_MASK; +} + +/** + * @brief Configure the output of flip-flop as "1" + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_ConfigFlipFlopTo1(LU_Type *pLu, LU_LG_Type eLg) +{ + pLu->LG[eLg].LG_CTRL |= (uint32_t)LU_LG_CTRL_FF_INIT_MASK; +} + +/** + * @brief Configure the output of flip-flop as "0" + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_ConfigFlipFlopTo0(LU_Type *pLu, LU_LG_Type eLg) +{ + pLu->LG[eLg].LG_CTRL &= ~(uint32_t)LU_LG_CTRL_FF_INIT_MASK; +} + +/** + * @brief Input filter sample count for LUT0 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample count value + */ +LOCAL_INLINE void LU_HWA_SetLUT0InputFilterSampleCount(LU_Type *pLu, LU_LG_Type eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].LG_FILT; + pLu->LG[eLg].LG_FILT = ((u32TempRegValue & ~(uint32_t)LU_LG_FILT_CNT0_MASK) | LU_LG_FILT_CNT0(u32Value)); +} + +/** + * @brief Input filter sample period for LUT0 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample period value + */ +LOCAL_INLINE void LU_HWA_SetLUT0InputFilterSamplePeriod(LU_Type *pLu, LU_LG_Type eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].LG_FILT; + pLu->LG[eLg].LG_FILT = ((u32TempRegValue & ~(uint32_t)LU_LG_FILT_PRE0_MASK) | LU_LG_FILT_PRE0(u32Value)); +} + +/** + * @brief Input filter sample count for LUT1 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample count value + */ +LOCAL_INLINE void LU_HWA_SetLUT1InputFilterSampleCount(LU_Type *pLu, LU_LG_Type eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].LG_FILT; + pLu->LG[eLg].LG_FILT = ((u32TempRegValue & ~(uint32_t)LU_LG_FILT_CNT1_MASK) | LU_LG_FILT_CNT1(u32Value)); +} + +/** + * @brief Input filter sample period for LUT1 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample period value + */ +LOCAL_INLINE void LU_HWA_SetLUT1InputFilterSamplePeriod(LU_Type *pLu, LU_LG_Type eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].LG_FILT; + pLu->LG[eLg].LG_FILT = ((u32TempRegValue & ~(uint32_t)LU_LG_FILT_PRE1_MASK) | LU_LG_FILT_PRE1(u32Value)); +} + +/** + * @brief Input filter sample period for LUT1 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample period value + */ +LOCAL_INLINE void LU_HWA_SetControlPrescaler(LU_Type *pLu, LU_PrescalerType ePrescaler) +{ + pLu->CTRL |= LU_CTRL_PS(ePrescaler); +} + +/** + * @brief Input filter sample period for LUT1 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample period value + */ +LOCAL_INLINE void LU_HWA_SetIntStatus(LU_Type *pLu, uint32_t u32W1cFlag) +{ + pLu->INT_ST |= LU_INT_ST_LUTINTST(u32W1cFlag); +} + +/** + * @brief Input filter sample period for LUT1 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample period value + */ +LOCAL_INLINE uint32_t LU_HWA_GetIntStatus(LU_Type *pLu) +{ + return (pLu->INT_ST & LU_INT_ST_LUTINTST_MASK); +} + +/** + * @brief Input filter sample period for LUT1 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample period value + */ +LOCAL_INLINE void LU_HWA_SetConfigCfg(LU_Type *pLu, uint32_t u32RegValue) +{ + pLu->CFG = u32RegValue; +} + +/** + * @brief Input filter sample period for LUT1 + * + * @param pLu LU instance + */ +LOCAL_INLINE void LU_HWA_EnableCofigCfgInt(LU_Type *pLu) +{ + pLu->CFG |= LU_CFG_INTEN_MASK; +} + +/** + * @brief Input filter sample period for LUT1 + * + * @param pLu LU instance + */ +LOCAL_INLINE void LU_HWA_DisableCofigCfgInt(LU_Type *pLu) +{ + pLu->CFG &= ~LU_CFG_INTEN_MASK; +} + +/** + * @brief Input filter sample period for LUT1 + * + * @param pLu LU instance + */ +LOCAL_INLINE void LU_HWA_SoftReset(LU_Type *pLu) +{ + pLu->SW_RESET = 0xFC50AF50; +} + +/** + * @brief Sets the configuration of the Data Unit Control Register + * + * @param pLu Pointer to the LU_Type instance + * @param u32RegValue The value to be written to the DU_CFG register + */ +LOCAL_INLINE void LU_HWA_SetConfigDuCfg(LU_Type *pLu, uint32_t u32RegValue) +{ + pLu->DU_CFG = u32RegValue; +} + +/** + * @brief Sets the configuration of the Data Unit Control Register + * + * @param pLu Pointer to the LU_Type instance + * @param u32RegValue The value to be written to the DU_CTRL register + */ +LOCAL_INLINE void LU_HWA_SetConfigDuCTRL(LU_Type *pLu, uint32_t u32RegValue) +{ + pLu->DU_CTRL = u32RegValue; +} + +/** + * @brief Enables the FlexMode Data Compare feature + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableDuCtrlComp(LU_Type *pLu) +{ + pLu->DU_CTRL |= LU_DU_CTRL_COMP_MASK; +} + +/** + * @brief Disables the FlexMode Data Compare feature + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableDuCtrlComp(LU_Type *pLu) +{ + pLu->DU_CTRL &= ~LU_DU_CTRL_COMP_MASK; +} + +/** + * @brief Enables the Continuous Mode + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableDuCfgCone(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CTRL_CONEN_MASK; +} + +/** + * @brief Disables the Continuous Mode + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableDuCfgCone(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CTRL_CONEN_MASK; +} + +/** + * @brief Enables the Capture Mode + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_ConfigDuCtrlCapture(LU_Type *pLu, LU_DU_CaptureModeType eCaptureCfg) +{ + pLu->DU_CTRL |= LU_DU_CTRL_CAPMODE(eCaptureCfg); +} + +/** + * @brief Enables the DMA Selection feature + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableDuCtrlDma(LU_Type *pLu) +{ + pLu->DU_CTRL |= LU_DU_CTRL_DMASEL_MASK; +} + +/** + * @brief Disables the DMA Selection feature + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableDuCtrlDma(LU_Type *pLu) +{ + pLu->DU_CTRL &= ~LU_DU_CTRL_DMASEL_MASK; +} + +/** + * @brief Enables the Interrupt Selection feature + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableDuCtrlInt(LU_Type *pLu) +{ + pLu->DU_CTRL |= LU_DU_CTRL_INTSEL_MASK; +} + +/** + * @brief Disables the Interrupt Selection feature + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableDuCtrlInt(LU_Type *pLu) +{ + pLu->DU_CTRL &= ~LU_DU_CTRL_INTSEL_MASK; +} + +/** + * @brief Sets the OUTC Initial Polarity to low valid + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_SetDuCfgOutLow(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CTRL_OUTCINIT_MASK; +} + +/** + * @brief Sets the OUTC Initial Polarity to high valid + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_SetDuCfgOutCHigh(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CTRL_OUTCINIT_MASK; +} + +/** + * @brief Enables the Initial Sample feature + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableDuCfgInitSamp(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CTRL_SAMPINIT_MASK; +} + +/** + * @brief Disables the Initial Sample feature + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableDuCfgInitSamp(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CTRL_SAMPINIT_MASK; +} + +/** + * @brief Enables the Initial Shift Out feature + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableDuCfgInitShift(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CTRL_SHIFTOUTINIT_MASK; +} + +/** + * @brief Disables the Initial Shift Out feature + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableDuCfgInitShift(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CTRL_SHIFTOUTINIT_MASK; +} + +/** + * @brief Sets the Compare Type to Equal compare + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_SetDuCfgCompEqual(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CTRL_COMPTYPE_MASK; +} + +/** + * @brief Sets the Compare Type to Toggle compare + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_SetDuCfgCompToggle(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CTRL_COMPTYPE_MASK; +} + +/** + * @brief Sets the Compare Size + * + * @param pLu Pointer to the LU_Type instance + * @param u32Value The size to be set (1-32 bits) + */ +LOCAL_INLINE void LU_HWA_SetDuCfgCompSize(LU_Type *pLu, uint32_t u32Value) +{ + pLu->DU_CFG |= LU_DU_CTRL_COMPSIZE(u32Value); +} + +/** + * @brief Sets the Input Trigger Mode + * + * @param pLu Pointer to the LU_Type instance + * @param u32Value The trigger mode value to be set + */ +LOCAL_INLINE void LU_HWA_SetDuCfgInTrigerMode(LU_Type *pLu, uint32_t u32Value) +{ + pLu->DU_CFG |= LU_DU_CTRL_INPUTTRIG(u32Value); +} + +/** + * @brief Sets the Multi Pin Compare Type to All pin meet + * + * @param pLu Pointer to the LU_Type instance + * @param u32Value The value to be set for the COMPTOGTYPE field + */ +LOCAL_INLINE void LU_HWA_SetDuCfgCompPinAll(LU_Type *pLu, uint32_t u32Value) +{ + (void)u32Value; + pLu->DU_CFG |= LU_DU_CTRL_COMPTYPE_MASK; +} + +/** + * @brief Sets the Multi Pin Compare Type to Any pin meet + * + * @param pLu Pointer to the LU_Type instance + * @param u32Value The value to be set for the COMPTOGTYPE field + */ +LOCAL_INLINE void LU_HWA_SetDuCfgCompPinAny(LU_Type *pLu, uint32_t u32Value) +{ + (void)u32Value; + pLu->DU_CFG &= ~LU_DU_CTRL_COMPTYPE_MASK; +} + +/** + * @brief Enables Both Edge Mode + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableDuCfgEdge(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CTRL_EDGEMODE_MASK; +} + +/** + * @brief Disables Both Edge Mode + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableDuCfgEdge(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CTRL_EDGEMODE_MASK; +} + +/** + * @brief Sets the Sample Control in Flex Mode + * + * @param pLu Pointer to the LU_Type instance + * @param u32Value The value to be set for the FLEX_SAMP field + */ +LOCAL_INLINE void LU_HWA_SetDuCfgFlexSamp(LU_Type *pLu, LU_FlexSampType eFlexSampValue) +{ + pLu->DU_CFG |= LU_DU_CTRL_FLEX_SAMP(eFlexSampValue); +} + +/** + * @brief Sets the Clock Initial Polarity to high + * + * @param pLu Pointer to the LU_Type instance + * @param u32Value The value to be set for the CLKINIT field + */ +LOCAL_INLINE void LU_HWA_SetDuCfgClkHigh(LU_Type *pLu, uint32_t u32Value) +{ + pLu->DU_CFG |= LU_DU_CTRL_CLKINIT(u32Value); +} + +/** + * @brief Sets the Clock Initial Polarity to low + * + * @param pLu Pointer to the LU_Type instance + * @param u32Value The value to be set for the CLKINIT field + */ +LOCAL_INLINE void LU_HWA_SetDuCfgClkLow(LU_Type *pLu, uint32_t u32Value) +{ + pLu->DU_CFG &= ~LU_DU_CTRL_CLKINIT(u32Value); +} + +/** + * @brief Sets the LU Data Unit Operation Code + * + * @param pLu Pointer to the LU_Type instance + * @param u32Value The value to be set for the OPC field + */ +LOCAL_INLINE void LU_HWA_SetDuCfgOpc(LU_Type *pLu, LU_DU_OpcType eOpcValue) +{ + // Note: There seems to be an error in the original code, it should use LU_DU_CTRL_OPC_MASK instead of LU_DU_CTRL_FLEX_SAMP(u32Value) + pLu->DU_CFG |= LU_DU_CTRL_OPC(eOpcValue); +} + +/** + * @brief Sets the INPUTAMUX selection + * + * @param pLu Pointer to the LU_Type instance + * @param sel The selection for INPUTAMUX + */ +LOCAL_INLINE void LU_HWA_SetInputAmux(LU_Type *pLu, LU_DU_InputMuxType eInputMuxSel) +{ + pLu->DU_INPUT_SEL |= LU_DU_INPUT_SEL_INPUTAMUX(eInputMuxSel); +} + +/** + * @brief Sets the INPUTBMUX selection (same as INPUTAMUX) + * + * @param pLu Pointer to the LU_Type instance + * @param sel The selection for INPUTBMUX + */ +LOCAL_INLINE void LU_HWA_SetInputBmux(LU_Type *pLu, LU_DU_InputMuxType eInputMuxSel) +{ + pLu->DU_INPUT_SEL |= LU_DU_INPUT_SEL_INPUTBMUX(eInputMuxSel); +} + +/** + * @brief Sets the INPUTCMUX selection (same as INPUTAMUX) + * + * @param pLu Pointer to the LU_Type instance + * @param sel The selection for INPUTCMUX + */ +LOCAL_INLINE void LU_HWA_SetInputCmux(LU_Type *pLu, LU_DU_InputMuxType eInputMuxSel) +{ + pLu->DU_INPUT_SEL |= LU_DU_INPUT_SEL_INPUTCMUX(eInputMuxSel); +} + +/** + * @brief Clears the buffer + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_ClearBuffer(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CFG_BUFFERCLR_MASK; +} + +/** + * @brief Disables buffer clearing + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableBufferClear(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CFG_BUFFERCLR_MASK; +} + +/** + * @brief Enables Interrupt Match + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableInterruptMatch(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CFG_INTMATCH_MASK; +} + +/** + * @brief Disables Interrupt Match + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableInterruptMatch(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CFG_INTMATCH_MASK; +} + +/** + * @brief Enables Interrupt Underflow + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableInterruptUnderflow(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CFG_INTUNDERFLOW_MASK; +} + +/** + * @brief Disables Interrupt Underflow + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableInterruptUnderflow(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CFG_INTUNDERFLOW_MASK; +} + +/** + * @brief Enables Interrupt Overflow + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableInterruptOverflow(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CFG_INTOVERFLOW_MASK; +} + +/** + * @brief Disables Interrupt Overflow + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableInterruptOverflow(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CFG_INTOVERFLOW_MASK; +} + +/** + * @brief Enables DMA Match + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableDmaMatch(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CFG_DMAMATCH_MASK; +} + +/** + * @brief Disables DMA Match + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableDmaMatch(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CFG_DMAMATCH_MASK; +} + +/** + * @brief Enables DMA Underflow + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableDmaUnderflow(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CFG_DMAUNDERFLOW_MASK; +} + +/** + * @brief Disables DMA Underflow + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableDmaUnderflow(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CFG_DMAUNDERFLOW_MASK; +} + +/** + * @brief Enables DMA Overflow + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_EnableDmaOverflow(LU_Type *pLu) +{ + pLu->DU_CFG |= LU_DU_CFG_DMAOVERFLOW_MASK; +} + +/** + * @brief Disables DMA Overflow + * + * @param pLu Pointer to the LU_Type instance + */ +LOCAL_INLINE void LU_HWA_DisableDmaOverflow(LU_Type *pLu) +{ + pLu->DU_CFG &= ~LU_DU_CFG_DMAOVERFLOW_MASK; +} + +/** + * @brief Sets the Start Counter Config + * + * @param pLu Pointer to the LU_Type instance + * @param config The configuration value for the start counter + */ +LOCAL_INLINE void LU_HWA_SetStartCounterConfig(LU_Type *pLu, uint8_t config) +{ + pLu->DU_CFG = (pLu->DU_CFG & ~LU_DU_CFG_STARTCFG_MASK) | LU_DU_CFG_STARTCFG(config); +} + +/** + * @brief Sets the Transmit Bit Number + * + * @param pLu Pointer to the LU_Type instance + * @param bitNumber The bit number to be transmitted + */ +LOCAL_INLINE void LU_HWA_SetTransmitBitNumber(LU_Type *pLu, uint8_t bitNumber) +{ + pLu->DU_CFG = (pLu->DU_CFG & ~LU_DU_CFG_BITCFG_MASK) | LU_DU_CFG_BITCFG(bitNumber); +} + +/** + * @brief Sets the value of the Data Unit Data0 Register + * + * @param pLu Pointer to the LU_Type instance + * @param data The value to be written to the DATA0 register + */ +LOCAL_INLINE void LU_HWA_SetLuDuData0(LU_Type *pLu, uint32_t data) +{ + pLu->DU_DATA0 = data; +} + +/** + * @brief Gets the value of the Data Unit Data0 Register + * + * @param pLu Pointer to the LU_Type instance + * @return The value of the DATA0 register + */ +LOCAL_INLINE uint32_t LU_HWA_GetLuDuData0(LU_Type *pLu) +{ + return pLu->DU_DATA0; +} + +/** + * @brief Sets the value of the Data Unit Data1 Register + * + * @param pLu Pointer to the LU_Type instance + * @param data The value to be written to the DATA1 register + */ +LOCAL_INLINE void LU_HWA_SetLuDuData1(LU_Type *pLu, uint32_t data) +{ + pLu->DU_DATA1 = data; +} + +/** + * @brief Gets the value of the Data Unit Data1 Register + * + * @param pLu Pointer to the LU_Type instance + * @return The value of the DATA1 register + */ +LOCAL_INLINE uint32_t LU_HWA_GetLuDuData1(LU_Type *pLu) +{ + return pLu->DU_DATA1; +} + +/** + * @brief Sets the value of the Data Unit Data2 Register + * + * @param pLu Pointer to the LU_Type instance + * @param data The value to be written to the DATA2 register + */ +LOCAL_INLINE void LU_HWA_SetLuDuData2(LU_Type *pLu, uint32_t data) +{ + pLu->DU_DATA2 = data; +} + +/** + * @brief Gets the value of the Data Unit Data2 Register + * + * @param pLu Pointer to the LU_Type instance + * @return The value of the DATA2 register + */ +LOCAL_INLINE uint32_t LU_HWA_GetLuDuData2(LU_Type *pLu) +{ + return pLu->DU_DATA2; +} + +/** + * @brief Gets the value of the Data Unit Data3 Register + * + * @param pLu Pointer to the LU_Type instance + * @return The value of the DATA3 register + */ +LOCAL_INLINE uint32_t LU_HWA_GetLuDuData3(LU_Type *pLu) +{ + return pLu->DU_DATA3; +} + +/** + * @brief Gets the value of the Data Unit Data4 Register + * + * @param pLu Pointer to the LU_Type instance + * @return The value of the DATA4 register + */ +LOCAL_INLINE uint32_t LU_HWA_GetLuDuData4(LU_Type *pLu) +{ + return pLu->DU_DATA4; +} + +/** + * @brief Gets the value of the Data Unit Data5 Register + * + * @param pLu Pointer to the LU_Type instance + * @return The value of the DATA5 register + */ +LOCAL_INLINE uint32_t LU_HWA_GetLuDuData5(LU_Type *pLu) +{ + return pLu->DU_DATA5; +} + +/** + * @brief Gets the value of the Data Unit Data6 Register + * + * @param pLu Pointer to the LU_Type instance + * @return The value of the DATA6 register + */ +LOCAL_INLINE uint32_t LU_HWA_GetLuDuData6(LU_Type *pLu) +{ + return pLu->DU_DATA6; +} + +/** + * @brief Sets the value of the Data Unit Data7 Register + * + * @param pLu Pointer to the LU_Type instance + * @param data The value to be written to the DATA7 register + */ +LOCAL_INLINE void LU_HWA_SetLuDuData7(LU_Type *pLu, uint32_t data) +{ + pLu->DU_DATA7 = data; +} + +/** + * @brief Gets the value of the Data Unit Data7 Register + * + * @param pLu Pointer to the LU_Type instance + * @return The value of the DATA7 register + */ +LOCAL_INLINE uint32_t LU_HWA_GetLuDuData7(LU_Type *pLu) +{ + return pLu->DU_DATA7; +} + +/** @}*/ + + +#endif /* #if ELU_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_LU_H_ */ diff --git a/Inc/HwA_enet.h b/Inc/HwA_enet.h new file mode 100644 index 0000000..d4d942c --- /dev/null +++ b/Inc/HwA_enet.h @@ -0,0 +1,13240 @@ +/** + * @file HwA_enet.h + * @author Flagchip + * @brief ENET hardware access layer + * @version 2.0.0 + * @date 2024-10-12 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip085 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip085 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_ENET_H_ +#define _HWA_ENET_H_ + +#include "device_header.h" + +#if ENET_INSTANCE_COUNT > 0u + + +/** + * @defgroup HwA_enet HwA_enet + * @ingroup module_driver_enet + * @{ + */ + +/** + * @brief ENE MAC status type definition + * + */ +typedef enum +{ + ENET_MAC_STATUS_IDLE = 0u, + ENET_MAC_STATUS_BUSY = 1u +} ENET_MAC_StatusType; + +/** + * @brief ENET MAC source address insertion control type definition + * + */ +typedef enum +{ + ENET_MAC_SRC_ADDR_CTRL_BY_INPUT_SIGNAL = 0u, + ENET_MAC_SRC_ADDR_INSERT_BY_MAC_ADDR_IDX_0 = 2u, + ENET_MAC_SRC_ADDR_REPLACE_BY_MAC_ADDR_IDX_0 = 3u, + ENET_MAC_SRC_ADDR_INSERT_BY_MAC_ADDR_IDX_1 = 6u, + ENET_MAC_SRC_ADDR_REPLACE_BY_MAC_ADDR_IDX_1 = 7u +} ENET_MAC_SrcAddrCtrlType; + +/** + * @brief MAC inter packet gap type definition + * + */ +typedef enum +{ + ENET_MAC_INTER_PACKET_GAP_96_BIT = 0u, + ENET_MAC_INTER_PACKET_GAP_88_BIT = 1u, + ENET_MAC_INTER_PACKET_GAP_80_BIT = 2u, + ENET_MAC_INTER_PACKET_GAP_72_BIT = 3u, + ENET_MAC_INTER_PACKET_GAP_64_BIT = 4u, + ENET_MAC_INTER_PACKET_GAP_56_BIT = 5u, + ENET_MAC_INTER_PACKET_GAP_48_BIT = 6u, + ENET_MAC_INTER_PACKET_GAP_40_BIT = 7u +} ENET_MAC_InterPacketGapType; + +/** + * @brief MAC extend inner packet gap type definition + * + */ +typedef enum +{ + ENET_MAC_EXT_INTER_PACKET_GAP_104_BIT = 0u, + ENET_MAC_EXT_INTER_PACKET_GAP_112_BIT = 1u, + ENET_MAC_EXT_INTER_PACKET_GAP_120_BIT = 2u, + ENET_MAC_EXT_INTER_PACKET_GAP_128_BIT = 3u, + ENET_MAC_EXT_INTER_PACKET_GAP_136_BIT = 4u, + ENET_MAC_EXT_INTER_PACKET_GAP_144_BIT = 5u, + ENET_MAC_EXT_INTER_PACKET_GAP_152_BIT = 6u, + ENET_MAC_EXT_INTER_PACKET_GAP_160_BIT = 7u, + ENET_MAC_EXT_INTER_PACKET_GAP_168_BIT = 8u, + ENET_MAC_EXT_INTER_PACKET_GAP_176_BIT = 9u, + ENET_MAC_EXT_INTER_PACKET_GAP_184_BIT = 10u, + ENET_MAC_EXT_INTER_PACKET_GAP_192_BIT = 11u, + ENET_MAC_EXT_INTER_PACKET_GAP_200_BIT = 12u, + ENET_MAC_EXT_INTER_PACKET_GAP_208_BIT = 13u, + ENET_MAC_EXT_INTER_PACKET_GAP_216_BIT = 14u, + ENET_MAC_EXT_INTER_PACKET_GAP_224_BIT = 15u, + ENET_MAC_EXT_INTER_PACKET_GAP_232_BIT = 16u, + ENET_MAC_EXT_INTER_PACKET_GAP_240_BIT = 17u, + ENET_MAC_EXT_INTER_PACKET_GAP_248_BIT = 18u, + ENET_MAC_EXT_INTER_PACKET_GAP_256_BIT = 19u, + ENET_MAC_EXT_INTER_PACKET_GAP_264_BIT = 20u, + ENET_MAC_EXT_INTER_PACKET_GAP_272_BIT = 21u, + ENET_MAC_EXT_INTER_PACKET_GAP_280_BIT = 22u, + ENET_MAC_EXT_INTER_PACKET_GAP_288_BIT = 23u, + ENET_MAC_EXT_INTER_PACKET_GAP_296_BIT = 24u, + ENET_MAC_EXT_INTER_PACKET_GAP_304_BIT = 25u, + ENET_MAC_EXT_INTER_PACKET_GAP_312_BIT = 26u, + ENET_MAC_EXT_INTER_PACKET_GAP_320_BIT = 27u, + ENET_MAC_EXT_INTER_PACKET_GAP_328_BIT = 28u, + ENET_MAC_EXT_INTER_PACKET_GAP_336_BIT = 29u, + ENET_MAC_EXT_INTER_PACKET_GAP_344_BIT = 30u, + ENET_MAC_EXT_INTER_PACKET_GAP_352_BIT = 31u +} ENET_MAC_ExtInterPacketGapType; + +/** + * @brief MAC speed mode type definition + * + */ +typedef enum +{ + ENET_MAC_SPEED_1000MBPS = 0u, + ENET_MAC_SPEED_2500MBPS = 1u, + ENET_MAC_SPEED_10MBPS = 2u, + ENET_MAC_SPEED_100MBPS = 3u +} ENET_MAC_SpeedType; + +/** + * @brief MAC duplex mode type definition + * + */ +typedef enum +{ + ENET_MAC_HALF_DUPLEX = 0u, + ENET_MAC_FULL_DUPLEX = 1u +} ENET_MAC_DuplexModeType; + +/** + * @brief MAC back off limit type definition + * + */ +typedef enum +{ + ENET_MAC_BACK_OFF_LIMIT_10_SLOT = 0u, + ENET_MAC_BACK_OFF_LIMIT_8_SLOT = 1u, + ENET_MAC_BACK_OFF_LIMIT_4_SLOT = 2u, + ENET_MAC_BACK_OFF_LIMIT_1_SLOT = 3u +} ENET_MAC_BackOffLimitType; + +/** + * @brief MAC slow protocol detect type definition + * + */ +typedef enum +{ + ENET_MAC_SLOW_PROTOCOL_DETECT_STANDARD = 0u, + ENET_MAC_SLOW_PROTOCOL_DETECT_EXTENDED = 1u +} ENET_MAC_SlowProtocolDetectType; + +/** + * @brief MAC address filter mode type definition + * + */ +typedef enum +{ + ENET_MAC_ADDR_FILTER_DIRECT = 0u, + ENET_MAC_ADDR_FILTER_INVERSE = 1u +} ENET_MAC_AddrFilterModeType; + +/** + * @brief MAC control packets filter mode type definition + * + */ +typedef enum +{ + ENET_MAC_CTRL_PACKET_FILTER_ALL = 0u, + ENET_MAC_CTRL_PACKET_FILTER_PAUSE_PACKET = 1u, + ENET_MAC_CTRL_PACKET_FORWARD_ALL = 2u, + ENET_MAC_CTRL_PACKET_ADDR_FILTER = 3u +} ENET_MAC_CtrlPacketFilterModeType; + +/** + * @brief MAC perfect or hash filter mode type definition + * + */ +typedef enum +{ + ENET_MAC_USE_PERFECT_FILTER = 0u, + ENET_MAC_USE_HASH_FILTER = 1u +} ENET_MAC_HashOrPerfectModeType; + +/** + * @brief MAC watchdog timer type definition + * + */ +typedef enum +{ + ENET_MAC_WDG_TIMER_SIZE_2KB = 0u, + ENET_MAC_WDG_TIMER_SIZE_3KB = 1u, + ENET_MAC_WDG_TIMER_SIZE_4KB = 2u, + ENET_MAC_WDG_TIMER_SIZE_5KB = 3u, + ENET_MAC_WDG_TIMER_SIZE_6KB = 4u, + ENET_MAC_WDG_TIMER_SIZE_7KB = 5u, + ENET_MAC_WDG_TIMER_SIZE_8KB = 6u, + ENET_MAC_WDG_TIMER_SIZE_9KB = 7u, + ENET_MAC_WDG_TIMER_SIZE_10KB = 8u, + ENET_MAC_WDG_TIMER_SIZE_11KB = 9u, + ENET_MAC_WDG_TIMER_SIZE_12KB = 10u, + ENET_MAC_WDG_TIMER_SIZE_13KB = 11u, + ENET_MAC_WDG_TIMER_SIZE_14KB = 12u, + ENET_MAC_WDG_TIMER_SIZE_15KB = 13u +} ENET_MAC_WDGTimerSizeType; + +/** + * @brief MAC VLAN tag strip type + * + */ +typedef enum +{ + ENET_MAC_VLAN_TAG_STRIP_NEVER = 0u, + ENET_MAC_VLAN_TAG_STRIP_FILTER_PASS = 1u, + ENET_MAC_VLAN_TAG_STRIP_FILTER_FAIL = 2u, + ENET_MAC_VLAN_TAG_STRIP_ALWAYS = 3u +} ENET_MAC_VLANTagStripModeType; + +/** + * @brief MAC VLAN indirect registers access command type + * + */ +typedef enum +{ + ENET_MAC_VLAN_COMMAND_WRITE = 0u, + ENET_MAC_VLAN_COMMAND_READ = 1u +} ENET_MAC_VLANCommandType; + +/** + * @brief MAC VLAN incl indirect registers access command type + * + */ +typedef enum +{ + ENET_MAC_VLAN_INCL_COMMAND_READ = 0u, + ENET_MAC_VLAN_INCL_COMMAND_WRITE = 1u +} ENET_MAC_VLANInclCommandType; + +/** + * @brief MAC VLAN tag control type + * + */ +typedef enum +{ + ENET_MAC_VLAN_TAG_NO_OPERATION = 0u, + ENET_MAC_VLAN_TAG_DELETION = 1u, + ENET_MAC_VLAN_TAG_INSERTION = 2u, + ENET_MAC_VLAN_TAG_REPLACEMENT = 3u +} ENET_MAC_VLANTagCtrlType; + +/** + * @brief MAC VLAN tag type + * S-VLAN IEEE802.1ad (Q-in-Q) + * C-VLAN IEEE802.1Q + */ +typedef enum +{ + ENET_MAC_VLAN_TYPE_C_VLAN = 0u, + ENET_MAC_VLAN_TYPE_S_VLAN = 1u +} ENET_MAC_VLANType; + +/** + * @brief MAC VLAN compare mode type + * + */ +typedef enum +{ + ENET_MAC_VLAN_16BITS_COMPARE = 0u, + ENET_MAC_VLAN_12BITS_COMPARE = 1u +} ENET_MAC_VLANCompareType; + +/** + * @brief MAC VLAN perfect filter group index type + * + */ +typedef enum +{ + ENET_MAC_VLAN_FILTER_GROUP_0 = 0u, + ENET_MAC_VLAN_FILTER_GROUP_1 = 1u, + ENET_MAC_VLAN_FILTER_GROUP_2 = 2u, + ENET_MAC_VLAN_FILTER_GROUP_3 = 3u +} ENET_MAC_VLANFilterGroupType; + +/** + * @brief ENET flow control pause threshold type + * + */ +typedef enum +{ + ENET_MAC_PAUSE_THRESHOLD_4SLOT_TIMES = 0u, + ENET_MAC_PAUSE_THRESHOLD_28SLOT_TIMES = 1u, + ENET_MAC_PAUSE_THRESHOLD_36SLOT_TIMES = 2u, + ENET_MAC_PAUSE_THRESHOLD_144SLOT_TIMES = 3u, + ENET_MAC_PAUSE_THRESHOLD_256SLOT_TIMES = 4u, + ENET_MAC_PAUSE_THRESHOLD_512SLOT_TIMES = 5u +} ENET_MAC_PauseThresholdType; + +/** + * @brief MAC TX packet controller status type + * + */ +typedef enum +{ + ENET_MAC_TX_PACKET_CONTROLLER_IDLE = 0u, + ENET_MAC_TX_PACKET_CONTROLLER_WAIT = 1u, + ENET_MAC_TX_PACKET_CONTROLLER_TRANSFER_PAUSE_PACKET = 2u, + ENET_MAC_TX_PACKET_CONTROLLER_TRANSFER_INPUT_PACKET = 3u +} ENET_MAC_TxPacketControllerStatusType; + +/** + * @brief MTL queue enable type + * + */ +typedef enum +{ + ENET_MTL_QUEUE_DISABLE = 0u, + ENET_MTL_QUEUE_ENABLE_AV_MODE = 1u, + ENET_MTL_QUEUE_ENABLE_GENERIC = 2u +} ENET_MTL_QueueEnableType; + +/** + * @brief Tagged PTP over Ethernet packets queuing control type + * + */ +typedef enum +{ + ENET_MAC_VLAN_PTPOE_ROUTED_AS_GENERIC = 0u, + ENET_MAC_VLAN_PTPOE_ROUTED_TO_PTP_QUEUE = 1u, + ENET_MAC_VLAN_PTPOE_ROUTED_BY_PRIORITY = 2u +} ENET_MAC_PTPoEQueueCtrlType; + +#if ENET_SUPPORT_RGMII +/** + * @brief MAC RGMII clock select type + * + */ +typedef enum +{ + ENET_MAC_RGMII_CLK_SEL_DISABLE = 0u, + ENET_MAC_RGMII_CLK_SEL_ENET_REF_CLK = 1u, + ENET_MAC_RGMII_CLK_SEL_PLL0DIVH = 2u, + ENET_MAC_RGMII_CLK_SEL_PLL1DIVH = 3u +} ENET_MAC_RGMIIClkSelType; +#endif + +/** + * @brief MAC TX clock select type + * + */ +typedef enum +{ + ENET_MAC_TX_CLK_SEL_DISABLE = 0u, + ENET_MAC_TX_CLK_SEL_PLL0DIVL = 1u, + ENET_MAC_TX_CLK_SEL_FOSC = 2u, + ENET_MAC_TX_CLK_SEL_ENET_TX_CLK = 3u +} ENET_MAC_TxClkSelType; + +/** + * @brief MAC PHY interface mode type + * + */ +typedef enum +{ + ENET_MAC_PHY_MII = 0u, + ENET_MAC_PHY_RGMII = 1u, + ENET_MAC_PHY_RMII = 4u +} ENET_MAC_MiiModeType; + +/** + * @brief MAC MDIO access clock source range type + * + */ +typedef enum +{ + ENET_MAC_CSR_CLOCK_RANGE_60_100MHZ = 0u, + ENET_MAC_CSR_CLOCK_RANGE_100_150MHZ = 1u, + ENET_MAC_CSR_CLOCK_RANGE_20_35MHZ = 2u, + ENET_MAC_CSR_CLOCK_RANGE_35_60MHZ = 3u, + ENET_MAC_CSR_CLOCK_RANGE_150_250MHZ = 4u, + ENET_MAC_CSR_CLOCK_RANGE_250_300MHZ = 5u +} ENET_MAC_CSRClockRangeType; + +/** + * @brief MAC MDIO bus operation command type + * + */ +typedef enum +{ + ENET_MAC_PHY_OPERATION_WRITE = 1u, + ENET_MAC_PHY_OPERATION_POST_READ_INCR_ADDR_FOR_CLAUSE_45 = 2u, + ENET_MAC_PHY_OPERATION_READ = 3u +} ENET_MAC_PhyOperationCmdType; + +/** + * @brief MAC MDIO bus clause type + * + */ +typedef enum +{ + ENET_MAC_PHY_CLAUSE_22 = 0u, + ENET_MAC_PHY_CLAUSE_45 = 1u +} ENET_MAC_PhyClauseVersionType; + +/** + * @brief MAC address destination or source type + * + */ +typedef enum +{ + ENET_MAC_ADDR_TYPE_DEST = 0u, + ENET_MAC_ADDR_TYPE_SRC = 1u +} ENET_MAC_AddrType; + +/** + * @brief MMC counter present level type + * + */ +typedef enum +{ + ENET_MAC_MMC_COUNTER_PRESET_LEVEL_HALF = 0u, + ENET_MAC_MMC_COUNTER_PRESET_LEVEL_FULL = 1u +} ENET_MAC_MmcCntPresetLevelType; + +/** + * @brief MAC layer 4 filter protocol type + * + */ +typedef enum +{ + ENET_MAC_LAYER_4_PROTOCOL_TCP = 0u, + ENET_MAC_LAYER_4_PROTOCOL_UDP = 1u +} ENET_MAC_Layer4ProtocolType; + +/** + * @brief MAC layer 3 filter protocol type + * + */ +typedef enum +{ + ENET_MAC_LAYER_3_PROTOCOL_IPV4 = 0u, + ENET_MAC_LAYER_3_PROTOCOL_IPV6 = 1u +} ENET_MAC_Layer3ProtocolType; + +/** + * @brief MAC layer3 layer 4 filter group index type + * + */ +typedef enum +{ + ENET_MAC_L3_L4_FILTER_GROUP_0 = 0u, + ENET_MAC_L3_L4_FILTER_GROUP_1 = 1u, + ENET_MAC_L3_L4_FILTER_GROUP_2 = 2u, + ENET_MAC_L3_L4_FILTER_GROUP_3 = 3u +} ENET_MAC_L3L4FilterGroupType; + +/** + * @brief MAC MMC transmit statistics counter type + * + */ +typedef enum +{ + ENET_CTR_TX_OCTET_COUNT_GOOD_BAD = 0u, + ENET_CTR_TX_PACKET_COUNT_GOOD_BAD, + ENET_CTR_TX_BROADCAST_PACKETS_GOOD, + ENET_CTR_TX_MULTICAST_PACKETS_GOOD, + ENET_CTR_TX_64OCTETS_PACKETS_GOOD_BAD, + ENET_CTR_TX_65TO127OCTETS_PACKETS_GOOD_BAD, + ENET_CTR_TX_128TO255OCTETS_PACKETS_GOOD_BAD, + ENET_CTR_TX_256TO511OCTETS_PACKETS_GOOD_BAD, + ENET_CTR_TX_512TO1023OCTETS_PACKETS_GOOD_BAD, + ENET_CTR_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD, + ENET_CTR_TX_UNICAST_PACKETS_GOOD_BAD, + ENET_CTR_TX_MULTICAST_PACKETS_GOOD_BAD, + ENET_CTR_TX_BROADCAST_PACKETS_GOOD_BAD, + ENET_CTR_TX_UNDERFLOW_ERROR_PACKETS, + ENET_CTR_TX_SINGLE_COLLISION_GOOD_PACKETS, + ENET_CTR_TX_MULTIPLE_COLLISION_GOOD_PACKETS, + ENET_CTR_TX_DEFERRED_PACKETS, + ENET_CTR_TX_LATE_COLLISION_PACKETS, + ENET_CTR_TX_EXCESSIVE_COLLISION_PACKETS, + ENET_CTR_TX_CARRIER_ERROR_PACKETS, + ENET_CTR_TX_OCTET_COUNT_GOOD, + ENET_CTR_TX_PACKET_COUNT_GOOD, + ENET_CTR_TX_EXCESSIVE_DEFERRAL_ERROR, + ENET_CTR_TX_PAUSE_PACKETS, + ENET_CTR_TX_VLAN_PACKETS_GOOD, + ENET_CTR_TX_OSIZE_PACKETS_GOOD, +} Enet_MMCTxCounterType; + +/** + * @brief MAC receive statistics counter type + * + */ +typedef enum +{ + ENET_CTR_RX_PACKETS_COUNT_GOOD_BAD = 0u, + ENET_CTR_RX_OCTET_COUNT_GOOD_BAD, + ENET_CTR_RX_OCTET_COUNT_GOOD, + ENET_CTR_RX_BROADCAST_PACKETS_GOOD, + ENET_CTR_RX_MULTICAST_PACKETS_GOOD, + ENET_CTR_RX_CRC_ERROR_PACKETS, + ENET_CTR_RX_ALIGNMENT_ERROR_PACKETS, + ENET_CTR_RX_RUNT_ERROR_PACKETS, + ENET_CTR_RX_JABBER_ERROR_PACKETS, + ENET_CTR_RX_UNDERSIZE_PACKETS_GOOD, + ENET_CTR_RX_OVERSIZE_PACKETS_GOOD, + ENET_CTR_RX_64OCTETS_PACKETS_GOOD_BAD, + ENET_CTR_RX_65TO127OCTETS_PACKETS_GOOD_BAD, + ENET_CTR_RX_128TO255OCTETS_PACKETS_GOOD_BAD, + ENET_CTR_RX_256TO511OCTETS_PACKETS_GOOD_BAD, + ENET_CTR_RX_512TO1023OCTETS_PACKETS_GOOD_BAD, + ENET_CTR_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD, + ENET_CTR_RX_UNICAST_PACKETS_GOOD, + ENET_CTR_RX_LENGTH_ERROR_PACKETS, + ENET_CTR_RX_OUT_OF_RANGE_TYPE_PACKETS, + ENET_CTR_RX_PAUSE_PACKETS, + ENET_CTR_RX_FIFO_OVERFLOW_PACKETS, + ENET_CTR_RX_VLAN_PACKETS_GOOD_BAD, + ENET_CTR_RX_WATCHDOG_ERROR_PACKETS, + ENET_CTR_RX_RECEIVE_ERROR_PACKETS, + ENET_CTR_RX_CONTROL_PACKETS_GOOD, +} Enet_MMCRxCounterType; + +/** + * @brief PTP TX status mode type + * + */ +typedef enum +{ + ENET_MAC_TX_TIMESTAMP_STATUS_MODE_PRESERVE = 0u, + ENET_MAC_TX_TIMESTAMP_STATUS_MODE_OVERWRITE = 1u +} ENET_MAC_TxTimestampStatusModeType; + +/** + * @brief PTP system time input source type + * + */ +typedef enum +{ + ENET_MAC_SYSTEM_TIME_INPUT_INTERNAL = 0u, + ENET_MAC_SYSTEM_TIME_INPUT_EXTERNAL = 1u +} ENET_MAC_SystemTimeInputType; + +/** + * @brief PTP IEEE1588 version type + * + */ +typedef enum +{ + ENET_MAC_PTP_IEEE_1588_V1 = 0u, + ENET_MAC_PTP_IEEE_1588_V2 = 1u, +} ENET_MAC_PTPVersionType; + +/** + * @brief PTP counter rollover mode type + * + */ +typedef enum +{ + ENET_MAC_TIMESTAMP_ROLLOVER_BINARY = 0u, + ENET_MAC_TIMESTAMP_ROLLOVER_DIGITAL = 1u, +} ENET_MAC_TimestampRolloverType; + +/** + * @brief PTP timestamp update mode type + * + */ +typedef enum +{ + ENET_MAC_TIMESTAMP_UPDATE_COARSE = 0u, + ENET_MAC_TIMESTAMP_UPDATE_FINE = 1u +} ENET_MAC_TimestampUpdateMethodType; + +/** + * @brief PTP system time offset update operation type + * + */ +typedef enum +{ + ENET_MAC_SYSTEM_TIME_ADD_TIME = 0u, + ENET_MAC_SYSTEM_TIME_SUBTRACT_TIME = 1u +} ENET_MAC_SystemTimeOperationType; + +/** + * @brief PTP PPS channel type + * + */ +typedef enum +{ + ENET_MAC_PPS_CHANNEL_0 = 0u, + ENET_MAC_PPS_CHANNEL_1 = 1u, + ENET_MAC_PPS_CHANNEL_2 = 2u, + ENET_MAC_PPS_CHANNEL_3 = 3u +} ENET_MAC_PPSChannelType; + +/** + * @brief PTP PPS channel operation mode type + * + */ +typedef enum +{ + ENET_MAC_PPS_MODE_PPS = 0u, + ENET_MAC_PPS_MODE_MCGR = 1u +} ENET_MAC_PPSModeType; + +/** + * @brief PPS target time mode type + * + */ +typedef enum +{ + ENET_MAC_PPS_TARGET_TIME_ONLY_INT = 0u, + ENET_MAC_PPS_TARGET_TIME_MCGR = 1u, + ENET_MAC_PPS_TARGET_TIME_INT_ST = 2u, + ENET_MAC_PPS_TARGET_TIME_ONLY_ST = 3u +} ENET_MAC_PPSTargetTimeModeType; + +/** + * @brief PTP fixed PPS output frequency control type + * + */ +typedef enum +{ + ENET_MAC_PPS_BINARY_1HZ_DIGITAL_NONE = 0u, /**< Fixed PPS output 1HZ in binary rollover mode, no output in digital mode. */ + ENET_MAC_PPS_BINARY_2HZ_DIGITAL_1HZ = 1u, /**< Fixed PPS output 2HZ in binary rollover mode, 1HZ in digital mode. */ + ENET_MAC_PPS_BINARY_4HZ_DIGITAL_2HZ = 2u, /**< Fixed PPS output 4HZ in binary rollover mode, 2HZ in digital mode. */ + ENET_MAC_PPS_BINARY_8HZ_DIGITAL_4HZ = 3u, /**< Fixed PPS output 8HZ in binary rollover mode, 4HZ in digital mode. */ + ENET_MAC_PPS_BINARY_16HZ_DIGITAL_8HZ = 4u, /**< Fixed PPS output 16HZ in binary rollover mode, 8HZ in digital mode. */ + ENET_MAC_PPS_BINARY_32HZ_DIGITAL_16HZ = 5u, /**< Fixed PPS output 32HZ in binary rollover mode, 16HZ in digital mode. */ + ENET_MAC_PPS_BINARY_64HZ_DIGITAL_32HZ = 6u, /**< Fixed PPS output 64HZ in binary rollover mode, 32HZ in digital mode. */ + ENET_MAC_PPS_BINARY_128HZ_DIGITAL_64HZ = 7u, /**< Fixed PPS output 128HZ in binary rollover mode, 64HZ in digital mode. */ + ENET_MAC_PPS_BINARY_256HZ_DIGITAL_128HZ = 8u, /**< Fixed PPS output 256HZ in binary rollover mode, 128HZ in digital mode. */ + ENET_MAC_PPS_BINARY_512HZ_DIGITAL_256HZ = 9u, /**< Fixed PPS output 512HZ in binary rollover mode, 256HZ in digital mode. */ + ENET_MAC_PPS_BINARY_1024HZ_DIGITAL_512HZ = 10u, /**< Fixed PPS output 1024HZ in binary rollover mode, 512HZ in digital mode. */ + ENET_MAC_PPS_BINARY_2048HZ_DIGITAL_1024HZ = 11u, /**< Fixed PPS output 2048HZ in binary rollover mode, 1024HZ in digital mode. */ + ENET_MAC_PPS_BINARY_4096HZ_DIGITAL_2048HZ = 12u, /**< Fixed PPS output 4096HZ in binary rollover mode, 2048HZ in digital mode. */ + ENET_MAC_PPS_BINARY_8192HZ_DIGITAL_4096HZ = 13u, /**< Fixed PPS output 8192HZ in binary rollover mode, 4096HZ in digital mode. */ + ENET_MAC_PPS_BINARY_16384HZ_DIGITAL_8192HZ = 14u, /**< Fixed PPS output 16384HZ in binary rollover mode, 8192HZ in digital mode. */ + ENET_MAC_PPS_BINARY_32768HZ_DIGITAL_16384HZ = 15u /**< Fixed PPS output 32768HZ in binary rollover mode, 16384HZ in digital mode. */ +} ENET_MAC_PPSFreqCtrlType; + +/** + * @brief PTP flexible PPS output command type + * + */ +typedef enum +{ + ENET_MAC_PPS_NO_COMMAND = 0u, + ENET_MAC_PPS_START_SINGLE_PULSE = 1u, + ENET_MAC_PPS_START_PULSE_TRAIN = 2u, + ENET_MAC_PPS_CANCEL_START = 3u, + ENET_MAC_PPS_STOP_PULSE_TRAIN_AT_TIME = 4u, + ENET_MAC_PPS_STOP_PULSE_TRAIN_IMMEDIATELY = 5u, + ENET_MAC_PPS_CANCEL_STOP_PULSE_TRAIN = 6u +} ENET_MAC_PPSCmdType; + +/** + * @brief PTP flexible MCGR command type + * + */ +typedef enum +{ + ENET_MAC_MCGR_OPERATION_NOT_CARRIED_OUT = 0u, + ENET_MAC_MCGR_CAPTURE_RISING_EDGE = 1u, + ENET_MAC_MCGR_CAPTURE_FALLING_EDGE = 2u, + ENET_MAC_MCGR_CAPTURE_BOTH_EDGE = 3u, + ENET_MAC_MCGR_TOGGLE_OUTPUT_ON_COMPARE = 9u, + ENET_MAC_MCGR_PULSE_OUTPUT_LOW_ON_COMPARE = 10u, + ENET_MAC_MCGR_PULSE_OUTPUT_HIGH_ON_COMPARE = 11u +} ENET_MAC_MCGRCmdType; + +/** + * @brief PTP snapshot packet select type + * + */ +typedef enum +{ + ENET_MAC_PTP_SNAPSHOT_FOR_E2E = (0x0u << 14u), + ENET_MAC_PTP_SNAPSHOT_FOR_SYNC = (0x1u << 14u), + ENET_MAC_PTP_SNAPSHOT_FOR_DELAYREQ = (0x3u << 14u), + ENET_MAC_PTP_SNAPSHOT_FOR_ALL_PTP = (0x4u << 14u), + ENET_MAC_PTP_SNAPSHOT_FOR_SLAVE_NODE_EVENT = (0x5u << 14u), + ENET_MAC_PTP_SNAPSHOT_FOR_MASTER_NODE_EVENT = (0x7u << 14u), + ENET_MAC_PTP_SNAPSHOT_FOR_E2E_EVENT = (0x8u << 14u), + ENET_MAC_PTP_SNAPSHOT_FOR_P2P_EVENT = (0xCu << 14u), +} ENET_MAC_PTPSnapshotMsgType; + +/** + * @brief PTP snapshot network layer select type + * + */ +typedef enum +{ + ENET_MAC_PTP_OVER_ETHERNET = ENET_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK, + ENET_MAC_PTP_OVER_IPV4 = ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK, + ENET_MAC_PTP_OVER_IPV6 = ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK, +} ENET_MAC_PTPPacketLayerType; + +/** + * @brief MAC PTP clock select type + * + */ +typedef enum +{ + ENET_MAC_PTP_CLK_SEL_PCC = 0u, + ENET_MAC_PTP_CLK_SEL_TX_CLK = 1u +#if ENET_SUPPORT_REFCLK_PIN + , + ENET_MAC_PTP_CLK_SEL_REFCLK_PIN = 2u +#endif +} ENET_MAC_PTPClkSelType; + +/** + * @brief PTP PPS channel direction type + * + */ +typedef enum +{ + ENET_PTP_PPS_DIR_INPUT = 0u, + ENET_PTP_PPS_DIR_OUTPUT = 1u +} ENET_MAC_PPSPinDirType; + +/** + * @brief ENET MTL queue type + * + */ +typedef enum +{ + ENET_MTL_QUEUE_0 = 0u, + ENET_MTL_QUEUE_1 = 1u +} ENET_MTL_QueueType; + +/** + * @brief ENET TX schedule algorithm type + * + */ +typedef enum +{ + ENET_MTL_SCHED_ALGO_WRR = 0u, /**< Weighted round robin algorithm. */ + ENET_MTL_SCHED_ALGO_SP = 3u /**< Strict priority algorithm. */ +} ENET_MTL_TxScheduleAlgorithmType; + +/** + * @brief ENET RX arbitration type + * + */ +typedef enum +{ + ENET_MTL_RX_ARBITRATION_STRICT_POLICY = 0u, + ENET_MTL_RX_ARBITRATION_WEIGHTED_STRICT_POLICY = 1u +} ENET_MTL_RxArbitrationAlgorithmType; + +/** + * @brief MTL debug access type + * + */ +typedef enum +{ + ENET_MTL_DEBUG_ACCESS_TX_FIFO = 0u, + ENET_MTL_DEBUG_ACCESS_TX_STATUS_FIFO = 1u, + ENET_MTL_DEBUG_ACCESS_TSO_FIFO = 2u, + ENET_MTL_DEBUG_ACCESS_RX_FIFO = 3u +} ENET_MTL_DebugAccessFIFOType; + +/** + * @brief MTL fifo packet status type + * + */ +typedef enum +{ + ENET_MTL_PACKET_STATE_PACKET_DATA = 0u, + ENET_MTL_PACKET_STATE_TX_CTRL_WORD_RX_NORMAL_STATUS = 1u, + ENET_MTL_PACKET_STATE_TX_SOP_DATA_RX_LAST_STATUS = 2u, + ENET_MTL_PACKET_STATE_TX_EOP_DATA_RX_EOP = 3u +} ENET_MTL_FIFOPacketStatusType; + +/** + * @brief MTL byte enable type + * + */ +typedef enum +{ + ENET_MTL_BYTE_0_VALID = 0u, + ENET_MTL_BYTE_0_1_VALID = 1u, + ENET_MTL_BYTE_0_1_2_VALID = 2u, + ENET_MTL_BYTE_ALL_VALID = 3u +} ENET_MTL_ByteEnableType; + +/** + * @brief MTL fifo debug access type + * + */ +typedef enum +{ + ENET_MTL_FIFO_DEBUG_ACCESS_RESTRICTED = 0u, + ENET_MTL_FIFO_DEBUG_ACCESS_UNRESTRICTED = 1u +} ENET_MTL_FIFODebugAccessType; + +/** + * @brief MTL TX threshold type + * + */ +typedef enum +{ + ENET_MTL_TX_THRESHOLD_32B = 0u, + ENET_MTL_TX_THRESHOLD_64B = 1u, + ENET_MTL_TX_THRESHOLD_96B = 2u, + ENET_MTL_TX_THRESHOLD_128B = 3u, + ENET_MTL_TX_THRESHOLD_192B = 4u, + ENET_MTL_TX_THRESHOLD_256B = 5u, + ENET_MTL_TX_STORE_FORWARD = (1u << ENET_MTL_TXQn_OPERATION_MODE_TTC_WIDTH) +} ENET_MTL_TxThresholdType; + +/** + * @brief MTL write controller status type + * + */ +typedef enum +{ + ENET_MTL_WRITE_CONTROLLER_IDLE = 0u, + ENET_MTL_WRITE_CONTROLLER_ACTIVE = 1u +} ENET_MTL_WriteControllerStatusType; + +/** + * @brief MTL read controller status type + * + */ +typedef enum +{ + ENET_MTL_READ_CONTROLLER_IDLE = 0u, + ENET_MTL_READ_CONTROLLER_READ = 1u, + ENET_MTL_READ_CONTROLLER_WAIT = 2u, + ENET_MTL_READ_CONTROLLER_FLUSH = 3u +} ENET_MTL_ReadControllerStatusType; + +/** + * @brief MTL RX flow control threshold type + * + */ +typedef enum +{ + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_1_KB = 0u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_1_5_KB = 1u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_2_KB = 2u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_2_5_KB = 3u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_3_KB = 4u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_3_5_KB = 5u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_4_KB = 6u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_4_5_KB = 7u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_5_KB = 8u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_5_5_KB = 9u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_6_KB = 10u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_6_5_KB = 11u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_7_KB = 12u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_7_5_KB = 13u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_8_KB = 14u, + ENET_MTL_RX_FLOWCTRL_THRESHOLD_FULL_8_5_KB = 15u +} ENET_MTL_RxFlowCtrlThresholdType; + +/** + * @brief MTL RX threshold type + * + */ +typedef enum +{ + ENET_MTL_RX_THRESHOLD_64B = 0u, + ENET_MTL_RX_THRESHOLD_32B = 1u, + ENET_MTL_RX_THRESHOLD_96B = 2u, + ENET_MTL_RX_THRESHOLD_128B = 3u, + ENET_MTL_RX_STORE_FORWARD = (1u << ENET_MTL_RXQn_OPERATION_MODE_RTC_WIDTH) +} ENET_MTL_RxThresholdType; + +/** + * @brief MTL RX queue status type + * + */ +typedef enum +{ + ENET_MTL_RX_QUEUE_EMPTY = 0u, + ENET_MTL_RX_QUEUE_BELOW_FLOW_CTRL_DEACTIVATE_THRES = 1u, + ENET_MTL_RX_QUEUE_ABOVE_FLOW_CTRL_ACTIVATE_THRES = 2u, + ENET_MTL_RX_QUEUE_FULL = 3u +} ENET_MTL_RxQueueStatusType; + +#if ENET_SUPPORT_TIME_SENSITIVE_NETWORK +/** + * @brief Multiple of gate control list interval time + * + */ +typedef enum +{ + ENET_MTL_GCL_INTERVAL_X_1 = 0x0u, + ENET_MTL_GCL_INTERVAL_X_2 = 0x1u, + ENET_MTL_GCL_INTERVAL_X_4 = 0x2u, + ENET_MTL_GCL_INTERVAL_X_8 = 0x3u, + ENET_MTL_GCL_INTERVAL_X_16 = 0x4u, + ENET_MTL_GCL_INTERVAL_X_32 = 0x5u, + ENET_MTL_GCL_INTERVAL_X_64 = 0x6u, + ENET_MTL_GCL_INTERVAL_X_128 = 0x7u +} ENET_MTL_GCLIntervalMultipleType; + +/** + * @brief Loop count to report Scheduling Error + * + */ +typedef enum +{ + ENET_MTL_GCL_4_ITERATIONS = 0x0u, + ENET_MTL_GCL_8_ITERATIONS = 0x1u, + ENET_MTL_GCL_16_ITERATIONS = 0x2u, + ENET_MTL_GCL_32_ITERATIONS = 0x3u +} ENET_MTL_ScheduleErrorLoopCountType; + +/** + * @brief Gcl related registers + * + */ +typedef enum +{ + ENET_MTL_GCL_BTR_LOW = 0x0u, + ENET_MTL_GCL_BTR_HIGH = 0x1u, + ENET_MTL_GCL_CTR_LOW = 0x2u, + ENET_MTL_GCL_CTR_HIGH = 0x3u, + ENET_MTL_GCL_TER = 0x4u, + ENET_MTL_GCL_LLR = 0x5 +} ENET_MTL_GclRegistersType; + +/** + * @brief Gcl operation type + * + */ +typedef enum +{ + ENET_MTL_GCL_WRITE = 0x0u, + ENET_MTL_GCL_READ = 0x1u +} ENET_MTL_GclOperationType; + +/** + * @brief MTL gate control list index type + * + */ +typedef enum +{ + ENET_MTL_GCL_NUMBER_0 = 0x0u, + ENET_MTL_GCL_NUMBER_1 = 0x1u +} ENET_MTL_GateControlListType; +#endif /* ENET_SUPPORT_TIME_SENSITIVE_NETWORK */ + +/** + * @brief ENET DMA channel index type + * + */ +typedef enum +{ + ENET_DMA_CHANNEL_0 = 0x0u, + ENET_DMA_CHANNEL_1 = 0x1u +} ENET_DMA_ChannelType; + +/** + * @brief ENET DMA running status + * + */ +typedef enum +{ + ENET_DMA_STATUS_IDLE = 0x0u, /**< The ENET DMA engine is stoppeed */ + ENET_DMA_STATUS_ACTIVE = 0x1u /**< The ENET DMA engine is running */ +} ENET_DMA_StatusType; + +/** + * @brief The interrupt mode of ENET DMA + * + */ +typedef enum +{ + ENET_DMA_INTM_SBD_PERCH_PULSE = 0u, /**< sbd_perch_* are pulse signals and sbd_inter_o will assert */ + ENET_DMA_INTM_SBD_PERCH_LEVEL = 1u, /**< sbd_perch_* are level signals and sbd_inter_o will not assert */ + ENET_DMA_INTM_SBD_PERCH_LEVEL_REENTRANT = 2u /**< sbd_perch_* are level signals and will regenerate if the same event + occur again before the signals cleared. sbd_inter_o will not assert */ +} ENET_DMA_IntModeType; + +/** + * @brief ENET DMA priority ratio type + * + */ +typedef enum +{ + ENET_DMA_PRIORITY_RATIO_1_1 = 0u, /**< The priority ratio is 1:1 */ + ENET_DMA_PRIORITY_RATIO_2_1 = 1u, /**< The priority ratio is 2:1 */ + ENET_DMA_PRIORITY_RATIO_3_1 = 2u, /**< The priority ratio is 3:1 */ + ENET_DMA_PRIORITY_RATIO_4_1 = 3u, /**< The priority ratio is 4:1 */ + ENET_DMA_PRIORITY_RATIO_5_1 = 4u, /**< The priority ratio is 5:1 */ + ENET_DMA_PRIORITY_RATIO_6_1 = 5u, /**< The priority ratio is 6:1 */ + ENET_DMA_PRIORITY_RATIO_7_1 = 6u, /**< The priority ratio is 7:1 */ + ENET_DMA_PRIORITY_RATIO_8_1 = 7u /**< The priority ratio is 8:1 */ +} ENET_DMA_PriorityRatioType; + +/** + * @brief ENET DMA priority mode type + * + */ +typedef enum +{ + ENET_DMA_PRIORITY_MODE_RX_TX = 0u, /**< The priority ratio is RX:TX */ + ENET_DMA_PRIORITY_MODE_TX_RX = 1u /**< The priority ratio is TX:RX */ +} ENET_DMA_PriorityModeType; + +/** + * @brief ENET DMA arbitration algorithm between transmit channels + * + */ +typedef enum +{ + ENET_DMA_TX_ARBITRATION_ALGORITHM_FIXED_PRIORITY = 0u, /**< Use the fixed priority for arbitration */ + ENET_DMA_TX_ARBITRATION_ALGORITHM_WEIGHTED_FIXED_PRIORITY = 1u, /**< Use the weighted fixed priority for arbitration */ + ENET_DMA_TX_ARBITRATION_ALGORITHM_WEIGHTED_ROUND_ROBIN = 2u /**< Use the weighted round-robin for arbitration */ +} ENET_DMA_TxArbitrationAlgorithmType; + +/** + * @brief ENET DMA arbitration scheme between the transmit and receive paths + * + */ +typedef enum +{ + ENET_DMA_TXRX_ARBITRATION_SCHEME_WEIGHTED_ROUND_ROBIN = 0u, /**< Use the weighted round-robin for arbitration */ + ENET_DMA_TXRX_ARBITRATION_SCHEME_FIXED_PRIORITY = 1u /**< Use the fixed priority for arbitration */ +} ENET_DMA_ArbitrationSchemeType; + +/** + * @brief ENET DMA burst mode type + * + */ +typedef enum +{ + ENET_BURSTLENGTH_FIXED = ENET_DMA_SYSBUS_MODE_FB_MASK, /**< Use the fixed burst */ + ENET_BURSTLENGTH_MIXED = ENET_DMA_SYSBUS_MODE_MB_MASK /**< Use the mixed burst Length */ +} ENET_DMA_BurstModeType; + +/** + * @brief ENET DMA interrupt flag type + * + */ +typedef enum +{ + ENET_DMA_TX_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_TIE_MASK, + ENET_DMA_TX_STOPPED_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_TXSE_MASK, + ENET_DMA_TX_BUFFER_UNAVAILABLE_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_TBUE_MASK, + ENET_DMA_RX_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_RIE_MASK, + ENET_DMA_RX_BUFFER_UNAVAILABLE_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_RBUE_MASK, + ENET_DMA_RX_STOPPED_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_RSE_MASK, + ENET_DMA_RX_WATCHDOG_TIMEOUT_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_RWTE_MASK, + ENET_DMA_EARLY_TX_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_ETIE_MASK, + ENET_DMA_EARLY_RX_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_ERIE_MASK, + ENET_DMA_FATAL_BUS_ERROR_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_FBEE_MASK, + ENET_DMA_CONTEXT_DESCRIPTOR_ERROR_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_CDEE_MASK, + ENET_DMA_ABNORMAL_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_AIE_MASK, + ENET_DMA_NORMAL_INTERRUPT = ENET_DMA_CHn_INTERRUPT_ENABLE_NIE_MASK +} ENET_DMA_InterruptFlagType; + +/** + * @brief ENET DMA watchdog counter unit type + * + */ +typedef enum +{ + ENET_DMA_WDG_COUNTER_UNIT_256_CYCLE = 0x0u, + ENET_DMA_WDG_COUNTER_UNIT_512_CYCLE = 0x1u, + ENET_DMA_WDG_COUNTER_UNIT_1024_CYCLE = 0x2u, + ENET_DMA_WDG_COUNTER_UNIT_2048_CYCLE = 0x3u +} ENET_DMA_WDGCounterUnitType; + +/** + * @brief ENET DMA RX error type + * + */ +typedef enum +{ + ENET_DMA_RX_NO_ERROR = 0x0u, + ENET_DMA_RX_READ_DESCRIPTER_ERROR = 0x7u, + ENET_DMA_RX_WRITE_DESCRIPTER_ERROR = 0x6u, + ENET_DMA_RX_READ_BUFFER_ERROR = 0x5u, + ENET_DMA_RX_WRITE_BUFFER_ERROR = 0x4u +} ENET_DMA_RxErrorType; + +/** + * @brief ENET DMA TX error type + * + */ +typedef enum +{ + ENET_DMA_TX_NO_ERROR = 0x0u, + ENET_DMA_TX_READ_DESCRIPTER_ERROR = 0x7u, + ENET_DMA_TX_WRITE_DESCRIPTER_ERROR = 0x6u, + ENET_DMA_TX_READ_BUFFER_ERROR = 0x5u, + ENET_DMA_TX_WRITE_BUFFER_ERROR = 0x4u +} ENET_DMA_TxErrorType; + + +/** ================================================================ * + * ENET system control + * ================================================================ */ + +#if ENET_SYSTEM_CONTROL_SMISC +/** + * @brief Get the Core Id. + * + * @return The Core Id number + */ +LOCAL_INLINE uint8_t ENET_HWA_Sysctrl_GetCoreId(void) +{ + return (uint8_t)0u; +} + +/** + * @brief Set ENET clock software reset + * + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_SetEnetClkSoftwareResetEnFlag(void) +{ + SMISC->PERICTLR |= SMISC_PERICTLR_ENET_CLK_SW_RESET_MASK; +} + +/** + * @brief Set PHY interface mode + * + * @param [in] eMode PHY interface mode + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_SetPhyMiiMode(ENET_MAC_MiiModeType eMode) +{ + SMISC->PERICTLR = (SMISC->PERICTLR & ~SMISC_PERICTLR_ENET_RMIIEN_MASK) | + SMISC_PERICTLR_ENET_RMIIEN((eMode == ENET_MAC_PHY_RMII) ? 1u : 0u); +} + +/** + * @brief Get TX clock select source + * + * @return ENET_MAC_TxClkSelType + */ +LOCAL_INLINE ENET_MAC_TxClkSelType ENET_HWA_Sysctrl_GetTxClockSrc(void) +{ + uint32_t u32TmpVal = 0u; + u32TmpVal = (SMISC->PERICTLR & SMISC_PERICTLR_RMII_CLK_SEL_MASK) >> SMISC_PERICTLR_RMII_CLK_SEL_SHIFT; + return (ENET_MAC_TxClkSelType)(u32TmpVal + 1u); +} + +/** + * @brief Set TX clock select source + * + * @param [in] eClkSrc TX clock source + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_SetTxClockSrc(ENET_MAC_TxClkSelType eClkSrc) +{ + uint32_t u32TmpVal = (uint32_t)eClkSrc - 1u; + SMISC->PERICTLR = (SMISC->PERICTLR & ~SMISC_PERICTLR_RMII_CLK_SEL_MASK) | + SMISC_PERICTLR_RMII_CLK_SEL(u32TmpVal); +} + +/** + * @brief Select the clock source of PTP module. + * + * @param [in] eClkSrc The clock source type + */ +LOCAL_INLINE ENET_MAC_PTPClkSelType ENET_HWA_Sysctrl_GetPTPClkSrc(void) +{ + return (ENET_MAC_PTPClkSelType)((SMISC->PERICTLR & SMISC_PERICTLR_ENET_TS_CLKSEL_MASK) >> SMISC_PERICTLR_ENET_TS_CLKSEL_SHIFT); +} + +/** + * @brief Select the clock source of PTP module. + * + * @param [in] eClkSrc The clock source type + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_SetPTPClkSrc(ENET_MAC_PTPClkSelType eClkSrc) +{ + SMISC->PERICTLR = (SMISC->PERICTLR & ~SMISC_PERICTLR_ENET_TS_CLKSEL_MASK) | + SMISC_PERICTLR_ENET_TS_CLKSEL(eClkSrc); +} + +/** + * @brief Get MAC 5M mode enable flag + * + * @return true 5M mode is enabled + * @return false 5M mode is disabled + */ +LOCAL_INLINE bool ENET_HWA_Sysctrl_Get5MModeEnFlag(void) +{ + return ((SMISC->PERICTLR & SMISC_PERICTLR_ENET_5M_MODE_MASK) != 0u) ? true : false; +} + +/** + * @brief Set MAC 5M mode enable flag + * + * @param [in] bEnable enable or disable 5M mode + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_Set5MModeEnFlag(bool bEnable) +{ + SMISC->PERICTLR = (SMISC->PERICTLR & ~SMISC_PERICTLR_ENET_5M_MODE_MASK) | + SMISC_PERICTLR_ENET_5M_MODE(bEnable); +} + +/** + * @brief Get PPS IO port direction + * + * @param [in] eChannel PPS channel + * @return ENET_MAC_PPSPinDirType + */ +LOCAL_INLINE ENET_MAC_PPSPinDirType ENET_HWA_Sysctrl_GetPPSPinDirection(ENET_MAC_PPSChannelType eChannel) +{ + uint32_t u32TmpVal; + u32TmpVal = (SMISC->PERICTLR & (1u << (SMISC_PERICTLR_ENET_PPS0_OBECTL_SHIFT + eChannel))); + return (u32TmpVal != 0u) ? ENET_PTP_PPS_DIR_OUTPUT : ENET_PTP_PPS_DIR_INPUT; +} + +/** + * @brief Set PPS IO port direction + * + * @param [in] eChannel PPS channel + * @param [in] eDir IO port direction + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_SetPPSPinDirection(ENET_MAC_PPSChannelType eChannel, + ENET_MAC_PPSPinDirType eDir) +{ + SMISC->PERICTLR = (SMISC->PERICTLR & (~(1u << (SMISC_PERICTLR_ENET_PPS0_OBECTL_SHIFT + eChannel)))) | + ((uint32_t)(((uint32_t)(eDir)) << (SMISC_PERICTLR_ENET_PPS0_OBECTL_SHIFT + eChannel))); +} +#endif /* ENET_SYSTEM_CONTROL_SMISC */ + +#if ENET_SYSTEM_CONTROL_SCM +/** + * @brief Get the Core Id. + * + * @return The Core Id number + */ +LOCAL_INLINE uint8_t ENET_HWA_Sysctrl_GetCoreId(void) +{ + return (uint8_t)Cpm_HWA_GetCoreId(); +} + +/** + * @brief Set ENET clock software reset + * + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_SetEnetClkSoftwareResetEnFlag(void) +{ + SCM->ENET_CTRL |= SCM_ENET_CTRL_ENET_CLK_SWRST_MASK; +} + +/** + * @brief Set PHY interface mode + * + * @param [in] eMode PHY interface mode + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_SetPhyMiiMode(ENET_MAC_MiiModeType eMode) +{ + SCM->ENET_CTRL = (SCM->ENET_CTRL & (~SCM_ENET_CTRL_PHY_SEL_MASK)) | SCM_ENET_CTRL_PHY_SEL(eMode); +} + +#if ENET_SUPPORT_RGMII +/** + * @brief Get RGMII clock select source + * + * @return ENET_MAC_RGMIIClkSelType + */ +LOCAL_INLINE ENET_MAC_RGMIIClkSelType ENET_HWA_Sysctrl_GetRGMIIClockSrc(void) +{ + return (ENET_MAC_RGMIIClkSelType)((SCM->ENET_CTRL & SCM_ENET_CTRL_ENET_RGMII_CLK_SEL_MASK) >> SCM_ENET_CTRL_ENET_RGMII_CLK_SEL_SHIFT); +} + +/** + * @brief Set RGMII clock select source + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eClkSrc RGMII clock source + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_SetRGMIIClockSrc(ENET_MAC_RGMIIClkSelType eClkSrc) +{ + SCM->ENET_CTRL = (SCM->ENET_CTRL & ~SCM_ENET_CTRL_ENET_RGMII_CLK_SEL_MASK) | SCM_ENET_CTRL_ENET_RGMII_CLK_SEL(eClkSrc); +} +#endif + +/** + * @brief Get TX clock select source + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_TxClkSelType + */ +LOCAL_INLINE ENET_MAC_TxClkSelType ENET_HWA_Sysctrl_GetTxClockSrc(void) +{ + return (ENET_MAC_TxClkSelType)((SCM->ENET_CTRL & SCM_ENET_CTRL_ENET_TXCLK_SEL_MASK) >> SCM_ENET_CTRL_ENET_TXCLK_SEL_SHIFT); +} + +/** + * @brief Set TX clock select source + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eClkSrc TX clock source + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_SetTxClockSrc(ENET_MAC_TxClkSelType eClkSrc) +{ + SCM->ENET_CTRL = (SCM->ENET_CTRL & ~SCM_ENET_CTRL_ENET_TXCLK_SEL_MASK) | SCM_ENET_CTRL_ENET_TXCLK_SEL(eClkSrc); +} + +/** + * @brief Select the clock source of PTP module. + * + * @return eClkSrc The clock source type + */ +LOCAL_INLINE ENET_MAC_PTPClkSelType ENET_HWA_Sysctrl_GetPTPClkSrc(void) +{ + return (ENET_MAC_PTPClkSelType)((SCM->ENET_CTRL & SCM_ENET_CTRL_PTPCLK_SEL_MASK) >> SCM_ENET_CTRL_PTPCLK_SEL_SHIFT); +} + +/** + * @brief Select the clock source of PTP module. + * + * @param [in] eClkSrc The PTP clock source + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_SetPTPClkSrc(ENET_MAC_PTPClkSelType eClkSrc) +{ + SCM->ENET_CTRL = (SCM->ENET_CTRL & ~SCM_ENET_CTRL_PTPCLK_SEL_MASK) | SCM_ENET_CTRL_PTPCLK_SEL(eClkSrc); +} + +/** + * @brief Get MAC 5M mode enable flag + * + * @return true 5M mode is enabled + * @return false 5M mode is disabled + */ +LOCAL_INLINE bool ENET_HWA_Sysctrl_Get5MModeEnFlag(void) +{ + return ((SCM->ENET_CTRL & SCM_ENET_CTRL_RMII_5M_MASK) != 0u) ? true : false; +} + +/** + * @brief Set MAC 5M mode enable flag + * + * @param [in] bEnable enable or disable 5M mode + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_Set5MModeEnFlag(bool bEnable) +{ + SCM->ENET_CTRL = (SCM->ENET_CTRL & ~SCM_ENET_CTRL_RMII_5M_MASK) | SCM_ENET_CTRL_RMII_5M(bEnable); +} + +/** + * @brief Get PPS IO port direction + * + * @param [in] eChannel PPS channel + * @return ENET_MAC_PPSPinDirType + */ +LOCAL_INLINE ENET_MAC_PPSPinDirType ENET_HWA_Sysctrl_GetPPSPinDirection(ENET_MAC_PPSChannelType eChannel) +{ + uint32_t u32TmpVal; + u32TmpVal = SCM->ENET_CTRL & (1u << (SCM_ENET_CTRL_ENET_TIMER_OBE_SHIFT + (uint32_t)eChannel)); + return (u32TmpVal != 0u) ? ENET_PTP_PPS_DIR_OUTPUT : ENET_PTP_PPS_DIR_INPUT; +} + +/** + * @brief Set PPS IO port direction + * + * @param [in] eChannel PPS channel + * @param [in] eDir IO port direction + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_SetPPSPinDirection(ENET_MAC_PPSChannelType eChannel, + ENET_MAC_PPSPinDirType eDir) +{ + SCM->ENET_CTRL = (SCM->ENET_CTRL & (~(1u << (SCM_ENET_CTRL_ENET_TIMER_OBE_SHIFT + (uint32_t) eChannel)))) | + SCM_ENET_CTRL_ENET_TIMER_OBE((uint32_t)eDir << (uint32_t)eChannel); +} + +/** + * @brief Get Mii TX clock output enable flag + * + * @return true Mii TX clock output is enabled + * @return false Mii TX clock output is disabled + */ +LOCAL_INLINE bool ENET_HWA_Sysctrl_GetMiiTxClkOutputEnFlag(void) +{ + return ((SCM->ENET_CTRL & SCM_ENET_CTRL_MII_TX_CLK_OBE_MASK) != 0u) ? true : false; +} + +/** + * @brief Set Mii TX clock output enable flag + * + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_Sysctrl_SetMiiTxClkOutputEnFlag(bool bEnable) +{ + SCM->ENET_CTRL = (SCM->ENET_CTRL & ~SCM_ENET_CTRL_MII_TX_CLK_OBE_MASK) | SCM_ENET_CTRL_MII_TX_CLK_OBE(bEnable); +} + +#if ENET_SUPPORT_TCM_SMP_MODE +/** + * @brief Get SMP mode enable flag + * + * @return true SMP mode is enabled + * @return false SMP mode is disabled + */ +LOCAL_INLINE bool ENET_HWA_Sysctrl_GetTcmSMPModeEnFlag(void) +{ + return ((SCM->CHIPCFG2 & SCM_CHIPCFG2_SMP_EN_MASK) != 0u) ? true : false; +} +#endif +#endif /* ENET_SYSTEM_CONTROL_SCM */ + + +/** ================================================================ * + * ENET MAC Configuration and Status * + * ================================================================ */ + + +/** + * @brief Get the MAC Configuration Register value. + * + * @param [in] pEnet The base address of the ENET instance + * @return The Register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetConfiguration(const ENET_Type *const pEnet) +{ + return pEnet->MAC_CONFIGURATION; +} + +/** + * @brief Set the MAC Configuration Register value. + * + * @param [in] pEnet The base address of the ENET instance + * @param [in] u32Config The Configuration Register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetConfiguration(ENET_Type *const pEnet, uint32_t u32Config) +{ + pEnet->MAC_CONFIGURATION = u32Config; +} + +/** + * @brief Get the source address insertion or replacement control type + * + * @param [in] pEnet the base address of the Ethernet instance + * @return source address insertion or replacement control type + */ +LOCAL_INLINE ENET_MAC_SrcAddrCtrlType ENET_HWA_MAC_GetSrcAddrInsertReplaceCtrl(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_SARC_MASK) >> ENET_MAC_CONFIGURATION_SARC_SHIFT; + return (ENET_MAC_SrcAddrCtrlType)u32TmpVal; +} + +/** + * @brief Set the source address insertion or replacement control type + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eInsertReplaceCtrl source address insertion or replacement control type + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSrcAddrInsertReplaceCtrl(ENET_Type *const pEnet, + ENET_MAC_SrcAddrCtrlType eInsertReplaceCtrl) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_SARC_MASK) | + ENET_MAC_CONFIGURATION_SARC(eInsertReplaceCtrl); +} + +/** + * @brief Get checksum offload function enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Checksum offload function is enabled + * @return false Checksum offload function is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetIPChecksumOffloadEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_IPC_MASK) >> ENET_MAC_CONFIGURATION_IPC_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set checksum offload function enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetIPChecksumOffloadEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_IPC_MASK) | + ENET_MAC_CONFIGURATION_IPC(bEnable ? 1u : 0u); +} + +/** + * @brief Get the minimum Inter-Packet Gap + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_InterPacketGapType. + */ +LOCAL_INLINE ENET_MAC_InterPacketGapType ENET_HWA_MAC_GetMinInterPacketGap(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_IPG_MASK) >> ENET_MAC_CONFIGURATION_IPG_SHIFT; + return (ENET_MAC_InterPacketGapType)u32TmpVal; +} + +/** + * @brief Set the minimum Inter-Packet Gap value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eGap Inter-Packet Gap value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMinInterPacketGap(ENET_Type *const pEnet, ENET_MAC_InterPacketGapType eGap) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_IPG_MASK) | + ENET_MAC_CONFIGURATION_IPG(eGap); +} + +/** + * @brief Get giant packet size Limit control enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Giant packet size Limit control is enabled + * @return false Giant packet size Limit control is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetGiantPacketSizeLimitCtrlEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_GPSLCE_MASK) >> + ENET_MAC_CONFIGURATION_GPSLCE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set giant packet size Limit control enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetGiantPacketSizeLimitCtrlEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_GPSLCE_MASK) | + ENET_MAC_CONFIGURATION_GPSLCE(bEnable ? 1u : 0u); +} + +/** + * @brief Get 2K packet support enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true 2K packet support is enabled + * @return false 2K packet support is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_Get2KPacketSupportFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_S2KP_MASK) >> + ENET_MAC_CONFIGURATION_S2KP_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set 2K packet support enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_Set2KPacketSupportFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_S2KP_MASK) | + ENET_MAC_CONFIGURATION_S2KP(bEnable ? 1u : 0u); +} + +/** + * @brief Get CRC stripping for type packets enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true CRC stripping for type packets is enabled + * @return false CRC stripping for type packets is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetStripTypePacketCRCEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_CST_MASK) >> + ENET_MAC_CONFIGURATION_CST_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set CRC stripping for type packets enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetStripTypePacketCRCEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_CST_MASK) | + ENET_MAC_CONFIGURATION_CST(bEnable ? 1u : 0u); +} + +/** + * @brief Get automatic Pad or CRC stripping enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Automatic Pad or CRC stripping is enabled + * @return false Automatic Pad or CRC stripping is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetAutoStripPadOrCRCEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_ACS_MASK) >> ENET_MAC_CONFIGURATION_ACS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set automatic Pad or CRC stripping enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetAutoStripPadOrCRCEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_ACS_MASK) | + ENET_MAC_CONFIGURATION_ACS(bEnable ? 1u : 0u); +} + +/** + * @brief Get receiver watchdog timer disabled flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Receiver watchdog timer is disabled + * @return false Receiver watchdog timer is enabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetWatchdogDisableFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_WD_MASK) >> ENET_MAC_CONFIGURATION_WD_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set receiver watchdog timer disabled flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bDisable Disable or enable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetWatchdogDisableFlag(ENET_Type *const pEnet, bool bDisable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_WD_MASK) | + ENET_MAC_CONFIGURATION_WD(bDisable ? 1u : 0u); +} + +/** + * @brief Get transmitter jabber timer disabled flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Transmitter jabber timer is disabled + * @return false Transmitter jabber timer is enabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetJabberTimerDisableFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_JD_MASK) >> ENET_MAC_CONFIGURATION_JD_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set transmitter jabber timer disabled flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bDisable Disable or enable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetJabberTimerDisableFlag(ENET_Type *const pEnet, bool bDisable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_JD_MASK) | + ENET_MAC_CONFIGURATION_JD(bDisable ? 1u : 0u); +} + +/** + * @brief Get jumbo packet enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Jumbo packet is enabled + * @return false Jumbo packet is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetJumboPacketEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_JE_MASK) >> ENET_MAC_CONFIGURATION_JE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set jumbo packet enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetJumboPacketEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_JE_MASK) | + ENET_MAC_CONFIGURATION_JE(bEnable ? 1u : 0u); +} + +/** + * @brief Get ethernet line speed + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_SpeedType + */ +LOCAL_INLINE ENET_MAC_SpeedType ENET_HWA_MAC_GetSpeed(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & (ENET_MAC_CONFIGURATION_FES_MASK | ENET_MAC_CONFIGURATION_PS_MASK)) + >> ENET_MAC_CONFIGURATION_FES_SHIFT; + return (ENET_MAC_SpeedType)u32TmpVal; +} + +/** + * @brief Set ethernet line speed + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eSpeed Ethernet line speed + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSpeed(ENET_Type *const pEnet, ENET_MAC_SpeedType eSpeed) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~(ENET_MAC_CONFIGURATION_FES_MASK | ENET_MAC_CONFIGURATION_PS_MASK)) | + (((uint32_t)eSpeed << ENET_MAC_CONFIGURATION_FES_SHIFT) & + (ENET_MAC_CONFIGURATION_FES_MASK | ENET_MAC_CONFIGURATION_PS_MASK)); +} + +/** + * @brief Get ethernet duplex mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_DuplexModeType + */ +LOCAL_INLINE ENET_MAC_DuplexModeType ENET_HWA_MAC_GetDuplexMode(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_DM_MASK) >> ENET_MAC_CONFIGURATION_DM_SHIFT; + return (ENET_MAC_DuplexModeType)u32TmpVal; +} + +/** + * @brief Set ethernet duplex mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eMode Ethernet duplex mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetDuplexMode(ENET_Type *const pEnet, ENET_MAC_DuplexModeType eMode) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_DM_MASK) | + ENET_MAC_CONFIGURATION_DM(eMode); +} + +/** + * @brief Get loopback mode enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Loopback mode is enabled + * @return false Loopback mode is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetLoopbackModeEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_LM_MASK) >> ENET_MAC_CONFIGURATION_LM_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set loopback mode enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLoopbackModeEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_LM_MASK) | + ENET_MAC_CONFIGURATION_LM(bEnable ? 1u : 0u); +} + +/** + * @brief Get carrier sense before transmission enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Carrier sense before transmission is enabled + * @return false Carrier sense before transmission is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetFullDuplexCRSEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_ECRSFD_MASK) >> + ENET_MAC_CONFIGURATION_ECRSFD_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set carrier sense before transmission enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetFullDuplexCRSEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_ECRSFD_MASK) | + ENET_MAC_CONFIGURATION_ECRSFD(bEnable ? 1u : 0u); +} + +/** + * @brief Get receive own disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Receive own is disabled + * @return false Receive own is enabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetReceiveOwnDisableFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_DO_MASK) >> + ENET_MAC_CONFIGURATION_DO_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set receive own disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bDisable Disable or enable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetReceiveOwnDisableFlag(ENET_Type *const pEnet, bool bDisable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_DO_MASK) | + ENET_MAC_CONFIGURATION_DO(bDisable ? 1u : 0u); +} + +/** + * @brief Get carrier sense during transmission disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Carrier sense during transmission is disabled + * @return false Carrier sense during transmission is enabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetHalfDuplexCRSDisableFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_DCRS_MASK) >> + ENET_MAC_CONFIGURATION_DCRS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set carrier sense during transmission disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bDisable Disable or enable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetHalfDuplexCRSDisableFlag(ENET_Type *const pEnet, bool bDisable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_DCRS_MASK) | + ENET_MAC_CONFIGURATION_DCRS(bDisable ? 1u : 0u); +} + +/** + * @brief Get transmission retry disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Ttransmission retry is disabled + * @return false Transmission retry is enabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetRetryDisableFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_DR_MASK) >> + ENET_MAC_CONFIGURATION_DR_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set transmission retry disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bDisable Disable or enable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRetryDisableFlag(ENET_Type *const pEnet, bool bDisable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_DR_MASK) | + ENET_MAC_CONFIGURATION_DR(bDisable ? 1u : 0u); +} + +/** + * @brief Get back-off limit + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_BackOffLimitType + */ +LOCAL_INLINE ENET_MAC_BackOffLimitType ENET_HWA_MAC_GetBackOffLimit(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_BL_MASK) >> + ENET_MAC_CONFIGURATION_BL_SHIFT; + return (ENET_MAC_BackOffLimitType)u32TmpVal; +} + +/** + * @brief Set back-off limit + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eLimit Back-off limit type value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetBackOffLimit(ENET_Type *const pEnet, ENET_MAC_BackOffLimitType eLimit) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_BL_MASK) | + ENET_MAC_CONFIGURATION_BL(eLimit); +} + +/** + * @brief Get deferral check enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Deferral check is enabled + * @return false Deferral check is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetDeferralCheckEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_DC_MASK) >> + ENET_MAC_CONFIGURATION_DC_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set deferral check enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetDeferralCheckEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_DC_MASK) | + ENET_MAC_CONFIGURATION_DC(bEnable ? 1u : 0u); +} + +/** + * @brief Get transmitter enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Transmitter is enabled + * @return false Transmitter is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTxEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_TE_MASK) >> + ENET_MAC_CONFIGURATION_TE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set transmitter enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTxEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_TE_MASK) | + ENET_MAC_CONFIGURATION_TE(bEnable ? 1u : 0u); +} + +/** + * @brief Get receiver enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Receiver is enabled + * @return false Receiver is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetRxEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_CONFIGURATION & ENET_MAC_CONFIGURATION_RE_MASK) >> + ENET_MAC_CONFIGURATION_RE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set receiver enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_CONFIGURATION = (pEnet->MAC_CONFIGURATION & ~ENET_MAC_CONFIGURATION_RE_MASK) | + ENET_MAC_CONFIGURATION_RE(bEnable ? 1u : 0u); +} + +/** + * @brief Get the MAC extended configuration register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return The register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetExtConfiguration(const ENET_Type *const pEnet) +{ + return pEnet->MAC_EXT_CONFIGURATION; +} + +/** + * @brief Set the MAC extended configuration register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32Configuration The configuration register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetExtConfiguration(ENET_Type *const pEnet, uint32_t u32Configuration) +{ + pEnet->MAC_EXT_CONFIGURATION = u32Configuration; +} + +/** + * @brief Get the MAC extended inter-packet gap + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_ExtInterPacketGapType + */ +LOCAL_INLINE ENET_MAC_ExtInterPacketGapType ENET_HWA_MAC_GetExtInterPacketGap(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_EXT_CONFIGURATION & ENET_MAC_EXT_CONFIGURATION_EIPG_MASK) >> + ENET_MAC_EXT_CONFIGURATION_EIPG_SHIFT; + return (ENET_MAC_ExtInterPacketGapType)u32TmpVal; +} + +/** + * @brief Set the MAC extended inter-packet gap + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eGap The MAC extended inter-packet gap value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetExtInterPacketGap(ENET_Type *const pEnet, ENET_MAC_ExtInterPacketGapType eGap) +{ + pEnet->MAC_EXT_CONFIGURATION = (pEnet->MAC_EXT_CONFIGURATION & ~ENET_MAC_EXT_CONFIGURATION_EIPG_MASK) | + ENET_MAC_EXT_CONFIGURATION_EIPG(eGap); +} + +/** + * @brief Get extended inter-packet gap enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Extended inter-packet gapis enabled + * @return false Extended inter-packet gap is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetExtInterPacketGapEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_EXT_CONFIGURATION & ENET_MAC_EXT_CONFIGURATION_EIPGEN_MASK) >> + ENET_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set extended inter-packet gap enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetExtInterPacketGapEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_EXT_CONFIGURATION = (pEnet->MAC_EXT_CONFIGURATION & ~ENET_MAC_EXT_CONFIGURATION_EIPGEN_MASK) | + ENET_MAC_EXT_CONFIGURATION_EIPGEN(bEnable ? 1u : 0u); +} + +/** + * @brief Get packet duplication control enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Packet duplication control enabled + * @return false Packet duplication control is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetPacketDuplicationCtrlEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_EXT_CONFIGURATION & ENET_MAC_EXT_CONFIGURATION_PDC_MASK) >> + ENET_MAC_EXT_CONFIGURATION_PDC_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set packet duplication control enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPacketDuplicationCtrlEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_EXT_CONFIGURATION = (pEnet->MAC_EXT_CONFIGURATION & ~ENET_MAC_EXT_CONFIGURATION_PDC_MASK) | + ENET_MAC_EXT_CONFIGURATION_PDC(bEnable ? 1u : 0u); +} + +/** + * @brief Get unicast slow protocol packet detect method + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_SlowProtocolDetectType + */ +LOCAL_INLINE ENET_MAC_SlowProtocolDetectType ENET_HWA_MAC_GetUnicastSlowProtocolPacketDetectMethod( + const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_EXT_CONFIGURATION & ENET_MAC_EXT_CONFIGURATION_USP_MASK) >> + ENET_MAC_EXT_CONFIGURATION_USP_SHIFT; + return (ENET_MAC_SlowProtocolDetectType)u32TmpVal; +} + +/** + * @brief Set unicast slow protocol packet detect method + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eMethod Unicast slow protocol packet detect method value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetUnicastSlowProtocolPacketDetectMethod(ENET_Type *const pEnet, + ENET_MAC_SlowProtocolDetectType eMethod) +{ + pEnet->MAC_EXT_CONFIGURATION = (pEnet->MAC_EXT_CONFIGURATION & ~ENET_MAC_EXT_CONFIGURATION_USP_MASK) | + ENET_MAC_EXT_CONFIGURATION_USP(eMethod); +} + +/** + * @brief Get slow protocol detection enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Slow protocol detection enabled + * @return false Slow protocol detection is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetSlowDetectEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_EXT_CONFIGURATION & ENET_MAC_EXT_CONFIGURATION_SPEN_MASK) >> + ENET_MAC_EXT_CONFIGURATION_SPEN_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set slow protocol detection enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSlowDetectEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_EXT_CONFIGURATION = (pEnet->MAC_EXT_CONFIGURATION & ~ENET_MAC_EXT_CONFIGURATION_SPEN_MASK) | + ENET_MAC_EXT_CONFIGURATION_SPEN(bEnable ? 1u : 0u); +} + +/** + * @brief Get CRC checking for Received packets disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true CRC checking for rReceived packets is disabled + * @return false CRC checking for rReceived packets is enabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetRxCRCCheckDisableFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_EXT_CONFIGURATION & ENET_MAC_EXT_CONFIGURATION_DCRCC_MASK) >> + ENET_MAC_EXT_CONFIGURATION_DCRCC_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set CRC checking for rReceived packets disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bDisable Disable or enable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxCRCCheckDisableFlag(ENET_Type *const pEnet, bool bDisable) +{ + pEnet->MAC_EXT_CONFIGURATION = (pEnet->MAC_EXT_CONFIGURATION & ~ENET_MAC_EXT_CONFIGURATION_DCRCC_MASK) | + ENET_MAC_EXT_CONFIGURATION_DCRCC(bDisable ? 1u : 0u); +} + +/** + * @brief Get giant packet size limit value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return Giant packet size limit value + */ +LOCAL_INLINE uint16_t ENET_HWA_MAC_GetGiantPacketSizeLimit(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_EXT_CONFIGURATION & ENET_MAC_EXT_CONFIGURATION_GPSL_MASK) >> + ENET_MAC_EXT_CONFIGURATION_GPSL_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set giant packet size limit value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u16SizeLimit Giant packet size limit value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetGiantPacketSizeLimit(ENET_Type *const pEnet, uint16_t u16SizeLimit) +{ + pEnet->MAC_EXT_CONFIGURATION = (pEnet->MAC_EXT_CONFIGURATION & ~ENET_MAC_EXT_CONFIGURATION_GPSL_MASK) | + ENET_MAC_EXT_CONFIGURATION_GPSL(u16SizeLimit); +} + +/** + * @brief Get the MAC packet filter register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return The register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetPacketFilter(const ENET_Type *const pEnet) +{ + return pEnet->MAC_PACKET_FILTER; +} + +/** + * @brief Set the MAC packet filter register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32FilterCtrl The filter control value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPacketFilter(ENET_Type *const pEnet, uint32_t u32FilterCtrl) +{ + pEnet->MAC_PACKET_FILTER = u32FilterCtrl; +} + +/** + * @brief Get receive all packets enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Receive all packets enabled + * @return false Receive all packets is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetReceiveAllEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_RA_MASK) >> ENET_MAC_PACKET_FILTER_RA_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set receive all packets enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetReceiveAllEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_RA_MASK) | + ENET_MAC_PACKET_FILTER_RA(bEnable ? 1u : 0u); +} + +/** + * @brief Get drop non-TCP/UDP over IP packets enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Drop non-TCP/UDP over IP packets + * @return false Forward non-TCP/UDP over IP packets + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetDropNonTCPUDPOverIPEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_DNTU_MASK) >> ENET_MAC_PACKET_FILTER_DNTU_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set drop non-TCP/UDP over IP packets enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Drop or forward non-TCP/UDP over IP packets + */ +LOCAL_INLINE void ENET_HWA_MAC_SetDropNonTCPUDPOverIPEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_DNTU_MASK) | + ENET_MAC_PACKET_FILTER_DNTU(bEnable ? 1u : 0u); +} + +/** + * @brief Get layer 3 and layer 4 filter enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Enable layer 3 and layer 4 filter + * @return false Disable layer 3 and layer 4 filter + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetLayer3Layer4FilterEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_IPFE_MASK) >> ENET_MAC_PACKET_FILTER_IPFE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set layer 3 and layer 4 filter enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3Layer4FilterEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_IPFE_MASK) | + ENET_MAC_PACKET_FILTER_IPFE(bEnable ? 1u : 0u); +} + +/** + * @brief Get VLAN tag filter enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Enable VLAN tag filter + * @return false Disable VLAN tag filter + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetVLANTagFilterEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_VTFE_MASK) >> ENET_MAC_PACKET_FILTER_VTFE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set VLAN tag filter enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANTagFilterFilterEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_VTFE_MASK) | + ENET_MAC_PACKET_FILTER_VTFE(bEnable ? 1u : 0u); +} + +/** + * @brief Get hash or perfect filter enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Enable hash or pPerfect filter + * @return false Disable hash or pPerfect filter + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetHashOrPerfectFilterEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_HPF_MASK) >> ENET_MAC_PACKET_FILTER_HPF_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set hash or perfect filter enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetHashOrPerfectFilterEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_HPF_MASK) | + ENET_MAC_PACKET_FILTER_HPF(bEnable ? 1u : 0u); +} + +/** + * @brief Get source address filter enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Enable source address filter + * @return false Disable source address fFilter + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetSourceAddressFilterEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_SAF_MASK) >> ENET_MAC_PACKET_FILTER_SAF_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set source address filter enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSourceAddressFilterEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_SAF_MASK) | + ENET_MAC_PACKET_FILTER_SAF(bEnable ? 1u : 0u); +} + +/** + * @brief Get source address filter mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_AddrFilterModeType + */ +LOCAL_INLINE ENET_MAC_AddrFilterModeType ENET_HWA_MAC_GetSrcAddrFilterMode(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_SAIF_MASK) >> ENET_MAC_PACKET_FILTER_SAIF_SHIFT; + return (ENET_MAC_AddrFilterModeType)u32TmpVal; +} + +/** + * @brief Set source address filter mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eFilterMode Source address filter mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSrcAddrFilterMode(ENET_Type *const pEnet, ENET_MAC_AddrFilterModeType eFilterMode) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_SAIF_MASK) | + ENET_MAC_PACKET_FILTER_SAIF(eFilterMode); +} + +/** + * @brief Get control packets filter mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_CtrlPacketFilterModeType + */ +LOCAL_INLINE ENET_MAC_CtrlPacketFilterModeType ENET_HWA_MAC_GetCtrlPacketFilterMode(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_PCF_MASK) >> ENET_MAC_PACKET_FILTER_PCF_SHIFT; + return (ENET_MAC_CtrlPacketFilterModeType)u32TmpVal; +} + +/** + * @brief Set control packets filter mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eFilterMode Control packets filter mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetCtrlPacketFilterMode(ENET_Type *const pEnet, + ENET_MAC_CtrlPacketFilterModeType eFilterMode) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_PCF_MASK) | + ENET_MAC_PACKET_FILTER_PCF(eFilterMode); +} + +/** + * @brief Get broadcast packets disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Drop broadcast packets + * @return false receive broadcast packets + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetBroadcastPacketDisableFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_DBF_MASK) >> ENET_MAC_PACKET_FILTER_DBF_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set broadcast packets disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bDisable Disable or enable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetBroadcastPacketDisableFlag(ENET_Type *const pEnet, bool bDisable) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_DBF_MASK) | + ENET_MAC_PACKET_FILTER_DBF(bDisable ? 1u : 0u); +} + +/** + * @brief Get pass all the received multicast packets enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Pass all the received multicast packets + * @return false Pass multicast packets that match the multicast filter + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetPassAllMulticastEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_PM_MASK) >> ENET_MAC_PACKET_FILTER_PM_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set pass all the received multicast packets enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPassAllMulticastEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_PM_MASK) | + ENET_MAC_PACKET_FILTER_PM(bEnable ? 1u : 0u); +} + +/** + * @brief Get destination address filter mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_AddrFilterModeType + */ +LOCAL_INLINE ENET_MAC_AddrFilterModeType ENET_HWA_MAC_GetDestAddrFilterMode(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_DAIF_MASK) >> ENET_MAC_PACKET_FILTER_DAIF_SHIFT; + return (ENET_MAC_AddrFilterModeType)u32TmpVal; +} + +/** + * @brief Set destination address filter mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @param eFilterMode Destination address filter mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetDestAddrFilterMode(ENET_Type *const pEnet, ENET_MAC_AddrFilterModeType eFilterMode) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_DAIF_MASK) | + ENET_MAC_PACKET_FILTER_DAIF(eFilterMode); +} + +/** + * @brief Get hash or perfect multicast filter mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_HashOrPerfectModeType + */ +LOCAL_INLINE ENET_MAC_HashOrPerfectModeType ENET_HWA_MAC_GetHashOrPerfectMulticastMode(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_HMC_MASK) >> ENET_MAC_PACKET_FILTER_HMC_SHIFT; + return (ENET_MAC_HashOrPerfectModeType)u32TmpVal; +} + +/** + * @brief Set hash or perfect multicast filter mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @param eMode Hash or perfect multicast filter mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetHashOrPerfectMulticastMode(ENET_Type *const pEnet, ENET_MAC_HashOrPerfectModeType eMode) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_HMC_MASK) | + ENET_MAC_PACKET_FILTER_HMC(eMode); +} + +/** + * @brief Get hash or perfect unicast filter mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_HashOrPerfectModeType + */ +LOCAL_INLINE ENET_MAC_HashOrPerfectModeType ENET_HWA_MAC_GetHashOrPerfectUnicastMode(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_HMC_MASK) >> ENET_MAC_PACKET_FILTER_HMC_SHIFT; + return (ENET_MAC_HashOrPerfectModeType)u32TmpVal; +} + +/** + * @brief Set hash or perfect unicast filter mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @param eMode Hash or perfect unicast filter mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetHashOrPerfectUnicastMode(ENET_Type *const pEnet, ENET_MAC_HashOrPerfectModeType eMode) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_HUC_MASK) | + ENET_MAC_PACKET_FILTER_HUC(eMode); +} + +/** + * @brief Get promiscuous mode enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Enable promiscuous mode + * @return false Disable promiscuous mode + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetPromiscuousModeEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_PACKET_FILTER & ENET_MAC_PACKET_FILTER_PR_MASK) >> ENET_MAC_PACKET_FILTER_PR_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set promiscuous mode enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPromiscuousModeEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_PACKET_FILTER = (pEnet->MAC_PACKET_FILTER & ~ENET_MAC_PACKET_FILTER_PR_MASK) | + ENET_MAC_PACKET_FILTER_PR(bEnable ? 1u : 0u); +} + +/** + * @brief Get programmable watchdog timeout register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return Watchdog timeout register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetWatchdogTimeout(const ENET_Type *const pEnet) +{ + return pEnet->MAC_WATCHDOG_TIMEOUT; +} + +/** + * @brief Set programmable watchdog timeout register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32Settings Watchdog timeout register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetWatchdogTimeout(ENET_Type *const pEnet, uint32_t u32Settings) +{ + pEnet->MAC_WATCHDOG_TIMEOUT = u32Settings; +} + +/** + * @brief Get programmable watchdog enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Programmable watchdog enabled + * @return false Programmable watchdog disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetWatchdogEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_WATCHDOG_TIMEOUT & ENET_MAC_WATCHDOG_TIMEOUT_PWE_MASK) >> + ENET_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set programmable watchdog enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetWatchdogEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_WATCHDOG_TIMEOUT = (pEnet->MAC_WATCHDOG_TIMEOUT & ~ENET_MAC_WATCHDOG_TIMEOUT_PWE_MASK) | + ENET_MAC_WATCHDOG_TIMEOUT_PWE(bEnable ? 1u : 0u); +} + +/** + * @brief Get programmable watchdog timer size value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_WDGTimerSizeType + */ +LOCAL_INLINE ENET_MAC_WDGTimerSizeType ENET_HWA_MAC_GetWatchdogTimerSize(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_WATCHDOG_TIMEOUT & ENET_MAC_WATCHDOG_TIMEOUT_WTO_MASK) >> + ENET_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT; + return (ENET_MAC_WDGTimerSizeType)u32TmpVal; +} + +/** + * @brief Set programmable watchdog timer size + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eSize Watchdog timer size + */ +LOCAL_INLINE void ENET_HWA_MAC_SetWatchdogTimerSize(ENET_Type *const pEnet, ENET_MAC_WDGTimerSizeType eSize) +{ + pEnet->MAC_WATCHDOG_TIMEOUT = (pEnet->MAC_WATCHDOG_TIMEOUT & ~ENET_MAC_WATCHDOG_TIMEOUT_WTO_MASK) | + ENET_MAC_WATCHDOG_TIMEOUT_WTO(eSize); +} + +/** + * @brief Get the hash table first 32 bits value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return Hash table first 32 bits value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetHashTableFirst32Bits(const ENET_Type *const pEnet) +{ + return pEnet->MAC_HASH_TABLE_REG0; +} + +/** + * @brief Set the hash table first 32 bits value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param u32Hash0 Hash table first 32 bits value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetHashTableFirst32Bits(ENET_Type *const pEnet, uint32_t u32Hash0) +{ + pEnet->MAC_HASH_TABLE_REG0 = u32Hash0; +} + +/** + * @brief Get the hash table second 32 bits value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return Hash table second 32 bits value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetHashTableSecond32Bits(const ENET_Type *const pEnet) +{ + return pEnet->MAC_HASH_TABLE_REG1; +} + +/** + * @brief Set the hash table second 32 bits value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32Hash1 Hash table second 32 bits value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetHashTableSecond32Bits(ENET_Type *const pEnet, uint32_t u32Hash1) +{ + pEnet->MAC_HASH_TABLE_REG1 = u32Hash1; +} + +/** + * @brief Get VLAN tag control register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return VLAN tag control register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetVLANTagCtrl(const ENET_Type *const pEnet) +{ + return pEnet->MAC_VLAN_TAG_CTRL; +} + +/** + * @brief Set VLAN tag control register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32VlanCtrl Register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANTagCtrl(ENET_Type *const pEnet, uint32_t u32VlanCtrl) +{ + pEnet->MAC_VLAN_TAG_CTRL = u32VlanCtrl; +} + +/** + * @brief Get inner VLAN tag enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Inner VLAN tag is enabled + * @return false Inner VLAN tag is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetRxStatusInnerVLANTagEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set inner VLAN tag enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxStatusInnerVLANTagEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK) | + ENET_MAC_VLAN_TAG_CTRL_EIVLRXS(bEnable ? 1u : 0u); +} + +/** + * @brief Get inner VLAN tag stripping mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_VLANTagStripModeType + */ +LOCAL_INLINE ENET_MAC_VLANTagStripModeType ENET_HWA_MAC_GetInnerVLANTagStripMode(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_EIVLS_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT; + return (ENET_MAC_VLANTagStripModeType)u32TmpVal; +} + +/** + * @brief Set inner VLAN tag stripping mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eMode Inner VLAN tag stripping mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetInnerVLANTagStripMode(ENET_Type *const pEnet, ENET_MAC_VLANTagStripModeType eMode) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_EIVLS_MASK) | + ENET_MAC_VLAN_TAG_CTRL_EIVLS(eMode); +} + +/** + * @brief Get inner VLAN tag comparison enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Inner VLAN tag comparison is enabled + * @return false Inner VLAN tag comparison is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetInnerVLANTagCmpEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_ERIVLT_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set inner VLAN tag comparison enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetInnerVLANTagCmpEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_ERIVLT_MASK) | + ENET_MAC_VLAN_TAG_CTRL_ERIVLT(bEnable ? 1u : 0u); +} + +/** + * @brief Get double VLAN processing enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Double VLAN processing is enabled + * @return false Double VLAN processing is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetDoubleVLANProcessEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_EDVLP_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set double VLAN processing enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetDoubleVLANProcessEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_EDVLP_MASK) | + ENET_MAC_VLAN_TAG_CTRL_EDVLP(bEnable ? 1u : 0u); +} + +/** + * @brief Get VLAN tag hash table match enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true VLAN tag hash table match is enabled + * @return false VLAN tag hash table match is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetVLANTagHashTableMatchEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_VTHM_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_VTHM_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set VLAN tag hash table match enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANTagHashTableMatchEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_VTHM_MASK) | + ENET_MAC_VLAN_TAG_CTRL_VTHM(bEnable ? 1u : 0u); +} + +/** + * @brief Get VLAN tag in rx status enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true VLAN tag in rx status is enabled + * @return false VLAN tag in rx status is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetRxStatusVLANTagEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_EVLRXS_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set VLAN tag in rx status enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxStatusVLANTagEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_EVLRXS_MASK) | + ENET_MAC_VLAN_TAG_CTRL_EVLRXS(bEnable ? 1u : 0u); +} + +/** + * @brief Get VLAN tag stripping mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_VLANTagStripModeType + */ +LOCAL_INLINE ENET_MAC_VLANTagStripModeType ENET_HWA_MAC_GetVLANTagStripMode(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_EVLS_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_EVLS_SHIFT; + return (ENET_MAC_VLANTagStripModeType)u32TmpVal; +} + +/** + * @brief Set VLAN tag stripping mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eMode VLAN tag stripping mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANTagStripMode(ENET_Type *const pEnet, ENET_MAC_VLANTagStripModeType eMode) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_EVLS_MASK) | + ENET_MAC_VLAN_TAG_CTRL_EVLS(eMode); +} + +/** + * @brief Get VLAN type check disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true VLAN type check is disabled + * @return false VLAN type check is enabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetVLANTypeCheckDisableFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_DOVLTC_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_DOVLTC_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set VLAN type check disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bDisable Disable or enable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANTypeCheckDisableFlag(ENET_Type *const pEnet, bool bDisable) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_DOVLTC_MASK) | + ENET_MAC_VLAN_TAG_CTRL_DOVLTC(bDisable ? 1u : 0u); +} + +/** + * @brief Get Receive S-VLAN match enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Receive S-VLAN match is enabled + * @return false Receive S-VLAN match is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetRxSVLANMatchEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_ERSVLM_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_ERSVLM_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set Receive S-VLAN match enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxSVLANMatchEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_ERSVLM_MASK) | + ENET_MAC_VLAN_TAG_CTRL_ERSVLM(bEnable ? 1u : 0u); +} + +/** + * @brief Get S-VLAN enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true S-VLAN is enabled + * @return false S-VLAN is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetSVLANEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_ESVL_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_ESVL_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set S-VLAN enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSVLANEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_ESVL_MASK) | + ENET_MAC_VLAN_TAG_CTRL_ESVL(bEnable ? 1u : 0u); +} + +/** + * @brief Get VLAN tag inverse match enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true VLAN tag inverse match is enabled + * @return false VLAN tag inverse match is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetVLANInverseMatchEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_VTIM_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_VTIM_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set VLAN tag inverse match enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANInverseMatchEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_VTIM_MASK) | + ENET_MAC_VLAN_TAG_CTRL_VTIM(bEnable ? 1u : 0u); +} + +/** + * @brief Get 12-Bit VLAN tag comparison enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true 12-Bit VLAN tag comparison is enabled + * @return false 12-Bit VLAN tag comparison is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_Get12BitVLANTagEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_ETV_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_ETV_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set 12-Bit VLAN tag comparison enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_Set12BitVLANTagEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_ETV_MASK) | + ENET_MAC_VLAN_TAG_CTRL_ETV(bEnable ? 1u : 0u); +} + +/** + * @brief Get VLAN tag filter register address offset + * + * @param [in] pEnet the base address of the Ethernet instance + * @return VLAN tag filter register address offset + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetVLANTagFilterRegOffset(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_OFS_MASK) >> + ENET_MAC_VLAN_TAG_CTRL_OFS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set VLAN tag filter register address offset + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u8Offset VLAN tag filter register address offset + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANTagFilterRegOffset(ENET_Type *const pEnet, uint8_t u8Offset) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_OFS_MASK) | + ENET_MAC_VLAN_TAG_CTRL_OFS(u8Offset); +} + +/** + * @brief Get VLAN tag filter register command type + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_VLANCommandType + */ +LOCAL_INLINE ENET_MAC_VLANCommandType ENET_HWA_MAC_GetVLANCommandType(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_CT_MASK) >> ENET_MAC_VLAN_TAG_CTRL_CT_SHIFT; + return (ENET_MAC_VLANCommandType)u32TmpVal; +} + +/** + * @brief Set VLAN tag filter register command type + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eCommand Command type + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANCommandType(ENET_Type *const pEnet, ENET_MAC_VLANCommandType eCommand) +{ + pEnet->MAC_VLAN_TAG_CTRL = (pEnet->MAC_VLAN_TAG_CTRL & ~ENET_MAC_VLAN_TAG_CTRL_CT_MASK) | + ENET_MAC_VLAN_TAG_CTRL_CT(eCommand); +} + +/** + * @brief Get VLAN tag filter register operation status + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_StatusType + */ +LOCAL_INLINE ENET_MAC_StatusType ENET_HWA_MAC_GetVLANOperationStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_OB_MASK) >> ENET_MAC_VLAN_TAG_CTRL_OB_SHIFT; + return (ENET_MAC_StatusType)u32TmpVal; +} + +/** + * @brief Set VLAN tag filter register operation busy status + * + * @param [in] pEnet the base address of the Ethernet instance + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANOperationBusy(ENET_Type *const pEnet) +{ + pEnet->MAC_VLAN_TAG_CTRL |= ENET_MAC_VLAN_TAG_CTRL_OB_MASK; +} + +/** + * @brief Get VLAN tag data registers value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return VLAN tag data registers value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetVLANTagData(const ENET_Type *const pEnet) +{ + return pEnet->MAC_VLAN_TAG_DATA; +} + +/** + * @brief Set VLAN tag data registers value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32VLANData Data value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANTagData(ENET_Type *const pEnet, uint32_t u32VLANData) +{ + pEnet->MAC_VLAN_TAG_DATA = u32VLANData; +} + +/** + * @brief Get VLAN hash table registers value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return VLAN hash tTable registers value + */ +LOCAL_INLINE uint16_t ENET_HWA_MAC_GetVLANHashTable(const ENET_Type *const pEnet) +{ + return (uint16_t)(pEnet->MAC_VLAN_HASH_TABLE & ENET_MAC_VLAN_HASH_TABLE_VLHT_MASK); +} + +/** + * @brief Set VLAN hash table registers value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u16HashTable VLAN hash table registers value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANHashTable(ENET_Type *const pEnet, uint16_t u16HashTable) +{ + pEnet->MAC_VLAN_HASH_TABLE = ENET_MAC_VLAN_HASH_TABLE_VLHT(u16HashTable); +} + +/** + * @brief Get VLAN tag inclusion register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return VLAN tag inclusion registers value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetVLANInclusion(const ENET_Type *const pEnet) +{ + return pEnet->MAC_VLAN_INCL_DATA; +} + +/** + * @brief Set VLAN tag inclusion register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32Inclusion VLAN tag inclusion register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANInclusion(ENET_Type *const pEnet, uint32_t u32Inclusion) +{ + pEnet->MAC_VLAN_INCL_DATA = u32Inclusion; +} + +/** + * @brief Get VLAN inclusion operation status + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_StatusType + */ +LOCAL_INLINE ENET_MAC_StatusType ENET_HWA_MAC_GetVLANInclusionOperationStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_INCL_DATA & ENET_MAC_VLAN_INCL_BUSY_MASK) >> + ENET_MAC_VLAN_INCL_BUSY_SHIFT; + return (ENET_MAC_StatusType)u32TmpVal; +} + +/** + * @brief Set VLAN inclusion operation status + * + * @param [in] pEnet the base address of the Ethernet instance + */ +LOCAL_INLINE ENET_MAC_VLANInclCommandType ENET_HWA_MAC_GetVLANInclusionCommandType(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_INCL_DATA & ENET_MAC_VLAN_INCL_RDWR_MASK) >> + ENET_MAC_VLAN_INCL_RDWR_SHIFT; + return (ENET_MAC_VLANInclCommandType)u32TmpVal; +} + +/** + * @brief Set VLAN tag inclusion command + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eCommand VLAN tag inclusion command + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANInclusionCommandType(ENET_Type *const pEnet, ENET_MAC_VLANInclCommandType eCommand) +{ + pEnet->MAC_VLAN_INCL_DATA = (pEnet->MAC_VLAN_INCL_DATA & ~ENET_MAC_VLAN_INCL_RDWR_MASK) | + ENET_MAC_VLAN_INCL_RDWR(eCommand); +} + +/** + * @brief Get VLAN inclusion address + * + * @param [in] pEnet the base address of the Ethernet instance + * @return VLAN inclusion address value + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetVLANInclusionAddr(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_INCL_DATA & ENET_MAC_VLAN_INCL_ADDR_MASK) >> + ENET_MAC_VLAN_INCL_ADDR_SHIFT; + return (uint8_t) u32TmpVal; +} + +/** + * @brief Set VLAN inclusion address + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u8Addr VLAN tag inclusion address value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANInclusionAddr(ENET_Type *const pEnet, uint8_t u8Addr) +{ + pEnet->MAC_VLAN_INCL_DATA = (pEnet->MAC_VLAN_INCL_DATA & ~ENET_MAC_VLAN_INCL_ADDR_MASK) | + ENET_MAC_VLAN_INCL_ADDR(u8Addr); +} + +/** + * @brief Get channel based tag insertion enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Channel based tag insertion is enabled + * @return false Channel based tag insertion is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetChannelBasedVLANTagInsertEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_INCL_DATA & ENET_MAC_VLAN_INCL_CBTI_MASK) >> + ENET_MAC_VLAN_INCL_CBTI_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set channel based tag insertion enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetChannelBasedVLANTagInsertEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_VLAN_INCL_DATA = (pEnet->MAC_VLAN_INCL_DATA & ~ENET_MAC_VLAN_INCL_CBTI_MASK) | + ENET_MAC_VLAN_INCL_CBTI(bEnable ? 1u : 0u); +} + +/** + * @brief Get VLAN tag input enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true VLAN tag input is enabled + * @return false VLAN tag input is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetVLANTagInputEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_INCL_DATA & ENET_MAC_VLAN_INCL_VLTI_MASK) >> + ENET_MAC_VLAN_INCL_VLTI_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set VLAN tag input enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANTagInputEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_VLAN_INCL_DATA = (pEnet->MAC_VLAN_INCL_DATA & ~ENET_MAC_VLAN_INCL_VLTI_MASK) | + ENET_MAC_VLAN_INCL_VLTI(bEnable ? 1u : 0u); +} + +/** + * @brief Get VLAN type + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_VLANType + */ +LOCAL_INLINE ENET_MAC_VLANType ENET_HWA_MAC_GetVLANType(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_INCL_DATA & ENET_MAC_VLAN_INCL_CSVL_MASK) >> + ENET_MAC_VLAN_INCL_CSVL_SHIFT; + return (ENET_MAC_VLANType)u32TmpVal; +} + +/** + * @brief Set VLAN type + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eType VLAN type + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANType(ENET_Type *const pEnet, ENET_MAC_VLANType eType) +{ + pEnet->MAC_VLAN_INCL_DATA = (pEnet->MAC_VLAN_INCL_DATA & ~ENET_MAC_VLAN_INCL_CSVL_MASK) | + ENET_MAC_VLAN_INCL_CSVL(eType); +} + +/** + * @brief Get VLAN priority control enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true VLAN priority control is enabled + * @return false VLAN priority control is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetVLANPriorityCtrlEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_INCL_DATA & ENET_MAC_VLAN_INCL_VLP_MASK) >> + ENET_MAC_VLAN_INCL_VLP_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set VLAN tag input enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANPriorityCtrlEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_VLAN_INCL_DATA = (pEnet->MAC_VLAN_INCL_DATA & ~ENET_MAC_VLAN_INCL_VLP_MASK) | + ENET_MAC_VLAN_INCL_VLP(bEnable ? 1u : 0u); +} + +/** + * @brief Get VLAN tag control mode in transmit packets + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_VLANTagCtrlType + */ +LOCAL_INLINE ENET_MAC_VLANTagCtrlType ENET_HWA_MAC_GetVLANTagCtrlOperation(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_INCL_DATA & ENET_MAC_VLAN_INCL_VLC_MASK) >> + ENET_MAC_VLAN_INCL_VLC_SHIFT; + return (ENET_MAC_VLANTagCtrlType)u32TmpVal; +} + +/** + * @brief Set VLAN tag control mode in transmit packets + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eCtrl VLAN tag control mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANTagCtrlOperation(ENET_Type *const pEnet, ENET_MAC_VLANTagCtrlType eCtrl) +{ + pEnet->MAC_VLAN_INCL_DATA = (pEnet->MAC_VLAN_INCL_DATA & ~ENET_MAC_VLAN_INCL_VLC_MASK) | + ENET_MAC_VLAN_INCL_VLC(eCtrl); +} + +/** + * @brief Get Tx VLAN tag value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return Tx VLAN tag value + */ +LOCAL_INLINE uint16_t ENET_HWA_MAC_GetTxVLANTag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_VLAN_INCL_DATA & ENET_MAC_VLAN_INCL_VLT_MASK) >> + ENET_MAC_VLAN_INCL_VLT_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set Tx VLAN tag value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u16VLANTag VLAN tag value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTxVLANTag(ENET_Type *const pEnet, uint16_t u16VLANTag) +{ + pEnet->MAC_VLAN_INCL_DATA = (pEnet->MAC_VLAN_INCL_DATA & ~ENET_MAC_VLAN_INCL_VLT_MASK) | + ENET_MAC_VLAN_INCL_VLT(u16VLANTag); +} + +/** + * @brief Get inner VLAN tag inclusion or replacement register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return The register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetInnerVLANInclusion(const ENET_Type *const pEnet) +{ + return pEnet->MAC_INNER_VLAN_INCL; +} + +/** + * @brief Set inner VLAN tag inclusion or replacement register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32Inclusion Register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetInnerVLANInclusion(ENET_Type *const pEnet, uint32_t u32Inclusion) +{ + pEnet->MAC_INNER_VLAN_INCL = u32Inclusion; +} + +/** + * @brief Get inner VLAN tag input enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Inner VLAN tag input is enabled + * @return false Inner VLAN tag input is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetInnerVLANTagInputEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INNER_VLAN_INCL & ENET_MAC_INNER_VLAN_INCL_VLTI_MASK) >> + ENET_MAC_INNER_VLAN_INCL_VLTI_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set inner VLAN tag input enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetInnerVLANTagInputEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_INNER_VLAN_INCL = (pEnet->MAC_INNER_VLAN_INCL & ~ENET_MAC_INNER_VLAN_INCL_VLTI_MASK) | + ENET_MAC_INNER_VLAN_INCL_VLTI(bEnable ? 1u : 0u); +} + +/** + * @brief Get inner VLAN type + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_VLANType + */ +LOCAL_INLINE ENET_MAC_VLANType ENET_HWA_MAC_GetInnerVLANType(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INNER_VLAN_INCL & ENET_MAC_INNER_VLAN_INCL_CSVL_MASK) >> + ENET_MAC_INNER_VLAN_INCL_CSVL_SHIFT; + return (ENET_MAC_VLANType)u32TmpVal; +} + +/** + * @brief Set inner VLAN type + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eType Inner VLAN type + */ +LOCAL_INLINE void ENET_HWA_MAC_SetInnerVLANType(ENET_Type *const pEnet, ENET_MAC_VLANType eType) +{ + pEnet->MAC_INNER_VLAN_INCL = (pEnet->MAC_INNER_VLAN_INCL & ~ENET_MAC_INNER_VLAN_INCL_CSVL_MASK) | + ENET_MAC_INNER_VLAN_INCL_CSVL(eType); +} + +/** + * @brief Get inner VLAN priority control enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Inner VLAN priority control is enabled + * @return false Inner VLAN priority control is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetInnerVLANPriorityCtrlEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INNER_VLAN_INCL & ENET_MAC_INNER_VLAN_INCL_VLP_MASK) >> + ENET_MAC_INNER_VLAN_INCL_VLP_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set inner VLAN priority control enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetInnerVLANPriorityCtrlEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_INNER_VLAN_INCL = (pEnet->MAC_INNER_VLAN_INCL & ~ENET_MAC_INNER_VLAN_INCL_VLP_MASK) | + ENET_MAC_INNER_VLAN_INCL_VLP(bEnable ? 1u : 0u); +} + +/** + * @brief Get inner VLAN tag control mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_VLANTagCtrlType + */ +LOCAL_INLINE ENET_MAC_VLANTagCtrlType ENET_HWA_MAC_GetInnerVLANTagCtrl(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INNER_VLAN_INCL & ENET_MAC_INNER_VLAN_INCL_VLC_MASK) >> + ENET_MAC_INNER_VLAN_INCL_VLC_SHIFT; + return (ENET_MAC_VLANTagCtrlType)u32TmpVal; +} + +/** + * @brief Set inner VLAN tag control mode + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eCtrl Inner VLAN tag control mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetInnerVLANTagCtrl(ENET_Type *const pEnet, ENET_MAC_VLANTagCtrlType eCtrl) +{ + pEnet->MAC_INNER_VLAN_INCL = (pEnet->MAC_INNER_VLAN_INCL & ~ENET_MAC_INNER_VLAN_INCL_VLC_MASK) | + ENET_MAC_INNER_VLAN_INCL_VLC(eCtrl); +} + +/** + * @brief Get inner VLAN tag value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return Inner VLAN tag value + */ +LOCAL_INLINE uint16_t ENET_HWA_MAC_GetTxInnerVLANTag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INNER_VLAN_INCL & ENET_MAC_INNER_VLAN_INCL_VLT_MASK) >> + ENET_MAC_INNER_VLAN_INCL_VLT_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set inner VLAN tag value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u16VLANTag Inner VLAN tag value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTxInnerVLANTag(ENET_Type *const pEnet, uint16_t u16VLANTag) +{ + pEnet->MAC_INNER_VLAN_INCL = (pEnet->MAC_INNER_VLAN_INCL & ~ENET_MAC_INNER_VLAN_INCL_VLT_MASK) | + ENET_MAC_INNER_VLAN_INCL_VLT(u16VLANTag); +} + +/** + * @brief Get Queue n tx flow control register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return The register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetQnTxFlowCtrl(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + return pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue]; +} + +/** + * @brief Set Queue n tx flow control register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32FlowCtrl The register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetQnTxFlowCtrl(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + uint32_t u32FlowCtrl) +{ + pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] = u32FlowCtrl; +} + +/** + * @brief Get Queue n tx pause time value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return Pause time value + */ +LOCAL_INLINE uint16_t ENET_HWA_MAC_GetQnTxPauseTime(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] & + ENET_MAC_Qn_TX_FLOW_CTRL_PT_MASK) >> ENET_MAC_Qn_TX_FLOW_CTRL_PT_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set Queue n tx pause time value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u16PauseTime Pause time value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetQnTxPauseTime(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + uint16_t u16PauseTime) +{ + pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] = (pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] & + ~(ENET_MAC_Qn_TX_FLOW_CTRL_PT_MASK | ENET_MAC_Qn_TX_FLOW_CTRL_FCB_BPA_MASK)) | + ENET_MAC_Qn_TX_FLOW_CTRL_PT(u16PauseTime); +} + +/** + * @brief Get Queue n tx zero quanta pause disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true Queue0 tx zero quanta pause is disabled + * @return false is Queue0 tx zero quanta pause enabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetQnTxZeroQuantaPauseDisableFlag(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] & ENET_MAC_Qn_TX_FLOW_CTRL_DZPQ_MASK) >> + ENET_MAC_Qn_TX_FLOW_CTRL_DZPQ_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set Queue n tx zero quanta pause disable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bDisable Disable or enable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetQnTxZeroQuantaPauseDisableFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + bool bDisable) +{ + pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] = (pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] & + ~(ENET_MAC_Qn_TX_FLOW_CTRL_DZPQ_MASK | ENET_MAC_Qn_TX_FLOW_CTRL_FCB_BPA_MASK)) | + ENET_MAC_Qn_TX_FLOW_CTRL_DZPQ(bDisable ? 1u : 0u); +} + +/** + * @brief Get Queue n tx pause low threshold + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_PauseThresholdType + */ +LOCAL_INLINE ENET_MAC_PauseThresholdType ENET_HWA_MAC_GetQnTxPauseLowThreshold(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] & ENET_MAC_Qn_TX_FLOW_CTRL_PLT_MASK) >> + ENET_MAC_Qn_TX_FLOW_CTRL_PLT_SHIFT; + return (ENET_MAC_PauseThresholdType)u32TmpVal; +} + +/** + * @brief Set Queue n tx pause low threshold + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] ePauseThreshold Threshold value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetQnTxPauseLowThreshold(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + ENET_MAC_PauseThresholdType ePauseThreshold) +{ + pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] = (pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] & + ~(ENET_MAC_Qn_TX_FLOW_CTRL_PLT_MASK | ENET_MAC_Qn_TX_FLOW_CTRL_FCB_BPA_MASK)) | + ENET_MAC_Qn_TX_FLOW_CTRL_PLT(ePauseThreshold); +} + +/** + * @brief Get Queue n tx flow control enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @retval true Queue0 tx flow control is enabled + * @retval false Queue0 tx flow control is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetQnTxFlowCtrlEnableFlag(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] & ENET_MAC_Qn_TX_FLOW_CTRL_TFE_MASK) >> + ENET_MAC_Qn_TX_FLOW_CTRL_TFE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set Queue n tx flow control enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetQnTxFlowCtrlEnableFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, bool bEnable) +{ + pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] = (pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] & + ~(ENET_MAC_Qn_TX_FLOW_CTRL_TFE_MASK | ENET_MAC_Qn_TX_FLOW_CTRL_FCB_BPA_MASK)) | + ENET_MAC_Qn_TX_FLOW_CTRL_TFE(bEnable ? 1u : 0u); +} + +/** + * @brief Get flow control busy or backpressure status of Queue n + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_StatusType + */ +LOCAL_INLINE ENET_MAC_StatusType ENET_HWA_MAC_GetFlowCtrlOrBackpressureStatus(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] & ENET_MAC_Qn_TX_FLOW_CTRL_FCB_BPA_MASK) >> + ENET_MAC_Qn_TX_FLOW_CTRL_FCB_BPA_SHIFT; + return (ENET_MAC_StatusType)u32TmpVal; +} + +/** + * @brief Initiate flow control busy or backpressure of Queue n + * + * @param [in] pEnet the base address of the Ethernet instance + */ +LOCAL_INLINE void ENET_HWA_MAC_InitiatePausePacketOrBackpressure(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MAC_Qn_TX_FLOW_CTRL[(uint32_t)eQueue] |= ENET_MAC_Qn_TX_FLOW_CTRL_FCB_BPA_MASK; +} + +/** + * @brief Get receive flow control register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return Register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxFlowCtrl(const ENET_Type *const pEnet) +{ + return pEnet->MAC_RX_FLOW_CTRL; +} + +/** + * @brief Set receive flow control register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32FlowCtrl Register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxFlowCtrl(ENET_Type *const pEnet, uint32_t u32FlowCtrl) +{ + pEnet->MAC_RX_FLOW_CTRL = u32FlowCtrl; +} + +/** + * @brief Get unicast pause packet detect enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @retval true Unicast pause packet detect is enabled + * @retval false Unicast pause packet detect is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetUnicastPausePacketDetectEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RX_FLOW_CTRL & ENET_MAC_RX_FLOW_CTRL_UP_MASK) >> ENET_MAC_RX_FLOW_CTRL_UP_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set unicast pause packet detect enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetUnicastPausePacketDetectEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_RX_FLOW_CTRL = (pEnet->MAC_RX_FLOW_CTRL & ~ENET_MAC_RX_FLOW_CTRL_UP_MASK) | + ENET_MAC_RX_FLOW_CTRL_UP(bEnable ? 1u : 0u); +} + +/** + * @brief Get receive flow control enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @retval true Receive flow control is enabled + * @retval false Receive flow control is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetRxFlowCtrlEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RX_FLOW_CTRL & ENET_MAC_RX_FLOW_CTRL_RFE_MASK) >> ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set receive flow control enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable Enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxFlowCtrlEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_RX_FLOW_CTRL = (pEnet->MAC_RX_FLOW_CTRL & ~ENET_MAC_RX_FLOW_CTRL_RFE_MASK) | + ENET_MAC_RX_FLOW_CTRL_RFE(bEnable ? 1u : 0u); +} + +/** + * @brief Get Receive queue control 0 register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return Register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxQueueCtrl0(const ENET_Type *const pEnet) +{ + return pEnet->MAC_RXQ_CTRL0; +} + +/** + * @brief Set Receive queue control 0 register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32Ctrl Register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxQueueCtrl0(ENET_Type *const pEnet, uint32_t u32Ctrl) +{ + pEnet->MAC_RXQ_CTRL0 = u32Ctrl; +} + +/** + * @brief Get Receive queue control 1 register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return Register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxQueueCtrl1(const ENET_Type *const pEnet) +{ + return pEnet->MAC_RXQ_CTRL1; +} + +/** + * @brief Set Receive queue control 1 register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32Ctrl Register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxQueueCtrl1(ENET_Type *const pEnet, uint32_t u32Ctrl) +{ + pEnet->MAC_RXQ_CTRL1 = u32Ctrl; +} + +/** + * @brief Get Receive queue control 2 register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return Register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxQueueCtrl2(const ENET_Type *const pEnet) +{ + return pEnet->MAC_RXQ_CTRL2; +} + +/** + * @brief Set Receive queue control 2 register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32Ctrl Register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxQueueCtrl2(ENET_Type *const pEnet, uint32_t u32Ctrl) +{ + pEnet->MAC_RXQ_CTRL2 = u32Ctrl; +} + +/** + * @brief Get Receive queue control 4 register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @return Register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxQueueCtrl4(const ENET_Type *const pEnet) +{ + return pEnet->MAC_RXQ_CTRL4; +} + +/** + * @brief Set Receive queue control 4 register value + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] u32Ctrl Register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxQueueCtrl4(ENET_Type *const pEnet, uint32_t u32Ctrl) +{ + pEnet->MAC_RXQ_CTRL4 = u32Ctrl; +} + +/** + * @brief Get Receive queue enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eQueue the queue number + * @return ENET_MTL_QueueEnableType + */ +LOCAL_INLINE ENET_MTL_QueueEnableType ENET_HWA_MTL_GetRxQueueEnStatus(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL0 & + ((uint32_t)ENET_MAC_RXQ_CTRL0_RXQ0EN_MASK << + (ENET_MAC_RXQ_CTRL0_RXQ0EN_SHIFT + + (ENET_MAC_RXQ_CTRL0_RXQ1EN_SHIFT - ENET_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) * (uint32_t)eQueue))) >> + (ENET_MAC_RXQ_CTRL0_RXQ0EN_SHIFT + + (ENET_MAC_RXQ_CTRL0_RXQ1EN_SHIFT - ENET_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) * (uint32_t)eQueue); + return (ENET_MTL_QueueEnableType)u32TmpVal; +} + +/** + * @brief Set Receive queue enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eQueue the queue number + * @param [in] eEnable receive queue enable mode + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxQueueEnStatus(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + ENET_MTL_QueueEnableType eEnable) +{ + pEnet->MAC_RXQ_CTRL0 = (pEnet->MAC_RXQ_CTRL0 & + ~((uint32_t)ENET_MAC_RXQ_CTRL0_RXQ0EN_MASK << + (ENET_MAC_RXQ_CTRL0_RXQ0EN_SHIFT + + (ENET_MAC_RXQ_CTRL0_RXQ1EN_SHIFT - ENET_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) * (uint32_t)eQueue))) | + (ENET_MAC_RXQ_CTRL0_RXQ0EN(eEnable) << + ((ENET_MAC_RXQ_CTRL0_RXQ1EN_SHIFT - ENET_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) * (uint32_t)eQueue)); +} + +/** + * @brief Get tagged PTP over ethernet packets queuing control + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MAC_PTPoEQueueCtrlType + */ +LOCAL_INLINE ENET_MAC_PTPoEQueueCtrlType ENET_HWA_MAC_GetTaggedPTPoEQueueCtrl(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL1 & ENET_MAC_RXQ_CTRL1_TPQC_MASK) >> ENET_MAC_RXQ_CTRL1_TPQC_SHIFT; + return (ENET_MAC_PTPoEQueueCtrlType)u32TmpVal; +} + +/** + * @brief Set tagged PTP over ethernet packets queuing control + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eCtrl the control mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTaggedPTPoEQueueCtrl(ENET_Type *const pEnet, ENET_MAC_PTPoEQueueCtrlType eCtrl) +{ + pEnet->MAC_RXQ_CTRL1 = (pEnet->MAC_RXQ_CTRL1 & ~ENET_MAC_RXQ_CTRL1_TPQC_MASK) | + ENET_MAC_RXQ_CTRL1_TPQC(eCtrl); +} + +/** + * @brief Get tagged AV control packets queuing enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true tagged AV control packets queue is enabled + * @return false tagged AV control packets queue is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTaggedAVCtrlPacketQueueEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL1 & ENET_MAC_RXQ_CTRL1_TACPQE_MASK) >> ENET_MAC_RXQ_CTRL1_TACPQE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set tagged AV control packets queuing enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTaggedAVCtrlPacketQueueEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_RXQ_CTRL1 = (pEnet->MAC_RXQ_CTRL1 & ~ENET_MAC_RXQ_CTRL1_TACPQE_MASK) | + ENET_MAC_RXQ_CTRL1_TACPQE(bEnable ? 1u : 0u); +} + +/** + * @brief Get multicast and broadcast queue enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true multicast and broadcast queue is enabled + * @return false multicast and broadcast queue is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMulticastAndBroadcastQueueEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL1 & ENET_MAC_RXQ_CTRL1_MCBCQEN_MASK) >> ENET_MAC_RXQ_CTRL1_MCBCQEN_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set multicast and broadcast queue enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMulticastAndBroadcastQueueEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_RXQ_CTRL1 = (pEnet->MAC_RXQ_CTRL1 & ~ENET_MAC_RXQ_CTRL1_MCBCQEN_MASK) | + ENET_MAC_RXQ_CTRL1_MCBCQEN(bEnable ? 1u : 0u); +} + +/** + * @brief Get multicast and broadcast queue id + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MTL_QueueType + */ +LOCAL_INLINE ENET_MTL_QueueType ENET_HWA_MAC_GetMulticastAndBroadcastQueue(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL1 & ENET_MAC_RXQ_CTRL1_MCBCQ_MASK) >> ENET_MAC_RXQ_CTRL1_MCBCQ_SHIFT; + return (ENET_MTL_QueueType)u32TmpVal; +} + +/** + * @brief Set multicast and broadcast queue id + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eQueue the queue id + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMulticastAndBroadcastQueue(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MAC_RXQ_CTRL1 = (pEnet->MAC_RXQ_CTRL1 & ~ENET_MAC_RXQ_CTRL1_MCBCQ_MASK) | + ENET_MAC_RXQ_CTRL1_MCBCQ(eQueue); +} + +/** + * @brief Get untagged packet queue id + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MTL_QueueType + */ +LOCAL_INLINE ENET_MTL_QueueType ENET_HWA_MAC_GetUntaggedPacketQueue(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL1 & ENET_MAC_RXQ_CTRL1_UPQ_MASK) >> ENET_MAC_RXQ_CTRL1_UPQ_SHIFT; + return (ENET_MTL_QueueType)u32TmpVal; +} + +/** + * @brief Set untagged packet queue id + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eQueue the queue id + */ +LOCAL_INLINE void ENET_HWA_MAC_SetUntaggedPacketQueue(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MAC_RXQ_CTRL1 = (pEnet->MAC_RXQ_CTRL1 & ~ENET_MAC_RXQ_CTRL1_UPQ_MASK) | + ENET_MAC_RXQ_CTRL1_UPQ(eQueue); +} + +/** + * @brief Get PTP over ethernet packet queue id + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MTL_QueueType + */ +LOCAL_INLINE ENET_MTL_QueueType ENET_HWA_MAC_GetPTPoEQueue(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL1 & ENET_MAC_RXQ_CTRL1_PTPQ_MASK) >> ENET_MAC_RXQ_CTRL1_PTPQ_SHIFT; + return (ENET_MTL_QueueType)u32TmpVal; +} + +/** + * @brief Set PTP over ethernet packet queue id + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eQueue the queue id + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPTPoEQueue(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MAC_RXQ_CTRL1 = (pEnet->MAC_RXQ_CTRL1 & ~ENET_MAC_RXQ_CTRL1_PTPQ_MASK) | + ENET_MAC_RXQ_CTRL1_PTPQ(eQueue); +} + +/** + * @brief Get AV untagged control packets queue id + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MTL_QueueType + */ +LOCAL_INLINE ENET_MTL_QueueType ENET_HWA_MAC_GetAVCtrlPacketQueue(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL1 & ENET_MAC_RXQ_CTRL1_AVCPQ_MASK) >> ENET_MAC_RXQ_CTRL1_AVCPQ_SHIFT; + return (ENET_MTL_QueueType)u32TmpVal; +} + +/** + * @brief Set AV untagged control packets queue id + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eQueue the queue id + */ +LOCAL_INLINE void ENET_HWA_MAC_SetAVCtrlPacketQueue(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MAC_RXQ_CTRL1 = (pEnet->MAC_RXQ_CTRL1 & ~ENET_MAC_RXQ_CTRL1_AVCPQ_MASK) | + ENET_MAC_RXQ_CTRL1_AVCPQ(eQueue); +} + +/** + * @brief Get receive queue priorities + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eQueue queue id + * @return eQueue priorities value + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetRxQueueSelectedPriorities(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL2 & + ((uint32_t)ENET_MAC_RXQ_CTRL2_PSRQ0_MASK << + (ENET_MAC_RXQ_CTRL2_PSRQ0_SHIFT + + (ENET_MAC_RXQ_CTRL2_PSRQ1_SHIFT - ENET_MAC_RXQ_CTRL2_PSRQ0_SHIFT) * (uint32_t)eQueue))) >> + (ENET_MAC_RXQ_CTRL2_PSRQ0_SHIFT + + (ENET_MAC_RXQ_CTRL2_PSRQ1_SHIFT - ENET_MAC_RXQ_CTRL2_PSRQ0_SHIFT) * (uint32_t)eQueue); + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set receive queue priorities + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eQueue queue id + * @param [in] u8SelPrio priorities value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxQueueSelectedPriorities(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + uint8_t u8SelPrio) +{ + pEnet->MAC_RXQ_CTRL2 = (pEnet->MAC_RXQ_CTRL2 & + ~(ENET_MAC_RXQ_CTRL2_PSRQ0_MASK << + (ENET_MAC_RXQ_CTRL2_PSRQ0_SHIFT + + (ENET_MAC_RXQ_CTRL2_PSRQ1_SHIFT - ENET_MAC_RXQ_CTRL2_PSRQ0_SHIFT) * (uint32_t)eQueue))) | + (ENET_MAC_RXQ_CTRL2_PSRQ0(u8SelPrio) << + ((ENET_MAC_RXQ_CTRL2_PSRQ1_SHIFT - ENET_MAC_RXQ_CTRL2_PSRQ0_SHIFT) * (uint32_t)eQueue)) ; +} + +/** + * @brief Get VLAN tag filter fail packets queue enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true VLAN tag filter fail packets queue is enabled + * @return false VLAN tag filter fail packets queue is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetVLANTagFilterFailPacketQueueEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL4 & ENET_MAC_RXQ_CTRL4_VFFQE_MASK) >> ENET_MAC_RXQ_CTRL4_VFFQE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set VLAN tag filter fail packets queue enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANTagFilterFailPacketQueueEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_RXQ_CTRL4 = (pEnet->MAC_RXQ_CTRL4 & ~ENET_MAC_RXQ_CTRL4_VFFQE_MASK) | + ENET_MAC_RXQ_CTRL4_VFFQE(bEnable ? 1u : 0u); +} + +/** + * @brief Get VLAN tag filter fail packets queue + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MTL_QueueType + */ +LOCAL_INLINE ENET_MTL_QueueType ENET_HWA_MAC_GetVLANTagFilterFailPacketQueue(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL4 & ENET_MAC_RXQ_CTRL4_VFFQ_MASK) >> ENET_MAC_RXQ_CTRL4_VFFQ_SHIFT; + return (ENET_MTL_QueueType)u32TmpVal; +} + +/** + * @brief Set VLAN tag filter fail packets queue + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eQueue queue id + */ +LOCAL_INLINE void ENET_HWA_MAC_SetVLANTagFilterFailPacketQueue(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MAC_RXQ_CTRL4 = (pEnet->MAC_RXQ_CTRL4 & ~ENET_MAC_RXQ_CTRL4_VFFQ_MASK) | + ENET_MAC_RXQ_CTRL4_VFFQ(eQueue); +} + +/** + * @brief Get multicast address filter fail packets queue enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true multicast address filter fail packets queue is enabled + * @return false multicast address filter fail packets queue is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMulticastAddrFilterFailPacketQueueEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL4 & ENET_MAC_RXQ_CTRL4_MFFQE_MASK) >> ENET_MAC_RXQ_CTRL4_MFFQE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set multicast address filter fail packets queue enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMulticastAddrFilterFailPacketQueueEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_RXQ_CTRL4 = (pEnet->MAC_RXQ_CTRL4 & ~ENET_MAC_RXQ_CTRL4_MFFQE_MASK) | + ENET_MAC_RXQ_CTRL4_MFFQE(bEnable ? 1u : 0u); +} + +/** + * @brief Get multicast address filter fail packets queue + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MTL_QueueType + */ +LOCAL_INLINE ENET_MTL_QueueType ENET_HWA_MAC_GetMulticastAddrFilterFailPacketQueue(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL4 & ENET_MAC_RXQ_CTRL4_MFFQ_MASK) >> ENET_MAC_RXQ_CTRL4_MFFQ_SHIFT; + return (ENET_MTL_QueueType)u32TmpVal; +} + +/** + * @brief Set multicast address filter fail packets queue + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eQueue queue id + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMulticastAddrFilterFailPacketQueue(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MAC_RXQ_CTRL4 = (pEnet->MAC_RXQ_CTRL4 & ~ENET_MAC_RXQ_CTRL4_MFFQ_MASK) | + ENET_MAC_RXQ_CTRL4_MFFQ(eQueue); +} + +/** + * @brief Get unicast address filter fail packets queue enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @return true unicast address filter fail packets queue is enabled + * @return false unicast address filter fail packets queue is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetUnicastAddrFilterFailPacketQueueEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL4 & ENET_MAC_RXQ_CTRL4_UFFQE_MASK) >> ENET_MAC_RXQ_CTRL4_UFFQE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set unicast address filter fail packets queue enable flag + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetUnicastAddrFilterFailPacketQueueEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_RXQ_CTRL4 = (pEnet->MAC_RXQ_CTRL4 & ~ENET_MAC_RXQ_CTRL4_UFFQE_MASK) | + ENET_MAC_RXQ_CTRL4_UFFQE(bEnable ? 1u : 0u); +} + +/** + * @brief Get unicast address filter fail packets queue + * + * @param [in] pEnet the base address of the Ethernet instance + * @return ENET_MTL_QueueType + */ +LOCAL_INLINE ENET_MTL_QueueType ENET_HWA_MAC_GetUnicastAddrFilterFailPacketQueue(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RXQ_CTRL4 & ENET_MAC_RXQ_CTRL4_UFFQ_MASK) >> ENET_MAC_RXQ_CTRL4_UFFQ_SHIFT; + return (ENET_MTL_QueueType)u32TmpVal; +} + +/** + * @brief Set unicast address filter fail packets queue + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eQueue queue id + */ +LOCAL_INLINE void ENET_HWA_MAC_SetUnicastAddrFilterFailPacketQueue(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MAC_RXQ_CTRL4 = (pEnet->MAC_RXQ_CTRL4 & ~ENET_MAC_RXQ_CTRL4_UFFQ_MASK) | + ENET_MAC_RXQ_CTRL4_UFFQ(eQueue); +} + +/** + * @brief Get the interrupt status of ENET MAC + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t the interrupt status + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetInterruptStatus(const ENET_Type *const pEnet) +{ + return pEnet->MAC_INTERRUPT_STATUS; +} + +/** + * @brief Clear the interrupt flags of MAC + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Interrupt the interrupt events to be cleared + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearInterruptStatus(ENET_Type *const pEnet, uint32_t u32Interrupt) +{ + pEnet->MAC_INTERRUPT_STATUS = u32Interrupt; +} + +/** + * @brief Get the MDIO interrupt status + * + * @param [in] pEnet the base address of the ENET instance + * @return true the MDIO operation is complete + * @return false there is no MDIO operation completion event + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMDIOInterruptStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_STATUS & ENET_MAC_INTERRUPT_STATUS_MDIOIS_MASK) >> + ENET_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear the MDIO interrupt status + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearMDIOInterruptStatus(ENET_Type *const pEnet) +{ + pEnet->MAC_INTERRUPT_STATUS &= ENET_MAC_INTERRUPT_STATUS_MDIOIS_MASK; +} + +/** + * @brief Get the receive interrupt status + * + * @param [in] pEnet the base address of the ENET instance + * @return bool indicate the status of received packets + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetRxInterruptStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_STATUS & ENET_MAC_INTERRUPT_STATUS_RXSTSIS_MASK) >> + ENET_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get the transmit interrupt status + * + * @param [in] pEnet the base address of the ENET instance + * @return bool indicate the status of transmit packets + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTxInterruptStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_STATUS & ENET_MAC_INTERRUPT_STATUS_TXSTSIS_MASK) >> + ENET_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get the timestamp interrupt status + * + * @param [in] pEnet the base address of the ENET instance + * @return bool indicate the status of timestamp interrupt + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTimestampInterruptStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_STATUS & ENET_MAC_INTERRUPT_STATUS_TSIS_MASK) >> + ENET_MAC_INTERRUPT_STATUS_TSIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get the MMC transmit interrupt status + * @note This field is valid only when you enable MAC Management Counters(MMC) + * + * @param [in] pEnet the base address of the ENET instance + * @return bool indicate the status of MMC transmit + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMMCTxInterruptStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_STATUS & ENET_MAC_INTERRUPT_STATUS_MMCTXIS_MASK) >> + ENET_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get the MMC receive interrupt status + * @note This field is valid only when you enable MAC Management Counters(MMC) + * + * @param [in] pEnet the base address of the ENET instance + * @return bool indicate the status of MMC receive + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMMCRxInterruptStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_STATUS & ENET_MAC_INTERRUPT_STATUS_MMCRXIS_MASK) >> + ENET_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get the MMC interrupt status + * @note This field is valid only when you enable MAC Management Counters(MMC) + * + * @param [in] pEnet the base address of the ENET instance + * @return bool indicate the status of MMC interrupt + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMMCInterruptStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_STATUS & ENET_MAC_INTERRUPT_STATUS_MMCIS_MASK) >> + ENET_MAC_INTERRUPT_STATUS_MMCIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get the PHY interrupt status + * + * @param [in] pEnet the base address of the ENET instance + * @return bool indicate whether the PHY interrupt is detected + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetPhyInterruptStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_STATUS & ENET_MAC_INTERRUPT_STATUS_PHYIS_MASK) >> + ENET_MAC_INTERRUPT_STATUS_PHYIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear the PHY interrupt status + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearPhyInterruptStatus(ENET_Type *const pEnet) +{ + pEnet->MAC_INTERRUPT_STATUS &= ENET_MAC_INTERRUPT_STATUS_MDIOIS_MASK; +} + +/** + * @brief Get the MAC interrupts enable register value + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC interrupts enable register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetInterruptEnable(const ENET_Type *const pEnet) +{ + return pEnet->MAC_INTERRUPT_ENABLE; +} + +/** + * @brief Set the MAC interrupts enable register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32IntEnable interrupts enable value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetInterruptEnable(ENET_Type *const pEnet, uint32_t u32IntEnable) +{ + pEnet->MAC_INTERRUPT_ENABLE = u32IntEnable; +} + +/** + * @brief Get MDIO interrupt enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true MDIO interrupt is enabled + * @return false MDIO interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMDIOInterruptEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_ENABLE & ENET_MAC_INTERRUPT_ENABLE_MDIOIE_MASK) >> + ENET_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set MDIO interrupt enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMDIOInterruptEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_INTERRUPT_ENABLE = (pEnet->MAC_INTERRUPT_ENABLE & ~ENET_MAC_INTERRUPT_ENABLE_MDIOIE_MASK) | + ENET_MAC_INTERRUPT_ENABLE_MDIOIE(bEnable ? 1u : 0u); +} + +/** + * @brief Get receive status interrupt enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true receive status interrupt is enabled + * @return false receive status interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetRxStatusInterruptEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_ENABLE & ENET_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK) >> + ENET_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set receive status interrupt enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetRxStatusInterruptEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_INTERRUPT_ENABLE = (pEnet->MAC_INTERRUPT_ENABLE & ~ENET_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK) | + ENET_MAC_INTERRUPT_ENABLE_RXSTSIE(bEnable ? 1u : 0u); +} + +/** + * @brief Get transmit status interrupt enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true transmit status interrupt is enabled + * @return false transmit status interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTxStatusInterruptEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_ENABLE & ENET_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK) >> + ENET_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set transmit status interrupt enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTxStatusInterruptEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_INTERRUPT_ENABLE = (pEnet->MAC_INTERRUPT_ENABLE & ~ENET_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK) | + ENET_MAC_INTERRUPT_ENABLE_TXSTSIE(bEnable ? 1u : 0u); +} + +/** + * @brief Get timestamp interrupt enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true timestamp interrupt is enabled + * @return false timestamp interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTimestampInterruptEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_ENABLE & ENET_MAC_INTERRUPT_ENABLE_TSIE_MASK) >> + ENET_MAC_INTERRUPT_ENABLE_TSIE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set timestamp interrupt enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimestampInterruptEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_INTERRUPT_ENABLE = (pEnet->MAC_INTERRUPT_ENABLE & ~ENET_MAC_INTERRUPT_ENABLE_TSIE_MASK) | + ENET_MAC_INTERRUPT_ENABLE_TSIE(bEnable ? 1u : 0u); +} + +/** + * @brief Get phy interrupt enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true phy interrupt is enabled + * @return false phy interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetPhyInterruptEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_INTERRUPT_ENABLE & ENET_MAC_INTERRUPT_ENABLE_PHYIE_MASK) >> + ENET_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set phy interrupt enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPhyInterruptEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_INTERRUPT_ENABLE = (pEnet->MAC_INTERRUPT_ENABLE & ~ENET_MAC_INTERRUPT_ENABLE_PHYIE_MASK) | + ENET_MAC_INTERRUPT_ENABLE_PHYIE(bEnable ? 1u : 0u); +} + +/** + * @brief Get the MAC receive and transmit status + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t the MAC receive and transmit status + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxTxStatus(const ENET_Type *const pEnet) +{ + return pEnet->MAC_RX_TX_STATUS; +} + +/** + * @brief Clear the MAC receive and transmit status + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Status the status flags to be cleared + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearRxTxStatus(ENET_Type *const pEnet, uint32_t u32Status) +{ + pEnet->MAC_RX_TX_STATUS = u32Status; +} + +/** + * @brief Get the receive watchdog timeout status + * + * @param [in] pEnet the base address of the ENET instance + * @return true receive watchdog timeout + * @return false no receive watchdog timeout + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetRxWDGTimeoutStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RX_TX_STATUS & ENET_MAC_RX_TX_STATUS_RWT_MASK) >> ENET_MAC_RX_TX_STATUS_RWT_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear the receive watchdog timeout status + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearRxWDGTimeoutStatus(ENET_Type *const pEnet) +{ + pEnet->MAC_RX_TX_STATUS &= ENET_MAC_RX_TX_STATUS_RWT_MASK; +} + +/** + * @brief Get the excessive collision status + * + * @param [in] pEnet the base address of the ENET instance + * @return true excessive collision is sensed + * @return false no collision + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTxExcessiveCollisionStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RX_TX_STATUS & ENET_MAC_RX_TX_STATUS_EXCOL_MASK) >> ENET_MAC_RX_TX_STATUS_EXCOL_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear the excessive collision status + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearTxExcessiveCollisionStatus(ENET_Type *const pEnet) +{ + pEnet->MAC_RX_TX_STATUS &= ENET_MAC_RX_TX_STATUS_EXCOL_MASK; +} + +/** + * @brief Get the late collision status + * + * @param [in] pEnet the base address of the ENET instance + * @return true late collision is sensed + * @return false no collision + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTxLateCollisionStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RX_TX_STATUS & ENET_MAC_RX_TX_STATUS_LCOL_MASK) >> ENET_MAC_RX_TX_STATUS_LCOL_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear the late collision status + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearTxLateCollisionStatus(ENET_Type *const pEnet) +{ + pEnet->MAC_RX_TX_STATUS &= ENET_MAC_RX_TX_STATUS_LCOL_MASK; +} + +/** + * @brief Get the excessive deferral status + * + * @param [in] pEnet the base address of the ENET instance + * @return true excessive deferral is sensed + * @return false no excessive deferral + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTxExcessiveDeferralStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RX_TX_STATUS & ENET_MAC_RX_TX_STATUS_EXDEF_MASK) >> ENET_MAC_RX_TX_STATUS_EXDEF_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear the excessive deferral status + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearExcessiveDeferralStatus(ENET_Type *const pEnet) +{ + pEnet->MAC_RX_TX_STATUS &= ENET_MAC_RX_TX_STATUS_EXDEF_MASK; +} + +/** + * @brief Indicates the status of carrier signal + * + * @param [in] pEnet the base address of the ENET instance + * @return true loss of carrier + * @return false carrier is present + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTxLossOfCarrierStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RX_TX_STATUS & ENET_MAC_RX_TX_STATUS_LCARR_MASK) >> ENET_MAC_RX_TX_STATUS_LCARR_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear the loss of carrier status + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearLossOfCarrierStatus(ENET_Type *const pEnet) +{ + pEnet->MAC_RX_TX_STATUS &= ENET_MAC_RX_TX_STATUS_LCARR_MASK; +} + +/** + * @brief Indicates whether the carrier signal is present from the PHY at the end of preamble transmission + * + * @param [in] pEnet the base address of the ENET instance + * @return true carrier is absent + * @return false carrier is present + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTxNoCarrierStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RX_TX_STATUS & ENET_MAC_RX_TX_STATUS_NCARR_MASK) >> ENET_MAC_RX_TX_STATUS_NCARR_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear the no carrier status + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearTxNoCarrierStatus(ENET_Type *const pEnet) +{ + pEnet->MAC_RX_TX_STATUS &= ENET_MAC_RX_TX_STATUS_NCARR_MASK; +} + +/** + * @brief Indicates whether a transmit jabber timer timeout occurred + * + * @param [in] pEnet the base address of the ENET instance + * @return true transmit jabber timeout occured + * @return false no transmit jabber timeout occured + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTxJabberTimeoutStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_RX_TX_STATUS & ENET_MAC_RX_TX_STATUS_TJT_MASK) >> ENET_MAC_RX_TX_STATUS_TJT_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear the transmit jabber timer timeout status + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearTxJabberTimeoutStatus(ENET_Type *const pEnet) +{ + pEnet->MAC_RX_TX_STATUS &= ENET_MAC_RX_TX_STATUS_TJT_MASK; +} + +/** + * @brief Get MAC version + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC version number + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMACVersion(const ENET_Type *const pEnet) +{ + return pEnet->MAC_VERSION; +} + +/** + * @brief Get MAC debug status + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC debug status + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetDebugStatus(const ENET_Type *const pEnet) +{ + return pEnet->MAC_DEBUG; +} + +/** + * @brief Get MAC transmit packet controller status + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_TxPacketControllerStatusType + */ +LOCAL_INLINE ENET_MAC_TxPacketControllerStatusType ENET_HWA_MAC_GetTxPacketControllerStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_DEBUG & ENET_MAC_DEBUG_TFCSTS_MASK) >> ENET_MAC_DEBUG_TFCSTS_SHIFT; + return (ENET_MAC_TxPacketControllerStatusType)u32TmpVal; +} + +/** + * @brief Get MAC GMII or MII transmit protocol engine status + * + * @param [in] pEnet the base address of the ENET instance + * @return true transmit protocol engine is active + * @return false transmit protocol engine is inactive + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTxPacketEngineStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_DEBUG & ENET_MAC_DEBUG_TPESTS_MASK) >> ENET_MAC_DEBUG_TPESTS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get MAC receive packet controller FIFO status + * + * @param [in] pEnet the base address of the ENET instance + * @return true receive packet controller FIFO is active + * @return false receive packet controller FIFO is inactive + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetRxPacketControllerFIFOStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_DEBUG & ENET_MAC_DEBUG_RFCFCSTS_MASK) >> ENET_MAC_DEBUG_RFCFCSTS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get MAC GMII or MII receive protocol engine status + * + * @param [in] pEnet the base address of the ENET instance + * @return true receive protocol engine is active + * @return false receive protocol engine is inactive + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetRxProtocalEngineStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_DEBUG & ENET_MAC_DEBUG_RPESTS_MASK) >> ENET_MAC_DEBUG_RPESTS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get MAC hardware features 0 + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC hardware features 0 + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetHwFeature0(const ENET_Type *const pEnet) +{ + return pEnet->MAC_HW_FEATURE0; +} + +/** + * @brief Get phy interface mii mode + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_MiiModeType + */ +LOCAL_INLINE ENET_MAC_MiiModeType ENET_HWA_MAC_GetPhyMiiMode(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_HW_FEATURE0 & ENET_MAC_HW_FEATURE0_ACTPHYSEL_MASK) >> + ENET_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT; + return (ENET_MAC_MiiModeType)u32TmpVal; +} + +/** + * @brief Get MAC hardware features 1 + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC hardware features 1 + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetHwFeature1(const ENET_Type *const pEnet) +{ + return pEnet->MAC_HW_FEATURE1; +} + +/** + * @brief Get MAC hardware features 2 + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC hardware features 2 + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetHwFeature2(const ENET_Type *const pEnet) +{ + return pEnet->MAC_HW_FEATURE2; +} + +/** + * @brief Get MAC hardware features 3 + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC hardware features 3 + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetHwFeature3(const ENET_Type *const pEnet) +{ + return pEnet->MAC_HW_FEATURE3; +} + +/** + * @brief Get MAC MDIO address register value + * + * @param [in] pEnet the base address of the ENET instance + * @return MDIO address register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMDIOAddress(const ENET_Type *const pEnet) +{ + return pEnet->MAC_MDIO_ADDRESS; +} + +/** + * @brief Set MAC MDIO address register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32MDIOAddr MDIO address register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMDIOAddress(ENET_Type *const pEnet, uint32_t u32MDIOAddr) +{ + pEnet->MAC_MDIO_ADDRESS = u32MDIOAddr; +} + +/** + * @brief Get preamble suppression enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true MDIO preamble suppression is enabled + * @return false MDIO preamble suppression is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetPreambleSuppressionEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_MDIO_ADDRESS & ENET_MAC_MDIO_ADDRESS_PSE_MASK) >> ENET_MAC_MDIO_ADDRESS_PSE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set MDIO preamble suppression enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPreambleSuppressionEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_MDIO_ADDRESS = (pEnet->MAC_MDIO_ADDRESS & ~ENET_MAC_MDIO_ADDRESS_PSE_MASK) | + ENET_MAC_MDIO_ADDRESS_PSE(bEnable ? 1u : 0u); +} + +/** + * @brief Get MDIO back to back transactions enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true MDIO back to back transactions is enabled + * @return false MDIO back to back transactions is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetBackToBackTransactionEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_MDIO_ADDRESS & ENET_MAC_MDIO_ADDRESS_BTB_MASK) >> ENET_MAC_MDIO_ADDRESS_BTB_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set MDIO back to back transactions enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetBackToBackTransactionEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_MDIO_ADDRESS = (pEnet->MAC_MDIO_ADDRESS & ~ENET_MAC_MDIO_ADDRESS_BTB_MASK) | + ENET_MAC_MDIO_ADDRESS_BTB(bEnable ? 1u : 0u); +} + +/** + * @brief Get MDIO physical layer address + * + * @param [in] pEnet the base address of the ENET instance + * @return phy address + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetPhysicalLayerAddr(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_MDIO_ADDRESS & ENET_MAC_MDIO_ADDRESS_PA_MASK) >> ENET_MAC_MDIO_ADDRESS_PA_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set MDIO physical layer address + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Addr phy address + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPhysicalLayerAddr(ENET_Type *const pEnet, uint8_t u8Addr) +{ + pEnet->MAC_MDIO_ADDRESS = (pEnet->MAC_MDIO_ADDRESS & ~ENET_MAC_MDIO_ADDRESS_PA_MASK) | + ENET_MAC_MDIO_ADDRESS_PA(u8Addr); +} + +/** + * @brief Get MDIO phy register(clause22) or MMD device(clause 45) + * + * @param [in] pEnet the base address of the ENET instance + * @return phy register or device address + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetPhyRegisterOrDeviceAddr(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_MDIO_ADDRESS & ENET_MAC_MDIO_ADDRESS_RDA_MASK) >> ENET_MAC_MDIO_ADDRESS_RDA_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set MDIO phy register(clause22) or MMD device(clause 45) + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Addr phy register or device address + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPhyRegisterOrDeviceAddr(ENET_Type *const pEnet, uint8_t u8Addr) +{ + pEnet->MAC_MDIO_ADDRESS = (pEnet->MAC_MDIO_ADDRESS & ~ENET_MAC_MDIO_ADDRESS_RDA_MASK) | + ENET_MAC_MDIO_ADDRESS_RDA(u8Addr); +} + +/** + * @brief Get the number of trailing clock cycles + * + * @param [in] pEnet the base address of the ENET instance + * @return trailing clock cycles + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetTrailingClockCnt(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_MDIO_ADDRESS & ENET_MAC_MDIO_ADDRESS_NTC_MASK) >> ENET_MAC_MDIO_ADDRESS_NTC_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set MDIO trailing clock cycles + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Cnt trailing clock cycles(range 0~7) + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTrailingClockCnt(ENET_Type *const pEnet, uint8_t u8Cnt) +{ + pEnet->MAC_MDIO_ADDRESS = (pEnet->MAC_MDIO_ADDRESS & ~ENET_MAC_MDIO_ADDRESS_NTC_MASK) | + ENET_MAC_MDIO_ADDRESS_NTC(u8Cnt); +} + +/** + * @brief Get the MDC clock range + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_CSRClockRangeType + */ +LOCAL_INLINE ENET_MAC_CSRClockRangeType ENET_HWA_MAC_GetCSRClockRange(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_MDIO_ADDRESS & ENET_MAC_MDIO_ADDRESS_CR_MASK) >> ENET_MAC_MDIO_ADDRESS_CR_SHIFT; + return (ENET_MAC_CSRClockRangeType)u32TmpVal; +} + +/** + * @brief Set the MDC clock range + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eRange values defined in ENET_MAC_CSRClockRangeType + */ +LOCAL_INLINE void ENET_HWA_MAC_SetCSRClockRange(ENET_Type *const pEnet, ENET_MAC_CSRClockRangeType eRange) +{ + pEnet->MAC_MDIO_ADDRESS = (pEnet->MAC_MDIO_ADDRESS & ~ENET_MAC_MDIO_ADDRESS_CR_MASK) | + ENET_MAC_MDIO_ADDRESS_CR(eRange); +} + +/** + * @brief Get skip address packet enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true skip address packet is enabled + * @return false skip address packet is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetSkipAddrPacketEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_MDIO_ADDRESS & ENET_MAC_MDIO_ADDRESS_SKAP_MASK) >> ENET_MAC_MDIO_ADDRESS_SKAP_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set skip address packet enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSkipAddrPacketEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_MDIO_ADDRESS = (pEnet->MAC_MDIO_ADDRESS & ~ENET_MAC_MDIO_ADDRESS_SKAP_MASK) | + ENET_MAC_MDIO_ADDRESS_SKAP(bEnable ? 1u : 0u); +} + +/** + * @brief Get phy operation command + * + * @param [in] pEnet the base address of the ENET instance + * @return Commands defined in ENET_MAC_PhyOperationCmdType + */ +LOCAL_INLINE ENET_MAC_PhyOperationCmdType ENET_HWA_MAC_GetPhyOperationCommand(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_MDIO_ADDRESS & (ENET_MAC_MDIO_ADDRESS_GOC_0_MASK | + ENET_MAC_MDIO_ADDRESS_GOC_1_MASK)) >> + ENET_MAC_MDIO_ADDRESS_GOC_0_SHIFT; + return (ENET_MAC_PhyOperationCmdType)u32TmpVal; +} + +/** + * @brief Set phy operation command + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eCmd Commands defined in ENET_MAC_PhyOperationCmdType + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPhyOperationCommand(ENET_Type *const pEnet, ENET_MAC_PhyOperationCmdType eCmd) +{ + pEnet->MAC_MDIO_ADDRESS = (pEnet->MAC_MDIO_ADDRESS & ~(ENET_MAC_MDIO_ADDRESS_GOC_0_MASK | + ENET_MAC_MDIO_ADDRESS_GOC_1_MASK)) | + ENET_MAC_MDIO_ADDRESS_GOC_0((uint32_t)eCmd & 0x01u) | + ENET_MAC_MDIO_ADDRESS_GOC_1(((uint32_t)eCmd & 0x02u) >> 1u); +} + +/** + * @brief Get MDIO clause version + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_PHY_CLAUSE_22 access phy use clause 22 mode + @return ENET_MAC_PHY_CLAUSE_45 access phy use clause 45 mode + */ +LOCAL_INLINE ENET_MAC_PhyClauseVersionType ENET_HWA_MAC_GetPhyClauseVersion(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_MDIO_ADDRESS & ENET_MAC_MDIO_ADDRESS_C45E_MASK) >> ENET_MAC_MDIO_ADDRESS_C45E_SHIFT; + return (ENET_MAC_PhyClauseVersionType)u32TmpVal; +} + +/** + * @brief Set MDIO clause version + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eVersion ENET_MAC_PHY_CLAUSE_22 or ENET_MAC_PHY_CLAUSE_45 + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPhyClauseVersion(ENET_Type *const pEnet, ENET_MAC_PhyClauseVersionType eVersion) +{ + pEnet->MAC_MDIO_ADDRESS = (pEnet->MAC_MDIO_ADDRESS & ~ENET_MAC_MDIO_ADDRESS_C45E_MASK) | + ENET_MAC_MDIO_ADDRESS_C45E(eVersion); +} + +/** + * @brief Get MDIO busy status + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_STATUS_IDLE GMII status is idle + @return ENET_MAC_STATUS_BUSY GMII status is busy, + */ +LOCAL_INLINE ENET_MAC_StatusType ENET_HWA_MAC_GetGMIIStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_MDIO_ADDRESS & ENET_MAC_MDIO_ADDRESS_GB_MASK) >> ENET_MAC_MDIO_ADDRESS_GB_SHIFT; + return (ENET_MAC_StatusType)u32TmpVal; +} + +/** + * @brief Set MDIO busy to initiate a read or write access + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_SetGMIIBusy(ENET_Type *const pEnet) +{ + pEnet->MAC_MDIO_ADDRESS |= ENET_MAC_MDIO_ADDRESS_GB_MASK; +} + +/** + * @brief Get MDIO data register value + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMDIOData(const ENET_Type *const pEnet) +{ + return pEnet->MAC_MDIO_DATA; +} + +/** + * @brief Set MDIO data register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Data data register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMDIOData(ENET_Type *const pEnet, uint32_t u32Data) +{ + pEnet->MAC_MDIO_DATA = u32Data; +} + +/** + * @brief Get phy register address + * @note This field is valid only in clause 45 mode + * + * @param [in] pEnet the base address of the ENET instance + * @return phy register address + */ +LOCAL_INLINE uint16_t ENET_HWA_MAC_GetPhyRegisterAddr(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_MDIO_DATA & ENET_MAC_MDIO_DATA_RA_MASK) >> ENET_MAC_MDIO_DATA_RA_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set phy register address + * @note This field is valid only in clause 45 mode + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u16Addr phy register address + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPhyRegisterAddr(ENET_Type *const pEnet, uint16_t u16Addr) +{ + pEnet->MAC_MDIO_DATA = (pEnet->MAC_MDIO_DATA & ~ENET_MAC_MDIO_DATA_RA_MASK) | ENET_MAC_MDIO_DATA_RA(u16Addr); +} + +/** + * @brief Get MDIO data + * + * @param [in] pEnet the base address of the ENET instance + * @return data value + */ +LOCAL_INLINE uint16_t ENET_HWA_MAC_GetGMIIData(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_MDIO_DATA & ENET_MAC_MDIO_DATA_GD_MASK) >> ENET_MAC_MDIO_DATA_GD_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set MDIO data + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u16Data MDIO data + */ +LOCAL_INLINE void ENET_HWA_MAC_SetGMIIData(ENET_Type *const pEnet, uint16_t u16Data) +{ + pEnet->MAC_MDIO_DATA = (pEnet->MAC_MDIO_DATA & ~ENET_MAC_MDIO_DATA_GD_MASK) | ENET_MAC_MDIO_DATA_GD(u16Data); +} + +#if ENET_SUPPORT_TIME_SENSITIVE_NETWORK +/** + * @brief Enable TX frame preemption + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable 1U enable or 0U disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetFramePreemptionEnFlag(ENET_Type *const pEnet, uint8_t bEnable) +{ + pEnet->MAC_FPE_CTRL_STS = (pEnet->MAC_FPE_CTRL_STS & ~ENET_MAC_FPE_CTRL_STS_EFPE_MASK) | + ENET_MAC_FPE_CTRL_STS_EFPE(bEnable); +} +#endif /* ENET_SUPPORT_TIME_SENSITIVE_NETWORK */ + +/** + * @brief Get presentation time in ns + * + * @param [in] pEnet the base address of the ENET instance + * @return presentation time + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetPresentationTime(const ENET_Type *const pEnet) +{ + return pEnet->MAC_PRESN_TIME_NS; +} + +/** + * @brief Get presentation time update + * + * @param [in] pEnet the base address of the ENET instance + * @return update time value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetPresentationTimeUpdata(const ENET_Type *const pEnet) +{ + return pEnet->MAC_PRESN_TIME_UPDT; +} + +/** + * @brief Set presentation time update + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32NanoSeconds update time value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPresentationTimeUpdata(ENET_Type *const pEnet, uint32_t u32NanoSeconds) +{ + pEnet->MAC_PRESN_TIME_UPDT = u32NanoSeconds; +} + +/** + * @brief Get MAC address0 high register value + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC address0 high register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMacAddr0High(const ENET_Type *const pEnet) +{ + return pEnet->MAC_ADDRESS0_HIGH; +} + +/** + * @brief Set MAC address0 high register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32AddrHigh MAC address0 high register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetAddr0High(ENET_Type *const pEnet, uint32_t u32AddrHigh) +{ + pEnet->MAC_ADDRESS0_HIGH = u32AddrHigh; +} + +/** + * @brief Get MAC address0 low register value + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC address0 low register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMacAddr0Low(const ENET_Type *const pEnet) +{ + return pEnet->MAC_ADDRESS0_LOW; +} + +/** + * @brief Set MAC address0 low register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32AddrLow MAC address0 low register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMacAddr0Low(ENET_Type *const pEnet, uint32_t u32AddrLow) +{ + pEnet->MAC_ADDRESS0_LOW = u32AddrLow; +} + +/** + * @brief Get MAC address0 enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true MAC address0 is enabled + * @return false MAC address0 is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMacAddr0EnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_ADDRESS0_HIGH & ENET_MAC_ADDRESS0_HIGH_AE_MASK) >> ENET_MAC_ADDRESS0_HIGH_AE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get MAC address0 DMA channel select + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC address0 DMA channel select + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetMacAddr0DMAChannelSelect(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_ADDRESS0_HIGH & ENET_MAC_ADDRESS0_HIGH_DCS_MASK) >> ENET_MAC_ADDRESS0_HIGH_DCS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set MAC address0 DMA channel select + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8DMAChannelSel MAC address0 DMA channel select + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMacAddr0DMAChannelSelect(ENET_Type *const pEnet, uint8_t u8DMAChannelSel) +{ + pEnet->MAC_ADDRESS0_HIGH = (pEnet->MAC_ADDRESS0_HIGH & ~ENET_MAC_ADDRESS0_HIGH_DCS_MASK) | + ENET_MAC_ADDRESS0_HIGH_DCS(u8DMAChannelSel); +} + +/** + * @brief Get MAC address1 high register value + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC address1 high register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMacAddr1High(const ENET_Type *const pEnet) +{ + return pEnet->MAC_ADDRESS1_HIGH; +} + +/** + * @brief Set MAC address1 high register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32AddrHigh MAC address1 high register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetAddr1High(ENET_Type *const pEnet, uint32_t u32AddrHigh) +{ + pEnet->MAC_ADDRESS1_HIGH = u32AddrHigh; +} + +/** + * @brief Get MAC address1 low register value + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC address1 low register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMacAddr1Low(const ENET_Type *const pEnet) +{ + return pEnet->MAC_ADDRESS1_LOW; +} + +/** + * @brief Set MAC address1 low register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32AddrLow MAC address1 low register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMacAddr1Low(ENET_Type *const pEnet, uint32_t u32AddrLow) +{ + pEnet->MAC_ADDRESS1_LOW = u32AddrLow; +} + +/** + * @brief Get MAC address1 enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true MAC address1 is enabled + * @return false MAC address1 is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMacAddr1EnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_ADDRESS1_HIGH & ENET_MAC_ADDRESS1_HIGH_AE_MASK) >> ENET_MAC_ADDRESS1_HIGH_AE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set MAC address1 enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMacAddr1EnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_ADDRESS1_HIGH = (pEnet->MAC_ADDRESS1_HIGH & ~ENET_MAC_ADDRESS1_HIGH_AE_MASK) | + ENET_MAC_ADDRESS1_HIGH_AE(bEnable ? 1u : 0u); +} + +/** + * @brief Get MAC address1 compare mode + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_ADDR_TYPE_DEST MAC Address1 is used to compare with the DA fields + * @return ENET_MAC_ADDR_TYPE_SRC MAC Address1 is used to compare with the SA fields + */ +LOCAL_INLINE ENET_MAC_AddrType ENET_HWA_MAC_GetMacAddr1Type(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_ADDRESS1_HIGH & ENET_MAC_ADDRESS1_HIGH_SA_MASK) >> ENET_MAC_ADDRESS1_HIGH_SA_SHIFT; + return (ENET_MAC_AddrType)u32TmpVal; +} + +/** + * @brief Set MAC address1 compare mode + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eAddrType ENET_MAC_ADDR_TYPE_DEST or ENET_MAC_ADDR_TYPE_SRC + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMacAddr1Type(ENET_Type *const pEnet, ENET_MAC_AddrType eAddrType) +{ + pEnet->MAC_ADDRESS1_HIGH = (pEnet->MAC_ADDRESS1_HIGH & ~ENET_MAC_ADDRESS1_HIGH_SA_MASK) | + ENET_MAC_ADDRESS1_HIGH_SA(eAddrType); +} + +/** + * @brief Get MAC address1 mask byte control + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC address1 mask byte value + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetMacAddr1MaskByteCtrl(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_ADDRESS1_HIGH & ENET_MAC_ADDRESS1_HIGH_MBC_MASK) >> ENET_MAC_ADDRESS1_HIGH_MBC_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set MAC address1 mask byte control + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8MaskCtrl MAC address1 mask byte value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMacAddr1MaskByteCtrl(ENET_Type *const pEnet, uint8_t u8MaskCtrl) +{ + pEnet->MAC_ADDRESS1_HIGH = (pEnet->MAC_ADDRESS1_HIGH & ~ENET_MAC_ADDRESS1_HIGH_MBC_MASK) | + ENET_MAC_ADDRESS1_HIGH_MBC(u8MaskCtrl); +} + +/** + * @brief Get MAC address1 DMA channel select + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC address1 DMA channel select + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetMacAddr1DMAChannelSelect(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_ADDRESS1_HIGH & ENET_MAC_ADDRESS1_HIGH_DCS_MASK) >> ENET_MAC_ADDRESS1_HIGH_DCS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set MAC address1 DMA channel select + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8DMAChannelSel MAC address1 DMA channel select + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMacAddr1DMAChannelSelect(ENET_Type *const pEnet, uint8_t u8DMAChannelSel) +{ + pEnet->MAC_ADDRESS1_HIGH = (pEnet->MAC_ADDRESS1_HIGH & ~ENET_MAC_ADDRESS1_HIGH_DCS_MASK) | + ENET_MAC_ADDRESS1_HIGH_DCS(u8DMAChannelSel); +} + +/** + * @brief Get MAC address2 high register value + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC address2 high register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMacAddr2High(const ENET_Type *const pEnet) +{ + return pEnet->MAC_ADDRESS2_HIGH; +} + +/** + * @brief Set MAC address2 high register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32AddrHigh MAC address2 high register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetAddr2High(ENET_Type *const pEnet, uint32_t u32AddrHigh) +{ + pEnet->MAC_ADDRESS2_HIGH = u32AddrHigh; +} + +/** + * @brief Get MAC address2 low register value + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC address2 low register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMacAddr2Low(const ENET_Type *const pEnet) +{ + return pEnet->MAC_ADDRESS2_LOW; +} + +/** + * @brief Set MAC address2 low register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32AddrLow MAC address2 low register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMacAddr2Low(ENET_Type *const pEnet, uint32_t u32AddrLow) +{ + pEnet->MAC_ADDRESS2_LOW = u32AddrLow; +} + +/** + * @brief Get MAC address2 enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true MAC address2 is enabled + * @return false MAC address2 is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMacAddr2EnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_ADDRESS2_HIGH & ENET_MAC_ADDRESS2_HIGH_AE_MASK) >> ENET_MAC_ADDRESS2_HIGH_AE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set MAC address2 enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMacAddr2EnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_ADDRESS2_HIGH = (pEnet->MAC_ADDRESS2_HIGH & ~ENET_MAC_ADDRESS2_HIGH_AE_MASK) | + ENET_MAC_ADDRESS2_HIGH_AE(bEnable ? 1u : 0u); +} + +/** + * @brief Get MAC address2 compare mode + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_ADDR_TYPE_DEST MAC Address2 is used to compare with the DA fields + * @return ENET_MAC_ADDR_TYPE_SRC MAC Address2 is used to compare with the SA fields + */ +LOCAL_INLINE ENET_MAC_AddrType ENET_HWA_MAC_GetMacAddr2Type(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_ADDRESS2_HIGH & ENET_MAC_ADDRESS2_HIGH_SA_MASK) >> ENET_MAC_ADDRESS2_HIGH_SA_SHIFT; + return (ENET_MAC_AddrType)u32TmpVal; +} + +/** + * @brief Set MAC address2 compare mode + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eAddrType ENET_MAC_ADDR_TYPE_DEST or ENET_MAC_ADDR_TYPE_SRC + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMacAddr2Type(ENET_Type *const pEnet, ENET_MAC_AddrType eAddrType) +{ + pEnet->MAC_ADDRESS2_HIGH = (pEnet->MAC_ADDRESS2_HIGH & ~ENET_MAC_ADDRESS2_HIGH_SA_MASK) | + ENET_MAC_ADDRESS2_HIGH_SA(eAddrType); +} + +/** + * @brief Get MAC address2 mask byte control + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC address2 mask byte value + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetMacAddr2MaskByteCtrl(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_ADDRESS2_HIGH & ENET_MAC_ADDRESS2_HIGH_MBC_MASK) >> ENET_MAC_ADDRESS2_HIGH_MBC_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set MAC address2 mask byte control + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8MaskCtrl MAC address2 mask byte value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMacAddr2MaskByteCtrl(ENET_Type *const pEnet, uint8_t u8MaskCtrl) +{ + pEnet->MAC_ADDRESS2_HIGH = (pEnet->MAC_ADDRESS2_HIGH & ~ENET_MAC_ADDRESS2_HIGH_MBC_MASK) | + ENET_MAC_ADDRESS2_HIGH_MBC(u8MaskCtrl); +} + +/** + * @brief Get MAC address2 DMA channel select + * + * @param [in] pEnet the base address of the ENET instance + * @return MAC address2 DMA channel select + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetMacAddr2DMAChannelSelect(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_ADDRESS2_HIGH & ENET_MAC_ADDRESS2_HIGH_DCS_MASK) >> ENET_MAC_ADDRESS2_HIGH_DCS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set MAC address2 DMA channel select + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8DMAChannelSel MAC address2 DMA channel select + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMacAddr2DMAChannelSelect(ENET_Type *const pEnet, uint8_t u8DMAChannelSel) +{ + pEnet->MAC_ADDRESS2_HIGH = (pEnet->MAC_ADDRESS2_HIGH & ~ENET_MAC_ADDRESS2_HIGH_DCS_MASK) | + ENET_MAC_ADDRESS2_HIGH_DCS(u8DMAChannelSel); +} + +/* ================================================================ * + * ENET MAC Management Counters (MMC) * + * ================================================================ */ + +/** + * @brief Get MMC control register value + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC control register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMmcControl(const ENET_Type *const pEnet) +{ + return pEnet->MMC_CONTROL; +} + +/** + * @brief Set MMC control register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Ctrl MMC control register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMmcControl(ENET_Type *const pEnet, uint32_t u32Ctrl) +{ + pEnet->MMC_CONTROL = u32Ctrl; +} + +/** + * @brief Get update MMC counters for dropped broadcast packets enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true update MMC counters for dropped broadcast packets + * @return false do not update MMC counters for dropped broadcast packets + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetUpdateMmcCntForDroppedBroadcastPktEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MMC_CONTROL & ENET_MMC_CONTROL_UCDBC_MASK) >> ENET_MMC_CONTROL_UCDBC_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set update MMC counters for dropped broadcast packets enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetUpdateMmcCntForDroppedBroadcastPktEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MMC_CONTROL = (pEnet->MMC_CONTROL & ~ENET_MMC_CONTROL_UCDBC_MASK) | + ENET_MMC_CONTROL_UCDBC(bEnable ? 1u : 0u); +} + +/** + * @brief Get MMC counters full-half preset level + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_MMC_COUNTER_PRESET_LEVEL_FULL MMC counter preset to almost-full value + * @return ENET_MAC_MMC_COUNTER_PRESET_LEVEL_HALF MMC counter preset to almost-half value + */ +LOCAL_INLINE ENET_MAC_MmcCntPresetLevelType ENET_HWA_MAC_GetMmcCounterPresetLevel(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MMC_CONTROL & ENET_MMC_CONTROL_CNTPRSTLVL_MASK) >> ENET_MMC_CONTROL_CNTPRSTLVL_SHIFT; + return (ENET_MAC_MmcCntPresetLevelType)u32TmpVal; +} + +/** + * @brief Set MMC counters full-half preset level + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eLevel ENET_MAC_MMC_COUNTER_PRESET_LEVEL_FULL or ENET_MAC_MMC_COUNTER_PRESET_LEVEL_HALF + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMmcCounterPresetLevel(ENET_Type *const pEnet, ENET_MAC_MmcCntPresetLevelType eLevel) +{ + pEnet->MMC_CONTROL = (pEnet->MMC_CONTROL & ~ENET_MMC_CONTROL_CNTPRSTLVL_MASK) | + ENET_MMC_CONTROL_CNTPRSTLVL(eLevel); +} + +/** + * @brief Get MMC counters preset status + * + * @param [in] pEnet the base address of the ENET instance + * @return true MMC counter preset is enabled + * @return false MMC counter preset is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMmcCounterPresetStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MMC_CONTROL & ENET_MMC_CONTROL_CNTPRST_MASK) >> ENET_MMC_CONTROL_CNTPRST_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set MMC counters preset + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_PresetMmcCounters(ENET_Type *const pEnet) +{ + pEnet->MMC_CONTROL |= ENET_MMC_CONTROL_CNTPRST_MASK; +} + +/** + * @brief Get MMC counters freeze status + * + * @param [in] pEnet the base address of the ENET instance + * @return true MMC counter freeze is enabled + * @return false MMC counter freeze is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMmcCounterFreezeStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MMC_CONTROL & ENET_MMC_CONTROL_CNTFREEZ_MASK) >> ENET_MMC_CONTROL_CNTFREEZ_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set MMC counters freeze + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bFreeze enable or disable freeze + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMmcCounterFreezeStatus(ENET_Type *const pEnet, bool bFreeze) +{ + pEnet->MMC_CONTROL = (pEnet->MMC_CONTROL & ~ENET_MMC_CONTROL_CNTFREEZ_MASK) | + ENET_MMC_CONTROL_CNTFREEZ(bFreeze ? 1u : 0u); +} + +/** + * @brief Get MMC counters reset on read enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true MMC counters are reset to zero after read + * @return false MMC counters are not reset to zero after read + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMmcCounterResetOnReadEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MMC_CONTROL & ENET_MMC_CONTROL_RSTONRD_MASK) >> ENET_MMC_CONTROL_RSTONRD_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set MMC counters reset on read enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMmcCounterResetOnReadEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MMC_CONTROL = (pEnet->MMC_CONTROL & ~ENET_MMC_CONTROL_RSTONRD_MASK) | + ENET_MMC_CONTROL_RSTONRD(bEnable ? 1u : 0u); +} + +/** + * @brief Get MMC counters stop rollover enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true MMC counters does not roll over to zero after reaching the maximum value + * @return false MMC counters roll over to zero after reaching the maximum value + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMmcCounterStopRolloverEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MMC_CONTROL & ENET_MMC_CONTROL_CNTSTOPRO_MASK) >> ENET_MMC_CONTROL_CNTSTOPRO_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set MMC counters stop rollover enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMmcCounterStopRolloverEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MMC_CONTROL = (pEnet->MMC_CONTROL & ~ENET_MMC_CONTROL_CNTSTOPRO_MASK) | + ENET_MMC_CONTROL_CNTSTOPRO(bEnable ? 1u : 0u); +} + +/** + * @brief Get MMC counters reset status + * + * @param [in] pEnet the base address of the ENET instance + * @return true All MMC counters are reset + * @return false MMC counters are not reset + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMmcCounterResetStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MMC_CONTROL & ENET_MMC_CONTROL_CNTRST_MASK) >> ENET_MMC_CONTROL_CNTRST_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Reset all MMC counters + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_ResetMmcCounters(ENET_Type *const pEnet) +{ + pEnet->MMC_CONTROL |= ENET_MMC_CONTROL_CNTRST_MASK; +} + +/** + * @brief Get MMC interrupts of receive statistics counters + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC interrupts status + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMmcRxInterruptStatus(const ENET_Type *const pEnet) +{ + return pEnet->MMC_RX_INTERRUPT; +} + +/** + * @brief Get MMC interrupts of transmit statistics counters + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC interrupts status + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMmcTxInterruptStatus(const ENET_Type *const pEnet) +{ + return pEnet->MMC_TX_INTERRUPT; +} + +/** + * @brief Get MMC interrupts mask of receive statistics counters + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC interrupts mask + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMmcRxInterruptMask(const ENET_Type *const pEnet) +{ + return pEnet->MMC_RX_INTERRUPT_MASK; +} + +/** + * @brief Set MMC interrupts mask of receive statistics counters + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Mask MMC interrupts mask value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMmcRxInterruptMask(ENET_Type *const pEnet, uint32_t u32Mask) +{ + pEnet->MMC_RX_INTERRUPT_MASK = u32Mask; +} + +/** + * @brief Get MMC interrupts mask of transmit statistics counters + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC interrupts mask + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetMmcTxInterruptMask(const ENET_Type *const pEnet) +{ + return pEnet->MMC_TX_INTERRUPT_MASK; +} + +/** + * @brief Set MMC interrupts mask of transmit statistics counters + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Mask MMC interrupts mask value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMmcTxInterruptMask(ENET_Type *const pEnet, uint32_t u32Mask) +{ + pEnet->MMC_TX_INTERRUPT_MASK = u32Mask; +} + +/** + * @brief Get transmitted bytes of good and bad packets + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxOctetCntGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->TX_OCTET_COUNT_GOOD_BAD; +} + +/** + * @brief Get the number of good and bad packets transmitted + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->TX_PACKET_COUNT_GOOD_BAD; +} + +/** + * @brief Get the number of good broadcast packets transmitted + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxBroadcastPacketGood(const ENET_Type *const pEnet) +{ + return pEnet->TX_BROADCAST_PACKETS_GOOD; +} + +/** + * @brief Get the number of good multicast packets transmitted + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxMulticastPacketGood(const ENET_Type *const pEnet) +{ + return pEnet->TX_MULTICAST_PACKETS_GOOD; +} + +/** + * @brief Get the number of good and bad packets transmitted with length 64 bytes + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTx64OctetPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->TX_64OCTETS_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of good and bad packets transmitted with length between 65 and 127 bytes + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTx65To127OctetPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->TX_65TO127OCTETS_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of good and bad packets transmitted with length between 128 and 255 bytes + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTx128To255OctetPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->TX_128TO255OCTETS_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of good and bad packets transmitted with length between 256 and 511 bytes + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTx256To511OctetPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->TX_256TO511OCTETS_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of good and bad packets transmitted with length between 512 and 1023 bytes + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTx512To1023OctetPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->TX_512TO1023OCTETS_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of good and bad packets transmitted with length 1024 to maxsize bytes + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTx1024ToMaxOctetPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of good and bad unicast packets transmitted + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxUnicastPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->TX_UNICAST_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of good and bad multicast packets transmitted + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxMulticastPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->TX_MULTICAST_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of good and bad broadcast packets transmitted + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxBroadcastPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->TX_BROADCAST_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of packets with transmit underflow error + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxUnderflowErrorPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->TX_UNDERFLOW_ERROR_PACKETS; +} + +/** + * @brief Get the number of successfully transmitted packets after a single collision in half-duplex mode. + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxSingleCollisionGoodPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->TX_SINGLE_COLLISION_GOOD_PACKETS; +} + +/** + * @brief Get the number of successfully transmitted packets after a multiple collision in half-duplex mode. + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxMultipleCollisionGoodPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->TX_MULTIPLE_COLLISION_GOOD_PACKETS; +} + +/** + * @brief Get the number of successfully transmitted packets after a deferral in half-duplex mode. + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxDeferredPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->TX_DEFERRED_PACKETS; +} + +/** + * @brief Get the number of packets with transmit late collision error + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxLateCollisionPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->TX_LATE_COLLISION_PACKETS; +} + +/** + * @brief Get the number of packets with transmit excessive collision errors + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxExcessiveCollisionPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->TX_EXCESSIVE_COLLISION_PACKETS; +} + +/** + * @brief Get the number of packets with transmit carrier sense error + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxCarrierErrorPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->TX_CARRIER_ERROR_PACKETS; +} + +/** + * @brief Get the number of bytes of good packets transmitted + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxOctetCntGood(const ENET_Type *const pEnet) +{ + return pEnet->TX_OCTET_COUNT_GOOD; +} + +/** + * @brief Get the number of good packets transmitted + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxPacketCntGood(const ENET_Type *const pEnet) +{ + return pEnet->TX_PACKET_COUNT_GOOD; +} + +/** + * @brief Get the number of packets with transmit excessive deferral error + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxExcessiveDeferralErrorCnt(const ENET_Type *const pEnet) +{ + return pEnet->TX_EXCESSIVE_DEFERRAL_ERROR; +} + +/** + * @brief Get the number of good pause packets transmitted + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxPausePacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->TX_PAUSE_PACKETS; +} + +/** + * @brief Get the number of good VLAN packets transmitted + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxVLANPacketGood(const ENET_Type *const pEnet) +{ + return pEnet->TX_VLAN_PACKETS_GOOD; +} + +/** + * @brief Get the number of transmitted packets without errors and with length greater than the maxsize + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxOverSizePacketGood(const ENET_Type *const pEnet) +{ + return pEnet->TX_OSIZE_PACKETS_GOOD; +} + +/** + * @brief Get the number of good and bad packets received + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxPacketCntGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->RX_PACKETS_COUNT_GOOD_BAD; +} + +/** + * @brief Get the number of bytes received in good and bad packets + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxOctetCntGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->RX_OCTET_COUNT_GOOD_BAD; +} + +/** + * @brief Get the number of bytes received in good packets + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxOctetCntGood(const ENET_Type *const pEnet) +{ + return pEnet->RX_OCTET_COUNT_GOOD; +} + +/** + * @brief Get the number of good broadcast packets received + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxBroadcastPacketGood(const ENET_Type *const pEnet) +{ + return pEnet->RX_BROADCAST_PACKETS_GOOD; +} + +/** + * @brief Get the number of good multicast packets received + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxMulticastPacketGood(const ENET_Type *const pEnet) +{ + return pEnet->RX_MULTICAST_PACKETS_GOOD; +} + +/** + * @brief Get the number of packets received with CRC error + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxCRCErrorPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->RX_CRC_ERROR_PACKETS; +} + +/** + * @brief Get the number of packets received with alignment error + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxAlignmentErrorPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->RX_ALIGNMENT_ERROR_PACKETS; +} + +/** + * @brief Get the number of packets received with runt error + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxRuntErrorPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->RX_RUNT_ERROR_PACKETS; +} + +/** + * @brief Get the number of packets received with jabber error + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxJabberErrorPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->RX_JABBER_ERROR_PACKETS; +} + +/** + * @brief Get the number of packets received with length less than 64 bytes, without any errors + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxUndersizePacketGood(const ENET_Type *const pEnet) +{ + return pEnet->RX_UNDERSIZE_PACKETS_GOOD; +} + +/** + * @brief Get the number of packets received withouterrors and with length greater than maxsize + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxOverSizeGood(const ENET_Type *const pEnet) +{ + return pEnet->RX_OVERSIZE_PACKETS_GOOD; +} + +/** + * @brief Get the number of packets received with length 64 bytes + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRx64OctetPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->RX_64OCTETS_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of packets received with length 65 to 127 bytes + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRx65To127OctetPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->RX_65TO127OCTETS_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of packets received with length 128 to 255 bytes + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRx128To255OctetPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->RX_128TO255OCTETS_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of packets received with length 256 to 511 bytes + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRx256To511OctetPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->RX_256TO511OCTETS_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of packets received with length 512 to 1023 bytes + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRx512To1023OctetPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->RX_512TO1023OCTETS_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of packets received with length 1024 to maxsize + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRx1024ToMaxOctetPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of good unicast packets received + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetUnicastPacketGood(const ENET_Type *const pEnet) +{ + return pEnet->RX_UNICAST_PACKETS_GOOD; +} + +/** + * @brief Get the number of packets received with length error + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxLengthErrorPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->RX_LENGTH_ERROR_PACKETS; +} + +/** + * @brief Get the number of packets received with length greater than 1500 but less than 1536 + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxOutOfRangeTypePacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->RX_OUT_OF_RANGE_TYPE_PACKETS; +} + +/** + * @brief Get the number of good and valid pause packets received + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxPausePacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->RX_PAUSE_PACKETS; +} + +/** + * @brief Get the number of missed received packets because of FIFO overflow + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxFIFOOverflowPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->RX_FIFO_OVERFLOW_PACKETS; +} + +/** + * @brief Get the number of good and bad VLAN packets received + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxVLANPacketGoodBad(const ENET_Type *const pEnet) +{ + return pEnet->RX_VLAN_PACKETS_GOOD_BAD; +} + +/** + * @brief Get the number of packets received with error because of watchdog timeout error + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxWatchdogErrorPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->RX_WATCHDOG_ERROR_PACKETS; +} + +/** + * @brief Get the number of packets received with receive error or Packet Extension error + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxReceiveErrorPacketCnt(const ENET_Type *const pEnet) +{ + return pEnet->RX_RECEIVE_ERROR_PACKETS; +} + +/** + * @brief Get the number of good control packets received + * + * @param [in] pEnet the base address of the ENET instance + * @return MMC counter value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetRxControlPacketGood(const ENET_Type *const pEnet) +{ + return pEnet->RX_CONTROL_PACKETS_GOOD; +} + +/* ================================================================ * + * ENET MAC Layer 3 and Layer 4 Filter * + * ================================================================ */ + +/** + * @brief Get the layer 3 and layer 4 control register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return layer 3 and layer 4 control register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetLayer3Layer4Ctrl(const ENET_Type *const pEnet, uint8_t u8Index) +{ + return pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL; +} + +/** + * @brief Set the layer 3 and layer 4 control register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u32Ctrl control value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3Layer4Ctrl(ENET_Type *const pEnet, uint8_t u8Index, uint32_t u32Ctrl) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = u32Ctrl; +} + +/** + * @brief Get layer 3 and layer 4 control DMA channel select enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return true DMA channel select is enabled + * @return false DMA channel select is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetLayer3Layer4DMASelectEnFlag(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_DMCHEN0_MASK) >> + ENET_MAC_L3_L4_CONTROL_DMCHEN0_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set layer 3 and layer 4 control DMA channel select enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] bEnable enabled or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3Layer4DMASelectEnFlag(ENET_Type *const pEnet, uint8_t u8Index, bool bEnable) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + ~ENET_MAC_L3_L4_CONTROL_DMCHEN0_MASK) | + ENET_MAC_L3_L4_CONTROL_DMCHEN0(bEnable ? 1u : 0u); +} + +/** + * @brief Get layer 3 and layer 4 control DMA channel number + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return ENET_DMA_ChannelType + */ +LOCAL_INLINE ENET_DMA_ChannelType ENET_HWA_MAC_GetLayer3Layer4DMAChannel(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_DMCHN0_MASK) >> + ENET_MAC_L3_L4_CONTROL_DMCHN0_SHIFT; + return (ENET_DMA_ChannelType)u32TmpVal; +} + +/** + * @brief Set layer 3 and layer 4 control DMA channel number + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] eChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3Layer4DMAChannel(ENET_Type *const pEnet, uint8_t u8Index, + ENET_DMA_ChannelType eChannel) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + ~ENET_MAC_L3_L4_CONTROL_DMCHN0_MASK) | + ENET_MAC_L3_L4_CONTROL_DMCHN0(eChannel); +} + +/** + * @brief Get layer 4 destination port inverse match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return true layer 4 destination port inverse match is enabled + * @return false layer 4 destination port inverse match is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetLayer4DestPortInvMatchEnFlag(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_L4DPIM0_MASK) >> + ENET_MAC_L3_L4_CONTROL_L4DPIM0_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set layer 4 destination port inverse match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] bEnable enabled or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer4DestPortInvMatchEnFlag(ENET_Type *const pEnet, uint8_t u8Index, bool bEnable) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~ENET_MAC_L3_L4_CONTROL_L4DPIM0_MASK)) | + ENET_MAC_L3_L4_CONTROL_L4DPIM0(bEnable ? 1u : 0u); +} + +/** + * @brief Get layer 4 destination port match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return true layer 4 destination port match is enabled + * @return false layer 4 destination port match is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetLayer4DestPortMatchEnFlag(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_L4DPM0_MASK) >> + ENET_MAC_L3_L4_CONTROL_L4DPM0_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set layer 4 destination port match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] bEnable enabled or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer4DestPortMatchEnFlag(ENET_Type *const pEnet, uint8_t u8Index, bool bEnable) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~ENET_MAC_L3_L4_CONTROL_L4DPM0_MASK)) | + ENET_MAC_L3_L4_CONTROL_L4DPM0(bEnable ? 1u : 0u); +} + +/** + * @brief Get layer 4 source port inverse match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return true layer 4 source port inverse match is enabled + * @return false layer 4 source port inverse match is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetLayer4SrcPortInvMatchEnFlag(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_L4SPIM0_MASK) >> + ENET_MAC_L3_L4_CONTROL_L4SPIM0_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set layer 4 source port inverse match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] bEnable enabled or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer4SrcPortInvMatchEnFlag(ENET_Type *const pEnet, uint8_t u8Index, bool bEnable) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~ENET_MAC_L3_L4_CONTROL_L4SPIM0_MASK)) | + ENET_MAC_L3_L4_CONTROL_L4SPIM0(bEnable ? 1u : 0u); +} + +/** + * @brief Get layer 4 source port match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return true layer 4 source port match is enabled + * @return false layer 4 source port match is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetLayer4SrcPortMatchEnFlag(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_L4SPM0_MASK) >> + ENET_MAC_L3_L4_CONTROL_L4SPM0_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set layer 4 source port match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] bEnable enabled or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer4SrcPortMatchEnFlag(ENET_Type *const pEnet, uint8_t u8Index, bool bEnable) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~ENET_MAC_L3_L4_CONTROL_L4SPM0_MASK)) | + ENET_MAC_L3_L4_CONTROL_L4SPM0(bEnable ? 1u : 0u); +} + +/** + * @brief Get layer 4 protocol type (UDP or TCP) + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return ENET_MAC_Layer4ProtocolType + */ +LOCAL_INLINE ENET_MAC_Layer4ProtocolType ENET_HWA_MAC_GetLayer4ProtocalType(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_L4PEN0_MASK) >> + ENET_MAC_L3_L4_CONTROL_L4PEN0_SHIFT; + return (ENET_MAC_Layer4ProtocolType)u32TmpVal; +} + +/** + * @brief Set layer 4 protocol type (UDP or TCP) + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] eProtocol protocol type (UDP or TCP) + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer4ProtocalType(ENET_Type *const pEnet, uint8_t u8Index, + ENET_MAC_Layer4ProtocolType eProtocol) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~ENET_MAC_L3_L4_CONTROL_L4PEN0_MASK)) | + ENET_MAC_L3_L4_CONTROL_L4PEN0(eProtocol); +} + +/** + * @brief Get layer3 IPv4 destination address bits match + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return lower retval bits are masked + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetLayer3IPv4DestAddrBitsMatch(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_L3HDBM0_MASK) >> + ENET_MAC_L3_L4_CONTROL_L3HDBM0_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set layer3 IPv4 destination address bits match + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u8MaskBits lower u8MaskBits bits are masked + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3IPv4DestAddrBitsMatch(ENET_Type *const pEnet, uint8_t u8Index, uint8_t u8MaskBits) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~ENET_MAC_L3_L4_CONTROL_L3HDBM0_MASK)) | + ENET_MAC_L3_L4_CONTROL_L3HDBM0(u8MaskBits); +} + +/** + * @brief Get layer3 IPv4 source address bits match + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return lower retval bits are masked + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetLayer3IPv4SrcAddrBitsMatch(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_L3HSBM0_MASK) >> + ENET_MAC_L3_L4_CONTROL_L3HSBM0_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set layer3 IPv4 source address bits match + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u8MaskBits lower u8MaskBits bits are masked + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3IPv4SrcAddrBitsMatch(ENET_Type *const pEnet, uint8_t u8Index, uint8_t u8MaskBits) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~ENET_MAC_L3_L4_CONTROL_L3HSBM0_MASK)) | + ENET_MAC_L3_L4_CONTROL_L3HSBM0(u8MaskBits); +} + +/** + * @brief Get layer3 IPv6 address bits match + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return lower retval bits are masked + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetLayer3IPv6AddrBitsMatch(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (ENET_MAC_L3_L4_CONTROL_L3HDBM0_MASK | ENET_MAC_L3_L4_CONTROL_L3HSBM0_MASK)) >> + ENET_MAC_L3_L4_CONTROL_L3HSBM0_SHIFT; + return (uint8_t)(u32TmpVal & 0x7Fu); +} + +/** + * @brief Set layer3 IPv6 address bits match + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u8MaskBits lower u8MaskBits bits are masked + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3IPv6AddrBitsMatch(ENET_Type *const pEnet, uint8_t u8Index, uint8_t u8MaskBits) +{ + uint8_t u8HighBits = (u8MaskBits & 0x60u) >> 5u; + uint8_t u8LowBits = u8MaskBits & 0x1Fu; + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~(ENET_MAC_L3_L4_CONTROL_L3HDBM0_MASK | ENET_MAC_L3_L4_CONTROL_L3HSBM0_MASK))) | + (ENET_MAC_L3_L4_CONTROL_L3HDBM0(u8HighBits) | ENET_MAC_L3_L4_CONTROL_L3HSBM0(u8LowBits)); +} + +/** + * @brief Get layer 3 destination address inverse match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return true layer 3 destination address inverse match is enabled + * @return false layer 3 destination address inverse match is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetLayer3DestAddrInvMatchEnFlag(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_L3DAIM0_MASK) >> + ENET_MAC_L3_L4_CONTROL_L3DAIM0_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set layer 3 destination address inverse match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] bEnable enabled or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3DestAddrInvMatchEnFlag(ENET_Type *const pEnet, uint8_t u8Index, bool bEnable) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~ENET_MAC_L3_L4_CONTROL_L3DAIM0_MASK)) | + ENET_MAC_L3_L4_CONTROL_L3DAIM0(bEnable ? 1u : 0u); +} + +/** + * @brief Get layer 3 destination address match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return true layer 3 destination address match is enabled + * @return false layer 3 destination address match is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetLayer3DestAddrMatchEnFlag(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_L3DAM0_MASK) >> + ENET_MAC_L3_L4_CONTROL_L3DAM0_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set layer 3 destination address match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] bEnable enabled or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3DestAddrMatchEnFlag(ENET_Type *const pEnet, uint8_t u8Index, bool bEnable) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~ENET_MAC_L3_L4_CONTROL_L3DAM0_MASK)) | + ENET_MAC_L3_L4_CONTROL_L3DAM0(bEnable ? 1u : 0u); +} + +/** + * @brief Get layer 3 source address inverse match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return true layer 3 source address inverse match is enabled + * @return false layer 3 source address inverse match is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetLayer3SrcAddrInvMatchEnFlag(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_L3SAIM0_MASK) >> + ENET_MAC_L3_L4_CONTROL_L3SAIM0_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set layer 3 source address inverse match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] bEnable enabled or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3SrcAddrInvMatchEnFlag(ENET_Type *const pEnet, uint8_t u8Index, bool bEnable) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~ENET_MAC_L3_L4_CONTROL_L3SAIM0_MASK)) | + ENET_MAC_L3_L4_CONTROL_L3SAIM0(bEnable ? 1u : 0u); +} + +/** + * @brief Get layer 3 source address match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return true layer 3 source address match is enabled + * @return false layer 3 source address match is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetLayer3SrcAddrMatchEnFlag(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_L3SAM0_MASK) >> + ENET_MAC_L3_L4_CONTROL_L3SAM0_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set layer 3 source address match enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] bEnable enabled or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3SrcAddrMatchEnFlag(ENET_Type *const pEnet, uint8_t u8Index, bool bEnable) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~ENET_MAC_L3_L4_CONTROL_L3SAM0_MASK)) | + ENET_MAC_L3_L4_CONTROL_L3SAM0(bEnable ? 1u : 0u); +} + +/** + * @brief Get layer 3 protocol type (IPV4 or IPV6) + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return ENET_MAC_Layer3ProtocolType (IPV4 or IPV6) + */ +LOCAL_INLINE ENET_MAC_Layer3ProtocolType ENET_HWA_MAC_GetLayer3ProtocolType(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & ENET_MAC_L3_L4_CONTROL_L3PEN0_MASK) >> + ENET_MAC_L3_L4_CONTROL_L3PEN0_SHIFT; + return (ENET_MAC_Layer3ProtocolType)u32TmpVal; +} + +/** + * @brief Set layer 3 protocol type (IPV4 or IPV6) + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] eProtocol IPV4 or IPV6 + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3ProtocolType(ENET_Type *const pEnet, uint8_t u8Index, + ENET_MAC_Layer3ProtocolType eProtocol) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL = (pEnet->L3_L4_FILTER[u8Index].MAC_L3_L4_CONTROL & + (~ENET_MAC_L3_L4_CONTROL_L3PEN0_MASK)) | + ENET_MAC_L3_L4_CONTROL_L3PEN0(eProtocol); +} + +/** + * @brief Get layer 4 address + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return layer 4 address value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetLayer4Addr(const ENET_Type *const pEnet, uint8_t u8Index) +{ + return pEnet->L3_L4_FILTER[u8Index].MAC_LAYER4_ADDRESS; +} + +/** + * @brief Set layer 4 address + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u32Addr layer 4 address value + */ +LOCAL_INLINE void ENET_MAC_SetLayer4Addr(ENET_Type *const pEnet, uint8_t u8Index, uint32_t u32Addr) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER4_ADDRESS = u32Addr; +} + +/** + * @brief Get layer 4 destination port number + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return layer 4 destination port number + */ +LOCAL_INLINE uint16_t ENET_HWA_MAC_GetLayer4DestPort(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_LAYER4_ADDRESS & ENET_MAC_LAYER4_ADDRESS_L4DP0_MASK) >> + ENET_MAC_LAYER4_ADDRESS_L4DP0_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set layer 4 destination port number + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u16DestPort port number + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer4DestPort(ENET_Type *const pEnet, uint8_t u8Index, uint16_t u16DestPort) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER4_ADDRESS = (pEnet->L3_L4_FILTER[u8Index].MAC_LAYER4_ADDRESS & + (~ENET_MAC_LAYER4_ADDRESS_L4DP0_MASK)) | + ENET_MAC_LAYER4_ADDRESS_L4DP0(u16DestPort); +} + +/** + * @brief Get layer 4 source port number + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return layer 4 source port number + */ +LOCAL_INLINE uint16_t ENET_HWA_MAC_GetLayer4SrcPort(const ENET_Type *const pEnet, uint8_t u8Index) +{ + uint32_t u32TmpVal = (pEnet->L3_L4_FILTER[u8Index].MAC_LAYER4_ADDRESS & ENET_MAC_LAYER4_ADDRESS_L4SP0_MASK) >> + ENET_MAC_LAYER4_ADDRESS_L4SP0_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set layer 4 source port number + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u16SrcPort port number + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer4SrcPort(ENET_Type *const pEnet, uint8_t u8Index, uint16_t u16SrcPort) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER4_ADDRESS = (pEnet->L3_L4_FILTER[u8Index].MAC_LAYER4_ADDRESS & + (~ENET_MAC_LAYER4_ADDRESS_L4SP0_MASK)) | + ENET_MAC_LAYER4_ADDRESS_L4SP0(u16SrcPort); +} + +/** + * @brief Get layer 3 address0 + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return layer 3 address0 value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetLayer3Addr0(const ENET_Type *const pEnet, uint8_t u8Index) +{ + return pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR0_REG; +} + +/** + * @brief Set layer 3 address0 + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u32Addr layer 3 address0 value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3Addr0(ENET_Type *const pEnet, uint8_t u8Index, uint32_t u32Addr) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR0_REG = u32Addr; +} + +/** + * @brief Get layer 3 address1 + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return layer 3 address1 value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetLayer3Addr1(const ENET_Type *const pEnet, uint8_t u8Index) +{ + return pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR1_REG; +} + +/** + * @brief Set layer 3 address1 + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u32Addr layer 3 address1 value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3Addr1(ENET_Type *const pEnet, uint8_t u8Index, uint32_t u32Addr) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR1_REG = u32Addr; +} + +/** + * @brief Get layer 3 address2 + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return layer 3 address2 value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetLayer3Addr2(const ENET_Type *const pEnet, uint8_t u8Index) +{ + return pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR2_REG; +} + +/** + * @brief Set layer 3 address2 + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u32Addr layer 3 address2 value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3Addr2(ENET_Type *const pEnet, uint8_t u8Index, uint32_t u32Addr) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR2_REG = u32Addr; +} + +/** + * @brief Get layer 3 address3 + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return layer 3 address3 value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetLayer3Addr3(const ENET_Type *const pEnet, uint8_t u8Index) +{ + return pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR3_REG; +} + +/** + * @brief Set layer 3 address3 + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u32Addr layer 3 address3 value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3Addr3(ENET_Type *const pEnet, uint8_t u8Index, uint32_t u32Addr) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR3_REG = u32Addr; +} + +/** + * @brief Get layer 3 source IPv4 address + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return layer 3 source IPv4 address value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetLayer3SrcIPv4Addr(const ENET_Type *const pEnet, uint8_t u8Index) +{ + return pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR0_REG; +} + +/** + * @brief Set layer 3 source IPv4 address + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u32SrcAddr layer 3 source IPv4 address value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3SrcIPv4Addr(ENET_Type *const pEnet, uint8_t u8Index, uint32_t u32SrcAddr) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR0_REG = u32SrcAddr; +} + +/** + * @brief Get layer 3 destination IPv4 address + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @return layer 3 destination IPv4 address value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetLayer3DestIPv4Addr(const ENET_Type *const pEnet, uint8_t u8Index) +{ + return pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR1_REG; +} + +/** + * @brief Set layer 3 destination IPv4 address + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] u32DestAddr layer 3 destination IPv4 address value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3DestIPv4Addr(ENET_Type *const pEnet, uint8_t u8Index, uint32_t u32DestAddr) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR1_REG = u32DestAddr; +} + +/** + * @brief Get layer 3 IPv6 address + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [out] aIPv6Addr layer 3 IPv6 address value + */ +LOCAL_INLINE void ENET_HWA_MAC_GetLayer3IPv6Addr(const ENET_Type *const pEnet, uint8_t u8Index, uint8_t aIPv6Addr[16u]) +{ + uint32_t u32AddrHH = pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR3_REG; + uint32_t u32AddrHL = pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR2_REG; + uint32_t u32AddrLH = pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR1_REG; + uint32_t u32AddrLL = pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR0_REG; + + aIPv6Addr[0u] = (uint8_t)((u32AddrHH & 0xFF000000u) >> 24u); + aIPv6Addr[1u] = (uint8_t)((u32AddrHH & 0x00FF0000u) >> 16u); + aIPv6Addr[2u] = (uint8_t)((u32AddrHH & 0x0000FF00u) >> 8u); + aIPv6Addr[3u] = (uint8_t)(u32AddrHH & 0x000000FFu); + aIPv6Addr[4u] = (uint8_t)((u32AddrHL & 0xFF000000u) >> 24u); + aIPv6Addr[5u] = (uint8_t)((u32AddrHL & 0x00FF0000u) >> 16u); + aIPv6Addr[6u] = (uint8_t)((u32AddrHL & 0x0000FF00u) >> 8u); + aIPv6Addr[7u] = (uint8_t)(u32AddrHL & 0x000000FFu); + aIPv6Addr[8u] = (uint8_t)((u32AddrLH & 0xFF000000u) >> 24u); + aIPv6Addr[9u] = (uint8_t)((u32AddrLH & 0x00FF0000u) >> 16u); + aIPv6Addr[10u] = (uint8_t)((u32AddrLH & 0x0000FF00u) >> 8u); + aIPv6Addr[11u] = (uint8_t)(u32AddrLH & 0x000000FFu); + aIPv6Addr[12u] = (uint8_t)((u32AddrLL & 0xFF000000u) >> 24u); + aIPv6Addr[13u] = (uint8_t)((u32AddrLL & 0x00FF0000u) >> 16u); + aIPv6Addr[14u] = (uint8_t)((u32AddrLL & 0x0000FF00u) >> 8u); + aIPv6Addr[15u] = (uint8_t)(u32AddrLL & 0x000000FFu); +} + +/** + * @brief Set layer 3 IPv6 address + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Index layer 3 and layer 4 filter group index + * @param [in] aIPv6Addr layer 3 IPv6 address value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetLayer3IPv6Addr(ENET_Type *const pEnet, uint8_t u8Index, const uint8_t aIPv6Addr[16]) +{ + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR3_REG = ((uint32_t)aIPv6Addr[0u] << 24u) | + ((uint32_t)aIPv6Addr[1u] << 16u) | + ((uint32_t)aIPv6Addr[2u] << 8u) | + ((uint32_t)aIPv6Addr[3u]); + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR2_REG = ((uint32_t)aIPv6Addr[4u] << 24u) | + ((uint32_t)aIPv6Addr[5u] << 16u) | + ((uint32_t)aIPv6Addr[6u] << 8u) | + ((uint32_t)aIPv6Addr[7u]); + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR1_REG = ((uint32_t)aIPv6Addr[8u] << 24u) | + ((uint32_t)aIPv6Addr[9u] << 16u) | + ((uint32_t)aIPv6Addr[10u] << 8u) | + ((uint32_t)aIPv6Addr[11u]); + pEnet->L3_L4_FILTER[u8Index].MAC_LAYER3_ADDR0_REG = ((uint32_t)aIPv6Addr[12u] << 24u) | + ((uint32_t)aIPv6Addr[13u] << 16u) | + ((uint32_t)aIPv6Addr[14u] << 8u) | + ((uint32_t)aIPv6Addr[15u]); +} + +/* ================================================================ * + * ENET MAC Timestamp Control * + * ================================================================ */ + +/** + * @brief Get time stamp control register value + * + * @param [in] pEnet the base address of the ENET instance + * @return time stamp control value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTimestampControl(const ENET_Type *const pEnet) +{ + return pEnet->MAC_TIMESTAMP_CONTROL; +} + +/** + * @brief Set time stamp control register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Ctrl time stamp control value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimestampControl(ENET_Type *const pEnet, uint32_t u32Ctrl) +{ + pEnet->MAC_TIMESTAMP_CONTROL = u32Ctrl; +} + + +/** + * @brief Get time stamp AV802_1AS mode enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true time stamp AV802_1AS mode is enabled + * @return false time stamp AV802_1AS mode is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetAV802_1ASModeEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set time stamp AV802_1AS mode enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetAV802_1ASModeEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(bEnable ? 1u : 0u); +} + +/** + * @brief Get transmit timestamp status mode + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_TxTimestampStatusModeType + */ +LOCAL_INLINE ENET_MAC_TxTimestampStatusModeType ENET_HWA_MAC_GetTxTimestampStatusMode(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT; + return (ENET_MAC_TxTimestampStatusModeType)u32TmpVal; +} + +/** + * @brief Set transmit timestamp status mode + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eMode transmit timestamp status mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTxTimestampStatusMode(ENET_Type *const pEnet, ENET_MAC_TxTimestampStatusModeType eMode) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TXTSSTSM(eMode); +} + +/** + * @brief Get MAC address for PTP packet filter enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true MAC address for PTP packet filter is enabled + * @return false MAC address for PTP packet filter is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetUseMACAddrForPTPPacketFilterEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set MAC address for PTP packet filter enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetUseMACAddrForPTPPacketFilterEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSENMACADDR(bEnable ? 1u : 0u); +} + +/** + * @brief Get PTP packets type for taking snapshots + * + * @param [in] pEnet the base address of the ENET instance + * @return PTP packets type + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetSnapshotPTPPacketType(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set PTP packets type for taking snapshots + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Type PTP packets type + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSnapshotPTPPacketType(ENET_Type *const pEnet, uint8_t u8Type) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(u8Type); +} + +/** + * @brief Get snapshot for messages relevant to master enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true snapshot for messages relevant to master + * @return false snapshot for messages relevant to slave + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetMasterMsgSanpshotEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set snapshot for messages relevant to master enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetMasterMsgSanpshotEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSMSTRENA(bEnable ? 1u : 0u); +} + +/** + * @brief Get snapshot for event messages enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true snapshot for event messages is enabled + * @return false snapshot for event messages is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetEventMsgSnapshotEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set snapshot for event messages enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetEventMsgSanpshotEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSEVNTENA(bEnable ? 1u : 0u); +} + +/** + * @brief Get processing of PTP packets over IPv4-UDP enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true processing of PTP packets over IPv4-UDP is enabled + * @return false processing of PTP packets over IPv4-UDP is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetIPv4UDPPTPPacketProcessEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set processing of PTP packets over IPv4-UDP enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetIPv4UDPPTPPacketProcessEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(bEnable ? 1u : 0u); +} + +/** + * @brief Get processing of PTP packets over IPv6-UDP enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true processing of PTP packets over IPv6-UDP is enabled + * @return false processing of PTP packets over IPv6-UDP is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetIPv6UDPPTPPacketProcessEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set processing of PTP packets over IPv6-UDP enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetIPv6UDPPTPPacketProcessEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(bEnable ? 1u : 0u); +} + +/** + * @brief Get processing of PTP packets over ethernet enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true processing of PTP packets over ethernet is enabled + * @return false processing of PTP packets over ethernet is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetEthernetPTPPacketProcessEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set processing of PTP packets over ethernet enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetEthernetPTPPacketProcessEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSIPENA(bEnable ? 1u : 0u); +} + +/** + * @brief Get PTP packets processing format version + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_PTPVersionType + */ +LOCAL_INLINE ENET_MAC_PTPVersionType ENET_HWA_MAC_GetPTPPacketVersion(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT; + return (ENET_MAC_PTPVersionType)u32TmpVal; +} + +/** + * @brief Set PTP packets processing format version + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eVersion PTP version + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPTPPacketVersion(ENET_Type *const pEnet, ENET_MAC_PTPVersionType eVersion) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSVER2ENA(eVersion); +} + +/** + * @brief Get PTP timestamp rollover mode + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_TimestampRolloverType + */ +LOCAL_INLINE ENET_MAC_TimestampRolloverType ENET_HWA_MAC_GetTimestampRolloverCtrl(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT; + return (ENET_MAC_TimestampRolloverType)u32TmpVal; +} + +/** + * @brief Set PTP timestamp rollover mode + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eCtrl timestamp rollover mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetIimestampRolloverCtrl(ENET_Type *const pEnet, ENET_MAC_TimestampRolloverType eCtrl) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(eCtrl); +} + +/** + * @brief Get timestamp for all packets enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true timestamp for all packets is enabled + * @return false timestamp for all packets is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTimestampForAllPacketEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSENALL_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set timestamp for all packets enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimestampForAllPacketEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSENALL_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSENALL(bEnable ? 1u : 0u); +} + +/** + * @brief Get presentation time generation enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true presentation time generation is enabled + * @return false presentation time generation is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetPresentationTimeGenerationEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_PTGE_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set presentation time generation enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPresentationTimeGenerationEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_PTGE_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_PTGE(bEnable ? 1u : 0u); +} + +/** + * @brief Get PTP addend register update status + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_StatusType + */ +LOCAL_INLINE ENET_MAC_StatusType ENET_HWA_MAC_GetAddendRegisterUpdateStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT; + return (ENET_MAC_StatusType)u32TmpVal; +} + +/** + * @brief Initiate the addend register update operation + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_UpdateAddendRegister(ENET_Type *const pEnet) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK; +} + +/** + * @brief Get timestamp update status + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_StatusType + */ +LOCAL_INLINE ENET_MAC_StatusType ENET_HWA_MAC_GetTimestampUpdateStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT; + return (ENET_MAC_StatusType)u32TmpVal; +} + +/** + * @brief Initiate the timestamp update operation + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_UpdateTimestamp(ENET_Type *const pEnet) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK; +} + +/** + * @brief Get timestamp initialize status + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_StatusType + */ +LOCAL_INLINE ENET_MAC_StatusType ENET_HWA_MAC_GetTimestampInitStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT; + return (ENET_MAC_StatusType)u32TmpVal; +} + +/** + * @brief Initialize PTP timestamp + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_InitTimestamp(ENET_Type *const pEnet) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK; +} + +/** + * @brief Get timestamp update method (fine or coarse) + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_TimestampUpdateMethodType + */ +LOCAL_INLINE ENET_MAC_TimestampUpdateMethodType ENET_HWA_MAC_GetTimestampUpdateMethod(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT; + return (ENET_MAC_TimestampUpdateMethodType)u32TmpVal; +} + +/** + * @brief Set timestamp update method (fine or coarse) + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eMethod (fine update or coarse update) + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimestampUpdateMethod(ENET_Type *const pEnet, ENET_MAC_TimestampUpdateMethodType eMethod) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSCFUPDT(eMethod); +} + +/** + * @brief Get timestamp enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true timestamp processing is enabled + * @return false timestamp processing is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTimestampEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_CONTROL & ENET_MAC_TIMESTAMP_CONTROL_TSENA_MASK) >> + ENET_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + + +/** + * @brief Set timestamp processing enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable timestamp processing + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimestampEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MAC_TIMESTAMP_CONTROL = (pEnet->MAC_TIMESTAMP_CONTROL & + ~(ENET_MAC_TIMESTAMP_CONTROL_TSENA_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK | + ENET_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)) | + ENET_MAC_TIMESTAMP_CONTROL_TSENA(bEnable ? 1u : 0u); +} + +/** + * @brief Get PTP sub-second increment register value + * + * @param [in] pEnet the base address of the ENET instance + * @return sub-second increment register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetSubSecondIncrementReg(const ENET_Type *const pEnet) +{ + return pEnet->MAC_SUB_SECOND_INCREMENT; +} + +/** + * @brief Set PTP sub-second increment register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Increment increment value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSubSecondIncrementReg(ENET_Type *const pEnet, uint32_t u32Increment) +{ + pEnet->MAC_SUB_SECOND_INCREMENT = u32Increment; +} + +/** + * @brief Get PTP sub-second increment value + * + * @param [in] pEnet the base address of the ENET instance + * @return sub-second increment value + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetSubSecondIncrementValue(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_SUB_SECOND_INCREMENT & ENET_MAC_SUB_SECOND_INCREMENT_SSINC_MASK) >> + ENET_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set PTP sub-second increment value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Increment sub-second increment value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSubSecondIncrementValue(ENET_Type *const pEnet, uint8_t u8Increment) +{ + pEnet->MAC_SUB_SECOND_INCREMENT = (pEnet->MAC_SUB_SECOND_INCREMENT & ~ENET_MAC_SUB_SECOND_INCREMENT_SSINC_MASK) | + ENET_MAC_SUB_SECOND_INCREMENT_SSINC(u8Increment); +} + +/** + * @brief Get PTP sub-nanosecond increment value + * + * @param [in] pEnet the base address of the ENET instance + * @return sub-nanosecond increment value + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetSubNanoSecondIncrementValue(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_SUB_SECOND_INCREMENT & ENET_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK) >> + ENET_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set PTP sub-nanosecond increment value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Increment sub-nanosecond increment value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSubNanoSecondIncrementValue(ENET_Type *const pEnet, uint8_t u8Increment) +{ + pEnet->MAC_SUB_SECOND_INCREMENT = (pEnet->MAC_SUB_SECOND_INCREMENT & ~ENET_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK) | + ENET_MAC_SUB_SECOND_INCREMENT_SNSINC(u8Increment); +} + +/** + * @brief Get PTP system time seconds + * + * @param [in] pEnet the base address of the ENET instance + * @return seconds value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetSystemTimeSeconds(const ENET_Type *const pEnet) +{ + return pEnet->MAC_SYSTEM_TIME_SECONDS; +} + +/** + * @brief Get PTP system time nanoseconds + * + * @param [in] pEnet the base address of the ENET instance + * @return nanoseconds value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetSystemTimeNanoSeconds(const ENET_Type *const pEnet) +{ + return pEnet->MAC_SYSTEM_TIME_NANOSECONDS; +} + +/** + * @brief Get PTP system time seconds update register value + * + * @param [in] pEnet the base address of the ENET instance + * @return seconds update register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetSystemTimeSecondsUpdateValue(const ENET_Type *const pEnet) +{ + return pEnet->MAC_SYSTEM_TIME_SECONDS_UPDATE; +} + +/** + * @brief Set PTP system time seconds update register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Seconds seconds update register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSystemTimeSecondsUpdateValue(ENET_Type *const pEnet, uint32_t u32Seconds) +{ + pEnet->MAC_SYSTEM_TIME_SECONDS_UPDATE = u32Seconds; +} + +/** + * @brief Get PTP system time nanoseconds update register value + * + * @param [in] pEnet the base address of the ENET instance + * @return nanoseconds update register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetSystemTimeNanoSecondsUpdateReg(const ENET_Type *const pEnet) +{ + return pEnet->MAC_SYSTEM_TIME_NANOSECONDS_UPDATE; +} + +/** + * @brief Set PTP system time nanoseconds update register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Reg nanoseconds update register value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSystemTimeNanoSecondsUpdateReg(ENET_Type *const pEnet, uint32_t u32Reg) +{ + pEnet->MAC_SYSTEM_TIME_NANOSECONDS_UPDATE = u32Reg; +} + +/** + * @brief Get PTP system time update operation,add or subtract time + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_SystemTimeOperationType + */ +LOCAL_INLINE ENET_MAC_SystemTimeOperationType ENET_HWA_MAC_GetTimeUpdateOperation(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_SYSTEM_TIME_NANOSECONDS_UPDATE & + ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK) >> + ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT; + return (ENET_MAC_SystemTimeOperationType)u32TmpVal; +} + +/** + * @brief Set PTP system time update operation,add or subtract time + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eOperation add or subtract time + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimeUpdateOperation(ENET_Type *const pEnet, ENET_MAC_SystemTimeOperationType eOperation) +{ + pEnet->MAC_SYSTEM_TIME_NANOSECONDS_UPDATE = (pEnet->MAC_SYSTEM_TIME_NANOSECONDS_UPDATE & + ~ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK) | + ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(eOperation); +} + +/** + * @brief Get PTP system time nanoseconds update value + * + * @param [in] pEnet the base address of the ENET instance + * @return nanoseconds update value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetSystemTimeNanoSecondsUpdateValue(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_SYSTEM_TIME_NANOSECONDS_UPDATE & + ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK) >> + ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set PTP system time nanoseconds update value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32NanoSeconds nanoseconds update value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSystemTimeNanoSecondsUpdateValue(ENET_Type *const pEnet, uint32_t u32NanoSeconds) +{ + pEnet->MAC_SYSTEM_TIME_NANOSECONDS_UPDATE = (pEnet->MAC_SYSTEM_TIME_NANOSECONDS_UPDATE & + ~ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK) | + ENET_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(u32NanoSeconds); +} + +/** + * @brief Get PTP timestamp addend register value + * + * @param [in] pEnet the base address of the ENET instance + * @return timestamp addend value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTimestampAddend(const ENET_Type *const pEnet) +{ + return pEnet->MAC_TIMESTAMP_ADDEND; +} + +/** + * @brief Set PTP timestamp addend register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Time timestamp addend value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimestampAddend(ENET_Type *const pEnet, uint32_t u32Time) +{ + pEnet->MAC_TIMESTAMP_ADDEND = u32Time; +} + +/** + * @brief Get PTP system time seconds bits[47:32] value + * + * @param [in] pEnet the base address of the ENET instance + * @return seconds bits[47:32] value + */ +LOCAL_INLINE uint16_t ENET_HWA_MAC_GetSystemTimeHigherWordSeconds(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS & + ENET_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK) >> + ENET_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set PTP system time seconds bits[47:32] value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u16Seconds seconds bits[47:32] value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetSystemTimeHigherWordSeconds(ENET_Type *const pEnet, uint16_t u16Seconds) +{ + pEnet->MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS = ENET_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(u16Seconds); +} + +/** + * @brief Get the timestamp status + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t the timestamp status + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTimestampStatus(const ENET_Type *const pEnet) +{ + return pEnet->MAC_TIMESTAMP_STATUS; +} + +/** + * @brief Indicates whether the transmit timestamp interrupt status is detected + * + * @param [in] pEnet the base address of the ENET instance + * @return true transmit timestamp interrupt is detected + * @return false transmit timestamp interrupt is not detected + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTxTimestampInterruptStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_STATUS & ENET_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK) >> + ENET_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + + +/** + * @brief Clear the transmit timestamp interrupt status + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearTxTimestampInterruptStatus(ENET_Type *const pEnet) +{ + pEnet->MAC_TX_TIMESTAMP_STATUS_SECONDS = ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_MASK; +} + +/** + * @brief Indicates whether the timestamp target time error status of the PPS channel is detected + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann the channel number of PPS + * @return true timestamp target time error is detected + * @return false timestamp target time error is not detected + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTimestampTargetTimeError(const ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_STATUS & + ((uint32_t)ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK << (2u * (uint32_t)ePPSChann))) >> + ((uint32_t)ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT + 2u * (uint32_t)ePPSChann); + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear the timestamp target time error status of the PPS channel + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann the channel number of PPS + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearTimestampTargetTimeError(ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann) +{ + pEnet->MAC_TIMESTAMP_STATUS &= (uint32_t)ENET_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK << (2u * (uint32_t)ePPSChann); +} + +/** + * @brief Indicates whether the timestamp target time reached for target time of the PPS channel + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann the channel number of PPS + * @return true timestamp target time is reached + * @return false timestamp target time is not reached + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTimestampTargetTimeReachedStatus(const ENET_Type *const pEnet, + ENET_MAC_PPSChannelType ePPSChann) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_STATUS & + ((uint32_t)ENET_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK << (2u * (uint32_t)ePPSChann))) >> + ((uint32_t)ENET_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT + 2u * (uint32_t)ePPSChann); + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear the status of the timestamp target time reached for target time of the PPS channel + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann the channel number of PPS + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearTimestampTargetTimeReachedStatus(ENET_Type *const pEnet, + ENET_MAC_PPSChannelType ePPSChann) +{ + pEnet->MAC_TIMESTAMP_STATUS &= (uint32_t)ENET_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK << (2u * (uint32_t)ePPSChann); +} + +/** + * @brief Indicates whether the timestamp seconds overflow status is detected + * + * @param [in] pEnet the base address of the ENET instance + * @return true timestamp seconds overflow status is detected + * @return false timestamp seconds overflow status is not detected + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetTimestampSecondsOverflowStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_STATUS & ENET_MAC_TIMESTAMP_STATUS_TSSOVF_MASK) >> + ENET_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear the timestamp seconds overflow status + * @note This function shall only be called when MAC_CSR_SW_CTRL[RCWE] = 1 + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MAC_ClearTimestampSecondsOverflowStatus(ENET_Type *const pEnet) +{ + pEnet->MAC_TIMESTAMP_STATUS &= ENET_MAC_TIMESTAMP_STATUS_TSSOVF_MASK; +} + +/** + * @brief Contains the nanosecond part of timestamp captured for transmit packets when tx status is disabled + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t transmit timestamp status in nanoseconds + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxTimestampStatusInNanoseconds(const ENET_Type *const pEnet) +{ + return pEnet->MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; +} + +/** + * @brief Contains the second part of timestamp captured for transmit packets when tx status is disabled + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t transmit timestamp status in seconds + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTxTimestampStatusInSeconds(const ENET_Type *const pEnet) +{ + return pEnet->MAC_TX_TIMESTAMP_STATUS_SECONDS; +} + +/** + * @brief Get timestamp ingress asymmetry correction, used for PDelay_Resp PTP messages + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t correction value + */ +LOCAL_INLINE int32_t ENET_HWA_MAC_GetTimestampIngressAsymmetryCorrection(const ENET_Type *const pEnet) +{ + return (int32_t)pEnet->MAC_TIMESTAMP_INGRESS_ASYM_CORR; +} + +/** + * @brief Set timestamp ingress asymmetry correction, used for PDelay_Resp PTP messages + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] s32Correction correction value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimestampIngressAsymmetryCorrection(ENET_Type *const pEnet, int32_t s32Correction) +{ + pEnet->MAC_TIMESTAMP_INGRESS_ASYM_CORR = (uint32_t)s32Correction; +} + +/** + * @brief Get timestamp egress asymmetry correction, used for PDelay_Req PTP messages + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t correction value + */ +LOCAL_INLINE int32_t ENET_HWA_MAC_GetTimestampEgressAsymmetryCorrection(const ENET_Type *const pEnet) +{ + return (int32_t)pEnet->MAC_TIMESTAMP_EGRESS_ASYM_CORR; +} + +/** + * @brief Set timestamp egress asymmetry correction, used for PDelay_Req PTP messages + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] s32Correction correction value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimestampEgressAsymmetryCorrection(ENET_Type *const pEnet, int32_t s32Correction) +{ + pEnet->MAC_TIMESTAMP_EGRESS_ASYM_CORR = (uint32_t)s32Correction; +} + +/** + * @brief Get timestamp ingress correction in nanoseconds, used for timestamp in ingress path + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t correction value + */ +LOCAL_INLINE int32_t ENET_HWA_MAC_GetTimestampIngressCorrectionInNanoseconds(const ENET_Type *const pEnet) +{ + return (int32_t)pEnet->MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; +} + +/** + * @brief Set timestamp ingress correction in nanoseconds, used for timestamp in ingress path + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] s32NanoSec correction value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimestampIngressCorrectionInNanoseconds(ENET_Type *const pEnet, int32_t s32NanoSec) +{ + pEnet->MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND = (uint32_t)s32NanoSec; +} + +/** + * @brief Get timestamp egress correction in nanoseconds, used for timestamp in egress path + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t correction value + */ +LOCAL_INLINE int32_t ENET_HWA_MAC_GetTimestampEgressCorrectionInNanoseconds(const ENET_Type *const pEnet) +{ + return (int32_t)pEnet->MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; +} + +/** + * @brief Set timestamp egress correction in nanoseconds, used for timestamp in egress path + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] s32NanoSec correction value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimestampEgressCorrectionInNanoseconds(ENET_Type *const pEnet, int32_t s32NanoSec) +{ + pEnet->MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND = (uint32_t)s32NanoSec; +} + +/** + * @brief Get timestamp ingress correction in sub-nanoseconds, used for timestamp in ingress path + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t correction value + */ +LOCAL_INLINE int8_t ENET_HWA_MAC_GetTimestampIngressCorrectionInSubNanoseconds(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC & + ENET_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK) >> + ENET_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT; + return (int8_t)u32TmpVal; +} + +/** + * @brief Set timestamp ingress correction in sub-nanoseconds, used for timestamp in ingress path + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] s8SubNanoSec correction value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimestampIngressCorrectionInSubNanoseconds(ENET_Type *const pEnet, int8_t s8SubNanoSec) +{ + pEnet->MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC = ENET_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(s8SubNanoSec); +} + +/** + * @brief Get timestamp egress correction in sub-nanoseconds, used for timestamp in egress path + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t correction value + */ +LOCAL_INLINE int8_t ENET_HWA_MAC_GetTimestampEgressCorrectionInSubNanoseconds(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC & + ENET_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK) >> + ENET_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT; + return (int8_t)u32TmpVal; +} + +/** + * @brief Set timestamp egress correction in sub-nanoseconds, used for timestamp in egress path + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] s8SubNanoSec correction value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetTimestampEgressCorrectionInSubNanoseconds(ENET_Type *const pEnet, int8_t s8SubNanoSec) +{ + pEnet->MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC = ENET_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(s8SubNanoSec); +} + +/** + * @brief Get the ingress MAC latency + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t ingress latency + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTimestampIngressLatency(const ENET_Type *const pEnet) +{ + return pEnet->MAC_TIMESTAMP_INGRESS_LATENCY; +} + +/** + * @brief Get the ingress MAC latency in nanoseconds + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t ingress latency in nanoseconds + */ +LOCAL_INLINE uint16_t ENET_HWA_MAC_GetTimestampIngressLatencyInNanoseconds(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_INGRESS_LATENCY & ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK) >> + ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get the ingress MAC latency in sub-nanoseconds + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t ingress latency in sub-nanoseconds + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetTimestampIngressLatencyInSubNanoseconds(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_INGRESS_LATENCY & ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK) >> + ENET_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get the egress MAC latency + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t egress latency + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetTimestampEgressLatency(const ENET_Type *const pEnet) +{ + return pEnet->MAC_TIMESTAMP_EGRESS_LATENCY; +} + +/** + * @brief Get the egress MAC latency in nanoseconds + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t egress latency in nanoseconds + */ +LOCAL_INLINE uint16_t ENET_HWA_MAC_GetTimestampEgressLatencyInNanoseconds(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_EGRESS_LATENCY & ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK) >> + ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT; + return (uint16_t)u32TmpVal; +} + + +/** + * @brief Get the egress MAC latency in sub-nanoseconds + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t egress latency in sub-nanoseconds + */ +LOCAL_INLINE uint8_t ENET_HWA_MAC_GetTimestampEgressLatencyInSubNanoseconds(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MAC_TIMESTAMP_EGRESS_LATENCY & ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK) >> + ENET_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get PPS control register value + * + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t PPS control value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetPPSControl(const ENET_Type *const pEnet) +{ + return pEnet->PPS.CONTROL; +} + +/** + * @brief Set PPS control register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Ctrl PPS control value + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPPSControl(ENET_Type *const pEnet, uint32_t u32Ctrl) +{ + pEnet->PPS.CONTROL = u32Ctrl; +} + +/** + * @brief Get PPS MCGR Mode enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @return true PPS MCGR Mode is enabled + * @return false PPS MCGR Mode is disabled + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetPPSMCGRModeEnFlag(const ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann) +{ + uint32_t u32TmpVal = pEnet->PPS.CONTROL & ((uint32_t)ENET_MAC_PPS_CONTROL_MCGREN0_MASK << (8u * (uint32_t)ePPSChann)); + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set PPS MCGR Mode enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPPSMCGRModeEnFlag(ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann, bool bEnable) +{ + pEnet->PPS.CONTROL = (pEnet->PPS.CONTROL & (~(ENET_MAC_PPS_CONTROL_MCGREN0_MASK << (8u * (uint32_t)ePPSChann)))) | + ((uint32_t)ENET_MAC_PPS_CONTROL_MCGREN0(bEnable ? 1u : 0u) << (8u * (uint32_t)ePPSChann)); +} + +/** + * @brief Get PPS channel target time register operating mode + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @return ENET_MAC_PPSTargetTimeModeType + */ +LOCAL_INLINE ENET_MAC_PPSTargetTimeModeType ENET_HWA_MAC_GetChannelPPSTargetTimeModeSelect(const ENET_Type *const pEnet, + ENET_MAC_PPSChannelType ePPSChann) +{ + uint32_t u32TmpVal = (pEnet->PPS.CONTROL & (ENET_MAC_PPS_CONTROL_TRGTMODSEL0_MASK << (8u * (uint32_t)ePPSChann))) >> + (ENET_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT + (8u * (uint32_t)ePPSChann)); + return (ENET_MAC_PPSTargetTimeModeType)u32TmpVal; +} + +/** + * @brief Set PPS channel target time register operating mode + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @param [in] eTrgtMode target time operating mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetChannelPPSTargetTimeModeSelect(ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann, + ENET_MAC_PPSTargetTimeModeType eTrgtMode) +{ + pEnet->PPS.CONTROL = (pEnet->PPS.CONTROL & (~(ENET_MAC_PPS_CONTROL_TRGTMODSEL0_MASK << (8u * (uint32_t)ePPSChann)))) | + (ENET_MAC_PPS_CONTROL_TRGTMODSEL0(eTrgtMode) << (8u * (uint32_t)ePPSChann)); +} + +/** + * @brief Get PPS flexible mode enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true PPS work in flexible mode + * @return false PPS work in fixed mode + */ +LOCAL_INLINE bool ENET_HWA_MAC_GetChannelFlexiblePPSOutputEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->PPS.CONTROL & ENET_MAC_PPS_CONTROL_PPSEN0_MASK) >> ENET_MAC_PPS_CONTROL_PPSEN0_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set PPS flexible mode enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable PPS flexible or fixed mode + */ +LOCAL_INLINE void ENET_HWA_MAC_SetChannelFlexiblePPSOutputEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->PPS.CONTROL = (pEnet->PPS.CONTROL & (~ENET_MAC_PPS_CONTROL_PPSEN0_MASK)) | + ENET_MAC_PPS_CONTROL_PPSEN0(bEnable ? 1u : 0u); +} + +/** + * @brief Get PPS MCGR command + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @return ENET_MAC_MCGRCmdType + */ +LOCAL_INLINE ENET_MAC_MCGRCmdType ENET_HWA_MAC_GetPPSMCGRCommand(const ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann) +{ + uint32_t u32TmpVal = (pEnet->PPS.CONTROL & ((uint32_t)ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK << (8u * (uint32_t)ePPSChann))) >> + ((uint32_t)ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT + (8u * (uint32_t)ePPSChann)); + return (ENET_MAC_MCGRCmdType)u32TmpVal; +} + +/** + * @brief Set PPS MCGR command + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @param [in] eCmd MCGR command + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPPSMCGRCommand(ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann, + ENET_MAC_MCGRCmdType eCmd) +{ + pEnet->PPS.CONTROL = (pEnet->PPS.CONTROL & (~(ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK << (8u * (uint32_t)ePPSChann)))) | + (ENET_MAC_PPS_CONTROL_MCGREN0(1u) << (8u * (uint32_t)ePPSChann)) | + (ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(eCmd) << (8u * (uint32_t)ePPSChann)); +} + +/** + * @brief Get flexible PPS command + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @return ENET_MAC_PPSCmdType + */ +LOCAL_INLINE ENET_MAC_PPSCmdType ENET_HWA_MAC_GetFlexiblePPSCommand(ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann) +{ + uint32_t u32TmpVal = (pEnet->PPS.CONTROL & ((uint32_t)ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK << (8u * (uint32_t)ePPSChann))) >> + ((uint32_t)ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT + (8u * (uint32_t)ePPSChann)); + return (ENET_MAC_PPSCmdType)u32TmpVal; +} + +/** + * @brief Set flexible PPS command + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @param [in] eCmd flexible PPS command + */ +LOCAL_INLINE void ENET_HWA_MAC_SetFlexiblePPSCommand(ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann, + ENET_MAC_PPSCmdType eCmd) +{ + pEnet->PPS.CONTROL = (pEnet->PPS.CONTROL & (~(ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK << (8u * (uint32_t)ePPSChann)))) | + (ENET_MAC_PPS_CONTROL_PPSEN0(1u)) | + (ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(eCmd) << (8u * (uint32_t)ePPSChann)); +} + +/** + * @brief Get fixed PPS output frequency + * + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MAC_PPSFreqCtrlType + */ +LOCAL_INLINE ENET_MAC_PPSFreqCtrlType ENET_HWA_MAC_GetFixedPPSOutputFrequency(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->PPS.CONTROL & ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK) >> + ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT; + return (ENET_MAC_PPSFreqCtrlType)u32TmpVal; +} + +/** + * @brief Set fixed PPS output frequency + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eFreq frequency value defined in ENET_MAC_PPSFreqCtrlType + */ +LOCAL_INLINE void ENET_HWA_MAC_SetFixedPPSOutputFrequency(ENET_Type *const pEnet, ENET_MAC_PPSFreqCtrlType eFreq) +{ + pEnet->PPS.CONTROL = ENET_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(eFreq); +} + +/** + * @brief Get PPS target time seconds + + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @return uint32_t target time seconds + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetPPSTargetTimeInSeconds(const ENET_Type *const pEnet, + ENET_MAC_PPSChannelType ePPSChann) +{ + return pEnet->PPS.CH[ePPSChann].TARGET_TIME_SECONDS; +} + +/** + * @brief Set PPS target time seconds + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @param [in] u32Seconds target time seconds + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPPSTargetTimeInSeconds(ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann, + uint32_t u32Seconds) +{ + pEnet->PPS.CH[ePPSChann].TARGET_TIME_SECONDS = u32Seconds; +} + +/** + * @brief Get PPS target time busy status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @return ENET_MAC_StatusType + */ +LOCAL_INLINE ENET_MAC_StatusType ENET_HWA_MAC_GetPPSTargetTimeBusyStatus(const ENET_Type *const pEnet, + ENET_MAC_PPSChannelType ePPSChann) +{ + uint32_t u32TmpVal = (pEnet->PPS.CH[ePPSChann].TARGET_TIME_NANOSECONDS & + ENET_MAC_PPSn_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK) >> + ENET_MAC_PPSn_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT; + return (ENET_MAC_StatusType)u32TmpVal; +} + +/** + * @brief Get PPS target time nanoseconds + + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @return uint32_t target time nanoseconds + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetPPSTargetTimeInNanoseconds(const ENET_Type *const pEnet, + ENET_MAC_PPSChannelType ePPSChann) +{ + uint32_t u32TmpVal = (pEnet->PPS.CH[ePPSChann].TARGET_TIME_NANOSECONDS & + ENET_MAC_PPSn_TARGET_TIME_NANOSECONDS_TTSL0_MASK) >> + ENET_MAC_PPSn_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set PPS target time nanoseconds + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @param [in] u32NanoSeconds target time nanoseconds + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPPSTargetTimeInNanoseconds(ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann, + uint32_t u32NanoSeconds) +{ + pEnet->PPS.CH[ePPSChann].TARGET_TIME_NANOSECONDS = ENET_MAC_PPSn_TARGET_TIME_NANOSECONDS_TTSL0(u32NanoSeconds); +} + +/** + * @brief Get PPS pulse interval + + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @return uint32_t PPS interval value + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetPPSInterval(const ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann) +{ + return pEnet->PPS.CH[ePPSChann].INTERVAL; +} + +/** + * @brief Set PPS pulse interval + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @param [in] u32Interval PPS pulse interval + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPPSInterval(ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann, + uint32_t u32Interval) +{ + pEnet->PPS.CH[ePPSChann].INTERVAL = u32Interval; +} + +/** + * @brief Get PPS pulse width + + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @return uint32_t PPS pulse width + */ +LOCAL_INLINE uint32_t ENET_HWA_MAC_GetPPSWidth(const ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann) +{ + return pEnet->PPS.CH[ePPSChann].WIDTH; +} + +/** + * @brief Set PPS pulse width + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePPSChann PPS channel + * @param [in] u32Width PPS pulse width + */ +LOCAL_INLINE void ENET_HWA_MAC_SetPPSWidth(ENET_Type *const pEnet, ENET_MAC_PPSChannelType ePPSChann, uint32_t u32Width) +{ + pEnet->PPS.CH[ePPSChann].WIDTH = u32Width; +} + +/* ================================================================ * + * ENET MTL Configuration and Status * + * ================================================================ */ + +/** + * @brief Get MTL operation mode register value + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t MTL operation mode + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetOperationMode(const ENET_Type *const pEnet) +{ + return pEnet->MTL.OPERATION_MODE; +} + +/** + * @brief Set MTL operation mode register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32OpMode MTL operation mode + */ +LOCAL_INLINE void ENET_HWA_MTL_SetOperationMode(ENET_Type *const pEnet, uint32_t u32OpMode) +{ + pEnet->MTL.OPERATION_MODE = u32OpMode; +} + +/** + * @brief Get MTL counter reset status + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t counter reset status + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetCounterResetStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.OPERATION_MODE & ENET_MTL_OPERATION_MODE_CNTCLR_MASK) >> + ENET_MTL_OPERATION_MODE_CNTCLR_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Reset MTL counters + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MTL_ResetCounters(ENET_Type *const pEnet) +{ + pEnet->MTL.OPERATION_MODE |= ENET_MTL_OPERATION_MODE_CNTCLR_MASK; +} + +/** + * @brief Get MTL counter preset status + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t counter preset status + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetPresetCounterStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.OPERATION_MODE & ENET_MTL_OPERATION_MODE_CNTPRST_MASK) >> + ENET_MTL_OPERATION_MODE_CNTPRST_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Preset MTL counters + * + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MTL_InitPresetCounters(ENET_Type *const pEnet) +{ + pEnet->MTL.OPERATION_MODE |= ENET_MTL_OPERATION_MODE_CNTPRST_MASK; +} + +/** + * @brief Get MTL algorithm for transmit scheduling + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MTL_TxScheduleAlgorithmType + */ +LOCAL_INLINE ENET_MTL_TxScheduleAlgorithmType ENET_HWA_MTL_GetTxSchedulingAlgorithm(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.OPERATION_MODE & ENET_MTL_OPERATION_MODE_SCHALG_MASK) >> + ENET_MTL_OPERATION_MODE_SCHALG_SHIFT; + return (ENET_MTL_TxScheduleAlgorithmType)u32TmpVal; +} + +/** + * @brief Set MTL algorithm for transmit scheduling + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eScheduleAlgorithm algorithm mode + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTxSchedulingAlgorithm(ENET_Type *const pEnet, + ENET_MTL_TxScheduleAlgorithmType eScheduleAlgorithm) +{ + pEnet->MTL.OPERATION_MODE = (pEnet->MTL.OPERATION_MODE & ~ENET_MTL_OPERATION_MODE_SCHALG_MASK) | + ENET_MTL_OPERATION_MODE_SCHALG(eScheduleAlgorithm); +} + +/** + * @brief Get MTL algorithm for receive arbitration + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MTL_RxArbitrationAlgorithmType + */ +LOCAL_INLINE ENET_MTL_RxArbitrationAlgorithmType ENET_HWA_MTL_GetRxArbitrationAlgorithm(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.OPERATION_MODE & ENET_MTL_OPERATION_MODE_RAA_MASK) >> + ENET_MTL_OPERATION_MODE_RAA_SHIFT; + return (ENET_MTL_RxArbitrationAlgorithmType)u32TmpVal; +} + +/** + * @brief Set MTL algorithm for receive arbitration + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eArbitrationAlgorithm arbitration algorithm mode + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxArbitrationAlgorithm(ENET_Type *const pEnet, + ENET_MTL_RxArbitrationAlgorithmType eArbitrationAlgorithm) +{ + pEnet->MTL.OPERATION_MODE = (pEnet->MTL.OPERATION_MODE & ~ENET_MTL_OPERATION_MODE_RAA_MASK) | + ENET_MTL_OPERATION_MODE_RAA(eArbitrationAlgorithm); +} + +/** + * @brief Get whether tx packet status received from the MAC is droped or not + + * @param [in] pEnet the base address of the ENET instance + * @return true tx packet status is droped + * @return false tx packet status is forwarded to application + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetDropTxPacketStatusEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.OPERATION_MODE & ENET_MTL_OPERATION_MODE_DTXSTS_MASK) >> + ENET_MTL_OPERATION_MODE_DTXSTS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set drop tx packet status enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable drop or forward tx packet status + */ +LOCAL_INLINE void ENET_HWA_MTL_SetDropTxPacketStatusEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.OPERATION_MODE = (pEnet->MTL.OPERATION_MODE & ~ENET_MTL_OPERATION_MODE_DTXSTS_MASK) | + ENET_MTL_OPERATION_MODE_DTXSTS(bEnable ? 1u : 0u); +} + +/** + * @brief Get MTL debug control register value + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t MTL debug control value + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetDebugCtrl(const ENET_Type *const pEnet) +{ + return pEnet->MTL.DBG_CTL; +} + +/** + * @brief Set MTL debug control register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32DebugCtrl control value + */ +LOCAL_INLINE void ENET_HWA_MTL_SetDebugCtrl(ENET_Type *const pEnet, uint32_t u32DebugCtrl) +{ + pEnet->MTL.DBG_CTL = u32DebugCtrl; +} + +/** + * @brief Get transmit status available interrupt status enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true transmit status available interrupt status is enabled + * @return false transmit status available interrupt status is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetTxStatusAvailableIntEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_CTL & ENET_MTL_DBG_CTL_STSIE_MASK) >> ENET_MTL_DBG_CTL_STSIE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set transmit status available interrupt status enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTxStatusAvailableIntEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.DBG_CTL = (pEnet->MTL.DBG_CTL & ~ENET_MTL_DBG_CTL_STSIE_MASK) | ENET_MTL_DBG_CTL_STSIE(bEnable ? 1u : 0u); +} + +/** + * @brief Get receive packet available interrupt status enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true receive packet available interrupt status is enabled + * @return false receive packet available interrupt status is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetRxPacketAvailableIntEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_CTL & ENET_MTL_DBG_CTL_PKTIE_MASK) >> ENET_MTL_DBG_CTL_PKTIE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set receive packet available interrupt status enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxPacketAvailableIntEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.DBG_CTL = (pEnet->MTL.DBG_CTL & ~ENET_MTL_DBG_CTL_PKTIE_MASK) | ENET_MTL_DBG_CTL_PKTIE(bEnable ? 1u : 0u); +} + +/** + * @brief Get the FIFO selected for debug access + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MTL_DebugAccessFIFOType + */ +LOCAL_INLINE ENET_MTL_DebugAccessFIFOType ENET_HWA_MTL_GetDebugAccessFIFO(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_CTL & ENET_MTL_DBG_CTL_FIFOSEL_MASK) >> ENET_MTL_DBG_CTL_FIFOSEL_SHIFT; + return (ENET_MTL_DebugAccessFIFOType)u32TmpVal; +} + +/** + * @brief Set the FIFO selected for debug access + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eFIFOType debug FIFO defined in ENET_MTL_DebugAccessFIFOType + */ +LOCAL_INLINE void ENET_HWA_MTL_SetDebugAccessFIFO(ENET_Type *const pEnet, ENET_MTL_DebugAccessFIFOType eFIFOType) +{ + pEnet->MTL.DBG_CTL = (pEnet->MTL.DBG_CTL & ~ENET_MTL_DBG_CTL_FIFOSEL_MASK) | ENET_MTL_DBG_CTL_FIFOSEL(eFIFOType); +} + +/** + * @brief Get write operation on selected FIFO enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true write operation on selected FIFO is enabled + * @return false write operation on selected FIFO is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetFIFOWriteEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_CTL & ENET_MTL_DBG_CTL_FIFOWREN_MASK) >> ENET_MTL_DBG_CTL_FIFOWREN_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set write operation on selected FIFO enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetFIFOWriteEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.DBG_CTL = (pEnet->MTL.DBG_CTL & ~ENET_MTL_DBG_CTL_FIFOWREN_MASK) | ENET_MTL_DBG_CTL_FIFOWREN(bEnable ? 1u : 0u); +} + +/** + * @brief Get pointers of selected FIFO reset status + + * @param [in] pEnet the base address of the ENET instance + * @return true FIFO reset is enabled + * @return false FIFO reset is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetSelectedFIFOPointerResetStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_CTL & ENET_MTL_DBG_CTL_RSTSEL_MASK) >> ENET_MTL_DBG_CTL_RSTSEL_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Reset pointers of selected FIFO + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetSelectedFIFOPointerResetFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.DBG_CTL = (pEnet->MTL.DBG_CTL & ~ENET_MTL_DBG_CTL_RSTSEL_MASK) | ENET_MTL_DBG_CTL_RSTSEL(bEnable ? 1u : 0u); +} + +/** + * @brief Get pointers of all FIFOs reset status + + * @param [in] pEnet the base address of the ENET instance + * @return true all FIFOs reset is enabled + * @return false all FIFOs reset is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetAllFIFOPointersResetStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_CTL & ENET_MTL_DBG_CTL_RSTALL_MASK) >> ENET_MTL_DBG_CTL_RSTALL_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Reset pointers of all FIFOs + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetAllFIFOPointerResetFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.DBG_CTL = (pEnet->MTL.DBG_CTL & ~ENET_MTL_DBG_CTL_RSTALL_MASK) | ENET_MTL_DBG_CTL_RSTALL(bEnable ? 1u : 0u); +} + +/** + * @brief Encoded packet state,the control information to the Tx FIFO or Rx FIFO + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eState + */ +LOCAL_INLINE void ENET_HWA_MTL_SetFIFOPacketState(ENET_Type *const pEnet, ENET_MTL_FIFOPacketStatusType eState) +{ + pEnet->MTL.DBG_CTL = (pEnet->MTL.DBG_CTL & ~ENET_MTL_DBG_CTL_PKTSTATE_MASK) | ENET_MTL_DBG_CTL_PKTSTATE(eState); +} + +/** + * @brief Indicates the number of data bytes valid in the data register during Write operation + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eByteValid the number of data bytes valid + */ +LOCAL_INLINE void ENET_HWA_MTL_SetByteEnable(ENET_Type *const pEnet, ENET_MTL_ByteEnableType eByteValid) +{ + pEnet->MTL.DBG_CTL = (pEnet->MTL.DBG_CTL & ~ENET_MTL_DBG_CTL_BYTEEN_MASK) | ENET_MTL_DBG_CTL_BYTEEN(eByteValid); +} + +/** + * @brief Get pointers of all FIFOs reset status + + * @param [in] pEnet the base address of the ENET instance + * @return true all FIFOs reset is enabled + * @return false all FIFOs reset is disabled + */ +LOCAL_INLINE ENET_MTL_FIFODebugAccessType ENET_HWA_MTL_GetFIFODebugModeAccessType(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_CTL & ENET_MTL_DBG_CTL_DBGMOD_MASK) >> ENET_MTL_DBG_CTL_DBGMOD_SHIFT; + return (ENET_MTL_FIFODebugAccessType)u32TmpVal; +} + +/** + * @brief Set the debug mode of accessing to fifo + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eAccessType accessing to fifo is restricted or not + */ +LOCAL_INLINE void ENET_HWA_MTL_SetFIFODebugModeAccessType(ENET_Type *const pEnet, ENET_MTL_FIFODebugAccessType eAccessType) +{ + pEnet->MTL.DBG_CTL = (pEnet->MTL.DBG_CTL & ~ENET_MTL_DBG_CTL_DBGMOD_MASK) | ENET_MTL_DBG_CTL_DBGMOD(eAccessType); +} + +/** + * @brief Get FIFO debug access enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true the debug mode access to the FIFO is enabled + * @return false the debug mode access to the FIFO is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetFIFODebugAccessEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_CTL & ENET_MTL_DBG_CTL_FDBGEN_MASK) >> ENET_MTL_DBG_CTL_FDBGEN_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set FIFO debug access enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetFIFODebugAccessEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.DBG_CTL = (pEnet->MTL.DBG_CTL & ~ENET_MTL_DBG_CTL_FDBGEN_MASK) | ENET_MTL_DBG_CTL_FDBGEN(bEnable ? 1u : 0u); +} + +/** + * @brief Get MTL debug status register value + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t debug status + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetDebugStatus(const ENET_Type *const pEnet) +{ + return pEnet->MTL.DBG_STS; +} + +/** + * @brief Get MTL remaining locations in the FIFO + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetFIFORemainingLocation(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_STS & ENET_MTL_DBG_STS_LOCR_MASK) >> ENET_MTL_DBG_STS_LOCR_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get MTL transmit status available interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @return true transmit status available interrupt not detected + * @return false transmit status available interrupt detected + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetTxStatusAvailableIntStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_STS & ENET_MTL_DBG_STS_STSI_MASK) >> ENET_MTL_DBG_STS_STSI_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear MTL transmit status available interrupt status + + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MTL_ClearTxStatusAvailableIntStatus(ENET_Type *const pEnet) +{ + pEnet->MTL.DBG_STS = ENET_MTL_DBG_STS_STSI_MASK; +} + +/** + * @brief Get MTL receive packet available interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @return true receive packet available interrupt not detected + * @return false receive packet available interrupt detected + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetRxPacketAvailableIntStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_STS & ENET_MTL_DBG_STS_PKTI_MASK) >> ENET_MTL_DBG_STS_PKTI_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear MTL receive packet available interrupt status + + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MTL_ClearRxPacketAvailableIntStatus(ENET_Type *const pEnet) +{ + pEnet->MTL.DBG_STS = ENET_MTL_DBG_STS_PKTI_MASK; +} + +/** + * @brief Get the number of data bytes valid in the data register during Read operation + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MTL_ByteEnableType + */ +LOCAL_INLINE ENET_MTL_ByteEnableType ENET_HWA_MTL_GetByteEnable(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_STS & ENET_MTL_DBG_STS_BYTEEN_MASK) >> ENET_MTL_DBG_STS_BYTEEN_SHIFT; + return (ENET_MTL_ByteEnableType)u32TmpVal; +} + +/** + * @brief Get the control or status information of the selected FIFO. + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MTL_FIFOPacketStatusType + */ +LOCAL_INLINE ENET_MTL_FIFOPacketStatusType ENET_HWA_MTL_GetFIFOPacketState(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_STS & ENET_MTL_DBG_STS_PKTSTATE_MASK) >> ENET_MTL_DBG_STS_PKTSTATE_SHIFT; + return (ENET_MTL_FIFOPacketStatusType)u32TmpVal; +} + +/** + * @brief Get MTL FIFO busy status + + * @param [in] pEnet the base address of the ENET instance + * @return true FIFO is busy + * @return false FIFO is not busy + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetFIFOBusy(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.DBG_STS & ENET_MTL_DBG_STS_FIFOBUSY_MASK) >> ENET_MTL_DBG_STS_FIFOBUSY_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get MTL FIFO debug data + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t FIFO debug data + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetFIFODebugData(const ENET_Type *const pEnet) +{ + return pEnet->MTL.FIFO_DEBUG_DATA; +} + +/** + * @brief Set MTL FIFO debug data + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Data debug data to set + */ +LOCAL_INLINE void ENET_HWA_MTL_SetFIFODebugData(ENET_Type *const pEnet, uint32_t u32Data) +{ + pEnet->MTL.FIFO_DEBUG_DATA = u32Data; +} + +/** + * @brief Get MTL interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t MTL interrupt status + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetIntStatus(const ENET_Type *const pEnet) +{ + return pEnet->MTL.INTERRUPT_STATUS; +} + +/** + * @brief Get debug interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @return true Debug interrupt status detected + * @return false Debug interrupt status not detected + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetDebugIntStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.INTERRUPT_STATUS & ENET_MTL_INTERRUPT_STATUS_DBGIS_MASK) >> + ENET_MTL_INTERRUPT_STATUS_DBGIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get Queue 1 interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @return true Queue 1 interrupt status detected + * @return false Queue 1 interrupt status not detected + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetQueue1IntStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.INTERRUPT_STATUS & ENET_MTL_INTERRUPT_STATUS_Q1IS_MASK) >> + ENET_MTL_INTERRUPT_STATUS_Q1IS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get Queue 0 interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @return true Queue 0 interrupt status detected + * @return false Queue 0 interrupt status not detected + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetQueue0IntStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.INTERRUPT_STATUS & ENET_MTL_INTERRUPT_STATUS_Q0IS_MASK) >> + ENET_MTL_INTERRUPT_STATUS_Q0IS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get DA-based DMA channel selection enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true eQueue is enabled for DA-based DMA channel selection + * @return false eQueue is disabled for DA-based DMA channel selection + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetRxDABasedDMAChannelSelectionEnFlag(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.RXQ_DMA_MAP0 & + ((uint32_t)ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK << + ((uint32_t)ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT + + ((uint32_t)ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT - ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT) * (uint32_t)eQueue))); + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set DA-based DMA channel selection enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxDABasedDMAChannelSelectionEnFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + bool bEnable) +{ + pEnet->MTL.RXQ_DMA_MAP0 = (pEnet->MTL.RXQ_DMA_MAP0 & + ~(ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK << + (ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT + + (ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT - ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT) * (uint32_t)eQueue))) | + (ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH(bEnable ? 1u : 0u) << + ((ENET_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT - ENET_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT) * (uint32_t)eQueue)); +} + +/** + * @brief Get DMA channel mapped to eQueue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return ENET_DMA_ChannelType + */ +LOCAL_INLINE ENET_DMA_ChannelType ENET_HWA_MTL_GetRxDMAChannelMap(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.RXQ_DMA_MAP0 & + ((uint32_t)ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK << + ((uint32_t)ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT + + (uint32_t)(ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT - ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT) * (uint32_t)eQueue))) >> + ((uint32_t)ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT + + (uint32_t)(ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT - ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT) * (uint32_t)eQueue); + return (ENET_DMA_ChannelType)u32TmpVal; +} + +/** + * @brief Set DMA channel mapped to eQueue + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxDMAChannelMap(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->MTL.RXQ_DMA_MAP0 = (pEnet->MTL.RXQ_DMA_MAP0 & + ~(ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK << + (ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT + + (ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT - ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT) * (uint32_t)eQueue))) | + (ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH(eDMAChannel) << + ((ENET_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT - ENET_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT) * (uint32_t)eQueue)); +} + +#if ENET_SUPPORT_TIME_SENSITIVE_NETWORK +/** + * @brief Get Time Based Scheduling control register + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t Time Based Scheduling control + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetTBSCtrl(const ENET_Type *const pEnet) +{ + return pEnet->MTL.TBS_CTRL; +} + +/** + * @brief Set Time Based Scheduling control register + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Ctrl control value + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTBSCtrl(ENET_Type *const pEnet, uint32_t u32Ctrl) +{ + pEnet->MTL.TBS_CTRL = u32Ctrl; +} + +/** + * @brief Get launch expiry offset + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t launch expiry offset + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetLaunchExpiryOffset(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.TBS_CTRL & ENET_MTL_TBS_CTRL_LEOS_MASK) >> ENET_MTL_TBS_CTRL_LEOS_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set launch expiry offset + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32ExpiryOffset launch expiry offset value + */ +LOCAL_INLINE void ENET_HWA_MTL_SetLaunchExpiryOffset(ENET_Type *const pEnet, uint32_t u32ExpiryOffset) +{ + pEnet->MTL.TBS_CTRL = (pEnet->MTL.TBS_CTRL & ~ENET_MTL_TBS_CTRL_LEOS_MASK) | ENET_MTL_TBS_CTRL_LEOS(u32ExpiryOffset); +} + +/** + * @brief Get launch expiry offset enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true launch expiry offset is valid + * @return false launch expiry offset is invalid + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetLaunchExpiryOffsetEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.TBS_CTRL & ENET_MTL_TBS_CTRL_LEOV_MASK) >> ENET_MTL_TBS_CTRL_LEOV_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set launch expiry offset enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable launch expiry offset + */ +LOCAL_INLINE void ENET_HWA_MTL_SetLaunchExpiryOffsetEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.TBS_CTRL = (pEnet->MTL.TBS_CTRL & ~ENET_MTL_TBS_CTRL_LEOV_MASK) | ENET_MTL_TBS_CTRL_LEOV(bEnable ? 1u : 0u); +} + +/** + * @brief Get enhancements to scheduled transmission control register value + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t EST control value + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetEstControl(const ENET_Type *const pEnet) +{ + return pEnet->MTL.EST_CONTROL; +} + +/** + * @brief Set enhancements to scheduled transmission control register value + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32EstControl EST control value + */ +LOCAL_INLINE void ENET_HWA_MTL_SetEstControl(ENET_Type *const pEnet, uint32_t u32EstControl) +{ + pEnet->MTL.EST_CONTROL = u32EstControl; +} + +/** + * @brief Get enhancements to scheduled transmission PTP time offset + + * @param [in] pEnet the base address of the ENET instance + * @return uint8_t PTP time offset + */ +LOCAL_INLINE uint8_t ENET_HWA_MTL_GetEstPtpTimeOffset(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_CONTROL & ENET_MTL_EST_CONTROL_PTOV_MASK) >> + ENET_MTL_EST_CONTROL_PTOV_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set enhancements to scheduled transmission PTP time offset + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8Value PTP time offset + */ +LOCAL_INLINE void ENET_HWA_MTL_SetEstPtpTimeOffset(ENET_Type *const pEnet, uint8_t u8Value) +{ + pEnet->MTL.EST_CONTROL = (pEnet->MTL.EST_CONTROL & + ~ENET_MTL_EST_CONTROL_PTOV_MASK) | + ENET_MTL_EST_CONTROL_PTOV(u8Value); +} + +/** + * @brief Get enhancements to scheduled transmission current time offset + + * @param [in] pEnet the base address of the ENET instance + * @return uint16_t current time offset + */ +LOCAL_INLINE uint16_t ENET_HWA_MTL_GetEstCurrentTimeOffset(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_CONTROL & ENET_MTL_EST_CONTROL_CTOV_MASK) >> + ENET_MTL_EST_CONTROL_CTOV_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set enhancements to scheduled transmission current time offset + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u16Value current time offset + */ +LOCAL_INLINE void ENET_HWA_MTL_SetEstCurrentTimeOffset(ENET_Type *const pEnet, uint16_t u16Value) +{ + pEnet->MTL.EST_CONTROL = (pEnet->MTL.EST_CONTROL & + ~ENET_MTL_EST_CONTROL_CTOV_MASK) | + ENET_MTL_EST_CONTROL_CTOV(u16Value); +} + +/** + * @brief Get EST time interval left shift amount + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MTL_GCLIntervalMultipleType + */ +LOCAL_INLINE ENET_MTL_GCLIntervalMultipleType ENET_HWA_MTL_GetEstTimeIntervalLeftShift(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_CONTROL & ENET_MTL_EST_CONTROL_TILS_MASK) >> + ENET_MTL_EST_CONTROL_TILS_SHIFT; + return (ENET_MTL_GCLIntervalMultipleType)u32TmpVal; +} + +/** + * @brief Set EST time interval left shift amount + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eValue left shift amount + */ +LOCAL_INLINE void ENET_HWA_MTL_SetEstTimeIntervalLeftShift(ENET_Type *const pEnet, ENET_MTL_GCLIntervalMultipleType eValue) +{ + pEnet->MTL.EST_CONTROL = (pEnet->MTL.EST_CONTROL & + ~ENET_MTL_EST_CONTROL_TILS_MASK) | + ENET_MTL_EST_CONTROL_TILS(eValue); +} + +/** + * @brief Get the loop count to report scheduling error + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MTL_ScheduleErrorLoopCountType + */ +LOCAL_INLINE ENET_MTL_ScheduleErrorLoopCountType ENET_HWA_MTL_GetEstScheduleErrorLoopCount(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_CONTROL & ENET_MTL_EST_CONTROL_LCSE_MASK) >> + ENET_MTL_EST_CONTROL_LCSE_SHIFT; + return (ENET_MTL_ScheduleErrorLoopCountType)u32TmpVal; +} + +/** + * @brief Set the loop count to report scheduling error + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] eValue loop count + */ +LOCAL_INLINE void ENET_HWA_MTL_SetEstScheduleErrorLoopCount(ENET_Type *const pEnet, ENET_MTL_ScheduleErrorLoopCountType eValue) +{ + pEnet->MTL.EST_CONTROL = (pEnet->MTL.EST_CONTROL & + ~ENET_MTL_EST_CONTROL_LCSE_MASK) | + ENET_MTL_EST_CONTROL_LCSE(eValue); +} + +/** + * @brief Drop frames causing scheduling error + + * @param [in] pEnet the base address of the ENET instance + * @return true Drop frames causing scheduling error + * @return false Do not drop frames causing scheduling error + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetDropSchedulingErrorFramesEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_CONTROL & ENET_MTL_EST_CONTROL_DFBS_MASK) >> + ENET_MTL_EST_CONTROL_DFBS_SHIFT; + return (bool)u32TmpVal; +} + +/** + * @brief Enable dropping frames causing scheduling error + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetDropSchedulingErrorFramesEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_CONTROL = (pEnet->MTL.EST_CONTROL & + ~ENET_MTL_EST_CONTROL_DFBS_MASK) | + ENET_MTL_EST_CONTROL_DFBS(bEnable ? 1u : 0u); +} + +/** + * @brief Drop frames during frame size error + + * @param [in] pEnet the base address of the ENET instance + * @return true Do not drop frames during frame size error + * @return false Drop frames during frame size error + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetDropFrameSizeErrorFramesDisableFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_CONTROL & ENET_MTL_EST_CONTROL_DDBF_MASK) >> + ENET_MTL_EST_CONTROL_DDBF_SHIFT; + return (bool)u32TmpVal; +} + +/** + * @brief Enable dropping frames causing scheduling error + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bDisable disable or enable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetDropFrameSizeErrorFramesDisableFlag(ENET_Type *const pEnet, bool bDisable) +{ + pEnet->MTL.EST_CONTROL = (pEnet->MTL.EST_CONTROL & + ~ENET_MTL_EST_CONTROL_DDBF_MASK) | + ENET_MTL_EST_CONTROL_DDBF(bDisable ? 1u : 0u); +} + +/** + * @brief Get switch gate control list enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true switch gate control list is enabled + * @return false switch gate control list is diabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetSwitchGateControlListEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_CONTROL & ENET_MTL_EST_CONTROL_SSWL_MASK) >> + ENET_MTL_EST_CONTROL_SSWL_SHIFT; + return (bool)u32TmpVal; +} + +/** + * @brief Switch gate control list + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetSwitchGateControlListEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_CONTROL = (pEnet->MTL.EST_CONTROL & + ~ENET_MTL_EST_CONTROL_SSWL_MASK) | + ENET_MTL_EST_CONTROL_SSWL(bEnable ? 1u : 0u); +} + +/** + * @brief Get EST enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true EST is enabled + * @return false EST is diabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetEstEnableFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_CONTROL & ENET_MTL_EST_CONTROL_EEST_MASK) >> + ENET_MTL_EST_CONTROL_EEST_SHIFT; + return (bool)u32TmpVal; +} + +/** + * @brief Enable EST + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetEstEnableFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_CONTROL = (pEnet->MTL.EST_CONTROL & + ~ENET_MTL_EST_CONTROL_EEST_MASK) | + ENET_MTL_EST_CONTROL_EEST(bEnable ? 1u : 0u); +} + +/** + * @brief Get EST overhead bytes value + + * @param [in] pEnet the base address of the ENET instance + * @return uint8_t EST overhead bytes value + */ +LOCAL_INLINE uint8_t ENET_HWA_MTL_GetEstOverheadBytes(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_EXT_CONTROL & ENET_MTL_EST_EXT_CONTROL_OVHD_MASK) >> + ENET_MTL_EST_EXT_CONTROL_OVHD_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set EST overhead bytes value + * + * @param[in] pEnet the base address of the ENET instance + * @param[in] u8Value EST overhead bytes value + */ +LOCAL_INLINE void ENET_HWA_MTL_SetEstOverheadBytes(ENET_Type *const pEnet, uint8_t u8Value) +{ + pEnet->MTL.EST_CONTROL = (pEnet->MTL.EST_EXT_CONTROL & + ~ENET_MTL_EST_EXT_CONTROL_OVHD_MASK) | + ENET_MTL_EST_EXT_CONTROL_OVHD(u8Value); +} + +/** + * @brief Get EST status register value + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t EST status register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetEstStatus(const ENET_Type *const pEnet) +{ + return pEnet->MTL.EST_STATUS; +} + +/** + * @brief Get current GCL slot number + + * @param [in] pEnet the base address of the ENET instance + * @return uint8_t current GCL slot number + */ +LOCAL_INLINE uint8_t ENET_HWA_MTL_GetCurrentGCLSlotNumber(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_STATUS & ENET_MTL_EST_STATUS_CGSN_MASK) >> + ENET_MTL_EST_STATUS_CGSN_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get BTR error loop count + + * @param [in] pEnet the base address of the ENET instance + * @return uint8_t BTR error loop count + */ +LOCAL_INLINE uint8_t ENET_HWA_MTL_GetBTRErrorLoopCount(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_STATUS & ENET_MTL_EST_STATUS_BTRL_MASK) >> + ENET_MTL_EST_STATUS_BTRL_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get the gate control list owned by software + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MTL_GateControlListType + */ +LOCAL_INLINE ENET_MTL_GateControlListType ENET_HWA_MTL_GetSoftwareOwnedList(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_STATUS & ENET_MTL_EST_STATUS_SWOL_MASK) >> + ENET_MTL_EST_STATUS_SWOL_SHIFT; + return (ENET_MTL_GateControlListType)u32TmpVal; +} + +/** + * @brief Get constant gate control error + + * @param [in] pEnet the base address of the ENET instance + * @return true constant gate control error detected + * @return false constant gate control error not detected + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetConstantGateControlErrorFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_STATUS & ENET_MTL_EST_STATUS_CGCE_MASK) >> + ENET_MTL_EST_STATUS_CGCE_SHIFT; + return (bool)u32TmpVal; +} + +/** + * @brief Clear constant gate control error flag + + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MTL_ClearConstantGateControlErrorFlag(ENET_Type *const pEnet) +{ + pEnet->MTL.EST_STATUS = pEnet->MTL.EST_STATUS | ENET_MTL_EST_STATUS_CGCE_MASK; +} + +/** + * @brief Get Head-Of-Line blocking due to scheduling + + * @param [in] pEnet the base address of the ENET instance + * @return true Head-Of-Line blocking due to scheduling detected + * @return false Head-Of-Line blocking due to scheduling not detected + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetHeadOfLineBlockingDueToSchedulingFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_STATUS & ENET_MTL_EST_STATUS_HLBS_MASK) >> + ENET_MTL_EST_STATUS_HLBS_SHIFT; + return (bool)u32TmpVal; +} + +/** + * @brief Get Head-Of-Line blocking due to frame size + + * @param [in] pEnet the base address of the ENET instance + * @return true Head-Of-Line blocking due to frame size detected + * @return false Head-Of-Line blocking due to frame size not detected + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetHeadOfLineBlockingDueToFrameSizeFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_STATUS & ENET_MTL_EST_STATUS_HLBF_MASK) >> + ENET_MTL_EST_STATUS_HLBF_SHIFT; + return (bool)u32TmpVal; +} + +/** + * @brief Get BTR error flag + + * @param [in] pEnet the base address of the ENET instance + * @return true BTR error detected + * @return false BTR error not detected + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetBTRErrorFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_STATUS & ENET_MTL_EST_STATUS_BTRE_MASK) >> + ENET_MTL_EST_STATUS_BTRE_SHIFT; + return (bool)u32TmpVal; +} + +/** + * @brief Clear BTR error flag + + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MTL_ClearBTRErrorFlag(ENET_Type *const pEnet) +{ + pEnet->MTL.EST_STATUS = pEnet->MTL.EST_STATUS | ENET_MTL_EST_STATUS_BTRE_MASK; +} + +/** + * @brief Get switch gate control list complete status + + * @param [in] pEnet the base address of the ENET instance + * @return true Switching to S/W owned list completed + * @return false Switching to S/W owned list not completed + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetSwitchGateControlListCompleteFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_STATUS & ENET_MTL_EST_STATUS_SWLC_MASK) >> + ENET_MTL_EST_STATUS_SWLC_SHIFT; + return (bool)u32TmpVal; +} + +/** + * @brief Clear switch gate control list complete status + + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MTL_ClearSwitchGateControlListCompleteFlag(ENET_Type *const pEnet) +{ + pEnet->MTL.EST_STATUS = pEnet->MTL.EST_STATUS | ENET_MTL_EST_STATUS_SWLC_MASK; +} + +/** + * @brief Get the One Hot encoded queue numbers that are having the scheduling related error + + * @param [in] pEnet the base address of the ENET instance + * @return true queue 1 caused scheduling error + * @return false queue 0 caused scheduling error + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetScheduleErrorQueueNumber(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_SCH_ERROR & ENET_MTL_EST_SCH_ERROR_SEQN_MASK) >> + ENET_MTL_EST_SCH_ERROR_SEQN_SHIFT; + return (bool)u32TmpVal; +} + +/** + * @brief Clear the value of schedule error queue number register + + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MTL_ClearScheduleErrorQueueNumber(ENET_Type *const pEnet) +{ + pEnet->MTL.EST_SCH_ERROR = pEnet->MTL.EST_SCH_ERROR | ENET_MTL_EST_SCH_ERROR_SEQN_MASK; +} + +/** + * @brief Get the One Hot encoded queue numbers that are having the frame size error + + * @param [in] pEnet the base address of the ENET instance + * @return true queue 1 caused frame size error + * @return false queue 0 caused frame size error + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetFrameSizeErrorQueueNumber(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_FRM_SIZE_ERROR & ENET_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK) >> + ENET_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT; + return (bool)u32TmpVal; +} + +/** + * @brief Clear the value of frame size error queue number register + + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_MTL_ClearFrameSizeErrorQueueNumber(ENET_Type *const pEnet) +{ + pEnet->MTL.EST_FRM_SIZE_ERROR = pEnet->MTL.EST_FRM_SIZE_ERROR | ENET_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK; +} + +/** + * @brief Get the queue numbers that are having the first frame size error + + * @param [in] pEnet the base address of the ENET instance + * @return true queue 1 caused the first frame size error + * @return false queue 0 caused the first frame size error + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetFrameSizeErrorFirstQueueNumber(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_FRM_SIZE_CAPTURE & ENET_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK) >> + ENET_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT; + return (bool)u32TmpVal; +} + +/** + * @brief Get the frame size of the first frame size error + + * @param [in] pEnet the base address of the ENET instance + * @return uint16_t frame size of the first frame size error + */ +LOCAL_INLINE uint16_t ENET_HWA_MTL_GetFrameSizeErrorFirstFrameSize(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_FRM_SIZE_CAPTURE & ENET_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK) >> + ENET_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get enable flag of constant gate control error interrupt + + * @param [in] pEnet the base address of the ENET instance + * @return true CGCE interrupt is enabled + * @return false CGCE interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetConstantGateControlErrorInterruptEnFlag(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_INTR_ENABLE & ENET_MTL_EST_INTR_ENABLE_CGCE_MASK) >> + ENET_MTL_EST_INTR_ENABLE_CGCE_SHIFT; + return u32TmpVal != 0u ? true : false; +} + +/** + * @brief Set enable flag of constant gate control error interrupt + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetConstantGateControlErrorInterruptEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_INTR_ENABLE = (pEnet->MTL.EST_INTR_ENABLE & ~ENET_MTL_EST_INTR_ENABLE_CGCE_MASK) | + ENET_MTL_EST_INTR_ENABLE_CGCE(bEnable ? 1u : 0u); +} + +/** + * @brief Get enable flag of head of line blocking due to scheduling interrupt + + * @param [in] pEnet the base address of the ENET instance + * @return true HLBS interrupt is enabled + * @return false HLBS interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetHeadofLineBlockingDueToSchedulingInterruptEnFlag(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_INTR_ENABLE & ENET_MTL_EST_INTR_ENABLE_IEHS_MASK) >> + ENET_MTL_EST_INTR_ENABLE_IEHS_SHIFT; + return u32TmpVal != 0u ? true : false; +} + +/** + * @brief Set enable flag of head of line blocking due to scheduling interrupt + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetHeadofLineBlockingDueToSchedulingInterruptEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_INTR_ENABLE = (pEnet->MTL.EST_INTR_ENABLE & ~ENET_MTL_EST_INTR_ENABLE_IEHS_MASK) | + ENET_MTL_EST_INTR_ENABLE_IEHS(bEnable ? 1u : 0u); +} + +/** + * @brief Get enable flag of head of line blocking due to frame size interrupt + + * @param [in] pEnet the base address of the ENET instance + * @return true HLBF interrupt is enabled + * @return false HLBF interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetHeadofLineBlockingDueToFrameSizeInterruptEnFlag(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_INTR_ENABLE & ENET_MTL_EST_INTR_ENABLE_IEHF_MASK) >> + ENET_MTL_EST_INTR_ENABLE_IEHF_SHIFT; + return u32TmpVal != 0u ? true : false; +} + +/** + * @brief Set enable flag of head of line blocking due to frame size interrupt + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetHeadofLineBlockingDueToFrameSizeInterruptEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_INTR_ENABLE = (pEnet->MTL.EST_INTR_ENABLE & ~ENET_MTL_EST_INTR_ENABLE_IEHF_MASK) | + ENET_MTL_EST_INTR_ENABLE_IEHF(bEnable ? 1u : 0u); +} + +/** + * @brief Get enable flag of base time register error interrupt + + * @param [in] pEnet the base address of the ENET instance + * @return true BTR Error interrupt is enabled + * @return false BTR Error interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetBaseTimeRegisterErrorInterruptEnFlag(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_INTR_ENABLE & ENET_MTL_EST_INTR_ENABLE_IEBE_MASK) >> + ENET_MTL_EST_INTR_ENABLE_IEBE_SHIFT; + return u32TmpVal != 0u ? true : false; +} + +/** + * @brief Set enable flag of base time register error interrupt + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetBaseTimeRegisterErrorInterruptEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_INTR_ENABLE = (pEnet->MTL.EST_INTR_ENABLE & ~ENET_MTL_EST_INTR_ENABLE_IEBE_MASK) | + ENET_MTL_EST_INTR_ENABLE_IEBE(bEnable ? 1u : 0u); +} + +/** + * @brief Get enable flag of switch GCL completion interrupt + + * @param [in] pEnet the base address of the ENET instance + * @return true BTR Error interrupt is enabled + * @return false BTR Error interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetSwitchListInterruptEnFlag(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_INTR_ENABLE & ENET_MTL_EST_INTR_ENABLE_IECC_MASK) >> + ENET_MTL_EST_INTR_ENABLE_IECC_SHIFT; + return u32TmpVal != 0u ? true : false; +} + +/** + * @brief Set enable flag of base time switch GCL completion interrupt + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetSwitchListInterruptEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_INTR_ENABLE = (pEnet->MTL.EST_INTR_ENABLE & ~ENET_MTL_EST_INTR_ENABLE_IECC_MASK) | + ENET_MTL_EST_INTR_ENABLE_IECC(bEnable ? 1u : 0u); +} + +/** + * @brief Get the mode of EST ECC inject error control for EST memory + + * @param [in] pEnet the base address of the ENET instance + * @return true inject 2 bit errors + * @return false inject 1 bit error + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetEstEccInjectErrorControl(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_GCL_CONTROL & ENET_MTL_EST_GCL_CONTROL_ESTEIEC_MASK) >> + ENET_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT; + return u32TmpVal != 0u ? true : false; +} + +/** + * @brief Set the mode of EST ECC inject error control for EST memory + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable true inject 2 bit errors,false inject 1 bit error + */ +LOCAL_INLINE void ENET_HWA_MTL_SetEstEccInjectErrorControl(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_GCL_CONTROL = (pEnet->MTL.EST_GCL_CONTROL & ~ENET_MTL_EST_GCL_CONTROL_ESTEIEC_MASK) | + ENET_MTL_EST_GCL_CONTROL_ESTEIEC(bEnable ? 1u : 0u); +} + +/** + * @brief Get enable flag of EST ECC address error injection + + * @param [in] pEnet the base address of the ENET instance + * @return true inject 2 bit errors + * @return false inject 1 bit error + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetEstEccInjectAddressErrorEnFlag(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_GCL_CONTROL & ENET_MTL_EST_GCL_CONTROL_ESTEIAEE_MASK) >> + ENET_MTL_EST_GCL_CONTROL_ESTEIAEE_SHIFT; + return u32TmpVal != 0u ? true : false; +} + +/** + * @brief Set enable flag of EST ECC address error injection + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetEstEccInjectAddressErrorEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_GCL_CONTROL = (pEnet->MTL.EST_GCL_CONTROL & ~ENET_MTL_EST_GCL_CONTROL_ESTEIAEE_MASK) | + ENET_MTL_EST_GCL_CONTROL_ESTEIAEE(bEnable ? 1u : 0u); +} + +/** + * @brief Get enable flag of EST ECC error injection + + * @param [in] pEnet the base address of the ENET instance + * @return true EST ECC inject error is enabled + * @return false EST ECC inject error is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetEstEccInjectErrorEnFlag(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_GCL_CONTROL & ENET_MTL_EST_GCL_CONTROL_ESTEIEE_MASK) >> + ENET_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT; + return u32TmpVal != 0u ? true : false; +} + +/** + * @brief Set enable flag of EST ECC error injection + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetEstEccInjectErrorEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_GCL_CONTROL = (pEnet->MTL.EST_GCL_CONTROL & ~ENET_MTL_EST_GCL_CONTROL_ESTEIEE_MASK) | + ENET_MTL_EST_GCL_CONTROL_ESTEIEE(bEnable ? 1u : 0u); +} + +/** + * @brief Get GCL address or GCL related registers address depend on GCRR bit + + * @param [in] pEnet the base address of the ENET instance + * @return uint8_t GCL address or GCL related registers address + */ +LOCAL_INLINE uint8_t ENET_HWA_MTL_GetEstGateControlListAddress(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_GCL_CONTROL & ENET_MTL_EST_GCL_CONTROL_ADDR_MASK) >> + ENET_MTL_EST_GCL_CONTROL_ADDR_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set GCL address or GCL related registers address depend on GCRR bit + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eAddress GCL address or GCL related registers address + */ +LOCAL_INLINE void ENET_HWA_MTL_SetEstGateControlListAddress(ENET_Type *const pEnet, uint8_t eAddress) +{ + pEnet->MTL.EST_GCL_CONTROL = (pEnet->MTL.EST_GCL_CONTROL & ~ENET_MTL_EST_GCL_CONTROL_ADDR_MASK) | + ENET_MTL_EST_GCL_CONTROL_ADDR(eAddress); +} + +/** + * @brief Get GCL debug mode bank selected + + * @param [in] pEnet the base address of the ENET instance + * @return uint8_t debug mode bank + */ +LOCAL_INLINE uint8_t ENET_HWA_MTL_GetGclDebugModeBankSelect(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_GCL_CONTROL & ENET_MTL_EST_GCL_CONTROL_DBGB_MASK) >> + ENET_MTL_EST_GCL_CONTROL_DBGB_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set GCL debug mode bank + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eBank debug mode bank + */ +LOCAL_INLINE void ENET_HWA_MTL_SetGclDebugModeBankSelect(ENET_Type *const pEnet, uint8_t eBank) +{ + pEnet->MTL.EST_GCL_CONTROL = (pEnet->MTL.EST_GCL_CONTROL & ~ENET_MTL_EST_GCL_CONTROL_DBGB_MASK) | + ENET_MTL_EST_GCL_CONTROL_DBGB(eBank); +} + +/** + * @brief Get GCL debug mode enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true debug mode is enabled + * @return false debug mode is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetGclDebugModeEnFlag(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_GCL_CONTROL & ENET_MTL_EST_GCL_CONTROL_DBGM_MASK) >> + ENET_MTL_EST_GCL_CONTROL_DBGM_SHIFT; + return u32TmpVal != 0u ? true : false; +} + +/** + * @brief Set GCL debug mode enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetGclDebugModeEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_GCL_CONTROL = (pEnet->MTL.EST_GCL_CONTROL & ~ENET_MTL_EST_GCL_CONTROL_DBGM_MASK) | + ENET_MTL_EST_GCL_CONTROL_DBGM(bEnable ? 1u : 0u); +} + +/** + * @brief Get gate control releated registers enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true ADDR fields is used for gate control releated registers + * @return false ADDR fields is used for gate control list address + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetGateControlReleatedRegistersEnFlag(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_GCL_CONTROL & ENET_MTL_EST_GCL_CONTROL_GCRR_MASK) >> + ENET_MTL_EST_GCL_CONTROL_GCRR_SHIFT; + return u32TmpVal != 0u ? true : false; +} + +/** + * @brief Set gate control releated registers enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetGateControlReleatedRegistersEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_GCL_CONTROL = (pEnet->MTL.EST_GCL_CONTROL & ~ENET_MTL_EST_GCL_CONTROL_GCRR_MASK) | + ENET_MTL_EST_GCL_CONTROL_GCRR(bEnable ? 1u : 0u); +} + +/** + * @brief Get GCL operation mode (read or write) + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_MTL_GclOperationType (read or write) + */ +LOCAL_INLINE ENET_MTL_GclOperationType ENET_HWA_MTL_GetGclOperation(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_GCL_CONTROL & ENET_MTL_EST_GCL_CONTROL_R1W0_MASK) >> + ENET_MTL_EST_GCL_CONTROL_R1W0_SHIFT; + return (ENET_MTL_GclOperationType)u32TmpVal; +} + +/** + * @brief Set GCL operation mode (read or write) + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eOperation (read or write) + */ +LOCAL_INLINE void ENET_HWA_MTL_SetGclOperation(ENET_Type *const pEnet, ENET_MTL_GclOperationType eOperation) +{ + pEnet->MTL.EST_GCL_CONTROL = (pEnet->MTL.EST_GCL_CONTROL & ~ENET_MTL_EST_GCL_CONTROL_R1W0_MASK) | + ENET_MTL_EST_GCL_CONTROL_R1W0(eOperation); +} + +/** + * @brief Get GCL operation busy status + + * @param [in] pEnet the base address of the ENET instance + * @return true Start Read/Write operation is enabled,status is busy + * @return false Start Read/Write operation is disabled,status is idle + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetGclOperationBusyState(ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.EST_GCL_CONTROL & ENET_MTL_EST_GCL_CONTROL_SRWO_MASK) >> + ENET_MTL_EST_GCL_CONTROL_SRWO_SHIFT; + return u32TmpVal != 0u ? true : false; +} + +/** + * @brief Start GCL Read/Write operation + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetGclOperationStartFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.EST_GCL_CONTROL = (pEnet->MTL.EST_GCL_CONTROL & ~ENET_MTL_EST_GCL_CONTROL_SRWO_MASK) | + ENET_MTL_EST_GCL_CONTROL_SRWO(bEnable ? 1u : 0u); +} + +/** + * @brief Get GCL data + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t GCL data value + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetGclData(ENET_Type *const pEnet) +{ + return pEnet->MTL.EST_GCL_DATA; +} + +/** + * @brief Set GCL data register value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eData data to set + */ +LOCAL_INLINE void ENET_HWA_MTL_SetGclData(ENET_Type *const pEnet, uint32_t eData) +{ + pEnet->MTL.EST_GCL_DATA = eData; +} + +/** + * @brief Set the corresponding Queue classified as express or preemptable. + * @details Set the Classification of Queues.A bit indicates a queue, when '1' indicates the + * corresponding Queue must be classified as preemptable, when '0' Queue is classified + * as express. + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u8value Preemption classification value + */ +LOCAL_INLINE void ENET_HWA_MTL_SetPreemptionClassification(ENET_Type *const pEnet, uint8_t u8value) +{ + pEnet->MTL.FPE_CTRL_STS = (pEnet->MTL.FPE_CTRL_STS & ~ENET_MTL_FPE_CTRL_STS_PEC_MASK) | + ENET_MTL_FPE_CTRL_STS_PEC(u8value); +} + +/** + * @brief Set the maximum time in nanoseconds that can elapse between issuing a RELEASE to the MAC + * and the MAC being ready to resume transmission of preemptable frames. + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u16value Release Advance time value + */ +LOCAL_INLINE void ENET_HWA_MTL_SetPreemptionReleaseAdvance(ENET_Type *const pEnet, uint16_t u16value) +{ + pEnet->MTL.FPE_ADVANCE = (pEnet->MTL.FPE_ADVANCE & ~ENET_MTL_FPE_ADVANCE_RADV_MASK) | + ENET_MTL_FPE_ADVANCE_RADV(u16value); +} + +/** + * @brief Set the maximum time in nanoseconds that can elapse between issuing a HOLD to the MAC + * and the MAC ceasing to transmit any preemptable frame. + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] u16value Hold Advance time value + */ +LOCAL_INLINE void ENET_HWA_MTL_SetPreemptionHoldAdvance(ENET_Type *const pEnet, uint16_t u16value) +{ + pEnet->MTL.FPE_ADVANCE = (pEnet->MTL.FPE_ADVANCE & ~ENET_MTL_FPE_ADVANCE_HADV_MASK) | + ENET_MTL_FPE_ADVANCE_HADV(u16value); +} +#endif /* ENET_SUPPORT_TIME_SENSITIVE_NETWORK */ + +/** + * @brief Get MTL queue Tx operation mode register value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint32_t MTL queue Tx operation mode + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetTxOperationMode(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + return pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE; +} + +/** + * @brief Set MTL queue Tx operation mode register value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] u32OpMode MTL queue Tx operation mode + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTxOperationMode(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, uint32_t u32OpMode) +{ + pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE = u32OpMode; +} + +/** + * @brief Get MTL transmit queue size + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint8_t queue size in blocks of 256 bytes + */ +LOCAL_INLINE uint8_t ENET_HWA_MTL_GetTxQueueSize(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE & ENET_MTL_TXQn_OPERATION_MODE_TQS_MASK) >> + ENET_MTL_TXQn_OPERATION_MODE_TQS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set MTL transmit queue size + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] u8QueueSize queue size in blocks of 256 bytes,range(0~15) + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTxQueueSize(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, uint8_t u8QueueSize) +{ + pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE = (pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE & + (~ENET_MTL_TXQn_OPERATION_MODE_TQS_MASK)) | + ENET_MTL_TXQn_OPERATION_MODE_TQS(u8QueueSize); +} + +/** + * @brief Get the threshold level of the MTL Tx Queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return ENET_MTL_TxThresholdType_t threshold level + */ +LOCAL_INLINE ENET_MTL_TxThresholdType ENET_HWA_MTL_GetTxThreshold(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE; + uint32_t u32Threshold = (u32TmpVal & ENET_MTL_TXQn_OPERATION_MODE_TTC_MASK) >> ENET_MTL_TXQn_OPERATION_MODE_TTC_SHIFT; + return ((u32TmpVal & ENET_MTL_TXQn_OPERATION_MODE_TSF_MASK) == ENET_MTL_TXQn_OPERATION_MODE_TSF_MASK) ? + ENET_MTL_TX_STORE_FORWARD : (ENET_MTL_TxThresholdType)u32Threshold; +} + +/** + * @brief Set the threshold level of the MTL Tx Queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] eThreshold threshold level + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTxThreshold(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + ENET_MTL_TxThresholdType eThreshold) +{ + pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE = (pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE & + (~(ENET_MTL_TXQn_OPERATION_MODE_TTC_MASK | ENET_MTL_TXQn_OPERATION_MODE_TSF_MASK))) | + (ENET_MTL_TXQn_OPERATION_MODE_TTC(eThreshold) | + ENET_MTL_TXQn_OPERATION_MODE_TSF((uint32_t)eThreshold >> ENET_MTL_TXQn_OPERATION_MODE_TTC_WIDTH)); +} + +/** + * @brief Get the transmit queue enable mode + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return ENET_MTL_QueueEnableType queue enable mode + */ +LOCAL_INLINE ENET_MTL_QueueEnableType ENET_HWA_MTL_GetTxQueueEnStatus(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE & ENET_MTL_TXQn_OPERATION_MODE_TXQEN_MASK) >> + ENET_MTL_TXQn_OPERATION_MODE_TXQEN_SHIFT; + return (ENET_MTL_QueueEnableType)u32TmpVal; +} + +/** + * @brief Set the transmit queue enable mode + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] eEnable queue enable mode + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTxQueueEnStatus(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + ENET_MTL_QueueEnableType eEnable) +{ + pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE = (pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE & + (~ENET_MTL_TXQn_OPERATION_MODE_TXQEN_MASK)) | + ENET_MTL_TXQn_OPERATION_MODE_TXQEN(eEnable); +} + +/** + * @brief Get transmit queue store and forward enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true store and forward is enabled + * @return false store and forward is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetTxStoreForwardModeEnFlag(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE & ENET_MTL_TXQn_OPERATION_MODE_TSF_MASK) >> + ENET_MTL_TXQn_OPERATION_MODE_TSF_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set transmit queue store and forward enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTxStoreForwardModeEnFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + bool bEnable) +{ + pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE = (pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE & + (~ENET_MTL_TXQn_OPERATION_MODE_TSF_MASK)) | + ENET_MTL_TXQn_OPERATION_MODE_TSF(bEnable ? 1u : 0u); +} + +/** + * @brief Get transmit queue flush state + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true flush transmit queue is enabled + * @return false flush transmit queue is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetTxFlushState(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE & ENET_MTL_TXQn_OPERATION_MODE_FTQ_MASK) >> + ENET_MTL_TXQn_OPERATION_MODE_FTQ_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Flush transmit queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + */ +LOCAL_INLINE void ENET_HWA_MTL_FlushTxQueue(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MTL.QUEUE[eQueue].TX_OPERATION_MODE |= ENET_MTL_TXQn_OPERATION_MODE_FTQ_MASK; +} + +/** + * @brief Get the underflow counter register of transmit queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [out] pPacketCnt packet counter value + * @retval true Underflow packet counter overflow and rollover happened + * @retval false Underflow packet counter is not overflowed + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetTxUnderflowPacketCount(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + uint16_t *pPacketCnt) +{ + bool bRet; + uint32_t u32TmpVal = pEnet->MTL.QUEUE[eQueue].TX_UNDERFLOW; + *pPacketCnt = (uint16_t)(u32TmpVal & ENET_MTL_TXQn_UNDERFLOW_UFFRMCNT_MASK) >> ENET_MTL_TXQn_UNDERFLOW_UFFRMCNT_SHIFT; + bRet = (((u32TmpVal & ENET_MTL_TXQn_UNDERFLOW_UFCNTOVF_MASK) >> ENET_MTL_TXQn_UNDERFLOW_UFCNTOVF_SHIFT) != 0u) ? + true : false; + return bRet; +} + +/** + * @brief Get transmit queue debug status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint32_t transmit queue debug status register value + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetTxDebugStatus(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + return pEnet->MTL.QUEUE[eQueue].TX_DEBUG; +} + +/** + * @brief Get the current number of status in the transmit Status FIFO of this queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint8_t number of status + */ +LOCAL_INLINE uint8_t ENET_HWA_MTL_GetTxStatusWordCount(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_DEBUG & ENET_MTL_TXQn_DEBUG_STXSTSF_MASK) >> + ENET_MTL_TXQn_DEBUG_STXSTSF_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get the current number of packets in the transmit queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint8_t number of packets + */ +LOCAL_INLINE uint8_t ENET_HWA_MTL_GetTxPacketCount(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_DEBUG & ENET_MTL_TXQn_DEBUG_PTXQ_MASK) >> + ENET_MTL_TXQn_DEBUG_PTXQ_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get the full flag of transmit Status FIFO + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true transmit Status FIFO is full + * @return false transmit Status FIFO is not full + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetTxStatusFIFOFullStatus(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_DEBUG & ENET_MTL_TXQn_DEBUG_TXSTSFSTS_MASK) >> + ENET_MTL_TXQn_DEBUG_TXSTSFSTS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get the not empty flag of transmit queue data + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true transmit queue data is empty + * @return false transmit queue data is not empty + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetTxQueueNotEmptyStatus(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_DEBUG & ENET_MTL_TXQn_DEBUG_TXQSTS_MASK) >> + ENET_MTL_TXQn_DEBUG_TXQSTS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get the transmit queue write controller status,indicates that the MTL Tx Queue Write + controller is active, and it is transferring the data to the transmit queue. + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return ENET_MTL_WriteControllerStatusType + */ +LOCAL_INLINE ENET_MTL_WriteControllerStatusType ENET_HWA_MTL_GetTxQueueWriteControllerStatus(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_DEBUG & ENET_MTL_TXQn_DEBUG_TWCSTS_MASK) >> + ENET_MTL_TXQn_DEBUG_TWCSTS_SHIFT; + return (ENET_MTL_WriteControllerStatusType)u32TmpVal; +} + +/** + * @brief Get the transmit queue read controller status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return ENET_MTL_ReadControllerStatusType + */ +LOCAL_INLINE ENET_MTL_ReadControllerStatusType ENET_HWA_MTL_GetTxQueueReadControllerStatus(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_DEBUG & ENET_MTL_TXQn_DEBUG_TRCSTS_MASK) >> + ENET_MTL_TXQn_DEBUG_TRCSTS_SHIFT; + return (ENET_MTL_ReadControllerStatusType)u32TmpVal; +} + +/** + * @brief Get the transmit queue paused status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true transmit queue is paused + * @return false transmit queue is not paused + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetTxQueuePausedStatus(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_DEBUG & ENET_MTL_TXQn_DEBUG_TXQPAUSED_MASK) >> + ENET_MTL_TXQn_DEBUG_TXQPAUSED_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Enable or disable credit control. + * If credit control is enabled, the credit accumulates even when there is + * no packet waiting in Tx Queue and another Tx Queue is transmitting. + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable 1U enable credit control, 0U disable credit control. + */ +LOCAL_INLINE void ENET_HWA_MTL_SetCreditControlEnFlag(ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue, uint8_t bEnable) +{ + pEnet->MTL.QUEUE[eQueue].TX_ETS_CONTROL = (pEnet->MTL.QUEUE[eQueue].TX_ETS_CONTROL & + (~ENET_MTL_TXQn_ETS_CONTROL_CC_MASK)) | + ENET_MTL_TXQn_ETS_CONTROL_CC(bEnable); +} + +/** + * @brief Set AV algorithm for strict priority or credit based shaper. + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable 1U use credit based shaper or 0U use strict priority. + */ +LOCAL_INLINE void ENET_HWA_MTL_SetAVAlgorithmCBSEnFlag(ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue, uint8_t bEnable) +{ + pEnet->MTL.QUEUE[eQueue].TX_ETS_CONTROL = (pEnet->MTL.QUEUE[eQueue].TX_ETS_CONTROL & + (~ENET_MTL_TXQn_ETS_CONTROL_AVALG_MASK)) | + ENET_MTL_TXQn_ETS_CONTROL_AVALG(bEnable); +} + +/** + * @brief Get the average bits per slot,when the DCB operation is enabled for the queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint32_t average bits per slot + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetSlotAverageBits(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_ETS_STATUS & ENET_MTL_TXQn_ETS_STATUS_ABS_MASK) >> + ENET_MTL_TXQn_ETS_STATUS_ABS_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the quantum or weights for transmit algorithm (DWRR WRR WFQ) + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint32_t quantum or weights + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetTxQueueQuantumOrWeight(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].TX_QUANTUM_WEIGHT & ENET_MTL_TXQn_QUANTUM_WEIGHT_ISCQW_MASK) >> + ENET_MTL_TXQn_QUANTUM_WEIGHT_ISCQW_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set the quantum or weights for transmit algorithm (DWRR WRR WFQ) + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] u32QuantumWeight quantum or weights + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTxQueueQuantumOrWeight(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + uint32_t u32QuantumWeight) +{ + pEnet->MTL.QUEUE[eQueue].TX_QUANTUM_WEIGHT = ENET_MTL_TXQn_QUANTUM_WEIGHT_ISCQW(u32QuantumWeight); +} + +/** + * @brief Set the sendSlope credit value required for the credit-based shaper algorithm for the + * Queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] u32SendSlopeCredit sendSlope credit credit based shaper. + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTxQueueSendSlopeCredit(ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue, uint32_t u32SendSlopeCredit) +{ + pEnet->MTL.QUEUE[eQueue].TX_SENDSLOPECREDIT = + ENET_MTL_TXQn_SENDSLOPECREDIT_SSC(u32SendSlopeCredit); +} + +/** + * @brief Set hiCredit value required for the credit-based shaper algorithm for the Queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] u32hiCredit hiCredit credit based shaper. + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTxQueueHiCredit(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + uint32_t u32hiCredit) +{ + pEnet->MTL.QUEUE[eQueue].TX_HICREDIT = ENET_MTL_TXQn_HICREDIT_HC(u32hiCredit); +} + +/** + * @brief Set the loCredit value required for the credit-based shaper algorithm for the Queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] u32LoCredit loCredit credit based shaper. + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTxQueueLoCredit(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + uint32_t u32LoCredit) +{ + pEnet->MTL.QUEUE[eQueue].TX_LOCREDIT = ENET_MTL_TXQn_LOCREDIT_LC(u32LoCredit); +} + +/** + * @brief Get the interrupt enable and status for the queue interrupts + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint32_t interrupt enable and status + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetInterruptCtrlStatus(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + return pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS; +} + +/** + * @brief Set the interrupt enable and status for the queue interrupts + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] u32CtrlStatus interrupt enable and status + */ +LOCAL_INLINE void ENET_HWA_MTL_SetInterruptCtrlStatus(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + uint32_t u32CtrlStatus) +{ + pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS = u32CtrlStatus; +} + +/** + * @brief Clear all the interrupts of the MTL queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + */ +LOCAL_INLINE void ENET_HWA_MTL_ClearAllIntStatus(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS = pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS; +} + +/** + * @brief Get receive queue overflow interrupt enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true receive queue overflow interrupt is enabled + * @return false receive queue overflow interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetRxQueueOverflowIntEnFlag(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS & + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOIE_MASK) >> + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set receive queue overflow interrupt enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable enable receive queue overflow interrupt + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxQueueOverflowIntEnFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + bool bEnable) +{ + pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS = (pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS & + ~(ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOIE_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK)) | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOIE(bEnable ? 1u : 0u); +} + +/** + * @brief Get receive queue overflow interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true receive queue overflow interrupt detected + * @return false receive queue overflow interrupt not detected + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetRxQueueOverflowIntStatus(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS & + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK) >> + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear receive queue overflow interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + */ +LOCAL_INLINE void ENET_HWA_MTL_ClearRxQueueOverflowIntStatus(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS = (pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS & + ~(ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK)) | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK; +} + +/** + * @brief Get average bits per slot interrupt enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true average bits per slot interrupt is enabled + * @return false average bits per slot interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetSlotAverageBitsIntEnFlag(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS & + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK) >> + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set average bits per slot interrupt enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable enable average bits per slot interrupt + */ +LOCAL_INLINE void ENET_HWA_MTL_SetSlotAverageBitsIntEnFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + bool bEnable) +{ + pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS = (pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS & + ~(ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK)) | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIE(bEnable ? 1u : 0u); +} + +/** + * @brief Get transmit queue underflow interrupt enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @retval true transmit queue underflow interrupt is enabled + * @retval false transmit queue underflow interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetTxQueueUnderflowIntEnFlag(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS & + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUIE_MASK) >> + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set transmit queue underflow interrupt enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable enable transmit queue underflow interrupt + */ +LOCAL_INLINE void ENET_HWA_MTL_SetTxQueueUnderflowIntEnFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + bool bEnable) +{ + pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS = (pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS & + ~(ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUIE_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK)) | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUIE(bEnable ? 1u : 0u); +} + +/** + * @brief Get average bits per slot interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true average bits per slot interrupt detected + * @return false average bits per slot interrupt not detected + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetSlotAverageBitsIntStatus(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS & + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK) >> + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear average bits per slot interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + */ +LOCAL_INLINE void ENET_HWA_MTL_ClearSlotAverageBitsIntStatus(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS = (pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS & + ~(ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK)) | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK; +} + +/** + * @brief Get transmit queue underflow interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true transmit queue underflow interrupt detected + * @return false transmit queue underflow interrupt not detected + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetTxQueueUnderflowIntStatus(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS & + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK) >> + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear transmit queue underflow interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + */ +LOCAL_INLINE void ENET_HWA_MTL_ClearTxQueueUnderflowIntStatus(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS = (pEnet->MTL.QUEUE[eQueue].INTERRUPT_CONTROL_STATUS & + ~(ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK)) | + ENET_MTL_Qn_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK; +} + +/** + * @brief Get receive operation mode of the queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint32_t receive operation mode + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetRxOperationMode(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + return pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE; +} + +/** + * @brief Set receive operation mode of the queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] u32OpMode receive operation mode + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxOperationMode(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, uint32_t u32OpMode) +{ + pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE = u32OpMode; +} + +/** + * @brief Get receive queue size + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint8_t receive queues size in blocks of 256 bytes + */ +LOCAL_INLINE uint8_t ENET_HWA_MTL_GetRxQueueSize(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & ENET_MTL_RXQn_OPERATION_MODE_RQS_MASK) >> + ENET_MTL_RXQn_OPERATION_MODE_RQS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set receive queue size + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] u8QueueSize receive queues size in blocks of 256 bytes, range(0~15) + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxQueueSize(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, uint8_t u8QueueSize) +{ + pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & + (~ENET_MTL_RXQn_OPERATION_MODE_RQS_MASK)) | + ENET_MTL_RXQn_OPERATION_MODE_RQS(u8QueueSize); +} + +/** + * @brief Get the threshold of receive queue at which the flow control is deactivated + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return ENET_MTL_RxFlowCtrlThresholdType flow control deactivating threshold + */ +LOCAL_INLINE ENET_MTL_RxFlowCtrlThresholdType ENET_HWA_MTL_GetRxDeactivateFlowCtrlThres(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & ENET_MTL_RXQn_OPERATION_MODE_RFD_MASK) >> + ENET_MTL_RXQn_OPERATION_MODE_RFD_SHIFT; + return (ENET_MTL_RxFlowCtrlThresholdType)u32TmpVal; +} + +/** + * @brief Set the threshold of receive queue at which the flow control is deactivated + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] eThreshold flow control deactivating threshold + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxDeactivateFlowCtrlThres(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + ENET_MTL_RxFlowCtrlThresholdType eThreshold) +{ + pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & + (~ENET_MTL_RXQn_OPERATION_MODE_RFD_MASK)) | + ENET_MTL_RXQn_OPERATION_MODE_RFD(eThreshold); +} + +/** + * @brief Get the threshold of receive queue at which the flow control is activated + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return ENET_MTL_RxFlowCtrlThresholdType flow control activating threshold + */ +LOCAL_INLINE ENET_MTL_RxFlowCtrlThresholdType ENET_HWA_MTL_GetRxActivateFlowCtrlThres(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & ENET_MTL_RXQn_OPERATION_MODE_RFA_MASK) >> + ENET_MTL_RXQn_OPERATION_MODE_RFA_SHIFT; + return (ENET_MTL_RxFlowCtrlThresholdType)u32TmpVal; +} + +/** + * @brief Set the threshold of receive queue at which the flow control is activated + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] eThreshold flow control activating threshold + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxActivateFlowCtrlThres(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + ENET_MTL_RxFlowCtrlThresholdType eThreshold) +{ + pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & + (~ENET_MTL_RXQn_OPERATION_MODE_RFA_MASK)) | + ENET_MTL_RXQn_OPERATION_MODE_RFA(eThreshold); +} + +/** + * @brief Get receive queue hardware flow control enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true receive queue hardware flow control is enabled + * @return false receive queue hardware flow control is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetRxHwFlowCtrlEnFlag(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & ENET_MTL_RXQn_OPERATION_MODE_EHFC_MASK) >> + ENET_MTL_RXQn_OPERATION_MODE_EHFC_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set receive queue hardware flow control enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable enable hardware flow control + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxHwFlowCtrlEnFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, bool bEnable) +{ + pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & + (~ENET_MTL_RXQn_OPERATION_MODE_EHFC_MASK)) | + ENET_MTL_RXQn_OPERATION_MODE_EHFC(bEnable ? 1u : 0u); +} + +/** + * @brief Get forwarding of TCP/IP checksum error packets enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true forward TCP/IP checksum error packets to application + * @return false drop TCP/IP checksum error packets + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetForwardTCPChecksumErrorPacketEnFlag(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & ENET_MTL_RXQn_OPERATION_MODE_DIS_TCP_EF_MASK) >> + ENET_MTL_RXQn_OPERATION_MODE_DIS_TCP_EF_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set forwarding of TCP/IP checksum error packets enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable forward TCP/IP checksum error packets + */ +LOCAL_INLINE void ENET_HWA_MTL_SetForwardTCPChecksumErrorPacketEnFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + bool bEnable) +{ + pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE = (uint32_t)(pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & + (~ENET_MTL_RXQn_OPERATION_MODE_DIS_TCP_EF_MASK)) | + ENET_MTL_RXQn_OPERATION_MODE_DIS_TCP_EF(bEnable ? 1u : 0u); +} + +/** + * @brief Get receive queue store and forward enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true store and forward is enabled + * @return false store and forward is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetRxStoreForwardModeEnFlag(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & ENET_MTL_RXQn_OPERATION_MODE_RSF_MASK) >> + ENET_MTL_RXQn_OPERATION_MODE_RSF_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set receive queue store and forward enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxStoreForwardModeEnFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + bool bEnable) +{ + pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & + (~ENET_MTL_RXQn_OPERATION_MODE_RSF_MASK)) | + ENET_MTL_RXQn_OPERATION_MODE_RSF(bEnable ? 1u : 0u); +} + +/** + * @brief Get forward error packets enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true forward error packets to application + * @return false drop error packets + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetForwardErrorPacketEnFlag(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & ENET_MTL_RXQn_OPERATION_MODE_FEP_MASK) >> + ENET_MTL_RXQn_OPERATION_MODE_FEP_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set forward error packets enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetForwardErrorPacketEnFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, bool bEnable) +{ + pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & + (~ENET_MTL_RXQn_OPERATION_MODE_FEP_MASK)) | + ENET_MTL_RXQn_OPERATION_MODE_FEP(bEnable ? 1u : 0u); +} + +/** + * @brief Get forward undersized good packets enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true forward undersized good packets to application + * @return false drop undersized good packets + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetForwardUndersizedPacketEnFlag(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & ENET_MTL_RXQn_OPERATION_MODE_FUP_MASK) >> + ENET_MTL_RXQn_OPERATION_MODE_FUP_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set forward undersized good packets enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetForwardUndersizedPacketEnFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + bool bEnable) +{ + pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & + (~ENET_MTL_RXQn_OPERATION_MODE_FUP_MASK)) | + ENET_MTL_RXQn_OPERATION_MODE_FUP(bEnable ? 1u : 0u); +} + +/** + * @brief Get the receive queue threshold control + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return ENET_MTL_RxThresholdType + */ +LOCAL_INLINE ENET_MTL_RxThresholdType ENET_HWA_MTL_GetRxThreshold(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE; + uint32_t u32Thrshold = (u32TmpVal & ENET_MTL_RXQn_OPERATION_MODE_RTC_MASK) >> ENET_MTL_RXQn_OPERATION_MODE_RTC_SHIFT; + return ((u32TmpVal & ENET_MTL_RXQn_OPERATION_MODE_RSF_MASK) == ENET_MTL_RXQn_OPERATION_MODE_RSF_MASK) ? + ENET_MTL_RX_STORE_FORWARD : (ENET_MTL_RxThresholdType)u32Thrshold; +} + +/** + * @brief Set the receive queue threshold + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] eThreshold receive queue threshold + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxThreshold(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + ENET_MTL_RxThresholdType eThreshold) +{ + pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE = (pEnet->MTL.QUEUE[eQueue].RX_OPERATION_MODE & + ~(ENET_MTL_RXQn_OPERATION_MODE_RTC_MASK | ENET_MTL_RXQn_OPERATION_MODE_RSF_MASK)) | + (ENET_MTL_RXQn_OPERATION_MODE_RTC(eThreshold) | + ENET_MTL_RXQn_OPERATION_MODE_RSF((uint32_t)eThreshold >> ENET_MTL_RXQn_OPERATION_MODE_RTC_WIDTH)); +} + +/** + * @brief Get the missed packet and overflow counters of the queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [out] pMissedPacketCntOverflowFlag missed packet counter overflow detected + * @param [out] pMissedPacketCnt missed pPacket counter + * @param [out] pOverflowPacketCntOverflowFlag overflow packet counter overflow detected + * @param [out] pOverflowPacketCnt overflow packet counter + */ +LOCAL_INLINE void ENET_HWA_MTL_GetRxMissedPacketOverflowCount(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + bool *pMissedPacketCntOverflowFlag, uint16_t *pMissedPacketCnt, + bool *pOverflowPacketCntOverflowFlag, uint16_t *pOverflowPacketCnt) +{ + uint32_t u32TmpVal = pEnet->MTL.QUEUE[eQueue].RX_MISSED_PACKET_OVERFLOW_CNT; + *pMissedPacketCntOverflowFlag = ((u32TmpVal & ENET_MTL_RXQn_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK) == + ENET_MTL_RXQn_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK) ? true : false; + *pMissedPacketCnt = (uint16_t)((u32TmpVal & ENET_MTL_RXQn_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK) >> + ENET_MTL_RXQn_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT); + *pOverflowPacketCntOverflowFlag = ((u32TmpVal & ENET_MTL_RXQn_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK) == + ENET_MTL_RXQn_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK) ? true : false; + *pOverflowPacketCnt = (uint16_t)((u32TmpVal & ENET_MTL_RXQn_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK) >> + ENET_MTL_RXQn_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT); +} + +/** + * @brief Get the receive queue debug status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint32_t receive queue debug status + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetRxDebugStatus(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + return pEnet->MTL.QUEUE[eQueue].RX_DEBUG; +} + +/** + * @brief Get the number of packets in receive queue + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint8_t packets number + */ +LOCAL_INLINE uint8_t ENET_HWA_MTL_GetRxPacketCount(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_DEBUG & ENET_MTL_RXQn_DEBUG_PRXQ_MASK) >> + ENET_MTL_RXQn_DEBUG_PRXQ_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get receive queue Fill-Level status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return ENET_MTL_RxQueueStatusType (empty,below flow-control deactivate threshold,above flow-control activate threshold,full) + */ +LOCAL_INLINE ENET_MTL_RxQueueStatusType ENET_HWA_MTL_GetRxFillLevelStatus(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_DEBUG & ENET_MTL_RXQn_DEBUG_RXQSTS_MASK) >> + ENET_MTL_RXQn_DEBUG_RXQSTS_SHIFT; + return (ENET_MTL_RxQueueStatusType)u32TmpVal; +} + +/** + * @brief Get receive queue read controller state + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return ENET_MTL_ReadControllerStatusType + */ +LOCAL_INLINE ENET_MTL_ReadControllerStatusType ENET_HWA_MTL_GetRxQueueReadControllerStatus(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_DEBUG & ENET_MTL_RXQn_DEBUG_RRCSTS_MASK) >> + ENET_MTL_RXQn_DEBUG_RRCSTS_SHIFT; + return (ENET_MTL_ReadControllerStatusType)u32TmpVal; +} + +/** + * @brief Get receive queue write controller state + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return ENET_MTL_WriteControllerStatusType + */ +LOCAL_INLINE ENET_MTL_WriteControllerStatusType ENET_HWA_MTL_GetRxQueueWriteControllerStatus(const ENET_Type *const pEnet, + ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_DEBUG & ENET_MTL_RXQn_DEBUG_RWCSTS_MASK) >> + ENET_MTL_RXQn_DEBUG_RWCSTS_SHIFT; + return (ENET_MTL_WriteControllerStatusType)u32TmpVal; +} + +/** + * @brief Get MTL queue receive control register value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint32_t receive control value + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetRxControl(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + return pEnet->MTL.QUEUE[eQueue].RX_CONTROL; +} + +/** + * @brief Set MTL queue receive control register value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] u32Ctrl receive control value + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxControl(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, uint32_t u32Ctrl) +{ + pEnet->MTL.QUEUE[eQueue].RX_CONTROL = u32Ctrl; +} + +/** + * @brief Get receive queue packet arbitration enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return true receive queue packet arbitration is enabled + * @return false receive queue packet arbitration is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetRxQueuePacketArbitrationEnFlag(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_CONTROL & ENET_MTL_RXQn_CONTROL_RXQ_FRM_ARBIT_MASK) >> + ENET_MTL_RXQn_CONTROL_RXQ_FRM_ARBIT_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set receive queue packet arbitration enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] bEnable enable or disable + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxQueuePacketArbitrationEnFlag(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, + bool bEnable) +{ + pEnet->MTL.QUEUE[eQueue].RX_CONTROL = (pEnet->MTL.QUEUE[eQueue].RX_CONTROL & ~ENET_MTL_RXQn_CONTROL_RXQ_FRM_ARBIT_MASK) | + ENET_MTL_RXQn_CONTROL_RXQ_FRM_ARBIT(bEnable ? 1u : 0u); +} + +/** + * @brief Get receive queue weight + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @return uint8_t receive queue weight + */ +LOCAL_INLINE uint8_t ENET_HWA_MTL_GetRxQueueWeight(const ENET_Type *const pEnet, ENET_MTL_QueueType eQueue) +{ + uint32_t u32TmpVal = (pEnet->MTL.QUEUE[eQueue].RX_CONTROL & ENET_MTL_RXQn_CONTROL_RXQ_WEGT_MASK) >> + ENET_MTL_RXQn_CONTROL_RXQ_WEGT_SHIFT; + return (uint8_t)(u32TmpVal + 1u); +} + +/** + * @brief Set receive queue weight + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eQueue MTL queue id + * @param [in] u8Weight receive queue weight + */ +LOCAL_INLINE void ENET_HWA_MTL_SetRxQueueWeight(ENET_Type *const pEnet, ENET_MTL_QueueType eQueue, uint8_t u8Weight) +{ + pEnet->MTL.QUEUE[eQueue].RX_CONTROL = (pEnet->MTL.QUEUE[eQueue].RX_CONTROL & ~ENET_MTL_RXQn_CONTROL_RXQ_WEGT_MASK) | + ENET_MTL_RXQn_CONTROL_RXQ_WEGT((uint32_t)u8Weight - 1u); +} + +/* ================================================================ * + * ENET DMA Configuration and Status * + * ================================================================ */ + +/** + * @brief Get DMA bus mode register value + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t DMA bus mode register value + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetMode(const ENET_Type *const pEnet) +{ + return pEnet->ENET_DMA.MODE; +} + +/** + * @brief Set DMA bus mode register value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] u32Mode DMA bus mode value + */ +LOCAL_INLINE void ENET_HWA_DMA_SetMode(ENET_Type *const pEnet, uint32_t u32Mode) +{ + pEnet->ENET_DMA.MODE = u32Mode; +} + +/** + * @brief Get DMA software reset status + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_DMA_StatusType + */ +LOCAL_INLINE ENET_DMA_StatusType ENET_HWA_DMA_GetSwResetStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.MODE & ENET_DMA_MODE_SWR_MASK) >> ENET_DMA_MODE_SWR_SHIFT; + return (ENET_DMA_StatusType)u32TmpVal; +} + +/** + * @brief Initiate DMA software reset + + * @param [in] pEnet the base address of the ENET instance + */ +LOCAL_INLINE void ENET_HWA_DMA_SwReset(ENET_Type *const pEnet) +{ + pEnet->ENET_DMA.MODE |= ENET_DMA_MODE_SWR_MASK; +} + +/** + * @brief Get DMA interrupt mode + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_DMA_IntModeType + */ +LOCAL_INLINE ENET_DMA_IntModeType ENET_HWA_DMA_GetInterruptMode(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.MODE & ENET_DMA_MODE_INTM_MASK) >> ENET_DMA_MODE_INTM_SHIFT; + return (ENET_DMA_IntModeType)u32TmpVal; +} + +/** + * @brief Set DMA interrupt mode + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eIntMode DMA interrupt mode + */ +LOCAL_INLINE void ENET_HWA_DMA_SetInterruptMode(ENET_Type *const pEnet, ENET_DMA_IntModeType eIntMode) +{ + pEnet->ENET_DMA.MODE = (pEnet->ENET_DMA.MODE & ~ENET_DMA_MODE_INTM_MASK) | ENET_DMA_MODE_INTM(eIntMode); +} + +/** + * @brief Get DMA Rx:Tx or Tx:Rx priority ratio + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_DMA_PriorityRatioType + */ +LOCAL_INLINE ENET_DMA_PriorityRatioType ENET_HWA_DMA_GetPriorityRatio(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.MODE & ENET_DMA_MODE_PR_MASK) >> ENET_DMA_MODE_PR_SHIFT; + return (ENET_DMA_PriorityRatioType)u32TmpVal; +} + +/** + * @brief Set DMA Rx:Tx or Tx:Rx priority ratio + + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePriorityRatio priority ratio + */ +LOCAL_INLINE void ENET_HWA_DMA_SetPriorityRatio(ENET_Type *const pEnet, ENET_DMA_PriorityRatioType ePriorityRatio) +{ + pEnet->ENET_DMA.MODE = (pEnet->ENET_DMA.MODE & ~ENET_DMA_MODE_PR_MASK) | ENET_DMA_MODE_PR(ePriorityRatio); +} + +/** + * @brief Get DMA priority mode + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_DMA_PRIORITY_MODE_RX_TX the priority ratio is RX:TX + * @return ENET_DMA_PRIORITY_MODE_TX_RX the priority ratio is TX:RX + */ +LOCAL_INLINE ENET_DMA_PriorityModeType ENET_HWA_DMA_GetPriorityMode(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.MODE & ENET_DMA_MODE_TXPR_MASK) >> ENET_DMA_MODE_TXPR_SHIFT; + return (ENET_DMA_PriorityModeType)u32TmpVal; +} + +/** + * @brief Set DMA priority mode,Rx:Tx or Tx:Rx + + * @param [in] pEnet the base address of the ENET instance + * @param [in] ePriorityMode priority mode + */ +LOCAL_INLINE void ENET_HWA_DMA_SetPriorityMode(ENET_Type *const pEnet, ENET_DMA_PriorityModeType ePriorityMode) +{ + pEnet->ENET_DMA.MODE = (pEnet->ENET_DMA.MODE & ~ENET_DMA_MODE_TXPR_MASK) | ENET_DMA_MODE_TXPR(ePriorityMode); +} + +/** + * @brief Get DMA arbitration algorithm between transmit channels + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_DMA_TxArbitrationAlgorithmType + */ +LOCAL_INLINE ENET_DMA_TxArbitrationAlgorithmType ENET_HWA_DMA_GetTxArbitrationAlgorithm(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.MODE & ENET_DMA_MODE_TAA_MASK) >> ENET_DMA_MODE_TAA_SHIFT; + return (ENET_DMA_TxArbitrationAlgorithmType)u32TmpVal; +} + +/** + * @brief Set DMA arbitration algorithm between transmit channels + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eArbitrationAlgorithm DMA arbitration algorithm + */ +LOCAL_INLINE void ENET_HWA_DMA_SetTxArbitrationAlgorithm(ENET_Type *const pEnet, ENET_DMA_TxArbitrationAlgorithmType eArbitrationAlgorithm) +{ + pEnet->ENET_DMA.MODE = (pEnet->ENET_DMA.MODE & ~ENET_DMA_MODE_TAA_MASK) | ENET_DMA_MODE_TAA(eArbitrationAlgorithm); +} + +/** + * @brief Get DMA arbitration scheme between the transmit and receive paths + + * @param [in] pEnet the base address of the ENET instance + * @return ENET_DMA_ArbitrationSchemeType + */ +LOCAL_INLINE ENET_DMA_ArbitrationSchemeType ENET_HWA_DMA_GetTxRxArbitrationScheme(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.MODE & ENET_DMA_MODE_DA_MASK) >> ENET_DMA_MODE_DA_SHIFT; + return (ENET_DMA_ArbitrationSchemeType)u32TmpVal; +} + +/** + * @brief Set DMA arbitration scheme between the transmit and receive paths + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eArbitrationScheme DMA arbitration algorithm + */ +LOCAL_INLINE void ENET_HWA_DMA_SetTxRxArbitrationScheme(ENET_Type *const pEnet, ENET_DMA_ArbitrationSchemeType eArbitrationScheme) +{ + pEnet->ENET_DMA.MODE = (pEnet->ENET_DMA.MODE & ~ENET_DMA_MODE_DA_MASK) | ENET_DMA_MODE_DA(eArbitrationScheme); +} + +/** + * @brief Get DMA rebuild INCRx burst enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true rebuild INCRx burst is enabled + * @return false rebuild INCRx burst is disabled + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetRebuildINCRxBurstEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.SYSBUS_MODE & ENET_DMA_SYSBUS_MODE_RB_MASK) >> ENET_DMA_SYSBUS_MODE_RB_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set DMA rebuild INCRx burst enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_DMA_SetRebuildINCRxBurstEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->ENET_DMA.SYSBUS_MODE = (pEnet->ENET_DMA.SYSBUS_MODE & ~ENET_DMA_SYSBUS_MODE_RB_MASK) | + ENET_DMA_SYSBUS_MODE_RB(bEnable ? 1u : 0u); +} + +/** + * @brief Get DMA mixed burst length enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true mixed burst is enabled + * @return false mixed burst is disabled + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetMixedBurstEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.SYSBUS_MODE & ENET_DMA_SYSBUS_MODE_MB_MASK) >> ENET_DMA_SYSBUS_MODE_MB_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set DMA mixed burst length enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_DMA_SetMixedBurstEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->ENET_DMA.SYSBUS_MODE = (pEnet->ENET_DMA.SYSBUS_MODE & ~ENET_DMA_SYSBUS_MODE_MB_MASK) | + ENET_DMA_SYSBUS_MODE_MB(bEnable ? 1u : 0u); +} + +/** + * @brief Get DMA Address-Aligned Beats enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true Address-Aligned Beats is enabled + * @return false Address-Aligned Beats is disabled + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetAddressAlignedBeatsEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.SYSBUS_MODE & ENET_DMA_SYSBUS_MODE_AAL_MASK) >> ENET_DMA_SYSBUS_MODE_AAL_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set DMA Address-Aligned Beats enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_DMA_SetAddressAlignedBeatsEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->ENET_DMA.SYSBUS_MODE = (pEnet->ENET_DMA.SYSBUS_MODE & ~ENET_DMA_SYSBUS_MODE_AAL_MASK) | + ENET_DMA_SYSBUS_MODE_AAL(bEnable ? 1u : 0u); +} + +/** + * @brief Get DMA fixed burst length enable flag + + * @param [in] pEnet the base address of the ENET instance + * @return true fixed burst length is enabled + * @return false fixed burst length is disabled + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetFixedBurstLengthEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.SYSBUS_MODE & ENET_DMA_SYSBUS_MODE_FB_MASK) >> ENET_DMA_SYSBUS_MODE_FB_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set DMA fixed burst length enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_DMA_SetFixedBurstLengthEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->ENET_DMA.SYSBUS_MODE = (pEnet->ENET_DMA.SYSBUS_MODE & ~ENET_DMA_SYSBUS_MODE_FB_MASK) | + ENET_DMA_SYSBUS_MODE_FB(bEnable ? 1u : 0u); +} + +/** + * @brief Get DMA interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t DMA interrupt status value + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetDMAIntStatus(const ENET_Type *const pEnet) +{ + return pEnet->ENET_DMA.INTERRUPT_STATUS; +} + +/** + * @brief Get MAC interrupt event in DMA interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @return true MAC interrupt event detected + * @return false MAC interrupt event not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetMACIntStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.INTERRUPT_STATUS & ENET_DMA_INTERRUPT_STATUS_MACIS_MASK) >> + ENET_DMA_INTERRUPT_STATUS_MACIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get MTL interrupt event in DMA interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @return true MTL interrupt event detected + * @return false MTL interrupt event not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetMTLIntStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.INTERRUPT_STATUS & ENET_DMA_INTERRUPT_STATUS_MTLIS_MASK) >> + ENET_DMA_INTERRUPT_STATUS_MTLIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get DMA channel0 interrupt event in DMA interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @return true DMA channel0 interrupt event detected + * @return false DMA channel0 interrupt event not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetDMAChannel0IntStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.INTERRUPT_STATUS & ENET_DMA_INTERRUPT_STATUS_DC0IS_MASK) >> + ENET_DMA_INTERRUPT_STATUS_DC0IS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get DMA channel1 interrupt event in DMA interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @return true DMA channel1 interrupt event detected + * @return false DMA channel1 interrupt event not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetDMAChannel1IntStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.INTERRUPT_STATUS & ENET_DMA_INTERRUPT_STATUS_DC1IS_MASK) >> + ENET_DMA_INTERRUPT_STATUS_DC1IS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get DMA channel interrupt event in DMA interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eChannel DMA channel + * @return true eChannel interrupt event detected + * @return false eChannel interrupt event not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetDMAChannelIntStatus(const ENET_Type *const pEnet, ENET_DMA_ChannelType eChannel) +{ + uint32_t u32TmpVal = pEnet->ENET_DMA.INTERRUPT_STATUS & ((uint32_t)1u << (uint32_t)eChannel); + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Get AXI Master Read Channel Status + + * @param [in] pEnet the base address of the ENET instance + * @return true AXI Master Read Channel detected + * @return false AXI Master Read Channel not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetAHBMasterBusyStatus(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.DEBUG_STATUS0 & ENET_DMA_DEBUG_STATUS0_AXWHSTS_MASK) >> + ENET_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +#if ENET_SUPPORT_TIME_SENSITIVE_NETWORK +/** + * @brief Get DMA TBS fetch time offset + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eCtrlIndex DMA TBS control index + * @return uint32_t DMA TBS fetch time offset + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetFetchTimeOffset(const ENET_Type *const pEnet, uint8_t eCtrlIndex) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.TBS_CTRL[eCtrlIndex] & ENET_DMA_TBS_CTRL_FTOS_MASK) >> ENET_DMA_TBS_CTRL_FTOS_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set DMA TBS fetch time offset + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eCtrlIndex DMA TBS control index + * @param [in] u32FetchTimeOffset DMA TBS fetch time offset + */ +LOCAL_INLINE void ENET_HWA_DMA_SetFetchTimeOffset(ENET_Type *const pEnet, uint8_t eCtrlIndex, uint32_t u32FetchTimeOffset) +{ + pEnet->ENET_DMA.TBS_CTRL[eCtrlIndex] = (pEnet->ENET_DMA.TBS_CTRL[eCtrlIndex] & ~ENET_DMA_TBS_CTRL_FTOS_MASK) | + ENET_DMA_TBS_CTRL_FTOS(u32FetchTimeOffset); +} + +/** + * @brief Get DMA TBS fetch time offset valid + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eCtrlIndex DMA TBS control index + * @return true TBS fetch time offset is valid + * @return false TBS fetch time offset is invalid + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetFetchTimeOffsetValid(const ENET_Type *const pEnet, uint8_t eCtrlIndex) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.TBS_CTRL[eCtrlIndex] & ENET_DMA_TBS_CTRL_FTOV_MASK) >> ENET_DMA_TBS_CTRL_FTOV_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set DMA TBS fetch time offset valid + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eCtrlIndex DMA TBS control index + * @param [in] bEnable set valid + */ +LOCAL_INLINE void ENET_HWA_DMA_SetFetchTimeOffsetValid(ENET_Type *const pEnet, uint8_t eCtrlIndex, bool bEnable) +{ + pEnet->ENET_DMA.TBS_CTRL[eCtrlIndex] = (pEnet->ENET_DMA.TBS_CTRL[eCtrlIndex] & ~ENET_DMA_TBS_CTRL_FTOV_MASK) | + ENET_DMA_TBS_CTRL_FTOV(bEnable ? 1u : 0u); +} +#endif /* ENET_SUPPORT_TIME_SENSITIVE_NETWORK */ + +/** + * @brief Get DMA channel control register value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t register value + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetChannelCtrl(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].CONTROL; +} + +/** + * @brief Set DMA channel control register value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u32ChannelCtrl control value + */ +LOCAL_INLINE void ENET_HWA_DMA_SetChannelCtrl(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint32_t u32ChannelCtrl) +{ + pEnet->ENET_DMA.CH[eDMAChannel].CONTROL = u32ChannelCtrl; +} + +/** + * @brief Get DMA descriptor skip length + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint8_t descriptor skip length + */ +LOCAL_INLINE uint8_t ENET_HWA_DMA_GetDescriptorSkipLength(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].CONTROL & ENET_DMA_CHn_CONTROL_DSL_MASK) >> + ENET_DMA_CHn_CONTROL_DSL_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set DMA descriptor skip length + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u8Length descriptor skip length + */ +LOCAL_INLINE void ENET_HWA_DMA_SetDescriptorSkipLength(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint8_t u8Length) +{ + pEnet->ENET_DMA.CH[eDMAChannel].CONTROL = (pEnet->ENET_DMA.CH[eDMAChannel].CONTROL & ~ENET_DMA_CHn_CONTROL_DSL_MASK) | + ENET_DMA_CHn_CONTROL_DSL(u8Length); +} + +/** + * @brief Get DMA burst length multiply by 8 mode + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true DMA Tx and Rx burst length is multipled by 8 + * @return false use DMA Tx and Rx burst length + */ +LOCAL_INLINE bool ENET_HWA_DMA_Get8xPBLModeEnFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].CONTROL & ENET_DMA_CHn_CONTROL_PBLX8_MASK) >> + ENET_DMA_CHn_CONTROL_PBLX8_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set DMA burst length multiply by 8 mode + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] bEnable enable x8 mode + */ +LOCAL_INLINE void ENET_HWA_DMA_Set8xPBLModeEnFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + bool bEnable) +{ + pEnet->ENET_DMA.CH[eDMAChannel].CONTROL = (pEnet->ENET_DMA.CH[eDMAChannel].CONTROL & ~ENET_DMA_CHn_CONTROL_PBLX8_MASK) | + ENET_DMA_CHn_CONTROL_PBLX8(bEnable ? 1u : 0u); +} + +/** + * @brief Get DMA transmit channel control register value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t register value + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetChannelTxCtrl(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL; +} + +/** + * @brief Set DMA transmit channel control register value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u32TxCtrl control value + */ +LOCAL_INLINE void ENET_HWA_DMA_SetChannelTxCtrl(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint32_t u32TxCtrl) +{ + pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL = u32TxCtrl; +} + +/** + * @brief Get DMA enhanced descriptor enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true enhanced descriptor is enabled + * @return false enhanced descriptor is disabled + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetEnhancedDescriptorEnFlag(const ENET_Type *const pEnet, + ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL & ENET_DMA_CHn_TX_CONTROL_EDSE_MASK) >> + ENET_DMA_CHn_TX_CONTROL_EDSE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set DMA enhanced descriptor enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_DMA_SetEnhancedDescriptorEnFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + bool bEnable) +{ + pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL = (pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL & + (~ENET_DMA_CHn_TX_CONTROL_EDSE_MASK)) | + ENET_DMA_CHn_TX_CONTROL_EDSE(bEnable ? 1u : 0u); +} + +/** + * @brief Get DMA early transmit interrupt enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true early transmit interrupt is enabled + * @return false early transmit interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetEarlyTxIntEnFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL & ENET_DMA_CHn_TX_CONTROL_ETIC_MASK) >> + ENET_DMA_CHn_TX_CONTROL_ETIC_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set DMA early transmit interrupt enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_DMA_SetEarlyTxIntEnFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + bool bEnable) +{ + pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL = (pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL & + (~ENET_DMA_CHn_TX_CONTROL_ETIC_MASK)) | + ENET_DMA_CHn_TX_CONTROL_ETIC(bEnable ? 1u : 0u); +} + +/** + * @brief Get DMA transmit programmable burst length + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint8_t transmit burst length + */ +LOCAL_INLINE uint8_t ENET_HWA_DMA_GetTxBurstLength(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL & ENET_DMA_CHn_TX_CONTROL_TXPBL_MASK) >> + ENET_DMA_CHn_TX_CONTROL_TXPBL_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set DMA transmit programmable burst length + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u8Length transmit burst length + */ +LOCAL_INLINE void ENET_HWA_DMA_SetTxBurstLength(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, uint8_t u8Length) +{ + pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL = (pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL & + (~ENET_DMA_CHn_TX_CONTROL_TXPBL_MASK)) | + ENET_DMA_CHn_TX_CONTROL_TXPBL(u8Length); +} + +/** + * @brief Get DMA operate on second packet enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true operate on second packet is enabled + * @return false operate on second packet is disabled + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetOperateOnSecondPacketEnFlag(const ENET_Type *const pEnet, + ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL & ENET_DMA_CHn_TX_CONTROL_OSF_MASK) >> + ENET_DMA_CHn_TX_CONTROL_OSF_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set DMA operate on second packet enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_DMA_SetOperateOnSecondPacketEnFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + bool bEnable) +{ + pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL = (pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL & + (~ENET_DMA_CHn_TX_CONTROL_OSF_MASK)) | + ENET_DMA_CHn_TX_CONTROL_OSF(bEnable ? 1u : 0u); +} + +/** + * @brief Get DMA transmit channel weight + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint8_t transmit channel weight + */ +LOCAL_INLINE uint8_t ENET_HWA_DMA_GetTxChannelWeight(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL & ENET_DMA_CHn_TX_CONTROL_TCW_MASK) >> + ENET_DMA_CHn_TX_CONTROL_TCW_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set DMA transmit channel weight + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u8Weight transmit channel weight + */ +LOCAL_INLINE void ENET_HWA_DMA_SetTxChannelWeight(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint8_t u8Weight) +{ + pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL = (pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL & + (~ENET_DMA_CHn_TX_CONTROL_TCW_MASK)) | + ENET_DMA_CHn_TX_CONTROL_TCW(u8Weight); +} + +/** + * @brief Get DMA transmit channel active status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return ENET_DMA_STATUS_IDLE DMA transmission is stopped + * @return ENET_DMA_STATUS_ACTIVE DMA transmission is running + */ +LOCAL_INLINE ENET_DMA_StatusType ENET_HWA_DMA_GetTxActiveStatus(const ENET_Type *const pEnet, + ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL & ENET_DMA_CHn_TX_CONTROL_ST_MASK) >> + ENET_DMA_CHn_TX_CONTROL_ST_SHIFT; + return (ENET_DMA_StatusType)u32TmpVal; +} + +/** + * @brief Start DMA transmission + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_StartTx(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL |= ENET_DMA_CHn_TX_CONTROL_ST_MASK; +} + +/** + * @brief Stop DMA transmission + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_StopTx(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].TX_CONTROL &= ~ENET_DMA_CHn_TX_CONTROL_ST_MASK; +} + +/** + * @brief Get DMA receive channel control register value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t register value + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetChannelRxCtrl(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL; +} + +/** + * @brief Set DMA receive channel control register value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u32RxCtrl control value + */ +LOCAL_INLINE void ENET_HWA_DMA_SetChannelRxCtrl(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint32_t u32RxCtrl) +{ + pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL = u32RxCtrl; +} + +/** + * @brief Get DMA receive packet flush enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true Rx packet flush is enabled + * @return false Rx packet flush is disabled + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetRxPacketFlushEnFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL & ENET_DMA_CHn_RX_CONTROL_RPF_MASK) >> + ENET_DMA_CHn_RX_CONTROL_RPF_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set DMA receive packet flush enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_DMA_SetRxPacketFlushEnFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + bool bEnable) +{ + pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL = (pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL & + (~ENET_DMA_CHn_RX_CONTROL_RPF_MASK)) | + ENET_DMA_CHn_RX_CONTROL_RPF(bEnable ? 1u : 0u); +} + +/** + * @brief Get DMA early receive interrupt enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true early receive interrupt is enabled + * @return false early receive interrupt is disabled + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetEarlyRxIntEnFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL & ENET_DMA_CHn_RX_CONTROL_ERIC_MASK) >> + ENET_DMA_CHn_RX_CONTROL_ERIC_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set DMA early receive interrupt enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_DMA_SetEarlyRxIntEnFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + bool bEnable) +{ + pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL = (pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL & + (~ENET_DMA_CHn_RX_CONTROL_ERIC_MASK)) | + ENET_DMA_CHn_RX_CONTROL_ERIC(bEnable ? 1u : 0u); +} + +/** + * @brief Get DMA receive programmable burst length + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint8_t receive burst length + */ +LOCAL_INLINE uint8_t ENET_HWA_DMA_GetRxBurstLength(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL & ENET_DMA_CHn_RX_CONTROL_RXPBL_MASK) >> + ENET_DMA_CHn_RX_CONTROL_RXPBL_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set DMA receive programmable burst length + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u8Length receive burst length + */ +LOCAL_INLINE void ENET_HWA_DMA_SetRxBurstLength(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, uint8_t u8Length) +{ + pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL = (pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL & + (~ENET_DMA_CHn_RX_CONTROL_RXPBL_MASK)) | + ENET_DMA_CHn_RX_CONTROL_RXPBL(u8Length); +} + +/** + * @brief Get DMA receive buffer size + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint16_t receive buffer size + */ +LOCAL_INLINE uint16_t ENET_HWA_DMA_GetRxBufferSize(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL & + (ENET_DMA_CHn_RX_CONTROL_RBSZ_13_Y_MASK | ENET_DMA_CHn_RX_CONTROL_RBSZ_X_0_MASK)) >> + ENET_DMA_CHn_RX_CONTROL_RBSZ_X_0_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set DMA receive buffer size + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u16BufferSize receive buffer size + */ +LOCAL_INLINE void ENET_HWA_DMA_SetRxBufferSize(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint16_t u16BufferSize) +{ + pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL = (pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL & + (~ENET_DMA_CHn_RX_CONTROL_RBSZ_13_Y_MASK)) | + ENET_DMA_CHn_RX_CONTROL_RBSZ_13_Y(((uint32_t)u16BufferSize >> + (ENET_DMA_CHn_RX_CONTROL_RBSZ_13_Y_SHIFT - + ENET_DMA_CHn_RX_CONTROL_RBSZ_X_0_SHIFT))); +} + +/** + * @brief Get DMA receive channel active status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return ENET_DMA_STATUS_IDLE DMA reception is stopped + * @return ENET_DMA_STATUS_ACTIVE DMA reception is running + */ +LOCAL_INLINE ENET_DMA_StatusType ENET_HWA_DMA_GetRxActiveStatus(const ENET_Type *const pEnet, + ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL & ENET_DMA_CHn_RX_CONTROL_SR_MASK) >> + ENET_DMA_CHn_RX_CONTROL_SR_SHIFT; + return (ENET_DMA_StatusType)u32TmpVal; +} + +/** + * @brief Start DMA reception + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_StartRx(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL |= ENET_DMA_CHn_RX_CONTROL_SR_MASK; +} + +/** + * @brief Stop DMA reception + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_StopRx(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL &= ~ENET_DMA_CHn_RX_CONTROL_SR_MASK; +} + +/** + * @brief Get DMA channel Tx descriptor list header address + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t Tx descriptor list header address + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetTxDescListHeadAddr(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].TXDESC_LIST_ADDRESS; +} + +/** + * @brief Set DMA channel Tx descriptor list header address + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u32TxAddr Tx descriptor list header address + */ +LOCAL_INLINE void ENET_HWA_DMA_SetTxDescListHeadAddr(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint32_t u32TxAddr) +{ + pEnet->ENET_DMA.CH[eDMAChannel].TXDESC_LIST_ADDRESS = + ENET_DMA_CHn_TXDESC_LIST_ADDRESS_TDESLA(u32TxAddr >> ENET_DMA_CHn_TXDESC_LIST_ADDRESS_TDESLA_SHIFT); +} + +/** + * @brief Get DMA channel Rx descriptor list header address + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t Rx descriptor list header address + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetRxDescListHeadAddr(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].RXDESC_LIST_ADDRESS; +} + +/** + * @brief Set DMA channel Rx descriptor list header address + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u32RxAddr Rx descriptor list header address + */ +LOCAL_INLINE void ENET_HWA_DMA_SetRxDescListHeadAddr(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint32_t u32RxAddr) +{ + pEnet->ENET_DMA.CH[eDMAChannel].RXDESC_LIST_ADDRESS = + ENET_DMA_CHn_RXDESC_LIST_ADDRESS_RDESLA(u32RxAddr >> ENET_DMA_CHn_RXDESC_LIST_ADDRESS_RDESLA_SHIFT); +} + +/** + * @brief Get DMA channel Tx descriptor list tail address + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t Tx descriptor list tail address + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetTxDescListTailAddr(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].TXDESC_TAIL_POINTER; +} + +/** + * @brief Set DMA channel Tx descriptor list tail address + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u32TxAddr Tx descriptor list tail address + */ +LOCAL_INLINE void ENET_HWA_DMA_SetTxDescListTailAddr(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint32_t u32TxAddr) +{ + pEnet->ENET_DMA.CH[eDMAChannel].TXDESC_TAIL_POINTER = + ENET_DMA_CHn_TXDESC_TAIL_POINTER_TDTP(u32TxAddr >> ENET_DMA_CHn_TXDESC_TAIL_POINTER_TDTP_SHIFT); +} + +/** + * @brief Get DMA channel Rx descriptor list tail address + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t Rx descriptor list tail address + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetRxDescListTailAddr(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].RXDESC_TAIL_POINTER; +} + +/** + * @brief Set DMA channel Rx descriptor list tail address + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u32RxAddr Rx descriptor list tail address + */ +LOCAL_INLINE void ENET_HWA_DMA_SetRxDescListTailAddr(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint32_t u32RxAddr) +{ + pEnet->ENET_DMA.CH[eDMAChannel].RXDESC_TAIL_POINTER = + ENET_DMA_CHn_RXDESC_TAIL_POINTER_RDTP(u32RxAddr >> ENET_DMA_CHn_RXDESC_TAIL_POINTER_RDTP_SHIFT); +} + +/** + * @brief Get DMA channel Tx descriptor ring length + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint16_t Tx descriptor ring length + */ +LOCAL_INLINE uint16_t ENET_HWA_DMA_GetTxDescRingLength(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].TXDESC_RING_LENGTH & ENET_DMA_CHn_TXDESC_RING_LENGTH_TDRL_MASK) >> + ENET_DMA_CHn_TXDESC_RING_LENGTH_TDRL_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set DMA channel Tx descriptor ring length + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u16Length Tx descriptor ring length + */ +LOCAL_INLINE void ENET_HWA_DMA_SetTxDescRingLength(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint16_t u16Length) +{ + pEnet->ENET_DMA.CH[eDMAChannel].TXDESC_RING_LENGTH = ENET_DMA_CHn_TXDESC_RING_LENGTH_TDRL(u16Length); +} + +/** + * @brief Get DMA channel Rx descriptor ring length + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t Rx descriptor ring length + */ +LOCAL_INLINE uint16_t ENET_HWA_DMA_GetRxDescRingLength(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL2 & ENET_DMA_CHn_RX_CONTROL2_RDRL_MASK) >> + ENET_DMA_CHn_RX_CONTROL2_RDRL_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set DMA channel Rx descriptor ring length + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u16Length Rx descriptor ring length + */ +LOCAL_INLINE void ENET_HWA_DMA_SetRxDescRingLength(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint16_t u16Length) +{ + pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL2 = (pEnet->ENET_DMA.CH[eDMAChannel].RX_CONTROL2 & + (~ENET_DMA_CHn_RX_CONTROL2_RDRL_MASK)) | + ENET_DMA_CHn_RX_CONTROL2_RDRL(u16Length); +} + +/** + * @brief Get DMA channel enabled interrupts + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t enabled interrupts + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetEnabledInterrupts(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].INTERRUPT_ENABLE; +} + +/** + * @brief Set DMA channel interrupts enable state + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u32IntEnable interrupts to be enabled + */ +LOCAL_INLINE void ENET_HWA_DMA_SetEnabledInterrupts(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint32_t u32IntEnable) +{ + pEnet->ENET_DMA.CH[eDMAChannel].INTERRUPT_ENABLE = u32IntEnable; +} + +/** + * @brief Enable one of the DMA channel interrupts + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] eIntFlag interrupt to be enabled + */ +LOCAL_INLINE void ENET_HWA_DMA_EnableInterrupt(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + ENET_DMA_InterruptFlagType eIntFlag) +{ + pEnet->ENET_DMA.CH[eDMAChannel].INTERRUPT_ENABLE |= (uint32_t)eIntFlag; +} + +/** + * @brief Disable one of the DMA channel interrupts + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] eIntFlag interrupt to be disbled + */ +LOCAL_INLINE void ENET_HWA_DMA_DisableInterrupt(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + ENET_DMA_InterruptFlagType eIntFlag) +{ + pEnet->ENET_DMA.CH[eDMAChannel].INTERRUPT_ENABLE &= ~(uint32_t)eIntFlag; +} + +/** + * @brief Get receive interrupt watchdog timer count unit + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return ENET_DMA_WDGCounterUnitType + */ +LOCAL_INLINE ENET_DMA_WDGCounterUnitType ENET_HWA_DMA_GetRxWDGCounterUnit(const ENET_Type *const pEnet, + ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].RX_INTERRUPT_WATCHDOG_TIMER & + ENET_DMA_CHn_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK) >> + ENET_DMA_CHn_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT; + return (ENET_DMA_WDGCounterUnitType)u32TmpVal; +} + +/** + * @brief Set receive interrupt watchdog timer count unit + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] eCounterUnit watchdog timer count unit + */ +LOCAL_INLINE void ENET_HWA_DMA_SetRxWDGCounterUnit(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + ENET_DMA_WDGCounterUnitType eCounterUnit) +{ + pEnet->ENET_DMA.CH[eDMAChannel].RX_INTERRUPT_WATCHDOG_TIMER = + (pEnet->ENET_DMA.CH[eDMAChannel].RX_INTERRUPT_WATCHDOG_TIMER & + (~ENET_DMA_CHn_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK)) | + ENET_DMA_CHn_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(eCounterUnit); +} + +/** + * @brief Get receive interrupt watchdog timer count + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint8_t watchdog timer count value + */ +LOCAL_INLINE uint8_t ENET_HWA_DMA_GetRxWDGCount(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].RX_INTERRUPT_WATCHDOG_TIMER & + ENET_DMA_CHn_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK) >> + ENET_DMA_CHn_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set receive interrupt watchdog timer count + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u8WDGCnt watchdog timer count + */ +LOCAL_INLINE void ENET_HWA_DMA_SetRxWDGCount(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, uint8_t u8WDGCnt) +{ + pEnet->ENET_DMA.CH[eDMAChannel].RX_INTERRUPT_WATCHDOG_TIMER = + (pEnet->ENET_DMA.CH[eDMAChannel].RX_INTERRUPT_WATCHDOG_TIMER & + (~ENET_DMA_CHn_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK)) | + ENET_DMA_CHn_RX_INTERRUPT_WATCHDOG_TIMER_RWT(u8WDGCnt); +} + +/** + * @brief Get reference slot number in the DMA + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint8_t reference slot number + */ +LOCAL_INLINE uint8_t ENET_HWA_DMA_GetRefSlotNumber(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].SLOT_FUNCTION_CONTROL_STATUS & + ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK) >> + ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set reference slot number in the DMA + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u8SlotNumber reference slot number + */ +LOCAL_INLINE void ENET_HWA_DMA_SetRefSlotNumber(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint8_t u8SlotNumber) +{ + pEnet->ENET_DMA.CH[eDMAChannel].SLOT_FUNCTION_CONTROL_STATUS = + (pEnet->ENET_DMA.CH[eDMAChannel].SLOT_FUNCTION_CONTROL_STATUS & + (~ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK)) | + ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_RSN(u8SlotNumber); +} + +/** + * @brief Get slot interval value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint16_t slot interval + */ +LOCAL_INLINE uint16_t ENET_HWA_DMA_GetSlotInterval(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].SLOT_FUNCTION_CONTROL_STATUS & + ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK) >> + ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT; + return (uint16_t)(u32TmpVal + 1u); +} + +/** + * @brief Set slot interval value + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u16SlotInterval slot interval + */ +LOCAL_INLINE void ENET_HWA_DMA_SetSlotInterval(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint16_t u16SlotInterval) +{ + pEnet->ENET_DMA.CH[eDMAChannel].SLOT_FUNCTION_CONTROL_STATUS = + (pEnet->ENET_DMA.CH[eDMAChannel].SLOT_FUNCTION_CONTROL_STATUS & + (~ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK)) | + ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_SIV((uint32_t)(u16SlotInterval - (uint32_t)1u)); +} + +/** + * @brief Get advance slot check enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true advance slot check is enabled + * @return false advance slot check is disabled + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetAdvanceSlotCheckEnFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].SLOT_FUNCTION_CONTROL_STATUS & + ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK) >> + ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set advance slot check enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_DMA_SetAdvanceSlotCheckEnFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + bool bEnable) +{ + pEnet->ENET_DMA.CH[eDMAChannel].SLOT_FUNCTION_CONTROL_STATUS = + (pEnet->ENET_DMA.CH[eDMAChannel].SLOT_FUNCTION_CONTROL_STATUS & + (~ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK)) | + ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_ASC(bEnable ? 1u : 0u); +} + +/** + * @brief Get slot comparison enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true slot comparison is enabled + * @return false slot comparison is disabled + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetSlotComparisonEnFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].SLOT_FUNCTION_CONTROL_STATUS & + ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK) >> + ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set slot comparison enable flag + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] bEnable + */ +LOCAL_INLINE void ENET_HWA_DMA_SetSlotComparisonEnFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + bool bEnable) +{ + pEnet->ENET_DMA.CH[eDMAChannel].SLOT_FUNCTION_CONTROL_STATUS = + (pEnet->ENET_DMA.CH[eDMAChannel].SLOT_FUNCTION_CONTROL_STATUS & + (~ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK)) | + ENET_DMA_CHn_SLOT_FUNCTION_CONTROL_STATUS_ESC(bEnable ? 1u : 0u); +} + +/** + * @brief Get DMA current Tx descriptor address pointer + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t current Tx descriptor + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetCurrentTxDescAddr(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].CURRENT_APP_TXDESC; +} + +/** + * @brief Get DMA current Rx descriptor address pointer + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t current Rx descriptor + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetCurrentRxDescAddr(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].CURRENT_APP_RXDESC; +} + +/** + * @brief Get DMA current Tx buffer address pointer + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t current Tx buffer + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetCurrentTxBufAddr(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].CURRENT_APP_TXBUFFER; +} + +/** + * @brief Get DMA current Rx buffer address pointer + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t current Rx buffer + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetCurrentRxBufAddr(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].CURRENT_APP_RXBUFFER; +} + +/** + * @brief Get DMA current status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return uint32_t DMA status + */ +LOCAL_INLINE uint32_t ENET_HWA_DMA_GetCurrentStatus(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + return pEnet->ENET_DMA.CH[eDMAChannel].STATUS; +} + +/** + * @brief Set DMA current status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @param [in] u32Status DMA status + */ +LOCAL_INLINE void ENET_HWA_DMA_SetCurrentStatus(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint32_t u32Status) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = u32Status; +} + +/** + * @brief Clear all DMA abnormal interrupts + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearAllAbnormalInterruptFlags(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_AIS_MASK | + ENET_DMA_CHn_STATUS_CDE_MASK | + ENET_DMA_CHn_STATUS_FBE_MASK | + ENET_DMA_CHn_STATUS_ETI_MASK | + ENET_DMA_CHn_STATUS_RPS_MASK | + ENET_DMA_CHn_STATUS_RBU_MASK | + ENET_DMA_CHn_STATUS_TPS_MASK; +} + +/** + * @brief Clear all DMA normal interrupts + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearAllNormalInterruptFlags(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_NIS_MASK | + ENET_DMA_CHn_STATUS_ERI_MASK | + ENET_DMA_CHn_STATUS_RI_MASK | + ENET_DMA_CHn_STATUS_TBU_MASK | + ENET_DMA_CHn_STATUS_TI_MASK; +} + +/** + * @brief Get DMA Rx error status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return ENET_DMA_RxErrorType + */ +LOCAL_INLINE ENET_DMA_RxErrorType ENET_HWA_DMA_GetRxError(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_REB_MASK) >> + ENET_DMA_CHn_STATUS_REB_SHIFT; + return (ENET_DMA_RxErrorType)u32TmpVal; +} + +/** + * @brief Clear DMA Rx error status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearRxError(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_TEB_MASK) & + (~ENET_DMA_CHn_STATUS_REB_MASK); +} + +/** + * @brief Get DMA Tx error status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return ENET_DMA_TxErrorType + */ +LOCAL_INLINE ENET_DMA_TxErrorType ENET_HWA_DMA_GetTxError(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_TEB_MASK) >> + ENET_DMA_CHn_STATUS_TEB_SHIFT; + return (ENET_DMA_TxErrorType)u32TmpVal; +} + +/** + * @brief Clear DMA Tx error status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearTxError(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_REB_MASK) & + (~ENET_DMA_CHn_STATUS_TEB_MASK); +} + +/** + * @brief Get DMA normal interrupt summary + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true normal interrupt detected + * @return false normal interrupt not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetNormalInterruptFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_NIS_MASK) >> + ENET_DMA_CHn_STATUS_NIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA normal interrupt summary + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearNormalInterruptFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_NIS_MASK; +} + +/** + * @brief Get DMA abnormal interrupt summary + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true abnormal interrupt detected + * @return false abnormal interrupt not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetAbnormalInterruptFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_AIS_MASK) >> + ENET_DMA_CHn_STATUS_AIS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA abnormal interrupt summary + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearAbnormalInterruptFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_AIS_MASK; +} + +/** + * @brief Get DMA context descriptor error + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true context descriptor error detected + * @return false context descriptor error not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetContextDescriptorErrorFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_CDE_MASK) >> + ENET_DMA_CHn_STATUS_CDE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA context descriptor error + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearContextDescriptorErrorFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_CDE_MASK; +} + +/** + * @brief Get DMA fatal bus error + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true fatal bus error detected + * @return false fatal bus error not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetFatalBusErrorFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_FBE_MASK) >> + ENET_DMA_CHn_STATUS_FBE_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA fatal bus error + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearFatalBusErrorFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + /* When FBE cleared, REB and TEB becomes invalid and shall also be cleared */ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = ENET_DMA_CHn_STATUS_FBE_MASK; +} + +/** + * @brief Get DMA early receive interrupt + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true early receive interrupt detected + * @return false early receive interrupt not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetEarlyRxInterruptFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_ERI_MASK) >> + ENET_DMA_CHn_STATUS_ERI_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA early receive interrupt + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearEarlyRxInterruptFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_ERI_MASK; +} + +/** + * @brief Get DMA early transmit interrupt + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true early transmit interrupt detected + * @return false early transmit interrupt not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetEarlyTxInterruptFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_ETI_MASK) >> + ENET_DMA_CHn_STATUS_ETI_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA early transmit interrupt + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearEarlyTxInterruptFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_ETI_MASK; +} + +/** + * @brief Get DMA receive watchdog timeout status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true receive watchdog timeout status detected + * @return false receive watchdog timeout status not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetRxWDGTimeoutFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_RWT_MASK) >> + ENET_DMA_CHn_STATUS_RWT_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA receive watchdog timeout status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearRxWDGTimeoutFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_RWT_MASK; +} + +/** + * @brief Get DMA receive process stopped status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true receive process stopped status detected + * @return false receive process stopped status not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetRxProcessStoppedFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_RPS_MASK) >> + ENET_DMA_CHn_STATUS_RPS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA receive process stopped status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearRxProcessStoppedFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_RPS_MASK; +} + +/** + * @brief Get DMA receive buffer unavailable status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true receive buffer unavailable status detected + * @return false receive buffer unavailable status not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetRxBufferUnavailableFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_RBU_MASK) >> + ENET_DMA_CHn_STATUS_RBU_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA receive buffer unavailable status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearRxBufferUnavailableFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_RBU_MASK; +} + +/** + * @brief Get DMA receive interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true receive interrupt detected + * @return false receive interrupt not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetRxInterruptFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_RI_MASK) >> + ENET_DMA_CHn_STATUS_RI_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA receive interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearRxInterruptFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_RI_MASK; +} + +/** + * @brief Get DMA transmit buffer unavailable status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true transmit buffer unavailable status detected + * @return false transmit buffer unavailable status not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetTxBufferUnavailableFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_TBU_MASK) >> + ENET_DMA_CHn_STATUS_TBU_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA transmit buffer unavailable status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearTxBufferUnavailableFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_TBU_MASK; +} + +/** + * @brief Get DMA transmit process stopped status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true transmit process stopped status detected + * @return false transmit process stopped status not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetTxProcessStoppedFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_TPS_MASK) >> + ENET_DMA_CHn_STATUS_TPS_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA transmit process stopped status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearTxProcessStoppedFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_TPS_MASK; +} + +/** + * @brief Get DMA transmit interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + * @return true transmit interrupt detected + * @return false transmit interrupt not detected + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetTxInterruptFlag(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & ENET_DMA_CHn_STATUS_TI_MASK) >> + ENET_DMA_CHn_STATUS_TI_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Clear DMA transmit interrupt status + + * @param [in] pEnet the base address of the ENET instance + * @param [in] eDMAChannel DMA channel + */ +LOCAL_INLINE void ENET_HWA_DMA_ClearTxInterruptFlag(ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + pEnet->ENET_DMA.CH[eDMAChannel].STATUS = (pEnet->ENET_DMA.CH[eDMAChannel].STATUS & + (ENET_DMA_CHn_STATUS_REB_MASK | ENET_DMA_CHn_STATUS_TEB_MASK)) | + ENET_DMA_CHn_STATUS_TI_MASK; +} + +/** + * @brief Get the miss frame count and overflow status of the Ethernet DMA channel + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eDMAChannel the DMA channel of the Ethernet instance + * @param [out] pMissPacketCnt the miss frame count of the channel + * @return true The miss frame count is overflow + * @return false the miss frame count is not overflow + */ +LOCAL_INLINE bool ENET_HWA_DMA_GetMissFrameCount(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel, + uint16_t *pMissPacketCnt) +{ + bool bRet; + uint32_t u32TmpVal = pEnet->ENET_DMA.CH[eDMAChannel].MISS_FRAME_CNT; + *pMissPacketCnt = (uint16_t)((u32TmpVal & ENET_DMA_CHn_MISS_FRAME_CNT_MFC_MASK) >> + ENET_DMA_CHn_MISS_FRAME_CNT_MFC_SHIFT); + bRet = (((u32TmpVal & ENET_DMA_CHn_MISS_FRAME_CNT_MFCO_MASK) >> ENET_DMA_CHn_MISS_FRAME_CNT_MFCO_SHIFT) != 0u) ? + true : false; + return bRet; +} + +/** + * @brief Get the count of the number of times Early Receive Interrupt was asserted. + * + * @param [in] pEnet the base address of the Ethernet instance + * @param [in] eDMAChannel the DMA channel of the Ethernet instance + * @return The count value + */ +LOCAL_INLINE uint16_t ENET_HWA_DMA_GetEarlyRxInterruptCount(const ENET_Type *const pEnet, ENET_DMA_ChannelType eDMAChannel) +{ + uint32_t u32TmpVal = (pEnet->ENET_DMA.CH[eDMAChannel].RX_ERI_CNT & ENET_DMA_CHn_RX_ERI_CNT_ECNT_MASK) >> + ENET_DMA_CHn_RX_ERI_CNT_ECNT_SHIFT; + return (uint16_t)u32TmpVal; +} + +#if ENET_SUPPORT_TIME_SENSITIVE_NETWORK +/** + * @brief Get EST offset Mode enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @return true EST offset Mode is enabled + * @return false EST offset Mode is disabled + */ +LOCAL_INLINE bool ENET_HWA_MTL_GetEstOffsetModeEnFlag(const ENET_Type *const pEnet) +{ + uint32_t u32TmpVal = (pEnet->MTL.TBS_CTRL & ENET_MTL_TBS_CTRL_ESTM_MASK) >> + ENET_MTL_TBS_CTRL_ESTM_SHIFT; + return (u32TmpVal != 0u) ? true : false; +} + +/** + * @brief Set EST offset Mode enable flag + * + * @param [in] pEnet the base address of the ENET instance + * @param [in] bEnable Enable or disable EST offset Mode + */ +LOCAL_INLINE void ENET_HWA_MTL_SetEstOffsetModeEnFlag(ENET_Type *const pEnet, bool bEnable) +{ + pEnet->MTL.TBS_CTRL = (pEnet->MTL.TBS_CTRL & ~ENET_MTL_TBS_CTRL_ESTM_MASK) | + ENET_MTL_TBS_CTRL_ESTM(bEnable ? 1u : 0u); +} + +/** + * @brief Get enhancements to scheduled transmission Status register value + + * @param [in] pEnet the base address of the ENET instance + * @return uint32_t EST Status value + */ +LOCAL_INLINE uint32_t ENET_HWA_MTL_GetEstCGSN(const ENET_Type *const pEnet) +{ + return (pEnet->MTL.EST_STATUS & ENET_MTL_EST_STATUS_CGSN_MASK) >> ENET_MTL_EST_STATUS_CGSN_SHIFT; +} + +#endif + +/** @}*/ + +#endif /* ENET_INSTANCE_COUNT > 0u */ + +#endif /* _HWA_ENET_H_ */ diff --git a/Inc/HwA_erm.h b/Inc/HwA_erm.h new file mode 100644 index 0000000..3e4cfc6 --- /dev/null +++ b/Inc/HwA_erm.h @@ -0,0 +1,153 @@ +/** + * @file HwA_erm.h + * @author Flagchip0100 + * @brief ERM Module Register API + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright 2020-2024 Flagchip Semiconductors Co., Ltd. + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip052 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip100 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_ERM_H_ +#define _HWA_ERM_H_ + +#include "device_header.h" + +#if (ERM_INSTANCE_COUNT > 0U) + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @defgroup HwA_erm HwA_erm + * @ingroup module_driver_erm + * @{ + */ + +/******************************************************************************* + * Local inline function + ******************************************************************************/ +/** + * @brief set erm configuration register. + * + * @param pErm ERM Instance. + * @param u8Idx Control register index. + * @param u32RegValue access control value. + */ +LOCAL_INLINE void ERM_HWA_SetCRn(ERM_Type *const pErm, uint8_t u8Idx, uint32_t u32RegValue) +{ +#ifdef ERM_CR4_SR4_SUPPORT + if (u8Idx == 4U) + { + pErm->CR4 = u32RegValue; + } + else +#endif + { + pErm->CR[u8Idx] = u32RegValue; + } +} + +/** + * @brief get ERM configuration register. + * + * @param pErm ERM Instance. + * @param u8Idx Control register index. + * @return ERM CRn value. + */ +LOCAL_INLINE uint32_t ERM_HWA_GetCRn(const ERM_Type *const pErm, uint8_t u8Idx) +{ + uint32_t u32Value = 0U; +#ifdef ERM_CR4_SR4_SUPPORT + if (u8Idx == 4U) + { + u32Value = pErm->CR4; + } + else +#endif + { + u32Value = pErm->CR[u8Idx]; + } + return u32Value; +} + +/** + * @brief set erm status register. + * + * @param pErm ERM Instance. + * @param u8Idx Status register index. + * @param u32RegValue access control value. + */ +LOCAL_INLINE void ERM_HWA_SetSRn(ERM_Type *const pErm, uint8_t u8Idx, uint32_t u32RegValue) +{ +#ifdef ERM_CR4_SR4_SUPPORT + if (u8Idx == 4U) + { + pErm->SR4 = u32RegValue; + } + else +#endif + { + pErm->SR[u8Idx] = u32RegValue; + } +} + +/** + * @brief get ERM status register. + * + * @param pErm ERM Instance. + * @param u8Idx Status register index. + * @return ERM SRn value. + */ +LOCAL_INLINE uint32_t ERM_HWA_GetSRn(const ERM_Type *const pErm, uint8_t u8Idx) +{ + uint32_t u32Value = 0U; +#ifdef ERM_CR4_SR4_SUPPORT + if (u8Idx == 4U) + { + u32Value = pErm->SR4; + } + else +#endif + { + u32Value = pErm->SR[u8Idx]; + } + return u32Value;; +} + +/** + * @brief get ERM error address register. + * + * @param pErm ERM Instance. + * @param u8Idx Error address register index. + * @return ERM error address register value. + */ +LOCAL_INLINE uint32_t ERM_HWA_GetEARn(const ERM_Type *const pErm, uint8_t u8Idx) +{ + return pErm->EAR[u8Idx].value; +} + + + +#if defined(__cplusplus) +} +#endif + +/** @}*/ /* HwA_erm */ + +#endif /* (ERM_INSTANCE_COUNT > 0U) */ + +#endif /* _HWA_ERM_H_ */ diff --git a/Inc/HwA_fciic.h b/Inc/HwA_fciic.h new file mode 100644 index 0000000..bffeebe --- /dev/null +++ b/Inc/HwA_fciic.h @@ -0,0 +1,1071 @@ +/** + * @file HwA_fciic.h + * @author flagchip + * @brief FCIIC hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip038 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip113 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_FCIIC_H_ +#define _HWA_FCIIC_H_ + +#include "device_header.h" + +#if FCIIC_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_fciic HwA_fciic + * @ingroup module_driver_fciic + * @{ + */ + +/** + * @brief FCIIC MSR flags. + * + */ +typedef enum +{ + FCIIC_MSR_TDF = FCIIC_MSR_TDF_MASK, /*!< Transmit data flag */ + FCIIC_MSR_RDF = FCIIC_MSR_RDF_MASK, /*!< Receive data flag */ + FCIIC_MSR_EPF = FCIIC_MSR_EPF_MASK, /*!< End Packet flag */ + FCIIC_MSR_SDF = FCIIC_MSR_SDF_MASK, /*!< Stop detect flag */ + FCIIC_MSR_NDF = FCIIC_MSR_NDF_MASK, /*!< NACK detect flag */ + FCIIC_MSR_ALF = FCIIC_MSR_ALF_MASK, /*!< Arbitration lost flag */ + FCIIC_MSR_FEF = FCIIC_MSR_FEF_MASK, /*!< FIFO error flag */ + FCIIC_MSR_PLTF = FCIIC_MSR_PLTF_MASK, /*!< Pin low timeout flag */ + FCIIC_MSR_DMF = FCIIC_MSR_DMF_MASK, /*!< Data match flag */ + FCIIC_MSR_MBF = FCIIC_MSR_MBF_MASK, /*!< Master busy flag */ + FCIIC_MSR_BBF = FCIIC_MSR_BBF_MASK, /*!< Bus busy flag */ + + /** All flags which are cleared by the driver upon starting a transfer. */ + FCIIC_MasterClearFlags = FCIIC_MSR_EPF | FCIIC_MSR_SDF | FCIIC_MSR_NDF | + FCIIC_MSR_ALF | FCIIC_MSR_FEF | + FCIIC_MSR_PLTF | FCIIC_MSR_DMF, + /** Errors to check for. */ + FCIIC_MasterErrorFlags = FCIIC_MSR_NDF | FCIIC_MSR_ALF + | FCIIC_MSR_FEF | FCIIC_MSR_PLTF +} FCIIC_MsrType; + +/** + * @brief FCIIC MIER flags. + * + */ +typedef enum +{ + FCIIC_MIER_TDIE = FCIIC_MIER_TDIE_MASK, /*!< Transmit data interrupt */ + FCIIC_MIER_RDIE = FCIIC_MIER_RDIE_MASK, /*!< Receive data interrupt */ + FCIIC_MIER_EPIE = FCIIC_MIER_EPIE_MASK, /*!< End Packet interrupt */ + FCIIC_MIER_SDIE = FCIIC_MIER_SDIE_MASK, /*!< Stop detect interrupt */ + FCIIC_MIER_NDIE = FCIIC_MIER_NDIE_MASK, /*!< NACK detect interrupt */ + FCIIC_MIER_ALIE = FCIIC_MIER_ALIE_MASK, /*!< Arbitration lost interrupt */ + FCIIC_MIER_FEIE = FCIIC_MIER_FEIE_MASK, /*!< FIFO error interrupt */ + FCIIC_MIER_PLTIE = FCIIC_MIER_PLTIE_MASK, /*!< Pin low timeout interrupt */ + FCIIC_MIER_DMIE = FCIIC_MIER_DMIE_MASK, /*!< Data match interrupt */ + + /** IRQ sources enabled for error. */ + FCIIC_MasterIrqErrorFlags = FCIIC_MIER_ALIE | FCIIC_MIER_FEIE | FCIIC_MIER_PLTIE, + + /** IRQ sources enabled by the non-blocking transactional API. */ + FCIIC_MasterIrqFlags = FCIIC_MIER_TDIE | FCIIC_MIER_RDIE | + FCIIC_MIER_SDIE | FCIIC_MIER_NDIE | + FCIIC_MIER_ALIE | FCIIC_MIER_FEIE | + FCIIC_MIER_PLTIE, +} FCIIC_MierType; + +/** + * @brief IIC Command Type Enumeration + * + */ +typedef enum +{ + FCIIC_TX_CMD_TRANSMIT = 0, /**< FCIIC_TX_CMD_TRANSMIT transmit command */ + FCIIC_TX_CMD_RECEIVE, /**< FCIIC_TX_CMD_RECEIVE receive command*/ + FCIIC_TX_CMD_STOP, /**< FCIIC_TX_CMD_STOP stop command */ + FCIIC_TX_CMD_RECANDDISCARD, /**< FCIIC_TX_CMD_RECANDDISCARD receive and discard data command*/ + FCIIC_TX_CMD_STARTANDTRANSMIT, /**< FCIIC_TX_CMD_STARTANDTRANSMIT start and then transmit data */ + FCIIC_TX_CMD_STARTANDTRANSMIT_WITHNAK/**< FCIIC_TX_CMD_STARTANDTRANSMIT_WITHNAK start and then transmit and don't care ACK */ +} FCIIC_TX_CMDType; + + +/** + * @brief IIC Master status type enumeration + * + */ +typedef enum +{ + FCIIC_MSR_BBF_STATUS = 25U, /**< FCIIC_MSR_BBF_STATUS Bus Busy Flag */ + FCIIC_MSR_MBF_STATUS = 24U, /**< FCIIC_MSR_MBF_STATUS Master Busy Flag */ + FCIIC_MSR_DMF_STATUS = 14U, /**< FCIIC_MSR_DMF_STATUS Data Match Flag */ + FCIIC_MSR_PLTF_STATUS = 13U, /**< FCIIC_MSR_PLTF_STATUS Pin Low Timeout Flag */ + FCIIC_MSR_FEF_STATUS = 12U, /**< FCIIC_MSR_FEF_STATUS FIFO Error Flag */ + FCIIC_MSR_ALF_STATUS = 11U, /**< FCIIC_MSR_ALF_STATUS Arbitration Lost Flag */ + FCIIC_MSR_NDF_STATUS = 10U, /**< FCIIC_MSR_NDF_STATUS NACK Detect Flag */ + FCIIC_MSR_SDF_STATUS = 9U, /**< FCIIC_MSR_SDF_STATUS STOP Detect Flag */ + FCIIC_MSR_EPF_STATUS = 8U, /**< FCIIC_MSR_EPF_STATUS End Packet Flag */ + FCIIC_MSR_RDF_STATUS = 1U, /**< FCIIC_MSR_RDF_STATUS Receive Data Flag */ + FCIIC_MSR_TDF_STATUS = 0U /**< FCIIC_MSR_TDF_STATUS Transmit Data Flag */ +} FCIIC_MasterStatusType; + +/** + * @brief FCIIC SSR flags. + * + */ +typedef enum +{ + FCIIC_SSR_TDF = FCIIC_SSR_TDF_MASK, /*!< Transmit data flag */ + FCIIC_SSR_RDF = FCIIC_SSR_RDF_MASK, /*!< Receive data flag */ + FCIIC_SSR_AVF = FCIIC_SSR_AVF_MASK, /*!< Address Valid Flag */ + FCIIC_SSR_TAF = FCIIC_SSR_TAF_MASK, /*!< Transmit ACK Flag */ + FCIIC_SSR_RSF = FCIIC_SSR_RSF_MASK, /*!< Repeated Start Flag */ + FCIIC_SSR_SDF = FCIIC_SSR_SDF_MASK, /*!< STOP Detect Flag */ + FCIIC_SSR_BEF = FCIIC_SSR_BEF_MASK, /*!< Bit Error Flag */ + FCIIC_SSR_TREF = FCIIC_SSR_TREF_MASK, /*!MCR = FCIIC_MCR_RST_MASK; + base->MCR = 0; +} + +/** + * @brief Enables or disables the FCIIC module as master. + * + * This function sets or clears the MEN bit in the MCR register to enable or disable the FCIIC module as master. + * + * @param base The FCIIC peripheral base address. + * @param enable Pass true to enable or false to disable the specified FCIIC as master. + */ +LOCAL_INLINE void FCIIC_HwA_MasterEnable(FCIIC_Type *const base, bool enable) +{ + base->MCR = (base->MCR & ~FCIIC_MCR_MEN_MASK) | FCIIC_MCR_MEN(enable); +} + +/** + * @brief Resets the FCIIC module's transmit and receive FIFOs. + * + * This function sets the RRF and RTF bits in the MCR register to reset the transmit and receive FIFOs. + * + * @param base The FCIIC peripheral base address. + */ +LOCAL_INLINE void FCIIC_HWA_MasterResetFIFO(FCIIC_Type *const base) +{ + volatile uint32_t u32Timeout = 0xFFFFu; + uint32_t u32EnableFlag = 0; + while(((base->MSR & FCIIC_MSR_BBF_MASK) == FCIIC_MSR_BBF_MASK) && (u32Timeout > 0)) + { + u32Timeout--; + } + if(u32Timeout != 0) + { + /* Save current men bit and disable iic function */ + u32EnableFlag = (base->MCR & FCIIC_MCR_MEN_MASK); + if(u32EnableFlag != 0) + { + base->MCR &= ~FCIIC_MCR_MEN_MASK; + } + /* Clear the TX and RX FIFOs */ + base->MCR |= (FCIIC_MCR_RRF_MASK | FCIIC_MCR_RTF_MASK); + /* Re-enable FCIIC if it was enabled previously */ + if(u32EnableFlag != 0) + { + base->MCR |= FCIIC_MCR_MEN_MASK; + } + } +} + +/** + * @brief Retrieves the current status of the FCIIC master enable bit. + * + * This function checks the MEN bit in the MCR register to determine if the FCIIC is enabled as master. + * + * @param base The FCIIC peripheral base address. + * @return State of the master enable bit: 0x01 if enabled, 0x00 if disabled. + */ +LOCAL_INLINE uint8_t FCIIC_HWA_MasterGetEnable(FCIIC_Type *const base) +{ + return (base->MCR & FCIIC_MCR_MEN_MASK) == FCIIC_MCR_MEN_MASK ? 0x01 : 0x00; +} + +/** + * @brief Gets the FCIIC master status flags. + * + * This function reads the MSR register to get the current status flags. + * + * @param base The FCIIC peripheral base address. + * @return The value of the MSR register. + */ +LOCAL_INLINE uint32_t FCIIC_HWA_MasterGetStatusFlags(const FCIIC_Type *const base) +{ + return base->MSR; +} + +/** + * @brief Clears the FCIIC master status flag state. + * + * This function clears specific status flags by writing to the MSR register. + * + * @param base The FCIIC peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. + */ +LOCAL_INLINE void FCIIC_HWA_MasterClearStatusFlags(FCIIC_Type *const base, uint32_t statusMask) +{ + base->MSR = statusMask; +} + +/** + * @brief Enables the FCIIC master interrupt requests. + * + * This function enables specific interrupt requests by setting bits in the MIER register. + * + * @param base The FCIIC peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. + */ +LOCAL_INLINE void FCIIC_HWA_MasterEnableInterrupts(FCIIC_Type *const base, uint32_t interruptMask) +{ + base->MIER |= interruptMask; +} + +/** + * @brief Disables the FCIIC master interrupt requests. + * + * @param base The FCIIC peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. + */ +LOCAL_INLINE void FCIIC_HWA_MasterDisableInterrupts(FCIIC_Type *const base, uint32_t interruptMask) +{ + base->MIER &= ~interruptMask; +} + +/** + * @brief Returns the set of currently enabled FCIIC master interrupt requests. + * + * @param base The FCIIC peripheral base address. + * @return A bitmask composed of FCIIC_MierType enumerators + */ +LOCAL_INLINE uint32_t FCIIC_HwA_MasterGetEnabledInterrupts(const FCIIC_Type *const base) +{ + return base->MIER; +} + +/** + * @brief Enables or disables FCIIC master DMA requests. + * + * @param base The FCIIC peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + */ +LOCAL_INLINE void FCIIC_HWA_MasterEnableDMA(FCIIC_Type *const base, bool enableTx, bool enableRx) +{ + base->MDER = FCIIC_MDER_TDDE(enableTx) | FCIIC_MDER_RDDE(enableRx); +} + +/** + * @brief Gets FCIIC master transmit data register address for DMA transfer. + * + * @param base The FCIIC peripheral base address. + * @return The FCIIC Master Transmit Data Register address. + */ +LOCAL_INLINE uint32_t FCIIC_HwA_MasterGetTxFifoAddress(const FCIIC_Type *const base) +{ + return (uint32_t)&base->MTDR; +} + +/** + * @brief Gets FCIIC master receive data register address for DMA transfer. + * + * @param base The FCIIC peripheral base address. + * @return The FCIIC Master Receive Data Register address. + */ +LOCAL_INLINE uint32_t FCIIC_HwA_MasterGetRxFifoAddress(const FCIIC_Type *const base) +{ + return (uint32_t)&base->MRDR; +} + +/** + * @brief Sets the watermarks for FCIIC master FIFOs. + * + * @param base The FCIIC peripheral base address. + * @param txWords Transmit FIFO watermark value. + * @param rxWords Receive FIFO watermark value. + */ +LOCAL_INLINE void FCIIC_HwA_MasterSetWatermarks(FCIIC_Type *const base, uint16_t txWords, uint16_t rxWords) +{ + base->MFCR = FCIIC_MFCR_TXWATER(txWords) | FCIIC_MFCR_RXWATER(rxWords); +} + +/** + * @brief Gets the current number of words in the FCIIC master FIFOs. + * + * @param base The FCIIC peripheral base address. + * @param[out] txCount Pointer through which the current number of words in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of words in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void FCIIC_HwA_MasterGetFifoCounts(const FCIIC_Type *const base, uint16_t *rxCount, uint16_t *txCount) +{ + if (NULL != txCount) + { + *txCount = (base->MFSR & FCIIC_MFSR_TXCOUNT_MASK) >> FCIIC_MFSR_TXCOUNT_SHIFT; + } + if (NULL != rxCount) + { + *rxCount = (base->MFSR & FCIIC_MFSR_RXCOUNT_MASK) >> FCIIC_MFSR_RXCOUNT_SHIFT; + } +} + +/** + * @brief Master Transmit Data + * + * Transmits data in the master mode. + * + * @param pFciic Pointer to the IIC instance value. + * @param tCmdType Command type to be sent. + * @param u8Data Data byte to be transmitted. + */ +LOCAL_INLINE void FCIIC_Master_HWA_Transmit(FCIIC_Type *pFciic, FCIIC_TX_CMDType tCmdType, uint8_t u8Data) +{ + pFciic->MTDR = FCIIC_MTDR_CMD(tCmdType) | FCIIC_MTDR_DATA(u8Data); +} + +/** + * @brief Get the number of bytes transmitted by the master + * + * Returns the count of bytes transmitted by the master. + * + * @param pFciic Pointer to the IIC instance value. + * @return Number of bytes transmitted. + */ +LOCAL_INLINE uint32 FCIIC_Master_HWA_GetTxCount(FCIIC_Type *pFciic) +{ + return (pFciic->MFSR & FCIIC_MFSR_TXCOUNT_MASK); +} + +/** + * @brief Master Receive Data + * + * Receives a data byte in the master mode. + * + * @param pFciic Pointer to the IIC instance value. + * @return Received data byte. + */ +LOCAL_INLINE uint8_t FCIIC_Master_HWA_Receive(FCIIC_Type *pFciic) +{ + /* copy data */ + return (uint8_t)((uint8_t)(pFciic->MRDR) & 0xFFU); +} + +/** + * @brief Get and clear IIC master status + * + * Checks and clears a specific status flag in the master mode. + * + * @param pFciic Pointer to the IIC instance value. + * @param eStatus Status type to check and clear. + */ +LOCAL_INLINE void FCIIC_Master_HwA_CheckClearStatus(FCIIC_Type *pFciic, FCIIC_MasterStatusType eStatus) +{ + uint32_t u32RetVal; + + u32RetVal = (pFciic->MSR >> eStatus) & 0x01U; + + + if (u32RetVal != 0U) + { + pFciic->MSR = (1UL << eStatus); /* write one to clear */ + } +} + +/** + * @brief Get master status + * + * Reads a specific status flag in the master mode. + * + * @param pFciic Pointer to the IIC instance value. + * @param eStatus Status type to read. + * @return Status value (0 or 1), where 1 indicates the status is set. + */ +LOCAL_INLINE uint8_t FCIIC_Master_HWA_GetStatus(FCIIC_Type *pFciic, FCIIC_MasterStatusType eStatus) +{ + uint32_t u32RetVal; + + u32RetVal = (pFciic->MSR >> (uint32_t)eStatus) & 0x01U; + + return (uint8_t)(u32RetVal == 1U ? 1U : 0U); +} + +/** + * @brief Clear master status + * + * Clears specific status flags in the master mode. + * + * @param pFciic Pointer to the IIC instance value. + * @param u32Value Bitmask of the status flags to clear. + */ +LOCAL_INLINE void FCIIC_Master_HWA_ClrStatus(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MSR = u32Value; +} + +/** + * @brief Enable Receive Interrupt + * + * Enables the receive interrupt in the master mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Master_HWA_EnableReceiveInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER |= FCIIC_MIER_RDIE_MASK; +} + +/** + * @brief Disable Receive Interrupt + * + * Disables the receive interrupt in the master mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Master_HWA_DisableReceiveInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER &= ~FCIIC_MIER_RDIE_MASK; +} + +/** + * @brief Enable Error Interrupt + * + * Enables the error interrupt in the master mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Master_HWA_EnableErrorInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER |= FCIIC_MIER_FEIE_MASK; +} + +/** + * @brief Disable Error Interrupt + * + * Disables the error interrupt in the master mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Master_HWA_DisableErrorInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER &= ~FCIIC_MIER_FEIE_MASK; +} + +/** + * @brief Get Error Flag + * + * Gets the error flag in the master mode. + * + * @param pFciic Pointer to the IIC instance value. + * @return Error flag value. + */ +LOCAL_INLINE uint32_t FCIIC_Master_HWA_GetErrorFlag(FCIIC_Type *pFciic) +{ + return pFciic->MSR & FCIIC_MSR_FEF_MASK; +} + +/** + * @brief Enable Transmit Interrupt + * + * Enables the transmit interrupt in the master mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Master_HWA_EnableTransmitInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER |= FCIIC_MIER_TDIE_MASK; +} + +/** + * @brief Disable Transmit Interrupt + * + * Disables the transmit interrupt in the master mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Master_HWA_DisableTransmitInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER &= ~FCIIC_MIER_TDIE_MASK; +} + +/** + * @brief Enable FCIIC SIER register bit. + * + * Enables a specific bit in the SIER register of the slave mode. + * + * @param[in] pFciic Pointer to the FCIIC instance value. + * @param[in] u32Mask The enable bit mask. + */ +LOCAL_INLINE void FCIIC_Slave_HWA_EnableInterrupt(FCIIC_Type *const pFciic, uint32 u32Mask) +{ + pFciic->SIER |= u32Mask; +} + +/** + * @brief Disable FCIIC SIER register bit. + * + * Disables a specific bit in the SIER register of the slave mode. + * + * @param[in] pFciic Pointer to the FCIIC instance value. + * @param[in] u32Mask The disable bit mask. + */ +LOCAL_INLINE void FCIIC_Slave_HWA_DisableInterrupt(FCIIC_Type *const pFciic, uint32 u32Mask) +{ + pFciic->SIER &= ~u32Mask; +} + +/** + * @brief Enable Receive Interrupt + * + * Enables the receive interrupt in the slave mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Slave_HWA_EnableReceiveInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER |= FCIIC_SIER_RDIE_MASK; +} + +/** + * @brief Disable Receive Interrupt + * + * Disables the receive interrupt in the slave mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Slave_HWA_DisableReceiveInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER &= ~FCIIC_SIER_RDIE_MASK; +} + +/** + * @brief Enable Error Interrupt + * + * Enables the error interrupt in the slave mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Slave_HWA_EnableErrorInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER |= FCIIC_SIER_TREIE_MASK | FCIIC_SIER_BEIE_MASK ; +} + +/** + * @brief Disable Error Interrupt + * + * Disables the error interrupt in the slave mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Slave_HWA_DisableErrorInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER &= ~(FCIIC_SIER_TREIE_MASK | FCIIC_SIER_BEIE_MASK); +} + +/** + * @brief Get Error Flag + * + * Gets the error flag in the slave mode. + * + * @param pFciic Pointer to the IIC instance value. + * @return Error flag value. + */ +LOCAL_INLINE uint32_t FCIIC_Slave_HWA_GetErrorFlag(FCIIC_Type *pFciic) +{ + return pFciic->SSR & (FCIIC_SSR_TREF_MASK | FCIIC_SSR_BEF_MASK); +} + +/** + * @brief Clear Error Flag + * + * Clears the error flag in the slave mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Slave_HWA_ClrErrorFlag(FCIIC_Type *pFciic) +{ + pFciic->SSR = (FCIIC_SSR_TREF_MASK | FCIIC_SSR_BEF_MASK); +} + +/** + * @brief Enable Transmit Interrupt + * + * Enables the transmit interrupt in the slave mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Slave_HWA_EnableTransmitInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER |= FCIIC_SIER_TDIE_MASK; +} + +/** + * @brief Disable Transmit Interrupt + * + * Disables the transmit interrupt in the slave mode. + * + * @param pFciic Pointer to the IIC instance value. + */ +LOCAL_INLINE void FCIIC_Slave_HWA_DisableTransmitInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER &= ~FCIIC_SIER_TDIE_MASK; /* Receive Interrupt Enable */ +} + +/** + * @brief Enables or disables FCIIC Slave DMA requests. + * + * Enables or disables DMA requests for transmit and receive operations in the slave mode. + * + * @param pFciic Pointer to the FCIIC peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + */ +LOCAL_INLINE void FCIIC_HWA_SlaveEnableDMA(FCIIC_Type *const pFciic, bool enableTx, bool enableRx) +{ + pFciic->SDER = FCIIC_SDER_TDDE(enableTx) | FCIIC_SDER_RDDE(enableRx); +} + +/** + * @brief Checks if the slave enable flag is set in the SCR register. + * + * This function checks if the slave is enabled by reading the SCR register. + * + * @param pFciic Pointer to the FCIIC module instance. + * @return 0x01 if the slave is enabled, 0x00 otherwise. + */ +LOCAL_INLINE uint8_t FCIIC_HWA_SlaveGetEnable(FCIIC_Type *const pFciic) +{ + return (pFciic->SCR & FCIIC_SCR_SEN_MASK) == FCIIC_SCR_SEN_MASK ? 0x01 : 0x00; +} + +/** + * @brief This Function is used to get slave status + * + * Reads a specific status flag in the slave mode. + * + * @param pFciic Pointer to the IIC instance value. + * @param eStatus Status type to read. + * @return Status value (0 or 1), where 1 indicates the status is set. + */ +LOCAL_INLINE uint8_t FCIIC_Slave_HWA_GetStatus(FCIIC_Type *pFciic, FCIIC_SlaveStatusType eStatus) +{ + uint32_t u32RetVal; + + u32RetVal = (pFciic->SSR >> (uint32_t)eStatus) & 0x01U; + + return (uint8_t)(u32RetVal == 1U ? 1U : 0U); +} + +/** + * @brief This Function is used to clear slave status + * + * Clears specific status flags in the slave mode. + * + * @param pFciic Pointer to the IIC instance value. + * @param u32Value Bitmask of the status flags to clear. + */ +LOCAL_INLINE void FCIIC_Slave_HWA_ClrStatus(FCIIC_Type *pFciic, uint32_t eStatus) +{ + pFciic->SSR = ((uint32)1U << (uint8)eStatus); /* w1c */; +} + +/** + * @brief get FCIIC SIER register. + * + * Reads the SIER register value in the slave mode. + * + * @param pFciic Pointer to the FCIIC instance value. + * @return SIER register value. + */ +LOCAL_INLINE uint32 FCIIC_HWA_GetSIER(const FCIIC_Type *const pFciic) +{ + return (pFciic->SIER & FCIIC_SIER_MASK); +} + +/** + * @brief Slave Transmit Data + * + * Transmits data in the slave mode. + * + * @param pFciic Pointer to the IIC instance value. + * @param u8Data Data byte to be transmitted. + */ +LOCAL_INLINE void FCIIC_Slave_HWA_Transmit(FCIIC_Type *pFciic, uint8_t u8Data) +{ + pFciic->STDR = FCIIC_STDR_DATA(u8Data); +} + +/** + * @brief Slave Get Data + * + * Receives a data byte in the slave mode. + * + * @param pFciic Pointer to the IIC instance value. + * @return Received data byte. + */ +LOCAL_INLINE uint8_t FCIIC_Slave_HWA_Receive(FCIIC_Type *pFciic) +{ + /* copy data */ + return (uint8_t)((uint8_t)(pFciic->SRDR) & 0xFFU); +} + +/** + * @brief Set FCIIC STAR register. + * + * Sets the STAR register value in the slave mode. + * + * @param pFciic Pointer to the FCIIC instance value. + * @param u32Value Register value to set. + */ +LOCAL_INLINE void FCIIC_Slave_HWA_NACK(FCIIC_Type *const pFciic, uint32 u32Value) +{ + pFciic->STAR = u32Value; +} + +/** + * @brief Set FCIIC MCR register + * + * Sets the MCR register value. + * + * @param pFciic Pointer to the FCIIC instance value. + * @param u32Value Register value to set. + */ +LOCAL_INLINE void FCIIC_HWA_SetMcr(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCR = u32Value; +} + +/** + * @brief Set FCIIC SSR register + * + * Reads the MSR register value. + * + * @param pFciic Pointer to the FCIIC instance value. + * @return MSR register value. + */ +LOCAL_INLINE uint32_t FCIIC_HWA_GetMSR(FCIIC_Type *pFciic) +{ + return pFciic->MSR; +} + +/** + * @brief Attach FCIIC MCR register + * + * Attaches a value to the MCR register. + * + * @param pFciic Pointer to the FCIIC instance value. + * @param u32Value Value to attach. + */ +LOCAL_INLINE void FCIIC_HWA_AttachMcr(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCR |= u32Value; +} + +/** + * @brief Set FCIIC MDER register + * + * Sets the MDER register value. + * + * @param pFciic Pointer to the FCIIC instance value. + * @param u32Value Register value to set. + */ +LOCAL_INLINE void FCIIC_HWA_SetMder(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MDER = u32Value; +} + +/** + * @brief get FCIIC MIER register. + * + * Reads the MIER register value. + * + * @param pFciic Pointer to the FCIIC instance value. + * @return MIER register value. + */ +LOCAL_INLINE uint32 FCIIC_HWA_GetMIER(const FCIIC_Type *const pFciic) +{ + return (pFciic->MIER & FCIIC_MIER_MASK); +} + +/** + * @brief Set FCIIC MCFGR0 register + * + * Sets the MCFGR0 register value. + * + * @param pFciic Pointer to the FCIIC instance value. + * @param u32Value Register value to set. + */ +LOCAL_INLINE void FCIIC_HWA_SetMCFGR0(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCFGR0 = u32Value; +} + +/** + * @brief get FCIIC MCFGR1 register + * + * Sets the MCFGR1 register value. + * + * @param pFciic Pointer to the FCIIC instance value. + */ +LOCAL_INLINE uint32_t FCIIC_HWA_GetMCFGR1(FCIIC_Type *pFciic) +{ + return pFciic->MCFGR1; +} + +/** + * @brief Set FCIIC MCFGR1 register + * + * @param pFciic FCIIC instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCFGR1(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCFGR1 = u32Value; +} + +/** + * @brief Set FCIIC MCFGR2 register + * + * @param pFciic FCIIC instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCFGR2(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCFGR2 = u32Value; +} + +/** + * @brief Set FCIIC MCFGR2 register + * + * @param pFciic FCIIC instance value + */ +LOCAL_INLINE uint32_t FCIIC_HWA_GetMCFGR2(FCIIC_Type *pFciic) +{ + return pFciic->MCFGR2; +} + +/** + * @brief Set FCIIC MCFGR3 register + * + * @param pFciic FCIIC instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCFGR3(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCFGR3 = u32Value; +} + +/** + * @brief Set FCIIC MFCR register + * + * @param pFciic FCIIC instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMFCR(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MFCR = u32Value; +} + +/** + * @brief Set FCIIC MCCR register + * + * @param pFciic FCIIC instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCCR(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCCR = u32Value; +} + +/** + * @brief Set FCIIC SDER register + * + * @param pFciic FCIIC instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSDER(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SDER = u32Value; +} + +/** + * @brief Set FCIIC SCFGR1 register + * + * @param pFciic FCIIC instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSCFGR1(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SCFGR1 = u32Value; +} + +/** + * @brief Get FCIIC SCFGR1 register + * + * @param pFciic FCIIC instance value + */ +LOCAL_INLINE uint32_t FCIIC_HWA_GetSCFGR1(FCIIC_Type *pFciic) +{ + return pFciic->SCFGR1; +} + +/** + * @brief Set FCIIC SCFGR2 register + * + * @param pFciic FCIIC instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSCFGR2(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SCFGR2 = u32Value; +} + +/** + * @brief Set FCIIC SAMR register + * + * @param pFciic FCIIC instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSAMR(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SAMR = u32Value; +} + +/** + * @brief Set FCIIC SCR register + * + * @param pFciic FCIIC instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSCR(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SCR = u32Value; +} + +/** + * @brief Set FCIIC SSR register + * + * @param pFciic FCIIC instance value + */ +LOCAL_INLINE uint32_t FCIIC_HWA_GetSSR(FCIIC_Type *pFciic) +{ + return pFciic->SSR; +} + +/** + * @brief Set FCIIC SDER register. + * + * @param[in] pFciic The FCIIC instance value. + * + * @return void. + */ +LOCAL_INLINE uint32 FCIIC_HWA_GetSDER(FCIIC_Type *const pFciic) +{ + return pFciic->SDER ; +} +/** + * @brief Get FCIIC slave received address. + * + * @param[in] pFciic The FCIIC instance value. + * + * @return uint32 The received address. + */ +LOCAL_INLINE uint32 FCIIC_HWA_GetSASR(const FCIIC_Type *const pFciic) +{ + return (pFciic->SASR & FCIIC_SASR_RADDR_MASK); +} + +/** @}*/ +#endif + +#endif /* end for #ifndef _HWA_FCIIC_H_ */ diff --git a/Inc/HwA_fcpit.h b/Inc/HwA_fcpit.h new file mode 100644 index 0000000..4ae022c --- /dev/null +++ b/Inc/HwA_fcpit.h @@ -0,0 +1,409 @@ +/** + * @file HwA_fcpit.h + * @author Flagchip + * @brief FCPIT hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip071 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip071 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_FCPIT_H_ +#define _HWA_FCPIT_H_ + +#include "device_header.h" + +#if FCPIT_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_fcpit HwA_fcpit + * @ingroup module_driver_fcpit + * @{ + */ + +/********* Local typedef ************/ +/** @brief Fcpit counter mode, the default mode is 32bit periodic count mode */ +typedef enum +{ + FCPIT_32PERIODIC_COUNTER = 0, + FCPIT_DUAL_16PERIODIC_COUNTER, + FCPIT_ACCUMULATOR, + FCPIT_INPUT_CAPTURE, + FCPIT_CHANNEL_NOMODE +} FCPIT_TimerModeType; + +/** @brief Fcpit channel number */ +typedef enum +{ + FCPIT_CHANNEL_0 = 0U, + FCPIT_CHANNEL_1, + FCPIT_CHANNEL_2, + FCPIT_CHANNEL_3, + FCPIT_CHANNEL_MAX +} FCPIT_ChannelType; + + + +/********* Local inline function ************/ +/** + * @brief Set FCPIT channel value + * + * @param eChannel FCPIT channel number + * @param u32RegValue Timer value + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelValue(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint32_t u32RegValue) +{ + pFcpit->CONTROLS[eChannel].TVAL = u32RegValue; +} + +/** + * @brief Configure FCPIT channel + * + * @param eChannel FCPIT channel number + * @param u32RegValue TCTRL register value + */ +LOCAL_INLINE void FCPIT_HWA_ConfigChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint32_t u32RegValue) +{ + pFcpit->CONTROLS[eChannel].TCTRL = u32RegValue; +} + +/** + * @brief Configure FCPIT module + * + * @param u32RegValue MCR register value + */ +LOCAL_INLINE void FCPIT_HWA_ConfigModule(FCPIT_Type *pFcpit, uint32_t u32RegValue) +{ + pFcpit->MCR = u32RegValue; +} + + +/** + * @brief Read FCPIT module enable + * + * @return MCR register with FCPIT_MCR_M_CEN_MASK + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadModuleEnable(FCPIT_Type *pFcpit) +{ + return (uint32_t)(pFcpit->MCR & FCPIT_MCR_M_CEN_MASK); +} + +/** + * @brief Read FCPIT channel + * + * @param eChannel Channel number + * @return TCTRL register with FCPIT_TCTRL_T_EN_MASK + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadChannelEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + return (uint32_t)(pFcpit->CONTROLS[eChannel].TCTRL & FCPIT_TCTRL_T_EN_MASK); +} + +/** + * @brief Read FCPIT active interrupt flag + * + * @return FCPIT active interrupt flag + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadInterruptFlag(FCPIT_Type *pFcpit) +{ + return (pFcpit->MSR); +} + +/** + * @brief Read FCPIT enable interrupt flag + * + * @return FCPIT enable interrupt flag + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadEnableInterruptFlag(FCPIT_Type *pFcpit) +{ + return (pFcpit->MIER); +} + +/** + * @brief Set FCPIT channel running on debug mode + * + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelRunOnDebug(FCPIT_Type *pFcpit) +{ + pFcpit->MCR |= FCPIT_MCR_DBG_EN_MASK; +} + +/** + * @brief Set FCPIT channel running on low power mode + * + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelRunOnLpm(FCPIT_Type *pFcpit) +{ + pFcpit->MCR |= FCPIT_MCR_LPM_EN_MASK; +} + +/** + * @brief Enable FCPIT module + * + */ +LOCAL_INLINE void FCPIT_HWA_EnableModule(FCPIT_Type *pFcpit) +{ + pFcpit->MCR |= FCPIT_MCR_M_CEN_MASK; +} + +/** + * @brief Enable FCPIT channel(n) interrupt + * + * @param u32RegValue u32RegValue 0-3 bit indicate TIE0-TIE3 + */ +LOCAL_INLINE void FCPIT_HWA_EnableChannelsInterrupt(FCPIT_Type *pFcpit, uint32_t u32RegValue) +{ + pFcpit->MIER |= u32RegValue; +} + +/** + * @brief Enable FCPIT channel + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_EnableChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_T_EN_MASK; +} + +/** + * @brief Enable FCPIT channel + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetTimerEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->SETTEN |= (FCPIT_SETTEN_SET_T_EN_0_MASK << (uint32_t)eChannel); +} + + +/** + * @brief Disable FCPIT channel + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearTimerEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CLRTEN |= (FCPIT_CLRTEN_CLR_T_EN_0_MASK << (uint32_t)eChannel); +} + +/** + * @brief Enable FCPIT channel(n) chain mode + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_EnableChannelChainMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_CHAIN_MASK; +} + +/** + * @brief Configure FCPIT channel operation mode + * + * @param eChannel FCPIT channel number + * @param eMode FCPIT operation mode + */ +LOCAL_INLINE void FCPIT_HWA_ConfigChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, FCPIT_TimerModeType eMode) +{ + uint32_t u32RegValue = pFcpit->CONTROLS[eChannel].TCTRL; + pFcpit->CONTROLS[eChannel].TCTRL = (u32RegValue & ~(uint32_t)FCPIT_TCTRL_MODE_MASK) | FCPIT_TCTRL_MODE(eMode); +} + +/** + * @brief Set FCPIT channel start on trigger + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelStartOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TSOT_MASK; +} + +/** + * @brief Set FCPIT channel stop on interrupt + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnInterrupt(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TSOI_MASK; +} + +/** + * @brief Set FCPIT channel reload on trigger + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelReloadOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TROT_MASK; +} + +/** + * @brief Set FCPIT channel trigger source + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelTriggerSrc(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TRG_SRC_MASK; +} + +/** + * @brief Select FCPIT channel trigger + * + * @param eChannel FCPIT channel number + * @param u8SelChannel Select channel, range is 0-3 + */ +LOCAL_INLINE void FCPIT_HWA_SelectChannelTrigger(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint8_t u8SelChannel) +{ + uint32_t u32RegValue = pFcpit->CONTROLS[eChannel].TCTRL; + pFcpit->CONTROLS[eChannel].TCTRL = (u32RegValue & ~(uint32_t)FCPIT_TCTRL_TRG_SEL_MASK) | + FCPIT_TCTRL_TRG_SEL(u8SelChannel); +} + +/** + * @brief Set FCPIT channel stop on debug mode + * + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnDebug(FCPIT_Type *pFcpit) +{ + pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_DBG_EN_MASK; +} + +/** + * @brief Set FCPIT channel stop on low power mode + * + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnLpm(FCPIT_Type *pFcpit) +{ + pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_LPM_EN_MASK; +} + +/** + * @brief Disable FCPIT module + * + */ +LOCAL_INLINE void FCPIT_HWA_DisableModule(FCPIT_Type *pFcpit) +{ + pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_M_CEN_MASK; +} + +/** + * @brief Clear FCPIT channel(n) interrupt flag + * + * @param u32RegValue 0-3 bit indicate TIF0-TIF3 + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT_Type *pFcpit, uint32_t u32RegValue) +{ + pFcpit->MSR = u32RegValue; +} + +/** + * @brief Disable FCPIT channel(n) interrupt + * + * @param u32RegValue u32RegValue 0-3 bit indicate TIE0-TIE3 + */ +LOCAL_INLINE void FCPIT_HWA_DisableChannelsInterrupt(FCPIT_Type *pFcpit, uint32_t u32RegValue) +{ + pFcpit->MIER &= ~u32RegValue; +} + +/** + * @brief Disable FCPIT channel + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_DisableChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_T_EN_MASK; +} + +/** + * @brief Disable FCPIT channel chain mode + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_DisableChannelChainMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_CHAIN_MASK; +} + +/** + * @brief Clear FCPIT channel operation mode + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_MODE_MASK; +} + +/** + * @brief Clear FCPIT channel start on trigger + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelStartOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TSOT_MASK; +} + +/** + * @brief Clear FCPIT channel stop on interrupt + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelStopOnInterrupt(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TSOI_MASK; +} + +/** + * @brief Clear FCPIT channel reload on trigger + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelReloadOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TROT_MASK; +} + +/** + * @brief Clear FCPIT channel trigger source + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelTriggerSrc(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TRG_SRC_MASK; +} + +/** + * @brief Clear FCPIT channel trigger select + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelTriggerSelect(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TRG_SEL_MASK; +} + +/** @}*/ + +#endif /* #if FCPIT_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_FCPIT_H_ */ diff --git a/Inc/HwA_fcsmu.h b/Inc/HwA_fcsmu.h new file mode 100644 index 0000000..11ad4f0 --- /dev/null +++ b/Inc/HwA_fcsmu.h @@ -0,0 +1,708 @@ +/** + * @file HwA_fcsmu.h + * @author Flagchip0100 + * @brief FCSMU module register API + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright 2020-2024 Flagchip Semiconductors Co., Ltd. + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip052 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip100 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_FCSMU_H_ +#define _HWA_FCSMU_H_ + +#include "device_header.h" + +#if (FCSMU_INSTANCE_COUNT > 0U) + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @defgroup HwA_fcsmu HwA_fcsmu + * @ingroup module_driver_fcsmu + * @{ + */ + +/******************************************************************************* + * Local inline function + ******************************************************************************/ +/** + * @brief Set the fcsmu CTRL register + * + * @param pFcsmu FCSMU Instance + * @param u32Value The register value + */ +LOCAL_INLINE void FCSMU_HWA_SetCrtl(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->CTRL = u32Value; +} + +/** + * @brief Get the fcsmu CTRL register + * + * @param pFcsmu FCSMU Instance + * @return CTRL register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCtrl(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->CTRL; +} + +/** + * @brief Get the fcsmu CTRL register OPS + * + * @param pFcsmu FCSMU Instance + * @return CTRL register OPS value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCtrlOps(const FCSMU_Type *const pFcsmu) +{ + return ((pFcsmu->CTRL & FCSMU_CTRL_OPS_MASK) >> FCSMU_CTRL_OPS_SHIFT); +} + +/** + * @brief Set the fcsmu OPRK register + * + * @param pFcsmu FCSMU Instance + * @param u32Value The register value + */ +LOCAL_INLINE void FCSMU_HWA_SetOprk(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->OPRK = u32Value; +} + +/** + * @brief Set the fcsmu SOCTRL register + * + * @param pFcsmu FCSMU Instance + * @param u32Value The register value + */ +LOCAL_INLINE void FCSMU_HWA_SetSoctrl(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->SOCTRL = u32Value; +} + +/** + * @brief Get the fcsmu SOCTRL register + * + * @param pFcsmu FCSMU Instance + * @return SOCTRL register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetSoctrl(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->SOCTRL; +} + +/** + * @brief Set the fcsmu FCCR0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FCCR0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFccr0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FCCR0 = u32Value; +} + +/** + * @brief Get the fcsmu FCCR0 register + * + * @param pFcsmu FCSMU Instance + * @return FCCR0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFccr0(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FCCR0; +} + +/** + * @brief Set the fcsmu FRST0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FRST0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFrst0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FRST0 = u32Value; +} + +/** + * @brief Get the fcsmu FRST0 register + * + * @param pFcsmu FCSMU Instance + * @return FRST0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFrst0(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FRST0; +} + +/** + * @brief Set the fcsmu FST0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FST0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFst0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FST0 = u32Value; +} + +/** + * @brief Get the fcsmu FST0 register + * + * @param pFcsmu FCSMU Instance + * @return FST0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFst0(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FST0; +} + +/** + * @brief Set the fcsmu FST_UNLK register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FST_UNLK register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFstUnlk(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FST_UNLK = u32Value; +} + +/** + * @brief Set the fcsmu FE0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FE0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFe0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FE0 = u32Value; +} + +/** + * @brief Get the fcsmu FE0 register + * + * @param pFcsmu FCSMU Instance + * @return FE0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFe0(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FE0; +} + +/** + * @brief Set the fcsmu WARNING_EN0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value WARNING_EN0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetWarningEn0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->WARNING_EN0 = u32Value; +} + +/** + * @brief Get the fcsmu WARNING_EN0 register + * + * @param pFcsmu FCSMU Instance + * @return WARNING_EN0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetWarningEn0(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->WARNING_EN0; +} + +/** + * @brief Set the fcsmu WARNING_TO register + * + * @param pFcsmu FCSMU Instance + * @param u32Value WARNING_TO register value + */ +LOCAL_INLINE void FCSMU_HWA_SetWarningTo(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->WARNING_TO = u32Value; +} + +/** + * @brief Get the fcsmu WARNING_TO register + * + * @param pFcsmu FCSMU Instance + * @return WARNING_TO register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetWarningTo(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->WARNING_TO; +} + +/** + * @brief Set the fcsmu CFG_TO register + * + * @param pFcsmu FCSMU Instance + * @param u32Value CFG_TO register value + */ +LOCAL_INLINE void FCSMU_HWA_SetCfgTo(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->CFG_TO = u32Value; +} + +/** + * @brief Get the fcsmu CFG_TO register + * + * @param pFcsmu FCSMU Instance + * @return CFG_TO register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCfgTo(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->CFG_TO; +} + +/** + * @brief Set the fcsmu SOUT_DIAG register + * + * @param pFcsmu FCSMU Instance + * @param u32Value SOUT_DIAG register value + */ +LOCAL_INLINE void FCSMU_HWA_SetSoutDiag(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->SOUT_DIAG = u32Value; +} + +/** + * @brief Get the fcsmu SOUT_DIAG register + * + * @param pFcsmu FCSMU Instance + * @return SOUT_DIAG register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetSoutDiag(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->SOUT_DIAG; +} + +/** + * @brief Get the fcsmu STATUS register + * + * @param pFcsmu FCSMU Instance + * @return STATUS register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetStatus(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->STATUS; +} + +/** + * @brief Get the fcsmu STATUS register FIF value + * + * @param pFcsmu FCSMU Instance + * @return STATUS register FIF value + */ +LOCAL_INLINE bool FCSMU_HWA_GetFaultState(const FCSMU_Type *const pFcsmu) +{ + return ((pFcsmu->STATUS & FCSMU_STATUS_FIF_MASK) == FCSMU_STATUS_FIF_MASK) ? true : false; +} + +/** + * @brief Get the fcsmu STATUS register STAT value + * + * @param pFcsmu FCSMU Instance + * @return STATUS register STAT value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFcsmuState(const FCSMU_Type *const pFcsmu) +{ + return ((pFcsmu->STATUS & FCSMU_STATUS_STAT_MASK) >> FCSMU_STATUS_STAT_SHIFT); +} + +/** + * @brief Get the fcsmu NTW register + * + * @param pFcsmu FCSMU Instance + * @return NTW register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetNtw(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->NTW; +} + +/** + * @brief Get the fcsmu WTF register + * + * @param pFcsmu FCSMU Instance + * @return WTF register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetWtf(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->WTF; +} + +/** + * @brief Get the fcsmu NTF register + * + * @param pFcsmu FCSMU Instance + * @return NTF register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetNtf(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->NTF; +} + +/** + * @brief Get the fcsmu FTW register + * + * @param pFcsmu FCSMU Instance + * @return FTW register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFtw(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FTW; +} + +/** + * @brief Set the fcsmu INJECT register + * + * @param pFcsmu FCSMU Instance + * @param u32Value INJECT register value + */ +LOCAL_INLINE void FCSMU_HWA_SetInject(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->INJECT = u32Value; +} + +/** + * @brief Get the fcsmu IRQ_STAT register + * + * @param pFcsmu FCSMU Instance + * @return IRQ_STAT register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetIrqStat(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->IRQ_STAT; +} + +/** + * @brief Clear the fcsmu IRQ_STAT register + * + * @param pFcsmu FCSMU Instance + */ +LOCAL_INLINE void FCSMU_HWA_ClearCfgToIrq(FCSMU_Type *const pFcsmu) +{ + pFcsmu->IRQ_STAT = FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK; +} + +/** + * @brief Set the fcsmu IRQ_EN register + * + * @param pFcsmu FCSMU Instance + * @param bEnable IRQ_EN register value + */ +LOCAL_INLINE void FCSMU_HWA_EnableCfgToIrq(FCSMU_Type *const pFcsmu, bool bEnable) +{ + pFcsmu->IRQ_EN = FCSMU_IRQ_EN_CFG_TO_IEN(bEnable); +} + +/** + * @brief Set the fcsmu TEMP_UNLK register + * + * @param pFcsmu FCSMU Instance + * @param u32Value TEMP_UNLK register value + */ +LOCAL_INLINE void FCSMU_HWA_SetTempUnlk(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->TEMP_UNLK = u32Value; +} + +/** + * @brief Set the fcsmu PERMNT_LOCK register + * + * @param pFcsmu FCSMU Instance + * @param u32Value PERMNT_LOCK register value + */ +LOCAL_INLINE void FCSMU_HWA_SetPermntLock(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->PERMNT_LOCK = u32Value; +} + +/** + * @brief Set the fcsmu STMR register + * + * @param pFcsmu FCSMU Instance + * @param u32Value STMR register value + */ +LOCAL_INLINE void FCSMU_HWA_SetStmr(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->STMR = u32Value; +} + +/** + * @brief Set the fcsmu WARNING_IEN0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value WARNING_IEN0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetWarningIen0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->WARNING_IEN0 = u32Value; +} + +/** + * @brief Set the fcsmu FAULT_IEN0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FAULT_IEN0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFaultIen0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FAULT_IEN0 = u32Value; +} + +/** + * @brief Set the fcsmu SOUT_EN0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value SOUT_EN0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetSoutEn0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->SOUT_EN0 = u32Value; +} + +/** + * @brief Get the fcsmu WARNING_TMR register + * + * @param pFcsmu FCSMU Instance + * @return WARNING_TMR register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetWarningTmr(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->WARNING_TMR; +} + +/** + * @brief Get the fcsmu SM_TMR register + * + * @param pFcsmu FCSMU Instance + * @return SM_TMR register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetSafeModeTmr(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->SM_TMR; +} + +/** + * @brief Get the fcsmu CFG_TMR register + * + * @param pFcsmu FCSMU Instance + * @return CFG_TMR register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCfgTmr(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->CFG_TMR; +} + +/** + * @brief Get the fcsmu SOUT_TMR register + * + * @param pFcsmu FCSMU Instance + * @return SOUT_TMR register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetSoutTmr(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->SOUT_TMR; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + * @param u32Value CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_SetCrcCtrl(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->CRC_CTRL = u32Value; +} + +/** + * @brief Get the fcsmu CRC_CTRL register BUSY value + * + * @param pFcsmu FCSMU Instance + * @return BUSY value + */ +LOCAL_INLINE bool FCSMU_HWA_GetCrcBusy(const FCSMU_Type *const pFcsmu) +{ + bool bRet = false; +#ifdef FCSMU_CRC_CTRL_DONE_SUPPORT + bRet = ((pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_DONE_MASK) == FCSMU_CRC_CTRL_DONE_MASK) ? false : true; +#else + bRet = ((pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_BUSY_MASK) == FCSMU_CRC_CTRL_BUSY_MASK) ? true : false; +#endif /* FCSMU_CRC_CTRL_DONE_SUPPORT */ + + return bRet; +} + +/** + * @brief Get the fcsmu CRC_CTRL register EF value + * + * @param pFcsmu FCSMU Instance + * @return EF value + */ +LOCAL_INLINE bool FCSMU_HWA_GetCrcErrorFlag(const FCSMU_Type *const pFcsmu) +{ + return ((pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_EF_MASK) == FCSMU_CRC_CTRL_EF_MASK) ? true : false; +} + +/** + * @brief Clear the fcsmu CRC_CTRL register EF + * + * @param pFcsmu FCSMU Instance + */ +LOCAL_INLINE void FCSMU_HWA_ClearCrcErrorFlag(FCSMU_Type *const pFcsmu) +{ + uint32_t u32RegValue = pFcsmu->CRC_CTRL; + /* Reserve RW bits */ + u32RegValue = u32RegValue & (FCSMU_CRC_CTRL_EOEN_MASK | + FCSMU_CRC_CTRL_CHKEN_MASK | + FCSMU_CRC_CTRL_TRGEN_MASK); + u32RegValue = u32RegValue | FCSMU_CRC_CTRL_EF_MASK; + pFcsmu->CRC_CTRL = u32RegValue; +} + +#ifdef FCSMU_CRC_CTRL_DONE_SUPPORT +/** + * @brief Clear the fcsmu CRC_CTRL register DONE + * + * @param pFcsmu FCSMU Instance + */ +LOCAL_INLINE void FCSMU_HWA_ClearCrcDoneFlag(FCSMU_Type *const pFcsmu) +{ + uint32_t u32RegValue = pFcsmu->CRC_CTRL; + /* Reserve RW bits */ + u32RegValue = u32RegValue & (FCSMU_CRC_CTRL_EOEN_MASK | + FCSMU_CRC_CTRL_CHKEN_MASK | + FCSMU_CRC_CTRL_TRGEN_MASK); + u32RegValue = u32RegValue | FCSMU_CRC_CTRL_DONE_MASK; + pFcsmu->CRC_CTRL = u32RegValue; +} +#endif + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + * @param bEnable Enable or Disable CRC_CTRL register EOEN bit value + */ +LOCAL_INLINE void FCSMU_HWA_EnableErrorOutput(FCSMU_Type *const pFcsmu, bool bEnable) +{ + uint32_t u32RegValue = pFcsmu->CRC_CTRL; + /* Reserve RW bits */ + u32RegValue = u32RegValue & (FCSMU_CRC_CTRL_CHKEN_MASK | + FCSMU_CRC_CTRL_TRGEN_MASK); + + u32RegValue = (u32RegValue & ~FCSMU_CRC_CTRL_EOEN_MASK) | FCSMU_CRC_CTRL_EOEN(bEnable); + pFcsmu->CRC_CTRL = u32RegValue; +} + +/** + * @brief Get the fcsmu CRC_CTRL register EOEN value + * + * @param pFcsmu FCSMU Instance + * @return EOEN value + */ +LOCAL_INLINE bool FCSMU_HWA_GetCrcErrorOutputEnable(const FCSMU_Type *const pFcsmu) +{ + return ((pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_EOEN_MASK) == FCSMU_CRC_CTRL_EOEN_MASK) ? true : false; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + * @param bEnable CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_EnableCrcChecker(FCSMU_Type *const pFcsmu, bool bEnable) +{ + pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_CHKEN_MASK) | FCSMU_CRC_CTRL_CHKEN(bEnable); +} + +/** + * @brief Get the fcsmu CRC_CTRL register CHKEN value + * + * @param pFcsmu FCSMU Instance + * @return CHKEN value + */ +LOCAL_INLINE bool FCSMU_HWA_GetCrcCheckerEnable(const FCSMU_Type *const pFcsmu) +{ + return ((pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_CHKEN_MASK) == FCSMU_CRC_CTRL_CHKEN_MASK) ? true : false; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + * @param bEnable CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_EnableTrigger(FCSMU_Type *const pFcsmu, bool bEnable) +{ + pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_TRGEN_MASK) | FCSMU_CRC_CTRL_TRGEN(bEnable); +} + +/** + * @brief Get the fcsmu CRC_CTRL register TRGEN value + * + * @param pFcsmu FCSMU Instance + * @return TRGEN value + */ +LOCAL_INLINE bool FCSMU_HWA_GetTriggerEnable(const FCSMU_Type *const pFcsmu) +{ + return ((pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_TRGEN_MASK) == FCSMU_CRC_CTRL_TRGEN_MASK) ? true : false; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + */ +LOCAL_INLINE void FCSMU_HWA_GenerateCrc(FCSMU_Type *const pFcsmu) +{ + uint32_t u32RegValue = pFcsmu->CRC_CTRL; + /* Reserve RW bits */ + u32RegValue = u32RegValue & (FCSMU_CRC_CTRL_EOEN_MASK | + FCSMU_CRC_CTRL_CHKEN_MASK | + FCSMU_CRC_CTRL_TRGEN_MASK); + u32RegValue = u32RegValue | FCSMU_CRC_CTRL_GEN(1U); + pFcsmu->CRC_CTRL = u32RegValue; +} + +/** + * @brief Get the fcsmu CRC_RES register + * + * @param pFcsmu FCSMU Instance + * @return CRC_RES register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCrcResult(const FCSMU_Type *const pFcsmu) +{ + return pFcsmu->CRC_RES; +} + + +#if defined(__cplusplus) +} +#endif + +/** @}*/ + +#endif /* (FCSMU_INSTANCE_COUNT > 0U) */ + +#endif /* _HWA_FCSMU_H_ */ diff --git a/Inc/HwA_fcspi.h b/Inc/HwA_fcspi.h new file mode 100644 index 0000000..2195cba --- /dev/null +++ b/Inc/HwA_fcspi.h @@ -0,0 +1,412 @@ + +#ifndef _HWA_FCSPI_H_ +#define _HWA_FCSPI_H_ + +#include "device_header.h" + +#define FCSPI_SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define FCSPI_CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define FCSPI_READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define FCSPI_CLEAR_REG(REG) ((REG) = (0x0)) + +#define FCSPI_WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define FCSPI_READ_REG(REG) ((REG)) + +#define FCSPI_MODIFY_REG(REG, CLEARMASK, SETMASK) FCSPI_WRITE_REG((REG), (((FCSPI_READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + + + + +#if FCSPI_INSTANCE_COUNT > 0U + +/** + * @brief FCSPI Mode type, master or slave. + */ +typedef enum { + FCSPI_MODE_SLAVE = 0, + FCSPI_MODE_MASTER = 1 +} FCSPI_MasterSlaveModeType; + +typedef enum { + FCSPI_PCS_0 = 0, /**< Transfer using pcs_0 */ + FCSPI_PCS_1 = 1, /**< Transfer using pcs_1 */ + FCSPI_PCS_2 = 2, /**< Transfer using pcs_2 */ + FCSPI_PCS_3 = 3 /**< Transfer using pcs_3 */ +} FCSPI_PcsSelType; + +typedef enum { + FCSPI_PCS_ACTIVE_LOW = 0, /**< pcs use low level to select external device */ + FCSPI_PCS_ACTIVE_HIGH = 1 /**< pcs use high level to select external device */ +} FCSPI_PcsPolarityType; + +typedef enum { + FCSPI_SIN_INPUT_SOUT_OUTPUT = 0, /**< SIN is configured as input pin and SOUT is configured as output pin */ + FCSPI_SIN_INPUT_OUTPUT = 1, /**< SIN is configured as input and output pin */ + FCSPI_SOUT_INPUT_OUTPUT = 2, /**< SOUT is configured as input and output pin */ + FCSPI_SOUT_INPUT_SIN_OUTPUT = 3 /**< SOUT is configured as input pin and SIN is configured as output pin */ +} FCSPI_PinConfigType; + +typedef enum { + FCSPI_OUTPUT_RETAIN_LAST = 0, /**< SIN is configured as input pin and SOUT is configured as output pin */ + FCSPI_OUTPUT_TRISTATE = 1 +} FCSPI_OutputConfigType; + +typedef enum { + FCSPI_TRANSFER_WIDTH_1_BIT = 0, /**< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */ + FCSPI_TRANSFER_WIDTH_2_BIT = 1, /**< 2-bits shift out on SDO/SDI and in on SDO/SDI */ + FCSPI_TRANSFER_WIDTH_4_BIT = 2 /**< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */ +} FCSPI_TransferWidthType; + +typedef enum +{ + FCSPI_MSB_FIRST = 0, /**< most significant bit first handle, from msb to lsb */ + FCSPI_LSB_FIRST = 1 /**< least significant bit first handle, from lsb to msb */ +} FCSPI_DataFirstBitType; + +typedef enum +{ + FCSPI_PRESCALE_DIV_1 = 0, /**< most significant bit first handle, from msb to lsb */ + FCSPI_PRESCALE_DIV_2 = 1, + FCSPI_PRESCALE_DIV_4 = 2, + FCSPI_PRESCALE_DIV_8 = 3, + FCSPI_PRESCALE_DIV_16 = 4, + FCSPI_PRESCALE_DIV_32 = 5, + FCSPI_PRESCALE_DIV_64 = 6, + FCSPI_PRESCALE_DIV_128 = 7 +} FCSPI_PrescaleType; + +typedef enum +{ + FCSPI_SCK_SAMPLE_FIRST_EDGE = 0, /**< sample on first edge of sck active polarity, change on second */ + FCSPI_SCK_SAMPLE_SECOND_EDGE = 1 /**< sample on second edge of sck active polarity, change on first */ +} FCSPI_SckPhaseType; + +typedef enum +{ + FCSPI_SCK_IDLE_LOW = 0, /**< sck is high level when active (idles low). */ + FCSPI_SCK_IDLE_HIGH = 1 /**< sck is low level when active (idles high). */ +} FCSPI_SckPolarityType; + +/********* Local inline function ************/ + +/** + * @brief Manipulate CTRL.M_EN to enable/disable FCSPI. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + */ +LOCAL_INLINE void FCSPI_HWA_EnableModule(FCSPI_Type *pFCSPI, bool enable) +{ + enable ? FCSPI_WRITE_REG(pFCSPI->CTRL, 1) : FCSPI_WRITE_REG(pFCSPI->CTRL, 0); +} + +LOCAL_INLINE void FCSPI_HWA_EnableDebugMode(FCSPI_Type *pFCSPI, bool enable) +{ + enable ? FCSPI_SET_BIT(pFCSPI->CTRL, FCSPI_CTRL_DBG_EN_MASK) : FCSPI_CLEAR_BIT(pFCSPI->CTRL, FCSPI_CTRL_DBG_EN_MASK); +} + +LOCAL_INLINE bool FCSPI_HWA_IsEnabled(FCSPI_Type *pFCSPI) +{ + return FCSPI_READ_BIT(pFCSPI->CTRL, FCSPI_CTRL_M_EN_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_ResetRxFIFO(FCSPI_Type *pFCSPI) +{ + FCSPI_SET_BIT(pFCSPI->CTRL, FCSPI_CTRL_RST_RF_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_ResetTxFIFO(FCSPI_Type *pFCSPI) +{ + FCSPI_SET_BIT(pFCSPI->CTRL, FCSPI_CTRL_RST_TF_MASK); +} + +/** + * @brief Set the FCSPI INT_EN register value for enable or disable some interrupts. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_EnableInterrupts(FCSPI_Type *pFCSPI, uint32_t IntsMask, bool enable) +{ + if (true == enable) + { + FCSPI_SET_BIT(pFCSPI->INT_EN, IntsMask); + } + else + { + FCSPI_CLEAR_BIT(pFCSPI->INT_EN, IntsMask); + } +} + +LOCAL_INLINE bool FCSPI_HWA_IsEnabledInterrupt(FCSPI_Type *pFCSPI, uint32_t IntMask) +{ + return FCSPI_READ_BIT(pFCSPI->INT_EN, IntMask); +} + +/** + * @brief Enable or disable the DMA feature by setting the FCSPI DMA_EN register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_EnableRxDMA(FCSPI_Type *pFCSPI, bool enable) +{ + enable ? FCSPI_SET_BIT(pFCSPI->DMA_EN, FCSPI_DMA_EN_RFDE_MASK) : FCSPI_CLEAR_BIT(pFCSPI->DMA_EN, FCSPI_DMA_EN_RFDE_MASK); +} + +LOCAL_INLINE bool FCSPI_HWA_IsEnabledRxDMA(FCSPI_Type *pFCSPI) +{ + return FCSPI_READ_BIT(pFCSPI->DMA_EN, FCSPI_DMA_EN_RFDE_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_EnableTxDMA(FCSPI_Type *pFCSPI, bool enable) +{ + enable ? FCSPI_SET_BIT(pFCSPI->DMA_EN, FCSPI_DMA_EN_TFDE_MASK) : FCSPI_CLEAR_BIT(pFCSPI->DMA_EN, FCSPI_DMA_EN_TFDE_MASK); +} + +LOCAL_INLINE bool FCSPI_HWA_IsEnabledTxDMA(FCSPI_Type *pFCSPI) +{ + return FCSPI_READ_BIT(pFCSPI->DMA_EN, FCSPI_DMA_EN_TFDE_MASK); +} + +/** + * @brief Software reset FCSPI. This operation can be done regardless of whether the module is enabled or not(CTRL.M_EN). + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + */ +LOCAL_INLINE void FCSPI_HWA_SoftwareReset(FCSPI_Type *pFCSPI) +{ + /* Disable DMA before software reset */ + FCSPI_HWA_EnableRxDMA(pFCSPI, false); + FCSPI_HWA_EnableTxDMA(pFCSPI, false); + /* Disable all SPI interrupt before software reset */ + FCSPI_HWA_EnableInterrupts(pFCSPI, FCSPI_INT_EN_MASK, false); + /* Disable module before software reset */ + FCSPI_HWA_EnableModule(pFCSPI, false); + /* software reset */ + FCSPI_SET_BIT(pFCSPI->CTRL, FCSPI_CTRL_SW_RST_MASK); + FCSPI_CLEAR_BIT(pFCSPI->CTRL, FCSPI_CTRL_SW_RST_MASK); +} + +/** + * @brief Set the FCSPI to master mode. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + */ +LOCAL_INLINE void FCSPI_HWA_SetMasterMode(FCSPI_Type *pFCSPI) +{ + FCSPI_SET_BIT(pFCSPI->CFG1, FCSPI_CFG1_MASTER_MASK); +} + +/** + * @brief Set FCSPI to slave mode. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + */ +LOCAL_INLINE void FCSPI_HWA_SetSlaveMode(FCSPI_Type *pFCSPI) +{ + FCSPI_CLEAR_BIT(pFCSPI->CFG1, FCSPI_CFG1_MASTER_MASK); +} + +/** + * @brief Check the current mode status, master or slave. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return the mode type of FCSPI, FCSPI_MODE_MASTER or FCSPI_MODE_SLAVE + */ +LOCAL_INLINE FCSPI_MasterSlaveModeType FCSPI_HWA_GetMode(FCSPI_Type *pFCSPI) +{ + return (FCSPI_MasterSlaveModeType)(FCSPI_READ_BIT(pFCSPI->CFG1, FCSPI_CFG1_MASTER_MASK)); +} + +LOCAL_INLINE void FCSPI_HWA_ClearStatus(FCSPI_Type *pFCSPI, uint32_t u32StatusMask) +{ + FCSPI_WRITE_REG(pFCSPI->STATUS, u32StatusMask); +} + +/** + * @brief Clear FCSPI STATUS register for certain function. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetStatus(FCSPI_Type *pFCSPI, uint32_t u32FlagBitMask) +{ + return FCSPI_READ_BIT(pFCSPI->STATUS, u32FlagBitMask); +} + +LOCAL_INLINE void FCSPI_HWA_EnableSckLoopback(FCSPI_Type *pFCSPI, bool enable) +{ + enable ? FCSPI_SET_BIT(pFCSPI->CFG1, FCSPI_CFG1_SCK_LB_MASK) : FCSPI_CLEAR_BIT(pFCSPI->CFG1, FCSPI_CFG1_SCK_LB_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_EnableInternalPcs(FCSPI_Type *pFCSPI, bool enable) +{ + enable ? FCSPI_SET_BIT(pFCSPI->CFG1, FCSPI_CFG1_INT_PCS_MASK) : FCSPI_CLEAR_BIT(pFCSPI->CFG1, FCSPI_CFG1_INT_PCS_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_SetPcsPolarity(FCSPI_Type *pFCSPI, FCSPI_PcsSelType PCSn, FCSPI_PcsPolarityType PcsPolarity) +{ + FCSPI_MODIFY_REG(pFCSPI->CFG1, FCSPI_CFG1_PCS_POL_MASK, (uint32_t)(PcsPolarity << PCSn) << FCSPI_CFG1_PCS_POL_SHIFT); +} + +LOCAL_INLINE void FCSPI_HWA_SetPinConfig(FCSPI_Type *pFCSPI, FCSPI_PinConfigType PinCfg) +{ + FCSPI_MODIFY_REG(pFCSPI->CFG1, FCSPI_CFG1_PIN_CFG_MASK, (uint32_t)PinCfg << FCSPI_CFG1_PIN_CFG_SHIFT); +} + +LOCAL_INLINE void FCSPI_HWA_SetOutputConfig(FCSPI_Type *pFCSPI, FCSPI_OutputConfigType OutputCfg) +{ + if (FCSPI_OUTPUT_RETAIN_LAST == OutputCfg) { + FCSPI_CLEAR_BIT(pFCSPI->CFG1, FCSPI_CFG1_OUT_CFG_MASK); + } else { + FCSPI_SET_BIT(pFCSPI->CFG1, FCSPI_CFG1_OUT_CFG_MASK); + } +} + +LOCAL_INLINE void FCSPI_HWA_SetPcsConfig(FCSPI_Type *pFCSPI, bool Is4bitMode) +{ + Is4bitMode ? FCSPI_SET_BIT(pFCSPI->CFG1, FCSPI_CFG1_PCS_CFG_MASK) : FCSPI_CLEAR_BIT(pFCSPI->CFG1, FCSPI_CFG1_PCS_CFG_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_SetSCKDIV(FCSPI_Type *pFCSPI, uint8 u8Value) +{ + FCSPI_MODIFY_REG(pFCSPI->CLK_CFG, FCSPI_CLK_CFG_SCKDIV_MASK, (uint32_t)u8Value << FCSPI_CLK_CFG_SCKDIV_SHIFT); +} + +LOCAL_INLINE void FCSPI_HWA_SetDelayPCSPCS(FCSPI_Type *pFCSPI, uint8 u8Value) +{ + FCSPI_MODIFY_REG(pFCSPI->CLK_CFG, FCSPI_CLK_CFG_PCSPCS_MASK, (uint32_t)u8Value << FCSPI_CLK_CFG_PCSPCS_SHIFT); +} + +LOCAL_INLINE void FCSPI_HWA_SetDelayPCSSCK(FCSPI_Type *pFCSPI, uint8 u8Value) +{ + FCSPI_MODIFY_REG(pFCSPI->CLK_CFG, FCSPI_CLK_CFG_PCSSCK_MASK, (uint32_t)u8Value << FCSPI_CLK_CFG_PCSSCK_SHIFT); +} + +LOCAL_INLINE void FCSPI_HWA_SetDelaySCKPCS(FCSPI_Type *pFCSPI, uint8 u8Value) +{ + FCSPI_MODIFY_REG(pFCSPI->CLK_CFG, FCSPI_CLK_CFG_SCKPCS_MASK, (uint32_t)u8Value << FCSPI_CLK_CFG_SCKPCS_SHIFT); +} + +LOCAL_INLINE void FCSPI_HWA_SetWatermarkTx(FCSPI_Type *pFCSPI, uint8 u8Value) +{ + FCSPI_MODIFY_REG(pFCSPI->FIFO_WTM, FCSPI_FIFO_WTM_TXWATER_MASK, (uint32_t)u8Value & FCSPI_FIFO_WTM_TXWATER_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_SetWatermarkRx(FCSPI_Type *pFCSPI, uint8 u8Value) +{ + FCSPI_MODIFY_REG(pFCSPI->FIFO_WTM, FCSPI_FIFO_WTM_RXWATER_MASK, + (uint32_t)(u8Value << FCSPI_FIFO_WTM_RXWATER_SHIFT) & FCSPI_FIFO_WTM_RXWATER_MASK); +} + +LOCAL_INLINE uint32 FCSPI_HWA_GetTxFIFOCnt(FCSPI_Type *pFCSPI) +{ + return (FCSPI_READ_BIT(pFCSPI->FIFO_STATUS, FCSPI_FIFO_STATUS_TXCNT_MASK)); +} + +LOCAL_INLINE uint32 FCSPI_HWA_GetRxFIFOCnt(FCSPI_Type *pFCSPI) +{ + return (FCSPI_READ_BIT(pFCSPI->FIFO_STATUS, FCSPI_FIFO_STATUS_RXCNT_MASK) >> FCSPI_FIFO_STATUS_RXCNT_SHIFT); +} + +LOCAL_INLINE void FCSPI_HWA_SetFrameSize(FCSPI_Type *pFCSPI, uint16 FrameSize) +{ + FCSPI_MODIFY_REG(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_FRM_SZ_MASK, FrameSize - 1u); +} + +LOCAL_INLINE void FCSPI_HWA_SetTransferWidth(FCSPI_Type *pFCSPI, FCSPI_TransferWidthType Width) +{ + FCSPI_MODIFY_REG(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_WIDTH_MASK, ((uint32_t)Width << FCSPI_TR_CTRL_WIDTH_SHIFT) & FCSPI_TR_CTRL_WIDTH_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_EnableTxMask(FCSPI_Type *pFCSPI, bool enable) +{ + enable ? FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_TX_MSK_MASK) : FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_TX_MSK_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_EnableRxMask(FCSPI_Type *pFCSPI, bool enable) +{ + enable ? FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_RX_MSK_MASK) : FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_RX_MSK_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_EnableCTGO(FCSPI_Type *pFCSPI, bool enable) +{ + enable ? FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_CT_GO_MASK) : FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_CT_GO_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_EnableCTEN(FCSPI_Type *pFCSPI, bool enable) +{ + enable ? FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_CT_EN_MASK) : FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_CT_EN_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_EnableByteSwap(FCSPI_Type *pFCSPI, bool enable) +{ + enable ? FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_BYSW_MASK) : FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_BYSW_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_SetDataFirstBit(FCSPI_Type *pFCSPI, FCSPI_DataFirstBitType eFirstBit) +{ + if (FCSPI_MSB_FIRST == eFirstBit) { + FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_LSBF_MASK); + } else { + FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_LSBF_MASK); + } +} + +LOCAL_INLINE void FCSPI_HWA_SelectPCS(FCSPI_Type *pFCSPI, FCSPI_PcsSelType PCSn) +{ + FCSPI_MODIFY_REG(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_PCS_MASK, (uint32_t)PCSn << FCSPI_TR_CTRL_PCS_SHIFT); +} + +LOCAL_INLINE void FCSPI_HWA_SetPrescale(FCSPI_Type *pFCSPI, FCSPI_PrescaleType PrescaleValue) +{ + FCSPI_MODIFY_REG(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_PRESCALE_MASK, ((uint32_t)PrescaleValue << FCSPI_TR_CTRL_PRESCALE_SHIFT) & FCSPI_TR_CTRL_PRESCALE_MASK); +} + +LOCAL_INLINE void FCSPI_HWA_SetSckPhase(FCSPI_Type *pFCSPI, FCSPI_SckPhaseType SckPhase) +{ + if (FCSPI_SCK_SAMPLE_FIRST_EDGE == SckPhase) { + FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_SCK_PHA_MASK); + } else { + FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_SCK_PHA_MASK); + } +} + +LOCAL_INLINE void FCSPI_HWA_SetSckPolarity(FCSPI_Type *pFCSPI, FCSPI_SckPolarityType SckPolarity) +{ + if (FCSPI_SCK_IDLE_LOW == SckPolarity) { + FCSPI_CLEAR_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_SCK_POL_MASK); + } else { + FCSPI_SET_BIT(pFCSPI->TR_CTRL, FCSPI_TR_CTRL_SCK_POL_MASK); + } +} + +LOCAL_INLINE void FCSPI_HWA_WriteTxData(FCSPI_Type *pFCSPI, uint32 TxData) +{ + FCSPI_WRITE_REG(pFCSPI->TX_DATA, TxData); +} + +LOCAL_INLINE bool FCSPI_HWA_GetFirstDataFlag(FCSPI_Type *pFCSPI) +{ + return (bool)FCSPI_READ_BIT(pFCSPI->RX_STATUS, FCSPI_RX_STATUS_FD_MASK); +} + +LOCAL_INLINE bool FCSPI_HWA_IsRxFIFOEmpty(FCSPI_Type *pFCSPI) +{ + return (bool)(FCSPI_READ_BIT(pFCSPI->RX_STATUS, FCSPI_RX_STATUS_RX_EMPTY_MASK)); +} + +LOCAL_INLINE uint32 FCSPI_HWA_ReadRxData(FCSPI_Type *pFCSPI) +{ + return FCSPI_READ_REG(pFCSPI->RX_DATA); +} + +/** @}*/ + +#endif /* #if FCSPI_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_FCPIT_H_ */ diff --git a/Inc/HwA_fcuart.h b/Inc/HwA_fcuart.h new file mode 100644 index 0000000..8ffa2ac --- /dev/null +++ b/Inc/HwA_fcuart.h @@ -0,0 +1,924 @@ +/** + * @file HwA_fcuart.h + * @author Flagchip + * @brief FCUart register API + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip055 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip122 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_FCUART_H_ +#define _HWA_FCUART_H_ + +#include "device_header.h" + +#if FCUART_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_fcuart HwA_fcuart + * @ingroup module_driver_fcuart + * @{ + */ + + +/********* Local typedef ************/ + +/** + * @brief UART STAT register flag + * + */ +typedef enum +{ + FCUART_STAT_LBKDIF = FCUART_STAT_LBKDIF_MASK, /**< FCUART_STAT_LBKDIF LIN Break Detect Interrupt Flag, w1c */ + FCUART_STAT_RPAEIF = FCUART_STAT_RPAEIF_MASK, /**< FCUART_STAT_RPAEIF RXD Pin Active Edge Interrupt Flag, w1c */ + FCUART_STAT_MSBF = FCUART_STAT_MSBF_MASK, /**< FCUART_STAT_MSBF MSB First, RW */ + FCUART_STAT_RXINV = FCUART_STAT_RXINV_MASK, /**< FCUART_STAT_RXINV Receive Data Inversion, RW */ + FCUART_STAT_RWUID = FCUART_STAT_RWUID_MASK, /**< FCUART_STAT_RWUID Receive Wake Up Idle Detect, RW */ + FCUART_STAT_BCGL = FCUART_STAT_BCGL_MASK, /**< FCUART_STAT_BCGL Break Character Generation Length, RW */ + FCUART_STAT_LBKDE = FCUART_STAT_LBKDE_MASK, /**< FCUART_STAT_LBKDE LIN Break Detection Enable, RW */ + FCUART_STAT_RAF = FCUART_STAT_RAF_MASK, /**< FCUART_STAT_RAF Receiver Active Flag, RO */ + FCUART_STAT_TDREF = FCUART_STAT_TDREF_MASK, /**< FCUART_STAT_TDREF Transmit Data Register Empty Flag, RO */ + FCUART_STAT_TCF = FCUART_STAT_TCF_MASK, /**< FCUART_STAT_TCF Transmission Complete Flag, RO */ + FCUART_STAT_RDRFF = FCUART_STAT_RDRFF_MASK, /**< FCUART_STAT_RDRFF Receive Data Register Full Flag, RO */ + FCUART_STAT_IDLEF = FCUART_STAT_IDLEF_MASK, /**< FCUART_STAT_IDLEF Idle Line Flag, w1c */ + FCUART_STAT_RORF = FCUART_STAT_RORF_MASK, /**< FCUART_STAT_RORF Receiver Overrun Flag, w1c */ + FCUART_STAT_NF = FCUART_STAT_NF_MASK, /**< FCUART_STAT_NF Noise Flag, w1c */ + FCUART_STAT_FEF = FCUART_STAT_FEF_MASK, /**< FCUART_STAT_FEF Frame Error Flag, w1c */ + FCUART_STAT_PEF = FCUART_STAT_PEF_MASK, /**< FCUART_STAT_PEF Parity Error Flag, w1c */ + FCUART_STAT_M0F = FCUART_STAT_M0F_MASK, /**< FCUART_STAT_M0F Match address 0 Flag, w1c */ + FCUART_STAT_M1F = FCUART_STAT_M1F_MASK, /**< FCUART_STAT_M1F Match address 1 Flag, w1c */ + FCUART_STAT_RPEF = FCUART_STAT_RPEF_MASK, /**< FCUART_STAT_RPEF Receive Data Parity Error Flag, w1c */ + FCUART_STAT_TPEF = FCUART_STAT_TPEF_MASK /**< FCUART_STAT_TPEF Transmit Data Parity Error Flag, w1c */ +} FCUART_StatType; + +/** + * @brief UART data bit length mode + * + */ +typedef enum +{ + UART_BITMODE_8 = 0, /**< UART_BITMODE_8 */ + UART_BITMODE_9 /**< UART_BITMODE_9 */ +} FCUART_BitModeType; + +/** + * @brief UART stop bits number + * + */ +typedef enum +{ + UART_STOPBIT_NUM_1 = 0, /**< UART_STOPBIT_NUM_1 */ + UART_STOPBIT_NUM_2 /**< UART_STOPBIT_NUM_2 */ +} FCUART_StopBitNumType; + +/** + * @brief UART parity check type + * + */ +typedef enum +{ + UART_PARITY_EVEN = 0, /**< UART_PARITY_EVEN */ + UART_PARITY_ODD /**< UART_PARITY_ODD */ +} FCUART_ParityType; + + + + +/********* Local inline function ************/ +/** + * @brief Get Stat Flag + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_SetSoftWareReset(FCUART_Type *pUart) +{ + pUart->RST |= FCUART_RST_RST_MASK; + pUart->RST &= ~FCUART_RST_RST_MASK; +} + +/** + * @brief Get Stat Flag + * + * @param pUart UART instance value + * @param eStatusType stat type + * @return FCUART STAT status flag + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetStatus(FCUART_Type *pUart, FCUART_StatType eStatusType) +{ + return (pUart->STAT & (uint32_t)eStatusType); +} + +/** + * @brief Clear Stat Flag + * + * @param pUart UART instance value + * @param u32StatusType stat type + */ +LOCAL_INLINE void FCUART_HWA_ClearStatus(FCUART_Type *pUart, uint32_t u32StatusType) +{ + pUart->STAT = (u32StatusType | (pUart->STAT & FCUART_CHANGE_MASK)); +} + +/** + * @brief Enable Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableInterrupt(FCUART_Type *pUart, uint32 u32Value) +{ + pUart->CTRL |= u32Value; /* Interrupt Enable */ +} + +/** + * @brief Disable Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableInterrupt(FCUART_Type *pUart, uint32 u32Value) +{ + pUart->CTRL &= ~u32Value; /* Interrupt Disable */ +} + +/** + * @brief Enable Receive Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableReceiveInterrupt(FCUART_Type *pUart) +{ + pUart->CTRL |= FCUART_CTRL_RIE_MASK; /* Receive Interrupt Enable */ +} + +/** + * @brief Disable Receive Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableReceiveInterrupt(FCUART_Type *pUart) +{ + pUart->CTRL &= ~FCUART_CTRL_RIE_MASK; /* Receive Interrupt Enable */ + +} + +/** + * @brief Enable Error Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableErrorInterrupt(FCUART_Type *pUart) +{ + pUart->CTRL |= FCUART_CTRL_ORIE_MASK | /* Overrun Interrupt Enable */ + FCUART_CTRL_NEIE_MASK | /* Noise Error Interrupt Enable */ + FCUART_CTRL_FEIE_MASK | /* Frame Error Interrupt Enable */ + FCUART_CTRL_PEIE_MASK; /* Parity Error Interrupt Enable */ +} + +/** + * @brief Disable Error Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableErrorInterrupt(FCUART_Type *pUart) +{ + pUart->CTRL &= ~(FCUART_CTRL_ORIE_MASK | /* Overrun Interrupt Enable */ + FCUART_CTRL_NEIE_MASK | /* Noise Error Interrupt Enable */ + FCUART_CTRL_FEIE_MASK | /* Frame Error Interrupt Enable */ + FCUART_CTRL_PEIE_MASK); /* Parity Error Interrupt Enable */ + +} + +/** + * @brief Set FCUART Ctrl register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetCtrl(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->CTRL = u32Value; +} + +/** + * @brief Get FCUART Ctrl register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetCtrl(FCUART_Type *pUart) +{ + return pUart->CTRL; +} + +/** + * @brief Attach FCUART Ctrl register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachCtrl(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->CTRL |= u32Value; +} + +/** + * @brief Set FCUART Baud register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetBaud(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->BAUD = u32Value; +} + +/** + * @brief Get FCUART baud register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetBaud(FCUART_Type *pUart) +{ + return pUart->BAUD; +} + +/** + * @brief Attach FCUART Baud register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachBaud(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->BAUD |= u32Value; +} + +/** + * @brief Set FCUART Fifo register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetFifo(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->FIFO = u32Value; +} + +/** + * @brief Get FCUART fifo register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetFifo(FCUART_Type *pUart) +{ + return pUart->FIFO; +} + +/** + * @brief Flush FCUART Tx Rx Fifo register + * + * @param pUart UART instance value + */ + LOCAL_INLINE void FCUART_HWA_FlushTxRxFifo(FCUART_Type *pUart) + { + pUart->FIFO |= (FCUART_FIFO_TXFLUSH_MASK | + FCUART_FIFO_RXFLUSH_MASK); + } + +/** + * @brief Get FCUART fifo register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE bool FCUART_HWA_GetEnStatusRxFifo(FCUART_Type *pUart) +{ + return ((((pUart->FIFO & FCUART_FIFO_RXFEN_MASK) >> FCUART_FIFO_RXFEN_SHIFT) == 1U) ? true: false); +} + +/** + * @brief Get FCUART fifo register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE bool FCUART_HWA_GetEnStatusTxFifo(FCUART_Type *pUart) +{ + return ((((pUart->FIFO & FCUART_FIFO_TXFEN_MASK) >> FCUART_FIFO_TXFEN_SHIFT) == 1U) ? true: false); +} + +/** + * @brief Attach FCUART Fifo register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachFifo(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->FIFO |= u32Value; +} + +/** + * @brief Set FCUART WaterMark register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetWaterMark(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->WATERMARK = u32Value; +} + +/** + * @brief Get FCUART Rx WaterMark + * + * @param pUart UART instance value + * @return Rxcount value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetRxWaterMark(FCUART_Type *pUart) +{ + return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_RXWATER_MASK) >> FCUART_WATERMARK_RXWATER_SHIFT)); +} + +/** + * @brief Get FCUART Tx WaterMark + * + * @param pUart UART instance value + * @return Rxcount value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetTxWaterMark(FCUART_Type *pUart) +{ + return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_TXWATER_MASK) >> FCUART_WATERMARK_TXWATER_SHIFT)); +} + +/** + * @brief Get FCUART WaterMark Rxcount + * + * @param pUart UART instance value + * @return Rxcount value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetFifoRxCount(FCUART_Type *pUart) +{ + return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_RXCOUNT_MASK) >> FCUART_WATERMARK_RXCOUNT_SHIFT)); +} + +/** + * @brief Get FCUART WaterMark Txcount + * + * @param pUart UART instance value + * @return Rxcount value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetFifoTxCount(FCUART_Type *pUart) +{ + return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_TXCOUNT_MASK) >> FCUART_WATERMARK_TXCOUNT_SHIFT)); +} + +/** + * @brief Attach FCUART WaterMark register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachWaterMark(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->WATERMARK |= u32Value; +} + +/** + * @brief Set FCUART Match register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetMatch(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->MATCH = u32Value; +} + +/** + * @brief Attach FCUART Match register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachMatch(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->MATCH |= u32Value; +} + +/** + * @brief Get FCUART Match register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetMatch(FCUART_Type *pUart) +{ + return pUart->MATCH; +} + +/** + * @brief Read FCUART STAT register + * + * @param pUart UART instance value + * @return STAT read value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetSTAT(FCUART_Type *pUart) +{ + return pUart->STAT; +} + +/** + * @brief Write 1 Clear FCUART STAT register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_WriteClearSTAT(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->STAT = ((pUart->STAT & FCUART_CHANGE_MASK) | u32Value); +} + +/** + * @brief Set Bit Mode and Parity + * + * @param pUart UART instance value + * @param eBitMode is bit mode, 8 or 9 bits + */ +LOCAL_INLINE void FCUART_HWA_SetBitMode(FCUART_Type *pUart, FCUART_BitModeType eBitMode) +{ + uint32_t u32RegVal = pUart->CTRL; + pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_BMSEL_MASK)) | FCUART_CTRL_BMSEL(eBitMode)); +} + +/** + * @brief Set Bit Mode and Parity + * + * @param pUart UART instance value + * @param bParityEnable If enable Parity, set 1U, or set 0U + * @param eParityType Parity type, odd-even + */ +LOCAL_INLINE void FCUART_HWA_SetParity(FCUART_Type *pUart, FCUART_ParityType eParityType, bool bParityEnable) +{ + uint32_t u32RegVal = pUart->CTRL; + pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_PE_MASK | FCUART_CTRL_PT_MASK)) | + FCUART_CTRL_PE(bParityEnable) | + FCUART_CTRL_PT(eParityType) ); +} + +/** + * @brief Set Bit Mode and Parity + * + * @param pUart UART instance value + * @param eStopBit stop bits number 1 or 2 bits + */ +LOCAL_INLINE void FCUART_HWA_SetStopBit(FCUART_Type *pUart, FCUART_StopBitNumType eStopBit) +{ + uint32_t u32RegVal = pUart->BAUD; + pUart->BAUD = ((u32RegVal & (~ FCUART_BAUD_SBNS_MASK)) | FCUART_BAUD_SBNS(eStopBit)); +} + +/** + * @brief Enable Receive DMA + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableReceiveDMA(FCUART_Type *pUart) +{ + pUart->BAUD |= FCUART_BAUD_RDMAEN_MASK; +} + +/** + * @brief Disable Receive DMA + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableReceiveDMA(FCUART_Type *pUart) +{ + pUart->BAUD &= ~FCUART_BAUD_RDMAEN_MASK; + +} + +/** + * @brief Enable Receive FIFO + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableReceiveFIFO(FCUART_Type *pUart) +{ + pUart->FIFO |= FCUART_FIFO_RXFEN_MASK; +} + +/** + * @brief Disable Receive FIFO + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableReceiveFIFO(FCUART_Type *pUart) +{ + pUart->FIFO &= ~FCUART_FIFO_RXFEN_MASK; + +} + +/** + * @brief Clear Fifo Overflow/Underflow flag + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_ClearFIFOErrorFlag(FCUART_Type *pUart) +{ + pUart->FIFO |= FCUART_FIFO_TXOF_MASK | FCUART_FIFO_RXUF_MASK; +} + +/** + * @brief Set FCUART Tx WaterMark + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_SetTxWaterMark(FCUART_Type *pUart, uint8_t u8Value) +{ + uint32_t u32Value = 0; + u32Value = pUart->WATERMARK & (~(uint32_t)FCUART_WATERMARK_TXWATER_MASK); + u32Value |= FCUART_WATERMARK_TXWATER(u8Value); + pUart->WATERMARK = u32Value; +} + +/** + * @brief Set FCUART Rx WaterMark + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_SetRxWaterMark(FCUART_Type *pUart, uint8_t u8Value) +{ + uint32_t u32Value = 0; + u32Value = pUart->WATERMARK & (~(uint32_t)FCUART_WATERMARK_RXWATER_MASK); + u32Value |= FCUART_WATERMARK_RXWATER(u8Value); + pUart->WATERMARK = u32Value; +} + + +/** + * @brief Set Data Value + * + * @param pUart UART instance value + * @param u32Data Set data + */ +LOCAL_INLINE void FCUART_HWA_SetData(FCUART_Type *pUart, uint32_t u32Data) +{ + pUart->DATA = u32Data; /* data 32 bit */ +} + +/** + * @brief Get Data Value + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetData(FCUART_Type *pUart) +{ + uint8_t u8Data; + + u8Data = *((volatile uint8_t *)&pUart->DATA); /* data 32 bit */ + + return u8Data; +} + + +/** + * @brief Get Data Value with check frame error flag + * + * @param pUart UART instance value + * @param data Received data + * @return the frame error exist or not + */ +LOCAL_INLINE bool FCUART_HWA_GetDataWithFef(FCUART_Type *pUart, uint8_t *data) +{ + uint32_t u32Val; + u32Val = pUart->DATA; + *data = (uint8_t)u32Val; + return ((u32Val & FCUART_DATA_FETSC_MASK) == FCUART_DATA_FETSC_MASK) ? true : false; +} + +/** + * @brief Set R8T9 bit + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE void FCUART_HWA_SetR8T9(FCUART_Type *pUart, uint8_t u8Data) +{ + uint32_t u32RegVal = pUart->CTRL; + pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_R8T9_MASK)) | FCUART_CTRL_R8T9(u8Data)); +} + +/** + * @brief Get R8T9 bit + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetR8T9(FCUART_Type *pUart) +{ + return (uint8_t)((pUart->CTRL & FCUART_CTRL_R8T9_MASK) >> FCUART_CTRL_R8T9_SHIFT); +} + +/** + * @brief Set R9T8 bit + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE void FCUART_HWA_SetR9T8(FCUART_Type *pUart, uint8_t u8Data) +{ + uint32_t u32RegVal = pUart->CTRL; + pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_R9T8_MASK)) | FCUART_CTRL_R9T8(u8Data)); +} + +/** + * @brief Get R9T8 bit + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetR9T8(FCUART_Type *pUart) +{ + return (uint8_t)((pUart->CTRL & FCUART_CTRL_R9T8_MASK) >> FCUART_CTRL_R9T8_SHIFT); +} + +/** + * @brief Reset the instance by software. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_SoftwareReset(FCUART_Type *pUart) +{ + pUart->RST |= FCUART_RST_RST_MASK; + pUart->RST &= ~FCUART_RST_RST_MASK; +} + +/** + * @brief Set fcuart TX Transfer enable or disable. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetTxTransfer(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->CTRL |= FCUART_CTRL_TE_MASK; + } + else + { + pUart->CTRL &= ~FCUART_CTRL_TE_MASK; + } +} + +/** + * \brief Start transmit + * + * \param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_StartTransmit(FCUART_Type *pUart) +{ + pUart->CTRL |= FCUART_CTRL_TE_MASK; /* start transmit */ +} + + +/** + * @brief Set fcuart RX Transfer enable or disable. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetRxTransfer(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->CTRL |= FCUART_CTRL_RE_MASK; + } + else + { + pUart->CTRL &= ~FCUART_CTRL_RE_MASK; + } +} + +/** + * @brief Set fcuart start transfer. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_StartTransfer(FCUART_Type *pUart) +{ + pUart->CTRL |= (uint32_t)(FCUART_CTRL_TE_MASK | FCUART_CTRL_RE_MASK); +} + + +/** + * @brief Set fcuart stop transfer. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_StopTransfer(FCUART_Type *pUart) +{ + pUart->CTRL &= ~(uint32_t)(FCUART_CTRL_TE_MASK | FCUART_CTRL_RE_MASK); +} + +/** + * @brief Set lin break detect interrupt. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetLinBreakDetectInterrupt(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->BAUD |= FCUART_BAUD_LBKDIE_MASK; + } + else + { + pUart->BAUD &= ~FCUART_BAUD_LBKDIE_MASK; + } +} + +/** + * @brief Set lin break detect feature enable. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetLinBreakDetectEnable(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + + pUart->STAT = ((FCUART_STAT_LBKDE_MASK | FCUART_STAT_BCGL_MASK)|(pUart->STAT & FCUART_CHANGE_MASK)); + } + else + { + pUart->STAT &= ((~(FCUART_STAT_LBKDE_MASK | FCUART_STAT_BCGL_MASK))&FCUART_CHANGE_MASK); + } +} + +/** + * @brief Send a lin break field. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_SendBreakField(FCUART_Type *pUart) +{ + pUart->DATA = FCUART_DATA_FETSC_MASK; +} + +/** + * @brief Set uart receive active interrupt. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetReceiveActiveInterrupt(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->BAUD |= FCUART_BAUD_RIAEIE_MASK; + } + else + { + pUart->BAUD &= ~FCUART_BAUD_RIAEIE_MASK; + } +} + +/** + * @brief Set uart receive active interrupt. + * + * @param pUart UART instance value + * @param return false for disable, true for enable. + */ +LOCAL_INLINE bool FCUART_HWA_GetReceiveActiveInterrupt(FCUART_Type *pUart) +{ + bool bRetVal = false; + + if (0U != (pUart->BAUD & FCUART_BAUD_RIAEIE_MASK)) + { + bRetVal = true; + } + + return bRetVal; +} + +/** + * @brief Set FCUART inverse feature. + * + * @param pUart UART instance value + * @param bEnable false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetReceiveDataInverse(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->STAT = (FCUART_STAT_RXINV_MASK | (pUart->STAT & FCUART_CHANGE_MASK)); + } + else + { + pUart->STAT &= ((~FCUART_STAT_RXINV_MASK)&FCUART_CHANGE_MASK); + } +} + +/** + * @brief Get the FCUART inverse bit value. + * + * @param pUart UART instance value + * @param return false for disable, true for enable. + */ +LOCAL_INLINE bool FCUART_HWA_GetReceiveDataInverse(FCUART_Type *pUart) +{ + bool bRetVal = false; + + if (0U != (pUart->STAT & FCUART_STAT_RXINV_MASK)) + { + bRetVal = true; + } + + return bRetVal; +} + +/** + * @brief Set the FCUART frame error interrupt. + * + * @param pUart UART instance value + * @param bEnable false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetFrameErrorInterrupt(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->CTRL |= FCUART_CTRL_FEIE_MASK; + } + else + { + pUart->CTRL &= ~FCUART_CTRL_FEIE_MASK; + } +} + +/** + * @brief Enable the FCUART loop mode. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableLoopMode(FCUART_Type *pUart) +{ + pUart->CTRL |= FCUART_CTRL_LOOPMS_MASK; +} + +/** + * @brief Disable the FCUART loop mode. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableLoopMode(FCUART_Type *pUart) +{ + pUart->CTRL &= ~FCUART_CTRL_LOOPMS_MASK; +} + +/** + * \brief Set FCUART MODIR value + * + * \param pUart UART instance value + * \param u32Data Set data + */ +LOCAL_INLINE void FCUART_HWA_SetModir(FCUART_Type *pUart, uint32_t u32Data) +{ + pUart->HFCR = u32Data; /* data 32 bit */ +} + +/** + * \brief Get FCUART MODIR value + * + * \param pUart UART instance value + * \param u32Data Get data + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetModir(FCUART_Type *pUart) +{ + return pUart->HFCR ; +} + +/** @}*/ + +#endif + +#endif /* end for #ifndef _HWA_FCUART_H_ */ diff --git a/Inc/HwA_flexcan.h b/Inc/HwA_flexcan.h new file mode 100644 index 0000000..5eeb2d4 --- /dev/null +++ b/Inc/HwA_flexcan.h @@ -0,0 +1,2096 @@ +/** + * @file HwA_flexcan.h + * @author Flagchip + * @brief FLEXCAN hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip038 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip120 N/A Change version and release + * 2.1.0 2025-02-19 Flagchip038 N/A SRR bit must be same to IDE + * 2.2.0 2025-02-20 Flagchip038 N/A Fix 96MBs mb address calculation issue + ******************************************************************************** */ + +#ifndef _HWA_FLEXCAN_H_ +#define _HWA_FLEXCAN_H_ + +#include "device_header.h" + + +#if FLEXCAN_INSTANCE_COUNT > 0U + + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + +/******************************* Message Buffer Structure **************************************/ + +/************************************************* 8bytes data ********************************************************/ +/* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 */ +/* 0x00 | EDL | BRS | ESI | | CODE | | SRR | IDE | RTR | DLC | TIME STAMP | */ +/* 0x04 | PRIO | ID (STD/EXT high 11bits) | ID (EXT low 18bits) | */ +/* 0x08 | Data Byte 0 | Data Byte 1 | Data Byte 2 | Data Byte 3 | */ +/* 0x0C | Data Byte 4 | Data Byte 5 | Data Byte 6 | Data Byte 7 | */ + + +/************************************************* 16bytes data *******************************************************/ +/* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 */ +/* 0x00 | EDL | BRS | ESI | | CODE | | SRR | IDE | RTR | DLC | TIME STAMP | */ +/* 0x04 | PRIO | ID (STD/EXT high 11bits) | ID (EXT low 18bits) | */ +/* 0x08 | Data Byte 0 | Data Byte 1 | Data Byte 2 | Data Byte 3 | */ +/* 0x0C | Data Byte 4 | Data Byte 5 | Data Byte 6 | Data Byte 7 | */ +/* ................................ */ +/* 0x1C | Data Byte 12 | Data Byte 13 | Data Byte 14 | Data Byte 15| */ + + +/************************************************* 32bytes data *******************************************************/ +/* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 */ +/* 0x00 | EDL | BRS | ESI | | CODE | | SRR | IDE | RTR | DLC | TIME STAMP | */ +/* 0x04 | PRIO | ID (STD/EXT high 11bits) | ID (EXT low 18bits) | */ +/* 0x08 | Data Byte 0 | Data Byte 1 | Data Byte 2 | Data Byte 3 | */ +/* 0x0C | Data Byte 4 | Data Byte 5 | Data Byte 6 | Data Byte 7 | */ +/* ................................ */ +/* 0x30 | Data Byte 28 | Data Byte 29 | Data Byte 30 | Data Byte 31| */ + + +/************************************************* 64bytes data *******************************************************/ +/* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 */ +/* 0x00 | EDL | BRS | ESI | | CODE | | SRR | IDE | RTR | DLC | TIME STAMP | */ +/* 0x04 | PRIO | ID (STD/EXT high 11bits) | ID (EXT low 18bits) | */ +/* 0x08 | Data Byte 0 | Data Byte 1 | Data Byte 2 | Data Byte 3 | */ +/* 0x0C | Data Byte 4 | Data Byte 5 | Data Byte 6 | Data Byte 7 | */ +/* ................................ */ +/* 0x44 | Data Byte 60 | Data Byte 61 | Data Byte 62 | Data Byte 63| */ + + +/** + * @defgroup HwA_flexcan HwA_flexcan + * @ingroup module_driver_flexcan + * @{ + */ + + +/* Register address with offset */ +#define FLEXCAN_REGISTER_WITHOFFSET2(reg,offset1) ((uint32_t)(reg)+(uint32_t)(offset1)) +/* Register address with offset */ +#define FLEXCAN_REGISTER_WITHOFFSET(reg,offset1,offset2) ((uint32_t)(reg)+(uint32_t)(offset1)+(uint32_t)(offset2)) +/* Get register value */ +#define FLEXCAN_REG32_CONTENT(reg) (*((uint32_t*)(reg))) + + + + +/** @brief U32 value around */ +#define FLEXCAN_U32MACRO(var) ((uint32_t)(var)) +/** @brief U32 value shift */ +#define FLEXCAN_U32SHIFT(var,mask,shift) ((uint32_t)((((uint32_t)(var))&(mask))<<(shift))) +/** @brief U32 value shift and revert */ +#define FLEXCAN_U32NOTSHIFT(mask,shift) ((uint32_t)(~(((uint32_t)(mask))<<(shift)))) + +/** @breif Flexcan SRR bit mask */ +#define FLEXCAN_MB_SRR_MASK_U32 0x00400000U + +/* legacy message buffer */ + +/** one region contains 32MBs */ +#define FLEXCAN_ONE_REGION_SIZE 0x200U + +/** @brief Legacy/EnHanced Message Buffer Header */ +#define FLEXCAN_MB_HEADER_BYTELEN 8UL +/** @brief Legacy Message Buffer Address */ +#define FLEXCAN_MB_ADDR(mbOffset, mbIndex, dataLen) ( \ + (dataLen<=8)? \ + (\ + FLEXCAN_U32MACRO(FLEXCAN_U32MACRO(mbOffset)+FLEXCAN_U32MACRO(mbIndex)*(FLEXCAN_U32MACRO(dataLen)+FLEXCAN_MB_HEADER_BYTELEN)) \ + )\ + : \ + (\ + (dataLen==16)? \ + (\ + (mbIndex<21)?\ + (\ + FLEXCAN_U32MACRO(FLEXCAN_U32MACRO(mbOffset)+FLEXCAN_U32MACRO(mbIndex)*(FLEXCAN_U32MACRO(dataLen)+FLEXCAN_MB_HEADER_BYTELEN)) \ + )\ + :( \ + (mbIndex<42)?\ + (\ + FLEXCAN_U32MACRO((FLEXCAN_U32MACRO(mbOffset)+FLEXCAN_ONE_REGION_SIZE)+FLEXCAN_U32MACRO(mbIndex-21)*(FLEXCAN_U32MACRO(dataLen)+FLEXCAN_MB_HEADER_BYTELEN)) \ + )\ + :\ + (\ + FLEXCAN_U32MACRO((FLEXCAN_U32MACRO(mbOffset)+FLEXCAN_ONE_REGION_SIZE*2)+FLEXCAN_U32MACRO(mbIndex-42)*(FLEXCAN_U32MACRO(dataLen)+FLEXCAN_MB_HEADER_BYTELEN)) \ + )\ + )\ + )\ + :\ + (\ + (dataLen ==32)? \ + (\ + (mbIndex<12)?\ + (\ + FLEXCAN_U32MACRO(FLEXCAN_U32MACRO(mbOffset)+FLEXCAN_U32MACRO(mbIndex)*(FLEXCAN_U32MACRO(dataLen)+FLEXCAN_MB_HEADER_BYTELEN)) \ + )\ + :( \ + (mbIndex<24)?\ + (\ + FLEXCAN_U32MACRO((FLEXCAN_U32MACRO(mbOffset)+FLEXCAN_ONE_REGION_SIZE)+FLEXCAN_U32MACRO(mbIndex-12)*(FLEXCAN_U32MACRO(dataLen)+FLEXCAN_MB_HEADER_BYTELEN)) \ + )\ + :\ + (\ + FLEXCAN_U32MACRO((FLEXCAN_U32MACRO(mbOffset)+FLEXCAN_ONE_REGION_SIZE*2)+FLEXCAN_U32MACRO(mbIndex-24)*(FLEXCAN_U32MACRO(dataLen)+FLEXCAN_MB_HEADER_BYTELEN)) \ + )\ + )\ + )\ + : \ + (\ + (mbIndex<7)?\ + (\ + FLEXCAN_U32MACRO(FLEXCAN_U32MACRO(mbOffset)+FLEXCAN_U32MACRO(mbIndex)*(FLEXCAN_U32MACRO(dataLen)+FLEXCAN_MB_HEADER_BYTELEN)) \ + )\ + : ( \ + (mbIndex<14)?\ + (\ + FLEXCAN_U32MACRO((FLEXCAN_U32MACRO(mbOffset)+FLEXCAN_ONE_REGION_SIZE)+FLEXCAN_U32MACRO(mbIndex-7)*(FLEXCAN_U32MACRO(dataLen)+FLEXCAN_MB_HEADER_BYTELEN)) \ + )\ + :\ + (\ + FLEXCAN_U32MACRO((FLEXCAN_U32MACRO(mbOffset)+FLEXCAN_ONE_REGION_SIZE*2)+FLEXCAN_U32MACRO(mbIndex-14)*(FLEXCAN_U32MACRO(dataLen)+FLEXCAN_MB_HEADER_BYTELEN)) \ + )\ + )\ + )\ + )\ + )\ + ) + + + + +/** @brief Legacy Message Buffer word n Address */ +#define FLEXCAN_MB_WORDN_ADDR(mbOffset, mbIndex, dataLen, offset) (FLEXCAN_MB_ADDR((mbOffset), (mbIndex), (dataLen))+FLEXCAN_U32MACRO(offset)) + +/** @brief check mb data length */ +#define FLEXCAN_MB_GET_DATALEN(mbindex, mbNum, datalenNum, datalenarray) ((uint8_t)(datalenarray[( ((mbindex)*(datalenNum)/(mbNum)) )])) + +/** @brief Legacy Message Buffer Data Address */ +/* #define FLEXCAN_MB_DATA_ADDR_GET(mbOffset, mbIndex, dataLen) (FLEXCAN_MB_WORDN_ADDR((mbOffset), (mbIndex), (dataLen),2U)) */ + +/** @brief Legacy Message Buffer EDL Get */ +#define FLEXCAN_MB_EDL_GET(edlAddr) ((FLEXCAN_REG32_CONTENT(edlAddr)>>31)&0x01U) +/** @brief Legacy Message Buffer EDL Clear */ +#define FLEXCAN_MB_EDL_CLR(edlAddr) (FLEXCAN_REG32_CONTENT(edlAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,31)) +/** @brief Legacy Message Buffer EDL Attach */ +#define FLEXCAN_MB_EDL_ATTACH(edlAddr,var) (FLEXCAN_REG32_CONTENT(edlAddr) |= FLEXCAN_U32SHIFT(var,0x01U,31)) +/** @brief Legacy Message Buffer EDL Set */ +#define FLEXCAN_MB_EDL_SET(edlAddr,var) FLEXCAN_REG32_CONTENT(edlAddr) = ((FLEXCAN_REG32_CONTENT(edlAddr) & FLEXCAN_U32NOTSHIFT(0x01U,31)) | FLEXCAN_U32SHIFT(var,0x01U,31)) + + +/** @brief Legacy Message Buffer BRS Get */ +#define FLEXCAN_MB_BRS_GET(brsAddr) (((FLEXCAN_REG32_CONTENT(brsAddr))>>30)&0x01U) +/** @brief Legacy Message Buffer BRS Clear */ +#define FLEXCAN_MB_BRS_CLR(brsAddr) (FLEXCAN_REG32_CONTENT(brsAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,30)) +/** @brief Legacy Message Buffer BRS Attach */ +#define FLEXCAN_MB_BRS_ATTACH(brsAddr,var) (FLEXCAN_REG32_CONTENT(brsAddr) |= FLEXCAN_U32SHIFT(var,0x01U,30)) +/** @brief Legacy Message Buffer BRS set */ +#define FLEXCAN_MB_BRS_SET(brsAddr,var) FLEXCAN_REG32_CONTENT(brsAddr) = ((FLEXCAN_REG32_CONTENT(brsAddr) & FLEXCAN_U32NOTSHIFT(0x01U,30)) | FLEXCAN_U32SHIFT(var,0x01U,30)) + +/** @brief Legacy Message Buffer ESI Get */ +#define FLEXCAN_MB_ESI_GET(esiAddr) (((FLEXCAN_REG32_CONTENT(esiAddr))>>29)&0x01U) +/** @brief Legacy Message Buffer ESI Clear */ +#define FLEXCAN_MB_ESI_CLR(esiAddr) (FLEXCAN_REG32_CONTENT(esiAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,29)) +/** @brief Legacy Message Buffer ESI Attach */ +#define FLEXCAN_MB_ESI_ATTACH(esiAddr,var) (FLEXCAN_REG32_CONTENT(esiAddr) |= FLEXCAN_U32SHIFT(var,0x01U,29)) +/** @brief Legacy Message Buffer ESI Set */ +#define FLEXCAN_MB_ESI_SET(esiAddr,var) FLEXCAN_REG32_CONTENT(esiAddr) = ((FLEXCAN_REG32_CONTENT(esiAddr) & FLEXCAN_U32NOTSHIFT(0x01U,29)) | FLEXCAN_U32SHIFT(var,0x01U,29)) + +/** @brief Legacy Message Buffer CODE Get */ +#define FLEXCAN_MB_CODE_GET(codeAddr) (((FLEXCAN_REG32_CONTENT(codeAddr))>>24)&0x0EU) +/** @brief Legacy Message Buffer CODE Clear */ +#define FLEXCAN_MB_CODE_CLR(codeAddr) (FLEXCAN_REG32_CONTENT(codeAddr) &= FLEXCAN_U32NOTSHIFT(0x0FU,24)) +/** @brief Legacy Message Buffer CODE Attach */ +#define FLEXCAN_MB_CODE_ATTACH(codeAddr,var) (FLEXCAN_REG32_CONTENT(codeAddr) |= FLEXCAN_U32SHIFT(var,0x0FU,24)) +/** @brief Legacy Message Buffer CODE set */ +#define FLEXCAN_MB_CODE_SET(codeAddr,var) FLEXCAN_REG32_CONTENT(codeAddr) = ((FLEXCAN_REG32_CONTENT(codeAddr) & FLEXCAN_U32NOTSHIFT(0x0FU,24)) | FLEXCAN_U32SHIFT(var,0x0FU,24)) + + +/** @brief Legacy Message Buffer SRR Get */ +#define FLEXCAN_MB_SRR_GET(srrAddr) (((FLEXCAN_REG32_CONTENT(srrAddr)) >>22)&0x01U) +/** @brief Legacy Message Buffer SRR Clear */ +#define FLEXCAN_MB_SRR_CLR(srrAddr) (FLEXCAN_REG32_CONTENT(srrAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,22)) +/** @brief Legacy Message Buffer SRR Attach */ +#define FLEXCAN_MB_SRR_ATTACH(srrAddr,var) (FLEXCAN_REG32_CONTENT(srrAddr) |= FLEXCAN_U32SHIFT(var,0x01U,22)) +/** @brief Legacy Message Buffer SRR set */ +#define FLEXCAN_MB_SRR_SET(srrAddr,var) FLEXCAN_REG32_CONTENT(srrAddr) = ((FLEXCAN_REG32_CONTENT(srrAddr) & FLEXCAN_U32NOTSHIFT(0x0FU,22)) | FLEXCAN_U32SHIFT(var,0x0FU,22)) + +/** @brief Legacy Message Buffer IDE Get */ +#define FLEXCAN_MB_IDE_GET(ideAddr) (((FLEXCAN_REG32_CONTENT(ideAddr))>>21)&0x01U) +/** @brief Legacy Message Buffer IDE Clear */ +#define FLEXCAN_MB_IDE_CLR(ideAddr) (FLEXCAN_REG32_CONTENT(ideAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,21)) +/** @brief Legacy Message Buffer IDE Attach */ +#define FLEXCAN_MB_IDE_ATTACH(ideAddr,var) (FLEXCAN_REG32_CONTENT(ideAddr) |= FLEXCAN_U32SHIFT(var,0x01U,21)) +/** @brief Legacy Message Buffer IDE set with SRR */ +#define FLEXCAN_MB_IDE_SRR_SET(ideAddr,var) FLEXCAN_REG32_CONTENT(ideAddr) = ((FLEXCAN_REG32_CONTENT(ideAddr) & FLEXCAN_U32NOTSHIFT(0x03U,21)) | FLEXCAN_U32SHIFT(var,0x03U,21)) + + +/** @brief Legacy Message Buffer RTR Get */ +#define FLEXCAN_MB_RTR_GET(rtrAddr) (((FLEXCAN_REG32_CONTENT(rtrAddr))>>20)&0x01U) +/** @brief Legacy Message Buffer RTR Clear */ +#define FLEXCAN_MB_RTR_CLR(rtrAddr) (FLEXCAN_REG32_CONTENT(rtrAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,20)) +/** @brief Legacy Message Buffer RTR Attach */ +#define FLEXCAN_MB_RTR_ATTACH(rtrAddr,var) (FLEXCAN_REG32_CONTENT(rtrAddr) |= FLEXCAN_U32SHIFT(var,0x01U,20)) +/** @brief Legacy Message Buffer RTR set */ +#define FLEXCAN_MB_RTR_SET(rtrAddr,var) FLEXCAN_REG32_CONTENT(rtrAddr) = ((FLEXCAN_REG32_CONTENT(rtrAddr) & FLEXCAN_U32NOTSHIFT(0x01U,20)) | FLEXCAN_U32SHIFT(var,0x01U,20)) + +/** @brief Legacy Message Buffer DLC Get */ +#define FLEXCAN_MB_DLC_GET(dlcAddr) (((FLEXCAN_REG32_CONTENT(dlcAddr))>>16)&0x0FU) +/** @brief Legacy Message Buffer DLC Clear */ +#define FLEXCAN_MB_DLC_CLR(dlcAddr) (FLEXCAN_REG32_CONTENT(dlcAddr) &= FLEXCAN_U32NOTSHIFT(0x0FU,16)) +/** @brief Legacy Message Buffer DLC Attach */ +#define FLEXCAN_MB_DLC_ATTACH(dlcAddr,var) (FLEXCAN_REG32_CONTENT(dlcAddr) |= FLEXCAN_U32SHIFT(var,0x0FU,16)) +/** @brief Legacy Message Buffer DLC Set */ +#define FLEXCAN_MB_DLC_SET(dlcAddr,var) FLEXCAN_REG32_CONTENT(dlcAddr) = ((FLEXCAN_REG32_CONTENT(dlcAddr) & FLEXCAN_U32NOTSHIFT(0x0FU,16)) | FLEXCAN_U32SHIFT(var,0x0FU,16)) + +/** @brief Legacy Message Buffer TIME STAMP Get */ +#define FLEXCAN_MB_TIMESTAMP_GET(timestampAddr) (FLEXCAN_REG32_CONTENT(timestampAddr)&0xFFFFU) +/** @brief Legacy Message Buffer TIME STAMP Clear */ +#define FLEXCAN_MB_TIMESTAMP_CLR(timestampAddr) (FLEXCAN_REG32_CONTENT(timestampAddr) &= FLEXCAN_U32NOTSHIFT(0xFFFFU,0)) +/** @brief Legacy Message Buffer TIME STAMP Attach */ +#define FLEXCAN_MB_TIMESTAMP_ATTACH(timestampAddr,var) (FLEXCAN_REG32_CONTENT(timestampAddr) |= FLEXCAN_U32SHIFT(var,0xFFFFU,0)) +/** @brief Legacy Message Buffer TIME STAMP Set */ +#define FLEXCAN_MB_TIMESTAMP_SET(timestampAddr,var) FLEXCAN_REG32_CONTENT(timestampAddr) = ((FLEXCAN_REG32_CONTENT(timestampAddr) & FLEXCAN_U32NOTSHIFT(0xFFFFU,0)) | FLEXCAN_U32SHIFT(var,0xFFFFU,0)) + +/** @brief Legacy Message Buffer PRIO Get */ +#define FLEXCAN_MB_PRIO_GET(prioAddr) (((FLEXCAN_REG32_CONTENT(prioAddr))>>29)&0x07U) +/** @brief Legacy Message Buffer PRIO Clear */ +#define FLEXCAN_MB_PRIO_CLR(prioAddr) (FLEXCAN_REG32_CONTENT(prioAddr) &= FLEXCAN_U32NOTSHIFT(0x07U,29)) +/** @brief Legacy Message Buffer PRIO Attach */ +#define FLEXCAN_MB_PRIO_ATTACH(prioAddr,var) (FLEXCAN_REG32_CONTENT(prioAddr) |= FLEXCAN_U32SHIFT(var,0x07U,29)) +/** @brief Legacy Message Buffer PRIO Set */ +#define FLEXCAN_MB_PRIO_SET(prioAddr,var) FLEXCAN_REG32_CONTENT(prioAddr) = ((FLEXCAN_REG32_CONTENT(prioAddr) & FLEXCAN_U32NOTSHIFT(0x07U,29)) | FLEXCAN_U32SHIFT(var,0x07U,29)) + +/** @brief Legacy Message Buffer STD ID Get */ +#define FLEXCAN_MB_STDID_GET(stdidAddr) (((FLEXCAN_REG32_CONTENT(stdidAddr))>>18)&0x7FFU) +/** @brief Legacy Message Buffer STD ID CLR */ +#define FLEXCAN_MB_STDID_CLR(stdidAddr) (FLEXCAN_REG32_CONTENT(stdidAddr) &= FLEXCAN_U32NOTSHIFT(0x7FFU,18)) +/** @brief Legacy Message Buffer STD ID Attach */ +#define FLEXCAN_MB_STDID_ATTACH(stdidAddr,var) (FLEXCAN_REG32_CONTENT(stdidAddr) |= FLEXCAN_U32SHIFT(var,0x7FFU,18)) +/** @brief Legacy Message Buffer STD ID set */ +#define FLEXCAN_MB_STDID_SET(stdidAddr,var) FLEXCAN_REG32_CONTENT(stdidAddr) = ((FLEXCAN_REG32_CONTENT(stdidAddr) & FLEXCAN_U32NOTSHIFT(0x7FFU,18)) | FLEXCAN_U32SHIFT(var,0x7FFU,18)) + +/** @brief Legacy Message Buffer EXT ID Get */ +#define FLEXCAN_MB_EXTID_GET(extidAddr) ((FLEXCAN_REG32_CONTENT(extidAddr))&0x1FFFFFFF) +/** @brief Legacy Message Buffer EXT ID Clear */ +#define FLEXCAN_MB_EXTID_CLR(extidAddr) (FLEXCAN_REG32_CONTENT(extidAddr) &= FLEXCAN_U32NOTSHIFT(0x1FFFFFFF,0)) +/** @brief Legacy Message Buffer EXT ID Attach */ +#define FLEXCAN_MB_EXTID_ATTACH(extidAddr,var) (FLEXCAN_REG32_CONTENT(extidAddr) |= FLEXCAN_U32SHIFT(var,0x1FFFFFFF,0)) +/** @brief Legacy Message Buffer EXT ID set */ +#define FLEXCAN_MB_EXTID_SET(extidAddr,var) FLEXCAN_REG32_CONTENT(extidAddr) = ((FLEXCAN_REG32_CONTENT(extidAddr) & FLEXCAN_U32NOTSHIFT(0x1FFFFFFF,0)) | FLEXCAN_U32SHIFT(var,0x1FFFFFFF,0)) + +/* enhanced fifo message buffer */ + +/** @brief Enhanced FIFO Message Buffer EDL Get */ +#define FLEXCAN_EFIFOMB_EDL_GET() ((pCan->ERX_FIFO[0U]>>31)&0x01U) + +/** @brief Enhanced FIFO Message Buffer BRS Get */ +#define FLEXCAN_EFIFOMB_BRS_GET() ((pCan->ERX_FIFO[0U]>>30)&0x01U) + +/** @brief Enhanced FIFO Message Buffer ESI Get */ +#define FLEXCAN_EFIFOMB_ESI_GET() ((pCan->ERX_FIFO[0U]>>29)&0x01U) + +/** @brief Enhanced FIFO Message Buffer SRR Get */ +#define FLEXCAN_EFIFOMB_SRR_GET() ((pCan->ERX_FIFO[0U] >>22)&0x01U) + +/** @brief Enhanced FIFO Message Buffer IDE Get */ +#define FLEXCAN_EFIFOMB_IDE_GET() ((pCan->ERX_FIFO[0U]>>21)&0x01U) + +/** @brief Enhanced FIFO Message Buffer RTR Get */ +#define FLEXCAN_EFIFOMB_RTR_GET() ((pCan->ERX_FIFO[0U]>>20)&0x01U) + +/** @brief Enhanced FIFO Message Buffer DLC Get */ +#define FLEXCAN_EFIFOMB_DLC_GET() ((pCan->ERX_FIFO[0U]>>16)&0x0FU) + +/** @brief Enhanced FIFO Message Buffer TIME STAMP Get */ +#define FLEXCAN_EFIFOMB_TIMESTAMP_GET() (pCan->ERX_FIFO[0U]&0xFFU) + +/** @brief Enhanced FIFO Message Buffer STD ID Get */ +#define FLEXCAN_EFIFOMB_STDID_GET() ((pCan->ERX_FIFO[1U]>>18)&0x7FFU) + +/** @brief Enhanced FIFO Message Buffer EXT ID Get */ +#define FLEXCAN_EFIFOMB_EXTID_GET() (pCan->ERX_FIFO[1U]&0x1FFFFFFF) + +/** @brief Enhanced FIFO Message Buffer Data Get */ +#define FLEXCAN_EFIFOMB_DATAADDR_GET(wordIndex) (&(pCan->ERX_FIFO[2U+(wordIndex)])) + +/** @brief Enhanced FIFO Message Buffer IDHIT Get */ +#define FLEXCAN_EFIFOMB_IDHIT_GET(dataWordLen) ((pCan->ERX_FIFO[2U+(dataWordLen)])&0x1FFU) + +/** @brief Enhanced FIFO Message Buffer HR Time Stamp Get */ +#define FLEXCAN_EFIFOMB_HRTIMESTAMP_GET(dataWordLen) (pCan->ERX_FIFO[3U+(dataWordLen)]) + +/* enhanced fifo message buffer from user buffer*/ + +/** @brief Enhanced FIFO Message Buffer EDL Get */ +#define FLEXCAN_EFIFOMB_EDL_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>31)&0x01U) + +/** @brief Enhanced FIFO Message Buffer BRS Get */ +#define FLEXCAN_EFIFOMB_BRS_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>30)&0x01U) + +/** @brief Enhanced FIFO Message Buffer ESI Get */ +#define FLEXCAN_EFIFOMB_ESI_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>29)&0x01U) + +/** @brief Enhanced FIFO Message Buffer SRR Get */ +#define FLEXCAN_EFIFOMB_SRR_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U] >>22)&0x01U) + +/** @brief Enhanced FIFO Message Buffer IDE Get */ +#define FLEXCAN_EFIFOMB_IDE_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>21)&0x01U) + +/** @brief Enhanced FIFO Message Buffer RTR Get */ +#define FLEXCAN_EFIFOMB_RTR_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>20)&0x01U) + +/** @brief Enhanced FIFO Message Buffer DLC Get */ +#define FLEXCAN_EFIFOMB_DLC_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>16)&0x0FU) + +/** @brief Enhanced FIFO Message Buffer TIME STAMP Get */ +#define FLEXCAN_EFIFOMB_TIMESTAMP_GET_FROM_BUFFER(Addr) (((uint32_t*)Addr)[0U]&0xFFU) + +/** @brief Enhanced FIFO Message Buffer STD ID Get */ +#define FLEXCAN_EFIFOMB_STDID_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[1U]>>18)&0x7FFU) + +/** @brief Enhanced FIFO Message Buffer EXT ID Get */ +#define FLEXCAN_EFIFOMB_EXTID_GET_FROM_BUFFER(Addr) (((uint32_t*)Addr)[1U]&0x1FFFFFFF) + +/** @brief Enhanced FIFO Message Buffer Data Get */ +#define FLEXCAN_EFIFOMB_DATAADDR_GET_FROM_BUFFER(Addr, wordIndex) (&(((uint32_t*)Addr)[2U+(wordIndex)])) + +/** @brief Enhanced FIFO Message Buffer IDHIT Get */ +#define FLEXCAN_EFIFOMB_IDHIT_GET_FROM_BUFFER(Addr, dataWordLen) ((((uint32_t*)Addr)[2U+(dataWordLen)])&0x1FFU) + +/** @brief Enhanced FIFO Message Buffer HR Time Stamp Get */ +#define FLEXCAN_EFIFOMB_HRTIMESTAMP_GET_FROM_BUFFER(Addr, dataWordLen) (((uint32_t*)Addr)[3U+(dataWordLen)]) + +/* ################################################################################## */ +/* ################################### Type define ################################## */ + +/** + * @brief FLEXCAN Clock Source Select Enumeration + * + */ +typedef enum +{ + FLEXCAN_CLOCK_CANPE = 0x00U, /**< FLEXCAN_CLOCK_CANPE clock from can peripheral clock */ + FLEXCAN_CLOCK_INTERFACE = 0x01U /**< FLEXCAN_CLOCK_INTERFACE clock from can interface clock */ +} FLEXCAN_ClockSrcType; + +/** + * @brief FLEXCAN data length type + * + */ +typedef enum +{ + FLEXCAN_DATAWIDTH_8 = 8U, /**< FLEXCAN_DATALEN_8 8 bytes data width */ + FLEXCAN_DATAWIDTH_16 = 16U,/**< FLEXCAN_DATALEN_16 16 bytes data width */ + FLEXCAN_DATAWIDTH_32 = 32U,/**< FLEXCAN_DATALEN_32 32 bytes data width */ + FLEXCAN_DATAWIDTH_64 = 64U /**< FLEXCAN_DATALEN_64 64 bytes data width */ + +} FLEXCAN_DataWidthType; + +/** + * @brief CAN Pretended Network Filter type + * + */ +typedef enum +{ + FLEXCAN_PNET_ID_FILTER = 0U, /**< FLEXCAN_PNET_ID_FILTER only ID filter */ + FLEXCAN_PNET_ID_AND_PAYLOAD_FILTER = 1U, /**< FLEXCAN_PNET_ID_AND_PAYLOAD_FILTER id and payload filter */ + FLEXCAN_PNET_ID_FILTER_WITH_NCOUNT = 2U, /**< FLEXCAN_PNET_ID_FILTER_WITH_NCOUNT id with count */ + FLEXCAN_PNET_ID_AND_PAYLOAD_FILTER_WITH_NCOUNT = 3U/**< FLEXCAN_PNET_ID_AND_PAYLOAD_FILTER_WITH_NCOUNT id and payload with count */ +}FLEXCAN_PNET_FilterType; + +/** + * @brief CAN Pretended Network ID Filter type + * + */ +typedef enum +{ + FLEXCAN_PNET_ID_FILTER_SAME = 0U, /**< FLEXCAN_PNET_ID_FILTER_SAME id with mask check match */ + FLEXCAN_PNET_ID_FILTER_GREATER_EQUAL = 1U,/**< FLEXCAN_PNET_ID_FILTER_GREATER_EQUAL only match greater and equal ID1 */ + FLEXCAN_PNET_ID_FILTER_SMALLER_EQUAL = 2U,/**< FLEXCAN_PNET_ID_FILTER_SMALLER_EQUAL only match less and equal ID1 */ + FLEXCAN_PNET_ID_FILTER_RANGE = 3U /**< FLEXCAN_PNET_ID_FILTER_RANGE greater and equal ID1 and less and equal ID2 */ +}FLEXCAN_PNET_IdFilterType; + +/** + * @brief CAN Pretended Network Payload Filter type + * + */ +typedef enum +{ + FLEXCAN_PNET_PAYLOAD_FILTER_SAME = 0U, /**< FLEXCAN_PNET_PAYLOAD_FILTER_SAME payload with mask check match, FLT_DLC_LO must equal to FLT_DLC_HI */ + FLEXCAN_PNET_PAYLOAD_FILTER_GREATER_EQUAL = 1U,/**< FLEXCAN_PNET_PAYLOAD_FILTER_GREATER_EQUAL payload greater and equal than PL1_HI+PL1_LO */ + FLEXCAN_PNET_PAYLOAD_FILTER_SMALLER_EQUAL = 2U,/**< FLEXCAN_PNET_PAYLOAD_FILTER_SMALLER_EQUAL payload less and equal than PL1_HI+PL1_LO */ + FLEXCAN_PNET_PAYLOAD_FILTER_RANGE = 3U /**< FLEXCAN_PNET_PAYLOAD_FILTER_RANGE payload greater and equal than PL1_HI+PL1_LO and less and equal than PL2_HI+PL2_LO */ +}FLEXCAN_PNET_PayloadFilterType; + +/* ################################################################################## */ +/* ################################## Local Inline ################################## */ + + + +/** + * @brief Set Module Disable + * + * @param pCan FLEXCAN instance value + * @param bDisable set whether disable + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMcrDisable(FLEXCAN_Type *const pCan, uint8_t bDisable) +{ + if (bDisable == TRUE) + { + pCan->MCR |= FLEXCAN_MCR_MDIS_MASK; /* bitMDIS=1: Disable module before selecting clock */ + } + else + { + pCan->MCR &= ~FLEXCAN_MCR_MDIS_MASK; + } +} + +/** + * @brief Set Module Freeze + * + * @param pCan FLEXCAN instance value + * @param bFreeze set whether freeze + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMcrFreeze(FLEXCAN_Type *const pCan, uint8_t bFreeze) +{ + if (bFreeze == TRUE) + { + pCan->MCR |= FLEXCAN_MCR_FRZ_MASK; /* bitMDIS=1: Disable module before selecting clock */ + } + else + { + pCan->MCR &= ~FLEXCAN_MCR_FRZ_MASK; + } +} + + +/** + * @brief Set Module Halt and Freeze + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetHaltFreeze(FLEXCAN_Type *const pCan) +{ + pCan->MCR |= FLEXCAN_MCR_FRZ_MASK | FLEXCAN_MCR_HALT_MASK; +} + +/** + * @brief Wait FLEXCAN Module Enter Freezen mode + * + * @param pCan FLEXCAN instance value + * @param u32TimeoutTick Timeout tick + * @return 0U is really in freezen mode + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_WaitMcrFreezen(FLEXCAN_Type *const pCan, uint32_t u32TimeoutTick) +{ + /* wait for bitFRZACK=1 on freeze mode entry/exit */ + while ( (!((pCan->MCR & FLEXCAN_MCR_FRZACK_MASK) >> FLEXCAN_MCR_FRZACK_SHIFT)) && (u32TimeoutTick-->0U) ) + { + + } + + return (u32TimeoutTick==0U); +} + +/** + * @brief Wait FLEXCAN Module Exit Freezen mode + * + * @param pCan FLEXCAN instance value + * @param u32TimeoutTick Timeout tick + * @return 1U is really in freezen mode + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_WaitMcrExitFreezen(FLEXCAN_Type *const pCan, uint32_t u32TimeoutTick) +{ + while ( ((pCan->MCR & FLEXCAN_MCR_FRZACK_MASK) >> FLEXCAN_MCR_FRZACK_SHIFT) && (u32TimeoutTick-->0U) ) + {} + /* wait for bitFRZACK to clear (not in freeze mode) */ + + return (u32TimeoutTick==0U); +} + +/** + * @brief Wait FLEXCAN Module Ready + * + * @param pCan FLEXCAN instance value + * @param u32TimeoutTick Timeout tick + * @return 1U is really ready + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_WaitMcrReady(FLEXCAN_Type *const pCan, uint32_t u32TimeoutTick) +{ + while ( ((pCan->MCR & FLEXCAN_MCR_NOTRDY_MASK) >> FLEXCAN_MCR_NOTRDY_SHIFT) && (u32TimeoutTick-->0U) ) + {} + /* wait for bitNOTRDY to clear (module ready) */ + + return (u32TimeoutTick==0U); +} + +/** + * @brief Wait FLEXCAN Module Not Ready + * + * @param pCan FLEXCAN instance value + * @param u32TimeoutTick Timeout tick + * @return 1U is really not ready + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_WaitMcrNoReady(FLEXCAN_Type *const pCan, uint32_t u32TimeoutTick) +{ + while ( (!((pCan->MCR & FLEXCAN_MCR_NOTRDY_MASK) >> FLEXCAN_MCR_NOTRDY_SHIFT)) && (u32TimeoutTick-->0U) ) + {} + /* wait for bitNOTRDY to set (module ready) */ + + return (u32TimeoutTick==0U); +} + +/** + * @brief Set FLEXCAN MCR value + * + * @param pCan FLEXCAN instance value + * @param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMCR(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->MCR = u32Value; +} + +/** + * @brief Get FLEXCAN MCR value + * + * @param pCan FLEXCAN instance value + * @return MCR value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetMCR(FLEXCAN_Type *const pCan) +{ + return (uint32_t)pCan->MCR; +} + +/** + * @brief Attach FLEXCAN MCR value + * + * @param pCan FLEXCAN instance value + * @param u32Value attached value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachMCR(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->MCR |= u32Value; +} + +/** + * @brief Check FLEXCAN LegacyFifo Enabled + * + * @param pCan FLEXCAN instance value + * @return 0 is disable, others are enabled + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckLegacyFifoEn(FLEXCAN_Type *const pCan) +{ + return (uint32_t)pCan->MCR & FLEXCAN_MCR_RFEN_MASK; +} + +/** + * @brief Check if fifo dma enable + * + * @param pCan FLEXCAN instance value + * @return 0 is none, others is dma enabled + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckFifoDma(FLEXCAN_Type *const pCan) +{ + return (pCan->MCR & FLEXCAN_MCR_DMA_MASK); +} + +/** + * @brief Check if it is in pretended mode + * + * @param pCan FLEXCAN instance value + * @param bEntryPNET if entry or out of pretended network + * @param u32TimeoutTick timeout counter of tick + * @return 0 is not ok, other is ok + */ +LOCAL_INLINE uint8_t FLEXCAN_HWA_CheckPNETAck(FLEXCAN_Type *const pCan, uint8_t bEntryPNET, uint32_t u32TimeoutTick) +{ + if(bEntryPNET) + { + while ( (!(pCan->MCR & FLEXCAN_MCR_LPMACK_MASK)) && (u32TimeoutTick-->0U) ) + {} + /* wait for bit LPMACK to set (low power mode ready) */ + } + else + { + while ( (pCan->MCR & FLEXCAN_MCR_LPMACK_MASK) && (u32TimeoutTick-->0U) ) + {} + } + + return (u32TimeoutTick==0U); + +} + +/** + * @brief Set FLEXCAN baudrate clock source + * + * @param pCan FLEXCAN instance value + * @param tBaudClk Baudrate clock source + */ +LOCAL_INLINE void FLEXCAN_HWA_SetCtrl1BaudSrc(FLEXCAN_Type *const pCan, FLEXCAN_ClockSrcType tBaudClk) +{ + if (tBaudClk == FLEXCAN_CLOCK_INTERFACE) + { + pCan->CTRL1 |= FLEXCAN_CTRL1_CLKSRC_MASK; + } + else + { + pCan->CTRL1 &= ~FLEXCAN_CTRL1_CLKSRC_MASK; + } +} + +/** + * @brief Set FLEXCAN ctrl1 value + * + * @param pCan FLEXCAN instance value + * @param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetCtrl1(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CTRL1 = u32Value; +} + +/** + * @brief Attach FLEXCAN ctrl1 value + * + * @param pCan FLEXCAN instance value + * @param u32Value attached value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachCtrl1(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CTRL1 |= u32Value; +} + +/** + * @brief Get FLEXCAN ctrl1 value + * + * @param pCan FLEXCAN instance value + * @return CTRL1 value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetCtrl1(FLEXCAN_Type *const pCan) +{ + return pCan->CTRL1; +} + + +/** + * @brief Set CTRL2 value + * + * @param pCan FLEXCAN instance value + * @param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetCtrl2(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CTRL2 = u32Value; +} + +/** + * @brief Attach FLEXCAN ctrl2 value + * + * @param pCan FLEXCAN instance value + * @param u32Value attached value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachCtrl2(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CTRL2 |= u32Value; +} + +/** + * @brief Get CTRL2 value + * + * @param pCan FLEXCAN instance value + * @return CTRL2 value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetCtrl2(FLEXCAN_Type *const pCan) +{ + return pCan->CTRL2; +} + + +/** + * @brief Check Interrupt Mask + * + * @param pCan FLEXCAN instance value + * @return 0 is disable, others is enable + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckErrorInterrupt(FLEXCAN_Type *const pCan) +{ + return ( (FLEXCAN_HWA_GetCtrl1(pCan) & (FLEXCAN_CTRL1_BOFFMSK_MASK | FLEXCAN_CTRL1_ERRMSK_MASK | FLEXCAN_CTRL1_TWRNMSK_MASK | FLEXCAN_CTRL1_RWRNMSK_MASK )) | + (FLEXCAN_HWA_GetCtrl2(pCan) & ( FLEXCAN_CTRL2_ERRMSK_FAST_MASK | FLEXCAN_CTRL2_BOFFDONEMSK_MASK)) ); +} + + +/** + * @brief Clear IFLAG1 Flag + * + * @param pCan FLEXCAN instance value + * @param u32W1cFlag write clear value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetFlag1(FLEXCAN_Type *const pCan, uint32_t u32W1cFlag) +{ + pCan->IFLAG1 = u32W1cFlag; +} + +#if FLEXCAN_IFLAGMASK_NUM_MAX > 1U +/** + * @brief Clear IFLAG2 Flag + * + * @param pCan FLEXCAN instance value + * @param u32W1cFlag write clear value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetFlag2(FLEXCAN_Type *const pCan, uint32_t u32W1cFlag) +{ + pCan->IFLAG2 = u32W1cFlag; +} +#endif + +#if FLEXCAN_IFLAGMASK_NUM_MAX > 2U +/** + * @brief Clear IFLAG3 Flag + * + * @param pCan FLEXCAN instance value + * @param u32W1cFlag write clear value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetFlag3(FLEXCAN_Type *const pCan, uint32_t u32W1cFlag) +{ + pCan->IFLAG3 = u32W1cFlag; +} +#endif + + +/** + * @brief Get IFLAG1 Flag + * + * @param pCan FLEXCAN instance value + * @return flag1 value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetFlag1(FLEXCAN_Type *const pCan) +{ + return pCan->IFLAG1; +} + +#if FLEXCAN_IFLAGMASK_NUM_MAX > 1U +/** + * @brief Get IFLAG2 Flag + * + * @param pCan FLEXCAN instance value + * @return flag2 value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetFlag2(FLEXCAN_Type *const pCan) +{ + return pCan->IFLAG2; +} +#endif + +#if FLEXCAN_IFLAGMASK_NUM_MAX > 2U +/** + * @brief Get IFLAG3 Flag + * + * @param pCan FLEXCAN instance value + * @return flag3 value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetFlag3(FLEXCAN_Type *const pCan) +{ + return pCan->IFLAG3; +} + +#endif + +/** + * @brief Clear Rx Flag and unlock MB + * + * @param pCan FLEXCAN instance value + * @param u32MbIndex Message Buffer Index + */ +LOCAL_INLINE void FLEXCAN_HWA_UnlockMbNoFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32MbIndex) +{ + (void)pCan->TIMER; /* Read TIMER to unlock message buffers */ + if(u32MbIndex<32) + { + pCan->IFLAG1 = 1U << u32MbIndex; + } +#if FLEXCAN_IFLAGMASK_NUM_MAX > 1U + else if(u32MbIndex < 64) + { + pCan->IFLAG2 = 1U << (u32MbIndex-32); + } +#endif +#if FLEXCAN_IFLAGMASK_NUM_MAX > 2U + else if(u32MbIndex < 96) + { + pCan->IFLAG3 = 1U << (u32MbIndex-64); + } +#endif + else + { + + } +} + +/** + * @brief Clear MB Flag + * + * @param pCan FLEXCAN instance value + * @param u32MbIndex Message Buffer Index + */ +LOCAL_INLINE void FLEXCAN_HWA_W1cFlag1NoFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32MbIndex) +{ + if(u32MbIndex<32) + { + pCan->IFLAG1 = 1U << u32MbIndex; + } +#if FLEXCAN_IFLAGMASK_NUM_MAX > 1U + else if(u32MbIndex < 64) + { + pCan->IFLAG2 = 1U << (u32MbIndex-32); + } +#endif +#if FLEXCAN_IFLAGMASK_NUM_MAX > 2U + else if(u32MbIndex < 96) + { + pCan->IFLAG3 = 1U << (u32MbIndex-64); + } +#endif + else + { + + } +} + +/** + * @brief Get MB Flag + * + * @param pCan FLEXCAN instance value + * @param u32MbIndex Message Buffer Index + * @return flag value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetFlag1NoFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32MbIndex) +{ + if(u32MbIndex<32) + { + return (pCan->IFLAG1 >> u32MbIndex) & 0x01U; + } +#if FLEXCAN_IFLAGMASK_NUM_MAX > 1U + else if(u32MbIndex < 64) + { + return (pCan->IFLAG2 >> (u32MbIndex-32)) & 0x01U; + } +#endif +#if FLEXCAN_IFLAGMASK_NUM_MAX > 2U + else if(u32MbIndex < 96) + { + return (pCan->IFLAG3 >> (u32MbIndex-64)) & 0x01U; + } +#endif + else + { + return 0U; + } +} + +/** + * @brief Check if legacy fifo contains at least one data + * + * @param pCan FLEXCAN instance value + * @return 0 is none, others is data avaliable + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckLegacyFifoData(FLEXCAN_Type *const pCan) +{ + /* IFLAG1[BIT5] (Frames available in Rx FIFO) is asserted when there is at least one frame available to be read from the FIFO. */ + return (pCan->IFLAG1 & 0x20U); +} + +/** + * @brief Check if legacy fifo contains 5 data and trigger warning + * + * @param pCan FLEXCAN instance value + * @return 0 is none, others are warning + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckLegacyFifoWarning(FLEXCAN_Type *const pCan) +{ + /* IFLAG1[BIT6] is asserted when there is 5 data. */ + return (pCan->IFLAG1 & 0x40U); +} + +/** + * @brief Check if legacy fifo data lost + * + * @param pCan FLEXCAN instance value + * @return 0 is none, others are lost + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckLegacyFifoDataLost(FLEXCAN_Type *const pCan) +{ + /* IFLAG1[BIT7] is asserted when there is data lost. */ + return (pCan->IFLAG1 & 0x80U); +} + +/** + * @brief Clear Legacy Fifo Rx data available Flag + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ClearIFLAG1FifoFlag(FLEXCAN_Type *const pCan) +{ + /* Read TIMER to unlock message buffers */ + (void)pCan->TIMER; + + pCan->IFLAG1 = 1U << 5; +} + +/** + * @brief Clear Legacy Fifo Rx warning Flag + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ClearIFLAG1FifoWarningFlag(FLEXCAN_Type *const pCan) +{ + pCan->IFLAG1 = 1U << 6; +} + +/** + * @brief Clear Legacy Fifo Rx error Flag + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ClearIFLAG1FifoErrorFlag(FLEXCAN_Type *const pCan) +{ + pCan->IFLAG1 = 1U << 7; +} + +/** + * @brief Check Legacy Fifo Data Valid Polling Flag + * + * @param pCan FLEXCAN instance value + * @return data valid polling flag, 0 is not ok, 1 is ok + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckLegacyFifoDataPolling(FLEXCAN_Type *const pCan) +{ + /* IFLAG1[BIT5] (Frames available in Rx FIFO) is asserted when there is at least one frame available to be read from the FIFO. */ + uint32_t u32Temp = (~pCan->IMASK1); + return (pCan->IFLAG1 & u32Temp & 0x20U); +} + + +/** + * @brief Check Legacy Fifo Data warning Polling Flag + * + * @param pCan FLEXCAN instance value + * @return data warning polling flag, 0 is not ok, 1 is ok + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckLegacyFifoWarningPolling(FLEXCAN_Type *const pCan) +{ + /* IFLAG1[BIT6] is asserted when there is 5 data. */ + uint32_t u32Temp = (~pCan->IMASK1); + return (pCan->IFLAG1 & u32Temp & 0x40U); +} + +/** + * @brief Check Legacy Fifo Data lost Polling Flag + * + * @param pCan FLEXCAN instance value + * @return data lost polling flag, 0 is not ok, 1 is ok + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckLegacyFifoErrorPolling(FLEXCAN_Type *const pCan) +{ + /* IFLAG1[BIT7] is asserted when there is data lost. */ + uint32_t u32Temp = (~pCan->IMASK1); + return (pCan->IFLAG1 & u32Temp & 0x80U); +} + +/** + * @brief Check Legacy Fifo Data Valid Interrupt Flag + * + * @param pCan FLEXCAN instance value + * @return data valid interrupt flag, 0 is not ok, 1 is ok + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckLegacyFifoDataInterrupt(FLEXCAN_Type *const pCan) +{ + /* IFLAG1[BIT5] (Frames available in Rx FIFO) is asserted when there is at least one frame available to be read from the FIFO. */ + uint32_t u32Temp = (pCan->IMASK1); + return (pCan->IFLAG1 & u32Temp & 0x20U); +} +/** + * @brief Check Legacy Fifo Data warning interrupt Flag + * + * @param pCan FLEXCAN instance value + * @return data warning interrupt flag, 0 is not ok, 1 is ok + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckLegacyFifoWarningInterrupt(FLEXCAN_Type *const pCan) +{ + /* IFLAG1[BIT6] is asserted when there is 5 data. */ + uint32_t u32Temp = (pCan->IMASK1); + return (pCan->IFLAG1 & u32Temp & 0x40U); +} + +/** + * @brief Check Legacy Fifo Data lost interrupt Flag + * + * @param pCan FLEXCAN instance value + * @return data lost interrupt flag, 0 is not ok, 1 is ok + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckLegacyFifoErrorInterrupt(FLEXCAN_Type *const pCan) +{ + /* IFLAG1[BIT7] is asserted when there is data lost. */ + uint32_t u32Temp = (pCan->IMASK1); + return (pCan->IFLAG1 & u32Temp & 0x80U); +} + +/** + * @brief Set special message buffer interrupt + * + * @param pCan FLEXCAN instance value + * @param u32Mask Message Buffer interrupt mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMask1MbInterrupt(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->IMASK1 = u32Mask; +} + +/** + * @brief Attach special message buffer interrupt MASK1 + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachMask1MbInterrupt(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->IMASK1 |= u32Mask; +} + +#if FLEXCAN_IFLAGMASK_NUM_MAX > 1U +/** + * @brief Attach special message buffer interrupt MASK2 + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachMask2MbInterrupt(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->IMASK2 |= u32Mask; +} +#endif + +#if FLEXCAN_IFLAGMASK_NUM_MAX > 2U +/** + * @brief Attach special message buffer interrupt MASK2 + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachMask3MbInterrupt(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->IMASK3 |= u32Mask; +} +#endif + +/** + * @brief Attach special message buffer interrupt + * + * @param pCan FLEXCAN instance value + * @param u32MbIndex Message Buffer index + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachMbIndexInterrupt(FLEXCAN_Type *const pCan, uint32_t u32MbIndex) +{ + pCan->IMASK1 |= 1U << u32MbIndex; +} + +/** + * @brief Set Legacy Fifo Rx interrupt + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMaskFifoInterrupt(FLEXCAN_Type *const pCan) +{ + pCan->IMASK1 = 1U << 5U; +} + +/** + * @brief Get special message buffer interrupt + * + * @param pCan FLEXCAN instance value + * @return IMASK1 value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetMask1(FLEXCAN_Type *const pCan) +{ + return pCan->IMASK1; +} + + +#if FLEXCAN_IFLAGMASK_NUM_MAX > 1U +/** + * @brief Get special message buffer interrupt + * + * @param pCan FLEXCAN instance value + * @return IMASK2 value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetMask2(FLEXCAN_Type *const pCan) +{ + return pCan->IMASK2; +} + +#if FLEXCAN_IFLAGMASK_NUM_MAX > 2U +/** + * @brief Get special message buffer interrupt + * + * @param pCan FLEXCAN instance value + * @return IMASK3 value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetMask3(FLEXCAN_Type *const pCan) +{ + return pCan->IMASK3; +} +#endif + +#endif + +/** + * @brief Set CBT value + * + * @param pCan FLEXCAN instance value + * @param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetCBT(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CBT = u32Value; +} + +/** + * @brief Set FDCBT value + * + * @param pCan FLEXCAN instance value + * @param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetFDCBT(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->FDCBT = u32Value; +} + +/** + * @brief Set FDCTRL value + * + * @param pCan FLEXCAN instance value + * @param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetFDCTRL(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->FDCTRL = u32Value; +} + + + +/** + * @brief Set MB data width in MBDSR + * + * @param pCan FLEXCAN instance value + * @param u32Value write value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CalDataWidth(uint8_t* pDataWidthArr) +{ + uint32_t u32Ret; + /* MBDSR0, pMb 0-31 data length, 8-0,16-1,32-2,64-3 */ + u32Ret = (FLEXCAN_FDCTRL_MBDSR0(pDataWidthArr[0] == FLEXCAN_DATAWIDTH_8?0U:(pDataWidthArr[0] == FLEXCAN_DATAWIDTH_16?1U:(pDataWidthArr[0] == FLEXCAN_DATAWIDTH_32?2U:3U)))); + + +#if FLEXCAN_FD_DATALEN_RANGE_NUM_MAX > 1U + u32Ret |= (FLEXCAN_FDCTRL_MBDSR1(pDataWidthArr[1] == FLEXCAN_DATAWIDTH_8?0U:(pDataWidthArr[1] == FLEXCAN_DATAWIDTH_16?1U:(pDataWidthArr[1] == FLEXCAN_DATAWIDTH_32?2U:3U)))); +#endif + +#if FLEXCAN_FD_DATALEN_RANGE_NUM_MAX > 2U + u32Ret |= (FLEXCAN_FDCTRL_MBDSR2(pDataWidthArr[2] == FLEXCAN_DATAWIDTH_8?0U:(pDataWidthArr[2] == FLEXCAN_DATAWIDTH_16?1U:(pDataWidthArr[2] == FLEXCAN_DATAWIDTH_32?2U:3U)))); +#endif + return u32Ret; +} + +/** + * @brief Set EPRS value + * + * @param pCan FLEXCAN instance value + * @param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetEPRS(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->EPRS = u32Value; +} + +/** + * @brief Set ENCBT value + * + * @param pCan FLEXCAN instance value + * @param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetENCBT(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->ENCBT = u32Value; +} + +/** + * @brief Set EDCBT value + * + * @param pCan FLEXCAN instance value + * @param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetEDCBT(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->EDCBT = u32Value; +} + +/** + * @brief Set ETDC value + * + * @param pCan FLEXCAN instance value + * @param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetETDC(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->ETDC = u32Value; +} + + +/** + * @brief This Function is used to get FLEXCAN rx timestamp + * + * @param pCan is FLEXCAN instance value + * @return timestamp Register Value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetTimeStamp(FLEXCAN_Type *const pCan) +{ + return pCan->TIMER; +} + +/** + * @brief This Function is used to get FLEXCAN error + * + * @param pCan is FLEXCAN instance value + * @return ESR1 Register Value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetErrorInfo(FLEXCAN_Type *const pCan) +{ + return pCan->ESR1; +} + +/** + * @brief This Function is used to get FLEXCAN error with interrupt + * + * @param pCan is FLEXCAN instance value + * @return ESR1 Register Value with interrupt mask + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetErrorIntInfo(FLEXCAN_Type *const pCan) +{ + uint32_t u32IntMask = 0U; + + u32IntMask = ((0U == (pCan->CTRL1 & FLEXCAN_CTRL1_ERRMSK_MASK))?0U:FLEXCAN_ESR1_ERRINT_MASK); + u32IntMask |= ((0U == (pCan->CTRL1 & FLEXCAN_CTRL1_BOFFMSK_MASK))?0U:FLEXCAN_ESR1_BOFFINT_MASK); + u32IntMask |= ((0U == (pCan->CTRL2 & FLEXCAN_CTRL2_ERRMSK_FAST_MASK))?0U:FLEXCAN_ESR1_ERRINT_FAST_MASK); + u32IntMask |= ((0U == (pCan->CTRL2 & FLEXCAN_CTRL2_BOFFDONEMSK_MASK))?0U:FLEXCAN_ESR1_BOFFDONEINT_MASK); + + return (pCan->ESR1 & u32IntMask); +} + +/** + * @brief Clear Error Info + * + * @param pCan FLEXCAN instance value + * @param u32ErrorEsr1 is read from FLEXCAN_GetErrorInfo + */ +LOCAL_INLINE void FLEXCAN_HWA_ClrErrorInfo(FLEXCAN_Type *const pCan, uint32_t u32ErrorEsr1) +{ + pCan->ESR1 = u32ErrorEsr1; +} + +/** + * @brief This Function is used to get FLEXCAN error count + * + * @param pCan is FLEXCAN instance value + * @return ECR Register Value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetErrorCount(FLEXCAN_Type *const pCan) +{ + return pCan->ECR; +} + +/** + * @brief This Function is used to get FLEXCAN enhanced fifo error count + * + * @param pCan is FLEXCAN instance value + * @return ERFSR Register Value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetERFSR(FLEXCAN_Type *const pCan) +{ + return pCan->ERFSR; +} + + +/** + * @brief Enable FLEXCAN Legacy Fifo + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_EnableLegacyFifo(FLEXCAN_Type *const pCan) +{ + /* if enable legacy fifo, FD fifo must be disabled */ + pCan->MCR |= FLEXCAN_MCR_RFEN_MASK; /* set legacy fifo */ +} + +/** + * @brief Disable FLEXCAN Legacy Fifo + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_DisableLegacyFifo(FLEXCAN_Type *const pCan) +{ + /* if enable legacy fifo, FD fifo must be disabled */ + pCan->MCR &= ~FLEXCAN_MCR_RFEN_MASK; /* clear legacy fifo */ +} + + +/** + * @brief Attach FLEXCAN ERFCR value + * + * @param pCan FLEXCAN instance value + * @param u32Value attached value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachERFCR(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->ERFCR |= u32Value; +} + +/** + * @brief Check Enhanced FIFO Enable + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckEnhancedFIFOEn(FLEXCAN_Type *const pCan) +{ + return (pCan->ERFCR & FLEXCAN_ERFCR_ERFEN_MASK); +} + +/** + * @brief Enable FLEXCAN FD Fifo + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_EnableFDFifo(FLEXCAN_Type *const pCan) +{ + /* if enable fd fifo, legacy fifo must be disabled */ + pCan->ERFCR |= FLEXCAN_ERFCR_ERFEN_MASK; /* set enhanced fifo */ +} + +/** + * @brief Disable FLEXCAN FD Fifo + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_DisableFDFifo(FLEXCAN_Type *const pCan) +{ + /* if enable fd fifo, legacy fifo must be disabled */ + pCan->ERFCR &= ~FLEXCAN_ERFCR_ERFEN_MASK; /* clear enhanced fifo */ +} + + + +/** + * @brief Check FLEXCAN legacy fifo if enabled + * + * @param pCan FLEXCAN instance value + * @return 1 is legacy fifo enabled, 0 is disabled + */ +LOCAL_INLINE uint8_t FLEXCAN_HWA_CheckLegacyFifoEnabled(FLEXCAN_Type *const pCan) +{ + uint8_t u8RetVal; + uint32_t u32Value; + + /* get legacy fifo */ + u32Value = (pCan->MCR & FLEXCAN_MCR_RFEN_MASK) >> FLEXCAN_MCR_RFEN_SHIFT; + + u8RetVal = u32Value == 0U ? (uint8_t)0x0U : (uint8_t)0x1U; + + return u8RetVal; +} + +/** + * @brief Check FLEXCAN FD fifo if enabled + * + * @param pCan FLEXCAN instance value + * @return 1 is legacy fifo enabled, 0 is disabled + */ +LOCAL_INLINE uint8_t FLEXCAN_HWA_CheckFdFifoEnabled(FLEXCAN_Type *const pCan) +{ + uint8_t u8RetVal; + uint32_t u32Value; + /* get enhanced fifo */ + u32Value = (pCan->ERFCR & FLEXCAN_ERFCR_ERFEN_MASK) >> FLEXCAN_ERFCR_ERFEN_SHIFT; + + u8RetVal = u32Value == 0U ? (uint8_t)0x0U : (uint8_t)0x1U; + + return u8RetVal; +} + + +/** + * @brief Set legacy fifo filter number number + * + * @param pCan FLEXCAN instance value + * @param u32RFFN is total filter number + */ +LOCAL_INLINE void FLEXCAN_HWA_SetLegacyFifoFilterNum(FLEXCAN_Type *const pCan, uint32_t u32RFFN) +{ + pCan->CTRL2 &= ~FLEXCAN_CTRL2_RFFN_MASK; /* clear fifo filter number */ + pCan->CTRL2 |= ((u32RFFN) << FLEXCAN_CTRL2_RFFN_SHIFT)&FLEXCAN_CTRL2_RFFN_MASK; +} + +/** + * @brief Set legacy fifo filter number number + * + * @param pCan FLEXCAN instance value + * @param u32FilterNum is total filter number + */ +LOCAL_INLINE void FLEXCAN_HWA_SetLegacyFifoFilterNum1(FLEXCAN_Type *const pCan, uint32_t u32FilterNum) +{ + pCan->CTRL2 &= ~FLEXCAN_CTRL2_RFFN_MASK; /* clear fifo filter number */ + pCan->CTRL2 |= ((u32FilterNum - 1U) << FLEXCAN_CTRL2_RFFN_SHIFT)&FLEXCAN_CTRL2_RFFN_MASK; +} + + +/** + * @brief Check FLEXCAN FD enable + * + * @param pCan FLEXCAN instance value + * @return 1 is fd enabled, 0 is disabled + */ +LOCAL_INLINE uint8_t FLEXCAN_HWA_CheckFd(FLEXCAN_Type *const pCan) +{ + uint8_t u8RetVal; + uint32_t u32Value; + + /* get fd enable */ + u32Value = (pCan->MCR & FLEXCAN_MCR_FDEN_MASK) >> FLEXCAN_MCR_FDEN_SHIFT; + + u8RetVal = u32Value == 0U ? (uint8_t)0x0U : (uint8_t)0x1U; + + return u8RetVal; +} + + +/** + * @brief Set RXIMR for FLEXCAN + * + * @param pCan FLEXCAN instance value + * @param u32MbIndex Message Buffer Index + * @param u32Mask ID Mask + */ +LOCAL_INLINE void FLEXCAN_HWA_SetIndividualMask(FLEXCAN_Type *const pCan, uint32_t u32MbIndex, uint32_t u32Mask) +{ + pCan->RXIMR[u32MbIndex] = u32Mask; +} + +/** + * @brief Set MB global mask value + * + * @param pCan FLEXCAN instance value + * @param u32Mask mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMBGlobalMask(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->RXMGMASK = u32Mask; +} + +/** + * @brief Set Fifo global mask value + * + * @param pCan FLEXCAN instance value + * @param u32Mask mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetFifoGlobalMask(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->RXFGMASK = u32Mask; +} + + +/** + * @brief Set rx14 mask value + * + * @param pCan FLEXCAN instance value + * @param u32Mask mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetRx14Mask(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->RX14MASK = u32Mask; +} + +/** + * @brief Set rx15 mask value + * + * @param pCan FLEXCAN instance value + * @param u32Mask mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetRx15Mask(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->RX15MASK = u32Mask; +} + +/** + * @brief Set value to FLEXCAN RAM + * + * @param pCan FLEXCAN instance value + * @param u32RamIndex RAM index for FLEXCAN + * @param u32Value written value + */ +LOCAL_INLINE void FLEXCAN_HWA_MbRam(FLEXCAN_Type *const pCan, uint32_t u32RamIndex, uint32_t u32Value) +{ + pCan->RAM[u32RamIndex] = u32Value; +} + +/** + * @brief Clear PNET CTRL1_PN + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ClrPNET_CTRL1_PN(FLEXCAN_Type *const pCan) +{ + pCan->CTRL1_PN = 0U; +} + +/** + * @brief Set PNET timeout Interrupt + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetPNET_TimeoutInterrupt(FLEXCAN_Type *const pCan) +{ + pCan->CTRL1_PN = FLEXCAN_CTRL1_PN_WTOF_MSK_MASK; +} + +/** + * @brief Check PNET timeout Interrupt + * + * @param pCan FLEXCAN instance value + * + * @return 0 is no timeout interrupt, others means contains interrupt + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_ChkPNET_TimeoutInterrupt(FLEXCAN_Type *const pCan) +{ + uint32_t u32Temp = pCan->CTRL1_PN & FLEXCAN_CTRL1_PN_WTOF_MSK_MASK; + u32Temp = u32Temp & pCan->WU_MTC & FLEXCAN_WU_MTC_WTOF_MASK; + return u32Temp; +} + +/** + * @brief Check PNET match Interrupt + * + * @param pCan FLEXCAN instance value + * + * @return 0 is no timeout interrupt, others means contains interrupt + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_ChkPNET_MatchInterrupt(FLEXCAN_Type *const pCan) +{ + uint32_t u32Temp = pCan->CTRL1_PN & FLEXCAN_CTRL1_PN_WUMF_MSK_MASK; + u32Temp = u32Temp & pCan->WU_MTC & FLEXCAN_WU_MTC_WUMF_MASK; + return u32Temp; +} + +/** + * @brief Attach PNET timeout Interrupt + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachPNET_TimeoutInterrupt(FLEXCAN_Type *const pCan) +{ + pCan->CTRL1_PN |= FLEXCAN_CTRL1_PN_WTOF_MSK_MASK; +} + +/** + * @brief Set PNET match Interrupt + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetPNET_MatchInterrupt(FLEXCAN_Type *const pCan) +{ + pCan->CTRL1_PN = FLEXCAN_CTRL1_PN_WUMF_MSK_MASK; +} + +/** + * @brief Attach PNET match Interrupt + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachPNET_MatchInterrupt(FLEXCAN_Type *const pCan) +{ + pCan->CTRL1_PN |= FLEXCAN_CTRL1_PN_WUMF_MSK_MASK; +} + +/** + * @brief Set PNET Match Count value + * + * @param pCan FLEXCAN instance value + * @param u8Value written value, match count + */ +LOCAL_INLINE void FLEXCAN_HWA_SetPNET_MatchCount(FLEXCAN_Type *const pCan, uint8_t u8Value) +{ + pCan->CTRL1_PN = FLEXCAN_CTRL1_PN_NMATCH(u8Value); +} + +/** + * @brief Attach PNET Match Count value + * + * @param pCan FLEXCAN instance value + * @param u8Value written value, match count + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachPNET_MatchCount(FLEXCAN_Type *const pCan, uint8_t u8Value) +{ + pCan->CTRL1_PN |= FLEXCAN_CTRL1_PN_NMATCH(u8Value); +} + +/** + * @brief Set PNET Filter Type + * + * @param pCan FLEXCAN instance value + * @param u8Value written value, Filter Type + */ +LOCAL_INLINE void FLEXCAN_HWA_SetPNET_FilterType(FLEXCAN_Type *const pCan, uint8_t u8Value) +{ + pCan->CTRL1_PN = FLEXCAN_CTRL1_PN_FCS(u8Value); +} + +/** + * @brief Attach PNET Filter Type + * + * @param pCan FLEXCAN instance value + * @param u8Value written value, Filter Type + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachPNET_FilterType(FLEXCAN_Type *const pCan, uint8_t u8Value) +{ + pCan->CTRL1_PN |= FLEXCAN_CTRL1_PN_FCS(u8Value); +} + + +/** + * @brief Set PNET ID Filter Type + * + * @param pCan FLEXCAN instance value + * @param u8Value written value, ID Filter Type + */ +LOCAL_INLINE void FLEXCAN_HWA_SetPNET_IDFilterType(FLEXCAN_Type *const pCan, uint8_t u8Value) +{ + pCan->CTRL1_PN = FLEXCAN_CTRL1_PN_IDFS(u8Value); +} + + +/** + * @brief Attach PNET ID Filter Type + * + * @param pCan FLEXCAN instance value + * @param u8Value written value, ID Filter Type + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachPNET_IDFilterType(FLEXCAN_Type *const pCan, uint8_t u8Value) +{ + pCan->CTRL1_PN |= FLEXCAN_CTRL1_PN_IDFS(u8Value); +} + + +/** + * @brief Set PNET Payload Filter Type + * + * @param pCan FLEXCAN instance value + * @param u8Value written value, Payload Filter Type + */ +LOCAL_INLINE void FLEXCAN_HWA_SetPNET_PayloadFilterType(FLEXCAN_Type *const pCan, uint8_t u8Value) +{ + pCan->CTRL1_PN = FLEXCAN_CTRL1_PN_PLFS(u8Value); +} + + +/** + * @brief Attach PNET Payload Filter Type + * + * @param pCan FLEXCAN instance value + * @param u8Value written value, Payload Filter Type + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachPNET_PayloadFilterType(FLEXCAN_Type *const pCan, uint8_t u8Value) +{ + pCan->CTRL1_PN |= FLEXCAN_CTRL1_PN_PLFS(u8Value); +} + + +/** + * @brief Set PNET ID 1 + * + * @param pCan FLEXCAN instance value + * @param u8IDE 0-standard, 1-extended + * @param u8RTR 0-data, 1-remote + * @param u32ID1 id value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetPNET_ID1(FLEXCAN_Type *const pCan, uint8_t u8IDE, uint8_t u8RTR, uint32_t u32ID1) +{ + pCan->FLT_ID1 = FLEXCAN_FLT_ID1_FLT_IDE(u8IDE) | FLEXCAN_FLT_ID1_FLT_RTR(u8RTR) | ((u8IDE==0)?(((uint32_t)u32ID1)<<18U):u32ID1); +} + + +/** + * @brief Set PNET ID 2 + * + * @param pCan FLEXCAN instance value + * @param u8IDE 0-standard, 1-extended + * @param u8RTR 0-data, 1-remote + * @param u32ID2 id value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetPNET_ID2(FLEXCAN_Type *const pCan, uint8_t u8IDE, uint8_t u8RTR, uint32_t u32ID2) +{ + pCan->FLT_ID2_IDMASK = FLEXCAN_FLT_ID2_IDMASK_IDE_MSK(u8IDE) | FLEXCAN_FLT_ID2_IDMASK_RTR_MSK(u8RTR) | ((u8IDE==0)?(((uint32_t)u32ID2)<<18U):u32ID2); +} + + +/** + * @brief Set PNET DLC + * + * @param pCan FLEXCAN instance value + * @param u8DLC1 Low value + * @param u8DLC2 High value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetPNET_DlcRange(FLEXCAN_Type *const pCan, uint8_t u8DLC1, uint8_t u8DLC2) +{ + pCan->FLT_DLC = FLEXCAN_FLT_DLC_FLT_DLC_HI(u8DLC2) | FLEXCAN_FLT_DLC_FLT_DLC_LO(u8DLC1); +} + +/** + * @brief Set PNET Payload 1 data content + * + * @param pCan FLEXCAN instance value + * @param u32High High value + * @param u32Low Low value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetPNET_Payload1Content(FLEXCAN_Type *const pCan, uint32_t u32High, uint32_t u32Low) +{ + pCan->PL1_HI = u32High; + pCan->PL1_LO = u32Low; +} + +/** + * @brief Set PNET Payload 2 data content + * + * @param pCan FLEXCAN instance value + * @param u32High High value + * @param u32Low Low value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetPNET_Payload2Content(FLEXCAN_Type *const pCan, uint32_t u32High, uint32_t u32Low) +{ + pCan->PL2_PLMASK_HI = u32High; + pCan->PL2_PLMASK_LO = u32Low; +} + + +/** + * @brief Set PNET Timeout value + * + * @param pCan FLEXCAN instance value + * @param u16Value written value, period is 64 times of can bit time + */ +LOCAL_INLINE void FLEXCAN_HWA_SetPNET_Timeout(FLEXCAN_Type *const pCan, uint16_t u16Value) +{ + pCan->CTRL2_PN = u16Value; +} + +/** + * @brief Clear PNET Interrupt flag + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ClrPNET_IntFlag(FLEXCAN_Type *const pCan) +{ + pCan->WU_MTC = FLEXCAN_WU_MTC_WTOF_MASK | FLEXCAN_WU_MTC_WUMF_MASK; +} + +/** + * @brief Clear PNET timeout Interrupt flag + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ClrPNET_TimeoutFlag(FLEXCAN_Type *const pCan) +{ + pCan->WU_MTC = FLEXCAN_WU_MTC_WTOF_MASK; +} + +/** + * @brief Clear PNET match Interrupt flag + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ClrPNET_MatchFlag(FLEXCAN_Type *const pCan) +{ + pCan->WU_MTC = FLEXCAN_WU_MTC_WUMF_MASK; +} + +/** + * @brief Get PNET Match Counter + * + * @param pCan FLEXCAN instance value + * + * @return count value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetPNET_MatchCount(FLEXCAN_Type *const pCan) +{ + return ((pCan->WU_MTC & FLEXCAN_WU_MTC_MCOUNTER_MASK)>>FLEXCAN_WU_MTC_MCOUNTER_SHIFT); +} + + +/** + * @brief Get value from FLEXCAN Wake-up message index + * + * @param pCan FLEXCAN instance value + * @param u32MsgIndex Wake-up Message index for FLEXCAN + * @return ram address + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_PNETRamAddr(FLEXCAN_Type *const pCan, uint32_t u32MsgIndex) +{ + return (uint32_t)(&(pCan->WMB_RAM[u32MsgIndex*4])); +} + + +/** + * @brief Set ERFCR value + * + * @param pCan FLEXCAN instance value + * @param u32Value written value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetERFCR(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->ERFCR = u32Value; +} + + +/** + * @brief Set ERFIER value + * + * @param pCan FLEXCAN instance value + * @param u32Value written value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetERFIER(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->ERFIER = u32Value; +} + + +/** + * @brief Attache ERFIER value + * + * @param pCan FLEXCAN instance value + * @param u32Value written value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachERFIER(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->ERFIER |= u32Value; +} + + +/** + * @brief Check Enhanced FIFO Polling flag + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckEnhancedFifoPollingFlag(FLEXCAN_Type *const pCan) +{ + return ((~pCan->ERFIER) & pCan->ERFSR & (FLEXCAN_ERFSR_ERFDA_MASK | FLEXCAN_ERFSR_ERFOVF_MASK | + FLEXCAN_ERFSR_ERFUFW_MASK | FLEXCAN_ERFSR_ERFWMI_MASK) ); +} + + +/** + * @brief Check Enhanced FIFO data polling flag + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckEnhancedFifoDataPolling(FLEXCAN_Type *const pCan) +{ + uint32_t u32Temp = pCan->ERFSR; + u32Temp = ((~pCan->ERFIER) & u32Temp & (FLEXCAN_ERFSR_ERFDA_MASK |FLEXCAN_ERFSR_ERFWMI_MASK) ); + u32Temp = u32Temp | (pCan->MCR & FLEXCAN_MCR_DMA_MASK); /* no dma enable */ + return u32Temp; +} + + +/** + * @brief Check Enhanced FIFO error polling flag + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckEnhancedFifoErrorPolling(FLEXCAN_Type *const pCan) +{ + uint32_t u32Temp = pCan->ERFSR; + return ((~pCan->ERFIER) & u32Temp & (FLEXCAN_ERFSR_ERFOVF_MASK | FLEXCAN_ERFSR_ERFUFW_MASK) ); +} + +/** + * @brief Check Enhanced FIFO data interrupt flag + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckEnhancedFifoDataInterrupt(FLEXCAN_Type *const pCan) +{ + uint32_t u32Temp = pCan->ERFSR; + u32Temp = (pCan->ERFIER & u32Temp & (FLEXCAN_ERFSR_ERFDA_MASK |FLEXCAN_ERFSR_ERFWMI_MASK) ); + u32Temp = u32Temp | (pCan->MCR & FLEXCAN_MCR_DMA_MASK); /* no dma enable */ + return u32Temp; +} + + +/** + * @brief Check Enhanced FIFO error interrupt flag + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_CheckEnhancedFifoErrorInterrupt(FLEXCAN_Type *const pCan) +{ + uint32_t u32Temp = pCan->ERFSR; + return (pCan->ERFIER & u32Temp & (FLEXCAN_ERFSR_ERFOVF_MASK | FLEXCAN_ERFSR_ERFUFW_MASK) ); +} + + +/** + * @brief Reset Enhanced FIFO Engine + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ERFSRResetEnhancedFifo(FLEXCAN_Type *const pCan) +{ + /* Write one to ERFSR[ERFCLR] to reset Enhanced Rx FIFO engine */ + pCan->ERFSR |= FLEXCAN_ERFSR_ERFCLR_MASK; +} + + +/** + * @brief Get Enhanced Fifo Flag with mask + * + * @param pCan FLEXCAN instance value + * @param u32Shift flag shift + * @param u32Mask flag mask + * @return flag value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_ERFSRGetEnhancedFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32Shift, uint32_t u32Mask) +{ + /* Write one clear status */ + return ((pCan->ERFSR & u32Mask) >> u32Shift); +} + +/** + * @brief Get Enhanced Fifo Data valid + * + * @param pCan FLEXCAN instance value + * @return flag value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_ERFSRGetDataValid(FLEXCAN_Type *const pCan) +{ + /* Write one clear status */ + return (pCan->ERFSR & (FLEXCAN_ERFSR_ERFDA_MASK | FLEXCAN_ERFSR_ERFWMI_MASK)); +} + +/** + * @brief Clear Enhanced Fifo underflow + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ERFSRClrUnderflow(FLEXCAN_Type *const pCan) +{ + /* Write one clear status */ + pCan->ERFSR = FLEXCAN_ERFSR_ERFUFW_MASK; +} + +/** + * @brief Clear Enhanced Fifo overflow + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ERFSRClrOverflow(FLEXCAN_Type *const pCan) +{ + /* Write one clear status */ + pCan->ERFSR = FLEXCAN_ERFSR_ERFOVF_MASK; +} + +/** + * @brief Get Enhanced Fifo underflow + * + * @param pCan FLEXCAN instance value + * @return flag value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_ERFSRGetUnderflow(FLEXCAN_Type *const pCan) +{ + /* Write one clear status */ + return (pCan->ERFSR & FLEXCAN_ERFSR_ERFUFW_MASK); +} + +/** + * @brief Get Enhanced Fifo overflow + * + * @param pCan FLEXCAN instance value + * @return flag value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_ERFSRGetOverflow(FLEXCAN_Type *const pCan) +{ + /* Write one clear status */ + return (pCan->ERFSR & FLEXCAN_ERFSR_ERFOVF_MASK); +} + +/** + * @brief Clear Enhanced Fifo status + * + * @param pCan FLEXCAN instance value + * @param u32ClearMask clear mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_ERFSRClearEnhancedFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32ClearMask) +{ + /* Write one clear status */ + pCan->ERFSR = u32ClearMask; +} + +/** + * @brief Clear Enhanced Fifo Error + * + * @param pCan FLEXCAN instance value + * @param u32ClearMask clear mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_ERFSRClearError(FLEXCAN_Type *const pCan, uint32_t u32ClearMask) +{ + /* Write one clear status */ + pCan->ERFSR = u32ClearMask; +} + +/** + * @brief Set Enhance Fifo interrupt value + * + * @param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachERFIERDataInterrupt(FLEXCAN_Type *const pCan) +{ + pCan->ERFIER |= FLEXCAN_ERFIER_ERFDAIE_MASK; +} + +/** + * @brief Set Enhanced Fifo filter value + * + * @param pCan FLEXCAN instance value + * @param u32FilterIndex Filter index + * @param u32Value filter value + */ +LOCAL_INLINE void FLEXCAN_HWA_EnhancedFifoFilter(FLEXCAN_Type *const pCan, uint32_t u32FilterIndex, uint32_t u32Value) +{ + pCan->ERFFEL[u32FilterIndex] = u32Value; +} + +/** @}*/ + +#endif + +#endif diff --git a/Inc/HwA_freqm.h b/Inc/HwA_freqm.h new file mode 100644 index 0000000..1f0ae82 --- /dev/null +++ b/Inc/HwA_freqm.h @@ -0,0 +1,187 @@ +/** + * @file HwA_freqm.h + * @author Flagchip0100 + * @brief FREQM Module Register API + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright 2020-2024 Flagchip Semiconductors Co., Ltd. + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip087 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip100 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_FREQM_H_ +#define _HWA_FREQM_H_ + +#include "device_header.h" + +#if (FREQM_INSTANCE_COUNT > 0U) + +/** + * @defgroup HwA_freqm HwA_freqm + * @ingroup module_driver_freqm + * @{ + */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @defgroup HwA_freqm + * @{ + */ + +/******************************************************************************* + * Local inline function + ******************************************************************************/ +/** + * @brief Set the measured clock selection. + * + * @param pFreqm the base address of the FREQM. + * @param u8ClkSel the clock selection index. + */ +LOCAL_INLINE void FREQM_HWA_MesClkSel(FREQM_Type *const pFreqm, uint8_t u8ClkSel) +{ + pFreqm->CTRL = (pFreqm->CTRL & ~((uint32_t)FREQM_CTRL_MES_CLK_SEL_MASK)) | FREQM_CTRL_MES_CLK_SEL(u8ClkSel); +} + +/** + * @brief Set the clock selection. + * + * @param pFreqm the base address of the FREQM. + * @param u8PredivVal the measure clock prediv value. + */ +LOCAL_INLINE void FREQM_HWA_MesClk_PreDiv(FREQM_Type *const pFreqm, uint8_t u8PredivVal) +{ + pFreqm->CTRL = (pFreqm->CTRL & ~((uint32_t)FREQM_CTRL_MES_CLK_PREDIV_MASK)) | FREQM_CTRL_MES_CLK_PREDIV(u8PredivVal); +} + +/** + * @brief Enable count event interrupt. + * + * @param pFreqm the base address of the FREQM. + */ +LOCAL_INLINE void FREQM_HWA_EnableCntEventInterrupt(FREQM_Type *const pFreqm) +{ + pFreqm->CTRL |= FREQM_CTRL_CNT_EVENT_IE_MASK; +} + +/** + * @brief Disable count event interrupt. + * + * @param pFreqm the base address of the FREQM. + */ +LOCAL_INLINE void FREQM_HWA_DisableCntEventInterrupt(FREQM_Type *const pFreqm) +{ + pFreqm->CTRL &= ~((uint32_t)FREQM_CTRL_CNT_EVENT_IE_MASK); +} + +/** + * @brief Set counting length of measure counter. + * + * @param pFreqm the base address of the FREQM. + * @param u32MesLen counting length of measure counter. + */ +LOCAL_INLINE void FREQM_HWA_SetMesLength(FREQM_Type *const pFreqm, uint32_t u32MesLen) +{ + pFreqm->MES_LENGTH = u32MesLen; +} + +/** + * @brief Set timeout value of reference counter. + * + * @param pFreqm the base address of the FREQM. + * @param u32RefTo timeout value of reference counter. + */ +LOCAL_INLINE void FREQM_HWA_SetRefTimeout(FREQM_Type *const pFreqm, uint32_t u32RefTo) +{ + pFreqm->REF_TIMEOUT = u32RefTo; +} + +/** + * @brief Set value of reference counter. + * + * @param pFreqm the base address of the FREQM. + * @param u32RefCnt value of reference counter. + */ +LOCAL_INLINE void FREQM_HWA_SetRefCnt(FREQM_Type *const pFreqm, uint32_t u32RefCnt) +{ + pFreqm->REF_CNT = u32RefCnt; +} + +/** + * @brief Clear counter event interrupt flag. + * + * @param pFreqm the base address of the FREQM. + */ +LOCAL_INLINE void FREQM_HWA_ClearInterruptFlag(FREQM_Type *const pFreqm) +{ + pFreqm->CNT_STATUS = FREQM_CNT_STATUS_CNT_EVENT_MASK; +} + +/** + * @brief Get counter event interrupt flag + * + * @param pFreqm the base address of the FREQM + * @return false for disable, true for enable. + */ +LOCAL_INLINE bool FREQM_HWA_GetInterruptFlag(const FREQM_Type *const pFreqm) +{ + return ((pFreqm->CNT_STATUS & FREQM_CNT_STATUS_CNT_EVENT_MASK) == FREQM_CNT_STATUS_CNT_EVENT_MASK) ? true : false; +} + +/** + * @brief Get counter status + * + * @param pFreqm the base address of the FREQM + * @return Counter status. + */ +LOCAL_INLINE uint32_t FREQM_HWA_GetCntStatus(const FREQM_Type *const pFreqm) +{ + return (pFreqm->CNT_STATUS & (FREQM_CNT_STATUS_MES_CNT_START_MASK | FREQM_CNT_STATUS_MES_CNT_STOP_MASK | FREQM_CNT_STATUS_REF_CNT_STOP_MASK)); +} + +/** + * @brief Set value of measure counter. + * + * @param pFreqm the base address of the FREQM. + * @param u32MesCnt value of measure counter. + */ +LOCAL_INLINE void FREQM_HWA_SetMesCnt(FREQM_Type *const pFreqm, uint32_t u32MesCnt) +{ + pFreqm->MES_CNT = u32MesCnt; +} + +/** + * @brief Get saved reference counter value. + * + * @param pFreqm the base address of the FREQM. + * @return saved reference counter value. + */ +LOCAL_INLINE uint32_t FREQM_HWA_GetRefCntSave(const FREQM_Type *const pFreqm) +{ + return pFreqm->REF_CNT_SAVE; +} + +/** @}*/ /* HwA_freqm */ + +#if defined(__cplusplus) +} +#endif + +/** @}*/ + +#endif /* (FREQM_INSTANCE_COUNT > 0U) */ + +#endif /* _HWA_FREQM_H_ */ diff --git a/Inc/HwA_ftu.h b/Inc/HwA_ftu.h new file mode 100644 index 0000000..8f0d5b9 --- /dev/null +++ b/Inc/HwA_ftu.h @@ -0,0 +1,1955 @@ +/** + * @file HwA_ftu.h + * @author flagchip + * @brief FTU hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip032 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip070 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_FTU_H_ +#define _HWA_FTU_H_ + +#include "device_header.h" + +#if FTU_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_ftu HwA_ftu + * @ingroup module_driver_ftu + * @{ + */ + +/********* Local typedef ************/ +/** + * @brief The definition of enable the deadtime of channel and channel+1 + * + */ +#define FTU_CHCTRL_DEADTIME_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 4U)) +/** + * @brief The definition of enable the complement of channel + * + */ +#define FTU_CHCTRL_COMPLEMENT_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 1U)) +/** + * @brief The definition of enable the synchronization for channel and channel+1 + * + */ +#define FTU_CHCTRL_SYNCEN_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 5U)) +/** + * @brief The definition of enable the Phase shift mode for channel and channel+1 + * + */ +#define FTU_CHCTRL_PHASE_CHANNEL(channel) (uint32_t)((uint32_t)1U << (((uint32_t)(channel) >> 1U) << 3U)) +/** + * @brief The definition of enable the Enhanced Phase shift mode for channel and channel+1 + * + */ +#define FTU_CHCTRL_EPHASE_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 7U)) +/** + * @brief The definition of enable the fault control in channel and channel+1 + * + */ +#define FTU_CHCTRL_FAULT_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 6U)) + +/********* Local typedef ************/ +/** + * @brief Select the FTU Debug Mode + * + */ +typedef enum +{ + FTU_DBG_COUNTER_STOP_CHN_WORKS = 0U, /*!< FTU counter stopped, channel works as function mode. */ + FTU_DBG_COUNTER_STOP_CHN_FORCE_SAFE = 1U, /*!< FTU counter stopped, channel output force to safe state. */ + FTU_DBG_COUNTER_STOP_CHN_FROZEN = 2U, /*!< FTU counter stopped, channel output is frozen. */ + FTU_DBG_COUNTER_WORKS_CHN_WORKS = 3U /*!< FTU counter works as function mode, channel works as function mode. */ +} FTU_DebugModeType; + +typedef enum +{ + FTU_CHANNEL_MODE_INPUT = 0u, + FTU_CHANNEL_MODE_OUTPUT_COMPARE = 1u, + FTU_CHANNEL_MODE_EDGE_ALIGN_PWM = 2u, + FTU_CHANNEL_MODE_DO_NOT_CARE = 3u, +} FTU_ChannelModeType; + +typedef enum +{ + FTU_CHANNEL_EDGE_NOT_USED = 0u, + FTU_CHANNEL_EDGE_RISING = 1u, + FTU_CHANNEL_EDGE_FALLING = 2u, + FTU_CHANNEL_EDGE_BOTH = 3u, + FTU_CHANNEL_OC_TOGGLE = 1u, + FTU_CHANNEL_OC_CLEAR = 2u, + FTU_CHANNEL_OC_SET = 3u, + FTU_CHANNEL_PWM_HIGH_TRUE = 2u, + FTU_CHANNEL_PWM_LOW_TRUE = 3u, +} FTU_ChannelEdgeLevelType; +/** + * @brief Select the prescaler of the FTU + * + */ +typedef enum +{ + FTU_DIV_1 = 0U, + FTU_DIV_2, + FTU_DIV_4, + FTU_DIV_8, + FTU_DIV_16, + FTU_DIV_32, + FTU_DIV_64, + FTU_DIV_128 +} FTU_PrescalerType; + +/** + * @brief Select the prescaler of the FTU filter + * + */ +typedef enum +{ + FTU_FLT_DIV_1 = 0U, + FTU_FLT_DIV_2, + FTU_FLT_DIV_3, + FTU_FLT_DIV_4, + FTU_FLT_DIV_5, + FTU_FLT_DIV_6, + FTU_FLT_DIV_7, + FTU_FLT_DIV_8, + FTU_FLT_DIV_9, + FTU_FLT_DIV_10, + FTU_FLT_DIV_11, + FTU_FLT_DIV_12, + FTU_FLT_DIV_13, + FTU_FLT_DIV_14, + FTU_FLT_DIV_15, + FTU_FLT_DIV_16 +} FTU_FilterPrescalerType; + +/** + * @brief selects the encoding mode used in the Quadrature Decoder mode + * + */ +typedef enum +{ + FTU_QUADMODE_PHA_PHB_ENCODING_MODE = 0U, /*!< Phase A and phase B encoding mode */ + FTU_QUADMODE_COUNT_DIR_ENCODING_MODE, /*!< Count and direction encoding mode */ +} FTU_QuadratureModeType; + +/** + * @brief FTU Counter Direction In Quadrature Decoder Mode + * + */ +typedef enum +{ + FTU_QUADIR_DECREMENT = 0U, /*!< FTU counter decrement */ + FTU_QUADIR_INCREMENT, /*!< FTU counter increment */ +} FTU_QuadratureDirectionType; + +/** + * @brief register bit status + * + */ +typedef enum +{ + FTU_BIT_LOW = 0U, + FTU_BIT_HIGH +} FTU_BitStatusType; + +/** + * @brief Ftu module clock source + * + */ +typedef enum +{ + FTU_MODULE_NO_CLK = 0U, /*!< No clock selected */ + FTU_MODULE_INTERNAL_CLK = 1U, /*!< FTU input clock */ + FTU_MODULE_EXTERNAL_CLK = 3U, /*!< External pin input clock */ +} FTU_ModuleClkSrcType; +#ifdef FTU_UPDOWN_DIS_FEATURE +/** + * @brief Disable channel match trigger/interrupt when count-up/down in CPWM/QUAD mode + * + */ +typedef enum +{ + FTU_DISABLE_TRIG_INTR_NONE = 0U, /*!< No effect */ + FTU_DISABLE_TRIG_INTR_CNT_DOWN = 1U, /*!< Disable trigger/interrupt when count-down */ + FTU_DISABLE_TRIG_INTR_CNT_UP = 2U, /*!< Disable trigger/interrupt when count-up */ + FTU_DISABLE_TRIG_INTR_CNT_UP_DOWN = 3U, /*!< Disable trigger/interrupt when count-up/down */ +}FTU_UpDownDisableType; +#endif +/** + * @brief hardware trig(n) mode + * + */ +typedef enum +{ + FTU_CLEARS_TRIG_WHEN_DETECTED = 0x0U, /*!< FTU clears the TRIG(n) bit when the hardware trigger j is detected, where n = 0, 1,2. */ + FTU_NOT_CLEARS_TRIG_WHEN_DETECTED = 0x01U /*!< FTU does not clear the TRIG(n) bit when the hardware trigger j is detected, where n = 0, 1,2. */ +} FTU_TrigModeType; + +/** + * @brief fault mode enumeration + * + */ +typedef enum +{ + FTU_FAULT_MODE_DISABLED = 0x00U, /*!< Fault control is disabled for all channels */ + FTU_FAULT_MODE_EVEN_CHANNEL = 0x01U, /*!< Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing */ + FTU_FAULT_MODE_CHANNEL_ALL = 0x02U, /*!< Fault control is enabled for all channels, and the selected mode is the manual fault clearing */ + FTU_FAULT_MODE_AUTO = 0x03U /*!< Fault control is enabled for all channels, and the selected mode is the automatic fault clearing */ +} FTU_FaultModeType; + +#ifdef FTU_CNT_SEL_EXIST +/** + * @brief FTU Counter Select enumeration + * + */ +typedef enum +{ + FTU_CNT_SEL_INTERNAL_CNT = 0U, /*!< Select the FTU internal counter (FTU_SC.CLKS) */ + FTU_CNT_SEL_EXTERNAL_CNT = 1U, /*!< Select an external counter as FTU counter (EFTU_CNT) */ +} FTU_CounterSelectType; +#endif + +#ifdef FTU_TCKSEL_EXIST +/** + * @brief external clock enumeration + * + */ +typedef enum +{ + FTU_TCLK0_USED = 0U, /*!< FTU_TCLK0 pin as FTU external clock */ + FTU_TCLK1_USED = 1U, /*!< FTU_TCLK1 pin as FTU external clock */ + FTU_TCLK2_USED = 2U, /*!< FTU_TCLK2 pin as FTU external clock */ + FTU_NO_CLK_USED = 3U, /*!< No clock input */ +} FTU_TclkSelType; +#endif +/** + * @brief Deadtime Prescaler Value + * + */ +typedef enum +{ + FTU_DEADTIME_PRESCALER_DIV_1 = 0U, /*!< Divide the FTU input clock by 1 */ + FTU_DEADTIME_PRESCALER_DIV_4 = 2U, /*!< Divide the FTU input clock by 4 */ + FTU_DEADTIME_PRESCALER_DIV_16 = 3U, /*!< Divide the FTU input clock by 16 */ +} FTU_DeadTimePrescalerType; + +/** + * @brief Trigger output control + * + */ +typedef enum +{ + FTU_TRIG_OUTPUT_AS_CHANNEL_MODE = 0U, /*!< channel outputs will be controlled by channel mode */ + FTU_TRIG_OUTPUT_AS_TRIGGER = 1U, /*!< If a match in the channel occurs, channel output will be a trigger */ +}FTU_TrigOutputModeType; +#ifdef FTU_FAULT_DIS_DELAY_FEATURE +/** + * @brief Fault disable channel output delay value selection + * + */ +typedef enum +{ + FTU_FAULT_DISABLE_DELAY_NO_DELAY = 0u, /*!< Select no delay */ + FTU_FAULT_DISABLE_DELAY_VALUE_0 = 1u, /*!< Select delay value 0 */ + FTU_FAULT_DISABLE_DELAY_VALUE_1 = 2u /*!< Select delay value 1 */ +}FTU_FaultDisableDelayType; +#endif +#ifdef FTU_ICM_FEATURE +/** + * @brief Input Capture Measurement Mode + * + */ +typedef enum +{ + FTU_MEASURE_MODE_OFF = 0u, /*!< Do not use measurement mode */ + FTU_MEASURE_MODE_DUTY_CYCLE = 1u, /*!< Duty-cycle Measure */ + FTU_MEASURE_MODE_PERIOD = 2u, /*!< Period Measure */ + FTU_MEASURE_EDGE_NUMBER = 3u, /*!< Edge Number Measure */ + FTU_MEASURE_EXPECT_EDGE_NUMBER = 4u, /*!< Expect Edge Number Measure */ + FTU_MEASURE_ICENM_WIND_WRITE = 7u, /*!< Configure ICENM Window */ +}FTU_MeasurementModeType; +#endif + +/********* Local inline function ************/ + +/** + * @brief Clear FTU module registers + * + * @param pFtu FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearModuleRegister(FTU_Type *pFtu) +{ + uint32_t u32Loop; + pFtu->SC = 0U; + pFtu->CNT = 0U; + pFtu->MOD = 0U; + for(u32Loop = 0u; u32Loop < FTU_CHANNEL_CONTROLS_COUNT; u32Loop++) + { + pFtu->CONTROLS[u32Loop].CSCn = (uint32_t)0u; + pFtu->CONTROLS[u32Loop].CVn = (uint32_t)0u; + } + pFtu->CNTIN = 0U; + pFtu->STATUS = pFtu->STATUS & (~FTU_STATUS_MASK); + pFtu->MODE = 0x00000004U; + pFtu->SYNC = 0U; + pFtu->OUTINIT = 0U; + pFtu->OUTMASK = 0U; + pFtu->CHCTRL = 0U; + pFtu->DEADTIME = 0U; + pFtu->TRIGCONF = 0U; + pFtu->POL = 0U; + pFtu->FMS = 0U; + pFtu->FILTER = 0U; + pFtu->FLTCTRL = 0U; + pFtu->QDCTRL = 0U; + pFtu->CONF = FTU_CONF_DBG(3u); + pFtu->FLTPOL = 0U; + pFtu->SYNCONF = 0U; + pFtu->INVCTRL = 0U; + pFtu->SWOCTRL = 0U; + pFtu->PWMLOAD = 0U; + pFtu->PAIR0DEADTIME = 0U; + pFtu->PAIR1DEADTIME = 0U; + pFtu->PAIR2DEADTIME = 0U; + pFtu->PAIR3DEADTIME = 0U; +} + +/** + * @brief Disable Global Time Base Enable + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableGlobalTimeBase(FTU_Type *pFtu) +{ + pFtu->CONF &= ~FTU_CONF_GTBEEN_MASK; +} + +/** + * @brief Enable Global Time Base Enable + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableGlobalTimeBase(FTU_Type *pFtu) +{ + pFtu->CONF |= FTU_CONF_GTBEEN_MASK; +} + +/** + * @brief Set the LDOK flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetPwmLoadEnable(FTU_Type *pFtu) +{ + pFtu->PWMLOAD |= FTU_PWMLOAD_LDOK_MASK; +} + +/** + * @brief Clear the LDOK flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearPwmLoadEnable(FTU_Type *pFtu) +{ + pFtu->PWMLOAD &= ~FTU_PWMLOAD_LDOK_MASK; +} + +/** + * @brief Set the CNTINC flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetCntinSync(FTU_Type *pFtu) +{ + pFtu->SYNCONF |= FTU_SYNCONF_CNTINC_MASK; +} + +/** + * @brief Clear the CNTINC flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearCntinSync(FTU_Type *pFtu) +{ + pFtu->SYNCONF &= ~FTU_SYNCONF_CNTINC_MASK; +} + +/** + * @brief Set the SYNCEN flag + * + * @param pFtu the base address of the FTU instance + * @param u32Index the index of SYNCEN + */ +LOCAL_INLINE void FTU_HWA_SetChannelSyncEnable(FTU_Type *pFtu, uint32_t u32Index) +{ + pFtu->CHCTRL |= (FTU_CHCTRL_SYNCEN0_MASK << (u32Index * 8)); +} + +/** + * @brief Clear the SYNCEN flag + * + * @param pFtu the base address of the FTU instance + * @param u32Index the index of SYNCEN + */ +LOCAL_INLINE void FTU_HWA_ClearChannelSyncEnable(FTU_Type *pFtu, uint32_t u32Index) +{ + pFtu->CHCTRL &= (~(FTU_CHCTRL_SYNCEN0_MASK << (u32Index * 8))); +} + +/** + * @brief Set the PWMSYNC flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetPwmSyncMode(FTU_Type *pFtu) +{ + pFtu->MODE |= FTU_MODE_PWMSYNC_MASK; +} + +/** + * @brief Clear the PWMSYNC flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearPwmSyncMode(FTU_Type *pFtu) +{ + pFtu->MODE &= ~FTU_MODE_PWMSYNC_MASK; +} + +/** + * @brief Set the REINIT flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetReinitBySync(FTU_Type *pFtu) +{ + pFtu->SYNC |= FTU_SYNC_REINIT_MASK; +} + +/** + * @brief Clear the REINIT flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearReinitBySync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~FTU_SYNC_REINIT_MASK; +} + +/** + * @brief Set the CNTMAX flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableMaxLoadPoint(FTU_Type *pFtu) +{ + pFtu->SYNC |= FTU_SYNC_CNTMAX_MASK; +} + +/** + * @brief Clear the CNTMAX flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableMaxLoadPoint(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~FTU_SYNC_CNTMAX_MASK; +} + +/** + * @brief Set the CNTMIN flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableMinLoadPoint(FTU_Type *pFtu) +{ + pFtu->SYNC |= FTU_SYNC_CNTMIN_MASK; +} + +/** + * @brief Clear the CNTMIN flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableMinLoadPoint(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~FTU_SYNC_CNTMIN_MASK; +} + +/** + * @brief Set the CHNSEL flag of a channel + * + * @param pFtu the base address of the FTU instance + * @param u32Channel channel index + */ +LOCAL_INLINE void FTU_HWA_EnableChannelMatchReload(FTU_Type *pFtu, uint32_t u32Channel) +{ + pFtu->PWMLOAD |= FTU_PWMLOAD_CHNSEL((uint32_t)1u << u32Channel); +} + +/** + * @brief Clear the CHNSEL flag of a channel + * + * @param pFtu the base address of the FTU instance + * @param u32Channel channel index + */ +LOCAL_INLINE void FTU_HWA_DisableChannelMatchReload(FTU_Type *pFtu, uint32_t u32Channel) +{ + pFtu->PWMLOAD &= ~FTU_PWMLOAD_CHNSEL((uint32_t)1u << u32Channel); +} + +/** + * @brief configure the frequency of the reload opportunities + * + * @param pFtu the base address of the FTU instance + * @param u8Freq the number of enabled reload opportunities that should happen until an + * enabled reload opportunity becomes a reload point + */ +LOCAL_INLINE void FTU_HWA_ConfigFreqOfReloadOp(FTU_Type *pFtu, uint8_t u8Freq) +{ + pFtu->CONF = (pFtu->CONF & (~FTU_CONF_LDFQ_MASK)) | FTU_CONF_LDFQ(u8Freq); +} + +/** + * @brief Selects the FTU behavior in Debug mode + * + * @param pFtu the base address of the FTU instance + * @param u32Mode debug mode + */ +LOCAL_INLINE void FTU_HWA_ConfigDebugMode(FTU_Type *pFtu, uint32_t u32Mode) +{ + pFtu->CONF = (pFtu->CONF & (~FTU_CONF_DBG_MASK)) | FTU_CONF_DBG(u32Mode); +} +#ifdef FTU_UPDOWN_DIS_FEATURE +/** + * @brief Disable channel match trigger/interrupt when count-up/down in CPWM/QUAD mode + * + * @param pFtu the base address of the FTU instance + * @param eUpdownDisable up-down disable mode + */ +LOCAL_INLINE void FTU_HWA_ConfigUpDownDisable(FTU_Type *pFtu, FTU_UpDownDisableType eUpdownDisable) +{ + pFtu->SC = (pFtu->SC & (~FTU_SC_UPDOWN_DIS_MASK)) | FTU_SC_UPDOWN_DIS((uint32_t)eUpdownDisable); +} +#endif + +#ifdef FTU_FDUTYCTL_EXIST +/** + * @brief Enable channel interrupt when CPWM full duty cycle + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableFullDutyIntrEnable(FTU_Type *pFtu) +{ + pFtu->SC |= FTU_SC_FDUTYCTL_MASK; +} + +/** + * @brief Disable channel interrupt when CPWM full duty cycle + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableFullDutyIntrEnable(FTU_Type *pFtu) +{ + pFtu->SC &= ~FTU_SC_FDUTYCTL_MASK; +} +#endif +/** + * @brief Enable reload point interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableReloadPointInterrupt(FTU_Type *pFtu) +{ + pFtu->SC |= FTU_SC_RIE_MASK; +} + +/** + * @brief Disable reload point interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableReloadPointInterrupt(FTU_Type *pFtu) +{ + pFtu->SC &= ~((uint32_t)FTU_SC_RIE_MASK); +} + +/** + * @brief Enable software output control of channels + * + * @param pFtu the base address of the FTU instance + * @param u32Mask channel mask + */ +LOCAL_INLINE void FTU_HWA_EnalbeSWOControl(FTU_Type *pFtu, uint32_t u32Mask) +{ + pFtu->SWOCTRL |= FTU_SWOCTRL_CHNOC(u32Mask); +} + +/** + * @brief Disable software output control of channels + * + * @param pFtu the base address of the FTU instance + * @param u32Mask channel mask + */ +LOCAL_INLINE void FTU_HWA_DisalbeSWOControl(FTU_Type *pFtu, uint32_t u32Mask) +{ + pFtu->SWOCTRL &= ~FTU_SWOCTRL_CHNOC(u32Mask); +} + +/** + * @brief Set the software output control value + * + * @param pFtu the base address of the FTU instance + * @param u32Mask channel mask + */ +LOCAL_INLINE void FTU_HWA_SetSWOValue(FTU_Type *pFtu, uint32_t u32Mask) +{ + pFtu->SWOCTRL |= FTU_SWOCTRL_CHNOCV(u32Mask); +} + +/** + * @brief Clear the software output control value + * + * @param pFtu the base address of the FTU instance + * @param u32Mask channel mask + */ +LOCAL_INLINE void FTU_HWA_ClearSWOValue(FTU_Type *pFtu, uint32_t u32Mask) +{ + pFtu->SWOCTRL &= ~FTU_SWOCTRL_CHNOCV(u32Mask); +} + +/** + * @brief Configure the pair deadtime prescaler value + * + * @param pFtu the base address of the FTU instance + * @param u32Channel channel index + * @param ePrescaler prescaler value + */ +LOCAL_INLINE void FTU_HWA_ConfigPairDeadtimePrescaler(FTU_Type *pFtu, uint32_t u32Channel, FTU_DeadTimePrescalerType ePrescaler) +{ + u32Channel &= (~1u); + ((volatile uint32_t *)(&pFtu->PAIR0DEADTIME))[u32Channel] = + ((((volatile uint32_t *)(&pFtu->PAIR0DEADTIME))[u32Channel]) & (~(uint32_t)FTU_DEADTIME_DTPS_MASK)) + | FTU_DEADTIME_DTPS(ePrescaler); +} + +/** + * @brief Configure the deadtime value + * + * @param pFtu the base address of the FTU instance + * @param u32Channel channel index + * @param u32Value deadtime value + */ +LOCAL_INLINE void FTU_HWA_ConfigPairDeadtimeValue(FTU_Type *pFtu, uint32_t u32Channel, uint32_t u32Value) +{ + u32Channel &= (~1u); + ((volatile uint32_t *)(&pFtu->PAIR0DEADTIME))[u32Channel] = + ((((volatile uint32_t *)(&pFtu->PAIR0DEADTIME))[u32Channel]) & (~(uint32_t)(FTU_DEADTIME_DTVAL_MASK | FTU_DEADTIME_DTVALEX_MASK))) + | FTU_DEADTIME_DTVAL(u32Value & 0x3Fu) | FTU_DEADTIME_DTVALEX(u32Value >> 6); +} + +/** + * @brief Configure the deadtime prescaler value + * + * @param pFtu the base address of the FTU instance + * @param ePrescaler prescaler value + */ +LOCAL_INLINE void FTU_HWA_ConfigDeadtimePrescaler(FTU_Type *pFtu, FTU_DeadTimePrescalerType ePrescaler) +{ + pFtu->DEADTIME = (pFtu->DEADTIME & (~(uint32_t)FTU_DEADTIME_DTPS_MASK)) | FTU_DEADTIME_DTPS(ePrescaler); +} + +/** + * @brief Configure the deadtime value + * + * @param pFtu the base address of the FTU instance + * @param u32Value deadtime value + */ +LOCAL_INLINE void FTU_HWA_ConfigDeadtimeValue(FTU_Type *pFtu, uint32_t u32Value) +{ + pFtu->DEADTIME = (pFtu->DEADTIME & ((uint32_t)(FTU_DEADTIME_DTVAL_MASK | FTU_DEADTIME_DTVALEX_MASK))) + | FTU_DEADTIME_DTVAL(u32Value & 0x3Fu) | FTU_DEADTIME_DTVALEX(u32Value >> 6); +} + +/** + * @brief Get the counter value of the selected FTU module + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE uint32_t FTU_HWA_GetCounterValue(FTU_Type *pFtu) +{ + return (uint32_t)pFtu->CNT; +} + +/** + * @brief Clear FTU counter + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue CNT register value + */ +LOCAL_INLINE void FTU_HWA_ClearModuleCounter(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->CNT = u32RegValue; +} + +/** + * @brief Configure FTU channel + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + * @param u32RegValue the value to write to CSC register + */ +LOCAL_INLINE void FTU_HWA_ConfigChannel(FTU_Type *pFtu, uint8_t u8Channel, uint32_t u32RegValue) +{ + pFtu->CONTROLS[u8Channel].CSCn = u32RegValue; +} + +/** + * @brief Get FTU channel value + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + * @return CVn register value + */ +LOCAL_INLINE uint32_t FTU_HWA_GetChannelValue(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (pFtu->CONTROLS[u8Channel].CVn); +} + +/** + * @brief Set FTU channel value + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + * @param u32RegValue CVn register value + */ +LOCAL_INLINE void FTU_HWA_SetChannelValue(FTU_Type *pFtu, uint8_t u8Channel, uint32_t u32RegValue) +{ + pFtu->CONTROLS[u8Channel].CVn = u32RegValue; +} + +/** + * @brief Set FTU counter compare val + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue MOD register value + */ +LOCAL_INLINE void FTU_HWA_SetModuleCompareValue(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->MOD = u32RegValue & FTU_MOD_MASK; +} + +/** + * @brief Set FTU counter initial value + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue CNTIN register value + */ +LOCAL_INLINE void FTU_HWA_SetCounterInitialValue(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->CNTIN = u32RegValue & FTU_CNTIN_INIT_MASK; +} + +/** + * @brief Configure FTU mode + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue MODE register value + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleMode(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->MODE = u32RegValue; +} + +/** + * @brief Configure FTU deadtime + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue DEADTIME register value + */ +LOCAL_INLINE void FTU_HWA_ConfigDeadtime(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->DEADTIME = u32RegValue; +} + +/** + * @brief Configure input capture filter + * + * @param pFtu the base address of the FTU instance + * @param u32Channel Channel of FTU instance + * @param u32FilterValue Filter value + */ +LOCAL_INLINE void FTU_HWA_ConfigInputCaptureFilter(FTU_Type *pFtu, uint32_t u32Channel, uint32_t u32FilterValue) +{ + u32Channel = u32Channel << 2; + pFtu->FILTER = (pFtu->FILTER & (~((uint32_t)0xFu << u32Channel))) + | (u32FilterValue << u32Channel); +} + +/** + * @brief Enable FTU module fault + * + * @param pFtu the base address of the FTU instance + * @param u8InputMask Fault input mask, 0-3 bit indicate fault 0-3 + */ +LOCAL_INLINE void FTU_HWA_EnableModuleFault(FTU_Type *pFtu, uint8_t u8InputMask) +{ + pFtu->FLTCTRL |= ((uint32_t)u8InputMask & (uint32_t)0xFU); +} + +/** + * @brief get the fault input enable status + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE uint32_t FTU_HWA_GetFaultEnable(FTU_Type *pFtu) +{ + return (pFtu->FLTCTRL & (uint32_t)0xFU); +} + +/** + * @brief Disable FTU module fault + * + * @param pFtu the base address of the FTU instance + * @param u8Input Fault input number, 0-3 bit indicate fault 0-3 + */ +LOCAL_INLINE void FTU_HWA_DisableModuleFault(FTU_Type *pFtu, uint8_t u8Input) +{ + pFtu->FLTCTRL &= ~((uint32_t)u8Input & (uint32_t)0xFU); +} + +/** + * @brief Enable FTU module fault glitch filter + * + * @param pFtu the base address of the FTU instance + * @param u8Input Fault input number, 0-3 bit indicate fault 0-3 + */ +LOCAL_INLINE void FTU_HWA_EnableModuleFaultGlitchFilter(FTU_Type *pFtu, uint8_t u8Input) +{ + pFtu->FLTCTRL |= (((uint32_t)u8Input & (uint32_t)0xFU) << 4U); +} + +/** + * @brief Disable FTU module fault glitch filter + * + * @param pFtu the base address of the FTU instance + * @param u8Input Fault input number, 0-3 bit indicate fault 0-3 + */ +LOCAL_INLINE void FTU_HWA_DisableModuleFaultGlitchFilter(FTU_Type *pFtu, uint8_t u8Input) +{ + pFtu->FLTCTRL &= ~(((uint32_t)u8Input & (uint32_t)0xFU) << FTU_FLTCTRL_FLT0GFEN_SHIFT); +} + +/** + * @brief Set FTU module fault filter value + * + * @param pFtu the base address of the FTU instance + * @param u8Value FTU fault filter value + */ +LOCAL_INLINE void FTU_HWA_SetModuleFaultFilterValue(FTU_Type *pFtu, uint8_t u8Value) +{ + pFtu->FLTCTRL = (pFtu->FLTCTRL & ~(uint32_t)FTU_FLTCTRL_FFVAL_MASK) | FTU_FLTCTRL_FFVAL(u8Value); +} + +#ifdef FTU_FAULT_DIS_DELAY_FEATURE +/** + * @brief Set FTU module fault disable channel output delay value0 + * + * @param pFtu the base address of the FTU instance + * @param u8Value FTU fault delay value0 + */ +LOCAL_INLINE void FTU_HWA_SetFaultDelay0(FTU_Type *pFtu, uint8_t u8Value) +{ + pFtu->FLTCTRL = (pFtu->FLTCTRL & (~(uint32_t)FTU_FLTCTRL_FDLYV0_MASK)) + | FTU_FLTCTRL_FDLYV0(u8Value); +} + +/** + * @brief Set FTU module fault disable channel output delay value + * + * @param pFtu the base address of the FTU instance + * @param u8Value FTU fault delay value1 + */ +LOCAL_INLINE void FTU_HWA_SetFaultDelay1(FTU_Type *pFtu, uint8_t u8Value) +{ + pFtu->FLTPOL = (pFtu->FLTPOL & (~(uint32_t)FTU_FLTPOL_FDLYV1_MASK)) + | FTU_FLTPOL_FDLYV1(u8Value); +} +#endif +/** + * @brief Configure FTU module fault polarity + * + * @param pFtu the base address of the FTU instance + * @param u32FaultIndex index of the fault + * @param u8InputPol the polarity of the fault input + */ +LOCAL_INLINE void FTU_HWA_ConfigFaultPolarity(FTU_Type *pFtu, uint32_t u32FaultIndex, uint8_t u8InputPol) +{ + pFtu->FLTPOL = (pFtu->FLTPOL & (~(uint32_t)(FTU_FLTPOL_FLT0POL_MASK << u32FaultIndex))) + | (FTU_FLTPOL_FLT0POL(u8InputPol) << u32FaultIndex); +} + +/** + * @brief Set FTU module prescale + * + * @param pFtu the base address of the FTU instance + * @param ePs FTU clock prescaler enumeration + */ +LOCAL_INLINE void FTU_HWA_SetModulePrescale(FTU_Type *pFtu, FTU_PrescalerType ePs) +{ + pFtu->SC = (pFtu->SC & ~(uint32_t)FTU_SC_PS_MASK) | FTU_SC_PS(ePs); +} + +/** + * @brief Read FTU module overflow flag + * + * @param pFtu the base address of the FTU instance + * @return FTU overflow flag + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadModuleOverflowFlag(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_TOF_MASK) >> FTU_SC_TOF_SHIFT); +} + +/** + * @brief Read FTU module overflow interrupt enable + * + * @param pFtu the base address of the FTU instance + * @return FTU overflow interrupt enable + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadModuleOverflowIntrEnable(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_TOIE_MASK) >> FTU_SC_TOIE_SHIFT); +} + +/** + * @brief Read FTU module reload flag + * + * @param pFtu the base address of the FTU instance + * @return FTU reload flag + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadModuleReloadFlag(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_RF_MASK) >> FTU_SC_RF_SHIFT); +} + +/** + * @brief Read FTU module reload interrupt enable + * + * @param pFtu the base address of the FTU instance + * @return reload interrupt enable + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadReloadIntrEnable(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_RIE_MASK) >> FTU_SC_RIE_SHIFT); +} + +/** + * @brief Read FTU channel interrupt flag + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @return FTU channel interrupt flag + */ +LOCAL_INLINE bool FTU_HWA_ReadChannelInterruptFlag(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (0u != (pFtu->CONTROLS[u8Channel].CSCn & (uint32_t)FTU_CnSC_CHF_MASK)); +} + +/** + * @brief Configure the channel output mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param eMode output mode of the selected channel. + */ +LOCAL_INLINE void FTU_HWA_ConfigTrigOutputMode(FTU_Type *pFtu, uint8_t u8Channel, FTU_TrigOutputModeType eMode) +{ + pFtu->CONTROLS[u8Channel].CSCn = (pFtu->CONTROLS[u8Channel].CSCn & (~(uint32_t)FTU_CnSC_TRIGMODE_MASK)) + | (uint32_t)FTU_CnSC_TRIGMODE(eMode); +} +#ifdef FTU_FAULT_DIS_DELAY_FEATURE +/** + * @brief Select fault disable channel output delay value + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param eSelection Fault disable channel output delay value selection. + */ +LOCAL_INLINE void FTU_HWA_SelectFaultDelay(FTU_Type *pFtu, uint8_t u8Channel, FTU_FaultDisableDelayType eSelection) +{ + pFtu->CONTROLS[u8Channel].CSCn = (pFtu->CONTROLS[u8Channel].CSCn & (~(uint32_t)FTU_CnSC_FDLYSEL_MASK)) + | (uint32_t)FTU_CnSC_FDLYSEL(eSelection); +} +#endif +/** + * @brief Read FTU channel interrupt enable flag + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @return FTU channel interrupt flag + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadChannelInterruptEnableFlag(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (uint8_t)((pFtu->CONTROLS[u8Channel].CSCn & (uint32_t)FTU_CnSC_CHIE_MASK) >> FTU_CnSC_CHIE_SHIFT); +} + +/** + * @brief Read FTU module fault(n) flag + * + * @param pFtu the base address of the FTU instance + * @return FTU fault flag + */ +LOCAL_INLINE uint32_t FTU_HWA_ReadModuleFaultFlag(FTU_Type *pFtu) +{ + return (uint32_t)(pFtu->FMS & (uint32_t)0xFU); +} + +/** + * @brief Read FTU module fault interrupt enable + * + * @param pFtu the base address of the FTU instance + * @return FTU fault interrupt enable + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadFaultIntrEnable(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->MODE & (uint32_t)FTU_MODE_FAULTIE_MASK) >> FTU_MODE_FAULTIE_SHIFT); +} + +/** + * @brief Read FTU module fault detection flag + * + * @param pFtu the base address of the FTU instance + * @return FTU fault detection flag + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadModuleFaultDetectionFlag(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->FMS & (uint32_t)FTU_FMS_FAULTF_MASK) >> FTU_FMS_FAULTF_SHIFT); +} + +/** + * @brief Enable FTU module channel(n) output + * + * @param pFtu the base address of the FTU instance + * @param u8ChannelMask 0-7 bit indicate 0-7 channel + */ +LOCAL_INLINE void FTU_HWA_EnableChannelsOutput(FTU_Type *pFtu, uint8_t u8ChannelMask) +{ + pFtu->SC |= (uint32_t)FTU_SC_CHNOUTEN(u8ChannelMask); +} + +/** + * @brief Get cpwm mode of the FTU module + * + * @param pFtu the base address of the FTU instance + * @return cpwm mode bit value of the FTU module + */ +LOCAL_INLINE uint8_t FTU_HWA_GetModuleCpwmMode(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_CPWMS_MASK) >> FTU_SC_CPWMS_SHIFT); +} + +/** + * @brief Enable FTU module cpwm mode + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableModuleCpwmMode(FTU_Type *pFtu) +{ + pFtu->SC |= (uint32_t)FTU_SC_CPWMS_MASK; +} + +/** + * @brief Disable FTU module cpwm mode + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableModuleCpwmMode(FTU_Type *pFtu) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_CPWMS_MASK; +} + +/** + * @brief Set FTU module filter prescale + * + * @param pFtu the base address of the FTU instance + * @param eFilterPs FTU clock filter prescaler enumeration + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleFilterPrescale(FTU_Type *pFtu, FTU_FilterPrescalerType eFilterPs) +{ + pFtu->SC = (pFtu->SC & (~(uint32_t)FTU_SC_FLTPS_MASK)) + | FTU_SC_FLTPS(eFilterPs); +} + +#ifdef FTU_CNT_SEL_EXIST +/** + * @brief Select the FTU counter + * + * @param pFtu the base address of the FTU instance + * @param eCntSel FTU Counter select + */ +LOCAL_INLINE void FTU_HWA_ConfigFTUCntSel(FTU_Type *pFtu, FTU_CounterSelectType eCntSel) +{ + pFtu->SC = (pFtu->SC & (~(uint32_t)FTU_SC_FTUCNTSEL_MASK)) | FTU_SC_FTUCNTSEL(eCntSel); +} +#endif + +#ifdef FTU_TCKSEL_EXIST +/** + * @brief Selects the external clock as the FTU function clock + * + * @param pFtu the base address of the FTU instance + * @param eTclk FTU external clock enumeration + */ +LOCAL_INLINE void FTU_HWA_ConfigExternalClkSrc(FTU_Type *pFtu, FTU_TclkSelType eTclk) +{ +#if defined(FTU_SC_TCLKSEL_MASK) + pFtu->SC = (pFtu->SC & (~(uint32_t)FTU_SC_TCLKSEL_MASK)) + | FTU_SC_TCLKSEL(eTclk); +#elif defined(FTU_SC_TCKSEL_MASK) + pFtu->SC = (pFtu->SC & (~(uint32_t)FTU_SC_TCKSEL_MASK)) + | FTU_SC_TCKSEL(eTclk); +#else +#error "No valid FTU_SC_TC*KSEL_MASK definition" +#endif +} +#endif + +LOCAL_INLINE void FTU_HWA_ConfigChannelMode(FTU_Type *pFtu, uint8_t u8Channel, FTU_ChannelModeType eMode) +{ + pFtu->CONTROLS[u8Channel].CSCn = ( pFtu->CONTROLS[u8Channel].CSCn + & (~(uint32_t)(FTU_CnSC_MSB_MASK | FTU_CnSC_MSA_MASK))) + | ( ((uint32_t)eMode << FTU_CnSC_MSA_SHIFT) + & ((uint32_t)(FTU_CnSC_MSB_MASK | FTU_CnSC_MSA_MASK))); +} + +LOCAL_INLINE void FTU_HWA_ConfigChannelEdgeLevel(FTU_Type *pFtu, uint8_t u8Channel, FTU_ChannelEdgeLevelType eEdgeLevel) +{ + pFtu->CONTROLS[u8Channel].CSCn = (pFtu->CONTROLS[u8Channel].CSCn & (~(uint32_t)(FTU_CnSC_ELSB_MASK | FTU_CnSC_ELSA_MASK))) + | (((uint32_t)eEdgeLevel << FTU_CnSC_ELSA_SHIFT) & (uint32_t)(FTU_CnSC_ELSB_MASK | FTU_CnSC_ELSA_MASK)); +} +#ifdef FTU_ICM_FEATURE +LOCAL_INLINE uint8_t FTU_HWA_GetEdgeNumberCount(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (uint8_t)((pFtu->CONTROLS[u8Channel].CSCn & FTU_CnSC_ICEXP_NUM_ICM_ECNT_MASK) >> FTU_CnSC_ICEXP_NUM_ICM_ECNT_SHIFT); +} + +LOCAL_INLINE void FTU_HWA_ConfigEdgeNumber(FTU_Type *pFtu, uint8_t u8Channel, uint8_t u8EdgeNumber) +{ + pFtu->CONTROLS[u8Channel].CSCn = ( pFtu->CONTROLS[u8Channel].CSCn + & ((uint32_t)(~FTU_CnSC_ICEXP_NUM_ICM_ECNT_MASK))) + | FTU_CnSC_ICEXP_NUM_ICM_ECNT(u8EdgeNumber); +} + +/** + * @brief Re-start measurement when in single mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_SingleMeasurement(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CnSC_ICM_SINGLE_MASK; +} +/** + * @brief Set the measurement channel to continuous mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_EnableMeasureContinous(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CnSC_ICM_CONT_MASK; +} +/** + * @brief Set the measurement channel to single mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_DisableMeasureContinous(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CnSC_ICM_CONT_MASK; +} +/** + * @brief Set the channel starts measuring after the first edge is detected + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_EnableMeasureStartImmd(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CnSC_ICDPM_START_MASK; +} + +LOCAL_INLINE void FTU_HWA_ConfigInputCaptureMeasureMode(FTU_Type *pFtu, uint8_t u8Channel, FTU_MeasurementModeType eMode) +{ + pFtu->CONTROLS[u8Channel].CSCn = (pFtu->CONTROLS[u8Channel].CSCn & (~(uint32_t)FTU_CnSC_ICM_MODE_MASK)) + | FTU_CnSC_ICM_MODE(eMode); +} + +/** + * @brief Set the measurement starts immediately after activating the channel + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_DisableMeasureStartImmd(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CnSC_ICDPM_START_MASK; +} + +/** + * @brief Get channel measure mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel + * @return measure mode + */ +LOCAL_INLINE FTU_MeasurementModeType FTU_HWA_GetMeasureMode(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (FTU_MeasurementModeType)((pFtu->CONTROLS[u8Channel].CSCn & FTU_CnSC_ICM_MODE_MASK) >> FTU_CnSC_ICM_MODE_SHIFT); +} +#endif +/** + * @brief Configure Edge-Aligned pwm mode channel to High-true pulses(clear output on match) + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_SetChannelEpwmHighTrue(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn = (pFtu->CONTROLS[u8Channel].CSCn & (~(uint32_t)FTU_CnSC_ELSA_MASK)) + | ((uint32_t)(FTU_CnSC_MSB_MASK | FTU_CnSC_ELSB_MASK)); +} + +/** + * @brief Configure Edge-Aligned pwm mode channel to Low-true pulses(set output on match) + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_SetChannelEpwmLowTrue(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)(FTU_CnSC_MSB_MASK | FTU_CnSC_ELSA_MASK); +} + +/** + * @brief Configure pwm link mode channel + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_ConfigChannelPwmLinkMode(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn = ( pFtu->CONTROLS[u8Channel].CSCn + & (~(uint32_t)(FTU_CnSC_ELSA_MASK | FTU_CnSC_MSB_MASK | FTU_CnSC_MSA_MASK))) + | ((uint32_t)FTU_CnSC_ELSB_MASK); +} + +/** + * @brief Enable FTU channel interrupt + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_EnableChannelInterrupt(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CnSC_CHIE_MASK; +} + +/** + * @brief Set MODE[FTUEN], this field define different free running counter and synchronization behavior. + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetModuleUpdateRegBySync(FTU_Type *pFtu) +{ + pFtu->MODE |= (uint32_t)FTU_MODE_FTUEN_MASK; +} + +/** + * @brief Clear MODE[FTUEN], this field define different free running counter and synchronization behavior. + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearModuleUpdateRegBySync(FTU_Type *pFtu) +{ + pFtu->MODE &= ~(uint32_t)FTU_MODE_FTUEN_MASK; +} + +/** + * @brief Enable FTU module fault interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableModuleFaultInterrupt(FTU_Type *pFtu) +{ + pFtu->MODE |= (uint32_t)FTU_MODE_FAULTIE_MASK; +} + + +/** + * @brief Enable FTU channel dma + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_EnableChannelDma(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CnSC_DMA_MASK; +} + + +/** + * @brief Configure FTU module fault mode + * + * @param pFtu the base address of the FTU instance + * @param eMode Fault mode type + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleFaultMode(FTU_Type *pFtu, FTU_FaultModeType eMode) +{ + pFtu->MODE = (pFtu->MODE & (~(uint32_t)FTU_MODE_FAULTM_MASK)) + | FTU_MODE_FAULTM(eMode); +} + +/** + * @brief Enable synchronization hardware trigger 0 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableTrigger0Sync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_TRIG0_MASK; +} + +/** + * @brief Enable synchronization hardware trigger 1 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableTrigger1Sync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_TRIG1_MASK; +} + +/** + * @brief Enable synchronization hardware trigger 2 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableTrigger2Sync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_TRIG2_MASK; +} + +/** + * @brief Enable FTU module output mask synchronization + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableOutputMaskBySync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_SYNCHOM_MASK; +} + +/** + * @brief Disable FTU module output mask synchronization + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableOutputMaskBySync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_SYNCHOM_MASK; +} + +/** + * @brief Generate FTU software trigger + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_GenerateSwSync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_SWSYNC_MASK; +} + +/** + * @brief Configure FTU trigger mode + * + * @param pFtu the base address of the FTU instance + * @param eTrigMode Trigger mode type + */ +LOCAL_INLINE void FTU_HWA_ConfigTrigMode(FTU_Type *pFtu, FTU_TrigModeType eTrigMode) +{ + pFtu->SYNCONF = (pFtu->SYNCONF & (~(uint32_t)FTU_SYNCONF_HWTRIGMODE_MASK)) + | (uint32_t)FTU_SYNCONF_HWTRIGMODE(eTrigMode); +} + +/** + * @brief Enable channel(n/n+1) deadtime functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelDeadtime(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_DEADTIME_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel(n/n+1) complement functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelComplement(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_COMPLEMENT_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel(n/n+1) synchronization functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelSync(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_SYNCEN_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel(n/n+1) Phase Shift Mode functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelPhase(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_PHASE_CHANNEL(u8Channel); +} +/** + * @brief Disable channel(n/n+1) Phase Shift Mode functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelPhase(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_PHASE_CHANNEL(u8Channel); +} +/** + * @brief Enable channel(n/n+1) Enhanced Phase Shift Mode functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelEnhancedPhase(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_EPHASE_CHANNEL(u8Channel); +} +/** + * @brief Disable channel(n/n+1) Enhanced Phase Shift Mode functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelEnhancedPhase(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_EPHASE_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel(n/n+1) fault functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelFault(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_FAULT_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel trigger out + * + * @param pFtu the base address of the FTU instance + * @param u8ChannelMask FTU channel mask, bit 0-7 indicate channel 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelTriggerOut(FTU_Type *pFtu, uint8_t u8ChannelMask) +{ + pFtu->TRIGCONF = pFtu->TRIGCONF + | FTU_TRIGCONF_CH7TRIG(((uint32_t)u8ChannelMask >> 7u) & 1u) + | FTU_TRIGCONF_CH6TRIG(((uint32_t)u8ChannelMask >> 6u) & 1u) + | FTU_TRIGCONF_CH5TRIG(((uint32_t)u8ChannelMask >> 5u) & 1u) + | FTU_TRIGCONF_CH4TRIG(((uint32_t)u8ChannelMask >> 4u) & 1u) + | FTU_TRIGCONF_CH3TRIG(((uint32_t)u8ChannelMask >> 3u) & 1u) + | FTU_TRIGCONF_CH2TRIG(((uint32_t)u8ChannelMask >> 2u) & 1u) + | FTU_TRIGCONF_CH1TRIG(((uint32_t)u8ChannelMask >> 1u) & 1u) + | FTU_TRIGCONF_CH0TRIG((uint32_t)u8ChannelMask & 1u); +} + +/** + * @brief Disable channel trigger out + * + * @param pFtu the base address of the FTU instance + * @param u8ChannelMask FTU channel mask, bit 0-7 indicate channel 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelTriggerOut(FTU_Type *pFtu, uint8_t u8ChannelMask) +{ + pFtu->TRIGCONF &= (~( FTU_TRIGCONF_CH7TRIG(((uint32_t)u8ChannelMask >> 7u) & 1u) + | FTU_TRIGCONF_CH6TRIG(((uint32_t)u8ChannelMask >> 6u) & 1u) + | FTU_TRIGCONF_CH5TRIG(((uint32_t)u8ChannelMask >> 5u) & 1u) + | FTU_TRIGCONF_CH4TRIG(((uint32_t)u8ChannelMask >> 4u) & 1u) + | FTU_TRIGCONF_CH3TRIG(((uint32_t)u8ChannelMask >> 3u) & 1u) + | FTU_TRIGCONF_CH2TRIG(((uint32_t)u8ChannelMask >> 2u) & 1u) + | FTU_TRIGCONF_CH1TRIG(((uint32_t)u8ChannelMask >> 1u) & 1u) + | FTU_TRIGCONF_CH0TRIG((uint32_t)u8ChannelMask & 1u))); +} + +/** + * @brief clear the channel trigger flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearChannelTriggerFlag(FTU_Type *pFtu) +{ + pFtu->TRIGCONF &= ~FTU_TRIGCONF_TRIGF_MASK; +} + +/** + * @brief Enable reload trigger + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableReloadTrigger(FTU_Type *pFtu) +{ + pFtu->TRIGCONF |= (uint32_t)FTU_TRIGCONF_RELOADTRIGEN_MASK; +} + +/** + * @brief Set channel polarity + * + * @param pFtu the base address of the FTU instance + * @param u8Mask FTU channel mask, bit 0-7 indicate channel 0-7 + */ +LOCAL_INLINE void FTU_HWA_SetChannelPolarity(FTU_Type *pFtu, uint8_t u8Mask) +{ + pFtu->POL |= FTU_POL_POLN(u8Mask); +} + +/** + * @brief Set FTU module outmask + * + * @param pFtu the base address of the FTU instance + * @param u8Channel Bit of channel indicate channel number, range: 0~7 bit + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleOutmask(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->OUTMASK = (pFtu->OUTMASK & (~(uint32_t)0xFFU)) + | ((uint32_t)u8Channel & (uint32_t)0xFFU); +} + +/** + * @brief Set channel filter value + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-3 + * @param u8FilterVal FTU filter value + */ +LOCAL_INLINE void FTU_HWA_ConfigChannelFilterValue(FTU_Type *pFtu, uint8_t u8Channel, uint8_t u8FilterVal) +{ + pFtu->FILTER = (pFtu->FILTER & (~((uint32_t)0xFu << ((uint32_t)u8Channel << 2U)))) + | ((uint32_t)u8FilterVal << ((uint32_t)u8Channel << 2U)); +} + +/** + * @brief Configure quadrature mode + * + * @param pFtu the base address of the FTU instance + * @param eMode FTU quadrature mode + */ +LOCAL_INLINE void FTU_HWA_ConfigQuadratureMode(FTU_Type *pFtu, FTU_QuadratureModeType eMode) +{ + pFtu->QDCTRL = (pFtu->QDCTRL & (~(uint32_t)FTU_QDCTRL_QUADMODE_MASK)) + | ((uint32_t)FTU_QDCTRL_QUADMODE(eMode)); +} + +/** + * @brief inverted polarity of phase B input signal + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnablePhbInv(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_PHBPOL_MASK; +} + +/** + * @brief do not inverted polarity of phase B input signal + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisablePhbInv(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_PHBPOL_MASK; +} + +/** + * @brief inverted polarity of phase A input signal + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnablePhaInv(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_PHAPOL_MASK; +} + +/** + * @brief do not inverted polarity of phase B input signal + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisablePhaInv(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_PHAPOL_MASK; +} + +/** + * @brief Enable phase A glitch filter + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnablePhaGlitchFilter(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_PHAGFEN_MASK; +} + +/** + * @brief Disable phase A glitch filter + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisablePhaGlitchFilter(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_PHAGFEN_MASK; +} + +/** + * @brief Enable phase B glitch filter + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnablePhbGlitchFilter(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_PHBGFEN_MASK; +} + +/** + * @brief Disable phase B glitch filter + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisablePhbGlitchFilter(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_PHBGFEN_MASK; +} + +/** + * @brief Enable FTU module quadrature mode + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableQuadratureMode(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_QUADEN_MASK; +} + +/** + * @brief Disable FTU module quadrature mode + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableQuadratureMode(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_QUADEN_MASK; +} + +/** + * @brief Configure FTU module debug mode + * + * @param pFtu the base address of the FTU instance + * @param eDbgMode debug mode enumeration + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleDebugMode(FTU_Type *pFtu, FTU_DebugModeType eDbgMode) +{ + pFtu->CONF = (pFtu->CONF & (~(uint32_t)FTU_CONF_DBG_MASK)) + | FTU_CONF_DBG(eDbgMode); +} + +/** + * @brief Set FTU module clock source + * + * @param pFtu the base address of the FTU instance + * @param eClkSrc FTU module clock source type + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleClkSrc(FTU_Type *pFtu, FTU_ModuleClkSrcType eClkSrc) +{ + pFtu->SC = (pFtu->SC & (~(uint32_t)FTU_SC_CLKS_MASK)) + | FTU_SC_CLKS(eClkSrc); +} + +/** + * @brief Clear FTU module overflow flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearOverflowFlag(FTU_Type *pFtu) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_TOF_MASK; +} + +/** + * @brief Clear FTU module reload flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearReloadFlag(FTU_Type *pFtu) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_RF_MASK; +} + +/** + * @brief Enable FTU module interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableOverflowInterrupt(FTU_Type *pFtu) +{ + pFtu->SC |= (uint32_t)FTU_SC_TOIE_MASK; +} + +/** + * @brief Disable FTU module overflow interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableOverflowInterrupt(FTU_Type *pFtu) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_TOIE_MASK; +} + +/** + * @brief Clear FTU channel interrupt flag + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_ClearChannelInterruptFlag(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CnSC_CHF_MASK; +} + +/** + * @brief Disable channel interrupt + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_DisableChannelInterrupt(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CnSC_CHIE_MASK; +} + +/** + * @brief Disable write protection + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableWriteProtection(FTU_Type *pFtu) +{ + pFtu->MODE |= (uint32_t)FTU_MODE_WPDIS_MASK; +} + +/** + * @brief Disable FTU module fault interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableModuleFaultInterrupt(FTU_Type *pFtu) +{ + pFtu->MODE &= ~(uint32_t)FTU_MODE_FAULTIE_MASK; +} + +/** + * @brief Disable synchronization hardware trigger 0 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableTrigger0Sync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_TRIG0_MASK; +} + +/** + * @brief Disable synchronization hardware trigger 1 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableTrigger1Sync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_TRIG1_MASK; +} + +/** + * @brief Disable synchronization hardware trigger 2 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableTrigger2Sync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_TRIG2_MASK; +} + +/** + * @brief Disable generate FTU software trigger + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableGenerateSwSync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_SWSYNC_MASK; +} + +/** + * @brief Disable reload trigger + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableReloadTrigger(FTU_Type *pFtu) +{ + pFtu->TRIGCONF &= ~(uint32_t)FTU_TRIGCONF_RELOADTRIGEN_MASK; +} + +/** + * @brief Disable channel(n/n+1) deadtime functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelDeadtime(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_DEADTIME_CHANNEL(u8Channel); +} + +/** + * @brief Disable channel(n/n+1) complement functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelComplement(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_COMPLEMENT_CHANNEL(u8Channel); +} + +/** + * @brief Disable channel(n/n+1) synchronization functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelSync(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_SYNCEN_CHANNEL(u8Channel); +} + +/** + * @brief Disable channel(n/n+1) fault functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelFault(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_FAULT_CHANNEL(u8Channel); +} + +/** + * @brief Clear channel polarity + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel, bit 0-7 indicate channel 0-7 + */ +LOCAL_INLINE void FTU_HWA_ClearChannelPolarity(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->POL &= ~FTU_POL_POLN(u8Channel); +} + +/** + * @brief Get channel polarity + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel, bit 0-7 indicate channel 0-7 + * @return polarity of the channels + */ +LOCAL_INLINE uint32_t FTU_HWA_GetChannelPolarity(FTU_Type *pFtu, uint8_t u8Channel) +{ + return pFtu->POL & FTU_POL_POLN(u8Channel); +} + +/** + * @brief Clear FTU module fault flag + * + * @param pFtu the base address of the FTU instance + * @param u8Flag bit 0-3 indicate fault flag 0-3. + */ +LOCAL_INLINE void FTU_HWA_ClearModuleFaultFlag(FTU_Type *pFtu, uint8_t u8Flag) +{ + pFtu->FMS &= ~(uint32_t)((uint32_t)u8Flag & 0xFu); +} + +/** + * @brief Get FTU Counter Direction In Quadrature Decoder Mode + * + * @param pFtu the base address of the FTU instance + * @return FTU Counter Direction In Quadrature Decoder Mode + */ +LOCAL_INLINE FTU_QuadratureDirectionType FTU_HWA_GetQuadDirection(FTU_Type *pFtu) +{ + return (FTU_QuadratureDirectionType)((pFtu->QDCTRL & FTU_QDCTRL_QUADIR_MASK) + >> FTU_QDCTRL_QUADIR_SHIFT); +} + +/** + * @brief Clear FTU global fault flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearGlobalFaultFlag(FTU_Type *pFtu) +{ + pFtu->FMS &= ~(uint32_t)FTU_FMS_FAULTF_MASK; +} + +/** @}*/ + +#endif + +#endif /* #ifndef _HWA_FTU_H_ */ diff --git a/Inc/HwA_gpio.h b/Inc/HwA_gpio.h new file mode 100644 index 0000000..2d7bfbd --- /dev/null +++ b/Inc/HwA_gpio.h @@ -0,0 +1,151 @@ +/** + * @file HwA_gpio.h + * @author Flagchip + * @brief GPIO hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip071 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip071 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_GPIO_H_ +#define _HWA_GPIO_H_ + +#include "device_header.h" + +#if GPIO_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_gpio HwA_gpio + * @ingroup module_driver_gpio + * @{ + */ + +/** + * @brief Set port output to 1 + * + * @param pGpio Gpio instance + * @param u32Pins Pin numbers + */ +LOCAL_INLINE void GPIO_HWA_SetPortOutput(GPIO_Type *pGpio, uint32_t u32Pins) +{ + pGpio->PSOR = u32Pins; +} + +/** + * @brief Set port output to 0 + * + * @param pGpio Gpio instance + * @param u32Pins Pin numbers + */ +LOCAL_INLINE void GPIO_HWA_ClearPortOutput(GPIO_Type *pGpio, uint32_t u32Pins) +{ + pGpio->PCOR = u32Pins; +} + +/** + * @brief Toggle port output + * + * @param pGpio Gpio instance + * @param u32Pins Pin numbers + */ +LOCAL_INLINE void GPIO_HWA_TogglePort(GPIO_Type *pGpio, uint32_t u32Pins) +{ + pGpio->PTOR = u32Pins; +} + +/** + * @brief Set port direction Input + * + * @param pGpio Gpio instance + * @param u32Pins Pin numbers + */ +LOCAL_INLINE void GPIO_HWA_SetPortDirectionInput(GPIO_Type *pGpio, uint32_t u32Pins) +{ + pGpio->PDDR &= (~u32Pins); +} + +/** + * @brief Set port direction output + * + * @param pGpio Gpio instance + * @param u32Pins Pin numbers + */ +LOCAL_INLINE void GPIO_HWA_SetPortDirectionOutput(GPIO_Type *pGpio, uint32_t u32Pins) +{ + pGpio->PDDR |= u32Pins; +} + +/** + * @brief Read port data input, this register indicate data on pad. + * + * @param pGpio Gpio instance + * @return PDIR register value + */ +LOCAL_INLINE uint32_t GPIO_HWA_ReadPortDataInput(GPIO_Type *pGpio) +{ + return pGpio->PDIR; +} + +/** + * @brief Set pin output to 1 + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_SetPinOutput(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PSOR = (uint32_t)1 << u8Pin; +} + +/** + * @brief Set pin output to 0 + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_ClearPinOutput(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PCOR = (uint32_t)1 << u8Pin; +} + +/** + * @brief Set pin direction + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_SetPinDirection(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PDDR |= (uint32_t)1 << u8Pin; +} + +/** + * @brief Clear pin direction + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_ClearPinDirection(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PDDR &= ~((uint32_t)1 << u8Pin); +} + +/** @}*/ + +#endif + +#endif /* #ifndef _HWA_GPIO_H_ */ diff --git a/Inc/HwA_hrpwm.h b/Inc/HwA_hrpwm.h new file mode 100644 index 0000000..3af602c --- /dev/null +++ b/Inc/HwA_hrpwm.h @@ -0,0 +1,256 @@ +/** + * @file HwA_hrpwm.h + * @author Flagchip + * @brief HRPWM hardware access layer + * @version 2.0.0 + * @date 2024-11-06 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip070 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip070 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_HRPWM_H_ +#define _HWA_HRPWM_H_ +#include "device_header.h" + +#if defined(HRPWM_INSTANCE_COUNT) && (HRPWM_INSTANCE_COUNT > 0U) + +/** + * @defgroup HwA_hrpwm HwA_hrpwm + * @ingroup module_driver_hrpwm + * @{ + */ + +/* Define the unlock write code for the HRPWM module, used to unlock HRPWM registers for configuration */ +#define HRPWM_UNLOCK_WRITE_CODE 0x10248888U +/* Define the lock write code for the HRPWM module, used to lock HRPWM registers to protect configuration */ +#define HRPWM_LOCK_WRITE_CODE 0x1024CAFEU + +/** + * @brief Enable or disable an HRPWM channel + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param u8Channel The HRPWM channel number to control + * @param bEnable True to enable the channel, False to disable the channel + */ +LOCAL_INLINE void HRPWM_HWA_SetChannelEnable(HRPWM_Type * const pHrpwm, uint8_t u8Channel, bool bEnable) +{ + pHrpwm->EN_CTRL = (pHrpwm->EN_CTRL & (~(1U << u8Channel))) | ((uint32_t)bEnable << u8Channel); +} + +/** + * @brief Set bypass mode for an HRPWM channel + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param u8Channel The HRPWM channel number to control + * @param bBypass True to enable bypass mode, False to disable bypass mode + */ +LOCAL_INLINE void HRPWM_HWA_SetChannelBypass(HRPWM_Type * const pHrpwm, uint8_t u8Channel, bool bBypass) +{ + pHrpwm->BYPASS_CTRL = (pHrpwm->BYPASS_CTRL & (~(1U << u8Channel))) | ((uint32_t)bBypass << u8Channel); +} + +/** + * @brief Set Fault bypass enable for an HRPWM channel + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param u8Channel The HRPWM channel number to control + * @param bBypass True to enable HRPWM fault, False to disable HRPWM fault + */ +LOCAL_INLINE void HRPWM_HWA_SetChannelFaultEnable(HRPWM_Type * const pHrpwm, uint8_t u8Channel, bool bBypass) +{ + pHrpwm->FAULT_BYPASS_CTRL = (pHrpwm->FAULT_BYPASS_CTRL & (~(1U << u8Channel))) | ((uint32_t)bBypass << u8Channel); +} + +/** + * @brief Enable or disable the internal LDO + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param bEnable True to enable the internal LDO, False to disable the internal LDO + */ +LOCAL_INLINE void HRPWM_HWA_SetInternalLDOEnable(HRPWM_Type * const pHrpwm, bool bEnable) +{ + pHrpwm->ANA_CTRL = (pHrpwm->ANA_CTRL & (~HRPWM_ANA_CTRL_PH_LDOEN_MASK)) | HRPWM_ANA_CTRL_PH_LDOEN(bEnable); +} + +/** + * @brief Set bypass mode for the internal LDO + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param bEnable True to enable LDO bypass mode, False to disable LDO bypass mode + */ +LOCAL_INLINE void HRPWM_HWA_SetInternalLDOBypass(HRPWM_Type * const pHrpwm, bool bEnable) +{ + pHrpwm->ANA_CTRL = (pHrpwm->ANA_CTRL & (~HRPWM_ANA_CTRL_PH_LDOBYPASSEN_MASK)) | HRPWM_ANA_CTRL_PH_LDOBYPASSEN(bEnable); +} + +/** + * @brief Enable or disable phase generation + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param bEnable True to enable phase generation, False to disable phase generation + */ +LOCAL_INLINE void HRPWM_HWA_SetPhaseGeneration(HRPWM_Type * const pHrpwm, bool bEnable) +{ + pHrpwm->ANA_CTRL = (pHrpwm->ANA_CTRL & (~HRPWM_ANA_CTRL_PH_EN_MASK)) | HRPWM_ANA_CTRL_PH_EN(bEnable); +} + +/** + * @brief Set the value of the ANA_CTRL register + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param u32Value The value to set for the ANA_CTRL register + */ +LOCAL_INLINE void HRPWM_HWA_SetANACtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value) +{ + pHrpwm->ANA_CTRL = u32Value; +} + +/** + * @brief Get the value of the ANA_CTRL register + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @return uint32_t The value of the ANA_CTRL register + */ +LOCAL_INLINE uint32_t HRPWM_HWA_GetANACtrl(HRPWM_Type * const pHrpwm) +{ + return pHrpwm->ANA_CTRL; +} + +/** + * @brief Check if the analog power is OK + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @return true If the analog power is OK, otherwise false + */ +LOCAL_INLINE bool HRPWM_HWA_GetAnolagPowerOK(HRPWM_Type * const pHrpwm) +{ + return (bool)((pHrpwm->ANA_CTRL & HRPWM_ANA_CTRL_ANA_POWER_OK_MASK) >> HRPWM_ANA_CTRL_ANA_POWER_OK_SHIFT); +} + +/** + * @brief Check if phase generation is locked + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @return true If phase generation is locked, otherwise false + */ +LOCAL_INLINE bool HRPWM_HWA_GetPhaseGenLock(HRPWM_Type * const pHrpwm) +{ + return (bool)pHrpwm->ANA_CTRL & HRPWM_ANA_CTRL_PH_LOCK_MASK; +} + +/** + * @brief Unlock HRPWM registers for write operations + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + */ +LOCAL_INLINE void HRPWM_HWA_UnlockRegisterWrite(HRPWM_Type * const pHrpwm) +{ + pHrpwm->LOCK_CTRL = HRPWM_UNLOCK_WRITE_CODE; +} + +/** + * @brief Lock HRPWM registers to prevent write operations + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + */ +LOCAL_INLINE void HRPWM_HWA_LockRegisterWrite(HRPWM_Type * const pHrpwm) +{ + pHrpwm->LOCK_CTRL = HRPWM_LOCK_WRITE_CODE; +} + +/** + * @brief Set fault software release mode + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param u8Channel The HRPWM channel number to configure + * @param bSwRelease True: fault release by writing FAULT_STATUS, False: fault release without software + */ +LOCAL_INLINE void HRPWM_HWA_SetSWFaultRelease(HRPWM_Type * const pHrpwm, uint8_t u8Channel, bool bSwRelease) +{ + pHrpwm->FAULT_SW_CTRL_EN = (pHrpwm->FAULT_SW_CTRL_EN & (~(1U << u8Channel))) | ((uint32_t)bSwRelease << u8Channel); +} + +/** + * @brief Get fault status + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @return uint8_t The current fault status + */ +LOCAL_INLINE uint8_t HRPWM_HWA_GetFaultStatus(HRPWM_Type * const pHrpwm) +{ + return (uint8_t)(pHrpwm->FAULT_STATUS & HRPWM_FAULT_STATUS_MASK); +} + +/** + * @brief Clear fault status + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param u8Mask The fault status mask to clear + */ +LOCAL_INLINE void HRPWM_HWA_ClearFaultStatus(HRPWM_Type * const pHrpwm, uint8_t u8Mask) +{ + pHrpwm->FAULT_STATUS = (uint32_t)u8Mask; +} + +/** + * @brief Set the value of the EN_CTRL register + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param u32Value The value to set for the EN_CTRL register + */ +LOCAL_INLINE void HRPWM_HWA_SetENCtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value) +{ + pHrpwm->EN_CTRL = u32Value; +} + +/** + * @brief Set the value of the BYPASS_CTRL register + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param u32Value The value to set for the BYPASS_CTRL register + */ +LOCAL_INLINE void HRPWM_HWA_SetBypassCtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value) +{ + pHrpwm->BYPASS_CTRL = u32Value; +} + +/** + * @brief Set the value of the FAULT_BYPASS_CTRL register + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param u32Value The value to set for the FAULT_BYPASS_CTRL register + */ +LOCAL_INLINE void HRPWM_HWA_SetFltBypassCtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value) +{ + pHrpwm->FAULT_BYPASS_CTRL = u32Value; +} + +/** + * @brief Set the value of the FAULT_SW_CTRL_EN register + * + * @param pHrpwm Base address pointer of the HRPWM peripheral + * @param u32Value The value to set for the FAULT_SW_CTRL_EN register + */ +LOCAL_INLINE void HRPWM_HWA_SetFltSWCtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value) +{ + pHrpwm->FAULT_SW_CTRL_EN = u32Value; +} + +/** @}*/ + +#endif /* defined(HRPWM_INSTANCE_COUNT) && (HRPWM_INSTANCE_COUNT > 0U) */ +#endif /* _HWA_HRPWM_H_ */ + + diff --git a/Inc/HwA_hsadc.h b/Inc/HwA_hsadc.h new file mode 100644 index 0000000..86897fb --- /dev/null +++ b/Inc/HwA_hsadc.h @@ -0,0 +1,2069 @@ +/** + * @file HwA_hsadc.h + * @author flagchip + * @brief Hardware access layer for HSADC + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip126 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip126 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_HSADC_H_ +#define _HWA_HSADC_H_ + +#include "device_header.h" + +#if HSADC_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_hsadc HwA_hsadc + * @ingroup module_driver_hsadc + * @{ + */ + +/** + * @brief Select the HSADC result alignment + * + */ +typedef enum +{ + HSADC_ALIGN_RIGHT = 0U, /*!< HSADC result is aligned in right */ + HSADC_ALIGN_LEFT = 1U /*!< HSADC result is aligned in left */ +} HSADC_AlignType; + +/** + * @brief Select the HSADC trigger mode + * + * @note This option is only valid in HSADC single sequence mode and HSADC continuous mode. + * In HSADC discontinuous mode, the HSADC trigger mode is fixed as HSADC_TRIGMODE_RISING_EDGE + * + */ +typedef enum +{ + HSADC_TRGMODE_SW = 0U, /*!< HSADC is triggered by software */ + HSADC_TRGMODE_RISING_EDGE = 1U, /*!< HSADC is triggered by hardware trigger on rising edge */ + HSADC_TRGMODE_FALLING_EDGE = 2U, /*!< HSADC is triggered by hardware trigger on falling edge */ + HSADC_TRGMODE_BOTH_EDGE = 3U, /*!< HSADC is triggered by hardware trigger on both edges */ + HSADC_TRGMODE_HIGH_VOLTAGE = 4U, /*!< HSADC is triggered when hardware trigger is high voltage */ + HSADC_TRGMODE_LOW_VOLTAGE = 5U, /*!< HSADC is triggered when hardware trigger is low voltage */ + HSADC_TRGMODE_INTERNAL_PERIODIC = 6U /*!< HSADC is triggered by internal generated periodic trigger */ +} HSADC_TrgModeType; + +/** + * @brief Select the HSADC sequence mode + * + */ +typedef enum +{ + HSADC_SEQMODE_SINGLE = 0U, /*!< HSADC single sequence mode */ + HSADC_SEQMODE_CONTINUOUS = 1U, /*!< HSADC continuous mode */ + HSADC_SEQMODE_DISCONTINUOUS = 2U, /*!< HSADC discontinuous mode */ + /*!< 3 is reserved*/ + HSADC_SEQMODE_GROUP = 4U /*!< HSADC sequence group mode */ +} HSADC_SeqModeType; + +typedef enum +{ + HSADC_FAST_CMP_REFMODE_SW = 0U, + HSADC_FAST_CMP_REFMODE_RAMP = 1U, + HSADC_FAST_CMP_REFMODE_ALT = 2U +} HSADC_FastCmpRefMode; + +typedef enum +{ + HSADC_FAST_CMP_RAMPDIR_UP = 0U, + HSADC_FAST_CMP_RAMPDIR_DOWN = 1U +} HSADC_FastCmpRampDir; + +typedef enum +{ + HSADC_FAST_CMP_RAMPTRGMODE_SW_AUTO = 0U, + HSADC_FAST_CMP_RAMPTRGMODE_SW_EXT = 1U, + HSADC_FAST_CMP_RAMPTRGMODE_EXT_AUTO = 2U +} HSADC_FastCmpRampTrgMode; + + +typedef enum +{ + HSADC_FAST_CMP_RAMPTRGPOL_RISING_OR_HIGH = 0U, + HSADC_FAST_CMP_RAMPTRGPOL_FALLING_OR_LOW = 1U, +} HSADC_FastCmpRampTrgPolarity; + +typedef enum +{ + HSADC_FAST_CMP_BFA_A1B0 = 0U, + HSADC_FAST_CMP_BFA_A0B1 = 1U, +} HSADC_FCmpBFLAction; + +/** + * @brief Select the HSADC overrun management mode + * + * To select whether the old data are preserved or overwritten by the new data when HSADC + * is overrun (The FIFO is full when new convertion result comes) + * + */ +typedef enum +{ + HSADC_OVERRUN_MODE_PRESERVE = 0U, /*!< old data are preserved when HSADC is overrun */ + HSADC_OVERRUN_MODE_OVERWRITE = 1U /*!< old data are overwritten when HSADC is overrun */ +} HSADC_OvrModeType; + +/** + * @brief Select the priority of Trigger Latch Unit + * + */ +typedef enum +{ + TRG_LATCH_UNIT_PRI_ROUND_ROBIN = 0U, /*!< select the round robin scheduling priority */ + TRG_LATCH_UNIT_PRI_FIX = 1U /*!< select the fixed priority(0>1>2>3) */ +} HSADC_TrgLatchUnitPri; + +/** + * @brief Select the HSADC hardware average samples + * + */ +typedef enum +{ + HSADC_AVERAGE_LEN_4 = 0U, /*!< result average by 4 samples */ + HSADC_AVERAGE_LEN_8 = 1U, /*!< result average by 8 samples */ + HSADC_AVERAGE_LEN_16 = 2U, /*!< result average by 16 samples */ + HSADC_AVERAGE_LEN_32 = 3U /*!< result average by 32 samples */ +} HSADC_AverageLenType; + +/** + * @brief Set the HSADC clock divider + * + * @note HSADC clock divider is not available in FC7300F512K + * + */ +typedef enum +{ + HSADC_CLOCK_DIV_1 = 0U, + HSADC_CLOCK_DIV_2 = 1U, + HSADC_CLOCK_DIV_4 = 2U, + HSADC_CLOCK_DIV_8 = 3U +} HSADC_ClockDivideType; + +/** + * @brief The trigger source of the HSADC instance + * + * @note In HSADC discontinuous 1 mode, the trigger source is from Ptimer + * In HSADC single and continuous mode, if hardware trigger is enabled, the trigger + * source is from TRGSEL + * + */ +typedef enum +{ + HSADC_TRGSRC_TRGSEL = 2U, /**< Trigger source from TRGSEL */ + HSADC_TRGSRC_TRIG_LATCH_UNIT = 3U /**< Trigger source from LATCH UNIT */ +} HSADC_TrgSrcType; + +/** + * @brief Select the channel compare mode + * + * Select whether the channel compare is enabled on all channels or on the single + * selected channel + * + */ +typedef enum +{ + HSADC_CMP_CHANNEL_ALL = 0U, /*!< Compare enabled in all channels */ + HSADC_CMP_CHANNEL_SINGLE = 1U /*!< Compare enabled in the specified channel */ +} HSADC_CmpChannelType; + +typedef enum +{ + FUNCTION_CLOCK_FROM_PCC = 0U, + FUNCTION_CLOCK_FROM_PAD = 1U +} HSADC_FunctionClockType; + +/** + * @brief The HSADC Sequence Group Index + * + */ +typedef enum +{ + HSADC_SEQ_GROUP_0 = 0U, + HSADC_SEQ_GROUP_1 = 1U, +} HSADC_SeqGroupIndex; + +/** + * @brief Check whether detect fast compare falling edge + * + * @param pHsadc the base address of the HSADC instance + * @return true detect fast compare falling edge + * @return false not detect fast compare falling edge + */ +LOCAL_INLINE bool HSADC_HWA_GetFCRFFlag(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->INT_STATUS; + u32TmpVal = (u32TmpVal & HSADC_INT_STATUS_FCR_F_MASK) >> HSADC_INT_STATUS_FCR_F_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the fast compare falling edge flag + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_ClearFCRFFlag(HSADC_Type *const pHsadc) +{ + pHsadc->INT_STATUS = HSADC_INT_STATUS_FCR_F(1U); +} + +/** + * @brief Check whether detect fast compare rising edge + * + * @param pHsadc the base address of the HSADC instance + * @return true detect fast compare rising edge + * @return false not detect fast compare rising edge + */ +LOCAL_INLINE bool HSADC_HWA_GetFCRRFlag(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->INT_STATUS; + u32TmpVal = (u32TmpVal & HSADC_INT_STATUS_FCR_R_MASK) >> HSADC_INT_STATUS_FCR_R_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the fast compare rising edge flag + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_ClearFCRRFlag(HSADC_Type *const pHsadc) +{ + pHsadc->INT_STATUS = HSADC_INT_STATUS_FCR_R(1U); +} + +/** + * @brief Check whether the data quantity in the FIFO is greater than watermark + * + * @param pHsadc the base address of the HSADC instance + * @return true the HSADC FIFO is ready + * @return false the HSADC FIFO is unready + */ +LOCAL_INLINE bool HSADC_HWA_GetFIFOReadyFlag(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->INT_STATUS; + u32TmpVal = (u32TmpVal & HSADC_INT_STATUS_FIFO_RDY_MASK) >> HSADC_INT_STATUS_FIFO_RDY_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the conversion result is in the comparing range + * + * @param pHsadc the base address of the HSADC instance + * @return true the conversion result is in the comparing range + * @return false the conversion result is not in the comparing range + */ +LOCAL_INLINE bool HSADC_HWA_GetCmpFlag(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->INT_STATUS; + u32TmpVal = (u32TmpVal & HSADC_INT_STATUS_ACMP_MASK) >> HSADC_INT_STATUS_ACMP_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the compare flag + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_ClearCmpFlag(HSADC_Type *const pHsadc) +{ + pHsadc->INT_STATUS = HSADC_INT_STATUS_ACMP(1U); +} + +/** + * @brief Check whether the HSADC FIFO is empty + * + * @param pHsadc the base address of the HSADC instance + * @return true the HSADC FIFO is empty + * @return false the HSADC FIFO is not empty + */ +LOCAL_INLINE bool HSADC_HWA_GetFIFOEmptyFlag(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->INT_STATUS; + u32TmpVal = (u32TmpVal & HSADC_INT_STATUS_EMPTY_MASK) >> HSADC_INT_STATUS_EMPTY_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the HSADC FIFO is full + * + * @param pHsadc the base address of the HSADC instance + * @return true the HSADC FIFO is full + * @return false the HSADC FIFO is not full + */ +LOCAL_INLINE bool HSADC_HWA_GetFIFOFullFlag(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->INT_STATUS; + u32TmpVal = (u32TmpVal & HSADC_INT_STATUS_FULL_MASK) >> HSADC_INT_STATUS_FULL_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the overrrun status of the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @return true the HSADC is in overrun status + * @return false the HSADC is not overrun + */ +LOCAL_INLINE bool HSADC_HWA_GetOverrunFlag(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->INT_STATUS; + u32TmpVal = (u32TmpVal & HSADC_INT_STATUS_OVR_MASK) >> HSADC_INT_STATUS_OVR_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the overrun flag of the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_ClearOverrunFlag(HSADC_Type *const pHsadc) +{ + pHsadc->INT_STATUS = HSADC_INT_STATUS_OVR(1U); +} + +/** + * @brief Check whether the HSADC conversion sequence is finished + * + * @param pHsadc the base address of the HSADC instance + * @return true the HSADC conversion sequence is finished + * @return false the HSADC conversion sequence is unfinished + */ +LOCAL_INLINE bool HSADC_HWA_GetEndOfSequenceFlag(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->INT_STATUS; + u32TmpVal = (u32TmpVal & HSADC_INT_STATUS_EOSEQ_MASK) >> HSADC_INT_STATUS_EOSEQ_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the HSADC conversion sequence complete flag + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_ClearEndOfSequenceFlag(HSADC_Type *const pHsadc) +{ + pHsadc->INT_STATUS = HSADC_INT_STATUS_EOSEQ(1U); +} + +/** + * @brief Check whether the current HSADC conversion is finished + * + * @param pHsadc the base address of the HSADC instance + * @return true the current HSADC conversion is finished + * @return false the current HSADC conversion is unfinished + */ +LOCAL_INLINE bool HSADC_HWA_GetEndOfConversionFlag(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->INT_STATUS; + u32TmpVal = (u32TmpVal & HSADC_INT_STATUS_EOC_MASK) >> HSADC_INT_STATUS_EOC_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the HSADC single conversion complete flag + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_ClearEndOfConversionFlag(HSADC_Type *const pHsadc) +{ + pHsadc->INT_STATUS = HSADC_INT_STATUS_EOC(1U); +} + +/** + * @brief Check whether the sampling phase of the current HSADC conversion is finished + * + * @param pHsadc the base address of the HSADC instance + * @return true the sampling phase of the HSADC conversion is finished + * @return false the sampling phase of the HSADC conversion is unfinished + */ +LOCAL_INLINE bool HSADC_HWA_GetEndOfSampleFlag(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->INT_STATUS; + u32TmpVal = (u32TmpVal & HSADC_INT_STATUS_EOSMP_MASK) >> HSADC_INT_STATUS_EOSMP_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the HSADC sampling complete flag + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_ClearEndOfSampleFlag(HSADC_Type *const pHsadc) +{ + pHsadc->INT_STATUS = HSADC_INT_STATUS_EOSMP(1U); +} + +/** + * @brief Check whether the HSADC instance is ready to operate + * + * @param pHsadc the base address of the HSADC instance + * @return true the HSADC instance is ready for a new conversion + * @return false the HSADC instance is unready + */ +LOCAL_INLINE bool HSADC_HWA_GetHSADCReadyFlag(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->INT_STATUS; + u32TmpVal = (u32TmpVal & HSADC_INT_STATUS_ADRDY_MASK) >> HSADC_INT_STATUS_ADRDY_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ready flag of the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_ClearHSADCReadyFlag(HSADC_Type *const pHsadc) +{ + pHsadc->INT_STATUS = HSADC_INT_STATUS_ADRDY(1U); +} + +/** + * @brief Get the fast compare falling edge interrupt + * If enabled, HSADC interrupt is generated when detect fast compare falling edge + * @param pHsadc the base address of the HSADC instance + * @return true fast compare falling interrupt is enabled + * @return false fast compare falling interrupt is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetFCRFIntEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->INT_ENABLE & HSADC_INT_ENABLE_FCR_F_IE_MASK) >> HSADC_INT_ENABLE_FCR_F_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the fast compare falling edge interrupt + * If enabled, HSADC interrupt is generated when detect fast compare falling edge + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable the fast compare falling interrupt + */ +LOCAL_INLINE void HSADC_HWA_SetFCRFIntEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->INT_ENABLE = (pHsadc->INT_ENABLE & ~HSADC_INT_ENABLE_FCR_F_IE_MASK) | HSADC_INT_ENABLE_FCR_F_IE(bEnable); +} + +/** + * @brief Get the fast compare rising edge interrupt + * If enabled, ADC interrupt is generated when detect fast compare rising edge + * @param pAdc the base address of the ADC instance + * @return true fast compare rising interrupt is enabled + * @return false fast compare rising interrupt is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetFCRRIntEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->INT_ENABLE & HSADC_INT_ENABLE_FCR_R_IE_MASK) >> HSADC_INT_ENABLE_FCR_R_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the fast compare rising edge interrupt + * If enabled, HSADC interrupt is generated when detect fast compare rising edge + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable the fast compare rising interrupt + */ +LOCAL_INLINE void HSADC_HWA_SetFCRRIntEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->INT_ENABLE = (pHsadc->INT_ENABLE & ~HSADC_INT_ENABLE_FCR_R_IE_MASK) | HSADC_INT_ENABLE_FCR_R_IE(bEnable); +} + +/** + * @brief Get the FIFO Ready interrupt flag + * If enabled, HSADC interrupt is generated when the FIFO water mark is greater than FWMARK + * @param pHsadc the base address of the HSADC instance + * @return true HSADC FIFO Ready interrupt is enabled + * @return false HSADC FIFO Ready interrupt is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetFIFOReadyIntEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->INT_ENABLE & HSADC_INT_ENABLE_FIFO_RDY_IE_MASK) >> HSADC_INT_ENABLE_FIFO_RDY_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the FIFO Ready interrupt flag + * If enabled, HSADC interrupt is generated when the FIFO water mark is greater than FWMARK + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable the HSADC FIFO Ready interrupt + */ +LOCAL_INLINE void HSADC_HWA_SetFIFOReadyIntEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->INT_ENABLE = (pHsadc->INT_ENABLE & ~HSADC_INT_ENABLE_FIFO_RDY_IE_MASK) | HSADC_INT_ENABLE_FIFO_RDY_IE(bEnable); +} + +/** + * @brief Get the Compare interrupt flag + * If enabled, HSADC interrupt is generated when the HSADC conversion result is not within the compare threshold + * @param pHsadc the base address of the HSADC instance + * @return true HSADC Compare interrupt is enabled + * @return false HSADC Compare interrupt is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetCmpIntEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->INT_ENABLE & HSADC_INT_ENABLE_ACMP_IE_MASK) >> HSADC_INT_ENABLE_ACMP_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Compare interrupt flag + * If enabled, HSADC interrupt is generated when the HSADC conversion result is not within the compare threshold + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable the HSADC Compare interrupt + */ +LOCAL_INLINE void HSADC_HWA_SetCmpIntEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->INT_ENABLE = (pHsadc->INT_ENABLE & ~HSADC_INT_ENABLE_ACMP_IE_MASK) | HSADC_INT_ENABLE_ACMP_IE(bEnable); +} + +/** + * @brief Get the Overrun interrupt flag + * If enabled, HSADC interrupt is generated when the HSADC instance is overrun + * @param pHsadc the base address of the HSADC instance + * @return true HSADC Overrun interrupt is enabled + * @return false HSADC Overrun interrupt is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetOverrunIntEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->INT_ENABLE & HSADC_INT_ENABLE_OVRIE_MASK) >> HSADC_INT_ENABLE_OVRIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Overrun interrupt flag + * If enabled, HSADC interrupt is generated when the HSADC instance is overrun + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable the HSADC Overrun interrupt + */ +LOCAL_INLINE void HSADC_HWA_SetOverrunIntEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->INT_ENABLE = (pHsadc->INT_ENABLE & ~HSADC_INT_ENABLE_OVRIE_MASK) | HSADC_INT_ENABLE_OVRIE(bEnable); +} + +/** + * @brief Get the End of Sequence interrupt enable flag + * If enabled, HSADC interrupt is generated when the HSADC sequence conversion is completed + * @param pHsadc the base address of the HSADC instance + * @return true HSADC End of Sequence interrupt is enabled + * @return false HSADC End of Sequence interrupt is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetEndOfSequenceIntEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->INT_ENABLE & HSADC_INT_ENABLE_EOSEQIE_MASK) >> HSADC_INT_ENABLE_EOSEQIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the End of Sequence interrupt enable flag + * If enabled, HSADC interrupt is generated when the HSADC sequence conversion is completed + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable the HSADC End of Sequence interrupt + */ +LOCAL_INLINE void HSADC_HWA_SetEndOfSequenceIntEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->INT_ENABLE = (pHsadc->INT_ENABLE & ~HSADC_INT_ENABLE_EOSEQIE_MASK) | HSADC_INT_ENABLE_EOSEQIE(bEnable); +} + +/** + * @brief Get the conversion complete interrupt enable flag + * If enabled, HSADC interrupt is generated when each HSADC conversion is completed + * @param pHsadc the base address of the HSADC instance + * @return true the HSADC End of Conversion interrupt is enabled + * @return false the HSADC End of Conversion interrupt is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetEndOfConversionIntEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->INT_ENABLE & HSADC_INT_ENABLE_EOCIE_MASK) >> HSADC_INT_ENABLE_EOCIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the conversion complete interrupt enable flag + * If enabled, HSADC interrupt is generated when each HSADC conversion is completed + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable the conversion complete interrupt + */ +LOCAL_INLINE void HSADC_HWA_SetEndOfConversionIntEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->INT_ENABLE = (pHsadc->INT_ENABLE & ~HSADC_INT_ENABLE_EOCIE_MASK) | HSADC_INT_ENABLE_EOCIE(bEnable); +} + +/** + * @brief Get the sample complete interrupt enable flag + * If enabled, HSADC interrupt is generated when each HSADC conversion finished the sampling phase + * @param pHsadc the base address of the HSADC instance + * @return true the sample complete interrupt is enabled + * @return false the sample complete interrupt is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetEndOfSampleIntEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->INT_ENABLE & HSADC_INT_ENABLE_EOSMPIE_MASK) >> HSADC_INT_ENABLE_EOSMPIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the sample complete interrupt enable flag + * If enabled, HSADC interrupt is generated when each HSADC conversion finished the sampling phase + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable the sample complete interrupt + */ +LOCAL_INLINE void HSADC_HWA_SetEndOfSampleIntEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->INT_ENABLE = (pHsadc->INT_ENABLE & ~HSADC_INT_ENABLE_EOSMPIE_MASK) | HSADC_INT_ENABLE_EOSMPIE(bEnable); +} + +/** + * @brief Get the HSADC ready interrupt enable flag + * If enabled, HSADC interrupt is generated when the HSADC module is ready for conversion + * @param pHsadc the base address of the HSADC instance + * @return true the HSADC ready interrupt is enabled + * @return false the HSADC ready interrupt is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetHSADCReadyIntEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->INT_ENABLE & HSADC_INT_ENABLE_ADRDYIE_MASK) >> HSADC_INT_ENABLE_ADRDYIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the HSADC ready interrupt enable flag + * If enabled, HSADC interrupt is generated when the HSADC module is ready for conversion + * @param pHsadc the base address of the HSADC instance + * @param bEnable Whether to enable the HSADC ready interrupt + */ +LOCAL_INLINE void HSADC_HWA_SetHSADCReadyIntEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->INT_ENABLE = (pHsadc->INT_ENABLE & ~HSADC_INT_ENABLE_ADRDYIE_MASK) | HSADC_INT_ENABLE_ADRDYIE(bEnable); +} + +/** + * @brief Get the interrupt enable config + * + * @param pHsadc the base address of the HSADC instance + * @return uint32_t the interrupt enable config + */ +LOCAL_INLINE uint32_t HSADC_HWA_GetIntEnable(const HSADC_Type *const pHsadc) +{ + return pHsadc->INT_ENABLE; +} + +/** + * @brief Set the interrupt enable + * + * @param u32IntCfg the interrupt enable config + */ +LOCAL_INLINE void HSADC_HWA_SetInterruptEnable(HSADC_Type *const pHsadc, uint32_t u32IntCfg) +{ + pHsadc->INT_ENABLE = u32IntCfg; +} + +/** + * @brief Select HSADC function clock + * + * @param pHsadc the base address of the HSADC instance + * @note To ensure stability, we recommend that the ADSTART ADSTOP ADEN ADDIS + * bits must be 0 before executing this function. + */ +LOCAL_INLINE void HSADC_HWA_SetFClkSel(HSADC_Type *const pHsadc, const HSADC_FunctionClockType Type) +{ + uint32_t u32TmpVal = pHsadc->CTRL & HSADC_CTRL_FCLK_SEL_MASK; + pHsadc->CTRL = u32TmpVal | HSADC_CTRL_ADRST(1U); + pHsadc->CTRL = HSADC_CTRL_ADRST(1U) | HSADC_CTRL_FCLK_SEL(Type); + pHsadc->CTRL = HSADC_CTRL_FCLK_SEL(Type); +} + +/** + * @brief Assert the HSADC hardware Reset bit + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_Reset(HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CTRL; + pHsadc->CTRL = u32TmpVal | HSADC_CTRL_ADRST(1U); + pHsadc->CTRL = u32TmpVal & ~HSADC_CTRL_ADRST_MASK; +} + +/** + * @brief Get whether HSADC is in stopping status + * + * @param pHsadc the base address of the HSADC instance + * @return true the HSADC instance is stopping + * @return false the HSADC instance is not in stopping status + */ +LOCAL_INLINE bool HSADC_HWA_GetStop(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CTRL; + u32TmpVal = (u32TmpVal & HSADC_CTRL_ADSTP_MASK) >> HSADC_CTRL_ADSTP_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Stop the HSADC conversion + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_Stop(HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CTRL; + pHsadc->CTRL = u32TmpVal | HSADC_CTRL_ADSTP(1U); +} + +/** + * @brief Get the conversion start status of the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @return true the conversion of the HSADC instance is started + * @return false the conversion of the HSADC instance has not been started + */ +LOCAL_INLINE bool HSADC_HWA_GetStart(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CTRL; + u32TmpVal = (u32TmpVal & HSADC_CTRL_ADSTART_MASK) >> HSADC_CTRL_ADSTART_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Start the HSADC conversion + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_Start(HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CTRL; + pHsadc->CTRL = (u32TmpVal | HSADC_CTRL_ADSTART(1U)); +} + +/** + * @brief Get whether the HSADC instance is in disable status + * + * @param pHsadc the base address of the HSADC instance + * @return true the HSADC instance is in disable status + * @return false the HSADC instance is not in disable status + */ +LOCAL_INLINE bool HSADC_HWA_GetDisable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CTRL; + u32TmpVal = (u32TmpVal & HSADC_CTRL_ADDIS_MASK) >> HSADC_CTRL_ADDIS_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Disable the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_Disable(HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CTRL; + pHsadc->CTRL = u32TmpVal | HSADC_CTRL_ADDIS(1U); +} + +/** + * @brief Get the enable status of the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @return true the HSADC instance is enabled + * @return false the HSADC instance has not been enabled + */ +LOCAL_INLINE bool HSADC_HWA_GetEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CTRL; + u32TmpVal = (u32TmpVal & HSADC_CTRL_ADEN_MASK) >> HSADC_CTRL_ADEN_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_Enable(HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CTRL; + pHsadc->CTRL = u32TmpVal | HSADC_CTRL_ADEN(1U); +} + +/** + * @brief Get the overrun mode + * + * @param pHsadc the base address of the HSADC instance + * @return HSADC_OVERRUN_MODE_PRESERVE the conversion data is preserved when HSADC is overrun + * @return HSADC_OVERRUN_MODE_OVERWRITE the conversion data is overwritten when HSADC is overrun + */ +LOCAL_INLINE HSADC_OvrModeType HSADC_HWA_GetOverrunMode(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG1 & HSADC_CFG1_OVRMOD_MASK) >> HSADC_CFG1_OVRMOD_SHIFT; + return (HSADC_OvrModeType)u32TmpVal; +} + +/** + * @brief Set the overrun mode + * + * @param pHsadc the base address of the HSADC instance + * @param eOvrMode the overrun mode for the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_SetOverrunMode(HSADC_Type *const pHsadc, HSADC_OvrModeType eOvrMode) +{ + pHsadc->CFG1 = (pHsadc->CFG1 & ~HSADC_CFG1_OVRMOD_MASK) | HSADC_CFG1_OVRMOD(eOvrMode); +} + +/** + * @brief Get the sequence group mode state + * + * @param pHsadc the base address of the HSADC instance + * @return the sequence group mode state + */ +LOCAL_INLINE bool HSADC_HWA_GetSGEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG1 & HSADC_CFG1_SEQGP_EN_MASK) >> HSADC_CFG1_SEQ_LEN_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the sequence group mode state + * + * @param pHsadc the base address of the HSADC instance + * @param the sequence group mode state + */ +LOCAL_INLINE void HSADC_HWA_SetSGEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->CFG1 = (pHsadc->CFG1 & ~HSADC_CFG1_SEQGP_EN_MASK) | HSADC_CFG1_SEQGP_EN(bEnable); +} + +/** + * @brief Get the sequence length of the HSADC conversion sequence + * + * @param pHsadc the base address of the HSADC instance + * @return uint8_t the sequence length of the HSADC conversion sequence + */ +LOCAL_INLINE uint8_t HSADC_HWA_GetSequenceLength(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CFG1; + u32TmpVal = (u32TmpVal & HSADC_CFG1_SEQ_LEN_MASK) >> HSADC_CFG1_SEQ_LEN_SHIFT; + + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the sequence length of the HSADC conversion sequence + * + * @param pHsadc the base address of the HSADC instance + * @param u8SequenceLength the sequence length of the HSADC conversion sequence + */ +LOCAL_INLINE void HSADC_HWA_SetSequenceLength(HSADC_Type *const pHsadc, uint8_t u8SequenceLength) +{ + pHsadc->CFG1 = (pHsadc->CFG1 & ~HSADC_CFG1_SEQ_LEN_MASK) | HSADC_CFG1_SEQ_LEN(u8SequenceLength); +} + +/** + * @brief Get the HSADC sequence mode + * + * @param pHsadc the base address of the HSADC instance + * @return HSADC_SeqModeType the sequence mode the the HSADC instance + */ +LOCAL_INLINE HSADC_SeqModeType HSADC_HWA_GetSequenceMode(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CFG1; + u32TmpVal = (u32TmpVal & HSADC_CFG1_SEQ_MOD_MASK) >> HSADC_CFG1_SEQ_MOD_SHIFT; + + return (HSADC_SeqModeType)u32TmpVal; +} + +/** + * @brief Set the HSADC sequence mode + * + * @param pHsadc the base address of the HSADC instance + * @param eSequenceMode the sequence mode the the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_SetSequenceMode(HSADC_Type *const pHsadc, HSADC_SeqModeType eSequenceMode) +{ + pHsadc->CFG1 = (pHsadc->CFG1 & ~HSADC_CFG1_SEQ_MOD_MASK) | HSADC_CFG1_SEQ_MOD(eSequenceMode); +} + +/** + * @brief Get whether auto disable is enabled + * + * @note Auto disable mode is only available in FC7300F2M + * + * @param pHsadc the base address of the HSADC instance + * @return true auto disable mode is enabled + * @return false auto disable mode is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetAutoDisableModeEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CFG1; + u32TmpVal = (u32TmpVal & HSADC_CFG1_AUTO_DIS_MASK) >> HSADC_CFG1_AUTO_DIS_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable auto disable mode + * + * @note Auto disable mode is only available in FC7300F2M + * + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable auto disable mode + */ +LOCAL_INLINE void HSADC_HWA_SetAutoDisableModeEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->CFG1 = (pHsadc->CFG1 & ~HSADC_CFG1_AUTO_DIS_MASK) | HSADC_CFG1_AUTO_DIS(bEnable); +} + +/** + * @brief Get whether the wait conversion mode is enabled + * + * @param pHsadc the base address of the HSADC instance + * @return true the wait conversion mode is enabled + * @return false the wait conversion mode is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetWaitConversionModeEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG1 & HSADC_CFG1_WAIT_MASK) >> HSADC_CFG1_WAIT_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the wait conversion mode + * + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable the wait conversion mode + */ +LOCAL_INLINE void HSADC_HWA_SetWaitConversionModeEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->CFG1 = (pHsadc->CFG1 & ~HSADC_CFG1_WAIT_MASK) | HSADC_CFG1_WAIT(bEnable); +} + +/** + * @brief Get the trigger source the the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @return HSADC_TrigSrcType the trigger source of the HSADC instance + */ +LOCAL_INLINE HSADC_TrgSrcType HSADC_HWA_GetTriggerSource(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CFG1; + u32TmpVal = (u32TmpVal & HSADC_CFG1_TRIGSRC_MASK) >> HSADC_CFG1_TRIGSRC_SHIFT; + + return (HSADC_TrgSrcType)u32TmpVal; +} + +/** + * @brief Set the trigger source the the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @param eTriggerSource the trigger source of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_SetTriggerSource(HSADC_Type *const pHsadc, HSADC_TrgSrcType eTrgSource) +{ + pHsadc->CFG1 = (pHsadc->CFG1 & ~HSADC_CFG1_TRIGSRC_MASK) | HSADC_CFG1_TRIGSRC(eTrgSource); +} + +/** + * @brief Get the trigger mode of the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @return HSADC_TrigModeType the trigger mode if the HSADC instance + */ +LOCAL_INLINE HSADC_TrgModeType HSADC_HWA_GetTriggerMode(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CFG1; + u32TmpVal = (u32TmpVal & HSADC_CFG1_TRIGMODE_MASK) >> HSADC_CFG1_TRIGMODE_SHIFT; + + return (HSADC_TrgModeType)u32TmpVal; +} + +/** + * @brief Set the trigger mode of the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @param eTriggerMode the trigger mode if the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_SetTriggerMode(HSADC_Type *const pHsadc, HSADC_TrgModeType eTrgMode) +{ + pHsadc->CFG1 = (pHsadc->CFG1 & ~HSADC_CFG1_TRIGMODE_MASK) | HSADC_CFG1_TRIGMODE(eTrgMode); +} + +/** + * @brief Get the data align mode + * + * @param pHsadc the base address of the HSADC instance + * @return HSADC_ALIGN_RIGHT the conversion data is aligned right + * @return HSADC_ALIGN_LEFT the conversion is aligned left + */ +LOCAL_INLINE HSADC_AlignType HSADC_HWA_GetDataAlignment(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG1 & HSADC_CFG1_ALIGN_MASK) >> HSADC_CFG1_ALIGN_SHIFT; + return (HSADC_AlignType)u32TmpVal; +} + +/** + * @brief Set the data align mode + * + * @param pHsadc the base address of the HSADC instance + * @param eAlign the data align mode + */ +LOCAL_INLINE void HSADC_HWA_SetDataAlignment(HSADC_Type *const pHsadc, HSADC_AlignType eAlign) +{ + pHsadc->CFG1 = (pHsadc->CFG1 & ~HSADC_CFG1_ALIGN_MASK) | HSADC_CFG1_ALIGN(eAlign); +} + +/** + * @brief Get SGDMA SEL for the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @return the SGDMA SEL for the HSADC instance + */ +LOCAL_INLINE uint8_t HSADC_HWA_GetSGDMASEL(const HSADC_Type *const pHsadc) +{ + return (pHsadc->CFG1 & HSADC_CFG1_SGDMA_SEL_MASK) >> HSADC_CFG1_SGDMA_SEL_SHIFT; +} + +/** + * @brief Set the SGDMA SEL for the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @param bEnable the SGDMA SEL for the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_SetSGDMASEL(HSADC_Type *const pHsadc, uint8_t index) +{ + pHsadc->CFG1 = (pHsadc->CFG1 & ~HSADC_CFG1_SGDMA_SEL_MASK) | HSADC_CFG1_SGDMA_SEL(index); +} + +/** + * @brief Get whether SGDMA for the HSADC instance is enabled + * + * @param pHsadc the base address of the HSADC instance + * @return true SGDMA is enabled for the HSADC instance + * @return false SGDMA is disabled for the HSADC instance + */ +LOCAL_INLINE bool HSADC_HWA_GetSGDMAEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG1 & HSADC_CFG1_SGDMAEN_MASK) >> HSADC_CFG1_SGDMAEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable or disable the SGDMA for the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable the SGDMA for the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_SetSGDMAEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->CFG1 = (pHsadc->CFG1 & ~HSADC_CFG1_SGDMAEN_MASK) | HSADC_CFG1_DMAEN(bEnable); +} + +/** + * @brief Get whether DMA for the HSADC instance is enabled + * + * @param pHsadc the base address of the HSADC instance + * @return true DMA is enabled for the HSADC instance + * @return false DMA is disabled for the HSADC instance + */ +LOCAL_INLINE bool HSADC_HWA_GetDMAEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG1 & HSADC_CFG1_DMAEN_MASK) >> HSADC_CFG1_DMAEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable or disable the DMA for the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable the DMA for the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_SetDMAEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->CFG1 = (pHsadc->CFG1 & ~HSADC_CFG1_DMAEN_MASK) | HSADC_CFG1_DMAEN(bEnable); +} + +/** + * @brief Get the HSADC_CFG1 config + * + * @param pHsadc the base address of the HSADC instance + * @return uint32_t the HSADC_CFG1 config + */ +LOCAL_INLINE uint32_t HSADC_HWA_GetConfig1(const HSADC_Type *const pHsadc) +{ + return pHsadc->CFG1; +} + +/** + * @brief Set the HSADC_CFG1 config + * + * @param pHsadc the base address of the HSADC instance + * @param u32Config the HSADC_CFG1 config + */ +LOCAL_INLINE void HSADC_HWA_SetConfig1(HSADC_Type *const pHsadc, uint32_t u32Config) +{ + pHsadc->CFG1 = u32Config; +} + +/** + * @brief Get the extend channel enable settings for the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @return bool the HSADC extend channel enable setting + */ +LOCAL_INLINE bool HSADC_HWA_GetExtChEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG2 & HSADC_CFG2_EXT_CH_EN_MASK) >> HSADC_CFG2_EXT_CH_EN_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the extend channel feature for the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @param bEnable the enable/disable flag + */ +LOCAL_INLINE void HSADC_HWA_SetExtChEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->CFG2 = (pHsadc->CFG2 & ~HSADC_CFG2_EXT_CH_EN_MASK) | HSADC_CFG2_EXT_CH_EN(bEnable); +} + +/** + * @brief Get the FIFO water mark settings for the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @return uint8_t the HSADC FIFO water mark setting + */ +LOCAL_INLINE uint8_t HSADC_HWA_GetFIFOWaterMark(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG2 & HSADC_CFG2_FWMARK_MASK) >> HSADC_CFG2_FWMARK_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the FIFO water mark for the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @param u8WaterMark the HSADC FIFO water mark setting + */ +LOCAL_INLINE void HSADC_HWA_SetFIFOWaterMark(HSADC_Type *const pHsadc, uint8_t u8WaterMark) +{ + pHsadc->CFG2 = (pHsadc->CFG2 & ~HSADC_CFG2_FWMARK_MASK) | HSADC_CFG2_FWMARK(u8WaterMark); +} + +LOCAL_INLINE uint8_t HSADC_HWA_GetSmpSpare(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG2 & HSADC_CFG2_SMP_SPARE_EN_MASK) >> HSADC_CFG2_SMP_SPARE_EN_SHIFT; + return (uint8_t)u32TmpVal; +} + +LOCAL_INLINE void HSADC_HWA_SetSmpSpare(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->CFG2 = (pHsadc->CFG2 & ~HSADC_CFG2_SMP_SPARE_EN_MASK) | HSADC_CFG2_SMP_SPARE_EN(bEnable); +} + +/** + * @brief Get the priority of Trigger Latch + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE uint8_t HSADC_HWA_GetTriggerLatchUnitPriority(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG2 & HSADC_CFG2_TRG_PRI_MASK) >> HSADC_CFG2_TRG_PRI_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the priority of Trigger Latch + * + * @param pHsadc the base address of the HSADC instance + * @param eTrgLatchUnitPri the priority of Trigger Latch Unit setting + */ +LOCAL_INLINE void HSADC_HWA_SetTriggerLatchUnitPriority(HSADC_Type *const pHsadc, HSADC_TrgLatchUnitPri eTrgLatchUnitPri) +{ + pHsadc->CFG2 = (pHsadc->CFG2 & ~HSADC_CFG2_TRG_CLR_MASK) | HSADC_CFG2_TRG_CLR(eTrgLatchUnitPri); +} + +/** + * @brief Clear Latch Trigger in Trigger Latch Unit + * + * @param pHsadc the base address of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_ClearLatchTrigger(HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->CFG2; + pHsadc->CFG2 = u32TmpVal | HSADC_CFG2_TRG_CLR(1); +} + +/** + * @brief Get whether hardware average is enabled + * + * @param pHsadc the base address of the HSADC instance + * @return true hardware average is enabled + * @return false hardware average is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetAverageEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG2 & HSADC_CFG2_AVG_EN_MASK) >> HSADC_CFG2_AVG_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable or disable hardware average for the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable the HSADC hardware average + */ +LOCAL_INLINE void HSADC_HWA_SetAverageEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->CFG2 = (pHsadc->CFG2 & ~HSADC_CFG2_AVG_EN_MASK) | HSADC_CFG2_AVG_EN(bEnable); +} + +/** + * @brief Get the hardware average number + * + * @param pHsadc the base address of the HSADC instance + * @return HSADC_AverageType the hardware average number + */ +LOCAL_INLINE HSADC_AverageLenType HSADC_HWA_GetAverageNumber(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG2 & HSADC_CFG2_AVG_LEN_MASK) >> HSADC_CFG2_AVG_LEN_SHIFT; + return (HSADC_AverageLenType)u32TmpVal; +} + +/** + * @brief Set the hardware average number + * + * @param pHsadc the base address of the HSADC instance + * @param eAverageNumber the hardware average number to set + */ +LOCAL_INLINE void HSADC_HWA_SetAverageNumber(HSADC_Type *const pHsadc, HSADC_AverageLenType eAverageNumber) +{ + pHsadc->CFG2 = (pHsadc->CFG2 & ~HSADC_CFG2_AVG_LEN_MASK) | HSADC_CFG2_AVG_LEN(eAverageNumber); +} +/** + * @brief Whether clock gating is acknowledged + * + * @note This feature is only available in FC7300F2M + * + * @param pHsadc the base address of the HSADC instance + * @return true HSADC clock source is off after setting Clock Gating Enable Flag + * @return false HSADC clock source is on after clearing Clock Gating Enable Flag + */ +LOCAL_INLINE bool HSADC_HWA_GetClockGatingAck(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG2 & HSADC_CFG2_CG_ACK_MASK) >> HSADC_CFG2_CG_ACK_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether clock gating is enabled + * + * @note This feature is only available in FC7300F2M + * + * @param pHsadc the base address of the HSADC instance + * @return true Clock gating is enabled, HSADC clock is off + * @return false Clock gating is disabled, HSADC clock is on + */ +LOCAL_INLINE bool HSADC_HWA_GetClockGatingEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG2 & HSADC_CFG2_CG_MASK) >> HSADC_CFG2_CG_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable HSADC clock gating + * + * @note This feature is only available in FC7300F2M + * + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether to enable HSADC clock gating + */ +LOCAL_INLINE void HSADC_HWA_SetClockGatingEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->CFG2 = (pHsadc->CFG2 & ~HSADC_CFG2_CG_MASK) | HSADC_CFG2_CG(bEnable); +} + +/** + * @brief Get the HSADC clock divider + * + * @note This feature is only available in FC7300F2M + * + * @param pHsadc the base address of the HSADC instance + * @return HSADC_ClockDivideType the HSADC clock divider + */ +LOCAL_INLINE HSADC_ClockDivideType HSADC_HWA_GetClockDivider(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG2 & HSADC_CFG2_DIV_MASK) >> HSADC_CFG2_DIV_SHIFT; + return (HSADC_ClockDivideType)u32TmpVal; +} + +/** + * @brief Set the HSADC clock divider + * + * @note Before configuring DIV, must set CG and wait for CG_ACK=1. + * After configuring DIV, must clear CG and wait for CG_ACK=0. + * @note This feature is only available in FC7300F2M + * + * @param pHsadc the base address of the HSADC instance + * @param eDivider the HSADC clock divider to set + */ +LOCAL_INLINE void HSADC_HWA_SetClockDivider(HSADC_Type *const pHsadc, HSADC_ClockDivideType eDivider) +{ + pHsadc->CFG2 = (pHsadc->CFG2 & ~HSADC_CFG2_DIV_MASK) | HSADC_CFG2_DIV(eDivider); +} + +/** + * @brief Get the HSADC start up count + * + * @param pHsadc the base address of the HSADC instance + * @return uint8_t the start count of the HSADC instance + */ +LOCAL_INLINE uint8_t HSADC_HWA_GetStartupCnt(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CFG2 & HSADC_CFG2_STCNT_MASK) >> HSADC_CFG2_STCNT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the HSADC start up count + * + * @param pHsadc the base address of the HSADC instance + * @param u8StartupCnt the start count of the HSADC instance + */ +LOCAL_INLINE void HSADC_HWA_SetStartupCnt(HSADC_Type *const pHsadc, uint8_t u8StartupCnt) +{ + pHsadc->CFG2 = (pHsadc->CFG2 & ~HSADC_CFG2_STCNT_MASK) | HSADC_CFG2_STCNT(u8StartupCnt); +} + +/** + * @brief Get the HSADC_CFG2 config + * + * @param pHsadc the base address of the HSADC instance + * @return uint32_t the HSADC_CFG2 config + */ +LOCAL_INLINE uint32_t HSADC_HWA_GetConfig2(const HSADC_Type *const pHsadc) +{ + return pHsadc->CFG2; +} + +/** + * @brief Set the HSADC_CFG2 config + * + * @param pHsadc the base address of the HSADC instance + * @param u32Config the HSADC_CFG2 config + */ +LOCAL_INLINE void HSADC_HWA_SetConfig2(HSADC_Type *const pHsadc, uint32_t u32Config) +{ + pHsadc->CFG2 = u32Config; +} + +/** + * @brief Get the sample time of the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @param u8Selection the sample time index, range 0~3 + * @return uint8_t the sample time of the selected index + */ +LOCAL_INLINE uint8_t HSADC_HWA_GetSampleTime(HSADC_Type *const pHsadc, uint8_t u8Selection) +{ + uint32_t ret; + ret = (pHsadc->SMPR & (HSADC_SMPR_SMP_OPT0_MASK << (8U * u8Selection))) >> (8U * u8Selection); + return (uint8_t)ret; +} + +/** + * @brief Set the sample time of the HSADC instance + * + * @param pHsadc the base address of the HSADC instance + * @param u8Selection the sample time index, range 0~3 + * @param u8SampleTime the sample time of the selected index + */ +LOCAL_INLINE void HSADC_HWA_SetSampleTime(HSADC_Type *const pHsadc, uint8_t u8Selection, uint8_t u8SampleTime) +{ + DEV_ASSERT(u8Selection < HSADC_SAMPLE_TIME_OPTION_COUNT); + pHsadc->SMPR = (pHsadc->SMPR & ~(HSADC_SMPR_SMP_OPT0_MASK << (8U * u8Selection))) | + (HSADC_SMPR_SMP_OPT0(u8SampleTime) << (8U * u8Selection)); +} + +/** + * @brief Get whether hardware compare is enabled + * + * @param pHsadc the base address of the HSADC instance + * @return true hardware compare is enabled + * @return false hardware compare is disabled + */ +LOCAL_INLINE bool HSADC_HWA_GetCmpEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->CMP_CTRL & HSADC_CMP_CTRL_ACMPEN_MASK) >> HSADC_CMP_CTRL_ACMPEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set to enable or disable the hardware compare + * + * @param pHsadc the base address of the HSADC instance + * @param bEnable whether the HSADC hardware compare is enabled + */ +LOCAL_INLINE void HSADC_HWA_SetCmpEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->CMP_CTRL = (pHsadc->CMP_CTRL & ~HSADC_CMP_CTRL_ACMPEN_MASK) | HSADC_CMP_CTRL_ACMPEN(bEnable); +} + +/** + * @brief Set the HSADC hardware compare channel + * + * @param pHsadc the base address of the HSADC instance + * @param eType whether the hardware compare enabled on single channel or all channels + * @param u8ChannalNum if hardware compare is enabled on single channel, this specifies the channel number + */ +LOCAL_INLINE void HSADC_HWA_SetCmpChannel(HSADC_Type *const pHsadc, HSADC_CmpChannelType eType, + uint8_t u8ChannalNum) +{ + pHsadc->CMP_CTRL = (pHsadc->CMP_CTRL & (~HSADC_CMP_CTRL_ACMPSGL_MASK) & (~HSADC_CMP_CTRL_ACMPCH_MASK)) | + HSADC_CMP_CTRL_ACMPSGL(eType) | HSADC_CMP_CTRL_ACMPCH(u8ChannalNum); +} + +/** + * @brief Set the HSADC hardware compare threshold + * + * @param pHsadc the base address of the HSADC instance + * @param u16LowThres the lower threshold + * @param u16HighThres the higher threshold + */ +LOCAL_INLINE void HSADC_HWA_SetCmpThreshold(HSADC_Type *const pHsadc, uint16_t u16LowThres, uint16_t u16HighThres) +{ + pHsadc->CMP_TR = HSADC_CMP_TR_LT(u16LowThres) | HSADC_CMP_TR_HT(u16HighThres); +} + +/** + * @brief Get the HSADC_CFG3 config + * + * @param pHsadc the base address of the HSADC instance + * @return uint32_t the HSADC_CFG3 config + */ +LOCAL_INLINE uint32_t HSADC_HWA_GetConfig3(const HSADC_Type *const pHsadc) +{ + return pHsadc->CFG3; +} + +/** + * @brief Set the HSADC_CFG3 config + * + * @param pHsadc the base address of the HSADC instance + * @param u32Config the HSADC_CFG3 config + */ +LOCAL_INLINE void HSADC_HWA_SetConfig3(HSADC_Type *const pHsadc, uint32_t u32Config) +{ + pHsadc->CFG3 = u32Config; +} + +/** + * @brief Get the end of sequence group flag + * + * @param pHsadc the base address of the HSADC instance + * @param u8SeqGroupIndex the index of the sequence group + * @param bool the sequence group interrupt flag + */ +LOCAL_INLINE bool HSADC_HWA_GetEndOfSGFlag(HSADC_Type *const pHsadc, const uint8_t u8SeqGroupIndex) +{ + uint32_t u32TmpVal = (pHsadc->SGCSR[u8SeqGroupIndex] & HSADC_SGCSR_EOSG_MASK) >> HSADC_SGCSR_EOSG_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Clear the end of sequence group flag + * + * @param pHsadc the base address of the HSADC instance + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE void HSADC_HWA_ClearEndOfSGFlag(HSADC_Type *const pHsadc, const uint8_t u8SeqGroupIndex) +{ + uint32_t u32TmpVal = pHsadc->SGCSR[u8SeqGroupIndex]; + pHsadc->SGCSR[u8SeqGroupIndex] = (u32TmpVal & ~HSADC_SGCSR_EOSG_MASK) | HSADC_SGCSR_EOSG(1U); +} + +/** + * @brief Set the sequence group end of sequence interrupt enable + * + * @param pHsadc the base address of the HSADC instance + * @param u8SeqGroupIndex the index of the sequence group + * @param bEnable the sequence group interrupt enable or disable + */ +LOCAL_INLINE void HSADC_HWA_SetEndOfSGIntEnable(HSADC_Type *const pHsadc, const uint8_t u8SeqGroupIndex, const bool bEnable) +{ + uint32_t u32TmpVal = pHsadc->SGCSR[u8SeqGroupIndex]; + pHsadc->SGCSR[u8SeqGroupIndex] = (u32TmpVal & ~HSADC_SGCSR_EOSGIE_MASK) | HSADC_SGCSR_EOSGIE(bEnable); +} + +/** + * @brief Set the sequence group end of sequence interrupt enable + * + * @param pHsadc the base address of the HSADC instance + * @param u8SeqGroupIndex the index of the sequence group + * @return bool the sequence group interrupt enable or disable + */ +LOCAL_INLINE bool HSADC_HWA_GetEndOfSGIntEnable(HSADC_Type *const pHsadc, const uint8_t u8SeqGroupIndex) +{ + uint32_t u32TmpVal = pHsadc->SGCSR[u8SeqGroupIndex]; + u32TmpVal = (u32TmpVal & HSADC_SGCSR_EOSGIE_MASK); + return u32TmpVal ? true : false; +} + +/** + * @brief Get the sequence group start point + * + * @param pHsadc the base address of the HSADC instance + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE uint8_t HSADC_HWA_GetSGStartPoint(HSADC_Type *const pHsadc, const uint8_t u8SeqGroupIndex) +{ + return (uint8_t)((pHsadc->SGCSR[u8SeqGroupIndex] & HSADC_SGCSR_SG_START_MASK) >> HSADC_SGCSR_SG_START_SHIFT); +} + +/** + * @brief Get the sequence group end point + * + * @param pHsadc the base address of the HSADC instance + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE uint8_t HSADC_HWA_GetSGEndPoint(HSADC_Type *const pHsadc, const uint8_t u8SeqGroupIndex) +{ + return (uint8_t)((pHsadc->SGCSR[u8SeqGroupIndex] & HSADC_SGCSR_SG_END_MASK) >> HSADC_SGCSR_SG_END_SHIFT); +} + +/** + * @brief Set the sequence group start and end point + * + * @param pHsadc the base address of the HSADC instance + * @param u8SeqGroupIndex the index of the sequence group + * @param u8Start the sequence group start point + * @param u8End the sequence group end point + */ +LOCAL_INLINE void HSADC_HWA_SetSGStartEndPoint(HSADC_Type *const pHsadc, const uint8_t u8SeqGroupIndex, const uint8_t u8Start, const uint8_t u8End) +{ + uint32_t u32TmpVal = pHsadc->SGCSR[u8SeqGroupIndex]; + u32TmpVal = (u32TmpVal & ~HSADC_SGCSR_SG_END_MASK) | HSADC_SGCSR_SG_END(u8End); + u32TmpVal = (u32TmpVal & ~HSADC_SGCSR_SG_START_MASK) | HSADC_SGCSR_SG_START(u8Start); + pHsadc->SGCSR[u8SeqGroupIndex] = u32TmpVal; +} + +LOCAL_INLINE void HSADC_HWA_SetOGCOffset(HSADC_Type *const pHsadc, uint16_t val) +{ + pHsadc->OGCR = (pHsadc->OGCR & ~HSADC_OGCR_OFFSET_MASK) | HSADC_OGCR_OFFSET(val); +} + +LOCAL_INLINE void HSADC_HWA_SetOGCGain(HSADC_Type *const pHsadc, uint16_t val) +{ + pHsadc->OGCR = (pHsadc->OGCR & ~HSADC_OGCR_GAIN_MASK) | HSADC_OGCR_GAIN(val); +} + +LOCAL_INLINE void HSADC_HWA_SetOGCEnable(HSADC_Type *const pHsadc, bool bEnable) +{ + pHsadc->OGCR = (pHsadc->OGCR & ~HSADC_OGCR_OGC_EN_MASK) | HSADC_OGCR_OGC_EN(bEnable); +} + +/** + * @brief Set the HSADC_CCAL config + * + * @param pHsadc the base address of the HSADC instance + * @param u32Cal the HSADC_CCAL config + */ +LOCAL_INLINE void HSADC_HWA_SetCCal(HSADC_Type *const pHsadc, uint32_t u32CCal) +{ + pHsadc->CCAL = u32CCal; +} + +/** + * @brief Get the conversion result FIFO data of the HSADC instance + * + * @note only reslut data of HSADC single mode and continuous mode will be stored + * in FIFO register. + * + * @param pHsadc the base address of the HSADC instance + * @return uint32_t the HSADC conversion result + */ +LOCAL_INLINE uint32_t HSADC_HWA_GetFIFOData(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = pHsadc->FIFO_DATA; + u32TmpVal = (u32TmpVal & HSADC_FIFO_DATA_FIFO_DATA_MASK) >> HSADC_FIFO_DATA_FIFO_DATA_SHIFT; + return (uint32_t)u32TmpVal; +} + +/** + * @brief Get the sample time index of the HSADC channel + * + * @param pHsadc the base address of the HSADC instance + * @param u8ChnIdx the index of the channel + * @return uint8_t the sample time index of the HSADC channel + */ +LOCAL_INLINE uint8_t HSADC_HWA_GetChannelSampleTimeIndex(const HSADC_Type *const pHsadc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = (pHsadc->SC[u8ChnIdx] & HSADC_SC_SMPSEL_MASK) >> HSADC_SC_SMPSEL_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the sample time index of the HSADC channel + * + * @param pHsadc the base address of the HSADC instance + * @param u8ChnIdx the index of the channel + * @param u8SmpSel the sample time index of the HSADC channel + */ +LOCAL_INLINE void HSADC_HWA_SetChannelSampleTimeIndex(HSADC_Type *const pHsadc, const uint8_t u8ChnIdx, uint8_t u8SmpSel) +{ + pHsadc->SC[u8ChnIdx] = (pHsadc->SC[u8ChnIdx] & ~HSADC_SC_SMPSEL_MASK) | HSADC_SC_SMPSEL(u8SmpSel); +} + +/** + * @brief Get the channel conversion complete status of the HSADC instance + * + * @note this function is used only in HSADC discontinuous mode to get the channel complete + * status + * + * @param pHsadc the base address of the HSADC instance + * @param u8ChnIdx the index of the channel + * @return true the HSADC conversion on the selected channel is completed + * @return false the HSADC conversion on the selected channel is not completed + */ +LOCAL_INLINE bool HSADC_HWA_GetChannelCoCoFlag(const HSADC_Type *const pHsadc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pHsadc->SC[u8ChnIdx]; + u32TmpVal = (u32TmpVal & HSADC_SC_COCO_MASK) >> HSADC_SC_COCO_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the channel conversion complete status of the HSADC instance + * + * @note this function is used only in HSADC sequence group mode to clear the channel complete + * flag + * + * @param pHsadc the base address of the HSADC instance + * @param u8ChnIdx the index of the channel + * @return true the HSADC conversion on the selected channel is completed + * @return false the HSADC conversion on the selected channel is not completed + */ +LOCAL_INLINE void HSADC_HWA_ClearChannelCoCoFlag(HSADC_Type *const pHsadc, uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pHsadc->SC[u8ChnIdx]; + u32TmpVal = u32TmpVal | HSADC_SC_COCO_MASK; + pHsadc->SC[u8ChnIdx] = u32TmpVal; +} + +/** + * @brief Check whether interrupt is enabled on the selected HSADC channel + * + * @note this function is used only in HSADC sequence group mode to get the channel interrupt + * settings + * + * @param pHsadc the base address of the HSADC instance + * @param u8ChnIdx the index of the channel + * @return true interrupt is enabled on the selected channel + * @return false interrupt is disabled on the selected channel + */ +LOCAL_INLINE bool HSADC_HWA_GetChannelCoCoIntEnable(const HSADC_Type *const pHsadc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pHsadc->SC[u8ChnIdx]; + u32TmpVal = (u32TmpVal & HSADC_SC_AIEN_MASK) >> HSADC_SC_AIEN_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set to enable or disable interrupt on the selected HSADC channel + * + * @note this function is used only in HSADC sequence group mode to get the channel interrupt + * settings + * + * @param pHsadc the base address of the HSADC instance + * @param u8ChnIdx the index of the channel + * @param bEnable whether to enable interrupt on the selected HSADC channel + */ +LOCAL_INLINE void HSADC_HWA_SetChannelCoCoIntEnable(HSADC_Type *const pHsadc, const uint8_t u8ChnIdx, bool bEnable) +{ + pHsadc->SC[u8ChnIdx] = (pHsadc->SC[u8ChnIdx] & ~HSADC_SC_AIEN_MASK) | HSADC_SC_AIEN(bEnable); +} + +/** + * @brief Get the input channel of the selected HSADC channel + * + * @param pHsadc the base address of the HSADC instance + * @param u8ChnIdx the index of the channel + * @return uint8_t the hardware input channel + */ +LOCAL_INLINE uint8_t HSADC_HWA_GetChannelInput(const HSADC_Type *const pHsadc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = (pHsadc->SC[u8ChnIdx] & HSADC_SC_CHS_MASK) >> HSADC_SC_CHS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the input channel to the selected HSADC channel + * + * @param pHsadc the base address of the HSADC instance + * @param u8ChnIdx the index of the channel + * @param u8InputChann the hardware input channel + */ +LOCAL_INLINE void HSADC_HWA_SetChannelInput(HSADC_Type *const pHsadc, const uint8_t u8ChnIdx, uint8_t u8InputChann) +{ + pHsadc->SC[u8ChnIdx] = (pHsadc->SC[u8ChnIdx] & ~HSADC_SC_CHS_MASK) | HSADC_SC_CHS(u8InputChann); +} + +LOCAL_INLINE void HSADC_HWA_SetSCCfg(HSADC_Type *const pHsadc, const uint8_t u8ChnIdx, uint32_t val) +{ + pHsadc->SC[u8ChnIdx] = val; +} + +/** + * @brief Get the conversion result data of the HSADC instance + * + * @note only result data of HSADC discontinuous mode will be stored in RESULTn register. + * + * @param pHsadc the base address of the HSADC instance + * @param u8ChnIdx the index of the HSADC channel + * @return uint32_t the HSADC conversion result + */ +LOCAL_INLINE uint32_t HSADC_HWA_GetChannelData(const HSADC_Type *const pHsadc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pHsadc->RESULT[u8ChnIdx]; + u32TmpVal = (u32TmpVal & HSADC_RESULT_RESULT_MASK) >> HSADC_RESULT_RESULT_SHIFT; + + return (uint32_t)u32TmpVal; +} + +LOCAL_INLINE uint16_t HSADC_HWA_GetResultCal(HSADC_Type *const pHsadc) +{ + return (uint16_t)((pHsadc->RESULT_CAL & HSADC_RESULT_CAL_DATA_MASK) >> HSADC_RESULT_CAL_DATA_SHIFT); +} + +/** + * @brief Get the fast compare enable + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @return bool whether the HSADC fast compare enable + */ +LOCAL_INLINE bool HSADC_HWA_GetFCEnable(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->FCMP_CTRL & HSADC_FCMP_CTRL_FC_EN_MASK) >> HSADC_FCMP_CTRL_FC_EN_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the fast compare reference of the HSADC instance + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @param enable whether the HSADC fast compare enable + * @return none + */ +LOCAL_INLINE void HSADC_HWA_SetFCEnable(HSADC_Type *const pHsadc, bool enable) +{ + pHsadc->FCMP_CTRL = (pHsadc->FCMP_CTRL & ~HSADC_FCMP_CTRL_FC_EN_MASK) | HSADC_FCMP_CTRL_FC_EN(enable); +} + +/** + * @brief Set the fast compare control register + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @param value control register value + * @return none + */ +LOCAL_INLINE void HSADC_HWA_SetFCCtrl(HSADC_Type *const pHsadc, uint32_t value) +{ + pHsadc->FCMP_CTRL = value; +} + +/** + * @brief Get the fast compare reference of the HSADC instance + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @return int16_t the HSADC fast compare reference + */ +LOCAL_INLINE int16_t HSADC_HWA_GetFCRef(const HSADC_Type *const pHsadc) +{ + return (pHsadc->FCREF & HSADC_FCREF_FCREF_MASK) >> HSADC_FCREF_FCREF_SHIFT; +} + +/** + * @brief Set the fast compare reference of the HSADC instance + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @param ref the index of the HSADC channel + * @return none + */ +LOCAL_INLINE void HSADC_HWA_SetFCRef(HSADC_Type *const pHsadc, uint16_t ref) +{ + pHsadc->FCREF = (pHsadc->FCREF & ~HSADC_FCREF_FCREF_MASK) | HSADC_FCREF_FCREF(ref); +} + +/** + * @brief Get the fast compare ramp reference A of the HSADC instance + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @return int16_t the HSADC fast compare ramp reference A + */ +LOCAL_INLINE int16_t HSADC_HWA_GetFCRampRefA(const HSADC_Type *const pHsadc) +{ + return (pHsadc->FCRAMP0 & HSADC_FCRAMP0_FCREF_A_MASK) >> HSADC_FCRAMP0_FCREF_A_SHIFT; +} + +/** + * @brief Set the fast compare ramp reference A of the HSADC instance + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @param ref the HSADC fast compare ramp reference A + * @return none + */ +LOCAL_INLINE void HSADC_HWA_SetFCRampRefA(HSADC_Type *const pHsadc, uint16_t ref) +{ + pHsadc->FCRAMP0 = (pHsadc->FCRAMP0 & ~HSADC_FCRAMP0_FCREF_A_MASK) | HSADC_FCRAMP0_FCREF_A(ref); +} + +/** + * @brief Get the fast compare ramp step of the HSADC instance + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @return uint8_t the HSADC fast compare ramp step + */ +LOCAL_INLINE uint8_t HSADC_HWA_GetFCRampStep(const HSADC_Type *const pHsadc) +{ + return (pHsadc->FCRAMP0 & HSADC_FCRAMP0_RPSTEP_MASK) >> HSADC_FCRAMP0_RPSTEP_SHIFT; +} + +/** + * @brief Set the fast compare ramp step + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @param step the HSADC fast compare ramp step + * @return none + */ +LOCAL_INLINE void HSADC_HWA_SetFCRampStep(HSADC_Type *const pHsadc, uint16_t step) +{ + pHsadc->FCRAMP0 = (pHsadc->FCRAMP0 & ~HSADC_FCRAMP0_RPSTEP_MASK) | HSADC_FCRAMP0_RPSTEP(step); +} + +/** + * @brief Set the fast compare ramp0 register + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @param value the HSADC fast compare ramp0 register value + * @return none + */ +LOCAL_INLINE void HSADC_HWA_SetFCRamp0(HSADC_Type *const pHsadc, uint32_t value) +{ + pHsadc->FCRAMP0 = value; +} + +/** + * @brief Get the fast compare ramp reference B of the HSADC instance + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @return int16_t the HSADC fast compare ramp reference B + */ +LOCAL_INLINE int16_t HSADC_HWA_GetFCRampRefB(const HSADC_Type *const pHsadc) +{ + return (pHsadc->FCRAMP1 & HSADC_FCRAMP1_FCREF_B_MASK) >> HSADC_FCRAMP1_FCREF_B_SHIFT; +} + +/** + * @brief Set the fast compare ramp reference B of the HSADC instance + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @param ref the HSADC fast compare ramp reference B + * @return none + */ +LOCAL_INLINE void HSADC_HWA_SetFCRampRefB(HSADC_Type *const pHsadc, uint16_t ref) +{ + pHsadc->FCRAMP1 = (pHsadc->FCRAMP1 & ~HSADC_FCRAMP1_FCREF_B_MASK) | HSADC_FCRAMP1_FCREF_B(ref); +} + +/** + * @brief Get the fast compare ramp dir + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @return HSADC_FCmpRampDir the HSADC fast compare ramp dir + */ +LOCAL_INLINE HSADC_FastCmpRampDir HSADC_HWA_GetFCRampDir(const HSADC_Type *const pHsadc) +{ + uint32_t u32TmpVal = (pHsadc->FCRAMP1 & HSADC_FCRAMP1_RPDIR_MASK) >> HSADC_FCRAMP1_RPDIR_SHIFT; + return u32TmpVal ? HSADC_FAST_CMP_RAMPDIR_DOWN : HSADC_FAST_CMP_RAMPDIR_UP; +} + +/** + * @brief Set the fast compare ramp dir + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @param dir the HSADC fast compare ramp dir + * @return none + */ +LOCAL_INLINE void HSADC_HWA_SetFCRampDir(HSADC_Type *const pHsadc, HSADC_FastCmpRampDir dir) +{ + pHsadc->FCRAMP1 = (pHsadc->FCRAMP1 & ~HSADC_FCRAMP1_RPDIR_MASK) | HSADC_FCRAMP1_RPDIR(dir); +} + +/** + * @brief Set the fast compare ramp1 register + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @param value the HSADC fast compare ramp1 register value + * @return none + */ +LOCAL_INLINE void HSADC_HWA_SetFCRamp1(HSADC_Type *const pHsadc, uint32_t value) +{ + pHsadc->FCRAMP1 = value; +} + +/** + * @brief Get the fast compare reference upper delta + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @return uint16_t the HSADC fast compare ref upper delta + */ +LOCAL_INLINE uint16_t HSADC_HWA_GetFCRefDeltaP(const HSADC_Type *const pHsadc) +{ + return (pHsadc->FCHYST & HSADC_FCHYST_DELTAP_MASK) >> HSADC_FCHYST_DELTAP_SHIFT; +} + +/** + * @brief Set the fast compare reference upper delta + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @param delta the HSADC fast compare ref upper delta + * @return none + */ +LOCAL_INLINE void HSADC_HWA_SetFCRefDeltaP(HSADC_Type *const pHsadc, uint16_t delta) +{ + pHsadc->FCHYST = (pHsadc->FCHYST & ~HSADC_FCHYST_DELTAP_MASK) | HSADC_FCHYST_DELTAP(delta); +} + +/** + * @brief Get the fast compare reference lower delta + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @return uint16_t the HSADC fast compare ref lower delta + */ +LOCAL_INLINE uint16_t HSADC_HWA_GetFCRefDeltaN(const HSADC_Type *const pHsadc) +{ + return (pHsadc->FCHYST & HSADC_FCHYST_DELTAN_MASK) >> HSADC_FCHYST_DELTAN_SHIFT; +} + +/** + * @brief Set the fast compare reference lower delta + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @param delta the HSADC fast compare ref lower delta + * @return none + */ +LOCAL_INLINE void HSADC_HWA_SetFCRefDeltaN(HSADC_Type *const pHsadc, uint16_t delta) +{ + pHsadc->FCHYST = (pHsadc->FCHYST & ~HSADC_FCHYST_DELTAN_MASK) | HSADC_FCHYST_DELTAN(delta); +} + +/** + * @brief Set the fast compare reference hysteresis + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @param u32Hyst the HSADC fast compare reference hysteresis + * @return none + */ +LOCAL_INLINE void HSADC_HWA_SetFCHysteresis(HSADC_Type *const pHsadc, uint32_t u32Hyst) +{ + pHsadc->FCHYST = u32Hyst; +} + +/** + * @brief Get the fast compare result + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @return bool fast compare result + */ +LOCAL_INLINE bool HSADC_HWA_GetFCResult(HSADC_Type *const pHsadc) +{ + return (bool)((pHsadc->FCBFR & HSADC_FCBFR_FCR_MASK) >> HSADC_FCBFR_FCR_SHIFT); +} + +/** + * @brief Get the fast compare boundary flag + * + * @note + * + * @param pHsadc the base address of the HSADC instance + * @return bool fast compare boundary flag + */ +LOCAL_INLINE bool HSADC_HWA_GetFCBoundaryFlag(HSADC_Type *const pHsadc) +{ + return (bool)((pHsadc->FCBFR & HSADC_FCBFR_BFL_MASK) >> HSADC_FCBFR_BFL_SHIFT); +} + +/** @}*/ + +#endif /* #if HSADC_INSTANCE_COUNT > 0U */ + +#endif /* _HWA_HSADC_H_ */ diff --git a/Inc/HwA_intm.h b/Inc/HwA_intm.h new file mode 100644 index 0000000..2ee855c --- /dev/null +++ b/Inc/HwA_intm.h @@ -0,0 +1,189 @@ +/** + * @file HwA_intm.h + * @author flagchip + * @brief Interrupt monitor + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_INTM_H_ +#define _HWA_INTM_H_ + +#include "device_header.h" + +#if INTM_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_fciic HwA_fciic + * @ingroup module_driver_fciic + * @{ + */ + +typedef struct +{ + __IO uint32_t IRQSELR; /**< INTM Interrupt Request Select Register*/ + __IO uint32_t LATR; /**< INTM Latency Register */ + __IO uint32_t TMR; /**< INTM Timer Register */ + __I uint32_t SR; /**< INTM Status Register */ +} INTM_MonitorType, *INTM_MonitorMemMapPtr; + +/** + * @brief Enable the INTM. + * @param pIntm INTM instance. INTM instance. + * @param bEnable Enable the ITNM. + */ +LOCAL_INLINE void INTM_HWA_Enable(INTM_Type *const pIntm, bool bEnable) +{ + if (bEnable) + { + pIntm->ER = INTM_ER_EN_MASK; + } + else + { + pIntm->ER = 0U; + } +} + +/** + * @brief Get the instance of interrupt monitor. + * @param pIntm INTM instance. + * @param u8IrqMonitorIndex Interrupt monitor index. + * @return Monitor Instance. + */ +LOCAL_INLINE INTM_MonitorType *INTM_HWA_GetIrqMonitor(INTM_Type *const pIntm, uint8_t u8IrqMonitorIndex) +{ + return (INTM_MonitorType *)((uint32_t) & (pIntm->IRQSELR0) + (uint32_t)u8IrqMonitorIndex * 0x10U); +} + +/** + * @brief Set the interrupt acknowledge. + * @param pIntm INTM instance. + * @param u16IrqNum Interrupt number to be monitored. + */ +LOCAL_INLINE void INTM_HWA_SetIACKR(INTM_Type *const pIntm, uint16_t u16IrqNum) +{ + pIntm->IACKR = u16IrqNum; +} + +/** + * @brief Set which interrupt to be monoterd. + * @param pIrqMon Interrupt monitor instance. + * @param u16IrqNum Interrupt number to be monitored. + */ +LOCAL_INLINE void INTM_HWA_SetIRQReqNum(INTM_MonitorType *const pIrqMon, uint16_t u16IrqNum) +{ + pIrqMon->IRQSELR = u16IrqNum; +} + +/** + * @brief Enable reset when interrupt delays overtime. + * @param pIrqMon Interrupt monitor instance. + * @param bEnable Enable reset. + */ +LOCAL_INLINE void INTM_HWA_EnableReset(INTM_MonitorType *const pIrqMon, bool bEnable) +{ + pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_RSTE_MASK) | INTM_IRQSELR_RSTE(bEnable); +} + +/** + * @brief Enable interrupt when monitored interrupt delays overtime. + * @param pIrqMon Interrupt monitor instance. + * @param bEnable Enabel the interrupt. + */ +LOCAL_INLINE void INTM_HWA_EnableInterrupt(INTM_MonitorType *const pIrqMon, bool bEnable) +{ + pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_INTE_MASK) | INTM_IRQSELR_INTE(bEnable); +} + +/** + * @brief Enable inactive mode. + * @param pIrqMon Interrupt monitor instance. + * @param bEnable Enable inactive mode. + */ +LOCAL_INLINE void INTM_HWA_EnableInactiveMode(INTM_MonitorType *const pIrqMon, bool bEnable) +{ + pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_IACTE_MASK) | INTM_IRQSELR_IACTE(bEnable); +} + +/** + * @brief Start the inactive mode. + * @param pIrqMon Interrupt monitor instance. + */ +LOCAL_INLINE void INTM_HWA_StartInactiveMode(INTM_MonitorType *const pIrqMon) +{ + pIrqMon->IRQSELR |= INTM_IRQSELR_IACTST_MASK; + __asm volatile( + "dmb \n" + "ldr r8, [%[IRQSELR]] \n"/* Must Read IRQSELR after set. */ + : : [IRQSELR] "r"(&pIrqMon->IRQSELR) : "r8", "memory" + ); +} + +/** + * @brief Stop the inactive mode. + * @param pIrqMon Interrupt monitor instance. + */ +LOCAL_INLINE void INTM_HWA_StopInactiveMode(INTM_MonitorType *const pIrqMon) +{ + pIrqMon->IRQSELR &= ~INTM_IRQSELR_IACTST_MASK; +} + +/** + * @brief Set the timeout value of interrupt. + * @param pIrqMon Interrupt monitor instance. + * @param u32Latency the timeout value of interrupt monitor. + */ +LOCAL_INLINE void INTM_HWA_SetLatency(INTM_MonitorType *const pIrqMon, uint32_t u32Latency) +{ + pIrqMon->LATR = u32Latency; +} + +/** + * @brief Get the value of timer. + * @param pIrqMon Interrupt monitor instance. + * @return Timer value + */ +LOCAL_INLINE uint32_t INTM_HWA_GetTimerCounter(INTM_MonitorType *const pIrqMon) +{ + return pIrqMon->TMR; +} + +/** + * @brief Set the value of timer. + * @param pIrqMon Interrupt monitor instance. + * @param u32Value The value to be set. + */ +LOCAL_INLINE void INTM_HWA_SetTimerCounter(INTM_MonitorType *const pIrqMon, uint32_t u32Value) +{ + pIrqMon->TMR = u32Value; +} + +/** + * @brief Read interrupt status. + * @param pIrqMon Interrupt monitor instance. + * @return Interrupt status. + */ +LOCAL_INLINE bool INTM_HWA_ReadStatus(INTM_MonitorType *const pIrqMon) +{ + return (pIrqMon->SR & INTM_SR_MASK) == INTM_SR_MASK ? true : false; +} + +/** @}*/ + +#endif /* #if INTM_INSTANCE_COUNT > 0U */ + +#endif /*#ifndef _HWA_INTM_H_*/ diff --git a/Inc/HwA_ism.h b/Inc/HwA_ism.h new file mode 100644 index 0000000..fe6454e --- /dev/null +++ b/Inc/HwA_ism.h @@ -0,0 +1,654 @@ +/** + * @file HwA_ism.h + * @author flagchip + * @brief ISM hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_ISM_H_ +#define _HWA_ISM_H_ + +#include "device_header.h" + +#if ISM_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_ism HwA_ism + * @ingroup module_driver_ism + * @{ + */ + +/********* macros ************/ + +/********* Local typedef ************/ + +typedef struct +{ + __IO uint32_t FPC_STATUS; + __IO uint32_t FPC_CTRL; + __IO uint32_t FPC_CONFIG; + __IO uint32_t FPC_TIMER; +} FPC_Type, *FPC_MemMapPtr; + +typedef struct +{ + __IO uint32_t LAM_STATUS; + __IO uint32_t LAM_CTRL; + __IO uint32_t LAM_CONFIG; + __IO uint32_t LAM_CONTER; +} LAM_Type, *LAM_MemMapPtr; + +typedef enum +{ + ISM_FPC_DETECT_NO_FILTER = 0U, /**< No filter mode. Copy input to SOUT directly, which is LAM input.*/ + ISM_FPC_DETECT_IMMI_FILTER = 1U, /**< Immediate filter mode.*/ + ISM_FPC_DETECT_DELAY_MODE = 2U, /**< Delay mode.*/ + ISM_FPC_DETECT_PRESCALER_MODE = 3U /**< Prescaler mode.*/ +} ISM_FPC_EdgeDetectModeType; + +typedef enum +{ + ISM_FPC_DELAY_FIXED0 = 0U, /**< Fixed delay mode.*/ + ISM_FPC_DELAY_FIXED1 = 1U, /**< Fixed delay mode.*/ + ISM_FPC_DELAY_SMART_DELAY0 = 2U, /**< Smart delay mode. The counter is decremented when a glitch happens.*/ + ISM_FPC_DELAY_SMART_DELAY1 = 3U /**< Smart delay mode. The counter is reset when a glitch happens.*/ +} ISM_FPC_EdgeDelayModeType; + + +typedef enum +{ + ISM_LAM_EVT_WIN_NON_INVERT = 0U, /**< Event window non-inverted.*/ + ISM_LAM_EVT_WIN_INVERT = 1U /**< Event window inverted.*/ +} ISM_LAM_InvertEventWindowType; + +typedef enum +{ + ISM_LAM_NTR_CLEAR_NTR_GATE = 0U, /**< Neither edge used to clear the event window counter. Neither edge used to gate event generation.*/ + ISM_LAM_POS_CLEAR_NTR_GATE = 1U, /**< Positive edge used to clear the event window counter. Neither edge used to gate event generation.*/ + ISM_LAM_NEG_CLEAR_NTR_GATE = 2U, /**< Negative edge used to clear the event window counter. Neither edge used to gate event generation.*/ + ISM_LAM_ETR_CLEAR_NTR_GATE = 3U, /**< Either edge used to clear the event window counter. Neither edge used to gate event generation.*/ + ISM_LAM_NTR_CLEAR_POS_GATE = 4U, /**< Neither edge used to clear the event window counter. Positive edge used to gate event generation.*/ + ISM_LAM_POS_CLEAR_POS_GATE = 5U, /**< Positive edge used to clear the event window counter. Positive edge used to gate event generation.*/ + ISM_LAM_NEG_CLEAR_POS_GATE = 6U, /**< Negative edge used to clear the event window counter. Positive edge used to gate event generation.*/ + ISM_LAM_ETR_CLEAR_POS_GATE = 7U, /**< Either edge used to clear the event window counter. Positive edge used to gate event generation.*/ + ISM_LAM_NTR_CLEAR_NEG_GATE = 8U, /**< Neither edge used to clear the event window counter. Negative edge used to gate event generation.*/ + ISM_LAM_POS_CLEAR_NEG_GATE = 9U, /**< Positive edge used to clear the event window counter. Negative edge used to gate event generation.*/ + ISM_LAM_NEG_CLEAR_NEG_GATE = 10U, /**< Negative edge used to clear the event window counter. Negative edge used to gate event generation.*/ + ISM_LAM_ETR_CLEAR_NEG_GATE = 11U, /**< Either edge used to clear the event window counter. Negative edge used to gate event generation.*/ + ISM_LAM_NTR_CLEAR_ETR_GATE = 12U, /**< Neither edge used to clear the event window counter. Either edge used to gate event generation.*/ + ISM_LAM_POS_CLEAR_ETR_GATE = 13U, /**< Positive edge used to clear the event window counter. Either edge used to gate event generation.*/ + ISM_LAM_NEG_CLEAR_ETR_GATE = 14U, /**< Negative edge used to clear the event window counter. Either edge used to gate event generation.*/ + ISM_LAM_ETR_CLEAR_ETR_GATE = 15U /**< Either edge used to clear the event window counter. Either edge used to gate event generation.*/ +} ISM_LAM_EventWindowEdgeType; + +typedef enum +{ + ISM_LAM_EVT_WIN_SEL_REF = 0U, /**< Event window generation is determined from the reference signal.*/ + ISM_LAM_EVT_WIN_SEL_MON = 1U /**< Event window generation is determined from the monitor signal.*/ +} ISM_LAM_EventWindowSelectType; + +typedef enum +{ + ISM_LAM_RUN_FREE = 0U, /**< Event window generation is free-running.*/ + ISM_LAM_RUN_GATED = 1U /**< Event window generation is gated with the monitor or reference signal.*/ +} ISM_LAM_RunModeSelectType; + + +typedef enum +{ + ISM_LAM_SRC_FPC_MON = 0U, /**< Monitor signal is sourced directly from FPC monitor channel.*/ + ISM_LAM_SRC_EXORD_FPC_REF = 1U /**< Monitor signal is EXOR'd with FPC reference channel.*/ +} ISM_LAM_MonitorSourceType; + +typedef enum +{ + ISM_LAM_FPC_MON_NON_INVERT = 0U, /**< Do not invert the monitor signal from FPC.*/ + ISM_LAM_FPC_MON_INVERT = 1U /**< Invert the monitor signal from FPC.*/ +} ISM_LAM_InvertMonitorType; + +typedef enum +{ + ISM_LAM_FPC_REF_NON_INVERT = 0U, /**< Do not invert the reference signal from FPC.*/ + ISM_LAM_FPC_REF_INVERT = 1U /**< Invert the reference signal from FPC.*/ +} ISM_LAM_InvertReferenceType; + +/********* Local inline function ************/ + +/********* ISM Register interface ************/ + +/** + * @brief Get ISM ECM count + * + * @param pIsm ISM Instance + * @return ECM count + */ +LOCAL_INLINE uint8_t ISM_HWA_PARAM_ECMC(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->PARAM & ISM_PARAM_ECMC_MASK) >> ISM_PARAM_ECMC_SHIFT); +} + +/** + * @brief Get ISM FPC count + * + * @param pIsm ISM Instance + * @return FPC count + */ +LOCAL_INLINE uint8_t ISM_HWA_PARAM_FPC(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->PARAM & ISM_PARAM_FPC_MASK) >> ISM_PARAM_FPC_SHIFT); +} + +/** + * @brief Get ISM LAM count + * + * @param pIsm ISM Instance + * @return LAM count + */ +LOCAL_INLINE uint8_t ISM_HWA_PARAM_LAM(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->PARAM & ISM_PARAM_LAM_MASK) >> ISM_PARAM_LAM_SHIFT); +} + +/** + * @brief Enable ISM + * + * @param pIsm ISM Instance + * @param bEnable EN value + */ +LOCAL_INLINE void ISM_HWA_Enable(ISM_Type *const pIsm, bool bEnable) +{ + pIsm->CTRL = (pIsm->CTRL & ~ISM_CTRL_EN_MASK) | ISM_CTRL_EN(bEnable); +} + +/** + * @brief Enable ISM Interrupt + * + * @param pIsm ISM Instance + * @param bEnable IEN value + */ +LOCAL_INLINE void ISM_HWA_InterruptEnable(ISM_Type *const pIsm, bool bEnable) +{ + pIsm->CTRL = (pIsm->CTRL & ~ISM_CTRL_IEN_MASK) | ISM_CTRL_IEN(bEnable); +} + +/** + * @brief Get ECS of ISM_E_STATUS register + * + * @param pIsm ISM Instance + * @return ECS value + */ +LOCAL_INLINE uint8_t ISM_HWA_GetEcs(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->E_STATUS & ISM_E_STATUS_ECS_MASK) >> ISM_E_STATUS_ECS_SHIFT); +} + +/** + * @brief Clear ECS of ISM_E_STATUS register + * + * @param pIsm ISM Instance + * @param u32Channels ECM channels + */ +LOCAL_INLINE void ISM_HWA_ClearEcs(ISM_Type *const pIsm, uint32_t u32Channels) +{ + pIsm->E_STATUS = (u32Channels << ISM_E_STATUS_ECS_SHIFT) & ISM_E_STATUS_ECS_MASK; +} + +/** + * @brief Get ES of ISM_E_STATUS register + * + * @param pIsm ISM Instance + * @return ES value + */ +LOCAL_INLINE uint16_t ISM_HWA_GetEs(ISM_Type *const pIsm) +{ + return (uint16_t)((pIsm->E_STATUS & ISM_E_STATUS_ES_MASK) >> ISM_E_STATUS_ES_SHIFT); +} + +/** + * @brief Clear ES of ISM_E_STATUS register + * + * @param pIsm ISM Instance + * @param u32Channels ECM channels + */ +LOCAL_INLINE void ISM_HWA_ClearEs(ISM_Type *const pIsm, uint32_t u32Channels) +{ + pIsm->E_STATUS = (u32Channels << ISM_E_STATUS_ES_SHIFT) & ISM_E_STATUS_ES_MASK; +} + +/** + * @brief Enable ISM ECM channels system event + * + * @param pIsm ISM Instance + * @param u32Channels ECM Channels + * @param bEnable enable value + */ +LOCAL_INLINE void ISM_HWA_EnableEcmSystemEvent(ISM_Type *const pIsm, uint32_t u32Channels, bool bEnable) +{ + if (bEnable) + { + pIsm->E_CTRL = pIsm->E_CTRL | (u32Channels << ISM_E_CTRL_ECE_SHIFT); + } + else + { + pIsm->E_CTRL = pIsm->E_CTRL & ~(u32Channels << ISM_E_CTRL_ECE_SHIFT); + } +} + +/** + * @brief Get Enabled ISM ECM channels system event + * + * @param pIsm ISM Instance + * @return Enabled ECM event + */ +LOCAL_INLINE uint8_t ISM_HWA_GetEnabledEcmSystemEvent(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->E_CTRL & ISM_E_CTRL_ECE_MASK) >> ISM_E_CTRL_ECE_SHIFT); +} + +/** + * @brief Enable ISM LAM channels system event + * + * @param pIsm ISM Instance + * @param u32Channels LAM Channels + * @param bEnable enable value + */ +LOCAL_INLINE void ISM_HWA_EnableLamSystemEvent(ISM_Type *const pIsm, uint32_t u32Channels, bool bEnable) +{ + if (bEnable) + { + pIsm->E_CTRL = pIsm->E_CTRL | (u32Channels << ISM_E_CTRL_EE_SHIFT); + } + else + { + pIsm->E_CTRL = pIsm->E_CTRL & ~(u32Channels << ISM_E_CTRL_EE_SHIFT); + } +} + +/** + * @brief Get Enabled ISM LAM channels system event + * + * @param pIsm ISM Instance + * @return Enabled LAM event + */ +LOCAL_INLINE uint16_t ISM_HWA_GetEnabledLamSystemEvent(ISM_Type *const pIsm) +{ + return (uint16_t)((pIsm->E_CTRL & ISM_E_CTRL_EE_MASK) >> ISM_E_CTRL_EE_SHIFT); +} + +/** + * @brief Set the EC_CTRL register + * + * @param pIsm ISM Instance + * @param u32Value register Value + */ +LOCAL_INLINE void ISM_HWA_SetEcCtrl(ISM_Type *const pIsm, uint32_t u32Value) +{ + pIsm->EC_CTRL = u32Value; +} + +/** + * @brief Set THRL and LAM channel of ECM0 + * + * @param pIsm ISM Instance + * @param u32Value THRL value + * @param u32LamChannel Lam channel + */ +LOCAL_INLINE void ISM_HWA_SetEcm0EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel) +{ + uint32_t u32TempValue = pIsm->EC_CTRL; + + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_0_MASK) | ISM_EC_CTRL_SEL_0(u32LamChannel); + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_0_MASK) | ISM_EC_CTRL_THRL_0(u32Value); + pIsm->EC_CTRL = u32TempValue; +} + +/** + * @brief Set THRL and LAM channel of ECM1 + * + * @param pIsm ISM Instance + * @param u32Value THRL value + * @param u32LamChannel Lam channel + */ +LOCAL_INLINE void ISM_HWA_SetEcm1EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel) +{ + uint32_t u32TempValue = pIsm->EC_CTRL; + + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_1_MASK) | ISM_EC_CTRL_SEL_1(u32LamChannel); + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_1_MASK) | ISM_EC_CTRL_THRL_1(u32Value); + pIsm->EC_CTRL = u32TempValue; +} + +/** + * @brief Set THRL and LAM channel of ECM2 + * + * @param pIsm ISM Instance + * @param u32Value THRL value + * @param u32LamChannel Lam channel + */ +LOCAL_INLINE void ISM_HWA_SetEcm2EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel) +{ + uint32_t u32TempValue = pIsm->EC_CTRL; + + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_2_MASK) | ISM_EC_CTRL_SEL_2(u32LamChannel); + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_2_MASK) | ISM_EC_CTRL_THRL_2(u32Value); + pIsm->EC_CTRL = u32TempValue; +} + +/** + * @brief Set THRL and LAM channel of ECM3 + * + * @param pIsm ISM Instance + * @param u32Value THRL value + * @param u32LamChannel Lam channel + */ +LOCAL_INLINE void ISM_HWA_SetEcm3EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel) +{ + uint32_t u32TempValue = pIsm->EC_CTRL; + + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_3_MASK) | ISM_EC_CTRL_SEL_3(u32LamChannel); + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_3_MASK) | ISM_EC_CTRL_THRL_3(u32Value); + pIsm->EC_CTRL = u32TempValue; +} + +/** + * @brief Get the RGD value of FPC_STATUS + * + * @param pFpc FPC Instance + * @return RGD value + */ +LOCAL_INLINE bool ISM_HWA_GetFpcRgd(FPC_Type *const pFpc) +{ + return (pFpc->FPC_STATUS & ISM_FPC_STATUS_RGD_MASK) == ISM_FPC_STATUS_RGD_MASK ? true : false; +} + +/** + * @brief Clear the RGD value of FPC_STATUS + * + * @param pFpc FPC Instance + */ +LOCAL_INLINE void ISM_HWA_ClearFpcRgd(FPC_Type *const pFpc) +{ + pFpc->FPC_STATUS = ISM_FPC_STATUS_RGD_MASK; +} + +/** + * @brief Get the FGD value of FPC_STATUS + * + * @param pFpc FPC Instance + * @return FGD value + */ +LOCAL_INLINE bool ISM_HWA_GetFpcFgd(FPC_Type *const pFpc) +{ + return (pFpc->FPC_STATUS & ISM_FPC_STATUS_FGD_MASK) == ISM_FPC_STATUS_FGD_MASK ? true : false; +} + +/** + * @brief Clear the FGD value of FPC_STATUS + * + * @param pFpc FPC Instance + */ +LOCAL_INLINE void ISM_HWA_ClearFpcFgd(FPC_Type *const pFpc) +{ + pFpc->FPC_STATUS = ISM_FPC_STATUS_FGD_MASK; +} + +/** + * @brief Set the EN of FPC_CTRL + * + * @param pFpc FPC Instance + * @param bEnable EN value + */ +LOCAL_INLINE void ISM_HWA_SetFpcCtrlEn(FPC_Type *const pFpc, bool bEnable) +{ + pFpc->FPC_CTRL = (pFpc->FPC_CTRL & ~ISM_FPC_CTRL_EN_MASK) | ISM_FPC_CTRL_EN(bEnable); +} + +/** + * @brief Set the IEN of FPC_CTRL + * + * @param pFpc FPC Instance + * @param bEnable IEN value + */ +LOCAL_INLINE void ISM_HWA_SetFpcCtrlIen(FPC_Type *const pFpc, bool bEnable) +{ + pFpc->FPC_CTRL = (pFpc->FPC_CTRL & ~ISM_FPC_CTRL_IEN_MASK) | ISM_FPC_CTRL_IEN(bEnable); +} + +/** + * @brief Get the IEN of FPC_CTRL + * + * @param pFpc FPC Instance + * @return Interrupt enable bit + */ +LOCAL_INLINE bool ISM_HWA_GetFpcCtrlIen(FPC_Type *const pFpc) +{ + return (pFpc->FPC_CTRL & ISM_FPC_CTRL_IEN_MASK) == ISM_FPC_CTRL_IEN_MASK ? true : false; +} + +/** + * @brief Set the FEG of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param eMode FEG mode + */ +LOCAL_INLINE void ISM_HWA_SetFpcFallingDetectMode(FPC_Type *const pFpc, ISM_FPC_EdgeDetectModeType eMode) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_FEG_MASK) | ISM_FPC_CONFIG_FEG(eMode); +} + +/** + * @brief Set the FED of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param eMode FED mode + */ +LOCAL_INLINE void ISM_HWA_SetFpcFallingDelayMode(FPC_Type *const pFpc, ISM_FPC_EdgeDelayModeType eMode) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_FED_MASK) | ISM_FPC_CONFIG_FED(eMode); +} + +/** + * @brief Set the REG of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param eMode REG mode + */ +LOCAL_INLINE void ISM_HWA_SetFpcRisingDetectMode(FPC_Type *const pFpc, ISM_FPC_EdgeDetectModeType eMode) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_REG_MASK) | ISM_FPC_CONFIG_REG(eMode); +} + +/** + * @brief Set the RED of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param eMode RED mode + */ +LOCAL_INLINE void ISM_HWA_SetFpcRisingDelayMode(FPC_Type *const pFpc, ISM_FPC_EdgeDelayModeType eMode) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_RED_MASK) | ISM_FPC_CONFIG_RED(eMode); +} + +/** + * @brief Set the CMP of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param u32Value FPC threshold value that is compared with the 16-bit timer. + */ +LOCAL_INLINE void ISM_HWA_SetFpcConfigCmp(FPC_Type *const pFpc, uint32_t u32Value) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_CMP_MASK) | ISM_FPC_CONFIG_CMP(u32Value); +} + +/** + * @brief Set the value of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param u32Value Register value + */ +LOCAL_INLINE void ISM_HWA_SetFpcConfig(FPC_Type *const pFpc, uint32_t u32Value) +{ + pFpc->FPC_CONFIG = u32Value; +} + +/** + * @brief Get the TIM of FPC_TIMER + * + * @param pFpc FPC Instance + * @return TIM value + */ +LOCAL_INLINE uint16_t ISM_HWA_GetFpcTimer(FPC_Type *const pFpc) +{ + return (uint16_t)((pFpc->FPC_TIMER & ISM_FPC_TIMER_TIM_MASK) >> ISM_FPC_TIMER_TIM_SHIFT); +} + +/** + * @brief Clear the TIM of FPC_TIMER + * + * @param pFpc FPC Instance + */ +LOCAL_INLINE void ISM_HWA_ClearFpcTimer(FPC_Type *const pFpc) +{ + pFpc->FPC_TIMER = ISM_FPC_TIMER_TIM_MASK; +} + +/** + * @brief Get the COUNT of LAM_STATUS + * + * @param pLam LAM Instance + * @return COUNT value + */ +LOCAL_INLINE uint32_t ISM_HWA_GetLamStatusCounter(LAM_Type *const pLam) +{ + return (pLam->LAM_STATUS & ISM_LAM_STATUS_COUNT_MASK) >> ISM_LAM_STATUS_COUNT_SHIFT; +} + +/** + * @brief Clear the COUNT of LAM_STATUS + * + * @param pLam LAM Instance + */ +LOCAL_INLINE void ISM_HWA_ClearLamStatusCounter(LAM_Type *const pLam) +{ + pLam->LAM_STATUS = ISM_LAM_STATUS_COUNT_MASK; +} + +/** + * @brief Get the OVFL of LAM_STATUS + * + * @param pLam LAM Instance + * @return OVFL value + */ +LOCAL_INLINE bool ISM_HWA_GetLamStatusOvfl(LAM_Type *const pLam) +{ + return (pLam->LAM_STATUS & ISM_LAM_STATUS_OVFL_MASK) == ISM_LAM_STATUS_OVFL_MASK ? true : false; +} + +/** + * @brief Clear the OVFL of LAM_STATUS + * + * @param pLam LAM Instance + */ +LOCAL_INLINE void ISM_HWA_ClearLamStatusOvfl(LAM_Type *const pLam) +{ + pLam->LAM_STATUS = ISM_LAM_STATUS_OVFL_MASK; +} + +/** + * @brief Set the IEN of LAM_CTRL + * + * @param pLam LAM Instance + * @param bEnable IEN value, LAM Channel Overflow Interrupt Enable + */ +LOCAL_INLINE void ISM_HWA_SetLamCtrIen(LAM_Type *const pLam, bool bEnable) +{ + pLam->LAM_CTRL = (pLam->LAM_CTRL & ~ISM_LAM_CTRL_IEN_MASK) | ISM_LAM_CTRL_IEN(bEnable); +} + +/** + * @brief Get the IEN of LAM_CTRL + * + * @param pLam LAM Instance + * @return LAM Channel Overflow Interrupt Enable bit + */ +LOCAL_INLINE bool ISM_HWA_GetLamCtrIen(LAM_Type *const pLam) +{ + return (pLam->LAM_CTRL & ISM_LAM_CTRL_IEN_MASK) == ISM_LAM_CTRL_IEN_MASK ? true : false; +} + +/** + * @brief Set the EN of LAM_CTRL + * + * @param pLam LAM Instance + * @param bEnable EN value, LAM Channel Enable + */ +LOCAL_INLINE void ISM_HWA_SetLamCtrEn(LAM_Type *const pLam, bool bEnable) +{ + pLam->LAM_CTRL = (pLam->LAM_CTRL & ~ISM_LAM_CTRL_EN_MASK) | ISM_LAM_CTRL_EN(bEnable); +} + +/** + * @brief Set the value of LAM_CONFIG + * + * @param pLam LAM Instance + * @param u32Value Reigster value + */ +LOCAL_INLINE void ISM_HWA_SetLamConfig(LAM_Type *const pLam, uint32_t u32Value) +{ + pLam->LAM_CONFIG = u32Value; +} + +/** + * @brief Set the value of LAM_COUNTER + * + * @param pLam LAM Instance + * @param u32Value Reigster value + */ +LOCAL_INLINE void ISM_HWA_SetLamCounter(LAM_Type *const pLam, uint32_t u32Value) +{ + pLam->LAM_CONTER = u32Value; +} + +/** + * @brief Get the FPC instance. + * @param pIsm ISM Instance + * @param u8FpcIndex FPC index + * @return FPC Instance + */ +LOCAL_INLINE FPC_Type *ISM_HWA_GetFpc(ISM_Type *const pIsm, uint8_t u8FpcIndex) +{ + return (FPC_Type *)((uint32_t) & (pIsm->FPC_STATUS0) + (uint32_t)u8FpcIndex * 0x10U); +} + +/** + * @brief Get the LAM instance. + * @param pIsm ISM Instance + * @param u8FpcIndex LAM index + * @return LAM Instance + */ +LOCAL_INLINE LAM_Type *ISM_HWA_GetLam(ISM_Type *const pIsm, uint8_t u8LamIndex) +{ + return (LAM_Type *)((uint32_t) & (pIsm->LAM_STATUS0) + (uint32_t)u8LamIndex * 0x10U); +} + +/** @}*/ /* HwA_ism */ + +#endif /* #if ISM_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_ISM_H_ */ diff --git a/Inc/HwA_ldi.h b/Inc/HwA_ldi.h new file mode 100644 index 0000000..3f80bda --- /dev/null +++ b/Inc/HwA_ldi.h @@ -0,0 +1,490 @@ +/** + * @file HwA_ldi.h + * @author Flagchip + * @brief LDI hardware access layer + * @version 2.0.0 + * @date 2025-06-18 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2025-06-18 Flagchip0121 N/A Init version + ******************************************************************************** */ + +#ifndef _HWA_LDI_H_ +#define _HWA_LDI_H_ + +#include "device_header.h" + +#if LDI_INSTANCE_COUNT > 0U + + +#define LDI_SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define LDI_CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define LDI_READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define LDI_CLEAR_REG(REG) ((REG) = (0x0U)) + +#define LDI_WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define LDI_READ_REG(REG) ((REG)) + +#define LDI_MODIFY_REG(REG, CLEARMASK, SETMASK) LDI_WRITE_REG((REG), (((LDI_READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @defgroup HwA_ldi HwA_ldi + * @ingroup module_driver_ldi + * @{ + */ + +/********* Local inline function ************/ + +/** + * @brief Ldi clear all FIFO + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_ClearFIFO(LDI_Type *pLdi) +{ + LDI_SET_BIT(pLdi->CTRL, LDI_CTRL_CLR_FIFO3_MASK|LDI_CTRL_CLR_FIFO2_MASK|LDI_CTRL_CLR_FIFO1_MASK|LDI_CTRL_CLR_FIFO0_MASK); +} + +/** + * @brief Ldi clear all FIFO Status + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_ClearFIFOStatus(LDI_Type *pLdi) +{ + LDI_SET_BIT(pLdi->FSR, LDI_FSR_FF3_MASK|LDI_FSR_FU3_MASK|LDI_FSR_FF2_MASK|LDI_FSR_FU2_MASK| + LDI_FSR_FF1_MASK|LDI_FSR_FU1_MASK|LDI_FSR_FF0_MASK|LDI_FSR_FU0_MASK); +} + +/** + * @brief Ldi Set DDR Mode + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_SetDdrMode(LDI_Type *pLdi) +{ + LDI_CLEAR_BIT(pLdi->CTRL, LDI_CTRL_DDR_MASK); +} + +/** + * @brief Ldi Set SDR Mode + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_SetSdrMode(LDI_Type *pLdi) +{ + LDI_CLEAR_BIT(pLdi->CTRL, LDI_CTRL_DDR_MASK); +} + +/** + * @brief Ldi Set DDR delay + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_SetDdrDelay(LDI_Type *pLdi) +{ + LDI_SET_BIT(pLdi->CTRL, LDI_CTRL_DDRT_MASK); +} + +/** + * @brief Ldi Set SDR delay + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_SetSdrDelay(LDI_Type *pLdi) +{ + LDI_SET_BIT(pLdi->CTRL, LDI_CTRL_DCLK_INV_MASK); +} + +/** + * @brief Ldi config Ctrl register + * + * @param pLdi Ldi instance + * @param u32LdiCtrlReg Register value + */ +LOCAL_INLINE void LDI_HWA_CfgCtrl(LDI_Type *pLdi, uint32_t u32LdiCtrlReg) +{ + LDI_WRITE_REG(pLdi->CTRL, u32LdiCtrlReg); +} + +/** + * @brief Ldi config clock Ctrl register + * + * @param pLdi Ldi instance + * @param u32LdiClkCtrlReg Register value + */ +LOCAL_INLINE void LDI_HWA_CfgClkCtrl(LDI_Type *pLdi, uint32_t u32LdiClkCtrlReg) +{ + LDI_WRITE_REG(pLdi->CTRL, u32LdiClkCtrlReg); +} + +/** + * @brief Ldi enable function clock reference + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_EnFuncClkRef(LDI_Type *pLdi) +{ + LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_FCRE_MASK); +} + +/** + * @brief Ldi enable clock + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_EnableClk(LDI_Type *pLdi) +{ + LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_FCE_MASK); +} + +/** + * @brief Ldi set DDR/SDR Prediv + * + * @param pLdi Ldi instance + * @param u32DclkDivValue Dclk prediv + */ +LOCAL_INLINE void LDI_HWA_DdrSdrPrediv(LDI_Type *pLdi, uint32_t u32DclkDivValue) +{ + LDI_SET_BIT(pLdi->CLK_CTRL, u32DclkDivValue); +} + +/** + * @brief Ldi set gclk Prediv + * + * @param pLdi Ldi instance + * @param u32DclkDivValue Gclk prediv + */ +LOCAL_INLINE void LDI_HWA_GCLKPrediv(LDI_Type *pLdi, uint32_t u32GclkDivValue) +{ + LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_GCLKDIV(u32GclkDivValue)); +} + +/** + * @brief Ldi set gclk source + * + * @param pLdi Ldi instance + * @param u32GclkSrc Gclk source + */ +LOCAL_INLINE void LDI_HWA_GCLKSrc(LDI_Type *pLdi, uint32_t u32GclkSrc) +{ + LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_GCLKMUX(u32GclkSrc)); +} + +/** + * @brief Ldi set Spread Spectrum Mode + * + * @param pLdi Ldi instance + * @param u32SpreadMode Spread Spectrum Mode + */ +LOCAL_INLINE void LDI_HWA_SetSpreadMode(LDI_Type *pLdi, uint32_t u32SpreadMode) +{ + LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_SSM(u32SpreadMode)); +} + +/** + * @brief Ldi set Spread Spectrum Direction + * + * @param pLdi Ldi instance + * @param u32SpreadDirction Spread direction Mode + */ +LOCAL_INLINE void LDI_HWA_SetSpreadDirection(LDI_Type *pLdi, uint32_t u32SpreadDirction) +{ + LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_SSD(u32SpreadDirction)); +} + +/** + * @brief Ldi set clock config + * + * @param pLdi Ldi instance + * @param u32Clkcfg Spread direction Mode + */ +LOCAL_INLINE void LDI_HWA_SetClkcfg(LDI_Type *pLdi, uint32_t u32Clkcfg) +{ + LDI_SET_BIT(pLdi->CLK_CTRL, u32Clkcfg); +} + +/** + * @brief Ldi Enable Fut + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_EnableFut(LDI_Type *pLdi) +{ + LDI_SET_BIT(pLdi->CLK_CTRL, LDI_CLK_CTRL_FUT_MASK); +} + +/** + * @brief Ldi config px ctrl register + * + * @param pLdi Ldi instance + * @param u32LdiPxCtrlReg Px ctlr register value + */ +LOCAL_INLINE void LDI_HWA_CfgPxCtrl(LDI_Type *pLdi, uint32_t u32LdiPxCtrlReg) +{ + LDI_WRITE_REG(pLdi->PX_CTRL, u32LdiPxCtrlReg); +} + +/** + * @brief Ldi config px ctrl2 register + * + * @param pLdi Ldi instance + * @param u32LdiPxCtrl2Reg Px ctlr register value + */ +LOCAL_INLINE void LDI_HWA_CfgPxCtrl2(LDI_Type *pLdi, uint32_t u32LdiPxCtrl2Reg) +{ + LDI_WRITE_REG(pLdi->PX_CTRL2, u32LdiPxCtrl2Reg); +} + +/** + * @brief Ldi config px status register + * + * @param pLdi Ldi instance + * @param u32LdiPxStatusReg Px ctlr register value + */ +LOCAL_INLINE void LDI_HWA_CfgPxStatus(LDI_Type *pLdi, uint32_t u32LdiPxStatusReg) +{ + LDI_WRITE_REG(pLdi->PX_CTRL2, u32LdiPxStatusReg); +} + +/** + * @brief Ldi claer Tr size + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_ClearTrSize(LDI_Type *pLdi) +{ + LDI_SET_BIT(pLdi->PX_STATUS, LDI_PX_STATUS_TR_SIZE_MASK); +} + +/** + * @brief Ldi Enable channel + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_EnableChannel(LDI_Type *pLdi, uint32_t u32PinsMaskValue) +{ + LDI_SET_BIT(pLdi->PX_CTRL2, LDI_PX_CTRL2_PINS(u32PinsMaskValue)); +} + +/** + * @brief Ldi enable interrupt + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_EnableInterrupt(LDI_Type *pLdi) +{ + LDI_WRITE_REG(pLdi->IRQ_EN, LDI_IRQ_EN_PX_UPDT_MASK); +} + +/** + * @brief Ldi disable interrupt + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_DisableInterrupt(LDI_Type *pLdi) +{ + LDI_CLEAR_BIT(pLdi->IRQ_EN, LDI_IRQ_EN_PX_UPDT_MASK | LDI_IRQ_EN_PX_DISP_MASK); +} + +/** + * @brief Ldi clear interrupt flag + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_ClearInterruptFlag(LDI_Type *pLdi) +{ + LDI_WRITE_REG(pLdi->IRQ_ST, LDI_IRQ_EN_PX_UPDT_MASK | LDI_IRQ_EN_PX_DISP_MASK); +} + +/** + * @brief Ldi config pixel display row configuration register + * + * @param pLdi Ldi instance + * @param u32PxdRcfgReg Register value + */ +LOCAL_INLINE void LDI_HWA_CfgPxdRcfg(LDI_Type *pLdi, uint32_t u32PxdRcfgReg) +{ + LDI_WRITE_REG(pLdi->PXD_RCFG, u32PxdRcfgReg); +} + +/** + * @brief Ldi config pixel display gclk configuration register + * + * @param pLdi Ldi instance + * @param u32PxdGcfgReg Register value + */ +LOCAL_INLINE void LDI_HWA_CfgPxdGcfg(LDI_Type *pLdi, uint32_t u32PxdGcfgReg) +{ + LDI_WRITE_REG(pLdi->PXD_GCFG, u32PxdGcfgReg); +} + +/** + * @brief Ldi config pixel display SOE configuration register + * + * @param pLdi Ldi instance + * @param u32PxdScfgReg Register value + */ +LOCAL_INLINE void LDI_HWA_CfgPxdScfg(LDI_Type *pLdi, uint32_t u32PxdScfgReg) +{ + LDI_WRITE_REG(pLdi->PXD_SCFG, u32PxdScfgReg); +} + +/** + * @brief Ldi config pixel display DOE configuration register + * + * @param pLdi Ldi instance + * @param u32PxdDcfgReg Register value + */ +LOCAL_INLINE void LDI_HWA_CfgPxdDcfg(LDI_Type *pLdi, uint32_t u32PxdDcfgReg) +{ + LDI_WRITE_REG(pLdi->PXD_DCFG, u32PxdDcfgReg); +} + +/** + * @brief Ldi config pixel display SDI configuration register + * + * @param pLdi Ldi instance + * @param u32PxdIcfgReg Register value + */ +LOCAL_INLINE void LDI_HWA_CfgPxdIcfg(LDI_Type *pLdi, uint32_t u32PxdIcfgReg) +{ + LDI_WRITE_REG(pLdi->PXD_ICFG, u32PxdIcfgReg); +} + +/** + * @brief Ldi config Fcr0 register + * + * @param pLdi Ldi instance + * @param u32Fcr0Reg Register value + */ +LOCAL_INLINE void LDI_HWA_CfgFcr0(LDI_Type *pLdi, uint32_t u32Fcr0Reg) +{ + LDI_WRITE_REG(pLdi->FCR0, u32Fcr0Reg); +} + +/** + * @brief Ldi config Fcr1 register + * + * @param pLdi Ldi instance + * @param u32Fcr1Reg Register value + */ +LOCAL_INLINE void LDI_HWA_CfgFcr1(LDI_Type *pLdi, uint32_t u32Fcr1Reg) +{ + LDI_WRITE_REG(pLdi->FCR1, u32Fcr1Reg); +} + +/** + * @brief Ldi config Fcr2 register + * + * @param pLdi Ldi instance + * @param u32Fcr2Reg Register value + */ +LOCAL_INLINE void LDI_HWA_CfgFcr2(LDI_Type *pLdi, uint32_t u32Fcr2Reg) +{ + LDI_WRITE_REG(pLdi->FCR2, u32Fcr2Reg); +} + +/** + * @brief Ldi config Fcr3 register + * + * @param pLdi Ldi instance + * @param u32Fcr3Reg Register value + */ +LOCAL_INLINE void LDI_HWA_CfgFcr3(LDI_Type *pLdi, uint32_t u32Fcr3Reg) +{ + LDI_WRITE_REG(pLdi->FCR3, u32Fcr3Reg); +} + + +/** + * @brief Ldi set Tr size + * + * @param pLdi Ldi instance + * @param u32TrSize Tr size + */ +LOCAL_INLINE void LDI_HWA_SetTrSize(LDI_Type *pLdi, uint32_t u32TrSize) +{ + LDI_WRITE_REG(pLdi->PX_STATUS, LDI_PX_STATUS_TR_SIZE(u32TrSize)); +} + +/** + * @brief Ldi start update + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_UpdateStart(LDI_Type *pLdi) +{ + LDI_SET_BIT(pLdi->PX_STATUS, LDI_PX_STATUS_UP_START_MASK); +} + +/** + * @brief Ldi get update flag + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE uint32_t LDI_HWA_GetUpdateFlag(LDI_Type *pLdi) +{ + return(LDI_READ_BIT(pLdi->IRQ_ST, LDI_IRQ_ST_PX_UPDT_MASK) >> LDI_IRQ_ST_PX_UPDT_SHIFT); +} + +/** + * @brief Ldi get fifo 0 filling level + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE uint32_t LDI_HWA_GetCh0FifoFillLevel(LDI_Type *pLdi) +{ + return (LDI_READ_BIT(pLdi->FCR0, LDI_FCR0_FL_MASK ) >> LDI_FCR0_FL_SHIFT); +} + +/** + * @brief Ldi enable dma mode + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_EnableDma(LDI_Type *pLdi) +{ + LDI_SET_BIT(pLdi->CTRL, LDI_CTRL_EDME_MASK ); +} + +/** + * @brief Ldi disable dma mode + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_DisableDma(LDI_Type *pLdi) +{ + LDI_CLEAR_BIT(pLdi->CTRL, LDI_CTRL_EDME_MASK ); +} + +/** + * @brief Ldi config display + * + * @param pLdi Ldi instance + */ +LOCAL_INLINE void LDI_HWA_CfgDisplay(LDI_Type *pLdi) +{ + LDI_SET_BIT(pLdi->PX_STATUS, LDI_PX_STATUS_DISP_START_MASK); +} + +/** @}*/ + +#endif + +#endif /* #ifndef _HWA_LDI_H_ */ diff --git a/Inc/HwA_lu.h b/Inc/HwA_lu.h new file mode 100644 index 0000000..0697d01 --- /dev/null +++ b/Inc/HwA_lu.h @@ -0,0 +1,265 @@ +/** + * @file HwA_lu.h + * @author Flagchip + * @brief LU hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_LU_H_ +#define _HWA_LU_H_ + +#include "device_header.h" + +#if LU_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_lu HwA_lu + * @ingroup module_driver_lu + * @{ + */ + +/********* Local typedef ************/ +/** @brief LU LG instance */ +typedef enum +{ + LU_LG_0 = 0U, + LU_LG_1, + LU_LG_2, + LU_LG_3 +} LU_LgType; + +/** @brief LU AOI mode */ +typedef enum +{ + LU_NO_BYPASS = 0U, + LU_AOI0_BYPASS, + LU_AOI1_BYPASS, + LU_AOI0_AOI1_BYPASS +} LU_BypassModeType; + +/** @brief LU FF mode */ +typedef enum +{ + LU_BYPASS_MODE0 = 0U, + LU_RS_MODE, + LU_TFF_MODE, + LU_DFF_MODE, + LU_JKFF_MODE, + LU_LATCH_MODE +} LU_ConfigModeType; + +/** @brief LU Input(n) type */ +typedef enum +{ + LU_INPUT_N_A = 0U, + LU_INPUT_N_B, + LU_INPUT_N_C, + LU_INPUT_N_D +} LU_InputNType; +/********* Local inline function ************/ +/** + * @brief Configure LU LG(n) AOI0 configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue AOI0 register value + */ +LOCAL_INLINE void LU_HWA_ConfigAOI0(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].AOI_0 = u32RegValue; +} + +/** + * @brief Configure LU LG(n) AOI1 configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue AOI1 register value + */ +LOCAL_INLINE void LU_HWA_ConfigAOI1(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].AOI_1 = u32RegValue; +} + +/** + * @brief Configure LU LG(n) contrl configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue CTRL register value + */ +LOCAL_INLINE void LU_HWA_ConfigCtrl(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].CTRL = u32RegValue; +} + +/** + * @brief Configure LU LG(n) filter configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue FILT register value + */ +LOCAL_INLINE void LU_HWA_ConfigFilter(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].FILT = u32RegValue; +} + +/** + * @brief Set LG bypass control + * + * @param pLu LU instance + * @param eLg LG instance + * @param eMode LG bypass control mode + */ +LOCAL_INLINE void LU_HWA_SetLgBypassControl(LU_Type* pLu, LU_LgType eLg, LU_BypassModeType eMode) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].CTRL; + pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_BYPASS_MASK) | LU_CTRL_BYPASS(eMode)); +} + +/** + * @brief Set LG Flip-Flop mode + * + * @param pLu LU instance + * @param eLg LG instance + * @param eMode Flip-Flop mode + */ +LOCAL_INLINE void LU_HWA_SetLgFlipFlopMode(LU_Type* pLu, LU_LgType eLg, LU_ConfigModeType eMode) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].CTRL; + pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_MOD_MASK) | LU_CTRL_MOD(eMode)); +} + +/** + * @brief Set LG inputs synchronous control + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value LG input bit,0-3 bit indicate INPUT(n)A/INPUT(n)B/INPUT(n)C/INPUT(n)D + */ +LOCAL_INLINE void LU_HWA_SetLgInputsSyncCtrl(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].CTRL; + pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_SYNC_MASK) | LU_CTRL_SYNC(u32Value)); +} + +/** + * @brief Set LG output feedback override control + * + * @param pLu LU instance + * @param eLg LG instance + * @param eInput Feedback to LG input + */ +LOCAL_INLINE void LU_HWA_SetLgFeedbackOverrideCtrl(LU_Type* pLu, LU_LgType eLg, LU_InputNType eInput) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].CTRL; + pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_FB_OVRD_MASK) | LU_CTRL_FB_OVRD(eInput)); +} + +/** + * @brief Configure the output of flip-flop as "1" + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_ConfigFlipFlopTo1(LU_Type* pLu, LU_LgType eLg) +{ + pLu->LG[eLg].CTRL |= (uint32_t)LU_CTRL_FF_INIT_MASK; +} + +/** + * @brief Generate enable pulse + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_EnableControlFlipFlopInitOutput(LU_Type* pLu, LU_LgType eLg) +{ + pLu->LG[eLg].CTRL |= (uint32_t)LU_CTRL_INIT_EN_MASK; +} + +/** + * @brief Input filter sample count for AOI0 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample count value + */ +LOCAL_INLINE void LU_HWA_SetAOI0InputFilterSampleCount(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].FILT; + pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_CNT0_MASK) | LU_FILT_CNT0(u32Value)); +} + +/** + * @brief Input filter sample period for AOI0 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample period value + */ +LOCAL_INLINE void LU_HWA_SetAOI0InputFilterSamplePeriod(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].FILT; + pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_PRE0_MASK) | LU_FILT_PRE0(u32Value)); +} + +/** + * @brief Input filter sample count for AOI1 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample count value + */ +LOCAL_INLINE void LU_HWA_SetAOI1InputFilterSampleCount(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].FILT; + pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_CNT1_MASK) | LU_FILT_CNT1(u32Value)); +} + +/** + * @brief Input filter sample period for AOI1 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample period value + */ +LOCAL_INLINE void LU_HWA_SetAOI1InputFilterSamplePeriod(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].FILT; + pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_PRE1_MASK) | LU_FILT_PRE1(u32Value)); +} + +/** + * @brief Configure the output of flip-flop as "0" + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_ConfigFlipFlopTo0(LU_Type* pLu, LU_LgType eLg) +{ + pLu->LG[eLg].CTRL &= ~(uint32_t)LU_CTRL_FF_INIT_MASK; +} + +/** @}*/ + +#endif /* #if LU_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_LU_H_ */ diff --git a/Inc/HwA_mam.h b/Inc/HwA_mam.h new file mode 100644 index 0000000..ab2c218 --- /dev/null +++ b/Inc/HwA_mam.h @@ -0,0 +1,306 @@ +/** + * @file HwA_mam.h + * @author Flagchip + * @brief Hardware access layer for MAM + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip054 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip054 N/A Change version and release + * 2.5.0 2025-08-20 Flagchip0100 N/A Add FC7300F4MDDxxxT1C support + ******************************************************************************** */ + +#ifndef _HWA_MAM_H_ +#define _HWA_MAM_H_ +#include "device_header.h" + +#if MAM_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_mam HwA_mam + * @ingroup module_driver_mam + * @{ + */ + +/** + * @brief Set Mam module Matrix Configure register + * + * @param1 MAM base pointer + * + * @param2 u32Value Matrix Configure register value + */ +LOCAL_INLINE void Mam_HWA_SetMatrixCfg(MAM_Type *MAM, uint32_t u32Value) +{ + MAM->MAXCFG = u32Value; +} + +/** + * @brief Read Mam module Ctrl register + * + * @param MAM base pointer + * + * @return Matrix Configure register value + */ +LOCAL_INLINE uint32_t Mam_HWA_GetMatrixCfg(MAM_Type *MAM) +{ + return (uint32_t)(MAM->MAXCFG); +} + +/** + * @brief Set Mam module Wdgctr register + * + * @param1 MAM base pointer + * + * @param2 u32Value Wdgctr register value + */ +LOCAL_INLINE void Mam_HWA_SetWdgCr(MAM_Type *MAM, uint32_t u32Value) +{ + MAM->WDGCR = u32Value; +} + +/** + * @brief Read Mam module Wdgctr register + * + * @param MAM base pointer + * + * @return Wdgctr register value + */ +LOCAL_INLINE uint32 Mam_HWA_GetWdgCr(MAM_Type *MAM) +{ + return MAM->WDGCR; +} + +/** + * @brief Set Mam module timeout control register + * + * @param1 MAM base pointer + * + * @param2 u32Value timeout control register value + */ +LOCAL_INLINE void Mam_HWA_SetWdgToCr(MAM_Type *MAM, uint32_t u32Value) +{ + MAM->TOCR = u32Value; +} + +/** + * @brief Read Mam module timeout control register + * + * @param MAM base pointer + * + * @return timeout control register value + */ +LOCAL_INLINE uint32 Mam_HWA_GetWdgToCr(MAM_Type *MAM) +{ + return MAM->TOCR; +} + +#ifdef MAM_WDOG_DIV_SUPPORT +/** + * @brief Set Mam module watchdog div register + * + * @param1 MAM base pointer + * + * @param2 u32Value watchdog div register value + */ +LOCAL_INLINE void Mam_HWA_SetWdgDiv(MAM_Type *MAM, uint32_t u32Value) +{ + MAM->WDGDIV = u32Value; +} + +/** + * @brief Read Mam module watchdog div register + * + * @param MAM base pointer + * + * @return watchdog div register value + */ +LOCAL_INLINE uint32 Mam_HWA_GetWdgDiv(MAM_Type *MAM) +{ + return MAM->WDGDIV; +} +#endif + + +/** + * @brief Set Mam module ACR register + * + * @param1 MAM base pointer + * + * @param2 idx ACR register index + * + * @param3 u32Value ACR register value + */ +LOCAL_INLINE void Mam_HWA_Set_ACR(MAM_Type *MAM, uint32_t idx, uint32_t u32Value) +{ + MAM->ACR[idx] = u32Value; +} + +/** + * @brief Read Mam module ACR register + * + * @param1 MAM base pointer + * + * @param2 idx ACR register index + * + * @return ACR register value + */ +LOCAL_INLINE uint32_t Mam_HWA_Get_ACR(MAM_Type *MAM, uint32_t idx) +{ + return MAM->ACR[idx]; +} + +/** + * @brief Set Mam module ACLR register + * + * @param1 MAM base pointer + * + * @param2 idx ACLR register index + * + * @param3 u32Value ACLR register value + */ +LOCAL_INLINE void Mam_HWA_Set_ACLR(MAM_Type *MAM, uint32_t idx, uint32_t u32Value) +{ + MAM->ACLR[idx] = u32Value; +} + +/** + * @brief Read Mam module ACLR register + * + * @param1 MAM base pointer + * + * @param2 idx ACLR register index + * + * @return ACLR register value + */ +LOCAL_INLINE uint32_t Mam_HWA_Get_ACLR(MAM_Type *MAM, uint32_t idx) +{ + return MAM->ACLR[idx]; +} + +#ifdef MAM_PORT_MONITOR_SUPPORT +/** + * @brief Set the Check Control Register (CCLR) value + * + * @param MAM Pointer to the MAM peripheral register structure + * @param u32Value Value to write to the CCLR register + * - Each bit corresponds to a monitor port (0-31) + * - Setting a bit enables monitoring for that port + * - Clearing a bit disables monitoring for that port + */ +LOCAL_INLINE void Mam_HWA_Set_CCLR(MAM_Type *MAM, uint32_t u32Value) +{ + MAM->CCLR = u32Value; +} + +/** + * @brief Get the current Check Control Register (CCLR) value + * + * @param MAM Pointer to the MAM peripheral register structure + * @return uint32_t Current CCLR register value + * - Each bit represents the enabled state of a monitor port (0-31) + * - Bit set to 1: monitoring enabled for that port + * - Bit set to 0: monitoring disabled for that port + */ +LOCAL_INLINE uint32_t Mam_HWA_Get_CCLR(MAM_Type *MAM) +{ + return MAM->CCLR; +} +#endif + +#ifdef MAM_SLAVE_PRIORITY_SUPPORT +/** + * @brief Set the Priority Enable Register (PRI_EN) value + * + * @param MAM Pointer to the MAM peripheral register structure + * @param u32Value Priority enable configuration value + * - Each bit (0-31) enables/disables priority arbitration for a slave + * - Bit set to 1: priority arbitration enabled for corresponding slave + * - Bit set to 0: round-robin arbitration used for corresponding slave + */ +LOCAL_INLINE void Mam_HWA_Set_PRI_EN(MAM_Type *MAM, uint32_t u32Value) +{ + MAM->PRI_EN = MAM_PRIORITY_EN_KEY; + MAM->PRI_EN = u32Value; +} + +/** + * @brief Get the current Priority Enable Register (PRI_EN) value + * + * @param MAM Pointer to the MAM peripheral register structure + * @return uint32_t Current PRI_EN register value + * - Each bit (0-31) represents priority enable state for a slave + * - Bit set to 1: priority arbitration enabled for corresponding slave + * - Bit set to 0: round-robin arbitration used for corresponding slave + */ +LOCAL_INLINE uint32_t Mam_HWA_Get_PRI_EN(MAM_Type *MAM) +{ + return MAM->PRI_EN; +} + +/** + * @brief Set Priority ID for Slave Group 0 (slaves 0-7) + * + * @param MAM Pointer to the MAM peripheral register structure + * @param u32Value Priority configuration value + * - Bits [3:0]: Priority master for slave 0 + * - Bits [7:4]: Priority master for slave 1 + * - ... up to Bits [31:28]: Priority master for slave 7 + */ +LOCAL_INLINE void Mam_HWA_Set_PRI_ID_SLVGRP0(MAM_Type *MAM, uint32_t u32Value) +{ + MAM->PRI_ID_SLVGRP0 = u32Value; +} + +/** + * @brief Get current Priority ID for Slave Group 0 (slaves 0-7) + * + * @param MAM Pointer to the MAM peripheral register structure + * @return uint32_t Current priority configuration for slaves 0-7 + */ +LOCAL_INLINE uint32_t Mam_HWA_Get_PRI_ID_SLVGRP0(MAM_Type *MAM) +{ + return MAM->PRI_ID_SLVGRP0; +} + +/** + * @brief Set Priority ID for Slave Group 1 (slaves 8-15) + * + * @param MAM Pointer to the MAM peripheral register structure + * @param u32Value Priority configuration value + * - Byte 0: Priority master for slave 8 (bits [7:0]) + * - Byte 1: Priority master for slave 9 (bits [15:8]) + * - ... up to Byte 7: Priority master for slave 15 (bits [63:56]) + */ +LOCAL_INLINE void Mam_HWA_Set_PRI_ID_SLVGRP1(MAM_Type *MAM, uint32_t u32Value) +{ + MAM->PRI_ID_SLVGRP1 = u32Value; +} + +/** + * @brief Get current Priority ID for Slave Group 1 (slaves 8-15) + * + * @param MAM Pointer to the MAM peripheral register structure + * @return uint32_t Current priority configuration for slaves 8-15 + */ +LOCAL_INLINE uint32_t Mam_HWA_Get_PRI_ID_SLVGRP1(MAM_Type *MAM) +{ + return MAM->PRI_ID_SLVGRP1; +} +#endif + +/** @}*/ + +#endif /* #if MAM_INSTANCE_COUNT > 0U */ + +#endif diff --git a/Inc/HwA_mb.h b/Inc/HwA_mb.h new file mode 100644 index 0000000..7099a0d --- /dev/null +++ b/Inc/HwA_mb.h @@ -0,0 +1,638 @@ +/** + * @file HwA_mb.h + * @author flagchip + * @brief Mailbox hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip070 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip070 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_MAILBOX_H_ +#define _HWA_MAILBOX_H_ +#include "device_header.h" + +#if MB_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_mb HwA_mb + * @ingroup module_driver_mb + * @{ + */ + +/** + * @brief The definition of mask all events + * + */ +#define MB_EVENT_NONE 0u +/** + * @brief The definition of receiving all events + * + */ +#define MB_EVENT_ALL 0xFFFFFFFFu +/** + * @brief The definition of receiving all request events + * + */ +#define MB_EVENT_ALL_REQ 0x0000FFFFu +/** + * @brief The definition of receiving all done events + * + */ +#define MB_EVENT_ALL_DONE 0xFFFF0000u +/** + * @brief The definition of request events on ch + * + */ +#define MB_EVENT_REQ(ch) (uint32_t)((uint32_t)1u << (ch)) +/** + * @brief The definition of done events on ch + * + */ +#define MB_EVENT_DONE(ch) (uint32_t)((uint32_t)1u << ((ch) + MB_INTn_FLG_MASK_DONE_FLAG_MASK_SHIFT)) +/** + * @brief The definition of issue to no core + * + */ +#define MB_CORE_MASK_CORE_NONE 0u +/** + * @brief The definition of issue to core 0 + * + */ +#define MB_CORE_MASK_CORE_0 1u +/** + * @brief The definition of issue to core 1 + * + */ +#define MB_CORE_MASK_CORE_1 2u +/** + * @brief The definition of issue to core 2 + * + */ +#define MB_CORE_MASK_CORE_2 4u +/** + * @brief The definition of issue to HSM + * + */ +#define MB_CORE_MASK_HSM 8u +/** + * @brief The definition of issue to all cores + * + */ +#define MB_CORE_MASK_ALL 0xFu +/** + * @brief The definition of issue to core + * + */ +#define MB_CORE_MASK(core) (uint32_t)(1ul << (core)) + +/** + * @brief Lock the MB_INTn registers + * + * @param u8CoreIndex the index of the core + * @param u32Mask the lock bits + */ +LOCAL_INLINE void MB_HWA_LockIntrReg(uint8_t u8CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u8CoreIndex].CCn_CTRL |= u32Mask; +} + +/** + * @brief Unlock the MB_INTn registers + * + * @param u8CoreIndex the index of the core + * @param u32Mask the unlock bits + */ +LOCAL_INLINE void MB_HWA_UnlockIntrReg(uint8_t u8CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u8CoreIndex].CCn_CTRL &= ~u32Mask; +} + +/** + * @brief Lock the MB_INTn_FLG + * + * @param u8CoreIndex the index of the core + */ +LOCAL_INLINE void MB_HWA_LockFlag(uint8_t u8CoreIndex) +{ + MB->INTR[u8CoreIndex].CCn_CTRL |= MB_INTn_CTRL_FLG_LOCK_MASK; +} + +/** + * @brief Unlock the MB_INTn_FLG + * + * @param u8CoreIndex the index of the core + */ +LOCAL_INLINE void MB_HWA_UnlockFlag(uint8_t u8CoreIndex) +{ + MB->INTR[u8CoreIndex].CCn_CTRL &= ~MB_INTn_CTRL_FLG_LOCK_MASK; +} + +/** + * @brief Lock the MB_INTn_FLG_MASK + * + * @param u8CoreIndex the index of the core + */ +LOCAL_INLINE void MB_HWA_LockFlagMask(uint8_t u8CoreIndex) +{ + MB->INTR[u8CoreIndex].CCn_CTRL |= MB_INTn_CTRL_FLG_MASK_LOCK_MASK; +} + +/** + * @brief Unlock the MB_INTn_FLG_MASK + * + * @param u8CoreIndex the index of the core + */ +LOCAL_INLINE void MB_HWA_UnlockFlagMask(uint8_t u8CoreIndex) +{ + MB->INTR[u8CoreIndex].CCn_CTRL &= ~MB_INTn_CTRL_FLG_MASK_LOCK_MASK; +} + +/** + * @brief Lock the MB_INTn_INTEN + * + * @param u8CoreIndex the index of the core + */ +LOCAL_INLINE void MB_HWA_LockInten(uint8_t u8CoreIndex) +{ + MB->INTR[u8CoreIndex].CCn_CTRL |= MB_INTn_CTRL_INTEN_LOCK_MASK; +} + +/** + * @brief Unlock the MB_INTn_INTEN + * + * @param u8CoreIndex the index of the core + */ +LOCAL_INLINE void MB_HWA_UnlockInten(uint8_t u8CoreIndex) +{ + MB->INTR[u8CoreIndex].CCn_CTRL &= ~MB_INTn_CTRL_INTEN_LOCK_MASK; +} + +/** + * @brief Configure receive events of mailbox interrupt channel + * + * @param u8CoreIndex the index of the core + * @param u32Mask configuration for receiving events + */ +LOCAL_INLINE void MB_HWA_ConfigFlagMask(uint8_t u8CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u8CoreIndex].CCn_FLG_MASK = u32Mask; +} + +/** + * @brief Enable receive events of mailbox interrupt channel + * + * @param u8CoreIndex the index of the core + * @param u32Mask indicates the events to be enabled + */ +LOCAL_INLINE void MB_HWA_EnableEvent(uint8_t u8CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u8CoreIndex].CCn_FLG_MASK |= u32Mask; +} + +/** + * @brief Disable receive events of mailbox interrupt channel + * + * @param u8CoreIndex the index of the core + * @param u32Mask indicates the events to be enabled + */ +LOCAL_INLINE void MB_HWA_DisableEvent(uint8_t u8CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u8CoreIndex].CCn_FLG_MASK &= ~u32Mask; +} + +/** + * @brief Configure the interrupt of mailbox interrupt channel + * + * @param u8CoreIndex the index of the core + * @param u32Mask configuration for interrupts + */ +LOCAL_INLINE void MB_HWA_ConfigIntrEnable(uint8_t u8CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u8CoreIndex].CCn_INTEN = u32Mask; +} + +/** + * @brief Enable the interrupt of mailbox interrupt channel + * + * @param u8CoreIndex the index of the core + * @param u32Mask indicates the interrupts to be enabled + */ +LOCAL_INLINE void MB_HWA_EnableIntr(uint8_t u8CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u8CoreIndex].CCn_INTEN |= u32Mask; +} + +/** + * @brief Disable the interrupt of mailbox interrupt channel + * + * @param u8CoreIndex the index of the core + * @param u32Mask indicates the interrupts to be disabled + */ +LOCAL_INLINE void MB_HWA_DisableIntr(uint8_t u8CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u8CoreIndex].CCn_INTEN &= ~u32Mask; +} + +/** + * @brief Clear the flag of mailbox interrupt channel + * + * @param u8CoreIndex the index of the core + * @param u32Mask indicates the flags to be cleared + */ +LOCAL_INLINE void MB_HWA_ClearFlag(uint8_t u8CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u8CoreIndex].CCn_FLG = u32Mask; +} + +/** + * @brief Get the flag masks of mailbox interrupt channel + * + * @param u8CoreIndex the index of the core + * @param u32Mask the mask to get + * @return the flag masks of the mailbox interrupt channel + */ +LOCAL_INLINE uint32_t MB_HWA_GetFlagMask(uint8_t u8CoreIndex, uint32_t u32Mask) +{ + return MB->INTR[u8CoreIndex].CCn_FLG_MASK & u32Mask; +} + +/** + * @brief Get the flags of mailbox interrupt channel + * + * @param u8CoreIndex the index of the core + * @param u32Mask the mask to get + * @return the flags of the mailbox interrupt channel + */ +LOCAL_INLINE uint32_t MB_HWA_GetFlag(uint8_t u8CoreIndex, uint32_t u32Mask) +{ + return MB->INTR[u8CoreIndex].CCn_FLG & u32Mask; +} + +/** + * @brief Get the result of flag & inten of mailbox interrupt channel + * + * @param u8CoreIndex the index of the core + * @param u32Mask the mask to get + * @return the result of flag & inten of the mailbox interrupt channel + */ +LOCAL_INLINE uint32_t MB_HWA_GetFlagStat(uint8_t u8CoreIndex, uint32_t u32Mask) +{ + return MB->INTR[u8CoreIndex].CCn_FLG_STAT & u32Mask; +} + +/** + * @brief Get the master ID of the currently obtained channel + * + * @param u32Channel the index of the channel + * @return the master ID + */ +LOCAL_INLINE uint32_t MB_HWA_GetMasterID(uint32_t u32Channel) +{ + return (MB->CHANNEL[u32Channel].CCn_STAT & MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_MASK) >> MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_SHIFT; +} + +/** + * @brief Send data to the mailbox channel + * + * @param u32Channel the index of the channel + * @param pData the buffer to be written + */ +LOCAL_INLINE void MB_HWA_WriteData(uint32_t u32Channel, uint32_t *pData) +{ + MB->CHANNEL[u32Channel].CCn_DATA0 = pData[0]; + MB->CHANNEL[u32Channel].CCn_DATA1 = pData[1]; +} + +/** + * @brief Receive data from the mailbox channel + * + * @param u32Channel the index of the channel + * @param pData the buffer to receive data + */ +LOCAL_INLINE void MB_HWA_GetData(uint32_t u32Channel, uint32_t *pData) +{ + pData[0] = MB->CHANNEL[u32Channel].CCn_DATA0; + pData[1] = MB->CHANNEL[u32Channel].CCn_DATA1; +} + +/** + * @brief Get the automatically clear status of the mailbox channel + * + * @param u32Channel the index of the channel + * @param u8CoreIndex the index of the core + * @return automatically clear the channel lock enable bit + */ +LOCAL_INLINE uint32_t MB_HWA_GetAutoClear(uint32_t u32Channel, uint8_t u8CoreIndex) +{ + return MB->CHANNEL[u32Channel].CCn_SEMA_UNLK & ((uint32_t)1u << u8CoreIndex); +} + +/** + * @brief Release the mailbox channel + * + * @param u32Channel the index of the channel + */ +LOCAL_INLINE void MB_HWA_ReleaseChannel(uint32_t u32Channel) +{ + MB->CHANNEL[u32Channel].CCn_DONE = MB_MASTER_DONE_CODE; +} + +/** + * @brief Software clears channel lock + * + * @param u32Channel the index of the channel + */ +LOCAL_INLINE void MB_HWA_UnlockChannel(uint32_t u32Channel) +{ + MB->CHANNEL[u32Channel].CCn_CLR = MB_FORCE_UNLOCK_CODE; +} + +/** + * @brief Issue a done event + * + * @param u32Channel the index of the channel + * @param u32DoneMask the cores to issue + */ +LOCAL_INLINE void MB_HWA_SetDone(uint32_t u32Channel, uint32_t u32DoneMask) +{ + MB->CHANNEL[u32Channel].CCn_DONE |= (u32DoneMask & MB_CCn_DONE_MASK); +} + +/** + * @brief Get the Communication Channel Semaphore Register + * + * @param u32Channel the index of the channel + * @return Channel Lock Acquisition + */ +LOCAL_INLINE uint32_t MB_HWA_GetSemaphore(uint32_t u32Channel, uint32_t u32Mask) +{ + return MB->CHANNEL[u32Channel].CCn_SEMA & u32Mask; +} + +/** + * @brief Configure the master ID of the core that generates a done event + * + * @param u32Channel the index of the channel + * @param u32MasterId master ID + */ +LOCAL_INLINE void MB_HWA_ConfigDoneMasterId(uint32_t u32Channel, uint32_t u32MasterId) +{ + MB->CHANNEL[u32Channel].CCn_DONE_MASK = (MB->CHANNEL[u32Channel].CCn_DONE_MASK & (~MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK)) \ + | MB_CCn_DONE_MASK_DONE_MASTER_ID(u32MasterId); +} + +/** + * @brief Get the master ID of the core that generates a done event + * + * @param u32Channel the index of the channel + * @return the master ID + */ +LOCAL_INLINE uint32_t MB_HWA_GetDoneMasterId(uint32_t u32Channel) +{ + return (MB->CHANNEL[u32Channel].CCn_DONE_MASK & MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK) \ + >> MB_CCn_DONE_MASK_DONE_MASTER_ID_SHIFT; + +} + +/** + * @brief Configure the mask of the done events + * + * @param u32Channel the index of the channel + * @param u32DoneMask the cores to issue + */ +LOCAL_INLINE void MB_HWA_ConfigDoneMask(uint32_t u32Channel, uint32_t u32DoneMask) +{ + MB->CHANNEL[u32Channel].CCn_DONE_MASK = (MB->CHANNEL[u32Channel].CCn_DONE_MASK & (~MB_CCn_DONE_MASK)) | \ + (u32DoneMask & MB_CCn_DONE_MASK); +} + +/** + * @brief Get the mask of the done events + * + * @param u32Channel the index of the channel + * @return the mask of the done events + */ +LOCAL_INLINE uint32_t MB_HWA_GetDoneMask(uint32_t u32Channel) +{ + return MB->CHANNEL[u32Channel].CCn_DONE_MASK & MB_CCn_DONE_MASK; +} + +/** + * @brief Configure the automatically clear of the lock enable bit + * + * @param u32Channel the index of the channel + * @param u32AutoUnlockMask the automatically clear of the lock enable bit + */ +LOCAL_INLINE void MB_HWA_ConfigAutoUnlock(uint32_t u32Channel, uint32_t u32AutoUnlockMask) +{ + MB->CHANNEL[u32Channel].CCn_SEMA_UNLK = u32AutoUnlockMask & MB_CCn_SEMA_UNLK_MASK; +} + +/** + * @brief Issue request events + * + * @param u32Channel the index of the channel + * @param u32RequestMask the cores to issue + */ +LOCAL_INLINE void MB_HWA_ConfigRequest(uint32_t u32Channel, uint32_t u32RequestMask) +{ + MB->CHANNEL[u32Channel].CCn_REQUEST = u32RequestMask & MB_CCn_REQUEST_MASK; +} + +#ifdef MB_SEMA_EXSIST +/** + * @brief Function to get the semaphore status + * + * This function retrieves the status of a semaphore specified by the identifier u32Sema. + * It accesses the SEMAn_STATUS array of a predefined MB object, which contains the status values of all semaphores. + * + * @param u32Sema Semaphore identifier used to specify the semaphore whose status is to be retrieved. + * @return uint32_t Returns the status value of the specified semaphore. + * + */ +LOCAL_INLINE uint32_t MB_HWA_GetSemaStatus(uint32_t u32Sema) +{ + return MB->SEMAn_STATUS[u32Sema]; +} + +/** + * @brief Get semaphore lock status + * + * @param u32Sema Semaphore identifier + * + * @return bool Returns the semaphore lock status + * + * @note This function checks the specific bit in the SEMAn_STATUS register to determine if the semaphore is locked + */ +LOCAL_INLINE bool MB_HWA_GetSemaLock(uint32_t u32Sema) +{ + return (bool)(MB->SEMAn_STATUS[u32Sema] & MB_SEMAn_STATUS_SEMA_FLG_MASK); +} +/** + * @brief Get the master ID of a semaphore + * + * @param u32Sema Semaphore identifier used to select the specific semaphore status register + * @return uint8_t The master ID of the semaphore + */ +LOCAL_INLINE uint8_t MB_HWA_GetSemaMasterID(uint32_t u32Sema) +{ + return (uint8_t)((MB->SEMAn_STATUS[u32Sema] & MB_SEMAn_STATUS_SEMA_MID_MASK) >> MB_SEMAn_STATUS_SEMA_MID_SHIFT); +} + +/** + * @brief Get Semaphore Resource ID + * + * @param u32Sema Semaphore index, indicating which semaphore register to use. + * @return uint8_t Semaphore resource ID. + */ +LOCAL_INLINE uint8_t MB_HWA_GetSemaResourceID(uint32_t u32Sema) +{ + return (uint8_t)((MB->SEMAn_STATUS[u32Sema] & MB_SEMAn_STATUS_SEMA_RSRC_ID_MASK) >> MB_SEMAn_STATUS_SEMA_RSRC_ID_SHIFT); +} + +/** + * @brief Get the global semaphore status + * + * @return uint16_t The current global semaphore status value + */ +LOCAL_INLINE uint16_t MB_HWA_GetSemaGlobalStatus(void) +{ + return (uint16_t)(MB->SEMA_GLOBAL_STATUS & MB_SEMA_GLOBAL_STATUS_MASK); +} + +/** + * @brief Enable semaphore lock protection + * + */ +LOCAL_INLINE void MB_HWA_EnableSemaLockProtect(void) +{ + MB->SEMA_CTRL &= ~MB_SEMA_CTRL_MASK; +} + +/** + * @brief Disable semaphore lock protection + * + */ +LOCAL_INLINE void MB_HWA_DisableSemaLockProtect(void) +{ + MB->SEMA_CTRL |= MB_SEMA_CTRL_MASK; +} + +/** + * @brief Get the SEMA error status register value + * + * @return uint32_t The current value of the SEMA error status register + */ +LOCAL_INLINE uint32_t MB_HWA_ReadSemaErrorStatus(void) +{ + return MB->SEMA_ERROR_STATUS; +} + +/** + * @brief Get Semaphore Error Resource ID + * + * @return uint8_t The value of the semaphore error resource ID + */ +LOCAL_INLINE uint8_t MB_HWA_GetSemaErrorResourceID(void) +{ + return (uint8_t)((MB->SEMA_ERROR_STATUS & MB_SEMA_ERROR_STATUS_SEMA_ERR_RSRC_ID_MASK) >> MB_SEMA_ERROR_STATUS_SEMA_ERR_RSRC_ID_SHIFT); +} + +/** + * @brief Get Semaphore Master ID + * + * @return uint8_t The value of the semaphore error master ID + */ +LOCAL_INLINE uint8_t MB_HWA_GetSemaErrorMasterID(void) +{ + return (uint8_t)((MB->SEMA_ERROR_STATUS & MB_SEMA_ERROR_STATUS_SEMA_ERR_MID_MASK) >> MB_SEMA_ERROR_STATUS_SEMA_ERR_MID_SHIFT); +} + +/** + * @brief Get Semaphore Error Status + * + * @return uint8_t The value of the semaphore error status + */ +LOCAL_INLINE uint32_t MB_HWA_GetSemaErrorStatus(void) +{ + return MB->SEMA_ERROR_STATUS; +} + +/** + * @brief Sets the software reset signal for the MB module + * + */ +LOCAL_INLINE void MB_HWA_SoftwareResetSema(void) +{ + MB->SEMA_SW_RESET = MB_SEMA_KEY_SW_RESET; +} + +/** + * @brief Release all semaphores + * + * @param u8MasterId The Master Index used to identify the resource to be acquired, the value should be 0~4 + */ +LOCAL_INLINE void MB_HWA_ReleaseAllSema(uint8_t u8MasterIdx) +{ + MB->SEMA_RELEASE = MB_SEMA_KEY_RELEASE_ALL | (uint32_t)(u8MasterIdx & 0x7u); +} + +/** + * @brief Acquire a resource by its ID + * + * @param u32ResourceID The resource ID used to identify the resource to be acquired + */ +LOCAL_INLINE uint32_t MB_HWA_GetResource(uint32_t u32ResourceID) +{ + return MB->SEMA_RSRC[u32ResourceID]; +} + +/** + * @brief Unlocks the specified resource + * + * This function unlocks the resource identified by u32ResourceID by setting the associated semaphore key to an unlocked state. + * + * @param u32ResourceID The resource identifier used to specify the resource to unlock + */ +LOCAL_INLINE void MB_HWA_UnlockResource(uint32_t u32ResourceID) +{ + MB->SEMA_RSRC[u32ResourceID] = MB_SEMA_KEY_UNLOCK; +} + +LOCAL_INLINE void MB_HWA_ReleaseResource(uint32_t u32ResourceID) +{ + MB->SEMA_RSRC[u32ResourceID] = MB_SEMA_KEY_RELEASE; +} + +/** + * @brief Clear error status function + * + * Sets the status flag for the specified resource ID to the key value that clears the error status. + * + */ +LOCAL_INLINE void MB_HWA_ClearErrorStatus(void) +{ + MB->SEMA_ERROR_STATUS = MB_SEMA_KEY_CLEAR_ERROR; +} +#endif + +/** @}*/ + +#endif /* #if MB_INSTANCE_COUNT > 0U */ + +#endif + diff --git a/Inc/HwA_msc.h b/Inc/HwA_msc.h new file mode 100644 index 0000000..55ee528 --- /dev/null +++ b/Inc/HwA_msc.h @@ -0,0 +1,710 @@ +/** + * @file HwA_msc.h + * @author flagchip + * @brief MSC hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + ******************************************************************************** */ +#ifndef _HWA_MSC_H_ +#define _HWA_MSC_H_ + +#include "device_header.h" + +#if MSC_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_msc HwA_msc + * @ingroup module_driver_msc + * @{ + */ + +/********* macros ************/ + +typedef enum +{ + MSC_RSV_SUCCESS = 0x0U, /*!< MSC receive status is successful. */ + MSC_RSV_PARITY_ERROR = 0x1U, /*!< MSC receive has parity error. */ + MSC_RSV_STOP_ERROR = 0x2U, /*!< MSC receive has stop error. */ + MSC_RSV_ERROR = 0x4U, /*!< MSC receive status is not successful. */ +} MSC_ReceiveStatusType; + +/********* Local typedef ************/ + +/********* Local inline function ************/ + +/********* xxx Register interface ************/ + +/** + * @brief Get the msc TCCTR register + * + * @param pMsc MSCInstance + * @param u32Value TCCTR register value + */ +LOCAL_INLINE void MSC_HWA_SetTcctr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCCTR = u32Value; +} + +/** + * @brief Get the msc TCCTR register DTS bit + * + * @param pMsc MSCInstance + * @return DTS value + */ +LOCAL_INLINE bool MSC_HWA_GetDataNeedSend(MSC_Type *const pMsc) +{ + return (pMsc->TCCTR & MSC_TCCTR_DTS_MASK) == MSC_TCCTR_DTS_MASK ? true : false; +} + +/** + * @brief Set the msc TCCTR register DTS bit + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_SetDataNeedSend(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_SDTS_MASK; +} + +/** + * @brief Get the msc TCCTR register CTS bit + * + * @param pMsc MSCInstance + * @return CTS value + */ +LOCAL_INLINE bool MSC_HWA_GetCmdNeedSend(MSC_Type *const pMsc) +{ + return (pMsc->TCCTR & MSC_TCCTR_CTS_MASK) == MSC_TCCTR_CTS_MASK ? true : false; +} + +/** + * @brief Get the CFB value of TCSTR register + * + * @param pMsc MSCInstance + * @return CFB value + */ +LOCAL_INLINE bool MSC_HWA_GetCfb(MSC_Type *const pMsc) +{ + return (bool)(((pMsc->TCSTR & (uint32_t)MSC_TCSTR_CFB_MASK) != 0U) ? true : false); +} + +/** + * @brief Get the DFB value of TCSTR register + * + * @param pMsc MSCInstance + * @return DFB value + */ +LOCAL_INLINE bool MSC_HWA_GetDfb(MSC_Type *const pMsc) +{ + return ((pMsc->TCSTR & (uint32_t)MSC_TCSTR_DFB_MASK) != 0U) ? true : false; +} + + +/** + * @brief Set the NP value of TCSTR register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_SetNp(MSC_Type *const pMsc, uint8_t u8Np) +{ + pMsc->TCSTR = (pMsc->TCSTR & ~MSC_TCSTR_NP_MASK) | MSC_TCSTR_NP(u8Np); +} + +/** + * @brief Get the NP value of TCSTR register + * + * @param pMsc MSCInstance + * @return NP value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetNp(MSC_Type *const pMsc) +{ + return ((pMsc->TCSTR & (uint32_t)MSC_TCSTR_NP_MASK)) >> MSC_TCSTR_NP_SHIFT; +} + +/** + * @brief Set the msc TCDAR register + * + * @param pMsc MSCInstance + * @param u32Value TCDAR value + */ +LOCAL_INLINE void MSC_HWA_SetTcdar(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCDAR = u32Value; +} + +/** + * @brief Set the TDH of TCDAR register + * + * @param pMsc MSCInstance + * @param u16Value TDH value + */ +LOCAL_INLINE void MSC_HWA_SetTcdarTdh(MSC_Type *const pMsc, uint16_t u16Value) +{ + pMsc->TCDAR = (pMsc->TCDAR & ~MSC_TCDAR_TDH_MASK) | MSC_TCDAR_TDH(u16Value); +} + +/** + * @brief Set the TDL of TCDAR register + * + * @param pMsc MSCInstance + * @param u16Value TDL value + */ +LOCAL_INLINE void MSC_HWA_SetTcdarTdl(MSC_Type *const pMsc, uint16_t u16Value) +{ + pMsc->TCDAR = (pMsc->TCDAR & ~MSC_TCDAR_TDL_MASK) | MSC_TCDAR_TDL(u16Value); +} + +/** + * @brief Set the TCCOR register + * + * @param pMsc MSCInstance + * @param u32Value TCCOR value + */ +LOCAL_INLINE void MSC_HWA_SetTccor(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCCOR = u32Value; +} + +/** + * @brief Set the TCH of TCCOR register + * + * @param pMsc MSCInstance + * @param u16Value TCH value + */ +LOCAL_INLINE void MSC_HWA_SetTccorTch(MSC_Type *const pMsc, uint16_t u16Value) +{ + pMsc->TCCOR = (pMsc->TCCOR & ~MSC_TCCOR_TCH_MASK) | MSC_TCCOR_TCH(u16Value); +} + +/** + * @brief Set the TCL of TCCOR register + * + * @param pMsc MSCInstance + * @param u16Value TCL value + */ +LOCAL_INLINE void MSC_HWA_SetTccorTcl(MSC_Type *const pMsc, uint16_t u16Value) +{ + pMsc->TCCOR = (pMsc->TCCOR & ~MSC_TCCOR_TCL_MASK) | MSC_TCCOR_TCL(u16Value); +} + +/** + * @brief Set the TCSLR register + * + * @param pMsc MSCInstance + * @param u32Value TCSLR value + */ +LOCAL_INLINE void MSC_HWA_SetTcslr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCSLR = u32Value; +} + +/** + * @brief Set the TCSHR register + * + * @param pMsc MSCInstance + * @param u32Value TCSHR value + */ +LOCAL_INLINE void MSC_HWA_SetTcshr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCSHR = u32Value; +} + +/** + * @brief Set the TCELR register + * + * @param pMsc MSCInstance + * @param u32Value TCELR value + */ +LOCAL_INLINE void MSC_HWA_SetTcelr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCELR = u32Value; +} + +/** + * @brief Set the IOCR register + * + * @param pMsc MSCInstance + * @param u32Value IOCR value + */ +LOCAL_INLINE void MSC_HWA_SetIocr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->IOCR = u32Value; +} + +/** + * @brief Set the ISCR register + * + * @param pMsc MSCInstance + * @param u32Value ISCR value + */ +LOCAL_INLINE void MSC_HWA_SetIscr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->ISCR = u32Value; +} + +/** + * @brief Set the msc TCDIS + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_SetTcdis(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_SDIS_MASK; +} + +/** + * @brief Clear the msc TCDIS + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearTcdis(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CDIS_MASK; +} + +/** + * @brief Clear the msc CRFI + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearCrfi(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CRFI_MASK; +} + +/** + * @brief Clear the msc CTFI + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearCtfi(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CTFI_MASK; +} + +/** + * @brief Clear the msc CCFI + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearCcfi(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CCFI_MASK; +} + +/** + * @brief Clear the msc CDFI + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearCdfi(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CDFI_MASK; +} + +/** + * @brief Get the msc INSR register + * + * @param pMsc MSCInstance + * @return INSR register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetInsr(MSC_Type *const pMsc) +{ + return pMsc->INSR & (uint32_t)MSC_INSR_MASK; +} + +/** + * @brief Set the INCR register + * + * @param pMsc MSCInstance + * @param u32Value INCR value + */ +LOCAL_INLINE void MSC_HWA_SetIncr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->INCR = u32Value; +} + +/** + * @brief Get the msc INCR register + * + * @param pMsc MSCInstance + * @return INCR register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetIncr(MSC_Type *const pMsc) +{ + return pMsc->INCR; +} + +/** + * @brief Get the msc RCCSR register + * + * @param pMsc MSCInstance + * @return RCCSR register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetRccsr(MSC_Type *const pMsc) +{ + return pMsc->RCCSR; +} + +/** + * @brief Set the RCCSR register + * + * @param pMsc MSCInstance + * @param u32Value RCCSR value + */ +LOCAL_INLINE void MSC_HWA_SetRccsr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->RCCSR = u32Value; +} + +/** + * @brief Get the DATA of RDR0 register + * + * @param pMsc MSCInstance + * @return RDATA value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr0Data(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR0 & MSC_RDR0_RDATA_MASK) >> MSC_RDR0_RDATA_SHIFT); +} + +/** + * @brief Get the LAF of RDR0 register + * + * @param pMsc MSCInstance + * @return LAF value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr0Addr(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR0 & MSC_RDR0_LAF_MASK) >> MSC_RDR0_LAF_SHIFT); +} + +/** + * @brief Get the VLD of RDR0 register + * + * @param pMsc MSCInstance + * @return VLD value + */ +LOCAL_INLINE bool MSC_HWA_GetRdr0Vld(MSC_Type *const pMsc) +{ + return (pMsc->RDR0 & MSC_RDR0_VLD_MASK) == MSC_RDR0_VLD_MASK ? true : false; +} + +/** + * @brief Get the RERR of RDR0 register + * + * @param pMsc MSCInstance + * @return RERR value + */ +LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr0Rerr(MSC_Type *const pMsc) +{ + uint32_t u32Tempvalue = (pMsc->RDR0 & MSC_RDR0_RERR_MASK) >> MSC_RDR0_RERR_SHIFT; + return (MSC_ReceiveStatusType)u32Tempvalue; +} + +/** + * @brief Clear the VLD of register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearRdr0Vld(MSC_Type *const pMsc) +{ + pMsc->RDR0 |= MSC_RDR0_CLR_MASK; +} + + +/** + * @brief Get the DATA of RDR1 register + * + * @param pMsc MSCInstance + * @return RDATA value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr1Data(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR1 & MSC_RDR1_RDATA_MASK) >> MSC_RDR1_RDATA_SHIFT); +} + +/** + * @brief Get the LAF of RDR1 register + * + * @param pMsc MSCInstance + * @return LAF value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr1Addr(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR1 & MSC_RDR1_LAF_MASK) >> MSC_RDR1_LAF_SHIFT); +} + +/** + * @brief Get the VLD of RDR1 register + * + * @param pMsc MSCInstance + * @return VLD value + */ +LOCAL_INLINE bool MSC_HWA_GetRdr1Vld(MSC_Type *const pMsc) +{ + return (pMsc->RDR1 & MSC_RDR1_VLD_MASK) == MSC_RDR1_VLD_MASK ? true : false; +} + +/** + * @brief Get the RERR of RDR1 register + * + * @param pMsc MSCInstance + * @return RERR value + */ +LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr1Rerr(MSC_Type *const pMsc) +{ + uint32_t u32Tempvalue = (pMsc->RDR1 & MSC_RDR1_RERR_MASK) >> MSC_RDR1_RERR_SHIFT; + return (MSC_ReceiveStatusType)u32Tempvalue ; +} + +/** + * @brief Clear the VLD of register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearRdr1Vld(MSC_Type *const pMsc) +{ + pMsc->RDR1 |= MSC_RDR1_CLR_MASK; +} + + +/** + * @brief Get the DATA of RDR2 register + * + * @param pMsc MSCInstance + * @return RDATA value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr2Data(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR2 & MSC_RDR2_RDATA_MASK) >> MSC_RDR2_RDATA_SHIFT); +} + +/** + * @brief Get the LAF of RDR2 register + * + * @param pMsc MSCInstance + * @return LAF value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr2Addr(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR2 & MSC_RDR2_LAF_MASK) >> MSC_RDR2_LAF_SHIFT); +} + +/** + * @brief Get the VLD of RDR2 register + * + * @param pMsc MSCInstance + * @return VLD value + */ +LOCAL_INLINE bool MSC_HWA_GetRdr2Vld(MSC_Type *const pMsc) +{ + return (pMsc->RDR2 & MSC_RDR2_VLD_MASK) == MSC_RDR2_VLD_MASK ? true : false; +} + +/** + * @brief Get the RERR of RDR2 register + * + * @param pMsc MSCInstance + * @return RERR value + */ +LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr2Rerr(MSC_Type *const pMsc) +{ + uint32_t u32Tempvalue = (pMsc->RDR2 & MSC_RDR2_RERR_MASK) >> MSC_RDR2_RERR_SHIFT; + return (MSC_ReceiveStatusType)u32Tempvalue; +} + +/** + * @brief Clear the VLD of register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearRdr2Vld(MSC_Type *const pMsc) +{ + pMsc->RDR2 |= MSC_RDR2_CLR_MASK; +} + + +/** + * @brief Get the DATA of RDR3 register + * + * @param pMsc MSCInstance + * @return RDATA value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr3Data(MSC_Type *const pMsc) +{ + return (uint8_t)(pMsc->RDR3 & MSC_RDR3_RDATA_MASK) >> MSC_RDR3_RDATA_SHIFT; +} + +/** + * @brief Get the LAF of RDR3 register + * + * @param pMsc MSCInstance + * @return LAF value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr3Addr(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR3 & MSC_RDR3_LAF_MASK) >> MSC_RDR3_LAF_SHIFT); +} + +/** + * @brief Get the VLD of RDR3 register + * + * @param pMsc MSCInstance + * @return VLD value + */ +LOCAL_INLINE bool MSC_HWA_GetRdr3Vld(MSC_Type *const pMsc) +{ + return (pMsc->RDR3 & MSC_RDR3_VLD_MASK) == MSC_RDR3_VLD_MASK ? true : false; +} + +/** + * @brief Get the RERR of RDR3 register + * + * @param pMsc MSCInstance + * @return RERR value + */ +LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr3Rerr(MSC_Type *const pMsc) +{ + uint32_t u32Tempvalue = (pMsc->RDR3 & MSC_RDR3_RERR_MASK) >> MSC_RDR3_RERR_SHIFT; + return (MSC_ReceiveStatusType)u32Tempvalue; +} + +/** + * @brief Clear the VLD of register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearRdr3Vld(MSC_Type *const pMsc) +{ + pMsc->RDR3 |= MSC_RDR3_CLR_MASK; +} + +/** + * @brief Reset the msc + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_SetMsrRst(MSC_Type *const pMsc) +{ + pMsc->MSR |= MSC_MSR_RST_MASK; +} + +/** + * @brief Get the reset status + * + * @param pMsc MSCInstance + * @return reset status + */ +LOCAL_INLINE bool MSC_HWA_GetMsrRdone(MSC_Type *const pMsc) +{ + return (bool)(((pMsc->MSR & MSC_MSR_RDONE_MASK) != 0U) ? true : false); +} + +/** + * @brief clear reset status + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearMsrDone(MSC_Type *const pMsc) +{ + pMsc->SRCR = MSC_SRCR_RCLR_MASK; +} + +/** + * @brief Get the msc RTOR register + * + * @param pMsc MSCInstance + * @return RTOR register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetRtor(MSC_Type *const pMsc) +{ + return pMsc->RTOR; +} + +/** + * @brief Set the msc RTOR register + * + * @param pMsc MSCInstance + * @param u32Value RTOR value + */ +LOCAL_INLINE void MSC_HWA_SetRtor(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->RTOR = u32Value; +} + +/** + * @brief Get the msc TCCTR1 register + * + * @param pMsc MSCInstance + * @return TCCTR1 register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetTcctr1(MSC_Type *const pMsc) +{ + return pMsc->TCCTR1; +} + +/** + * @brief Set the msc TCCTR1 register + * + * @param pMsc MSCInstance + * @param u32Value TCCTR1 value + */ +LOCAL_INLINE void MSC_HWA_SetTcctr1(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCCTR1 = u32Value; +} + +/** + * @brief Set the EN msc GCR register + * + * @param pMsc MSCInstance + * @param bEnable EN value + */ +LOCAL_INLINE void MSC_HWA_SetMscEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->GCR = (pMsc->GCR & ~MSC_GCR_EN_MASK) | MSC_GCR_EN(bEnable); +} + +/** + * @brief Set the WP_EN of msc GCR register + * + * @param pMsc MSCInstance + * @param bEnable WP_EN value + */ +LOCAL_INLINE void MSC_HWA_SetMscWriteProtection(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->GCR = (pMsc->GCR & ~MSC_GCR_WP_EN_MASK) | MSC_GCR_WP_EN(bEnable); +} + +/** + * @brief Unlock the msc CCULR register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_Unlock(MSC_Type *const pMsc) +{ + pMsc->CCULR = 0x10248888U; +} + + +/** @}*/ /* HwA_msc */ + +#endif /* #if MSC_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_MSC_H_ */ diff --git a/Inc/HwA_ospi.h b/Inc/HwA_ospi.h new file mode 100644 index 0000000..c25cad5 --- /dev/null +++ b/Inc/HwA_ospi.h @@ -0,0 +1,874 @@ +/** + * @file HwA_ospi.h + * @author Flagchip + * @brief ospi hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip087 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip087 N/A Change version and release + ******************************************************************************** */ +#ifndef _HWA_OSPI_H_ +#define _HWA_OSPI_H_ + +#include "device_header.h" + +#if OSPI_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_ospi HwA_ospi + * @ingroup module_driver_ospi + * @{ + */ + +typedef enum +{ + DQS_INTER_LOOPBACK = 0, + DQS_PAD_LOOPBACK, + DQS_EXTERNAL_PADINPUT +}OSPI_DqsSrcSelType; + +typedef enum +{ + OSPI_CLOCK_DIV_1 = 0U, + OSPI_CLOCK_DIV_2 = 1U, + OSPI_CLOCK_DIV_3 = 2U, + OSPI_CLOCK_DIV_4 = 3U, + OSPI_CLOCK_DIV_5 = 4U, + OSPI_CLOCK_DIV_6 = 5U, + OSPI_CLOCK_DIV_7 = 6U, + OSPI_CLOCK_DIV_8 = 7U +}OSPI_ClockDivideType; + +typedef enum +{ + OSPI_MUX_PLL0 = 0, + OSPI_MUX_FIRC, + OSPI_MUX_PLL1 +}OSPI_ClockMuxType; + +typedef enum +{ + OSPI_BIG_ENDIAN = 0, + OSPI_LITTLE_ENDIAN, +}OSPI_EndianType; + +#define CTRL_RST_VALUE 0x34000 +/********* Local inline function ************/ +#ifdef OSPI_CTRL_SWRST +/** + * @brief Generate a software reset of OSPI hardware. + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_SW_Reset(OSPI_Type *pOSPI) +{ + pOSPI->CTRL |= OSPI_CTRL_SWRST(1); + pOSPI->CTRL &= ~OSPI_CTRL_SWRST(1); +} +#endif + +/** + * @brief OSPI DIO3 Default High + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_Dio3DefHigh(OSPI_Type *pOSPI) +{ + pOSPI->CTRL |= OSPI_CTRL_DSDIO3_MASK; +} + +/** + * @brief OSPI DIO3 Default Low + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_Dio3DefLow(OSPI_Type *pOSPI) +{ + pOSPI->CTRL &= ~OSPI_CTRL_DSDIO3_MASK; +} + +/** + * @brief OSPI DIO2 Default High + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_Dio2DefHigh(OSPI_Type *pOSPI) +{ + pOSPI->CTRL |= OSPI_CTRL_DSDIO2_MASK; +} + +/** + * @brief OSPI DIO2 Default Low + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_Dio2DefLow(OSPI_Type *pOSPI) +{ + pOSPI->CTRL &= ~OSPI_CTRL_DSDIO2_MASK; +} + + +/** + * @brief OSPI Module Enable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_ModuleEnable(OSPI_Type *pOSPI) +{ + pOSPI->CTRL &= ~OSPI_CTRL_MDIS_MASK; +} + +/** + * @brief OSPI Module Disable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_ModuleDisable(OSPI_Type *pOSPI) +{ + pOSPI->CTRL |= OSPI_CTRL_MDIS_MASK; +} + +/** + * @brief OSPI Clear Tx fifo + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_ClearTxFifo(OSPI_Type *pOSPI) +{ + pOSPI->CTRL |= OSPI_CTRL_CLR_TF_MASK; +} + +/** + * @brief OSPI Clear Rx fifo + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_ClearRxFifo(OSPI_Type *pOSPI) +{ + pOSPI->CTRL |= OSPI_CTRL_CLR_RF_MASK; +} + + +/** + * @brief OSPI DDR Mode Enable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_DdrModeEnable(OSPI_Type *pOSPI) +{ + pOSPI->CTRL |= OSPI_CTRL_DDR_EN_MASK; +} + +/** + * @brief OSPI DDR Mode Disable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_DdrModeDisable(OSPI_Type *pOSPI) +{ + pOSPI->CTRL &= ~OSPI_CTRL_DDR_EN_MASK; +} + +/** + * @brief OSPI DQS Mode Enable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_DqsModeEnable(OSPI_Type *pOSPI) +{ + pOSPI->CTRL |= OSPI_CTRL_RWDS_EN_MASK; +} + +/** + * @brief OSPI DQS Mode Disable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_DqsModeDisable(OSPI_Type *pOSPI) +{ + pOSPI->CTRL &= ~OSPI_CTRL_RWDS_EN_MASK; +} + +/** + * @brief OSPI DQS Lantency Enable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_DqsLatEnable(OSPI_Type *pOSPI) +{ + pOSPI->CTRL |= OSPI_CTRL_RWDS_LAT_MASK; +} + +/** + * @brief OSPI DQS Lantency Disable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_DqsLatDisable(OSPI_Type *pOSPI) +{ + pOSPI->CTRL &= ~OSPI_CTRL_RWDS_LAT_MASK; +} + +/** + * @brief OSPI DQS Out Enable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_DqsOutEnable(OSPI_Type *pOSPI) +{ + pOSPI->CTRL |= OSPI_CTRL_RWDS_OUT_MASK; +} + +/** + * @brief OSPI DQS Out Disable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_DqsOutDisable(OSPI_Type *pOSPI) +{ + pOSPI->CTRL &= ~OSPI_CTRL_RWDS_OUT_MASK; +} + +/** + * @brief Set OSPI Endian value. + * + * @param pOSPI the base address of the OSPI. + * @param eEndian Endian select value. + */ +LOCAL_INLINE void OSPI_HWA_EndianSelect(OSPI_Type *pOSPI,OSPI_EndianType eEndian) +{ + pOSPI->CTRL &= ~OSPI_CTRL_ENDIAN_MASK; + pOSPI->CTRL |= OSPI_CTRL_ENDIAN(eEndian); +} +/** + * @brief Set OSPI CTRL value, users should write the whole value to this register. + * + * @param pOSPI the base address of the OSPI. + * @param u32Value the value which will be written to the CTRL register. + */ +LOCAL_INLINE void OSPI_HWA_SetCtrlValue(OSPI_Type *pOSPI, uint32_t u32Value) +{ + pOSPI->CTRL = u32Value; +} + +/** + * @brief Read the OSPI CTRL register value for all. + * + * @param pOSPI pOSPI the base address of the OSPI. + * @return OSPI CTRL regsiter value. + */ +LOCAL_INLINE uint32_t OSPI_HWA_GetCtrlValue(OSPI_Type *pOSPI) +{ + return pOSPI->CTRL; +} +/** + * @brief Set CMD ID. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value Pointers of current CMD stored in LUT registers. + */ +LOCAL_INLINE void OSPI_HWA_SetCmdId(OSPI_Type *pOSPI, uint16_t u16Value) +{ + pOSPI->CMDC &= ~OSPI_CMDC_CMD_ID_MASK; + pOSPI->CMDC |= OSPI_CMDC_CMD_ID(u16Value); +} + +/** + * @brief Set CMD SIZE. + * + * @param pOSPI the base address of the OSPI. + * @param u16Value Transfer sizes of current CMD. + */ +LOCAL_INLINE void OSPI_HWA_SetCmdSize(OSPI_Type *pOSPI, uint16_t u16Value) +{ + pOSPI->CMDC &= ~OSPI_CMDC_CMD_SIZE_MASK; + pOSPI->CMDC |= OSPI_CMDC_CMD_SIZE(u16Value); +} + +/** + * @brief Set CMD id and size. + * + * @param pOSPI the base address of the OSPI. + * @param u8SeqId Pointers of current CMD stored in LUT registers. + * @param u16Size Transfer sizes of current CMD. + */ +LOCAL_INLINE void OSPI_HWA_SetCmdIdSize(OSPI_Type *pOSPI,uint8_t u8SeqId,uint16_t u16Size) +{ + pOSPI->CMDC = OSPI_CMDC_CMD_ID(u8SeqId)|OSPI_CMDC_CMD_SIZE(u16Size); +} +/** + * @brief Read the OSPI CMDC register value for all. + * + * @param pOSPI pOSPI the base address of the OSPI. + * @return OSPI CMDC regsiter value. + */ +LOCAL_INLINE uint32_t OSPI_HWA_GetCmdcValue(OSPI_Type *pOSPI) +{ + return pOSPI->CMDC; +} + +/** + * @brief Set Data Hold Time,This bit should only be valid in DDR mode. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value Data Hold Time. + */ +LOCAL_INLINE void OSPI_HWA_SetDataHoldTime(OSPI_Type *pOSPI, uint8_t u8Value) +{ + pOSPI->FLS_CFG &= ~OSPI_FLS_CFG_TDH_MASK; + pOSPI->FLS_CFG |= OSPI_FLS_CFG_TDH(u8Value); +} + +/** + * @brief Set CS Hold Time. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value CS Hold Time. + */ +LOCAL_INLINE void OSPI_HWA_SetCsHoldTime(OSPI_Type *pOSPI, uint8_t u8Value) +{ + pOSPI->FLS_CFG &= ~OSPI_FLS_CFG_TCSH_MASK; + pOSPI->FLS_CFG |= OSPI_FLS_CFG_TCSH(u8Value); +} + +/** + * @brief Set CS Setup Time. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value CS Setup Time. + */ +LOCAL_INLINE void OSPI_HWA_SetCsSetupTime(OSPI_Type *pOSPI, uint8_t u8Value) +{ + pOSPI->FLS_CFG &= ~OSPI_FLS_CFG_TCSS_MASK; + pOSPI->FLS_CFG |= OSPI_FLS_CFG_TCSS(u8Value); +} + +/** + * @brief Read the OSPI CMDC register value for all. + * + * @param pOSPI pOSPI the base address of the OSPI. + * @return OSPI CMDC regsiter value. + */ +LOCAL_INLINE uint32_t OSPI_HWA_GetFlashCfgValue(OSPI_Type *pOSPI) +{ + return pOSPI->FLS_CFG; +} + +/** + * @brief OSPI Enable internal reference clock + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_InternalRefclkEnable(OSPI_Type *pOSPI) +{ + pOSPI->SOC_CFG |= OSPI_SOC_CFG_CLK_EN_MASK; +} + +/** + * @brief OSPI Disable internal reference clock + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_InternalRefclkDisable(OSPI_Type *pOSPI) +{ + pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_CLK_EN_MASK; +} + +/** + * @brief OSPI Set Internal Reference Clock Divider. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value Internal Reference Clock Divider. + */ +LOCAL_INLINE void OSPI_HWA_InternalRefclkDiv(OSPI_Type *pOSPI, OSPI_ClockDivideType eClkDiv) +{ + pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_CLK_DIV_MASK; + pOSPI->SOC_CFG |= OSPI_SOC_CFG_CLK_DIV(eClkDiv); +} + +/** + * @brief OSPI PAD IBE Enable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_PadIbeEnable(OSPI_Type *pOSPI) +{ + pOSPI->SOC_CFG |= OSPI_SOC_CFG_IBE_EN_MASK; +} + +/** + * @brief OSPI PAD IBE Disable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_PadIbeDisable(OSPI_Type *pOSPI) +{ + pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_IBE_EN_MASK; +} + +/** + * @brief OSPI Select Internal Reference Clock Source. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value Internal Reference Clock Source. + */ +LOCAL_INLINE void OSPI_HWA_InternalRefclkSource(OSPI_Type *pOSPI, OSPI_ClockMuxType u8Value) +{ + pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_CLK_MUX_MASK; + pOSPI->SOC_CFG |= OSPI_SOC_CFG_CLK_MUX(u8Value); +} + +/** + * @brief OSPI Use inverted DQS + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_DqsInvertedEnable(OSPI_Type *pOSPI) +{ + pOSPI->SOC_CFG |= OSPI_SOC_CFG_RWDS_INV_MASK; +} + +/** + * @brief OSPI Not use inverted DQS + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_DqsInvertedDisable(OSPI_Type *pOSPI) +{ + pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_RWDS_INV_MASK; +} + +/** + * @brief OSPI Select DQS Source. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value DQS Source. + */ +LOCAL_INLINE void OSPI_HWA_DqsSource(OSPI_Type *pOSPI, OSPI_DqsSrcSelType u8Value) +{ + pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_RWDS_INV_MASK; + pOSPI->SOC_CFG |= OSPI_SOC_CFG_RWDS_MUX(u8Value); +} + +/** + * @brief OSPI OBE timing relax enable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_ObeTimRelaxEnable(OSPI_Type *pOSPI) +{ + pOSPI->SOC_CFG |= OSPI_SOC_CFG_OBE_RELAX_MASK; +} + +/** + * @brief OSPI OBE timing relax disable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_ObeTimRelaxDisable(OSPI_Type *pOSPI) +{ + pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_OBE_RELAX_MASK; +} + +/** + * @brief OSPI DDR Clock Enable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_DdrClkEnable(OSPI_Type *pOSPI) +{ + pOSPI->SOC_CFG |= OSPI_SOC_CFG_DDR_EN_MASK; +} + +/** + * @brief OSPI DDR Clock Disable + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_DdrClkDisable(OSPI_Type *pOSPI) +{ + pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_DDR_EN_MASK; +} + +/** + * @brief OSPI Switch Delay Line into DQS for timing. DQS will delay for DLLINE_CFG * Tcell. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value DQS Delay Line Cfg Value. + */ +LOCAL_INLINE void OSPI_HWA_CfgDelayLine(OSPI_Type *pOSPI, uint8_t u8Value) +{ + pOSPI->SOC_CFG &= ~OSPI_SOC_CFG_DLLINE_CFG_MASK; + pOSPI->SOC_CFG |= OSPI_SOC_CFG_DLLINE_CFG(u8Value); +} + +/** + * @brief Write the OSPI SOC CFG register. + * + * @param pOSPI pOSPI the base address of the OSPI. + * @param u32Value the value to be writen. + */ +LOCAL_INLINE void OSPI_HWA_SetSocCfgValue(OSPI_Type *pOSPI, uint32_t u32Value) +{ + pOSPI->SOC_CFG = u32Value; +} + +/** + * @brief Read the OSPI SOC CFG register value for all. + * + * @param pOSPI pOSPI the base address of the OSPI. + * @return OSPI SOC_CFG regsiter value. + */ +LOCAL_INLINE uint32_t OSPI_HWA_GetSocCfgValue(OSPI_Type *pOSPI) +{ + return pOSPI->SOC_CFG; +} + +/** + * @brief Set flash address, users should write the whole value to this register. + * + * @param pOSPI the base address of the OSPI. + * @param u32Value the value which will be written to the FLS_AR register. + */ +LOCAL_INLINE void OSPI_HWA_SetFlashAddr(OSPI_Type *pOSPI, uint32_t u32Value) +{ + pOSPI->FLS_AR = u32Value; +} + +/** + * @brief Set flash addressable mode. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value the value of addressable mode. + */ +LOCAL_INLINE void OSPI_HWA_SetFlashAddrMode(OSPI_Type *pOSPI, uint8_t u8Value) +{ + pOSPI->FLS_CAR &= ~OSPI_FLS_CAR_WA_MASK; + pOSPI->FLS_CAR |= OSPI_FLS_CAR_WA(u8Value); +} + +/** + * @brief Set Column Address Space. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value the value of Column Address Space. + */ +LOCAL_INLINE void OSPI_HWA_SetColAddrSpace(OSPI_Type *pOSPI, uint8_t u8Value) +{ + pOSPI->FLS_CAR &= ~OSPI_FLS_CAR_CAS_MASK; + pOSPI->FLS_CAR |= OSPI_FLS_CAR_CAS(u8Value); +} + +/** + * @brief Set Sample delay clock cycle. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value the value of Sample Delay clock cycle. + */ +LOCAL_INLINE void OSPI_HWA_SetSampleDlyClkCycle(OSPI_Type *pOSPI, uint8_t u8Value) +{ + pOSPI->SAMP_CTRL &= ~OSPI_SAMP_CTRL_DLY_MASK; + pOSPI->SAMP_CTRL |= OSPI_SAMP_CTRL_DLY(u8Value); +} + +/** + * @brief Selects reference clock edge for valid sampling phase. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value the value of reference clock edge. + */ +LOCAL_INLINE void OSPI_HWA_SelectRefClkEdge(OSPI_Type *pOSPI, uint8_t u8Value) +{ + pOSPI->SAMP_CTRL &= ~OSPI_SAMP_CTRL_PHS_MASK; + pOSPI->SAMP_CTRL |= OSPI_SAMP_CTRL_PHS(u8Value); +} + +/** + * @brief Read RX FIFO Counter,Indicates the current RX FIFO read pointer; + * Automatically increases when RX FIFO pops an event. + * + * @param pOSPI pOSPI the base address of the OSPI. + * @return RX FIFO Counter. + */ +LOCAL_INLINE uint16_t OSPI_HWA_GetRxFifoCnt(OSPI_Type *pOSPI) +{ + return (uint16_t)((pOSPI->RFSR&OSPI_RFSR_RFCTR_MASK)>>OSPI_RFSR_RFCTR_SHIFT); +} + +/** + * @brief Read RX FIFO Fill Level,Indicates how many words are available in RX FIFO. + * + * @param pOSPI pOSPI the base address of the OSPI. + * @return RX FIFO Fill Level. + */ +LOCAL_INLINE uint8_t OSPI_HWA_GetRxFifoFillLevel(OSPI_Type *pOSPI) +{ + return (uint8_t)((pOSPI->RFSR&OSPI_RFSR_RFFL_MASK)>>OSPI_RFSR_RFFL_SHIFT); +} + +/** + * @brief Set RX FIFO Watermark, + * Indicates how many valid entries will trigger a readout action. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value the value of RX FIFO Watermark. + */ +LOCAL_INLINE void OSPI_HWA_SetRxFifoWaterMark(OSPI_Type *pOSPI, uint8_t u8Value) +{ + pOSPI->RF_CFG &= ~OSPI_RF_CFG_WMRK_MASK; + pOSPI->RF_CFG |= OSPI_RF_CFG_WMRK(u8Value); +} + +/** + * @brief Read TX FIFO Counter,Indicates the current TX FIFO stored data pointer; + * Automatically increases when TX FIFO pops an event. + * + * @param pOSPI pOSPI the base address of the OSPI. + * @return TX FIFO Counter. + */ +LOCAL_INLINE uint16_t OSPI_HWA_GetTxFifoCnt(OSPI_Type *pOSPI) +{ + return (uint16_t)((pOSPI->TFSR&OSPI_TFSR_TFCTR_MASK)>>OSPI_TFSR_TFCTR_SHIFT); +} + +/** + * @brief Read TX FIFO Fill Level,Indicates how many words are available in TX FIFO. + * + * @param pOSPI pOSPI the base address of the OSPI. + * @return TX FIFO Fill Level. + */ +LOCAL_INLINE uint8_t OSPI_HWA_GetTxFifoFillLevel(OSPI_Type *pOSPI) +{ + return (uint8_t)((pOSPI->TFSR&OSPI_TFSR_TFFL_MASK)>>OSPI_TFSR_TFFL_SHIFT); +} + +/** + * @brief Get transmit fifo register address. + * + * @param pOSPI the base address of the OSPI. + * @return Transmit fifo register address. + */ +LOCAL_INLINE uint32_t OSPI_HWA_GetTFDRAddr(OSPI_Type *pOSPI) +{ + return (uint32_t)&pOSPI->TFDR; +} + +/** + * @brief Writing this register will trigger data entry of TX FIFO. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value the value of tx data. + */ +LOCAL_INLINE void OSPI_HWA_WriteTxData(OSPI_Type *pOSPI, uint32_t u32Value) +{ + pOSPI->TFDR = u32Value; +} + +/** + * @brief Set TX FIFO Watermark, + * Indicates how many valid entries will trigger a transmit action. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value the value of TX FIFO Watermark. + */ +LOCAL_INLINE void OSPI_HWA_SetTxFifoWaterMark(OSPI_Type *pOSPI, uint8_t u8Value) +{ + pOSPI->TF_CFG &= ~OSPI_TF_CFG_WMRK_MASK; + pOSPI->TF_CFG |= OSPI_TF_CFG_WMRK(u8Value); +} + +/** + * @brief Read status register. + * + * @param pOSPI pOSPI the base address of the OSPI. + * @return Status register. + */ +LOCAL_INLINE uint32_t OSPI_HWA_GetStatus(OSPI_Type *pOSPI) +{ + return pOSPI->STATUS&OSPI_STATUS_MASK; +} + +/** + * @brief Read flag register. + * + * @param pOSPI pOSPI the base address of the OSPI. + * @return flag register. + */ +LOCAL_INLINE uint32_t OSPI_HWA_GetFlag(OSPI_Type *pOSPI) +{ + return pOSPI->FLAG&OSPI_FLAG_MASK; +} + +/** + * @brief Writing this register will clear ospi flag. + * + * @param pOSPI the base address of the OSPI. + * @param u8Value the value of flag to be cleared. + */ +LOCAL_INLINE void OSPI_HWA_ClearFlag(OSPI_Type *pOSPI, uint32_t u32Value) +{ + pOSPI->FLAG = (u32Value&OSPI_FLAG_MASK); +} + +/** + * @brief Set the OSPI IND_EN register value for enable or disable interrupts&DMA. + * + * @param pOSPI the base address of the OSPI. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void OSPI_HWA_SetIntDmasEnableReg(OSPI_Type *pOSPI, uint32_t u32Value) +{ + pOSPI->IND_EN = (u32Value&OSPI_IND_EN_MASK); +} + +/** + * @brief Set the OSPI Rx DMA mode. + * + * @param pOSPI the base address of the OSPI. + * @param u8Enable open or close rx dma mode. + */ +LOCAL_INLINE void OSPI_HWA_SetRxDMA(OSPI_Type *pOSPI, uint8_t u8Enable) +{ + if (u8Enable) + { + pOSPI->IND_EN |= OSPI_IND_EN_RFDDRE_MASK; + } + else + { + pOSPI->IND_EN &= ~OSPI_IND_EN_RFDDRE_MASK; + } +} + +/** + * @brief Set the OSPI Tx DMA mode. + * + * @param pOSPI the base address of the OSPI. + * @param u8Enable open or close tx dma mode. + */ +LOCAL_INLINE void OSPI_HWA_SetTxDMA(OSPI_Type *pOSPI, uint8_t u8Enable) +{ + if (u8Enable) + { + pOSPI->IND_EN |= OSPI_IND_EN_TFFDRE_MASK; + } + else + { + pOSPI->IND_EN &= ~OSPI_IND_EN_TFFDRE_MASK; + } +} + +/** + * @brief Set flash top address register. + * + * @param pOSPI the base address of the OSPI. + * @param Top Address of Flash Device. + */ +LOCAL_INLINE void OSPI_HWA_SetFlashTopAddr(OSPI_Type *pOSPI, uint32_t u32Value) +{ + pOSPI->FLS_TAR = (u32Value&OSPI_FLS_TAR_MASK); +} + +/** + * @brief Get receive fifo register address. + * + * @param pOSPI the base address of the OSPI. + * @return Receive fifo register address. + */ +LOCAL_INLINE uint32_t OSPI_HWA_GetRFDRAddr(OSPI_Type *pOSPI) +{ + return (uint32_t)pOSPI->RFDR; +} + +/** + * @brief Read receive fifo data register. + * + * @param pOSPI the base address of the OSPI. + * @param u8Idx Fifo index to be read. + * @return Receive fifo data register. + */ +LOCAL_INLINE uint32_t OSPI_HWA_ReadRcvFifoReg(OSPI_Type *pOSPI,uint8_t u8Idx) +{ + return pOSPI->RFDR[u8Idx]; +} + +/** + * @brief Read secondary receive fifo data register. + * + * @param pOSPI the base address of the OSPI. + * @return Secondary receive fifo data register. + */ +LOCAL_INLINE uint32_t OSPI_HWA_ReadSecondaryRcvFifoReg(OSPI_Type *pOSPI) +{ + return pOSPI->RFD2R; +} + +/** + * @brief Write LUT Key register. + * + * @param pOSPI the base address of the OSPI. + * @param u32Value LUT Key Value to be writed. + */ +LOCAL_INLINE void OSPI_HWA_WriteLutKey(OSPI_Type *pOSPI, uint32_t u32Value) +{ + pOSPI->LUT_KEY = u32Value; +} + +/** + * @brief Read LUT Key register. + * + * @param pOSPI the base address of the OSPI. + * @return LUT Key Value. + */ +LOCAL_INLINE uint32_t OSPI_HWA_ReadLutKey(OSPI_Type *pOSPI) +{ + return pOSPI->LUT_KEY; +} + +/** + * @brief Lock the LUT. + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_LockLut(OSPI_Type *pOSPI) +{ + pOSPI->LUT_CFG = OSPI_LUT_CFG_LOCK_MASK; +} + +/** + * @brief Unlock the LUT. + * + * @param pOSPI the base address of the OSPI. + */ +LOCAL_INLINE void OSPI_HWA_UnlockLut(OSPI_Type *pOSPI) +{ + pOSPI->LUT_CFG = OSPI_LUT_CFG_UNLOCK_MASK; +} + +/** + * @brief Write lookup table register. + * + * @param pOSPI the base address of the OSPI. + * @param u8Idx Index of LUT. + * @param u32Value LUT Value to be writed. + */ +LOCAL_INLINE void OSPI_HWA_WriteLut(OSPI_Type *pOSPI, uint8_t u8Idx, uint32_t u32Value) +{ + pOSPI->LUT[u8Idx] = u32Value; +} + +#endif /* #if OSPI_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_OSPI_H_ */ diff --git a/Inc/HwA_overlay.h b/Inc/HwA_overlay.h new file mode 100644 index 0000000..835a0e9 --- /dev/null +++ b/Inc/HwA_overlay.h @@ -0,0 +1,324 @@ +/** + * @file HwA_overlay.h + * @author Flagchip + * @brief FC4xxx Overlay hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip038 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip038 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_OVERLAY_H_ +#define _HWA_OVERLAY_H_ + +#include "device_header.h" + +#if AHB_OVERLAY_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_overlay HwA_overlay + * @ingroup module_driver_overlay + * @{ + */ + + +/** @brief Overlay Region Count */ +#define OVERLYA_REGION_CNT 3U + +/** @brief FAR source address */ +#define OVERLAY_FAR_SRC 0x08000000U + +/** @brief FAR max size */ +#define OVERLAY_FAR_SIZE_MAX 0x2000000U +/** @brief FAR size align */ +#define OVERLAY_FAR_SIZE_ALIGN 0x10000U +/** @brief FAR size max mask **/ +#define OVERLAY_FAR_SIZE_MASK 0xFFFFU + +#if AHB_OVERLAY_EN_UNLOCK == STD_ON +#define OVERLAY_EN_UNLOCK_KEY 0xECFEAA55 +#endif + +/** + * @brief FAR Size + * + */ +typedef enum +{ + OVERLAY_FARUINTSIZE_64KB = 0x10000, /**< OVERLAY_FARUINTSIZE_64KB, remapping far uint size to 64KB */ +}OVERLAY_FARSizeType; + +/** + * @brief enable overlay global switch + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayEnable(void) +{ +#if AHB_OVERLAY_EN_UNLOCK == STD_ON + AHB_OVERLAY->GLOBAL_EN = OVERLAY_EN_UNLOCK_KEY; +#endif + AHB_OVERLAY->GLOBAL_EN |= AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK; +} + +/** + * @brief disable overlay global switch + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayDisable(void) +{ +#if AHB_OVERLAY_EN_UNLOCK == STD_ON + AHB_OVERLAY->GLOBAL_EN = OVERLAY_EN_UNLOCK_KEY; +#endif + AHB_OVERLAY->GLOBAL_EN &= ~((uint32_t)AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK); +} + +/** + * @brief enable far global switch + * + */ +LOCAL_INLINE void OVERLAY_HWA_FAREnable(void) +{ +#if AHB_OVERLAY_EN_UNLOCK == STD_ON + AHB_OVERLAY->GLOBAL_EN = OVERLAY_EN_UNLOCK_KEY; +#endif + AHB_OVERLAY->GLOBAL_EN |= AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK; +} + +/** + * @brief disable far global switch + * + */ +LOCAL_INLINE void OVERLAY_HWA_FARDisable(void) +{ +#if AHB_OVERLAY_EN_UNLOCK == STD_ON + AHB_OVERLAY->GLOBAL_EN = OVERLAY_EN_UNLOCK_KEY; +#endif + AHB_OVERLAY->GLOBAL_EN &= ~((uint32_t)AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK); +} + +/** + * @brief enable overlay region 0 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion0Enable(void) +{ + AHB_OVERLAY->REGION_0_EN |= AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK; +} + +/** + * @brief disable overlay region 0 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion0Disable(void) +{ + AHB_OVERLAY->REGION_0_EN &= ~((uint32_t)AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK); +} + +/** + * @brief Set Overlay Region 0 Source + * + * @param u32Src Source address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Src(uint32_t u32Src) +{ + AHB_OVERLAY->REGION_0_SRC = AHB_OVERLAY_REGION_0_SRC_REGION0_SRC(u32Src); +} + +/** + * @brief Set Overlay Region 0 Destination + * + * @param u32Dst Destination address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Dst(uint32_t u32Dst) +{ + AHB_OVERLAY->REGION_0_DST = AHB_OVERLAY_REGION_0_DST_REGION0_DST(u32Dst); +} + +/** + * @brief Set Overlay Region 0 Size + * + * @param eSize size + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Size(OVERLAY_OverlaySizeType eSize) +{ + AHB_OVERLAY->REGION_0_SIZE = AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE((uint32_t)eSize); +} + + + +/** + * @brief enable overlay region 1 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion1Enable(void) +{ + AHB_OVERLAY->REGION_1_EN |= AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK; +} + +/** + * @brief disable overlay region 1 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion1Disable(void) +{ + AHB_OVERLAY->REGION_1_EN &= ~((uint32_t)AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK); +} + +/** + * @brief Set Overlay Region 1 Source + * + * @param u32Src Source address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Src(uint32_t u32Src) +{ + AHB_OVERLAY->REGION_1_SRC = AHB_OVERLAY_REGION_1_SRC_REGION1_SRC(u32Src); +} + +/** + * @brief Set Overlay Region 1 Destination + * + * @param u32Dst Destination address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Dst(uint32_t u32Dst) +{ + AHB_OVERLAY->REGION_1_DST = AHB_OVERLAY_REGION_1_DST_REGION1_DST(u32Dst); +} + +/** + * @brief Set Overlay Region 1 Size + * + * @param eSize size + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Size(OVERLAY_OverlaySizeType eSize) +{ + AHB_OVERLAY->REGION_1_SIZE = AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE((uint32_t)eSize); +} + + +/** + * @brief enable overlay region 2 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion2Enable(void) +{ + AHB_OVERLAY->REGION_2_EN |= AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK; +} + +/** + * @brief disable overlay region 2 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion2Disable(void) +{ + AHB_OVERLAY->REGION_2_EN &= ~((uint32_t)AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK); +} + +/** + * @brief Set Overlay Region 2 Source + * + * @param u32Src Source address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Src(uint32_t u32Src) +{ + AHB_OVERLAY->REGION_2_SRC = AHB_OVERLAY_REGION_2_SRC_REGION2_SRC(u32Src); +} + +/** + * @brief Set Overlay Region 2 Destination + * + * @param u32Dst Destination address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Dst(uint32_t u32Dst) +{ + AHB_OVERLAY->REGION_2_DST = AHB_OVERLAY_REGION_2_DST_REGION2_DST(u32Dst); +} + +/** + * @brief Set Overlay Region 2 Size + * + * @param eSize size + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Size(OVERLAY_OverlaySizeType eSize) +{ + AHB_OVERLAY->REGION_2_SIZE = AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE((uint32_t)eSize); +} + + + + +/** + * @brief Set Far Destination + * + * @param u32Dst Destination address, must pflash + */ +LOCAL_INLINE void OVERLAY_HWA_SetFarDst(uint32_t u32Dst) +{ + AHB_OVERLAY->FAR_DST = AHB_OVERLAY_FAR_DST_FAR_DST_ADDR(u32Dst); +} + +/** + * @brief Set Far Size + * + * @param u32Size size=(u32Size+1)*64KB + */ +LOCAL_INLINE void OVERLAY_HWA_SetFarSize(uint32_t u32Size) +{ + AHB_OVERLAY->FAR_SIZE = AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL(u32Size); +} + + +/** + * @brief enable error interrupt + * + */ +LOCAL_INLINE void OVERLAY_HWA_ErrorInterruptEnable(void) +{ + AHB_OVERLAY->INTR_EN |= AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK; +} + +/** + * @brief disable error interrupt + * + */ +LOCAL_INLINE void OVERLAY_HWA_ErrorInterruptDisable(void) +{ + AHB_OVERLAY->INTR_EN &= ~((uint32_t)AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK); +} + +/** + * @brief get error flag + * + */ +LOCAL_INLINE uint32 OVERLAY_HWA_GetErrorFlag(void) +{ + return (AHB_OVERLAY->INTR_FLAG & AHB_OVERLAY_INTR_FLAG_MASK); +} + +/** + * @brief clear error flag + * + */ +LOCAL_INLINE uint32 OVERLAY_HWA_ClrErrorFlag(uint32_t u32ClrBits) +{ + return AHB_OVERLAY->INTR_CLR |= AHB_OVERLAY_INTR_FLAG_MASK & u32ClrBits; +} + + +/** @}*/ + +#endif /* #if AHB_OVERLAY_INSTANCE_COUNT > 0U */ + +#endif /* _HWA_OVERLAY_H_ */ diff --git a/Inc/HwA_pmc.h b/Inc/HwA_pmc.h new file mode 100644 index 0000000..83fdcef --- /dev/null +++ b/Inc/HwA_pmc.h @@ -0,0 +1,122 @@ +/** + * @file HwA_pmc.h + * @author flagchip + * @brief PMC register API + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip095 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip095 N/A Change version and release + ******************************************************************************** */ +#ifndef HWA_INCLUDE_HWA_PMC_H_ +#define HWA_INCLUDE_HWA_PMC_H_ +#include "device_header.h" + +#if PMC_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_pmc + * @ingroup module_driver_pmc + * @{ + */ + +/** + * @brief get PMC LVCSR register + * + * @return uint32_t LVCSR register value + */ +LOCAL_INLINE uint32_t PMC_HWA_GetLVSCR(void) +{ + return (uint32)(PMC->LVSCR); +} + +/** + * @brief set PMC LVCSR register. + * + * This function configures the PMC LVCSR registe. + * + * @param u32Val Set PMC LVCSR register value. + */ +LOCAL_INLINE void PMC_HWA_SetLVSCR(uint32_t u32Val) +{ + PMC->LVSCR = u32Val; +} + +/** + * @brief get PMC CONFIG register + * + * @return uint32_t CONFIG register value + */ +LOCAL_INLINE uint32_t PMC_HWA_GetCONFIG(void) +{ + return (uint32)(PMC->CONFIG); +} + +/** + * @brief set PMC CONFIG register. + * + * This function configures the PMC CONFIG registe. + * + * @param u32LVSCRValue Set PMC CONFIG register value. + */ +LOCAL_INLINE void PMC_HWA_SetCONFIG(uint32_t u32Val) +{ + PMC->CONFIG = u32Val; +} + +/** + * @brief HWA Disable PMC interrupt + * + * @param the parameter of interrupt flag + */ +LOCAL_INLINE void PMC_HWA_DisableInterrupt(uint32 u32Val) +{ + PMC->CONFIG &= (~u32Val); +} + +/** + * @brief HWA Enable PMC interrupt + * + * @param the parameter of interrupt flag + */ +LOCAL_INLINE void Pmc_HWA_EnableInterrupt(uint32 u32Val) +{ + PMC->CONFIG |= u32Val; +} + +/** + * @brief Return Low Voltage Detect Interrupt Enable Flag + * + * @return 0: Low Voltage Detect Interrupt Disabled; 1: Low Voltage Detect Interrupt Enabled + */ +LOCAL_INLINE bool PMC_ReadLVDInterruptFlag(void) +{ + return (bool) ((PMC->CONFIG & PMC_CONFIG_LVD_IE_MASK) >> PMC_CONFIG_LVD_IE_SHIFT); +} + +/** + * @brief Return High Voltage Detect Interrupt Enable Flag + * + * @return 0: High Voltage Detect Interrupt Disabled; 1: High Voltage Detect Interrupt Enabled + */ +LOCAL_INLINE bool PMC_ReadHVDInterruptFlag(void) +{ + return (bool) ((PMC->CONFIG & PMC_CONFIG_HVD_IE_MASK) >> PMC_CONFIG_HVD_IE_SHIFT); +} + +/** @}*/ + +#endif /* #if PMC_INSTANCE_COUNT > 0U */ + +#endif /* HWA_INCLUDE_HWA_PMC_H_ */ diff --git a/Inc/HwA_port.h b/Inc/HwA_port.h new file mode 100644 index 0000000..d551b7c --- /dev/null +++ b/Inc/HwA_port.h @@ -0,0 +1,282 @@ +/** + * @file HwA_port.h + * @author Flagchip + * @brief PORT hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip071 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip071 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_PORT_H_ +#define _HWA_PORT_H_ + +#include "device_header.h" + +#if PORT_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_port HwA_port + * @ingroup module_driver_port + * @{ + */ + +/********* Local inline function ************/ +/** + * @brief Configure pin + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u32PcrReg Pin PCR register value + */ +LOCAL_INLINE void PORT_HWA_ConfigPin(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32PcrReg) +{ + pPort->PCR[u8Pin] = u32PcrReg; +} + + +/** + * @brief Read pin interrupt flag + * + * @param pPort Port instance + * @param u8Pin Pin number + * @return interrupt flag value + */ +LOCAL_INLINE uint32_t PORT_HWA_ReadPinInterruptFlag(PORT_Type *pPort, uint8_t u8Pin) +{ + return pPort->PCR[u8Pin] & (uint32_t)PORT_PCR_ISF_MASK; +} + + +/** + * @brief Set pin multiplexing + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param Port_PinMuxType Pin MXU configuration value + */ +LOCAL_INLINE void PORT_HWA_SetPinMux(PORT_Type *pPort, uint8_t u8Pin, Port_PinMuxType u32PinMux) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_MUX_MASK) | PORT_PCR_MUX(u32PinMux.u32PortPinMode)); +} + +/** + * @brief Set Pin Emergency Stop + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param bEnable Enable or Disable Emergency Stop of this Pin + */ +LOCAL_INLINE void PORT_HWA_SetPinEmgcyStop(PORT_Type *pPort, uint8_t u8Pin, bool bEnable) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = (u32TempRegVal & (~ (uint32_t)PORT_PCR_ESTOP_MASK)) | PORT_PCR_ESTOP(bEnable); +} + +/** + * @brief Set pin interrupt mode + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u32PinIrqc Pin IRQC configuration value + */ +LOCAL_INLINE void PORT_HWA_SetPinInterruptMode(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32PinIrqc) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(u32PinIrqc)); +} + +/** + * @brief Set pin pull enable + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u8PeValue Pin PE configuration value(1/0) + */ +LOCAL_INLINE void PORT_HWA_SetPinPullEnable(PORT_Type *pPort, uint8_t u8Pin, uint8_t u8PeValue) +{ + if (u8PeValue) + { + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_PE_MASK; + } + else + { + pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_PE_MASK; + } +} + +/** + * @brief Set pin pull mode + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u8PsValue Pin PS configuration value(1/0) + */ +LOCAL_INLINE void PORT_HWA_SetPinPullMode(PORT_Type *pPort, uint8_t u8Pin, uint8_t u8PsValue) +{ + if (u8PsValue) + { + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_PS_MASK; + } + else + { + pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_PS_MASK; + } +} + +/** + * @brief Set pin drive strength + * + * @param pPort Port instance + * @param u8Pin Pin number + * @note only hs PAD use this bit + */ +LOCAL_INLINE void PORT_HWA_SetPinDriveStrength(PORT_Type *pPort, uint8_t u8Pin) +{ + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_DSE0_MASK; +} + +/** + * @brief Set pin passive filter enable + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u8PfeValue Pin PFE configuration value(1/0) + */ +LOCAL_INLINE void PORT_HWA_SetPinPassiveFilterEnable(PORT_Type *pPort, uint8_t u8Pin, uint8_t u8PfeValue) +{ + if (u8PfeValue) + { + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_PFE_MASK; + } + else + { + pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_PFE_MASK; + } +} + +/** + * @brief Configure port digital filter + * + * @param pPort Port instance + * @param u32RegValue Enable bit,0-31 bit indicate pin 0-31 + */ +LOCAL_INLINE void PORT_HWA_ConfigDigitalFilter(PORT_Type *pPort, uint32_t u32RegValue) +{ + pPort->DFER = u32RegValue; +} + +/** + * @brief Set port digital filter enable + * + * @param pPort Port instance + * @param u8RegBit DFER register bit + */ +LOCAL_INLINE void PORT_HWA_SetDigitalFilterEnable(PORT_Type *pPort, uint8_t u8RegBit) +{ + pPort->DFER |= (uint32_t)1 << u8RegBit; +} + +/** + * @brief Set port digital filter clock source + * + * @param pPort Port instance + * @param eClkSrc Digital filter clock source + */ +LOCAL_INLINE void PORT_HWA_SetDigitalFilterClkSrc(PORT_Type *pPort) +{ + pPort->DFCR |= 1U; +} + +/** + * @brief Configure digital filter width + * @param pPort Port instance + * @param u32FilterWidth Digital filter length value,range:0-31 + */ +LOCAL_INLINE void PORT_HWA_ConfigDigitalFilterWidth(PORT_Type *pPort, uint32_t u32FilterWidth) +{ + pPort->DFWR = PORT_DFWR_FILT(u32FilterWidth); +} + +/** + * @brief Clear pin interrupt mode + * + * @param pPort Port instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void PORT_HWA_ClearPinInterruptMode(PORT_Type *pPort, uint8_t u8Pin) +{ + pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_IRQC_MASK; +} + +/** + * @brief Clear pin interrupt flag + * + * @param pPort Port instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void PORT_HWA_ClearPinInterruptFlag(PORT_Type *pPort, uint8_t u8Pin) +{ + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_ISF_MASK; +} + +/** + * @brief CLear port digital filter enable + * + * @param pPort Port instance + */ +LOCAL_INLINE void PORT_HWA_ClearDigitalFilterEnable(PORT_Type *pPort) +{ + pPort->DFER = (uint32_t)0U; +} + +/** + * @brief Clear port digital filter enable for specific pin + * + * @param pPort Port instance + * @param u8RegBit DFER register bit + */ +LOCAL_INLINE void PORT_HWA_ClearDigitalFilterPin(PORT_Type *pPort, uint8_t u8RegBit) +{ + pPort->DFER &= (uint32_t)~((uint32_t)1 << u8RegBit); +} + +/** + * @brief Clear port digital filter clock source + * + * @param pPort Port instance + */ +LOCAL_INLINE void PORT_HWA_ClearDigitalFilterClkSrc(PORT_Type *pPort) +{ + pPort->DFCR &= ~(uint32_t)PORT_DFCR_CS_MASK; +} + +/** + * @brief Clear port digital filter width + * + * @param pPort Port instance + */ +LOCAL_INLINE void PORT_HWA_ClearDigitalFilterWidth(PORT_Type *pPort) +{ + pPort->DFWR &= ~(uint32_t)PORT_DFWR_FILT_MASK; +} + +/** @}*/ + +#endif + +#endif /* #ifndef _HWA_PORT_H_ */ diff --git a/Inc/HwA_ptimer.h b/Inc/HwA_ptimer.h new file mode 100644 index 0000000..5e71588 --- /dev/null +++ b/Inc/HwA_ptimer.h @@ -0,0 +1,722 @@ +/** + * @file HwA_ptimer.h + * @author flagchip + * @brief Hardware access layer for PTIMER + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip030 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_PTIMER_H_ +#define _HWA_PTIMER_H_ + +#include "device_header.h" + +#if PTIMER_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_ptimer HwA_ptimer + * @ingroup module_driver_ptimer + * @{ + */ + +/** + * @brief Ptimer value load mode + * + * Some Ptimer registers are buffered and will only take effect after called + * PTIMER_LoadValue() function, and this option selects when the buffered configurations + * will tack effect after PTIMER_LoadValue() is called. + * + */ +typedef enum +{ + PTIMER_LOAD_VAL_IMMEDIATELY = 0U, + /*!< Loaded immediately after load operation. */ + PTIMER_LOAD_VAL_AT_MODULO_COUNTER = 1U, + /*!< Loaded when counter hits the max count after load operation. */ + PTIMER_LOAD_VAL_AT_NEXT_TRIGGER = 2U, + /*!< Loaded when detecting an input trigger after load operation. */ + PTIMER_LOAD_VAL_AT_MODULO_COUNTER_OR_NEXT_TRIGGER = 3U + /*!< Loaded when counter hits the max count or detecting an input trigger after load operation. */ +} PTIMER_LoadValueModeType; + +/** + * @brief Ptimer clock pre-divider factor + * + * The Ptimer clock source is from core clock and the divider is a multiplication of + * PTIMER_ClockPreDividerType and PTIMER_ClockPreDivMultiplyFactorType, and thus: + * Freq = Core_Freq / (PTIMER_ClockPreDividerType * PTIMER_ClockPreDivMultiplyFactorType) + * + */ +typedef enum +{ + PTIMER_PRE_DIVIDE_BY_1 = 0U, + PTIMER_PRE_DIVIDE_BY_2 = 1U, + PTIMER_PRE_DIVIDE_BY_4 = 2U, + PTIMER_PRE_DIVIDE_BY_8 = 3U, + PTIMER_PRE_DIVIDE_BY_16 = 4U, + PTIMER_PRE_DIVIDE_BY_32 = 5U, + PTIMER_PRE_DIVIDE_BY_64 = 6U, + PTIMER_PRE_DIVIDE_BY_128 = 7U +} PTIMER_ClockPreDividerType; + +/** + * @brief Ptimer clock divider multiplication factor + * + * The Ptimer clock source is from core clock and the divider is a multiplication of + * PTIMER_ClockPreDividerType and PTIMER_ClockPreDivMultiplyFactorType, and thus: + * Freq = Core_Freq / (PTIMER_ClockPreDividerType * PTIMER_ClockPreDivMultiplyFactorType) + * + */ +typedef enum +{ + PTIMER_PRE_DIVIDER_MULTIPLY_BY_1 = 0U, + PTIMER_PRE_DIVIDER_MULTIPLY_BY_10 = 1U, + PTIMER_PRE_DIVIDER_MULTIPLY_BY_20 = 2U, + PTIMER_PRE_DIVIDER_MULTIPLY_BY_40 = 3U +} PTIMER_ClockPreDivMultiplyFactorType; + +/** + * @brief Ptimer trigger source + * + */ +typedef enum +{ + PTIMER_TRGSRC_TRGSEL = 0x00U, /*!< Ptimer trigger source from TrgSel */ + PTIMER_TRGSRC_SW = 0x0FU /*!< Ptimer trigger source from software trigger*/ +} PTIMER_TrgSrcType; + +#if PTIMER_SUPPORT_DEBUG_MODE +/** + * @brief Disable debug mode of Ptimer + * + * @param pPtimer the base address of the pPtimer instance + * @param disable true. disable debug mode fasle enable debug mode + */ +LOCAL_INLINE void PTIMER_HWA_DisableDebugMode(PTIMER_Type *pPtimer, bool disable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & (~PTIMER_STATUS_CTRL_DBG_DISEN_MASK)) | PTIMER_STATUS_CTRL_DBG_DISEN(disable); +} +#endif + +/** + * @brief Get the STATUS_CTRL register value + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE uint32_t PTIMER_HWA_GetStatusCtrl(const PTIMER_Type *const pPtimer) +{ + return pPtimer->STATUS_CTRL; +} + +/** + * @brief Set the STATUS_CTRL register value + * + * @param pPtimer the base address of the Ptimer instance + * @param u32CfgValue the register value to set + */ +LOCAL_INLINE void PTIMER_HWA_SetStatusCtrl(PTIMER_Type *const pPtimer, uint32_t u32CfgValue) +{ + pPtimer->STATUS_CTRL = u32CfgValue; +} + +/** + * @brief Get the load mode of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return PTIMER_LoadValueModeType the load mode of the Ptimer instance + */ +LOCAL_INLINE PTIMER_LoadValueModeType PTIMER_HWA_GetLoadMode(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_LDMODE_MASK) >> PTIMER_STATUS_CTRL_LDMODE_SHIFT; + return (PTIMER_LoadValueModeType)u32TmpVal; +} + +/** + * @brief Set the load mode of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param eLoadMode the load mode of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetLoadMode(PTIMER_Type *const pPtimer, PTIMER_LoadValueModeType eLoadMode) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_LDMODE_MASK) | PTIMER_STATUS_CTRL_LDMODE(eLoadMode); +} + +/** + * @brief Get whether sequence error interrupt is enabled + * + * @param pPtimer the base address of the Ptimer instance + * @return true sequence error interrupt is enabled + * @return false sequence error interrupt is disabled + */ +LOCAL_INLINE bool PTIMER_HWA_GetSeqErrIntEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_SERR_INTEN_MASK) >> PTIMER_STATUS_CTRL_SERR_INTEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable sequence error interrupt + * + * @param pPtimer the base address of the Ptimer instance + * @param bEnable whether to enable sequence error interrupt + */ +LOCAL_INLINE void PTIMER_HWA_SetSeqErrIntEnableFlag(PTIMER_Type *const pPtimer, bool bEnable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_SERR_INTEN_MASK) | PTIMER_STATUS_CTRL_SERR_INTEN( + bEnable ? 1U : 0U); +} + +/** + * @brief Generate software trigger signal for Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_GenerateSwTrigger(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_SWTRG_MASK; +} + +/** + * @brief Get whether DMA is enabled for the Ptimer insstance + * + * @param pPtimer the base address of the Ptimer instance + * @return true DMA is enabled + * @return false DMA is disabled + */ +LOCAL_INLINE bool PTIMER_HWA_GetDMAEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_DMAEN_MASK) >> PTIMER_STATUS_CTRL_DMAEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable Ptimer DMA + * + * @param pPtimer the base address of the Ptimer instance + * @param bEnable whether to enable DMA for the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetDMAEnableFlag(PTIMER_Type *const pPtimer, bool bEnable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_DMAEN_MASK) | PTIMER_STATUS_CTRL_DMAEN(bEnable ? 1U : 0U); +} + +/** + * @brief Get the predivider value of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return PTIMER_ClockPreDividerType the predivider of the Ptimer instance + */ +LOCAL_INLINE PTIMER_ClockPreDividerType PTIMER_HWA_GetDivPrescaler(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_PRESCALER_MASK) >> PTIMER_STATUS_CTRL_PRESCALER_SHIFT; + return (PTIMER_ClockPreDividerType)u32TmpVal; +} + +/** + * @brief Set the predivider value of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param eDivPrescaler the predivider of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetDivPrescaler(PTIMER_Type *const pPtimer, PTIMER_ClockPreDividerType eDivPrescaler) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_PRESCALER_MASK) | PTIMER_STATUS_CTRL_PRESCALER( + eDivPrescaler); +} + +/** + * @brief Get the trigger source of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return PTIMER_TRGSRC_TRGSEL the trigger source is from TrgSel + * @return PTIMER_TRGSRC_SW the trigger source is from software + */ +LOCAL_INLINE PTIMER_TrgSrcType PTIMER_HWA_GetTriggerSource(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_TRGSEL_MASK) >> PTIMER_STATUS_CTRL_TRGSEL_SHIFT; + return (PTIMER_TrgSrcType)u32TmpVal; +} + +/** + * @brief Set the trigger source of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param eTriggerSource the trigger source of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetTriggerSource(PTIMER_Type *const pPtimer, PTIMER_TrgSrcType eTriggerSource) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_TRGSEL_MASK) | PTIMER_STATUS_CTRL_TRGSEL( + eTriggerSource); +} + +/** + * @brief Get whether the Ptimer instance is enabled + * + * @param pPtimer the base address of the Ptimer instance + * @return true the Ptimer instance is enabled + * @return false the Ptimer instance is disabled + */ +LOCAL_INLINE bool PTIMER_HWA_GetEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_ENABLE_MASK) >> PTIMER_STATUS_CTRL_ENABLE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_Enable(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_ENABLE_MASK; +} + +/** + * @brief Disable the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_Disable(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL &= ~PTIMER_STATUS_CTRL_ENABLE_MASK; +} + +/** + * @brief Get the delay interrupt flag of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return true the delay interrupt flag of the Ptimer instance is generated + * @return false the delay interrupt flag of the Ptimer instance is not generated + */ +LOCAL_INLINE bool PTIMER_HWA_GetInterruptFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_INTFLAG_MASK) >> PTIMER_STATUS_CTRL_INTFLAG_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the delay interrupt flag of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_ClearInterruptFlag(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL &= ~PTIMER_STATUS_CTRL_INTFLAG_MASK; +} + +/** + * @brief Get whether delay interrupt is enabled for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE bool PTIMER_HWA_GetInterruptEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_INTEN_MASK) >> PTIMER_STATUS_CTRL_INTEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable delay interrupt for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param bEnable whether to enable delay interrupt for the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetInterruptEnableFlag(PTIMER_Type *const pPtimer, bool bEnable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_INTEN_MASK) | PTIMER_STATUS_CTRL_INTEN(bEnable ? 1U : 0U); +} + +/** + * @brief Get the multiply factor of the predivider of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return PTIMER_ClockPreDivMultiplyFactorType the multiply factor of the Ptimer instance + */ +LOCAL_INLINE PTIMER_ClockPreDivMultiplyFactorType PTIMER_HWA_GetDivMultiply(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_MULT_MASK) >> PTIMER_STATUS_CTRL_MULT_SHIFT; + return (PTIMER_ClockPreDivMultiplyFactorType)u32TmpVal; +} + +/** + * @brief Set the multiply factor of the predivider of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param eMultFactor the multiply factor of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetDivMultiply(PTIMER_Type *const pPtimer, + PTIMER_ClockPreDivMultiplyFactorType eMultFactor) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_MULT_MASK) | PTIMER_STATUS_CTRL_MULT(eMultFactor); +} + +/** + * @brief Get whether continuous mode is enabled for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return true continuous mode is enabled for the Ptimer instance + * @return false continuous mode is disabled for the Ptimer instance + */ +LOCAL_INLINE bool PTIMER_HWA_GetContinuoiusModeFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_CONT_MASK) >> PTIMER_STATUS_CTRL_CONT_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable continuous mode for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param bEnable whether to enable continuous mode for the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetContinuoiusModeFlag(PTIMER_Type *const pPtimer, bool bEnable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_CONT_MASK) | PTIMER_STATUS_CTRL_CONT(bEnable ? 1U : 0U); +} + +/** + * @brief Get the config value loading status + * + * @param pPtimer the base address of the Ptimer instance + * @return true the config values are in loading status + * @return false the config values are loaded + */ +LOCAL_INLINE bool PTIMER_HWA_GetValueLoadStatus(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_LDOK_MASK) >> PTIMER_STATUS_CTRL_LDOK_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Load the buffered values into register + * + * @note Some Ptimer registers are buffered and will only take effect after called + * this function + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_LoadValue(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_LDOK_MASK; +} + +/** + * @brief Get the Ptimer max counter period + * When the Ptimer counter reaches the period, it will return to zero + * + * @param pPtimer the base address of the Ptimer instance + * @return uint16_t the Ptimer max count + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetMaxCount(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->MAX_CNT & PTIMER_MAX_CNT_MAX_CNT_MASK) >> PTIMER_MAX_CNT_MAX_CNT_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set the Ptimer max counter period + * When the Ptimer counter reaches the period, it will return to zero + * + * @note the period parameter is buffered and will take effect only after called PTIMER_LoadValue() + * function. + * + * @param pPtimer the base address of the Ptimer instance + * @param u16MaxCnt the Ptimer max count + */ +LOCAL_INLINE void PTIMER_HWA_SetMaxCount(PTIMER_Type *const pPtimer, uint16_t u16MaxCnt) +{ + pPtimer->MAX_CNT = PTIMER_MAX_CNT_MAX_CNT(u16MaxCnt); +} + +/** + * @brief Get the Ptimer current count value + * + * @param pPtimer the base address of the Ptimer instance + * @return uint16_t the Ptimer current count value + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetCounterValue(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->CNT & PTIMER_CNT_CNT_MASK) >> PTIMER_CNT_CNT_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get the ptimer interrupt period + * + * @param pPtimer the base address of the Ptimer instance + * @return uint16_t the Ptimer interrupt period + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetInterruptDelay(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->INT_DLY & PTIMER_INT_DLY_INT_DLY_MASK) >> PTIMER_INT_DLY_INT_DLY_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set the ptimer interrupt period + * + * @param pPtimer the base address of the Ptimer instance + * @param u16InterruptDelay the Ptimer interrupt period + */ +LOCAL_INLINE void PTIMER_HWA_SetInterruptDelay(PTIMER_Type *const pPtimer, uint16_t u16InterruptDelay) +{ + pPtimer->INT_DLY = PTIMER_INT_DLY_INT_DLY(u16InterruptDelay); +} + +/** + * @brief Get whether back to back trigger is enbaled for the Ptimer channel + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return true back to back trigger is enbaled for the Ptimer channel + * @return false back to back trigger is disabled for the Ptimer channel + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelBackToBackFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerCtrlIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_BTB(1UL << u8PtimerCtrlIdx)) >> + (PTIMER_CTRL_CH_BTB_SHIFT + u8PtimerCtrlIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether pre-trigger output is enbaled for the Ptimer channel + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return true pre-trigger output is enbaled for the Ptimer channel + * @return false pre-trigger output is disabled for the Ptimer channel + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelPretriggerOutputFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerCtrlIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_PTOS(1UL << u8PtimerCtrlIdx)) >> + (PTIMER_CTRL_CH_PTOS_SHIFT + u8PtimerCtrlIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether pre-trigger is enbaled for the Ptimer channel + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return true pre-trigger is enbaled for the Ptimer channel + * @return false pre-trigger is disabled for the Ptimer channel + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelPretriggerEnableFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerCtrlIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_PTEN(1UL << u8PtimerCtrlIdx)) >> + (PTIMER_CTRL_CH_PTEN_SHIFT + u8PtimerCtrlIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Ptimer channel control flags + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @param bEnablePretrigger whether to enable pre-trigger + * @param bEnablePretriggerOutput whether to enable pre-trigger output + * @param bEnableBackToBack whether to enable back to back trigger + */ +LOCAL_INLINE void PTIMER_HWA_SetChannelControl(PTIMER_Type *const pPtimer, uint8_t u8Channel, bool bEnablePretrigger, + bool bEnablePretriggerOutput, bool bEnableBackToBack) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerCtrlIdx = u8Channel % 8U; + uint32_t u32CtrlMask = PTIMER_CTRL_CH_PTEN(1UL << u8PtimerCtrlIdx) | + PTIMER_CTRL_CH_PTOS(1UL << u8PtimerCtrlIdx) | + PTIMER_CTRL_CH_BTB(1UL << u8PtimerCtrlIdx); + pPtimer->CH[u8PtimerChannelIdx].CTRL = (pPtimer->CH[u8PtimerChannelIdx].CTRL & ~u32CtrlMask) | + PTIMER_CTRL_CH_PTEN((bEnablePretrigger ? 1UL : 0UL) << u8PtimerCtrlIdx) | + PTIMER_CTRL_CH_PTOS((bEnablePretriggerOutput ? 1UL : 0UL) << u8PtimerCtrlIdx) | + PTIMER_CTRL_CH_BTB((bEnableBackToBack ? 1UL : 0UL) << u8PtimerCtrlIdx); +} + +/** + * @brief Get whether the Ptimer counter matches the channel counter + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return true the Ptimer counter matches the channel counter + * @return false the Ptimer counter has not reached the channel counter + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelCounterFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerStatusIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].STATUS & PTIMER_STATUS_CH_CHN_FLAG(1UL << u8PtimerStatusIdx)) >> + (PTIMER_STATUS_CH_CHN_FLAG_SHIFT + u8PtimerStatusIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the Ptimer channel counter match flag + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + */ +LOCAL_INLINE void PTIMER_HWA_ClearChannelCounterFlag(PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerStatusIdx = u8Channel % 8U; + pPtimer->CH[u8PtimerChannelIdx].STATUS &= ~PTIMER_STATUS_CH_CHN_FLAG(1UL << u8PtimerStatusIdx); +} + +/** + * @brief Get the sequence error status of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the channel related to the sequence error + * @return true the selected channel has sequence error + * @return false the selected channel does not have sequence error + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelSequenceErrorFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerStatusIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].STATUS & PTIMER_STATUS_CH_SERR_FLAG(1UL << u8PtimerStatusIdx)) >> + (PTIMER_STATUS_CH_SERR_FLAG_SHIFT + u8PtimerStatusIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the sequence error flag of the selected Ptimer channel + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel to clear the sequence error flag + */ +LOCAL_INLINE void PTIMER_HWA_ClearChannelSequenceErrorFlag(PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerStatusIdx = u8Channel % 8U; + pPtimer->CH[u8PtimerChannelIdx].STATUS &= ~PTIMER_STATUS_CH_SERR_FLAG(1UL << u8PtimerStatusIdx); +} + +/** + * @brief Get the channel delay value + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return uint16_t the channel delay value + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetChannelDelay(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / PTIMER_CH_DLY_CNT; + uint8_t u8PtimerDelayIdx = u8Channel % PTIMER_CH_DLY_CNT; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].DLY[u8PtimerDelayIdx] & PTIMER_DLY0_CH_CHNDLY_MASK) >> + PTIMER_DLY0_CH_CHNDLY_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set the channel delay value + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @param u16Delay the channel delay value + */ +LOCAL_INLINE void PTIMER_HWA_SetChannelDelay(PTIMER_Type *const pPtimer, uint8_t u8Channel, uint16_t u16Delay) +{ + uint8_t u8PtimerChannelIdx = u8Channel / PTIMER_CH_DLY_CNT; + uint8_t u8PtimerDelayIdx = u8Channel % PTIMER_CH_DLY_CNT; + pPtimer->CH[u8PtimerChannelIdx].DLY[u8PtimerDelayIdx] = PTIMER_DLY0_CH_CHNDLY(u16Delay); +} + +/** + * @brief Get whether pulse-out is enabled + * + * @param pPtimer the base address of the Ptimer instance + * @return true pulse-out is enabled + * @return false pulse-out is disabled + */ +LOCAL_INLINE bool PTIMER_HWA_GetPulseOutEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->POEN & PTIMER_POEN_POEN_MASK) >> PTIMER_POEN_POEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable pulse-out for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_EnablePulseOut(PTIMER_Type *const pPtimer) +{ + pPtimer->POEN |= PTIMER_POEN_POEN_MASK; +} + +/** + * @brief Disable pulse-out for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_DisablePulseOut(PTIMER_Type *const pPtimer) +{ + pPtimer->POEN &= ~PTIMER_POEN_POEN_MASK; +} + +/** + * @brief Get the delay high value for the pulse-out function + * When the Ptimer counter reach the delay high value, the pulse output goes high + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetPulseOutDelayHigh(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->PODLY & PTIMER_PODLY_DLY1_MASK) >> PTIMER_PODLY_DLY1_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get the delay low value for the pulse-out function + * When the Ptimer counter reach the delay low value, the pulse output goes low + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetPulseOutDelayLow(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->PODLY & PTIMER_PODLY_DLY2_MASK) >> PTIMER_PODLY_DLY2_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set the pulse out delay value + * When the Ptimer counter reach the delay high value, the pulse output goes high + * When the Ptimer counter reach the delay low value, the pulse output goes low + * The delay high value can be either greater or less than the delay low value + * + * @param pPtimer the base address of the Ptimer instance + * @param u16DelayHigh the delay high value + * @param u16DelayLow the delay low value + */ +LOCAL_INLINE void PTIMER_HWA_SetPulseOutDelay(PTIMER_Type *const pPtimer, uint16_t u16DelayHigh, uint16_t u16DelayLow) +{ + pPtimer->PODLY = PTIMER_PODLY_DLY1(u16DelayHigh) | PTIMER_PODLY_DLY2(u16DelayLow); +} + +/** @}*/ + +#endif /* #if PTIMER_INSTANCE_COUNT > 0U */ + +#endif /* _HWA_PTIMER_H_ */ diff --git a/Inc/HwA_qdt.h b/Inc/HwA_qdt.h new file mode 100644 index 0000000..ba903d2 --- /dev/null +++ b/Inc/HwA_qdt.h @@ -0,0 +1,1858 @@ +/** + * @file HwA_qdt.h + * @author Flagchip0084 + * @brief Hardware access layer for QDT + * @version 2.0.0 + * @date 2024-07-25 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_QDT_H_ +#define _HWA_QDT_H_ + +#include "device_header.h" + +#if QDT_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_qdt + * @ingroup fc7xxx_driver_qdt + * @{ + */ + +/** + * @brief Get the value of EXTCLK_SEL. + * External Clock Select + * Selects the external clock as the QDT function clock. + * This field is write protected (depends on WPDIS/WPEN). + * 00b - QDT_TCLK0 pin as QDT external clock. + * 01b - QDT_TCLK1 pin as QDT external clock. + * 10b - QDT_TCLK2 pin as QDT external clock. + * 11b - No clock input + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of EXTCLK_SEL. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetEXTCLK_SEL(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_EXTCLK_SEL_MASK) >> QDT_SC_EXTCLK_SEL_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set EXTCLK_SEL. + * External Clock Select + * Selects the external clock as the QDT function clock. + * This field is write protected (depends on WPDIS/WPEN). + * 00b - QDT_TCLK0 pin as QDT external clock. + * 01b - QDT_TCLK1 pin as QDT external clock. + * 10b - QDT_TCLK2 pin as QDT external clock. + * 11b - No clock input + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value EXTCLK_SEL value. + */ +LOCAL_INLINE void QDT_HWA_SetEXTCLK_SEL(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SC = (pQdt->SC & ~QDT_SC_EXTCLK_SEL_MASK) | QDT_SC_EXTCLK_SEL(u8Value); +} + + + +/** + * @brief Get the value of WDOGF. + * WDOG Timerout Flag + * Same as WDOG[WDOGF]. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of WDOGF. + */ +LOCAL_INLINE uint8_t QDT_HWA_SC_GetWDOGF(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_WDOGF_MASK) >> QDT_SC_WDOGF_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Clear WDOGF. + * WDOG Timerout Flag + * Same as WDOG[WDOGF]. + * @param pQdt the base address of the QDT instance. + + */ +LOCAL_INLINE void QDT_HWA_SC_ClearWDOGF(QDT_Type *const pQdt) +{ + pQdt->SC &= ~QDT_SC_WDOGF_MASK; +} + + +/** + * @brief Get the value of CHNF. + * Channel (n) Flag + * Same as CSnC[CHF]. + * MSB is CH3, LSB is CH0. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of CHNF. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetCHNF(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_CHNF_MASK) >> QDT_SC_CHNF_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Clear CHNF. + * Channel (n) Flag + * Same as CSnC[CHF]. + * MSB is CH3, LSB is CH0. + * @param pQdt the base address of the QDT instance. + + */ +LOCAL_INLINE void QDT_HWA_ClearCHNF(QDT_Type *const pQdt) +{ + pQdt->SC &= ~QDT_SC_CHNF_MASK; +} + + +/** + * @brief Get the value of TOF. + * Timer Overflow Flag + * When the QDT counter (also is position counter) passes the value in the MOD register, this bit asserted. + * The TOF bit is cleared by reading the SC register while TOF is set and then writing a 0 to TOF bit. Writing a 1 to TOF has no effect. + * If another QDT overflow occurs between the read and write operations, the write operation has no effect; therefore, TOF remains set indicating an overflow has occurred. In this case, a TOF interrupt request is not lost due to the clearing sequence for a previous TOF. + * 0b - QDT counter has not overflowed. + * 1b - QDT counter has overflowed. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of TOF. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetTOF(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_TOF_MASK) >> QDT_SC_TOF_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Clear TOF. + * Timer Overflow Flag + * When the QDT counter (also is position counter) passes the value in the MOD register, this bit asserted. + * The TOF bit is cleared by reading the SC register while TOF is set and then writing a 0 to TOF bit. Writing a 1 to TOF has no effect. + * If another QDT overflow occurs between the read and write operations, the write operation has no effect; therefore, TOF remains set indicating an overflow has occurred. In this case, a TOF interrupt request is not lost due to the clearing sequence for a previous TOF. + * 0b - QDT counter has not overflowed. + * 1b - QDT counter has overflowed. + * @param pQdt the base address of the QDT instance. + + */ +LOCAL_INLINE void QDT_HWA_ClearTOF(QDT_Type *const pQdt) +{ + pQdt->SC &= ~QDT_SC_TOF_MASK; +} + + +/** + * @brief Get the value of TOIE. + * Timer Overflow Interrupt Enable + * 0b - Disable TOF interrupts. + * 1b - Enable TOF interrupts. An interrupt is generated when TOF asserted. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of TOIE. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetTOIE(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_TOIE_MASK) >> QDT_SC_TOIE_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set TOIE. + * Timer Overflow Interrupt Enable + * 0b - Disable TOF interrupts. + * 1b - Enable TOF interrupts. An interrupt is generated when TOF asserted. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value TOIE value. + */ +LOCAL_INLINE void QDT_HWA_SetTOIE(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SC = (pQdt->SC & ~QDT_SC_TOIE_MASK) | QDT_SC_TOIE(u8Value); +} + + + +/** + * @brief Get the value of WPDIS. + * Write Protection Disable + * When write protection is enabled (WPDIS = 0), write protected bits cannot be written. When write protection is disabled (WPDIS = 1), write protected bits can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPDIS has no effect. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of WPDIS. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetWPDIS(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_WPDIS_MASK) >> QDT_SC_WPDIS_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set WPDIS. + * Write Protection Disable + * When write protection is enabled (WPDIS = 0), write protected bits cannot be written. When write protection is disabled (WPDIS = 1), write protected bits can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPDIS has no effect. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value WPDIS value. + */ +LOCAL_INLINE void QDT_HWA_SetWPDIS(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SC = (pQdt->SC & ~QDT_SC_WPDIS_MASK) | QDT_SC_WPDIS(u8Value); +} + +/** + * @brief Disable the Write protection. + * @param pQdt the base address of the QDT instance. + */ +LOCAL_INLINE void QDT_HWA_DisableWP(QDT_Type *const pQdt) +{ + pQdt->SC = (pQdt->SC | QDT_SC_WPDIS_MASK) & ~QDT_SC_WPEN_MASK; +} + +/** + * @brief Get the value of WPEN. + * Write Protection Enable + * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPEN has no effect. + * 0b - Write protection is disabled. Write protected bits can be written. + * 1b - Write protection is enabled. Write protected bits cannot be written. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of WPEN. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetWPEN(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_WPEN_MASK) >> QDT_SC_WPEN_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set WPEN. + * Write Protection Enable + * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPEN has no effect. + * 0b - Write protection is disabled. Write protected bits can be written. + * 1b - Write protection is enabled. Write protected bits cannot be written. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value WPEN value. + */ +LOCAL_INLINE void QDT_HWA_SetWPEN(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SC = (pQdt->SC & ~QDT_SC_WPEN_MASK) | QDT_SC_WPEN(u8Value); +} + +/** + * @brief Enable the Write protection. + * @param pQdt the base address of the QDT instance. + */ +LOCAL_INLINE void QDT_HWA_EnableWP(QDT_Type *const pQdt) +{ + pQdt->SC = (pQdt->SC & ~QDT_SC_WPDIS_MASK) | QDT_SC_WPEN_MASK; +} + +/** + * @brief Get the value of DBG. + * Debug Mode + * Selects the QDT behavior in Debug Mode. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - All counters in QDT are stopped. + * 1b - QDT works as function mode. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of DBG. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetDBG(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_DBG_MASK) >> QDT_SC_DBG_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set DBG. + * Debug Mode + * Selects the QDT behavior in Debug Mode. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - All counters in QDT are stopped. + * 1b - QDT works as function mode. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value DBG value. + */ +LOCAL_INLINE void QDT_HWA_SetDBG(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SC = (pQdt->SC & ~QDT_SC_DBG_MASK) | QDT_SC_DBG(u8Value); +} + + + +/** + * @brief Get the value of MTRIGCTRL. + * Match Trigger Control + * Match Trigger Control controls the pulsing of the match trigger output signal. + * 0b - Match Trigger pulses when a match occurs between the position counters (POS) and the corresponding channel value (CV) + * 1b - Match Trigger pulses when the POSCNT, REVCNT, or POSDCNT are read + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of MTRIGCTRL. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetMTRIGCTRL(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_MTRIGCTRL_MASK) >> QDT_SC_MTRIGCTRL_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set MTRIGCTRL. + * Match Trigger Control + * Match Trigger Control controls the pulsing of the match trigger output signal. + * 0b - Match Trigger pulses when a match occurs between the position counters (POS) and the corresponding channel value (CV) + * 1b - Match Trigger pulses when the POSCNT, REVCNT, or POSDCNT are read + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value MTRIGCTRL value. + */ +LOCAL_INLINE void QDT_HWA_SetMTRIGCTRL(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SC = (pQdt->SC & ~QDT_SC_MTRIGCTRL_MASK) | QDT_SC_MTRIGCTRL(u8Value); +} + + + +/** + * @brief Get the value of QUADIR. + * QDT Counter Direction In Quadrature Decoder Mode + * Indicates the counting direction. + * 0b - QDT counter decrement. + * 1b - QDT counter increment. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of QUADIR. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetQUADIR(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_QUADIR_MASK) >> QDT_SC_QUADIR_SHIFT; + return u8TmpVal; +} + + + +/** + * @brief Get the value of TOFDIR. + * Timer Overflow Direction In Quadrature Decoder Mode + * Indicates if the TOF bit was set on the top or the bottom of counting. + * 0b - TOF bit was set on the bottom of counting. QDT counter decrement and counter changes from CNTIN to MOD. + * 1b - TOF bit was set on the top of counting. QDT counter increment and counter changes from MOD to CNTIN. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of TOFDIR. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetTOFDIR(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_TOFDIR_MASK) >> QDT_SC_TOFDIR_SHIFT; + return u8TmpVal; +} + + + +/** + * @brief Get the value of QUADMODE. + * Quadrature Decoder Mode + * Selects the encoding mode used in the Quadrature Decoder mode. + * 0b - Phase A and phase B encoding mode. + * 1b - Count and direction encoding mode. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of QUADMODE. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetQUADMODE(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_QUADMODE_MASK) >> QDT_SC_QUADMODE_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set QUADMODE. + * Quadrature Decoder Mode + * Selects the encoding mode used in the Quadrature Decoder mode. + * 0b - Phase A and phase B encoding mode. + * 1b - Count and direction encoding mode. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value QUADMODE value. + */ +LOCAL_INLINE void QDT_HWA_SetQUADMODE(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SC = (pQdt->SC & ~QDT_SC_QUADMODE_MASK) | QDT_SC_QUADMODE(u8Value); +} + + + +/** + * @brief Get the value of QUADEN. + * Quadrature Decoder Mode Enable + * Enables the Quadrature Decoder mode. In this mode, the phase A and B input signals control the QDT counter. this mode has precedence over the other modes. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - Quadrature Decoder mode is disabled. + * 1b - Quadrature Decoder mode is enabled. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of QUADEN. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetQUADEN(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_QUADEN_MASK) >> QDT_SC_QUADEN_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set QUADEN. + * Quadrature Decoder Mode Enable + * Enables the Quadrature Decoder mode. In this mode, the phase A and B input signals control the QDT counter. this mode has precedence over the other modes. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - Quadrature Decoder mode is disabled. + * 1b - Quadrature Decoder mode is enabled. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value QUADEN value. + */ +LOCAL_INLINE void QDT_HWA_SetQUADEN(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SC = (pQdt->SC & ~QDT_SC_QUADEN_MASK) | QDT_SC_QUADEN(u8Value); +} + + + +/** + * @brief Get the value of CLKS. + * Clock Source Selection + * This field is write protected (depends on WPDIS/WPEN). + * 00b - No clock selected. + * 01b - QDT input clock + * 10b - Reserved + * 11b - External pin input clock + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of CLKS. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetCLKS(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_CLKS_MASK) >> QDT_SC_CLKS_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set CLKS. + * Clock Source Selection + * This field is write protected (depends on WPDIS/WPEN). + * 00b - No clock selected. + * 01b - QDT input clock + * 10b - Reserved + * 11b - External pin input clock + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value CLKS value. + */ +LOCAL_INLINE void QDT_HWA_SetCLKS(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SC = (pQdt->SC & ~QDT_SC_CLKS_MASK) | QDT_SC_CLKS(u8Value); +} + + + +/** + * @brief Get the value of PS. + * Prescale Setting + * This field would affect the QDT counter clock frequency. + * This field is write protected (depends on WPDIS/WPEN). + * 000b - Divide by 1 + * 001b - Divide by 2 + * ... + * 111b - Divide by 128 + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of PS. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetPS(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SC & QDT_SC_PS_MASK) >> QDT_SC_PS_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set PS. + * Prescale Setting + * This field would affect the QDT counter clock frequency. + * This field is write protected (depends on WPDIS/WPEN). + * 000b - Divide by 1 + * 001b - Divide by 2 + * ... + * 111b - Divide by 128 + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value PS value. + */ +LOCAL_INLINE void QDT_HWA_SetPS(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SC = (pQdt->SC & ~QDT_SC_PS_MASK) | QDT_SC_PS(u8Value); +} + + + + + +/** + * @brief Get the value of SYNCMODE. + * CV SYNC MODE + * This field is write protected (depends on WPDIS/WPEN). + * This field define different synchronization behavior, for more information, please refer to Function Description chapter + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of SYNCMODE. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetSYNCMODE(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SYNC & QDT_SYNC_SYNCMODE_MASK) >> QDT_SYNC_SYNCMODE_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set SYNCMODE. + * CV SYNC MODE + * This field is write protected (depends on WPDIS/WPEN). + * This field define different synchronization behavior, for more information, please refer to Function Description chapter + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value SYNCMODE value. + */ +LOCAL_INLINE void QDT_HWA_SetSYNCMODE(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SYNC = (pQdt->SYNC & ~QDT_SYNC_SYNCMODE_MASK) | QDT_SYNC_SYNCMODE(u8Value); +} + + + +/** + * @brief Get the value of TRIG_UPHOLD. + * Hardware Trigger Update Hold Registers + * • When Hardware Trigger Update Hold Registers is set (=1), it allows the TRIGGER input to cause an update of the POSCNTH, REVCNTH and POSDCNTH registers + * • When Hardware Trigger Update Hold Registers is clear (=0), the hold registers (POSCNTH, REVCNTH and POSDCNTH) are not updated by the TRIGGER input + * Updating the Position Difference Counter Hold Register (POSDH) will also cause the Position Difference Counter Register (POSD) to be cleared. + * 0b - Disable updates of hold registers on the rising edge of TRIGGER input signal + * 1b - Enable updates of hold registers on the rising edge of TRIGGER input signal + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of TRIG_UPHOLD. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetTRIG_UPHOLD(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SYNC & QDT_SYNC_TRIG_UPHOLD_MASK) >> QDT_SYNC_TRIG_UPHOLD_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set TRIG_UPHOLD. + * Hardware Trigger Update Hold Registers + * • When Hardware Trigger Update Hold Registers is set (=1), it allows the TRIGGER input to cause an update of the POSCNTH, REVCNTH and POSDCNTH registers + * • When Hardware Trigger Update Hold Registers is clear (=0), the hold registers (POSCNTH, REVCNTH and POSDCNTH) are not updated by the TRIGGER input + * Updating the Position Difference Counter Hold Register (POSDH) will also cause the Position Difference Counter Register (POSD) to be cleared. + * 0b - Disable updates of hold registers on the rising edge of TRIGGER input signal + * 1b - Enable updates of hold registers on the rising edge of TRIGGER input signal + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value TRIG_UPHOLD value. + */ +LOCAL_INLINE void QDT_HWA_SetTRIG_UPHOLD(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SYNC = (pQdt->SYNC & ~QDT_SYNC_TRIG_UPHOLD_MASK) | QDT_SYNC_TRIG_UPHOLD(u8Value); +} + + + +/** + * @brief Get the value of TRIG_RSTCNT. + * Hardware Trigger Reset Counter + * Allow Hardware TRIGGER input event to reset POSCNT, REVCNT and POSDCNT + * 0b - Hardware Trigger input event will not reset the counters. + * 1b - Hardware Trigger input event will reset the counters. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of TRIG_RSTCNT. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetTRIG_RSTCNT(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SYNC & QDT_SYNC_TRIG_RSTCNT_MASK) >> QDT_SYNC_TRIG_RSTCNT_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set TRIG_RSTCNT. + * Hardware Trigger Reset Counter + * Allow Hardware TRIGGER input event to reset POSCNT, REVCNT and POSDCNT + * 0b - Hardware Trigger input event will not reset the counters. + * 1b - Hardware Trigger input event will reset the counters. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value TRIG_RSTCNT value. + */ +LOCAL_INLINE void QDT_HWA_SetTRIG_RSTCNT(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SYNC = (pQdt->SYNC & ~QDT_SYNC_TRIG_RSTCNT_MASK) | QDT_SYNC_TRIG_RSTCNT(u8Value); +} + + + +/** + * @brief Get the value of TRIG0. + * Synchronization Hardware Trigger Input 0 + * Enables hardware trigger 0 to the synchronization and reset. Hardware trigger 0 occurs when a rising edge is detected at the trigger 0 input signal. + * 0b - Trigger is disabled. + * 1b - Trigger is enabled. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of TRIG0. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetTRIG0(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SYNC & QDT_SYNC_TRIG0_MASK) >> QDT_SYNC_TRIG0_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set TRIG0. + * Synchronization Hardware Trigger Input 0 + * Enables hardware trigger 0 to the synchronization and reset. Hardware trigger 0 occurs when a rising edge is detected at the trigger 0 input signal. + * 0b - Trigger is disabled. + * 1b - Trigger is enabled. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value TRIG0 value. + */ +LOCAL_INLINE void QDT_HWA_SetTRIG0(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SYNC = (pQdt->SYNC & ~QDT_SYNC_TRIG0_MASK) | QDT_SYNC_TRIG0(u8Value); +} + + + +/** + * @brief Get the value of SW_RSTCNT. + * SW Reset Counter + * Allow SW event to reset POSCNT, REVCNT and POSDCNT + * 0b - SW event will only reset the POSCNT. + * 1b - SW event will reset the POSCNT, REVCNT and POSDCNT. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of SW_RSTCNT. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetSW_RSTCNT(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SYNC & QDT_SYNC_SW_RSTCNT_MASK) >> QDT_SYNC_SW_RSTCNT_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set SW_RSTCNT. + * SW Reset Counter + * Allow SW event to reset POSCNT, REVCNT and POSDCNT + * 0b - SW event will only reset the POSCNT. + * 1b - SW event will reset the POSCNT, REVCNT and POSDCNT. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value SW_RSTCNT value. + */ +LOCAL_INLINE void QDT_HWA_SetSW_RSTCNT(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SYNC = (pQdt->SYNC & ~QDT_SYNC_SW_RSTCNT_MASK) | QDT_SYNC_SW_RSTCNT(u8Value); +} + + + +/** + * @brief Get the value of SWSYNC. + * Synchronization Software Trigger + * Selects the software trigger as the synchronization trigger. The software trigger happens when a 1 is written to SWSYNC bit. It will be cleared automatic. + * 0b - Software trigger is not selected. + * 1b - Software trigger is selected. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of SWSYNC. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetSWSYNC(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->SYNC & QDT_SYNC_SWSYNC_MASK) >> QDT_SYNC_SWSYNC_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set SWSYNC. + * Synchronization Software Trigger + * Selects the software trigger as the synchronization trigger. The software trigger happens when a 1 is written to SWSYNC bit. It will be cleared automatic. + * 0b - Software trigger is not selected. + * 1b - Software trigger is selected. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value SWSYNC value. + */ +LOCAL_INLINE void QDT_HWA_SetSWSYNC(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->SYNC = (pQdt->SYNC & ~QDT_SYNC_SWSYNC_MASK) | QDT_SYNC_SWSYNC(u8Value); +} + + + + + +/** + * @brief Get the value of PHZPOL. + * Phase Z Input Polarity + * Selects the polarity for ICDM pair channel input. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - Low-active for ICDM. + * 1b - High-active for ICDM. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of PHZPOL. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetPHZPOL(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->POL & QDT_POL_PHZPOL_MASK) >> QDT_POL_PHZPOL_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set PHZPOL. + * Phase Z Input Polarity + * Selects the polarity for ICDM pair channel input. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - Low-active for ICDM. + * 1b - High-active for ICDM. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value PHZPOL value. + */ +LOCAL_INLINE void QDT_HWA_SetPHZPOL(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->POL = (pQdt->POL & ~QDT_POL_PHZPOL_MASK) | QDT_POL_PHZPOL(u8Value); +} + + + +/** + * @brief Get the value of PHBPOL. + * Phase B Input Polarity + * Selects the polarity for the quadrature decoder phase B input. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - Normal polarity. + * 1b - Inverted polarity. + * Phase B input signal is inverted before identifying the rising and falling edges of this signal. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of PHBPOL. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetPHBPOL(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->POL & QDT_POL_PHBPOL_MASK) >> QDT_POL_PHBPOL_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set PHBPOL. + * Phase B Input Polarity + * Selects the polarity for the quadrature decoder phase B input. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - Normal polarity. + * 1b - Inverted polarity. + * Phase B input signal is inverted before identifying the rising and falling edges of this signal. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value PHBPOL value. + */ +LOCAL_INLINE void QDT_HWA_SetPHBPOL(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->POL = (pQdt->POL & ~QDT_POL_PHBPOL_MASK) | QDT_POL_PHBPOL(u8Value); +} + + + +/** + * @brief Get the value of PHAPOL. + * Phase A Input Polarity + * Selects the polarity for the quadrature decoder phase A input. + * Selects the polarity for ICDM pair channel input. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - Normal polarity for phase A; Low-active for ICDM. + * 1b - Inverted polarity for phase A; High-active for ICDM. + * Phase A input signal is inverted before identifying the rising and falling edges of this signal. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of PHAPOL. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetPHAPOL(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->POL & QDT_POL_PHAPOL_MASK) >> QDT_POL_PHAPOL_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set PHAPOL. + * Phase A Input Polarity + * Selects the polarity for the quadrature decoder phase A input. + * Selects the polarity for ICDM pair channel input. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - Normal polarity for phase A; Low-active for ICDM. + * 1b - Inverted polarity for phase A; High-active for ICDM. + * Phase A input signal is inverted before identifying the rising and falling edges of this signal. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value PHAPOL value. + */ +LOCAL_INLINE void QDT_HWA_SetPHAPOL(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->POL = (pQdt->POL & ~QDT_POL_PHAPOL_MASK) | QDT_POL_PHAPOL(u8Value); +} + +/** + * @brief Set PHxPOL. + * Phase x Input Polarity + * Selects the polarity for the quadrature decoder phase X input. + * Selects the polarity for ICDM pair channel input. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - Normal polarity for phase X; Low-active for ICDM. + * 1b - Inverted polarity for phase X; High-active for ICDM. + * Phase X input signal is inverted before identifying the rising and falling edges of this signal. + * @param pQdt the base address of the QDT instance. + * @param u8Channel QDT Channel. + * @param uint8_t u8Value PHXPOL value. + */ +LOCAL_INLINE void QDT_HWA_SetPHXPOL(QDT_Type *const pQdt, uint8_t u8Channel, uint8_t u8Value) +{ + pQdt->POL = (pQdt->POL & ~(QDT_POL_PHAPOL_MASK << u8Channel)) | (QDT_POL_PHAPOL(u8Value) << u8Channel); +} + +/** + * @brief Get PHxPOL value. + * Phase x Input Polarity + * Selects the polarity for the quadrature decoder phase X input. + * Selects the polarity for ICDM pair channel input. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - Normal polarity for phase X; Low-active for ICDM. + * 1b - Inverted polarity for phase X; High-active for ICDM. + * Phase X input signal is inverted before identifying the rising and falling edges of this signal. + * @param pQdt the base address of the QDT instance. + * @param u8Channel QDT Channel. + * @return uint8_t u8Value PHXPOL value. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetPHXPOL(QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (uint8_t)((pQdt->POL & (QDT_POL_PHAPOL_MASK << u8Channel)) >> (QDT_POL_PHAPOL_SHIFT << u8Channel)); + return u8TmpVal; +} + +/** + * @brief Get the value of HOMEGFVAL. + * HOME Input Filter + * Selects the filter value for the HOME input. The filter is disabled when the value is zero. + * The filter value is HOMEGFVAL*4 + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of HOMEGFVAL. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetHOMEGFVAL(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->FILTER & QDT_FILTER_HOMEGFVAL_MASK) >> QDT_FILTER_HOMEGFVAL_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set HOMEGFVAL. + * HOME Input Filter + * Selects the filter value for the HOME input. The filter is disabled when the value is zero. + * The filter value is HOMEGFVAL*4 + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value HOMEGFVAL value. + */ +LOCAL_INLINE void QDT_HWA_SetHOMEGFVAL(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->FILTER = (pQdt->FILTER & ~QDT_FILTER_HOMEGFVAL_MASK) | QDT_FILTER_HOMEGFVAL(u8Value); +} + + + +/** + * @brief Get the value of PHZGFVAL. + * PHZ Input Filter + * Selects the filter value for the PHZ input. The filter is disabled when the value is zero. + * The filter value is PHZGFVAL*4 + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of PHZGFVAL. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetPHZGFVAL(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->FILTER & QDT_FILTER_PHZGFVAL_MASK) >> QDT_FILTER_PHZGFVAL_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set PHZGFVAL. + * PHZ Input Filter + * Selects the filter value for the PHZ input. The filter is disabled when the value is zero. + * The filter value is PHZGFVAL*4 + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value PHZGFVAL value. + */ +LOCAL_INLINE void QDT_HWA_SetPHZGFVAL(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->FILTER = (pQdt->FILTER & ~QDT_FILTER_PHZGFVAL_MASK) | QDT_FILTER_PHZGFVAL(u8Value); +} + + + +/** + * @brief Get the value of PHBGFVAL. + * PHB Input Filter + * Selects the filter value for the PHB input. The filter is disabled when the value is zero. + * The filter value is PHBGFVAL*4 + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of PHBGFVAL. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetPHBGFVAL(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->FILTER & QDT_FILTER_PHBGFVAL_MASK) >> QDT_FILTER_PHBGFVAL_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set PHBGFVAL. + * PHB Input Filter + * Selects the filter value for the PHB input. The filter is disabled when the value is zero. + * The filter value is PHBGFVAL*4 + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value PHBGFVAL value. + */ +LOCAL_INLINE void QDT_HWA_SetPHBGFVAL(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->FILTER = (pQdt->FILTER & ~QDT_FILTER_PHBGFVAL_MASK) | QDT_FILTER_PHBGFVAL(u8Value); +} + + + +/** + * @brief Get the value of PHAGFVAL. + * PHA Input Filter + * Selects the filter value for the PHA input. The filter is disabled when the value is zero. + * The filter value is PHAGFVAL*4 + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of PHAGFVAL. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetPHAGFVAL(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->FILTER & QDT_FILTER_PHAGFVAL_MASK) >> QDT_FILTER_PHAGFVAL_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set PHAGFVAL. + * PHA Input Filter + * Selects the filter value for the PHA input. The filter is disabled when the value is zero. + * The filter value is PHAGFVAL*4 + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value PHAGFVAL value. + */ +LOCAL_INLINE void QDT_HWA_SetPHAGFVAL(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->FILTER = (pQdt->FILTER & ~QDT_FILTER_PHAGFVAL_MASK) | QDT_FILTER_PHAGFVAL(u8Value); +} + + + +/** + * @brief Get the value of FLTPS. + * Filter Prescaler + * HOME/PHZ/PHB/PHA input glitch filters clock prescaler + * Writing to the bits FLTPS has immediate effect. + * 0000b - Divide by 1 + * 0001b - Divide by 2 + * ... + * 1111b - Divide by 16 + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of FLTPS. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetFLTPS(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->FILTER & QDT_FILTER_FLTPS_MASK) >> QDT_FILTER_FLTPS_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set FLTPS. + * Filter Prescaler + * HOME/PHZ/PHB/PHA input glitch filters clock prescaler + * Writing to the bits FLTPS has immediate effect. + * 0000b - Divide by 1 + * 0001b - Divide by 2 + * ... + * 1111b - Divide by 16 + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value FLTPS value. + */ +LOCAL_INLINE void QDT_HWA_SetFLTPS(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->FILTER = (pQdt->FILTER & ~QDT_FILTER_FLTPS_MASK) | QDT_FILTER_FLTPS(u8Value); +} + + + + + +/** + * @brief Get the value of WDOGVAL. + * WDOG Timeout Value + * WDOG is disabled if WDOGVAL = 0 + * @param pQdt the base address of the QDT instance. + + * @return uint16_t the value of WDOGVAL. + */ +LOCAL_INLINE uint16_t QDT_HWA_GetWDOGVAL(const QDT_Type *const pQdt) +{ + uint16_t u16TmpVal = (pQdt->WDOG & QDT_WDOG_WDOGVAL_MASK) >> QDT_WDOG_WDOGVAL_SHIFT; + return u16TmpVal; +} + + +/** + * @brief Set WDOGVAL. + * WDOG Timeout Value + * WDOG is disabled if WDOGVAL = 0 + * @param pQdt the base address of the QDT instance. + + * @param uint16_t u8Value WDOGVAL value. + */ +LOCAL_INLINE void QDT_HWA_SetWDOGVAL(QDT_Type *const pQdt, uint16_t u16Value) +{ + pQdt->WDOG = (pQdt->WDOG & ~QDT_WDOG_WDOGVAL_MASK) | QDT_WDOG_WDOGVAL(u16Value); +} + + + +/** + * @brief Get the value of WDOGF. + * WDOG Timerout Flag + * When the WDOG counter passes the value in the WDOGVAL register, this bit asserted. + * The WDOGF bit is cleared by reading the WDOG register while WDOGF is set and then writing a 0 to WDOGF bit. Writing a 1 to WDOGF has no effect. + * If another WDOG Timeout occurs between the read and write operations, the write operation has no effect; therefore, WDOGF remains set indicating an overflow has occurred. In this case, a WDOGF interrupt request is not lost due to the clearing sequence for a previous WDOGF. + * 0b - WODG counter has not timeout. + * 1b - WDOG counter has timeout. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of WDOGF. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetWDOGF(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->WDOG & QDT_WDOG_WDOGF_MASK) >> QDT_WDOG_WDOGF_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Clear WDOGF. + * WDOG Timerout Flag + * When the WDOG counter passes the value in the WDOGVAL register, this bit asserted. + * The WDOGF bit is cleared by reading the WDOG register while WDOGF is set and then writing a 0 to WDOGF bit. Writing a 1 to WDOGF has no effect. + * If another WDOG Timeout occurs between the read and write operations, the write operation has no effect; therefore, WDOGF remains set indicating an overflow has occurred. In this case, a WDOGF interrupt request is not lost due to the clearing sequence for a previous WDOGF. + * 0b - WODG counter has not timeout. + * 1b - WDOG counter has timeout. + * @param pQdt the base address of the QDT instance. + + */ +LOCAL_INLINE void QDT_HWA_ClearWDOGF(QDT_Type *const pQdt) +{ + pQdt->WDOG &= ~QDT_WDOG_WDOGF_MASK; +} + + +/** + * @brief Get the value of WDOGIE. + * WDOG Timerout Interrupt Enable + * 0b - Disable WDOGF interrupts. + * 1b - Enable WDOGF interrupts. An interrupt is generated when WDOGF asserted. + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of WDOGIE. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetWDOGIE(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->WDOG & QDT_WDOG_WDOGIE_MASK) >> QDT_WDOG_WDOGIE_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set WDOGIE. + * WDOG Timerout Interrupt Enable + * 0b - Disable WDOGF interrupts. + * 1b - Enable WDOGF interrupts. An interrupt is generated when WDOGF asserted. + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value WDOGIE value. + */ +LOCAL_INLINE void QDT_HWA_SetWDOGIE(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->WDOG = (pQdt->WDOG & ~QDT_WDOG_WDOGIE_MASK) | QDT_WDOG_WDOGIE(u8Value); +} + + + +/** + * @brief Get the value of WDOGEN. + * WDOG Enable + * @param pQdt the base address of the QDT instance. + + * @return uint8_t the value of WDOGEN. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetWDOGEN(const QDT_Type *const pQdt) +{ + uint8_t u8TmpVal = (pQdt->WDOG & QDT_WDOG_WDOGEN_MASK) >> QDT_WDOG_WDOGEN_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set WDOGEN. + * WDOG Enable + * @param pQdt the base address of the QDT instance. + + * @param uint8_t u8Value WDOGEN value. + */ +LOCAL_INLINE void QDT_HWA_SetWDOGEN(QDT_Type *const pQdt, uint8_t u8Value) +{ + pQdt->WDOG = (pQdt->WDOG & ~QDT_WDOG_WDOGEN_MASK) | QDT_WDOG_WDOGEN(u8Value); +} + + + + + +/** + * @brief Get the value of ICEXP_NUM_ICM_ECNT. + * Edge number counter in even channel (ICM_ECNT), read, write 8'h5a clear + * Expect number of edge in odd channel (ICEXP_NUM) read-write (rw) + * This field is write protected (depends on WPDIS/WPEN). + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of ICEXP_NUM_ICM_ECNT. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetICEXP_NUM_ICM_ECNT(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_ICEXP_NUM_ICM_ECNT_MASK) >> QDT_CSC_ICEXP_NUM_ICM_ECNT_SHIFT; + return u8TmpVal; +} + +/** + * @brief Clear CSC register. + * @param pQdt the base address of the QDT instance. + * @param u8Channel QDT Channel. + */ +LOCAL_INLINE void QDT_HWA_ClearCSC(QDT_Type *const pQdt, uint8_t u8Channel) +{ + pQdt->Channel[u8Channel].CSC = 0U; +} + +/** + * @brief Set ICEXP_NUM_ICM_ECNT. + * Edge number counter in even channel (ICM_ECNT), read, write 8'h5a clear + * Expect number of edge in odd channel (ICEXP_NUM) read-write (rw) + * This field is write protected (depends on WPDIS/WPEN). + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @param uint8_t u8Value ICEXP_NUM_ICM_ECNT value. + */ +LOCAL_INLINE void QDT_HWA_SetICEXP_NUM_ICM_ECNT(QDT_Type *const pQdt, uint8_t u8Channel, uint8_t u8Value) +{ + pQdt->Channel[u8Channel].CSC = (pQdt->Channel[u8Channel].CSC & ~QDT_CSC_ICEXP_NUM_ICM_ECNT_MASK) | QDT_CSC_ICEXP_NUM_ICM_ECNT(u8Value); +} + + + +/** + * @brief Get the value of ICM_SIG_REG. + * Re-start a measurement in Single Measurement Mode + * Valid in EVEN Channel + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of ICM_SIG_REG. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetICM_SIG_REG(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_ICM_SIG_REG_MASK) >> QDT_CSC_ICM_SIG_REG_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set ICM_SIG_REG. + * Re-start a measurement in Single Measurement Mode + * Valid in EVEN Channel + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @param uint8_t u8Value ICM_SIG_REG value. + */ +LOCAL_INLINE void QDT_HWA_SetICM_SIG_REG(QDT_Type *const pQdt, uint8_t u8Channel, uint8_t u8Value) +{ + pQdt->Channel[u8Channel].CSC = (pQdt->Channel[u8Channel].CSC & ~QDT_CSC_ICM_SIG_REG_MASK) | QDT_CSC_ICM_SIG_REG(u8Value); +} + + + +/** + * @brief Get the value of ICDPM_START. + * Start in ICDM & ICPM + * (value in ODD Channel is the same as EVEN) + * This field is write protected (depends on WPDIS/WPEN). + * 0b – the channel starts measuring after the first edge is detected. + * 1b – the measurement starts immediately after activating the channel by ICDM=1 or ICPM=1. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of ICDPM_START. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetICDPM_START(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_ICDPM_START_MASK) >> QDT_CSC_ICDPM_START_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set ICDPM_START. + * Start in ICDM & ICPM + * (value in ODD Channel is the same as EVEN) + * This field is write protected (depends on WPDIS/WPEN). + * 0b – the channel starts measuring after the first edge is detected. + * 1b – the measurement starts immediately after activating the channel by ICDM=1 or ICPM=1. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @param uint8_t u8Value ICDPM_START value. + */ +LOCAL_INLINE void QDT_HWA_SetICDPM_START(QDT_Type *const pQdt, uint8_t u8Channel, uint8_t u8Value) +{ + pQdt->Channel[u8Channel].CSC = (pQdt->Channel[u8Channel].CSC & ~QDT_CSC_ICDPM_START_MASK) | QDT_CSC_ICDPM_START(u8Value); +} + + + +/** + * @brief Get the value of ICM_CONT. + * The measurement is single or continuous + * (value in ODD Channel is the same as EVEN) + * This field is write protected (depends on WPDIS/WPEN). + * 0b – single mode. + * 1b – continuous mode. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of ICM_CONT. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetICM_CONT(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_ICM_CONT_MASK) >> QDT_CSC_ICM_CONT_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set ICM_CONT. + * The measurement is single or continuous + * (value in ODD Channel is the same as EVEN) + * This field is write protected (depends on WPDIS/WPEN). + * 0b – single mode. + * 1b – continuous mode. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @param uint8_t u8Value ICM_CONT value. + */ +LOCAL_INLINE void QDT_HWA_SetICM_CONT(QDT_Type *const pQdt, uint8_t u8Channel, uint8_t u8Value) +{ + pQdt->Channel[u8Channel].CSC = (pQdt->Channel[u8Channel].CSC & ~QDT_CSC_ICM_CONT_MASK) | QDT_CSC_ICM_CONT(u8Value); +} + + + +/** + * @brief Get the value of ICM_MODE. + * Channel Input Measurement Mode + * (value in ODD Channel is the same as EVEN) + * This field is write protected (depends on WPDIS/WPEN). + * 001b – select ICDM mode. + * 010b – select ICPM mode. + * 011b – select ICENM mode. + * 100b – select ICEXPENM mode. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of ICM_MODE. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetICM_MODE(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_ICM_MODE_MASK) >> QDT_CSC_ICM_MODE_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set ICM_MODE. + * Channel Input Measurement Mode + * (value in ODD Channel is the same as EVEN) + * This field is write protected (depends on WPDIS/WPEN). + * 001b – select ICDM mode. + * 010b – select ICPM mode. + * 011b – select ICENM mode. + * 100b – select ICEXPENM mode. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @param uint8_t u8Value ICM_MODE value. + */ +LOCAL_INLINE void QDT_HWA_SetICM_MODE(QDT_Type *const pQdt, uint8_t u8Channel, uint8_t u8Value) +{ + pQdt->Channel[u8Channel].CSC = (pQdt->Channel[u8Channel].CSC & ~QDT_CSC_ICM_MODE_MASK) | QDT_CSC_ICM_MODE(u8Value); +} + + + +/** + * @brief Get the value of REVMODE. + * Match point is POSCNT or REVCNT + * 0b – Match point is POSCNT (CV==POSCNT). + * 1b – Match point is REVCNT (CV==REVCNT). + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of REVMODE. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetREVMODE(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_REVMODE_MASK) >> QDT_CSC_REVMODE_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set REVMODE. + * Match point is POSCNT or REVCNT + * 0b – Match point is POSCNT (CV==POSCNT). + * 1b – Match point is REVCNT (CV==REVCNT). + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @param uint8_t u8Value REVMODE value. + */ +LOCAL_INLINE void QDT_HWA_SetREVMODE(QDT_Type *const pQdt, uint8_t u8Channel, uint8_t u8Value) +{ + pQdt->Channel[u8Channel].CSC = (pQdt->Channel[u8Channel].CSC & ~QDT_CSC_REVMODE_MASK) | QDT_CSC_REVMODE(u8Value); +} + + + +/** + * @brief Get the value of CHTRIG. + * Channel (n) Match Trigger Enable + * Enables the generation of the match Trigger when QDT counter (also is POSCNT) = CV if channel is in quad mode. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - The generation of this match Trigger is disabled. + * 1b - The generation of this match Trigger is enabled. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of CHTRIG. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetCHTRIG(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_CHTRIG_MASK) >> QDT_CSC_CHTRIG_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set CHTRIG. + * Channel (n) Match Trigger Enable + * Enables the generation of the match Trigger when QDT counter (also is POSCNT) = CV if channel is in quad mode. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - The generation of this match Trigger is disabled. + * 1b - The generation of this match Trigger is enabled. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @param uint8_t u8Value CHTRIG value. + */ +LOCAL_INLINE void QDT_HWA_SetCHTRIG(QDT_Type *const pQdt, uint8_t u8Channel, uint8_t u8Value) +{ + pQdt->Channel[u8Channel].CSC = (pQdt->Channel[u8Channel].CSC & ~QDT_CSC_CHTRIG_MASK) | QDT_CSC_CHTRIG(u8Value); +} + + + +/** + * @brief Get the value of CHIS. + * Channel (n) Input State + * The CHIS bit has the value of the channel (n) input before the double-sampling. + * 0b - The channel (n) input is zero. + * 1b - The channel (n) input is one. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of CHIS. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetCHIS(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_CHIS_MASK) >> QDT_CSC_CHIS_SHIFT; + return u8TmpVal; +} + + + +/** + * @brief Get the value of FLTCHIS. + * Channel (n) Input Filter State + * The CHIS bit has the value of the channel (n) input after the double-sampling and the filtering (if the channel (n) filter is enabled). + * 0b - The channel (n) input is zero. + * 1b - The channel (n) input is one. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of FLTCHIS. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetFLTCHIS(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_FLTCHIS_MASK) >> QDT_CSC_FLTCHIS_SHIFT; + return u8TmpVal; +} + + + +/** + * @brief Get the value of CHF. + * Channel (n) Flag + * Set by hardware when an event occurs on the channel (n) if channel is in input capture mode. + * Also set by hardware when channel value is equal to POSCNT (REVMODE=0) or REVCNT (REVMODE=1) if channel is in quad mode. + * CHF is cleared by reading the CSC register while CHF is set and then writing a 0 to the CHF bit. + * Writing a 1 to CHF has no effect. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of CHF. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetCHF(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_CHF_MASK) >> QDT_CSC_CHF_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Clear CHF. + * Channel (n) Flag + * Set by hardware when an event occurs on the channel (n) if channel is in input capture mode. + * Also set by hardware when channel value is equal to POSCNT (REVMODE=0) or REVCNT (REVMODE=1) if channel is in quad mode. + * CHF is cleared by reading the CSC register while CHF is set and then writing a 0 to the CHF bit. + * Writing a 1 to CHF has no effect. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + */ +LOCAL_INLINE void QDT_HWA_ClearCHF(QDT_Type *const pQdt, uint8_t u8Channel) +{ + pQdt->Channel[u8Channel].CSC &= ~QDT_CSC_CHF_MASK; +} + + +/** + * @brief Get the value of CHIE. + * Channel (n) Interrupt Enable + * 0b - Disable channel (n) interrupt. + * 1b - Enable channel (n) interrupt. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of CHIE. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetCHIE(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_CHIE_MASK) >> QDT_CSC_CHIE_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set CHIE. + * Channel (n) Interrupt Enable + * 0b - Disable channel (n) interrupt. + * 1b - Enable channel (n) interrupt. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @param uint8_t u8Value CHIE value. + */ +LOCAL_INLINE void QDT_HWA_SetCHIE(QDT_Type *const pQdt, uint8_t u8Channel, uint8_t u8Value) +{ + pQdt->Channel[u8Channel].CSC = (pQdt->Channel[u8Channel].CSC & ~QDT_CSC_CHIE_MASK) | QDT_CSC_CHIE(u8Value); +} + + + +/** + * @brief Get the value of ELSB. + * Channel (n) Edge or Level Select + * This field is write protected (depends on WPDIS/WPEN). + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of ELSB. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetELSB(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_ELSB_MASK) >> QDT_CSC_ELSB_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set ELSB. + * Channel (n) Edge or Level Select + * This field is write protected (depends on WPDIS/WPEN). + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @param uint8_t u8Value ELSB value. + */ +LOCAL_INLINE void QDT_HWA_SetELSB(QDT_Type *const pQdt, uint8_t u8Channel, uint8_t u8Value) +{ + pQdt->Channel[u8Channel].CSC = (pQdt->Channel[u8Channel].CSC & ~QDT_CSC_ELSB_MASK) | QDT_CSC_ELSB(u8Value); +} + + + +/** + * @brief Get the value of ELSA. + * Channel (n) Edge or Level Select + * This field is write protected (depends on WPDIS/WPEN). + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of ELSA. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetELSA(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_ELSA_MASK) >> QDT_CSC_ELSA_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set ELSA. + * Channel (n) Edge or Level Select + * This field is write protected (depends on WPDIS/WPEN). + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @param uint8_t u8Value ELSA value. + */ +LOCAL_INLINE void QDT_HWA_SetELSA(QDT_Type *const pQdt, uint8_t u8Channel, uint8_t u8Value) +{ + pQdt->Channel[u8Channel].CSC = (pQdt->Channel[u8Channel].CSC & ~QDT_CSC_ELSA_MASK) | QDT_CSC_ELSA(u8Value); +} + + + +/** + * @brief Get the value of ICRST. + * QDT counter reset is driven by the selected event of the channel (n) in the Input Capture mode. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - QDT counter is not reset when the selected channel (n) input event is detected. + * 1b - QDT counter is reset when the selected channel (n) input event is detected. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint8_t the value of ICRST. + */ +LOCAL_INLINE uint8_t QDT_HWA_GetICRST(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pQdt->Channel[u8Channel].CSC & QDT_CSC_ICRST_MASK) >> QDT_CSC_ICRST_SHIFT; + return u8TmpVal; +} + + +/** + * @brief Set ICRST. + * QDT counter reset is driven by the selected event of the channel (n) in the Input Capture mode. + * This field is write protected (depends on WPDIS/WPEN). + * 0b - QDT counter is not reset when the selected channel (n) input event is detected. + * 1b - QDT counter is reset when the selected channel (n) input event is detected. + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @param uint8_t u8Value ICRST value. + */ +LOCAL_INLINE void QDT_HWA_SetICRST(QDT_Type *const pQdt, uint8_t u8Channel, uint8_t u8Value) +{ + pQdt->Channel[u8Channel].CSC = (pQdt->Channel[u8Channel].CSC & ~QDT_CSC_ICRST_MASK) | QDT_CSC_ICRST(u8Value); +} + + + + + +/** + * @brief Get the value of CV. + * Channel Value + * Captured QDT counter value of the input modes or the match value for the quadrature decoder modes + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @return uint32_t the value of CV. + */ +LOCAL_INLINE uint32_t QDT_HWA_GetCV(const QDT_Type *const pQdt, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pQdt->Channel[u8Channel].CV & QDT_CV_CV_MASK) >> QDT_CV_CV_SHIFT; + return u32TmpVal; +} + + +/** + * @brief Set CV. + * Channel Value + * Captured QDT counter value of the input modes or the match value for the quadrature decoder modes + * @param pQdt the base address of the QDT instance. +* @param u8Channel QDT Channel. + * @param uint32_t u8Value CV value. + */ +LOCAL_INLINE void QDT_HWA_SetCV(QDT_Type *const pQdt, uint8_t u8Channel, uint32_t u32Value) +{ + pQdt->Channel[u8Channel].CV = (pQdt->Channel[u8Channel].CV & ~QDT_CV_CV_MASK) | QDT_CV_CV(u32Value); +} + + + + + +/** + * @brief Get the value of REVCNT. + * Revolution Counter + * @param pQdt the base address of the QDT instance. + + * @return uint16_t the value of REVCNT. + */ +LOCAL_INLINE uint16_t QDT_HWA_GetREVCNT(const QDT_Type *const pQdt) +{ + uint16_t u16TmpVal = (pQdt->REVCNT & QDT_REVCNT_REVCNT_MASK) >> QDT_REVCNT_REVCNT_SHIFT; + return u16TmpVal; +} + + + + + +/** + * @brief Get the value of REVCNT_HOLD. + * Revolution Hold Counter + * @param pQdt the base address of the QDT instance. + + * @return uint16_t the value of REVCNT_HOLD. + */ +LOCAL_INLINE uint16_t QDT_HWA_GetREVCNT_HOLD(const QDT_Type *const pQdt) +{ + uint16_t u16TmpVal = (pQdt->REVCNT_HOLD & QDT_REVCNT_HOLD_REVCNT_HOLD_MASK) >> QDT_REVCNT_HOLD_REVCNT_HOLD_SHIFT; + return u16TmpVal; +} + + + + + +/** + * @brief Get the value of POSCNT. + * Position Counter + * Write action will reset Position Counter + * @param pQdt the base address of the QDT instance. + + * @return uint32_t the value of POSCNT. + */ +LOCAL_INLINE uint32_t QDT_HWA_GetPOSCNT(const QDT_Type *const pQdt) +{ + uint32_t u32TmpVal = (pQdt->POSCNT & QDT_POSCNT_POSCNT_MASK) >> QDT_POSCNT_POSCNT_SHIFT; + return u32TmpVal; +} + + +/** + * @brief Set POSCNT. + * Position Counter + * Write action will reset Position Counter + * @param pQdt the base address of the QDT instance. + + * @param uint32_t u8Value POSCNT value. + */ +LOCAL_INLINE void QDT_HWA_SetPOSCNT(QDT_Type *const pQdt, uint32_t u8Value) +{ + pQdt->POSCNT = (pQdt->POSCNT & ~QDT_POSCNT_POSCNT_MASK) | QDT_POSCNT_POSCNT(u8Value); +} + + + + + +/** + * @brief Get the value of POSCNT_HOLD. + * Position Hold Counter + * @param pQdt the base address of the QDT instance. + + * @return uint32_t the value of POSCNT_HOLD. + */ +LOCAL_INLINE uint32_t QDT_HWA_GetPOSCNT_HOLD(const QDT_Type *const pQdt) +{ + uint32_t u32TmpVal = (pQdt->POSCNT_HOLD & QDT_POSCNT_HOLD_POSCNT_HOLD_MASK) >> QDT_POSCNT_HOLD_POSCNT_HOLD_SHIFT; + return u32TmpVal; +} + + + + + +/** + * @brief Get the value of POSDCNT. + * Position Difference Counter + * @param pQdt the base address of the QDT instance. + + * @return uint16_t the value of POSDCNT. + */ +LOCAL_INLINE uint16_t QDT_HWA_GetPOSDCNT(const QDT_Type *const pQdt) +{ + uint16_t u16TmpVal = (pQdt->POSDCNT & QDT_POSDCNT_POSDCNT_MASK) >> QDT_POSDCNT_POSDCNT_SHIFT; + return u16TmpVal; +} + + + + + +/** + * @brief Get the value of POSDCNT_HOLD. + * Position Difference Hold Counter + * @param pQdt the base address of the QDT instance. + + * @return uint16_t the value of POSDCNT_HOLD. + */ +LOCAL_INLINE uint16_t QDT_HWA_GetPOSDCNT_HOLD(const QDT_Type *const pQdt) +{ + uint16_t u16TmpVal = (pQdt->POSDCNT_HOLD & QDT_POSDCNT_HOLD_POSDCNT_HOLD_MASK) >> QDT_POSDCNT_HOLD_POSDCNT_HOLD_SHIFT; + return u16TmpVal; +} + + + + + +/** + * @brief Get the value of LECNT. + * Last PHA/B Edge Time Counter + * @param pQdt the base address of the QDT instance. + + * @return uint16_t the value of LECNT. + */ +LOCAL_INLINE uint16_t QDT_HWA_GetLECNT(const QDT_Type *const pQdt) +{ + uint16_t u16TmpVal = (pQdt->LECNT & QDT_LECNT_LECNT_MASK) >> QDT_LECNT_LECNT_SHIFT; + return u16TmpVal; +} + + + + + +/** + * @brief Get the value of LECNT_HOLD. + * Last PHA/B Edge Time Hold Counter + * @param pQdt the base address of the QDT instance. + + * @return uint16_t the value of LECNT_HOLD. + */ +LOCAL_INLINE uint16_t QDT_HWA_GetLECNT_HOLD(const QDT_Type *const pQdt) +{ + uint16_t u16TmpVal = (pQdt->LECNT_HOLD & QDT_LECNT_HOLD_LECNT_HOLD_MASK) >> QDT_LECNT_HOLD_LECNT_HOLD_SHIFT; + return u16TmpVal; +} + + + + + +/** + * @brief Get the value of POSDTMRCNT. + * Position Difference Time Counter + * @param pQdt the base address of the QDT instance. + + * @return uint16_t the value of POSDTMRCNT. + */ +LOCAL_INLINE uint16_t QDT_HWA_GetPOSDTMRCNT(const QDT_Type *const pQdt) +{ + uint16_t u16TmpVal = (pQdt->POSDTMRCNT & QDT_POSDTMRCNT_POSDTMRCNT_MASK) >> QDT_POSDTMRCNT_POSDTMRCNT_SHIFT; + return u16TmpVal; +} + + + + + +/** + * @brief Get the value of POSDTMRCNT_HOLD. + * Position Difference Time Hold Counter + * @param pQdt the base address of the QDT instance. + + * @return uint16_t the value of POSDTMRCNT_HOLD. + */ +LOCAL_INLINE uint16_t QDT_HWA_GetPOSDTMRCNT_HOLD(const QDT_Type *const pQdt) +{ + uint16_t u16TmpVal = (pQdt->POSDTMRCNT_HOLD & QDT_POSDTMRCNT_HOLD_POSDTMRCNT_HOLD_MASK) >> QDT_POSDTMRCNT_HOLD_POSDTMRCNT_HOLD_SHIFT; + return u16TmpVal; +} + +#endif + + +/** @}*/ + +#endif /* _HWA_QDT_H_ */ diff --git a/Inc/HwA_rgm.h b/Inc/HwA_rgm.h new file mode 100644 index 0000000..13b001e --- /dev/null +++ b/Inc/HwA_rgm.h @@ -0,0 +1,1095 @@ +/** + * @file HwA_rgm.h + * @author Flagchip + * @brief RGM hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_RGM_H_ +#define _HWA_RGM_H_ + +#include "device_header.h" + +#if RGM_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_rgm HwA_rgm + * @ingroup module_driver_rgm + * @{ + */ + + +/********* Local typedef ************/ +/** @brief Rgm reset event */ +typedef enum +{ + RGM_WAKEUP = RGM_SRS_WAKEUP_MASK, /**< Wakeup reset */ + RGM_LVD = RGM_SRS_LVR_MASK, /**< Low voltage reset */ + RGM_CLKERR1 = RGM_SRS_CLKERR1_MASK, /**< Clock error 1 reset */ + RGM_CLKERR0 = RGM_SRS_CLKERR0_MASK, /**< Clock error 0 reset */ + RGM_FSCMU = RGM_SRS_FCSMU_MASK, /**< FCSMU reset */ + RGM_HSMWDOG = RGM_SRS_HSM_WDOG_MASK, /**< HSM watchdog reset */ + RGM_PIN = RGM_SRS_PIN_MASK, /**< Pin reset */ + RGM_POR = RGM_SRS_POR_MASK, /**< Power on reset */ + RGM_JTAG = RGM_SRS_JTAG_MASK, /**< JTAG reset */ + RGM_SYSAP = RGM_SRS_SYSAP_MASK, /**< System AP reset */ +#if RGM_WDG1_RIE_SUPPORT + RGM_WDOG1 = RGM_SRS_WDOG1_MASK, /**< Watchdog 1 reset */ +#endif + RGM_SACKERR = RGM_SRS_SACKERR_MASK, /**< SACKERR reset */ + RGM_CMU3 = RGM_SRS_CMU3_MASK, /**< CMU3 reset */ + RGM_LBIST = RGM_SRS_LBIST_MASK, /**< LBIST reset */ + RGM_CPU_LOCKUP = RGM_C0_SRS_C0_LOCKUP_MASK, /**< CPU lockup reset */ + RGM_CPU_SYSRST = RGM_C0_SRS_C0_SYSRST_MASK, /**< CPU system core reset */ + RGM_CPU_WDOG = RGM_C0_SRS_C0_WDOG_MASK, /**< Watchdog 0 reset */ + RGM_CPU_INTM = RGM_C0_SRS_C0_INTM_MASK, /**< CPU interrupt monitor reset */ + RGM_CPU_SWRST = RGM_C0_SRS_C0_SWRST_MASK, /**< System software reset */ + RGM_FSMERR = RGM_SRS_FSM_ERR_MASK, /**< FSM error reset */ + RGM_PINRSTTOUT = RGM_SRS_PINRST_TOUT_MASK, /**< Pin reset timeout reset */ + RGM_SYSRSTTOUT = RGM_SRS_SYSRST_TOUT_MASK /**< System reset timeout reset */ +} RGM_ResetEventType; + +/** @brief Rgm reset interrupt delay cycles type. */ +typedef enum +{ + RGM_8_CLOCK_CYCLES = 0U, /**< 8 clock cycles */ + RGM_32_CLOCK_CYCLES, /**< 32 clock cycles */ + RGM_128_CLOCK_CYCLES, /**< 128 clock cycles */ + RGM_512_CLOCK_CYCLES /**< 512 clock cycles */ +} RGM_ResetDelayType; + +/** @brief Rgm reset interrupt event manger */ +typedef enum +{ + RGM_INT_CLKERR0 = RGM_SRIE_CLKERR0_RIE_MASK, /**< Clock error 0 reset interrupt */ + RGM_INT_WDG = RGM_SRIE_WDG_RIE_MASK, /**< Watchdog reset interrupt */ +#if RGM_PIN_RIE_SUPPORT + RGM_INT_PIN = RGM_SRIE_PIN_RIE_MASK, /**< Pin reset interrupt */ +#endif + RGM_INT_JTAG = RGM_SRIE_JTAG_RIE_MASK, /**< JTAG reset interrupt */ + RGM_INT_CPULOC = RGM_SRIE_CPULOC_RIE_MASK, /**< CPU lockup reset interrupt */ + RGM_INT_SW = RGM_SRIE_SW_RIE_MASK, /**< Software reset interrupt */ + RGM_INT_SYSAP = RGM_SRIE_SYSAP_RIE_MASK, /**< System AP reset interrupt */ +#if RGM_INTM_TOUT_RIE_SUPPORT + RGM_INT_INTM_TOUT = RGM_SRIE_INTM_TOUT_RIE_MASK, /**< Interrupt monitor timeout reset interrupt */ +#endif +#if RGM_WDG1_RIE_SUPPORT + RGM_INT_WDG1 = RGM_SRIE_WDOG1_RIE_MASK, /**< Watchdog1 reset interrupt */ +#endif + RGM_INT_SACKERR = RGM_SRIE_SACKERR_RIE_MASK, /**< SACKERR reset interrupt */ + RGM_INT_ALL = RGM_SRIE_ALL_RIE_MASK /**< All reset interrupt */ +} RGM_SysResetIntMangerType; + +/** @brief Rgm CPU0,1,2,3 related interrupt event manger */ +typedef enum +{ + RGM_CPU_INT_LOCKUP = RGM_C0_CFG_C0_LOCKUP_IE_MASK, /**< CPU lockup reset */ + RGM_CPU_INT_SYSRST = RGM_C0_CFG_C0_SYSRST_IE_MASK, /**< CPU system core reset */ + RGM_CPU_INT_WDOG = RGM_C0_CFG_C0_WDOG_IE_MASK, /**< Watchdog reset */ + RGM_CPU_INT_INTM = RGM_C0_CFG_C0_INTM_IE_MASK, /**< Interrupt monitor reset */ + RGM_CPU_INT_SWRST = RGM_C0_CFG_C0_SWRST_IE_MASK /**< Software reset */ +} RGM_CoreResetIntMangerType; + +/** @brief Rgm CPU0,1,2,3 software reset status */ +typedef enum +{ + RGM_REEST_STATUS_UNDER_RESET = 0U, /**< Under reset */ + RGM_REEST_STATUS_OUT_RESET /**< Out of reset */ +} RGM_CoreResetStatusType; + +/** @brief Rgm CPU1,2,3 system reset enable flag */ +typedef enum +{ + RGM_CPU_EN_LOCKUP = RGM_C0_CFG_C0_LOCKUP_EN_MASK, /**< Core lockup reset trigger system reset */ + RGM_CPU_EN_SYSRST = RGM_C0_CFG_C0_SYSRST_EN_MASK, /**< Core system core reset trigger system reset */ + RGM_CPU_EN_WDOG = RGM_C0_CFG_C0_WDOG_EN_MASK, /**< Core watchdog reset trigger system reset */ + RGM_CPU_EN_INTM = RGM_C0_CFG_C0_INTM_EN_MASK, /**< Core interrupt monitor reset trigger system reset */ + RGM_CPU_EN_SWRST = RGM_C0_CFG_C0_SWRST_EN_MASK, /**< Core software reset trigger system reset */ + RGM_CPU_EN_ALL = 0x1F0000 /**< Core All reset trigger system reset */ +} RGM_CoreRstTrigSysRstMangerType; + +/********* Local inline function ************/ +/** + * @brief Read last reset flag + * + * @return Last reset flag + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadLastResetFlag(void) +{ + return (uint32_t)RGM->SRS; +} + +/** + * @brief Read all reset flag before POR,SSRS register is reset on POR only + * + * @return All reset flag before POR + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadAllResetFlagBeforePOR(void) +{ + return (uint32_t)RGM->SSRS; +} + +/** + * @brief Set SSRS register + * + * @param u32Value SSRS register value + */ +LOCAL_INLINE void RGM_HWA_SetSsrsReg(uint32_t u32Value) +{ + RGM->SSRS = u32Value; +} + +/** + * @brief This api can clear all reset flag of SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +LOCAL_INLINE void RGM_HWA_ClearAllResetFlagAfterPOR(void) +{ + RGM->SSRS = RGM_SSRS_ALLFLAG; +} + +/** + * @brief Read reset pin filter register + * + * @return Reset pin filter register + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadResetPinFilterEnable(void) +{ + return (uint32_t)RGM->RSTFLT; +} + +/** + * @brief Set RSTFLT register + * + * @param u32Value RSTFLT register value + */ +LOCAL_INLINE void RGM_HWA_SetRstfltReg(uint32_t u32Value) +{ + RGM->RSTFLT = u32Value; +} + +/** + * @brief Set reset pin filter bus clock filter width + * + * @param u8Value Bus clock filter width value + */ +LOCAL_INLINE void RGM_HWA_SetBusClockFilterWidth(uint8_t u8Value) +{ + uint32_t u32RegValue = RGM->RSTFLT; + RGM->RSTFLT = (u32RegValue & ~(uint32_t)RGM_RSTFLT_RSTFLT_BUSW_MASK) | RGM_RSTFLT_RSTFLT_BUSW(u8Value); +} + +/** + * @brief Enable reset pin filter bus clock + * + */ +LOCAL_INLINE void RGM_HWA_EnableBusClockFilter(void) +{ + RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_BUS_MASK; +} + +/** + * @brief Enable reset pin filter AON32K clock + * + */ +LOCAL_INLINE void RGM_HWA_EnableAon32kClockFilter(void) +{ + RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_AON_MASK; +} + +/** + * @brief Enable reset pin filter AON32K low power clock + * + */ +LOCAL_INLINE void RGM_HWA_EnableAon32kLPClockFilter(void) +{ + RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_AON_LP_MASK; +} + +/** + * @brief Clear reset pin filter bus clock filter width + * + */ +LOCAL_INLINE void RGM_HWA_ClearBusClockFilterWidth(void) +{ + RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_BUSW_MASK; +} + +/** + * @brief Disable reset pin filter bus clock + * + */ +LOCAL_INLINE void RGM_HWA_DisableBusClockFilter(void) +{ + RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_BUS_MASK; +} + +/** + * @brief Disable reset pin filter AON32K clock + * + */ +LOCAL_INLINE void RGM_HWA_DisableAon32kClockFilter(void) +{ + RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_AON_MASK; +} + +/** + * @brief Disable reset pin filter AON32K low power clock + * + */ +LOCAL_INLINE void RGM_HWA_DisableAon32kLPClockFilter(void) +{ + RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_AON_LP_MASK; +} + +/** + * @brief Set SRIE register + * + * @param u32Value SRIE register value + */ +LOCAL_INLINE void RGM_HWA_SetSrieReg(uint32_t u32Value) +{ + RGM->SRIE = u32Value; +} + +/** + * @brief Get SRIE register + * + * @return SRIE register value + */ +LOCAL_INLINE uint32_t RGM_HWA_GetSrieReg(void) +{ + return RGM->SRIE; +} + +/** + * @brief Set Reset delay + * + * @param eDelay Reset delay type + */ +LOCAL_INLINE void RGM_HWA_SetResetDelay(RGM_ResetDelayType eDelay) +{ + uint32_t u32RegValue = RGM->SRIE; + RGM->SRIE = (u32RegValue & ~(uint32_t)RGM_SRIE_DELAY_MASK) | RGM_SRIE_DELAY(eDelay); +} + +/** + * @brief Enable global reset interrupt + * + */ +LOCAL_INLINE void RGM_HWA_EnableGlobalResetInterrupt(void) +{ + RGM->SRIE |= (uint32_t)RGM_SRIE_GLOBAL_RIE_MASK; +} + +/** + * @brief Enable reset interrupt + * + * @param eResetInterrupt Reset interrupt type + */ +LOCAL_INLINE void RGM_HWA_EnableResetInterrupt(RGM_SysResetIntMangerType eResetInterrupt) +{ + RGM->SRIE |= (uint32_t)((uint32_t)eResetInterrupt & RGM_SRIE_ALL_RIE_MASK); +} + +/** + * @brief Disable reset interrupt + * + * @param eResetInterrupt Reset interrupt type + */ +LOCAL_INLINE void RGM_HWA_DisableResetInterrupt(RGM_SysResetIntMangerType eResetInterrupt) +{ + RGM->SRIE &= ~(uint32_t)((uint32_t)eResetInterrupt & RGM_SRIE_ALL_RIE_MASK); +} + +/** + * @brief Get enabling status of system reset + * + * @return Interrupt enabling status of system reset + */ +LOCAL_INLINE uint32_t RGM_HWA_GetResetInterrupt(void) +{ + return (uint32_t)(RGM->SRIE & RGM_SRIE_ALL_RIE_MASK); +} + +/** + * @brief Perform system core reset. + * + */ +LOCAL_INLINE void CM7_HWA_SystemCoreReset(void) +{ + __DSB(); + + uint32 u32Temp; + u32Temp = SCB->AIRCR; + u32Temp &= ~(uint32)(SCB_AIRCR_VECTKEY_Msk); + u32Temp |= (uint32)((((uint32_t)(((uint32_t)(0x5FAU))<AIRCR = u32Temp; + + __DSB(); +} + +/** + * @brief Set C0_CFG register + * + * @param u32Value C0_CFG register value + */ +LOCAL_INLINE void RGM_HWA_SetC0CfgReg(uint32_t u32Value) +{ + RGM->C0_CFG = u32Value; +} + +/** + * @brief Get C0_CFG register + * + * @return C0_CFG register value + */ +LOCAL_INLINE uint32_t RGM_HWA_GetC0CfgReg(void) +{ + return RGM->C0_CFG; +} + +/** + * @brief Enable CPU0 interrupt + * + * @param u32CPU0ResetInterrupt CPU0 related interrupt type + */ +LOCAL_INLINE void RGM_HWA_EnableCPU0InterruptFlag(uint32_t u32CPU0ResetInterrupt) +{ + RGM->C0_CFG |= (uint32_t)(u32CPU0ResetInterrupt & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK | + RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK)); +} + +/** + * @brief Disable CPU0 interrupt + * + * @param u32CPU0ResetInterrupt CPU0 related interrupt type + */ +LOCAL_INLINE void RGM_HWA_DisableCPU0InterruptFlag(uint32_t u32CPU0ResetInterrupt) +{ + RGM->C0_CFG &= ~(uint32_t)(u32CPU0ResetInterrupt & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK | + RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK)); +} + +/** + * @brief Get enabling status of CPU0 core related reset + * + * @return Interrupt enabling status of CPU0 core related reset + */ +LOCAL_INLINE uint32_t RGM_HWA_GetCPU0ResetInterrupt(void) +{ + return (uint32_t)(RGM->C0_CFG & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK | + RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK)); +} + +/** + * @brief Get the CPU0 exit reset flag + * + * @return RGM_CPU_OUT_RST_UNDER CPU0 is under reset + * @return RGM_CPU_OUT_RST_OUT CPU0 is out of reset + */ +LOCAL_INLINE RGM_CoreResetStatusType RGM_HWA_GetCPU0OutResetFlag(void) +{ + uint8_t u8TmpVal = (uint8_t)(RGM->C0_RST & RGM_C0_RST_C0_OUT_OF_RST_MASK) >> RGM_C0_RST_C0_OUT_OF_RST_SHIFT; + return (RGM_CoreResetStatusType)u8TmpVal; +} + +/** + * @brief Issue a CPU0 system software reset. + * + */ +LOCAL_INLINE void RGM_HWA_CPU0_SystemSoftWareReset(void) +{ + RGM->C0_RST |= (uint32_t)RGM_C0_RST_C0_SWRST_MASK; +} + +/** + * @brief Read CPU0 last reset flag + * + * @return CPU0 last reset flag + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadCPU0LastResetFlag(void) +{ + return (uint32_t)RGM->C0_SRS; +} + +/** + * @brief Read CPU0 all reset flag before POR,SSRS register is reset on POR only + * + * @return CPU0 all reset flag before POR + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadCPU0AllResetFlagBeforePOR(void) +{ + return (uint32_t)RGM->C0_SSRS; +} + +/** + * @brief Set C0_SSRS register + * + * @param u32Value C0_SSRS register value + */ +LOCAL_INLINE void RGM_HWA_SetC0SsrsReg(uint32_t u32Value) +{ + RGM->C0_SSRS = u32Value; +} + +/** + * @brief This api can clear all reset flag of SSRGM_C0_SSRSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +LOCAL_INLINE void RGM_HWA_ClearC0AllResetFlagAfterPOR(void) +{ + RGM->C0_SSRS = (uint32_t)(RGM_SSRS_ALLFLAG|RGM_C0_SSRS_C0_SWRST_MASK| + RGM_C0_SSRS_C0_INTM_MASK|RGM_C0_SSRS_C0_WDOG_MASK| + RGM_C0_SSRS_C0_SYSRST_MASK|RGM_C0_SSRS_C0_LOCKUP_MASK); +} + +#if RGM_C1_SUPPORT +/** + * @brief Set C1_CFG register + * + * @param u32Value C1_CFG register value + */ +LOCAL_INLINE void RGM_HWA_SetC1CfgReg(uint32_t u32Value) +{ + RGM->C1_CFG = u32Value; +} + +/** + * @brief Get C1_CFG register + * + * @return C1_CFG register value + */ +LOCAL_INLINE uint32_t RGM_HWA_GetC1CfgReg(void) +{ + return RGM->C1_CFG; +} + +/** + * @brief Enable CPU1 reset to trigger system reset + * + * @param eCPU1SystemReset The CPU1 reset that triggers the system reset + */ +LOCAL_INLINE void RGM_HWA_EnableCPU1SystemResetFlag(RGM_CoreRstTrigSysRstMangerType eCPU1SystemReset) +{ + RGM->C1_CFG |= (uint32_t)((uint32_t)eCPU1SystemReset & (RGM_C1_CFG_C1_LOCKUP_EN_MASK | RGM_C1_CFG_C1_SYSRST_EN_MASK | RGM_C1_CFG_C1_WDOG_EN_MASK | + RGM_C1_CFG_C1_INTM_EN_MASK | RGM_C1_CFG_C1_SWRST_EN_MASK)); +} + +/** + * @brief Disable CPU1 reset to trigger system reset + * + * @param eCPU1SystemReset The CPU1 reset that triggers the system reset + */ +LOCAL_INLINE void RGM_HWA_DisableCPU1SystemResetFlag(RGM_CoreRstTrigSysRstMangerType eCPU1SystemReset) +{ + RGM->C1_CFG &= ~(uint32_t)((uint32_t)eCPU1SystemReset & (RGM_C1_CFG_C1_LOCKUP_EN_MASK | RGM_C1_CFG_C1_SYSRST_EN_MASK | RGM_C1_CFG_C1_WDOG_EN_MASK | + RGM_C1_CFG_C1_INTM_EN_MASK | RGM_C1_CFG_C1_SWRST_EN_MASK)); +} + +/** + * @brief Enable CPU1 interrupts + * + * @param u32CPU1ResetInterrupt CPU1 related interrupt type + */ +LOCAL_INLINE void RGM_HWA_EnableCPU1InterruptFlag(uint32_t u32CPU1ResetInterrupt) +{ + RGM->C1_CFG |= (uint32_t)(u32CPU1ResetInterrupt & (RGM_C1_CFG_C1_SWRST_IE_MASK | RGM_C1_CFG_C1_INTM_IE_MASK | RGM_C1_CFG_C1_WDOG_IE_MASK | + RGM_C1_CFG_C1_SYSRST_IE_MASK | RGM_C1_CFG_C1_LOCKUP_IE_MASK)); +} + +/** + * @brief Disable CPU1 interrupts + * + * @param u32CPU1ResetInterrupt CPU1 related interrupt type + */ +LOCAL_INLINE void RGM_HWA_DisableCPU1InterruptFlag(uint32_t u32CPU1ResetInterrupt) +{ + RGM->C1_CFG &= ~(uint32_t)(u32CPU1ResetInterrupt & (RGM_C1_CFG_C1_SWRST_IE_MASK | RGM_C1_CFG_C1_INTM_IE_MASK | RGM_C1_CFG_C1_WDOG_IE_MASK | + RGM_C1_CFG_C1_SYSRST_IE_MASK | RGM_C1_CFG_C1_LOCKUP_IE_MASK)); +} + +/** + * @brief Get the status of CPU1 core related reset configured as system reset + * + * @return CPU1 core related reset configured as system reset + */ +LOCAL_INLINE uint32_t RGM_HWA_GetCPU1SystemResetFlag(void) +{ + return (uint32_t)(RGM->C1_CFG & (RGM_C1_CFG_C1_LOCKUP_EN_MASK | RGM_C1_CFG_C1_SYSRST_EN_MASK | RGM_C1_CFG_C1_WDOG_EN_MASK | + RGM_C1_CFG_C1_INTM_EN_MASK | RGM_C1_CFG_C1_SWRST_EN_MASK)); +} + +/** + * @brief Get enabling status of CPU1 core related reset interrupt + * + * @return Interrupt enabling status of CPU1 core related reset + */ +LOCAL_INLINE uint32_t RGM_HWA_GetCPU1ResetInterrupt(void) +{ + return (uint32_t)(RGM->C1_CFG & (RGM_C1_CFG_C1_SWRST_IE_MASK | RGM_C1_CFG_C1_INTM_IE_MASK | RGM_C1_CFG_C1_WDOG_IE_MASK | + RGM_C1_CFG_C1_SYSRST_IE_MASK | RGM_C1_CFG_C1_LOCKUP_IE_MASK)); +} + +/** + * @brief Get the CPU1 exit reset flag + * + * @return RGM_CPU_OUT_RST_UNDER CPU1 is under reset + * @return RGM_CPU_OUT_RST_OUT CPU1 is out of reset + */ +LOCAL_INLINE RGM_CoreResetStatusType RGM_HWA_GetCPU1OutResetFlag(void) +{ + uint8_t u8TmpVal = (uint8_t)(RGM->C1_RST & RGM_C1_RST_C1_OUT_OF_RST_MASK) >> RGM_C1_RST_C1_OUT_OF_RST_SHIFT; + return (RGM_CoreResetStatusType)u8TmpVal; +} + +/** + * @brief Issue a CPU1 system software reset. + * + */ +LOCAL_INLINE void RGM_HWA_CPU1_SystemSoftWareReset(void) +{ + RGM->C1_RST |= (uint32_t)RGM_C1_RST_C1_SWRST_MASK; +} + +/** + * @brief Read CPU1 last reset flag + * + * @return CPU1 last reset flag + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadCPU1LastResetFlag(void) +{ + return (uint32_t)RGM->C1_SRS; +} + +/** + * @brief Release CPU1. After writing, this bit will be locked + * + */ +LOCAL_INLINE void RGM_HWA_ReleaseCPU1(void) +{ + RGM->C1_RLS |= (uint32_t)RGM_C1_RLS_C1_RELEASE_MASK; +} + +/** + * @brief Get the CPU1 reset interrupt flag + * + * @return true CPU1 reset interrupt happens + * @return false CPU1 reset interrupt not happened or cleared + */ +LOCAL_INLINE bool RGM_HWA_GetCPU1IntFlag(void) +{ + uint32_t u32TmpVal = (RGM->C1_RIC & RGM_C1_RIC_C1_RIC_RST_MASK) >> RGM_C1_RIC_C1_RIC_RST_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the CPU1 reset interrupt flag + * + */ +LOCAL_INLINE void RGM_HWA_ClearCPU1IntFlag(void) +{ + RGM->C1_RIC |= (uint32_t)RGM_C1_RIC_C1_RIC_RST_MASK; +} + +/** + * @brief Set whether to enable CPU1 reset interrupt to CPU0 + * + * @param bEnable whether to enable CPU1 reset interrupt to CPU0 + */ +LOCAL_INLINE void RGM_HWA_SetC1IntToC0EnableFlag(bool bEnable) +{ + RGM->C1_RIC = (RGM->C1_RIC & ~RGM_C1_RIC_C1_RIC_TOC0_MASK) | RGM_C1_RIC_C1_RIC_TOC0(bEnable); +} + +/** + * @brief Read CPU1 all reset flag before POR,SSRS register is reset on POR only + * + * @return CPU1 all reset flag before POR + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadCPU1AllResetFlagBeforePOR(void) +{ + return (uint32_t)RGM->C1_SSRS; +} + +/** + * @brief Set C1_SSRS register + * + * @param u32Value C1_SSRS register value + */ +LOCAL_INLINE void RGM_HWA_SetC1SsrsReg(uint32_t u32Value) +{ + RGM->C1_SSRS = u32Value; +} + +/** + * @brief This api can clear all reset flag of SSRGM_C1_SSRSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +LOCAL_INLINE void RGM_HWA_ClearC1AllResetFlagAfterPOR(void) +{ + RGM->C1_SSRS = (uint32_t)(RGM_SSRS_ALLFLAG|RGM_C1_SSRS_C1_SWRST_MASK| + RGM_C1_SSRS_C1_INTM_MASK|RGM_C1_SSRS_C1_WDOG_MASK| + RGM_C1_SSRS_C1_SYSRST_MASK|RGM_C1_SSRS_C1_LOCKUP_MASK); +} +#endif + +#if RGM_C2_SUPPORT + +/** + * @brief Set C2_CFG register + * + * @param u32Value C2_CFG register value + */ +LOCAL_INLINE void RGM_HWA_SetC2CfgReg(uint32_t u32Value) +{ + RGM->C2_CFG = u32Value; +} + +/** + * @brief Get C2_CFG register + * + * @return C2_CFG register value + */ +LOCAL_INLINE uint32_t RGM_HWA_GetC2CfgReg(void) +{ + return RGM->C2_CFG; +} + +/** + * @brief Enable CPU2 reset to trigger system reset + * + * @param eCPU2SystemReset The CPU2 reset that triggers the system reset + */ +LOCAL_INLINE void RGM_HWA_EnableCPU2SystemResetFlag(RGM_CoreRstTrigSysRstMangerType eCPU2SystemReset) +{ + RGM->C2_CFG |= (uint32_t)((uint32_t)eCPU2SystemReset & (RGM_C2_CFG_C2_LOCKUP_EN_MASK | RGM_C2_CFG_C2_SYSRST_EN_MASK | RGM_C2_CFG_C2_WDOG_EN_MASK | + RGM_C2_CFG_C2_INTM_EN_MASK | RGM_C2_CFG_C2_SWRST_EN_MASK)); +} + +/** + * @brief Disable CPU2 reset to trigger system reset + * + * @param eCPU2SystemReset The CPU2 reset that triggers the system reset + */ +LOCAL_INLINE void RGM_HWA_DisableCPU2SystemResetFlag(RGM_CoreRstTrigSysRstMangerType eCPU2SystemReset) +{ + RGM->C2_CFG &= ~(uint32_t)((uint32_t)eCPU2SystemReset & (RGM_C2_CFG_C2_LOCKUP_EN_MASK | RGM_C2_CFG_C2_SYSRST_EN_MASK | RGM_C2_CFG_C2_WDOG_EN_MASK | + RGM_C2_CFG_C2_INTM_EN_MASK | RGM_C2_CFG_C2_SWRST_EN_MASK)); +} + +/** + * @brief Enable CPU2 interrupt + * + * @param u32CPU2ResetInterrupt CPU2 related interrupt type + */ +LOCAL_INLINE void RGM_HWA_EnableCPU2InterruptFlag(uint32_t u32CPU2ResetInterrupt) +{ + RGM->C2_CFG |= (uint32_t)(u32CPU2ResetInterrupt & (RGM_C2_CFG_C2_SWRST_IE_MASK | RGM_C2_CFG_C2_INTM_IE_MASK | RGM_C2_CFG_C2_WDOG_IE_MASK | + RGM_C2_CFG_C2_SYSRST_IE_MASK | RGM_C2_CFG_C2_LOCKUP_IE_MASK)); +} + +/** + * @brief Disable CPU2 interrupts + * + * @param u32CPU2ResetInterrupt CPU2 related interrupt type + */ +LOCAL_INLINE void RGM_HWA_DisableCPU2InterruptFlag(uint32_t u32CPU2ResetInterrupt) +{ + RGM->C2_CFG &= ~(uint32_t)(u32CPU2ResetInterrupt & (RGM_C2_CFG_C2_SWRST_IE_MASK | RGM_C2_CFG_C2_INTM_IE_MASK | RGM_C2_CFG_C2_WDOG_IE_MASK | + RGM_C2_CFG_C2_SYSRST_IE_MASK | RGM_C2_CFG_C2_LOCKUP_IE_MASK)); +} + +/** + * @brief Get the status of CPU2 core related reset configured as system reset + * + * @return CPU2 core related reset configured as system reset + */ +LOCAL_INLINE uint32_t RGM_HWA_GetCPU2SystemResetFlag(void) +{ + return (uint32_t)(RGM->C2_CFG & (RGM_C2_CFG_C2_LOCKUP_EN_MASK | RGM_C2_CFG_C2_SYSRST_EN_MASK | RGM_C2_CFG_C2_WDOG_EN_MASK | + RGM_C2_CFG_C2_INTM_EN_MASK | RGM_C2_CFG_C2_SWRST_EN_MASK)); +} + +/** + * @brief Get enabling status of CPU2 core related reset interrupt + * + * @return Interrupt enabling status of CPU2 core related reset + */ +LOCAL_INLINE uint32_t RGM_HWA_GetCPU2ResetInterrupt(void) +{ + return (uint32_t)(RGM->C2_CFG & (RGM_C2_CFG_C2_SWRST_IE_MASK | RGM_C2_CFG_C2_INTM_IE_MASK | RGM_C2_CFG_C2_WDOG_IE_MASK | + RGM_C2_CFG_C2_SYSRST_IE_MASK | RGM_C2_CFG_C2_LOCKUP_IE_MASK)); +} + +/** + * @brief Get the CPU2 exit reset flag + * + * @return RGM_CPU_OUT_RST_UNDER CPU2 is under reset + * @return RGM_CPU_OUT_RST_OUT CPU2 is out of reset + */ +LOCAL_INLINE RGM_CoreResetStatusType RGM_HWA_GetCPU2OutResetFlag(void) +{ + uint8_t u8TmpVal = (uint8_t)(RGM->C2_RST & RGM_C2_RST_C2_OUT_OF_RST_MASK) >> RGM_C2_RST_C2_OUT_OF_RST_SHIFT; + return (RGM_CoreResetStatusType)u8TmpVal; +} + +/** + * @brief Issue a CPU2 software reset. + * + */ +LOCAL_INLINE void RGM_HWA_CPU2_SystemSoftWareReset(void) +{ + RGM->C2_RST |= (uint32_t)RGM_C2_RST_C2_SWRST_MASK; +} + +/** + * @brief Read CPU2 last reset flag + * + * @return CPU2 last reset flag + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadCPU2LastResetFlag(void) +{ + return (uint32_t)RGM->C2_SRS; +} + +/** + * @brief Release CPU2. After writing, this bit will be locked + * + */ +LOCAL_INLINE void RGM_HWA_ReleaseCPU2(void) +{ + RGM->C2_RLS |= (uint32_t)RGM_C2_RLS_C2_RELEASE_MASK; +} + +/** + * @brief Get the CPU2 reset interrupt flag + * + * @return true CPU2 reset interrupt happens + * @return false CPU2 reset interrupt not happened or cleared + */ +LOCAL_INLINE bool RGM_HWA_GetCPU2IntFlag(void) +{ + uint32_t u32TmpVal = (RGM->C2_RIC & RGM_C2_RIC_C2_RIC_RST_MASK) >> RGM_C2_RIC_C2_RIC_RST_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the CPU2 reset interrupt flag + * + */ +LOCAL_INLINE void RGM_HWA_ClearCPU2IntFlag(void) +{ + RGM->C2_RIC |= (uint32_t)RGM_C2_RIC_C2_RIC_RST_MASK; +} + +/** + * @brief Set whether to enable CPU2 reset interrupt to CPU0 + * + */ +LOCAL_INLINE void RGM_HWA_SetC2IntToC0EnableFlag(bool bEnable) +{ + RGM->C2_RIC = (RGM->C2_RIC & ~RGM_C2_RIC_C2_RIC_TOC0_MASK) | RGM_C2_RIC_C2_RIC_TOC0(bEnable); +} + +/** + * @brief Set whether to enable CPU2 reset interrupt to CPU1 + * + */ +LOCAL_INLINE void RGM_HWA_SetC2IntToC1EnableFlag(bool bEnable) +{ + RGM->C2_RIC = (RGM->C2_RIC & ~RGM_C2_RIC_C2_RIC_TOC13_MASK) | RGM_C2_RIC_C2_RIC_TOC13(bEnable); +} + +/** + * @brief Set whether to enable CPU1 reset interrupt to CPU2 + * + * @param bEnable whether to enable CPU1 reset interrupt to CPU2 + */ +LOCAL_INLINE void RGM_HWA_SetC1IntToC2EnableFlag(bool bEnable) +{ + RGM->C1_RIC = (RGM->C1_RIC & ~RGM_C1_RIC_C1_RIC_TOC23_MASK) | RGM_C1_RIC_C1_RIC_TOC23(bEnable); +} + +/** + * @brief Read CPU2 all reset flag before POR,SSRS register is reset on POR only + * + * @return CPU2 all reset flag before POR + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadCPU2AllResetFlagBeforePOR(void) +{ + return (uint32_t)RGM->C2_SSRS; +} + +/** + * @brief Set C2_SSRS register + * + * @param u32Value C2_SSRS register value + */ +LOCAL_INLINE void RGM_HWA_SetC2SsrsReg(uint32_t u32Value) +{ + RGM->C2_SSRS = u32Value; +} + +/** + * @brief This api can clear all reset flag of SSRGM_C2_SSRSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +LOCAL_INLINE void RGM_HWA_ClearC2AllResetFlagAfterPOR(void) +{ + RGM->C2_SSRS = (uint32_t)(RGM_SSRS_ALLFLAG|RGM_C2_SSRS_C2_SWRST_MASK| + RGM_C2_SSRS_C2_INTM_MASK|RGM_C2_SSRS_C2_WDOG_MASK| + RGM_C2_SSRS_C2_SYSRST_MASK|RGM_C2_SSRS_C2_LOCKUP_MASK); +} +#endif + +#if RGM_C3_SUPPORT +/** + * @brief Set PORSW Key register + * + * @param u32Value PORSW register value + */ +LOCAL_INLINE void RGM_HWA_SetPORSWKEY(uint32_t u32Value) +{ + RGM->PORSW = (RGM->PORSW & ~RGM_PORSW_KEY_MASK) | RGM_PORSW_KEY(u32Value); +} + +/** + * @brief Set PORSW SWE register + * + * @param u8Value PORSW SWE register value + */ +LOCAL_INLINE void RGM_HWA_SetPORSWSWE(uint8_t u8Value) +{ + RGM->PORSW = (RGM->PORSW & ~RGM_PORSW_SWE_MASK) | RGM_PORSW_SWE(u8Value); +} + +/** + * @brief Get PORSW SWE register + * + * @return PORSW SWE register value + */ +LOCAL_INLINE uint32_t RGM_HWA_GetPORSWSWE(void) +{ + uint32_t u32Value = (RGM->PORSW | RGM_PORSW_SWE_MASK) >> RGM_PORSW_SWE_SHIFT; + return u32Value; +} + +/** + * @brief Set C3_CFG register + * + * @param u32Value C3_CFG register value + */ +LOCAL_INLINE void RGM_HWA_SetC3CfgReg(uint32_t u32Value) +{ + RGM->C3_CFG = u32Value; +} + +/** + * @brief Get C3_CFG register + * + * @return C3_CFG register value + */ +LOCAL_INLINE uint32_t RGM_HWA_GetC3CfgReg(void) +{ + return RGM->C3_CFG; +} + +/** + * @brief Enable CPU3 reset to trigger system reset + * + * @param eCPU3SystemReset The CPU3 reset that triggers the system reset + */ +LOCAL_INLINE void RGM_HWA_EnableCPU3SystemResetFlag(RGM_CoreRstTrigSysRstMangerType eCPU3SystemReset) +{ + RGM->C3_CFG |= (uint32_t)((uint32_t)eCPU3SystemReset & (RGM_C3_CFG_C3_LOCKUP_EN_MASK | RGM_C3_CFG_C3_SYSRST_EN_MASK | RGM_C3_CFG_C3_WDOG_EN_MASK | + RGM_C3_CFG_C3_INTM_EN_MASK | RGM_C3_CFG_C3_SWRST_EN_MASK)); +} + +/** + * @brief Disable CPU3 reset to trigger system reset + * + * @param eCPU3SystemReset The CPU3 reset that triggers the system reset + */ +LOCAL_INLINE void RGM_HWA_DisableCPU3SystemResetFlag(RGM_CoreRstTrigSysRstMangerType eCPU3SystemReset) +{ + RGM->C3_CFG &= ~(uint32_t)((uint32_t)eCPU3SystemReset & (RGM_C3_CFG_C3_LOCKUP_EN_MASK | RGM_C3_CFG_C3_SYSRST_EN_MASK | RGM_C3_CFG_C3_WDOG_EN_MASK | + RGM_C3_CFG_C3_INTM_EN_MASK | RGM_C3_CFG_C3_SWRST_EN_MASK)); +} + +/** + * @brief Enable CPU3 interrupt + * + * @param u32CPU3ResetInterrupt CPU3 related interrupt type + */ +LOCAL_INLINE void RGM_HWA_EnableCPU3InterruptFlag(uint32_t u32CPU3ResetInterrupt) +{ + RGM->C3_CFG |= (uint32_t)(u32CPU3ResetInterrupt & (RGM_C3_CFG_C3_SWRST_IE_MASK | RGM_C3_CFG_C3_INTM_IE_MASK | RGM_C3_CFG_C3_WDOG_IE_MASK | + RGM_C3_CFG_C3_SYSRST_IE_MASK | RGM_C3_CFG_C3_LOCKUP_IE_MASK)); +} + +/** + * @brief Disable CPU3 interrupts + * + * @param u32CPU3ResetInterrupt CPU3 related interrupt type + */ +LOCAL_INLINE void RGM_HWA_DisableCPU3InterruptFlag(uint32_t u32CPU3ResetInterrupt) +{ + RGM->C3_CFG &= ~(uint32_t)(u32CPU3ResetInterrupt & (RGM_C3_CFG_C3_SWRST_IE_MASK | RGM_C3_CFG_C3_INTM_IE_MASK | RGM_C3_CFG_C3_WDOG_IE_MASK | + RGM_C3_CFG_C3_SYSRST_IE_MASK | RGM_C3_CFG_C3_LOCKUP_IE_MASK)); +} + +/** + * @brief Get the status of CPU3 core related reset configured as system reset + * + * @return CPU3 core related reset configured as system reset + */ +LOCAL_INLINE uint32_t RGM_HWA_GetCPU3SystemResetFlag(void) +{ + return (uint32_t)(RGM->C3_CFG & (RGM_C3_CFG_C3_LOCKUP_EN_MASK | RGM_C3_CFG_C3_SYSRST_EN_MASK | RGM_C3_CFG_C3_WDOG_EN_MASK | + RGM_C3_CFG_C3_INTM_EN_MASK | RGM_C3_CFG_C3_SWRST_EN_MASK)); +} + +/** + * @brief Get enabling status of CPU3 core related reset interrupt + * + * @return Interrupt enabling status of CPU3 core related reset + */ +LOCAL_INLINE uint32_t RGM_HWA_GetCPU3ResetInterrupt(void) +{ + return (uint32_t)(RGM->C3_CFG & (RGM_C3_CFG_C3_SWRST_IE_MASK | RGM_C3_CFG_C3_INTM_IE_MASK | RGM_C3_CFG_C3_WDOG_IE_MASK | + RGM_C3_CFG_C3_SYSRST_IE_MASK | RGM_C3_CFG_C3_LOCKUP_IE_MASK)); +} + +/** + * @brief Get the CPU3 exit reset flag + * + * @return RGM_CPU_OUT_RST_UNDER CPU3 is under reset + * @return RGM_CPU_OUT_RST_OUT CPU3 is out of reset + */ +LOCAL_INLINE RGM_CoreResetStatusType RGM_HWA_GetCPU3OutResetFlag(void) +{ + uint8_t u8TmpVal = (uint8_t)(RGM->C3_RST & RGM_C3_RST_C3_OUT_OF_RST_MASK) >> RGM_C3_RST_C3_OUT_OF_RST_SHIFT; + return (RGM_CoreResetStatusType)u8TmpVal; +} + +/** + * @brief Issue a CPU3 software reset. + * + */ +LOCAL_INLINE void RGM_HWA_CPU3_SystemSoftWareReset(void) +{ + RGM->C3_RST |= (uint32_t)RGM_C3_RST_C3_SWRST_MASK; +} + +/** + * @brief Read CPU3 last reset flag + * + * @return CPU3 last reset flag + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadCPU3LastResetFlag(void) +{ + return (uint32_t)RGM->C3_SRS; +} + +/** + * @brief Release CPU3. After writing, this bit will be locked + * + */ +LOCAL_INLINE void RGM_HWA_ReleaseCPU3(void) +{ + RGM->C3_RLS |= (uint32_t)RGM_C3_RLS_C3_RELEASE_MASK; +} + +/** + * @brief Get the CPU3 reset interrupt flag + * + * @return true CPU3 reset interrupt happens + * @return false CPU3 reset interrupt not happened or cleared + */ +LOCAL_INLINE bool RGM_HWA_GetCPU3IntFlag(void) +{ + uint32_t u32TmpVal = (RGM->C3_RIC & RGM_C3_RIC_C3_RIC_RST_MASK) >> RGM_C3_RIC_C3_RIC_RST_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the CPU3 reset interrupt flag + * + */ +LOCAL_INLINE void RGM_HWA_ClearCPU3IntFlag(void) +{ + RGM->C3_RIC |= (uint32_t)RGM_C3_RIC_C3_RIC_RST_MASK; +} + +/** + * @brief Set whether to enable CPU3 reset interrupt to CPU1 + * + */ +LOCAL_INLINE void RGM_HWA_SetC3IntToC12EnableFlag(bool bEnable) +{ + RGM->C3_RIC = (RGM->C3_RIC & ~RGM_C3_RIC_C3_RIC_TOC12_MASK) | RGM_C3_RIC_C3_RIC_TOC12(bEnable); +} + +/** + * @brief Set whether to enable CPU3 reset interrupt to CPU0 + * + */ +LOCAL_INLINE void RGM_HWA_SetC3IntToC0EnableFlag(bool bEnable) +{ + RGM->C3_RIC = (RGM->C3_RIC & ~RGM_C3_RIC_C3_RIC_TOC0_MASK) | RGM_C3_RIC_C3_RIC_TOC0(bEnable); +} + +/** + * @brief Read CPU3 all reset flag before POR,SSRS register is reset on POR only + * + * @return CPU3 all reset flag before POR + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadCPU3AllResetFlagBeforePOR(void) +{ + return (uint32_t)RGM->C3_SSRS; +} + +/** + * @brief Set C3_SSRS register + * + * @param u32Value C3_SSRS register value + */ +LOCAL_INLINE void RGM_HWA_SetC3SsrsReg(uint32_t u32Value) +{ + RGM->C3_SSRS = u32Value; +} + +/** + * @brief This api can clear all reset flag of SSRGM_C3_SSRSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +LOCAL_INLINE void RGM_HWA_ClearC3AllResetFlagAfterPOR(void) +{ + RGM->C3_SSRS = (uint32_t)0xE01FF9FFU; +} +#endif + + +/** @}*/ + +#endif /* #if RGM_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_RGM_H_ */ diff --git a/Inc/HwA_rtc.h b/Inc/HwA_rtc.h new file mode 100644 index 0000000..350ee42 --- /dev/null +++ b/Inc/HwA_rtc.h @@ -0,0 +1,362 @@ +/** + * @file HwA_rtc.h + * @author Flagchip + * @brief rtc hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip076 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip120 N/A Change version and release + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_RTC_H_ +#define HWA_INCLUDE_HWA_RTC_H_ + + +#include "device_header.h" + +#if RTC_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_rtc HwA_rtc + * @ingroup module_driver_rtc + * @{ + */ + +/********* Local typedef ************/ + +/** + * @brief in the second interrupt mode, this type indicates the interrupt frequency. + * in the clkout mode , this type indicates the clkout frequency . + * + * */ +typedef enum +{ + RTC_FREQ_1HZ = 0, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 1Hz */ + RTC_FREQ_2HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 2Hz */ + RTC_FREQ_4HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 4Hz */ + RTC_FREQ_8HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 8Hz */ + RTC_FREQ_16HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 16Hz */ + RTC_FREQ_32hZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 32Hz */ + RTC_FREQ_64HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 64Hz */ + RTC_FREQ_128HZ /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 128Hz */ +} RTC_ClkoutSecIntFreqType; +/********* Local inline function ************/ + +/** + * @brief Read second value + * + * @param pRtc the base address of the pRtc instance. + * @return Second value + */ +LOCAL_INLINE uint32_t RTC_HWA_ReadSecondValue(RTC_Type *const pRtc) +{ + uint32_t u32SecondValue0, u32SecondValue1; + do + { + u32SecondValue0 = pRtc->SR; + u32SecondValue1 = pRtc->SR; + }while (u32SecondValue0 != u32SecondValue1); + return u32SecondValue0; +} + +/** + * @brief Read RTC SR overflow flag + * + * @param pRtc the base address of the pRtc instance. + * @return true means Overflow flag is 1 ;false means Overflow flag is 0. + */ +LOCAL_INLINE bool RTC_HWA_ReadOverflowFlag(RTC_Type *const pRtc) +{ + return (bool)(((pRtc->STR & (uint32_t)RTC_STR_TOF_MASK)!=0u)? true:false); +} + +/** + * @brief Read RTC IER overflow enable bit + * + * @param pRtc the base address of the pRtc instance. + * @return true means enable Overflow Interrupt ;false means disable Overflow Interrupt + */ +LOCAL_INLINE bool RTC_HWA_ReadOverflowEnable(RTC_Type *const pRtc) +{ + return (bool)(((pRtc->IER & (uint32_t)RTC_IER_TOIE_MASK)!=0u) ? true:false); +} + +/** + * @brief Read RTC alarm flag + * + * @param pRtc the base address of the pRtc instance. + * @return true means alarm flag is 1 ;false means alarm flag is 0. + */ +LOCAL_INLINE bool RTC_HWA_ReadAlarmFlag(RTC_Type *const pRtc) +{ + return (bool)(((pRtc->STR & (uint32_t)RTC_STR_TAF_MASK)!=0u)?true:false); +} + +/** + * @brief Read RTC alarm Enable + * + * @param pRtc the base address of the pRtc instance. + * @return true means enable alarm Interrupt ;false means disable alarm Interrupt + */ +LOCAL_INLINE bool RTC_HWA_ReadAlarmEnable(RTC_Type *const pRtc) +{ + return (bool)(((pRtc->IER & (uint32_t)RTC_IER_TAIE_MASK)!=0u)?true:false); +} + +/** + * @brief Read RTC second interrupt Enable + * + * @param pRtc the base address of the pRtc instance. + * @return true means enable second Interrupt ;false means disable second Interrupt + */ +LOCAL_INLINE bool RTC_HWA_ReadSecondEnable(RTC_Type *const pRtc) +{ + return (bool)(((pRtc->IER & (uint32_t)RTC_IER_TSIE_MASK)!=0u)?true:false); +} + +/** + * @brief Read RTC Compensation Interbal + * + * @param pRtc the base address of the pRtc instance. + * @return Compensation Interbal + */ +LOCAL_INLINE uint8_t RTC_HWA_ReadCompInterval(RTC_Type *const pRtc) +{ + return (uint8_t)((pRtc->COMPR & (uint32_t)RTC_COMPR_CIC_MASK) >> RTC_COMPR_CIC_SHIFT); +} + +/** + * @brief Read RTC Compensation Value + * + * @param pRtc the base address of the pRtc instance. + * @return Compensation Value + */ +LOCAL_INLINE uint8_t RTC_HWA_ReadCompValue(RTC_Type *const pRtc) +{ + return (uint8_t)((pRtc->COMPR & (uint32_t)RTC_COMPR_TCV_MASK) >> RTC_COMPR_TCV_SHIFT); +} + +/** + * @brief Sets the RTC compare interval. + * + * @param pRtc the base address of the pRtc instance. + * @param u8Interval The compare interval reload value, in seconds. + */ +LOCAL_INLINE void RTC_HWA_SetCompInterval(RTC_Type *const pRtc, uint8_t u8Interval) +{ + pRtc->COMPR = ((pRtc->COMPR & ~RTC_COMPR_CIR_MASK) | (uint32_t)(u8Interval << RTC_COMPR_CIR_SHIFT)); +} + +/** + * @brief Sets the RTC compare value. + * + * @param pRtc the base address of the pRtc instance. + * @param u8Value The compare value, in ticks. + */ +LOCAL_INLINE void RTC_HWA_SetCompValue(RTC_Type *const pRtc, uint8_t u8Value) +{ + pRtc->COMPR = ((pRtc->COMPR & ~RTC_COMPR_TCR_MASK) | (uint32_t)(u8Value << RTC_COMPR_TCR_SHIFT)); +} + +/** + * @brief Set RTC prescaler register + * + * @param pRtc the base address of the pRtc instance. + * @param u16Value PR register value + */ +LOCAL_INLINE void RTC_HWA_SetPrescalerCounterValue(RTC_Type *const pRtc, uint16_t u16Value) +{ + pRtc->PR = (uint32_t)u16Value; + pRtc->PR = (uint32_t)u16Value; +} + +/** + * @brief Set RTC seconds register + * + * @param pRtc the base address of the pRtc instance. + * @param u32Value SR register value + */ +LOCAL_INLINE void RTC_HWA_SetSecondCounterValue(RTC_Type *const pRtc, uint32_t u32Value) +{ + pRtc->SR = u32Value; +} + +/** + * @brief Set RTC alarm value + * + * @param pRtc the base address of the pRtc instance. + * @param u32Value TAR register value + */ +LOCAL_INLINE void RTC_HWA_SetAlarmCounterValue(RTC_Type *const pRtc, uint32_t u32Value) +{ + pRtc->AR = u32Value; +} + +/** + * @brief Set RTC interrupt value + * + * @param pRtc the base address of the pRtc instance. + * @param u32Value IER register value + */ +LOCAL_INLINE void RTC_HWA_SetInterruptValue(RTC_Type *const pRtc, uint32_t u32Value) +{ + pRtc->IER = u32Value; +} + +/** + * @brief Configure control register + * + * @param pRtc the base address of the pRtc instance. + * @param u32Value Control value + */ +LOCAL_INLINE void RTC_HWA_ConfigControl(RTC_Type *const pRtc, uint32_t u32Value) +{ + pRtc->CR = u32Value; +} + +/** + * @brief Enable RTC time counter + * + * @param pRtc the base address of the pRtc instance. + */ +LOCAL_INLINE void RTC_HWA_EnableRtcCounter(RTC_Type *const pRtc) +{ + uint32_t u32RegValue = pRtc->STR; + u32RegValue |= (uint32_t)RTC_STR_TCE_MASK; + u32RegValue &= ~(uint32_t)0x8u; + pRtc->STR = u32RegValue; +} + +/** + * @brief Set RTC_CLKOUT is from the 32.768 khz clock + * + * @param pRtc the base address of the pRtc instance. + */ +LOCAL_INLINE void RTC_HWA_SetClkoutFreqStable(RTC_Type *const pRtc) +{ + pRtc->CR |= (uint32_t)RTC_CR_CKPS_MASK; +} + +/** + * @brief Enable alarm interrupt + * + * @param pRtc the base address of the pRtc instance. + * @param bEnable Indicates whether to enable the interrupt. true: Enable interrupt, false: Disable interrupt. + */ +LOCAL_INLINE void RTC_HWA_EnableAlarmInterrupt(RTC_Type *const pRtc, bool bEnable) +{ + pRtc->IER = (pRtc->IER & ~(uint32_t)RTC_IER_TAIE_MASK) | RTC_IER_TAIE(bEnable); +} + +/** + * @brief Enable second interrupt + * + * @param pRtc the base address of the pRtc instance. + * @param bEnable A boolean indicating whether to enable (true) or disable (false) the interrupt. + */ +LOCAL_INLINE void RTC_HWA_EnableSecondInterrupt(RTC_Type *const pRtc, bool bEnable) +{ + pRtc->IER = (pRtc->IER & ~(uint32_t)RTC_IER_TSIE_MASK) | RTC_IER_TSIE(bEnable); +} + +/** + * @brief Enable overflow interrupt + * + * @param pRtc the base address of the pRtc instance. + * @param bEnable Boolean value indicating whether to enable (true) or disable (false) the interrupt. + */ +LOCAL_INLINE void RTC_HWA_EnableOverflowInterrupt(RTC_Type *const pRtc, bool bEnable) +{ + pRtc->IER = (pRtc->IER & ~(uint32_t)RTC_IER_TOIE_MASK) | RTC_IER_TOIE(bEnable); +} + +/** + * @brief Unlock lock/status/control/compensation register + * + * @param pRtc the base address of the pRtc instance. + */ +LOCAL_INLINE void RTC_HWA_UnlockStatusControlCompensationReg(RTC_Type *const pRtc) +{ + pRtc->LR |= (uint32_t)(RTC_LR_LRL_MASK | RTC_LR_STRL_MASK | RTC_LR_CRL_MASK | RTC_LR_CPL_MASK); +} + +/** + * @brief Set second interrupt and RTC_CLKOUT frequency + * + * @param pRtc the base address of the pRtc instance. + * @param eFreq Frequency value + */ +LOCAL_INLINE void RTC_HWA_SetSecondAndClkoutFreq(RTC_Type *const pRtc, RTC_ClkoutSecIntFreqType eFreq) +{ + uint32_t u32RegValue = pRtc->IER; + pRtc->IER &= ~(uint32_t)RTC_IER_TSIE_MASK; + pRtc->IER = (u32RegValue & ~(uint32_t)RTC_IER_TSIC_MASK) | RTC_IER_TSIC(eFreq); +} + +/** + * @brief Disable RTC time counter + * + * @param pRtc the base address of the pRtc instance. + */ +LOCAL_INLINE void RTC_HWA_DisableRtcCounter(RTC_Type *const pRtc) +{ + pRtc->STR &= ~(uint32_t)(RTC_STR_TCE_MASK | 0x8u); +} + +/** + * @brief Set RTC_CLKOUT is from the prescaler output clock selected by IER[TSIC] + * + * @param pRtc the base address of the pRtc instance. + */ +LOCAL_INLINE void RTC_HWA_SetClkoutFromSelectFreq(RTC_Type *const pRtc) +{ + pRtc->CR &= ~(uint32_t)RTC_CR_CKPS_MASK; +} + +/** + * @brief Disable alarm interrupt + * + * @param pRtc the base address of the pRtc instance. + */ +LOCAL_INLINE void RTC_HWA_DisableAlarmInterrupt(RTC_Type *const pRtc) +{ + pRtc->IER &= ~(uint32_t)RTC_IER_TAIE_MASK; +} + +/** + * @brief Disable second interrupt + * + * @param pRtc the base address of the pRtc instance. + */ +LOCAL_INLINE void RTC_HWA_DisableSecondInterrupt(RTC_Type *const pRtc) +{ + pRtc->IER &= ~(uint32_t)RTC_IER_TSIE_MASK; +} + +/** + * @brief Disable overflow interrupt + * + * @param pRtc the base address of the pRtc instance. + */ +LOCAL_INLINE void RTC_HWA_DisableOverflowInterrupt(RTC_Type *const pRtc) +{ + pRtc->IER &= ~(uint32_t)RTC_IER_TOIE_MASK; +} + +#endif + +/** @}*/ /* HwA_RTC */ +#endif /* HWA_INCLUDE_HWA_RTC_H_ */ diff --git a/Inc/HwA_scg.h b/Inc/HwA_scg.h new file mode 100644 index 0000000..6a804c1 --- /dev/null +++ b/Inc/HwA_scg.h @@ -0,0 +1,1101 @@ +/** + * @file HwA_SCG.h + * @author Flagchip + * @brief SCG hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip055 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip055 N/A Change version and release + ******************************************************************************** */ + + +#ifndef _HWA_SCG_H_ +#define _HWA_SCG_H_ + +#include "device_header.h" + +#if SCG_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_scg HwA_scg + * @ingroup module_driver_scg + * @{ + */ + +/********* macros ************/ +/** @brief PLL related */ +#define SCG_PLLCSR_LK_MASK 0x800000u +#define SCG_PLLCSR_EN_MASK 0x1u +#define SCG_PLLCSR_CMRE_MASK 0x20000u +#define SCG_PLLCSR_CMRE_SHIFT 17u +#define SCG_PLLCSR_CMRE(x) (((uint32_t)(((uint32_t)(x))<_pll_##CSR = val +#define SCG_HWA_SetPllCsr(pll, val) _SCG_HWA_SetPllCsr(pll, val) + +#define _SCG_HWA_UnlockPllCsr(_pll_) SCG->_pll_##CSR &= ~(uint32_t)SCG_PLLCSR_LK_MASK +#define SCG_HWA_UnlockPllCsr(pll) _SCG_HWA_UnlockPllCsr(pll) + +#define _SCG_HWA_LockPllCsr(_pll_) SCG->_pll_##CSR |= (uint32_t)SCG_PLLCSR_LK_MASK +#define SCG_HWA_LockPllCsr(pll) _SCG_HWA_LockPllCsr(pll) + +#define _SCG_HWA_EnablePllClockMonitor(_pll_) SCG->_pll_##CSR |= (uint32_t)SCG_PLLCSR_CM_MASK +#define SCG_HWA_EnablePllClockMonitor(pll) _SCG_HWA_EnablePllClockMonitor(pll) + +#define _SCG_HWA_EnablePllClockMonitorReset(_pll_) SCG->_pll_##CSR |= (uint32_t)SCG_PLLCSR_CMRE_MASK +#define SCG_HWA_EnablePllClockMonitorReset(pll) _SCG_HWA_EnablePllClockMonitorReset(pll) + +#define _SCG_HWA_SetPllCfg(_pll_, val) SCG->_pll_##CFG = val +#define SCG_HWA_SetPllCfg(pll, val) _SCG_HWA_SetPllCfg(pll, val) + +#define _SCG_HWA_SetPllDiv(_pll_, val) SCG->_pll_##DIV = val +#define SCG_HWA_SetPllDiv(pll, val) _SCG_HWA_SetPllDiv(pll, val) + +#define _SCG_HWA_EnablePll(_pll_) SCG->_pll_##CSR |= (uint32_t)(SCG_PLLCSR_EN_MASK) +#define SCG_HWA_EnablePll(pll) _SCG_HWA_EnablePll(pll) + +#define _SCG_HWA_EnablePllDiv(_pll_) SCG->_pll_##DIV |= (uint32_t)(SCG_PLLDIV_DIVL_EN_MASK | SCG_PLLDIV_DIVM_EN_MASK | SCG_PLLDIV_DIVH_EN_MASK) +#define SCG_HWA_EnablePllDiv(pll) _SCG_HWA_EnablePllDiv(pll) + +#define _SCG_HWA_DisablePllDiv(_pll_) SCG->_pll_##DIV &= (~(uint32_t)(SCG_PLLDIV_DIVL_EN_MASK | SCG_PLLDIV_DIVM_EN_MASK | SCG_PLLDIV_DIVH_EN_MASK)) +#define SCG_HWA_DisablePllDiv(pll) _SCG_HWA_DisablePllDiv(pll) + +#define _SCG_HWA_GetPllMult(_pll_) ((uint16_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_MULT_MASK) >> SCG_PLLCFG_MULT_SHIFT)) +#define SCG_HWA_GetPllMult(pll) _SCG_HWA_GetPllMult(pll) + +#define _SCG_HWA_GetPllPrediv(_pll_) ((uint8_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_PREDIV_MASK) >> SCG_PLLCFG_PREDIV_SHIFT)) +#define SCG_HWA_GetPllPrediv(pll) _SCG_HWA_GetPllPrediv(pll) + +#define _SCG_HWA_GetPllPstdiv(_pll_) ((uint8_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_PSTDIV_MASK) >> SCG_PLLCFG_PSTDIV_SHIFT)) +#define SCG_HWA_GetPllPstdiv(pll) _SCG_HWA_GetPllPstdiv(pll) + +#define _SCG_HWA_GetPllPstdiv1(_pll_) ((uint8_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_PSTDIV1_MASK) >> SCG_PLLCFG_PSTDIV1_SHIFT)) +#define SCG_HWA_GetPllPstdiv1(pll) _SCG_HWA_GetPllPstdiv1(pll) + +#define _SCG_HWA_GetPllSrc(_pll_) ((uint8_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_SOURCE_MASK) >> SCG_PLLCFG_SOURCE_SHIFT)) +#define SCG_HWA_GetPllSrc(pll) _SCG_HWA_GetPllSrc(pll) + +/* Clock valid, locked and div related */ +#define _SCG_HWA_GetPllLocked(_clock_) ((bool)((((uint32_t)SCG->_clock_##CSR & (uint32_t)SCG_##_clock_##CSR_PLLLK_MASK) != 0U) ? true : false)) +#define SCG_HWA_GetPllLocked(_clock_) _SCG_HWA_GetPllLocked(_clock_) + +#define _SCG_HWA_GetClockValid(_clock_) ((bool)((((uint32_t)SCG->_clock_##CSR & (uint32_t)SCG_##_clock_##CSR_VLD_MASK) != 0U) ? true : false)) +#define SCG_HWA_GetClockValid(_clock_) _SCG_HWA_GetClockValid(_clock_) + +#define _SCG_HWA_GetClockDiv(_clock_) (uint32_t)SCG->_clock_##DIV +#define SCG_HWA_GetClockDiv(_clock_) _SCG_HWA_GetClockDiv(_clock_) + +#define _SCG_HWA_GetTrimLocked(_clock_) ((bool)((((uint32_t)SCG->_clock_##CSR & (uint32_t)SCG_##_clock_##CSR_TRLK_MASK) != 0U) ? true : false)) +#define SCG_HWA_GetTrimLocked(_clock_) _SCG_HWA_GetTrimLocked(_clock_) + +#define SCG_CLOCKDIV_DIVL_ACK_MASK 0x40000000u +#define SCG_CLOCKDIV_DIVM_ACK_MASK 0x20000000u +#define SCG_CLOCKDIV_DIVH_ACK_MASK 0x10000000u +#define SCG_CLOCKDIV_DIV_ACK_MASK 0x70000000u +#define SCG_CLOCKDIV_DIV_ACK_MASK_SHIFT 0x7u +#define SCG_CLOCKDIV_DIVL_ACK_SHIFT 30u +#define SCG_CLOCKDIV_DIVM_ACK_SHIFT 29u +#define SCG_CLOCKDIV_DIVH_ACK_SHIFT 28u +#define SCG_CLOCKDIV_DIV_ACK_SHIFT 28u + +#define SCG_CLOCKDIV_DIVL_EN_MASK 0x4000000u +#define SCG_CLOCKDIV_DIVM_EN_MASK 0x2000000u +#define SCG_CLOCKDIV_DIVH_EN_MASK 0x1000000u +#define SCG_CLOCKDIV_DIVL_EN_SHIFT 26u +#define SCG_CLOCKDIV_DIVM_EN_SHIFT 25u +#define SCG_CLOCKDIV_DIVH_EN_SHIFT 24u + +#define SCG_CLOCKDIV_DIVL_VAL_MASK 0x70000u +#define SCG_CLOCKDIV_DIVM_VAL_MASK 0x700u +#define SCG_CLOCKDIV_DIVH_VAL_MASK 0x7u +#define SCG_CLOCKDIV_DIVL_VAL_SHIFT 16u +#define SCG_CLOCKDIV_DIVM_VAL_SHIFT 8u +#define SCG_CLOCKDIV_DIVH_VAL_SHIFT 0u + +#define SCG_CHECK_DIVL_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIVL_ACK_MASK) >> SCG_CLOCKDIV_DIVL_ACK_SHIFT) +#define SCG_CHECK_DIVM_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIVM_ACK_MASK) >> SCG_CLOCKDIV_DIVM_ACK_SHIFT) +#define SCG_CHECK_DIVH_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIVH_ACK_MASK) >> SCG_CLOCKDIV_DIVH_ACK_SHIFT) +#define SCG_CHECK_DIV_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIV_ACK_MASK) >> SCG_CLOCKDIV_DIV_ACK_SHIFT) +#define SCG_CHECK_DIVL_EN(reg_val) ((reg_val & SCG_CLOCKDIV_DIVL_EN_MASK) >> SCG_CLOCKDIV_DIVL_EN_SHIFT) +#define SCG_CHECK_DIVM_EN(reg_val) ((reg_val & SCG_CLOCKDIV_DIVM_EN_MASK) >> SCG_CLOCKDIV_DIVM_EN_SHIFT) +#define SCG_CHECK_DIVH_EN(reg_val) ((reg_val & SCG_CLOCKDIV_DIVH_EN_MASK) >> SCG_CLOCKDIV_DIVH_EN_SHIFT) +#define SCG_GET_DIVL_VAL(reg_val) ((0U == ((reg_val & SCG_CLOCKDIV_DIVL_VAL_MASK) >> SCG_CLOCKDIV_DIVL_VAL_SHIFT)) ? 1U : ((reg_val & SCG_CLOCKDIV_DIVL_VAL_MASK) >> SCG_CLOCKDIV_DIVL_VAL_SHIFT)) +#define SCG_GET_DIVM_VAL(reg_val) ((0U == ((reg_val & SCG_CLOCKDIV_DIVM_VAL_MASK) >> SCG_CLOCKDIV_DIVM_VAL_SHIFT)) ? 1U : ((reg_val & SCG_CLOCKDIV_DIVM_VAL_MASK) >> SCG_CLOCKDIV_DIVM_VAL_SHIFT)) +#define SCG_GET_DIVH_VAL(reg_val) ((0U == ((reg_val & SCG_CLOCKDIV_DIVH_VAL_MASK) >> SCG_CLOCKDIV_DIVH_VAL_SHIFT)) ? 1U : ((reg_val & SCG_CLOCKDIV_DIVH_VAL_MASK) >> SCG_CLOCKDIV_DIVH_VAL_SHIFT)) +#define SCG_CALCULATE_DIVL_FREQ(clk_freq, reg_val) (((1U == SCG_CHECK_DIVL_EN(reg_val)) && (clk_freq != UNKNOWN_CLOCK)) ? (uint32_t)clk_freq >> (uint8_t)(SCG_GET_DIVL_VAL(reg_val) - 1U) : (uint32_t)UNKNOWN_CLOCK) +#define SCG_CALCULATE_DIVM_FREQ(clk_freq, reg_val) (((1U == SCG_CHECK_DIVM_EN(reg_val)) && (clk_freq != UNKNOWN_CLOCK)) ? (uint32_t)clk_freq >> (uint8_t)(SCG_GET_DIVM_VAL(reg_val) - 1U) : (uint32_t)UNKNOWN_CLOCK) +#define SCG_CALCULATE_DIVH_FREQ(clk_freq, reg_val) (((1U == SCG_CHECK_DIVH_EN(reg_val)) && (clk_freq != UNKNOWN_CLOCK)) ? (uint32_t)clk_freq >> (uint8_t)(SCG_GET_DIVH_VAL(reg_val) - 1U) : (uint32_t)UNKNOWN_CLOCK) + + +/********* Local inline function ************/ + +/** + * @brief Get clock out configure register CLKOUTSEL value + */ +LOCAL_INLINE uint8_t SCG_HWA_GetClkOutSel(void) +{ + return (uint8_t)(((uint32_t)SCG->CLKOUTCFG & SCG_CLKOUTCFG_CLKOUTSEL_MASK) >> SCG_CLKOUTCFG_CLKOUTSEL_SHIFT); +} + +/** + * @brief Get clock out configure register value + */ +LOCAL_INLINE uint32_t SCG_HWA_GetClkOutCfg(void) +{ + return SCG->CLKOUTCFG; +} + +/********* Sosc Register interface ************/ +/** + * @brief Unlock SOSC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_UnlockSoscCsr(void) +{ + SCG->SOSCCSR &= ~(uint32_t)(SCG_SOSCCSR_LK_MASK); +} + +/** + * @brief Lock SOSC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_LockSoscCsr(void) +{ + SCG->SOSCCSR |= (uint32_t)(SCG_SOSCCSR_LK_MASK); +} + +/** + * @brief Enable SOSC clock monitor + * + */ +LOCAL_INLINE void SCG_HWA_EnableSoscClockMonitor(void) +{ + SCG->SOSCCSR |= (uint32_t)(SCG_SOSCCSR_CM_MASK); +} + +/** + * @brief Enable SOSC clock monitor Reset + * + */ +LOCAL_INLINE void SCG_HWA_EnableSoscClockMonitorReset(void) +{ + SCG->SOSCCSR |= (uint32_t)(SCG_SOSCCSR_CMRE_MASK); +} + +/** + * @brief Set SOSC enable + */ +LOCAL_INLINE void SCG_HWA_EnableSosc(void) +{ + SCG->SOSCCSR |= (uint32_t)SCG_SOSCCSR_EN_MASK; +} + +/** + * @brief Diable SOSC + */ +LOCAL_INLINE void SCG_HWA_DisableSosc(void) +{ + SCG->SOSCCSR &= ~(uint32_t)SCG_SOSCCSR_EN_MASK; +} + +/** + * @brief Set SOSC CFG register value + * + * @param u32CfgValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSoscCfg(uint32_t u32CfgValue) +{ + SCG->SOSCCFG = u32CfgValue; +} + +/** + * @brief Set SOSC CSR register value + * + * @param u32CsrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSoscCsr(uint32_t u32CsrValue) +{ + SCG->SOSCCSR = u32CsrValue; +} + +/** + * @brief Get SOSC CSR register value + * + */ +LOCAL_INLINE uint32_t SCG_HWA_GetSoscCsr(void) +{ + return (uint32_t)SCG->SOSCCSR; +} + +/********* Fosc Register interface ************/ +/** + * @brief Enable FOSC + */ +LOCAL_INLINE void SCG_HWA_EnableFosc(void) +{ + SCG->FOSCCSR |= (uint32_t)SCG_FOSCCSR_EN_MASK; +} + +/** + * @brief Disable FOSC + */ +LOCAL_INLINE void SCG_HWA_DisableFosc(void) +{ + SCG->FOSCCSR &= ~SCG_FOSCCSR_EN_MASK; +} + +/** + * @brief Set FOSCCFG register value + * + * @param u32CfgValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFoscCfg(uint32_t u32CfgValue) +{ + SCG->FOSCCFG = u32CfgValue; +} + +/** + * @brief Set FOSCCSR register value + * + * @param u32CsrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFoscCsr(uint32_t u32CsrValue) +{ + SCG->FOSCCSR = u32CsrValue; +} + +/** + * @brief Get FOSCCSR register value + * + */ +LOCAL_INLINE uint32_t SCG_HWA_GetFoscCsr(void) +{ + return (uint32_t)SCG->FOSCCSR; +} + +/** + * @brief Unlock FOSC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_UnlockFoscCsr(void) +{ + SCG->FOSCCSR &= ~(uint32_t)(SCG_FOSCCSR_LK_MASK); +} + +/** + * @brief lock FOSC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_LockFoscCsr(void) +{ + SCG->FOSCCSR |= (uint32_t)(SCG_FOSCCSR_LK_MASK); +} + +/** + * @brief Enable FOSC clock monitor + * + */ +LOCAL_INLINE void SCG_HWA_EnableFoscClockMonitor(void) +{ + SCG->FOSCCSR |= (uint32_t)(SCG_FOSCCSR_CM_MASK); +} + +/** + * @brief Enable FOSC clock monitor Reset + * + */ +LOCAL_INLINE void SCG_HWA_EnableFoscClockMonitorReset(void) +{ + SCG->FOSCCSR |= (uint32_t)(SCG_FOSCCSR_CMRE_MASK); +} + +/** + * @brief enable FOSCDIV as user manual request sequence + */ +LOCAL_INLINE void SCG_HWA_EnableFoscDiv(void) +{ + SCG->FOSCDIV |= (uint32_t)(SCG_FOSCDIV_DIVL_EN_MASK + | SCG_FOSCDIV_DIVM_EN_MASK + | SCG_FOSCDIV_DIVH_EN_MASK); +} + +/** + * @brief Disable FOSCDIV as user manual request sequence + */ +LOCAL_INLINE void SCG_HWA_DiableFoscDiv(void) +{ + SCG->FOSCDIV &= ~(uint32_t)(SCG_FOSCDIV_DIVL_EN_MASK + | SCG_FOSCDIV_DIVM_EN_MASK + | SCG_FOSCDIV_DIVH_EN_MASK); +} + +/** + * @brief Set FOSCDIV register value + * + * @param u32DivValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFoscDiv(uint32_t u32DivValue) +{ + SCG->FOSCDIV = u32DivValue; +} + +#if SCG_LP_WKPWDG_SUPPORT +/** + * @brief Set Low Power Wakeup WDOG Register + * + * @param u8MSBVal Most Significant value, if OSC is 40M + * and FOSC not valid after 1.8ms wakeup, + * the chip will reset and RGM register will + * report clock error reset reason. + */ +LOCAL_INLINE void SCG_HWA_SetWKPWDG(uint8_t u8MSBVal) +{ + SCG->WKPWDG = SCG_WKPWDG_MSB(u8MSBVal) | SCG_WKPWDG_EN_MASK; +} +#endif + + +/********* Sirc Register interface ************/ +/** + * @brief Set SIRCCSR register value + * + * @param u32CsrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSircCsr(uint32_t u32CsrValue) +{ + SCG->SIRCCSR = u32CsrValue; +} + +/** + * @brief Get SIRCCSR register value + * + */ +LOCAL_INLINE uint32_t SCG_HWA_GetSircCsr(void) +{ + return (uint32_t)SCG->SIRCCSR; +} + +/** + * @brief Unlock SIRC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_UnlockSircCsr(void) +{ + SCG->SIRCCSR &= ~(uint32_t)SCG_SIRCCSR_LK_MASK; +} + +/** + * @brief Lock SIRC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_LockSircCsr(void) +{ + SCG->SIRCCSR |= (uint32_t)SCG_SIRCCSR_LK_MASK; +} + +/** + * @brief Enable SIRC clock monitor + * + */ +LOCAL_INLINE void SCG_HWA_EnableSircClockMonitor(void) +{ + SCG->SIRCCSR |= (uint32_t)(SCG_SIRCCSR_CM_MASK); +} + +/** + * @brief Set SIRCDIV register value + * + * @param u32DivValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSircDiv(uint32_t u32DivValue) +{ + SCG->SIRCDIV = u32DivValue; +} + +/** + * @brief Disable SIRCDIV as user manual request sequence + */ +LOCAL_INLINE void SCG_HWA_DiableSircDiv(void) +{ + SCG->SIRCDIV &= ~(uint32_t)(SCG_SIRCDIV_DIVL_EN_MASK + | SCG_SIRCDIV_DIVM_EN_MASK + | SCG_SIRCDIV_DIVH_EN_MASK); +} + +/** + * @brief enable FIRCDIV as user manual request sequence + */ +LOCAL_INLINE void SCG_HWA_EnableSircDiv(void) +{ + SCG->SIRCDIV |= (uint32_t)(SCG_SIRCDIV_DIVL_EN_MASK + | SCG_SIRCDIV_DIVM_EN_MASK + | SCG_SIRCDIV_DIVH_EN_MASK); +} + +/** + * @brief Set SIRCTCFG register value for SIRC Trim configure. + * + * @param u32TcfgValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSircTcfg(uint32_t u32TcfgValue) +{ + SCG->SIRCTCFG = u32TcfgValue; +} + +/********* Sirc32k Register interface ************/ +/** + * @brief Enable SIRC32KCSR register + * + */ +LOCAL_INLINE void SCG_HWA_EnableSirc32kCsr(void) +{ + SCG->SIRC32KCSR |= (uint32_t)SCG_SIRC32KCSR_EN_MASK; +} + +/** + * @brief Disable SIRC32KCSR register + * + */ +LOCAL_INLINE void SCG_HWA_DisableSirc32kCsr(void) +{ + SCG->SIRC32KCSR &= ~(uint32_t)SCG_SIRC32KCSR_EN_MASK; +} + +/** + * @brief Unlock SIRC32K CSR register + */ +LOCAL_INLINE void SCG_HWA_UnlockSirc32kCsr(void) +{ + SCG->SIRC32KCSR &= ~(uint32_t)(SCG_SIRC32KCSR_LK_MASK); +} + +/** + * @brief Lock SIRC32K CSR register + */ +LOCAL_INLINE void SCG_HWA_LockSirc32kCsr(void) +{ + SCG->SIRC32KCSR |= (uint32_t)(SCG_SIRC32KCSR_LK_MASK); +} + +/********* Firc Register interface ************/ +/** + * @brief Get FIRC CSR register value. + */ +LOCAL_INLINE uint32_t SCG_HWA_GetFircCsr(void) +{ + return (uint32_t)SCG->FIRCCSR; +} + +/** + * @brief Enable FIRC. + */ +LOCAL_INLINE void SCG_HWA_EnableFirc(void) +{ + SCG->FIRCCSR |= (uint32_t)SCG_FIRCCSR_EN_MASK; +} + +/** + * @brief Unlock FIRC CSR register + */ +LOCAL_INLINE void SCG_HWA_UnlockFircCsr(void) +{ + SCG->FIRCCSR &= ~(uint32_t)(SCG_FIRCCSR_LK_MASK); +} + +/** + * @brief Lock FIRC CSR register + */ +LOCAL_INLINE void SCG_HWA_LockFircCsr(void) +{ + SCG->FIRCCSR |= (uint32_t)(SCG_FIRCCSR_LK_MASK); +} + +/** + * @brief Enable FIRC clock monitor + * + */ +LOCAL_INLINE void SCG_HWA_EnableFircClockMonitor(void) +{ + SCG->FIRCCSR |= (uint32_t)(SCG_FIRCCSR_CM_MASK); +} + +/** + * @brief Disable FIRC. + */ +LOCAL_INLINE void SCG_HWA_DisableFirc(void) +{ + SCG->FIRCCSR &= ~(uint32_t)SCG_FIRCCSR_EN_MASK; +} + +/** + * @brief Set FIRCCSR register value + * + * @param u32CsrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFircCsr(uint32_t u32CsrValue) +{ + SCG->FIRCCSR = u32CsrValue; +} + +/** + * @brief Set FIRCCFG register value + * + * @param u32CfgValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFircCfg(uint32_t u32CfgValue) +{ + SCG->FIRCCFG = u32CfgValue; +} + +/** + * @brief Set FOSCDIV register value + * + * @param u32DivValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFircDiv(uint32_t u32DivValue) +{ + SCG->FIRCDIV = u32DivValue; +} + +/** + * @brief Disable FIRCDIV as user manual request sequence + */ +LOCAL_INLINE void SCG_HWA_DiableFircDiv(void) +{ + SCG->FIRCDIV &= ~(uint32_t)(SCG_FIRCDIV_DIVL_EN_MASK + | SCG_FIRCDIV_DIVM_EN_MASK + | SCG_FIRCDIV_DIVH_EN_MASK); +} + +/** + * @brief enable FIRCDIV as user manual request sequence + */ +LOCAL_INLINE void SCG_HWA_EnableFircDiv(void) +{ + SCG->FIRCDIV |= (uint32_t)(SCG_FIRCDIV_DIVL_EN_MASK + | SCG_FIRCDIV_DIVM_EN_MASK + | SCG_FIRCDIV_DIVH_EN_MASK); +} + +/** + * @brief Set FIRCTCFG register value for FIRC clock trim configure. + * + * @param u32TcfgValue configured register value. + */ +LOCAL_INLINE void SCG_HWA_SetFircTcfg(uint32_t u32TcfgValue) +{ + SCG->FIRCTCFG = u32TcfgValue; +} + +/********* System clock Register interface ************/ +/** + * @brief Set system clock CCR register value + * + * @param u32CcrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetCCR(uint32_t u32CcrValue) +{ + SCG->CCR = u32CcrValue; +} + +/** + * @brief Set system clock CCR register value + * + */ +LOCAL_INLINE uint32_t SCG_HWA_GetCCR(void) +{ + return SCG->CCR; +} + +/** + * @brief Set system clock CSR register value + * + */ +LOCAL_INLINE uint32_t SCG_HWA_GetCSR(void) +{ + return SCG->CSR; +} + +/********* Pll0 Register interface ************/ +/** + * @brief Get PLL0CSR register value. + * + * @return PLL0CSR register value. + */ +LOCAL_INLINE uint32_t SCG_HWA_GetPll0Csr(void) +{ + return SCG->PLL0CSR; +} + +/** + * @brief Get PLL0CFG register value. + * + * @return PLL0CFG register value. + */ +LOCAL_INLINE uint32_t SCG_HWA_GetPll0Cfg(void) +{ + return SCG->PLL0CFG; +} + +/********* Pll1 Register interface ************/ +#if SCG_PLL1_SUPPORT +/** + * @brief Get PLL1CSR register value. + * + * @return PLL1CSR register value. + */ +LOCAL_INLINE uint32_t SCG_HWA_GetPll1Csr(void) +{ + return SCG->PLL1CSR; +} +#endif /* SCG_PLL1_SUPPORT */ + +/** + * @brief Set system clock + * + * @param u8SystemCLock System clock value + */ +LOCAL_INLINE void SCG_HWA_SetSystemClock(uint8_t u8SystemCLock) +{ + SCG->CCR = ((SCG->CCR & ~(uint32_t)SCG_CCR_SCS_MASK) | SCG_CCR_SCS(u8SystemCLock)); +} + +/** + * @brief Get system clock source. used to calculate system clock frequency at startup. + * used to check if the target clock soure successfully switched. + * @return uint8_t. system clock source. + */ +LOCAL_INLINE uint8_t SCG_HWA_GetSysClkSrc(void) +{ + return (uint8_t)(((uint32_t)(SCG->CSR) & (uint32_t)SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT); +} + +/** + * @brief Get system clock valid status, use this status to check system clock update finished or not. + * @return bool. true as updated; false as not updated. + */ +LOCAL_INLINE bool SCG_HWA_GetSysClkUPRD(void) +{ + return (bool)((((uint32_t)SCG->CSR & (uint32_t)SCG_CSR_CCR_UPRD_MASK) != 0U) ? true : false); +} + +/** + * @brief Get system clock Divcore. used to calculate core clock frequency at startup. + * @return uint8_t. system clock Divcore. + */ +LOCAL_INLINE uint8_t SCG_HWA_GetSysClkDivCore(void) +{ + return (uint8_t)(((uint32_t)(SCG->CSR) & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT); +} + +/** + * @brief Get system clock Divbus. used to calculate bus clock frequency at startup. + * @return uint8_t. system clock Divbus. + */ +LOCAL_INLINE uint8_t SCG_HWA_GetSysClkDivBus(void) +{ + return (uint8_t)(((uint32_t)(SCG->CSR) & SCG_CSR_DIVBUS_MASK) >> SCG_CSR_DIVBUS_SHIFT); +} + +/** + * @brief Get system clock Divslow. used to calculate slow clock frequency at startup. + * @return uint8_t. system clock Divslow. + */ +LOCAL_INLINE uint8_t SCG_HWA_GetSysClkDivSlow(void) +{ + return (uint8_t)(((uint32_t)(SCG->CSR) & SCG_CSR_DIVSLOW_MASK) >> SCG_CSR_DIVSLOW_SHIFT); +} + +/********* Clkout Register interface ************/ +/** + * @brief Select clock out source + * + * @param u8ClkOutSel Clock out select + */ +LOCAL_INLINE void SCG_HWA_SetClkOutSel(uint8_t u8ClkOutSel) +{ + SCG->CLKOUTCFG = ((SCG->CLKOUTCFG & ~(uint32_t)SCG_CLKOUTCFG_CLKOUTSEL_MASK) | SCG_CLKOUTCFG_CLKOUTSEL(u8ClkOutSel)); +} + +/** + * @brief Set Nvm clock source + * + * @param u32NvmClkMask Nvm clock source mask + */ +LOCAL_INLINE void SCG_HWA_SetNvmClk(uint32_t u32NvmClkMask) +{ + SCG->CLKOUTCFG &= ~(uint32_t)(SCG_CLKOUTCFG_NVMCLK_FIRC_MASK | SCG_CLKOUTCFG_NVMCLK_SIRC_MASK); + SCG->CLKOUTCFG |= u32NvmClkMask; +} + +/** + * @brief Set CMU4 clock source + * + * @param u32Cmu4ClkMask CMU4 clock source mask + */ +LOCAL_INLINE void SCG_HWA_SetCmu4Clk(uint32_t u32Cmu4ClkMask) +{ + SCG->CLKOUTCFG &= ~(uint32_t)(SCG_CLKOUTCFG_CMU4CLK_FOSC_MASK | SCG_CLKOUTCFG_CMU4CLK_SIRC_MASK); + SCG->CLKOUTCFG |= u32Cmu4ClkMask; +} + +/** + * @brief Check and clear SIRC clock error + * + */ +LOCAL_INLINE bool SCG_HWA_CheckAndClearSircClkErr(void) +{ + bool bFlag = false; + if (SCG_SIRCCSR_ERR_MASK == (SCG->SIRCCSR & SCG_SIRCCSR_ERR_MASK)) + { + SCG->SIRCCSR |= (uint32_t)SCG_SIRCCSR_ERR_MASK; + bFlag = true; + } + return bFlag; +} + +/** + * @brief Check and clear SOSC clock error + * + */ +LOCAL_INLINE bool SCG_HWA_CheckAndClearSoscClkErr(void) +{ + bool bFlag = false; + if (SCG_SOSCCSR_ERR_MASK == (SCG->SOSCCSR & SCG_SOSCCSR_ERR_MASK)) + { + SCG->SOSCCSR |= (uint32_t)SCG_SOSCCSR_ERR_MASK; + bFlag = true; + } + return bFlag; +} + +/** + * @brief Check and clear FOSC clock error + * + */ +LOCAL_INLINE bool SCG_HWA_CheckAndClearFoscClkErr(void) +{ + bool bFlag = false; + if (SCG_FOSCCSR_ERR_MASK == (SCG->FOSCCSR & SCG_FOSCCSR_ERR_MASK)) + { + SCG->FOSCCSR |= (uint32_t)SCG_FOSCCSR_ERR_MASK; + bFlag = true; + } + return bFlag; +} + +/** + * @brief Check and clear PLL0 clock error + * + */ +LOCAL_INLINE bool SCG_HWA_CheckAndClearPll0ClkErr(void) +{ + bool bFlag = false; + if (SCG_PLL0CSR_ERR_MASK == (SCG->PLL0CSR & SCG_PLL0CSR_ERR_MASK)) + { + SCG->PLL0CSR |= (uint32_t)SCG_PLL0CSR_ERR_MASK; + bFlag = true; + } + return bFlag; +} + +#if SCG_PLL1_SUPPORT +/** + * @brief Check and clear PLL1 clock error + * + */ +LOCAL_INLINE bool SCG_HWA_CheckAndClearPll1ClkErr(void) +{ + bool bFlag = false; + if (SCG_PLL1CSR_ERR_MASK == (SCG->PLL1CSR & SCG_PLL1CSR_ERR_MASK)) + { + SCG->PLL1CSR |= (uint32_t)SCG_PLL1CSR_ERR_MASK; + bFlag = true; + } + return bFlag; +} +#endif /* SCG_PLL1_SUPPORT */ + +/** + * @brief Check and clear FIRC clock error + * + */ +LOCAL_INLINE bool SCG_HWA_CheckAndClearFircClkErr(void) +{ + bool bFlag = false; + if (SCG_FIRCCSR_ERR_MASK == (SCG->FIRCCSR & SCG_FIRCCSR_ERR_MASK)) + { + SCG->FIRCCSR |= (uint32)SCG_FIRCCSR_ERR_MASK; + bFlag = (boolean)TRUE; + } + return bFlag; +} + +#if SCG_PLLX_CLK1_SUPPORT +/** + * @brief Enable PLL0CK1 output + */ +LOCAL_INLINE void SCG_HWA_EnablePLL0CLK1Output(void) +{ + SCG->PLL0CSR |= (uint32_t)SCG_PLL0CSR_CK1EN_MASK; +} + +/** + * @brief Disable PLL0CK1 output + */ +LOCAL_INLINE void SCG_HWA_DisablePLL0CLK1Output(void) +{ + SCG->PLL0CSR &= ~(uint32_t)SCG_PLL0CSR_CK1EN_MASK; +} + +/** + * @brief Enable PLL0 Force Off. + */ +LOCAL_INLINE void SCG_HWA_EnablePll0ForceOff(void) +{ + SCG->PLL0PDIS = 0xFC200001; +} + +#if SCG_PLL1_SUPPORT +/** + * @brief Enable PLL1CK1 output + */ +LOCAL_INLINE void SCG_HWA_EnablePLL1CLK1Output(void) +{ + SCG->PLL1CSR |= (uint32_t)SCG_PLL1CSR_CK1EN_MASK; +} + +/** + * @brief Disable PLL1CK1 output + */ +LOCAL_INLINE void SCG_HWA_DisablePLL1CLK1Output(void) +{ + SCG->PLL1CSR &= ~(uint32_t)SCG_PLL1CSR_CK1EN_MASK; +} + +/** + * @brief Enable PLL1 Force Off. + */ +LOCAL_INLINE void SCG_HWA_EnablePll1ForceOff(void) +{ + SCG->PLL1PDIS = 0xFC200001; +} +#endif /* SCG_PLL1_SUPPORT */ +#else +/** + * @brief Set configuration register protection enable/disable . + * + * @param bEnable Enable/Disable protection + */ +LOCAL_INLINE void SCG_HWA_SetCfgRegProt(boolean bEnable) +{ + SCG->CFG = (SCG_CFG_PORT_LOCK_KEY(0x5A5A) | SCG_CFG_PORT_CFG_EN(bEnable)); +} + +/** + * @brief Set PLL0 fast start enable/disable . + * + */ +LOCAL_INLINE void SCG_HWA_EnablePll0FastStart(void) +{ + SCG->PLL0SCFG |= SCG_PLL0SCFG_FS_EN(1U); +} + +/** + * @brief Set PLL1 fast start enable/disable . + * + */ +LOCAL_INLINE void SCG_HWA_EnablePll1FastStart(void) +{ + SCG->PLL1SCFG |= SCG_PLL1SCFG_FS_EN(1U); +} + +#endif /* SCG_PLLX_CLK1_SUPPORT */ + +#if SCG_PLL0_CLK2_SUPPORT +/** + * @brief Enable PLL0CK2 output + */ +LOCAL_INLINE void SCG_HWA_EnablePLL0CLK2Output(void) +{ + SCG->PLL0CSR |= (uint32_t)SCG_PLL0CSR_CK2EN_MASK; +} + +/** + * @brief Disable PLL0CK2 output + */ +LOCAL_INLINE void SCG_HWA_DisablePLL0CLK2Output(void) +{ + SCG->PLL0CSR &= ~(uint32_t)SCG_PLL0CSR_CK2EN_MASK; +} + +/** + * @brief Set PLL0ECFG register + */ +LOCAL_INLINE void SCG_HWA_SetPll0Ecfg(uint32_t u32Value) +{ + uint32 u32Temp; + SCG->PLL0ECFG = u32Value; + /* PLL0ECFG will active after PLL0CFG is written */ + u32Temp = SCG->PLL0CFG; + SCG->PLL0CFG = u32Temp; +} + +/** + * @brief Get PLL0ECFG register value + */ +LOCAL_INLINE uint32_t SCG_HWA_GetPll0Ecfg(void) +{ + return SCG->PLL0ECFG; +} + +#endif /* SCG_PLL0_CLK2_SUPPORT */ + +/********* CRC Register interface ************/ +/** + * @brief Generate SCG register CRC value + */ +LOCAL_INLINE void SCG_HWA_GenCrcVal(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_GEN_MASK; +} + +/** + * @brief Enable SCG register CRC check + */ +LOCAL_INLINE void SCG_HWA_EnableCrcCheck(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_CHKEN_MASK; +} + +/** + * @brief Disable SCG register CRC check + */ +LOCAL_INLINE void SCG_HWA_DisableCrcCheck(void) +{ + SCG->CRCCSR &= ~(uint32_t)SCG_CRCCSR_CHKEN_MASK; +} + +/** + * @brief Enable SCG register CRC hardware trigger generate + */ +LOCAL_INLINE void SCG_HWA_EnableCrcTrigger(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_TRGEN_MASK; +} + +/** + * @brief Disable SCG register CRC hardware trigger generate + */ +LOCAL_INLINE void SCG_HWA_DisableCrcTrigger(void) +{ + SCG->CRCCSR &= ~(uint32_t)SCG_CRCCSR_TRGEN_MASK; +} + +/** + * @brief Enable SCG register CRC error output + */ +LOCAL_INLINE void SCG_HWA_EnableCrcErrorOutput(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_EOEN_MASK; +} + +/** + * @brief Disable SCG register CRC error output + */ +LOCAL_INLINE void SCG_HWA_DisableCrcErrorOutput(void) +{ + SCG->CRCCSR &= ~(uint32_t)SCG_CRCCSR_EOEN_MASK; +} + +/** + * @brief Get CRC busy status + */ +LOCAL_INLINE bool SCG_HWA_GetCrcBusyStatus(void) +{ + return (0U != (SCG->CRCCSR & (uint32_t)SCG_CRCCSR_BUSY_MASK)); +} + +/** + * @brief Get CRC error status + */ +LOCAL_INLINE bool SCG_HWA_GetCrcErrorStatus(void) +{ + return (0U != (SCG->CRCCSR & (uint32_t)SCG_CRCCSR_ERR_MASK)); +} + +/** + * @brief Clear CRC error flag + */ +LOCAL_INLINE void SCG_HWA_ClearCrcErrorFlag(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_ERR_MASK; +} + +/** + * @brief Get CRC result + */ +LOCAL_INLINE uint32_t SCG_HWA_GetCrcResult(void) +{ + return SCG->CRCRES; +} + +/** @}*/ /* HwA_SCG */ + +#endif /* #if SCG_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_SCG_H_ */ diff --git a/Inc/HwA_scm.h b/Inc/HwA_scm.h new file mode 100644 index 0000000..eabedc6 --- /dev/null +++ b/Inc/HwA_scm.h @@ -0,0 +1,724 @@ +/** + * @file HwA_scm.h + * @author flagchip + * @brief Hardware access layer for SCM + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip055 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip055 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_SCM_H_ +#define _HWA_SCM_H_ +#include "device_header.h" + +#if SCM_INSTANCE_COUNT > 0U + +/** + * @brief SCM adc trigger selection + */ +typedef enum +{ + SCM_ADC_INSTANCE_0 = 0U, + SCM_ADC_INSTANCE_1 = 1U, + SCM_ADC_INSTANCE_2 = 2U, + SCM_ADC_INSTANCE_3 = 3U, + SCM_ADC_INSTANCE_4 = 4U, + SCM_ADC_INSTANCE_5 = 5U, +} SCM_AdcInstance; + +/** + * @brief SCM adc trigger selection + */ +typedef enum +{ + SCM_ADC_TRIGGER_PTIMER = 0U, + SCM_ADC_TRIGGER_TRGSEL = 1U, +} SCM_AdcTriggerSel; + +/** + * @brief SCM adc pre-trigger selection + */ +typedef enum +{ + SCM_ADC_PRE_TRIGGER_PTIMER = 0U, + SCM_ADC_PRE_TRIGGER_TRGSEL = 1U, + SCM_ADC_PRE_TRIGGER_SCM_SOFTWARE_PRE_TRIGGER = 2U, +} SCM_AdcPreTriggerSel; + +/** + * @brief SCM software trigger source + */ +typedef enum +{ + SCM_SOFTWARE_PRE_TRIGGER_0 = 0U, /*!< SCM software pre-trigger 0 */ + SCM_SOFTWARE_PRE_TRIGGER_1 = 1U, /*!< SCM software pre-trigger 1 */ + SCM_SOFTWARE_PRE_TRIGGER_2 = 2U, /*!< SCM software pre-trigger 2 */ + SCM_SOFTWARE_PRE_TRIGGER_3 = 3U, /*!< SCM software pre-trigger 3 */ +} SCM_SoftwarePreTrigger; + +/** + * @defgroup HwA_scm HwA_scm + * @ingroup module_driver_scm + * @{ + */ + +/********* Local typedef ************/ + + +/********* Local inline function ************/ +/** + * @brief Get UIDL data(Unique identification for the chip. Loaded from NVR) + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDL(void) +{ + return SCM->UIDL; +} + +/** + * @brief Get UIDML data(Unique identification for the chip. Loaded from NVR) + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDML(void) +{ + return SCM->UIDML; +} + +/** + * @brief Get UIDMH data(Unique identification for the chip. Loaded from NVR) + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDMH(void) +{ + return SCM->UIDMH; +} + +/** + * @brief Get UIDH data(Unique identification for the chip. Loaded from NVR) + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDH(void) +{ + return SCM->UIDH; +} + +/** + * @brief Get Family Identification + * + * @return return value + */ +LOCAL_INLINE uint8_t SCM_HWA_GetData_FamilyID(void) +{ + return (uint8_t)((SCM->PARTID0 & (uint32_t)SCM_PARTID0_FAM_ID_MASK) >> (uint32_t)SCM_PARTID0_FAM_ID_SHIFT); +} + +/** + * @brief Get Revision Identification + * + * @return return value + */ +LOCAL_INLINE uint8_t SCM_HWA_GetData_RevID(void) +{ + return (uint8_t)((SCM->PARTID0 & (uint32_t)SCM_PARTID0_REVID_MASK)); +} + +/** + * @brief Set the ISM_ROUTING register value + * + * @param u32Val value to be set + */ +LOCAL_INLINE void SCM_HWA_Set_ISM_ROUTING(uint32_t u32Val) +{ + SCM->ISM_ROUTING = u32Val; +} + +/** + * @brief Get CHIPCFG0 register status + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_Get_CHIPCFG0(void) +{ + return SCM->CHIPCFG0; +} + +/** + * @brief Set the SOCMISC register value + * + * @param u32Val value to be set + */ +LOCAL_INLINE void SCM_HWA_Set_SOCMISC(uint32_t u32Val) +{ + SCM->SOCMISC = u32Val; +} + +/** + * @brief Get the SOCMISC register status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_Get_SOCMISC(void) +{ + return SCM->SOCMISC; +} + +#if SCM_GET_DEVICEID_SUPPORT +/** + * @brief Get device ID + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_DeviceID(void) +{ + return ((SCM->CHIPCFG1 & (uint32_t)SCM_CHIPCFG1_DEVICE_ID_MASK) >> (uint32_t)SCM_CHIPCFG1_DEVICE_ID_SHIFT); +} +#endif + +/** + * @brief Get SYSAP_CTRL register status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_Get_SYSAP_CTRL(void) +{ + return SCM->SYSAP_CTRL; +} + +#if SCM_CRC_SUPPORT +/** + * @brief Set the CRCCSR register value + * + * @param u32Val value to be set + */ +LOCAL_INLINE void SCM_HWA_Set_CRCCSR(uint32_t u32Val) +{ + SCM->CRCCSR = u32Val; +} + +/** + * @brief Get CRCCSR register status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_Get_CRCCSR(void) +{ + return SCM->CRCCSR; +} + +/** + * @brief Set CRC check enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetCrcCheckEnable(bool bEnable) +{ + SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_CHKEN_MASK))) | SCM_CRCCSR_CHKEN(bEnable); +} + +/** + * @brief Set CRC trigger enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetCrcTriggerEnable(bool bEnable) +{ + SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_TRGEN_MASK))) | SCM_CRCCSR_TRGEN(bEnable); +} + +/** + * @brief Set CRC error out enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetCrcErrorOutEnable(bool bEnable) +{ + SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_EOEN_MASK))) | SCM_CRCCSR_EOEN(bEnable); +} + +/** + * @brief Clear CRC error flag + */ +LOCAL_INLINE void SCM_HWA_ClearCrcErrorFlag(void) +{ + SCM->CRCCSR |= SCM_CRCCSR_ERR_MASK; +} + +/** + * @brief Get CRC Done Flag + * + * @return CRC Done Flag + */ +LOCAL_INLINE bool SCM_HWA_GetCrcDoneFlag(void) +{ + return ((SCM->CRCCSR & SCM_CRCCSR_BUY_MASK) == SCM_CRCCSR_BUY_MASK) ? false : true; +} + +/** + * @brief Set CRC software generate enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetCrcGenerateEnable(bool bEnable) +{ + SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_GEN_MASK))) | SCM_CRCCSR_GEN(bEnable); +} + +/** + * @brief Get CRC result + * + * @return CRC result + */ +LOCAL_INLINE uint32_t SCM_HWA_GetCrcResult(void) +{ + return SCM->CRCRES; +} +#endif +/** + * @brief Set the FTU_GTBC register value + * + * @param u32Val value to be set + */ +LOCAL_INLINE void SCM_HWA_Set_FTU_GTBC(uint32_t u32Val) +{ +#if defined (SCM_FTU_GTBC_FTU_GTBC_MASK) + SCM->FTU_GTBC = u32Val; +#elif defined (SCM_FTU_GTBC_FTU0_GTBC_MASK) + SCM->FTU_GTBC = u32Val; +#else +#error "No valid SCM_FTU_GTB*_FTU*_GTBC_MASK definition" +#endif +} + +#if defined(SCM_GTBC_TPU_SELECT_SUPPORT) && (SCM_GTBC_TPU_SELECT_SUPPORT) +/** + * @brief Configure TPU global time base control selection + * + * @param bEn Enable or disable TPU Global Time Base + */ +LOCAL_INLINE void SCM_HWA_ConfigTpuGTBSelect(bool bEn) +{ +#if defined(SCM_FTU_GTBC_ETPU_GTBC_MASK) + SCM->FTU_GTBC &= ~(uint32_t)SCM_FTU_GTBC_ETPU_GTBC_MASK; + SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_ETPU_GTBC(bEn); +#elif defined(SCM_FTU_GTBC_TPU_GTBC_MASK) + SCM->FTU_GTBC &= ~(uint32_t)SCM_FTU_GTBC_TPU_GTBC_MASK; + SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_TPU_GTBC(bEn); +#else +#error "No valid SCM_FTU_GTBC_*TPU definition" +#endif +} + +#endif + +/** + * @brief Set TPU clock enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_TPUClock(bool bEnable) +{ +#if defined(SCM_SUBSYSPCC_SUPPORT) && defined(SCM_SUBSYSPCC_SUPPORT) + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_CLKEN_TPU_MASK)) | + SCM_SUBSYS_PCC_CLKEN_TPU(bEnable)); +#elif (SCM_TPUPCC_SUPPORT && SCM_TPUPCC_SUPPORT) + SCM->TPU_PCC = ((SCM->TPU_PCC & (~(uint32_t)SCM_TPU_PCC_CLKEN_TPU_MASK)) | + SCM_TPU_PCC_CLKEN_TPU(bEnable)); +#else + PROCESS_UNUSED_VAR(bEnable); +#endif +} + +/** + * @brief Set SubSystem clock enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_SubSystemClock(bool bEnable) +{ +#if (SCM_FLEXHSM_PCC_SUPPORT && SCM_FLEXHSM_PCC_SUPPORT) + SCM->FLEXHSM_PCC = ((SCM->FLEXHSM_PCC & (~(uint32_t)SCM_FLEXHSM_PCC_CLKEN_FLEXHSM_MASK)) | + SCM_FLEXHSM_PCC_CLKEN_FLEXHSM(bEnable)); +#elif (SCM_SUBSYSPCC_SUPPORT && SCM_SUBSYSPCC_SUPPORT) + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_CLKEN_SUBSYS_MASK)) | + SCM_SUBSYS_PCC_CLKEN_SUBSYS(bEnable)); +#else + PROCESS_UNUSED_VAR(bEnable); +#endif +} + +#if defined(SCM_GTBC_FTU_SELECT_SUPPORT) && (SCM_GTBC_FTU_SELECT_SUPPORT) +/** + * @brief Set FTU global time base control selection + * + * @param u32SelectedFtu The GTBC mask of Selected Ftu instance,it is the or value of SCM_FTUGTBCtrlType. + * eg.u32SelectedFtu == 1 means FTU0 selected, u32SelectedFtu == 5 means FTU0 and FTU2 selected. + */ +LOCAL_INLINE void SCM_HWA_SetFtuGTBSelect(uint32_t u32SelectedFtu) +{ + SCM->FTU_GTBC |= (u32SelectedFtu & 0xFFu) << SCM_FTU_GTBC_FTU0_GTBC_SHIFT; +} + +/** + * @brief Clear FTU global time base control selection + * + * @param u32SelectedFtu The GTBC mask of Selected Ftu instance,it is the or value of SCM_FTUGTBCtrlType. + * eg.u32SelectedFtu == 1 means FTU0 selected, u32SelectedFtu == 5 means FTU0 and FTU2 selected. + */ +LOCAL_INLINE void SCM_HWA_ClearFtuGTBSelect(uint32_t u32SelectedFtu) +{ + SCM->FTU_GTBC &= ~(uint32_t)((u32SelectedFtu & 0xFFu) << SCM_FTU_GTBC_FTU0_GTBC_SHIFT); +} +#endif + +#if defined(SCM_FTU_GTBC_TSTMP_TRIG_SUPPORT) && (SCM_FTU_GTBC_TSTMP_TRIG_SUPPORT) +/** + * @brief Configure FTU Global Time Base Control Mask Register + * + * @param u8FtuIndex The selected FTU instance (must be 0 ~ 7) + * @param u32Value Value to be set (must be 0 ~ 15) + */ +LOCAL_INLINE void SCM_HWA_ConfigFtuGTBMask(uint8_t u8FtuIndex, uint32_t u32Value) +{ +#if defined(SCM_FTU_GTBEM_FTU0_GTBEM_MASK) + SCM->FTU_GTBEM = (SCM->FTU_GTBEM & (~((uint32_t)SCM_FTU_GTBEM_FTU0_GTBEM_MASK << (SCM_FTU_GTBEM_FTU0_GTBEM_WIDTH * u8FtuIndex)))) + | (((uint32_t)u32Value & SCM_FTU_GTBEM_FTU0_GTBEM_MASK) << (SCM_FTU_GTBEM_FTU0_GTBEM_WIDTH * u8FtuIndex)); +#elif defined(SCM_FTU_GTBCM_FTU0_GTBCM_MASK) + SCM->FTU_GTBCM = (SCM->FTU_GTBCM & (~((uint32_t)SCM_FTU_GTBCM_FTU0_GTBCM_MASK << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex)))) + | (((uint32_t)u32Value & SCM_FTU_GTBCM_FTU0_GTBCM_MASK) << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex)); + +#else +#error "No valid SCM_FTU_GTB*M_FTU*_GTB*M definition" +#endif +} + +/** + * @brief Clear FTU Global Time Base Control Mask Register + * + * @param u8FtuIndex The selected FTU instance (must be 0 ~ 7) + */ +LOCAL_INLINE void SCM_HWA_ClearFtuGTBMask(uint8_t u8FtuIndex) +{ +#if defined(SCM_FTU_GTBEM_FTU0_GTBEM_MASK) + SCM->FTU_GTBEM &= ~ ((uint32_t)SCM_FTU_GTBEM_FTU0_GTBEM_MASK << (SCM_FTU_GTBEM_FTU0_GTBEM_WIDTH * u8FtuIndex)); +#elif defined(SCM_FTU_GTBCM_FTU0_GTBCM_MASK) + SCM->FTU_GTBCM &= ~ ((uint32_t)SCM_FTU_GTBCM_FTU0_GTBCM_MASK << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex)); +#else +#error "No valid SCM_FTU_GTB*M_FTU*_GTB*M definition" +#endif +} +#endif + + +#if SCM_PTIMER_CHANNEL_SELECTION_SUPPORT +/** + * @brief Set the ADC_ROUTING2 register value + * + * @param u32Val value to be set + */ +LOCAL_INLINE void SCM_HWA_Set_ADC_ROUTING2(uint32_t u32Val) +{ + SCM->ADC_ROUTING2 = u32Val; +} + +/** + * @brief Get the ADC_ROUTING2 register status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_Get_ADC_ROUTING2(void) +{ + return SCM->ADC_ROUTING2; +} +#endif + +#ifdef SCM_CPU1VTOR_CPU1_INIT_VECTOR_MASK +/** + * @brief Set the CPU1VTOR register value + * + * @param u32Val value to be set + */ +LOCAL_INLINE void SCM_HWA_Set_CPU1VTOR(uint32_t u32Val) +{ + SCM->CPU1VTOR = u32Val; +} + +/** + * @brief Get the CPU1VTOR register status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_Get_CPU1VTOR(void) +{ + return SCM->CPU1VTOR; +} + +/** + * @brief Set CPU1 Vector Table Register vector initial vector + * + * @param u32Value value to be set + */ +LOCAL_INLINE void SCM_HWA_CPU1VTOR_SetVector(uint32_t u32Value) +{ + uint32_t u32RegVal = SCM->CPU1VTOR; + SCM->CPU1VTOR = ((u32RegVal & (~(uint32_t)SCM_CPU1VTOR_CPU1_INIT_VECTOR_MASK)) | SCM_CPU1VTOR_CPU1_INIT_VECTOR(u32Value)); +} +#endif + +#ifdef SCM_CPU2VTOR_CPU2_INIT_VECTOR_MASK +/** + * @brief Set the CPU2VTOR register value + * + * @param u32Val value to be set + */ +LOCAL_INLINE void SCM_HWA_Set_CPU2VTOR(uint32_t u32Val) +{ + SCM->CPU2VTOR = u32Val; +} + +/** + * @brief Get the CPU2VTOR register status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_Get_CPU2VTOR(void) +{ + return SCM->CPU2VTOR; +} + +/** + * @brief Set Core Hold Register vector initial vector + * + * @param u32Value value to be set + */ +LOCAL_INLINE void SCM_HWA_CPU2VTOR_SetVector(uint32_t u32Value) +{ + uint32_t u32RegVal = SCM->CPU2VTOR; + SCM->CPU2VTOR = ((u32RegVal & (~(uint32_t)SCM_CPU2VTOR_CPU2_INIT_VECTOR_MASK)) | SCM_CPU2VTOR_CPU2_INIT_VECTOR(u32Value)); +} +#endif + +#ifdef SCM_CPU3VTOR_CPU3_INIT_VECTOR_MASK +/** + * @brief Set the CPU3VTOR register value + * + * @param u32Val value to be set + */ +LOCAL_INLINE void SCM_HWA_Set_CPU3VTOR(uint32_t u32Val) +{ + SCM->CPU3VTOR = u32Val; +} + +/** + * @brief Get the CPU3VTOR register status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_Get_CPU3VTOR(void) +{ + return SCM->CPU3VTOR; +} + +/** + * @brief Set Core Hold Register vector initial vector + * + * @param u32Value value to be set + */ +LOCAL_INLINE void SCM_HWA_CPU3VTOR_SetVector(uint32_t u32Value) +{ + uint32_t u32RegVal = SCM->CPU3VTOR; + SCM->CPU3VTOR = ((u32RegVal & (~(uint32_t)SCM_CPU3VTOR_CPU3_INIT_VECTOR_MASK)) | SCM_CPU3VTOR_CPU3_INIT_VECTOR(u32Value)); +} +#endif + +#ifdef SCM_CORE_HOLD_CPU1_CORE_HOLD_MASK +/** + * @brief Set cpu1 hold enable status + * + * @param bEnable Enable/Disable status + */ +LOCAL_INLINE void SCM_HWA_SetCOREHOLD_Cpu1Hold(bool bEnable) +{ + if (true == bEnable) + { + SCM->CORE_HOLD |= (uint32_t)SCM_CORE_HOLD_CPU1_CORE_HOLD_MASK; + } + else + { + SCM->CORE_HOLD &= ~(uint32_t)SCM_CORE_HOLD_CPU1_CORE_HOLD_MASK; + } +} +#endif +#ifdef SCM_CORE_HOLD_CPU2_CORE_HOLD_MASK +/** + * @brief Set cpu2 hold enable status + * + * @param bEnable Enable/Disable status + */ +LOCAL_INLINE void SCM_HWA_SetCOREHOLD_Cpu2Hold(bool bEnable) +{ + if (true == bEnable) + { + SCM->CORE_HOLD |= (uint32_t)SCM_CORE_HOLD_CPU2_CORE_HOLD_MASK; + } + else + { + SCM->CORE_HOLD &= ~(uint32_t)SCM_CORE_HOLD_CPU2_CORE_HOLD_MASK; + } +} +#endif +#ifdef SCM_CORE_HOLD_CPU3_CORE_HOLD_MASK +/** + * @brief Set cpu3 hold enable status + * + * @param bEnable Enable/Disable status + */ +LOCAL_INLINE void SCM_HWA_SetCOREHOLD_Cpu3Hold(bool bEnable) +{ + if (true == bEnable) + { + SCM->CORE_HOLD |= (uint32_t)SCM_CORE_HOLD_CPU3_CORE_HOLD_MASK; + } + else + { + SCM->CORE_HOLD &= ~(uint32_t)SCM_CORE_HOLD_CPU3_CORE_HOLD_MASK; + } +} +#endif + +#if SCM_ADC_PRE_TRIGGER_SEL_SUPPORT +LOCAL_INLINE void SCM_HWA_SetAdcPretriggerSel(SCM_AdcInstance eInstance, SCM_AdcPreTriggerSel ePreTriggerSel) +{ + #if ADC_INSTANCE_COUNT > 5U + if (eInstance == SCM_ADC_INSTANCE_5) + { + SCM->ADC_ROUTING1 = (SCM->ADC_ROUTING1 & ~SCM_ADC_ROUTING1_ADC5_PRETRGSEL_MASK) | + SCM_ADC_ROUTING1_ADC5_PRETRGSEL(ePreTriggerSel); + } + else + #endif + #if ADC_INSTANCE_COUNT > 4U + if (eInstance == SCM_ADC_INSTANCE_4) + { + SCM->ADC_ROUTING1 = (SCM->ADC_ROUTING1 & ~SCM_ADC_ROUTING1_ADC4_PRETRGSEL_MASK) | + SCM_ADC_ROUTING1_ADC4_PRETRGSEL(ePreTriggerSel); + } + else + #endif + #if ADC_INSTANCE_COUNT > 3U + if (eInstance == SCM_ADC_INSTANCE_3) + { + SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC3_PRETRGSEL_MASK) | + SCM_ADC_ROUTING_ADC3_PRETRGSEL(ePreTriggerSel); + } + else + #endif + #if ADC_INSTANCE_COUNT > 2U + if (eInstance == SCM_ADC_INSTANCE_2) + { + SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC2_PRETRGSEL_MASK) | + SCM_ADC_ROUTING_ADC2_PRETRGSEL(ePreTriggerSel); + } + else + #endif + #if ADC_INSTANCE_COUNT > 1U + if (eInstance == SCM_ADC_INSTANCE_1) + { + SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC1_PRETRGSEL_MASK) | + SCM_ADC_ROUTING_ADC1_PRETRGSEL(ePreTriggerSel); + } + else + #endif + #if ADC_INSTANCE_COUNT > 0U + if (eInstance == SCM_ADC_INSTANCE_0) + { + SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC0_PRETRGSEL_MASK) | + SCM_ADC_ROUTING_ADC0_PRETRGSEL(ePreTriggerSel); + } + #endif +} +#endif + +#if SCM_ADC_TRIGGER_SEL_SUPPORT +LOCAL_INLINE void SCM_HWA_SetAdcTriggerSel(SCM_AdcInstance eInstance, SCM_AdcTriggerSel eTriggerSel) +{ + #if ADC_INSTANCE_COUNT > 5U + if (eInstance == SCM_ADC_INSTANCE_5) + { + SCM->ADC_ROUTING1 = (SCM->ADC_ROUTING1 & ~SCM_ADC_ROUTING1_ADC5_TRGSEL_MASK) | + SCM_ADC_ROUTING1_ADC5_TRGSEL(eTriggerSel); + } + else + #endif + #if ADC_INSTANCE_COUNT > 4U + if (eInstance == SCM_ADC_INSTANCE_4) + { + SCM->ADC_ROUTING1 = (SCM->ADC_ROUTING1 & ~SCM_ADC_ROUTING1_ADC4_TRGSEL_MASK) | + SCM_ADC_ROUTING1_ADC4_TRGSEL(eTriggerSel); + } + else + #endif + #if ADC_INSTANCE_COUNT > 3U + if (eInstance == SCM_ADC_INSTANCE_3) + { + SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC3_TRGSEL_MASK) | + SCM_ADC_ROUTING_ADC3_TRGSEL(eTriggerSel); + } + else + #endif + #if ADC_INSTANCE_COUNT > 2U + if (eInstance == SCM_ADC_INSTANCE_2) + { + SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC2_TRGSEL_MASK) | + SCM_ADC_ROUTING_ADC2_TRGSEL(eTriggerSel); + } + else + #endif + #if ADC_INSTANCE_COUNT > 1U + if (eInstance == SCM_ADC_INSTANCE_1) + { + SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC1_TRGSEL_MASK) | + SCM_ADC_ROUTING_ADC1_TRGSEL(eTriggerSel); + } + else + #endif + #if ADC_INSTANCE_COUNT > 0U + if (eInstance == SCM_ADC_INSTANCE_0) + { + SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC0_TRGSEL_MASK) | + SCM_ADC_ROUTING_ADC0_TRGSEL(eTriggerSel); + } + #endif +} +#endif + +#if SCM_HSADC_BIAS_FORCE_ENABLE_SUPPORT + +LOCAL_INLINE void SCM_HWA_SetHsadcBiasForceEnable(void) +{ + SCM->ADC_CFG = SCM->ADC_CFG | (1U << 31U); +} + +#endif + +/** @}*/ + +#endif /* #if SCM_INSTANCE_COUNT > 0U */ + +#endif /*#ifndef _HWA_SCM_H_ */ diff --git a/Inc/HwA_sdadc.h b/Inc/HwA_sdadc.h new file mode 100644 index 0000000..fecfed1 --- /dev/null +++ b/Inc/HwA_sdadc.h @@ -0,0 +1,5698 @@ +/** + * @file HwA_sdadc.h + * @author flagchip + * @brief Hardware access layer for SDADC + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_SDADC_H_ +#define _HWA_SDADC_H_ + +#include "device_header.h" + +#if SDADC_INSTANCE_COUNT > 0U + +#define SDADC_MSR_CHON_MASK 0x7u +#define SDADC_MSR_CHON_SHIFT 0u +#define SDADC_MSR_CHON_WIDTH 3u +#define SDADC_MSR_CHON(x) (((uint32_t)(((uint32_t)(x))<CCR0) + (int)(base))) + +/** + * @brief Get the value of CLKO2_DIS. + * Modulator Clock Output 2 Disable + * 0b - CLKO2 is enabled when MEN is asserted. + * 1b - CLKO2 is disabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CLKO2_DIS. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCLKO2_DIS(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_CLKO2_DIS_MASK) >> SDADC_CTRL_CLKO2_DIS_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set CLKO2_DIS. + * Modulator Clock Output 2 Disable + * 0b - CLKO2 is enabled when MEN is asserted. + * 1b - CLKO2 is disabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value CLKO2_DIS value. + */ +LOCAL_INLINE void SDADC_HWA_SetCLKO2_DIS(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_CLKO2_DIS_MASK) | SDADC_CTRL_CLKO2_DIS(u32Value); +} + +/** + * @brief Get the value of CLKO1_DIS. + * Modulator Clock Output 1 Disable + * 0b - CLKO1 is enabled when MEN is asserted. + * 1b - CLKO1 is disabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CLKO1_DIS. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCLKO1_DIS(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_CLKO1_DIS_MASK) >> SDADC_CTRL_CLKO1_DIS_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set CLKO1_DIS. + * Modulator Clock Output 1 Disable + * 0b - CLKO1 is enabled when MEN is asserted. + * 1b - CLKO1 is disabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value CLKO1_DIS value. + */ +LOCAL_INLINE void SDADC_HWA_SetCLKO1_DIS(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_CLKO1_DIS_MASK) | SDADC_CTRL_CLKO1_DIS(u32Value); +} + +/** + * @brief Get the value of CLKO0_DIS. + * Modulator Clock Output 0 Disable + * 0b - CLKO0 is enabled when MEN is asserted. + * 1b - CLKO0 is disabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CLKO0_DIS. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCLKO0_DIS(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_CLKO0_DIS_MASK) >> SDADC_CTRL_CLKO0_DIS_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set CLKO0_DIS. + * Modulator Clock Output 0 Disable + * 0b - CLKO0 is enabled when MEN is asserted. + * 1b - CLKO0 is disabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value CLKO0_DIS value. + */ +LOCAL_INLINE void SDADC_HWA_SetCLKO0_DIS(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_CLKO0_DIS_MASK) | SDADC_CTRL_CLKO0_DIS(u32Value); +} + +/** + * @brief Get the value of PRESCALE. + * PRE_DIV Divider Value + * 00b - No prescale. + * 01b - Divided by 2. + * 10b - Divided by 4. + * 11b - Divided by 8. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of PRESCALE. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetPRESCALE(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_PRESCALE_MASK) >> SDADC_CTRL_PRESCALE_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set PRESCALE. + * PRE_DIV Divider Value + * 00b - No prescale. + * 01b - Divided by 2. + * 10b - Divided by 4. + * 11b - Divided by 8. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value PRESCALE value. + */ +LOCAL_INLINE void SDADC_HWA_SetPRESCALE(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_PRESCALE_MASK) | SDADC_CTRL_PRESCALE(u32Value); +} + +/** + * @brief Get the value of MCLK_DIV. + * DIV Divider Value + * The (MCLK_DIV+1) sets the clock divider ratio for DIV block. + * The minimum value MCLK_DIV is 1. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of MCLK_DIV. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMCLK_DIV(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_MCLK_DIV_MASK) >> SDADC_CTRL_MCLK_DIV_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set MCLK_DIV. + * DIV Divider Value + * The (MCLK_DIV+1) sets the clock divider ratio for DIV block. + * The minimum value MCLK_DIV is 1. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value MCLK_DIV value. + */ +LOCAL_INLINE void SDADC_HWA_SetMCLK_DIV(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_MCLK_DIV_MASK) | SDADC_CTRL_MCLK_DIV(u32Value); +} + +/** + * @brief Get the value of MEN. + * Main Enable + * Setting this bit enables all Function block simultaneously if CHEN and corresponding enable bit are asserted. + * 0b - All function blocks are disabled. + * 1b - All function blocks are enabled simultaneously. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of MEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMEN(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_MEN_MASK) >> SDADC_CTRL_MEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set MEN. + * Main Enable + * Setting this bit enables all Function block simultaneously if CHEN and corresponding enable bit are asserted. + * 0b - All function blocks are disabled. + * 1b - All function blocks are enabled simultaneously. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value MEN value. + */ +LOCAL_INLINE void SDADC_HWA_SetMEN(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_MEN_MASK) | SDADC_CTRL_MEN(u32Value); +} + +/** + * @brief Get the value of MENSEL. + * Main Enable Selection + * Setting this bit to select main enable(MEN) from an enable from external of SDADC IP. By this way, all SDADC in a system can share one main enable and can be enable at the same time. + * 0b - Use internal MEN. + * 1b - Use external MEN. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of MENSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMENSEL(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_MENSEL_MASK) >> SDADC_CTRL_MENSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set MENSEL. + * Main Enable Selection + * Setting this bit to select main enable(MEN) from an enable from external of SDADC IP. By this way, all SDADC in a system can share one main enable and can be enable at the same time. + * 0b - Use internal MEN. + * 1b - Use external MEN. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value MENSEL value. + */ +LOCAL_INLINE void SDADC_HWA_SetMENSEL(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_MENSEL_MASK) | SDADC_CTRL_MENSEL(u32Value); +} + +/** + * @brief Get the value of RESET. + * Software Reset + * Used to reset all function blocks (filters, short circuit detect, etc) and all flags or status. + * Note, to reset all function domain, RESET must keep high at least 3 div_clk1 cycles. + * 0b - No reset. + * 1b - All function blocks are reset and disabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of RESET. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetRESET(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_RESET_MASK) >> SDADC_CTRL_RESET_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set RESET. + * Software Reset + * Used to reset all function blocks (filters, short circuit detect, etc) and all flags or status. + * Note, to reset all function domain, RESET must keep high at least 3 div_clk1 cycles. + * 0b - No reset. + * 1b - All function blocks are reset and disabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value RESET value. + */ +LOCAL_INLINE void SDADC_HWA_SetRESET(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_RESET_MASK) | SDADC_CTRL_RESET(u32Value); +} + +/** + * @brief Get the value of DBGM. + * Software Debug Mode Request + * This bit is writable only when MEN is asserted. + * 0b - SDADC is in Normal Mode. + * 1b - SDADC is in Debug Mode. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of DBGM. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetDBGM(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_DBGM_MASK) >> SDADC_CTRL_DBGM_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set DBGM. + * Software Debug Mode Request + * This bit is writable only when MEN is asserted. + * 0b - SDADC is in Normal Mode. + * 1b - SDADC is in Debug Mode. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value DBGM value. + */ +LOCAL_INLINE void SDADC_HWA_SetDBGM(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_DBGM_MASK) | SDADC_CTRL_DBGM(u32Value); +} + +/** + * @brief Get the value of DBGE. + * Module Enable in Debug Mode + * Enables/disables the SDADC operation in Debug mode. + * 0b - SDADC is enabled in debug mode. + * 1b - SDADC is disabled in debug mode. Need trigger again for new conversion. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of DBGE. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetDBGE(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_DBGE_MASK) >> SDADC_CTRL_DBGE_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set DBGE. + * Module Enable in Debug Mode + * Enables/disables the SDADC operation in Debug mode. + * 0b - SDADC is enabled in debug mode. + * 1b - SDADC is disabled in debug mode. Need trigger again for new conversion. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value DBGE value. + */ +LOCAL_INLINE void SDADC_HWA_SetDBGE(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_DBGE_MASK) | SDADC_CTRL_DBGE(u32Value); +} + +/** + * @brief Get the value of STRIG2. + * Software Trigger for Filter Channel 2 + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of STRIG2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSTRIG2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_STRIG2_MASK) >> SDADC_CTRL_STRIG2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set STRIG2. + * Software Trigger for Filter Channel 2 + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value STRIG2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetSTRIG2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_STRIG2_MASK) | SDADC_CTRL_STRIG2(u32Value); +} + +/** + * @brief Get the value of STRIG1. + * Software Trigger for Filter Channel 1 + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of STRIG1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSTRIG1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_STRIG1_MASK) >> SDADC_CTRL_STRIG1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set STRIG1. + * Software Trigger for Filter Channel 1 + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value STRIG1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetSTRIG1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_STRIG1_MASK) | SDADC_CTRL_STRIG1(u32Value); +} + +/** + * @brief Get the value of STRIG0. + * Software Trigger for Filter Channel 0 + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of STRIG0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSTRIG0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->CTRL & SDADC_CTRL_STRIG0_MASK) >> SDADC_CTRL_STRIG0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set STRIG0. + * Software Trigger for Filter Channel 0 + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value STRIG0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetSTRIG0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->CTRL = (pSdadc->CTRL & ~SDADC_CTRL_STRIG0_MASK) | SDADC_CTRL_STRIG0(u32Value); +} + +/** + * @brief Get the value of ZCDIE2. + * Filter Channel 2 Zero Cross Detected Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of ZCDIE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetZCDIE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NIER & SDADC_NIER_ZCDIE2_MASK) >> SDADC_NIER_ZCDIE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set ZCDIE2. + * Filter Channel 2 Zero Cross Detected Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value ZCDIE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetZCDIE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->NIER = (pSdadc->NIER & ~SDADC_NIER_ZCDIE2_MASK) | SDADC_NIER_ZCDIE2(u32Value); +} + +/** + * @brief Get the value of ZCDIE1. + * Filter Channel 1 Zero Cross Detected Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of ZCDIE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetZCDIE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NIER & SDADC_NIER_ZCDIE1_MASK) >> SDADC_NIER_ZCDIE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set ZCDIE1. + * Filter Channel 1 Zero Cross Detected Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value ZCDIE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetZCDIE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->NIER = (pSdadc->NIER & ~SDADC_NIER_ZCDIE1_MASK) | SDADC_NIER_ZCDIE1(u32Value); +} + +/** + * @brief Get the value of ZCDIE0. + * Filter Channel 0Zero Cross Detected Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of ZCDIE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetZCDIE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NIER & SDADC_NIER_ZCDIE0_MASK) >> SDADC_NIER_ZCDIE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set ZCDIE0. + * Filter Channel 0Zero Cross Detected Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value ZCDIE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetZCDIE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->NIER = (pSdadc->NIER & ~SDADC_NIER_ZCDIE0_MASK) | SDADC_NIER_ZCDIE0(u32Value); +} + +/** + * @brief Get the value of FRDYIE2. + * Filter Channel 2 FIFO Data Ready Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FRDYIE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFRDYIE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NIER & SDADC_NIER_FRDYIE2_MASK) >> SDADC_NIER_FRDYIE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set FRDYIE2. + * Filter Channel 2 FIFO Data Ready Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value FRDYIE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetFRDYIE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->NIER = (pSdadc->NIER & ~SDADC_NIER_FRDYIE2_MASK) | SDADC_NIER_FRDYIE2(u32Value); +} + +/** + * @brief Get the value of FRDYIE1. + * Filter Channel 1 FIFO Data Ready Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FRDYIE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFRDYIE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NIER & SDADC_NIER_FRDYIE1_MASK) >> SDADC_NIER_FRDYIE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set FRDYIE1. + * Filter Channel 1 FIFO Data Ready Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value FRDYIE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetFRDYIE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->NIER = (pSdadc->NIER & ~SDADC_NIER_FRDYIE1_MASK) | SDADC_NIER_FRDYIE1(u32Value); +} + +/** + * @brief Get the value of FRDYIE0. + * Filter Channel 0 FIFO Data Ready Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FRDYIE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFRDYIE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NIER & SDADC_NIER_FRDYIE0_MASK) >> SDADC_NIER_FRDYIE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set FRDYIE0. + * Filter Channel 0 FIFO Data Ready Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value FRDYIE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetFRDYIE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->NIER = (pSdadc->NIER & ~SDADC_NIER_FRDYIE0_MASK) | SDADC_NIER_FRDYIE0(u32Value); +} + +/** + * @brief Get the value of COCIE2. + * Filter Channel 2 Conversion Complete Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of COCIE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCOCIE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NIER & SDADC_NIER_COCIE2_MASK) >> SDADC_NIER_COCIE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set COCIE2. + * Filter Channel 2 Conversion Complete Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value COCIE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetCOCIE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->NIER = (pSdadc->NIER & ~SDADC_NIER_COCIE2_MASK) | SDADC_NIER_COCIE2(u32Value); +} + +/** + * @brief Get the value of COCIE1. + * Filter Channel 1 Conversion Complete Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of COCIE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCOCIE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NIER & SDADC_NIER_COCIE1_MASK) >> SDADC_NIER_COCIE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set COCIE1. + * Filter Channel 1 Conversion Complete Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value COCIE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetCOCIE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->NIER = (pSdadc->NIER & ~SDADC_NIER_COCIE1_MASK) | SDADC_NIER_COCIE1(u32Value); +} + +/** + * @brief Get the value of COCIE0. + * Filter Channel 0 Conversion Complete Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of COCIE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCOCIE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NIER & SDADC_NIER_COCIE0_MASK) >> SDADC_NIER_COCIE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set COCIE0. + * Filter Channel 0 Conversion Complete Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value COCIE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetCOCIE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->NIER = (pSdadc->NIER & ~SDADC_NIER_COCIE0_MASK) | SDADC_NIER_COCIE0(u32Value); +} + +/** + * @brief Get the value of HLMTIE2. + * Filter Channel 2 High Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of HLMTIE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetHLMTIE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER0 & SDADC_ABNIER0_HLMTIE2_MASK) >> SDADC_ABNIER0_HLMTIE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set HLMTIE2. + * Filter Channel 2 High Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value HLMTIE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetHLMTIE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER0 = (pSdadc->ABNIER0 & ~SDADC_ABNIER0_HLMTIE2_MASK) | SDADC_ABNIER0_HLMTIE2(u32Value); +} + +/** + * @brief Get the value of HLMTIE1. + * Filter Channel 1 High Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of HLMTIE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetHLMTIE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER0 & SDADC_ABNIER0_HLMTIE1_MASK) >> SDADC_ABNIER0_HLMTIE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set HLMTIE1. + * Filter Channel 1 High Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value HLMTIE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetHLMTIE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER0 = (pSdadc->ABNIER0 & ~SDADC_ABNIER0_HLMTIE1_MASK) | SDADC_ABNIER0_HLMTIE1(u32Value); +} + +/** + * @brief Get the value of HLMTIE0. + * Filter Channel 0 High Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of HLMTIE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetHLMTIE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER0 & SDADC_ABNIER0_HLMTIE0_MASK) >> SDADC_ABNIER0_HLMTIE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set HLMTIE0. + * Filter Channel 0 High Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value HLMTIE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetHLMTIE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER0 = (pSdadc->ABNIER0 & ~SDADC_ABNIER0_HLMTIE0_MASK) | SDADC_ABNIER0_HLMTIE0(u32Value); +} + +/** + * @brief Get the value of LLMTIE2. + * Filter Channel 2 Low Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of LLMTIE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLLMTIE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER0 & SDADC_ABNIER0_LLMTIE2_MASK) >> SDADC_ABNIER0_LLMTIE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set LLMTIE2. + * Filter Channel 2 Low Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value LLMTIE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetLLMTIE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER0 = (pSdadc->ABNIER0 & ~SDADC_ABNIER0_LLMTIE2_MASK) | SDADC_ABNIER0_LLMTIE2(u32Value); +} + +/** + * @brief Get the value of LLMTIE1. + * Filter Channel 1 Low Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of LLMTIE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLLMTIE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER0 & SDADC_ABNIER0_LLMTIE1_MASK) >> SDADC_ABNIER0_LLMTIE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set LLMTIE1. + * Filter Channel 1 Low Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value LLMTIE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetLLMTIE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER0 = (pSdadc->ABNIER0 & ~SDADC_ABNIER0_LLMTIE1_MASK) | SDADC_ABNIER0_LLMTIE1(u32Value); +} + +/** + * @brief Get the value of LLMTIE0. + * Filter Channel 0 Low Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of LLMTIE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLLMTIE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER0 & SDADC_ABNIER0_LLMTIE0_MASK) >> SDADC_ABNIER0_LLMTIE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set LLMTIE0. + * Filter Channel 0 Low Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value LLMTIE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetLLMTIE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER0 = (pSdadc->ABNIER0 & ~SDADC_ABNIER0_LLMTIE0_MASK) | SDADC_ABNIER0_LLMTIE0(u32Value); +} + +/** + * @brief Get the value of WLMTIE2. + * Filter Channel 2 Window Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of WLMTIE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetWLMTIE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER0 & SDADC_ABNIER0_WLMTIE2_MASK) >> SDADC_ABNIER0_WLMTIE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set WLMTIE2. + * Filter Channel 2 Window Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value WLMTIE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetWLMTIE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER0 = (pSdadc->ABNIER0 & ~SDADC_ABNIER0_WLMTIE2_MASK) | SDADC_ABNIER0_WLMTIE2(u32Value); +} + +/** + * @brief Get the value of WLMTIE1. + * Filter Channel 1 Window Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of WLMTIE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetWLMTIE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER0 & SDADC_ABNIER0_WLMTIE1_MASK) >> SDADC_ABNIER0_WLMTIE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set WLMTIE1. + * Filter Channel 1 Window Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value WLMTIE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetWLMTIE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER0 = (pSdadc->ABNIER0 & ~SDADC_ABNIER0_WLMTIE1_MASK) | SDADC_ABNIER0_WLMTIE1(u32Value); +} + +/** + * @brief Get the value of WLMTIE0. + * Filter Channel 0 Window Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of WLMTIE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetWLMTIE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER0 & SDADC_ABNIER0_WLMTIE0_MASK) >> SDADC_ABNIER0_WLMTIE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set WLMTIE0. + * Filter Channel 0 Window Limit Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value WLMTIE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetWLMTIE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER0 = (pSdadc->ABNIER0 & ~SDADC_ABNIER0_WLMTIE0_MASK) | SDADC_ABNIER0_WLMTIE0(u32Value); +} + +/** + * @brief Get the value of SCDIE2. + * Filter Channel 2 Short Circuit Detected Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SCDIE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSCDIE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER0 & SDADC_ABNIER0_SCDIE2_MASK) >> SDADC_ABNIER0_SCDIE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set SCDIE2. + * Filter Channel 2 Short Circuit Detected Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value SCDIE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetSCDIE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER0 = (pSdadc->ABNIER0 & ~SDADC_ABNIER0_SCDIE2_MASK) | SDADC_ABNIER0_SCDIE2(u32Value); +} + +/** + * @brief Get the value of SCDIE1. + * Filter Channel 1 Short Circuit Detected Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SCDIE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSCDIE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER0 & SDADC_ABNIER0_SCDIE1_MASK) >> SDADC_ABNIER0_SCDIE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set SCDIE1. + * Filter Channel 1 Short Circuit Detected Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value SCDIE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetSCDIE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER0 = (pSdadc->ABNIER0 & ~SDADC_ABNIER0_SCDIE1_MASK) | SDADC_ABNIER0_SCDIE1(u32Value); +} + +/** + * @brief Get the value of SCDIE0. + * Filter Channel 0 Short Circuit Detected Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SCDIE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSCDIE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER0 & SDADC_ABNIER0_SCDIE0_MASK) >> SDADC_ABNIER0_SCDIE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set SCDIE0. + * Filter Channel 0 Short Circuit Detected Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value SCDIE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetSCDIE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER0 = (pSdadc->ABNIER0 & ~SDADC_ABNIER0_SCDIE0_MASK) | SDADC_ABNIER0_SCDIE0(u32Value); +} + +/** + * @brief Get the value of SATIE2. + * Filter Channel 2 Saturation Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SATIE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSATIE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER1 & SDADC_ABNIER1_SATIE2_MASK) >> SDADC_ABNIER1_SATIE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set SATIE2. + * Filter Channel 2 Saturation Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value SATIE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetSATIE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER1 = (pSdadc->ABNIER1 & ~SDADC_ABNIER1_SATIE2_MASK) | SDADC_ABNIER1_SATIE2(u32Value); +} + +/** + * @brief Get the value of SATIE1. + * Filter Channel 1 Saturation Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SATIE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSATIE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER1 & SDADC_ABNIER1_SATIE1_MASK) >> SDADC_ABNIER1_SATIE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set SATIE1. + * Filter Channel 1 Saturation Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value SATIE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetSATIE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER1 = (pSdadc->ABNIER1 & ~SDADC_ABNIER1_SATIE1_MASK) | SDADC_ABNIER1_SATIE1(u32Value); +} + +/** + * @brief Get the value of SATIE0. + * Filter Channel 0 Saturation Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SATIE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSATIE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER1 & SDADC_ABNIER1_SATIE0_MASK) >> SDADC_ABNIER1_SATIE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set SATIE0. + * Filter Channel 0 Saturation Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value SATIE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetSATIE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER1 = (pSdadc->ABNIER1 & ~SDADC_ABNIER1_SATIE0_MASK) | SDADC_ABNIER1_SATIE0(u32Value); +} + +/** + * @brief Get the value of CADIE2. + * Filter Channel 2 Clock Absence Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CADIE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCADIE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER1 & SDADC_ABNIER1_CADIE2_MASK) >> SDADC_ABNIER1_CADIE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set CADIE2. + * Filter Channel 2 Clock Absence Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value CADIE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetCADIE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER1 = (pSdadc->ABNIER1 & ~SDADC_ABNIER1_CADIE2_MASK) | SDADC_ABNIER1_CADIE2(u32Value); +} + +/** + * @brief Get the value of CADIE1. + * Filter Channel 1 Clock Absence Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CADIE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCADIE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER1 & SDADC_ABNIER1_CADIE1_MASK) >> SDADC_ABNIER1_CADIE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set CADIE1. + * Filter Channel 1 Clock Absence Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value CADIE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetCADIE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER1 = (pSdadc->ABNIER1 & ~SDADC_ABNIER1_CADIE1_MASK) | SDADC_ABNIER1_CADIE1(u32Value); +} + +/** + * @brief Get the value of CADIE0. + * Filter Channel 0 Clock Absence Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CADIE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCADIE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER1 & SDADC_ABNIER1_CADIE0_MASK) >> SDADC_ABNIER1_CADIE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set CADIE0. + * Filter Channel 0 Clock Absence Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value CADIE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetCADIE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER1 = (pSdadc->ABNIER1 & ~SDADC_ABNIER1_CADIE0_MASK) | SDADC_ABNIER1_CADIE0(u32Value); +} + +/** + * @brief Get the value of FOVFIE2. + * Filter Channel 2 FIFO Overflow Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FOVFIE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFOVFIE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER1 & SDADC_ABNIER1_FOVFIE2_MASK) >> SDADC_ABNIER1_FOVFIE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set FOVFIE2. + * Filter Channel 2 FIFO Overflow Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value FOVFIE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetFOVFIE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER1 = (pSdadc->ABNIER1 & ~SDADC_ABNIER1_FOVFIE2_MASK) | SDADC_ABNIER1_FOVFIE2(u32Value); +} + +/** + * @brief Get the value of FOVFIE1. + * Filter Channel 1 FIFO Overflow Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FOVFIE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFOVFIE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER1 & SDADC_ABNIER1_FOVFIE1_MASK) >> SDADC_ABNIER1_FOVFIE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set FOVFIE1. + * Filter Channel 1 FIFO Overflow Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value FOVFIE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetFOVFIE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER1 = (pSdadc->ABNIER1 & ~SDADC_ABNIER1_FOVFIE1_MASK) | SDADC_ABNIER1_FOVFIE1(u32Value); +} + +/** + * @brief Get the value of FOVFIE0. + * Filter Channel 0 FIFO Overflow Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FOVFIE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFOVFIE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER1 & SDADC_ABNIER1_FOVFIE0_MASK) >> SDADC_ABNIER1_FOVFIE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set FOVFIE0. + * Filter Channel 0 FIFO Overflow Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value FOVFIE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetFOVFIE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER1 = (pSdadc->ABNIER1 & ~SDADC_ABNIER1_FOVFIE0_MASK) | SDADC_ABNIER1_FOVFIE0(u32Value); +} + +/** + * @brief Get the value of FUNFIE2. + * Filter Channel 2 FIFO Underflow Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FUNFIE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFUNFIE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER1 & SDADC_ABNIER1_FUNFIE2_MASK) >> SDADC_ABNIER1_FUNFIE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set FUNFIE2. + * Filter Channel 2 FIFO Underflow Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value FUNFIE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetFUNFIE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER1 = (pSdadc->ABNIER1 & ~SDADC_ABNIER1_FUNFIE2_MASK) | SDADC_ABNIER1_FUNFIE2(u32Value); +} + +/** + * @brief Get the value of FUNFIE1. + * Filter Channel 1 FIFO Underflow Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FUNFIE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFUNFIE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER1 & SDADC_ABNIER1_FUNFIE1_MASK) >> SDADC_ABNIER1_FUNFIE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set FUNFIE1. + * Filter Channel 1 FIFO Underflow Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value FUNFIE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetFUNFIE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER1 = (pSdadc->ABNIER1 & ~SDADC_ABNIER1_FUNFIE1_MASK) | SDADC_ABNIER1_FUNFIE1(u32Value); +} + +/** + * @brief Get the value of FUNFIE0. + * Filter Channel 0 FIFO Underflow Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FUNFIE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFUNFIE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNIER1 & SDADC_ABNIER1_FUNFIE0_MASK) >> SDADC_ABNIER1_FUNFIE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set FUNFIE0. + * Filter Channel 0 FIFO Underflow Interrupt Enable + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value FUNFIE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetFUNFIE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->ABNIER1 = (pSdadc->ABNIER1 & ~SDADC_ABNIER1_FUNFIE0_MASK) | SDADC_ABNIER1_FUNFIE0(u32Value); +} + +/** + * @brief Get the value of ZCD2. + * Filter Channel 2 Zero Cross Detected Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of ZCD2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetZCD2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NISR & SDADC_NISR_ZCD2_MASK) >> SDADC_NISR_ZCD2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear ZCD2. + * Filter Channel 2 Zero Cross Detected Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearZCD2(SDADC_Type *const pSdadc) +{ + pSdadc->NISR = SDADC_NISR_ZCD2(1); +} + +/** + * @brief Get the value of ZCD1. + * Filter Channel 1 Zero Cross Detected Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of ZCD1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetZCD1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NISR & SDADC_NISR_ZCD1_MASK) >> SDADC_NISR_ZCD1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear ZCD1. + * Filter Channel 1 Zero Cross Detected Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearZCD1(SDADC_Type *const pSdadc) +{ + pSdadc->NISR = SDADC_NISR_ZCD1(1); +} + +/** + * @brief Get the value of ZCD0. + * Filter Channel 0 Zero Cross Detected Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of ZCD0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetZCD0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NISR & SDADC_NISR_ZCD0_MASK) >> SDADC_NISR_ZCD0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear ZCD0. + * Filter Channel 0 Zero Cross Detected Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearZCD0(SDADC_Type *const pSdadc) +{ + pSdadc->NISR = SDADC_NISR_ZCD0(1); +} + +/** + * @brief Get the value of FRDY2. + * Filter Channel 2 FIFO Data Ready Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FRDY2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFRDY2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NISR & SDADC_NISR_FRDY2_MASK) >> SDADC_NISR_FRDY2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear FRDY2. + * Filter Channel 2 FIFO Data Ready Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearFRDY2(SDADC_Type *const pSdadc) +{ + pSdadc->NISR = SDADC_NISR_FRDY2(1); +} + +/** + * @brief Get the value of FRDY1. + * Filter Channel 1 FIFO Data Ready Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FRDY1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFRDY1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NISR & SDADC_NISR_FRDY1_MASK) >> SDADC_NISR_FRDY1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear FRDY1. + * Filter Channel 1 FIFO Data Ready Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearFRDY1(SDADC_Type *const pSdadc) +{ + pSdadc->NISR = SDADC_NISR_FRDY1(1); +} + +/** + * @brief Get the value of FRDY0. + * Filter Channel 0 FIFO Data Ready Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FRDY0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFRDY0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NISR & SDADC_NISR_FRDY0_MASK) >> SDADC_NISR_FRDY0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear FRDY0. + * Filter Channel 0 FIFO Data Ready Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearFRDY0(SDADC_Type *const pSdadc) +{ + pSdadc->NISR = SDADC_NISR_FRDY0(1); +} + +/** + * @brief Get the value of COC2. + * Filter Channel 2 Conversion Complete Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of COC2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCOC2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NISR & SDADC_NISR_COC2_MASK) >> SDADC_NISR_COC2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear COC2. + * Filter Channel 2 Conversion Complete Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearCOC2(SDADC_Type *const pSdadc) +{ + pSdadc->NISR = SDADC_NISR_COC2(1); +} + +/** + * @brief Get the value of COC1. + * Filter Channel 1 Conversion Complete Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of COC1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCOC1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NISR & SDADC_NISR_COC1_MASK) >> SDADC_NISR_COC1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear COC1. + * Filter Channel 1 Conversion Complete Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearCOC1(SDADC_Type *const pSdadc) +{ + pSdadc->NISR = SDADC_NISR_COC1(1); +} + +/** + * @brief Get the value of COC0. + * Filter Channel 0 Conversion Complete Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of COC0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCOC0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->NISR & SDADC_NISR_COC0_MASK) >> SDADC_NISR_COC0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear COC0. + * Filter Channel 0 Conversion Complete Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearCOC0(SDADC_Type *const pSdadc) +{ + pSdadc->NISR = SDADC_NISR_COC0(1); +} + +/** + * @brief Get the value of HLMT2. + * Filter Channel 2 High Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of HLMT2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetHLMT2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR0 & SDADC_ABNISR0_HLMT2_MASK) >> SDADC_ABNISR0_HLMT2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear HLMT2. + * Filter Channel 2 High Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearHLMT2(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR0 = SDADC_ABNISR0_HLMT2(1); +} + +/** + * @brief Get the value of HLMT1. + * Filter Channel 1 High Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of HLMT1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetHLMT1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR0 & SDADC_ABNISR0_HLMT1_MASK) >> SDADC_ABNISR0_HLMT1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear HLMT1. + * Filter Channel 1 High Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearHLMT1(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR0 = SDADC_ABNISR0_HLMT1(1); +} + +/** + * @brief Get the value of HLMT0. + * Filter Channel 0 High Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of HLMT0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetHLMT0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR0 & SDADC_ABNISR0_HLMT0_MASK) >> SDADC_ABNISR0_HLMT0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear HLMT0. + * Filter Channel 0 High Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearHLMT0(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR0 = SDADC_ABNISR0_HLMT0(1); +} + +/** + * @brief Get the value of LLMT2. + * Filter Channel 2 Low Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of LLMT2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLLMT2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR0 & SDADC_ABNISR0_LLMT2_MASK) >> SDADC_ABNISR0_LLMT2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear LLMT2. + * Filter Channel 2 Low Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearLLMT2(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR0 = SDADC_ABNISR0_LLMT2(1); +} + +/** + * @brief Get the value of LLMT1. + * Filter Channel 1 Low Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of LLMT1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLLMT1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR0 & SDADC_ABNISR0_LLMT1_MASK) >> SDADC_ABNISR0_LLMT1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear LLMT1. + * Filter Channel 1 Low Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearLLMT1(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR0 = SDADC_ABNISR0_LLMT1(1); +} + +/** + * @brief Get the value of LLMT0. + * Filter Channel 0 Low Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of LLMT0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLLMT0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR0 & SDADC_ABNISR0_LLMT0_MASK) >> SDADC_ABNISR0_LLMT0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear LLMT0. + * Filter Channel 0 Low Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearLLMT0(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR0 = SDADC_ABNISR0_LLMT0(1); +} + +/** + * @brief Get the value of WLMT2. + * Filter Channel 2 Window Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of WLMT2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetWLMT2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR0 & SDADC_ABNISR0_WLMT2_MASK) >> SDADC_ABNISR0_WLMT2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear WLMT2. + * Filter Channel 2 Window Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearWLMT2(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR0 = SDADC_ABNISR0_WLMT2(1); +} + +/** + * @brief Get the value of WLMT1. + * Filter Channel 1 Window Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of WLMT1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetWLMT1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR0 & SDADC_ABNISR0_WLMT1_MASK) >> SDADC_ABNISR0_WLMT1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear WLMT1. + * Filter Channel 1 Window Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearWLMT1(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR0 = SDADC_ABNISR0_WLMT1(1); +} + +/** + * @brief Get the value of WLMT0. + * Filter Channel 0 Window Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of WLMT0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetWLMT0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR0 & SDADC_ABNISR0_WLMT0_MASK) >> SDADC_ABNISR0_WLMT0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear WLMT0. + * Filter Channel 0 Window Limit Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearWLMT0(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR0 = SDADC_ABNISR0_WLMT0(1); +} + +/** + * @brief Get the value of SCD2. + * Filter Channel 2 Short Circuit Detected Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SCD2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSCD2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR0 & SDADC_ABNISR0_SCD2_MASK) >> SDADC_ABNISR0_SCD2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear SCD2. + * Filter Channel 2 Short Circuit Detected Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearSCD2(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR0 = SDADC_ABNISR0_SCD2(1); +} + +/** + * @brief Get the value of SCD1. + * Filter Channel 1 Short Circuit Detected Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SCD1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSCD1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR0 & SDADC_ABNISR0_SCD1_MASK) >> SDADC_ABNISR0_SCD1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear SCD1. + * Filter Channel 1 Short Circuit Detected Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearSCD1(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR0 = SDADC_ABNISR0_SCD1(1); +} + +/** + * @brief Get the value of SCD0. + * Filter Channel 0 Short Circuit Detected Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SCD0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSCD0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR0 & SDADC_ABNISR0_SCD0_MASK) >> SDADC_ABNISR0_SCD0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear SCD0. + * Filter Channel 0 Short Circuit Detected Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearSCD0(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR0 = SDADC_ABNISR0_SCD0(1); +} + +/** + * @brief Get the value of SAT2. + * Filter Channel 2 Saturation Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SAT2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSAT2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR1 & SDADC_ABNISR1_SAT2_MASK) >> SDADC_ABNISR1_SAT2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear SAT2. + * Filter Channel 2 Saturation Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearSAT2(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR1 = SDADC_ABNISR1_SAT2(1); +} + +/** + * @brief Get the value of SAT1. + * Filter Channel 1 Saturation Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SAT1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSAT1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR1 & SDADC_ABNISR1_SAT1_MASK) >> SDADC_ABNISR1_SAT1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear SAT1. + * Filter Channel 1 Saturation Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearSAT1(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR1 = SDADC_ABNISR1_SAT1(1); +} + +/** + * @brief Get the value of SAT0. + * Filter Channel 0 Saturation Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SAT0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSAT0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR1 & SDADC_ABNISR1_SAT0_MASK) >> SDADC_ABNISR1_SAT0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear SAT0. + * Filter Channel 0 Saturation Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearSAT0(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR1 = SDADC_ABNISR1_SAT0(1); +} + +/** + * @brief Get the value of CAD2. + * Filter Channel 2 Clock Absence Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CAD2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCAD2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR1 & SDADC_ABNISR1_CAD2_MASK) >> SDADC_ABNISR1_CAD2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear CAD2. + * Filter Channel 2 Clock Absence Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearCAD2(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR1 = SDADC_ABNISR1_CAD2(1); +} + +/** + * @brief Get the value of CAD1. + * Filter Channel 1 Clock Absence Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CAD1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCAD1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR1 & SDADC_ABNISR1_CAD1_MASK) >> SDADC_ABNISR1_CAD1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear CAD1. + * Filter Channel 1 Clock Absence Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearCAD1(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR1 = SDADC_ABNISR1_CAD1(1); +} + +/** + * @brief Get the value of CAD0. + * Filter Channel 0 Clock Absence Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CAD0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCAD0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR1 & SDADC_ABNISR1_CAD0_MASK) >> SDADC_ABNISR1_CAD0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear CAD0. + * Filter Channel 0 Clock Absence Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearCAD0(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR1 = SDADC_ABNISR1_CAD0(1); +} + +/** + * @brief Get the value of FOVF2. + * Filter Channel 2 FIFO Overflow Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FOVF2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFOVF2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR1 & SDADC_ABNISR1_FOVF2_MASK) >> SDADC_ABNISR1_FOVF2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear FOVF2. + * Filter Channel 2 FIFO Overflow Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearFOVF2(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR1 = SDADC_ABNISR1_FOVF2(1); +} + +/** + * @brief Get the value of FOVF1. + * Filter Channel 1 FIFO Overflow Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FOVF1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFOVF1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR1 & SDADC_ABNISR1_FOVF1_MASK) >> SDADC_ABNISR1_FOVF1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear FOVF1. + * Filter Channel 1 FIFO Overflow Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearFOVF1(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR1 = SDADC_ABNISR1_FOVF1(1); +} + +/** + * @brief Get the value of FOVF0. + * Filter Channel 0 FIFO Overflow flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FOVF0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFOVF0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR1 & SDADC_ABNISR1_FOVF0_MASK) >> SDADC_ABNISR1_FOVF0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear FOVF0. + * Filter Channel 0 FIFO Overflow flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearFOVF0(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR1 = SDADC_ABNISR1_FOVF0(1); +} + +/** + * @brief Get the value of FUNF2. + * Filter Channel 2 FIFO underflow flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FUNF2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFUNF2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR1 & SDADC_ABNISR1_FUNF2_MASK) >> SDADC_ABNISR1_FUNF2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear FUNF2. + * Filter Channel 2 FIFO underflow flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearFUNF2(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR1 = SDADC_ABNISR1_FUNF2(1); +} + +/** + * @brief Get the value of FUNF1. + * Filter Channel 1 FIFO Underflow Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FUNF1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFUNF1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR1 & SDADC_ABNISR1_FUNF1_MASK) >> SDADC_ABNISR1_FUNF1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear FUNF1. + * Filter Channel 1 FIFO Underflow Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearFUNF1(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR1 = SDADC_ABNISR1_FUNF1(1); +} + +/** + * @brief Get the value of FUNF0. + * Filter Channel 0 FIFO Underflow Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FUNF0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFUNF0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->ABNISR1 & SDADC_ABNISR1_FUNF0_MASK) >> SDADC_ABNISR1_FUNF0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear FUNF0. + * Filter Channel 0 FIFO Underflow Flag + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearFUNF0(SDADC_Type *const pSdadc) +{ + pSdadc->ABNISR1 = SDADC_ABNISR1_FUNF0(1); +} + +/** + * @brief Get the value of CLKO2_RDY. + * Modulator Clock Output 2 Ready Flag + * Indicate the modulator clock 2 output is ready. + * 0b - The clock is not ready. + * 1b - The clock is ready. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CLKO2_RDY. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCLKO2_RDY(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->MSR & SDADC_MSR_CLKO2_RDY_MASK) >> SDADC_MSR_CLKO2_RDY_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CLKO1_RDY. + * Modulator Clock Output 1 Ready Flag + * Indicate the modulator clock 1 output is ready. + * 0b - The clock is not ready. + * 1b - The clock is ready. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CLKO1_RDY. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCLKO1_RDY(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->MSR & SDADC_MSR_CLKO1_RDY_MASK) >> SDADC_MSR_CLKO1_RDY_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CLKO0_RDY. + * Modulator Clock Output 0 Ready Flag + * Indicate the modulator clock 0 output is ready. + * 0b - The clock is not ready. + * 1b - The clock is ready. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CLKO0_RDY. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCLKO0_RDY(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->MSR & SDADC_MSR_CLKO0_RDY_MASK) >> SDADC_MSR_CLKO0_RDY_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of FIFO_EMPTY. + * FIFO Empty Flag + * bit 18-16 are for filter channel 2-0. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of FIFO_EMPTY. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFIFO_EMPTY(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->MSR & SDADC_MSR_FIFO_EMPTY_MASK) >> SDADC_MSR_FIFO_EMPTY_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CHRDY. + * Filter Channel Ready Flag + * bit 10-8 are for filter channel 2-0. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CHRDY. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCHRDY(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->MSR & SDADC_MSR_CHRDY_MASK) >> SDADC_MSR_CHRDY_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CHON2. + * Filter Channel 2 Conversion Ongoing Flag + * 0b - The conversion is not ongoing. + * 1b - The conversion is ongoing. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CHON2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCHON2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->MSR & SDADC_MSR_CHON2_MASK) >> SDADC_MSR_CHON2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CHON1. + * Filter Channel 1 Conversion Ongoing Flag + * 0b - The conversion is not ongoing. + * 1b - The conversion is ongoing. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CHON1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCHON1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->MSR & SDADC_MSR_CHON1_MASK) >> SDADC_MSR_CHON1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CHON0. + * Filter Channel 0 Conversion Ongoing Flag + * 0b - The conversion is not ongoing. + * 1b - The conversion is ongoing. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CHON0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCHON0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->MSR & SDADC_MSR_CHON0_MASK) >> SDADC_MSR_CHON0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CHON. + * Filter Channel ON Flag + * bit 10-8 are for filter channel 2-0. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32 the value of CHON. + */ +LOCAL_INLINE uint32 SDADC_HWA_GetCHON(const SDADC_Type *const pSdadc) +{ + uint32 u32TmpVal = (pSdadc->MSR & SDADC_MSR_CHON_MASK) >> SDADC_MSR_CHON_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of the Channel Configuration Register (CCR) for a specified channel. + * + * This function retrieves the value of the Channel Configuration Register (CCR) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CCR value is to be retrieved. + * + * @return uint32_t the value of the CCR for the specified channel. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCCRn(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + return SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR; +} + +/** + * @brief Set the value of the Channel Configuration Register (CCR) for a specified channel. + * + * This function sets the value of the Channel Configuration Register (CCR) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CCR value is to be set. + * @param u32Value the value to be set in the CCR register. + */ +LOCAL_INLINE void SDADC_HWA_SetCCRn(const SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR = u32Value; +} + +/** + * @brief Get the value of LMT_SEL. + * Limit Check Input Selection + * Select the input from Main Filter or Auxiliary Filter. + * 0b - Auxiliary Filter. + * 1b - Main Filter. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of LMT_SEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLMT_SEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_LMT_SEL_MASK) >> SDADC_CCR_LMT_SEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of ZCD_SEL. + * Zero Cross Check Input Selection + * Select the input from Main Filter or Auxiliary Filter. + * 0b - Auxiliary Filter. + * 1b - Main Filter. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of ZCD_SEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetZCD_SEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_ZCD_SEL_MASK) >> SDADC_CCR_ZCD_SEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of DBG_SEL. + * Debug Output Selection + * Select which data is output when read debug register + * 0100b - Instantaneous Primary Filter shifted 24bit Data. + * 0110b - Instantaneous HPF Output Data. + * 1000b - Instantaneous GAIN Output Data. + * 1010b - Instantaneous Secondary Filter CIC Data. + * 1110b - Instantaneous Primary Filter offset removed 24bit Data. + * others - Reserved. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of DBG_SEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetDBG_SEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_DBG_SEL_MASK) >> SDADC_CCR_DBG_SEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of INTG_EN. + * Integration Enable + * Enable the integration block. + * 0b - Disabled and bypassed. + * 1b - Enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of INTG_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINTG_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_INTG_EN_MASK) >> SDADC_CCR_INTG_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of RECT_EN. + * Rectification Enable + * Enable the rectification block. + * 0b - Disabled and bypassed. + * 1b - Enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of RECT_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetRECT_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_RECT_EN_MASK) >> SDADC_CCR_RECT_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of FIFO_EN. + * FIFO Enable + * 0b - FIFO is disabled for the channel. + * 1b - FIFO is enabled for the channel. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of FIFO_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFIFO_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_FIFO_EN_MASK) >> SDADC_CCR_FIFO_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of LMT_EN. + * Limit Enable + * 0b - Limit check is disabled for the Main or Auxiliary Filter. + * 1b - Limit check is enabled for the Main or Auxiliary Filter. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of LMT_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLMT_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_LMT_EN_MASK) >> SDADC_CCR_LMT_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of ZCD_EN. + * Zero Cross Detect Enable + * 0b - Zero cross detection is disabled for the Main or Auxiliary Filter. + * 1b - Zero cross detection is enabled for the Main or Auxiliary Filter. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of ZCD_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetZCD_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_ZCD_EN_MASK) >> SDADC_CCR_ZCD_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CAD_EN. + * Clock Absence Detect Enable + * 0b - Clock absence detection is disabled for the channel. + * 1b - Clock absence detection is enabled for the channel. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of CAD_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCAD_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_CAD_EN_MASK) >> SDADC_CCR_CAD_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SCD_EN. + * Short Circuit Detect Enable + * 0b - Short current detection is disabled for the channel. + * 1b - Short current detection is enabled for the channel. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SCD_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSCD_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_SCD_EN_MASK) >> SDADC_CCR_SCD_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of DMA_EN. + * DMA Enable + * 0b - DMA is disabled for the channel. + * 1b - DMA is enabled for the channel. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of DMA_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetDMA_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_DMA_EN_MASK) >> SDADC_CCR_DMA_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of AF_EN. + * Auxiliary Filter Enable + * 0b - The Auxiliary Filter is disabled for the channel. + * 1b - The Auxiliary Filter is enabled for the channel. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of AF_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetAF_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_AF_EN_MASK) >> SDADC_CCR_AF_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of MF_EN. + * Main Filter Enable + * 0b - The Main Filter is disabled for the channel. + * 1b - The Main Filter is enabled for the channel. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of MF_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMF_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_MF_EN_MASK) >> SDADC_CCR_MF_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CH_EN. + * Channel Enable + * 0b - The channel is disabled. + * 0b - The channel is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of CH_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCH_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & SDADC_CCR_CH_EN_MASK) >> SDADC_CCR_CH_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set the value of CH_EN. + * Channel Enable + * 0b - The channel is disabled. + * 0b - The channel is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param u8Enable SDADC Channel Channel Enable. + * @return uint32_t the value of CH_EN. + */ +LOCAL_INLINE void SDADC_HWA_SetCH_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel, uint8_t u8Enable) +{ + SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & ~SDADC_CCR_CH_EN_MASK) | SDADC_CCR_CH_EN(u8Enable); +} + +/** + * @brief Get the value of AFCM. + * Auxiliary Filter Conversion Mode + * 0b - Always on. + * 1b - Follow Main Filter mode (trigger). + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of AFCM. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetAFCM(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CDR & SDADC_CDR_AFCM_MASK) >> SDADC_CDR_AFCM_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of AFORD. + * Auxiliary Filter Order + * 00b - Reserved. + * 01b - First order filter. + * 10b - Second order filter. + * 11b - Third order filter. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of AFORD. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetAFORD(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CDR & SDADC_CDR_AFORD_MASK) >> SDADC_CDR_AFORD_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of AFOSR. + * Auxiliary Filter Oversampling Rate + * The oversampling rate = (AFOSR + 1). + * The lower valid value of AFOSR is 3. + * The higher is depended on AFORD, in order to keep the internal CIC raw result not exceeding 24bit. If AFORD = 3, the maximum value is 202, else the maximum value is 511. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of AFOSR. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetAFOSR(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CDR & SDADC_CDR_AFOSR_MASK) >> SDADC_CDR_AFOSR_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of MFCM. + * Main Filter Conversion Mode + * 00b - Single mode. One conversion following a triggering event (edge or level). + * 01b - Continuous conversion mode. Multiple conversions following a triggering event, and the next trigger will cancel and restart conversion. + * 10b - Always conversion mode. Multiple conversions following the first trigger, and the next trigger will be ignored. + * 11b - Reserved. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of MFCM. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMFCM(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CDR & SDADC_CDR_MFCM_MASK) >> SDADC_CDR_MFCM_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of MFORD. + * Main Filter Order + * 000b - Reserved. + * 001b - First order filter. + * 010b - Second order filter. + * 011b - Third order filter. + * 100b - Fourth order filter. + * 101b - Fifth order filter. + * 110,111 - Reserved. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of MFORD. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMFORD(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CDR & SDADC_CDR_MFORD_MASK) >> SDADC_CDR_MFORD_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of MFOSR. + * Main Filter Oversampling Rate + * The oversampling rate = (MFOSR + 1). + * The lower valid of MFOSR value is 3. + * The higher is depended on MFORD, in order to keep the internal CIC raw result not exceeding 32bit. If MFORD = 4, the maximum value is 203. If MFORD = 5, the maximum value is 72, else the maximum value is 511. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of MFOSR. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMFOSR(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CDR & SDADC_CDR_MFOSR_MASK) >> SDADC_CDR_MFOSR_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SYNC_TRGEN. + * Synced Trigger Select Enable + * 0b - Synced trigger is selected on the channel itself. + * 1b - Synced trigger is selected on the channel defined by SYNC_TRGSEL. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SYNC_TRGEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCFR_SYNC_TRGEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR & SDADC_CFR_SYNC_TRGEN_MASK) >> SDADC_CFR_SYNC_TRGEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of TRGLVL. + * Trigger Level type + * 0b - Trigger is edge event. Next edge event will cancel the current conversion, and re-start in single or continuous mode. + * 1b - Trigger is level event. De-assert cancels the current conversion, and stop filter function in single or continuous mode. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of TRGLVL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTRGLVL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR & SDADC_CFR_TRGLVL_MASK) >> SDADC_CFR_TRGLVL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SYNC_TRGSEL. + * Synced Trigger Select + * Each will detect and sync the trigger input as a synced trigger, this bits can select to use the synced trigger from which channel. By this bits, two or more channels can share the same synced trigger and trigger to start at the same time. + * 000b - select the trigger from the channel 0. + * 001b - select the trigger from the channel 1. + * 010b - select the trigger from the channel 2. + * ... + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SYNC_TRGSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSYNC_TRGSEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR & SDADC_CFR_SYNC_TRGSEL_MASK) >> SDADC_CFR_SYNC_TRGSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of TRGSEL. + * Trigger Select + * 0b - Software trigger is selected. + * 1b - Hardware trigger is selected. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of TRGSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTRGSEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR & SDADC_CFR_TRGSEL_MASK) >> SDADC_CFR_TRGSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CLKEDG. + * Input Clock Edge Select + * This bits select the effective edge of the modulator clock recovery to generate mclk. When using on chip modulator, only posedge is supported. + * 01b - Posedge. + * 10b - Negedge. + * 11b - Both edge. + * 00b - Reserved. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of CLKEDG. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCLKEDG(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR & SDADC_CFR_CLKEDG_MASK) >> SDADC_CFR_CLKEDG_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CLKSEL. + * Input Clock Select + * This bits select the clock source for the clock recovery to generate mclk. + * 00b - Reserved. + * 01b - Internal generated function clock div_clk1 selected, used for the case where MA is using div_clk0 as its function clock. The clock recovery is worked in sync mode. + * 10b - Internal generated function clock div_clk2 selected, used for the case where MA is using div_clk1 as its function clock. The clock recovery is worked in sync mode. + * 11b - Modulator clock from external modulator selected. The clock recovery is worked in async mode. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of CLKSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCFRCLKSEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR & SDADC_CFR_CLKSEL_MASK) >> SDADC_CFR_CLKSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of IBFMT. + * Input Bit Format + * 00b - External one bit stream. + * 01b - External Manchester code, CLKEDG will determine rise or fall decoder. + * 10b - Reserved. + * 11b - Reserved. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of IBFMT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetIBFMT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR & SDADC_CFR_IBFMT_MASK) >> SDADC_CFR_IBFMT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of FWMK. + * FIFO Water Mark + * Controls the watermark of the FIFO used to set FRDYn. When the number of results in the FIFO is greater than FWMK value, the FRDYn flag will be set. A DMA request or interrupt can also be generated if related DMA_EN and FRDYIE bit-field is set. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of FWMK. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFWMK(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR & SDADC_CFR_FWMK_MASK) >> SDADC_CFR_FWMK_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CUTOFF. + * Cutoff Frequency Setting for High Pass Filter(HPF) + * HPF can only be enabled when RDFMT=0. + * 000b - HPF is disabled + * 001b - HPF is enabled and setting the cutoff frequency to rate 1(lowest cutoff frequency) + * �� + * 111b - HPF is enabled and setting the cutoff frequency to rate 7.(highest cutoff frequency) + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of CUTOFF. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCUTOFF(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR & SDADC_CFR_CUTOFF_MASK) >> SDADC_CFR_CUTOFF_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of RDFMT. + * Result Data Format + * 0b - Left justified, signed, for the case where input bitstream is signed + * 1b - Left justified, unsigned, for the case where input bitstream is unsigned + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of RDFMT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetRDFMT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR & SDADC_CFR_RDFMT_MASK) >> SDADC_CFR_RDFMT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of MFSHIFT. + * Main Filter Shift to Get Correct 24 bit Precision + * Main Filter CIC raw result is always 32bit width. The user should program MFSHIFT for cut-off and shift left/right to get 24bit result. + * MFSHIFT[4] = 1 means left shift, and MFSHIFT[4] = 0 means right shift. + * MFSHIFT[3:0] is the shift length. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of MFSHIFT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMFSHIFT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR & SDADC_CFR_MFSHIFT_MASK) >> SDADC_CFR_MFSHIFT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of the Channel Protection Register (CPR) for a specified channel. + * + * This function retrieves the value of the Channel Protection Register (CPR) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CPR value is to be retrieved. + * + * @return uint32_t the value of the CPR for the specified channel. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCPRn(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + return SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR; +} + +/** + * @brief Set the value of the Channel Protection Register (CPR) for a specified channel. + * + * This function sets the value of the Channel Protection Register (CPR) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CPR value is to be set. + * @param u32Value the value to be set in the CPR register. + */ +LOCAL_INLINE void SDADC_HWA_SetCPRn(const SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR = u32Value; +} + +/** + * @brief Get the value of HLMT_BKEN. + * Break Signal Enable for High Limit Event + * 0b - The Break signal is not enabled. + * 1b - The Break signal is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of HLMT_BKEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetHLMT_BKEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_HLMT_BKEN_MASK) >> SDADC_CPR_HLMT_BKEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of WLMT_BKEN. + * Break Signal Enabled for Window Limit Event + * 0b - The Break signal is not enabled. + * 1b - The Break signal is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of WLMT_BKEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetWLMT_BKEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_WLMT_BKEN_MASK) >> SDADC_CPR_WLMT_BKEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of LLMT_BKEN. + * Break Signal Enabled for Low Limit Event + * 0b - The Break signal is not enabled. + * 1b - The Break signal is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of LLMT_BKEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLLMT_BKEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_LLMT_BKEN_MASK) >> SDADC_CPR_LLMT_BKEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SCD_BKEN. + * Break Signal Enabled for Short Circuit Event + * 0b - The Break signal is not enabled. + * 1b - The Break signal is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SCD_BKEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSCD_BKEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_SCD_BKEN_MASK) >> SDADC_CPR_SCD_BKEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CAD_BKEN. + * Break Signal Enabled for Clock Absence Event + * 0b - The Break signal is not enabled. + * 1b - The Break signal is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of CAD_BKEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCAD_BKEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_CAD_BKEN_MASK) >> SDADC_CPR_CAD_BKEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of LMTF_PROTEN. + * Protection Singal Enabled for Limit Flag + * The protection signal can be enabled and sent to TRGSEL for application protection function. LMTOPT can be used to select which limit flag(HLMT/LLMT/WLMT) is used as the protection source. This protection signal can only be cleared by W1C of related flag reigsters. + * 0b - The Protection signal is not enabled. + * 1b - The Protection signal is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of LMTF_PROTEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLMTF_PROTEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_LMTF_PROTEN_MASK) >> SDADC_CPR_LMTF_PROTEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of LMTR_PROTEN. + * Protection Singal Enabled for Limit Result + * The protection signal can be enabled and sent to TRGSEL for application protection function. LMTOPT can be used to select which limit result(high/low/window limit result) is used as the protection source. This protection signal will keep on if related condition keeps(keep high/keep low/keep in window) until the condition is not satisfied. + * 0b - The Protection signal is not enabled. + * 1b - The Protection signal is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of LMTR_PROTEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLMTR_PROTEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_LMTR_PROTEN_MASK) >> SDADC_CPR_LMTR_PROTEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of HYSTR_PROTEN. + * Protection Singal Enabled for Limit Hysteresis Result + * The protection signal can be enabled and sent to TRGSEL for application protection function. This protection signal is from the result of hysteresis comparator in limit detector and will keep on if related condition keeps(keep high/keep low) until the condition is not satisfied. + * 0b - The Protection signal is not enabled. + * 1b - The Protection signal is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of HYSTR_PROTEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetHYSTR_PROTEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_HYSTR_PROTEN_MASK) >> SDADC_CPR_HYSTR_PROTEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SCD_PROTEN. + * Protection Singal Enabled for SCD Flag + * The protection signal can be enabled and sent to TRGSEL for application protection function. This protection signal can only be cleared by W1C of related flag reigsters. + * 0b - The Protection signal is not enabled. + * 1b - The Protection signal is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SCD_PROTEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSCD_PROTEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_SCD_PROTEN_MASK) >> SDADC_CPR_SCD_PROTEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CAD_PROTEN. + * Protection Singal Enabled for CAD Flag + * The protection signal can be enabled and sent to TRGSEL for application protection function. This protection signal can only be cleared by W1C of related flag reigsters. + * 0b - The Protection signal is not enabled. + * 1b - The Protection signal is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of CAD_PROTEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCAD_PROTEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_CAD_PROTEN_MASK) >> SDADC_CPR_CAD_PROTEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of LMTAVT. + * Limitation Result Activation Select + * The conversion results are compared with HILMTn and LOLMTn in limit detector, and HILMTn and LOLMTn can define a hysteresis range , A compare result is set/clear and sent to system with configurable activation. + * Note, When this hysteresis compare function is used in system, LMTOPTn need to be 00b to enable detect on exceed both high and low value. + * 0b - The compare result is set only when the conversion result is larger than HILMTn and clear only when the conversion result is smaller than LOLMTn. + * 1b - The compare result is clear only when the conversion result is larger than HILMTn and set only when the conversion result is smaller than LOLMTn. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of LMTAVT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLMTAVT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_LMTAVT_MASK) >> SDADC_CPR_LMTAVT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CADLMT. + * Clock Absence Detector Limitation Threshold + * The threshold value for the clock absence counter. + * The counter indicates the number of cycles the modulator clock not detected. If this value is reached, a clock absence detector event will occur on the dedicated channel. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of CADLMT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCADLMT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_CADLMT_MASK) >> SDADC_CPR_CADLMT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of LMTOPT. + * Limitation Option + * 00b - Limitation detect on exceed both high and low value. + * 01b - Limitation detect on exceed high threshold value. + * 10b - Limitation detect on exceed low threshold value. + * 11b - Limitation detect on windowed value. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of LMTOPT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLMTOPT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_LMTOPT_MASK) >> SDADC_CPR_LMTOPT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SCDOPT. + * Short Circuit Option + * 00b - Count on both 0 and 1. Detect both high and low value. + * 01b - Count on 1. Detect high value. + * 10b - Count on 0. Detect low value. + * 11b - Reserved. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SCDOPT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSCDOPT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_SCDOPT_MASK) >> SDADC_CPR_SCDOPT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SCDCM. + * Short Circuit Detect Conversion Mode + * 0b - Always on when CHEN and MEN are asserted. + * 1b - Only works when the any filter is in progress. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SCDCM. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSCDCM(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_SCDCM_MASK) >> SDADC_CPR_SCDCM_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SCDLMT. + * Short Circuit Detector Limitation extension + * The threshold value for short circuit detector counter. + * The counter indicates the number of continuous received bit 0 or bit 1. If this value is reached, a short-circuit detector event will occur on the dedicated channel. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SCDLMT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSCDLMT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CPR & SDADC_CPR_SCDLMT_MASK) >> SDADC_CPR_SCDLMT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of BIAS. + * Bias Value + * Bias offset for dedicated channel main filter; used for sign adjustment and compensation. It's a signed data. The main filter data after shift, will subtract this bias value. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of BIAS. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetBIAS(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CBR & SDADC_CBR_BIAS_MASK) >> SDADC_CBR_BIAS_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set the value of BIAS. + * Bias Value + * Bias offset for dedicated channel main filter; used for sign adjustment and compensation. It's a signed data. The main filter data after shift, will subtract this bias value. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param u32Value Bias value. + * @return uint32_t the value of BIAS. + */ +LOCAL_INLINE void SDADC_HWA_SetBIAS(const SDADC_Type *const pSdadc, uint8_t u8Channel, uint32 u32Value) +{ + SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CBR = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CBR & ~SDADC_CBR_BIAS_MASK) | SDADC_CBR_BIAS(u32Value); +} + +/** + * @brief Get the value of LOLMT. + * Low Limit Threshold + * When the data value exceeds this value, a low limit event will occur. The limit value format (signed or unsigned) depends on RDFMT. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of LOLMT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetLOLMT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CLLMT & SDADC_CLLMT_LOLMT_MASK) >> SDADC_CLLMT_LOLMT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of HILMT. + * High Limit Threshold + * When data value exceeds this value, high limit event will occur. The limit value format (signed or unsigned) is depended on RDFMT + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of HILMT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetHILMT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CHLMT & SDADC_CHLMT_HILMT_MASK) >> SDADC_CHLMT_HILMT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of RDATA. + * Result Data + * Read this register to get the conversion results. Bit[31] is sign bit if RDFMT is signed and only support 32bit read. + * The data format may changed by TSRDM. + * When TSRDM=2'b00, read CRDATA will pop data from FIFO. RDATA[31:8] is a 24-bit conversion results and RDATA[7:0] is 8'h00. At this case, CRDATA can only be read when FIFO is enabled and not empty. + * When TSRDM=2'b01, read CRDATA will feedback latest conversion result and timestamp info, RDATA[31:16] is a cut and round 16-bit latest conversion result(update on last COC) and RDATA[15:0] is latest timestamp counter value. FIFO is not used.At this case, CRDATA can only be read at any time. + * When TSRDM=2'b10, read CRDATA will pop data from FIFO and a timestamp info captured by trigger will also be included. RDATA[31:16] is a cut and round 16-bit result from FIFO and RDATA[15:0] is captured timestamp counter value. FIFO is used and gated by timestamp trigger. At this case, CRDATA can only be read when FIFO is enabled and not empty. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of RDATA. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetRDATA(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CRDATA & SDADC_CRDATA_RDATA_MASK) >> SDADC_CRDATA_RDATA_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of MPDATA. + * Multi Purpose Data + * This register can be accessed by DBG_SEL. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of MPDATA. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMPDATA(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CMPDATA & SDADC_CMPDATA_MPDATA_MASK) >> SDADC_CMPDATA_MPDATA_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SIGN. + * Sign Signal for the PWM pattern + * 0b - Positive values + * 1b - Negative values + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SIGN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSIGN(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->PWM_GEN & SDADC_PWM_GEN_SIGN_MASK) >> SDADC_PWM_GEN_SIGN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of PWM_CNT. + * PWM Counter Value + * Counts the 32 cycles for each PWM pattern step.(-16 to 15) + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of PWM_CNT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetPWM_CNT(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->PWM_GEN & SDADC_PWM_GEN_PWM_CNT_MASK) >> SDADC_PWM_GEN_PWM_CNT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of PAT_CNT. + * PWM Pattern Counter Value + * Counts the 32 steps for each PWM pattern period. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of PAT_CNT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetPAT_CNT(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->PWM_GEN & SDADC_PWM_GEN_PAT_CNT_MASK) >> SDADC_PWM_GEN_PAT_CNT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of ON. + * ON Status + * 0b - PWM generator is stopped + * 1b - PWM generator is ON + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of ON. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetON(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->PWM_GEN & SDADC_PWM_GEN_ON_MASK) >> SDADC_PWM_GEN_ON_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of TRGSIGN_OEN. + * Sign Signal Related Trigger Out Enable + * 0b - disabled. + * 1b - Related trigger is enabled and will be set once SIGN falling edge is got. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TRGSIGN_OEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTRGSIGN_OEN(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->PWM_GEN & SDADC_PWM_GEN_TRGSIGN_OEN_MASK) >> SDADC_PWM_GEN_TRGSIGN_OEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set TRGSIGN_OEN. + * Sign Signal Related Trigger Out Enable + * 0b - disabled. + * 1b - Related trigger is enabled and will be set once SIGN falling edge is got. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value TRGSIGN_OEN value. + */ +LOCAL_INLINE void SDADC_HWA_SetTRGSIGN_OEN(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->PWM_GEN = (pSdadc->PWM_GEN & ~SDADC_PWM_GEN_TRGSIGN_OEN_MASK) | SDADC_PWM_GEN_TRGSIGN_OEN(u32Value); +} + +/** + * @brief Get the value of CLKSEL. + * PWM Generator Clock selection + * 00b - div_clk0 + * 01b - div_clk1 + * 10b - div_clk2 + * 11b - off + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of CLKSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetPWMCLKSEL(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->PWM_GEN & SDADC_PWM_GEN_CLKSEL_MASK) >> SDADC_PWM_GEN_CLKSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set CLKSEL. + * PWM Generator Clock selection + * 00b - div_clk0 + * 01b - div_clk1 + * 10b - div_clk2 + * 11b - off + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value CLKSEL value. + */ +LOCAL_INLINE void SDADC_HWA_SetCLKSEL(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->PWM_GEN = (pSdadc->PWM_GEN & ~SDADC_PWM_GEN_CLKSEL_MASK) | SDADC_PWM_GEN_CLKSEL(u32Value); +} + +/** + * @brief Get the value of BIT_REV. + * Bit Reverse Mode + * 0b - Normal mode, a triangle wave is used as PWM carrier. + * 1b - Bit reverse mode. A bit reversed sawtooth wave is used as PWM carrier. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of BIT_REV. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetBIT_REV(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->PWM_GEN & SDADC_PWM_GEN_BIT_REV_MASK) >> SDADC_PWM_GEN_BIT_REV_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set BIT_REV. + * Bit Reverse Mode + * 0b - Normal mode, a triangle wave is used as PWM carrier. + * 1b - Bit reverse mode. A bit reversed sawtooth wave is used as PWM carrier. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value BIT_REV value. + */ +LOCAL_INLINE void SDADC_HWA_SetBIT_REV(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->PWM_GEN = (pSdadc->PWM_GEN & ~SDADC_PWM_GEN_BIT_REV_MASK) | SDADC_PWM_GEN_BIT_REV(u32Value); +} + +/** + * @brief Get the value of POL. + * PWM Generator Polarity + * 0b - PWM generator output begin with +1 + * 1b - PWM generator output begin with -1 + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of POL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetPOL(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->PWM_GEN & SDADC_PWM_GEN_POL_MASK) >> SDADC_PWM_GEN_POL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set POL. + * PWM Generator Polarity + * 0b - PWM generator output begin with +1 + * 1b - PWM generator output begin with -1 + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value POL value. + */ +LOCAL_INLINE void SDADC_HWA_SetPOL(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->PWM_GEN = (pSdadc->PWM_GEN & ~SDADC_PWM_GEN_POL_MASK) | SDADC_PWM_GEN_POL(u32Value); +} + +/** + * @brief Get the value of PATTERN. + * PWM Generator Pattern + * Config this before set MEN. Clear the bits during PWM generator run will terminate the PWM generator outputs after completion of the current period(indicated by bit ON=0) + * 00b - Stopped + * 01b - Square wave + * 10b - Triangle + * 11b - Sine wave + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of PATTERN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetPATTERN(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->PWM_GEN & SDADC_PWM_GEN_PATTERN_MASK) >> SDADC_PWM_GEN_PATTERN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set PATTERN. + * PWM Generator Pattern + * Config this before set MEN. Clear the bits during PWM generator run will terminate the PWM generator outputs after completion of the current period(indicated by bit ON=0) + * 00b - Stopped + * 01b - Square wave + * 10b - Triangle + * 11b - Sine wave + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value PATTERN value. + */ +LOCAL_INLINE void SDADC_HWA_SetPATTERN(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->PWM_GEN = (pSdadc->PWM_GEN & ~SDADC_PWM_GEN_PATTERN_MASK) | SDADC_PWM_GEN_PATTERN(u32Value); +} + +/** + * @brief Get the value of TSVLD2. + * Timestamp Valid Flag for Channel 2 + * Indicates timestamp inforamtion is captured, it will be cleared if CTSINFO reigister is readed. + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TSVLD2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSVLD2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIS & SDADC_EXTIS_TSVLD2_MASK) >> SDADC_EXTIS_TSVLD2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear TSVLD2. + * Timestamp Valid Flag for Channel 2 + * Indicates timestamp inforamtion is captured, it will be cleared if CTSINFO reigister is readed. + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearTSVLD2(SDADC_Type *const pSdadc) +{ + pSdadc->EXTIS = SDADC_EXTIS_TSVLD2(1); +} + +/** + * @brief Get the value of TSVLD1. + * Timestamp Valid Flag for Channel 1 + * Indicates timestamp inforamtion is captured, it will be cleared if CTSINFO reigister is readed. + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TSVLD1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSVLD1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIS & SDADC_EXTIS_TSVLD1_MASK) >> SDADC_EXTIS_TSVLD1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear TSVLD1. + * Timestamp Valid Flag for Channel 1 + * Indicates timestamp inforamtion is captured, it will be cleared if CTSINFO reigister is readed. + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearTSVLD1(SDADC_Type *const pSdadc) +{ + pSdadc->EXTIS = SDADC_EXTIS_TSVLD1(1); +} + +/** + * @brief Get the value of TSVLD0. + * Timestamp Valid Flag for Channel 0 + * Indicates timestamp inforamtion is captured, it will be cleared if CTSINFO reigister is readed. + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TSVLD0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSVLD0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIS & SDADC_EXTIS_TSVLD0_MASK) >> SDADC_EXTIS_TSVLD0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear TSVLD0. + * Timestamp Valid Flag for Channel 0 + * Indicates timestamp inforamtion is captured, it will be cleared if CTSINFO reigister is readed. + * 0b - The flag is not asserted. + * 1b - The flag is asserted. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearTSVLD0(SDADC_Type *const pSdadc) +{ + pSdadc->EXTIS = SDADC_EXTIS_TSVLD0(1); +} + +/** + * @brief Get the value of TSIGN_P2N2. + * Trigger Sign Changed from 1 to 0 for Channel 2 + * Indicates TSIGN changed from 1 to 0 when RECT is on, this can be used as an INTG start trigger for a better angular evaluation. + * 0b - TSIGN is not changed. + * 1b - TSIGN is changed from 1 to 0. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TSIGN_P2N2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSIGN_P2N2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIS & SDADC_EXTIS_TSIGN_P2N2_MASK) >> SDADC_EXTIS_TSIGN_P2N2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear TSIGN_P2N2. + * Trigger Sign Changed from 1 to 0 for Channel 2 + * Indicates TSIGN changed from 1 to 0 when RECT is on, this can be used as an INTG start trigger for a better angular evaluation. + * 0b - TSIGN is not changed. + * 1b - TSIGN is changed from 1 to 0. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearTSIGN_P2N2(SDADC_Type *const pSdadc) +{ + pSdadc->EXTIS = SDADC_EXTIS_TSIGN_P2N2(1); +} + +/** + * @brief Get the value of TSIGN_P2N1. + * Trigger Sign Changed from 1 to 0 for Channel 1 + * Indicates TSIGN changed from 1 to 0 when RECT is on, this can be used as an INTG start trigger for a better angular evaluation. + * 0b - TSIGN is not changed. + * 1b - TSIGN is changed from 1 to 0. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TSIGN_P2N1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSIGN_P2N1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIS & SDADC_EXTIS_TSIGN_P2N1_MASK) >> SDADC_EXTIS_TSIGN_P2N1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear TSIGN_P2N1. + * Trigger Sign Changed from 1 to 0 for Channel 1 + * Indicates TSIGN changed from 1 to 0 when RECT is on, this can be used as an INTG start trigger for a better angular evaluation. + * 0b - TSIGN is not changed. + * 1b - TSIGN is changed from 1 to 0. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearTSIGN_P2N1(SDADC_Type *const pSdadc) +{ + pSdadc->EXTIS = SDADC_EXTIS_TSIGN_P2N1(1); +} + +/** + * @brief Get the value of TSIGN_P2N0. + * Trigger Sign Changed from 1 to 0 for Channel 0 + * Indicates TSIGN changed from 1 to 0 when RECT is on, this can be used as an INTG start trigger for a better angular evaluation. + * 0b - TSIGN is not changed. + * 1b - TSIGN is changed from 1 to 0. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TSIGN_P2N0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSIGN_P2N0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIS & SDADC_EXTIS_TSIGN_P2N0_MASK) >> SDADC_EXTIS_TSIGN_P2N0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear TSIGN_P2N0. + * Trigger Sign Changed from 1 to 0 for Channel 0 + * Indicates TSIGN changed from 1 to 0 when RECT is on, this can be used as an INTG start trigger for a better angular evaluation. + * 0b - TSIGN is not changed. + * 1b - TSIGN is changed from 1 to 0. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearTSIGN_P2N0(SDADC_Type *const pSdadc) +{ + pSdadc->EXTIS = SDADC_EXTIS_TSIGN_P2N0(1); +} + +/** + * @brief Get the value of MCIC_COC2. + * Filter Channel 2 Conversion Complete Flag for MCIC + * Means MCIC data or rectification output or most recent accumulation data in Channel Integration Value Register is valid. + * When integration is not enabled, this is the same as COC. + * When integration is enabled and on, this is not the same as COC which is means integration output valid. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of MCIC_COC2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMCIC_COC2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIS & SDADC_EXTIS_MCIC_COC2_MASK) >> SDADC_EXTIS_MCIC_COC2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear MCIC_COC2. + * Filter Channel 2 Conversion Complete Flag for MCIC + * Means MCIC data or rectification output or most recent accumulation data in Channel Integration Value Register is valid. + * When integration is not enabled, this is the same as COC. + * When integration is enabled and on, this is not the same as COC which is means integration output valid. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearMCIC_COC2(SDADC_Type *const pSdadc) +{ + pSdadc->EXTIS = SDADC_EXTIS_MCIC_COC2(1); +} + +/** + * @brief Get the value of MCIC_COC1. + * Filter Channel 1 Conversion Complete Flag for MCIC + * Means MCIC data or rectification output or most recent accumulation data in Channel Integration Value Register is valid. + * When integration is not enabled, this is the same as COC. + * When integration is enabled and on, this is not the same as COC which is means integration output valid. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of MCIC_COC1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMCIC_COC1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIS & SDADC_EXTIS_MCIC_COC1_MASK) >> SDADC_EXTIS_MCIC_COC1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear MCIC_COC1. + * Filter Channel 1 Conversion Complete Flag for MCIC + * Means MCIC data or rectification output or most recent accumulation data in Channel Integration Value Register is valid. + * When integration is not enabled, this is the same as COC. + * When integration is enabled and on, this is not the same as COC which is means integration output valid. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearMCIC_COC1(SDADC_Type *const pSdadc) +{ + pSdadc->EXTIS = SDADC_EXTIS_MCIC_COC1(1); +} + +/** + * @brief Get the value of MCIC_COC0. + * Filter channel 0 Conversion Complete Flag for MCIC. + * Means MCIC data or rectification output or most recent accumulation data in Channel Integration Value Register is valid. + * When integration is not enabled, this is the same as COC. + * When integration is enabled and on, this is not the same as COC which is means integration output valid. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of MCIC_COC0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMCIC_COC0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIS & SDADC_EXTIS_MCIC_COC0_MASK) >> SDADC_EXTIS_MCIC_COC0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear MCIC_COC0. + * Filter channel 0 Conversion Complete Flag for MCIC. + * Means MCIC data or rectification output or most recent accumulation data in Channel Integration Value Register is valid. + * When integration is not enabled, this is the same as COC. + * When integration is enabled and on, this is not the same as COC which is means integration output valid. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearMCIC_COC0(SDADC_Type *const pSdadc) +{ + pSdadc->EXTIS = SDADC_EXTIS_MCIC_COC0(1); +} + +/** + * @brief Get the value of SD_CAPVLD2. + * Capture Valid Flag for channel 2 + * Indicates a new value in bitfield SD_CAP. This bit can be cleared by read related CSDRn register. + * 0b - no new result available. + * 1b - SD_CAP has been updated with a new captured value and has not been read. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SD_CAPVLD2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSD_CAPVLD2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIS & SDADC_EXTIS_SD_CAPVLD2_MASK) >> SDADC_EXTIS_SD_CAPVLD2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear SD_CAPVLD2. + * Capture Valid Flag for channel 2 + * Indicates a new value in bitfield SD_CAP. This bit can be cleared by read related CSDRn register. + * 0b - no new result available. + * 1b - SD_CAP has been updated with a new captured value and has not been read. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearSD_CAPVLD2(SDADC_Type *const pSdadc) +{ + pSdadc->EXTIS = SDADC_EXTIS_SD_CAPVLD2(1); +} + +/** + * @brief Get the value of SD_CAPVLD1. + * Capture Valid Flag for channel 1 + * Indicates a new value in bitfield SD_CAP. This bit can be cleared by read related CSDRn register. + * 0b - no new result available. + * 1b - SD_CAP has been updated with a new captured value and has not been read. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SD_CAPVLD1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSD_CAPVLD1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIS & SDADC_EXTIS_SD_CAPVLD1_MASK) >> SDADC_EXTIS_SD_CAPVLD1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear SD_CAPVLD1. + * Capture Valid Flag for channel 1 + * Indicates a new value in bitfield SD_CAP. This bit can be cleared by read related CSDRn register. + * 0b - no new result available. + * 1b - SD_CAP has been updated with a new captured value and has not been read. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearSD_CAPVLD1(SDADC_Type *const pSdadc) +{ + pSdadc->EXTIS = SDADC_EXTIS_SD_CAPVLD1(1); +} + +/** + * @brief Get the value of SD_CAPVLD0. + * Capture Valid Flag for channel 0 + * Indicates a new value in bitfield SD_CAP. This bit can be cleared by read related CSDRn register. + * 0b - no new result available. + * 1b - SD_CAP has been updated with a new captured value and has not been read. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SD_CAPVLD0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSD_CAPVLD0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIS & SDADC_EXTIS_SD_CAPVLD0_MASK) >> SDADC_EXTIS_SD_CAPVLD0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Clear SD_CAPVLD0. + * Capture Valid Flag for channel 0 + * Indicates a new value in bitfield SD_CAP. This bit can be cleared by read related CSDRn register. + * 0b - no new result available. + * 1b - SD_CAP has been updated with a new captured value and has not been read. + * @param pSdadc the base address of the SDADC instance. + + */ +LOCAL_INLINE void SDADC_HWA_ClearSD_CAPVLD0(SDADC_Type *const pSdadc) +{ + pSdadc->EXTIS = SDADC_EXTIS_SD_CAPVLD0(1); +} + +/** + * @brief Get the value of TSVLD_IE2. + * Timestamp Valid Interrupt Enable for channel 2 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TSVLD_IE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSVLD_IE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIE & SDADC_EXTIE_TSVLD_IE2_MASK) >> SDADC_EXTIE_TSVLD_IE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set TSVLD_IE2. + * Timestamp Valid Interrupt Enable for channel 2 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value TSVLD_IE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetTSVLD_IE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->EXTIE = (pSdadc->EXTIE & ~SDADC_EXTIE_TSVLD_IE2_MASK) | SDADC_EXTIE_TSVLD_IE2(u32Value); +} + +/** + * @brief Get the value of TSVLD_IE1. + * Timestamp Valid Interrupt Enable for channel 1 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TSVLD_IE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSVLD_IE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIE & SDADC_EXTIE_TSVLD_IE1_MASK) >> SDADC_EXTIE_TSVLD_IE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set TSVLD_IE1. + * Timestamp Valid Interrupt Enable for channel 1 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value TSVLD_IE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetTSVLD_IE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->EXTIE = (pSdadc->EXTIE & ~SDADC_EXTIE_TSVLD_IE1_MASK) | SDADC_EXTIE_TSVLD_IE1(u32Value); +} + +/** + * @brief Get the value of TSVLD_IE0. + * Timestamp Valid Interrupt Enable for channel 0 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TSVLD_IE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSVLD_IE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIE & SDADC_EXTIE_TSVLD_IE0_MASK) >> SDADC_EXTIE_TSVLD_IE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set TSVLD_IE0. + * Timestamp Valid Interrupt Enable for channel 0 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value TSVLD_IE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetTSVLD_IE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->EXTIE = (pSdadc->EXTIE & ~SDADC_EXTIE_TSVLD_IE0_MASK) | SDADC_EXTIE_TSVLD_IE0(u32Value); +} + +/** + * @brief Get the value of TSIGN_P2N_IE2. + * Trigger Sign Changed from 1 to 0 Interrupt Enable for channel 2 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TSIGN_P2N_IE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSIGN_P2N_IE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIE & SDADC_EXTIE_TSIGN_P2N_IE2_MASK) >> SDADC_EXTIE_TSIGN_P2N_IE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set TSIGN_P2N_IE2. + * Trigger Sign Changed from 1 to 0 Interrupt Enable for channel 2 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value TSIGN_P2N_IE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetTSIGN_P2N_IE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->EXTIE = (pSdadc->EXTIE & ~SDADC_EXTIE_TSIGN_P2N_IE2_MASK) | SDADC_EXTIE_TSIGN_P2N_IE2(u32Value); +} + +/** + * @brief Get the value of TSIGN_P2N_IE1. + * Trigger Sign Changed from 1 to 0 Interrupt Enable for channel 1 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TSIGN_P2N_IE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSIGN_P2N_IE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIE & SDADC_EXTIE_TSIGN_P2N_IE1_MASK) >> SDADC_EXTIE_TSIGN_P2N_IE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set TSIGN_P2N_IE1. + * Trigger Sign Changed from 1 to 0 Interrupt Enable for channel 1 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value TSIGN_P2N_IE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetTSIGN_P2N_IE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->EXTIE = (pSdadc->EXTIE & ~SDADC_EXTIE_TSIGN_P2N_IE1_MASK) | SDADC_EXTIE_TSIGN_P2N_IE1(u32Value); +} + +/** + * @brief Get the value of TSIGN_P2N_IE0. + * Trigger Sign Changed from 1 to 0 Interrupt Enable for channel 0 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of TSIGN_P2N_IE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSIGN_P2N_IE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIE & SDADC_EXTIE_TSIGN_P2N_IE0_MASK) >> SDADC_EXTIE_TSIGN_P2N_IE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set TSIGN_P2N_IE0. + * Trigger Sign Changed from 1 to 0 Interrupt Enable for channel 0 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value TSIGN_P2N_IE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetTSIGN_P2N_IE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->EXTIE = (pSdadc->EXTIE & ~SDADC_EXTIE_TSIGN_P2N_IE0_MASK) | SDADC_EXTIE_TSIGN_P2N_IE0(u32Value); +} + +/** + * @brief Get the value of SD_CAPVLD_IE2. + * Capture Valid Interrupt Enable for channel 2 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SD_CAPVLD_IE2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSD_CAPVLD_IE2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIE & SDADC_EXTIE_SD_CAPVLD_IE2_MASK) >> SDADC_EXTIE_SD_CAPVLD_IE2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set SD_CAPVLD_IE2. + * Capture Valid Interrupt Enable for channel 2 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value SD_CAPVLD_IE2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetSD_CAPVLD_IE2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->EXTIE = (pSdadc->EXTIE & ~SDADC_EXTIE_SD_CAPVLD_IE2_MASK) | SDADC_EXTIE_SD_CAPVLD_IE2(u32Value); +} + +/** + * @brief Get the value of SD_CAPVLD_IE1. + * Capture Valid Interrupt Enable for channel 1 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SD_CAPVLD_IE1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSD_CAPVLD_IE1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIE & SDADC_EXTIE_SD_CAPVLD_IE1_MASK) >> SDADC_EXTIE_SD_CAPVLD_IE1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set SD_CAPVLD_IE1. + * Capture Valid Interrupt Enable for channel 1 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value SD_CAPVLD_IE1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetSD_CAPVLD_IE1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->EXTIE = (pSdadc->EXTIE & ~SDADC_EXTIE_SD_CAPVLD_IE1_MASK) | SDADC_EXTIE_SD_CAPVLD_IE1(u32Value); +} + +/** + * @brief Get the value of SD_CAPVLD_IE0. + * Capture Valid Interrupt Enable for channel 0 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of SD_CAPVLD_IE0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSD_CAPVLD_IE0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTIE & SDADC_EXTIE_SD_CAPVLD_IE0_MASK) >> SDADC_EXTIE_SD_CAPVLD_IE0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set SD_CAPVLD_IE0. + * Capture Valid Interrupt Enable for channel 0 + * 0b - The interrupt is disabled. + * 1b - The interrupt is enabled. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value SD_CAPVLD_IE0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetSD_CAPVLD_IE0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->EXTIE = (pSdadc->EXTIE & ~SDADC_EXTIE_SD_CAPVLD_IE0_MASK) | SDADC_EXTIE_SD_CAPVLD_IE0(u32Value); +} + +/** + * @brief Get the value of INTG_STRIG2. + * Integration Software Trigger for channel 2 + * Setting this bit will trigger to start of the integration when the integration is enabled. + * Clearing this bit will stop integration. So it works like a level event. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of INTG_STRIG2. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINTG_STRIG2(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTCTRL & SDADC_EXTCTRL_INTG_STRIG2_MASK) >> SDADC_EXTCTRL_INTG_STRIG2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set INTG_STRIG2. + * Integration Software Trigger for channel 2 + * Setting this bit will trigger to start of the integration when the integration is enabled. + * Clearing this bit will stop integration. So it works like a level event. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value INTG_STRIG2 value. + */ +LOCAL_INLINE void SDADC_HWA_SetINTG_STRIG2(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->EXTCTRL = (pSdadc->EXTCTRL & ~SDADC_EXTCTRL_INTG_STRIG2_MASK) | SDADC_EXTCTRL_INTG_STRIG2(u32Value); +} + +/** + * @brief Get the value of INTG_STRIG1. + * Integration Software Trigger for channel 1 + * Setting this bit will trigger to start of the integration when the integration is enabled. + * Clearing this bit will stop integration. So it works like a level event. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of INTG_STRIG1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINTG_STRIG1(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTCTRL & SDADC_EXTCTRL_INTG_STRIG1_MASK) >> SDADC_EXTCTRL_INTG_STRIG1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set INTG_STRIG1. + * Integration Software Trigger for channel 1 + * Setting this bit will trigger to start of the integration when the integration is enabled. + * Clearing this bit will stop integration. So it works like a level event. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value INTG_STRIG1 value. + */ +LOCAL_INLINE void SDADC_HWA_SetINTG_STRIG1(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->EXTCTRL = (pSdadc->EXTCTRL & ~SDADC_EXTCTRL_INTG_STRIG1_MASK) | SDADC_EXTCTRL_INTG_STRIG1(u32Value); +} + +/** + * @brief Get the value of INTG_STRIG0. + * Integration Software Trigger for channel 0 + * Setting this bit will trigger to start of the integration when the integration is enabled. + * Clearing this bit will stop integration. So it works like a level event. + * @param pSdadc the base address of the SDADC instance. + + * @return uint32_t the value of INTG_STRIG0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINTG_STRIG0(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->EXTCTRL & SDADC_EXTCTRL_INTG_STRIG0_MASK) >> SDADC_EXTCTRL_INTG_STRIG0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set INTG_STRIG0. + * Integration Software Trigger for channel 0 + * Setting this bit will trigger to start of the integration when the integration is enabled. + * Clearing this bit will stop integration. So it works like a level event. + * @param pSdadc the base address of the SDADC instance. + + * @param uint32_t u32Value INTG_STRIG0 value. + */ +LOCAL_INLINE void SDADC_HWA_SetINTG_STRIG0(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->EXTCTRL = (pSdadc->EXTCTRL & ~SDADC_EXTCTRL_INTG_STRIG0_MASK) | SDADC_EXTCTRL_INTG_STRIG0(u32Value); +} + +/** + * @brief Get the value of BIAS_ON. + * Bias On Flag + * 0b - Bias analog is not ready for using. + * 1b - Bias analog is ready for using. + * @param pSdadc the base address of the SDADC instance. + * @return uint32_t the value of BIAS_ON. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetBIAS_ON(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->BACSR[0] & SDADC_BACSR_BIAS_ON_MASK) >> SDADC_BACSR_BIAS_ON_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of BSTC. + * Bias Start Time Control + * Bias analog need a ~2us start time, this bits control number of div_clk1 cycles before BIAS_ON flag set after BIAS_EN set. + * @param pSdadc the base address of the SDADC instance. + * @return uint32_t the value of BSTC. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetBSTC(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->BACSR[0] & SDADC_BACSR_BSTC_MASK) >> SDADC_BACSR_BSTC_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set BSTC. + * Bias Start Time Control + * Bias analog need a ~2us start time, this bits control number of div_clk1 cycles before BIAS_ON flag set after BIAS_EN set. + * @param pSdadc the base address of the SDADC instance. + * @param uint32_t u32Value BSTC value. + */ +LOCAL_INLINE void SDADC_HWA_SetBSTC(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->BACSR[0] = (pSdadc->BACSR[0] & ~SDADC_BACSR_BSTC_MASK) | SDADC_BACSR_BSTC(u32Value); +} + +/** + * @brief Get the value of VCM_BEN. + * Common Mode Voltage Bias Enable + * Enable common mode voltage for AC input of internal modulator analog. + * 0b - Common mode voltage Bias is disabled. + * 1b - Common mode voltage Bias is enabled. + * @param pSdadc the base address of the SDADC instance. + * @return uint32_t the value of VCM_BEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetVCM_BEN(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->BACSR[0] & SDADC_BACSR_VCM_BEN_MASK) >> SDADC_BACSR_VCM_BEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set VCM_BEN. + * Common Mode Voltage Bias Enable + * Enable common mode voltage for AC input of internal modulator analog. + * 0b - Common mode voltage Bias is disabled. + * 1b - Common mode voltage Bias is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param uint32_t u32Value VCM_BEN value. + */ +LOCAL_INLINE void SDADC_HWA_SetVCM_BEN(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->BACSR[0] = (pSdadc->BACSR[0] & ~SDADC_BACSR_VCM_BEN_MASK) | SDADC_BACSR_VCM_BEN(u32Value); +} + +/** + * @brief Get the value of HFVREF_EN. + * Half VREFH output Enable to Related Internal Modulator Analog. + * Bit 4 enable internal Half VREFH output to modulator analog for channel 0. + * Bit 5 enable internal Half VREFH output to modulator analog for channel 1. + * Bit 6 enable internal Half VREFH output to modulator analog for channel 2. + * Bit 7 enable internal Half VREFH output to modulator analog for channel 3. + * NOTE: Not all channels have internal modulator analog, if the channel has no internal modulator analog, related control bit is reserved. + * @param pSdadc the base address of the SDADC instance. + * @return uint32_t the value of HFVREF_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetHFVREF_EN(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->BACSR[0] & SDADC_BACSR_HFVREF_EN_MASK) >> SDADC_BACSR_HFVREF_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set HFVREF_EN. + * Half VREFH output Enable to Related Internal Modulator Analog. + * Bit 4 enable internal Half VREFH output to modulator analog for channel 0. + * Bit 5 enable internal Half VREFH output to modulator analog for channel 1. + * Bit 6 enable internal Half VREFH output to modulator analog for channel 2. + * Bit 7 enable internal Half VREFH output to modulator analog for channel 3. + * NOTE: Not all channels have internal modulator analog, if the channel has no internal modulator analog, related control bit is reserved. + * @param pSdadc the base address of the SDADC instance. + * @param uint32_t u32Value HFVREF_EN value. + */ +LOCAL_INLINE void SDADC_HWA_SetHFVREF_EN(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->BACSR[0] = (pSdadc->BACSR[0] & ~SDADC_BACSR_HFVREF_EN_MASK) | SDADC_BACSR_HFVREF_EN(u32Value); +} + +/** + * @brief Get the value of BIAS_EN. + * Bias Analog Enable + * 0b - Bias analog is disabled. + * 1b - Bias analog is enabled. + * @param pSdadc the base address of the SDADC instance. + * @return uint32_t the value of BIAS_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetBIAS_EN(const SDADC_Type *const pSdadc) +{ + uint32_t u32TmpVal = (pSdadc->BACSR[0] & SDADC_BACSR_BIAS_EN_MASK) >> SDADC_BACSR_BIAS_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set BIAS_EN. + * Bias Analog Enable + * 0b - Bias analog is disabled. + * 1b - Bias analog is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param uint32_t u32Value BIAS_EN value. + */ +LOCAL_INLINE void SDADC_HWA_SetBIAS_EN(SDADC_Type *const pSdadc, uint32_t u32Value) +{ + pSdadc->BACSR[0] = (pSdadc->BACSR[0] & ~SDADC_BACSR_BIAS_EN_MASK) | SDADC_BACSR_BIAS_EN(u32Value); +} + +/** + * @brief Get the value of DSIGN. + * Delayed Sign Signal + * 0b - Positive values. + * 1b - Negative values. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of DSIGN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetDSIGN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CRTCSR[u8Channel] & SDADC_CRTCSR_DSIGN_MASK) >> SDADC_CRTCSR_DSIGN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SSIGN. + * Selected Sign Signal + * 0b - Positive values. + * 1b - Negative values. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SSIGN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSSIGN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CRTCSR[u8Channel] & SDADC_CRTCSR_SSIGN_MASK) >> SDADC_CRTCSR_SSIGN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SDON. + * Sign Delay Counter on Flag + * Indicates the activity of the sign delay counter. + * 0b - Sign delay counter stopped. + * 1b - Sign delay counter enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SDON. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSDON(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CRTCSR[u8Channel] & SDADC_CRTCSR_SDON_MASK) >> SDADC_CRTCSR_SDON_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of TSIGN. + * Sign Signal for Channel Trigger Output + * This sign can be configured to some cycles before DSIGN, and can be used to generate channel trigger output, typically can be used to trigger integration so that it can start at the ZCD point + * 0b - Positive values. + * 1b - Negative values. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of TSIGN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSIGN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CRTCSR[u8Channel] & SDADC_CRTCSR_TSIGN_MASK) >> SDADC_CRTCSR_TSIGN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of DLY_TRG. + * Sign Delay Value for TSIGN Posedge + * TSIGN is clear at DLY_TRG and set at DLY_NEG in CSDRn + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of DLY_TRG. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetDLY_TRG(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CRTCSR[u8Channel] & SDADC_CRTCSR_DLY_TRG_MASK) >> SDADC_CRTCSR_DLY_TRG_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of CTRGSIGN_OEN. + * Channel Sign Signal Related Trigger Out Enable + * 0b - disabled. + * 1b - Related trigger is enabled and will be set once TSIGN falling edge is got. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of CTRGSIGN_OEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCTRGSIGN_OEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CRTCSR[u8Channel] & SDADC_CRTCSR_CTRGSIGN_OEN_MASK) >> SDADC_CRTCSR_CTRGSIGN_OEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set the value of CTRGSIGN_OEN. + * Channel Sign Signal Related Trigger Out Enable + * 0b - disabled. + * 1b - Related trigger is enabled and will be set once TSIGN falling edge is got. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param u8Enable Value. + */ +LOCAL_INLINE void SDADC_HWA_SetCTRGSIGN_OEN(SDADC_Type *const pSdadc, uint8_t u8Channel, uint8_t u8Enable) +{ + pSdadc->CRTCSR[u8Channel] = (pSdadc->CRTCSR[u8Channel] & ~SDADC_CRTCSR_CTRGSIGN_OEN_MASK) | SDADC_CRTCSR_CTRGSIGN_OEN(u8Enable); +} + +/** + * @brief Get the value of SSCH. + * Sign Signal From Channel Selection + * Select the channel providing the sign signal if SSRC =01b + * 0000b - From channel 0. + * 0001b - From channel 1. + * 0010b - From channel 2. + * ... + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SSCH. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSSCH(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CRTCSR[u8Channel] & SDADC_CRTCSR_SSCH_MASK) >> SDADC_CRTCSR_SSCH_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SSRC. + * Sign Source Selection + * Select the sign signal to be delayed. + * 00b - SDADC internal PWM generation block. + * 01b - Sign of result of channel selected by SSCH. + * 10b - External sign signal 0. + * 11b - External sign signal 1. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SSRC. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSSRC(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CRTCSR[u8Channel] & SDADC_CRTCSR_SSRC_MASK) >> SDADC_CRTCSR_SSRC_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of DLY_NEG. + * Sign Delay Value for Sign Negedge + * Defines the content of SD_CNT to generate a positive delayed sign DSIGN + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of DLY_NEG. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetDLY_NEG(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CSDR[u8Channel] & SDADC_CSDR_DLY_NEG_MASK) >> SDADC_CSDR_DLY_NEG_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of DLY_POS. + * Sign Delay Value for Sign Posedge + * Defines the content of SD_CNT to generate a negative delayed sign DSIGN + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of DLY_POS. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetDLY_POS(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CSDR[u8Channel] & SDADC_CSDR_DLY_POS_MASK) >> SDADC_CSDR_DLY_POS_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SD_CAP. + * Sign Delay Capture Value + * Indicates the results value counted between the negedge of SSIGN and the first received positive value + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SD_CAP. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSD_CAP(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CSDR[u8Channel] & SDADC_CSDR_SD_CAP_MASK) >> SDADC_CSDR_SD_CAP_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SD_CNT. + * Sign Delay Counter + * Counts the results values from the filter chain to delay the sign signal, this fild can only be checked after MCIC_COC assert. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SD_CNT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetSD_CNT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CSDR[u8Channel] & SDADC_CSDR_SD_CNT_MASK) >> SDADC_CSDR_SD_CNT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of NVALINT. + * Number of Values to be Accumulated + * NVALINT+1 defines a complete integration cycle + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of NVALINT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetNVALINT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CICFR[u8Channel] & SDADC_CICFR_NVALINT_MASK) >> SDADC_CICFR_NVALINT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of NVALDIS. + * Number of Values discarded + * Start the integration cycle after NVALDIS values + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of NVALDIS. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetNVALDIS(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CICFR[u8Channel] & SDADC_CICFR_NVALDIS_MASK) >> SDADC_CICFR_NVALDIS_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SYNC_TRGEN. + * Synced Trigger Select Enable for Integration + * 0b - Synced trigger is selected on the channel itself. + * 1b - Synced trigger is selected on the channel defined by SYNC_TRGSEL. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SYNC_TRGEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCICFR_SYNC_TRGEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CICFR[u8Channel] & SDADC_CICFR_SYNC_TRGEN_MASK) >> SDADC_CICFR_SYNC_TRGEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SYNC_TRGSEL. + * Synced Trigger Select for Integration + * Each will detect and sync the trigger input as a synced trigger, this bits can select to use the synced trigger from which channel. By this bits, two or more channels can share the same synced trigger and trigger to start at the same time. + * 000b - select the trigger from the channel 0. + * 001b - select the trigger from the channel 1. + * 010b - select the trigger from the channel 2. + * ... + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SYNC_TRGSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCICFR_SYNC_TRGSEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CICFR[u8Channel] & SDADC_CICFR_SYNC_TRGSEL_MASK) >> SDADC_CICFR_SYNC_TRGSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of NVALREP. + * Number of Integration Cycles + * NVALREP+1 defines number of integration cycles to be counted by REPCNT if activated(EXTSTP=0) + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of NVALREP. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetNVALREP(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CICFR[u8Channel] & SDADC_CICFR_NVALREP_MASK) >> SDADC_CICFR_NVALREP_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of ITRSEL. + * Integration Trigger Select + * 0b - Software trigger selected. + * 1b - Hardware trigger dedicate to channel selected. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of ITRSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetITRSEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CICFR[u8Channel] & SDADC_CICFR_ITRSEL_MASK) >> SDADC_CICFR_ITRSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of HTRPOL. + * Hardware Trigger Polarity + * 0b - High and rising edge effective. + * 1b - Low and falling edge effective. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of HTRPOL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetHTRPOL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CICFR[u8Channel] & SDADC_CICFR_HTRPOL_MASK) >> SDADC_CICFR_HTRPOL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of FCRC. + * Filter Chain Restart Control + * 0b - Do not restart. + * 1b - Restart the filter chain when an integration window starts. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of FCRC. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetFCRC(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CICFR[u8Channel] & SDADC_CICFR_FCRC_MASK) >> SDADC_CICFR_FCRC_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of EXTSTP. + * Integration Stop Control + * For Hardware trigger control only. + * 0b - Internal control, stop integration after NVALREP+1 integration cycles, support both edge and level events. + * 1b - External control, stop integration upon the inverse trigger event. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of EXTSTP. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetEXTSTP(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CICFR[u8Channel] & SDADC_CICFR_EXTSTP_MASK) >> SDADC_CICFR_EXTSTP_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of IOGT. + * Integration Output Gating + * Setting this bit will gate conversion complete flag and FIFO push when Integration is not on-going. conversion complete flag and FIFO push can only be effective when Integration is not on-going(INTON asserted) + * 0b - Conversion complete flag and FIFO push always works. + * 1b - Conversion complete flag and FIFO push can only work when Integration is not on-going(INTON asserted) + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of IOGT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetIOGT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CICFR[u8Channel] & SDADC_CICFR_IOGT_MASK) >> SDADC_CICFR_IOGT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of ISVAL. + * Integration Shift value + * 000b - Shift 0 bits + * 001b - Shift 1 bits, for 2 values integration + * 010b - Shift 2 bits, for 3-4 values integration + * 011b - Shift 3 bits, for 5-8 values integration + * 100b - Shift 4 bits, for 9-16 values integration + * 101b - Shift 5 bits, for 17-32 values integration + * 110b - Shift 6 bits, for 33-64 values integration + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of ISVAL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetISVAL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CICFR[u8Channel] & SDADC_CICFR_ISVAL_MASK) >> SDADC_CICFR_ISVAL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of INTGON. + * Integration on Flag + * Indicates the activity of the integration. + * 0b - Integration stopped. + * 1b - Integration enabled and on-going. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of INTGON. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINTGON(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CISR[u8Channel] & SDADC_CISR_INTGON_MASK) >> SDADC_CISR_INTGON_SHIFT; + return u32TmpVal; +} + +#ifdef SDADC_CISR_REPCNT_MASK +/** + * @brief Get the value of REPCNT. + * Repeat Integration Cycle Counter + * Counts the number of integration cycles if activated (EXTSTP=0), this field can only be checked after COC assert. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of REPCNT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetREPCNT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CISR[u8Channel] & SDADC_CISR_REPCNT_MASK) >> SDADC_CISR_REPCNT_SHIFT; + return u32TmpVal; +} +#endif + +#ifdef SDADC_CISR_VALCNT_MASK +/** + * @brief Get the value of VALCNT. + * Number of Values Counted + * Counts the number of integrated values during discard cycle or during integration cycles, this fild can only be checked after MCIC_COC assert. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of VALCNT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetVALCNT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CISR[u8Channel] & SDADC_CISR_VALCNT_MASK) >> SDADC_CISR_VALCNT_SHIFT; + return u32TmpVal; +} +#endif + +/** + * @brief Get the value of INTVAL. + * Results of most recent accumulation, this fild can only be checked after MCIC_COC assert. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of INTVAL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINTVAL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CIVAL[u8Channel] & SDADC_CIVAL_INTVAL_MASK) >> SDADC_CIVAL_INTVAL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of MASEL. + * Modulator Analog Selection + * 0b - External modulator analog is selected as channel input. + * 1b - Internal modulator analog is selected as channel input. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of MASEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMASEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_MASEL_MASK) >> SDADC_CMACSR_MASEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set MASEL. + * Modulator Analog Selection + * 0b - External modulator analog is selected as channel input. + * 1b - Internal modulator analog is selected as channel input. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param uint32_t u32Value MASEL value. + */ +LOCAL_INLINE void SDADC_HWA_SetMASEL(SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + pSdadc->CMACSR[u8Channel] = (pSdadc->CMACSR[u8Channel] & ~SDADC_CMACSR_MASEL_MASK) | SDADC_CMACSR_MASEL(u32Value); +} + +/** + * @brief Get the value of MACLKSEL. + * Internal Modulator Analog Clock Selection + * 00b - Div_clk1 is selected as the clock, output bitstream is sampled on a clock with frequency of F_div_clk1/2. + * 01b - Div_clk0 is selected as the clock, output bitstream is sampled on a clock with frequency of F_div_clk1/2. + * 1*b - Reserved. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of MACLKSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetMACLKSEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_MACLKSEL_MASK) >> SDADC_CMACSR_MACLKSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set MACLKSEL. + * Internal Modulator Analog Clock Selection + * 00b - Div_clk1 is selected as the clock, output bitstream is sampled on a clock with frequency of F_div_clk1/2. + * 01b - Div_clk0 is selected as the clock, output bitstream is sampled on a clock with frequency of F_div_clk1/2. + * 1*b - Reserved. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param uint32_t u32Value MACLKSEL value. + */ +LOCAL_INLINE void SDADC_HWA_SetMACLKSEL(SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + pSdadc->CMACSR[u8Channel] = (pSdadc->CMACSR[u8Channel] & ~SDADC_CMACSR_MACLKSEL_MASK) | SDADC_CMACSR_MACLKSEL(u32Value); +} + +/** + * @brief Get the value of RSTSEL. + * Modulator Analog Reset Cycle Selection + * Select RSTSEL+1 mclk cycles for modulator analog reset after a channel conversion trigger. This is needed especially when the input mux(INMUX) is changed. + * 0d - Modulator analog is not reset after a channel conversion trigger + * 1d - Modulator analog is reset for 2 mclk cycles after a channel conversion trigger. Total 7 mclk cycle cycles needed for filters start to run after a channel conversion trigger. + * 2d - Modulator analog is reset for 3 mclk cycles after a channel conversion trigger. Total 8 mclk cycle cycles needed for filters start to run after a channel conversion trigger. + * ... + * 8d - Modulator analog is reset for 9 mclk cycles after a channel conversion trigger. Total 14 mclk cycle cycles needed for filters start to run after a channel conversion trigger. + * 9-15d - Modulator analog is reset for 10 mclk cycles after a channel conversion trigger. Total 15 mclk cycle cycles needed for filters start to run after a channel conversion trigger. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of RSTSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetRSTSEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_RSTSEL_MASK) >> SDADC_CMACSR_RSTSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set RSTSEL. + * Modulator Analog Reset Cycle Selection + * Select RSTSEL+1 mclk cycles for modulator analog reset after a channel conversion trigger. This is needed especially when the input mux(INMUX) is changed. + * 0d - Modulator analog is not reset after a channel conversion trigger + * 1d - Modulator analog is reset for 2 mclk cycles after a channel conversion trigger. Total 7 mclk cycle cycles needed for filters start to run after a channel conversion trigger. + * 2d - Modulator analog is reset for 3 mclk cycles after a channel conversion trigger. Total 8 mclk cycle cycles needed for filters start to run after a channel conversion trigger. + * ... + * 8d - Modulator analog is reset for 9 mclk cycles after a channel conversion trigger. Total 14 mclk cycle cycles needed for filters start to run after a channel conversion trigger. + * 9-15d - Modulator analog is reset for 10 mclk cycles after a channel conversion trigger. Total 15 mclk cycle cycles needed for filters start to run after a channel conversion trigger. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param uint32_t u32Value RSTSEL value. + */ +LOCAL_INLINE void SDADC_HWA_SetRSTSEL(SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + pSdadc->CMACSR[u8Channel] = (pSdadc->CMACSR[u8Channel] & ~SDADC_CMACSR_RSTSEL_MASK) | SDADC_CMACSR_RSTSEL(u32Value); +} + +/** + * @brief Get the value of DITHER_EN. + * Dither Enable + * This bit enable the dither to analog circuit to remove the idle tone. + * 0b - Dither is disabled. + * 1b - Dither is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of DITHER_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetDITHER_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_DITHER_EN_MASK) >> SDADC_CMACSR_DITHER_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of INCFGPV11. + * Configuration of Positive Input Line with V11 from System + * This bit have higher priority then INCFGP, this this bit is set, INCFGP is ignored. + * 0b - Positive input from V11 disabled. + * 1b - Positive input from V11 enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of INCFGPV11. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINCFGPV11(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_INCFGPV11_MASK) >> SDADC_CMACSR_INCFGPV11_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of GAINSEL. + * Gain Select of Analog Input Path + * 00b - 1. + * 01b - 2. + * 10b - 4. + * 11b - 8. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of GAINSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetGAINSEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_GAINSEL_MASK) >> SDADC_CMACSR_GAINSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set GAINSEL. + * Gain Select of Analog Input Path + * 00b - 1. + * 01b - 2. + * 10b - 4. + * 11b - 8. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param uint32_t u32Value GAINSEL value. + */ +LOCAL_INLINE void SDADC_HWA_SetGAINSEL(SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + pSdadc->CMACSR[u8Channel] = (pSdadc->CMACSR[u8Channel] & ~SDADC_CMACSR_GAINSEL_MASK) | SDADC_CMACSR_GAINSEL(u32Value); +} + +/** + * @brief Get the value of CMENP. + * Common Voltage Configuration of Positive Inputs + * Defines the connection of respective negative input to the common mode voltage, bit n(0-3) controls if Pin n is connected to the common mode voltage. + * 0b - Is NOT connected to the common mode voltage. + * 1b - Is connected to the common mode voltage. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of CMENP. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCMENP(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_CMENP_MASK) >> SDADC_CMACSR_CMENP_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set CMENP. + * Common Voltage Configuration of Positive Inputs + * Defines the connection of respective negative input to the common mode voltage, bit n(0-3) controls if Pin n is connected to the common mode voltage. + * 0b - Is NOT connected to the common mode voltage. + * 1b - Is connected to the common mode voltage. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param uint32_t u32Value CMENP value. + */ +LOCAL_INLINE void SDADC_HWA_SetCMENP(SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + pSdadc->CMACSR[u8Channel] = (pSdadc->CMACSR[u8Channel] & ~SDADC_CMACSR_CMENP_MASK) | SDADC_CMACSR_CMENP(u32Value); +} + +/** + * @brief Get the value of CMENM. + * Common Voltage Configuration of Negative Inputs + * Defines the connection of respective negative input to the common mode voltage, bit n(0-3) controls if Pin n is connected to the common mode voltage. + * 0b - Is NOT connected to the common mode voltage. + * 1b - Is connected to the common mode voltage. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of CMENM. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCMENM(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_CMENM_MASK) >> SDADC_CMACSR_CMENM_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set CMENM. + * Common Voltage Configuration of Negative Inputs + * Defines the connection of respective negative input to the common mode voltage, bit n(0-3) controls if Pin n is connected to the common mode voltage. + * 0b - Is NOT connected to the common mode voltage. + * 1b - Is connected to the common mode voltage. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param uint32_t u32Value CMENM value. + */ +LOCAL_INLINE void SDADC_HWA_SetCMENM(SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + pSdadc->CMACSR[u8Channel] = (pSdadc->CMACSR[u8Channel] & ~SDADC_CMACSR_CMENM_MASK) | SDADC_CMACSR_CMENM(u32Value); +} + +/** + * @brief Get the value of INCFGP. + * Configuration of Positive Input Line + * 00b - From input Pin. + * 01b - From VREFL. + * 10b - From VREFH. + * 11b - From VREFH/2. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of INCFGP. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINCFGP(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_INCFGP_MASK) >> SDADC_CMACSR_INCFGP_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set INCFGP. + * Configuration of Positive Input Line + * 00b - From input Pin. + * 01b - From VREFL. + * 10b - From VREFH. + * 11b - From VREFH/2. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param uint32_t u32Value INCFGP value. + */ +LOCAL_INLINE void SDADC_HWA_SetINCFGP(SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + pSdadc->CMACSR[u8Channel] = (pSdadc->CMACSR[u8Channel] & ~SDADC_CMACSR_INCFGP_MASK) | SDADC_CMACSR_INCFGP(u32Value); +} + +/** + * @brief Get the value of INCFGM. + * Configuration of Negative Input Line + * 00b - From input Pin. + * 01b - From VREFL. + * 10b - From VREFH. + * 11b - From VREFH/2. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of INCFGM. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINCFGM(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_INCFGM_MASK) >> SDADC_CMACSR_INCFGM_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set INCFGM. + * Configuration of Negative Input Line + * 00b - From input Pin. + * 01b - From VREFL. + * 10b - From VREFH. + * 11b - From VREFH/2. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param uint32_t u32Value INCFGM value. + */ +LOCAL_INLINE void SDADC_HWA_SetINCFGM(SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + pSdadc->CMACSR[u8Channel] = (pSdadc->CMACSR[u8Channel] & ~SDADC_CMACSR_INCFGM_MASK) | SDADC_CMACSR_INCFGM(u32Value); +} + +/** + * @brief Get the value of INMUX. + * Active Input Pin Selection + * Indicates the active input pin selection for input MUX. + * 00b - Input pin 0 selected. + * 01b - Input pin 1 selected. + * 10b - Input pin 2 selected. + * 11b - Input pin 3 selected. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of INMUX. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINMUX(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_INMUX_MASK) >> SDADC_CMACSR_INMUX_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of INSEL. + * Input Pin Selection + * Defines the initial or permanent setting for the input MUX(bits INMUX) depending on the selected operating mode (bits INMOD). + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of INSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINSEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_INSEL_MASK) >> SDADC_CMACSR_INSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set INSEL. + * Input Pin Selection + * Defines the initial or permanent setting for the input MUX(bits INMUX) depending on the selected operating mode (bits INMOD). + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param uint32_t u32Value INSEL value. + */ +LOCAL_INLINE void SDADC_HWA_SetINSEL(SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + pSdadc->CMACSR[u8Channel] = (pSdadc->CMACSR[u8Channel] & ~SDADC_CMACSR_INSEL_MASK) | SDADC_CMACSR_INSEL(u32Value); +} + +/** + * @brief Get the value of INMOD. + * Input MUX Control Mode + * 00b - Software control mode (INMUX follows INSEL). + * 01b - Preset mode (load INMUX upon a channel conversion trigger). + * 10b - Scan mode (decrement INMUX upon a channel conversion trigger, wrap around to INSEL). + * 11b - Reserved. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of INMOD. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINMOD(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CMACSR[u8Channel] & SDADC_CMACSR_INMOD_MASK) >> SDADC_CMACSR_INMOD_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set INMOD. + * Input MUX Control Mode + * 00b - Software control mode (INMUX follows INSEL). + * 01b - Preset mode (load INMUX upon a channel conversion trigger). + * 10b - Scan mode (decrement INMUX upon a channel conversion trigger, wrap around to INSEL). + * 11b - Reserved. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param uint32_t u32Value INMOD value. + */ +LOCAL_INLINE void SDADC_HWA_SetINMOD(SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + pSdadc->CMACSR[u8Channel] = (pSdadc->CMACSR[u8Channel] & ~SDADC_CMACSR_INMOD_MASK) | SDADC_CMACSR_INMOD(u32Value); +} + +/** + * @brief Get the value of OPT1. + * Offset Option 1 + * This is an offset value provided by factory test for modulator analog input path gain=2. + * User need read this field and left shift it by 8 bit to form a 24-bit offset and then write to related CBR register + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of OPT1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetOffsetOPT1(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->COFCAL[u8Channel] & SDADC_COFCAL_OPT1_MASK) >> SDADC_COFCAL_OPT1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of OPT0. + * Offset Option 0 + * This is an offset value provided by factory test for modulator analog input path gain=1. + * User need read this field and left shift it by 8 bit to form a 24-bit offset and then write to related CBR register + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of OPT0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetOffsetOPT0(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->COFCAL[u8Channel] & SDADC_COFCAL_OPT0_MASK) >> SDADC_COFCAL_OPT0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of OPT1. + * Gain Option 1 + * This is a gain factor provided by factory test for modulator analog input path gain=2. + * User need read this field and multiply it with gain correction factor 2^m and then write to related CGNR register + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of OPT1. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetGainOPT1(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CGNCAL[u8Channel] & SDADC_CGNCAL_OPT1_MASK) >> SDADC_CGNCAL_OPT1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of OPT0. + * Gain Option 0 + * This is a gain factor provided by factory test for modulator analog input path gain=1. + * User need read this field and multiply it with gain correction factor 2^m and then write to related CGNR register + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of OPT0. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetGainOPT0(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CGNCAL[u8Channel] & SDADC_CGNCAL_OPT0_MASK) >> SDADC_CGNCAL_OPT0_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of GAIN_FAC. + * Gain Factor + * This bit field defines a gain factor(GAIN_FAC[17:0]/2^16, range is from 0 to 4) which is multiplied with the data after HPF to compensate the gain error caused by analog circuits or the gain mismatch when decimation factor is not 2^N, after compensation, the total gain from analog input to data from FIFO should be 1. + * GAIN_FAC can be got from calibration, it should be in a suitable range, or the data output may be saturated. + * When GAIN_FAC[17:0]=0, GAIN block is bypassed. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of GAIN_FAC. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetGAIN_FAC(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CGNR[u8Channel] & SDADC_CGNR_GAIN_FAC_MASK) >> SDADC_CGNR_GAIN_FAC_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SYNC_TRGEN. + * Synced Trigger Select Enable for Timestamp + * 0b - Synced trigger is selected on the channel itself. + * 1b - Synced trigger is selected on the channel defined by SYNC_TRGSEL. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SYNC_TRGEN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCTSCNT_SYNC_TRGEN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CTSCNT[u8Channel] & SDADC_CTSCNT_SYNC_TRGEN_MASK) >> SDADC_CTSCNT_SYNC_TRGEN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of SYNC_TRGSEL. + * Synced Trigger Select for Timestamp + * Each will detect and sync the trigger input as a synced trigger, this bits can select to use the synced trigger from which channel. By this bits, two or more channels can share the same synced trigger and trigger to start at the same time. + * 000b - Select the trigger from the channel 0. + * 001b - Select the trigger from the channel 1. + * 010b - Select the trigger from the channel 2. + * ... + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of SYNC_TRGSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCTSCNT_SYNC_TRGSEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CTSCNT[u8Channel] & SDADC_CTSCNT_SYNC_TRGSEL_MASK) >> SDADC_CTSCNT_SYNC_TRGSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of TSRDM. + * Timestamp Information Read Mode + * 00b - Default mode, timestamp information can only be got by reading CTSINFOn register captured by trigger event. FIFO is used for conversion results only and can be pop from FIFO by reading CRDATAn. + * + * 01b - Direct mode. Timestamp information is saved in CRDATAn[15:0]. Conversion result is not saved in FIFO(FIFO pop and push are gated), it is cut, round to 16-bit and saved in CRDATAn[31:16] once conversion completes. In this mode, application can read conversion result and timestamp information at same time. + * + * 10b - FIFO gating mode. The FIFO is gated before the timestamp trigger event(none active trigger level), a timestamp trigger event(rising edge or falling edge) will capture the current timestamp and save it in TSTAMP[15:0] of CTSINFOn register and CRDATAn[15:0] is bypass to TSTAMP[15:0]. This trigger will also capture last conversion result and save it in FIFO, and then following conversion results are push to FIFO one by one until trigger level is not active again, the 24 bits result out from FIFO is cut/ round to 16 bits and sent to CRDATAn[31:16]. In this mode, application read CRDATAn will get both conversion result and captured timestamp information at same time after the trigger. + * + * 11b - Reserved. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of TSRDM. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSRDM(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CTSCNT[u8Channel] & SDADC_CTSCNT_TSRDM_MASK) >> SDADC_CTSCNT_TSRDM_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of TSTRGM. + * Timestamp Counter Trigger Mode + * 00/11b - Trigger is ignored. + * 01b - Rising edge effective. Trigger level low will gating conversion results push to FIFO if TSRDM is 2'b10. Trigger level high will allow conversion results push to FIFO if TSRDM is 2'b10. + * 10b - Falling edge effective. Trigger level High will gating conversion results push to FIFO if TSRDM is 2'b10. Trigger level low will allow conversion results push to FIFO if TSRDM is 2'b10. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of TSTRGM. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSTRGM(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CTSCNT[u8Channel] & SDADC_CTSCNT_TSTRGM_MASK) >> SDADC_CTSCNT_TSTRGM_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of INMXCP. + * Input Mux Setting Copy Enable + * 0b - Disabled. + * 1b - Copy INMUX from CMACSR to TSTAMP[15:14]. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of INMXCP. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetINMXCP(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CTSCNT[u8Channel] & SDADC_CTSCNT_INMXCP_MASK) >> SDADC_CTSCNT_INMXCP_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of TS_EN. + * Timestamp Counter Enable + * 0b - Disabled. + * 1b - Counting at the rate selected by TSCLKSEL. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of TS_EN. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTS_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CTSCNT[u8Channel] & SDADC_CTSCNT_TS_EN_MASK) >> SDADC_CTSCNT_TS_EN_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of TSCLKSEL. + * Timestamp Counter Clock Selection + * 00b - Modulator clock. + * 01b - Modulator clock divided by 2. + * 10b - Modulator clock divided by 4. + * 11b - Modulator clock divided by 8. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of TSCLKSEL. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSCLKSEL(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CTSCNT[u8Channel] & SDADC_CTSCNT_TSCLKSEL_MASK) >> SDADC_CTSCNT_TSCLKSEL_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of TSCNT. + * Timestamp Counter Value + * TSCNT is clocked with the modulator clock and is cleared when a new result value has been generated. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of TSCNT. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSCNT(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CTSCNT[u8Channel] & SDADC_CTSCNT_TSCNT_MASK) >> SDADC_CTSCNT_TSCNT_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of TSDATA. + * The Latest Captured Conversion Result + * Copied from saved conversion result. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of TSDATA. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSDATA(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CTSINFO[u8Channel] & SDADC_CTSINFO_TSDATA_MASK) >> SDADC_CTSINFO_TSDATA_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of TSTAMP. + * The Latest Captured Timestamp Value + * Copy from timestamp counter TSCNT at the trigger event. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @return uint32_t the value of TSTAMP. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetTSTAMP(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pSdadc->CTSINFO[u8Channel] & SDADC_CTSINFO_TSTAMP_MASK) >> SDADC_CTSINFO_TSTAMP_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the value of the Channel Configuration Register (CFR) for a specified channel. + * + * This function retrieves the value of the Channel Configuration Register (CFR) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CFR value is to be retrieved. + * + * @return uint32_t the value of the CFR for the specified channel. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCFRn(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + return SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR; +} + +/** + * @brief Set the value of the Channel Configuration Register (CFR) for a specified channel. + * + * This function sets the value of the Channel Configuration Register (CFR) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CFR value is to be set. + * @param u32Value the value to be set in the CFR register. + */ +LOCAL_INLINE void SDADC_HWA_SetCFRn(const SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CFR = u32Value; +} + +/** + * @brief Get the value of the Channel Bias Register (CBR) for a specified channel. + * + * This function retrieves the value of the Channel Bias Register (CBR) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CBR value is to be retrieved. + * + * @return uint32_t the value of the CBR for the specified channel. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCBRn(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + return SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CBR; +} + +/** + * @brief Set the value of the Channel Bias Register (CBR) for a specified channel. + * + * This function sets the value of the Channel Bias Register (CBR) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CBR value is to be set. + * @param u32Value the value to be set in the CBR register. + */ +LOCAL_INLINE void SDADC_HWA_SetCBRn(const SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CBR = u32Value; +} + +/** + * @brief Get the value of the Channel Low Limit Register (CLLMT) for a specified channel. + * + * This function retrieves the value of the Channel Low Limit Register (CLLMT) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CLLMT value is to be retrieved. + * + * @return uint32_t the value of the CLLMT for the specified channel. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCLLMTn(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + return SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CLLMT; +} + +/** + * @brief Set the value of the Channel Low Limit Register (CLLMT) for a specified channel. + * + * This function sets the value of the Channel Low Limit Register (CLLMT) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CLLMT value is to be set. + * @param u32Value the value to be set in the CLLMT register. + */ +LOCAL_INLINE void SDADC_HWA_SetCLLMTn(const SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CLLMT = u32Value; +} + +/** + * @brief Get the value of the Channel High Limit Register (CHLMT) for a specified channel. + * + * This function retrieves the value of the Channel High Limit Register (CHLMT) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CHLMT value is to be retrieved. + * + * @return uint32_t the value of the CHLMT for the specified channel. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCHLMTn(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + return SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CHLMT; +} + +/** + * @brief Set the value of the Channel High Limit Register (CHLMT) for a specified channel. + * + * This function sets the value of the Channel High Limit Register (CHLMT) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CHLMT value is to be set. + * @param u32Value the value to be set in the CHLMT register. + */ +LOCAL_INLINE void SDADC_HWA_SetCHLMTn(const SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CHLMT = u32Value; +} + +/** + * @brief Get the value of the Channel Result Data Register (CRDATA) for a specified channel. + * + * This function retrieves the value of the Channel Result Data Register (CRDATA) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CRDATA value is to be retrieved. + * + * @return uint32_t the value of the CRDATA for the specified channel. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCRDATAn(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + return SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CRDATA; +} + +/** + * @brief Get the value of the Channel Multi Purpose Data Register (CMPDATA) for a specified channel. + * + * This function retrieves the value of the Channel Multi Purpose Data Register (CMPDATA) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CMPDATA value is to be retrieved. + * + * @return uint32_t the value of the CMPDATA for the specified channel. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCMPDATAn(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + return SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CMPDATA; +} + +/** + * @brief Get the value of the Channel Data Rate Register (CDR) for a specified channel. + * + * This function retrieves the value of the Channel Data Rate Register (CDR) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CDR value is to be retrieved. + * + * @return uint32_t the value of the CDR for the specified channel. + */ +LOCAL_INLINE uint32_t SDADC_HWA_GetCDRn(const SDADC_Type *const pSdadc, uint8_t u8Channel) +{ + return SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CDR; +} + +/** + * @brief Set the value of the Channel Data Rate Register (CDR) for a specified channel. + * + * This function sets the value of the Channel Data Rate Register (CDR) for a given channel + * in the SDADC instance. + * + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel the channel number for which the CDR value is to be set. + * @param u32Value the value to be set in the CDR register. + */ +LOCAL_INLINE void SDADC_HWA_SetCDRn(const SDADC_Type *const pSdadc, uint8_t u8Channel, uint32_t u32Value) +{ + SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CDR = u32Value; +} + +/** + * @brief Set the value of NISR. + * @param pSdadc the base address of the SDADC instance. + * @param u32Value Set Value. + */ +LOCAL_INLINE void SDADC_HWA_SetNISR(SDADC_Type *const pSdadc, uint32 u32Value) +{ + pSdadc->NISR = u32Value & SDADC_NISR_MASK; +} + +/** + * @brief Set the value of ABNISR0. + * @param pSdadc the base address of the SDADC instance. + * @param u32Value Set Value. + */ +LOCAL_INLINE void SDADC_HWA_SetABNISR0(SDADC_Type *const pSdadc, uint32 u32Value) +{ + pSdadc->ABNISR0 = u32Value & SDADC_ABNISR0_MASK; +} + +/** + * @brief Set the value of ABNISR1. + * @param pSdadc the base address of the SDADC instance. + * @param u32Value Set Value. + */ +LOCAL_INLINE void SDADC_HWA_SetABNISR1(SDADC_Type *const pSdadc, uint32 u32Value) +{ + pSdadc->ABNISR1 = u32Value & SDADC_ABNISR1_MASK; +} + +/** + * @brief Set the value of EXTIS. + * @param pSdadc the base address of the SDADC instance. + * @param u32Value Set Value. + */ +LOCAL_INLINE void SDADC_HWA_SetEXTIS(SDADC_Type *const pSdadc, uint32 u32Value) +{ + pSdadc->EXTIS = u32Value & SDADC_EXTIS_MASK; +} + + +/** + * @brief Set the value of DMA_EN. + * Channel Enable + * 0b - The channel dma is disabled. + * 0b - The channel dma is enabled. + * @param pSdadc the base address of the SDADC instance. + * @param u8Channel SDADC Channel. + * @param u8Enable SDADC Channel Channel Enable. + * @return uint32_t the value of DMA_EN. + */ +LOCAL_INLINE void SDADC_HWA_SetDMA_EN(const SDADC_Type *const pSdadc, uint8_t u8Channel, uint8_t u8Enable) +{ + SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR = (SDADC_CHANNELCFGREG(pSdadc)[u8Channel].CCR & ~SDADC_CCR_DMA_EN_MASK) | SDADC_CCR_DMA_EN(u8Enable); +} + + +/** @}*/ + +#endif /* #if SDADC_INSTANCE_COUNT > 0U */ + +#endif /* _HWA_SDADC_H_ */ diff --git a/Inc/HwA_sddf.h b/Inc/HwA_sddf.h new file mode 100644 index 0000000..303f6e7 --- /dev/null +++ b/Inc/HwA_sddf.h @@ -0,0 +1,2420 @@ +/** + * @file HwA_sddf.h + * @author Flagchip + * @brief Hardware access layer for SDDF + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip030 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_SDDF_H_ +#define _HWA_SDDF_H_ + +#include "device_header.h" + +#if SDDF_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_sddf HwA_sddf + * @ingroup module_driver_sddf + * @{ + */ + +/** + * @brief Select the SDDF function clock pre-divider ratio + * + */ +typedef enum +{ + SDDF_PREDIV_1 = 0U, /**< The clock is pre-diveded by 1 */ + SDDF_PREDIV_2 = 1U, /**< The clock is pre-diveded by 2 */ + SDDF_PREDIV_4 = 2U, /**< The clock is pre-diveded by 4 */ + SDDF_PREDIV_8 = 3U /**< The clock is pre-diveded by 8 */ +} SDDF_PreDivType; + +/** + * @brief Select the SDDF operation mode + * + */ +typedef enum +{ + SDDF_MODE_NORMAL = 0U, /**< SDDF is in normal mode */ + SDDF_MODE_DEBUG = 1U /**< SDDF is in debug mode */ +} SDDF_ModeType; + +/** + * @brief Select whether the SDDF module enables in debug mode + * + */ +typedef enum +{ + SDDF_MODULE_ENABLE_IN_DEBUG = 0U, /**< SDDF is enabled in debug mode */ + SDDF_MODULE_DISABLE_IN_DEBUG = 1U /**< SDDF is disabled in debug mode. Need trigger again for new conversion */ +} SDDF_DebugModuleEnableType; + +/** + * @brief Select the data source for limit check and zero cross check + * + */ +typedef enum +{ + SDDF_INPUT_SRC_MAIN_FILTER = 0U, /**< The input source is main filter */ + SDDF_INPUT_SRC_AUXILIARY_FILTER = 1U /**< The input source is auxiliary filter */ +} SDDF_InputSrcType; + +/** + * @brief Select the conversion mode for auxiliary filter + * + */ +typedef enum +{ + SDDF_AUX_FILTER_CONV_ALWAYS_ON = 0U, /**< Auxiliary filter is always on */ + SDDF_AUX_FILTER_CONV_FOLLOW_MAIN = 1U /**< Auxiliary filter operates following the main filter */ +} SDDF_AuxFilterConvModeType; + +/** + * @brief Selects the filter order for auxiliary filter + * + */ +typedef enum +{ + SDDF_AUX_FILTER_FIRST_ORDER = 1U, /**< The auxiliary filter is 1st order */ + SDDF_AUX_FILTER_SECOND_ORDER = 2U, /**< The auxiliary filter is 2nd order */ + SDDF_AUX_FILTER_THIRD_ORDER = 3U /**< The auxiliary filter is 3rd order */ +} SDDF_AuxFilterOrderType; + +/** + * @brief Selects the conversion mode for main filter + * + */ +typedef enum +{ + SDDF_MAIN_FILTER_CONV_SINGLE = 0U, /**< Single mode. One conversion following a triggering event */ + SDDF_MAIN_FILTER_CONV_CONTINUOUS = 1U, /**< Continuouts conversion mode. Multiple conversions following a triggering + event, and the next trigger will cancel and restart conversion */ + SDDF_MAIN_FILTER_CONV_ALWAYS = 2U /**< Always conversion mode. Multiple conversions following the first trigger, + and the next trigger will be ignored */ +} SDDF_MainFilterConvModeType; + +/** + * @brief Selects the filter order for main filter + * + */ +typedef enum +{ + SDDF_MAIN_FILTER_FIRST_ORDER = 1U, /**< The main filter is 1st order */ + SDDF_MAIN_FILTER_SECOND_ORDER = 2U, /**< The main filter is 2nd order */ + SDDF_MAIN_FILTER_THIRD_ORDER = 3U, /**< The main filter is 3rd order */ + SDDF_MAIN_FILTER_FOURTH_ORDER = 4U, /**< The main filter is 4th order */ + SDDF_MAIN_FILTER_FIFTH_ORDER = 5U /**< The main filter is 5th order */ +} SDDF_MainFilterOrderType; + +/** + * @brief Select the trigger level type + * + */ +typedef enum +{ + SDDF_TRIGGER_EVENT_EDGE = 0U, /**< Trigger is edge event. Next edge event will cancel the current conversion, + and re-start in single or continuous mode */ + SDDF_TRIGGER_EVENT_LEVEL = 1U /**< Trigger is level event. De-assert cancels the current conversion, and stop + filter function in single or continuous mode */ +} SDDF_TriggerEventType; + +/** + * @brief Select the trigger source + * + */ +typedef enum +{ + SDDF_TRIGGER_SRC_SOFTWARE = 0U, /**< Software trigger is selected */ + SDDF_TRIGGER_SRC_HARDWARE = 1U /**< Hardware trigger is selected */ +} SDDF_TriggerSrcType; + +/** + * @brief Select the input clock edge + * + */ +typedef enum +{ + SDDF_CLOCK_EDGE_RISING = 1U, /**< Use the input clock rising edge */ + SDDF_CLOCK_EDGE_FALLING = 2U, /**< Use the input clock falling edge */ + SDDF_CLOCK_EDGE_BOTH = 3U /**< Use both edges of the input clock */ +} SDDF_ClockEdgeType; + +/** + * @brief Select the input clock source + * + */ +typedef enum +{ + SDDF_CLOCK_SRC_EXTERNAL_MODULATOR_CLOCK = 3U /**< The input clock is from the external modulator clock dedicated to + this channel */ +} SDDF_ClockSrcType; + +/** + * @brief Select the input bit format + * + */ +typedef enum +{ + SDDF_BIT_FORMAT_EXTERNAL_ONE_BIT_STREAM = 0U, /**< External one bit stream */ + SDDF_BIT_FORMAT_EXTERNAL_MANCHSTER_CODE = 1U /**< External Manchester code, SDDF_ClockEdgeType will determine rise + or fall decoder */ +} SDDF_BitFormatType; + +/** + * @brief Select the result data format + * + */ +typedef enum +{ + SDDF_RESULT_DATA_LEFT_ALIGNED_SIGNED = 0U, /**< The result is left justfied, signed, for the case where input + bitstram is signed */ + SDDF_RESULT_DATA_LEFT_ALIGNED_UNSIGNED = 1U /**< The result is left justfied, unsigned, for the case where input + bitstram is unsigned */ +} SDDF_ResultFormatType; + +/** + * @brief Set the main filter shift to get correct 24 bit precision + * @details Main Filter CIC raw result is always 32bit width. The user should program MFSHIFT for cut-off and shift + * left/right to get 24bit result. + * + */ +typedef enum +{ + SDDF_MAIN_FILTER_NOT_SHIFT = 0U, /**< Main filter no shift needed */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_1 = 1U, /**< Main filter shift right by 1 bit */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_2 = 2U, /**< Main filter shift right by 2 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_3 = 3U, /**< Main filter shift right by 3 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_4 = 4U, /**< Main filter shift right by 4 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_5 = 5U, /**< Main filter shift right by 5 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_6 = 6U, /**< Main filter shift right by 6 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_7 = 7U, /**< Main filter shift right by 7 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_8 = 8U, /**< Main filter shift right by 8 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_9 = 9U, /**< Main filter shift right by 9 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_10 = 10U, /**< Main filter shift right by 10 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_11 = 11U, /**< Main filter shift right by 11 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_12 = 12U, /**< Main filter shift right by 12 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_13 = 13U, /**< Main filter shift right by 13 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_14 = 14U, /**< Main filter shift right by 14 bits */ + SDDF_MAIN_FILTER_SHIFT_RIGHT_15 = 15U, /**< Main filter shift right by 15 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_1 = 17U, /**< Main filter shift left by 1 bit */ + SDDF_MAIN_FILTER_SHIFT_LEFT_2 = 18U, /**< Main filter shift left by 2 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_3 = 19U, /**< Main filter shift left by 3 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_4 = 20U, /**< Main filter shift left by 4 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_5 = 21U, /**< Main filter shift left by 5 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_6 = 22U, /**< Main filter shift left by 6 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_7 = 23U, /**< Main filter shift left by 7 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_8 = 24U, /**< Main filter shift left by 8 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_9 = 25U, /**< Main filter shift left by 9 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_10 = 26U, /**< Main filter shift left by 10 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_11 = 27U, /**< Main filter shift left by 11 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_12 = 28U, /**< Main filter shift left by 12 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_13 = 29U, /**< Main filter shift left by 13 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_14 = 30U, /**< Main filter shift left by 14 bits */ + SDDF_MAIN_FILTER_SHIFT_LEFT_15 = 31U /**< Main filter shift left by 15 bits */ +} SDDF_MainFilterShiftType; + +/** + * @brief Select the limit detection option + * + */ +typedef enum +{ + SDDF_CHANNEL_LIMIT_BOTH_HITH_LOW_THRES = 0U, /**< Limitation detect on exceed both high and low value */ + SDDF_CHANNEL_LIMIT_HITH_THRES = 1U, /**< Limitation detect on exceed high threshold value */ + SDDF_CHANNEL_LIMIT_LOW_THRES = 2U, /**< Limitation detect on exceed low threshold value */ + SDDF_CHANNEL_LIMIT_WINDOW = 3U /**< Limitation detect on windowed value */ +} SDDF_ChannelLimitOptionType; + +/** + * @brief Select the short circuit detection option + * + */ +typedef enum +{ + SDDF_SHORT_CIRCUIT_COUNT_ON_BOTH = 0U, /**< Short circuit count on both 0 and 1, detect both high and low value*/ + SDDF_SHORT_CIRCUIT_COUNT_ON_1 = 1U, /**< Short circuit count on 1, detect high value */ + SDDF_SHORT_CIRCUIT_COUNT_ON_0 = 2U /**< Short circuit count on 0, detect low value */ +} SDDF_ShortCircuitOptionType; + +/** + * @brief Select sht short circuit detect conversion mode + * + */ +typedef enum +{ + SDDF_SHORT_DETECT_ALWAYS_ON = 0U, /**< Short circuit detect is always on when CHEN and MEN are asserted */ + SDDF_SHORT_DETECT_AUX_FILTER_EN = 1U /**< Short circuit detect only works when the Auxiliary Filter is enabled */ +} SDDF_ShortCircuitDetectModeType; + +/** + * @brief Get the global control register (SDDF_CTRL) value + * + * @param pSddf the base address of the SDDF instance + * @return uint32_t the SDDF_CTRL register value + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetCtrl(const SDDF_Type *const pSddf) +{ + return pSddf->CTRL; +} + +/** + * @brief Set the global control register (SDDF_CTRL) value + * + * @param pSddf the base address of the SDDF instance + * @param u32Ctrl the SDDF_CTRL register value to set + */ +LOCAL_INLINE void SDDF_HWA_SetCtrl(SDDF_Type *const pSddf, uint32_t u32Ctrl) +{ + pSddf->CTRL = u32Ctrl; +} + +/** + * @brief Get whether SDDF clock output 2 is disabled + * + * @param pSddf the base address of the SDDF instance + * @return true SDDF clock output 2 is diabled + * @return false SDDF clock output 2 is enabled + */ +LOCAL_INLINE bool SDDF_HWA_GetClockOut2DisableFlag(const SDDF_Type *const pSddf) +{ + uint32_t u32TmpVal = (pSddf->CTRL & SDDF_CTRL_CLKO2_DIS_MASK) >> SDDF_CTRL_CLKO2_DIS_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to disable clock output 2 + * + * @param pSddf the base address of the SDDF instance + * @param bDisable whether to disable clock output 2 + */ +LOCAL_INLINE void SDDF_HWA_SetClockOut2DisableFlag(SDDF_Type *const pSddf, bool bDisable) +{ + pSddf->CTRL = (pSddf->CTRL & ~SDDF_CTRL_CLKO2_DIS_MASK) | SDDF_CTRL_CLKO2_DIS(bDisable); +} + +/** + * @brief Get whether SDDF clock output 1 is disabled + * + * @param pSddf the base address of the SDDF instance + * @return true SDDF clock output 1 is diabled + * @return false SDDF clock output 1 is enabled + */ +LOCAL_INLINE bool SDDF_HWA_GetClockOut1DisableFlag(const SDDF_Type *const pSddf) +{ + uint32_t u32TmpVal = (pSddf->CTRL & SDDF_CTRL_CLKO1_DIS_MASK) >> SDDF_CTRL_CLKO1_DIS_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to disable clock output 1 + * + * @param pSddf the base address of the SDDF instance + * @param bDisable whether to disable clock output 1 + */ +LOCAL_INLINE void SDDF_HWA_SetClockOut1DisableFlag(SDDF_Type *const pSddf, bool bDisable) +{ + pSddf->CTRL = (pSddf->CTRL & ~SDDF_CTRL_CLKO1_DIS_MASK) | SDDF_CTRL_CLKO1_DIS(bDisable); +} + +/** + * @brief Get whether SDDF clock output 0 is disabled + * + * @param pSddf the base address of the SDDF instance + * @return true SDDF clock output 0 is diabled + * @return false SDDF clock output 0 is enabled + */ +LOCAL_INLINE bool SDDF_HWA_GetClockOut0DisableFlag(const SDDF_Type *const pSddf) +{ + uint32_t u32TmpVal = (pSddf->CTRL & SDDF_CTRL_CLKO0_DIS_MASK) >> SDDF_CTRL_CLKO0_DIS_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to disable clock output 0 + * + * @param pSddf the base address of the SDDF instance + * @param bDisable whether to disable clock output 0 + */ +LOCAL_INLINE void SDDF_HWA_SetClockOut0DisableFlag(SDDF_Type *const pSddf, bool bDisable) +{ + pSddf->CTRL = (pSddf->CTRL & ~SDDF_CTRL_CLKO0_DIS_MASK) | SDDF_CTRL_CLKO0_DIS(bDisable); +} + +/** + * @brief Get the function clock pre-divider value + * + * @param pSddf the base address of the SDDF instance + * @return SDDF_PreDivType the function clock pre-divider value + */ +LOCAL_INLINE SDDF_PreDivType SDDF_HWA_GetPreDivider(const SDDF_Type *const pSddf) +{ + uint32_t u32TmpVal = (pSddf->CTRL & SDDF_CTRL_PRESCALE_MASK) >> SDDF_CTRL_PRESCALE_SHIFT; + return (SDDF_PreDivType)u32TmpVal; +} + +/** + * @brief Set the function clock pre-divider value + * + * @param pSddf the base address of the SDDF instance + * @param eDiv the function clock pre-divider value + */ +LOCAL_INLINE void SDDF_HWA_SetPreDivider(SDDF_Type *const pSddf, SDDF_PreDivType eDiv) +{ + pSddf->CTRL = (pSddf->CTRL & ~SDDF_CTRL_PRESCALE_MASK) | SDDF_CTRL_PRESCALE(eDiv); +} + +/** + * @brief Get the clock divider value + * + * @param pSddf the base address of the SDDF instance + * @return uint32_t the clock out divider value + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetDivider(const SDDF_Type *const pSddf) +{ + uint32_t u32TmpVal = (pSddf->CTRL & SDDF_CTRL_MCLK_DIV_MASK) >> SDDF_CTRL_MCLK_DIV_SHIFT; + return (u32TmpVal + 1U); +} + +/** + * @brief Set the clock divider value + * + * @param pSddf the base address of the SDDF instance + * @param u32Div the clock out divider value + */ +LOCAL_INLINE void SDDF_HWA_SetDivider(SDDF_Type *const pSddf, uint32_t u32Div) +{ + DEV_ASSERT((u32Div >= 2U) && (u32Div <= 128U)); + pSddf->CTRL = (pSddf->CTRL & ~SDDF_CTRL_MCLK_DIV_MASK) | SDDF_CTRL_MCLK_DIV(u32Div - 1U); +} + +/** + * @brief Get whether the SDDF function blocks are enabled + * + * @param pSddf the base address of the SDDF instance + * @return true the fuction blocks are enabled + * @return false all function blocks are disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetMainEnableFlag(const SDDF_Type *const pSddf) +{ + uint32_t u32TmpVal = (pSddf->CTRL & SDDF_CTRL_MEN_MASK) >> SDDF_CTRL_MEN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Enable the SDDF function blocks + * + * @param pSddf the base address of the SDDF instance + */ +LOCAL_INLINE void SDDF_HWA_MainEnable(SDDF_Type *const pSddf) +{ + pSddf->CTRL |= SDDF_CTRL_MEN_MASK; +} + +/** + * @brief Disable all SDDF function blocks + * + * @param pSddf the base address of the SDDF instance + */ +LOCAL_INLINE void SDDF_HWA_MainDisable(SDDF_Type *const pSddf) +{ + pSddf->CTRL &= ~SDDF_CTRL_MEN_MASK; +} + +/** + * @brief Reset all SDDF function blocks and clock configuration bits + * + * @param pSddf the base address of the SDDF instance + */ +LOCAL_INLINE void SDDF_HWA_Reset(SDDF_Type *const pSddf) +{ + pSddf->CTRL |= SDDF_CTRL_RESET_MASK; + pSddf->CTRL &= ~SDDF_CTRL_RESET_MASK; +} + +/** + * @brief Get the SDDF operation mode (normal mode or debug mode) + * + * @param pSddf the base address of the SDDF instance + * @return SDDF_ModeType the operation mode of SDDF + */ +LOCAL_INLINE SDDF_ModeType SDDF_HWA_GetOperationMode(const SDDF_Type *const pSddf) +{ + uint32_t u32TmpVal = (pSddf->CTRL & SDDF_CTRL_DBG_MODE_MASK) >> SDDF_CTRL_DBG_MODE_SHIFT; + return (SDDF_ModeType)u32TmpVal; +} + +/** + * @brief Set the SDDF operation mode + * + * @param pSddf the base address of the SDDF instanc + * @param eMode the operation mode of SDDF + */ +LOCAL_INLINE void SDDF_HWA_SetOperationMode(SDDF_Type *const pSddf, SDDF_ModeType eMode) +{ + DEV_ASSERT((SDDF_HWA_GetMainEnableFlag(pSddf) == false)); + pSddf->CTRL = (pSddf->CTRL & ~SDDF_CTRL_DBG_MODE_MASK) | SDDF_CTRL_DBG_MODE(eMode); +} + +/** + * @brief Get whether SDDF module is enabled in debug mode + * + * @param pSddf the base address of the SDDF instanc + * @return SDDF_DebugModuleEnableType whether SDDF module is enabled in debug mode + */ +LOCAL_INLINE SDDF_DebugModuleEnableType SDDF_HWA_GetModuleDebugEnableFlag(const SDDF_Type *const pSddf) +{ + uint32_t u32TmpVal = (pSddf->CTRL & SDDF_CTRL_DBG_EN_MASK) >> SDDF_CTRL_DBG_EN_SHIFT; + return (SDDF_DebugModuleEnableType)u32TmpVal; +} + +/** + * @brief Set whether SDDF module is enabled in debug mode + * + * @param pSddf the base address of the SDDF instanc + * @param eEnable whether SDDF module is enabled in debug mode + */ +LOCAL_INLINE void SDDF_HWA_SetModuleDebugEnableFlag(SDDF_Type *const pSddf, SDDF_DebugModuleEnableType eEnable) +{ + pSddf->CTRL = (pSddf->CTRL & ~SDDF_CTRL_DBG_EN_MASK) | SDDF_CTRL_DBG_EN(eEnable); +} + +/** + * @brief Generate software trigger signal for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel to generate software trigger signal + */ +LOCAL_INLINE void SDDF_HWA_GenerateChannelSwTrigger(SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + pSddf->CTRL |= SDDF_CTRL_SWTRIG0_MASK << u8ChanIdx; +} + +/** + * @brief Get the normal interrupt (SDDF_NIER) register value + * + * @param pSddf the base address of the SDDF instance + * @return uint32_t the SDDF_NIER register value + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetNormalInterruptEnable(const SDDF_Type *const pSddf) +{ + return pSddf->NIER; +} + +/** + * @brief Set the normal interrupt (SDDF_NIER) register value + * + * @param pSddf the base address of the SDDF instance + * @param u32IntEn the SDDF_NIER register value to set + */ +LOCAL_INLINE void SDDF_HWA_SetNormalInterruptEnable(SDDF_Type *const pSddf, uint32_t u32IntEn) +{ + pSddf->NIER = u32IntEn; +} + +/** + * @brief Get whether zero cross detect interrupt is enabled + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @return true zero cross detect interrupt is enabled + * @return false zero cross detect interrupt is disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelZeroCrossDetectIntEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->NIER & (SDDF_NIER_ZCDIE0_MASK << u8ChanIdx)) >> (SDDF_NIER_ZCDIE0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable zero cross detect interrupt + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @param bEnable whether to enable zero cross detect interrupt + */ +LOCAL_INLINE void SDDF_HWA_SetChannelZeroCrossDetectIntEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + bool bEnable) +{ + pSddf->NIER = (pSddf->NIER & ~(SDDF_NIER_ZCDIE0_MASK << u8ChanIdx)) | (SDDF_NIER_ZCDIE0(bEnable) << u8ChanIdx); +} + +/** + * @brief Get whether channel FIFO data ready interrupt is enabled + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @return true channel FIFO data ready interrupt is enabled + * @return false channel FIFO data ready interrupt is disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelFIFODataReadyIntEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->NIER & (SDDF_NIER_FRDYIE0_MASK << u8ChanIdx)) >> (SDDF_NIER_FRDYIE0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable channel FIFO data ready interrupt + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @param bEnable whether to enable channel FIFO data ready interrupt + */ +LOCAL_INLINE void SDDF_HWA_SetChannelFIFODataReadyIntEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->NIER = (pSddf->NIER & ~(SDDF_NIER_FRDYIE0_MASK << u8ChanIdx)) | (SDDF_NIER_FRDYIE0(bEnable) << u8ChanIdx); +} + +/** + * @brief Get whether channel conversion complete interrupt is enabled + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @return true channel conversion complete interrupt is enabled + * @return false channel conversion complete interrupt is disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelConvCompleteIntEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->NIER & (SDDF_NIER_COCIE0_MASK << u8ChanIdx)) >> (SDDF_NIER_COCIE0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable channel conversion complete interrupt + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @param bEnable whether to enable channel conversion complete interrupt + */ +LOCAL_INLINE void SDDF_HWA_SetChannelConvCompleteIntEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->NIER = (pSddf->NIER & ~(SDDF_NIER_COCIE0_MASK << u8ChanIdx)) | (SDDF_NIER_COCIE0(bEnable) << u8ChanIdx); +} + +/** + * @brief Get the channel abnornal interrupt 0 (SDDF_ABNIER0) register value + * + * @param pSddf the base address of the SDDF instance + * @return uint32_t the SDDF_ABNIER0 register value + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetAbnormalInterruptEnable0(const SDDF_Type *const pSddf) +{ + return pSddf->ABNIER0; +} + +/** + * @brief Set the channel abnornal interrupt 0 (SDDF_ABNIER0) register value + * + * @param pSddf the base address of the SDDF instance + * @param u32IntEn the SDDF_ABNIER0 register value to set + */ +LOCAL_INLINE void SDDF_HWA_SetAbnormalInterruptEnable0(SDDF_Type *const pSddf, uint32_t u32IntEn) +{ + pSddf->ABNIER0 = u32IntEn; +} + +/** + * @brief Get whether channel high limit detect interrupt is enabled + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @return true the channel high limit detect interrupt is enabled + * @return false the channel high limit detect interrupt is disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelHighLimitIntEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNIER0 & (SDDF_ABNIER0_HLMTIE0_MASK << u8ChanIdx)) >> + (SDDF_ABNIER0_HLMTIE0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable channel high limit detect interrupt + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @param bEnable whether to enable channel high limit detect interrupt + */ +LOCAL_INLINE void SDDF_HWA_SetChannelHighLimitIntEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->ABNIER0 = (pSddf->ABNIER0 & ~(SDDF_ABNIER0_HLMTIE0_MASK << u8ChanIdx)) | (SDDF_ABNIER0_HLMTIE0( + bEnable) << u8ChanIdx); +} + +/** + * @brief Get whether channel low limit detect interrupt is enabled + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @return true the channel low limit detect interrupt is enabled + * @return false the channel low limit detect interrupt is disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelLowLimitIntEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNIER0 & (SDDF_ABNIER0_LLMTIE0_MASK << u8ChanIdx)) >> + (SDDF_ABNIER0_LLMTIE0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable channel low limit detect interrupt + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @param bEnable whether to enable channel low limit detect interrupt + */ +LOCAL_INLINE void SDDF_HWA_SetChannelLowLimitIntEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->ABNIER0 = (pSddf->ABNIER0 & ~(SDDF_ABNIER0_LLMTIE0_MASK << u8ChanIdx)) | (SDDF_ABNIER0_LLMTIE0( + bEnable) << u8ChanIdx); +} + +/** + * @brief Get whether channel window limit detect interrupt is enabled + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @return true the channel window limit detect interrupt is enabled + * @return false the channel window limit detect interrupt is disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelWindowLimitIntEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNIER0 & (SDDF_ABNIER0_WLMTIE0_MASK << u8ChanIdx)) >> + (SDDF_ABNIER0_WLMTIE0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable channel window limit detect interrupt + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @param bEnable whether to enable channel window limit detect interrupt + */ +LOCAL_INLINE void SDDF_HWA_SetChannelWindowLimitIntEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->ABNIER0 = (pSddf->ABNIER0 & ~(SDDF_ABNIER0_WLMTIE0_MASK << u8ChanIdx)) | (SDDF_ABNIER0_WLMTIE0( + bEnable) << u8ChanIdx); +} + +/** + * @brief Get whether channel short circuit detect interrupt is enabled + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @return true the channel short circuit detect interrupt is enabled + * @return false the channel short circuit detect interrupt is disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelShortCircuitDetectIntEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNIER0 & (SDDF_ABNIER0_SCDIE0_MASK << u8ChanIdx)) >> (SDDF_ABNIER0_SCDIE0_SHIFT + + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable channel short circuit detect interrupt + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @param bEnable whether to enable channel short circuit detect interrupt + */ +LOCAL_INLINE void SDDF_HWA_SetChannelShortCircuitDetectIntEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + bool bEnable) +{ + pSddf->ABNIER0 = (pSddf->ABNIER0 & ~(SDDF_ABNIER0_SCDIE0_MASK << u8ChanIdx)) | (SDDF_ABNIER0_SCDIE0( + bEnable) << u8ChanIdx); +} + +/** + * @brief Get the channel abnornal interrupt 1 (SDDF_ABNIER1) register value + * + * @param pSddf the base address of the SDDF instance + * @return uint32_t the SDDF_ABNIER1 register value + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetAbnormalInterruptEnable1(const SDDF_Type *const pSddf) +{ + return pSddf->ABNIER1; +} + +/** + * @brief Set the channel abnornal interrupt 1 (SDDF_ABNIER1) register value + * + * @param pSddf the base address of the SDDF instance + * @param u32IntEn the SDDF_ABNIER1 register value to set + */ +LOCAL_INLINE void SDDF_HWA_SetAbnormalInterruptEnable1(SDDF_Type *const pSddf, uint32_t u32IntEn) +{ + pSddf->ABNIER1 = u32IntEn; +} + +/** + * @brief Get whether channel result saturation interrupt is enabled + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @return true the channel result saturation interrupt is enabled + * @return false the channel result saturation interrupt is disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelSaturationIntEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNIER1 & (SDDF_ABNIER1_SATIE0_MASK << u8ChanIdx)) >> (SDDF_ABNIER1_SATIE0_SHIFT + + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable channel result saturation interrupt + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @param bEnable whether to enable channel result saturation interrupt + */ +LOCAL_INLINE void SDDF_HWA_SetChannelSaturationIntEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->ABNIER1 = (pSddf->ABNIER1 & ~(SDDF_ABNIER1_SATIE0_MASK << u8ChanIdx)) | (SDDF_ABNIER1_SATIE0( + bEnable) << u8ChanIdx); +} + +/** + * @brief Get whether channel clock absence detect interrupt is enabled + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @return true the channel clock absence detect interrupt is enabled + * @return false the channel clock absence detect interrupt is disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelClockAbsenceIntEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNIER1 & (SDDF_ABNIER1_CADIE0_MASK << u8ChanIdx)) >> (SDDF_ABNIER1_CADIE0_SHIFT + + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable channel clock absence detect interrupt + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @param bEnable whether to enable channel clock absence detect interrupt + */ +LOCAL_INLINE void SDDF_HWA_SetChannelClockAbsenceIntEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->ABNIER1 = (pSddf->ABNIER1 & ~(SDDF_ABNIER1_CADIE0_MASK << u8ChanIdx)) | (SDDF_ABNIER1_CADIE0( + bEnable) << u8ChanIdx); +} + +/** + * @brief Get whether channel FIFO overflow interrupt is enabled + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @return true the channel FIFO overflow interrupt is enabled + * @return false the channel FIFO overflow interrupt is disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelFIFOOverflowIntEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNIER1 & (SDDF_ABNIER1_FOVFIE0_MASK << u8ChanIdx)) >> + (SDDF_ABNIER1_FOVFIE0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable channel FIFO overflow interrupt + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @param bEnable whether to enable channel FIFO overflow interrupt + */ +LOCAL_INLINE void SDDF_HWA_SetChannelFIFOOverflowIntEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->ABNIER1 = (pSddf->ABNIER1 & ~(SDDF_ABNIER1_FOVFIE0_MASK << u8ChanIdx)) | (SDDF_ABNIER1_FOVFIE0( + bEnable) << u8ChanIdx); +} + +/** + * @brief Get whether channel FIFO underflow interrupt is enabled + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @return true the channel FIFO underflow interrupt is enabled + * @return false the channel FIFO underflow interrupt is disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelFIFOUnderflowIntEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNIER1 & (SDDF_ABNIER1_FUNFIE0_MASK << u8ChanIdx)) >> + (SDDF_ABNIER1_FUNFIE0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable channel FIFO underflow interrupt + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the channel index + * @param bEnable whether to enable channel FIFO underflow interrupt + */ +LOCAL_INLINE void SDDF_HWA_SetChannelFIFOUnderflowIntEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->ABNIER1 = (pSddf->ABNIER1 & ~(SDDF_ABNIER1_FUNFIE0_MASK << u8ChanIdx)) | (SDDF_ABNIER1_FUNFIE0( + bEnable) << u8ChanIdx); +} + +/** + * @brief Get the normal interrupt status register (SDDF_NISR) value + * + * @param pSddf the base address of the SDDF instance + * @return uint32_t the normal interrupt status (SDDF_NISR) register value + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetNormalInterruptStatus(const SDDF_Type *const pSddf) +{ + return pSddf->NISR; +} + +/** + * @brief Clear the normal interrupt status register (SDDF_NISR) value + * + * @param pSddf the base address of the SDDF instance + */ +LOCAL_INLINE void SDDF_HWA_ClearNormalInterruptStatus(SDDF_Type *const pSddf) +{ + pSddf->NISR = SDDF_NIER_MASK; +} + +/** + * @brief Get zero cross detect status of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true zero cross is detected + * @return false zero cross is not detected + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelZeroCrossDetectStatus(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->NISR & (SDDF_NISR_ZCD0_MASK << u8ChanIdx)) >> (SDDF_NISR_ZCD0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Clear zero cross detect flag of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + */ +LOCAL_INLINE void SDDF_HWA_ClearChannelZeroCrossDetectStatus(SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + pSddf->NISR = SDDF_NISR_ZCD0_MASK << u8ChanIdx; +} + +/** + * @brief Get FIFO data ready status of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true FIFO data ready is detected + * @return false FIFO data ready is not detected + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelFIFODataReadyStatus(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->NISR & (SDDF_NISR_FRDY0_MASK << u8ChanIdx)) >> (SDDF_NISR_FRDY0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Clear FIFO data ready flag of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + */ +LOCAL_INLINE void SDDF_HWA_ClearChannelFIFODataReadyStatus(SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + pSddf->NISR = SDDF_NISR_FRDY0_MASK << u8ChanIdx; +} + +/** + * @brief Get channel conversion complete status of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true channel conversion complete is detected + * @return false channel conversion complete is not detected + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelConvCompleteStatus(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->NISR & (SDDF_NISR_COC0_MASK << u8ChanIdx)) >> (SDDF_NISR_COC0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Clear channel conversion complete flag of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + */ +LOCAL_INLINE void SDDF_HWA_ClearChannelConvCompleteStatus(SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + pSddf->NISR = SDDF_NISR_COC0_MASK << u8ChanIdx; +} + +/** + * @brief Get the abnormal interrupt status 0 register (SDDF_ABNISR0) value + * + * @param pSddf the base address of the SDDF instance + * @return uint32_t the value of SDDF_ABNISR0 register + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetAbnormalInterruptStatus0(const SDDF_Type *const pSddf) +{ + return pSddf->ABNISR0; +} + +/** + * @brief Clear the abnormal interrupt status 0 register (SDDF_ABNISR0) value + * + * @param pSddf the base address of the SDDF instance + */ +LOCAL_INLINE void SDDF_HWA_ClearAbnormalInterruptStatus0(SDDF_Type *const pSddf) +{ + pSddf->ABNISR0 = SDDF_ABNISR0_MASK; +} + +/** + * @brief Get out of high limit range status of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true out of high limit range is detected + * @return false out of high limit range is not detected + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelHighLimitStatus(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNISR0 & (SDDF_ABNISR0_HLMT0_MASK << u8ChanIdx)) >> (SDDF_ABNISR0_HLMT0_SHIFT + + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Clear out of high limit range flag of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + */ +LOCAL_INLINE void SDDF_HWA_ClearChannelHighLimitStatus(SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + pSddf->ABNISR0 = SDDF_ABNISR0_HLMT0_MASK << u8ChanIdx; +} + +/** + * @brief Get out of low limit range status of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true out of low limit range is detected + * @return false out of low limit range is not detected + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelLowLimitStatus(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNISR0 & (SDDF_ABNISR0_LLMT0_MASK << u8ChanIdx)) >> (SDDF_ABNISR0_LLMT0_SHIFT + + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Clear out of low limit range flag of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + */ +LOCAL_INLINE void SDDF_HWA_ClearChannelLowLimitStatus(SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + pSddf->ABNISR0 = SDDF_ABNISR0_LLMT0_MASK << u8ChanIdx; +} + +/** + * @brief Get out of window limit range status of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true out of window limit range is detected + * @return false out of window limit range is not detected + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelWindowLimitStatus(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNISR0 & (SDDF_ABNISR0_WLMT0_MASK << u8ChanIdx)) >> (SDDF_ABNISR0_WLMT0_SHIFT + + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Clear out of window limit range flag of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + */ +LOCAL_INLINE void SDDF_HWA_ClearChannelWindowLimitStatus(SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + pSddf->ABNISR0 = SDDF_ABNISR0_WLMT0_MASK << u8ChanIdx; +} + +/** + * @brief Get short circuit detect status of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true short circuit is detected + * @return false short circuit is not detected + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelShortCircuitDetectStatus(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNISR0 & (SDDF_ABNISR0_SCD0_MASK << u8ChanIdx)) >> (SDDF_ABNISR0_SCD0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Clear short circuit flag of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + */ +LOCAL_INLINE void SDDF_HWA_ClearChannelShortCircuitDetectStatus(SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + pSddf->ABNISR0 = SDDF_ABNISR0_SCD0_MASK << u8ChanIdx; +} + +/** + * @brief Get the abnormal interrupt status 1 register (SDDF_ABNISR1) value + * + * @param pSddf the base address of the SDDF instance + * @return uint32_t the value of SDDF_ABNISR1 register + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetAbnormalInterruptStatus1(const SDDF_Type *const pSddf) +{ + return pSddf->ABNISR1; +} + +/** + * @brief Clear the abnormal interrupt status 0 register (SDDF_ABNISR0) value + * + * @param pSddf the base address of the SDDF instance + */ +LOCAL_INLINE void SDDF_HWA_ClearAbnormalInterruptStatus1(SDDF_Type *const pSddf) +{ + pSddf->ABNISR1 = SDDF_ABNISR1_MASK; +} + +/** + * @brief Get result saturation status of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true result saturation is detected + * @return false result saturation is not detected + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelSaturationStatus(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNISR1 & (SDDF_ABNISR1_SAT0_MASK << u8ChanIdx)) >> (SDDF_ABNISR1_SAT0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Clear result saturation flag of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + */ +LOCAL_INLINE void SDDF_HWA_ClearChannelSaturationStatus(SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + pSddf->ABNISR1 = SDDF_ABNISR1_SAT0_MASK << u8ChanIdx; +} + +/** + * @brief Get clock absence detect status of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true clock absence is detected + * @return false clock absence is not detected + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelClockAbsenceStatus(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNISR1 & (SDDF_ABNISR1_CAD0_MASK << u8ChanIdx)) >> (SDDF_ABNISR1_CAD0_SHIFT + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Clear clock absence flag of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + */ +LOCAL_INLINE void SDDF_HWA_ClearChannelClockAbsenceStatus(SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + pSddf->ABNISR1 = SDDF_ABNISR1_CAD0_MASK << u8ChanIdx; +} + +/** + * @brief Get FIFO overflow status of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true FIFO overflow is detected + * @return false FIFO overflow is not detected + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelFIFOOverflowStatus(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNISR1 & (SDDF_ABNISR1_FOVF0_MASK << u8ChanIdx)) >> (SDDF_ABNISR1_FOVF0_SHIFT + + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Clear FIFO overflow flag of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + */ +LOCAL_INLINE void SDDF_HWA_ClearChannelFIFOOverflowStatus(SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + pSddf->ABNISR1 = SDDF_ABNISR1_FOVF0_MASK << u8ChanIdx; +} + +/** + * @brief Get FIFO underflow status of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true FIFO underflow is detected + * @return false FIFO underflow is not detected + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelFIFOUnderflowStatus(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->ABNISR1 & (SDDF_ABNISR1_FUNF0_MASK << u8ChanIdx)) >> (SDDF_ABNISR1_FUNF0_SHIFT + + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Clear FIFO underflow flag of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + */ +LOCAL_INLINE void SDDF_HWA_ClearChannelFIFOUnderflowStatus(SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + pSddf->ABNISR1 = SDDF_ABNISR1_FUNF0_MASK << u8ChanIdx; +} + +/** + * @brief Get main status of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @return uint32_t the main status of the selected channel + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetMainStatus(const SDDF_Type *const pSddf) +{ + return pSddf->MSR; +} + +/** + * @brief Get whether the modulator clock 2 output is ready + * + * @param pSddf the base address of the SDDF instance + * @return true the modulator clock 2 output is ready + * @return false the modulator clock 2 output is not ready + */ +LOCAL_INLINE bool SDDF_HWA_GetClockOutput2ReadyFlag(const SDDF_Type *const pSddf) +{ + uint32_t u32TmpVal = (pSddf->MSR & SDDF_MSR_CLKO2_RDY_MASK) >> SDDF_MSR_CLKO2_RDY_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Get whether the modulator clock 1 output is ready + * + * @param pSddf the base address of the SDDF instance + * @return true the modulator clock 1 output is ready + * @return false the modulator clock 1 output is not ready + */ +LOCAL_INLINE bool SDDF_HWA_GetClockOutput1ReadyFlag(const SDDF_Type *const pSddf) +{ + uint32_t u32TmpVal = (pSddf->MSR & SDDF_MSR_CLKO1_RDY_MASK) >> SDDF_MSR_CLKO1_RDY_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Get whether the modulator clock 0 output is ready + * + * @param pSddf the base address of the SDDF instance + * @return true the modulator clock 0 output is ready + * @return false the modulator clock 0 output is not ready + */ +LOCAL_INLINE bool SDDF_HWA_GetClockOutput0ReadyFlag(const SDDF_Type *const pSddf) +{ + uint32_t u32TmpVal = (pSddf->MSR & SDDF_MSR_CLKO0_RDY_MASK) >> SDDF_MSR_CLKO0_RDY_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Get whether conversion of the selected channel is ongoing + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true the conversion is ongoing + * @return false the conversion is not ongoing + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelConvOngoingStatus(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->MSR & (SDDF_MSR_CHON0_MASK << u8ChanIdx)) >> (SDDF_MSR_CHON0_MASK + u8ChanIdx); + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Get channel control reigister (SDDF_CCRn) value of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return uint32_t the SDDF_CCRn register value + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetChannelControl(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + return pSddf->CH[u8ChanIdx].CCR; +} + +/** + * @brief Set channel control reigister (SDDF_CCRn) value of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param u32Ctrl the SDDF_CCRn register value to set + */ +LOCAL_INLINE void SDDF_HWA_SetChannelControl(SDDF_Type *const pSddf, uint8_t u8ChanIdx, uint32_t u32Ctrl) +{ + pSddf->CH[u8ChanIdx].CCR = u32Ctrl; +} + +/** + * @brief Get the result input source of channel limit check + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_InputSrcType the result input source of channel limit check + */ +LOCAL_INLINE SDDF_InputSrcType SDDF_HWA_GetChannelLimitCheckInputSrc(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CCR & SDDF_CCR_LMT_SEL_MASK) >> SDDF_CCR_LMT_SEL_SHIFT; + return (SDDF_InputSrcType)u32TmpVal; +} + +/** + * @brief Set the result input source of the channel limit check + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eSrc the result input source of channel limit check + */ +LOCAL_INLINE void SDDF_HWA_SetChannelLimitCheckInputSrc(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_InputSrcType eSrc) +{ + pSddf->CH[u8ChanIdx].CCR = (pSddf->CH[u8ChanIdx].CCR & ~SDDF_CCR_LMT_SEL_MASK) | SDDF_CCR_LMT_SEL(eSrc); +} + +/** + * @brief Get the result input source of channel zero cross check + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_InputSrcType the result input source of channel zero cross check + */ +LOCAL_INLINE SDDF_InputSrcType SDDF_HWA_GetChannelZeroCrossCheckInputSrc(const SDDF_Type *const pSddf, + uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CCR & SDDF_CCR_ZCD_SEL_MASK) >> SDDF_CCR_ZCD_SEL_SHIFT; + return (SDDF_InputSrcType)u32TmpVal; +} + +/** + * @brief Set the result input source of the channel zero cross check + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eSrc the result input source of channel zero cross check + */ +LOCAL_INLINE void SDDF_HWA_SetChannelZeroCrossCheckInputSrc(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_InputSrcType eSrc) +{ + pSddf->CH[u8ChanIdx].CCR = (pSddf->CH[u8ChanIdx].CCR & ~SDDF_CCR_ZCD_SEL_MASK) | SDDF_CCR_ZCD_SEL(eSrc); +} + +/** + * @brief Get whether FIFO is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true FIFO is enabled for the selected channel + * @return false FIFO is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelFIFOEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CCR & SDDF_CCR_FIFO_EN_MASK) >> SDDF_CCR_FIFO_EN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable FIFO for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable FIFO for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelFIFOEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->CH[u8ChanIdx].CCR = (pSddf->CH[u8ChanIdx].CCR & ~SDDF_CCR_FIFO_EN_MASK) | SDDF_CCR_FIFO_EN(bEnable); +} + +/** + * @brief Get whether limit check is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true limit check is enabled for the selected channel + * @return false limit check is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelLimitCheckEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CCR & SDDF_CCR_LMT_EN_MASK) >> SDDF_CCR_LMT_EN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable limit check for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable limit check for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelLimitCheckEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->CH[u8ChanIdx].CCR = (pSddf->CH[u8ChanIdx].CCR & ~SDDF_CCR_LMT_EN_MASK) | SDDF_CCR_LMT_EN(bEnable); +} + +/** + * @brief Get whether zero cross detect is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true zero cross detect is enabled for the selected channel + * @return false zero cross detect is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelZeroCrossDetectEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CCR & SDDF_CCR_ZCD_EN_MASK) >> SDDF_CCR_ZCD_EN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable zero cross detect for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable zero cross detect for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelZeroCrossDetectEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->CH[u8ChanIdx].CCR = (pSddf->CH[u8ChanIdx].CCR & ~SDDF_CCR_ZCD_EN_MASK) | SDDF_CCR_ZCD_EN(bEnable); +} + +/** + * @brief Get whether clocl absence detect is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true clocl absence detect is enabled for the selected channel + * @return false clocl absence detect is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelClockAbsenceDetectEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CCR & SDDF_CCR_CAD_EN_MASK) >> SDDF_CCR_CAD_EN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable clocl absence detect for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable clocl absence detect for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelClockAbsenceDetectEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + bool bEnable) +{ + pSddf->CH[u8ChanIdx].CCR = (pSddf->CH[u8ChanIdx].CCR & ~SDDF_CCR_CAD_EN_MASK) | SDDF_CCR_CAD_EN(bEnable); +} + +/** + * @brief Get whether short circuit detect is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true short circuit detect is enabled for the selected channel + * @return false short circuit detect is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelShortCircuitDetectEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CCR & SDDF_CCR_SCD_EN_MASK) >> SDDF_CCR_SCD_EN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable short circuit detect for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable short circuit detect for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelShortCircuitDetectEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + bool bEnable) +{ + pSddf->CH[u8ChanIdx].CCR = (pSddf->CH[u8ChanIdx].CCR & ~SDDF_CCR_SCD_EN_MASK) | SDDF_CCR_SCD_EN(bEnable); +} + +/** + * @brief Get whether DMA is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true DMA is enabled for the selected channel + * @return false DMA is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelDMAEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CCR & SDDF_CCR_DMA_EN_MASK) >> SDDF_CCR_DMA_EN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable DMA for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable DMA for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelDMAEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->CH[u8ChanIdx].CCR = (pSddf->CH[u8ChanIdx].CCR & ~SDDF_CCR_DMA_EN_MASK) | SDDF_CCR_DMA_EN(bEnable); +} + +/** + * @brief Get whether auxiliary filter is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true auxiliary filter is enabled for the selected channel + * @return false auxiliary filter is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelAuxiliaryFilterEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CCR & SDDF_CCR_AF_EN_MASK) >> SDDF_CCR_AF_EN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable auxiliary filter for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable auxiliary filter for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelAuxiliaryFilterEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->CH[u8ChanIdx].CCR = (pSddf->CH[u8ChanIdx].CCR & ~SDDF_CCR_AF_EN_MASK) | SDDF_CCR_AF_EN(bEnable); +} + +/** + * @brief Get whether main filter is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true main filter is enabled for the selected channel + * @return false main filter is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelMainFilterEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CCR & SDDF_CCR_MF_EN_MASK) >> SDDF_CCR_MF_EN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable main filter for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable main filter for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelMainFilterEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->CH[u8ChanIdx].CCR = (pSddf->CH[u8ChanIdx].CCR & ~SDDF_CCR_MF_EN_MASK) | SDDF_CCR_MF_EN(bEnable); +} + +/** + * @brief Get whether the selected channel is enabled + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true the selected channel is enabled + * @return false the selected channel is disabled + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CCR & SDDF_CCR_CH_EN_MASK) >> SDDF_CCR_CH_EN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, bool bEnable) +{ + pSddf->CH[u8ChanIdx].CCR = (pSddf->CH[u8ChanIdx].CCR & ~SDDF_CCR_CH_EN_MASK) | SDDF_CCR_CH_EN(bEnable); +} + +/** + * @brief Get the data rate register (SDDF_CDRn) value of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return uint32_t the data rate register value of the selected channel + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetChannelDataRate(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + return pSddf->CH[u8ChanIdx].CDR; +} + +/** + * @brief Set the data rate register (SDDF_CDRn) value of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param u32DataRate the data rate register value to set of the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelDataRate(SDDF_Type *const pSddf, uint8_t u8ChanIdx, uint32_t u32DataRate) +{ + pSddf->CH[u8ChanIdx].CDR = u32DataRate; +} + +/** + * @brief Get the auxiliary filter conversion mode of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_AuxFilterConvModeType the auxiliary filter conversion mode + */ +LOCAL_INLINE SDDF_AuxFilterConvModeType SDDF_HWA_GetChannelAuxiliaryFilterConvMode(const SDDF_Type *const pSddf, + uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CDR & SDDF_CDR_AFCM_MASK) >> SDDF_CDR_AFCM_SHIFT; + return (SDDF_AuxFilterConvModeType)u32TmpVal; +} + +/** + * @brief Set the auxiliary filter conversion mode of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eConvMode the auxiliary filter conversion mode + */ +LOCAL_INLINE void SDDF_HWA_SetChannelAuxiliaryFilterConvMode(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_AuxFilterConvModeType eConvMode) +{ + pSddf->CH[u8ChanIdx].CDR = (pSddf->CH[u8ChanIdx].CDR & ~SDDF_CDR_AFCM_MASK) | SDDF_CDR_AFCM(eConvMode); +} + +/** + * @brief Get the auxiliary filter order of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_AuxFilterOrderType the auxiliary filter order + */ +LOCAL_INLINE SDDF_AuxFilterOrderType SDDF_HWA_GetChannelAuxiliaryFilterOrder(const SDDF_Type *const pSddf, + uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CDR & SDDF_CDR_AFORD_MASK) >> SDDF_CDR_AFORD_SHIFT; + return (SDDF_AuxFilterOrderType)u32TmpVal; +} + +/** + * @brief Set the auxiliary filter order of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eOrder the auxiliary filter order + */ +LOCAL_INLINE void SDDF_HWA_SetChannelAuxiliaryFilterOrder(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_AuxFilterOrderType eOrder) +{ + pSddf->CH[u8ChanIdx].CDR = (pSddf->CH[u8ChanIdx].CDR & ~SDDF_CDR_AFORD_MASK) | SDDF_CDR_AFORD(eOrder); +} + +/** + * @brief Get the auxiliary filter oversampling rate of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return uint32_t the auxiliary filter oversampling rate + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetChannelAuxiliaryFilterOversampleRate(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CDR & SDDF_CDR_AFOSR_MASK) >> SDDF_CDR_AFOSR_SHIFT; + return (u32TmpVal + 1U); +} + +/** + * @brief Set the auxiliary filter oversampling rate of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param u32SampleRate the auxiliary filter oversampling rate + */ +LOCAL_INLINE void SDDF_HWA_SetChannelAuxiliaryFilterOversampleRate(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + uint32_t u32SampleRate) +{ + DEV_ASSERT(u32SampleRate >= 4U); +#ifndef NDEBUG + if (SDDF_HWA_GetChannelAuxiliaryFilterOrder(pSddf, u8ChanIdx) == SDDF_AUX_FILTER_THIRD_ORDER) + { + DEV_ASSERT(u32SampleRate <= 203U); + } + else + { + DEV_ASSERT(u32SampleRate <= 512U); + } +#endif + pSddf->CH[u8ChanIdx].CDR = (pSddf->CH[u8ChanIdx].CDR & ~SDDF_CDR_AFOSR_MASK) | SDDF_CDR_AFOSR(u32SampleRate - 1U); +} + +/** + * @brief Get the main filter conversion mode of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_AuxFilterConvModeType the main filter conversion mode + */ +LOCAL_INLINE SDDF_MainFilterConvModeType SDDF_HWA_GetChannelMainFilterConvMode(const SDDF_Type *const pSddf, + uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CDR & SDDF_CDR_MFCM_MASK) >> SDDF_CDR_MFCM_SHIFT; + return (SDDF_MainFilterConvModeType)u32TmpVal; +} + +/** + * @brief Set the main filter conversion mode of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eConvMode the main filter conversion mode + */ +LOCAL_INLINE void SDDF_HWA_SetChannelMainFilterConvMode(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_MainFilterConvModeType eConvMode) +{ + pSddf->CH[u8ChanIdx].CDR = (pSddf->CH[u8ChanIdx].CDR & ~SDDF_CDR_MFCM_MASK) | SDDF_CDR_MFCM(eConvMode); +} + +/** + * @brief Get the main filter order of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_AuxFilterOrderType the main filter order + */ +LOCAL_INLINE SDDF_MainFilterOrderType SDDF_HWA_GetChannelMainFilterOrder(const SDDF_Type *const pSddf, + uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CDR & SDDF_CDR_MFORD_MASK) >> SDDF_CDR_MFORD_SHIFT; + return (SDDF_MainFilterOrderType)u32TmpVal; +} + +/** + * @brief Set the main filter order of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eOrder the main filter order + */ +LOCAL_INLINE void SDDF_HWA_SetChannelMainFilterOrder(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_MainFilterOrderType eOrder) +{ + pSddf->CH[u8ChanIdx].CDR = (pSddf->CH[u8ChanIdx].CDR & ~SDDF_CDR_MFORD_MASK) | SDDF_CDR_MFORD(eOrder); +} + +/** + * @brief Get the main filter oversampling rate of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return uint32_t the main filter oversampling rate + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetChannelMainFilterOversampleRate(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CDR & SDDF_CDR_MFOSR_MASK) >> SDDF_CDR_MFOSR_SHIFT; + return (u32TmpVal + 1U); +} + +/** + * @brief Set the main filter oversampling rate of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param u32SampleRate the main filter oversampling rate + */ +LOCAL_INLINE void SDDF_HWA_SetChannelMainFilterOversampleRate(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + uint32_t u32SampleRate) +{ + DEV_ASSERT(u32SampleRate >= 4U); +#ifndef NDEBUG + if (SDDF_HWA_GetChannelMainFilterOrder(pSddf, u8ChanIdx) == SDDF_MAIN_FILTER_FOURTH_ORDER) + { + DEV_ASSERT(u32SampleRate <= 204U); + } + else if (SDDF_HWA_GetChannelMainFilterOrder(pSddf, u8ChanIdx) == SDDF_MAIN_FILTER_FIFTH_ORDER) + { + DEV_ASSERT(u32SampleRate <= 73U); + } + else + { + DEV_ASSERT(u32SampleRate <= 512U); + } +#endif + pSddf->CH[u8ChanIdx].CDR = (pSddf->CH[u8ChanIdx].CDR & ~SDDF_CDR_AFOSR_MASK) | SDDF_CDR_AFOSR(u32SampleRate - 1U); +} + +/** + * @brief Get the configuration register (SDDF_CFRn) value of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return uint32_t the channel configuration register value + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetChannelConfig(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + return pSddf->CH[u8ChanIdx].CFR; +} + +/** + * @brief Set the configuration register (SDDF_CFRn) value of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param u32Config the channel configuration register value to set + */ +LOCAL_INLINE void SDDF_HWA_SetChannelConfig(SDDF_Type *const pSddf, uint8_t u8ChanIdx, uint32_t u32Config) +{ + pSddf->CH[u8ChanIdx].CFR = u32Config; +} + +/** + * @brief Get the trigger level type of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_TriggerEventType the trigger level type + */ +LOCAL_INLINE SDDF_TriggerEventType SDDF_HWA_GetChannelTriggerEvent(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CFR & SDDF_CFR_TRGLVL_MASK) >> SDDF_CFR_TRGLVL_SHIFT; + return (SDDF_TriggerEventType)u32TmpVal; +} + +/** + * @brief Set the trigger level type of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eEvent the trigger level type + */ +LOCAL_INLINE void SDDF_HWA_SetChannelTriggerEvent(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_TriggerEventType eEvent) +{ + pSddf->CH[u8ChanIdx].CFR = (pSddf->CH[u8ChanIdx].CFR & ~SDDF_CFR_TRGLVL_MASK) | SDDF_CFR_TRGLVL(eEvent); +} + +/** + * @brief Get the trigger source type of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_TriggerSrcType the trigger source type + */ +LOCAL_INLINE SDDF_TriggerSrcType SDDF_HWA_GetChannelTriggerSource(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CFR & SDDF_CFR_TRGSEL_MASK) >> SDDF_CFR_TRGSEL_SHIFT; + return (SDDF_TriggerSrcType)u32TmpVal; +} + +/** + * @brief Set the trigger source type of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eSrc the trigger source type + */ +LOCAL_INLINE void SDDF_HWA_SetChannelTriggerSource(SDDF_Type *const pSddf, uint8_t u8ChanIdx, SDDF_TriggerSrcType eSrc) +{ + pSddf->CH[u8ChanIdx].CFR = (pSddf->CH[u8ChanIdx].CFR & ~SDDF_CFR_TRGSEL_MASK) | SDDF_CFR_TRGSEL(eSrc); +} + +/** + * @brief Get the clock edge for conversion of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_ClockEdgeType the input clock edge + */ +LOCAL_INLINE SDDF_ClockEdgeType SDDF_HWA_GetChannelInputClockEdge(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CFR & SDDF_CFR_CLKEDG_MASK) >> SDDF_CFR_CLKEDG_SHIFT; + return (SDDF_ClockEdgeType)u32TmpVal; +} + +/** + * @brief Set the clock edge for conversion of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eClkEdge the input clock edge + */ +LOCAL_INLINE void SDDF_HWA_SetChannelInputClockEdge(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_ClockEdgeType eClkEdge) +{ + pSddf->CH[u8ChanIdx].CFR = (pSddf->CH[u8ChanIdx].CFR & ~SDDF_CFR_CLKEDG_MASK) | SDDF_CFR_CLKEDG(eClkEdge); +} + +/** + * @brief Get the input clock select of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_ClockSrcType the input clock select + */ +LOCAL_INLINE SDDF_ClockSrcType SDDF_HWA_GetChannelInputClockSource(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CFR & SDDF_CFR_CLKSEL_MASK) >> SDDF_CFR_CLKSEL_SHIFT; + return (SDDF_ClockSrcType)u32TmpVal; +} + +/** + * @brief Set the input clock select of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eSrc the input clock select + */ +LOCAL_INLINE void SDDF_HWA_SetChannelInputClockSource(SDDF_Type *const pSddf, uint8_t u8ChanIdx, SDDF_ClockSrcType eSrc) +{ + pSddf->CH[u8ChanIdx].CFR = (pSddf->CH[u8ChanIdx].CFR & ~SDDF_CFR_CLKSEL_MASK) | SDDF_CFR_CLKSEL(eSrc); +} + +/** + * @brief Get the input bit format of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_BitFormatType the input bit format + */ +LOCAL_INLINE SDDF_BitFormatType SDDF_HWA_GetChannelInputBitFormat(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CFR & SDDF_CFR_IBFMT_MASK) >> SDDF_CFR_IBFMT_SHIFT; + return (SDDF_BitFormatType)u32TmpVal; +} + +/** + * @brief Set the input bit format of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eFormat the input bit format + */ +LOCAL_INLINE void SDDF_HWA_SetChannelInputBitFormat(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_BitFormatType eFormat) +{ + pSddf->CH[u8ChanIdx].CFR = (pSddf->CH[u8ChanIdx].CFR & ~SDDF_CFR_IBFMT_MASK) | SDDF_CFR_IBFMT(eFormat); +} + +/** + * @brief Get the FIFO watermark of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return uint8_t the FIFO watermark of the selected channel + */ +LOCAL_INLINE uint8_t SDDF_HWA_GetChannelFIFOWatermark(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CFR & SDDF_CFR_FWMK_MASK) >> SDDF_CFR_FWMK_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the FIFO watermark of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param u8Watermark the FIFO watermark of the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelFIFOWatermark(SDDF_Type *const pSddf, uint8_t u8ChanIdx, uint8_t u8Watermark) +{ + pSddf->CH[u8ChanIdx].CFR = (pSddf->CH[u8ChanIdx].CFR & ~SDDF_CFR_FWMK_MASK) | SDDF_CFR_FWMK(u8Watermark); +} + +/** + * @brief Get the result data format of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_ResultFormatType the result data format of the selected channel + */ +LOCAL_INLINE SDDF_ResultFormatType SDDF_HWA_GetChannelResultDataFormat(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CFR & SDDF_CFR_RDFMT_MASK) >> SDDF_CFR_RDFMT_SHIFT; + return (SDDF_ResultFormatType)u32TmpVal; +} + +/** + * @brief Set the result data format of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eFormat the result data format of the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelResultDataFormat(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_ResultFormatType eFormat) +{ + pSddf->CH[u8ChanIdx].CFR = (pSddf->CH[u8ChanIdx].CFR & ~SDDF_CFR_RDFMT_MASK) | SDDF_CFR_RDFMT(eFormat); +} + +/** + * @brief Get the main filter shift of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_MainFilterShiftType the main filter shift of the selected channel + */ +LOCAL_INLINE SDDF_MainFilterShiftType SDDF_HWA_GetChannelMainFilterShift(const SDDF_Type *const pSddf, + uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CFR & SDDF_CFR_MFSHIFT_MASK) >> SDDF_CFR_MFSHIFT_SHIFT; + if (u32TmpVal == 16U) + { + u32TmpVal = 0U; + } + return (SDDF_MainFilterShiftType)u32TmpVal; +} + +/** + * @brief Set the main filter shift to get correct 24 bit precision of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eShift the main filter shift to set + */ +LOCAL_INLINE void SDDF_HWA_SetChannelMainFilterShift(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_MainFilterShiftType eShift) +{ + pSddf->CH[u8ChanIdx].CFR = (pSddf->CH[u8ChanIdx].CFR & ~SDDF_CFR_MFSHIFT_MASK) | SDDF_CFR_RDFMT(eShift); +} + +/** + * @brief Get the protection settings (SDDF_CPRn) value of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return uint32_t the protection settings (SDDF_CPRn) value + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetChannelProtectionConfig(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + return pSddf->CH[u8ChanIdx].CPR; +} + +/** + * @brief Set the protection settings (SDDF_CPRn) value of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param u32Config the protection settings (SDDF_CPRn) value + */ +LOCAL_INLINE void SDDF_HWA_SetChannelProtectionConfig(SDDF_Type *const pSddf, uint8_t u8ChanIdx, uint32_t u32Config) +{ + pSddf->CH[u8ChanIdx].CPR = u32Config; +} + +/** + * @brief Get whether the high limit break signal is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true the high limit break signal is enabled for the selected channel + * @return false the high limit break signal is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelHighLimitBreakSignalEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CPR & SDDF_CPR_HLMT_BKEN_MASK) >> SDDF_CPR_HLMT_BKEN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable high limit break signal for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable high limit break signal for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelHighLimitBreakSignalEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + bool bEnable) +{ + pSddf->CH[u8ChanIdx].CPR = (pSddf->CH[u8ChanIdx].CPR & ~SDDF_CPR_HLMT_BKEN_MASK) | SDDF_CPR_HLMT_BKEN(bEnable); +} + +/** + * @brief Get whether the window limit break signal is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true the window limit break signal is enabled for the selected channel + * @return false the window limit break signal is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelWindowLimitBreakSignalEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CPR & SDDF_CPR_WLMT_BKEN_MASK) >> SDDF_CPR_WLMT_BKEN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable window limit break signal for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable window limit break signal for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelWindowLimitBreakSignalEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + bool bEnable) +{ + pSddf->CH[u8ChanIdx].CPR = (pSddf->CH[u8ChanIdx].CPR & ~SDDF_CPR_WLMT_BKEN_MASK) | SDDF_CPR_WLMT_BKEN(bEnable); +} + +/** + * @brief Get whether the low limit break signal is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true the low limit break signal is enabled for the selected channel + * @return false the low limit break signal is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelLowLimitBreakSignalEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CPR & SDDF_CPR_LLMT_BKEN_MASK) >> SDDF_CPR_LLMT_BKEN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable low limit break signal for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable low limit break signal for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelLowLimitBreakSignalEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + bool bEnable) +{ + pSddf->CH[u8ChanIdx].CPR = (pSddf->CH[u8ChanIdx].CPR & ~SDDF_CPR_LLMT_BKEN_MASK) | SDDF_CPR_LLMT_BKEN(bEnable); +} + +/** + * @brief Get whether short circuit detect break signal is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true short circuit detect break signal is enabled for the selected channel + * @return false short circuit detect break signal is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelShortCircuitBreakSignalEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CPR & SDDF_CPR_SCD_BKEN_MASK) >> SDDF_CPR_SCD_BKEN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable short circuit detect break signal for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable short circuit detect break signal for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelShortCircuitBreakSignalEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + bool bEnable) +{ + pSddf->CH[u8ChanIdx].CPR = (pSddf->CH[u8ChanIdx].CPR & ~SDDF_CPR_SCD_BKEN_MASK) | SDDF_CPR_SCD_BKEN(bEnable); +} + +/** + * @brief Get whether clock absence detect break signal is enabled for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return true clock absence detect break signal is enabled for the selected channel + * @return false clock absence detect break signal is disabled for the selected channel + */ +LOCAL_INLINE bool SDDF_HWA_GetChannelClockAbsenceBreakSignalEnableFlag(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CPR & SDDF_CPR_CAD_BKEN_MASK) >> SDDF_CPR_CAD_BKEN_SHIFT; + return (u32TmpVal != 0U ? true : false); +} + +/** + * @brief Set whether to enable clock absence detect break signal for the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param bEnable whether to enable clock absence detect break signal for the selected channel + */ +LOCAL_INLINE void SDDF_HWA_SetChannelClockAbsenceBreakSignalEnableFlag(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + bool bEnable) +{ + pSddf->CH[u8ChanIdx].CPR = (pSddf->CH[u8ChanIdx].CPR & ~SDDF_CPR_CAD_BKEN_MASK) | SDDF_CPR_CAD_BKEN(bEnable); +} + +/** + * @brief Get the clock absence detector limitation threshold + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return uint8_t the clock absence detector limitation threshold + */ +LOCAL_INLINE uint8_t SDDF_HWA_GetChannelClockAbsenceLimitThreshold(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CPR & SDDF_CPR_CADLMT_MASK) >> SDDF_CPR_CADLMT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the clock absence detector limitation threshold + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param u8Thres the clock absence detector limitation threshold + */ +LOCAL_INLINE void SDDF_HWA_SetChannelClockAbsenceLimitThreshold(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + uint8_t u8Thres) +{ + pSddf->CH[u8ChanIdx].CPR = (pSddf->CH[u8ChanIdx].CPR & ~SDDF_CPR_CADLMT_MASK) | SDDF_CPR_CADLMT(u8Thres); +} + +/** + * @brief Get the channel limit check option + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_ChannelLimitOptionType the channel limit check option + */ +LOCAL_INLINE SDDF_ChannelLimitOptionType SDDF_HWA_GetChannelLimitOption(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CPR & SDDF_CPR_LMTOPT_MASK) >> SDDF_CPR_LMTOPT_SHIFT; + return (SDDF_ChannelLimitOptionType)u32TmpVal; +} + +/** + * @brief Set the channel limit check option + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eOption the channel limit check option + */ +LOCAL_INLINE void SDDF_HWA_SetChannelLimitOption(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_ChannelLimitOptionType eOption) +{ + pSddf->CH[u8ChanIdx].CPR = (pSddf->CH[u8ChanIdx].CPR & ~SDDF_CPR_LMTOPT_MASK) | SDDF_CPR_LMTOPT(eOption); +} + +/** + * @brief Get the channel short circuit detect option + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_ShortCircuitOptionType the channel short circuit detect option + */ +LOCAL_INLINE SDDF_ShortCircuitOptionType SDDF_HWA_GetChannelShortCircuitOption(const SDDF_Type *const pSddf, + uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CPR & SDDF_CPR_SCDOPT_MASK) >> SDDF_CPR_SCDOPT_SHIFT; + return (SDDF_ShortCircuitOptionType)u32TmpVal; +} + +/** + * @brief Set the channel short circuit detect option + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eOption the channel short circuit detect option + */ +LOCAL_INLINE void SDDF_HWA_SetChannelShortCircuitOption(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_ShortCircuitOptionType eOption) +{ + pSddf->CH[u8ChanIdx].CPR = (pSddf->CH[u8ChanIdx].CPR & ~SDDF_CPR_SCDOPT_MASK) | SDDF_CPR_SCDOPT(eOption); +} + +/** + * @brief Get the channel short circuit detect conversion mode + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return SDDF_ShortCircuitDetectModeType the channel short circuit detect conversion mode + */ +LOCAL_INLINE SDDF_ShortCircuitDetectModeType SDDF_HWA_GetShortCircuitDetectMode(const SDDF_Type *const pSddf, + uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CPR & SDDF_CPR_SCDCM_MASK) >> SDDF_CPR_SCDCM_SHIFT; + return (SDDF_ShortCircuitDetectModeType)u32TmpVal; +} + +/** + * @brief Set the channel short circuit detect conversion mode + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param eMode the channel short circuit detect conversion mode + */ +LOCAL_INLINE void SDDF_HWA_SetShortCircuitDetectMode(SDDF_Type *const pSddf, uint8_t u8ChanIdx, + SDDF_ShortCircuitDetectModeType eMode) +{ + pSddf->CH[u8ChanIdx].CPR = (pSddf->CH[u8ChanIdx].CPR & ~SDDF_CPR_SCDCM_MASK) | SDDF_CPR_SCDCM(eMode); +} + +/** + * @brief Get the threshold value for short circuit detector counter of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return uint8_t the threshold value for short circuit detector counter + */ +LOCAL_INLINE uint8_t SDDF_HWA_GetShortCircuitLimitThreshold(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + uint32_t u32TmpVal = (pSddf->CH[u8ChanIdx].CPR & SDDF_CPR_SCDLMT_MASK) >> SDDF_CPR_SCDLMT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the threshold value for short circuit detector counter of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param u8Thres the threshold value for short circuit detector counter + */ +LOCAL_INLINE void SDDF_HWA_SetShortCircuitLimitThreshold(SDDF_Type *const pSddf, uint8_t u8ChanIdx, uint8_t u8Thres) +{ + pSddf->CH[u8ChanIdx].CPR = (pSddf->CH[u8ChanIdx].CPR & ~SDDF_CPR_SCDLMT_MASK) | SDDF_CPR_SCDLMT(u8Thres); +} + +/** + * @brief Get the bias value for the selected channel main filter + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return int32_t the bias value for result adjustment or compensation + */ +LOCAL_INLINE int32_t SDDF_HWA_GetChannelBias(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + return (int32_t)pSddf->CH[u8ChanIdx].CBR; +} + +/** + * @brief Set the bias value for the selected channel main filter + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param s32Bias the bias value for result adjustment or compensation + */ +LOCAL_INLINE void SDDF_HWA_SetChannelBias(SDDF_Type *const pSddf, uint8_t u8ChanIdx, int32_t s32Bias) +{ + pSddf->CH[u8ChanIdx].CBR = (uint32_t)s32Bias; +} + +/** + * @brief Get the low limit threshold for limit check of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return uint32_t the low limit threshold + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetChannelLowLimit(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + return pSddf->CH[u8ChanIdx].CLLMT; +} + +/** + * @brief Set the low limit threshold for limit check of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param u32LowLimit the low limit threshold + */ +LOCAL_INLINE void SDDF_HWA_SetChannelLowLimit(SDDF_Type *const pSddf, uint8_t u8ChanIdx, uint32_t u32LowLimit) +{ + pSddf->CH[u8ChanIdx].CLLMT = u32LowLimit; +} + +/** + * @brief Get the high limit threshold for limit check of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return uint32_t the high limit threshold + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetChannelHighLimit(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + return pSddf->CH[u8ChanIdx].CHLMT; +} + +/** + * @brief Set the high limit threshold for limit check of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @param u32HighLimit the high limit threshold + */ +LOCAL_INLINE void SDDF_HWA_SetChannelHighLimit(SDDF_Type *const pSddf, uint8_t u8ChanIdx, uint32_t u32HighLimit) +{ + pSddf->CH[u8ChanIdx].CHLMT = u32HighLimit; +} + +/** + * @brief Get the result data of the selected channel + * + * @param pSddf the base address of the SDDF instance + * @param u8ChanIdx the selected SDDF channel + * @return uint32_t the result data + */ +LOCAL_INLINE uint32_t SDDF_HWA_GetChannelData(const SDDF_Type *const pSddf, uint8_t u8ChanIdx) +{ + return pSddf->CH[u8ChanIdx].CRDATA; +} + +/** @}*/ + +#endif /* #if SDDF_INSTANCE_COUNT > 0U */ + +#endif /* _HWA_SDDF_H_ */ diff --git a/Inc/HwA_sec.h b/Inc/HwA_sec.h new file mode 100644 index 0000000..931c7c7 --- /dev/null +++ b/Inc/HwA_sec.h @@ -0,0 +1,753 @@ +/** + * @file HwA_sec.h + * @author Flagchip + * @brief sec hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip120 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip120 N/A Change version and release + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_SEC_H_ +#define HWA_INCLUDE_HWA_SEC_H_ +#include "device_header.h" + +#if SEC_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_sec HwA_sec + * @ingroup module_driver_sec + * @{ + */ + +/* DEN Bit Fields */ +/** + * @brief Enable the debug module + * + * @param pSec A pointer to the SEC registers. + */ +LOCAL_INLINE void SEC_HWA_EnDebug(SEC_Type *const pSec) +{ + pSec->DEN = SEC_DEN_DEN(0X5) ; +} + +/* FSEC0 Bit Fields */ +/** + * @brief Get the system security KEY0 + * + * @param pSec A pointer to the SEC registers. + * */ +LOCAL_INLINE uint16_t SEC_HWA_GetSScontrol0(SEC_Type *const pSec) +{ + return (uint16_t)((pSec->FSEC0) & (SEC_FSEC0_SSC0_MASK)); +} + +/* FSEC1 Bit Fields */ +/** + * @brief Get the system security KEY1 + * + * @param pSec A pointer to the SEC registers. + * */ +LOCAL_INLINE uint16_t SEC_HWA_GetSScontrol1(SEC_Type *const pSec) +{ + return (uint16_t)((pSec->FSEC1) & (SEC_FSEC1_SSC1_MASK)); +} + +/* DCWOR Bit Fields */ +/** + * @brief Re-enable the Debug mode. + * @note This register can only be write once. startup_fc4150.s has lock the register. + * + * @param pSec A pointer to the SEC registers. + * */ +LOCAL_INLINE void SEC_HWA_ReEnDebug(SEC_Type *const pSec) +{ + pSec->DCWOR = ((pSec->DCWOR & (~SEC_DCWOR_DEA_MASK)) | SEC_DCWOR_DEA(0X5)); +} + +/** + * @brief Get the Re-enable Debug permission. + * + * @param pSec A pointer to the SEC registers. + * */ +LOCAL_INLINE bool SEC_HWA_GetReEnDebug(SEC_Type *const pSec) +{ + bool ret = false; + uint8_t dea = (uint8_t)((pSec->DCWOR & (SEC_DCWOR_DEA_MASK)) >> SEC_DCWOR_DEA_SHIFT); + if (dea == 0x5U) + { + ret = true; + } + return ret; +} + +/** + * @brief Enable the write operation for SEC register. + * @note This register can only be write once. startup_fc4150.s has lock the register. + * + * @param pSec A pointer to the SEC registers. + * */ +LOCAL_INLINE void SEC_HWA_WriteUnlock(SEC_Type *const pSec) +{ + pSec->DCWOR = ((pSec->DCWOR & (~SEC_DCWOR_RWL_MASK)) | SEC_DCWOR_RWL(0X5)); +} + +/** + * @brief Get the sec write permission + * + * @param pSec A pointer to the SEC registers. + * @return true means allow write. false means forbid write. +*/ +LOCAL_INLINE bool SEC_HWA_GetWritePer(SEC_Type *const pSec) +{ + bool ret = false; + uint8_t rwl = (uint8_t)((pSec->DCWOR & (SEC_DCWOR_RWL_MASK)) >> SEC_DCWOR_RWL_SHIFT); + if ((rwl == 0x5U) || (rwl == 0xFU)) + { + ret = true; + } + return ret; +} + +/* DEK Bit Fields */ +/** + * @brief Enable the write operation for SEC register. + * + * @param pSec A pointer to the SEC registers. + * @param count Counter indicating the number of encryption executions + * @param key New encryption key to be written + * */ +LOCAL_INLINE void SEC_HWA_WriteReEnKeyn(SEC_Type *const pSec, uint8_t count, uint32_t key) +{ + if (count < 4u) + { + pSec->DEN = key; + } +} + +/* TME Bit Fields */ +/** + * @brief Enable the Test module + * + * @param pSec A pointer to the SEC registers. + * */ +LOCAL_INLINE void SEC_HWA_EnTest(SEC_Type *const pSec) +{ + pSec->TME = SEC_TME_TME(0X5) ; +} + +/* TMEA Bit Fields */ +/** + * @brief Re-Enable Test mode + * + * @param pSec A pointer to the SEC registers. + * */ +LOCAL_INLINE void SEC_HWA_ReEnTest(SEC_Type *const pSec) +{ + pSec->TMEA = SEC_TMEA_TMEA(0X5) ; +} + +/** + * @brief Get the Re-enable Test permission. + * + * @param pSec A pointer to the SEC registers. + * */ +LOCAL_INLINE bool SEC_HWA_GetReEnTest(SEC_Type *const pSec) +{ + bool ret = false; + uint8_t tmea = (uint8_t)((pSec->TMEA & (SEC_TMEA_TMEA_MASK)) >> SEC_TMEA_TMEA_SHIFT); + if ((tmea == 0x5U) || (tmea == 0xFU)) + { + ret = true; + } + return ret; +} + +/* TMEK Bit Fields */ +/** + * @brief write Test re-enable mode key + * + * @param pSec A pointer to the SEC registers. + * @param testkey The test key value to be reloaded into the TMEK register. + */ +LOCAL_INLINE void SEC_HWA_ReEnTestKey(SEC_Type *const pSec, uint32_t testkey) +{ + pSec->TMEK = SEC_TMEK_TMEK(testkey) ; +} + +/* FCR0 Bit Fields */ +/** + * @brief Enable the Mass Erase + * + * @param pSec A pointer to the SEC registers. + */ +LOCAL_INLINE void SEC_HWA_EnME(SEC_Type *const pSec) +{ + pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_MED_MASK)) | SEC_FCR0_MED(0x5)); +} + +#if SEC_FCR0_NRP_MASK +/** + * @brief Enable the Block 0 NVR read . + * + * @param pSec A pointer to the SEC registers. + */ +LOCAL_INLINE void SEC_HWA_EnReadB0NVR(SEC_Type *const pSec) +{ + pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_NRP_MASK)) | SEC_FCR0_NRP(0x5)) ; +} + +/** + * @brief Disable the Block 0 NVR read . + * + * @param pSec A pointer to the SEC registers. + */ +LOCAL_INLINE void SEC_HWA_DisReadB0NVR(SEC_Type *const pSec) +{ + pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_NRP_MASK)) | SEC_FCR0_NRP(0xA)) ; +} +#endif + +#if SEC_NKRP_NKRP_MASK +/** + * @brief Enable the Block 0 NVR key read . + * + * @param pSec A pointer to the SEC registers. + */ +LOCAL_INLINE void SEC_HWA_EnReadB0NVRKey(SEC_Type *const pSec) +{ + pSec->NKRP = ((pSec->NKRP & (~SEC_NKRP_NKRP_MASK)) | SEC_NKRP_NKRP(0x5)) ; +} + +/** + * @brief Disable the Block 0 NVR Key read . + * + * @param pSec A pointer to the SEC registers. + */ +LOCAL_INLINE void SEC_HWA_DisReadB0NVRKey(SEC_Type *const pSec) +{ + pSec->NKRP = ((pSec->NKRP & (~SEC_NKRP_NKRP_MASK)) | SEC_NKRP_NKRP(0xA)) ; +} +#endif + +/** + * @brief Enable the Block 0 NVR write . + * + * @param pSec A pointer to the SEC registers. + */ +LOCAL_INLINE void SEC_HWA_EnWriteB0NVR(SEC_Type *const pSec) +{ + pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_NWP_MASK)) | SEC_FCR0_NWP(0x5)) ; +} + +/** + * @brief Disable the Block 0 NVR write . + * + * @param pSec A pointer to the SEC registers. + */ +LOCAL_INLINE void SEC_HWA_DisWriteB0NVR(SEC_Type *const pSec) +{ + pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_NWP_MASK)) | SEC_FCR0_NWP(0xA)) ; +} + +/** + * @brief Enable the Block 0 NVR erase . + * + * @param pSec A pointer to the SEC registers. + */ +LOCAL_INLINE void SEC_HWA_EnEraseB0NVR(SEC_Type *const pSec) +{ + pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_NEP_MASK)) | SEC_FCR0_NEP(0x5)) ; +} + +/** + * @brief Disable the Block 0 NVR erase . + * + * @param pSec A pointer to the SEC registers. + */ +LOCAL_INLINE void SEC_HWA_DisEraseB0NVR(SEC_Type *const pSec) +{ + pSec->FCR0 = ((pSec->FCR0 & (~SEC_FCR0_NEP_MASK)) | SEC_FCR0_NEP(0xA)) ; +} + +/* BCS Bit Fields */ +/** + * @brief Get the Fast Boot Select. + * + * @param pSec A pointer to the SEC registers. + * @return 0b - Select PLL0 as the core clock source; the core clock is 300MHz + * 1b - Select FIRC as the core clock source; the core clock is 96MHz. + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetFastBootClock(SEC_Type *const pSec) +{ + return (uint8_t)((pSec->BCS & SEC_BCS_FBS_MASK) >> SEC_BCS_FBS_SHIFT); +} + +/** + * @brief NMI Function Enable/Disable + * + * @param pSec A pointer to the SEC registers. + * @return false - NMI pin function is disabled after reset. + * true - NMI pin function is enabled + * */ +LOCAL_INLINE bool SEC_HWA_GetNmiPin(SEC_Type *const pSec) +{ + return (bool)((pSec->BCS & SEC_BCS_NMIDIS_MASK) >> SEC_BCS_NMIDIS_SHIFT); +} + +#if SEC_BCS_ISPDIS_MASK +/** + * @brief ISP Function Enable/Disable + * + * @param pSec A pointer to the SEC registers. + * @return false - ISP pin function is disabled after reset. + * true - ISP pin function is enabled. + * */ +LOCAL_INLINE bool SEC_HWA_GetIspEn(SEC_Type *const pSec) +{ + return (bool)((pSec->BCS & SEC_BCS_ISPDIS_MASK) >> SEC_BCS_ISPDIS_SHIFT); +} +#endif + +/** + * @brief Boot Rom Configuration + * + * @param pSec A pointer to the SEC registers. + * @return false - Boot from GPR defined address (except ROM). + * true - Boot from ROM. + * */ +LOCAL_INLINE bool SEC_HWA_GetBootRom(SEC_Type *const pSec) +{ + return (bool)((pSec->BCS & SEC_BCS_BOOTROM_MASK) >> SEC_BCS_BOOTROM_SHIFT); +} + +/** + * @brief ISP Mode Status + * + * @param pSec A pointer to the SEC registers. + * @return false - ISP mode is inactive. + * true - ISP mode is active. + * */ +LOCAL_INLINE bool SEC_HWA_GetIspStatus(SEC_Type *const pSec) +{ + return (bool)((pSec->BCS & SEC_BCS_ISPMODE_MASK) >> SEC_BCS_ISPMODE_SHIFT); +} + +/* UKAC Bit Fields */ + +/** + * @brief User Key Access Enable. Only valid under non-secure boot + * + * @param pSec A pointer to the SEC registers. + * @return true means User key can be read/programmed/erased by host CPU ,false means User key is not available for host cpu + * */ + +LOCAL_INLINE bool SEC_HWA_GetUKAS(SEC_Type *const pSec) +{ + bool ret = false; + uint8_t uake =(uint8_t)((pSec->UKAC & SEC_UKAC_UKAE_MASK) >> SEC_UKAC_UKAE_SHIFT); + if ((uake == 0x5U) || (uake == 0xFU)) + { + ret = true; + } + return ret; +} + +/* BRC0 Bit Fields */ +/** + * @brief Secure Boot Disable (Value loaded from NVR sector) + * + * @param pSec A pointer to the SEC registers. + * @return true means Secure boot mode , false means Non secure boot mode. + */ +LOCAL_INLINE bool SEC_HWA_GetSB(SEC_Type *const pSec) +{ + bool ret = false; +#if SEC_BRC0_SECURE_BOOT_DIS_MASK + uint8_t sbdis = (uint8_t)((pSec->BRC0 & SEC_BRC0_SECURE_BOOT_DIS_MASK) >> SEC_BRC0_SECURE_BOOT_DIS_SHIFT); + + if (sbdis == 0x0u) + { + ret = true; + } + +#elif defined SEC_BRC0_SB_LC_EN_MASK + uint8_t sbdis = (uint8_t)((pSec->BRC0 & SEC_BRC0_SB_LC_EN_MASK) >> SEC_BRC0_SB_LC_EN_SHIFT); + + if (sbdis == 0x0u) + { + ret = true; + } + +#else + +#endif + + return ret; +} + +/** + * @brief Host Debug Auth Enable. Only valid in secure boot. (Value loaded from NVR sector) + * + * @param pSec A pointer to the SEC registers. + * @return true means Host debug authentication enable. false means Host debug authentication disable. + */ +LOCAL_INLINE bool SEC_HWA_GetDEAUEn(SEC_Type *const pSec) +{ + bool ret = false; + uint8_t dean = (uint8_t)((pSec->BRC0 & SEC_BRC0_DEBUG_AUTH_EN_MASK) >> SEC_BRC0_DEBUG_AUTH_EN_SHIFT); + if ((dean == 0x5u) || (dean == 0xFu)) + { + ret = true; + } + return ret; +} + +/** + * @brief ISP Auth Enable. Only valid in secure boot. (Value loaded from NVR sector) + * + * @param pSec A pointer to the SEC registers. + * @return true means ISP authentication enable, false means ISP authentication disable. + */ +LOCAL_INLINE bool SEC_HWA_GetISPAU(SEC_Type *const pSec) +{ + bool ret = false; + uint8_t isp = (uint8_t)((pSec->BRC0 & SEC_BRC0_ISP_AUTH_EN_MASK) >> SEC_BRC0_ISP_AUTH_EN_SHIFT); + if ((isp == 0x5u) || (isp == 0xFu)) + { + ret = true; + } + return ret; +} + +#if SEC_BRC0_FW_READ_DIS_MASK +/** + * @brief Firmware Read Disable/Enable. (Value loaded from NVR sector) + * + * @param pSec A pointer to the SEC registers. + * @return true means Host core read access to firmware read is disabled, false means - Host core read access to firmware read is enabled. + */ +LOCAL_INLINE bool SEC_HWA_GetFWRE(SEC_Type *const pSec) +{ + bool ret = false; + uint8_t fwre = (uint8_t)((pSec->BRC0 & SEC_BRC0_FW_READ_DIS_MASK) >> SEC_BRC0_FW_READ_DIS_SHIFT); + if ((fwre == 0x5u) || (fwre == 0xFu)) + { + ret = true; + } + return ret; +} +#endif + +#if SEC_BRC1_FW_VALID_MASK +/* BRC1 Bit Fields */ +/** + * @brief Get whether Flash Firmware is valid. + * + * @param pSec A pointer to the SEC registers. + * @return true means Flash Firmware is valid. false means Flash Firmware is invalid + * */ +LOCAL_INLINE bool SEC_HWA_GetFwValid(SEC_Type *const pSec) +{ + bool ret = false; + uint8_t fw = (uint8_t)((pSec->BRC1 & SEC_BRC1_FW_VALID_MASK) >> SEC_BRC1_FW_VALID_SHIFT); + if (fw != 0xFU) + { + ret = true; + } + return ret; +} +#endif + +/** + * @brief Get the FCUART Baud Rate for ISP + * + * @param pSec A pointer to the SEC registers. + * @return FCUART Baud Rate for ISP + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetUartBR(SEC_Type *const pSec) +{ + return (uint8_t)((pSec->BRC1 & SEC_BRC1_UARTBR_MASK) >> SEC_BRC1_UARTBR_SHIFT); +} + +/** + * @brief Get CAN Baud Rate for ISP + * + * @param pSec A pointer to the SEC registers. + * @return CAN Baud Rate for ISP + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetCanBR(SEC_Type *const pSec) +{ + return (uint8_t)((pSec->BRC1 & SEC_BRC1_CANBR_MASK) >> SEC_BRC1_CANBR_SHIFT); +} + +/** + * @brief Get OSC Frequency + * + * @param pSec A pointer to the SEC registers. + * @return OSC Frequency + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetOSCFre(SEC_Type *const pSec) +{ + return (uint8_t)((pSec->BRC1 & SEC_BRC1_OSCFREQ_MASK) >> SEC_BRC1_OSCFREQ_SHIFT); +} + +/** + * @brief Get whether OSC Available. + * + * @param pSec A pointer to the SEC registers. + * @return true means OSC is available. false means -OSC is not available + * */ +LOCAL_INLINE bool SEC_HWA_GetOSCAvail(SEC_Type *const pSec) +{ + bool ret = false; + uint8_t osc = (uint8_t)((pSec->BRC1 & SEC_BRC1_OSCA_MASK) >> SEC_BRC1_OSCA_SHIFT); + if (osc == 0x0U) + { + ret = true; + } + return ret; +} + +/** + * @brief Get whether Debug Mailbox Backdoor Key Enable. + * + * @param pSec A pointer to the SEC registers. + * @return true means user can enable debug by writing debug backdoor key, false means user can not enable debug + * */ + +LOCAL_INLINE bool SEC_HWA_GetMBBKEN(SEC_Type *const pSec) +{ + bool ret = false; +#if SEC_BRC1_DBG_MB_BKD_EN_MASK + uint8_t mbbk = (uint8_t)((pSec->BRC1 & SEC_BRC1_DBG_MB_BKD_EN_MASK) >> SEC_BRC1_DBG_MB_BKD_EN_SHIFT); + if (mbbk == 0x5U) +#elif SEC_BRC1_DBK_IN_EN_MASK + uint8_t mbbk = (uint8_t)((pSec->BRC1 & SEC_BRC1_DBK_IN_EN_MASK) >> SEC_BRC1_DBK_IN_EN_SHIFT); + if((mbbk == 0x3U) || (mbbk == 0xFU)) +#else +#endif + { + ret = true; + } + return ret; +} + +#if SEC_FWA_MASK +/* FWA Bit Fields */ +/** + * @brief Get the HSM Firmware Address. + * + * @param pSec A pointer to the SEC registers. + * @return the HSM Firmware Address. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetHsmAddr(SEC_Type *const pSec) +{ + return (uint32_t)(pSec->FWA & SEC_FWA_HSM_FW_ADDR_MASK); +} +#endif + +/* BRC2 Bit Fields */ +/** + * @brief Get Bootloader Verification Mask + * + * @param pSec A pointer to the SEC registers. + * @return Bootloader Verification Mask. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetBLMask(SEC_Type *const pSec) +{ +#if SEC_BRC2_USERCODE_VERIFY_MASK_MASK + return (uint32_t)((pSec->BRC2 & SEC_BRC2_USERCODE_VERIFY_MASK_MASK) >> SEC_BRC2_USERCODE_VERIFY_MASK_SHIFT); +#elif SEC_BRC2_IMG_VERIFY_MASK_MASK + return (uint32_t)((pSec->BRC2 & SEC_BRC2_IMG_VERIFY_MASK_MASK) >> SEC_BRC2_IMG_VERIFY_MASK_SHIFT); +#else +#endif +} + +/** + * @brief Get the ISP Instance Select. + * + * @param pSec A pointer to the SEC registers. + * @return ISP Instance Select + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetIspIns(SEC_Type *const pSec) +{ + return (uint8_t)((pSec->BRC2 & SEC_BRC2_ISP_INST_SEL_MASK) >> SEC_BRC2_ISP_INST_SEL_SHIFT); +} + +/** + * @brief Get Bootloader Verification Algorithm + * + * @param pSec A pointer to the SEC registers. + * @return Bootloader Verification Algorithm + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetBLVer(SEC_Type *const pSec) +{ +#if SEC_BRC2_USERCODE_VERIFICATION_ALG_MASK + return (uint8_t)((pSec->BRC2 & SEC_BRC2_USERCODE_VERIFICATION_ALG_MASK) >> SEC_BRC2_USERCODE_VERIFICATION_ALG_SHIFT); +#elif SEC_BRC2_IMG_VERIF_ALG_MASK + return (uint8_t)((pSec->BRC2 & SEC_BRC2_IMG_VERIF_ALG_MASK) >> SEC_BRC2_IMG_VERIF_ALG_SHIFT); +#else +#endif + +} + +#if SEC_BRC2_DECRP_ALG_MASK +/** + * @brief Get Debug/ISP/PREFA Authentication and USRK decryption algorithm + * + * @param pSec A pointer to the SEC registers. + * @return 1b - SM2, 0b - ECC256 + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetDecrypt(SEC_Type *const pSec) +{ + return (uint8_t)((pSec->BRC2 & SEC_BRC2_DECRP_ALG_MASK) >> SEC_BRC2_DECRP_ALG_SHIFT); +} +#endif + +/* BTLA Bit Fields */ +/** + * @brief Get the bootloader address. + * + * @param pSec A pointer to the SEC registers. + * @return Bootloader Address. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetBLAddr(SEC_Type *const pSec) +{ + return (uint32_t)((pSec->IMGEA & SEC_IMGEA_IMAGE_ADDR_MASK) >> SEC_IMGEA_IMAGE_ADDR_SHIFT); +} + +/* LCSTAT Bit Fields */ +/** + * @brief Get the life cycle status of the chip. + * + * @param pSec A pointer to the SEC registers. + * @return The lifecycle status + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetLCStaus(SEC_Type *const pSec) +{ + return (uint8_t)(pSec->LCSTAT & 0XFFU); +} + +/* FAC Bit Fields */ + +/** + * @brief Get the Host User Key Read Protection + * + * @param pSec A pointer to the SEC registers. + * @return true - Host read access to User Key region is enabled + * false - Host read access to User Key region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHUKRead(SEC_Type *const pSec) +{ + return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_UKEY_RPROT_MASK) >> SEC_FAC_HOST_UKEY_RPROT_SHIFT)); +} + +/** + * @brief Get the Host User Key write Protection + * + * @param pSec A pointer to the SEC registers. + * @return true - Host write access to User Key region is enabled + * false - Host write access to User Key region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHUKWrite(SEC_Type *const pSec) +{ + return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_UKEY_WPROT_MASK) >> SEC_FAC_HOST_UKEY_WPROT_SHIFT)); +} + +/** + * @brief Get the Host User Key erase Protection + * + * @param pSec A pointer to the SEC registers. + * @return true - Host erase access to User Key region is enabled + * false - Host erase access to User Key region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHUKErase(SEC_Type *const pSec) +{ + return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_UKEY_EPROT_MASK) >> SEC_FAC_HOST_UKEY_EPROT_SHIFT)); +} + +/** + * @brief Get the Host NVR Read Protection + * + * @param pSec A pointer to the SEC registers. + * @return true - Host read access to NVR region is enabled + * false - Host read access to NVR region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHostNvrRead(SEC_Type *const pSec) +{ + return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_NVR_RPROT_MASK) >> SEC_FAC_HOST_NVR_RPROT_SHIFT)); +} + +/** + * @brief Get the Host NVR write Protection + * + * @param pSec A pointer to the SEC registers. + * @return true - Host write access to NVR region is enabled + * false - Host write access to NVR region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHostNvrWrite(SEC_Type *const pSec) +{ + return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_NVR_WPROT_MASK) >> SEC_FAC_HOST_NVR_WPROT_SHIFT)); +} + +/** + * @brief Get the Host NVR erase Protection + * + * @param pSec A pointer to the SEC registers. + * @return true - Host erase access to NVR region is enabled + * false - Host erase access to NVR region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHostNvrErase(SEC_Type *const pSec) +{ + return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_NVR_EPROT_MASK) >> SEC_FAC_HOST_NVR_EPROT_SHIFT)); +} + +/** + * @brief Get the HSM User Key Erase Protection + * + * @param pSec A pointer to the SEC registers. + * @return true - HSM erase access to User Key region is enabled + * false -HSM erase access to User Key region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmUKErase(SEC_Type *const pSec) +{ +#if SEC_FAC_HSM_UKEY_EPROT_MASK + return (bool)(~(((pSec->FAC) & SEC_FAC_HSM_UKEY_EPROT_MASK) >> SEC_FAC_HSM_UKEY_EPROT_SHIFT)); +#elif SEC_FAC_HOST_EUKEY_EPROT_MASK + return (bool)(~(((pSec->FAC) & SEC_FAC_HOST_EUKEY_EPROT_MASK) >> SEC_FAC_HOST_EUKEY_EPROT_SHIFT)); +#else + +#endif +} + +/** + * @brief Get the HSM NVR Erase Protection + * + * @param pSec A pointer to the SEC registers. + * @return true - HSM erase access to NVR region is enabled + * false -HSM erase access to NVR region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmNvrErase(SEC_Type *const pSec) +{ + return (bool)(~(((pSec->FAC) & SEC_FAC_HSM_NVR_EPROT_MASK) >> SEC_FAC_HSM_NVR_EPROT_SHIFT)); +} + +/** @}*/ /* HwA_SEC */ + +#endif /* #if SEC_INSTANCE_COUNT > 0U */ + +#endif /* HWA_INCLUDE_HWA_SEC_H_ */ diff --git a/Inc/HwA_sent.h b/Inc/HwA_sent.h new file mode 100644 index 0000000..e3fdcf9 --- /dev/null +++ b/Inc/HwA_sent.h @@ -0,0 +1,1443 @@ +/** + * @file HwA_sent.h + * @author flagchip + * @brief Hardware access layer for SENT + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip073 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip073 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_SENT_H_ +#define _HWA_SENT_H_ + +#include "device_header.h" + +#if SENT_INSTANCE_COUNT > 0U + +#define DMA_CH_TO_DCHPRI(x) ((x) ^ 3U) + +/** + * @defgroup HwA_sent HwA_sent + * @ingroup module_driver_sent + * @{ + */ + +/** + * @brief sent running status + * + */ +typedef enum +{ + SENT_NIBBLE_DATA_MODE_A = 0x0U, /*!< Frame format A */ + SENT_NIBBLE_DATA_MODE_H1 = 0x1U, /*!< Frame format H1 */ + SENT_NIBBLE_DATA_MODE_H2 = 0x2U, /*!< Frame format H2 */ + SENT_NIBBLE_DATA_MODE_H3 = 0x3U, /*!< Frame format H3 */ + SENT_NIBBLE_DATA_MODE_H4 = 0x4U, /*!< Frame format H4 */ + SENT_NIBBLE_DATA_MODE_H5 = 0x5U, /*!< Frame format H5 */ + SENT_NIBBLE_DATA_MODE_H6 = 0x6U, /*!< Frame format H6 */ + SENT_NIBBLE_DATA_MODE_H7 = 0x7U /*!< Frame format H7 */ +} SENT_NibbleDataModeType; + +/** + * @brief sent slow message type + * + */ +typedef enum +{ + SENT_SLOW_MESSAGE_SHORT = 0x0U, /*!< short serial data message */ + SENT_SLOW_MESSAGE_ENHANCE_12DATA_8ID = 0x1U, /*!< enhanced serial data message with 12-bit data and 8-bit ID */ + SENT_SLOW_MESSAGE_ENHANCE_16DATA_4ID = 0x2U, /*!< enhanced serial data message with 16-bit data and 4-bit ID */ +} SENT_SlowMessageType; + +/** + * @brief sent SPC trigger type + * + */ +typedef enum +{ + SENT_SPC_SW_TRIGGER = 0x0U, /*!< SPC pulse triggered by software method */ + SENT_SPC_HW_TRIGGER = 0x1U, /*!< SPC pulse triggered by external trigger */ +} SENT_SPCTriggerType; + +/** + * @brief sent SPC tick base + * + */ +typedef enum +{ + SENT_SPC_TICK_PRE_RECEIVED_MESSAGE = 0x0U, /*!< Previous received message tick base */ + SENT_SPC_TICK_CONFIG = 0x1U, /*!< SENT configured tick base */ +} SENT_SPCTickType; + +/** + * @brief Set SENT Global pre-scaler value + * + * @param pSent the base address of the SENT instance + * @param u8PreScaler the value of the PreSclaer. + */ +LOCAL_INLINE void SENT_HWA_SetGlobalPreScaler(SENT_Type *const pSent, uint8_t u8PreScaler) +{ + pSent->GLBL_CTL = (pSent->GLBL_CTL & ~SENT_GLBL_CTL_PRE_SCALER_MASK) | SENT_GLBL_CTL_PRE_SCALER(u8PreScaler); +} + +/** + * @brief Set SENT Global DMA watermark value + * + * @param pSent the base address of the SENT instance + * @param u8WaterMark the value of the dma watermark. + */ +LOCAL_INLINE void SENT_HWA_SetDMAWaterMark(SENT_Type *const pSent, uint8_t u8WaterMark) +{ + pSent->GLBL_CTL = (pSent->GLBL_CTL & ~SENT_GLBL_CTL_DMA_WATERMARK_MASK) | SENT_GLBL_CTL_DMA_WATERMARK(u8WaterMark); +} + +/** + * @brief Enable SENT Fast message FIFO overflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableFastMessageFIFOOverflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_F_FIFO_OVFL_IE_MASK; +} + +/** + * @brief Disable SENT Fast message FIFO overflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableFastMessageFIFOOverflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_F_FIFO_OVFL_IE_MASK; +} + +/** + * @brief Enable SENT Fast message read underflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableFastMessagedmaReadUnderflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_F_DMA_UDFL_IE_MASK; +} + +/** + * @brief Disable SENT Fast message read underflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableFastMessagedmaReadUnderflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_F_DMA_UDFL_IE_MASK; +} + +/** + * @brief Enable SENT slow message read underflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableSlowMessagedmaReadUnderflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_S_DMA_UDFL_IE_MASK; +} + +/** + * @brief Disable SENT slow message read underflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableSlowMessagedmaReadUnderflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_S_DMA_UDFL_IE_MASK; +} + +/** + * @brief Enable SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableDebugMode(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_DBG_EN_MASK; +} + +/** + * @brief Disable SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableDebugMode(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_DBG_EN_MASK; +} + +/** + * @brief Enable Global SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableGlobal(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_SENT_EN_MASK; +} + +/** + * @brief Disable Global SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableGlobal(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_SENT_EN_MASK; +} + +/** + * @brief Enable Global SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableDataOverflowFlagFastClear(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_FAST_CLR_MASK; +} + +/** + * @brief Disable Global SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableDataOverflowFlagFastClear(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_FAST_CLR_MASK; +} + +/** + * @brief Enable SENT channel receive + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelReceive(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->CHN_EN |= SENT_CHN_EN_CHN_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel receive + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelReceive(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->CHN_EN &= ~SENT_CHN_EN_CHN_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Get SENT channel receive + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE bool SENT_HWA_GetChannelReceive(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_CHN_EN_CHN_EN((uint32_t)1u << u8Channel) == (pSent->CHN_EN & SENT_CHN_EN_CHN_EN((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Get Channel slow message dma read underflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel slow message dma is underflow + */ +LOCAL_INLINE bool SENT_HWA_GetSLowMessageUnderflowFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(((uint32_t)1u << u8Channel) == (pSent->GLBL_STAT & SENT_GLBL_STAT_S_DMA_UDFL((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel slow message dma read underflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearSLowMessageUnderflowFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->GLBL_STAT = SENT_GLBL_STAT_S_DMA_UDFL((uint32_t)1u << u8Channel); +} + +/** + * @brief Get Channel fast message ready flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel fast message is ready + */ +LOCAL_INLINE bool SENT_HWA_GetFastMessageReadyFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_FMSG_STAT_F_MSG_RDY((uint32_t)1u << u8Channel) == (pSent->FMSG_STAT & SENT_FMSG_STAT_F_MSG_RDY((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel fast message ready flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearFastMessageReadyFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FMSG_STAT = SENT_FMSG_STAT_F_MSG_RDY((uint32_t)1u << u8Channel); +} + +/** + * @brief Get Channel slow message ready flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel slow message is ready + */ +LOCAL_INLINE bool SENT_HWA_GetSlowMessageReadyFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(((uint32_t)1u << u8Channel) == (pSent->SMSG_STAT & ((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel slow message ready flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearSlowMessageReadyFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SMSG_STAT = SENT_FMSG_STAT_F_MSG_RDY((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel FIFO function + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFIFO(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FIFO_EN |= SENT_FIFO_EN_FIFO_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel receive function + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFIFO(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FIFO_EN &= ~SENT_FIFO_EN_FIFO_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Set SENT channel data nibble number + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u8Number the received data number + */ +LOCAL_INLINE void SENT_HWA_SetChannelNibbleNumber(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Number) +{ + pSent->DATA_NUM_CTL1 = (pSent->DATA_NUM_CTL1 & ~(SENT_DATA_NUM_CTL1_CH0_DATA_CTL_MASK >> (4u * u8Channel))) | (SENT_DATA_NUM_CTL1_CH0_DATA_CTL(u8Number) >> (4u * u8Channel)); +} + +/** + * @brief Get SENT channel data nibble number + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param uint8_t the config data number + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelNibbleNumber(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->DATA_NUM_CTL1 & (SENT_DATA_NUM_CTL1_CH0_DATA_CTL_MASK >> (4u * u8Channel))) >> (SENT_DATA_NUM_CTL1_CH0_DATA_CTL_SHIFT - (4u * u8Channel))); +} + +/** + * @brief Get Channel fast message FIFO overflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel fast message FIFO is overflow + */ +LOCAL_INLINE bool SENT_HWA_GetFastMessageFIFOOverflowFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_OVFL_UDFL_STAT_FIFO_F_OVFL_FLAG((uint32_t)1u << u8Channel) == (pSent->OVFL_UDFL_STAT & SENT_OVFL_UDFL_STAT_FIFO_F_OVFL_FLAG((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel fast message FIFO overflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearFastMessageFIFOOverflowFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->OVFL_UDFL_STAT = SENT_OVFL_UDFL_STAT_FIFO_F_OVFL_FLAG((uint32_t)1u << u8Channel); +} + +/** + * @brief Get Channel fast message DMA underflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel fast message DMA read is underflow + */ +LOCAL_INLINE bool SENT_HWA_GetFastMessageDMAUnderflowFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_OVFL_UDFL_STAT_DMA_F_UDFL_FLAG((uint32_t)1u << u8Channel) == (pSent->OVFL_UDFL_STAT & SENT_OVFL_UDFL_STAT_DMA_F_UDFL_FLAG((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel fast message DMA underflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearFastMessageDMAUnderflowFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->OVFL_UDFL_STAT = SENT_OVFL_UDFL_STAT_DMA_F_UDFL_FLAG((uint32_t)1u << u8Channel); +} + +/** + * @brief Set SENT channel nibble data mode + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param eMode the nibble data mode + */ +LOCAL_INLINE void SENT_HWA_SetChannelNibbleDataMode(SENT_Type *const pSent, uint8_t u8Channel, SENT_NibbleDataModeType eMode) +{ + pSent->NB_MODE1 = (pSent->NB_MODE1 & ~(SENT_NB_MODE1_CH0_NB_MODE_MASK >> (4u * u8Channel))) | (SENT_NB_MODE1_CH0_NB_MODE(eMode) >> (4u * u8Channel)); +} + +/** + * @brief Enable SENT channel fast message DMA request + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageDmaRequest(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FDMA_CTL |= SENT_FDMA_CTL_FDMA_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel fast message DMA request + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageDmaRequest(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FDMA_CTL &= ~SENT_FDMA_CTL_FDMA_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel slow message DMA request + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSlowMessageDmaRequest(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SDMA_CTL |= SENT_SDMA_CTL_SDMA_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel slow message DMA request + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSlowMessageDmaRequest(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SDMA_CTL &= ~SENT_SDMA_CTL_SDMA_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel Fast message interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FINT_CTL |= SENT_FINT_CTL_FINT_CTL((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel Fast message interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FINT_CTL &= ~SENT_FINT_CTL_FINT_CTL((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel slow message interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSlowMessageInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SINT_CTL |= SENT_SINT_CTL_SINT_CTL((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel slow message interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSlowMessageInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SINT_CTL &= ~SENT_SINT_CTL_SINT_CTL((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel Compensate + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCompensate(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CLK_CTL |= SENT_CHN_CLK_CTL_COMP_EN_MASK; +} + +/** + * @brief Disable SENT channel Compensate + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelCompensate(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CLK_CTL &= ~SENT_CHN_CLK_CTL_COMP_EN_MASK; +} + +/** + * @brief Set SENT channel pre-scaler + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u16PreScaler the related Channel Prescaler value + */ +LOCAL_INLINE void SENT_HWA_SetChannelPreScaler(SENT_Type *const pSent, uint8_t u8Channel, uint16_t u16PreScaler) +{ + pSent->SENT_CHN[u8Channel].CHN_CLK_CTL = (pSent->SENT_CHN[u8Channel].CHN_CLK_CTL & ~SENT_CHN_CLK_CTL_PRE_SCALER_MASK) | SENT_CHN_CLK_CTL_PRE_SCALER(u16PreScaler); +} + +/** + * @brief Get Channel Prescaler value after compensate + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return uint8_t the related Channel Prescaler value after compensate + */ +LOCAL_INLINE uint16_t SENT_HWA_GetChannelCompensatePreScaler(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint16_t)((pSent->SENT_CHN[u8Channel].CHN_CLK_CTL & SENT_CHN_CLK_CTL_COMPED_PRE_SCALER_MASK) >> SENT_CHN_CLK_CTL_COMPED_PRE_SCALER_SHIFT); +} + +/** + * @brief Get Channel status + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return uint32_t the related Channel status + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChannelStatus(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return pSent->SENT_CHN[u8Channel].CHN_STAT; +} + +/** + * @brief Clear Channel status + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u32W1CBit the status bits need to be clear. + */ +LOCAL_INLINE void SENT_HWA_ClearChannelStatus(SENT_Type *const pSent, uint8_t u8Channel, uint32_t u32W1CBit) +{ + pSent->SENT_CHN[u8Channel].CHN_STAT = u32W1CBit; +} + +/** + * @brief Enable SENT channel all error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelAllErrorInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= (SENT_CHN_CTL_CAL_RESYNC_IE_MASK | SENT_CHN_CTL_CAL_20_25_IE_MASK | SENT_CHN_CTL_SMSG_OVFL_IE_MASK | \ + SENT_CHN_CTL_FMSG_OVFL_IE_MASK | SENT_CHN_CTL_PP_DIAG_ERR_IE_MASK | SENT_CHN_CTL_CAL_DIAG_ERR_IE_MASK | \ + SENT_CHN_CTL_CAL_ERR_IE_MASK | SENT_CHN_CTL_NIB_ERR_IE_MASK | SENT_CHN_CTL_S_CRC_ERR_IE_MASK | \ + SENT_CHN_CTL_F_CRC_ERR_IE_MASK | SENT_CHN_CTL_EDGE_ERR_IE_MASK); +} + +/** + * @brief Disable SENT channel all error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelAllErrorInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~(SENT_CHN_CTL_CAL_RESYNC_IE_MASK | SENT_CHN_CTL_CAL_20_25_IE_MASK | SENT_CHN_CTL_SMSG_OVFL_IE_MASK | \ + SENT_CHN_CTL_FMSG_OVFL_IE_MASK | SENT_CHN_CTL_PP_DIAG_ERR_IE_MASK | SENT_CHN_CTL_CAL_DIAG_ERR_IE_MASK | \ + SENT_CHN_CTL_CAL_ERR_IE_MASK | SENT_CHN_CTL_NIB_ERR_IE_MASK | SENT_CHN_CTL_S_CRC_ERR_IE_MASK | \ + SENT_CHN_CTL_F_CRC_ERR_IE_MASK | SENT_CHN_CTL_EDGE_ERR_IE_MASK); +} + +/** + * @brief Enable/disable SENT channel idle flag interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelBusIdleInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_BUS_IDLE_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_BUS_IDLE_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel sync/calibration pulse error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalResyncInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_RESYNC_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_RESYNC_IE_MASK; + } +} + +/** + * @brief Enable/disable Sync/calibration pulse difference eceed 1.5625% error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalERRInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Calibration 20% pass 25% fail interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalFailInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_20_25_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_20_25_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Slow message overflow interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSOVFLInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_SMSG_OVFL_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_SMSG_OVFL_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel fast message overflow interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFOVFLInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_FMSG_OVFL_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_FMSG_OVFL_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Nibble value error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelNibbleErrorInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_NIB_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_NIB_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Previous pulse diagnosis error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelPPDiagInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_PP_DIAG_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_PP_DIAG_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Calibration diagnosis over 25% error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCALDiagInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_DIAG_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_DIAG_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Fast message CRC check error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFCRCInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_F_CRC_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_F_CRC_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel slow message CRC check error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSCRCInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_S_CRC_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_S_CRC_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Falling edge number error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelEdgeERRInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_EDGE_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_EDGE_ERR_IE_MASK; + } +} + +/** + * @brief Enable SENT channel Alternative 4-bit CRC algorithm + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelAltCRC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_ALT_4BIT_CRC_MASK; +} + +/** + * @brief Disable SENT channel Alternative 4-bit CRC algorithm + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelAltCRC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_ALT_4BIT_CRC_MASK; +} + +/** + * @brief Enable SENT channel Fast message data change + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageDataChange(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_DATA_CHANGE_EN_MASK; +} + +/** + * @brief Disable SENT channel Fast message data change + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageDataChange(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_DATA_CHANGE_EN_MASK; +} + +/** + * @brief Enable SENT channel calibration valid range from 20% tp 25% + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalValid20To25(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_SEL_MASK; +} + +/** + * @brief Disable SENT channel calibration valid range from 20% tp 25% + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelCalValid20To25(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_SEL_MASK; +} + +/** + * @brief Enable SENT channel calibration valid diagnostic + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalValidDiagnostic(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_PP_CHK_DIS_MASK; +} + +/** + * @brief Disable SENT channel calibration valid diagnostic + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelCalValidDiagnostic(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_PP_CHK_DIS_MASK; +} + +/** + * @brief Enable SENT channel fast message CRC with Augmentation + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageAugmentation(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_FCRC_SEL_MASK; +} + +/** + * @brief Disable SENT channel fast message CRC with Augmentation + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageAugmentation(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_FCRC_SEL_MASK; +} + +/** + * @brief Enable SENT channel Fast message crc with S&C + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageCRCWithSC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_FCRC_SC_EN_MASK; +} + +/** + * @brief Disable SENT channel Fast message crc with S&C + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageCRCWithSC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_FCRC_SC_EN_MASK; +} + +/** + * @brief Enable SENT channel slow message CRC with Augmentation + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSlowMessageAugmentation(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_SCRC_SEL_MASK; +} + +/** + * @brief Disable SENT channel slow message CRC with Augmentation + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSlowMessageAugmentation(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_SCRC_SEL_MASK; +} + +/** + * @brief Enable SENT channel Pause pulse + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelPausePulse(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_PAUSE_DET_EN_MASK; +} + +/** + * @brief Disable SENT channel Successive calibration pulses diagnostic option1 + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelPausePulse(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_PAUSE_DET_EN_MASK; +} + +/** + * @brief Enable SENT channel Successive calibration pulses diagnostic option1 + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSPCOption1(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_SCP_CHK_MASK; +} + +/** + * @brief Disable SENT channel Pause pulse + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSPCOption1(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_SCP_CHK_MASK; +} + +/** + * @brief Enable SENT channel Fast message crc check + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageCRCCheck(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_FMSG_CRC_CHECK_OFF_MASK; +} + +/** + * @brief Disable SENT channel Fast message crc check + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageCRCCheck(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_FMSG_CRC_CHECK_OFF_MASK; +} + +/** + * @brief Set SENT channel digital filter count + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u8Count the count of channel digital filter + */ +LOCAL_INLINE void SENT_HWA_SetChannelDigitalFilterCount(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Count) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL = (pSent->SENT_CHN[u8Channel].CHN_CTL & ~SENT_CHN_CTL_FILT_CNT_MASK) | SENT_CHN_CTL_FILT_CNT(u8Count); +} + +/** + * @brief Get Channel fast message data nibble + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the corresponding channel data nibble value + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChannelDataNibble(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return pSent->SENT_CHN[u8Channel].CHN_FDATA; +} + +/** + * @brief Get Channel fast message crc nibble + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel crc nibble value + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelFastMessageCRCNibble(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_FCRC & SENT_CHN_FCRC_CRC_DATA_MASK) >> SENT_CHN_FCRC_CRC_DATA_SHIFT); +} + +/** + * @brief Get Channel fast message status communication nibble + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel status communication nibble value + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelFastMessageStatusNibble(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_FCRC & SENT_CHN_FCRC_SC_NB_MASK) >> SENT_CHN_FCRC_SC_NB_SHIFT); +} + +/** + * @brief Get Channel fast message status timestamp + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the corresponding channel timestamp value + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChannelFastMessageTimeStamp(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return ((pSent->SENT_CHN[u8Channel].CHN_FTS & SENT_CHN_FTS_TIMESTAMP_VAL_MASK) >> SENT_CHN_FTS_TIMESTAMP_VAL_SHIFT); +} + +/** + * @brief Get Channel slow message type + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return SENT_SlowMessageType the corresponding channel slow message type + */ +LOCAL_INLINE SENT_SlowMessageType SENT_HWA_GetChannelSLowMessageType(const SENT_Type *const pSent, uint8_t u8Channel) +{ + SENT_SlowMessageType eRet = SENT_SLOW_MESSAGE_SHORT; + + if(SENT_CHN_SBIT3__MSG_TYPE_MASK == (pSent->SENT_CHN[u8Channel].CHN_SBIT3 & SENT_CHN_SBIT3__MSG_TYPE_MASK)) + { + if(SENT_CHN_SBIT3__CFG_MASK == (pSent->SENT_CHN[u8Channel].CHN_SBIT3 & SENT_CHN_SBIT3__CFG_MASK)) + { + eRet = SENT_SLOW_MESSAGE_ENHANCE_16DATA_4ID; + } + else + { + eRet = SENT_SLOW_MESSAGE_ENHANCE_12DATA_8ID; + } + } + else + { + //do nothing + } + return eRet; +} + +/** + * @brief Get Channel enhanced serial message id bit 7 to bit4 or id bit 3 to id bit 0 + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel enhanced serial message id bit 7 to bit4 or id bit 3 to id bit 0 + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelBit3EnhancedID7_4_OR_ID3_0(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_SBIT3 & SENT_CHN_SBIT3__ID7_4_OR_ID3_0_MASK) >> SENT_CHN_SBIT3__ID7_4_OR_ID3_0_SHIFT); +} + +/** + * @brief Get Channel enhanced serial message id bit 3 to bit0 or data bit 15 to id bit 12 + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel enhanced serial message id bit 3 to bit0 or data bit 15 to id bit 12 + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelBit3EnhancedID3_0_OR_DATA15_12(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_SBIT3 & SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_MASK) >> SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_SHIFT); +} + +/** + * @brief Get Channel slow message bit2 with CRC + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel slow message CRC value + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelBit2CRC(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_SBIT2 & SENT_CHN_SBIT2__SMSG_CRC_MASK) >> SENT_CHN_SBIT2__SMSG_CRC_SHIFT); +} + +/** + * @brief Get Channel slow message bit2 with DATA + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint16_t the corresponding channel slow message DATA value + */ +LOCAL_INLINE uint16_t SENT_HWA_GetChannelBit2DATA(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint16_t)((pSent->SENT_CHN[u8Channel].CHN_SBIT2 & SENT_CHN_SBIT2__SMSG_DATA_MASK) >> SENT_CHN_SBIT2__SMSG_DATA_SHIFT); +} + +/** + * @brief Get Channel slow message status timestamp + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the corresponding channel timestamp value + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChannelSlowMessageTimeStamp(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return ((pSent->SENT_CHN[u8Channel].CHN_STS & SENT_CHN_STS_SMSG_TIMESTAMP_MASK) >> SENT_CHN_STS_SMSG_TIMESTAMP_SHIFT); +} + +/** + * @brief Get Channel number of received frames + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the number of received frames + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChanneReceivedFrameNumber(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return ((pSent->SENT_CHN[u8Channel].CHN_MCNT & SENT_CHN_MCNT_FRAME_CNT_MASK) >> SENT_CHN_MCNT_FRAME_CNT_SHIFT); +} + +/** + * @brief Get Channel number of received edges + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the number of received edges + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChanneReceivedEdgeNumber(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return ((pSent->SENT_CHN[u8Channel].CHN_MCNT & SENT_CHN_MCNT_EDGE_CNT_MASK) >> SENT_CHN_MCNT_EDGE_CNT_SHIFT); +} + +/** + * @brief Clear the number of received frames + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearChannelReceivedFrameNumber(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_MCNT |= SENT_CHN_MCNT_FRAME_CNT_CLR_MASK; +} + +/** + * @brief Clear the number of received edges + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearChannelReceivedEdgeNumber(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_MCNT |= SENT_CHN_MCNT_EDGE_CNT_CLR_MASK; +} + +/** + * @brief Enable SENT channel SPC mode + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSPCMode(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL |= SENT_CHN_SPC_CTL_SPC_ENABLE_MASK; +} + +/** + * @brief Disable SENT channel SPC mode + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSPCMode(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL &= ~SENT_CHN_SPC_CTL_SPC_ENABLE_MASK; +} + +/** + * @brief Enable SENT channel calibration diagnosis in SPC mod + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalibrationDiag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL &= ~SENT_CHN_SPC_CTL_CAL_DIAG_DIS_MASK; +} + +/** + * @brief Disable SENT channel calibration diagnosis in SPC mod + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelCalibrationDiag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL |= SENT_CHN_SPC_CTL_CAL_DIAG_DIS_MASK; +} + + +/** + * @brief Set the SPC pulse trigger method + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param eTrigger the SPC pulse trigger method + */ +LOCAL_INLINE void SENT_HWA_SetChannelSPCTriggerMethod(SENT_Type *const pSent, uint8_t u8Channel, SENT_SPCTriggerType eTrigger) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL = (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & ~SENT_CHN_SPC_CTL_SPC_MODE_MASK) | SENT_CHN_SPC_CTL_SPC_MODE(eTrigger); +} + +/** + * @brief Set the delay between SPC-trigger assert and finally generate a SPC pulse + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param eTrigger the delay value + */ +LOCAL_INLINE void SENT_HWA_SetChannelSPCPulseDelay(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Delay) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL = (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & ~SENT_CHN_SPC_CTL_SPC_PULSE_DELAY_MASK) | SENT_CHN_SPC_CTL_SPC_PULSE_DELAY(u8Delay); +} + +/** + * @brief Set the delay between SPC-trigger assert and finally generate a SPC pulse + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param eTick the selected tick base of SPC + */ +LOCAL_INLINE void SENT_HWA_SetChannelSPCTickBase(SENT_Type *const pSent, uint8_t u8Channel, SENT_SPCTickType eTick) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL = (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & ~SENT_CHN_SPC_CTL_SPC_TICK_BASE_MASK) | SENT_CHN_SPC_CTL_SPC_TICK_BASE(eTick); +} + +/** + * @brief trigger the SENT to generate a SPC pulse by software + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_StartChannelSPC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL |= SENT_CHN_SPC_CTL_SPC_START_MASK; +} + +/** + * @brief Set the width of the SPC pulse. + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u8Width the width of the SPC pulse. + */ +LOCAL_INLINE void SENT_HWA_SetChannelSPCPulseWidth(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Width) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL = (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & ~SENT_CHN_SPC_CTL_SPC_PULSE_WIDTH_MASK) | SENT_CHN_SPC_CTL_SPC_PULSE_WIDTH(u8Width); +} + +/** + * @brief Set the idle count determines how long the bus idle flag will assert when bus is idle + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u8Count the idle count + */ +LOCAL_INLINE void SENT_HWA_SetChannelIdleCount(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Count) +{ + pSent->SENT_CHN[u8Channel].CHN_IDLE_CTL = (pSent->SENT_CHN[u8Channel].CHN_IDLE_CTL & ~SENT_CHN_IDLE_CTL_IDLE_CNT_MASK) | SENT_CHN_IDLE_CTL_IDLE_CNT(u8Count); +} + +/** + * @brief Get the flag indicating the spc is busy + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return bool the flag indicating the spc is busy + */ +LOCAL_INLINE bool SENT_HWA_GetChanneSPCBusyFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_CHN_SPC_CTL_SPC_BUSY_MASK == (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & SENT_CHN_SPC_CTL_SPC_BUSY_MASK)) + { + return true; + } + else + { + return false; + } +} + +/** @}*/ + +#endif /* #if SENT_INSTANCE_COUNT > 0U */ + +#endif /* _HWA_SENT_H_ */ diff --git a/Inc/HwA_smc.h b/Inc/HwA_smc.h new file mode 100644 index 0000000..49b4346 --- /dev/null +++ b/Inc/HwA_smc.h @@ -0,0 +1,1502 @@ +/** + * @file HwA_smc.h + * @author Flagchip + * @brief SMC hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + * 2.1.0 2024-11-28 Flagchip0122 N/A Add features for FC7300DQ + ******************************************************************************** */ + +#ifndef _HWA_SMC_H_ +#define _HWA_SMC_H_ + +#include "device_header.h" + +#if SMC_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_smc + * @ingroup module_driver_smc + * @{ + */ + +/********* Local typedef ************/ +/** @brief SMC stop mode control */ +typedef enum +{ + SMC_STOP_MODE = 0U, + SMC_STANDBY_MODE = 4U +} SMC_LpwModeCtrlType; + +/** @brief SMC standby mode */ +typedef enum +{ + SMC_CFG_STANDBY_0 = 0U, + SMC_CFG_STANDBY_1 = 1U, + SMC_CFG_STANDBY_2 = 2U, + SMC_CFG_STANDBY_3 = 3U +} SMC_StandbyModeType; + +#if SMC_CLOCKCONFIG_SUPPORT +/** + * @brief SMC clock out source type + * + */ +typedef enum +{ + SMC_CLKOUT_SCG_CLKOUT = 0U, /*!< SCG CLKOUT */ + SMC_CLKOUT_FOSC_DIVM_CLK = 2U, /*!< FOSC DIVM CLK */ + SMC_CLKOUT_SLOW_CLK = 3U, /*!< SLOW CLK */ + SMC_CLKOUT_SIRC_DIVM_CLK = 4U, /*!< SIRC DIVM CLK */ + SMC_CLKOUT_PLL1_DIVM_CLK = 5U, /*!< PLL1 DIVM CLK */ + SMC_CLKOUT_FIRC_DIVM_CLK = 6U, /*!< FIRC DIVM CLK */ + SMC_CLKOUT_CORE_CLK = 7U, /*!< CORE CLK */ + SMC_CLKOUT_PLL0_DIVM_CLK = 8U, /*!< PLL0 DIVM CLK */ + SMC_CLKOUT_BUS_CLK = 9U, /*!< BUS CLK */ + SMC_CLKOUT_SIRC_128K_CLK = 10U, /*!< SIRC 128K CLK */ + SMC_CLKOUT_AON_CLK = 12U, /*!< AON CLK */ + SMC_CLKOUT_RTC_CLK = 14U /*!< AON32K CLK */ +} SMC_ClockOutSrcType; + +/** + * @brief SMC clock out divide ratio type + * + */ +typedef enum +{ + SMC_CLKOUT_DIV_BY1 = 0U, /*!< Divided by 1 */ + SMC_CLKOUT_DIV_BY2 = 1U, /*!< Divided by 2 */ + SMC_CLKOUT_DIV_BY3 = 2U, /*!< Divided by 3 */ + SMC_CLKOUT_DIV_BY4 = 3U, /*!< Divided by 4 */ + SMC_CLKOUT_DIV_BY5 = 4U, /*!< Divided by 5 */ + SMC_CLKOUT_DIV_BY6 = 5U, /*!< Divided by 6 */ + SMC_CLKOUT_DIV_BY7 = 6U, /*!< Divided by 7 */ + SMC_CLKOUT_DIV_BY8 = 7U /*!< Divided by 8 */ +} SMC_ClockOutDivType; + +/** + * @brief Data type for SMC_AONCLKSR[32KAONCLKSR], set AON32KCLK source clock + * + */ +typedef enum +{ + SMC_AON32K_SIRCDIV_32K_CLK = 1U, /*!< SMC_AONCLKSR[32KAONCLKSR], SIRCDIV_32K */ + SMC_AON32K_SOSC32K_CLK = 2U, /*!< SMC_AONCLKSR[32KAONCLKSR], SOSC32K */ + SMC_AON32K_SIRC32K_CLK = 3U /*!< SMC_AONCLKSR[32KAONCLKSR], SIRC32K */ +} SMC_AON32KClkSrcType; + +/** + * @brief Data type for SMC_RTCCLKSEL[RTCCLKSEL], set RTCCLK source clock + * + */ +typedef enum +{ + SMC_RTC_FOSCDIVL_CLK = 0U, /*!< SMC_RTCCLKSEL[RTCCLKSEL], FOSC_DIVL */ + SMC_RTC_SIRCDIV_32K_CLK = 1U, /*!< SMC_RTCCLKSEL[RTCCLKSEL], SIRC_DIV */ + SMC_RTC_SOSC_CLK = 2U, /*!< SMC_RTCCLKSEL[RTCCLKSEL], SOSC */ + SMC_RTC_SIRC32K_CLK = 3U /*!< SMC_RTCCLKSEL[RTCCLKSEL], SIRC_32K */ +} SMC_RTCClkSrcType; + +/** + * @brief Data type for SMC_AONCLKSR[AONCLKSR], set AONCLK source clock + * + */ +typedef enum +{ + SMC_AON_SIRCDIV_128K_CLK = 0U, /*!< SMC_AONCLKSR[AONCLKSR], SIRCDIV_128K */ + SMC_AON_SIRC32K_CLK = 1U, /*!< SMC_AONCLKSR[AONCLKSR], SIRC32K */ + SMC_AON_SIRCDIV_32K_CLK = 2U, /*!< SMC_AONCLKSR[AONCLKSR], SIRCDIV_32K */ + SMC_AON_SIRC32_1K_CLK = 3U /*!< SMC_AONCLKSR[AONCLKSR], SIRC32_1K */ +} SMC_AONClkSrcType; +#endif + +/********* Local inline function ************/ +/** + * @brief Clear stop mode control value + * + */ +LOCAL_INLINE void SMC_HWA_ClearStopModeCtrl(void) +{ + SMC->PMCTRL &= ~(uint32_t)SMC_PMCTRL_STOP_MODE_MASK; +} + +/** + * @brief Set stop mode control + * + * @param eMode Stop mode control type + */ +LOCAL_INLINE void SMC_HWA_SetStopModeCtrl(SMC_LpwModeCtrlType eMode) +{ + SMC->PMCTRL = (uint32_t)eMode; +} + +/** + * @brief Clear standby mode + * + */ +LOCAL_INLINE void SMC_HWA_ClearStandbyMode(void) +{ + SMC->STANDBY_CFG &= ~(uint32_t)SMC_STANDBY_CFG_OPTION_MASK; +} + +/** + * @brief Set standby mode + * + * @param eMode Standby mode type + */ +LOCAL_INLINE void SMC_HWA_SetStandbyMode(SMC_StandbyModeType eMode) +{ + SMC->STANDBY_CFG = (uint32_t)eMode; +} + +#if SMC_CLOCKCONFIG_SUPPORT + +#if SMC_TSTMP0CLOCK_CONFIG_SUPPORT +/** + * @brief Set tstmp0 clock enable + * + */ +LOCAL_INLINE void SMC_HWA_EnableTstmp0Clk(void) +{ + SMC->TSTMP0_CLK_CFG |= SMC_TSTMP0_CLK_CFG_EN_MASK; +} + +/** + * @brief Set tstmp0 clock disable + * + */ +LOCAL_INLINE void SMC_HWA_DisableTstmp0Clk(void) +{ + SMC->TSTMP0_CLK_CFG &= ~(uint32_t)SMC_TSTMP0_CLK_CFG_EN_MASK; +} + +/** + * @brief Set TSTMP0_CLK_CFG reg + * + * @param u32Data Value to set + */ +LOCAL_INLINE void SMC_HWA_SetTstmp0_CLk_CfgReg(uint32_t u32Data) +{ + SMC->TSTMP0_CLK_CFG = u32Data; +} + +/** + * @brief Get TSTMP0_CLK_CFG reg + * + * @return uint32_t Register value + */ +LOCAL_INLINE uint32_t SMC_HWA_GetTstmp0_CLk_CfgReg(void) +{ + return SMC->TSTMP0_CLK_CFG; +} + +/** + * @brief Lock TSTMP0_CLK_CFG reg + * + */ +LOCAL_INLINE void SMC_HWA_LockTstmp0_CLk_CfgReg(void) +{ + SMC->TSTMP0_CLK_CFG |= SMC_TSTMP0_CLK_CFG_LOCK_MASK; +} + +/** + * @brief Unlock TSTMP0_CLK_CFG reg + * + */ +LOCAL_INLINE void SMC_HWA_UnlockTstmp0_CLk_CfgReg(void) +{ + SMC->TSTMP0_CLK_CFG &= ~(uint32_t)SMC_TSTMP0_CLK_CFG_LOCK_MASK; +} + +#endif /* #if SMC_TSTMP0CLOCK_CONFIG_SUPPORT */ + +/** + * @brief Set PMPORT register + * + * @param u32Data set value + */ +LOCAL_INLINE void SMC_HWA_SetPmportReg(uint32_t u32Data) +{ + SMC->PMPROT = u32Data; +} + +/** + * @brief Get the value of PGCTRL_PROT. + * + * @return uint32_t the value of PGCTRL_PROT. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetPGCTRL_PROT(void) +{ + return ((SMC->PMPROT & SMC_PMPROT_PGCTRL_PROT_MASK) >> SMC_PMPROT_PGCTRL_PROT_SHIFT); +} + +/** + * @brief Set PGCTRL_PROT. + * + * @param uint32_t u32Value PGCTRL_PROT value. + */ +LOCAL_INLINE void SMC_HWA_SetPGCTRL_PROT(uint32_t u32Value) +{ + SMC->PMPROT = ((SMC->PMPROT & ~SMC_PMPROT_PGCTRL_PROT_MASK) | SMC_PMPROT_PGCTRL_PROT(u32Value)); +} + +/** + * @brief Get the value of RAMRET_PROT. + * + * @return uint32_t the value of RAMRET_PROT. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetRAMRET_PROT(void) +{ + return ((SMC->PMPROT & SMC_PMPROT_RAMRET_PROT_MASK) >> SMC_PMPROT_RAMRET_PROT_SHIFT); +} + +/** + * @brief Set RAMRET_PROT. + * + * @param uint32_t u32Value RAMRET_PROT value. + */ +LOCAL_INLINE void SMC_HWA_SetRAMRET_PROT(uint32_t u32Value) +{ + SMC->PMPROT = ((SMC->PMPROT & ~SMC_PMPROT_RAMRET_PROT_MASK) | SMC_PMPROT_RAMRET_PROT(u32Value)); +} + +/** + * @brief Get the value of IOLOCK_PROT. + * + * @return uint32_t the value of IOLOCK_PROT. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetIOLOCK_PROT(void) +{ + return ((SMC->PMPROT & SMC_PMPROT_IOLOCK_PROT_MASK) >> SMC_PMPROT_IOLOCK_PROT_SHIFT); +} + +/** + * @brief Set IOLOCK_PROT. + * + * @param uint32_t u32Value IOLOCK_PROT value. + */ +LOCAL_INLINE void SMC_HWA_SetIOLOCK_PROT(uint32_t u32Value) +{ + SMC->PMPROT = ((SMC->PMPROT & ~SMC_PMPROT_IOLOCK_PROT_MASK) | SMC_PMPROT_IOLOCK_PROT(u32Value)); +} + +/** + * @brief Get the value of WAKEUP_PROT. + * + * @return uint32_t the value of WAKEUP_PROT. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetWAKEUP_PROT(void) +{ + return ((SMC->PMPROT & SMC_PMPROT_WAKEUP_PROT_MASK) >> SMC_PMPROT_WAKEUP_PROT_SHIFT); +} + +/** + * @brief Set WAKEUP_PROT. + * + * @param uint32_t u32Value WAKEUP_PROT value. + */ +LOCAL_INLINE void SMC_HWA_SetWAKEUP_PROT(uint32_t u32Value) +{ + SMC->PMPROT = (SMC->PMPROT & ~SMC_PMPROT_WAKEUP_PROT_MASK) | SMC_PMPROT_WAKEUP_PROT(u32Value); +} + +/** + * @brief Get the value of STANDBY_CFG_PROT. + * + * @return uint32_t the value of STANDBY_CFG_PROT. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetSTANDBY_CFG_PROT(void) +{ + return ((SMC->PMPROT & SMC_PMPROT_STANDBY_CFG_PROT_MASK) >> SMC_PMPROT_STANDBY_CFG_PROT_SHIFT); +} + +/** + * @brief Set STANDBY_CFG_PROT. + * + * @param uint32_t u32Value STANDBY_CFG_PROT value. + */ +LOCAL_INLINE void SMC_HWA_SetSTANDBY_CFG_PROT(uint32_t u32Value) +{ + SMC->PMPROT = ((SMC->PMPROT & ~SMC_PMPROT_STANDBY_CFG_PROT_MASK) | SMC_PMPROT_STANDBY_CFG_PROT(u32Value)); +} + +/** + * @brief Get the value of PMCTRL_PROT. + * + * @return uint32_t the value of PMCTRL_PROT. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetPMCTRL_PROT(void) +{ + return ((SMC->PMPROT & SMC_PMPROT_PMCTRL_PROT_MASK) >> SMC_PMPROT_PMCTRL_PROT_SHIFT); +} + +/** + * @brief Set PMCTRL_PROT. + * + * @param uint32_t u32Value PMCTRL_PROT value. + */ +LOCAL_INLINE void SMC_HWA_SetPMCTRL_PROT(uint32_t u32Value) +{ + SMC->PMPROT = ((SMC->PMPROT & ~SMC_PMPROT_PMCTRL_PROT_MASK) | SMC_PMPROT_PMCTRL_PROT(u32Value)); +} + +/** + * @brief Set low power wakeup PADx configure source + * + * @param u8PadNum Low power PAD number + * @param u8PadSrc Low power PAD source + */ +LOCAL_INLINE void SMC_HWA_SetLPWakeUpPadSrc(uint8_t u8PadNum, uint8_t u8PadSrc) +{ + SMC->WAKEUP = (((SMC->WAKEUP) & (~(SMC_WAKEUP_LP_WAKEUP_CFG0_MASK >> (4U * (uint32)u8PadNum)))) | + (SMC_WAKEUP_LP_WAKEUP_CFG0(u8PadSrc) >> (4U * (uint32)u8PadNum))); +} + +/** + * @brief Set low power wakeup PADx configure source polarity + * + * @param u8PadNum Low power PAD number + * @param u8PadPolarity Low power PAD polarity + */ +LOCAL_INLINE void SMC_HWA_SetLPWakeUpPadPol(uint8_t u8PadNum, uint8_t u8PadPolarity) +{ + SMC->WAKEUP = (((SMC->WAKEUP) & (~(SMC_WAKEUP_LP_WAKEUP_POL0_MASK >> (uint32)u8PadNum))) | + (SMC_WAKEUP_LP_WAKEUP_POL0(u8PadPolarity) >> (uint32)u8PadNum)); +} + +/** + * @brief Get the value of LP_WAKEUP_CFG0. + * + * @return uint32_t the value of LP_WAKEUP_CFG0. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetLP_WAKEUP_CFG0(void) +{ + return ((SMC->WAKEUP & SMC_WAKEUP_LP_WAKEUP_CFG0_MASK) >> SMC_WAKEUP_LP_WAKEUP_CFG0_SHIFT); +} + +/** + * @brief Set LP_WAKEUP_CFG0. + * + * @param uint32_t u32Value LP_WAKEUP_CFG0 value. + */ +LOCAL_INLINE void SMC_HWA_SetLP_WAKEUP_CFG0(uint32_t u32Value) +{ + SMC->WAKEUP = ((SMC->WAKEUP & ~SMC_WAKEUP_LP_WAKEUP_CFG0_MASK) | SMC_WAKEUP_LP_WAKEUP_CFG0(u32Value)); +} + +/** + * @brief Get the value of LP_WAKEUP_CFG1. + * + * @return uint32_t the value of LP_WAKEUP_CFG1. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetLP_WAKEUP_CFG1(void) +{ + return ((SMC->WAKEUP & SMC_WAKEUP_LP_WAKEUP_CFG1_MASK) >> SMC_WAKEUP_LP_WAKEUP_CFG1_SHIFT); +} + +/** + * @brief Set LP_WAKEUP_CFG1. + * + * @param uint32_t u32Value LP_WAKEUP_CFG1 value. + */ +LOCAL_INLINE void SMC_HWA_SetLP_WAKEUP_CFG1(uint32_t u32Value) +{ + SMC->WAKEUP = ((SMC->WAKEUP & ~SMC_WAKEUP_LP_WAKEUP_CFG1_MASK) | SMC_WAKEUP_LP_WAKEUP_CFG1(u32Value)); +} + +/** + * @brief Get the value of LP_WAKEUP_CFG2. + * + * @return uint32_t the value of LP_WAKEUP_CFG2. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetLP_WAKEUP_CFG2(void) +{ + return ((SMC->WAKEUP & SMC_WAKEUP_LP_WAKEUP_CFG2_MASK) >> SMC_WAKEUP_LP_WAKEUP_CFG2_SHIFT); +} + +/** + * @brief Set LP_WAKEUP_CFG2. + * + * @param uint32_t u32Value LP_WAKEUP_CFG2 value. + */ +LOCAL_INLINE void SMC_HWA_SetLP_WAKEUP_CFG2(uint32_t u32Value) +{ + SMC->WAKEUP = ((SMC->WAKEUP & ~SMC_WAKEUP_LP_WAKEUP_CFG2_MASK) | SMC_WAKEUP_LP_WAKEUP_CFG2(u32Value)); +} + +/** + * @brief Get the value of LP_WAKEUP_CFG3. + * + * @return uint32_t the value of LP_WAKEUP_CFG3. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetLP_WAKEUP_CFG3(void) +{ + return ((SMC->WAKEUP & SMC_WAKEUP_LP_WAKEUP_CFG3_MASK) >> SMC_WAKEUP_LP_WAKEUP_CFG3_SHIFT); +} + +/** + * @brief Set LP_WAKEUP_CFG3. + * + * @param uint32_t u32Value LP_WAKEUP_CFG3 value. + */ +LOCAL_INLINE void SMC_HWA_SetLP_WAKEUP_CFG3(uint32_t u32Value) +{ + SMC->WAKEUP = ((SMC->WAKEUP & ~SMC_WAKEUP_LP_WAKEUP_CFG3_MASK) | SMC_WAKEUP_LP_WAKEUP_CFG3(u32Value)); +} + +/** + * @brief Get the value of LP_WAKEUP_CFG4. + * + * @return uint32_t the value of LP_WAKEUP_CFG4. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetLP_WAKEUP_CFG4(void) +{ + return ((SMC->WAKEUP & SMC_WAKEUP_LP_WAKEUP_CFG4_MASK) >> SMC_WAKEUP_LP_WAKEUP_CFG4_SHIFT); +} + +/** + * @brief Set LP_WAKEUP_CFG4. + * + * @param uint32_t u32Value LP_WAKEUP_CFG4 value. + */ +LOCAL_INLINE void SMC_HWA_SetLP_WAKEUP_CFG4(uint32_t u32Value) +{ + SMC->WAKEUP = ((SMC->WAKEUP & ~SMC_WAKEUP_LP_WAKEUP_CFG4_MASK) | SMC_WAKEUP_LP_WAKEUP_CFG4(u32Value)); +} + +/** + * @brief Get the value of LP_WAKEUP_POL0. + * + * @return uint32_t the value of LP_WAKEUP_POL0. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetLP_WAKEUP_POL0(void) +{ + return ((SMC->WAKEUP & SMC_WAKEUP_LP_WAKEUP_POL0_MASK) >> SMC_WAKEUP_LP_WAKEUP_POL0_SHIFT); +} + +/** + * @brief Set LP_WAKEUP_POL0. + * + * @param uint32_t u32Value LP_WAKEUP_POL0 value. + */ +LOCAL_INLINE void SMC_HWA_SetLP_WAKEUP_POL0(uint32_t u32Value) +{ + SMC->WAKEUP = ((SMC->WAKEUP & ~SMC_WAKEUP_LP_WAKEUP_POL0_MASK) | SMC_WAKEUP_LP_WAKEUP_POL0(u32Value)); +} + +/** + * @brief Get the value of LP_WAKEUP_POL1. + * + * @return uint32_t the value of LP_WAKEUP_POL1. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetLP_WAKEUP_POL1(void) +{ + return ((SMC->WAKEUP & SMC_WAKEUP_LP_WAKEUP_POL1_MASK) >> SMC_WAKEUP_LP_WAKEUP_POL1_SHIFT); +} + +/** + * @brief Set LP_WAKEUP_POL1. + * + * @param uint32_t u32Value LP_WAKEUP_POL1 value. + */ +LOCAL_INLINE void SMC_HWA_SetLP_WAKEUP_POL1(uint32_t u32Value) +{ + SMC->WAKEUP = ((SMC->WAKEUP & ~SMC_WAKEUP_LP_WAKEUP_POL1_MASK) | SMC_WAKEUP_LP_WAKEUP_POL1(u32Value)); +} + +/** + * @brief Get the value of LP_WAKEUP_POL2. + * + * @return uint32_t the value of LP_WAKEUP_POL2. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetLP_WAKEUP_POL2(void) +{ + return ((SMC->WAKEUP & SMC_WAKEUP_LP_WAKEUP_POL2_MASK) >> SMC_WAKEUP_LP_WAKEUP_POL2_SHIFT); +} + +/** + * @brief Set LP_WAKEUP_POL2. + * + * @param uint32_t u32Value LP_WAKEUP_POL2 value. + */ +LOCAL_INLINE void SMC_HWA_SetLP_WAKEUP_POL2(uint32_t u32Value) +{ + SMC->WAKEUP = ((SMC->WAKEUP & ~SMC_WAKEUP_LP_WAKEUP_POL2_MASK) | SMC_WAKEUP_LP_WAKEUP_POL2(u32Value)); +} + +/** + * @brief Get the value of LP_WAKEUP_POL3. + * + * @return uint32_t the value of LP_WAKEUP_POL3. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetLP_WAKEUP_POL3(void) +{ + return ((SMC->WAKEUP & SMC_WAKEUP_LP_WAKEUP_POL3_MASK) >> SMC_WAKEUP_LP_WAKEUP_POL3_SHIFT); +} + +/** + * @brief Set LP_WAKEUP_POL3. + * + * @param uint32_t u32Value LP_WAKEUP_POL3 value. + */ +LOCAL_INLINE void SMC_HWA_SetLP_WAKEUP_POL3(uint32_t u32Value) +{ + SMC->WAKEUP = ((SMC->WAKEUP & ~SMC_WAKEUP_LP_WAKEUP_POL3_MASK) | SMC_WAKEUP_LP_WAKEUP_POL3(u32Value)); +} + +/** + * @brief Get the value of LP_WAKEUP_POL4. + * + * @return uint32_t the value of LP_WAKEUP_POL4. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetLP_WAKEUP_POL4(void) +{ + return ((SMC->WAKEUP & SMC_WAKEUP_LP_WAKEUP_POL4_MASK) >> SMC_WAKEUP_LP_WAKEUP_POL4_SHIFT); +} + +/** + * @brief Set LP_WAKEUP_POL4. + * + * @param uint32_t u32Value LP_WAKEUP_POL4 value. + */ +LOCAL_INLINE void SMC_HWA_SetLP_WAKEUP_POL4(uint32_t u32Value) +{ + SMC->WAKEUP = ((SMC->WAKEUP & ~SMC_WAKEUP_LP_WAKEUP_POL4_MASK) | SMC_WAKEUP_LP_WAKEUP_POL4(u32Value)); +} + +/** + * @brief Get IOLOCK register + * + * @return uint32 register value + */ +LOCAL_INLINE uint32 SMC_HWA_GetIolockReg(void) +{ + return SMC->IOLOCK; +} + +/** + * @brief Set IOLOCK register + * + * @param u32Data set value + */ +LOCAL_INLINE void SMC_HWA_SetIolockReg(uint32_t u32Data) +{ + SMC->IOLOCK = u32Data; +} + +/** + * @brief Get the value of IOLOCK_CTRL0. + * + * @return uint32_t the value of IOLOCK_CTRL0. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetIOLOCK_CTRL0(void) +{ + return ((SMC->IOLOCK & SMC_IOLOCK_IOLOCK_CTRL0_MASK) >> SMC_IOLOCK_IOLOCK_CTRL0_SHIFT); +} + +/** + * @brief Set IOLOCK_CTRL0. + * + * @param uint32_t u8Value IOLOCK_CTRL0 value. + */ +LOCAL_INLINE void SMC_HWA_SetIOLOCK_CTRL0(uint32_t u8Value) +{ + SMC->IOLOCK = ((SMC->IOLOCK & ~SMC_IOLOCK_IOLOCK_CTRL0_MASK) | SMC_IOLOCK_IOLOCK_CTRL0(u8Value)); +} + +/** + * @brief Get the value of IOLOCK_CTRL1. + * + * @return uint32_t the value of IOLOCK_CTRL1. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetIOLOCK_CTRL1(void) +{ + return ((SMC->IOLOCK & SMC_IOLOCK_IOLOCK_CTRL1_MASK) >> SMC_IOLOCK_IOLOCK_CTRL1_SHIFT); +} + +/** + * @brief Set IOLOCK_CTRL1. + * + * @param uint32_t u8Value IOLOCK_CTRL1 value. + */ +LOCAL_INLINE void SMC_HWA_SetIOLOCK_CTRL1(uint32_t u8Value) +{ + SMC->IOLOCK = ((SMC->IOLOCK & ~SMC_IOLOCK_IOLOCK_CTRL1_MASK) | SMC_IOLOCK_IOLOCK_CTRL1(u8Value)); +} + +/** + * @brief Get the value of IOLOCK_CTRL2. + * + * @return uint32_t the value of IOLOCK_CTRL2. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetIOLOCK_CTRL2(void) +{ + return ((SMC->IOLOCK & SMC_IOLOCK_IOLOCK_CTRL2_MASK) >> SMC_IOLOCK_IOLOCK_CTRL2_SHIFT); +} + +/** + * @brief Set IOLOCK_CTRL2. + * + * @param uint32_t u32Value IOLOCK_CTRL2 value. + */ +LOCAL_INLINE void SMC_HWA_SetIOLOCK_CTRL2(uint32_t u32Value) +{ + SMC->IOLOCK = ((SMC->IOLOCK & ~SMC_IOLOCK_IOLOCK_CTRL2_MASK) | SMC_IOLOCK_IOLOCK_CTRL2(u32Value)); +} + +/** + * @brief Get the value of IOLOCK_CTRL3. + * + * @return uint32_t the value of IOLOCK_CTRL3. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetIOLOCK_CTRL3(void) +{ + return ((SMC->IOLOCK & SMC_IOLOCK_IOLOCK_CTRL3_MASK) >> SMC_IOLOCK_IOLOCK_CTRL3_SHIFT); +} + +/** + * @brief Set IOLOCK_CTRL3. + * + * @param uint32_t u32Value IOLOCK_CTRL3 value. + */ +LOCAL_INLINE void SMC_HWA_SetIOLOCK_CTRL3(uint32_t u32Value) +{ + SMC->IOLOCK = ((SMC->IOLOCK & ~SMC_IOLOCK_IOLOCK_CTRL3_MASK) | SMC_IOLOCK_IOLOCK_CTRL3(u32Value)); +} + +/** + * @brief Get the value of IOLOCK_CTRL4. + * + * @return uint32_t the value of IOLOCK_CTRL4. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetIOLOCK_CTRL4(void) +{ + return ((SMC->IOLOCK & SMC_IOLOCK_IOLOCK_CTRL4_MASK) >> SMC_IOLOCK_IOLOCK_CTRL4_SHIFT); +} + +/** + * @brief Set IOLOCK_CTRL4. + * + * @param uint32_t u32Value IOLOCK_CTRL4 value. + */ +LOCAL_INLINE void SMC_HWA_SetIOLOCK_CTRL4(uint32_t u32Value) +{ + SMC->IOLOCK = ((SMC->IOLOCK & ~SMC_IOLOCK_IOLOCK_CTRL4_MASK) | SMC_IOLOCK_IOLOCK_CTRL4(u32Value)); +} + +/** + * @brief Get the value of RETEN. + * + * @return uint16_t the value of RETEN. + */ +LOCAL_INLINE uint16_t SMC_HWA_GetRETEN(void) +{ + return ((SMC->RAMRET & SMC_RAMRET_RETEN_MASK) >> SMC_RAMRET_RETEN_SHIFT); +} + +/** + * @brief Set RETEN. + * + * @param uint16_t u16Value RETEN value. + */ +LOCAL_INLINE void SMC_HWA_SetRETEN(uint16_t u16Value) +{ + SMC->RAMRET = ((SMC->RAMRET & ~SMC_RAMRET_RETEN_MASK) | SMC_RAMRET_RETEN(u16Value)); +} + +/** + * @brief Set PGCTRL register + * + * @param u32Data set value + */ +LOCAL_INLINE void SMC_HWA_SetPgctrlReg(uint32_t u32Data) +{ + SMC->PGCTRL = u32Data; +} + +/** + * @brief Get the value of PG_LOCK_EN. + * + * @return uint32_t the value of PG_LOCK_EN. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetPG_LOCK_EN(void) +{ + return ((SMC->PGCTRL & SMC_PGCTRL_PG_LOCK_EN_MASK) >> SMC_PGCTRL_PG_LOCK_EN_SHIFT); +} + +/** + * @brief Set PG_LOCK_EN. + * + * @param uint32_t u32Value PG_LOCK_EN value. + */ +LOCAL_INLINE void SMC_HWA_SetPG_LOCK_EN(uint32_t u32Value) +{ + SMC->PGCTRL = ((SMC->PGCTRL & ~SMC_PGCTRL_PG_LOCK_EN_MASK) | SMC_PGCTRL_PG_LOCK_EN(u32Value)); +} + +/** + * @brief Get the value of PG_LOCK_SEL. + * + * @return uint32_t the value of PG_LOCK_SEL. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetPG_LOCK_SEL(void) +{ + return ((SMC->PGCTRL & SMC_PGCTRL_PG_LOCK_SEL_MASK) >> SMC_PGCTRL_PG_LOCK_SEL_SHIFT); +} + +/** + * @brief Set PG_LOCK_SEL. + * + * @param uint32_t u32Value PG_LOCK_SEL value. + */ +LOCAL_INLINE void SMC_HWA_SetPG_LOCK_SEL(uint32_t u32Value) +{ + SMC->PGCTRL = ((SMC->PGCTRL & ~SMC_PGCTRL_PG_LOCK_SEL_MASK) | SMC_PGCTRL_PG_LOCK_SEL(u32Value)); +} + +/** + * @brief Get the value of PG_POL. + * + * @return uint32_t the value of PG_POL. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetPG_POL(void) +{ + return ((SMC->PGCTRL & SMC_PGCTRL_PG_POL_MASK) >> SMC_PGCTRL_PG_POL_SHIFT); +} + +/** + * @brief Set PG_POL. + * + * @param uint32_t u32Value PG_POL value. + */ +LOCAL_INLINE void SMC_HWA_SetPG_POL(uint32_t u32Value) +{ + SMC->PGCTRL = ((SMC->PGCTRL & ~SMC_PGCTRL_PG_POL_MASK) | SMC_PGCTRL_PG_POL(u32Value)); +} + +/** + * @brief Get the value of PG_EN. + * + * @return uint32_t the value of PG_EN. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetPG_EN(void) +{ + return ((SMC->PGCTRL & SMC_PGCTRL_PG_EN_MASK) >> SMC_PGCTRL_PG_EN_SHIFT); +} + +/** + * @brief Set PG_EN. + * + * @param uint32_t u32Value PG_EN value. + */ +LOCAL_INLINE void SMC_HWA_SetPG_EN(uint32_t u32Value) +{ + SMC->PGCTRL = ((SMC->PGCTRL & ~SMC_PGCTRL_PG_EN_MASK) | SMC_PGCTRL_PG_EN(u32Value)); +} + +/** + * @brief Get the value of AON32KCLKSEL. + * + * @return uint32_t the value of AON32KCLKSEL. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetAON32KCLKSEL(void) +{ + return ((SMC->AONCLKSR & SMC_AONCLKSR_AON32KCLKSEL_MASK) >> SMC_AONCLKSR_AON32KCLKSEL_SHIFT); +} + +/** + * @brief Set AON32KCLKSEL. + * + * @param uint32_t u32Value AON32KCLKSEL value. + */ +LOCAL_INLINE void SMC_HWA_SetAON32KCLKSEL(uint32_t u32Value) +{ + SMC->AONCLKSR = ((SMC->AONCLKSR & ~SMC_AONCLKSR_AON32KCLKSEL_MASK) | SMC_AONCLKSR_AON32KCLKSEL(u32Value)); +} + +/** + * @brief Get the value of RTCCLKSEL. + * + * @return uint32_t the value of RTCCLKSEL. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetRTCCLKSEL(void) +{ + return ((SMC->AONCLKSR & SMC_AONCLKSR_RTCCLKSEL_MASK) >> SMC_AONCLKSR_RTCCLKSEL_SHIFT); +} + +/** + * @brief Set RTCCLKSEL. + * + * @param uint32_t u32Value RTCCLKSEL value. + */ +LOCAL_INLINE void SMC_HWA_SetRTCCLKSEL(uint32_t u32Value) +{ + SMC->AONCLKSR = ((SMC->AONCLKSR & ~SMC_AONCLKSR_RTCCLKSEL_MASK) | SMC_AONCLKSR_RTCCLKSEL(u32Value)); +} + +/** + * @brief Get the value of AONCLKSR. + * + * @return uint32_t the value of AONCLKSR. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetAONCLKSR(void) +{ + return ((SMC->AONCLKSR & SMC_AONCLKSR_AONCLKSEL_MASK) >> SMC_AONCLKSR_AONCLKSEL_SHIFT); +} + +/** + * @brief Get the value of SIRCDIV32KEN. + * + * @param SMC the base address of the SMC instance. + + * @return uint32_t the value of SIRCDIV32KEN. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetSIRCDIV32KEN(void) +{ + return ((SMC->AONCLKSR & SMC_AONCLKSR_SIRCDIV32KEN_MASK) >> SMC_AONCLKSR_SIRCDIV32KEN_SHIFT); +} + +/** + * @brief Set SIRCDIV32KEN. + * + * @param uint32_t u32Value SIRCDIV32KEN value. + */ +LOCAL_INLINE void SMC_HWA_SetSIRCDIV32KEN(uint32_t u32Value) +{ + SMC->AONCLKSR = ((SMC->AONCLKSR & ~SMC_AONCLKSR_SIRCDIV32KEN_MASK) | SMC_AONCLKSR_SIRCDIV32KEN(u32Value)); +} + +/** + * @brief Get the value of AON1KCLKEN. + * + * @return uint32_t the value of AON1KCLKEN. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetAON1KCLKEN(void) +{ + return ((SMC->AONCLKSR & SMC_AONCLKSR_AON1KCLKEN_MASK) >> SMC_AONCLKSR_AON1KCLKEN_SHIFT); +} + +/** + * @brief Set AON1KCLKEN. + * + * @param uint32_t u32Value AON1KCLKEN value. + */ +LOCAL_INLINE void SMC_HWA_SetAON1KCLKEN(uint32_t u32Value) +{ + SMC->AONCLKSR = ((SMC->AONCLKSR & ~SMC_AONCLKSR_AON1KCLKEN_MASK) | SMC_AONCLKSR_AON1KCLKEN(u32Value)); +} + +/** + * @brief Get the value of LOCK. + * + * @return uint32_t the value of LOCK. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetAONCLKSRLOCK(void) +{ + return ((SMC->AONCLKSR & SMC_AONCLKSR_LOCK_MASK) >> SMC_AONCLKSR_LOCK_SHIFT); +} + +/** + * @brief Set LOCK. + * + * @param uint32_t u32Value LOCK value. + */ +LOCAL_INLINE void SMC_HWA_SetAONCLKSRLOCK(uint32_t u32Value) +{ + SMC->AONCLKSR = ((SMC->AONCLKSR & ~SMC_AONCLKSR_LOCK_MASK) | SMC_AONCLKSR_LOCK(u32Value)); +} + +/** + * @brief Set SMC_AON32KCLK source clock + * + * @param SMC_AON32KClkSrcType SMC_AON32KCLK source type + */ +LOCAL_INLINE void SMC_HWA_SetAON32kClkSrc(SMC_AON32KClkSrcType eClkSrcType) +{ + uint32_t u32RegVal = SMC->AONCLKSR; + SMC->AONCLKSR = ((u32RegVal & (~(uint32_t)SMC_AONCLKSR_AON32KCLKSEL_MASK)) | SMC_AONCLKSR_AON32KCLKSEL(eClkSrcType)); +} + +/** + * @brief Set SMC_RTCCLK source clock + * + * @param SMC_RTCClkSrcType SMC_RTCCLK source type + */ +LOCAL_INLINE void SMC_HWA_SetRTCClkSrc(SMC_RTCClkSrcType eClkSrcType) +{ + uint32_t u32RegVal = SMC->AONCLKSR; + SMC->AONCLKSR = ((u32RegVal & (~(uint32_t)SMC_AONCLKSR_RTCCLKSEL_MASK)) | SMC_AONCLKSR_RTCCLKSEL(eClkSrcType)); +} + +/** + * @brief Set SMC_AONCLK source clock + * + * @param SMC_AONClkSrcType SMC_AONCLK source type + */ +LOCAL_INLINE void SMC_HWA_SetAONClkSrc(SMC_AONClkSrcType eClkSrcType) +{ + uint32_t u32RegVal = SMC->AONCLKSR; + SMC->AONCLKSR = ((u32RegVal & (~(uint32_t)SMC_AONCLKSR_AONCLKSEL_MASK)) | SMC_AONCLKSR_AONCLKSEL(eClkSrcType)); +} + +/** + * @brief Get AONCLKSR register status + * + * @return AONCLKSR register status + */ +LOCAL_INLINE uint32_t SMC_HWA_Get_AONCLKSR(void) +{ + return SMC->AONCLKSR; +} + +/** + * @brief Get the value of RPM_EXIT_CNT. + * + * @return uint16_t the value of RPM_EXIT_CNT. + */ +LOCAL_INLINE uint16_t SMC_HWA_GetRPM_EXIT_CNT(void) +{ + return ((SMC->PCU_CTRL & SMC_PCU_CTRL_RPM_EXIT_CNT_MASK) >> SMC_PCU_CTRL_RPM_EXIT_CNT_SHIFT); +} + +/** + * @brief Set RPM_EXIT_CNT. + * + * @param uint16_t u8Value RPM_EXIT_CNT value. + */ +LOCAL_INLINE void SMC_HWA_SetRPM_EXIT_CNT(uint16_t u16Value) +{ + SMC->PCU_CTRL = ((SMC->PCU_CTRL & ~SMC_PCU_CTRL_RPM_EXIT_CNT_MASK) | SMC_PCU_CTRL_RPM_EXIT_CNT(u16Value)); +} + +/** + * @brief Get the value of LOCK. + * + * @return uint32_t the value of LOCK. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetPCULOCK(void) +{ + return ((SMC->PCU_CTRL & SMC_PCU_CTRL_LOCK_MASK) >> SMC_PCU_CTRL_LOCK_SHIFT); +} + +/** + * @brief Set LOCK. + * + * @param uint32_t u8Value LOCK value. + */ +LOCAL_INLINE void SMC_HWA_SetPCULOCK(uint32_t u32Value) +{ + SMC->PCU_CTRL = ((SMC->PCU_CTRL & ~SMC_PCU_CTRL_LOCK_MASK) | SMC_PCU_CTRL_LOCK(u32Value)); +} + +/** + * @brief Get the value of PAD_ISO_HOLD. + * + * @return uint32_t the value of PAD_ISO_HOLD. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetPAD_ISO_HOLD(void) +{ + return ((SMC->ISO_CTRL & SMC_ISO_CTRL_PAD_ISO_HOLD_MASK) >> SMC_ISO_CTRL_PAD_ISO_HOLD_SHIFT); +} + +/** + * @brief Set PAD_ISO_HOLD. + * + * @param uint32_t u32Value PAD_ISO_HOLD value. + */ +LOCAL_INLINE void SMC_HWA_SetPAD_ISO_HOLD(uint32_t u32Value) +{ + SMC->ISO_CTRL = ((SMC->ISO_CTRL & ~SMC_ISO_CTRL_PAD_ISO_HOLD_MASK) | SMC_ISO_CTRL_PAD_ISO_HOLD(u32Value)); +} + +/** + * @brief Get the value of PAD_ISO_HOLD_CLR. + * + * @return uint32_t the value of PAD_ISO_HOLD_CLR. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetPAD_ISO_HOLD_CLR(void) +{ + return ((SMC->ISO_CTRL & SMC_ISO_CTRL_PAD_ISO_HOLD_CLR_MASK) >> SMC_ISO_CTRL_PAD_ISO_HOLD_CLR_SHIFT); +} + +/** + * @brief Set PAD_ISO_HOLD_CLR. + * + * @param uint32_t u32Value PAD_ISO_HOLD_CLR value. + */ +LOCAL_INLINE void SMC_HWA_SetPAD_ISO_HOLD_CLR(uint32_t u32Value) +{ + SMC->ISO_CTRL = ((SMC->ISO_CTRL & ~SMC_ISO_CTRL_PAD_ISO_HOLD_CLR_MASK) | SMC_ISO_CTRL_PAD_ISO_HOLD_CLR(u32Value)); +} + +/** + * @brief Get the value of LOCK. + * + * @return uint32_t the value of LOCK. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetISOLOCK(void) +{ + return ((SMC->ISO_CTRL & SMC_ISO_CTRL_LOCK_MASK) >> SMC_ISO_CTRL_LOCK_SHIFT); +} + +/** + * @brief Set LOCK. + * + * @param uint32_t u32Value LOCK value. + */ +LOCAL_INLINE void SMC_HWA_SetISOLOCK(uint32_t u32Value) +{ + SMC->ISO_CTRL = ((SMC->ISO_CTRL & ~SMC_ISO_CTRL_LOCK_MASK) | SMC_ISO_CTRL_LOCK(u32Value)); +} + +#if SMC_SCG_WAKEUP_CONFIG_SUPPORT +/** + * @brief Get the value of SCG_WAKEUP_CFG. + * + * @return uint32_t the value of SCG_WAKEUP_CFG. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetSCG_WAKEUP_CFG(void) +{ + return ((SMC->SCG_WAKEUP & SMC_SCG_WAKEUP_SCG_WAKEUP_CFG_MASK) >> SMC_SCG_WAKEUP_SCG_WAKEUP_CFG_SHIFT); +} + +/** + * @brief Set SCG_WAKEUP_CFG. + * + * @param uint32_t u32Value SCG_WAKEUP_CFG value. + */ +LOCAL_INLINE void SMC_HWA_SetSCG_WAKEUP_CFG(uint32_t u32Value) +{ + SMC->SCG_WAKEUP = ((SMC->SCG_WAKEUP & ~SMC_SCG_WAKEUP_SCG_WAKEUP_CFG_MASK) | SMC_SCG_WAKEUP_SCG_WAKEUP_CFG(u32Value)); +} + +/** + * @brief Get the value of SCG_POL. + * + * @return uint32_t the value of SCG_POL. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetSCG_POL(void) +{ + return ((SMC->SCG_WAKEUP & SMC_SCG_WAKEUP_SCG_POL_MASK) >> SMC_SCG_WAKEUP_SCG_POL_SHIFT); +} + +/** + * @brief Set SCG_POL. + * + * @param uint32_t u32Value SCG_POL value. + */ +LOCAL_INLINE void SMC_HWA_SetSCG_POL(uint32_t u32Value) +{ + SMC->SCG_WAKEUP = ((SMC->SCG_WAKEUP & ~SMC_SCG_WAKEUP_SCG_POL_MASK) | SMC_SCG_WAKEUP_SCG_POL(u32Value)); +} + +/** + * @brief Get the value of SCG_TRGSEL. + * + * @return uint32_t the value of SCG_TRGSEL. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetSCG_TRGSEL(void) +{ + return ((SMC->SCG_WAKEUP & SMC_SCG_WAKEUP_SCG_TRGSEL_MASK) >> SMC_SCG_WAKEUP_SCG_TRGSEL_SHIFT); +} + +/** + * @brief Set SCG_TRGSEL. + * + * @param uint32_t u32Value SCG_TRGSEL value. + */ +LOCAL_INLINE void SMC_HWA_SetSCG_TRGSEL(uint32_t u32Value) +{ + SMC->SCG_WAKEUP = ((SMC->SCG_WAKEUP & ~SMC_SCG_WAKEUP_SCG_TRGSEL_MASK) | SMC_SCG_WAKEUP_SCG_TRGSEL(u32Value)); +} + +/** + * @brief Get the value of LOCK. + * + * @return uint32_t the value of LOCK. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetSCG_WAKEUPLOCK(void) +{ + return ((SMC->SCG_WAKEUP & SMC_SCG_WAKEUP_LOCK_MASK) >> SMC_SCG_WAKEUP_LOCK_SHIFT); +} + +/** + * @brief Set LOCK. + * + * @param uint32_t u32Value LOCK value. + */ +LOCAL_INLINE void SMC_HWA_SetSCG_WAKEUPLOCK(uint32_t u32Value) +{ + SMC->SCG_WAKEUP = ((SMC->SCG_WAKEUP & ~SMC_SCG_WAKEUP_LOCK_MASK) | SMC_SCG_WAKEUP_LOCK(u32Value)); +} + +/** + * @brief Set SCG Wakeup config register. + * + * @param uint32_t u32Value scg wakeup register value. + */ +LOCAL_INLINE void SMC_HWA_SetSCG_WAKEUP_REG(uint32_t u32Value) +{ + SMC->SCG_WAKEUP = u32Value & SMC_SCG_WAKEUP_MASK; +} +#endif /* SMC_SCG_WAKEUP_CONFIG_SUPPORT */ + +/** + * @brief Get the value of GPR_CCM_STANDBY_ABORT_DIS. + * + * @return uint32_t the value of GPR_CCM_STANDBY_ABORT_DIS. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetGPR_CCM_STANDBY_ABORT_DIS(void) +{ + return ((SMC->CCM_LPCTRL & SMC_CCM_LPCTRL_GPR_CCM_STANDBY_ABORT_DIS_MASK) >> SMC_CCM_LPCTRL_GPR_CCM_STANDBY_ABORT_DIS_SHIFT); +} + +/** + * @brief Set GPR_CCM_STANDBY_ABORT_DIS. + * + * @param uint32_t u32Value GPR_CCM_STANDBY_ABORT_DIS value. + */ +LOCAL_INLINE void SMC_HWA_SetGPR_CCM_STANDBY_ABORT_DIS(uint32_t u32Value) +{ + SMC->CCM_LPCTRL = ((SMC->CCM_LPCTRL & ~SMC_CCM_LPCTRL_GPR_CCM_STANDBY_ABORT_DIS_MASK) | SMC_CCM_LPCTRL_GPR_CCM_STANDBY_ABORT_DIS(u32Value)); +} + +/** + * @brief Get the value of LOCK. + * + * @return uint32_t the value of LOCK. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetCCM_LPCTRLLOCK(void) +{ + return ((SMC->CCM_LPCTRL & SMC_CCM_LPCTRL_LOCK_MASK) >> SMC_CCM_LPCTRL_LOCK_SHIFT); +} + +/** + * @brief Set LOCK. + * + * @param uint32_t u32Value LOCK value. + */ +LOCAL_INLINE void SMC_HWA_SetCCM_LPCTRLLOCK(uint32_t u32Value) +{ + SMC->CCM_LPCTRL = ((SMC->CCM_LPCTRL & ~SMC_CCM_LPCTRL_LOCK_MASK) | SMC_CCM_LPCTRL_LOCK(u32Value)); +} + +/** + * @brief Get the value of BANK0. + * + * @return uint32_t the value of BANK. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetBANK0(void) +{ + return SMC->SW_BANK0; +} + +/** + * @brief Set BANK0. + * + * @param uint32_t u32Value BANK value. + */ +LOCAL_INLINE void SMC_HWA_SetBANK0(uint32_t u32Value) +{ + SMC->SW_BANK0 = u32Value; +} + +/** + * @brief Get the value of BANK1. + * + * @return uint32_t the value of BANK. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetBANK1(void) +{ + return SMC->SW_BANK1; +} + +/** + * @brief Set BANK1. + * + * @param uint32_t u32Value BANK value. + */ +LOCAL_INLINE void SMC_HWA_SetBANK1(uint32_t u32Value) +{ + SMC->SW_BANK1 = u32Value; +} + +/** + * @brief Get the value of SGCMP_EN. + * + * @return uint32_t the value of SGCMP_EN. + */ +LOCAL_INLINE uint32_t SMC_HWA_ADCCFG0_GetSGCMP_EN(uint8_t Index) +{ + return ((SMC->ADC[Index].CFG0 & SMC_ADC_CFG0_SGCMP_EN_MASK) >> SMC_ADC_CFG0_SGCMP_EN_SHIFT); +} + +/** + * @brief Set SGCMP_EN. + * + * @param uint32_t u32Value SGCMP_EN value. + */ +LOCAL_INLINE void SMC_HWA_ADCCFG0_SetSGCMP_EN(uint8_t Index, uint32_t u32Value) +{ + SMC->ADC[Index].CFG0 = ((SMC->ADC[Index].CFG0 & ~SMC_ADC_CFG0_SGCMP_EN_MASK) | SMC_ADC_CFG0_SGCMP_EN(u32Value)); +} + +/** + * @brief Get the value of SGCMP_IEN. + * + * @return uint32_t the value of SGCMP_IEN. + */ +LOCAL_INLINE uint32_t SMC_HWA_ADCCFG0_GetSGCMP_IEN(uint8_t Index) +{ + return ((SMC->ADC[Index].CFG0 & SMC_ADC_CFG0_SGCMP_IEN_MASK) >> SMC_ADC_CFG0_SGCMP_IEN_SHIFT); +} + +/** + * @brief Set SGCMP_IEN. + * + * @param uint32_t u32Value SGCMP_IEN value. + */ +LOCAL_INLINE void SMC_HWA_ADCCFG0_SetSGCMP_IEN(uint8_t Index, uint32_t u32Value) +{ + SMC->ADC[Index].CFG0 = ((SMC->ADC[Index].CFG0 & ~SMC_ADC_CFG0_SGCMP_IEN_MASK) | SMC_ADC_CFG0_SGCMP_IEN(u32Value)); +} + +/** + * @brief Set SGCMP_FLAG_CLR. + * + */ +LOCAL_INLINE void SMC_HWA_ADCCFG0_CLRSGCMPFLAG(uint8_t Index) +{ + SMC->ADC[Index].CFG0 |= SMC_ADC_CFG0_SGCMP_FLAG_CLR_MASK; +} + +/** + * @brief Get the value of SGCMP_REF_SEL. + * + * @return uint32_t the value of SGCMP_REF_SEL. + */ +LOCAL_INLINE uint32_t SMC_HWA_ADCCFG0_GetSGCMPREFSEL(uint8_t Index) +{ + return ((SMC->ADC[Index].CFG0 & SMC_ADC_CFG0_SGCMP_REF_SEL_MASK) >> SMC_ADC_CFG0_SGCMP_REF_SEL_SHIFT); +} + +/** + * @brief Set SGCMP_REF_SEL. + * + * @param uint32_t u32Value SGCMP_REF_SEL value. + */ +LOCAL_INLINE void SMC_HWA_ADCCFG0_SetSGCMP_REF_SEL(uint8_t Index, uint32_t u32Value) +{ + SMC->ADC[Index].CFG0 = ((SMC->ADC[Index].CFG0 & ~SMC_ADC_CFG0_SGCMP_REF_SEL_MASK) | SMC_ADC_CFG0_SGCMP_REF_SEL(u32Value)); +} + +/** + * @brief Get ADC_CFG0. + * + * @return uint32_t the value of ADC_CFG0. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetADCCFG0(uint8_t Index) +{ + return SMC->ADC[Index].CFG0; +} + +/** + * @brief Set ADC_CFG0. + * + * @param uint32_t u32Value ADC_CFG0 value. + */ +LOCAL_INLINE void SMC_HWA_SetADCCFG0(uint8_t Index, uint32_t u32Value) +{ + SMC->ADC[Index].CFG0 = u32Value; +} + +/** + * @brief Get the value of SGCMP_ACT_SEL. + * + * @return uint32_t the value of SGCMP_ACT_SEL. + */ +LOCAL_INLINE uint32_t SMC_HWA_ADCCFG1_GetSGCMP_ACT_SEL(uint8_t Index) +{ + return ((SMC->ADC[Index].CFG1 & SMC_ADC_CFG1_SGCMP_ACT_SEL_MASK) >> SMC_ADC_CFG1_SGCMP_ACT_SEL_SHIFT); +} + +/** + * @brief Set SGCMP_ACT_SEL. + * + * @param uint32_t u32Value SGCMP_ACT_SEL value. + */ +LOCAL_INLINE void SMC_HWA_ADCCFG1_SetSGCMP_ACT_SEL(uint8_t Index, uint32_t u32Value) +{ + SMC->ADC[Index].CFG1 = ((SMC->ADC[Index].CFG1 & ~SMC_ADC_CFG1_SGCMP_ACT_SEL_MASK) | SMC_ADC_CFG1_SGCMP_ACT_SEL(u32Value)); +} + +/** + * @brief Get ADC_CFG1. + * + * @return uint32_t the value of ADC_CFG1. + */ +LOCAL_INLINE uint32_t SMC_HWA_GetADCCFG1(uint8_t Index) +{ + return SMC->ADC[Index].CFG1; +} + +/** + * @brief Set ADC_CFG1. + * + * @param uint32_t u32Value ADC_CFG1 value. + */ +LOCAL_INLINE void SMC_HWA_SetADCCFG1(uint8_t Index, uint32_t u32Value) +{ + SMC->ADC[Index].CFG1 = u32Value; +} + +/** + * @brief Get the value of SGCMP_ON. + * + * @return uint32_t the value of SGCMP_ON. + */ +LOCAL_INLINE uint32_t SMC_HWA_ADCRES_GetSGCMP_ON(uint8_t Index) +{ + return ((SMC->ADC[Index].RES & SMC_ADC_RES_SGCMP_ON_MASK) >> SMC_ADC_RES_SGCMP_ON_SHIFT); +} + +/** + * @brief Get the value of SGCMP_FLAG. + * + * @return uint32_t the value of SGCMP_FLAG. + */ +LOCAL_INLINE uint32_t SMC_HWA_ADCRES_GetSGCMP_FLAG(uint8_t Index) +{ + return ((SMC->ADC[Index].RES & SMC_ADC_RES_SGCMP_FLAG_MASK) >> SMC_ADC_RES_SGCMP_FLAG_SHIFT); +} + +/** + * @brief Get the value of SGCMP_RES. + * + * @return uint32_t the value of SGCMP_RES. + */ +LOCAL_INLINE uint32_t SMC_HWA_ADCRES_GetSGCMP_RES(uint8_t Index) +{ + return ((SMC->ADC[Index].RES & SMC_ADC_RES_SGCMP_RES_MASK) >> SMC_ADC_RES_SGCMP_RES_SHIFT); +} + +/** + * @brief Set clock out control register + * + * @param u32val the value to be set + */ +LOCAL_INLINE void SMC_HWA_Set_CLKOUT_CTRL(uint32_t u32val) +{ + SMC->CLKOUT_CTRL = u32val; +} + +/** + * @brief Get clock out control register + * + * @return Register status + */ +LOCAL_INLINE uint32_t SMC_HWA_Get_CLKOUT_CTRL(void) +{ + return SMC->CLKOUT_CTRL; +} + +/** + * @brief Enable SMC clock out + * + */ +LOCAL_INLINE void SMC_HWA_EnableClockOut(void) +{ + SMC->CLKOUT_CTRL |= (uint32_t)SMC_CLKOUT_CTRL_EN_MASK; +} + +/** + * @brief Disable SMC clock out + * + */ +LOCAL_INLINE void SMC_HWA_DisableClockOut(void) +{ + SMC->CLKOUT_CTRL &= ~(uint32_t)SMC_CLKOUT_CTRL_EN_MASK; +} + +/** + * @brief Get CLKOUT source Select + * + * @return SMC_ClockOutSrcType SMC clock out source + */ +LOCAL_INLINE SMC_ClockOutSrcType SMC_HWA_GetClkOutSel(void) +{ + uint32_t u32RegVal = (SMC->CLKOUT_CTRL & SMC_CLKOUT_CTRL_SEL_MASK) >> SMC_CLKOUT_CTRL_SEL_SHIFT; + return (SMC_ClockOutSrcType)u32RegVal; +} + +/** + * @brief Get CLKOUT SMC clock out divider + * + * @return SMC_ClockOutDivType SMC clock out divider + */ +LOCAL_INLINE SMC_ClockOutDivType SMC_HWA_GetClkOutDiv(void) +{ + uint32_t u32RegVal = (SMC->CLKOUT_CTRL & SMC_CLKOUT_CTRL_DIV_MASK) >> SMC_CLKOUT_CTRL_DIV_SHIFT; + return (SMC_ClockOutDivType)u32RegVal; +} + +/** + * @brief Set CLKOUTDIV + * + * @param eDivType SMC clock out devide ratio type + */ +LOCAL_INLINE void SMC_HWA_SetClkOutDiv(SMC_ClockOutDivType eDivType) +{ + uint32_t u32RegVal = SMC->CLKOUT_CTRL; + SMC->CLKOUT_CTRL = ((u32RegVal & (~(uint32_t)SMC_CLKOUT_CTRL_DIV_MASK)) | SMC_CLKOUT_CTRL_DIV(eDivType)); +} + +/** + * @brief Set CLKOUT Select + * + * @param eClkSrcType SMC clock out devide ratio type + */ +LOCAL_INLINE void SMC_HWA_SetClkOutSel(SMC_ClockOutSrcType eClkSrcType) +{ + uint32_t u32RegVal = SMC->CLKOUT_CTRL; + SMC->CLKOUT_CTRL = ((u32RegVal & (~(uint32_t)SMC_CLKOUT_CTRL_SEL_MASK)) | SMC_CLKOUT_CTRL_SEL(eClkSrcType)); +} + +/** + * @brief Lock SMC_CLKOUT_CTRL register + * + */ +LOCAL_INLINE void SMC_HWA_LockCLKOUT_CTRL(void) +{ + SMC->CLKOUT_CTRL |= (uint32_t)SMC_CLKOUT_CTRL_LOCK_MASK; +} + +/** + * @brief Get SMC_CLKOUT_CTRL register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SMC_HWA_CLKOUT_CTRL_GetLockStatus(void) +{ + return (SMC->CLKOUT_CTRL & (uint32_t)SMC_CLKOUT_CTRL_LOCK_MASK); +} +/** @}*/ +#endif /* #if SMC_CLOCKCONFIG_SUPPORT */ +#endif /* #if SMC_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_SMC_H_ */ diff --git a/Inc/HwA_ssi.h b/Inc/HwA_ssi.h new file mode 100644 index 0000000..a9986de --- /dev/null +++ b/Inc/HwA_ssi.h @@ -0,0 +1,929 @@ +/** + * @file HwA_ssi.h + * @author flagchip + * @brief ssi hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 2.0.0 2023-12-12 Flagchip054 N/A First version for FC7300 + ******************************************************************************** */ + +#ifndef _HWA_SSI_H_ +#define _HWA_SSI_H_ +#include "device_header.h" + +#if SSI_INSTANCE_COUNT > 0U + +/** + * @brief Enable Function Clock + * + * @param SSI instance value + */ +LOCAL_INLINE void SSI_HWA_Func_Enable(SSI_Type *pSsi) +{ + pSsi->GCR |= SSI_GCR_FUNC_EN_MASK; +} + +/** + * @brief Disable Function Clock + * + * @param SSI Pointer to the SSI_Type structure representing the SSI peripheral instance + */ +LOCAL_INLINE void SSI_HWA_Func_Disable(SSI_Type *pSsi) +{ + pSsi->GCR &= ~SSI_GCR_FUNC_EN_MASK; +} + +/** + * @brief Set Function Clock Divider + * + * @param SSI Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u32Value devider + */ +LOCAL_INLINE void SSI_HWA_SetFuncDev(SSI_Type *pSsi, uint32_t u32Value) +{ + pSsi->GCR = (pSsi->GCR & ~SSI_GCR_FUNC_DIV_MASK) | SSI_GCR_FUNC_DIV(u32Value); +} + +/** + * @brief Get the value of the Global Status Register (GSR) + * + * This function reads the value of the Global Status Register (GSR) for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @return The value of the Global Status Register (GSR) + */ +LOCAL_INLINE uint32_t SSI_HWA_GetGlobalStatus(SSI_Type *pSsi) +{ + return pSsi->GSR; +} + +/** + * @brief Get the value of the Global Error Status + * + * This function reads the value of the Global Error Status for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @return The value of the Global Error Status + */ +LOCAL_INLINE uint32_t SSI_HWA_GetGlobalErrStatus(SSI_Type *pSsi) +{ + uint32_t u32ErrStatus; + u32ErrStatus = pSsi->GSR & ~SSI_GSR_SPC_VLD_MASK; + return u32ErrStatus; +} + +/** + * @brief Get the value of the SpcVld Status + * + * This function reads the value of the SpcVld Status for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @return The value of the SpcVld Status + */ +LOCAL_INLINE uint32_t SSI_HWA_GetSpcVldStatus(SSI_Type *pSsi) +{ + return ((pSsi->GSR & SSI_GSR_SPC_VLD_MASK) >> SSI_GSR_SPC_VLD_SHIFT); +} + +/** + * @brief Get the value of the Wheel Stop Status + * + * This function reads the value of the Wheel Stop Status for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @return The value of the SpcVld + */ +LOCAL_INLINE uint32_t SSI_HWA_GetWhlStopStatus(SSI_Type *pSsi) +{ + return ((pSsi->GSR & SSI_GSR_WHL_STOP_MASK) >> SSI_GSR_WHL_STOP_WIDTH); +} + +/** + * @brief Get the value of the Sensor Protocol Counter Timeout Status + * + * This function reads the value of the SPC Timeout Status for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @return The value of the SpcTimeout Status + */ +LOCAL_INLINE uint32_t SSI_HWA_GetSpcTimeoutStatus(SSI_Type *pSsi) +{ + return ((pSsi->GSR & SSI_GSR_SPC_TIMEOUT_MASK) >> SSI_GSR_SPC_TIMEOUT_SHIFT); +} + +/** + * @brief Get the value of SPC Range Status + * + * This function reads the value of the SPC Range Status for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @return The value of the SPC Range Status + */ +LOCAL_INLINE uint32_t SSI_HWA_GetSpcRangeErrStatus(SSI_Type *pSsi) +{ + return ((pSsi->GSR & SSI_GSR_SPC_RANGE_ERR_MASK) >> SSI_GSR_SPC_RANGE_ERR_SHIFT); +} + +/** + * @brief Get the value of Protocol Decoder Status + * + * This function reads the value of the Protocol Decoder Status for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @return The value of the Protocol Decoder Status + */ +LOCAL_INLINE uint32_t SSI_HWA_GetDecodeErrStatus(SSI_Type *pSsi) +{ + return ((pSsi->GSR & SSI_GSR_DECODE_ERR_MASK) >> SSI_GSR_DECODE_ERR_SHIFT); +} + +/** + * @brief Get the value of Protocol Interval Status + * + * This function reads the value of the Protocol Interval Status for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @return The value of the Protocol Interval Status + */ +LOCAL_INLINE uint32_t SSI_HWA_GetIntervalErrStatus(SSI_Type *pSsi) +{ + return ((pSsi->GSR & SSI_GSR_INTERVAL_ERR_MASK) >> SSI_GSR_INTERVAL_ERR_SHIFT); +} + +/** + * @brief Get the value of Pulse Width Status + * + * This function reads the value of the Pulse Width Status for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @return The value of the Pulse Width Status + */ +LOCAL_INLINE uint32_t SSI_HWA_GetPulseWdhErrStatus(SSI_Type *pSsi) +{ + return ((pSsi->GSR & SSI_GSR_PULSE_WIDTH_ERR_MASK) >> SSI_GSR_PULSE_WIDTH_ERR_SHIFT); +} + +/** + * @brief Get the value of Protocol Status + * + * This function reads the value of the Protocol Status for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @return The value of Protocol Status + */ +LOCAL_INLINE uint32_t SSI_HWA_GetProtErrStatus(SSI_Type *pSsi) +{ + return ((pSsi->GSR & SSI_GSR_PROTOC_ERR_MASK) >> SSI_GSR_PROTOC_ERR_SHIFT); +} + +/** + * @brief Set the Lower Part of the Global Counter Window Register (GCWLR) + * + * This function sets the lower part of the Global Counter Window Register (GCWLR) for the specified + * SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u32Value The value to set in the lower part of the GCWLR register + */ +LOCAL_INLINE void SSI_HWA_SetGlobalCounterWindowsL(SSI_Type *pSsi, uint32_t u32Value) +{ + pSsi->GCWLR = (u32Value & SSI_GCWLR_WIN_L_MASK); +} + +/** + * @brief Set the High Part of the Global Counter Window Register (GCWHR) + * + * This function sets the High part of the Global Counter Window Register (GCWHR) for the specified + * SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u32Value The value to set in the High part of the GCWHR register + */ +LOCAL_INLINE void SSI_HWA_SetGlobalCounterWindowsH(SSI_Type *pSsi, uint32_t u32Value) +{ + pSsi->GCWHR = (u32Value & SSI_GCWHR_WIN_H_MASK); +} + +/** + * @brief Set the Global Protocol Configuration Register (GPCR) + * + * This function sets the Global Protocol Configuration Register (GPCR) for the specified SSI + * peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u32Value The value to set in the GPCR register + */ +LOCAL_INLINE void SSI_HWA_SetGlobalProCfg(SSI_Type *pSsi, uint32_t u32Value) +{ + pSsi->GPCR = u32Value; +} + +/** + * @brief Set the AK Interrupt Error Threshold Configuration + * + * This function sets the AK Interrupt Error Threshold configuration in the Global Protocol + * Configuration Register (GPCR) for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u32Value The value to set for the AK Interrupt Error Threshold + */ +LOCAL_INLINE void SSI_HWA_SetAKIntErrThrCfg(SSI_Type *pSsi, uint32_t u32Value) +{ + pSsi->GPCR = (pSsi->GPCR &= ~SSI_GPCR_AK_IETH_MASK) | SSI_GPCR_AK_IETH(u32Value); +} + +/** + * @brief Set the AK Period Error Threshold Configuration + * + * This function sets the AK Period Error Threshold configuration in the Global Protocol + * Configuration Register (GPCR) for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u32Value The value to set for the AK Period Error Threshold + */ +LOCAL_INLINE void SSI_HWA_SetAKPerErrThrCfg(SSI_Type *pSsi, uint32_t u32Value) +{ + pSsi->GPCR = (pSsi->GPCR &= ~SSI_GPCR_AK_PETH_MASK) | SSI_GPCR_AK_PETH(u32Value); +} + +/** + * @brief Set the PWM Period Error Threshold Configuration + * + * This function sets the PWM Period Error Threshold configuration in the Global Protocol + * Configuration Register (GPCR) for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u32Value The value to set for the PWM Period Error Threshold + */ +LOCAL_INLINE void SSI_HWA_SetPwmPerErrThrCfg(SSI_Type *pSsi, uint32_t u32Value) +{ + pSsi->GPCR = (pSsi->GPCR &= ~SSI_GPCR_PWM_PETH_MASK) | SSI_GPCR_PWM_PETH(u32Value); +} + +/** + * @brief Set the PWM Reference Pulse Width + * + * This function sets the PWM Reference Pulse Width configuration in the Global Protocol + * Configuration Register (GPCR) for the specified SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u32Value The value to set for the PWM Reference Pulse Width + */ +LOCAL_INLINE void SSI_HWA_SetPwmRefPulseWidth(SSI_Type *pSsi, uint32_t u32Value) +{ + pSsi->GPCR = (pSsi->GPCR &= ~SSI_GPCR_REF_WIDTH_MASK) | SSI_GPCR_REF_WIDTH(u32Value); +} + +/** + * @brief Set the Sub-instance Control Register + * + * This function sets the Sub-instance Control Register (ICR) for a specified sub-instance index + * in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to configure + * @param u32Value The value to set for the Sub-instance Control Register + */ +LOCAL_INLINE void SSI_HWA_SetSubinsCtr(SSI_Type *pSsi, uint8_t u8IcrIdx, uint32_t u32Value) +{ + pSsi->SUB_INS[u8IcrIdx].ICR = u32Value; +} + +/** + * @brief Enable the Sub-instance + * + * This function enables the sub-instance by setting the enable bit in the Sub-instance Control + * Register (ICR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to enable + */ +LOCAL_INLINE void SSI_HWA_Subins_Enable(SSI_Type *pSsi, uint8_t u8IcrIdx) +{ + pSsi->SUB_INS[u8IcrIdx].ICR |= SSI_ICR_SSI_EN_MASK; +} + +/** + * @brief Disable the Sub-instance + * + * This function Disable the sub-instance by setting the enable bit in the Sub-instance Control + * Register (ICR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to enable + */ +LOCAL_INLINE void SSI_HWA_Subins_Disable(SSI_Type *pSsi, uint8_t u8IcrIdx) +{ + pSsi->SUB_INS[u8IcrIdx].ICR &= ~SSI_ICR_SSI_EN_MASK; +} + +/** + * @brief Set the Sub-instance Channel Switch + * + * This function sets the channel switch configuration in the Sub-instance Control Register (ICR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to configure + * @param u32Value The value to set for the channel switch configuration + */ +LOCAL_INLINE void SSI_HWA_SetSubinsChlSwitch(SSI_Type *pSsi, uint8_t u8IcrIdx, uint32_t u32Value) +{ + uint32_t u32RegVal = pSsi->SUB_INS[u8IcrIdx].ICR; + pSsi->SUB_INS[u8IcrIdx].ICR = (u32RegVal & ~SSI_ICR_CHL_SW_MASK) | SSI_ICR_CHL_SW(u32Value); +} + +/** + * @brief Enable Window Range Check for Sub-instance + * + * This function enables the window range check feature in the Sub-instance Control Register (ICR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsWinRangChk_Enable(SSI_Type *pSsi, uint8_t u8IcrIdx) +{ + pSsi->SUB_INS[u8IcrIdx].ICR |= SSI_ICR_RANG_CHK_EN_MASK; +} + +/** + * @brief Disable Window Range Check for Sub-instance + * + * This function Disable the window range check feature in the Sub-instance Control Register (ICR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsWinRangChk_Disable(SSI_Type *pSsi, uint8_t u8IcrIdx) +{ + pSsi->SUB_INS[u8IcrIdx].ICR &= ~SSI_ICR_RANG_CHK_EN_MASK; +} + +/** + * @brief Set the Sub-instance Channel Selection + * + * This function sets the channel selection configuration in the Sub-instance Control Register (ICR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to configure + * @param u32Value The value to set for the channel selection configuration + */ +LOCAL_INLINE void SSI_HWA_SetSubinsChlSel(SSI_Type *pSsi, uint8_t u8IcrIdx, uint8_t u8Value) +{ + uint32_t u32RegVal = pSsi->SUB_INS[u8IcrIdx].ICR; + pSsi->SUB_INS[u8IcrIdx].ICR = (u32RegVal & ~SSI_ICR_CHL_SEL_MASK) | SSI_ICR_CHL_SEL(u8Value); +} + +/** + * @brief Set the Sub-instance Protocol Selection + * + * This function sets the Protocol selection configuration in the Sub-instance Control Register + * (ICR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to configure + * @param u32Value The value to set for the Protocol selection configuration + */ +LOCAL_INLINE void SSI_HWA_SetSubinsProtSel(SSI_Type *pSsi, uint8_t u8IcrIdx, uint32_t u32Value) +{ + uint32_t u32RegVal = pSsi->SUB_INS[u8IcrIdx].ICR; + pSsi->SUB_INS[u8IcrIdx].ICR = (u32RegVal & ~SSI_ICR_PROT_SEL_MASK) | SSI_ICR_PROT_SEL(u32Value); +} + +/** + * @brief Get the Sub-instance Protocol Selection + * + * This function Gets the Protocol selection configuration in the Sub-instance Control Register + * (ICR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to configure + * @return The value of the Sub-instance Protocol Selection + */ +LOCAL_INLINE uint32_t SSI_HWA_GetSubinsProtSel(SSI_Type *pSsi, uint8_t u8IcrIdx) +{ + return ((pSsi->SUB_INS[u8IcrIdx].ICR & SSI_ICR_PROT_SEL_MASK) >> SSI_ICR_PROT_SEL_SHIFT); +} + +#if SSI_INTERNAL_CMP_SUPPORT == STD_ON +/** + * @brief Enable internal cmp for Sub-instance + * + * This function enables the internal cmp in the Sub-instance Control Register (ICR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsIntCmp_Enable(SSI_Type *pSsi, uint8_t u8IcrIdx) +{ + pSsi->SUB_INS[u8IcrIdx].ICR |= SSI_ICR_CMP_EN_MASK; +} + +/** + * @brief Disable internal cmp for Sub-instance + * + * This function Disable the internal cmp in the Sub-instance Control Register (ICR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsIntCmp_Disable(SSI_Type *pSsi, uint8_t u8IcrIdx) +{ + pSsi->SUB_INS[u8IcrIdx].ICR &= ~SSI_ICR_CMP_EN_MASK; +} + +/** + * @brief Set the Sub-instance Resistance Select + * + * This function sets resistance select configuration in the Sub-instance Control Register (ICR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to configure + * @param u32Value The value to set for the resource selection configuration + */ +LOCAL_INLINE void SSI_HWA_SetSubinsResSel(SSI_Type *pSsi, uint8_t u8IcrIdx, uint32_t u32Value) +{ + uint32_t u32RegVal = pSsi->SUB_INS[u8IcrIdx].ICR; + pSsi->SUB_INS[u8IcrIdx].ICR = (u32RegVal & ~SSI_ICR_RES_SEL_MASK) | SSI_ICR_RES_SEL(u32Value); +} +#endif + +/** + * @brief Set the Sub-instance GPWM Polarity + * + * This function sets the GPWM polarity configuration in the Sub-instance Control Register (ICR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to configure + * @param u32Value The value to set for the GPWM polarity configuration + */ +LOCAL_INLINE void SSI_HWA_SetSubinsGpwmPola(SSI_Type *pSsi, uint8_t u8IcrIdx, uint32_t u32Value) +{ + uint32_t u32RegVal = pSsi->SUB_INS[u8IcrIdx].ICR; + pSsi->SUB_INS[u8IcrIdx].ICR = (u32RegVal & ~SSI_ICR_GPWM_INV_MASK) | SSI_ICR_GPWM_INV(u32Value); +} + +/** + * @brief Set the Sub-instance GPWM Time Counter + * + * This function sets the GPWM time counter configuration in the Sub-instance Control Register (ICR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IcrIdx The index of the sub-instance control register to configure + * @param u32Value The value to set for the GPWM time counter configuration + */ +LOCAL_INLINE void SSI_HWA_SetSubinsGpwmTimeCnt(SSI_Type *pSsi, uint8_t u8IcrIdx, uint32_t u32Value) +{ + uint32_t u32RegVal = pSsi->SUB_INS[u8IcrIdx].ICR; + pSsi->SUB_INS[u8IcrIdx].ICR = (u32RegVal & ~SSI_ICR_GPWM_TOC_MASK) | SSI_ICR_GPWM_TOC(u32Value); +} + +/** + * @brief Enable the Sub-instance Filter + * + * This function enables the filter in the Sub-instance Filter Register (IFR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IfrIdx The index of the sub-instance filter register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsFilter_Enable(SSI_Type *pSsi, uint8_t u8IfrIdx) +{ + pSsi->SUB_INS[u8IfrIdx].IFR |= SSI_IFR_FLT_EN_MASK; +} + +/** + * @brief Disable the Sub-instance Filter + * + * This function disable the filter in the Sub-instance Filter Register (IFR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IfrIdx The index of the sub-instance filter register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsFilter_Disable(SSI_Type *pSsi, uint8_t u8IfrIdx) +{ + pSsi->SUB_INS[u8IfrIdx].IFR &= ~SSI_IFR_FLT_EN_MASK; +} + +/** + * @brief Set the Sub-instance Filter Width + * + * This function sets the filter width configuration in the Sub-instance Filter Register (IFR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IfrIdx The index of the sub-instance filter register to configure + * @param u32Value The value to set for the filter width configuration + */ +LOCAL_INLINE void SSI_HWA_SetSubinsFilterWidth(SSI_Type *pSsi, uint8_t u8IfrIdx, uint32_t u32Value) +{ + uint32_t u32RegVal = pSsi->SUB_INS[u8IfrIdx].IFR; + pSsi->SUB_INS[u8IfrIdx].IFR = (u32RegVal & ~SSI_IFR_FLT_WIDTH_MASK) | + SSI_IFR_FLT_WIDTH(u32Value); +} + +/** + * @brief Set the Sub-instance Interrupt Configuration + * + * This function sets the interrupt configuration in the Sub-instance Interrupt Control Register + * (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + * @param u32Value The value to set for the interrupt configuration + */ +LOCAL_INLINE void SSI_HWA_SetSubinsIntCfg(SSI_Type *pSsi, uint8_t u8IntcrIdx, uint32_t u32Value) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR = u32Value; +} + +/** + * @brief Set the Sub-instance Interrupt Configuration + * + * This function sets the interrupt configuration in the Sub-instance Interrupt Control Register + * (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + * @param u32Value The value to set for the interrupt configuration + */ +LOCAL_INLINE void SSI_HWA_SubinsErrInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR |= 0xDE; +} + +/** + * @brief Enable Valid Interrupt in Sub-instance + * + * This function enables the valid interrupt in the Sub-instance Interrupt Control Register (INTCR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsValidInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_VLD_INT_EN_MASK; +} +/** + * @brief Disable Valid Interrupt in Sub-instance + * + * This function disables the valid interrupt in the Sub-instance Interrupt Control Register (INTCR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsValidInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_VLD_INT_EN_MASK; +} + +/** + * @brief Enable Stop Interrupt in Sub-instance + * + * This function enables the Stop interrupt in the Sub-instance Interrupt Control Register (INTCR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsStopInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_STOP_INT_EN_MASK; +} + +/** + * @brief Disable Stop Interrupt in Sub-instance + * + * This function disables the Stop interrupt in the Sub-instance Interrupt Control Register (INTCR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsStopInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_STOP_INT_EN_MASK; +} + +/** + * @brief Enable Timeout Interrupt in Sub-instance + * + * This function enables the timeout interrupt in the Sub-instance Interrupt Control Register + * (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsFTimeoutInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_TIMEOUT_INT_EN_MASK; +} + +/** + * @brief Disable Timeout Interrupt in Sub-instance + * + * This function disables the timeout interrupt in the Sub-instance Interrupt Control Register + * (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsFTimeoutInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_TIMEOUT_INT_EN_MASK; +} + +/** + * @brief Enable Range Error Interrupt in Sub-instance + * + * This function enables the Range Error interrupt in the Sub-instance Interrupt Control Register + * (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsRangeErrInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_RANGE_ERR_EN_MASK; +} + +/** + * @brief Disable Range Error Interrupt in Sub-instance + * + * This function disables the Range Error interrupt in the Sub-instance Interrupt Control Register + * (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsRangeErrInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_RANGE_ERR_EN_MASK; +} + +/** + * @brief Enable Decode Error Interrupt in Sub-instance + * + * This function enables the Decode Error interrupt in the Sub-instance Interrupt Control Register + * (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsDecodeErrInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_DECODE_ERR_EN_MASK; +} + +/** + * @brief Disable Decode Error Interrupt in Sub-instance + * + * This function disables the Decode Error interrupt in the Sub-instance Interrupt Control Register + * (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsDecodeErrInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_DECODE_ERR_EN_MASK; +} + +/** + * @brief Enable Interval Error Interrupt in Sub-instance + * + * This function enables the Interval Error interrupt in the Sub-instance Interrupt Control Register + * (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsIntervalErrInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_INTERVAL_ERR_EN_MASK; +} + +/** + * @brief Disable Interval Error Interrupt in Sub-instance + * + * This function disables the Interval Error interrupt in the Sub-instance Interrupt Control + * Register (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsIntervalErrInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_INTERVAL_ERR_EN_MASK; +} + +/** + * @brief Enable Pulse Width Error Interrupt in Sub-instance + * + * This function enables the Pulse Width Error interrupt in the Sub-instance Interrupt Control + * Register (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsPulseWidthErrInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_PULSE_WIDTH_ERR_EN_MASK; +} + +/** + * @brief Disable Pulse Width Error Interrupt in Sub-instance + * + * This function disables the Pulse Width Error interrupt in the Sub-instance Interrupt Control + * Register (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ + +LOCAL_INLINE void SSI_HWA_SubinsPulseWidthErrInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_PULSE_WIDTH_ERR_EN_MASK; +} + +/** + * @brief Enable Protocol Error Interrupt in Sub-instance + * + * This function enables the Protocol Error interrupt in the Sub-instance Interrupt Control Register + * (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsProtErrInt_Enable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR |= SSI_INTCR_PROTOC_ERR_INT_EN_MASK; +} + +/** + * @brief Disable Protocol Error Interrupt in Sub-instance + * + * This function disables the Protocol Error interrupt in the Sub-instance Interrupt Control + * Register (INTCR) for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8IntcrIdx The index of the sub-instance interrupt control register to configure + */ +LOCAL_INLINE void SSI_HWA_SubinsProtErrInt_Disable(SSI_Type *pSsi, uint8_t u8IntcrIdx) +{ + pSsi->SUB_INS[u8IntcrIdx].INTCR &= ~SSI_INTCR_PROTOC_ERR_INT_EN_MASK; +} + +/** + * @brief Get Sensor Protocol Counter Value + * + * This function retrieves the counter value from the Sensor Protocol Control Register (SPCR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8SpcrIdx The index of the sensor protocol control register to read + * @return The counter value from the specified sensor protocol control register + */ +LOCAL_INLINE uint32_t SSI_HWA_GetSensorProtocolCnt(SSI_Type *pSsi, uint8_t u8SpcrIdx) +{ + return (pSsi->SUB_INS[u8SpcrIdx].SPCR & SSI_SPCR_CNT_MASK); +} + +/** + * @brief Get High Pulse Counter Value + * + * This function retrieves the high pulse counter value from the High Pulse Control Register (HPCR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8HpcrIdx The index of the high pulse control register to read + * @return The high pulse counter value from the specified high pulse control register + */ +LOCAL_INLINE uint32_t SSI_HWA_GetHighPulseCnt(SSI_Type *pSsi, uint8_t u8HpcrIdx) +{ + return (pSsi->SUB_INS[u8HpcrIdx].HPCR & SSI_HPCR_HPULSE_MASK); +} + +/** + * @brief Get AK Manchester Code Value + * + * This function retrieves the AK man Manchester value from the AK Protocol Register (AKPR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8AkprIdx The index of the AK Protocol register to read + * @return The AK Manchester code value from the specified AK Protocol register + */ +LOCAL_INLINE uint32_t SSI_HWA_GetAkMancodeVal(SSI_Type *pSsi, uint8_t u8AkprIdx) +{ + return (pSsi->SUB_INS[u8AkprIdx].AKPR & SSI_AKPR_MCODE_MASK); +} + +/** + * @brief Get AK Manchester Decode Counter Value + * + * This function retrieves the AK Manchester decode counter value from the AK Protocol Register + * (AKPR) for a specified sub-instance index in the SSI peripheral. The counter value is extracted + * and right-shifted by the appropriate number of bits to align it correctly. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8AkprIdx The index of the AK Protocol register to read + * @return The AK Manchester decode counter value from the specified AK Protocol register + */ +LOCAL_INLINE uint32_t SSI_HWA_GetAkManDecodeCnt(SSI_Type *pSsi, uint8_t u8AkprIdx) +{ + return ((pSsi->SUB_INS[u8AkprIdx].AKPR & SSI_AKPR_MCODE_CNT_MASK) >> SSI_AKPR_MCODE_CNT_SHIFT); +} + +/** + * @brief Get PWM Decode Value + * + * This function retrieves the PWM decode value from the PWM Protocol Register (PWMPR) + * for a specified sub-instance index in the SSI peripheral. + * + * @param pSsi Pointer to the SSI_Type structure representing the SSI peripheral instance + * @param u8PwmprIdx The index of the PWM Protocol register to read + * @return The PWM decode value from the specified PWM Protocol register + */ +LOCAL_INLINE uint32_t SSI_HWA_GetPwmDecodeVal(SSI_Type *pSsi, uint8_t u8PwmprIdx) +{ + return (pSsi->SUB_INS[u8PwmprIdx].PWMPR & SSI_PWMPR_PCODE_MASK); +} + +/** + * @brief Unlock the MB_INTn registers + * + * @param u8CoreIndex the index of the core + * @param u32Mask the unlock bits + */ +LOCAL_INLINE uint32_t SSI_HWA_GetStatusVal(SSI_Type *pSsi, uint8_t u8IsrIdx) +{ + uint32 u32Status = SSI_ISR_PROTOC_ERR(1) | SSI_ISR_PULSE_WIDTH_ERR(1) | SSI_ISR_INTERVAL_ERR(1) | + SSI_ISR_DECODE_ERR(1) | SSI_ISR_SPC_RANGE_ERR(1) | SSI_ISR_SPC_TIMEOUT_ERR(1) | + SSI_ISR_WHL_STOP(1) | SSI_ISR_SPC_VLD(1); + return (pSsi->SUB_INS[u8IsrIdx].ISR & u32Status); +} + +/** + * @brief Unlock the MB_INTn registers + * + * @param u8CoreIndex the index of the core + * @param u32Mask the unlock bits + */ +LOCAL_INLINE uint32_t SSI_HWA_GetIntCmpStatus(SSI_Type *pSsi, uint8_t u8IsrIdx) +{ + return ((pSsi->SUB_INS[u8IsrIdx].ISR & SSI_ISR_CMP_IOK_MASK) >> SSI_ISR_CMP_IOK_SHIFT); +} + +/** + * @brief Unlock the MB_INTn registers + * + * @param u8CoreIndex the index of the core + * @param u32Mask the unlock bits + */ +LOCAL_INLINE void SSI_HWA_ClearSubStatus(SSI_Type *pSsi, uint8_t u8IsrIdx) +{ + uint32 u32Val = SSI_ISR_PROTOC_ERR(1) | SSI_ISR_PULSE_WIDTH_ERR(1) | SSI_ISR_INTERVAL_ERR(1) | + SSI_ISR_DECODE_ERR(1) | SSI_ISR_SPC_RANGE_ERR(1) | SSI_ISR_SPC_TIMEOUT_ERR(1) | + SSI_ISR_WHL_STOP(1) | SSI_ISR_SPC_VLD(1); + pSsi->SUB_INS[u8IsrIdx].ISR |= u32Val; +} + +/** + * @brief Unlock the MB_INTn registers + * + * @param u8CoreIndex the index of the core + * @param u32Mask the unlock bits + */ +LOCAL_INLINE void SSI_HWA_ClearSpcVldStatus(SSI_Type *pSsi, uint8_t u8IsrIdx) +{ + pSsi->SUB_INS[u8IsrIdx].ISR = SSI_ISR_SPC_VLD(1); +} + +#endif /* #if SSI_INSTANCE_COUNT > 0U */ + +#endif diff --git a/Inc/HwA_stcu.h b/Inc/HwA_stcu.h new file mode 100644 index 0000000..14574b7 --- /dev/null +++ b/Inc/HwA_stcu.h @@ -0,0 +1,274 @@ +/** + * @file HwA_stcu.h + * @author Flagchip + * @brief Safety Test and Control Unit + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip038 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip038 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_STCU_H_ +#define _HWA_STCU_H_ + +#include "device_header.h" + +#if STCU_INSTANCE_COUNT > 0U + +/** + * \brief Get Self Test Status + * + * \return Status, maybe more than one status, refer to "STCU_SelfTestStatusType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetSelfTestStatus(void) +{ + return STCU->SELF_TEST_STATUS; +} + +/** + * \brief Clear all Self Test Status + */ +LOCAL_INLINE void STCU_HWA_ClearSelfTestStatus(void) +{ + STCU->SELF_TEST_STATUS = 0x0UL; +} + + +/** + * \brief Mbist select for self-test + * + * \param u32MbistSel maybe more than one + */ +LOCAL_INLINE void STCU_HWA_MbistSelect(uint32_t u32MbistSel) +{ + STCU->MBIST_SEL = u32MbistSel; +} + +/** + * \brief Get Mbist Done Flag + * + * \return All Mbist Done flags, refer to "STCU_MbistDoneType" + */ +LOCAL_INLINE uint32_t STCU_GetMbistDone(void) +{ + return STCU->MBIST_DONE_STATUS; +} + +/** + * \brief Get Mbist Fail Flag + * + * \return All Mbist Fail flags "STCU_MbistFailedType" + */ +LOCAL_INLINE uint32_t STCU_GetMbistFail(void) +{ + return STCU->MBIST_FAIL_STATUS; +} + +/** + * \brief Check Lbist execution failed status + * + * \return LBIST status, refer to "STCU_LbistStatusType" + */ +LOCAL_INLINE uint32_t STCU_HWA_CheckLbistStatus(void) +{ + return STCU->LBIST_STATUS; +} + + +/** + * \brief Get STCU Hardware Ram Initial Status + * + * \return Initial Status, refer to "STCU_HardwareInitRamStatusType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetHardwareRamInitStatus(void) +{ + return STCU->SRAM_INI_STATUS; +} + +/** + * \brief STCU RAM Init Mode set, can select more than one, for example: STCU_INIT_RAM_TYPE_SRAM0 | STCU_INIT_RAM_TYPE_SRAM1 + * + * \param u32InitRamType Init Mode + */ +LOCAL_INLINE void STCU_HWA_SetRamInitType(uint32_t u32InitRamType) +{ + STCU->SRAM_INI_SEL = u32InitRamType; +} + +/** + * \brief Set STCU Interrupt + * + * \param bIntEn Normal interrupt enable + * \param bSequenceErrorIntEn Sequence error interrupt enable + * \param bSizeErrorIntEn Size error interrupt enable + */ +LOCAL_INLINE void STCU_HWA_SetInterrupt(uint8_t bIntEn, uint8_t bSequenceErrorIntEn, uint8_t bSizeErrorIntEn) +{ + STCU->IRQ = STCU_IRQ_EN(bIntEn) | STCU_IRQ_SEQ_ERR(bSequenceErrorIntEn) | STCU_IRQ_SIZE_ERR(bSizeErrorIntEn); +} + +/** + * \brief STCU Ram Initial Start + * + * \param eInitRamMode Initial mode + * \param bEnable Enable Initial + * \param bLock Lock after initial + */ +LOCAL_INLINE void STCU_HWA_StartRamInit(uint8_t eInitRamMode, uint8_t bLock) +{ + STCU->SRAM_INI_CTRL = STCU_SRAM_INI_CTRL_MODE(eInitRamMode) | STCU_SRAM_INI_CTRL_EN_MASK | STCU_SRAM_INI_CTRL_LOCK(bLock) ; +} + +/** + * \brief Get Ram Initial Done flag + * + * \return All Done flag, maybe more than one flag, refer to "STCU_InitRamDoneType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetRamInitDone(void) +{ + return STCU->SRAM_INI_DONE_STATUS; +} + +/** + * \brief Get Ram Initial status + * + * \return All Done flag, maybe more than one flag, refer to "STCU_HardwareInitRamStatusType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetRamInitStatus(void) +{ + return STCU->SRAM_INI_STATUS; +} + +/** + * \brief Set the LBIST pattern amount control value N. + * + * \param u32Amount LBIST pattern amount control value N. (pattern amount = N * 256) + */ +LOCAL_INLINE void STCU_HWA_SetLBISTPatternAmount(uint32_t u32Amount) +{ + STCU->LBIST_PAT_CTRL = u32Amount; +} + +/** + * \brief Set the MBIST algorithm for SW trigger self-test + * + * \param bFullTest Enable Full test for MBIST. + * \param bSRAMInit Enable SRAM initialization at the end of software trigger self-test. + */ +LOCAL_INLINE void STCU_HWA_SetMBISTSWAlg(bool bFullTest, bool bSRAMInit) +{ + STCU->MBIST_ALG = (STCU->MBIST_ALG & ~(STCU_MBIST_ALG_TRIG_ALG_SEL_MASK | STCU_MBIST_ALG_TRIG_INI_EN_MASK)) | \ + (STCU_MBIST_ALG_TRIG_ALG_SEL(bFullTest?0X1FU:0x19U) | STCU_MBIST_ALG_TRIG_INI_EN(bSRAMInit?0x1U:0x0U)); +} + +/** + * \brief Set safety key + * + * \param u32Key Safety Key. + */ +LOCAL_INLINE void STCU_HWA_SetSafetyKey(uint32_t u32Key) +{ + STCU->SELF_TEST_KEY = u32Key; +} + +/** + * \brief Enable A self-test software trigger. + */ +LOCAL_INLINE void STCU_HWA_SwTriggerA(void) +{ + STCU->SELF_TEST_TRIG_A = STCU_SELF_TEST_TRIG_A_MASK; +} + +/** + * \brief Enable B self-test software trigger. + */ +LOCAL_INLINE void STCU_HWA_SwTriggerB(void) +{ + STCU->SELF_TEST_TRIG_B = STCU_SELF_TEST_TRIG_B_MASK; +} + +/** + * \brief Set self test ctrl register + * + * \param u32Reg Register value. + */ +LOCAL_INLINE void STCU_HWA_SetSelfTestCTRL(uint32_t u32Reg) +{ + STCU->SELF_TEST_CTRL = u32Reg; +} + +/** + * \brief Enable interrupt + */ +LOCAL_INLINE void STCU_HWA_EnableInterrupt(void) +{ + STCU->IRQ |= STCU_IRQ_EN_MASK; +} + +/** + * \brief Disable interrupt + */ +LOCAL_INLINE void STCU_HWA_DisableInterrupt(void) +{ + STCU->IRQ &= ~STCU_IRQ_EN_MASK; +} + +/** + * \brief Get STCU interrupt flags + * + * \return Status, maybe more than one status, refer to "STCU_InterruptFlagType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetInterruptFlag(void) +{ + return ((STCU->IRQ) & (STCU_IRQ_SEQ_ERR_MASK | STCU_IRQ_SIZE_ERR_MASK)); +} + +/** + * \brief Clear STCU interrupt flags + */ +LOCAL_INLINE void STCU_HWA_ClearInterruptFlag(void) +{ + STCU->IRQ &= ~(STCU_IRQ_SEQ_ERR_MASK | STCU_IRQ_SIZE_ERR_MASK); +} + +/** + * \brief Set STCU LBIST expected misr value + */ +LOCAL_INLINE void STCU_HWA_SetExpectedMisr(uint32_t u32Misr) +{ + STCU->LBIST_EXP_MISR = STCU_LBIST_EXP_MISR_MISR(u32Misr); +} + +/** + * \brief Get STCU LBIST expected misr value + */ +LOCAL_INLINE uint32_t STCU_HWA_GetExpectedMisr(void) +{ + return STCU->LBIST_EXP_MISR; +} + +/** + * \brief Get STCU LBIST actual misr value + */ +LOCAL_INLINE uint32_t STCU_HWA_GetActualMisr(void) +{ + return STCU->LBIST_ACT_MISR; +} + +/** @}*/ + +#endif /* #if STCU_INSTANCE_COUNT > 0U */ + +#endif /*#ifndef _HWA_STCU_H_*/ diff --git a/Inc/HwA_tmu.h b/Inc/HwA_tmu.h new file mode 100644 index 0000000..e346ab2 --- /dev/null +++ b/Inc/HwA_tmu.h @@ -0,0 +1,702 @@ +/** + * @file HwA_tmu.h + * @author Flagchip + * @brief Hardware access layer for TMU + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip074 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip074 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_TMU_H +#define _HWA_TMU_H + +#include "device_header.h" + +#if TMU_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_tmu HwA_tmu + * @ingroup module_driver_tmu + * @{ + */ + +/** + * @brief Select the TF_CTRL and TV_CTRL register is lock or not + * + */ +typedef enum +{ + TMU_TF_TV_LOCK = 0U, /*!< TF_CTRL and TV_CTRL register is lock*/ + TMU_TF_TV_UNLOCK = 1U /*!< TF_CTRL and TV_CTRL register is unlock*/ +}TMU_LockType; + +/** + * @brief Select the Flag-based temperature sensor hysteresis control + * + */ +typedef enum +{ + TMU_TF_HYSOFF_ON = 0U, /*!< Flag-based temperature sensor hysteresis is on*/ + TMU_TF_HYSOFF_OFF = 1U /*!< Flag-based temperature sensor hysteresis is off*/ +}TMU_HysteresisType; + +/** + * @brief Select the Flag-based temperature sensor filter control + * + */ +typedef enum +{ + TMU_TF_FILT_BYP_BYPASSED = 0U, /*!< Flag-based temperature sensor filter is bypassed*/ + TMU_TF_FILT_BYP_ENABLED = 1U /*!< Flag-based temperature sensor filter is enabled*/ +}TMU_bypassType; + +/** + * @brief Get the status of whether the temperature sensor register is locked + * + * @param pTmu the base address of the TMU instance + * @return true Temperature register is locked(CTRL) + * @return false Temperature register is unlocked(CTRL) + */ +LOCAL_INLINE TMU_LockType TMU_HWA_GetTemperatureLockStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->UNLOCK & TMU_UNLOCK_UNLOCK_MASK) >> TMU_UNLOCK_UNLOCK_SHIFT; + return (TMU_LockType)u32TmpVal; +} + +/** + * @brief Set the status of whether the temperature sensor register is locked or not + * + * @param pTmu the base address of the TMU instance + * @param eLockStatus Select the TF_CTRL and TV_CTRL register is lock or not + */ +LOCAL_INLINE void TMU_HWA_SetTemperatureLockStatus(TMU_Type *const pTmu,TMU_LockType eLockStatus) +{ + if((bool)eLockStatus) + { + pTmu->UNLOCK = 0xA5A50000U | TMU_UNLOCK_UNLOCK(eLockStatus); + }else + { + pTmu->UNLOCK = TMU_UNLOCK_UNLOCK(eLockStatus); + } +} + +#if !TMU_SUPPORT_TV_ECMP +/** + * @brief Get the Flag-based temperature sensor over 150 Celsius interrupt flag + * + * @param pTmu the base address of the TMU instance + * @return true Temperature over 150 Celsius interrupt is enabled + * @return false Temperature over 150 Celsius interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperature150InterruptFlag(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_150F_IE_MASK) >> TMU_TF_CTRL_TF_150F_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor over 150 Celsius interrupt flag + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature over 150 Celsius interrupt + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperature150InterruptFlag(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_150F_IE_MASK) | TMU_TF_CTRL_TF_150F_IE(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor over 125 Celsius interrupt flag + * + * @param pTmu the base address of the TMU instance + * @return true Temperature over 125 Celsius interrupt is enabled + * @return false Temperature over 125 Celsius interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperature125InterruptFlag(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_125F_IE_MASK) >> TMU_TF_CTRL_TF_125F_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor over 125 Celsius interrupt flag + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature over 125 Celsius interrupt + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperature125InterruptFlag(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_125F_IE_MASK) | TMU_TF_CTRL_TF_125F_IE(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor ready interrupt flag + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor ready interrupt is enabled + * @return false Temperature sensor ready interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureReadyInterruptFlag(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_RDYF_IE_MASK) >> TMU_TF_CTRL_TF_RDYF_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor over ready interrupt flag + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature sensor ready interrupt + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureReadyInterruptFlag(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_RDYF_IE_MASK) | TMU_TF_CTRL_TF_RDYF_IE(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor hysteresis control status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor Hysteresis is off + * @return false Temperature sensor Hysteresis is on + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureHysteresisStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_HYSOFF_MASK) >> TMU_TF_CTRL_TF_HYSOFF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor hysteresis control status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to off(1)/on(0) the temperature sensor hysteresis + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureHysteresisStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_HYSOFF_MASK) | TMU_TF_CTRL_TF_HYSOFF(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor startup counter + * + * @param pTmu the base address of the TMU instance + * @return u32TmpVal count of the startup + */ +LOCAL_INLINE uint8_t TMU_HWA_GetFlagTemperatureCounter(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_START_CNT_MASK) >> TMU_TF_CTRL_TF_START_CNT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the Flag-based temperature sensor startup counter + * + * @param pTmu the base address of the TMU instance + * @param u8Counter the startup counter + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureCounter(TMU_Type *const pTmu,uint8_t u8Counter) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_START_CNT_MASK) | TMU_TF_CTRL_TF_START_CNT(u8Counter); +} + +#ifdef TMU_SUPPORT_STOP +/** + * @brief Configure the stop mode of the Flag-based temperature sensor + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether the Flag-based temperature sensor is run in stop mode + */ +LOCAL_INLINE void TMU_HWA_ConfigFlagTemperatureStopMode(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_STOP_EN_MASK) | TMU_TF_CTRL_TF_STOP_EN(bEnable); +} +#endif + +/** + * @brief Get the Flag-based temperature sensor filter bypass control status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor Filter is enabled + * @return false Temperature sensor Filter is bypassed + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureFilterBypassStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_FILT_BYP_MASK) >> TMU_TF_CTRL_TF_FILT_BYP_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor filter bypass control status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether the temperature sensor filter is enabled(1) or bypassed(0) + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureFilterBypassStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_FILT_BYP_MASK) | TMU_TF_CTRL_TF_FILT_BYP(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor enable status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor is on + * @return false Temperature sensor is off + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureEnableStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_EN_MASK) >> TMU_TF_CTRL_TF_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor enable status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether the temperature sensor is on(1) or off(0) + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureEnableStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_EN_MASK) | TMU_TF_CTRL_TF_EN(bEnable); +} + +/** + * @brief Check whether the temperature is over 150 Celsius + * + * @param pTmu the base address of the TMU instance + * @return true the temperature is over 150 Celsius + * @return false the temperature is not over 150 Celsius + */ +LOCAL_INLINE bool TMU_HWA_Get150Status(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_150_MASK) >> TMU_TF_STATUS_TF_150_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the temperature is over 125 Celsius + * + * @param pTmu the base address of the TMU instance + * @return true the temperature is over 125 Celsius + * @return false the temperature is not over 125 Celsius + */ +LOCAL_INLINE bool TMU_HWA_Get125Status(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_125_MASK) >> TMU_TF_STATUS_TF_125_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the flag for temperature over 150 Celsius is set + * + * @param pTmu the base address of the TMU instance + * @return true the temperature has exceeded 150 Celsius since last time W1C + * @return false the temperature has not exceeded 150 Celsius since TF is ready + */ +LOCAL_INLINE bool TMU_HWA_Get150Flag(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_150F_MASK) >> TMU_TF_STATUS_TF_150F_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the temperature over 150 Celsius flag + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_Clear150Flag(TMU_Type *const pTmu) +{ + pTmu->TF_STATUS = TMU_TF_STATUS_TF_150F(1U); +} + +/** + * @brief Check whether the flag for temperature over 125 Celsius is set + * + * @param pTmu the base address of the TMU instance + * @return true the temperature has exceeded 125 Celsius since last time W1C + * @return false the temperature has not exceeded 125 Celsius since TF is ready + */ +LOCAL_INLINE bool TMU_HWA_Get125Flag(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_125F_MASK) >> TMU_TF_STATUS_TF_125F_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the temperature over 125 Celsius flag + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_Clear125Flag(TMU_Type *const pTmu) +{ + pTmu->TF_STATUS = TMU_TF_STATUS_TF_125F(1U); +} + +/** + * @brief Check whether the Flag-based temperature sensor is ready + * + * @param pTmu the base address of the TMU instance + * @return true the Flag-based temperature sensor is ready + * @return false the Flag-based temperature sensor is not ready + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureReady(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_RDYF_MASK) >> TMU_TF_STATUS_TF_RDYF_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the Flag-based temperature sensor ready flag + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_ClearFlagTemperatureReady(TMU_Type *const pTmu) +{ + pTmu->TF_STATUS = TMU_TF_STATUS_TF_RDYF(1U); +} + +/** + * @brief Get the Vlotage-based temperature sensor ready interrupt flag + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor ready interrupt is enabled + * @return false Temperature sensor ready interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureReadyInterruptFlag(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_RDYF_IE_MASK) >> TMU_TV_CTRL_TV_RDYF_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Voltage-based temperature sensor over ready interrupt flag + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature sensor ready interrupt + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureReadyInterruptFlag(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_RDYF_IE_MASK) | TMU_TV_CTRL_TV_RDYF_IE(bEnable); +} + +/** + * @brief Get the Voltage-based temperature sensor startup counter + * + * @param pTmu the base address of the TMU instance + * @return u32TmpVal count of the startup + */ +LOCAL_INLINE uint8_t TMU_HWA_GetVoltageTemperatureCounter(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_START_CNT_MASK) >> TMU_TV_CTRL_TV_START_CNT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the Voltage-based temperature sensor startup counter + * + * @param pTmu the base address of the TMU instance + * @param u8Counter the startup counter + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureCounter(TMU_Type *const pTmu,uint8_t u8Counter) +{ + pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_START_CNT_MASK) | TMU_TV_CTRL_TV_START_CNT(u8Counter); +} +#endif + +#if TMU_SUPPORT_TV_ECMP +/** + * @brief Get the Vlotage-based temperature sensor compare flag 1 interrupt enable status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor compare flag 1 interrupt is enabled + * @return false Temperature sensor compare flag 1 interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureCompare1InterruptEnableStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_CMP1F_IE_MASK) >> TMU_TV_CTRL_TV_CMP1F_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the Vlotage-based temperature sensor compare flag 0 interrupt enable status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor compare flag 0 interrupt is enabled + * @return false Temperature sensor compare flag 0 interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureCompare0InterruptEnableStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_CMP0F_IE_MASK) >> TMU_TV_CTRL_TV_CMP0F_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Voltage-based temperature sensor compare flag 1 interrupt enable status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature sensor compare flag 1 interrupt + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureCompare1InterruptEnableStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_CMP1F_IE_MASK) | TMU_TV_CTRL_TV_CMP1F_IE(bEnable); +} + +/** + * @brief Set the Voltage-based temperature sensor compare flag 0 interrupt enable status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature sensor compare flag 0 interrupt + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureCompare0InterruptEnableStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_CMP0F_IE_MASK) | TMU_TV_CTRL_TV_CMP0F_IE(bEnable); +} +#endif + +#ifdef TMU_SUPPORT_STOP +/** + * @brief Configure the stop mode of the Voltage-based temperature sensor + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether the Voltage-based temperature sensor is run in stop mode + */ +LOCAL_INLINE void TMU_HWA_ConfigVoltageTemperatureStopMode(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_STOP_EN_MASK) | TMU_TV_CTRL_TV_STOP_EN(bEnable); +} +#endif + +/** + * @brief Get the Voltage-based temperature sensor enable status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor is on + * @return false Temperature sensor is off + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureEnableStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_EN_MASK) >> TMU_TV_CTRL_TV_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Voltage-based temperature sensor enable status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether the temperature sensor is on(1) or off(0) + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureEnableStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_EN_MASK) | TMU_TV_CTRL_TV_EN(bEnable); +} + +/** + * @brief Check whether the Voltage-based temperature sensor is ready + * + * @param pTmu the base address of the TMU instance + * @return true the Voltage-based temperature sensor is ready + * @return false the Voltage-based temperature sensor is not ready + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureReady(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_STATUS; + u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_RDYF_MASK) >> TMU_TV_STATUS_TV_RDYF_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +#if TMU_SUPPORT_TV_ECMP +/** + * @brief Get the Voltage-based temperature sensor compare status 1 + * + * @param pTmu the base address of the TMU instance + * @return true the real time status of ADC compare result 1 is assert + * @return false the real time status of ADC compare result 1 is de-assert + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureCompareStatus1(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_STATUS; + u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_CMP1_MASK) >> TMU_TV_STATUS_TV_CMP1_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the Voltage-based temperature sensor compare status 0 + * + * @param pTmu the base address of the TMU instance + * @return true the real time status of ADC compare result 0 is assert + * @return false the real time status of ADC compare result 0 is de-assert + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureCompareStatus0(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_STATUS; + u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_CMP0_MASK) >> TMU_TV_STATUS_TV_CMP0_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the Vlotage-based temperature sensor compare flag 1 + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor compare flag 1 is asserted + * @return false Temperature sensor compare flag 1 is not asserted + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureCompareFlag1(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_STATUS; + u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_CMP1F_MASK) >> TMU_TV_STATUS_TV_CMP1F_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the Vlotage-based temperature sensor compare flag 0 + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor compare flag 0 is asserted + * @return false Temperature sensor compare flag 0 is not asserted + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureCompareFlag0(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_STATUS; + u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_CMP0F_MASK) >> TMU_TV_STATUS_TV_CMP0F_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the Vlotage-based temperature sensor compare flag 1 + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_ClearVoltageTemperatureCompareFlag1(TMU_Type *const pTmu) +{ + pTmu->TV_STATUS = TMU_TV_STATUS_TV_CMP1F(1U); +} + +/** + * @brief Clear the Vlotage-based temperature sensor compare flag 0 + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_ClearVoltageTemperatureCompareFlag0(TMU_Type *const pTmu) +{ + pTmu->TV_STATUS = TMU_TV_STATUS_TV_CMP0F(1U); +} + +#endif + +#if !TMU_SUPPORT_TV_ECMP +/** + * @brief Clear the Voltage-based temperature sensor ready flag + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_ClearVoltageTemperatureReady(TMU_Type *const pTmu) +{ + pTmu->TV_STATUS = TMU_TV_STATUS_TV_RDYF(1U); +} + +/** + * @brief Get the TMU_TF_CTRL config + * + * @param pTmu the base address of the TMU instance + * @return uint32_t the TMU_TF_CTRL config + */ +LOCAL_INLINE uint32_t TMU_HWA_GetFlagTempCtrl(const TMU_Type *const pTmu) +{ + return pTmu->TF_CTRL; +} + +/** + * @brief Set the TMU_TF_CTRL config + * + * @param pTmu the base address of the TMU instance + * @param u32Config the TMU_TF_CTRL config + */ +LOCAL_INLINE void TMU_HWA_SetFlagTempCtrl(TMU_Type *const pTmu, uint32_t u32Config) +{ + pTmu->TF_CTRL = u32Config; +} +#endif + +/** + * @brief Get the TMU_TV_CTRL config + * + * @param pTmu the base address of the TMU instance + * @return uint32_t the TMU_TV_CTRL config + */ +LOCAL_INLINE uint32_t TMU_HWA_GetVoltageTempCtrl(const TMU_Type *const pTmu) +{ + return pTmu->TV_CTRL; +} + +/** + * @brief Set the TMU_TV_CTRL config + * + * @param pTmu the base address of the TMU instance + * @param u32Config the TMU_TV_CTRL config + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTempCtrl(TMU_Type *const pTmu, uint32_t u32Config) +{ + pTmu->TV_CTRL = u32Config; +} + +#ifdef TMU_SUPPORT_TRIM +/** + * @brief Get the TV_TRIM_TV_TCODE value + * + * @param pTmu the base address of the TMU instance + * @return uint32_t the TV_TRIM_TV_TCODE value + */ +LOCAL_INLINE uint32_t TMU_HWA_GetTemperatureCode(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_TRIM; + u32TmpVal = (u32TmpVal & TMU_TV_TRIM_TV_TCODE_MASK) >> TMU_TV_TRIM_TV_TCODE_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the TV_TRIM_TV_SLOPE value + * + * @param pTmu the base address of the TMU instance + * @return uint32_t the TV_TRIM_TV_SLOPE value + */ +LOCAL_INLINE uint32_t TMU_HWA_GetSlopeFactor(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_TRIM; + u32TmpVal = (u32TmpVal & TMU_TV_TRIM_TV_SLOPE_MASK) >> TMU_TV_TRIM_TV_SLOPE_SHIFT; + return u32TmpVal; +} +#endif +/** @}*/ + +#endif /* #if TMU_INSTANCE_COUNT > 0U */ + +#endif /* _HWA_TMU_H_ */ diff --git a/Inc/HwA_tpue.h b/Inc/HwA_tpue.h new file mode 100644 index 0000000..a4cbac5 --- /dev/null +++ b/Inc/HwA_tpue.h @@ -0,0 +1,2076 @@ +/** + * @file HwA_tpue.h + * @author Flagchip + * @brief FC7xxx TPUE hardware access layer + * @version 2.0.0 + * @date 2024-1-12 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + ******************************************************************************** */ +#ifndef _HWA_TPUE_H_ +#define _HWA_TPUE_H_ + +#include "device_header.h" + +#if TPU_INSTANCE_COUNT > 0U + +/********* Local typedef ************/ + +/** @brief TPU channel digital filter control type */ +typedef enum +{ + TPUE_TWO_SAMPLE_MODE = 0U, + TPUE_BYPASS_MODE = 1U, + TPUE_THREE_SAMPLE_MODE = 2U, + TPUE_CONTINUOUS_MODE = 3U +} TPUE_FilterCtrlType; + +/** @brief TPU filter clock source selection type */ +typedef enum +{ + TPUE_TPU_CLK_DIV2 = 0U, + TPUE_TPU_CLK = 1U +} TPUE_FilterClkSrcType; + +/** @brief TPU channel digital filter control type */ +typedef enum +{ + TPUE_SYSCLK_DIV_1 = 0U, + TPUE_SYSCLK_DIV_2 = 1U, + TPUE_SYSCLK_DIV_4 = 2U, + TPUE_SYSCLK_DIV_8 = 3U, + TPUE_SYSCLK_DIV_16 = 4U, + TPUE_SYSCLK_DIV_32 = 5U, + TPUE_SYSCLK_DIV_64 = 6U, + TPUE_SYSCLK_DIV_128 = 7U +} TPUE_FilterPrescalerCtrlType; + +/** @brief TPU TCR1 clock control mode type */ +typedef enum +{ + TPUE_TCR1CLK_CLK_SRC = 0U, + TPUE_TCR1CLK_UPDOWN_CNT_MODE = 3U, + TPUE_TCR1CLK_CLK_SRC_TPUCLKDIV2 = 4U, + TPUE_TCR1CLK_SRC_TPUCLK = 5U +} TPUE_TCR1ClkCtrlModeType; + +/** @brief TPU angle tick gen clk type */ +typedef enum +{ + TPUE_TCR1_PRESCAL_OUTPUT = 0U, + TPUE_TCR2_PRESCAL_OUTPUT = 1U +} TPUE_AngleTickGenClkType; + +/** @brief TPU Angle Mode Selection type */ +typedef enum +{ + TPUE_TCR2_TIMEBASE_EAC_DISABLE = 0U, + TPUE_TOOTHSIGNAL_AS_TCRCLK_TOOTH_CH_0 = 1U, + TPUE_TOOTHSIGNAL_AS_CH1INPUT_TOOTH_CH_1 = 2U, + TPUE_TOOTHSIGNAL_AS_CH1INPUT_TOOTH_CH_2 = 3U +} TPUE_AngleModeSel; + +/** @brief TPU Angle Mode Selection type */ +typedef enum +{ + TPUE_TWO_SAMPLE_MODE_TPU_CLK_DIV2 = 0U, + TPUE_TWO_SAMPLE_MODE_CH_CLK = 1U, + TPUE_INTEGRATOR_MODE_TPU_CLK_DIV2 = 2U, + TPUE_INTEGRATOR_MODE_CH_CLK = 3U +} TPUE_TCRClkFilterType; + +/** @brief TPU TCR2 clock control mode0 type */ +typedef enum +{ + TPUE_GATED_DIV8_CLK = 0U, + TPUE_RISE_TRANSITION_INCREMENT_TCR2_PRESCALER = 1U, + TPUE_FALL_TRANSITION_INCREMENT_TCR2_PRESCALER = 2U, + TPUE_DIV8_CLK = 4U, + TPUE_UPDOWN_CNT_MODE = 5U, + TPUE_FROZEN = 7U +} TPUE_TCR1ClkCtrlMode0Type; + +typedef enum +{ + TPUE_RSING_EDGE = 1U, + TPUE_FALLING_EDGE = 2U, + TPUE_BOTH_EDGES = 3U, + TPUE_NO_EDGE = 6U, +} TPUE_TCR1ClkCtrlMode1Type; + +/** @brief Missing Tooth Counter */ +typedef enum +{ + TPUE_NOT_A_MISSING_TOOTH = 0U, + TPUE_ONE_MISSING_TOOTH = 1U, + TPUE_TWO_MISSING_TOOTH = 2U, + TPUE_THREE_MISSING_TOOTH = 3U, +} TPUE_MissToothCntType; + +/** @brief Channel Trigger Configuration */ +typedef enum +{ + TPUE_DISABLED = 0U, + TPUE_ANY_EVENT_GATED_BY_MSRTSR = 2U, + TPUE_HSA_EVENT_ON_FLEXCORE_MODE = 3U, + TPUE_MRL1_EVENT_NOT_GATED_BY_MSR = 4U, + TPUE_MRL2_EVENT_NOT_GATED_BY_MSR = 5U, + TPUE_MRL1_OR_MRL2_EVENT_NOT_GATED_BY_MSR = 6U, + TPUE_MRL1_AND_MRL2_EVENT_NOT_GATED_BY_MSR = 7U, + TPUE_TDL1_OR_TDL2_EVENT_NOT_GATED_BY_TSR = 8U, + TPUE_TDL1_AND_TDL2_EVENT_NOT_GATED_BY_TSR = 9U, + TPUE_EVENT_EQUAL_TO_CH_DO_LEVEL = 10U, + TPUE_EVENT_NEGATIVE_TO_CH_DO_LEVEL = 11U, + TPUE_EVENT_EQUAL_TO_CH_DO_PART1_LEVEL = 12U, + TPUE_EVENT_EQUAL_TO_CH_DO_PART2_LEVEL = 13U, + TPUE_EVENT_EQUAL_TO_CH_IND_LEVEL = 14U, + TPUE_EVENT_EQUAL_TO_CH_IND_LATCH_LEVEL = 15U, +} TPUE_ChTrigCFGType; + +/** @brief Filter Grade for 7 value in 1 loop */ +typedef enum +{ + TPUE_FILTER_DISABLE = 0U, + TPUE_FILTER_LOW = 1U, + TPUE_FILTER_MIDDLE = 2U, + TPUE_FILTER_HIGH = 3U, +} TPUE_FilterGradeType; + +/** @brief Channel event triggered interrupt priority */ +typedef enum +{ + TPUE_PRIORITY_DISABLE = 0U, + TPUE_PRIORITY_LOW = 1U, + TPUE_PRIORITY_MIDDLE = 2U, + TPUE_PRIORITY_HIGH = 3U, +} TPUE_EventIntPriorityType; + +/** @brief Channel time base selection of part 1. */ +typedef enum +{ + TPUE_GREATER_OR_EQUAL_CAPBASE_TCR1_MATCHBASE_TCR1 = 0U, + TPUE_GREATER_OR_EQUAL_CAPBASE_TCR1_MATCHBASE_TCR2 = 1U, + TPUE_GREATER_OR_EQUAL_CAPBASE_TCR2_MATCHBASE_TCR1 = 2U, + TPUE_GREATER_OR_EQUAL_CAPBASE_TCR2_MATCHBASE_TCR2 = 3U, + TPUE_EQUAL_ONLY_CAPBASE_TCR1_MATCHBASE_TCR1 = 4U, + TPUE_EQUAL_ONLY_CAPBASE_TCR1_MATCHBASE_TCR2 = 5U, + TPUE_EQUAL_ONLY_CAPBASE_TCR2_MATCHBASE_TCR1 = 6U, + TPUE_EQUAL_ONLY_CAPBASE_TCR2_MATCHBASE_TCR2 = 7U, +} TPUE_TimeBaseSelctionType; + +/** @brief Channel Input Pin Action Control. */ +typedef enum +{ + TPUE_NO_TRANSITIONS = 0U, + TPUE_DETECT_RISING_EDGE_ONLY = 1U, + TPUE_DETECT_FALLING_EDGE_ONLY = 2U, + TPUE_DETECT_EITHER_EDGE_ONLY = 3U, + TPUE_DETECT_SIGNAL_0_ON_MATCH = 4U, + TPUE_DETECT_SIGNAL_1_ON_MATCH = 5U, +} TPUE_IPACType; + +/** @brief Channel output Pin Action Control. */ +typedef enum +{ + TPUE_NO_CHANGE_OUTPUT = 0U, + TPUE_MATCH_SET_OUTPUT_HIGH = 1U, + TPUE_MATCH_SET_OUTPUT_LOW = 2U, + TPUE_MATCH_TOGGLE_OUTPUT = 3U, + TPUE_TRANSITION_SET_OUTPUT_HIGH = 4U, + TPUE_TRANSITION_SET_OUTPUT_LOW = 5U, + TPUE_TRANSITION_TOGGLE_OUTPUT = 6U, + TPUE_NO_CHANGE_OPAC = 7U, +} TPUE_OPACType; + +/** @brief PDCM Encoding. */ +typedef enum +{ + TPUE_EM_B_ST = 0U, + TPUE_EM_B_DT = 1U, + TPUE_EM_NB_ST = 2U, + TPUE_EM_NB_DT = 3U, + TPUE_M2_ST = 4U, + TPUE_M2_DT = 5U, + TPUE_BM_ST = 6U, + TPUE_BM_DT = 7U, + TPUE_M2_O_ST = 8U, + TPUE_M2_O_DT = 9U, + TPUE_SM_ST = 12U, + TPUE_SM_DT = 13U, + TPUE_SM_ST_E = 14U, +} TPUE_PDCMEncodeType; + +/********* Local inline function ************/ +/** + * @brief Get channel digital filter control + * + */ +LOCAL_INLINE TPUE_FilterCtrlType TPU_E_HWA_GetFilterCtrl(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_CDFC_MASK) >> TPU_E_GCR_CR_CDFC_SHIFT; + return (TPUE_FilterCtrlType)u32TmpVal; +} + +/** + * @brief Set channel digital filter control + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFilterCtrl(TPU_E_Type *const pTPUE, TPUE_FilterCtrlType eControlMode) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_CDFC_MASK) | TPU_E_GCR_CR_CDFC(eControlMode); +} + +/** + * @brief Get filter clock source + * + */ +LOCAL_INLINE TPUE_FilterClkSrcType TPU_E_HWA_GetFilterClkSrc(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_FCSS_MASK) >> TPU_E_GCR_CR_FCSS_SHIFT; + return (TPUE_FilterClkSrcType)u32TmpVal; +} + +/** + * @brief Set filter clock source + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFilterClkSrc(TPU_E_Type *const pTPUE, TPUE_FilterClkSrcType eClkSrc) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_FCSS_MASK) | TPU_E_GCR_CR_FCSS(eClkSrc); +} + +/** + * @brief Get filter prescaler clock control + * + */ +LOCAL_INLINE TPUE_FilterPrescalerCtrlType TPU_E_HWA_GetFilterPrescaler(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_FPSCK_MASK) >> TPU_E_GCR_CR_FPSCK_SHIFT; + return (TPUE_FilterPrescalerCtrlType)u32TmpVal; +} + +/** + * @brief Get filter prescaler clock control + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFilterPrescaler(TPU_E_Type *const pTPUE, TPUE_FilterPrescalerCtrlType ePrescaler) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_FPSCK_MASK) | TPU_E_GCR_CR_FPSCK(ePrescaler); +} + +/** + * @brief Whether channel function is disabled in Stop mode + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetFuncDisableInStopMode(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_HALT_CH_MASK) >> TPU_E_GCR_CR_HALT_CH_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable channel function is disabled or normal in Stop mode + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFuncDisableInStopMode(TPU_E_Type *const pTPUE, bool bEnable) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_HALT_CH_MASK) | TPU_E_GCR_CR_HALT_CH(bEnable); +} + +/** + * @brief Whether channel function is disabled in Stop mode + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTimeBaseCntStopInStopMode(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_HALT_TB_MASK) >> TPU_E_GCR_CR_HALT_TB_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable channel function is disabled or normal in Stop mode + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTimeBaseCntStopInStopMode(TPU_E_Type *const pTPUE, bool bEnable) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_HALT_TB_MASK) | TPU_E_GCR_CR_HALT_TB(bEnable); +} + +/** + * @brief Enable channel function is disabled or normal in Stop mode + * + */ +LOCAL_INLINE void TPU_E_HWA_TrigReset(TPU_E_Type *const pTPUE) +{ + pTPUE->GCR_SRR = 0xFC005AFEU; +} + +/** + * @brief Get service request status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetSRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VSR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin input status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetInputStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VIR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin output status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetoutputStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VOR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin output enable status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetoutputEnStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VOBR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL1 status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMRL1Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VM1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL2 status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMRL2Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VM2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL1 status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTDL1Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VT1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL2 status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTDL2Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VT2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL1 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMRL1EventStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_EM1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL2 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMRL2EventStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_EM2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL1 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTDL1eventStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_ET1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL2 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTDL2eventStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_ET2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get HAS status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetHSRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VHSR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Filter Grade + * + */ +LOCAL_INLINE TPUE_FilterGradeType TPU_E_HWA_GetFilterGrade(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_AFGR & TPU_E_GCR_AFGR_FLT_GRD_MASK) >> TPU_E_GCR_AFGR_FLT_GRD_SHIFT; + return (TPUE_FilterGradeType)u32TmpVal; +} + +/** + * @brief Set Filter Grade + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFilterGrade(TPU_E_Type *const pTPUE, TPUE_FilterGradeType eGrade) +{ + pTPUE->GCR_AFGR = (pTPUE->GCR_AFGR & ~TPU_E_GCR_AFGR_FLT_GRD_MASK) | TPU_E_GCR_AFGR_FLT_GRD(eGrade); +} + +/** + * @brief Get Filter Grade setting results + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetFilterGradeCFGErrFlg(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_ASR & TPU_E_GCR_ASR_ERROR_MASK) >> TPU_E_GCR_ASR_ERROR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear filter grade setting results + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearFilterGradeCFGErrFlg(TPU_E_Type *const pTPUE) +{ + pTPUE->GCR_ASR = (pTPUE->GCR_ASR & ~TPU_E_GCR_ASR_ERROR_MASK) | TPU_E_GCR_ASR_ERROR(1U); +} + +/** + * @brief Get endian configuration + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetEndianCFG(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_ASR & TPU_E_GCR_ASR_ENDIAN_MASK) >> TPU_E_GCR_ASR_ENDIAN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set endian configuration + * + */ +LOCAL_INLINE void TPU_E_HWA_SetEndianCFG(TPU_E_Type *const pTPUE) +{ + pTPUE->GCR_ASR = (pTPUE->GCR_ASR & ~TPU_E_GCR_ASR_ENDIAN_MASK) | TPU_E_GCR_ASR_ENDIAN(1U); +} + +/** + * @brief Get channel function entry table select + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetEntryFuncSel(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_AID & TPU_E_GCR_AID_ETCS_MASK) >> TPU_E_GCR_AID_ETCS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get channel function entry table condition + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetEntryFuncCond(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_AID & TPU_E_GCR_AID_COND_MASK) >> TPU_E_GCR_AID_COND_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get channel ID info + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetChIDInfo(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_AID & TPU_E_GCR_AID_ID_MASK) >> TPU_E_GCR_AID_ID_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get TCR1 prescaler. + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetTCR1Prescaler(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR1P_MASK) >> TPU_E_TBR_CR_TCR1P_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get TCR1 prescaler. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR1Prescaler(TPU_E_Type *const pTPUE, uint8_t u8Prescaler) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCR1P_MASK) | TPU_E_TBR_CR_TCR1P(u8Prescaler); +} + +/** + * @brief Get TCR1 clock control. + * + */ +LOCAL_INLINE TPUE_TCR1ClkCtrlModeType TPU_E_HWA_GetTCR1ClkControl(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR1CTL_MASK) >> TPU_E_TBR_CR_TCR1CTL_SHIFT; + return (TPUE_TCR1ClkCtrlModeType)u32TmpVal; +} + +/** + * @brief Set TCR1 clock control. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR1ClkControl(TPU_E_Type *const pTPUE, TPUE_TCR1ClkCtrlModeType eMode) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCR1CTL_MASK) | TPU_E_TBR_CR_TCR1CTL(eMode); +} + +/** + * @brief Get TCR2 prescaler. + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetTCR2Prescaler(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR2P_MASK) >> TPU_E_TBR_CR_TCR2P_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set TCR2 prescaler. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR2Prescaler(TPU_E_Type *const pTPUE, uint8_t ePrescaler) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCR2P_MASK) | TPU_E_TBR_CR_TCR2P(ePrescaler); +} + +/** + * @brief Get Angle tick generator clock. + * + */ +LOCAL_INLINE TPUE_AngleTickGenClkType TPU_E_HWA_GetATGC(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_ATGC_MASK) >> TPU_E_TBR_CR_ATGC_SHIFT; + return (TPUE_AngleTickGenClkType)u32TmpVal; +} + +/** + * @brief Set Angle tick generator clock. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetATGC(TPU_E_Type *const pTPUE, TPUE_AngleTickGenClkType eSrc) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_ATGC_MASK) | TPU_E_TBR_CR_ATGC(eSrc); +} + +/** + * @brief Get Angle Mode Selection. + * + */ +LOCAL_INLINE TPUE_AngleModeSel TPU_E_HWA_GetAM(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_AM_MASK) >> TPU_E_TBR_CR_AM_SHIFT; + return (TPUE_AngleModeSel)u32TmpVal; +} + +/** + * @brief Set Angle Mode Selection. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetAM(TPU_E_Type *const pTPUE, TPUE_AngleModeSel eMode) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_AM_MASK) | TPU_E_TBR_CR_AM(eMode); +} + +/** + * @brief Get TCRCLK signal Filter Control. + * + */ +LOCAL_INLINE TPUE_TCRClkFilterType TPU_E_HWA_GetTCRClkFilter(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCRCF_MASK) >> TPU_E_TBR_CR_TCRCF_SHIFT; + return (TPUE_TCRClkFilterType)u32TmpVal; +} + +/** + * @brief Set TCRCLK signal Filter Control. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCRClkFilter(TPU_E_Type *const pTPUE, TPUE_TCRClkFilterType eMode) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCRCF_MASK) | TPU_E_TBR_CR_TCRCF(eMode); +} + +/** + * @brief Get TCR2 clock control. + * + */ +LOCAL_INLINE TPUE_TCR1ClkCtrlMode0Type TPU_E_HWA_GetTCR2ClkControlAM0(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR2CTL_MASK) >> TPU_E_TBR_CR_TCR2CTL_SHIFT; + return (TPUE_TCR1ClkCtrlMode0Type)u32TmpVal; +} + +/** + * @brief Get TCR2 clock control. + * + */ +LOCAL_INLINE TPUE_TCR1ClkCtrlMode1Type TPU_E_HWA_GetTCR2ClkControlAM1(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR2CTL_MASK) >> TPU_E_TBR_CR_TCR2CTL_SHIFT; + return (TPUE_TCR1ClkCtrlMode1Type)u32TmpVal; +} + +/** + * @brief Set TCR2 clock control. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR2ClkControlAM1(TPU_E_Type *const pTPUE, TPUE_TCR1ClkCtrlMode1Type eMode) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCR2CTL_MASK) | TPU_E_TBR_CR_TCR2CTL(eMode); +} + +/** + * @brief Get TCR1 cnt value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetTCR1CntVal(const TPU_E_Type *const pTPUE) +{ + return pTPUE->TBR_T1R; +} + +/** + * @brief Get TCR2 cnt value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetTCR2CntVal(const TPU_E_Type *const pTPUE) +{ + return pTPUE->TBR_T2R; +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_E_HWA_NotLastTooth(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_TPR & TPU_E_TBR_TPR_LAST_MASK) >> TPU_E_TBR_TPR_LAST_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Set last tooth indication. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetLastTooth(TPU_E_Type *const pTPUE, bool bEnable) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_LAST_MASK) | TPU_E_TBR_TPR_LAST(bEnable); +} + +/** + * @brief Get missing tooth counter. + * + */ +LOCAL_INLINE TPUE_MissToothCntType TPU_E_HWA_GetMissingTooth(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_TPR & TPU_E_TBR_TPR_MISSCNT_MASK) >> TPU_E_TBR_TPR_MISSCNT_SHIFT; + return (TPUE_MissToothCntType)u32TmpVal; +} + +/** + * @brief Set missing tooth counter. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetMissingTooth(TPU_E_Type *const pTPUE, TPUE_MissToothCntType eCnt) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_MISSCNT_MASK) | TPU_E_TBR_TPR_MISSCNT(eCnt); +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_E_HWA_NoInsertTooth(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_TPR & TPU_E_TBR_TPR_IPH_MASK) >> TPU_E_TBR_TPR_IPH_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Set last tooth indication to exit halt mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_InsertPhyTooth(TPU_E_Type *const pTPUE) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_IPH_MASK) | TPU_E_TBR_TPR_IPH(1U); +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_E_HWA_NoForceEACHalt(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_TPR & TPU_E_TBR_TPR_HOLD_MASK) >> TPU_E_TBR_TPR_HOLD_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE void TPU_E_HWA_HaltEAC(TPU_E_Type *const pTPUE) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_HOLD_MASK) | TPU_E_TBR_TPR_HOLD(1U); +} + +/** + * @brief Get angle ticks number. + * + */ +LOCAL_INLINE uint16_t TPU_E_HWA_GetAngleTicksVal(const TPU_E_Type *const pTPUE) +{ + return (uint16_t)(pTPUE->TBR_TPR & TPU_E_TBR_TPR_TICKS_MASK) >> TPU_E_TBR_TPR_TICKS_SHIFT; +} + +/** + * @brief Get angle ticks number. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetAngleTicksVal(TPU_E_Type *const pTPUE, uint16_t u16Tick) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_TICKS_MASK) | TPU_E_TBR_TPR_TICKS(u16Tick); +} + +/** + * @brief Get the integer part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetIntergerPerAngleTick(const TPU_E_Type *const pTPUE) +{ + return (pTPUE->TBR_TRR & TPU_E_TBR_TRR_INTEGER_MASK) >> TPU_E_TBR_TRR_INTEGER_SHIFT; +} + +/** + * @brief Set the integer part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetIntergerPerAngleTick(TPU_E_Type *const pTPUE, uint16_t u16Integer) +{ + pTPUE->TBR_TRR = (pTPUE->TBR_TRR & ~TPU_E_TBR_TRR_INTEGER_MASK) | TPU_E_TBR_TRR_INTEGER(u16Integer); +} + +/** + * @brief Get the fraction part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetFractionPerAngleTick(const TPU_E_Type *const pTPUE) +{ + return (pTPUE->TBR_TRR & TPU_E_TBR_TRR_FRACTION_MASK) >> TPU_E_TBR_TRR_FRACTION_SHIFT; +} + +/** + * @brief Set the fraction part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFractionPerAngleTick(TPU_E_Type *const pTPUE, uint16_t u16Fraction) +{ + pTPUE->TBR_TRR = (pTPUE->TBR_TRR & ~TPU_E_TBR_TRR_FRACTION_MASK) | TPU_E_TBR_TRR_FRACTION(u16Fraction); +} + +/** + * @brief Get TCR1 overflow flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTCR1Overflow(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_T1MR & TPU_E_TBR_T1MR_OVF_MASK) >> TPU_E_TBR_T1MR_OVF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear TCR1 overflow flag. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearTCR1Overflow(TPU_E_Type *const pTPUE) +{ + pTPUE->TBR_T1MR = (pTPUE->TBR_T1MR | TPU_E_TBR_T1MR_OVF_MASK); +} + +/** + * @brief Get TCR1 IRQ enable flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTCR1OVFIRQEn(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_T1MR & TPU_E_TBR_T1MR_IRQ_EN_MASK) >> TPU_E_TBR_T1MR_IRQ_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TCR1 IRQ enable flag. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableTCR1OVFIRQ(TPU_E_Type *const pTPUE, bool bEn) +{ + pTPUE->TBR_T1MR = (pTPUE->TBR_T1MR & ~TPU_E_TBR_T1MR_IRQ_EN_MASK) | TPU_E_TBR_T1MR_IRQ_EN(bEn); +} + +/** + * @brief Get the maximum value of TCR1 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetTCR1MaxCnt(const TPU_E_Type *const pTPUE) +{ + return (pTPUE->TBR_T1MR & TPU_E_TBR_T1MR_MAX_MASK) >> TPU_E_TBR_T1MR_MAX_SHIFT; +} + +/** + * @brief Get the maximum value of TCR1 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR1MaxCnt(TPU_E_Type *const pTPUE, uint32_t u32MaxCnt) +{ + pTPUE->TBR_T1MR = (pTPUE->TBR_T1MR & ~TPU_E_TBR_T1MR_MAX_MASK) | TPU_E_TBR_T1MR_MAX(u32MaxCnt); +} + +/** + * @brief Get TCR2 overflow flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTCR2Overflow(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_T2MR & TPU_E_TBR_T2MR_OVF_MASK) >> TPU_E_TBR_T2MR_OVF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear TCR2 overflow flag. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearTCR2Overflow(TPU_E_Type *const pTPUE) +{ + pTPUE->TBR_T2MR = (pTPUE->TBR_T2MR | TPU_E_TBR_T2MR_OVF_MASK); +} + +/** + * @brief Get TCR2 IRQ enable flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTCR2OVFIRQEnable(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_T2MR & TPU_E_TBR_T2MR_IRQ_EN_MASK) >> TPU_E_TBR_T2MR_IRQ_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable TCR2 IRQ enable flag. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableTCR2OVFIRQ(TPU_E_Type *const pTPUE, bool bEn) +{ + pTPUE->TBR_T2MR = (pTPUE->TBR_T2MR & ~TPU_E_TBR_T2MR_IRQ_EN_MASK) | TPU_E_TBR_T2MR_IRQ_EN(bEn); +} + +/** + * @brief Get the maximum value of TCR2 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetTCR2MaxCnt(const TPU_E_Type *const pTPUE) +{ + return (pTPUE->TBR_T2MR & TPU_E_TBR_T2MR_MAX_MASK) >> TPU_E_TBR_T2MR_MAX_SHIFT; +} + +/** + * @brief Set the maximum value of TCR2 counter in TCR2 updown mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR2MaxCnt(TPU_E_Type *const pTPUE, uint32_t u32MaxCnt) +{ + pTPUE->TBR_T2MR = (pTPUE->TBR_T2MR & ~TPU_E_TBR_T2MR_MAX_MASK) | TPU_E_TBR_T2MR_MAX(u32MaxCnt); +} + +/** + * @brief Get channel event triggered interrupt enable flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEventIntEnable(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CIE_MASK) >> TPU_E_CHn_CR_CIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable channel event triggered interrupt. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableChEventInt(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CIE_MASK) | TPU_E_CHn_CR_CIE(bEn); +} + +/** + * @brief Get channel event triggered interrupt priority. + * + */ +LOCAL_INLINE TPUE_EventIntPriorityType TPU_E_HWA_GetChEventIntPriority(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CPR_MASK) >> TPU_E_CHn_CR_CPR_SHIFT; + return (TPUE_EventIntPriorityType)u32TmpVal; +} + +/** + * @brief Set channel event triggered interrupt priority. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEventIntPriority(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_EventIntPriorityType ePriority) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CPR_MASK) | TPU_E_CHn_CR_CPR(ePriority); +} + +/** + * @brief Get channel Filter Bypass + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChFilterBypassEnable(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CFB_MASK) >> TPU_E_CHn_CR_CFB_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel Filter Bypass + * + */ +LOCAL_INLINE void TPU_E_HWA_OpenChFilter(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CFB_MASK) | TPU_E_CHn_CR_CFB(bEn); +} + +/** + * @brief Get channel entry function + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetChEntryFunc(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CFS_MASK) >> TPU_E_CHn_CR_CFS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set channel entry function + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryFunc(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint8_t u8EntryFunc) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CFS_MASK) | TPU_E_CHn_CR_CFS(u8EntryFunc); +} + +/** + * @brief Get channel entry table pin direction + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEntryTblPinDirOutput(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_ETPD_MASK) >> TPU_E_CHn_CR_ETPD_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel entry table pin direction + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryTblPinDirOutput(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_ETPD_MASK) | TPU_E_CHn_CR_ETPD(bEn); +} + +/** + * @brief Get channel entry table condition select + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEntryTblCondSelAlt(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_ECTS_MASK) >> TPU_E_CHn_CR_ECTS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel entry table condition select + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryTblCondSelAlt(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_ECTS_MASK) | TPU_E_CHn_CR_ECTS(bEn); +} + +/** + * @brief Get channel entry table flag1 + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEntryTblflag1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_FLG1_MASK) >> TPU_E_CHn_CR_FLG1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel entry table flag1 + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryTblflag1(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_FLG1_MASK) | TPU_E_CHn_CR_FLG1(bEn); +} + +/** + * @brief Get channel entry table flag0 + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEntryTblflag0(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_FLG0_MASK) >> TPU_E_CHn_CR_FLG0_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel entry table flag0 + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryTblflag0(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_FLG0_MASK) | TPU_E_CHn_CR_FLG0(bEn); +} + +/** + * @brief Get channel output polarity + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChOutputHigh(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_OPOL_MASK) >> TPU_E_CHn_CR_OPOL_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel output polarity + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChOutputActiveHigh(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_OPOL_MASK) | TPU_E_CHn_CR_OPOL(bEn); +} + +/** + * @brief Get channel output disable + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChOutputDisable(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_ODIS_MASK) >> TPU_E_CHn_CR_ODIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel output disable + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChOutputDisable(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_ODIS_MASK) | TPU_E_CHn_CR_ODIS(bEn); +} + +/** + * @brief Get channel HSA index. + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetChHSAIdx(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CHSA_MASK) >> TPU_E_CHn_CR_CHSA_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set channel HSA index. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChHSAIdx(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint8_t u8HSAIdx) +{ + pTPUE->CH[u8Channel].CR = ((pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CHSA_MASK) | TPU_E_CHn_CR_CHSA(u8HSAIdx)); +} + +/** + * @brief Get channel event trigger interrupt status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEventTrigISRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CIS_MASK) >> TPU_E_CHn_SR_CIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel host service request (HSR) status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChHSRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CHRS_MASK) >> TPU_E_CHn_SR_CHRS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Channel HSR Info & Index . + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetChHSRIdx(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CHRI_MASK) >> TPU_E_CHn_SR_CHRI_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get channel event as interrupt status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEventReqISRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CEIS_MASK) >> TPU_E_CHn_SR_CEIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel event as interrupt status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChDMAReq(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CHDS_MASK) >> TPU_E_CHn_SR_CHDS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel trigger status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTrigStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CTS_MASK) >> TPU_E_CHn_SR_CTS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel host service acknowledge (HSA) interrupt status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChHSAReqStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CHAS_MASK) >> TPU_E_CHn_SR_CHAS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear channel interrupt by event. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearChEventISRFlg(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].SCR = TPU_E_CHn_SCR_CISC_MASK; +} + +/** + * @brief Clear channel HSA Dma. + * + */ +LOCAL_INLINE void TPU_E_HWA_ChReqDMA(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].SCR = TPU_E_CHn_SCR_CHDT_MASK; +} + +/** + * @brief Clear channel HSA. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearChHSAISR(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].SCR = TPU_E_CHn_SCR_CHAT_MASK; +} + +/** + * @brief Clear channel HSR. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearChHSR(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].SCR = TPU_E_CHn_SCR_CHRC_MASK; +} + +/** + * @brief Get channel service request. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChServiceReq(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_CSR_MASK) >> TPU_E_CHn_EFR_CSR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel service request to HOST. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChServiceReqToHost(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_CHSR_MASK) >> TPU_E_CHn_EFR_CHSR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 event status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch1Event(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_EMRL1_MASK) >> TPU_E_CHn_EFR_EMRL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 event status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch2Event(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_EMRL2_MASK) >> TPU_E_CHn_EFR_EMRL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get transition detect latch 1 event status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTransDetectLatch1Event(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_ETDL1_MASK) >> TPU_E_CHn_EFR_ETDL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get transition detect latch 2 event status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTransDetectLatch2Event(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_ETDL2_MASK) >> TPU_E_CHn_EFR_ETDL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch1En(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_MRLE1_MASK) >> TPU_E_CHn_EFR_MRLE1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch2En(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_MRLE2_MASK) >> TPU_E_CHn_EFR_MRLE2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch1Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_MRL1_MASK) >> TPU_E_CHn_EFR_MRL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch2Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_MRL2_MASK) >> TPU_E_CHn_EFR_MRL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Transition Detect latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTransDetectLatch1Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_TDL1_MASK) >> TPU_E_CHn_EFR_TDL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Transition Detect latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTransDetectLatch2Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_TDL2_MASK) >> TPU_E_CHn_EFR_TDL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get comparator selection for time base selection. + * + */ +LOCAL_INLINE TPUE_TimeBaseSelctionType TPU_E_HWA_GetChTBS1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_TBS1_MASK) >> TPU_E_CHn_CR2_TBS1_SHIFT; + return (TPUE_TimeBaseSelctionType)u32TmpVal; +} + +/** + * @brief Set comparator selection for time base selection. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChTBS1(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_TimeBaseSelctionType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_TBS1_MASK) | TPU_E_CHn_CR2_TBS1(eType); +} + +/** + * @brief Get pin state input. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChPinStateInputHigh(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_PSTI_MASK) >> TPU_E_CHn_CR2_PSTI_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin state output. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChPinStateOutputHigh(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_PSTO_MASK) >> TPU_E_CHn_CR2_PSTO_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin request service sample. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChPinReqSrvSample(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_PRSS_MASK) >> TPU_E_CHn_CR2_PRSS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Input Pin Action Control of Part 1 . + * + */ +LOCAL_INLINE TPUE_IPACType TPU_E_HWA_GetIPAC1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_IPAC1_MASK) >> TPU_E_CHn_CR2_IPAC1_SHIFT; + return (TPUE_IPACType)u32TmpVal; +} + +/** + * @brief Set Input Pin Action Control of Part 1 . + * + */ +LOCAL_INLINE void TPU_E_HWA_SetIPAC1(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_IPACType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_IPAC1_MASK) | TPU_E_CHn_CR2_IPAC1(eType); +} + +/** + * @brief Get Output Buffer Enable. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChOutputBufEn(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_OBE_MASK) >> TPU_E_CHn_CR2_OBE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Output Buffer Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableChOutputBuf(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEnable) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_OBE_MASK) | TPU_E_CHn_CR2_OBE(bEnable); +} + +/** + * @brief Get Output Pin Action Control of Part 1. + * + */ +LOCAL_INLINE TPUE_OPACType TPU_E_HWA_GetOPAC1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_OPAC1_MASK) >> TPU_E_CHn_CR2_OPAC1_SHIFT; + return (TPUE_OPACType)u32TmpVal; +} + +/** + * @brief Set Input Pin Action Control of Part 2 . + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOPAC1(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_OPACType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_OPAC1_MASK) | TPU_E_CHn_CR2_OPAC1(eType); +} + +/** + * @brief Get comparator selection for time base selection. + * + */ +LOCAL_INLINE TPUE_TimeBaseSelctionType TPU_E_HWA_GetChTBS2(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_TBS2_MASK) >> TPU_E_CHn_CR2_TBS2_SHIFT; + return (TPUE_TimeBaseSelctionType)u32TmpVal; +} + +/** + * @brief Set comparator selection for time base selection. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChTBS2(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_TimeBaseSelctionType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_TBS2_MASK) | TPU_E_CHn_CR2_TBS2(eType); +} + +/** + * @brief Get Input Pin Action Control of Part 2. + * + */ +LOCAL_INLINE TPUE_IPACType TPU_E_HWA_GetIPAC2(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_IPAC2_MASK) >> TPU_E_CHn_CR2_IPAC2_SHIFT; + return (TPUE_IPACType)u32TmpVal; +} + +/** + * @brief Set Input Pin Action Control of Part 2. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetIPAC2(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_IPACType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_IPAC2_MASK) | TPU_E_CHn_CR2_IPAC2(eType); +} + +/** + * @brief Get Output Pin Action Control of Part 1. + * + */ +LOCAL_INLINE TPUE_OPACType TPU_E_HWA_GetOPAC2(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_OPAC2_MASK) >> TPU_E_CHn_CR2_OPAC2_SHIFT; + return (TPUE_OPACType)u32TmpVal; +} + +/** + * @brief Set Input Pin Action Control of Part 2 . + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOPAC2(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_OPACType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_OPAC2_MASK) | TPU_E_CHn_CR2_OPAC2(eType); +} + +/** + * @brief Clear sevice request write enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearSrvReqEn(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR | TPU_E_CHn_MR_SRIE_MASK); +} + +/** + * @brief Get service request inhibit latch. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetSrvReqEn(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_SRI_MASK) >> TPU_E_CHn_MR_SRI_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Set service request inhibit latch. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableSrvReq(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + if (bEn) + { + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & ~TPU_E_CHn_MR_SRI_MASK) | TPU_E_CHn_MR_SRIE_MASK; + } + else + { + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR | TPU_E_CHn_MR_SRI_MASK) | TPU_E_CHn_MR_SRIE_MASK; + } + +} + +/** + * @brief Clear PDCM Write Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearPDCMEn(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR | TPU_E_CHn_MR_PDME_MASK); +} + +/** + * @brief Get Predefined Channel Mode. + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetPDCM(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_PDCM_MASK) >> TPU_E_CHn_MR_PDCM_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set Predefined Channel Mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetPDCM(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_PDCMEncodeType eMode) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & ~TPU_E_CHn_MR_PDCM_MASK) | TPU_E_CHn_MR_PDCM(eMode) | TPU_E_CHn_MR_PDME_MASK; +} + +/** + * @brief Get transition continuous capture enable. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTransContinueEn(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_TCCE_MASK) >> TPU_E_CHn_MR_TCCE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set Predefined Channel Mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableTransContinue(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & ~TPU_E_CHn_MR_TCCE_MASK) | TPU_E_CHn_MR_TCCE(bEn); +} + +/** + * @brief Clear UDCM Write Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearUDCMWriteEn(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR | TPU_E_CHn_MR_UDME_MASK); +} + +/** + * @brief Get User Defined Channel Mode. + * + */ +LOCAL_INLINE uint16_t TPU_E_HWA_GetUDCM(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_UDCM_MASK) >> TPU_E_CHn_MR_UDCM_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set User Defined Channel Mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableUDCM(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint16_t u16Mode) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & ~TPU_E_CHn_MR_UDCM_MASK) | TPU_E_CHn_MR_UDCM(u16Mode) | TPU_E_CHn_MR_UDME_MASK; +} + +/** + * @brief Clear Match Configuration Enable part1. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatchEn1(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 | TPU_E_CHn_ER1_ERW_MASK); +} + +/** + * @brief Get User Defined Channel Mode part1. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMatchEn(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].ER1 & TPU_E_CHn_ER1_MEF_MASK) >> TPU_E_CHn_ER1_MEF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set User Defined Channel Mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableMatch(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_MEF_MASK) | TPU_E_CHn_ER1_MEF(bEn); +} + +/** + * @brief Set ER1 value for match. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetMatchER1(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint32_t u32ER1) +{ + uint32_t u32Temp; + u32Temp = pTPUE->CH[u8Channel].ER1 | TPU_E_CHn_ER1_ERS_MASK; + pTPUE->CH[u8Channel].ER1 = (u32Temp & ~TPU_E_CHn_ER1_ER1_MASK) | TPU_E_CHn_ER1_ER1(u32ER1) | TPU_E_CHn_ER1_ERW_MASK; +} + +/** + * @brief Set ER1 value for capture. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetCaptureER1(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint32_t u32ER1) +{ + uint32_t u32Temp; + u32Temp = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_ERS_MASK) | TPU_E_CHn_ER1_ERS(0U); + pTPUE->CH[u8Channel].ER1 = (u32Temp & ~TPU_E_CHn_ER1_ER1_MASK) | TPU_E_CHn_ER1_ER1(u32ER1) | TPU_E_CHn_ER1_ERW_MASK; +} + +/** + * @brief Get Capture/Match Select for Value of ER1/ER2. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMatchSelForERx(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].ER1 & TPU_E_CHn_ER1_ERS_MASK) >> TPU_E_CHn_ER1_ERS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get ER1 value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetER1Val(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].ER1 & TPU_E_CHn_ER1_ER1_MASK) >> TPU_E_CHn_ER1_ER1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get ER1 value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetCaptureER1Val(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_ERS_MASK) | TPU_E_CHn_ER1_ERS(0U); + u32TmpVal = (pTPUE->CH[u8Channel].ER1 & TPU_E_CHn_ER1_ER1_MASK) >> TPU_E_CHn_ER1_ER1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set ER1 value. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetER1(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint32_t u32ER1) +{ + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_ER1_MASK) | TPU_E_CHn_ER1_ER1(u32ER1) | TPU_E_CHn_ER1_ERW_MASK; +} + +/** + * @brief Clear Match Configuration Enable part2. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatchEn2(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ER2 = (pTPUE->CH[u8Channel].ER2 | TPU_E_CHn_ER2_ERW_MASK); +} + +/** + * @brief Get ER2 value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetER2Val(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].ER2 & TPU_E_CHn_ER2_ER2_MASK) >> TPU_E_CHn_ER2_ER2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get ER2 value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetCaptureER2Val(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_ERS_MASK); + u32TmpVal = (pTPUE->CH[u8Channel].ER2 & TPU_E_CHn_ER2_ER2_MASK) >> TPU_E_CHn_ER2_ER2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set ER2 value. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetER2(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint32_t u32ER2) +{ + pTPUE->CH[u8Channel].ER2 = (pTPUE->CH[u8Channel].ER2 & ~TPU_E_CHn_ER2_ER2_MASK) | TPU_E_CHn_ER2_ER2(u32ER2) | TPU_E_CHn_ER2_ERW_MASK; +} + +/** + * @brief Clear Match1 Configuration Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatch1CFGFlg(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_MRE1_CLR_MASK; +} + +/** + * @brief Clear Match1 event Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatch1Event(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_MRL1_CLR_MASK; +} + +/** + * @brief Clear transition detect1 Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearTransDetect1Event(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_TDL1_CLR_MASK; +} + +/** + * @brief Clear Match2 Configuration Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatch2CFGFlg(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_MRE2_CLR_MASK; +} + +/** + * @brief Clear Match2 event Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatch2Event(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_MRL2_CLR_MASK; +} + +/** + * @brief Clear transition detect2 Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearTransDetect2Event(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_TDL2_CLR_MASK; +} + +/** + * @brief Get output user control, high or low select. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetOutputSelHigh(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].OCR & TPU_E_CHn_OCR_OUT_HIS_MASK) >> TPU_E_CHn_OCR_OUT_HIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear output user control. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOutputSelHigh(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].OCR = TPU_E_CHn_OCR_OUT_HIS(bEn); +} +#ifdef TPU_E_CHn_OCR_OUT_OP1_MASK +/** + * @brief Get output user control, select OPAC1. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetOutputUsrCtrlSelOPAC1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].OCR & TPU_E_CHn_OCR_OUT_OP1_MASK) >> TPU_E_CHn_OCR_OUT_OP1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set output user control, select OPAC1. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOutputSelOPAC1(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].OCR = (pTPUE->CH[u8Channel].OCR & ~TPU_E_CHn_OCR_OUT_OP1_MASK) | TPU_E_CHn_OCR_OUT_OP1(bEn); +} + +/** + * @brief Get output user control, select OPAC2. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetOutputUsrCtrlSelOPAC2(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].OCR & TPU_E_CHn_OCR_OUT_OP2_MASK) >> TPU_E_CHn_OCR_OUT_OP2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set output user control, select OPAC2. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOutputSelOPAC2(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].OCR = (pTPUE->CH[u8Channel].OCR & ~TPU_E_CHn_OCR_OUT_OP2_MASK) | TPU_E_CHn_OCR_OUT_OP2(bEn); +} +#endif /* TPU_E_CHn_OCR_OUT_OP1_MASK */ +#endif + +#endif /* #ifndef _HWA_TPUE_H_ */ diff --git a/Inc/HwA_tpuh.h b/Inc/HwA_tpuh.h new file mode 100644 index 0000000..4b13031 --- /dev/null +++ b/Inc/HwA_tpuh.h @@ -0,0 +1,906 @@ +/** + * @file HwA_tpuh.h + * @author Flagchip + * @brief FC7xxx TPUH hardware access layer + * @version 2.0.0 + * @date 2024-1-12 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + ******************************************************************************** */ +#ifndef _HWA_TPUH_H_ +#define _HWA_TPUH_H_ + +#include "device_header.h" + +#if TPU_INSTANCE_COUNT > 0U + +/********* Local typedef ************/ +/** @brief TPU TCR1 clock control mode type */ +typedef enum +{ + TPUH_CLK_SRC_TCRCLK = 0U, + UTPUH_PDOWN_CNT_MODE = 3U, + TPUH_CLK_SRC_TPUCLKDIV2 = 4U, + TPUH_CLK_SRC_TPUCLK = 5U +} TPUH_TCR1ClkCtrlModeType; + +/** @brief TPU angle tick gen clk type */ +typedef enum +{ + TPUH_TCR1_PRESCAL_OUTPUT = 0U, + TPUH_TCR2_PRESCAL_OUTPUT = 1U +} TPUH_AngleTickGenClkType; + +/** @brief TPU Angle Mode Selection type */ +typedef enum +{ + TPUH_TCR2_TIMEBASE_EAC_DISABLE = 0U, + TPUH_TOOTHSIGNAL_AS_TCRCLK_TOOTH_CH_0 = 1U, + TPUH_TOOTHSIGNAL_AS_CH1INPUT_TOOTH_CH_1 = 2U, + TPUH_TOOTHSIGNAL_AS_CH2INPUT_TOOTH_CH_2 = 3U +} TPUH_AngleModeSel; + +/** @brief TPU Angle Mode Selection type */ +typedef enum +{ + TPUH_TWO_SAMPLE_MODE_TPU_CLK_DIV2 = 0U, + TPUH_TWO_SAMPLE_MODE_CH_CLK = 1U, + TPUH_INTEGRATOR_MODE_TPU_CLK_DIV2 = 2U, + TPUH_INTEGRATOR_MODE_CH_CLK = 3U +} TPUH_TCRClkFilterType; + +/** @brief TPU TCR2 clock control mode0 type */ +typedef enum +{ + TPUH_GATED_DIV8_CLK = 0U, + TPUH_RISE_TRANSITION_INCREMENT_TCR2_PRESCALER = 1U, + TPUH_FALL_TRANSITION_INCREMENT_TCR2_PRESCALER = 2U, + TPUH_DIV8_CLK = 4U, + TPUH_UPDOWN_CNT_MODE = 5U, + TPUH_FROZEN = 7U +} TPUH_TCR1ClkCtrlMode0Type; + +typedef enum +{ + TPUH_RSING_EDGE = 1U, + TPUH_FALLING_EDGE = 2U, + TPUH_BOTH_EDGES = 3U, + TPUH_NO_EDGE = 6U, +} TPUH_TCR1ClkCtrlMode1Type; + +/** @brief Missing Tooth Counter */ +typedef enum +{ + TPUH_NOT_A_MISSING_TOOTH = 0U, + TPUH_ONE_MISSING_TOOTH = 1U, + TPUH_TWO_MISSING_TOOTH = 2U, + TPUH_THREE_MISSING_TOOTH = 3U, +} TPUH_MissToothCntType; + +/** @brief Channel Trigger Configuration */ +typedef enum +{ + TPUH_DISABLED = 0U, + TPUH_ANY_EVENT_GATED_BY_MSRTSR = 2U, + TPUH_HSA_EVENT_ON_FLEXCORE_MODE = 3U, + TPUH_MRL1_EVENT_NOT_GATED_BY_MSR = 4U, + TPUH_MRL2_EVENT_NOT_GATED_BY_MSR = 5U, + TPUH_MRL1_OR_MRL2_EVENT_NOT_GATED_BY_MSR = 6U, + TPUH_MRL1_AND_MRL2_EVENT_NOT_GATED_BY_MSR = 7U, + TPUH_TDL1_OR_TDL2_EVENT_NOT_GATED_BY_TSR = 8U, + TPUH_TDL1_AND_TDL2_EVENT_NOT_GATED_BY_TSR = 9U, + TPUH_EVENT_EQUAL_TO_CH_DO_LEVEL = 10U, + TPUH_EVENT_NEGATIVE_TO_CH_DO_LEVEL = 11U, + TPUH_EVENT_EQUAL_TO_CH_DO_PART1_LEVEL = 12U, + TPUH_EVENT_EQUAL_TO_CH_DO_PART2_LEVEL = 13U, + TPUH_EVENT_EQUAL_TO_CH_IND_LEVEL = 14U, + TPUH_EVENT_EQUAL_TO_CH_IND_LATCH_LEVEL = 15U, +} TPUH_ChTrigCFGType; + +/********* Local inline function ************/ +/** + * @brief Get service request status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetSRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VSR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin input status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetInputStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VIR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin output status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetoutputStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VOR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin output enable status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetoutputEnStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VOBR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL1 status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetMRL1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VM1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL2 status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetMRL2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VM2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL1 status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTDL1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VT1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL2 status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTDL2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VT2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL1 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetMRL1EventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_EM1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL2 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetMRL2EventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_EM2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL1 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTDL1eventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_ET1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL2 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTDL2eventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_ET2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get HAS status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetHASStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VHSR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TCR1 prescaler. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1Prescaler(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR1P_MASK) >> TPU_H_TBR_CR_TCR1P_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get TCR1 clock control. + * + */ +LOCAL_INLINE TPUH_TCR1ClkCtrlModeType TPU_H_HWA_GetTCR1ClkControl(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR1CTL_MASK) >> TPU_H_TBR_CR_TCR1CTL_SHIFT; + return (TPUH_TCR1ClkCtrlModeType)u32TmpVal; +} + +/** + * @brief Get TCR2 prescaler. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2Prescaler(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2P_MASK) >> TPU_H_TBR_CR_TCR2P_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get Angle tick generator clock. + * + */ +LOCAL_INLINE TPUH_AngleTickGenClkType TPU_H_HWA_GetATGC(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_ATGC_MASK) >> TPU_H_TBR_CR_ATGC_SHIFT; + return (TPUH_AngleTickGenClkType)u32TmpVal; +} + +/** + * @brief Get Angle Mode Selection. + * + */ +LOCAL_INLINE TPUH_AngleModeSel TPU_H_HWA_GetAM(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_AM_MASK) >> TPU_H_TBR_CR_AM_SHIFT; + return (TPUH_AngleModeSel)u32TmpVal; +} + +/** + * @brief Get TCRCLK signal Filter Control. + * + */ +LOCAL_INLINE TPUH_TCRClkFilterType TPU_H_HWA_GetTCRClkFilter(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCRCF_MASK) >> TPU_H_TBR_CR_TCRCF_SHIFT; + return (TPUH_TCRClkFilterType)u32TmpVal; +} + +/** + * @brief Get TCR2 clock control. + * + */ +LOCAL_INLINE TPUH_TCR1ClkCtrlMode0Type TPU_H_HWA_GetTCR2ClkControlAM0(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2CTL_MASK) >> TPU_H_TBR_CR_TCR2CTL_SHIFT; + return (TPUH_TCR1ClkCtrlMode0Type)u32TmpVal; +} + +/** + * @brief Get TCR2 clock control. + * + */ +LOCAL_INLINE TPUH_TCR1ClkCtrlMode1Type TPU_H_HWA_GetTCR2ClkControlAM1(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2CTL_MASK) >> TPU_H_TBR_CR_TCR2CTL_SHIFT; + return (TPUH_TCR1ClkCtrlMode1Type)u32TmpVal; +} + +/** + * @brief Get TCR1 cnt value. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1CntVal(const TPU_H_Type *const pTPUH) +{ + return pTPUH->TBR_T1R; +} + +/** + * @brief Get TCR2 cnt value. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2CntVal(const TPU_H_Type *const pTPUH) +{ + return pTPUH->TBR_T2R; +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_H_HWA_NotLastTooth(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_LAST_MASK) >> TPU_H_TBR_TPR_LAST_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Get missing tooth counter. + * + */ +LOCAL_INLINE TPUH_MissToothCntType TPU_H_HWA_GetMissingTooth(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_MISSCNT_MASK) >> TPU_H_TBR_TPR_MISSCNT_SHIFT; + return (TPUH_MissToothCntType)u32TmpVal; +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_H_HWA_NoInsertTooth(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_IPH_MASK) >> TPU_H_TBR_TPR_IPH_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_H_HWA_NoForceEACHalt(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_HOLD_MASK) >> TPU_H_TBR_TPR_HOLD_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Get angle ticks number. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetAngleTicksVal(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_TPR & TPU_H_TBR_TPR_TICKS_MASK) >> TPU_H_TBR_TPR_TICKS_SHIFT; +} + +/** + * @brief Get the integer part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetIntergerPerAngleTick(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_TRR & TPU_H_TBR_TRR_INTEGER_MASK) >> TPU_H_TBR_TRR_INTEGER_SHIFT; +} + +/** + * @brief Get the fraction part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetFractionPerAngleTick(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_TRR & TPU_H_TBR_TRR_FRACTION_MASK) >> TPU_H_TBR_TRR_FRACTION_SHIFT; +} + +/** + * @brief Get TCR1 overflow flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTCR1Overflow(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_OVF_MASK) >> TPU_H_TBR_T1MR_OVF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TCR1 IRQ enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_TCR1IRQEnable(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_IRQ_EN_MASK) >> TPU_H_TBR_T1MR_IRQ_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the maximum value of TCR1 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1MaxCnt(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_MAX_MASK) >> TPU_H_TBR_T1MR_MAX_SHIFT; +} + +/** + * @brief Get TCR2 overflow flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_TCR2Overflow(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_OVF_MASK) >> TPU_H_TBR_T2MR_OVF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TCR2 IRQ enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_TCR2IRQEnable(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_IRQ_EN_MASK) >> TPU_H_TBR_T2MR_IRQ_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the maximum value of TCR2 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2MaxCnt(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_MAX_MASK) >> TPU_H_TBR_T2MR_MAX_SHIFT; +} + +/** + * @brief Get channel HSA enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChHSAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHAE_MASK) >> TPU_H_CHn_CR_CHAE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel HSA enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChHSA(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHAE_MASK) | TPU_H_CHn_CR_CHAE(benable)); +} + +/** + * @brief Set channel event trigger dma enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChEventDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CDFD_MASK) | TPU_H_CHn_CR_CDFD(benable)); +} + +/** + * @brief Set channel request Dma enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChReqDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHDE_MASK) | TPU_H_CHn_CR_CHDE(benable)); +} + +/** + * @brief Get channel HSR Dma request enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChDMAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHDE_MASK) >> TPU_H_CHn_CR_CHDE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel Sync isr from flexcore enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChSyncISR(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHEE_MASK) | TPU_H_CHn_CR_CHEE(benable)); +} + +/** + * @brief Get channel HSR event as interrupt enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChHSRISREnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHEE_MASK) >> TPU_H_CHn_CR_CHEE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel trigger configuration. + * + */ +LOCAL_INLINE TPUH_ChTrigCFGType TPU_H_HWA_GetChTrigCondition(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CTC_MASK) >> TPU_H_CHn_CR_CTC_SHIFT; + return (TPUH_ChTrigCFGType)u32TmpVal; +} + +/** + * @brief Set channel trigger configuration. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChTrig(TPU_H_Type *const pTPUH, uint8_t u8Channel, TPUH_ChTrigCFGType etrgcfg) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CTC_MASK) | TPU_H_CHn_CR_CTC(etrgcfg)); +} + +/** + * @brief Get channel trigger DMA enable. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTrigDMAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CDFD_MASK) >> TPU_H_CHn_CR_CDFD_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel trigger DMA enable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChTrigDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CDFD_MASK) | TPU_H_CHn_CR_CDFD(benable)); +} + +/** + * @brief Get channel HSR index. + * + */ +LOCAL_INLINE uint8 TPU_H_HWA_GetChHSRIdx(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHSR_MASK) >> TPU_H_CHn_CR_CHSR_SHIFT; + return (uint8)u32TmpVal; +} + +/** + * @brief Get channel HSR index. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChHSRIdx(TPU_H_Type *const pTPUH, uint8_t u8Channel, uint8_t u8HSRIdx) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHSR_MASK) | TPU_H_CHn_CR_CHSR(u8HSRIdx)); +} + +/** + * @brief Get channel event trigger interrupt status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChEventTrigISRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CIS_MASK) >> TPU_H_CHn_SR_CIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel host service request (HSR) status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChHSRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (uint32_t)((pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHRS_MASK) >> TPU_H_CHn_SR_CHRS_SHIFT); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get HSA. + * + */ +LOCAL_INLINE uint8 TPU_H_HWA_GetChHSAIdx(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHRI_MASK) >> TPU_H_CHn_SR_CHRI_SHIFT; + return (uint8_t)u32TmpVal; +} + + +/** + * @brief Get channel event as interrupt status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChDMAReq(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHDS_MASK) >> TPU_H_CHn_SR_CHDS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel trigger status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTrigStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CTS_MASK) >> TPU_H_CHn_SR_CTS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel host service acknowledge (HSA) interrupt status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChHSAReqStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHAS_MASK) >> TPU_H_CHn_SR_CHAS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear channel interrupt by event. + * + */ +LOCAL_INLINE void TPU_H_HWA_ClearChEventISRFlg(TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CEIC_MASK; +} + +/** + * @brief Clear channel HSA. + * + */ +LOCAL_INLINE void TPU_H_HWA_ClearChHSA(TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CHAC_MASK; +} + +/** + * @brief Clear channel HSR. + * + */ +LOCAL_INLINE void TPU_H_HWA_ClearChHSR(TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CHRT_MASK; +} + +/** + * @brief Get channel service request. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChServiceReq(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_CSR_MASK) >> TPU_H_CHn_EFR_CSR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel service request to HOST. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChServiceReqToHost(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_CHSR_MASK) >> TPU_H_CHn_EFR_CHSR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 event status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_EMRL1_MASK) >> TPU_H_CHn_EFR_EMRL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 event status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_EMRL2_MASK) >> TPU_H_CHn_EFR_EMRL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get transition detect latch 1 event status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch1Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_ETDL1_MASK) >> TPU_H_CHn_EFR_ETDL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get transition detect latch 2 event status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch2Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_ETDL2_MASK) >> TPU_H_CHn_EFR_ETDL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1En(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRLE1_MASK) >> TPU_H_CHn_EFR_MRLE1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2En(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRLE2_MASK) >> TPU_H_CHn_EFR_MRLE2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRL1_MASK) >> TPU_H_CHn_EFR_MRL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRL2_MASK) >> TPU_H_CHn_EFR_MRL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Transition Detect latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_TDL1_MASK) >> TPU_H_CHn_EFR_TDL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Transition Detect latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_TDL2_MASK) >> TPU_H_CHn_EFR_TDL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +#endif + +#endif /* #ifndef _HWA_TPUH_H_ */ diff --git a/Inc/HwA_trgsel.h b/Inc/HwA_trgsel.h new file mode 100644 index 0000000..905bc92 --- /dev/null +++ b/Inc/HwA_trgsel.h @@ -0,0 +1,164 @@ +/** + * @file HwA_trgsel.h + * @author flagchip + * @brief Hardware access layer for TrgSel + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip030 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip030 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_TRGSEL_H_ +#define _HWA_TRGSEL_H_ + +#include "device_header.h" + +#if TRGSEL_INSTANCE_COUNT > 0U + +#define TRGSEL_REGSIZE 4U + +/** + * @defgroup HwA_trgsel HwA_trgsel + * @ingroup module_driver_trgsel + * @{ + */ + +/** + * @brief Get the trigger source of the selected trigger target + * + * @param pTrgsel the base address of the TrgSel instance + * @param u32TargetIndex the trigger target to get the trigger source + * @return uint32_t the trigger source of the selected trigger target + */ +LOCAL_INLINE uint32_t TRGSEL_HWA_GetTargetTriggerSource(const TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex) +{ + uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE; + uint32_t u32SelIdx = u32TargetIndex % TRGSEL_REGSIZE; + + uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx]; + switch (u32SelIdx) + { + case 0U: + { + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_0_MASK) >> TRGSEL_OUT_SEL_SEL_0_SHIFT; + break; + } + case 1U: + { + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_1_MASK) >> TRGSEL_OUT_SEL_SEL_1_SHIFT; + break; + } + case 2U: + { + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_2_MASK) >> TRGSEL_OUT_SEL_SEL_2_SHIFT; + break; + } + case 3U: + { + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_3_MASK) >> TRGSEL_OUT_SEL_SEL_3_SHIFT; + break; + } + + default: + break; + } + + return (uint32_t)u32Tmp; +} + +/** + * @brief Set the trigger source of the selected trigger target + * + * @param pTrgsel the base address of the TrgSel instance + * @param u32TargetIndex the trigger target to set the trigger source + * @param u32SourceIndex the selected trigger source to trig the target + */ +LOCAL_INLINE void TRGSEL_HWA_SetTargetTriggerSource(TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex, + uint32_t u32SourceIndex) +{ + uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE; + uint32_t u32SelIdx = u32TargetIndex % TRGSEL_REGSIZE; + uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx]; + + switch (u32SelIdx) + { + case 0U: + { + u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_0_MASK) | TRGSEL_OUT_SEL_SEL_0(u32SourceIndex); + break; + } + case 1U: + { + u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_1_MASK) | TRGSEL_OUT_SEL_SEL_1(u32SourceIndex); + break; + } + case 2U: + { + u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_2_MASK) | TRGSEL_OUT_SEL_SEL_2(u32SourceIndex); + break; + } + case 3U: + { + u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_3_MASK) | TRGSEL_OUT_SEL_SEL_3(u32SourceIndex); + break; + } + + default: + break; + } + + pTrgsel->OUT_SEL[u32RegIdx] = u32Tmp; +} + +/** + * @brief Get wether the trigger source of the selected target is locked + * + * @param pTrgsel the base address of the TrgSel instance + * @param u32TargetIndex the trigger target to get the lock status + * @return true the trigger source of the selected target cannot be modified + * @return false the trigger source of the selected target can be modified + */ +LOCAL_INLINE bool TRGSEL_HWA_GetTargetLockStatus(const TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex) +{ + uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE; + + uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx]; + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_LOCK_MASK) >> TRGSEL_OUT_SEL_LOCK_SHIFT; + + return (bool)((u32Tmp != 0U) ? true : false); +} + +/** + * @brief Lock the trigger source of the selected target + * + * @note The trigger target is grouped by four, so if you lock the trigger source of one target, the + * adjacent three trigger targets in the same register group are also be locked. So please ensure the + * trigger sources are not to be modified before lock the trigger target. + * + * @param pTrgsel the base address of the TrgSel instance + * @param u32TargetIndex the trigger target to lock the trigger source + */ +LOCAL_INLINE void TRGSEL_HWA_LockTargetTriggerSource(TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex) +{ + uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE; + + pTrgsel->OUT_SEL[u32RegIdx] |= TRGSEL_OUT_SEL_LOCK_MASK; +} + +/** @}*/ + +#endif /* #if TRGSEL_INSTANCE_COUNT > 0U */ + +#endif /* _HWA_TRGSEL_H_ */ diff --git a/Inc/HwA_tstmp.h b/Inc/HwA_tstmp.h new file mode 100644 index 0000000..89ea76e --- /dev/null +++ b/Inc/HwA_tstmp.h @@ -0,0 +1,206 @@ +/** + * @file HwA_tstmp.h + * @author Flagchip + * @brief TSTMP hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + ******************************************************************************** */ +#ifndef _HWA_TSTMP_H_ +#define _HWA_TSTMP_H_ + +#include "device_header.h" + +#if TSTMP_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_tstmp HwA_tstmp + * @ingroup module_driver_tstmp + * @{ + */ + +/********* Local typedef ************/ +/** @brief Tstmp modulate number */ +typedef enum +{ + TSTMP_MODChn0 = 0U, + TSTMP_MODChn1, + TSTMP_MODChn2, + TSTMP_MODChn3 +} TSTMP_ModChannelType; + +#if (TSTMP_SUPPORT_MODULATE_SUPPOT == STD_ON) +/** @brief TSTMP counter mode + * (available on FC7300F1M_B only)*/ +typedef enum +{ + TSTMP_MODE_ALWAYS_RUNNING = 0U, + TSTMP_MODE_PERIOD_RUNNING = 1U +} TSTMP_ModeCounterRunningMode; +#endif +/********* Local inline function ************/ +/** + * @brief Read TSTMP value + * + * @param pTstmp TSTMP instance + * @return TSTMP value + */ +LOCAL_INLINE uint64_t TSTMP_HWA_ReadTstmpValue(TSTMP_Type *pTstmp) +{ + uint32_t u32TstmpL, u32TstmpH; + uint64_t u64TempValue = 0U; + u32TstmpL = pTstmp->VALL; + u32TstmpH = pTstmp->VALH; + + u64TempValue = u32TstmpH; + u64TempValue = (u64TempValue << 32) + u32TstmpL; + return u64TempValue; +} + +/** + * @brief Read TSTMP interrupt enable bits + * + * @param pTstmp TSTMP instance + * @return TSTMP interrupt enable bits + */ +LOCAL_INLINE uint32_t TSTMP_HWA_ReadTstmpInterruptEnable(TSTMP_Type *pTstmp) +{ + return (uint32_t)pTstmp->MOD_INTEN; +} + +/** + * @brief Read TSTMP all MOD match flag + * + * @param pTstmp TSTMP instance + * @return TSTMP all MOD match flag + */ +LOCAL_INLINE uint32_t TSTMP_HWA_ReadModMatchFlag(TSTMP_Type *pTstmp) +{ + return ((uint32_t)(pTstmp->MOD_STATUS) & (uint32_t)(TSTMP_MOD_STATUS_MOD0_MATCH_MASK | TSTMP_MOD_STATUS_MOD1_MATCH_MASK + | TSTMP_MOD_STATUS_MOD2_MATCH_MASK | TSTMP_MOD_STATUS_MOD3_MATCH_MASK)); +} + +/** + * @brief Clear TSTMP MOD match flag + * + * @param pTstmp TSTMP instance + */ +LOCAL_INLINE void TSTMP_HWA_ClearModMatchFlag(TSTMP_Type *pTstmp,TSTMP_ModChannelType eMod) +{ + pTstmp->MOD_STATUS = ((uint32_t)1U << (uint32_t)eMod); +} + + + +/** + * @brief Set MOD match value + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + * @param u32ModValue MOD value + */ +LOCAL_INLINE void TSTMP_HWA_SetModMatchValue(TSTMP_Type *pTstmp, TSTMP_ModChannelType eMod, uint32_t u32ModValue) +{ + switch(eMod) + { + case TSTMP_MODChn0: + pTstmp->MOD0_SETVAL = u32ModValue; + break; + + case TSTMP_MODChn1: + pTstmp->MOD1_SETVAL = u32ModValue; + break; + + case TSTMP_MODChn2: + pTstmp->MOD2_SETVAL = u32ModValue; + break; + + case TSTMP_MODChn3: + pTstmp->MOD3_SETVAL = u32ModValue; + break; + + default: + break; + } +} + +/** + * @brief Enable TSTMP MOD(n) match interrupt + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_EnableModMatchInterrupt(TSTMP_Type *pTstmp, TSTMP_ModChannelType eMod) +{ + pTstmp->MOD_INTEN |= ((uint32_t)1U << (uint32_t)eMod); +} + +/** + * @brief Disable TSTMP MOD(n) match interrupt + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_DisableModMatchInterrupt(TSTMP_Type *pTstmp, TSTMP_ModChannelType eMod) +{ + pTstmp->MOD_INTEN &= ~((uint32_t)1U << (uint32_t)eMod); +} + +#if (TSTMP_SUPPORT_MODULATE_SUPPOT == STD_ON) + +/** + * @brief Set the counting modes of TSTMP MOD(n) + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + * @param eCounterMode Counting mode set + */ +LOCAL_INLINE void TSTMP_HWA_SetModCounterMode(TSTMP_Type *pTstmp, TSTMP_ModChannelType eMod, TSTMP_ModeCounterRunningMode eCounterMode) +{ + pTstmp->MOD_INTEN = (pTstmp->MOD_INTEN & ~((uint32_t)0x100U << (uint32_t)eMod)) | + (((uint32_t)eCounterMode << 8U) << (uint32_t)eMod); +} + +/** + * @brief Enable TSTMP MOD(n) counter + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_EnableModCounter(TSTMP_Type *pTstmp, TSTMP_ModChannelType eMod) +{ + pTstmp->MOD_INTEN |= ((uint32_t)0x10000U << (uint32_t)eMod); +} + +/** + * @brief Disable TSTMP MOD(n) counter + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_DisableModCounter(TSTMP_Type *pTstmp, TSTMP_ModChannelType eMod) +{ + pTstmp->MOD_INTEN &= ~((uint32_t)0x10000U << (uint32_t)eMod); +} + +#endif + +/** @}*/ + +#endif /* #if TSTMP_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_TSTMP_H_ */ diff --git a/Inc/HwA_wdog.h b/Inc/HwA_wdog.h new file mode 100644 index 0000000..40d48a2 --- /dev/null +++ b/Inc/HwA_wdog.h @@ -0,0 +1,135 @@ +/** + * @file HwA_WDOG.h + * @author flagchip + * @brief Wdog hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip031 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip031 N/A Change version and release + ******************************************************************************** */ + +#ifndef _HWA_WDOG_H_ +#define _HWA_WDOG_H_ + +#include "device_header.h" + +#if WDOG_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_wdog HwA_wdog + * @ingroup module_driver_wdog + * @{ + */ + +/********* Local typedef ************/ + +/********* Local inline function ************/ + +/********* Wdog Register interface ************/ +/** + * @brief Set CS register value, for Wdog working mode configuration. + * + * @param WDOG_Type *pWdog. point to wdog instance base register address. + * @param uint32_t u32Cs. configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetCs(WDOG_Type *pWdog, uint32_t u32Cs) +{ + pWdog->CS = u32Cs; +} + +/** + * @brief Get CS register value, for WDOG working mode configuration. + * @return uint32_t CS register value. + */ +LOCAL_INLINE uint32_t WDOG_HWA_GetCs(WDOG_Type *pWdog) +{ + uint32_t u32Temp = 0U; + u32Temp = pWdog->CS; + return u32Temp; +} + +/** + * @brief Clear Wdog interrupt flag. + * + * @param WDOG_Type *pWdog. point to wdog instance base register address. + */ +LOCAL_INLINE void WDOG_HWA_ClearInterruptFlag(WDOG_Type *pWdog) +{ + pWdog->CS |= WDOG_CS_FLAG_MASK; +} + +/** + * @brief Get WDOG unlock status, if locked, register can't be written. + * @return bool. true as unlocked. false as locked. + */ +LOCAL_INLINE bool WDOG_HWA_GetUnlockStatus(WDOG_Type *pWdog) +{ + return (bool)((((uint32_t)pWdog->CS & (uint32_t)WDOG_CS_ULK_STAT_MASK) != 0U) ? true : false); +} + +/** + * @brief Set COUNTER register value. for Wdog unlock and refresh usage. + * + * @param pWdog. point to wdog instance base register address. + * + * @param u32Counter. configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetCounter(WDOG_Type *pWdog, uint32_t u32Counter) +{ + pWdog->COUNTER = u32Counter; +} + +/** + * @brief Set TIMEOUT register value. for WDOG timeout value + * + * @param WDOG_Type *pWdog. point to wdog instance base register address. + * + * @param uint16_t u16Timeout configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetTimeout(WDOG_Type *pWdog, uint16_t u16Timeout) +{ + pWdog->TIMEOUT = u16Timeout; +} + +/** + * @brief Set WINDOW register value. for windowed WDOG low threshold value. + * + * @param WDOG_Type *pWdog. point to wdog instance base register address. + * + * @param uint16_t u16Window. configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetWindow(WDOG_Type *pWdog, uint16_t u16Window) +{ + pWdog->WINDOW = u16Window; +} + +#if WDOG_SUPPORT_FASTCFG +/** + * @brief Set Fast Configuration Control. + * + * @param pWdog. point to wdog instance base register address. + * + * @param u32Value. configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetFastCfgState(WDOG_Type *pWdog, uint32_t u32Value) +{ + pWdog->FASTCFG = u32Value; +} +/** @}*/ /* HwA_WODG */ +#endif +#endif + +#endif /* #ifndef _HWA_WDOG_H_ */ diff --git a/Inc/HwA_wku.h b/Inc/HwA_wku.h new file mode 100644 index 0000000..65978e4 --- /dev/null +++ b/Inc/HwA_wku.h @@ -0,0 +1,216 @@ +/** + * @file HwA_wku.h + * @author Flagchip + * @brief WKU hardware access layer + * @version 2.0.0 + * @date 2024-08-20 + * + * SDK Version: 2.6.0 + * + + * @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300 + * 2.0.0 2024-10-12 Flagchip084 N/A Change version and release + ******************************************************************************** */ +#ifndef _HWA_WKU_H_ +#define _HWA_WKU_H_ + +#include "device_header.h" + +#if WKU_INSTANCE_COUNT > 0U + +/** + * @defgroup HwA_wku HwA_wku + * @ingroup module_driver_wku + * @{ + */ + +/********* Local typedef ************/ +#define WKU_MWR0 0x0000100U +#define WKU_MWR1 0x0010000U +#define WKU_MWR2 0x1000000U + +/** @brief Wku input */ +typedef enum +{ +#if (WKU_GPIO_TYPE_0_SUPPORT || WKU_GPIO_TYPE_1_SUPPORT) + WKU_INPUT_FCSPI0 = 0x000040U, + WKU_INPUT_FCUART = 0x000080U, + WKU_INPUT_CMP0 = 0x000400U, + WKU_INPUT_CMP1 = 0x000800U, + WKU_INPUT_TSTMP0 = 0x002000U, + WKU_INPUT_RTC_ALARM = 0x004000U, + WKU_INPUT_RTC_SECONDS = 0x008000U, + WKU_INPUT_FCPIT0 = 0x010000U, + WKU_INPUT_CMU0 = 0x020000U, + WKU_INPUT_AONTIMER = 0x040000U, + WKU_INPUT_GPIOA = 0x080000U, + +#if WKU_GPIO_TYPE_0_SUPPORT + WKU_INPUT_GPIOC = 0x100000U, + WKU_INPUT_GPIOE = 0x200000U, + WKU_INPUT_GPIOF = 0x400000U, + WKU_INPUT_GPIOG = 0x800000U, +#else + WKU_INPUT_GPIOC = 0x200000U, + WKU_INPUT_GPIOD = 0x400000U, + WKU_INPUT_GPIOE = 0x800000U, +#endif /* WKU_GPIO_TYPE_0_SUPPORT */ + +#elif WKU_GPIO_TYPE_2_SUPPORT + WKU_INPUT_GPIOB = 0x000001U, + WKU_INPUT_GPIOD = 0x000002U, + WKU_INPUT_GPIOF = 0x000004U, + WKU_INPUT_GPIOG = 0x000008U, + WKU_INPUT_GPIOH = 0x000010U, + WKU_INPUT_GPIOI = 0x000020U, + +#if WKU_GPIO_TYPE_2_ADC2_SUPPORT + WKU_INPUT_ADC1_LPWAKE = 0x000100U, + WKU_INPUT_ADC2_LPWAKE = 0x000200U, +#else + WKU_INPUT_ADC0_LPWAKE = 0x000100U, + WKU_INPUT_ADC1_LPWAKE = 0x000200U, +#endif /* WKU_GPIO_TYPE_2_ADC2_SUPPORT */ + +#if WKU_GPIO_TYPE_2_CMP0_SUPPORT + WKU_INPUT_CMP0 = 0x000400U, +#endif /* WKU_GPIO_TYPE_2_CMP0_SUPPORT */ + + WKU_INPUT_TSTMP0 = 0x002000U, + WKU_INPUT_RTC_ALARM = 0x004000U, + WKU_INPUT_RTC_SECONDS = 0x008000U, + WKU_INPUT_AONTIMER0 = 0x040000U, + WKU_INPUT_GPIOA = 0x080000U, + WKU_INPUT_GPIOC = 0x100000U, + WKU_INPUT_GPIOE = 0x200000U, +#else + /* More supoort */ +#endif /* (WKU_GPIO_TYPE_0_SUPPORT || WKU_GPIO_TYPE_1_SUPPORT) */ + WKU_INPUT_MAX = 0xFFFFFFU +} WKU_WakeupInputType; + +/********* Local inline function ************/ +/** + * @brief Enable wakeup source + * + * @param eWakeup Wakeup source type + */ +LOCAL_INLINE void WKU_HWA_EnableWakeupSource(const WKU_WakeupInputType eWakeup) +{ + if (eWakeup < WKU_MWR0) + { + WKU->MWER0 |= (uint32_t)eWakeup; + } + else if ((eWakeup < WKU_MWR1) && (eWakeup >= WKU_MWR0)) + { + WKU->MWER1 |= ((uint32_t)eWakeup >> 8U); + } + else + { + WKU->MWER2 |= ((uint32_t)eWakeup >> 16U); + } +} + +/** + * @brief Disable wakeup source + * + * @param eWakeup Wakeup source type + */ +LOCAL_INLINE void WKU_HWA_DisableWakeupSource(const WKU_WakeupInputType eWakeup) +{ + if (eWakeup < WKU_MWR0) + { + WKU->MWER0 &= ((~((uint32_t)eWakeup)) & (uint32_t)0xFF); + } + else if ((eWakeup < WKU_MWR1) && (eWakeup >= WKU_MWR0)) + { + WKU->MWER1 &= ((~(uint32_t)((uint32_t)eWakeup >> 8U)) & (uint32_t)0xFF); + } + else + { + WKU->MWER2 &= ((~(uint32_t)((uint32_t)eWakeup >> 16U)) & (uint32_t)0xFF); + } +} + +/** + * @brief Read WKU wakeup source + * + * @return WKU wakeup source value + */ +LOCAL_INLINE uint32_t WKU_HWA_ReadWakeupSource(void) +{ + uint32_t u32WakeupSource = 0U; + + u32WakeupSource = (uint32_t)(WKU->MWER0); + u32WakeupSource |= (uint32_t)((uint32_t)(WKU->MWER1) << 8U); + u32WakeupSource |= (uint32_t)((uint32_t)(WKU->MWER2) << 16U); + + return u32WakeupSource; +} + +#if WKU_GPIO_TYPE_2_SUPPORT +/** + * @brief Get wakeup flag + * + * @param eWakeup + * @return + */ +LOCAL_INLINE bool WKU_HWA_CheckWakeupFlag(const WKU_WakeupInputType eWakeup) +{ + uint32_t u32WakeupFlag = 0U; + + if (eWakeup < WKU_MWR0) + { + u32WakeupFlag = WKU->MWFR0 & (((uint32_t)eWakeup) & (uint32_t)0xFF); + } + else if ((eWakeup < WKU_MWR1) && (eWakeup >= WKU_MWR0)) + { + u32WakeupFlag = WKU->MWFR1 & (((uint32_t)((uint32_t)eWakeup >> 8U)) & (uint32_t)0xFF); + } + else + { + u32WakeupFlag = WKU->MWFR2 & (((uint32_t)((uint32_t)eWakeup >> 16U)) & (uint32_t)0xFF); + } + + if (u32WakeupFlag != 0U) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Get all wakeup flag + * + * @param void + * @return + */ +LOCAL_INLINE uint32_t WKU_HWA_GetAllWakeupFlag(void) +{ + uint32_t u32WakeupFlag = 0U; + + u32WakeupFlag = (uint32_t)(WKU->MWFR0); + u32WakeupFlag |= (uint32_t)((uint32_t)(WKU->MWFR1) << 8U); + u32WakeupFlag |= (uint32_t)((uint32_t)(WKU->MWFR2) << 16U); + + return u32WakeupFlag; +} +#endif /* WKU_GPIO_TYPE_2_SUPPORT */ + +/** @}*/ + +#endif /* #if WKU_INSTANCE_COUNT > 0U */ + +#endif /* #ifndef _HWA_WKU_H_ */ diff --git a/Inc/Hwa_eftu_spe.h b/Inc/Hwa_eftu_spe.h new file mode 100644 index 0000000..cd9ee94 --- /dev/null +++ b/Inc/Hwa_eftu_spe.h @@ -0,0 +1,333 @@ +/* + * Hwa_eftu_spe.h + * + * Created on: 2025年12月3日 + * Author: qxw0076 + */ + +#ifndef TEMPLATE_HWA_INCLUDE_HWA_EFTU_SPE_H_ +#define TEMPLATE_HWA_INCLUDE_HWA_EFTU_SPE_H_ +#include "device_header.h" + +#if (EFTU_INSTANCE_COUNT > 0U) && (EFTU_SPE_SUPPORT == STD_ON) && defined(EFTU_SPE_SUPPORT) + +typedef enum +{ + EFTU_SPE_INSTANCE_0 = 0U, + EFTU_SPE_INSTANCE_1 = 1U, +} EFTU_SPE_InstanceType; + +typedef enum +{ + EFTU_SPE_UPDATETRIGGER_NIPD = 0U, + EFTU_SPE_UPDATETRIGGER_TOM = 1U, + EFTU_SPE_UPDATETRIGGER_NIPD_DELAY = 2U, + EFTU_SPE_UPDATETRIGGER_TOM_DELAY = 3U, +} EFTU_SPE_UpdateTriggerType; + +typedef enum +{ + EFTU_SPE_EXUPDATETRIGGER_CH6_CM0 = 0U, + EFTU_SPE_EXUPDATETRIGGER_CH7_CM0 = 1U, + EFTU_SPE_EXUPDATETRIGGER_CH4_CM0 = 2U, + EFTU_SPE_EXUPDATETRIGGER_CH5_CM0 = 3U, +} EFTU_SPE_UpdateExTriggerType; + +typedef enum +{ + EFTU_SPE_REFTYPE_00 = 0U, + EFTU_SPE_REFTYPE_01 = 1U, + EFTU_SPE_REFTYPE_10 = 2U, + EFTU_SPE_REFTYPE_11 = 3U, + +} EFTU_SPE_RefSelectType; + +typedef enum +{ + EFTU_SPE_OUT_REF_H = 0U, + EFTU_SPE_OUT_REF_L = 1U, + EFTU_SPE_OUT_CONST_0 = 2U, + EFTU_SPE_OUT_CONST_1 = 3U, +} EFTU_SPE_PwmOutSelect; + +typedef enum +{ + EFTU_SPE_HALL_INPUT_0 = 0u, + EFTU_SPE_HALL_INPUT_1 = 1u, +} EFTU_SPE_HallLevel; + +typedef struct +{ + EFTU_SPE_HallLevel eHallA_level; + EFTU_SPE_HallLevel eHallB_level; + EFTU_SPE_HallLevel eHallC_level; + uint8 u8SpePtr; + uint8 u8SpePtrBwd; +} EFTU_SPE_HallPattern; + +typedef struct +{ + EFTU_SPE_PwmOutSelect ePwmoutpattern0; + EFTU_SPE_PwmOutSelect ePwmoutpattern1; + EFTU_SPE_PwmOutSelect ePwmoutpattern2; + EFTU_SPE_PwmOutSelect ePwmoutpattern3; + EFTU_SPE_PwmOutSelect ePwmoutpattern4; + EFTU_SPE_PwmOutSelect ePwmoutpattern5; +} EFTU_SPE_OutPattern; + +typedef enum +{ + CCM_CLK_RES_0 = 0U, + CCM_CLK_RES_1 = 1U, + CCM_CLK_RES_2 = 2U, + CCM_CLK_RES_3 = 3U, + CCM_CLK_RES_4 = 4U, + CCM_CLK_RES_5 = 5U, + CCM_CLK_RES_6 = 6U, + CCM_CLK_RES_7 = 7U, +} EFTU_SPE_DelayClockSrc; + +typedef enum +{ + DTM_AUX_IN0 = 0U, + DTM_AUX_IN1 = 1U, + DTM_AUX_IN2 = 2U, + DTM_AUX_IN3 = 3U, + DTM_AUX_IN4 = 4U, + DTM_AUX_IN5 = 5U, + DTM_AUX_IN6 = 6U, + DTM_AUX_IN7 = 7U, +} EFTU_SPE_FastShutSrc; + +typedef enum +{ + EFTU_SPE_PAT0 = 0U, + EFTU_SPE_PAT1 = 1U, + EFTU_SPE_PAT2 = 2U, + EFTU_SPE_PAT3 = 3U, + EFTU_SPE_PAT4 = 4U, + EFTU_SPE_PAT5 = 5U, + EFTU_SPE_PAT6 = 6U, + EFTU_SPE_PAT7 = 7U, +} EFTU_SPE_OutPatternType; + +typedef enum +{ + EFTU_SPE_OUT_PAT_PTR = 0U, + EFTU_SPE_OUT_PPAT_PTR_BWD = 1U, + EFTU_SPE_OUT_PAT_6 = 2U, + EFTU_SPE_OUT_PAT_7 = 3U, +} EFTU_SPE_ControlCmd; + +LOCAL_INLINE void EFTU_SPE_ConfigPAT(EFTU_SPE_Type *const pSpe, uint32 u32HallPta) +{ + pSpe->HALL_IN_PAT = u32HallPta; +} + +LOCAL_INLINE void EFTU_SPE_ConfigOutPwm(EFTU_SPE_Type *const pSpe, uint32 u32OutPwm, uint8 u8Channel) +{ + pSpe->PWM_OUT_PAT[u8Channel] = u32OutPwm; +} + +LOCAL_INLINE void EFTU_SPE_ConfigOutputDirect(EFTU_SPE_Type *const pSpe, uint32 u32Outpattern) +{ + pSpe->PWM_OUT_CTRL = u32Outpattern; +} + +LOCAL_INLINE void EFTU_SPE_ConfigNewInputIrq(EFTU_SPE_Type *const pSpe, boolean bEnable) +{ + if (bEnable == true) + { + pSpe->IRQ_EN |= EFTU_SPE_IRQ_EN_NIPD_EN_MASK; + } + else + { + pSpe->IRQ_EN &= ~EFTU_SPE_IRQ_EN_NIPD_EN_MASK; + } +} + +LOCAL_INLINE void EFTU_SPE_ConfigDircIrq(EFTU_SPE_Type *const pSpe, boolean bEnable) +{ + if (bEnable == true) + { + pSpe->IRQ_EN |= EFTU_SPE_IRQ_EN_DCHG_EN_MASK; + } + else + { + pSpe->IRQ_EN &= ~EFTU_SPE_IRQ_EN_DCHG_EN_MASK; + } +} + +LOCAL_INLINE void EFTU_SPE_ConfigEipdIrq(EFTU_SPE_Type *const pSpe, boolean bEnable) +{ + if (bEnable == true) + { + pSpe->IRQ_EN |= EFTU_SPE_IRQ_EN_EIPD_EN_MASK; + } + else + { + pSpe->IRQ_EN &= ~EFTU_SPE_IRQ_EN_EIPD_EN_MASK; + } +} + +LOCAL_INLINE void EFTU_SPE_ConfigBieIrq(EFTU_SPE_Type *const pSpe, boolean bEnable) +{ + if (bEnable == true) + { + pSpe->IRQ_EN |= EFTU_SPE_IRQ_EN_BIE_EN_MASK; + } + else + { + pSpe->IRQ_EN &= ~EFTU_SPE_IRQ_EN_BIE_EN_MASK; + } +} + +LOCAL_INLINE void EFTU_SPE_ConfigRcmpIrq(EFTU_SPE_Type *const pSpe, boolean bEnable) +{ + if (bEnable == true) + { + pSpe->IRQ_EN |= EFTU_SPE_IRQ_EN_RCMP_EN_MASK; + } + else + { + pSpe->IRQ_EN &= ~EFTU_SPE_IRQ_EN_RCMP_EN_MASK; + } +} + +LOCAL_INLINE uint8 EFTU_SPE_GetIrqFlag(EFTU_SPE_Type *const pSpe) +{ + return (uint8)((pSpe->IRQ_ST & EFTU_SPE_IRQ_ST_MASK)); +} + +LOCAL_INLINE uint8 EFTU_SPE_GetIrqnbleBit(EFTU_SPE_Type *const pSpe) +{ + return (uint8)((pSpe->IRQ_EN & EFTU_SPE_IRQ_EN_MASK)); +} + +LOCAL_INLINE void EFTU_SPE_ClearIrqMask(EFTU_SPE_Type *const pSpe, uint32 u32IrqMask) +{ + pSpe->IRQ_ST = u32IrqMask; +} + +LOCAL_INLINE void EFTU_SPE_SetCmpcntValue(EFTU_SPE_Type *const pSpe, uint32 u32CmpValue) +{ + pSpe->REV_CMP = u32CmpValue; +} + +LOCAL_INLINE void EFTU_SPE_SetIputcntValue(EFTU_SPE_Type *const pSpe, uint32 u32RevValue) +{ + pSpe->REV_CNT = u32RevValue; +} + +LOCAL_INLINE void EFTU_SPE_SoftWareTrigger(EFTU_SPE_Type *const pSpe) +{ + pSpe->CMD |= EFTU_SPE_CMD_SW_UPD_TRG_MASK; +} + +LOCAL_INLINE void EFTU_SPE_SetCmd(EFTU_SPE_Type *const pSpe, EFTU_SPE_ControlCmd eControlcmd) +{ + pSpe->CMD = ((pSpe->CMD & ~EFTU_SPE_CMD_CTRL_CMD_MASK) | (uint32)eControlcmd); +} + +LOCAL_INLINE void EFTU_SPE_SetFastshutSrc(EFTU_SPE_Type *const pSpe, EFTU_SPE_FastShutSrc eFastShut) +{ + pSpe->CTRL2 = ((pSpe->CTRL2 & ~EFTU_SPE_CTRL2_FSOI_SEL_MASK) | EFTU_SPE_CTRL2_FSOI_SEL(eFastShut)); +} + +LOCAL_INLINE void EFTU_SPE_SetDelayClkSrc(EFTU_SPE_Type *const pSpe, EFTU_SPE_DelayClockSrc eClockSrc) +{ + pSpe->CTRL2 = ((pSpe->CTRL2 & ~EFTU_SPE_CTRL2_DTRG_CLK_SEL_MASK) | + EFTU_SPE_CTRL2_DTRG_CLK_SEL(eClockSrc)); +} + +LOCAL_INLINE void EFTU_SPE_SetDelaycount(EFTU_SPE_Type *const pSpe, uint8 u8cnt) +{ + pSpe->CTRL2 = ((pSpe->CTRL2 & ~EFTU_SPE_CTRL2_DTRG_VAL_MASK) | EFTU_SPE_CTRL2_DTRG_VAL(u8cnt)); +} + +LOCAL_INLINE void EFTU_SPE_SetPatPtrBwd(EFTU_SPE_Type *const pSpe, EFTU_SPE_OutPatternType ePtrBwd) +{ + pSpe->CTRL2 = ((pSpe->CTRL2 & ~EFTU_SPE_CTRL2_PTR_BWD_MASK) | EFTU_SPE_CTRL2_PTR_BWD(ePtrBwd)); +} + +LOCAL_INLINE void EFTU_SPE_Enable(EFTU_SPE_Type *const pSpe) +{ + pSpe->CTRL |= EFTU_SPE_CTRL_EN_MASK; +} + +LOCAL_INLINE void EFTU_SPE_Disable(EFTU_SPE_Type *const pSpe) +{ + pSpe->CTRL &= ~EFTU_SPE_CTRL_EN_MASK; +} + +LOCAL_INLINE void EFTU_SPE_EnableHallInput(EFTU_SPE_Type *const pSpe) +{ + pSpe->CTRL |= EFTU_SPE_CTRL_SIE_MASK; +} + +LOCAL_INLINE void EFTU_SPE_DisableHallInput(EFTU_SPE_Type *const pSpe) +{ + pSpe->CTRL &= ~EFTU_SPE_CTRL_SIE_MASK; +} + +LOCAL_INLINE void EFTU_SPE_SetUpdateTrigger(EFTU_SPE_Type *const pSpe, + EFTU_SPE_UpdateTriggerType eUpdateTrigger) +{ + pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_TRG_SEL_MASK) | EFTU_SPE_CTRL_TRG_SEL(eUpdateTrigger)); +} + +LOCAL_INLINE void EFTU_SPE_SetExUpdateTrigger(EFTU_SPE_Type *const pSpe, + EFTU_SPE_UpdateExTriggerType eExUpdateTrigger) +{ + pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_TRG_ESEL_MASK) | + EFTU_SPE_CTRL_TRG_ESEL(eExUpdateTrigger)); +} + +LOCAL_INLINE void EFTU_SPE_SetPatPtr(EFTU_SPE_Type *const pSpe, EFTU_SPE_OutPatternType ePtr) +{ + pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_PAT_PTR_MASK) | EFTU_SPE_CTRL_PAT_PTR(ePtr)); +} + +LOCAL_INLINE void EFTU_SPE_EnableFastShut(EFTU_SPE_Type *const pSpe) +{ + pSpe->CTRL |= EFTU_SPE_CTRL_FSOM_MASK; +} + +LOCAL_INLINE void EFTU_SPE_DisableFastShut(EFTU_SPE_Type *const pSpe) +{ + pSpe->CTRL &= ~EFTU_SPE_CTRL_FSOM_MASK; +} + +LOCAL_INLINE void EFTU_SPE_ConfigAip(EFTU_SPE_Type *const pSpe, uint8 u8Aip) +{ + pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_AIP_MASK) | EFTU_SPE_CTRL_AIP(u8Aip)); +} + +LOCAL_INLINE void EFTU_SPE_ConfigPip(EFTU_SPE_Type *const pSpe, uint8 u8Pip) +{ + pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_PIP_MASK) | EFTU_SPE_CTRL_PIP(u8Pip)); +} + +LOCAL_INLINE void EFTU_SPE_ConfigRefSel(EFTU_SPE_Type *const pSpe, EFTU_SPE_RefSelectType eRefSel) +{ + pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_PIP_MASK) | EFTU_SPE_CTRL_REF_SEL(eRefSel)); +} + +LOCAL_INLINE void EFTU_SPE_ConfigShutoffLevel(EFTU_SPE_Type *const pSpe, uint8 u8Shutlevel) +{ + pSpe->CTRL = ((pSpe->CTRL & ~EFTU_SPE_CTRL_FSOL_MASK) | EFTU_SPE_CTRL_FSOL(u8Shutlevel)); +} + +LOCAL_INLINE uint8 EFTU_SPE_GetNip(EFTU_SPE_Type *const pSpe) +{ + return (uint8)((pSpe->CTRL & EFTU_SPE_CTRL_NIP_MASK) >> EFTU_SPE_CTRL_NIP_SHIFT); +} + +LOCAL_INLINE uint32 EFTU_SPE_GetHallPattern(EFTU_SPE_Type *const pSpe) +{ + return pSpe->HALL_IN_PAT; +} + +#endif /* (EFTU_INSTANCE_COUNT > 0U) && (EFTU_SPE_SUPPORT == STD_ON) && defined(EFTU_SPE_SUPPORT)*/ + +#endif /* TEMPLATE_HWA_INCLUDE_HWA_EFTU_SPE_H_ */ diff --git a/modular.json b/modular.json new file mode 100644 index 0000000..f32f9a8 --- /dev/null +++ b/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "./Inc" + ] + } +}