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Сборка нового проекта. Добавление основных модулей.

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/* Copyright Statement:
*
* This software/firmware and related documentation ("AutoChips Software") are
* protected under relevant copyright laws. The information contained herein is
* confidential and proprietary to AutoChips Inc. and/or its licensors. Without
* the prior written permission of AutoChips inc. and/or its licensors, any
* reproduction, modification, use or disclosure of AutoChips Software, and
* information contained herein, in whole or in part, shall be strictly
* prohibited.
*
* AutoChips Inc. (C) 2021. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE")
* RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
* ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
* NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH
* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
* INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES
* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS
* SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE
* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S
* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE
* RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE
* AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
* CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE.
*/
/*!
* @file device_assert.h
*
* @brief This file provides assert functions.
*
*/
#ifndef DEVICE_ASSERT_H
#define DEVICE_ASSERT_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* =========================================== Includes =========================================== */
/* ============================================ Define ============================================ */
/*!
* @brief The assert_param macro is used for function's check.
*
* @param expr: If x is false, it calls assert_failed function which reports
* the name of the source file and the source line number of the call
* that failed. If x is true, it returns no value.
* @retval none
*/
#ifdef ATC_DEVICE_ASSERT
#define DEVICE_ASSERT(x) ((x) ? (void)0 : (void)printf("[ASSERT]Detect error on %s %d\n", __FILE__, __LINE__) )
#elif defined(CUSTOM_DEVICE_ASSERT)
/* If the CUSTOM_DEVICE_ASSERT symbol is defined, then add the custom implementation */
#else
#define DEVICE_ASSERT(x) ((void)0)
#endif
/* =========================================== Typedef ============================================ */
/* ========================================== Variables =========================================== */
/* ==================================== Functions declaration ===================================== */
/* ====================================== Functions define ======================================== */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* DEVICE_ASSERT_H */
/* ============================================= EOF ============================================== */

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/* Copyright Statement:
*
* This software/firmware and related documentation ("AutoChips Software") are
* protected under relevant copyright laws. The information contained herein is
* confidential and proprietary to AutoChips Inc. and/or its licensors. Without
* the prior written permission of AutoChips inc. and/or its licensors, any
* reproduction, modification, use or disclosure of AutoChips Software, and
* information contained herein, in whole or in part, shall be strictly
* prohibited.
*
* AutoChips Inc. (C) 2021. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE")
* RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
* ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
* NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH
* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
* INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES
* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS
* SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE
* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S
* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE
* RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE
* AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
* CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE.
*/
/*!
* @file device_register.h
*
* @brief This file provides include the cpu specific register header files.
*
*/
#ifndef DEVICE_REGISTER_H
#define DEVICE_REGISTER_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "ac7840x.h"
#include "device_assert.h"
#include "ac7840x_features.h"
void nvic_system_reset(void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* DEVICE_REGISTER_H */
/* ============================================= EOF ============================================== */

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/* Copyright Statement:
*
* This software/firmware and related documentation ("AutoChips Software") are
* protected under relevant copyright laws. The information contained herein is
* confidential and proprietary to AutoChips Inc. and/or its licensors. Without
* the prior written permission of AutoChips inc. and/or its licensors, any
* reproduction, modification, use or disclosure of AutoChips Software, and
* information contained herein, in whole or in part, shall be strictly
* prohibited.
*
* AutoChips Inc. (C) 2021. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE")
* RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
* ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
* NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH
* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
* INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES
* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS
* SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE
* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S
* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE
* RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE
* AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
* CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE.
*/
/*!
* @file device_status.h
*
* @brief This file provides all device status enum.
*
*/
#ifndef DEVICE_STATUS_H
#define DEVICE_STATUS_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
typedef enum
{
/* Generic error codes */
STATUS_SUCCESS = 0x000U, /*!< Generic operation success status */
STATUS_ERROR = 0x001U, /*!< Generic operation failure status */
STATUS_BUSY = 0x002U, /*!< Generic operation busy status */
STATUS_TIMEOUT = 0x003U, /*!< Generic operation timeout status */
STATUS_UNSUPPORTED = 0x004U, /*!< Generic operation unsupported status */
/* MCU specific error codes */
STATUS_MCU_GATED_OFF = 0x100U, /*!< Module is gated off */
STATUS_MCU_TRANSITION_FAILED = 0x101U, /*!< Error occurs during transition. */
STATUS_MCU_INVALID_STATE = 0x102U, /*!< Unsupported in current state. */
STATUS_MCU_NOTIFY_BEFORE_ERROR = 0x103U, /*!< Error occurs during send "BEFORE" notification. */
STATUS_MCU_NOTIFY_AFTER_ERROR = 0x104U, /*!< Error occurs during send "AFTER" notification. */
/* I2C specific error codes */
STATUS_I2C_RECEIVED_NACK = 0x200U, /*!< NACK signal received */
STATUS_I2C_TX_UNDERRUN = 0x201U, /*!< TX underrun error */
STATUS_I2C_RX_OVERRUN = 0x202U, /*!< RX overrun error */
STATUS_I2C_ARBITRATION_LOST = 0x203U, /*!< Arbitration lost */
STATUS_I2C_ABORTED = 0x204U, /*!< A transfer was aborted */
STATUS_I2C_BUS_BUSY = 0x205U, /*!< I2C bus is busy, cannot start transfer */
/* Security specific error codes */
STATUS_SEC_SEQUENCE_ERROR = 0x402U, /*!< The sequence of commands or subcommands is out of
sequence */
STATUS_SEC_KEY_NOT_AVAILABLE = 0x403U, /*!< A key is locked due to failed boot measurement or
an active debugger */
STATUS_SEC_KEY_INVALID = 0x404U, /*!< A function is called to perform an operation with
a key that is not allowed for the given operation */
STATUS_SEC_KEY_EMPTY = 0x405U, /*!< Attempt to use a key that has not been initialized yet */
STATUS_SEC_NO_SECURE_BOOT = 0x406U, /*!< The conditions for a secure boot process are not met */
STATUS_SEC_KEY_WRITE_PROTECTED = 0x407U, /*!< Request for updating a write protected key slot,
or activating debugger with write protected key(s) */
STATUS_SEC_KEY_UPDATE_ERROR = 0x408U, /*!< Key update did not succeed due to errors in
verification of the messages */
STATUS_SEC_RNG_SEED = 0x409U, /*!< Returned by CMD_RND and CMD_DEBUG if the seed has not
been initialized before */
STATUS_SEC_NO_DEBUGGING = 0x40AU, /*!< DEBUG command authentication failed */
STATUS_SEC_MEMORY_FAILURE = 0x40CU, /*!< General memory technology failure
(multibit ECC error, common fault detected) */
STATUS_SEC_HSM_INTERNAL_MEMORY_ERROR = 0x410U, /*!< An internal memory error encountered while
executing the command */
STATUS_SEC_INVALID_COMMAND = 0x411U, /*!< Command value out of range */
STATUS_SEC_TRNG_ERROR = 0x412U, /*!< One or more statistical tests run on the TRNG output failed */
STATUS_SEC_HSM_FLASH_BLOCK_ERROR = 0x413U, /*!< Error reading, programming or erasing one of the HSM flash blocks */
STATUS_SEC_INTERNAL_CMD_ERROR = 0x414U, /*!< An internal command processor error while executing a command */
STATUS_SEC_MAC_LENGTH_ERROR = 0x415U, /*!< MAC/Message length out of range */
STATUS_SEC_INVALID_ARG = 0x421U, /*!< Invalid command argument */
STATUS_SEC_TRNG_CLOCK_ERROR = 0x423U, /*!< TRNG not provided with a stable clock */
/* SPI specific error codes */
STATUS_SPI_TX_UNDERRUN = 0x500U, /*!< TX underrun error */
STATUS_SPI_RX_OVERRUN = 0x501U, /*!< RX overrun error */
STATUS_SPI_ABORTED = 0x502U, /*!< A transfer was aborted */
/* UART specific error codes */
STATUS_UART_TX_UNDERRUN = 0x600U, /*!< TX underrun error */
STATUS_UART_RX_OVERRUN = 0x601U, /*!< RX overrun error */
STATUS_UART_ABORTED = 0x602U, /*!< A transfer was aborted */
STATUS_UART_FRAMING_ERROR = 0x603U, /*!< Framing error */
STATUS_UART_PARITY_ERROR = 0x604U, /*!< Parity error */
STATUS_UART_BREAK_ERROR = 0x605U, /*!< Break error */
STATUS_UART_NOISE_ERROR = 0x606U, /*!< Noise error */
/* I2S specific error codes */
STATUS_I2S_TX_UNDERRUN = 0x700U, /*!< TX underrun error */
STATUS_I2S_RX_OVERRUN = 0x701U, /*!< RX overrun error */
STATUS_I2S_ABORTED = 0x702U, /*!< A transfer was aborted */
} status_t;
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* DEVICE_STATUS_H */
/* ============================================= EOF ============================================== */

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/* Copyright Statement:
*
* This software/firmware and related documentation ("AutoChips Software") are
* protected under relevant copyright laws. The information contained herein is
* confidential and proprietary to AutoChips Inc. and/or its licensors. Without
* the prior written permission of AutoChips inc. and/or its licensors, any
* reproduction, modification, use or disclosure of AutoChips Software, and
* information contained herein, in whole or in part, shall be strictly
* prohibited.
*
* AutoChips Inc. (C) 2021. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE")
* RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
* ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
* NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH
* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
* INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES
* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS
* SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE
* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S
* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE
* RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE
* AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
* CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE.
*/
/*!
* @file system_ac7840x.h
*
* @brief This file provides system clock config integration functions interfaces.
*
*/
#ifndef SYSTEM_AC7840X_H
#define SYSTEM_AC7840X_H
#ifdef __cplusplus
extern "C" {
#endif
/* =========================================== Includes =========================================== */
#include <stdint.h>
/* ============================================ Define ============================================ */
#define STARTUP_HAL_MODULE_ID (13U)
#define STARTUP_HAL_SW_MAJOR_VERSION (3U)
#define STARTUP_HAL_SW_MINOR_VERSION (0U)
#define STARTUP_HAL_SW_PATCH_VERSION (5U)
/* ============================================ Define ============================================ */
/*!< Sram ECC read enable */
#define SRAM_ECC_READ_ENABLE (1UL)
/*!< Sram ECC 2bit error reset enable */
#define SRAM_ECC_ERR_RST_ENABLE (0UL)
/*!< Watchdog disable */
#ifndef WDG_DISABLE
#define WDG_DISABLE (1UL)
#endif
/*!< Don't initialize sram after reset except power on, lvr and standby wakeup */
#define NOT_INIT_SRAM_AFTER_RESET (1UL)
/*!< Default system clock */
#define DEFAULT_SYSTEM_CLOCK (48000000UL)
/*!< Default HSE(XOSC) frequency or user define */
#define CKGEN_HSE_FREQ (8000000UL)
/*!< System clock uses ckgen driver */
#define SYSTEM_USE_CKGEN (0UL)
/* PRQA S 3006,1006,3387 ++ */ /* assembler used. */
/*!< Global interrupt control */
extern volatile uint8_t s_disIrqReqTimes;
#define EnableInterrupts \
do { \
if (s_disIrqReqTimes > 0U) s_disIrqReqTimes--; \
if (s_disIrqReqTimes == 0U) __asm("CPSIE i"); \
} while(0)
#define DisableInterrupts \
do { \
if (s_disIrqReqTimes == 0U) __asm("CPSID i"); \
s_disIrqReqTimes++; \
} while(0)
/*!< Global fault control */
extern volatile uint8_t s_disIrqFltTimes;
#define EnableFatules \
do { \
if (s_disIrqFltTimes > 0U) s_disIrqFltTimes--; \
if (s_disIrqFltTimes == 0U) __asm("CPSIE F"); \
} while(0)
#define DisableFatules \
do { \
if (s_disIrqFltTimes == 0U) __asm("CPSID F"); \
s_disIrqFltTimes++; \
} while(0)
/* PRQA S 3006,1006,3387 -- */
/* =========================================== Typedef ============================================ */
/* ========================================== Variables =========================================== */
/* ==================================== Functions declaration ===================================== */
/*!
* @brief Initialize SPLL then set system clock to the SPLL clock
* (just support SPLL refer clock 4/8/12/16/30MHz, others need to modify).
*
* @param[in] refClk: 0: HSI clock, 1: HSE clock
* @param[in] freq: SPLL out frequency (16 - 120)
* @return status 0: success others: error
*/
uint32_t SetSysClkToSPLL(uint8_t refClk, uint8_t freq);
/*!
* @brief Initialize VHSI then set system clock to the VHSI clock.
*
* @param[in] none
* @return status 0: success others: error
*/
uint32_t SetSysClkToVHSI(void);
/*!
* @brief Initialize HSE then set system clock to the HSE clock.
*
* @param[in] bypass: 0: disable, 1: enable
* @return status 0: success others: error
*/
uint32_t SetSysClkToHSE(uint8_t bypass);
/*!
* @brief Initialize HSI then set system clock to the HSI clock.
*
* @param[in] none
* @return status 0: success others: error
*/
uint32_t SetSysClkToHSI(void);
/*!
* @brief Get UUID from devie
*
* @param[out] uuidBuffer: UUID buffer
* @return none
*/
void GetUUID(uint32_t *uuidBuffer);
/*!
* @brief Setup the microcontroller system. Initialize the System.
*
* @param[in] none
* @return none
*/
void SystemInit(void);
/*!
* @brief Initialize the SRAM to 0 for ECC.
*
* @param[in] StackBase: Main stack start address.
* @param[in] StackEnd: Main stack end address.
* @return none
*/
void InitSram(uint32_t StackBase, uint32_t StackEnd);
/*!
* @brief Update system clock frequence.
*
* @param[in] none
* @return none
*/
void SystemCoreClockUpdate(void);
/*!
* @brief Enable NMI, after set pinmux.
*
* @param[in] enable: enable state
* @return none
*/
void EnableNMI(uint8_t enable);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* SYSTEM_AC7840X_H */
/* ============================================= EOF ============================================== */

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{
"cmake": {
"inc_dirs": [
"inc"
],
"srcs": [
"src/**.c"
]
}
}

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/* Copyright Statement:
*
* This software/firmware and related documentation ("AutoChips Software") are
* protected under relevant copyright laws. The information contained herein is
* confidential and proprietary to AutoChips Inc. and/or its licensors. Without
* the prior written permission of AutoChips inc. and/or its licensors, any
* reproduction, modification, use or disclosure of AutoChips Software, and
* information contained herein, in whole or in part, shall be strictly
* prohibited.
*
* AutoChips Inc. (C) 2021. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE")
* RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
* ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL
* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
* NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH
* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
* INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES
* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS
* SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE
* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S
* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE
* RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE
* AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
* CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE.
*/
/*!
* @file system_ac7840x.c
*
* @brief This file provides system clock config integration functions.
*
*/
/* PRQA S 0380 EOF */ /* Number of macro definitions exceeds 4095 */
/* PRQA S 0306,0303 EOF */ /* Type conversion. */
/* PRQA S 2889 EOF */ /* More than one 'return'. */
/* PRQA S 3415 EOF */ /* with persistent side effects. */
/* PRQA S 1503,1505,3408 EOF */ /* Is defined but not used. */
/* =========================================== Includes =========================================== */
#include "device_register.h"
#if SYSTEM_USE_CKGEN
#include "ckgen_drv.h"
#endif
/* ============================================ Define ============================================ */
/** @brief Standby retention base address. */
#define SRAM_RETENTION_BASE (SRAM_U_START_ADDRESS - SRAM_RETENTION_SIZE)
/* =========================================== Typedef ============================================ */
/* ========================================== Variables =========================================== */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; /* System/core clock */
volatile uint8_t s_disIrqReqTimes = 0U;
volatile uint8_t s_disIrqFltTimes = 0U;
/* ==================================== Functions declaration ===================================== */
/* Externals declaration */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/* ====================================== Functions define ======================================== */
/*!
* @brief Initialize SPLL then set system clock to the SPLL clock
* (just support SPLL refer clock 4/8/12/16/30MHz, others need to modify).
*
* @param[in] refClk: 0: HSI clock, 1: HSE clock
* @param[in] freq: SPLL out frequency (16 - 120)
* @return status 0: success others: error
*/
uint32_t SetSysClkToSPLL(uint8_t refClk, uint8_t freq)
{
uint32_t ret = 0U, status, outFreq = freq;
uint32_t timeout = 100000U, posdiv, fbkdiv, prediv;
if (outFreq > 120U)
{
outFreq = 120U;
}
if (outFreq < 16U)
{
outFreq = 16U;
}
if (refClk != 0U)
{
/* Set XOSC bypass mode */
MODIFY_REG32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Msk, SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Pos, 0U);
/* XOSC enable */
SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_HSEEN_Msk);
do
{
status = READ_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_RDY_Msk);
--timeout;
} while ((0U == status) && (timeout != 0U));
if (0U == timeout)
{
ret = 1U;
}
/* SPLL configuration outFreq = (srcFreq / (prediv + 1)) * fbkdiv / (posdiv * 2) */
#if (CKGEN_HSE_FREQ == 30000000U) /* For HSE frequency 30MHz */
if (outFreq == 120U)
{
posdiv = 5U;
fbkdiv = 160U;
}
else if (outFreq == 96U)
{
posdiv = 5U;
fbkdiv = 128U;
}
else if (outFreq == 80U)
{
posdiv = 6U;
fbkdiv = 128U;
}
else /* Output frequency 48MHz */
{
posdiv = 10U;
fbkdiv = 128U;
outFreq = 48U;
}
prediv = 3U;
#elif (CKGEN_HSE_FREQ == 16000000U) /* For HSE frequency 16MHz */
if (outFreq > 64U)
{
posdiv = 4U;
fbkdiv = outFreq;
}
else if (outFreq > 32U)
{
posdiv = 8U;
fbkdiv = outFreq * 2U;
}
else
{
posdiv = 16U;
fbkdiv = outFreq * 4U;
}
prediv = 1U;
#elif (CKGEN_HSE_FREQ == 12000000U) /* For HSE frequency 12MHz */
if (outFreq > 62U)
{
posdiv = 6U;
fbkdiv = outFreq;
}
else if (outFreq > 31U)
{
posdiv = 12U;
fbkdiv = outFreq * 2U;
}
else
{
posdiv = 24U;
fbkdiv = outFreq * 4U;
}
prediv = 0U;
#elif (CKGEN_HSE_FREQ == 4000000U) /* For HSE frequency 4MHz */
if (outFreq > 64U)
{
posdiv = 4U;
fbkdiv = outFreq * 2;
}
else if (outFreq > 32U)
{
posdiv = 8U;
fbkdiv = outFreq * 4U;
}
else
{
posdiv = 16U;
fbkdiv = outFreq * 8U;
}
prediv = 0U;
#else /* For default HSE 8MHz */
if (outFreq > 64U)
{
posdiv = 4U;
fbkdiv = outFreq;
}
else if (outFreq > 32U)
{
posdiv = 8U;
fbkdiv = outFreq * 2U;
}
else
{
posdiv = 16U;
fbkdiv = outFreq * 4U;
}
prediv = 0U;
#endif
}
else
{
/* HSI enable */
SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_HSI_EN_NORMAL_Msk);
timeout = 1000U;
do
{
status = READ_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_HSI_RDY_Msk);
--timeout;
} while ((0U == status) && (timeout != 0U));
if (0U == timeout)
{
ret = 2U;
}
/* For HSI 8MHz */
if (outFreq > 64U)
{
posdiv = 4U;
fbkdiv = outFreq;
}
else if (outFreq > 32U)
{
posdiv = 8U;
fbkdiv = outFreq * 2U;
}
else
{
posdiv = 16U;
fbkdiv = outFreq * 4U;
}
prediv = 0U;
}
if (0U == ret)
{
CLEAR_BIT32(CKGEN->CTRL, CKGEN_CTRL_LOCK_Msk);
/* Configure SPLL */
if (refClk != 0U)
{
SET_BIT32(CKGEN->CTRL, CKGEN_CTRL_PLL_REF_SEL_Msk);
}
else
{
CLEAR_BIT32(CKGEN->CTRL, CKGEN_CTRL_PLL_REF_SEL_Msk);
}
MODIFY_REG32(ANA->SPLL_CFG0, ANA_SPLL_CFG0_POSDIV_Msk, ANA_SPLL_CFG0_POSDIV_Pos, posdiv);
MODIFY_REG32(ANA->SPLL_CFG0, ANA_SPLL_CFG0_FBKDIV_Msk, ANA_SPLL_CFG0_FBKDIV_Pos, fbkdiv);
MODIFY_REG32(ANA->SPLL_CFG0, ANA_SPLL_CFG0_PREDIV_Msk, ANA_SPLL_CFG0_PREDIV_Pos, prediv);
MODIFY_REG32(ANA->SPLL_CFG1, ANA_SPLL_CFG1_LD_DLY_SEL_Msk, ANA_SPLL_CFG1_LD_DLY_SEL_Pos, 3U);
/* SPLL enable */
SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_SPLL_EN_Msk);
timeout = 10000U;
do
{
status = READ_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_SPLL_RDY_Msk);
--timeout;
} while ((0U == status) && (timeout != 0U));
if (0U == timeout)
{
ret = 3U;
}
}
if (0U == ret)
{
/* Unlock and set flash clock frequency */
WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY1);
WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY2);
MODIFY_REG32(FLASH->CNFG, FLASH_CNFG_CLKFREQ_Msk, FLASH_CNFG_CLKFREQ_Pos, outFreq);
/* Switch system clock to spll */
MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos, 3U);
/* Set divider, default sysdiv is 1 divider and busdiv is 2 divider */
MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_DIV_Msk, CKGEN_CTRL_SYSCLK_DIV_Pos, 0U);
MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_BUS_CLK_DIV_RUN_Msk, CKGEN_CTRL_BUS_CLK_DIV_RUN_Pos, 1U);
/* Check current system clock */
if (3U != ((CKGEN->CTRL & CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk) >> CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos))
{
ret = 4U;
}
}
return ret;
}
/*!
* @brief Initialize VHSI then set system clock to the VHSI clock.
*
* @param[in] none
* @return status 0: success others: error
*/
uint32_t SetSysClkToVHSI(void)
{
uint32_t ret = 0U, status, timeout = 100U;
/* VHSI enable */
SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_VHSI_EN_Msk);
do
{
status = READ_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_VHSI_RDY_Msk);
--timeout;
} while ((0U == status) && (timeout != 0U));
if (0U == timeout)
{
ret = 1U;
}
if (0U == ret)
{
CLEAR_BIT32(CKGEN->CTRL, CKGEN_CTRL_LOCK_Msk);
/* Unlock and set flash clock frequency */
WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY1);
WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY2);
MODIFY_REG32(FLASH->CNFG, FLASH_CNFG_CLKFREQ_Msk, FLASH_CNFG_CLKFREQ_Pos, 48U);
/* Switch system clock to vhsi */
MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos, 0U);
/* Set divider, default sysdiv is 1 divider and busdiv is 2 divider */
MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_DIV_Msk, CKGEN_CTRL_SYSCLK_DIV_Pos, 0U);
MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_BUS_CLK_DIV_RUN_Msk, CKGEN_CTRL_BUS_CLK_DIV_RUN_Pos, 1U);
/* Check current system clock */
if (0U != ((CKGEN->CTRL & CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk) >> CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos))
{
ret = 2U;
}
}
return ret;
}
/*!
* @brief Initialize HSE then set system clock to the HSE clock.
*
* @param[in] bypass: 0: disable, 1: enable
* @return status 0: success others: error
*/
uint32_t SetSysClkToHSE(uint8_t bypass)
{
uint32_t ret = 0U, status, timeout = 100000U;
/* Set XOSC bypass mode */
if (bypass != 0U)
{
SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Msk);
}
else
{
CLEAR_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Msk);
}
/* XOSC enable */
SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_HSEEN_Msk);
do
{
status = READ_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_RDY_Msk);
--timeout;
} while ((0U == status) && (timeout != 0U));
if (0U == timeout)
{
ret = 1U;
}
if (0U == ret)
{
CLEAR_BIT32(CKGEN->CTRL, CKGEN_CTRL_LOCK_Msk);
/* Unlock and set flash clock frequency */
WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY1);
WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY2);
MODIFY_REG32(FLASH->CNFG, FLASH_CNFG_CLKFREQ_Msk, FLASH_CNFG_CLKFREQ_Pos, CKGEN_HSE_FREQ / 1000000U);
/* Switch system clock to hse */
MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos, 1U);
/* Set divider, default sysdiv is 1 divider and busdiv is 2 divider */
MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_DIV_Msk, CKGEN_CTRL_SYSCLK_DIV_Pos, 0U);
MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_BUS_CLK_DIV_RUN_Msk, CKGEN_CTRL_BUS_CLK_DIV_RUN_Pos, 1U);
/* Check current system clock */
if (1U != ((CKGEN->CTRL & CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk) >> CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos))
{
ret = 2U;
}
}
return ret;
}
/*!
* @brief Initialize HSI then set system clock to the HSI clock.
*
* @param[in] none
* @return status 0: success others: error
*/
uint32_t SetSysClkToHSI(void)
{
uint32_t ret = 0U, status, timeout = 100U;
/* HSI enable */
SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_HSI_EN_NORMAL_Msk);
do
{
status = READ_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_HSI_RDY_Msk);
--timeout;
} while ((0U == status) && (timeout != 0U));
if (0U == timeout)
{
ret = 1U;
}
if (0U == ret)
{
CLEAR_BIT32(CKGEN->CTRL, CKGEN_CTRL_LOCK_Msk);
/* Unlock and set flash clock frequency */
WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY1);
WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY2);
MODIFY_REG32(FLASH->CNFG, FLASH_CNFG_CLKFREQ_Msk, FLASH_CNFG_CLKFREQ_Pos, 8U);
/* Switch system clock to hsi */
MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos, 2U);
/* Set divider, default sysdiv is 1 divider and busdiv is 2 divider */
MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_DIV_Msk, CKGEN_CTRL_SYSCLK_DIV_Pos, 0U);
MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_BUS_CLK_DIV_RUN_Msk, CKGEN_CTRL_BUS_CLK_DIV_RUN_Pos, 1U);
/* Check current system clock */
if (2U != ((CKGEN->CTRL & CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk) >> CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos))
{
ret = 2U;
}
}
return ret;
}
/* PRQA S 3408 ++ */
/*!
* @brief Get MCU CPUID.
*
* @param[in] none
* @return MCU CPUID
*/
uint32_t GetCPUID(void)
{
return SCB->CPUID;
}
/* PRQA S 3408 -- */
/*!
* @brief Get UUID from device.
*
* @param[out] uuidBuffer: UUID buffer
* @return none
*/
void GetUUID(uint32_t *uuidBuffer)
{
#define UUID_BASE_ADDRESS 0x00201800U
uint32_t i;
if (uuidBuffer != NULL)
{
for (i = 0U; i < 4U; i++)
{
uuidBuffer[i] = (*(__IO uint32_t *)(UUID_BASE_ADDRESS + (i * 4U)));
}
}
}
/*!
* @brief Setup the microcontroller system. Initialize the System.
*
* @param[in] none
* @return none
*/
void SystemInit(void)
{
/* Sram L&U ECC read enable */
#if (SRAM_ECC_READ_ENABLE)
MCM->MLMDR0 |= MCM_MLMDR0_LREEN_Msk | MCM_MLMDR0_UREEN_Msk;
/* Sram ECC 2bit error reset disable */
#if !(SRAM_ECC_ERR_RST_ENABLE)
CKGEN->RCM_EN &= ~CKGEN_RCM_EN_ECC2_ERR_RST_EN_Msk;
#endif
#endif
/* Set CP10 and CP11 Full Access */
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << (10U * 2U)) | (3U << (11U * 2U)));
#endif
/* Disable watchdog */
#if (WDG_DISABLE)
#define WDG_UNLOCK_VALUE1 0xE064D987U
#define WDG_UNLOCK_VALUE2 0x868A8478U
WDG->CNT = (uint32_t)WDG_UNLOCK_VALUE1;
WDG->CNT = (uint32_t)WDG_UNLOCK_VALUE2;
WDG->CS0 &= ~WDG_CS0_EN_Msk;
#endif
/* Relocate vector table */
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if 0//NOT_INIT_SRAM_AFTER_RESET
/* Clear reset status, user can clear status in main when user need to read the reset status */
CKGEN->RCM_STATUS |= CKGEN_RCM_STATUS_RST_STATUS_CLR_Msk;
#endif
}
/*!
* @brief Initialize the SRAM to value.
*
* @param[in] Start: Main stack start address.
* @param[in] End: Main stack end address.
* @param[in] Val: Main stack end address.
* @return none
*/
/** @brief Initialize RAM from [start] to [end] with [val]. */
static void SystemInitRamInternal(uint32_t Start, uint32_t End, uint32_t Val)
{
uint32_t Addr = Start;
while (Addr < End)
{
*(__IO uint32_t *)(Addr) = Val;
*(__IO uint32_t *)(Addr + 4U) = Val;
Addr += 8U;
}
}
/*!
* @brief Initialize the SRAM to 0 for ECC.
*
* @param[in] StackBase: Main stack start address.
* @param[in] StackEnd: Main stack end address.
* @return none
*/
void InitSram(uint32_t StackBase, uint32_t StackEnd)
{
#if NOT_INIT_SRAM_AFTER_RESET
/* When the status is power on, lvr or standby wakeup, init SRAM */
if ((0U == (CKGEN->RCM_STATUS & (CKGEN_RCM_STATUS_POR_RST_FLAG_Msk | CKGEN_RCM_STATUS_LVR_RST_FLAG_Msk)))
&& (0U == (SPM->STB_WP_STATUS & 0x1FFFFU)))
{
return;
}
#endif
/* Initialize SRAM. */
if (0U == (SPM->STB_WP_STATUS & 0x1FFFFU)) /* POR. */
{
SystemInitRamInternal(SRAM_L_START_ADDRESS, StackBase, 0U);
SystemInitRamInternal(StackEnd, SRAM_U_END_ADDRESS, 0U);
}
else /* Standby wakeup skip the retention SRAM. */
{
if (StackEnd <= SRAM_RETENTION_BASE)
{ /* Stack locate in SRAM_L but not in retention. */
SystemInitRamInternal(SRAM_L_START_ADDRESS, StackBase, 0U);
SystemInitRamInternal(StackEnd, SRAM_RETENTION_BASE, 0U);
SystemInitRamInternal(SRAM_U_START_ADDRESS, SRAM_U_END_ADDRESS, 0U);
}
else if (StackBase >= SRAM_U_START_ADDRESS)
{ /* Stack locate in SRAM_U. */
SystemInitRamInternal(SRAM_L_START_ADDRESS, SRAM_RETENTION_BASE, 0U);
SystemInitRamInternal(SRAM_U_START_ADDRESS, StackBase, 0U);
SystemInitRamInternal(StackEnd, SRAM_U_END_ADDRESS, 0U);
}
else if ((StackBase < SRAM_RETENTION_BASE) && (StackEnd > SRAM_RETENTION_BASE))
{ /* Stack location in SRAM_L and retention. */
SystemInitRamInternal(SRAM_L_START_ADDRESS, StackBase, 0U);
SystemInitRamInternal(SRAM_U_START_ADDRESS, SRAM_U_END_ADDRESS, 0U);
}
else if ((StackBase < SRAM_U_START_ADDRESS) && (StackEnd > SRAM_U_START_ADDRESS))
{ /* Stack location in SRAM_U and retention. */
SystemInitRamInternal(SRAM_L_START_ADDRESS, SRAM_RETENTION_BASE, 0U);
SystemInitRamInternal(StackEnd, SRAM_U_END_ADDRESS, 0U);
}
else
{ /* Stack location in retention fullly. */
SystemInitRamInternal(SRAM_L_START_ADDRESS, SRAM_RETENTION_BASE, 0U);
SystemInitRamInternal(SRAM_U_START_ADDRESS, SRAM_U_END_ADDRESS, 0U);
}
}
/* Initialize FlexRAM if not used by CSE. */
if (READ_BIT32(FLASH->PART, FLASH_PART_EPART_Msk) == FLASH_PART_EPART_Msk)
{
SystemInitRamInternal(FLEXRAM_BASE_ADDRESS, (FLEXRAM_BASE_ADDRESS + FLEX_RAM_SIZE), 0U);
}
}
/*!
* @brief Update system clock frequence.
*
* @param[in] none
* @return none
*/
void SystemCoreClockUpdate(void)
{
#if SYSTEM_USE_CKGEN
(void)CKGEN_DRV_GetFreq(CORE_CLK, &SystemCoreClock);
#else
uint32_t runMode, clkSrc, sysDiv, prediv, fbkdiv, postdiv, srcFreq;
runMode = SPM->STATUS & SPM_STATUS_CURR_POWER_MODE_Msk;
if (1U == runMode) /* VLPR mode */
{
sysDiv = (CKGEN->CTRL & CKGEN_CTRL_SYSCLK_DIV_VLPR_Msk) >> CKGEN_CTRL_SYSCLK_DIV_VLPR_Pos;
srcFreq = CKGEN_HSI_FREQ;
}
else /* RUN mode */
{
sysDiv = (CKGEN->CTRL & CKGEN_CTRL_SYSCLK_DIV_Msk) >> CKGEN_CTRL_SYSCLK_DIV_Pos;
clkSrc = (CKGEN->CTRL & CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk) >> CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos;
switch (clkSrc)
{
case 1U: /* HSE clock, user define */
srcFreq = CKGEN_HSE_FREQ;
break;
case 2U: /* HSI clock */
srcFreq = CKGEN_HSI_FREQ;
break;
case 3U: /* SPLL clock */
prediv = (ANA->SPLL_CFG0 & ANA_SPLL_CFG0_PREDIV_Msk) >> ANA_SPLL_CFG0_PREDIV_Pos;
fbkdiv = (ANA->SPLL_CFG0 & ANA_SPLL_CFG0_FBKDIV_Msk) >> ANA_SPLL_CFG0_FBKDIV_Pos;
postdiv = (ANA->SPLL_CFG0 & ANA_SPLL_CFG0_POSDIV_Msk) >> ANA_SPLL_CFG0_POSDIV_Pos;
/* Get reference clock */
if (0U == ((CKGEN->CTRL & CKGEN_CTRL_PLL_REF_SEL_Msk) >> CKGEN_CTRL_PLL_REF_SEL_Pos))
{
srcFreq = CKGEN_HSI_FREQ;
}
else
{
srcFreq = CKGEN_HSE_FREQ;
}
/* Calculate SPLL frequency */
if (postdiv != 0U)
{
srcFreq = (srcFreq / (prediv + 1U)) * fbkdiv / (postdiv * 2U);
}
break;
default: /* VHSI clock */
srcFreq = CKGEN_VHSI_FREQ;
break;
}
}
SystemCoreClock = srcFreq / (sysDiv + 1U);
#endif
}
/*!
* @brief Enable NMI, after set pinmux.
*
* @param[in] enable: enable state
* @return none
*/
void EnableNMI(uint8_t enable)
{
if (enable != 0U)
{
SET_BIT32(MCM->MNCR, MCM_MNCR_NMI_EN_Msk);
}
else
{
CLEAR_BIT32(MCM->MNCR, MCM_MNCR_NMI_EN_Msk);
}
}
void nvic_system_reset(void)
{
NVIC_SystemReset();
}
/* ============================================= EOF ============================================== */