From eee622998c8e6746fd142e4f753447372f87faf3 Mon Sep 17 00:00:00 2001 From: cfif Date: Fri, 11 Jul 2025 13:36:31 +0300 Subject: [PATCH] =?UTF-8?q?=D0=A1=D0=B1=D0=BE=D1=80=D0=BA=D0=B0=20=D0=BD?= =?UTF-8?q?=D0=BE=D0=B2=D0=BE=D0=B3=D0=BE=20=D0=BF=D1=80=D0=BE=D0=B5=D0=BA?= =?UTF-8?q?=D1=82=D0=B0.=20=D0=94=D0=BE=D0=B1=D0=B0=D0=B2=D0=BB=D0=B5?= =?UTF-8?q?=D0=BD=D0=B8=D0=B5=20=D0=BE=D1=81=D0=BD=D0=BE=D0=B2=D0=BD=D1=8B?= =?UTF-8?q?=D1=85=20=D0=BC=D0=BE=D0=B4=D1=83=D0=BB=D0=B5=D0=B9.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- inc/ac7840x.h | 6936 ++++++++++++++++++++++++++++++++++++++++ inc/ac7840x_features.h | 1236 +++++++ inc/device_assert.h | 81 + inc/device_register.h | 60 + inc/device_status.h | 120 + inc/system_ac7840x.h | 197 ++ modular.json | 10 + src/system_ac7840x.c | 681 ++++ 8 files changed, 9321 insertions(+) create mode 100644 inc/ac7840x.h create mode 100644 inc/ac7840x_features.h create mode 100644 inc/device_assert.h create mode 100644 inc/device_register.h create mode 100644 inc/device_status.h create mode 100644 inc/system_ac7840x.h create mode 100644 modular.json create mode 100644 src/system_ac7840x.c diff --git a/inc/ac7840x.h b/inc/ac7840x.h new file mode 100644 index 0000000..6c17efb --- /dev/null +++ b/inc/ac7840x.h @@ -0,0 +1,6936 @@ +/* + * Copyright Statement: + * + * This software/firmware and related documentation ("AutoChips Software") are + * protected under relevant copyright laws. The information contained herein is + * confidential and proprietary to AutoChips Inc. and/or its licensors. Without + * the prior written permission of AutoChips inc. and/or its licensors, any + * reproduction, modification, use or disclosure of AutoChips Software, and + * information contained herein, in whole or in part, shall be strictly + * prohibited. + * + * AutoChips Inc. (C) 2021. All rights reserved. + * + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE") + * RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER + * ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL + * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR + * NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH + * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, + * INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES + * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. + * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO + * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS + * SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE + * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S + * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE + * RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE + * AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE + * CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE. + * + * @file AC7840x.h + * @brief CMSIS HeaderFile + * @version 1.0 + * @date 02. June 2021 + * @note Generated by SVDConv V3.3.27 on Wednesday, 02.06.2021 14:09:31 + * from File 'ac7840x.svd', + * last modified on Wednesday, 02.06.2021 06:05:59 + */ + + + +/** @addtogroup AutoChips + * @{ + */ + + +/** @addtogroup AC7840x + * @{ + */ + + +#ifndef AC7840X_H +#define AC7840X_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* PRQA S 3630 EOF */ /* The implementation of the object should be hidden, Maybe use by app. */ +/* PRQA S 1535 EOF */ /* A project should not contain unused type declarations, Maybe use by app. */ +/* PRQA S 0791 EOF */ /* Macro identifiers shall be distinct */ +/* PRQA S 0602 EOF */ +/* PRQA S 0603 EOF */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + NonMaskableInt_IRQn = -14, /*!< -14 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ +/* =========================================== AC7840x Specific Interrupt Numbers ========================================== */ + DMA0_CHANNEL0_IRQn = 0, /*!< 0 DMA0 channel 0 interrupt */ + DMA0_CHANNEL1_IRQn = 1, /*!< 1 DMA0 channel 1 interrupt */ + DMA0_CHANNEL2_IRQn = 2, /*!< 2 DMA0 channel 2 interrupt */ + DMA0_CHANNEL3_IRQn = 3, /*!< 3 DMA0 channel 3 interrupt */ + DMA0_CHANNEL4_IRQn = 4, /*!< 4 DMA0 channel 4 interrupt */ + DMA0_CHANNEL5_IRQn = 5, /*!< 5 DMA0 channel 5 interrupt */ + DMA0_CHANNEL6_IRQn = 6, /*!< 6 DMA0 channel 6 interrupt */ + DMA0_CHANNEL7_IRQn = 7, /*!< 7 DMA0 channel 7 interrupt */ + DMA0_CHANNEL8_IRQn = 8, /*!< 8 DMA0 channel 8 interrupt */ + DMA0_CHANNEL9_IRQn = 9, /*!< 9 DMA0 channel 9 interrupt */ + DMA0_CHANNEL10_IRQn = 10, /*!< 10 DMA0 channel 10 interrupt */ + DMA0_CHANNEL11_IRQn = 11, /*!< 11 DMA0 channel 11 interrupt */ + DMA0_CHANNEL12_IRQn = 12, /*!< 12 DMA0 channel 12 interrupt */ + DMA0_CHANNEL13_IRQn = 13, /*!< 13 DMA0 channel 13 interrupt */ + DMA0_CHANNEL14_IRQn = 14, /*!< 14 DMA0 channel 14 interrupt */ + DMA0_CHANNEL15_IRQn = 15, /*!< 15 DMA0 channel 15 interrupt */ + PORTA_IRQn = 16, /*!< 16 PORTA interrupt */ + PORTB_IRQn = 17, /*!< 17 PORTB interrupt */ + PORTC_IRQn = 18, /*!< 18 PORTC interrupt */ + PORTD_IRQn = 19, /*!< 19 PORTD interrupt */ + PORTE_IRQn = 20, /*!< 20 PORTE interrupt */ + UART0_IRQn = 21, /*!< 21 UART0 interrupt */ + UART1_IRQn = 22, /*!< 22 UART1 interrupt */ + UART2_IRQn = 23, /*!< 23 UART2 interrupt */ + UART3_IRQn = 24, /*!< 24 UART3 interrupt */ + SPI0_IRQn = 27, /*!< 27 SPI0 interrupt */ + SPI1_IRQn = 28, /*!< 28 SPI1 interrupt */ + SPI2_IRQn = 29, /*!< 29 SPI2 interrupt */ + I2C0_IRQn = 31, /*!< 31 I2C0 interrupt */ + EIO_IRQn = 33, /*!< 33 EIO interrupt */ + CAN0_IRQn = 34, /*!< 34 CAN0 interrupt */ + CAN0_WAKEUP_IRQn = 35, /*!< 35 CAN0 wakeup interrupt */ + CAN1_IRQn = 36, /*!< 36 CAN1 interrupt */ + CAN1_WAKEUP_IRQn = 37, /*!< 37 CAN1 wakeup interrupt */ + CAN2_IRQn = 38, /*!< 38 CAN2 interrupt */ + CAN2_WAKEUP_IRQn = 39, /*!< 39 CAN2 wakeup interrupt */ + CAN3_IRQn = 40, /*!< 40 CAN3 interrupt */ + CAN3_WAKEUP_IRQn = 41, /*!< 41 CAN3 wakeup interrupt */ + PDT0_IRQn = 46, /*!< 46 PDT0 interrupt */ + PDT1_IRQn = 47, /*!< 47 PDT1 interrupt */ + ADC0_IRQn = 48, /*!< 48 ADC0 interrupt */ + ADC1_IRQn = 49, /*!< 49 ADC1 interrupt */ + ACMP0_IRQn = 50, /*!< 50 ACMP0 interrupt */ + WDG_IRQn = 51, /*!< 51 WDG interrupt */ + EWDG_IRQn = 52, /*!< 52 EWDG interrupt */ + MCM_IRQn = 53, /*!< 53 MCM interrupt */ + LVD_IRQn = 54, /*!< 54 LVD interrupt */ + SPM_IRQn = 55, /*!< 55 SPM interrupt */ + RCM_IRQn = 56, /*!< 56 RCM interrupt */ + PWM0_OVERFLOW_IRQn = 57, /*!< 57 PWM0 Overflow interrupt */ + PWM0_CHANNEL_IRQn = 58, /*!< 58 PWM0 Channel interrupt */ + PWM0_FAULT_IRQn = 59, /*!< 59 PWM0 Fault interrupt */ + PWM1_OVERFLOW_IRQn = 60, /*!< 60 PWM1 Overflow interrupt */ + PWM1_CHANNEL_IRQn = 61, /*!< 61 PWM1 Channel interrupt */ + PWM1_FAULT_IRQn = 62, /*!< 62 PWM1 Fault interrupt */ + PWM2_OVERFLOW_IRQn = 63, /*!< 63 PWM2 Overflow interrupt */ + PWM2_CHANNEL_IRQn = 64, /*!< 64 PWM2 Channel interrupt */ + PWM2_FAULT_IRQn = 65, /*!< 65 PWM2 Fault interrupt */ + PWM3_OVERFLOW_IRQn = 66, /*!< 66 PWM3 Overflow interrupt */ + PWM3_CHANNEL_IRQn = 67, /*!< 67 PWM3 Channel interrupt */ + PWM3_FAULT_IRQn = 68, /*!< 68 PWM3 Fault interrupt */ + PWM4_OVERFLOW_IRQn = 69, /*!< 69 PWM4 Overflow interrupt */ + PWM4_CHANNEL_IRQn = 70, /*!< 70 PWM4 Channel interrupt */ + PWM4_FAULT_IRQn = 71, /*!< 71 PWM4 Fault interrupt */ + PWM5_OVERFLOW_IRQn = 72, /*!< 72 PWM5 Overflow interrupt */ + PWM5_CHANNEL_IRQn = 73, /*!< 73 PWM5 Channel interrupt */ + PWM5_FAULT_IRQn = 74, /*!< 74 PWM5 Fault interrupt */ + RTC_IRQn = 81, /*!< 81 RTC interrupt */ + PCT_IRQn = 82, /*!< 82 PCT interrupt */ + TIMER_CHANNEL0_IRQn = 83, /*!< 83 TIMER channel 0 interrupt */ + TIMER_CHANNEL1_IRQn = 84, /*!< 84 TIMER channel 1 interrupt */ + TIMER_CHANNEL2_IRQn = 85, /*!< 85 TIMER channel 2 interrupt */ + TIMER_CHANNEL3_IRQn = 86, /*!< 86 TIMER channel 3 interrupt */ + CSE_IRQn = 87, /*!< 87 CSE interrupt */ + FLASH_ECC_IRQn = 88, /*!< 88 FLASH ECC 2-bit interrupt */ + FLASH_IRQn = 89, /*!< 89 FLASH command complete interrupt */ + FLASH_COLLISION_IRQn = 90, /*!< 90 FLASH collision interrupt */ + ECC_1BIT_ERROR_IRQn = 91, /*!< 91 ECC 1bit error interrupt */ + ECC_2BIT_ERROR_IRQn = 92, /*!< 92 ECC 2bit error interrupt */ + MAX_IRQn = 93 /*!< 93 Max interrupt */ +} IRQn_Type; + + +/** + * @brief setting bits macro. + */ +#ifndef SET_BIT32 + #define SET_BIT32(reg, mask) ((reg) |= (uint32_t)(mask)) +#endif + +/** + * @brief clearing bits macro. + */ +#ifndef CLEAR_BIT32 + #define CLEAR_BIT32(reg, mask) ((reg) &= (~((uint32_t)(mask)))) +#endif + +/** + * @brief read bits macro. + */ +#ifndef READ_BIT32 + #define READ_BIT32(reg, mask) ((reg) & ((uint32_t)(mask))) +#endif + +/** + * @brief write register macro. + */ +#ifndef WRITE_REG32 + #define WRITE_REG32(reg, value) ((reg) = (uint32_t)(value)) +#endif + +/** + * @brief clear bits and set with new value. + */ +#ifndef MODIFY_REG32 + #define MODIFY_REG32(reg, mask, pos, value) (WRITE_REG32((reg), (((reg) & (~((uint32_t)(mask)))) | (((uint32_t)(value)) << (pos))))) +#endif + +/** + * @brief read register parameter macro. + */ +#ifndef READ_PARAM32 + #define READ_PARAM32(reg, mask, pos) (((reg) & ((uint32_t)(mask))) >> (pos)) +#endif + +/** + * @brief read 32 bits memory macro. + */ +#ifndef READ_MEM32 + #define READ_MEM32(address) (*(volatile uint32_t *)(address)) +#endif + +/** + * @brief write 32 bits memory macro. + */ +#ifndef WRITE_MEM32 + #define WRITE_MEM32(address, value) ((*(volatile uint32_t *)(address))= (uint32_t)(value)) +#endif + +/** + * @brief clear bits and set with new value for memory. + */ +#ifndef MODIFY_MEM32 + #define MODIFY_MEM32(address, mask, pos, value) (WRITE_MEM32((address), ((READ_MEM32(address) & (~((uint32_t)(mask)))) | (((uint32_t)(value)) << (pos))))) +#endif + +#include +#include +#include + +/* PRQA S 1535,2052,4548 ++ */ /* This type maybe use by app. */ +/** + * @brief global enumeration. + */ +typedef enum {DISABLE = 0U, ENABLE = !DISABLE} ACTION_Type; + +typedef enum {ERROR = 0U, SUCCESS = !ERROR} ERROR_Type; +/* PRQA S 1535,2052,4548 -- */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 0 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "device_status.h" /*!< device status */ +#include "system_ac7840x.h" /*!< AC7840x System */ + + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* PRQA S 3638 ++ */ +/* --------------------------------------------- section using anonymous unions ------------------------------------------- */ +#if defined(__CC_ARM) + #pragma anon_unions +#elif defined(CCARM__) + #pragma language=extended +#elif defined (__ICCARM__) +/* anonymous unions are enabled by default */ +#elif (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* anonymous unions are enabled by default */ +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__ghs__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #error Not supported compiler type +#endif +/* PRQA S 3638 -- */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ MCM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Core Platform Miscellaneous Control Module (MCM) + */ + +typedef struct { /*!< (@ 0xE008000C) MCM Structure */ + __IOM uint32_t MCPCR; /*!< (@ 0x00000000) MCM Core Platform Control Register */ + __IOM uint32_t MISCR; /*!< (@ 0x00000004) MCM Interrupt Status and Control Register */ + __IM uint32_t RESERVED[251]; + __IOM uint32_t MLMDR0; /*!< (@ 0x000003F4) MCM Local MCM Local Memory Descriptor Register0 */ + __IM uint32_t MBIST; /*!< (@ 0x000003F8) MCM Local Memory BIST Register */ + __IOM uint32_t MLMDR1; /*!< (@ 0x000003FC) MCM Local MCM Local Memory Descriptor Register1 */ + __IOM uint32_t LMPECR; /*!< (@ 0x00000400) MCM Local Memory Cache ECC Enable Control Register */ + __IOM uint32_t LMPEIR; /*!< (@ 0x00000404) MCM Local Memory Cache ECC Error Status Register */ + __IM uint32_t LMFAR; /*!< (@ 0x00000408) MCM Local Memory Cache ECC Error Address Register */ + __IOM uint32_t MCCR; /*!< (@ 0x0000040C) MCM Cache Control Register */ + __IM uint32_t RESERVED1[25]; + __IOM uint32_t MNCR; /*!< (@ 0x00000474) MCM NMI Control Register */ +} MCM_Type; /*!< Size = 1144 (0x478) */ + + +/* =========================================================================================================================== */ +/* ================ MPU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Memory protection unit (MPU) + */ +/* MPU - Size of Registers Arrays */ +#define MPU_EAR_EDR_COUNT (3UL) +#define MPU_RGD_COUNT (8UL) +#define MPU_RGDAAC_COUNT (8UL) + + +typedef struct { /*!< (@ 0x40006000) MPU Structure */ + __IOM uint32_t CESR; /*!< (@ 0x00000000) Control/Error Status Register */ + __IOM uint32_t EAR[MPU_EAR_EDR_COUNT]; + __IOM uint32_t EDR[MPU_EAR_EDR_COUNT]; + __IOM uint32_t MPID; + __IOM uint32_t WORD0_RGD[MPU_RGD_COUNT]; + __IOM uint32_t WORD1_RGD[MPU_RGD_COUNT]; + __IOM uint32_t WORD2_RGD[MPU_RGD_COUNT]; + __IOM uint32_t WORD3_RGD[MPU_RGD_COUNT]; + __IOM uint32_t RESERVED[216]; + __IOM uint32_t RGDAAC[MPU_RGDAAC_COUNT]; /*!< (@ 0x0000008C) Region Descriptor Alternate Access Control n */ +} MPU_Type; /*!< Size = 1056 (0x420) */ + + +/* =========================================================================================================================== */ +/* ================ CKGEN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock Generator (CKGEN) + */ + +typedef struct { /*!< (@ 0x40000000) CKGEN Structure */ + __IOM uint32_t CTRL; /*!< (@ 0x00000000) CKGEN Control Register */ + __IOM uint32_t LP_CLK_MUX; /*!< (@ 0x00000004) RTC LSI Clock Mux */ + __IOM uint32_t PERI_CLK_EN0; /*!< (@ 0x00000008) Periph Clock Enable Control 0 */ + __IOM uint32_t PERI_CLK_EN1; /*!< (@ 0x0000000C) Periph Clock Enable Control 1 */ + __IOM uint32_t PERI_CLK_EN2; /*!< (@ 0x00000010) Periph Clock Enable Control 2 */ + __IOM uint32_t RCM_CTRL; /*!< (@ 0x00000014) MCU Reset Control */ + __IOM uint32_t RCM_EN; /*!< (@ 0x00000018) MCU Reset Enable Control */ + __IOM uint32_t RCM_STATUS; /*!< (@ 0x0000001C) MCU Reset Status */ + __IOM uint32_t PERI_SFT_RST0; /*!< (@ 0x00000020) Periph Software Reset Control 0 */ + __IOM uint32_t PERI_SFT_RST1; /*!< (@ 0x00000024) Periph Software Reset Control 1 */ + __IOM uint32_t PERI_SFT_RST2; /*!< (@ 0x00000028) Periph Software Reset Control 2 */ + __IOM uint32_t CLK_DIV1; /*!< (@ 0x0000002C) Clock Divider 1 */ + __IOM uint32_t CLK_DIV2; /*!< (@ 0x00000030) Clock Divider 2 */ + __IOM uint32_t PERI_CLK_MUX0; /*!< (@ 0x00000034) Peripheral Clock MUX0 Register */ + __IOM uint32_t PERI_CLK_MUX1; /*!< (@ 0x00000038) Peripheral Clock MUX1 Register */ + __IOM uint32_t PERI_CLK_MUX2; /*!< (@ 0x0000003C) Peripheral Clock MUX2 Register */ + __IOM uint32_t PERI_CLK_MUX3; /*!< (@ 0x00000040) Peripheral Clock MUX3 Register */ + __IM uint32_t RESERVED; + __IOM uint32_t CLK_OUT_CFG; /*!< (@ 0x00000048) Clock Out Configure */ + __IOM uint32_t PERI_CLK_DIV; /*!< (@ 0x0000004C) Peripheral Clock Divider */ +} CKGEN_Type; /*!< Size = 80 (0x50) */ + + +/* =========================================================================================================================== */ +/* ================ PBR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Peripheral Bridge (PBR) + */ + +typedef struct { /*!< (@ 0x4008A000) PBR Structure */ + __IOM uint32_t MPR_CORE; /*!< (@ 0x00000000) Master Core Privilege Configure Register */ + __IOM uint32_t MPR_DEBUG; /*!< (@ 0x00000004) Master Debugger Privilege Configure Register */ + __IOM uint32_t MPR_DMA; /*!< (@ 0x00000008) Master DMA Privilege Configure Register */ + __IM uint32_t RESERVED; + __IOM uint32_t PACRA; /*!< (@ 0x00000010) Peripheral Access Control Register A */ + __IOM uint32_t PACRB; /*!< (@ 0x00000014) Peripheral Access Control Register B */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t PACRC; /*!< (@ 0x00000020) Peripheral Access Control Register C */ + __IOM uint32_t PACRD; /*!< (@ 0x00000024) Peripheral Access Control Register D */ + __IOM uint32_t PACRE; /*!< (@ 0x00000028) Peripheral Access Control Register E */ + __IM uint32_t RESERVED2; + __IOM uint32_t PACRF; /*!< (@ 0x00000030) Peripheral Access Control Register F */ + __IOM uint32_t PACRG; /*!< (@ 0x00000034) Peripheral Access Control Register G */ +} PBR_Type; /*!< Size = 56 (0x38) */ + + +/* =========================================================================================================================== */ +/* ================ SPM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System Power Manage (SPM) + */ + +typedef struct { /*!< (@ 0x40008000) SPM Structure */ + __IOM uint32_t PWR_MGR_CFG0; /*!< (@ 0x00000000) Power Manage Config Register 0 */ + __IOM uint32_t PWR_MGR_CFG1; /*!< (@ 0x00000004) Power Manage Config Register 1 */ + __IM uint32_t RESERVED; + __IM uint32_t PERIPH_SLEEP_ACK_STATUS; /*!< (@ 0x0000000C) Periph Sleep Ack Status Register */ + __IOM uint32_t PERIPH_SLEEP_ACK_EN; /*!< (@ 0x00000010) Periph Sleep Ack Enable Register */ + __IOM uint32_t STATUS; /*!< (@ 0x00000014) Status Register */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t STB_WP_EN; /*!< (@ 0x00000028) Standby Wakeup Enable Register */ + __IOM uint32_t STB_WP_STATUS; /*!< (@ 0x0000002C) Standby Wakeup Status Register */ +} SPM_Type; /*!< Size = 48 (0x30) */ + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* PRQA S 3630 ++ */ /* May be use by app. */ +/** + * @brief General Purpose Input/Output (GPIO) + */ + +typedef struct { /*!< (@ 0x40084000) GPIO Structure */ + __IOM uint32_t PODR; /*!< (@ 0x00000000) PORT Output Data Register */ + __IOM uint32_t PSOR; /*!< (@ 0x00000004) PORT Set Output Register */ + __IOM uint32_t PROR; /*!< (@ 0x00000008) PORT Reset Output Register */ + __IOM uint32_t PIOR; /*!< (@ 0x0000000C) PORT Invert Output Register */ + __IOM uint32_t PIDR; /*!< (@ 0x00000010) PORT Input Data Register */ + __IOM uint32_t POER; /*!< (@ 0x00000014) PORT Output Enable Register */ + __IOM uint32_t PIER; /*!< (@ 0x00000018) PORT Input Enable Register */ +} GPIO_Type; /*!< Size = 28 (0x1c) */ + + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + + +#define PORT_PCR_COUNT (32UL) /*!< PORT - size of registers array */ + +/** + * @brief Pin Control and Interrupts (PORT) + */ + +typedef struct { /*!< (@ 0x40084200) PORT Structure */ + __IOM uint32_t PCR[PORT_PCR_COUNT]; /*!< (@ 0x00000000~0x0000007C) Pin Control Register n */ + __IM uint32_t RESERVED[8]; + __IOM uint32_t ISFR; /*!< (@ 0x000000A0) Interrupt Status Flag Register */ + __IM uint32_t RESERVED1[7]; + __IOM uint32_t DFER; /*!< (@ 0x000000C0) Digital Filter Enable Register */ + __IOM uint32_t DFCR; /*!< (@ 0x000000C4) Digital Filter Clock Register */ + __IOM uint32_t DFWR; /*!< (@ 0x000000C8) Digital Filter Width Register */ +} PORT_Type; /*!< Size = 204 (0xcc) */ + + +/* =========================================================================================================================== */ +/* ================ CAN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controller Area Network (CAN) + */ + +#define CAN_BUF_LENGTH (64 / 4) /*!< CAN buffer length */ + +/** + * @brief CAN receive buffer register define structure + */ + +typedef struct +{ + __IO uint32_t ID_ESI; /*!< [0:28]: Identifier (ID), [30]: Transmit time-stamp enable (TTSEN) */ + /*!< [31]: Error state indicator (ESI) */ + __IO uint32_t CTRL; /*!< [0:3]: Data length code (DLC), [4]: Bit rate switch (BRS) */ + /*!< [5]: FD format indicator (FDF), [6]: Remote transmission request (RTR) */ + /*!< [7]: Identifier extension (IDE), [12]: For lookback mode (TX) */ + /*!< [13:15]: Kind of error (KOER) */ + __IO uint32_t DATA[CAN_BUF_LENGTH]; /*!< Buffer data */ + __IM uint32_t TS[2]; /*!< Receive or transmission time stamp */ +} CAN_BufType; + +typedef struct { /*!< (@ 0x40007800) CAN structure */ + CAN_BufType RBUF; /*!< (@ 0x00000000) Receive buffer */ + CAN_BufType TBUF; /*!< (@ 0x00000050) Transmit buffer */ + __IOM uint32_t CTRL0; /*!< (@ 0x000000A0) Config state and transmit/receive control register 0 */ + __IOM uint32_t CTRL1; /*!< (@ 0x000000A4) Interrupt enable and flag control register 1 */ + __IOM uint32_t SBITRATE; /*!< (@ 0x000000A8) CAN normal bitrate configuration register */ + __IOM uint32_t FBITRATE; /*!< (@ 0x000000AC) CAN FD data bitrate configuration register */ + __IOM uint32_t ERRINFO; /*!< (@ 0x000000B0) Error type and error counter register */ + __IOM uint32_t ACFCTRL0; /*!< (@ 0x000000B4) Acceptance filter control register 0 */ + __IOM uint32_t ACFCTRL1; /*!< (@ 0x000000B8) Acceptance filter control register 1 */ + __IOM uint32_t ACFCTRL2; /*!< (@ 0x000000BC) Acceptance filter control register 2 */ + __IOM uint32_t ACF; /*!< (@ 0x000000C0) Acceptance code register */ + __IOM uint32_t VERMEM; /*!< (@ 0x000000C4) Version and memory protection register */ + __IOM uint32_t MEMES; /*!< (@ 0x000000C8) Memory error simulation register */ + __IOM uint32_t WAKEUP; /*!< (@ 0x000000CC) Wakeup configuration register */ +} CAN_Type; /*!< Size = 208 (0xd0) */ + + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART) + */ + +typedef struct { /*!< (@ 0x40018000) UART Structure */ + __IOM uint32_t RBR; /*!< (@ 0x00000000) RX/TX Data Register */ + __IOM uint32_t DIV_L; /*!< (@ 0x00000004) Divisor low 8 bits register */ + __IOM uint32_t DIV_H; /*!< (@ 0x00000008) Divisor high 8 bits register */ + __IOM uint32_t LCR0; /*!< (@ 0x0000000C) UART control register 0 */ + __IOM uint32_t LCR1; /*!< (@ 0x00000010) UART control register 1 */ + __IOM uint32_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + __IOM uint32_t EFR; /*!< (@ 0x00000018) hardware flow control register */ + __IOM uint32_t IER; /*!< (@ 0x0000001C) Interrupt Enable register */ + __IOM uint32_t LSR0; /*!< (@ 0x00000020) Line Status Register 0 */ + __IOM uint32_t LSR1; /*!< (@ 0x00000024) Line Status Register 1 */ + __IOM uint32_t SMP_CNT; /*!< (@ 0x00000028) UART sample counter register */ + __IOM uint32_t ADDR; /*!< (@ 0x0000002C) UART match address register */ + __IOM uint32_t DATA; /*!< (@ 0x00000030) UART match data register */ + __IOM uint32_t GUARD; /*!< (@ 0x00000034) UART guard time register */ + __IM uint32_t RESERVED; + __IOM uint32_t SLEEP_EN; /*!< (@ 0x0000003C) UART sleep enable register */ + __IOM uint32_t DMA_EN; /*!< (@ 0x00000040) UART DMA enable register */ + __IOM uint32_t DIV_FRAC; /*!< (@ 0x00000044) Uart Fractional Divider Address */ + __IOM uint32_t MTCHCR; /*!< (@ 0x00000048) Uart match fucntion enable */ + __IOM uint32_t RS485CR; /*!< (@ 0x0000004C) Uart RS485 control register */ + __IM uint32_t RESERVED1; + __IOM uint32_t CNTR; /*!< (@ 0x00000054) Uart Counter time delay in RS485 mode */ + __IOM uint32_t IDLE; /*!< (@ 0x00000058) Uart IDLE register */ + __IOM uint32_t LINCR; /*!< (@ 0x0000005C) LIN Control register */ + __IOM uint32_t BRKLGH; /*!< (@ 0x00000060) LIN Break Length Select Register */ + __IOM uint32_t PMIN0; /*!< (@ 0x00000064) IrDA mode pulse minimum pulse */ + __IOM uint32_t PMIN1; /*!< (@ 0x00000068) IrDA mode pulse minimum pulse */ +} UART_Type; /*!< Size = 108 (0x6c) */ + + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Inter-Integrated Circuit (I2C) + */ + +typedef struct { /*!< (@ 0x4000E000) I2C Structure */ + __IOM uint32_t ADDR0; /*!< (@ 0x00000000) Address Register 0 */ + __IOM uint32_t ADDR1; /*!< (@ 0x00000004) Address register 1 */ + __IOM uint32_t SAMPLE_CNT; /*!< (@ 0x00000008) SAMPLE CNT Register */ + __IOM uint32_t STEP_CNT; /*!< (@ 0x0000000C) STEP CNT Register */ + __IOM uint32_t CTRL0; /*!< (@ 0x00000010) Control Register 0 */ + __IOM uint32_t CTRL1; /*!< (@ 0x00000014) Control Register 1 */ + __IOM uint32_t CTRL2; /*!< (@ 0x00000018) Control Register 2 */ + __IOM uint32_t CTRL3; /*!< (@ 0x0000001C) Control Register 3 */ + __IOM uint32_t STATUS0; /*!< (@ 0x00000020) Status Register 0 */ + __IOM uint32_t STATUS1; /*!< (@ 0x00000024) Status Register 1 */ + __IOM uint32_t DGLCFG; /*!< (@ 0x00000028) Deglitch Configuration Register */ + __IOM uint32_t DATA; /*!< (@ 0x0000002C) Data Register */ + __IOM uint32_t STARTSTOP; /*!< (@ 0x00000030) START_STOP Register */ +} I2C_Type; /*!< Size = 52 (0x34) */ + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface (SPI) + */ + +typedef struct { /*!< (@ 0x4000C000) SPI Structure */ + __IOM uint32_t CFG0; /*!< (@ 0x00000000) SPI Configuration Register 0 */ + __IOM uint32_t CFG1; /*!< (@ 0x00000004) SPI Configuration Register 1 */ + __IOM uint32_t CMD; /*!< (@ 0x00000008) SPI Command Register */ + __IOM uint32_t STATUS; /*!< (@ 0x0000000C) SPI Status Register */ + __IOM uint32_t DATA; /*!< (@ 0x00000010) SPI Data Register */ + __IOM uint32_t CFG2; /*!< (@ 0x00000014) SPI configuration register 2 */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t DMV; /*!< (@ 0x00000020) SPI data match register */ +} SPI_Type; /*!< Size = 36 (0x24) */ + + +/* =========================================================================================================================== */ +/* ================ ANA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog Control Registers (ANA) + */ + +typedef struct { /*!< (@ 0x40008800) ANA Structure */ + __IM uint32_t RESERVED[20]; + __IOM uint32_t ACMPDAC_CFG; /*!< (@ 0x00000050) ACMPDAC Configuration Register */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t AUXADC_CFG0; /*!< (@ 0x00000060) AUXADC Configuration Register0 */ + __IOM uint32_t AUXADC_CFG1; /*!< (@ 0x00000064) AUXADC Configuration Register1 */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t AUXADC_CFG4; /*!< (@ 0x00000070) AUXADC Configuration Register4 */ + __IOM uint32_t AUXADC_CFG5; /*!< (@ 0x00000074) AUXADC Configuration Register5 */ + __IM uint32_t RESERVED3[18]; + __IOM uint32_t SPLL_CFG0; /*!< (@ 0x000000C0) System PLL Config 0 */ + __IOM uint32_t SPLL_CFG1; /*!< (@ 0x000000C4) System PLL Config 1 */ +} ANA_Type; /*!< Size = 200 (0xc8) */ + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +#define ADC_REGULAR_SEQ_NUM (24U) +#define ADC_INJECT_SEQ_NUM (4U) +#define ADC_SAMPLE_REG_NUM (4U) + +/** + * @brief Analog to Digital Converter (ADC) + */ + +typedef struct { /*!< (@ 0x40003000) ADC Structure */ + __IOM uint32_t STR; /*!< (@ 0x00000000) ADC status Register */ + __IOM uint32_t CTRL0; /*!< (@ 0x00000004) ADC Control Register 0 */ + __IOM uint32_t CTRL1; /*!< (@ 0x00000008) ADC Control Register 1 */ + __IOM uint32_t IOFR[ADC_INJECT_SEQ_NUM]; /*!< (@ 0x0000000C) ADC Injection Group Offset Register */ + __IOM uint32_t AMOHR; /*!< (@ 0x0000001C) AMO High threshold and offset register */ + __IOM uint32_t AMOLR; /*!< (@ 0x00000020) AMO Low threshold and offset register */ + __IOM uint32_t SPT[ADC_SAMPLE_REG_NUM]; /*!< (@ 0x00000024) ADC Sample time setting register(n) */ + __IOM uint32_t RSQR[ADC_REGULAR_SEQ_NUM]; /*!< (@ 0x00000034) ADC regular group sequence configure register(n) */ + __IM uint32_t RESERVED1[8]; + __IOM uint32_t ISQR[ADC_INJECT_SEQ_NUM]; /*!< (@ 0x000000B4) ADC injected group sequence configure register(n) */ + __IOM uint32_t SQL; /*!< (@ 0x000000C4) Sequence length of group configure register */ + __IOM uint32_t CALI0; /*!< (@ 0x000000C8) ADC Calibration Register 0 */ + __IOM uint32_t CALI1; /*!< (@ 0x000000CC) ADC Calibration Register 1 */ + __IM uint32_t RESERVED2[6]; + __IM uint32_t RDR[ADC_REGULAR_SEQ_NUM]; /*!< (@ 0x000000E8) ADC Regular Group data Register(n) */ + __IM uint32_t RESERVED3[8]; + __IM uint32_t IDR[ADC_INJECT_SEQ_NUM]; /*!< (@ 0x00000168) ADC Injected Group data Register(n) */ +} ADC_Type; /*!< Size = 376 (0x178) */ + + +/* =========================================================================================================================== */ +/* ================ ACMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog comparator (ACMP) + */ + +typedef struct { /*!< (@ 0x40005000) ACMP Structure */ + __IOM uint32_t CR0; /*!< (@ 0x00000000) ACMP Configuration Register 0 */ + __IOM uint32_t CR1; /*!< (@ 0x00000004) ACMP Configuration Register 1 */ + __IOM uint32_t CR2; /*!< (@ 0x00000008) ACMP configuration register 2 */ + __IOM uint32_t CR3; /*!< (@ 0x0000000C) ACMP configuration register 3 */ + __IOM uint32_t CR4; /*!< (@ 0x00000010) ACMP configuration register 4 */ + __IM uint32_t DR; /*!< (@ 0x00000014) ACMP data output register 0 */ + __IOM uint32_t SR; /*!< (@ 0x00000018) ACMP status register 0 */ + __IOM uint32_t FD; /*!< (@ 0x0000001C) ACMP polling frequency divider register */ + __IOM uint32_t OPA; /*!< (@ 0x00000020) ACMP hall output A set register */ + __IOM uint32_t OPB; /*!< (@ 0x00000024) ACMP hall output B set register */ + __IOM uint32_t OPC; /*!< (@ 0x00000028) ACMP hall output C set register */ + __IM uint32_t RESERVED[7]; + __IOM uint32_t CLK; /*!< (@ 0x00000048) ACMP clock register */ +} ACMP_Type; /*!< Size = 76 (0x4c) */ + + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Width Modulation (PWM) + */ + +#define PWM_CHANNEL_MAX (8UL) /*!< Number of channel of the PWM module */ +typedef struct { /*!< (@ 0x40080000) PWM Structure */ + __IOM uint32_t INIT; /*!< (@ 0x00000000) PWM Initialize, Include Clock and Prescale Setting */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) PWM Counter Value */ + __IOM uint32_t MCVR; /*!< (@ 0x00000008) PWM Counter Max Count Value Register */ + struct { + __IOM uint32_t CHnSCR; /*!< (@ 0x0000000C + 0x8 * n) Channel (n) Status And Control Register */ + __IOM uint32_t CHnV; /*!< (@ 0x00000010 + 0x8 * n) Channel (n) Value */ + } CHANNELS[PWM_CHANNEL_MAX]; + __IOM uint32_t CNTIN; /*!< (@ 0x0000004C) Counter Initial Value */ + __IOM uint32_t STR; /*!< (@ 0x00000050) Status Register */ + __IOM uint32_t FUNCSEL; /*!< (@ 0x00000054) PWM Features(Functions) Mode Selection Register */ + __IOM uint32_t SYNC; /*!< (@ 0x00000058) Synchronization */ + __IOM uint32_t OUTINIT; /*!< (@ 0x0000005C) Initial State For Channels Output */ + __IOM uint32_t OMCR; /*!< (@ 0x00000060) Output Mask Control Register */ + __IOM uint32_t MODESEL; /*!< (@ 0x00000064) PWM Function Mode Selection */ + __IOM uint32_t DTSET0; /*!< (@ 0x00000068) Deadtime Insertion Control 0 */ + __IOM uint32_t DTSET1; /*!< (@ 0x0000006C) Deadtime Insertion Control 1 */ + __IOM uint32_t EXTTRIG; /*!< (@ 0x00000070) PWM External Trigger */ + __IOM uint32_t CHOPOLCR; /*!< (@ 0x00000074) Channel Output Polarity Register */ + __IOM uint32_t FDSR; /*!< (@ 0x00000078) Fault Detect Status Register */ + __IOM uint32_t CAPFILTER; /*!< (@ 0x0000007C) Input Capture Filter Control */ + __IOM uint32_t FFAFER; /*!< (@ 0x00000080) Fault Filter and Fault Enable Register */ + __IOM uint32_t QDI; /*!< (@ 0x00000084) Quadrature Decoder Interface Configuration Register */ + __IOM uint32_t CONF; /*!< (@ 0x00000088) Configuration */ + __IOM uint32_t FLTPOL; /*!< (@ 0x0000008C) PWM Fault Input Polarity */ + __IOM uint32_t SYNCONF; /*!< (@ 0x00000090) Synchronization Configuration */ + __IOM uint32_t INVCR; /*!< (@ 0x00000094) PWM Inverse Control Register */ + __IOM uint32_t CHOSWCR; /*!< (@ 0x00000098) PWM CHannel Software Output Control Register */ + __IOM uint32_t DITHER0; /*!< (@ 0x0000009C) Dither function register 0 */ + __IOM uint32_t DITHER1; /*!< (@ 0x000000A0) Dither function register 1 */ + __IOM uint32_t DITHER2; /*!< (@ 0x000000A4) Dither function register 2 */ + __IOM uint32_t DMACTRL; /*!< (@ 0x000000A8) DMA Control Register */ +} PWM_Type; /*!< Size = 172 (0xac) */ + + +/* =========================================================================================================================== */ +/* ================ PDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable Delay Timer (PDT) + */ +#define PDT_DLY_MAX (8UL) /*!< Number of channel of PDT DLY */ +typedef struct { /*!< (@ 0x40086000) PDT Structure */ + __IOM uint32_t SC; /*!< (@ 0x00000000) PDT Config Register1 */ + __IOM uint32_t MOD; /*!< (@ 0x00000004) PDT Config Register2 */ + struct { + __IOM uint32_t DLY; /*!< (@ 0x00000008 ~ 0x00000024) PDT Config Register3 ~ 10 */ + } DLY[PDT_DLY_MAX]; + __IOM uint32_t IDLY; /*!< (@ 0x00000028) PDT Config Register11 */ + union { + __IOM uint32_t PODLY; /*!< (@ 0x0000002C) PDT Config Register12 */ + struct + { + __IOM uint16_t DLY1; + __IOM uint16_t DLY2; + }ACCESS16BIT; + }PULSE; + __IOM uint32_t DLYn_EN; /*!< (@ 0x00000030) Delay Enable Register */ + __IOM uint32_t POEN; /*!< (@ 0x00000034) Pulse-Out Enable register */ + __IOM uint32_t CNT; /*!< (@ 0x00000038) Counter register */ +} PDT_Type; /*!< Size = 60 (0x3c) */ + + +/* =========================================================================================================================== */ +/* ================ TIMER_CTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer Control (TIMER_CTRL) + */ + +typedef struct { /*!< (@ 0x40011000) TIMER_CTRL Structure */ + __IOM uint32_t CR; /*!< (@ 0x00000000) Timer Control Regitser */ + __IOM uint32_t SR; /*!< (@ 0x00000004) Timer Status Regitser */ + __IOM uint32_t IER; /*!< (@ 0x00000008) TIMER Interrupt Enable Register */ + __IOM uint32_t ENR; /*!< (@ 0x0000000C) TIMER Enable Register */ +} TIMER_CTRL_Type; /*!< Size = 16 (0x10) */ + + +/* =========================================================================================================================== */ +/* ================ TIMER_CHANNEL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer channel (TIMER_CHANNEL) + */ + +typedef struct { /*!< (@ 0x40011010) TIMER_CHANNEL Structure */ + __IOM uint32_t TVAL; /*!< (@ 0x00000000) Timer Load Value Register */ + __IOM uint32_t CVAL; /*!< (@ 0x00000004) Timer Current Count Value Register */ + __IOM uint32_t CTRL; /*!< (@ 0x00000008) Timer channel Control Register */ +} TIMER_CHANNEL_Type; /*!< Size = 12 (0xc) */ + + +/* =========================================================================================================================== */ +/* ================ PCT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Count Timer (PCT) + */ + +typedef struct { /*!< (@ 0x40019000) PCT Structure */ + __IOM uint32_t CSR; /*!< (@ 0x00000000) PCT Control Status Register */ + __IOM uint32_t PSR; /*!< (@ 0x00000004) PCT prescaler Register */ + __IOM uint32_t CMR; /*!< (@ 0x00000008) PCT Compare Register */ + __IOM uint32_t CNR; /*!< (@ 0x0000000C) PCT Counter Register */ +} PCT_Type; /*!< Size = 16 (0x10) */ + + +/* =========================================================================================================================== */ +/* ================ CTU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Connect Unit Module (CTU) + */ +#define TRGMUX_MODULE_NUM (23UL) +typedef struct { /*!< (@ 0x40006000) CTU Structure */ + union { + struct { + __IOM uint32_t TRGMUX_DMA; /*!< (@ 0x00000000) TRGMUX Config Register1 */ + __IOM uint32_t TRGMUX_EXTOUT0; /*!< (@ 0x00000004) TRGMUX Config Register2 */ + __IOM uint32_t TRGMUX_EXTOUT1; /*!< (@ 0x00000008) TRGMUX Config Register3 */ + __IOM uint32_t TRGMUX_ADC0_REG; /*!< (@ 0x0000000C) TRGMUX Config Register4 */ + __IOM uint32_t TRGMUX_ADC0_INJ; /*!< (@ 0x00000010) TRGMUX Config Register5 */ + __IOM uint32_t TRGMUX_ADC1_REG; /*!< (@ 0x00000014) TRGMUX Config Register6 */ + __IOM uint32_t TRGMUX_ADC1_INJ; /*!< (@ 0x00000018) TRGMUX Config Register7 */ + __IOM uint32_t TRGMUX_ACMP; /*!< (@ 0x0000001C) TRGMUX Config Register8 */ + __IOM uint32_t TRGMUX_PWM0; /*!< (@ 0x00000020) TRGMUX Config Register9 */ + __IOM uint32_t TRGMUX_PWM1; /*!< (@ 0x00000024) TRGMUX Config Register10 */ + __IOM uint32_t TRGMUX_PWM2; /*!< (@ 0x00000028) TRGMUX Config Register11 */ + __IOM uint32_t TRGMUX_PWM3; /*!< (@ 0x0000002C) TRGMUX Config Register12 */ + __IOM uint32_t TRGMUX_PWM4; /*!< (@ 0x00000030) TRGMUX Config Register13 */ + __IOM uint32_t TRGMUX_PWM5; /*!< (@ 0x00000034) TRGMUX Config Register14 */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t TRGMUX_TIMER; /*!< (@ 0x00000040) TRGMUX Config Register15 */ + __IOM uint32_t TRGMUX_PCT; /*!< (@ 0x00000044) TRGMUX Config Register16 */ + __IOM uint32_t TRGMUX_UART0; /*!< (@ 0x00000048) TRGMUX Config Register17 */ + __IOM uint32_t TRGMUX_UART1; /*!< (@ 0x0000004C) TRGMUX Config Register18 */ + __IOM uint32_t TRGMUX_PDT0; /*!< (@ 0x00000050) TRGMUX Config Register19 */ + __IOM uint32_t TRGMUX_PDT1; /*!< (@ 0x00000054) TRGMUX Config Register20 */ + __IOM uint32_t TRGMUX_EIO; /*!< (@ 0x00000058) TRGMUX Config Register21 */ + } TRGMUX_MODULE; + __IOM uint32_t TRGMUXn[TRGMUX_MODULE_NUM]; + } TRGMUX; + __IOM uint32_t CTU_CFG; /*!< (@ 0x0000005C) CTU Config Register */ + __IOM uint32_t CTU_SW; /*!< (@ 0x00000060) CTU Config2 Register */ + __IOM uint32_t PWM_MODULATION; /*!< (@ 0x00000064) CTU Config3 Register */ + __IOM uint32_t ADC_SYNC; /*!< (@ 0x00000068) CTU ADC Interleave and Simultaneous Mode Register */ +} CTU_Type; /*!< Size = 108 (0x6c) */ + + +/* =========================================================================================================================== */ +/* ================ DMA0_TOP_RST ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA0 All Channnels Share The Registers (DMA0_TOP_RST) + */ + +typedef struct { /*!< (@ 0x40012000) DMA0_TOP_RST Structure */ + __IOM uint32_t TOP_RST; /*!< (@ 0x00000000) TOP_RST Register */ +} DMA_TopRstType; /*!< Size = 4 (0x4) */ + + +/* =========================================================================================================================== */ +/* ================ DMA0_Channel ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA channel (DMA0_Channel) + */ + +typedef struct { /*!< (@ 0x40012040) DMA0_Channel Structure */ + __IOM uint32_t STATUS; /*!< (@ 0x00000000) Status Register */ + __IOM uint32_t INTEN; /*!< (@ 0x00000004) Interrupt Enable Register */ + __IOM uint32_t RST; /*!< (@ 0x00000008) Reset Register */ + __IOM uint32_t STOP; /*!< (@ 0x0000000C) Stop Register */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000010) DMA Config Register */ + __IOM uint32_t CHAN_LENGTH; /*!< (@ 0x00000014) Channel Length Register */ + __IOM uint32_t SSTART_ADDR; /*!< (@ 0x00000018) Source Start Address Register */ + __IOM uint32_t SEND_ADDR; /*!< (@ 0x0000001C) Source End Address Register */ + __IOM uint32_t DSTART_ADDR; /*!< (@ 0x00000020) Destination Start Address Register */ + __IOM uint32_t CHAN_ENABLE; /*!< (@ 0x00000024) Channel Enable Register */ + __IOM uint32_t DATA_TRANS_NUM; /*!< (@ 0x00000028) Data Transfer Number Register */ + __IOM uint32_t FIFO_LEFT_NUM; /*!< (@ 0x0000002C) Internal FIFO Data Left Number Register */ + __IOM uint32_t DEND_ADDR; /*!< (@ 0x00000030) Destination End Address Register */ + __IOM uint32_t ADDR_OFFSET; /*!< (@ 0x00000034) Address Offset Register */ + __IOM uint32_t DMAMUX_CFG; /*!< (@ 0x00000038) DMAMUX Configuration Register */ +} DMA_ChannelType; /*!< Size = 60 (0x3c) */ + + +/* =========================================================================================================================== */ +/* ================ WDG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog (WDG) + */ + +typedef struct { /*!< (@ 0x4000B000) WDG Structure */ + __IOM uint32_t CS0; /*!< (@ 0x00000000) Watchdog Control and Status Register 0 */ + __IOM uint32_t CS1; /*!< (@ 0x00000004) Watchdog Control and Status Register 1 */ + __IOM uint32_t CNT; /*!< (@ 0x00000008) Watchdog Counter Value */ + __IOM uint32_t TOVAL; /*!< (@ 0x0000000C) Watchdog Timeout Value Register */ + __IOM uint32_t WIN; /*!< (@ 0x00000010) Watchdog Window Register */ +} WDG_Type; /*!< Size = 20 (0x14) */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real-time counter (RTC) + */ + +typedef struct { /*!< (@ 0x40009800) RTC Structure */ + __IOM uint32_t CTRL; /*!< (@ 0x00000000) RTC Control Register */ + __IOM uint32_t TAR; /*!< (@ 0x00000004) RTC Time Alarm Register */ + __IOM uint32_t TC; /*!< (@ 0x00000008) RTC Time Counter */ + __IOM uint32_t PSR; /*!< (@ 0x0000000C) RTC Prescaler Register */ + __IM uint32_t PSC; /*!< (@ 0x00000010) RTC Prescaler Counter Register */ + __IOM uint32_t SR; /*!< (@ 0x00000014) RTC Status Register */ + __IOM uint32_t LR; /*!< (@ 0x00000018) RTC Lock Register */ +} RTC_Type; /*!< Size = 28 (0x1c) */ + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CRC Cyclic redundancy check (CRC) + */ + +typedef struct { /*!< (@ 0x40084000) CRC Structure */ + union { + __IOM uint32_t DATA32; /*!< (@ 0x00000000) DATA Register */ + struct { + __IOM uint16_t L; /*!< (@ 0x00000000) DATA L Register */ + __IOM uint16_t H; /*!< (@ 0x00000002) DATA H Register */ + } DATA16; + struct { + __IOM uint8_t LL; /*!< (@ 0x00000000) DATA LL Register */ + __IOM uint8_t LU; /*!< (@ 0x00000001) DATA LU Register */ + __IOM uint8_t HL; /*!< (@ 0x00000002) DATA HL Register */ + __IOM uint8_t HU; /*!< (@ 0x00000003) DATA HU Register */ + } DATA8; + } DATAn; + __IOM uint32_t POLY; /*!< (@ 0x00000004) Poly Register */ + __IOM uint32_t CTRL; /*!< (@ 0x00000008) Control Register */ +} CRC_Type; /*!< Size = 12 (0xc) */ + + +/* =========================================================================================================================== */ +/* ================ EIM_CTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GLB_EN (EIM_CTRL) + */ + +typedef struct { /*!< (@ 0x40088000) EIM_CTRL Structure */ + __IOM uint32_t EIM_GLB_ENABLE; /*!< (@ 0x00000000) EIM global enable */ + __IOM uint32_t EIM_CHEN; /*!< (@ 0x00000004) EIM channel enable control */ +} EIM_CTRL_Type; /*!< Size = 8 (0x8) */ + + +/* =========================================================================================================================== */ +/* ================ EIM_CHANNEL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SRAM Error Injection Bit Control (EIM_CHANNEL) + */ + +typedef struct { /*!< (@ 0x40088010) EIM_CHANNEL Structure */ + __IOM uint32_t EIM_INJ_DATA; /*!< (@ 0x00000000) SRAML data injection control */ + __IOM uint32_t EIM_INJ_ADDR; /*!< (@ 0x00000004) SRAML address injection control */ + __IOM uint32_t EIM_INJ_ECC; /*!< (@ 0x00000008) SRAML ECC code injection control */ +} EIM_CHANNEL_Type; /*!< Size = 12 (0xc) */ + + +/* =========================================================================================================================== */ +/* ================ ECC_SRAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SRAM Error ctrl (ECC_SRAM) + */ + +typedef struct { /*!< (@ 0x40088100) ECC_SRAM Structure */ + __IM uint32_t CH0_STATUS0; /*!< (@ 0x00000000) SRAM ECC CH0 status and addr0 register */ + __IM uint32_t CH0_STATUS1; /*!< (@ 0x00000004) ECC CH0 2bit error addr */ + __IM uint32_t CH1_STATUS0; /*!< (@ 0x00000008) SRAM ECC CH1 status and addr0 register */ + __IM uint32_t CH1_STATUS1; /*!< (@ 0x0000000C) ECC CH1 2bit error addr */ + __IOM uint32_t ECC_ERR_CTRL; /*!< (@ 0x00000010) ECC Error status control registers */ +} ECC_SRAM_Type; /*!< Size = 20 (0x14) */ + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Embedded Flash (FLASH) + */ + +typedef struct { /*!< (@ 0x40002000) FLASH Structure */ + __IOM uint32_t STAT; /*!< (@ 0x00000000) Flash status register */ + __IM uint32_t SEC; /*!< (@ 0x00000004) MCU secure register */ + __IOM uint32_t CSESTAT; /*!< (@ 0x00000008) CSE status register */ + __IOM uint32_t KEYUNLK; /*!< (@ 0x0000000C) Flash unlock register */ + __IOM uint32_t CNFG; /*!< (@ 0x00000010) Flash configure register */ + __IOM uint32_t CMD; /*!< (@ 0x00000014) Flash command ID register */ + __IOM uint32_t ADDR; /*!< (@ 0x00000018) Flash address register */ + __IOM uint32_t DATA0; /*!< (@ 0x0000001C) Flash data register 0 */ + __IOM uint32_t DATA1; /*!< (@ 0x00000020) Flash data register 1 */ + __IOM uint32_t LEN; /*!< (@ 0x00000024) Flash length register */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t CST; /*!< (@ 0x00000030) Flash command start register */ + __IOM uint32_t PPROT; /*!< (@ 0x00000034) P-Flash write protection register */ + __IOM uint32_t DPROT; /*!< (@ 0x00000038) D-Flash write protection register */ + __IM uint32_t RESERVED1; + __IOM uint32_t DFADR; /*!< (@ 0x00000040) Flash ECC 2-bit error address register */ + __IM uint32_t RESERVED2; + __IM uint32_t PART; /*!< (@ 0x00000048) CSE partition information register */ +} FLASH_Type; /*!< Size = 76 (0x4c) */ + + +/* =========================================================================================================================== */ +/* ================ CSE ================ */ +/* =========================================================================================================================== */ + + +#define CSE_PRAM_RAMn_COUNT (32UL) /*!< Size of PRMA Registers Arrays */ +#define CSE_PRAM_INSTANCE_COUNT (1UL) /*!< Number of instances of the CSE_PRAM module */ + +/** + * @brief CSE + */ +typedef struct { + union { /*!< offset: 0x0, array step: 0x4 */ + __IO uint32_t DATA_32; /*!< CSE PRAM 0 Register..CSE PRAM 31 Register, array offset: 0x0, array step: 0x4 */ + struct { /*!< offset: 0x0, array step: 0x4 */ + __IO uint8_t DATA_8LL; /*!< CSE PRAM0LL register...CSE PRAM31LL register., array offset: 0x0, array step: 0x4 */ + __IO uint8_t DATA_8LU; /*!< CSE PRAM0LU register...CSE PRAM31LU register., array offset: 0x1, array step: 0x4 */ + __IO uint8_t DATA_8HL; /*!< CSE PRAM0HL register...CSE PRAM31HL register., array offset: 0x2, array step: 0x4 */ + __IO uint8_t DATA_8HU; /*!< CSE PRAM0HU register...CSE PRAM31HU register., array offset: 0x3, array step: 0x4 */ + } ACCESS8BIT; + } RAMn[CSE_PRAM_RAMn_COUNT]; +} CSE_PRAM_Type, *CSE_PRAM_MemMapPtr; + + +/* =========================================================================================================================== */ +/* ================ EIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief The EIO Memory Map/Register Definition can be found here. (EIO) + */ + +typedef struct { /*!< (@ 0x4000A000) EIO Structure */ + __IOM uint32_t CTRL; /*!< (@ 0x00000000) EIO Control Register */ + __IM uint32_t PIN; /*!< (@ 0x00000004) Pin State Register */ + __IOM uint32_t SHIFTSTAT; /*!< (@ 0x00000008) Shifter Status Register */ + __IOM uint32_t SHIFTERR; /*!< (@ 0x0000000C) Shifter Error Register */ + __IOM uint32_t TIMSTAT; /*!< (@ 0x00000010) Timer Status Register */ + __IOM uint32_t SHIFTSIEN; /*!< (@ 0x00000014) Shifter Status Interrupt Enable */ + __IOM uint32_t SHIFTEIEN; /*!< (@ 0x00000018) Shifter Error Interrupt Enable */ + __IOM uint32_t TIMIEN; /*!< (@ 0x0000001C) Timer Interrupt Enable Register */ + __IOM uint32_t SHIFTSDEN; /*!< (@ 0x00000020) Shifter Status DMA Enable */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t SHIFTCTL[4]; /*!< (@ 0x00000030) Shifter Control N Register */ + __IOM uint32_t SHIFTCFG[4]; /*!< (@ 0x00000040) Shifter Configuration N Register */ + __IOM uint32_t SHIFTBUF[4]; /*!< (@ 0x00000050) Shifter Buffer N Register */ + __IOM uint32_t SHIFTBUFBIS[4]; /*!< (@ 0x00000060) Shifter Buffer N Bit Swapped Register */ + __IOM uint32_t SHIFTBUFBYS[4]; /*!< (@ 0x00000070) Shifter Buffer N Byte Swapped Register */ + __IOM uint32_t SHIFTBUFBBS[4]; /*!< (@ 0x00000080) Shifter Buffer N Bit Byte Swapped Register */ + __IOM uint32_t TIMCTL[4]; /*!< (@ 0x00000090) Timer Control N Register */ + __IOM uint32_t TIMCFG[4]; /*!< (@ 0x000000A0) Timer Configuration N Register */ + __IOM uint32_t TIMCMP[4]; /*!< (@ 0x000000B0) Timer Compare N Register */ +} EIO_Type; /*!< Size = 192 (0xc0) */ + + +/* =========================================================================================================================== */ +/* ================ EWDG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief External Watchdog Timer (EWDG) + */ + +typedef struct { /*!< (@ 0x4000B400) EWDG Structure */ + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control Register */ + __IOM uint32_t SERV; /*!< (@ 0x00000004) Service Register */ + __IOM uint32_t CMPL; /*!< (@ 0x00000008) Compare Low Register */ + __IOM uint32_t CMPH; /*!< (@ 0x0000000C) Compare High Register */ + __IOM uint32_t CLKPRESCALER; /*!< (@ 0x00000010) Clock Prescaler Register */ +} EWDG_Type; /*!< Size = 20 (0x14) */ + + +/* =========================================================================================================================== */ +/* ================ AC784X_SysTick ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief The AC784X_SysTick Memory Map/Register Definition can be found here. (AC784X_SysTick) + */ + +typedef struct { /*!< (@ 0xE000E010) AC784X_SysTick Structure */ + __IOM uint32_t CSR; /*!< (@ 0x00000000) SysTick Control and Status Register, offset: 0x0 */ + __IOM uint32_t RVR; /*!< (@ 0x00000004) SysTick Reload Value Register, offset: 0x4 */ + __IOM uint32_t CVR; /*!< (@ 0x00000008) SysTick Current Value Register, offset: 0x8 */ + __IOM uint32_t CALIB; /*!< (@ 0x0000000C) SysTick Calibration Value Register, offset: 0xC */ +} AC784X_SysTickType; /*!< Size = 16 (0x10) */ + + +/* =========================================================================================================================== */ +/* ================ SMU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Safety Management Uint (SMU) + */ + +typedef struct { /*!< (@ 0x40089000) SMU Structure */ + __IOM uint32_t SFES; /*!< (@ 0x00000000) Single Point Fault Error Status Register */ + __IOM uint32_t SFESS; /*!< (@ 0x00000004) Single Point Fault Error Status Shadow Register */ + __IOM uint32_t LFES; /*!< (@ 0x00000008) Latent Fault Error Status Register */ + __IOM uint32_t LFESS; /*!< (@ 0x0000000C) Latent Fault Error Status Shadow Register */ + __IOM uint32_t LKSEQ0; /*!< (@ 0x00000010) Lock Sequence for Single Point Fault Path */ + __IOM uint32_t LKSEQ1; /*!< (@ 0x00000014) Lock Sequence for Latent Fault Path */ + __IOM uint32_t SWSFE; /*!< (@ 0x00000018) Software Single Point Fault Enable Register */ + __IOM uint32_t SWSFES; /*!< (@ 0x0000001C) Software Single Point Fault Enable Shadow Register */ + __IOM uint32_t SWLFE; /*!< (@ 0x00000020) Software Latent Fault Enable Register */ + __IOM uint32_t SWLFES; /*!< (@ 0x00000024) Software Latent Fault Enable Shadow Register */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t SFRSTEN; /*!< (@ 0x00000030) Single Point Fault Reset Enable Register */ + __IOM uint32_t LFRSTEN; /*!< (@ 0x00000034) Latent Fault Reset Request Enable Register */ + __IOM uint32_t SRSTCNTVAL; /*!< (@ 0x00000038) System Reset Request Counter Threshold Register */ + __IOM uint32_t SRSTCNT; /*!< (@ 0x0000003C) System Reset Request Counter Register */ + __IOM uint32_t SRSTCNTS; /*!< (@ 0x00000040) System Reset Request Counter Shadow Register */ + __IOM uint32_t PATHCHK0; /*!< (@ 0x00000044) Path Check for Single Point Fault Path Register */ + __IOM uint32_t PATHCHK1; /*!< (@ 0x00000048) Path Check for Latent Fault Error Path Register */ +} SMU_Type; /*!< Size = 76 (0x4c) */ + + +/* =========================================================================================================================== */ +/* ================ CMU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock Monitor Uint (CMU) + */ + +typedef struct { /*!< (@ 0x40000800) CMU Structure */ + __IOM uint32_t CR; /*!< (@ 0x00000000) Configure Register */ + __IOM uint32_t RCCR; /*!< (@ 0x00000004) Reference Count Configure Register */ + __IOM uint32_t HTCR; /*!< (@ 0x00000008) High Threshold Configure Register */ + __IOM uint32_t LTCR; /*!< (@ 0x0000000C) Low Threshold Configure Register */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t SR; /*!< (@ 0x00000018) Status Register */ + __IOM uint32_t MON_A7; /*!< (@ 0x0000001C) Monitor Register */ + __IOM uint32_t MON_A8; /*!< (@ 0x00000020) Monitor Register */ +} CMU_Type; /*!< Size = 36 (0x24) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define CKGEN_BASE 0x40000000UL +#define PBR_BASE 0x4008A000UL +#define SPM_BASE 0x40008000UL +#define GPIOA_BASE 0x40085000UL +#define GPIOB_BASE 0x40085040UL +#define GPIOC_BASE 0x40085080UL +#define GPIOD_BASE 0x400850C0UL +#define GPIOE_BASE 0x40085100UL +#define PORTA_BASE 0x40085200UL +#define PORTB_BASE 0x40085300UL +#define PORTC_BASE 0x40085400UL +#define PORTD_BASE 0x40085500UL +#define PORTE_BASE 0x40085600UL +#define CAN0_BASE 0x40007000UL +#define CAN1_BASE 0x40007200UL +#define CAN2_BASE 0x40007400UL +#define CAN3_BASE 0x40007600UL +#define UART0_BASE 0x40018000UL +#define UART1_BASE 0x40018200UL +#define UART2_BASE 0x40018400UL +#define UART3_BASE 0x40018600UL +#define I2C0_BASE 0x4000E000UL +#define SPI0_BASE 0x4000C000UL +#define SPI1_BASE 0x4000C800UL +#define SPI2_BASE 0x4000D000UL +#define ANA_BASE 0x40008800UL +#define ADC0_BASE 0x40003000UL +#define ADC1_BASE 0x40004000UL +#define ACMP0_BASE 0x40005000UL +#define PWM0_BASE 0x40080000UL +#define PWM1_BASE 0x40080800UL +#define PWM2_BASE 0x40081000UL +#define PWM3_BASE 0x40081800UL +#define PWM4_BASE 0x40082000UL +#define PWM5_BASE 0x40082800UL +#define PDT0_BASE 0x40086000UL +#define PDT1_BASE 0x40086800UL +#define TIMER_CTRL_BASE 0x40011000UL +#define TIMER_CHANNEL0_BASE 0x40011010UL +#define TIMER_CHANNEL1_BASE 0x40011020UL +#define TIMER_CHANNEL2_BASE 0x40011030UL +#define TIMER_CHANNEL3_BASE 0x40011040UL +#define PCT_BASE 0x40019000UL +#define CTU_BASE 0x40006000UL +#define DMA0_TOP_RST_BASE 0x40012000UL +#define DMA0_CHANNEL0_BASE 0x40012040UL +#define DMA0_CHANNEL1_BASE 0x40012080UL +#define DMA0_CHANNEL2_BASE 0x400120C0UL +#define DMA0_CHANNEL3_BASE 0x40012100UL +#define DMA0_CHANNEL4_BASE 0x40012140UL +#define DMA0_CHANNEL5_BASE 0x40012180UL +#define DMA0_CHANNEL6_BASE 0x400121C0UL +#define DMA0_CHANNEL7_BASE 0x40012200UL +#define DMA0_CHANNEL8_BASE 0x40012240UL +#define DMA0_CHANNEL9_BASE 0x40012280UL +#define DMA0_CHANNEL10_BASE 0x400122C0UL +#define DMA0_CHANNEL11_BASE 0x40012300UL +#define DMA0_CHANNEL12_BASE 0x40012340UL +#define DMA0_CHANNEL13_BASE 0x40012380UL +#define DMA0_CHANNEL14_BASE 0x400123C0UL +#define DMA0_CHANNEL15_BASE 0x40012400UL +#define WDG_BASE 0x4000B000UL +#define RTC_BASE 0x40009800UL +#define CRC_BASE 0x40084000UL +#define EIM_CTRL_BASE 0x40088000UL +#define EIM_CHANNEL0_BASE 0x40088010UL +#define EIM_CHANNEL1_BASE 0x40088080UL +#define ECC_SRAM_BASE 0x40088100UL +#define FLASH_BASE 0x40002000UL +#define EIO_BASE 0x4000A000UL +#define EWDG_BASE 0x4000B400UL +#define AC784X_SYSTICK_BASE 0xE000E010UL +#define MCM_BASE 0xE008000CUL +#define MPU_BASE 0x40087000UL +#define SMU_BASE 0x40089000UL +#define CMU_VHSI_BASE 0x40000800UL +#define CMU_HSE_BASE 0x40000A00UL +#define CMU_PLL_BASE 0x40000C00UL +#define CSE_PRAM_BASE 0x14001000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define CKGEN ((CKGEN_Type*) CKGEN_BASE) +#define PBR ((PBR_Type*) PBR_BASE) +#define SPM ((SPM_Type*) SPM_BASE) +#define GPIOA ((GPIO_Type*) GPIOA_BASE) +#define GPIOB ((GPIO_Type*) GPIOB_BASE) +#define GPIOC ((GPIO_Type*) GPIOC_BASE) +#define GPIOD ((GPIO_Type*) GPIOD_BASE) +#define GPIOE ((GPIO_Type*) GPIOE_BASE) +#define PORTA ((PORT_Type*) PORTA_BASE) +#define PORTB ((PORT_Type*) PORTB_BASE) +#define PORTC ((PORT_Type*) PORTC_BASE) +#define PORTD ((PORT_Type*) PORTD_BASE) +#define PORTE ((PORT_Type*) PORTE_BASE) +#define CAN0 ((CAN_Type*) CAN0_BASE) +#define CAN1 ((CAN_Type*) CAN1_BASE) +#define CAN2 ((CAN_Type*) CAN2_BASE) +#define CAN3 ((CAN_Type*) CAN3_BASE) +#define UART0 ((UART_Type*) UART0_BASE) +#define UART1 ((UART_Type*) UART1_BASE) +#define UART2 ((UART_Type*) UART2_BASE) +#define UART3 ((UART_Type*) UART3_BASE) +#define I2C0 ((I2C_Type*) I2C0_BASE) +#define SPI0 ((SPI_Type*) SPI0_BASE) +#define SPI1 ((SPI_Type*) SPI1_BASE) +#define SPI2 ((SPI_Type*) SPI2_BASE) +#define ANA ((ANA_Type*) ANA_BASE) +#define ADC0 ((ADC_Type*) ADC0_BASE) +#define ADC1 ((ADC_Type*) ADC1_BASE) +#define ACMP0 ((ACMP_Type*) ACMP0_BASE) +#define PWM0 ((PWM_Type*) PWM0_BASE) +#define PWM1 ((PWM_Type*) PWM1_BASE) +#define PWM2 ((PWM_Type*) PWM2_BASE) +#define PWM3 ((PWM_Type*) PWM3_BASE) +#define PWM4 ((PWM_Type*) PWM4_BASE) +#define PWM5 ((PWM_Type*) PWM5_BASE) +#define PDT0 ((PDT_Type*) PDT0_BASE) +#define PDT1 ((PDT_Type*) PDT1_BASE) +#define TIMER_CTRL ((TIMER_CTRL_Type*) TIMER_CTRL_BASE) +#define TIMER_CHANNEL0 ((TIMER_CHANNEL_Type*) TIMER_CHANNEL0_BASE) +#define TIMER_CHANNEL1 ((TIMER_CHANNEL_Type*) TIMER_CHANNEL1_BASE) +#define TIMER_CHANNEL2 ((TIMER_CHANNEL_Type*) TIMER_CHANNEL2_BASE) +#define TIMER_CHANNEL3 ((TIMER_CHANNEL_Type*) TIMER_CHANNEL3_BASE) +#define PCT ((PCT_Type*) PCT_BASE) +#define CTU ((CTU_Type*) CTU_BASE) +#define DMA0_TOP_RST ((DMA_TopRstType*) DMA0_TOP_RST_BASE) +#define DMA0_CHANNEL0 ((DMA_ChannelType*) DMA0_CHANNEL0_BASE) +#define DMA0_CHANNEL1 ((DMA_ChannelType*) DMA0_CHANNEL1_BASE) +#define DMA0_CHANNEL2 ((DMA_ChannelType*) DMA0_CHANNEL2_BASE) +#define DMA0_CHANNEL3 ((DMA_ChannelType*) DMA0_CHANNEL3_BASE) +#define DMA0_CHANNEL4 ((DMA_ChannelType*) DMA0_CHANNEL4_BASE) +#define DMA0_CHANNEL5 ((DMA_ChannelType*) DMA0_CHANNEL5_BASE) +#define DMA0_CHANNEL6 ((DMA_ChannelType*) DMA0_CHANNEL6_BASE) +#define DMA0_CHANNEL7 ((DMA_ChannelType*) DMA0_CHANNEL7_BASE) +#define DMA0_CHANNEL8 ((DMA_ChannelType*) DMA0_CHANNEL8_BASE) +#define DMA0_CHANNEL9 ((DMA_ChannelType*) DMA0_CHANNEL9_BASE) +#define DMA0_CHANNEL10 ((DMA_ChannelType*) DMA0_CHANNEL10_BASE) +#define DMA0_CHANNEL11 ((DMA_ChannelType*) DMA0_CHANNEL11_BASE) +#define DMA0_CHANNEL12 ((DMA_ChannelType*) DMA0_CHANNEL12_BASE) +#define DMA0_CHANNEL13 ((DMA_ChannelType*) DMA0_CHANNEL13_BASE) +#define DMA0_CHANNEL14 ((DMA_ChannelType*) DMA0_CHANNEL14_BASE) +#define DMA0_CHANNEL15 ((DMA_ChannelType*) DMA0_CHANNEL15_BASE) +#define WDG ((WDG_Type*) WDG_BASE) +#define RTC ((RTC_Type*) RTC_BASE) +#define CRC ((CRC_Type*) CRC_BASE) +#define EIM_CTRL ((EIM_CTRL_Type*) EIM_CTRL_BASE) +#define EIM_CHANNEL0 ((EIM_CHANNEL_Type*) EIM_CHANNEL0_BASE) +#define EIM_CHANNEL1 ((EIM_CHANNEL_Type*) EIM_CHANNEL1_BASE) +#define ECC_SRAM ((ECC_SRAM_Type*) ECC_SRAM_BASE) +#define FLASH ((FLASH_Type*) FLASH_BASE) +#define EIO ((EIO_Type*) EIO_BASE) +#define EWDG ((EWDG_Type*) EWDG_BASE) +#define AC784X_SYSTICK ((AC784X_SysTickType*) AC784X_SYSTICK_BASE) +#define MCM ((MCM_Type*) MCM_BASE) +#define MPU ((MPU_Type*) MPU_BASE) +#define SMU ((SMU_Type*) SMU_BASE) +#define CMU_VHSI ((CMU_Type*) CMU_VHSI_BASE) +#define CMU_HSE ((CMU_Type*) CMU_HSE_BASE) +#define CMU_PLL ((CMU_Type*) CMU_PLL_BASE) +#define CSE_PRAM ((CSE_PRAM_Type *) CSE_PRAM_BASE) + + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ MCM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MCPCR ========================================================= */ +#define MCM_MCPCR_SAPU_Pos (24UL) /*!< SAPU (Bit 24) */ +#define MCM_MCPCR_SAPU_Msk (0x3000000UL) /*!< SAPU (Bitfield-Mask: 0x03) */ +#define MCM_MCPCR_SWPU_Pos (26UL) /*!< SWPU (Bit 26) */ +#define MCM_MCPCR_SWPU_Msk (0x4000000UL) /*!< SWPU (Bitfield-Mask: 0x01) */ +#define MCM_MCPCR_SAPL_Pos (28UL) /*!< SAPL (Bit 28) */ +#define MCM_MCPCR_SAPL_Msk (0x30000000UL) /*!< SAPL (Bitfield-Mask: 0x03) */ +#define MCM_MCPCR_SWPL_Pos (30UL) /*!< SWPL (Bit 30) */ +#define MCM_MCPCR_SWPL_Msk (0x40000000UL) /*!< SWPL (Bitfield-Mask: 0x01) */ +/* ========================================================= MISCR ========================================================= */ +#define MCM_MISCR_FIOC_Pos (8UL) /*!< FIOC (Bit 8) */ +#define MCM_MISCR_FIOC_Msk (0x100UL) /*!< FIOC (Bitfield-Mask: 0x01) */ +#define MCM_MISCR_FDZC_Pos (9UL) /*!< FDZC (Bit 9) */ +#define MCM_MISCR_FDZC_Msk (0x200UL) /*!< FDZC (Bitfield-Mask: 0x01) */ +#define MCM_MISCR_FOFC_Pos (10UL) /*!< FOFC (Bit 10) */ +#define MCM_MISCR_FOFC_Msk (0x400UL) /*!< FOFC (Bitfield-Mask: 0x01) */ +#define MCM_MISCR_FUFC_Pos (11UL) /*!< FUFC (Bit 11) */ +#define MCM_MISCR_FUFC_Msk (0x800UL) /*!< FUFC (Bitfield-Mask: 0x01) */ +#define MCM_MISCR_FIXC_Pos (12UL) /*!< FIXC (Bit 12) */ +#define MCM_MISCR_FIXC_Msk (0x1000UL) /*!< FIXC (Bitfield-Mask: 0x01) */ +#define MCM_MISCR_FIDC_Pos (15UL) /*!< FIDC (Bit 15) */ +#define MCM_MISCR_FIDC_Msk (0x8000UL) /*!< FIDC (Bitfield-Mask: 0x01) */ +#define MCM_MISCR_FIOCEN_Pos (24UL) /*!< FIOCEN (Bit 24) */ +#define MCM_MISCR_FIOCEN_Msk (0x1000000UL) /*!< FIOCEN (Bitfield-Mask: 0x01) */ +#define MCM_MISCR_FDZCEN_Pos (25UL) /*!< FDZCEN (Bit 25) */ +#define MCM_MISCR_FDZCEN_Msk (0x2000000UL) /*!< FDZCEN (Bitfield-Mask: 0x01) */ +#define MCM_MISCR_FOFCEN_Pos (26UL) /*!< FOFCEN (Bit 26) */ +#define MCM_MISCR_FOFCEN_Msk (0x4000000UL) /*!< FOFCEN (Bitfield-Mask: 0x01) */ +#define MCM_MISCR_FUFCEN_Pos (27UL) /*!< FUFCEN (Bit 27) */ +#define MCM_MISCR_FUFCEN_Msk (0x8000000UL) /*!< FUFCEN (Bitfield-Mask: 0x01) */ +#define MCM_MISCR_FIXCEN_Pos (28UL) /*!< FIXCEN (Bit 28) */ +#define MCM_MISCR_FIXCEN_Msk (0x10000000UL) /*!< FIXCEN (Bitfield-Mask: 0x01) */ +#define MCM_MISCR_FIDCEN_Pos (31UL) /*!< FIDCEN (Bit 31) */ +#define MCM_MISCR_FIDCEN_Msk (0x80000000UL) /*!< FIDCEN (Bitfield-Mask: 0x01) */ +/* ======================================================== MLMDR0 ========================================================= */ +#define MCM_MLMDR0_LREEN_Pos (1UL) /*!< LREEN (Bit 1) */ +#define MCM_MLMDR0_LREEN_Msk (0x2UL) /*!< LREEN (Bitfield-Mask: 0x01) */ +#define MCM_MLMDR0_UREEN_Pos (3UL) /*!< UREEN (Bit 3) */ +#define MCM_MLMDR0_UREEN_Msk (0x8UL) /*!< UREEN (Bitfield-Mask: 0x01) */ +#define MCM_MLMDR0_LOCK_Pos (16UL) /*!< LOCK (Bit 16) */ +#define MCM_MLMDR0_LOCK_Msk (0x10000UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define MCM_MLMDR0_LMSZ_Pos (24UL) /*!< LMSZ (Bit 24) */ +#define MCM_MLMDR0_LMSZ_Msk (0x7000000UL) /*!< LMSZ (Bitfield-Mask: 0x07) */ +/* ========================================================= MBIST ========================================================= */ +/* ======================================================== MLMDR1 ========================================================= */ +#define MCM_MLMDR1_CPDE_Pos (5UL) /*!< CPDE (Bit 5) */ +#define MCM_MLMDR1_CPDE_Msk (0x20UL) /*!< CPDE (Bitfield-Mask: 0x01) */ +#define MCM_MLMDR1_CPFE_Pos (7UL) /*!< CPFE (Bit 7) */ +#define MCM_MLMDR1_CPFE_Msk (0x80UL) /*!< CPFE (Bitfield-Mask: 0x01) */ +#define MCM_MLMDR1_LOCK_Pos (16UL) /*!< LOCK (Bit 16) */ +#define MCM_MLMDR1_LOCK_Msk (0x10000UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +#define MCM_MLMDR1_CASZ_Pos (24UL) /*!< CASZ (Bit 24) */ +#define MCM_MLMDR1_CASZ_Msk (0xf000000UL) /*!< CASZ (Bitfield-Mask: 0x0f) */ +/* ======================================================== LMPECR ========================================================= */ +#define MCM_LMPECR_CPEIEN_Pos (20UL) /*!< CPEIEN (Bit 20) */ +#define MCM_LMPECR_CPEIEN_Msk (0x100000UL) /*!< CPEIEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LMPEIR ========================================================= */ +/* ========================================================= LMFAR ========================================================= */ +/* ========================================================= MCCR ========================================================== */ +#define MCM_MCCR_CADIS_Pos (0UL) /*!< CADIS (Bit 0) */ +#define MCM_MCCR_CADIS_Msk (0x1UL) /*!< CADIS (Bitfield-Mask: 0x01) */ +#define MCM_MCCR_CACL_Pos (1UL) /*!< CACL (Bit 1) */ +#define MCM_MCCR_CACL_Msk (0x2UL) /*!< CACL (Bitfield-Mask: 0x01) */ +/* ========================================================= MNCR ========================================================== */ +#define MCM_MNCR_NMI_EN_Pos (0UL) /*!< NMI_EN (Bit 0) */ +#define MCM_MNCR_NMI_EN_Msk (0x1UL) /*!< NMI_EN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ MPU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CESR ========================================================== */ +#define MPU_CESR_VLD_Pos (0UL) /*!< VLD (Bit 0) */ +#define MPU_CESR_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ +#define MPU_CESR_SPERR0_Pos (29UL) /*!< SPERR0 (Bit 29) */ +#define MPU_CESR_SPERR0_Msk (0x20000000UL) /*!< SPERR0 (Bitfield-Mask: 0x01) */ +#define MPU_CESR_SPERR1_Pos (30UL) /*!< SPERR1 (Bit 30) */ +#define MPU_CESR_SPERR1_Msk (0x40000000UL) /*!< SPERR1 (Bitfield-Mask: 0x01) */ +#define MPU_CESR_SPERR2_Pos (31UL) /*!< SPERR2 (Bit 31) */ +#define MPU_CESR_SPERR2_Msk (0x80000000UL) /*!< SPERR2 (Bitfield-Mask: 0x01) */ +/* ========================================================= EAR0 ========================================================== */ +#define MPU_EAR0_EADDR_Pos (0UL) /*!< EADDR (Bit 0) */ +#define MPU_EAR0_EADDR_Msk (0xffffffffUL) /*!< EADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EAR1 ========================================================== */ +#define MPU_EAR1_EADDR_Pos (0UL) /*!< EADDR (Bit 0) */ +#define MPU_EAR1_EADDR_Msk (0xffffffffUL) /*!< EADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EAR2 ========================================================== */ +#define MPU_EAR2_EADDR_Pos (0UL) /*!< EADDR (Bit 0) */ +#define MPU_EAR2_EADDR_Msk (0xffffffffUL) /*!< EADDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EDR0 ========================================================== */ +#define MPU_EDR0_ERW_Pos (0UL) /*!< ERW (Bit 0) */ +#define MPU_EDR0_ERW_Msk (0x1UL) /*!< ERW (Bitfield-Mask: 0x01) */ +#define MPU_EDR0_EATTR_Pos (1UL) /*!< EATTR (Bit 1) */ +#define MPU_EDR0_EATTR_Msk (0x1eUL) /*!< EATTR (Bitfield-Mask: 0x0f) */ +#define MPU_EDR0_EMN_Pos (5UL) /*!< EMN (Bit 5) */ +#define MPU_EDR0_EMN_Msk (0xe0UL) /*!< EMN (Bitfield-Mask: 0x07) */ +#define MPU_EDR0_EPID_Pos (8UL) /*!< EPID (Bit 8) */ +#define MPU_EDR0_EPID_Msk (0xff00UL) /*!< EPID (Bitfield-Mask: 0xff) */ +#define MPU_EDR0_EACD_Pos (16UL) /*!< EACD (Bit 16) */ +#define MPU_EDR0_EACD_Msk (0xff0000UL) /*!< EACD (Bitfield-Mask: 0xff) */ +#define MPU_EDR0_EFLG_Pos (31UL) /*!< EFLG (Bit 31) */ +#define MPU_EDR0_EFLG_Msk (0x80000000UL) /*!< EFLG (Bitfield-Mask: 0x01) */ +/* ========================================================= EDR1 ========================================================== */ +#define MPU_EDR1_ERW_Pos (0UL) /*!< ERW (Bit 0) */ +#define MPU_EDR1_ERW_Msk (0x1UL) /*!< ERW (Bitfield-Mask: 0x01) */ +#define MPU_EDR1_EATTR_Pos (1UL) /*!< EATTR (Bit 1) */ +#define MPU_EDR1_EATTR_Msk (0x1eUL) /*!< EATTR (Bitfield-Mask: 0x0f) */ +#define MPU_EDR1_EMN_Pos (5UL) /*!< EMN (Bit 5) */ +#define MPU_EDR1_EMN_Msk (0xe0UL) /*!< EMN (Bitfield-Mask: 0x07) */ +#define MPU_EDR1_EPID_Pos (8UL) /*!< EPID (Bit 8) */ +#define MPU_EDR1_EPID_Msk (0xff00UL) /*!< EPID (Bitfield-Mask: 0xff) */ +#define MPU_EDR1_EACD_Pos (16UL) /*!< EACD (Bit 16) */ +#define MPU_EDR1_EACD_Msk (0xff0000UL) /*!< EACD (Bitfield-Mask: 0xff) */ +#define MPU_EDR1_EFLG_Pos (31UL) /*!< EFLG (Bit 31) */ +#define MPU_EDR1_EFLG_Msk (0x80000000UL) /*!< EFLG (Bitfield-Mask: 0x01) */ +/* ========================================================= EDR2 ========================================================== */ +#define MPU_EDR2_ERW_Pos (0UL) /*!< ERW (Bit 0) */ +#define MPU_EDR2_ERW_Msk (0x1UL) /*!< ERW (Bitfield-Mask: 0x01) */ +#define MPU_EDR2_EATTR_Pos (1UL) /*!< EATTR (Bit 1) */ +#define MPU_EDR2_EATTR_Msk (0x1eUL) /*!< EATTR (Bitfield-Mask: 0x0f) */ +#define MPU_EDR2_EMN_Pos (5UL) /*!< EMN (Bit 5) */ +#define MPU_EDR2_EMN_Msk (0xe0UL) /*!< EMN (Bitfield-Mask: 0x07) */ +#define MPU_EDR2_EPID_Pos (8UL) /*!< EPID (Bit 8) */ +#define MPU_EDR2_EPID_Msk (0xff00UL) /*!< EPID (Bitfield-Mask: 0xff) */ +#define MPU_EDR2_EACD_Pos (16UL) /*!< EACD (Bit 16) */ +#define MPU_EDR2_EACD_Msk (0xff0000UL) /*!< EACD (Bitfield-Mask: 0xff) */ +#define MPU_EDR2_EFLG_Pos (31UL) /*!< EFLG (Bit 31) */ +#define MPU_EDR2_EFLG_Msk (0x80000000UL) /*!< EFLG (Bitfield-Mask: 0x01) */ +/* ========================================================= MPID ========================================================== */ +#define MPU_MPID_M0PID_Pos (0UL) /*!< M0PID (Bit 0) */ +#define MPU_MPID_M0PID_Msk (0xffUL) /*!< M0PID (Bitfield-Mask: 0xff) */ +#define MPU_MPID_M1PID_Pos (8UL) /*!< M1PID (Bit 8) */ +#define MPU_MPID_M1PID_Msk (0xff00UL) /*!< M1PID (Bitfield-Mask: 0xff) */ +/* ====================================================== RGD0_WORD0 ======================================================= */ +#define MPU_RGD0_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ +#define MPU_RGD0_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD0_WORD1 ======================================================= */ +#define MPU_RGD0_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ +#define MPU_RGD0_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD0_WORD2 ======================================================= */ +#define MPU_RGD0_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGD0_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGD0_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGD0_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGD0_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGD0_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGD0_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGD0_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGD0_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGD0_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGD0_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGD0_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGD0_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGD0_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGD0_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGD0_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGD0_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGD0_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ====================================================== RGD0_WORD3 ======================================================= */ +#define MPU_RGD0_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ +#define MPU_RGD0_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ +#define MPU_RGD0_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ +#define MPU_RGD0_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ +#define MPU_RGD0_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ +#define MPU_RGD0_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ +/* ====================================================== RGD1_WORD0 ======================================================= */ +#define MPU_RGD1_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ +#define MPU_RGD1_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD1_WORD1 ======================================================= */ +#define MPU_RGD1_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ +#define MPU_RGD1_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD1_WORD2 ======================================================= */ +#define MPU_RGD1_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGD1_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGD1_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGD1_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGD1_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGD1_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGD1_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGD1_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGD1_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGD1_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGD1_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGD1_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGD1_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGD1_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGD1_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGD1_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGD1_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGD1_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ====================================================== RGD1_WORD3 ======================================================= */ +#define MPU_RGD1_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ +#define MPU_RGD1_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ +#define MPU_RGD1_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ +#define MPU_RGD1_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ +#define MPU_RGD1_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ +#define MPU_RGD1_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ +/* ====================================================== RGD2_WORD0 ======================================================= */ +#define MPU_RGD2_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ +#define MPU_RGD2_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD2_WORD1 ======================================================= */ +#define MPU_RGD2_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ +#define MPU_RGD2_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD2_WORD2 ======================================================= */ +#define MPU_RGD2_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGD2_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGD2_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGD2_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGD2_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGD2_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGD2_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGD2_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGD2_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGD2_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGD2_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGD2_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGD2_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGD2_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGD2_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGD2_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGD2_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGD2_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ====================================================== RGD2_WORD3 ======================================================= */ +#define MPU_RGD2_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ +#define MPU_RGD2_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ +#define MPU_RGD2_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ +#define MPU_RGD2_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ +#define MPU_RGD2_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ +#define MPU_RGD2_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ +/* ====================================================== RGD3_WORD0 ======================================================= */ +#define MPU_RGD3_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ +#define MPU_RGD3_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD3_WORD1 ======================================================= */ +#define MPU_RGD3_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ +#define MPU_RGD3_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD3_WORD2 ======================================================= */ +#define MPU_RGD3_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGD3_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGD3_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGD3_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGD3_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGD3_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGD3_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGD3_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGD3_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGD3_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGD3_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGD3_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGD3_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGD3_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGD3_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGD3_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGD3_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGD3_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ====================================================== RGD3_WORD3 ======================================================= */ +#define MPU_RGD3_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ +#define MPU_RGD3_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ +#define MPU_RGD3_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ +#define MPU_RGD3_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ +#define MPU_RGD3_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ +#define MPU_RGD3_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ +/* ====================================================== RGD4_WORD0 ======================================================= */ +#define MPU_RGD4_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ +#define MPU_RGD4_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD4_WORD1 ======================================================= */ +#define MPU_RGD4_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ +#define MPU_RGD4_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD4_WORD2 ======================================================= */ +#define MPU_RGD4_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGD4_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGD4_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGD4_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGD4_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGD4_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGD4_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGD4_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGD4_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGD4_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGD4_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGD4_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGD4_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGD4_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGD4_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGD4_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGD4_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGD4_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ====================================================== RGD4_WORD3 ======================================================= */ +#define MPU_RGD4_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ +#define MPU_RGD4_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ +#define MPU_RGD4_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ +#define MPU_RGD4_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ +#define MPU_RGD4_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ +#define MPU_RGD4_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ +/* ====================================================== RGD5_WORD0 ======================================================= */ +#define MPU_RGD5_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ +#define MPU_RGD5_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD5_WORD1 ======================================================= */ +#define MPU_RGD5_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ +#define MPU_RGD5_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD5_WORD2 ======================================================= */ +#define MPU_RGD5_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGD5_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGD5_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGD5_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGD5_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGD5_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGD5_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGD5_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGD5_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGD5_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGD5_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGD5_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGD5_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGD5_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGD5_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGD5_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGD5_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGD5_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ====================================================== RGD5_WORD3 ======================================================= */ +#define MPU_RGD5_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ +#define MPU_RGD5_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ +#define MPU_RGD5_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ +#define MPU_RGD5_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ +#define MPU_RGD5_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ +#define MPU_RGD5_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ +/* ====================================================== RGD6_WORD0 ======================================================= */ +#define MPU_RGD6_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ +#define MPU_RGD6_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD6_WORD1 ======================================================= */ +#define MPU_RGD6_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ +#define MPU_RGD6_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD6_WORD2 ======================================================= */ +#define MPU_RGD6_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGD6_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGD6_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGD6_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGD6_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGD6_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGD6_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGD6_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGD6_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGD6_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGD6_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGD6_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGD6_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGD6_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGD6_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGD6_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGD6_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGD6_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ====================================================== RGD6_WORD3 ======================================================= */ +#define MPU_RGD6_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ +#define MPU_RGD6_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ +#define MPU_RGD6_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ +#define MPU_RGD6_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ +#define MPU_RGD6_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ +#define MPU_RGD6_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ +/* ====================================================== RGD7_WORD0 ======================================================= */ +#define MPU_RGD7_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ +#define MPU_RGD7_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD7_WORD1 ======================================================= */ +#define MPU_RGD7_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ +#define MPU_RGD7_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== RGD7_WORD2 ======================================================= */ +#define MPU_RGD7_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGD7_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGD7_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGD7_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGD7_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGD7_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGD7_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGD7_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGD7_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGD7_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGD7_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGD7_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGD7_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGD7_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGD7_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGD7_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGD7_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGD7_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ====================================================== RGD7_WORD3 ======================================================= */ +#define MPU_RGD7_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ +#define MPU_RGD7_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ +#define MPU_RGD7_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ +#define MPU_RGD7_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ +#define MPU_RGD7_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ +#define MPU_RGD7_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ +/* ======================================================== RGDAAC0 ======================================================== */ +#define MPU_RGDAAC0_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGDAAC0_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGDAAC0_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGDAAC0_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGDAAC0_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGDAAC0_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGDAAC0_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGDAAC0_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGDAAC0_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGDAAC0_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGDAAC0_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGDAAC0_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGDAAC0_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGDAAC0_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGDAAC0_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGDAAC0_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGDAAC0_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC0_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGDAAC0_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ======================================================== RGDAAC1 ======================================================== */ +#define MPU_RGDAAC1_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGDAAC1_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGDAAC1_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGDAAC1_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGDAAC1_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGDAAC1_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGDAAC1_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGDAAC1_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGDAAC1_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGDAAC1_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGDAAC1_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGDAAC1_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGDAAC1_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGDAAC1_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGDAAC1_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGDAAC1_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGDAAC1_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC1_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGDAAC1_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ======================================================== RGDAAC2 ======================================================== */ +#define MPU_RGDAAC2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGDAAC2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGDAAC2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGDAAC2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGDAAC2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGDAAC2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGDAAC2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGDAAC2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGDAAC2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGDAAC2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGDAAC2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGDAAC2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGDAAC2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGDAAC2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGDAAC2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGDAAC2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGDAAC2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGDAAC2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ======================================================== RGDAAC3 ======================================================== */ +#define MPU_RGDAAC3_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGDAAC3_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGDAAC3_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGDAAC3_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGDAAC3_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGDAAC3_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGDAAC3_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGDAAC3_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGDAAC3_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGDAAC3_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGDAAC3_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGDAAC3_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGDAAC3_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGDAAC3_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGDAAC3_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGDAAC3_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGDAAC3_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC3_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGDAAC3_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ======================================================== RGDAAC4 ======================================================== */ +#define MPU_RGDAAC4_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGDAAC4_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGDAAC4_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGDAAC4_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGDAAC4_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGDAAC4_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGDAAC4_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGDAAC4_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGDAAC4_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGDAAC4_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGDAAC4_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGDAAC4_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGDAAC4_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGDAAC4_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGDAAC4_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGDAAC4_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGDAAC4_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC4_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGDAAC4_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ======================================================== RGDAAC5 ======================================================== */ +#define MPU_RGDAAC5_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGDAAC5_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGDAAC5_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGDAAC5_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGDAAC5_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGDAAC5_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGDAAC5_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGDAAC5_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGDAAC5_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGDAAC5_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGDAAC5_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGDAAC5_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGDAAC5_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGDAAC5_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGDAAC5_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGDAAC5_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGDAAC5_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC5_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGDAAC5_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ======================================================== RGDAAC6 ======================================================== */ +#define MPU_RGDAAC6_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGDAAC6_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGDAAC6_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGDAAC6_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGDAAC6_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGDAAC6_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGDAAC6_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGDAAC6_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGDAAC6_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGDAAC6_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGDAAC6_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGDAAC6_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGDAAC6_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGDAAC6_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGDAAC6_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGDAAC6_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGDAAC6_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC6_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGDAAC6_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ +/* ======================================================== RGDAAC7 ======================================================== */ +#define MPU_RGDAAC7_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ +#define MPU_RGDAAC7_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ +#define MPU_RGDAAC7_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ +#define MPU_RGDAAC7_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ +#define MPU_RGDAAC7_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ +#define MPU_RGDAAC7_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ +#define MPU_RGDAAC7_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ +#define MPU_RGDAAC7_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ +#define MPU_RGDAAC7_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ +#define MPU_RGDAAC7_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ +#define MPU_RGDAAC7_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ +#define MPU_RGDAAC7_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ +#define MPU_RGDAAC7_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ +#define MPU_RGDAAC7_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ +#define MPU_RGDAAC7_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ +#define MPU_RGDAAC7_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ +#define MPU_RGDAAC7_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ +#define MPU_RGDAAC7_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ +#define MPU_RGDAAC7_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CKGEN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTRL ========================================================== */ +#define CKGEN_CTRL_BUS_CLK_DIV_VLPR_Pos (0UL) /*!< BUS_CLK_DIV_VLPR (Bit 0) */ +#define CKGEN_CTRL_BUS_CLK_DIV_VLPR_Msk (0xfUL) /*!< BUS_CLK_DIV_VLPR (Bitfield-Mask: 0x0f) */ +#define CKGEN_CTRL_BUS_CLK_DIV_RUN_Pos (4UL) /*!< BUS_CLK_DIV_RUN (Bit 4) */ +#define CKGEN_CTRL_BUS_CLK_DIV_RUN_Msk (0xf0UL) /*!< BUS_CLK_DIV_RUN (Bitfield-Mask: 0x0f) */ +#define CKGEN_CTRL_SYSCLK_DIV_VLPR_Pos (12UL) /*!< SYSCLK_DIV_VLPR (Bit 12) */ +#define CKGEN_CTRL_SYSCLK_DIV_VLPR_Msk (0xf000UL) /*!< SYSCLK_DIV_VLPR (Bitfield-Mask: 0x0f) */ +#define CKGEN_CTRL_SYSCLK_DIV_Pos (16UL) /*!< SYSCLK_DIV (Bit 16) */ +#define CKGEN_CTRL_SYSCLK_DIV_Msk (0xf0000UL) /*!< SYSCLK_DIV (Bitfield-Mask: 0x0f) */ +#define CKGEN_CTRL_PLL_REF_SEL_Pos (20UL) /*!< PLL_REF_SEL (Bit 20) */ +#define CKGEN_CTRL_PLL_REF_SEL_Msk (0x100000UL) /*!< PLL_REF_SEL (Bitfield-Mask: 0x01) */ +#define CKGEN_CTRL_XOSC_MON_EN_Pos (21UL) /*!< XOSC_MON_EN (Bit 21) */ +#define CKGEN_CTRL_XOSC_MON_EN_Msk (0x200000UL) /*!< XOSC_MON_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos (22UL) /*!< SYSCLK_SRC_SEL_RUN (Bit 22) */ +#define CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk (0x3c00000UL) /*!< SYSCLK_SRC_SEL_RUN (Bitfield-Mask: 0x0f) */ +#define CKGEN_CTRL_SYSCLK_SRC_SEL_VLPR_Pos (26UL) /*!< SYSCLK_SRC_SEL_VLPR (Bit 26) */ +#define CKGEN_CTRL_SYSCLK_SRC_SEL_VLPR_Msk (0x3c000000UL) /*!< SYSCLK_SRC_SEL_VLPR (Bitfield-Mask: 0x0f) */ +#define CKGEN_CTRL_LOCK_Pos (31UL) /*!< LOCK (Bit 31) */ +#define CKGEN_CTRL_LOCK_Msk (0x80000000UL) /*!< LOCK (Bitfield-Mask: 0x01) */ +/* ====================================================== LP_CLK_MUX ======================================================= */ +#define CKGEN_LP_CLK_MUX_LSI_CLK_MUX_Pos (0UL) /*!< LSI_CLK_MUX (Bit 0) */ +#define CKGEN_LP_CLK_MUX_LSI_CLK_MUX_Msk (0x3UL) /*!< LSI_CLK_MUX (Bitfield-Mask: 0x03) */ +#define CKGEN_LP_CLK_MUX_RTC_CLK_MUX_Pos (2UL) /*!< RTC_CLK_MUX (Bit 2) */ +#define CKGEN_LP_CLK_MUX_RTC_CLK_MUX_Msk (0xcUL) /*!< RTC_CLK_MUX (Bitfield-Mask: 0x03) */ +/* ===================================================== PERI_CLK_EN0 ====================================================== */ +#define CKGEN_PERI_CLK_EN0_UART0_EN_Pos (0UL) /*!< UART0_EN (Bit 0) */ +#define CKGEN_PERI_CLK_EN0_UART0_EN_Msk (0x1UL) /*!< UART0_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_UART1_EN_Pos (1UL) /*!< UART1_EN (Bit 1) */ +#define CKGEN_PERI_CLK_EN0_UART1_EN_Msk (0x2UL) /*!< UART1_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_UART2_EN_Pos (2UL) /*!< UART2_EN (Bit 2) */ +#define CKGEN_PERI_CLK_EN0_UART2_EN_Msk (0x4UL) /*!< UART2_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_UART3_EN_Pos (3UL) /*!< UART3_EN (Bit 3) */ +#define CKGEN_PERI_CLK_EN0_UART3_EN_Msk (0x8UL) /*!< UART3_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_SPI0_EN_Pos (6UL) /*!< SPI0_EN (Bit 6) */ +#define CKGEN_PERI_CLK_EN0_SPI0_EN_Msk (0x40UL) /*!< SPI0_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_SPI1_EN_Pos (7UL) /*!< SPI1_EN (Bit 7) */ +#define CKGEN_PERI_CLK_EN0_SPI1_EN_Msk (0x80UL) /*!< SPI1_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_SPI2_EN_Pos (8UL) /*!< SPI2_EN (Bit 8) */ +#define CKGEN_PERI_CLK_EN0_SPI2_EN_Msk (0x100UL) /*!< SPI2_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_I2C0_EN_Pos (9UL) /*!< I2C0_EN (Bit 9) */ +#define CKGEN_PERI_CLK_EN0_I2C0_EN_Msk (0x200UL) /*!< I2C0_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_PCT_EN_Pos (11UL) /*!< PCT_EN (Bit 11) */ +#define CKGEN_PERI_CLK_EN0_PCT_EN_Msk (0x800UL) /*!< PCT_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_PWM0_EN_Pos (15UL) /*!< PWM0_EN (Bit 15) */ +#define CKGEN_PERI_CLK_EN0_PWM0_EN_Msk (0x8000UL) /*!< PWM0_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_PWM1_EN_Pos (16UL) /*!< PWM1_EN (Bit 16) */ +#define CKGEN_PERI_CLK_EN0_PWM1_EN_Msk (0x10000UL) /*!< PWM1_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_PWM2_EN_Pos (17UL) /*!< PWM2_EN (Bit 17) */ +#define CKGEN_PERI_CLK_EN0_PWM2_EN_Msk (0x20000UL) /*!< PWM2_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_PWM3_EN_Pos (18UL) /*!< PWM3_EN (Bit 18) */ +#define CKGEN_PERI_CLK_EN0_PWM3_EN_Msk (0x40000UL) /*!< PWM3_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_PWM4_EN_Pos (19UL) /*!< PWM4_EN (Bit 19) */ +#define CKGEN_PERI_CLK_EN0_PWM4_EN_Msk (0x80000UL) /*!< PWM4_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN0_PWM5_EN_Pos (20UL) /*!< PWM5_EN (Bit 20) */ +#define CKGEN_PERI_CLK_EN0_PWM5_EN_Msk (0x100000UL) /*!< PWM5_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== PERI_CLK_EN1 ====================================================== */ +#define CKGEN_PERI_CLK_EN1_RTC_EN_Pos (1UL) /*!< RTC_EN (Bit 1) */ +#define CKGEN_PERI_CLK_EN1_RTC_EN_Msk (0x2UL) /*!< RTC_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN1_DMA_EN_Pos (2UL) /*!< DMA_EN (Bit 2) */ +#define CKGEN_PERI_CLK_EN1_DMA_EN_Msk (0x4UL) /*!< DMA_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN1_GPIO_EN_Pos (5UL) /*!< GPIO_EN (Bit 5) */ +#define CKGEN_PERI_CLK_EN1_GPIO_EN_Msk (0x20UL) /*!< GPIO_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN1_WDG_EN_Pos (6UL) /*!< WDG_EN (Bit 6) */ +#define CKGEN_PERI_CLK_EN1_WDG_EN_Msk (0x40UL) /*!< WDG_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN1_EWDG_EN_Pos (7UL) /*!< EWDG_EN (Bit 7) */ +#define CKGEN_PERI_CLK_EN1_EWDG_EN_Msk (0x80UL) /*!< EWDG_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN1_CRC_EN_Pos (8UL) /*!< CRC_EN (Bit 8) */ +#define CKGEN_PERI_CLK_EN1_CRC_EN_Msk (0x100UL) /*!< CRC_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN1_CAN0_EN_Pos (9UL) /*!< CAN0_EN (Bit 9) */ +#define CKGEN_PERI_CLK_EN1_CAN0_EN_Msk (0x200UL) /*!< CAN0_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN1_CAN1_EN_Pos (10UL) /*!< CAN1_EN (Bit 10) */ +#define CKGEN_PERI_CLK_EN1_CAN1_EN_Msk (0x400UL) /*!< CAN1_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN1_CAN2_EN_Pos (11UL) /*!< CAN2_EN (Bit 11) */ +#define CKGEN_PERI_CLK_EN1_CAN2_EN_Msk (0x800UL) /*!< CAN2_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN1_CAN3_EN_Pos (12UL) /*!< CAN3_EN (Bit 12) */ +#define CKGEN_PERI_CLK_EN1_CAN3_EN_Msk (0x1000UL) /*!< CAN3_EN (Bitfield-Mask: 0x01) */ +/* ===================================================== PERI_CLK_EN2 ====================================================== */ +#define CKGEN_PERI_CLK_EN2_CTU_EN_Pos (1UL) /*!< CTU_EN (Bit 1) */ +#define CKGEN_PERI_CLK_EN2_CTU_EN_Msk (0x2UL) /*!< CTU_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN2_ACMP_EN_Pos (8UL) /*!< ACMP_EN (Bit 8) */ +#define CKGEN_PERI_CLK_EN2_ACMP_EN_Msk (0x100UL) /*!< ACMP_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN2_PDT0_EN_Pos (9UL) /*!< PDT0_EN (Bit 9) */ +#define CKGEN_PERI_CLK_EN2_PDT0_EN_Msk (0x200UL) /*!< PDT0_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN2_PDT1_EN_Pos (10UL) /*!< PDT1_EN (Bit 10) */ +#define CKGEN_PERI_CLK_EN2_PDT1_EN_Msk (0x400UL) /*!< PDT1_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN2_ADC0_EN_Pos (11UL) /*!< ADC0_EN (Bit 11) */ +#define CKGEN_PERI_CLK_EN2_ADC0_EN_Msk (0x800UL) /*!< ADC0_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN2_ADC1_EN_Pos (12UL) /*!< ADC1_EN (Bit 12) */ +#define CKGEN_PERI_CLK_EN2_ADC1_EN_Msk (0x1000UL) /*!< ADC1_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN2_TIMER_EN_Pos (13UL) /*!< TIMER_EN (Bit 13) */ +#define CKGEN_PERI_CLK_EN2_TIMER_EN_Msk (0x2000UL) /*!< TIMER_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN2_EIO_EN_Pos (14UL) /*!< EIO_EN (Bit 14) */ +#define CKGEN_PERI_CLK_EN2_EIO_EN_Msk (0x4000UL) /*!< EIO_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_EN2_SMU_EN_Pos (19UL) /*!< SMU_EN (Bit 19) */ +#define CKGEN_PERI_CLK_EN2_SMU_EN_Msk (0x80000UL) /*!< SMU_EN (Bitfield-Mask: 0x01) */ +/* ======================================================= RCM_CTRL ======================================================== */ +#define CKGEN_RCM_CTRL_EXT_RST_FILTER_EN_Pos (0UL) /*!< EXT_RST_FILTER_EN (Bit 0) */ +#define CKGEN_RCM_CTRL_EXT_RST_FILTER_EN_Msk (0x1UL) /*!< EXT_RST_FILTER_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_CTRL_EXT_RST_FILTER_VAL_Pos (1UL) /*!< EXT_RST_FILTER_VAL (Bit 1) */ +#define CKGEN_RCM_CTRL_EXT_RST_FILTER_VAL_Msk (0xfeUL) /*!< EXT_RST_FILTER_VAL (Bitfield-Mask: 0x7f) */ +#define CKGEN_RCM_CTRL_RST_DLY_TIME_Pos (8UL) /*!< RST_DLY_TIME (Bit 8) */ +#define CKGEN_RCM_CTRL_RST_DLY_TIME_Msk (0x300UL) /*!< RST_DLY_TIME (Bitfield-Mask: 0x03) */ +#define CKGEN_RCM_CTRL_SW_RST_INT_EN_Pos (10UL) /*!< SW_RST_INT_EN (Bit 10) */ +#define CKGEN_RCM_CTRL_SW_RST_INT_EN_Msk (0x400UL) /*!< SW_RST_INT_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_CTRL_LOCKUP_RST_INT_EN_Pos (11UL) /*!< LOCKUP_RST_INT_EN (Bit 11) */ +#define CKGEN_RCM_CTRL_LOCKUP_RST_INT_EN_Msk (0x800UL) /*!< LOCKUP_RST_INT_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_CTRL_ACK_ERR_RST_INT_EN_Pos (12UL) /*!< ACK_ERR_RST_INT_EN (Bit 12) */ +#define CKGEN_RCM_CTRL_ACK_ERR_RST_INT_EN_Msk (0x1000UL) /*!< ACK_ERR_RST_INT_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_CTRL_WDG_RST_INT_EN_Pos (13UL) /*!< WDG_RST_INT_EN (Bit 13) */ +#define CKGEN_RCM_CTRL_WDG_RST_INT_EN_Msk (0x2000UL) /*!< WDG_RST_INT_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_CTRL_XOSC_LOSS_RST_INT_EN_Pos (15UL) /*!< XOSC_LOSS_RST_INT_EN (Bit 15) */ +#define CKGEN_RCM_CTRL_XOSC_LOSS_RST_INT_EN_Msk (0x8000UL) /*!< XOSC_LOSS_RST_INT_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_CTRL_PLL_UNLOCK_RST_INT_EN_Pos (16UL) /*!< PLL_UNLOCK_RST_INT_EN (Bit 16) */ +#define CKGEN_RCM_CTRL_PLL_UNLOCK_RST_INT_EN_Msk (0x10000UL) /*!< PLL_UNLOCK_RST_INT_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_CTRL_VHSI_LOSS_RST_INT_EN_Pos (17UL) /*!< VHSI_LOSS_RST_INT_EN (Bit 17) */ +#define CKGEN_RCM_CTRL_VHSI_LOSS_RST_INT_EN_Msk (0x20000UL) /*!< VHSI_LOSS_RST_INT_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_CTRL_SMU_ERR_RST_INT_EN_Pos (19UL) /*!< SMU_ERR_RST_INT_EN (Bit 19) */ +#define CKGEN_RCM_CTRL_SMU_ERR_RST_INT_EN_Msk (0x80000UL) /*!< SMU_ERR_RST_INT_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_CTRL_ECC2_ERR_RST_INT_EN_Pos (20UL) /*!< ECC2_ERR_RST_INT_EN (Bit 20) */ +#define CKGEN_RCM_CTRL_ECC2_ERR_RST_INT_EN_Msk (0x100000UL) /*!< ECC2_ERR_RST_INT_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_CTRL_RST_CLK_SEL_Pos (22UL) /*!< RST_CLK_SEL (Bit 22) */ +#define CKGEN_RCM_CTRL_RST_CLK_SEL_Msk (0x400000UL) /*!< RST_CLK_SEL (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_CTRL_RST_GLB_INT_EN_Pos (23UL) /*!< RST_GLB_INT_EN (Bit 23) */ +#define CKGEN_RCM_CTRL_RST_GLB_INT_EN_Msk (0x800000UL) /*!< RST_GLB_INT_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_CTRL_RST_CLK_AUTO_SEL_Pos (31UL) /*!< RST_CLK_AUTO_SEL (Bit 31) */ +#define CKGEN_RCM_CTRL_RST_CLK_AUTO_SEL_Msk (0x80000000UL) /*!< RST_CLK_AUTO_SEL (Bitfield-Mask: 0x01) */ +/* ======================================================== RCM_EN ========================================================= */ +#define CKGEN_RCM_EN_SW_RST_EN_Pos (0UL) /*!< SW_RST_EN (Bit 0) */ +#define CKGEN_RCM_EN_SW_RST_EN_Msk (0x1UL) /*!< SW_RST_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_EN_LOCKUP_RST_EN_Pos (1UL) /*!< LOCKUP_RST_EN (Bit 1) */ +#define CKGEN_RCM_EN_LOCKUP_RST_EN_Msk (0x2UL) /*!< LOCKUP_RST_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_EN_ACK_ERR_RST_EN_Pos (2UL) /*!< ACK_ERR_RST_EN (Bit 2) */ +#define CKGEN_RCM_EN_ACK_ERR_RST_EN_Msk (0x4UL) /*!< ACK_ERR_RST_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_EN_WDG_RST_EN_Pos (3UL) /*!< WDG_RST_EN (Bit 3) */ +#define CKGEN_RCM_EN_WDG_RST_EN_Msk (0x8UL) /*!< WDG_RST_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_EN_XOSC_LOSS_RST_EN_Pos (5UL) /*!< XOSC_LOSS_RST_EN (Bit 5) */ +#define CKGEN_RCM_EN_XOSC_LOSS_RST_EN_Msk (0x20UL) /*!< XOSC_LOSS_RST_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_EN_PLL_UNLOCK_RST_EN_Pos (6UL) /*!< PLL_UNLOCK_RST_EN (Bit 6) */ +#define CKGEN_RCM_EN_PLL_UNLOCK_RST_EN_Msk (0x40UL) /*!< PLL_UNLOCK_RST_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_EN_VHSI_LOSS_RST_EN_Pos (7UL) /*!< VHSI_LOSS_RST_EN (Bit 7) */ +#define CKGEN_RCM_EN_VHSI_LOSS_RST_EN_Msk (0x80UL) /*!< VHSI_LOSS_RST_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_EN_EXT_RST_EN_Pos (8UL) /*!< EXT_RST_EN (Bit 8) */ +#define CKGEN_RCM_EN_EXT_RST_EN_Msk (0x100UL) /*!< EXT_RST_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_EN_SMU_ERR_RST_EN_Pos (9UL) /*!< SMU_ERR_RST_EN (Bit 9) */ +#define CKGEN_RCM_EN_SMU_ERR_RST_EN_Msk (0x200UL) /*!< SMU_ERR_RST_EN (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_EN_ECC2_ERR_RST_EN_Pos (10UL) /*!< ECC2_ERR_RST_EN (Bit 10) */ +#define CKGEN_RCM_EN_ECC2_ERR_RST_EN_Msk (0x400UL) /*!< ECC2_ERR_RST_EN (Bitfield-Mask: 0x01) */ +/* ====================================================== RCM_STATUS ======================================================= */ +#define CKGEN_RCM_STATUS_SW_RST_INT_FLAG_Pos (0UL) /*!< SW_RST_INT_FLAG (Bit 0) */ +#define CKGEN_RCM_STATUS_SW_RST_INT_FLAG_Msk (0x1UL) /*!< SW_RST_INT_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_LOCKUP_RST_INT_FLAG_Pos (1UL) /*!< LOCKUP_RST_INT_FLAG (Bit 1) */ +#define CKGEN_RCM_STATUS_LOCKUP_RST_INT_FLAG_Msk (0x2UL) /*!< LOCKUP_RST_INT_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_ACK_ERR_RST_INT_FLAG_Pos (2UL) /*!< ACK_ERR_RST_INT_FLAG (Bit 2) */ +#define CKGEN_RCM_STATUS_ACK_ERR_RST_INT_FLAG_Msk (0x4UL) /*!< ACK_ERR_RST_INT_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_WDG_RST_INT_FLAG_Pos (3UL) /*!< WDG_RST_INT_FLAG (Bit 3) */ +#define CKGEN_RCM_STATUS_WDG_RST_INT_FLAG_Msk (0x8UL) /*!< WDG_RST_INT_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_XOSC_LOSS_RST_INT_FLAG_Pos (5UL) /*!< XOSC_LOSS_RST_INT_FLAG (Bit 5) */ +#define CKGEN_RCM_STATUS_XOSC_LOSS_RST_INT_FLAG_Msk (0x20UL) /*!< XOSC_LOSS_RST_INT_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_PLL_UNLOCK_RST_INT_FLAG_Pos (6UL) /*!< PLL_UNLOCK_RST_INT_FLAG (Bit 6) */ +#define CKGEN_RCM_STATUS_PLL_UNLOCK_RST_INT_FLAG_Msk (0x40UL) /*!< PLL_UNLOCK_RST_INT_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_VHSI_LOSS_RST_INT_FLAG_Pos (7UL) /*!< VHSI_LOSS_RST_INT_FLAG (Bit 7) */ +#define CKGEN_RCM_STATUS_VHSI_LOSS_RST_INT_FLAG_Msk (0x80UL) /*!< VHSI_LOSS_RST_INT_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_SMU_ERR_RST_INT_FLAG_Pos (9UL) /*!< SMU_ERR_RST_INT_FLAG (Bit 9) */ +#define CKGEN_RCM_STATUS_SMU_ERR_RST_INT_FLAG_Msk (0x200UL) /*!< SMU_ERR_RST_INT_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_ECC2_ERR_RST_INT_FLAG_Pos (10UL) /*!< ECC2_ERR_RST_INT_FLAG (Bit 10) */ +#define CKGEN_RCM_STATUS_ECC2_ERR_RST_INT_FLAG_Msk (0x400UL) /*!< ECC2_ERR_RST_INT_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_RST_INT_STATUS_CLR_Pos (15UL) /*!< RST_INT_STATUS_CLR (Bit 15) */ +#define CKGEN_RCM_STATUS_RST_INT_STATUS_CLR_Msk (0x8000UL) /*!< RST_INT_STATUS_CLR (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_POR_RST_FLAG_Pos (16UL) /*!< POR_RST_FLAG (Bit 16) */ +#define CKGEN_RCM_STATUS_POR_RST_FLAG_Msk (0x10000UL) /*!< POR_RST_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_LVR_RST_FLAG_Pos (17UL) /*!< LVR_RST_FLAG (Bit 17) */ +#define CKGEN_RCM_STATUS_LVR_RST_FLAG_Msk (0x20000UL) /*!< LVR_RST_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_SW_RST_FLAG_Pos (18UL) /*!< SW_RST_FLAG (Bit 18) */ +#define CKGEN_RCM_STATUS_SW_RST_FLAG_Msk (0x40000UL) /*!< SW_RST_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_LOCKUP_RST_FLAG_Pos (19UL) /*!< LOCKUP_RST_FLAG (Bit 19) */ +#define CKGEN_RCM_STATUS_LOCKUP_RST_FLAG_Msk (0x80000UL) /*!< LOCKUP_RST_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_ACK_ERR_RST_FLAG_Pos (20UL) /*!< ACK_ERR_RST_FLAG (Bit 20) */ +#define CKGEN_RCM_STATUS_ACK_ERR_RST_FLAG_Msk (0x100000UL) /*!< ACK_ERR_RST_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_WDG_RST_FLAG_Pos (21UL) /*!< WDG_RST_FLAG (Bit 21) */ +#define CKGEN_RCM_STATUS_WDG_RST_FLAG_Msk (0x200000UL) /*!< WDG_RST_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_XOSC_LOSS_RST_FLAG_Pos (23UL) /*!< XOSC_LOSS_RST_FLAG (Bit 23) */ +#define CKGEN_RCM_STATUS_XOSC_LOSS_RST_FLAG_Msk (0x800000UL) /*!< XOSC_LOSS_RST_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_PLL_UNLOCK_RST_FLAG_Pos (24UL) /*!< PLL_UNLOCK_RST_FLAG (Bit 24) */ +#define CKGEN_RCM_STATUS_PLL_UNLOCK_RST_FLAG_Msk (0x1000000UL) /*!< PLL_UNLOCK_RST_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_VHSI_LOSS_RST_FLAG_Pos (25UL) /*!< VHSI_LOSS_RST_FLAG (Bit 25) */ +#define CKGEN_RCM_STATUS_VHSI_LOSS_RST_FLAG_Msk (0x2000000UL) /*!< VHSI_LOSS_RST_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_EXT_RST_FLAG_Pos (26UL) /*!< EXT_RST_FLAG (Bit 26) */ +#define CKGEN_RCM_STATUS_EXT_RST_FLAG_Msk (0x4000000UL) /*!< EXT_RST_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_SMU_ERR_RST_FLAG_Pos (27UL) /*!< SMU_ERR_RST_FLAG (Bit 27) */ +#define CKGEN_RCM_STATUS_SMU_ERR_RST_FLAG_Msk (0x8000000UL) /*!< SMU_ERR_RST_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_ECC2_ERR_RST_FLAG_Pos (28UL) /*!< ECC2_ERR_RST_FLAG (Bit 28) */ +#define CKGEN_RCM_STATUS_ECC2_ERR_RST_FLAG_Msk (0x10000000UL) /*!< ECC2_ERR_RST_FLAG (Bitfield-Mask: 0x01) */ +#define CKGEN_RCM_STATUS_RST_STATUS_CLR_Pos (31UL) /*!< RST_STATUS_CLR (Bit 31) */ +#define CKGEN_RCM_STATUS_RST_STATUS_CLR_Msk (0x80000000UL) /*!< RST_STATUS_CLR (Bitfield-Mask: 0x01) */ +/* ===================================================== PERI_SFT_RST0 ===================================================== */ +#define CKGEN_PERI_SFT_RST0_SRST_UART0_Pos (0UL) /*!< SRST_UART0 (Bit 0) */ +#define CKGEN_PERI_SFT_RST0_SRST_UART0_Msk (0x1UL) /*!< SRST_UART0 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_UART1_Pos (1UL) /*!< SRST_UART1 (Bit 1) */ +#define CKGEN_PERI_SFT_RST0_SRST_UART1_Msk (0x2UL) /*!< SRST_UART1 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_UART2_Pos (2UL) /*!< SRST_UART2 (Bit 2) */ +#define CKGEN_PERI_SFT_RST0_SRST_UART2_Msk (0x4UL) /*!< SRST_UART2 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_UART3_Pos (3UL) /*!< SRST_UART3 (Bit 3) */ +#define CKGEN_PERI_SFT_RST0_SRST_UART3_Msk (0x8UL) /*!< SRST_UART3 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_SPI0_Pos (6UL) /*!< SRST_SPI0 (Bit 6) */ +#define CKGEN_PERI_SFT_RST0_SRST_SPI0_Msk (0x40UL) /*!< SRST_SPI0 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_SPI1_Pos (7UL) /*!< SRST_SPI1 (Bit 7) */ +#define CKGEN_PERI_SFT_RST0_SRST_SPI1_Msk (0x80UL) /*!< SRST_SPI1 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_SPI2_Pos (8UL) /*!< SRST_SPI2 (Bit 8) */ +#define CKGEN_PERI_SFT_RST0_SRST_SPI2_Msk (0x100UL) /*!< SRST_SPI2 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_I2C0_Pos (9UL) /*!< SRST_I2C0 (Bit 9) */ +#define CKGEN_PERI_SFT_RST0_SRST_I2C0_Msk (0x200UL) /*!< SRST_I2C0 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_PCT_Pos (11UL) /*!< SRST_PCT (Bit 11) */ +#define CKGEN_PERI_SFT_RST0_SRST_PCT_Msk (0x800UL) /*!< SRST_PCT (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_PWM0_Pos (15UL) /*!< SRST_PWM0 (Bit 15) */ +#define CKGEN_PERI_SFT_RST0_SRST_PWM0_Msk (0x8000UL) /*!< SRST_PWM0 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_PWM1_Pos (16UL) /*!< SRST_PWM1 (Bit 16) */ +#define CKGEN_PERI_SFT_RST0_SRST_PWM1_Msk (0x10000UL) /*!< SRST_PWM1 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_PWM2_Pos (17UL) /*!< SRST_PWM2 (Bit 17) */ +#define CKGEN_PERI_SFT_RST0_SRST_PWM2_Msk (0x20000UL) /*!< SRST_PWM2 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_PWM3_Pos (18UL) /*!< SRST_PWM3 (Bit 18) */ +#define CKGEN_PERI_SFT_RST0_SRST_PWM3_Msk (0x40000UL) /*!< SRST_PWM3 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_PWM4_Pos (19UL) /*!< SRST_PWM4 (Bit 19) */ +#define CKGEN_PERI_SFT_RST0_SRST_PWM4_Msk (0x80000UL) /*!< SRST_PWM4 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST0_SRST_PWM5_Pos (20UL) /*!< SRST_PWM5 (Bit 20) */ +#define CKGEN_PERI_SFT_RST0_SRST_PWM5_Msk (0x100000UL) /*!< SRST_PWM5 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERI_SFT_RST1 ===================================================== */ +#define CKGEN_PERI_SFT_RST1_SRST_DMA_Pos (2UL) /*!< SRST_DMA (Bit 2) */ +#define CKGEN_PERI_SFT_RST1_SRST_DMA_Msk (0x4UL) /*!< SRST_DMA (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST1_SRST_GPIO_Pos (5UL) /*!< SRST_GPIO (Bit 5) */ +#define CKGEN_PERI_SFT_RST1_SRST_GPIO_Msk (0x20UL) /*!< SRST_GPIO (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST1_SRST_WDG_Pos (6UL) /*!< SRST_WDG (Bit 6) */ +#define CKGEN_PERI_SFT_RST1_SRST_WDG_Msk (0x40UL) /*!< SRST_WDG (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST1_SRST_EWDG_Pos (7UL) /*!< SRST_EWDG (Bit 7) */ +#define CKGEN_PERI_SFT_RST1_SRST_EWDG_Msk (0x80UL) /*!< SRST_EWDG (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST1_SRST_CRC_Pos (8UL) /*!< SRST_CRC (Bit 8) */ +#define CKGEN_PERI_SFT_RST1_SRST_CRC_Msk (0x100UL) /*!< SRST_CRC (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST1_SRST_CAN0_Pos (9UL) /*!< SRST_CAN0 (Bit 9) */ +#define CKGEN_PERI_SFT_RST1_SRST_CAN0_Msk (0x200UL) /*!< SRST_CAN0 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST1_SRST_CAN1_Pos (10UL) /*!< SRST_CAN1 (Bit 10) */ +#define CKGEN_PERI_SFT_RST1_SRST_CAN1_Msk (0x400UL) /*!< SRST_CAN1 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST1_SRST_CAN2_Pos (11UL) /*!< SRST_CAN2 (Bit 11) */ +#define CKGEN_PERI_SFT_RST1_SRST_CAN2_Msk (0x800UL) /*!< SRST_CAN2 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST1_SRST_CAN3_Pos (12UL) /*!< SRST_CAN3 (Bit 12) */ +#define CKGEN_PERI_SFT_RST1_SRST_CAN3_Msk (0x1000UL) /*!< SRST_CAN3 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERI_SFT_RST2 ===================================================== */ +#define CKGEN_PERI_SFT_RST2_SRST_CTU_Pos (1UL) /*!< SRST_CTU (Bit 1) */ +#define CKGEN_PERI_SFT_RST2_SRST_CTU_Msk (0x2UL) /*!< SRST_CTU (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST2_SRST_ACMP_Pos (8UL) /*!< SRST_ACMP (Bit 8) */ +#define CKGEN_PERI_SFT_RST2_SRST_ACMP_Msk (0x100UL) /*!< SRST_ACMP (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST2_SRST_PDT0_Pos (9UL) /*!< SRST_PDT0 (Bit 9) */ +#define CKGEN_PERI_SFT_RST2_SRST_PDT0_Msk (0x200UL) /*!< SRST_PDT0 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST2_SRST_PDT1_Pos (10UL) /*!< SRST_PDT1 (Bit 10) */ +#define CKGEN_PERI_SFT_RST2_SRST_PDT1_Msk (0x400UL) /*!< SRST_PDT1 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST2_SRST_ADC0_Pos (11UL) /*!< SRST_ADC0 (Bit 11) */ +#define CKGEN_PERI_SFT_RST2_SRST_ADC0_Msk (0x800UL) /*!< SRST_ADC0 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST2_SRST_ADC1_Pos (12UL) /*!< SRST_ADC1 (Bit 12) */ +#define CKGEN_PERI_SFT_RST2_SRST_ADC1_Msk (0x1000UL) /*!< SRST_ADC1 (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST2_SRST_TIMER_Pos (13UL) /*!< SRST_TIMER (Bit 13) */ +#define CKGEN_PERI_SFT_RST2_SRST_TIMER_Msk (0x2000UL) /*!< SRST_TIMER (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_SFT_RST2_SRST_EIO_Pos (14UL) /*!< SRST_EIO (Bit 14) */ +#define CKGEN_PERI_SFT_RST2_SRST_EIO_Msk (0x4000UL) /*!< SRST_EIO (Bitfield-Mask: 0x01) */ +/* ======================================================= CLK_DIV1 ======================================================== */ +#define CKGEN_CLK_DIV1_SPLL_DIV1_Pos (0UL) /*!< SPLL_DIV1 (Bit 0) */ +#define CKGEN_CLK_DIV1_SPLL_DIV1_Msk (0x3fUL) /*!< SPLL_DIV1 (Bitfield-Mask: 0x3f) */ +#define CKGEN_CLK_DIV1_VHSI_DIV1_Pos (6UL) /*!< VHSI_DIV1 (Bit 6) */ +#define CKGEN_CLK_DIV1_VHSI_DIV1_Msk (0xfc0UL) /*!< VHSI_DIV1 (Bitfield-Mask: 0x3f) */ +#define CKGEN_CLK_DIV1_HSI_DIV1_Pos (12UL) /*!< HSI_DIV1 (Bit 12) */ +#define CKGEN_CLK_DIV1_HSI_DIV1_Msk (0x3f000UL) /*!< HSI_DIV1 (Bitfield-Mask: 0x3f) */ +#define CKGEN_CLK_DIV1_HSE_DIV1_Pos (18UL) /*!< HSE_DIV1 (Bit 18) */ +#define CKGEN_CLK_DIV1_HSE_DIV1_Msk (0xfc0000UL) /*!< HSE_DIV1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CLK_DIV2 ======================================================== */ +#define CKGEN_CLK_DIV2_SPLL_DIV2_Pos (0UL) /*!< SPLL_DIV2 (Bit 0) */ +#define CKGEN_CLK_DIV2_SPLL_DIV2_Msk (0x3fUL) /*!< SPLL_DIV2 (Bitfield-Mask: 0x3f) */ +#define CKGEN_CLK_DIV2_VHSI_DIV2_Pos (6UL) /*!< VHSI_DIV2 (Bit 6) */ +#define CKGEN_CLK_DIV2_VHSI_DIV2_Msk (0xfc0UL) /*!< VHSI_DIV2 (Bitfield-Mask: 0x3f) */ +#define CKGEN_CLK_DIV2_HSI_DIV2_Pos (12UL) /*!< HSI_DIV2 (Bit 12) */ +#define CKGEN_CLK_DIV2_HSI_DIV2_Msk (0x3f000UL) /*!< HSI_DIV2 (Bitfield-Mask: 0x3f) */ +#define CKGEN_CLK_DIV2_HSE_DIV2_Pos (18UL) /*!< HSE_DIV2 (Bit 18) */ +#define CKGEN_CLK_DIV2_HSE_DIV2_Msk (0xfc0000UL) /*!< HSE_DIV2 (Bitfield-Mask: 0x3f) */ +/* ===================================================== PERI_CLK_MUX0 ===================================================== */ +#define CKGEN_PERI_CLK_MUX0_I2C0_MUX_Pos (0UL) /*!< I2C0_MUX (Bit 0) */ +#define CKGEN_PERI_CLK_MUX0_I2C0_MUX_Msk (0x7UL) /*!< I2C0_MUX (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_MUX0_TIMER_MUX_Pos (8UL) /*!< TIMER_MUX (Bit 8) */ +#define CKGEN_PERI_CLK_MUX0_TIMER_MUX_Msk (0x700UL) /*!< TIMER_MUX (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_MUX0_SPI0_MUX_Pos (12UL) /*!< SPI0_MUX (Bit 12) */ +#define CKGEN_PERI_CLK_MUX0_SPI0_MUX_Msk (0x7000UL) /*!< SPI0_MUX (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_MUX0_SPI1_MUX_Pos (16UL) /*!< SPI1_MUX (Bit 16) */ +#define CKGEN_PERI_CLK_MUX0_SPI1_MUX_Msk (0x70000UL) /*!< SPI1_MUX (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_MUX0_SPI2_MUX_Pos (20UL) /*!< SPI2_MUX (Bit 20) */ +#define CKGEN_PERI_CLK_MUX0_SPI2_MUX_Msk (0x700000UL) /*!< SPI2_MUX (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_MUX0_ADC0_MUX_Pos (24UL) /*!< ADC0_MUX (Bit 24) */ +#define CKGEN_PERI_CLK_MUX0_ADC0_MUX_Msk (0x7000000UL) /*!< ADC0_MUX (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_MUX0_ADC1_MUX_Pos (28UL) /*!< ADC1_MUX (Bit 28) */ +#define CKGEN_PERI_CLK_MUX0_ADC1_MUX_Msk (0x70000000UL) /*!< ADC1_MUX (Bitfield-Mask: 0x07) */ +/* ===================================================== PERI_CLK_MUX1 ===================================================== */ +#define CKGEN_PERI_CLK_MUX1_CAN0_MUX_Pos (0UL) /*!< CAN0_MUX (Bit 0) */ +#define CKGEN_PERI_CLK_MUX1_CAN0_MUX_Msk (0x3UL) /*!< CAN0_MUX (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX1_CAN1_MUX_Pos (2UL) /*!< CAN1_MUX (Bit 2) */ +#define CKGEN_PERI_CLK_MUX1_CAN1_MUX_Msk (0xcUL) /*!< CAN1_MUX (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX1_CAN2_MUX_Pos (4UL) /*!< CAN2_MUX (Bit 4) */ +#define CKGEN_PERI_CLK_MUX1_CAN2_MUX_Msk (0x30UL) /*!< CAN2_MUX (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX1_CAN3_MUX_Pos (6UL) /*!< CAN3_MUX (Bit 6) */ +#define CKGEN_PERI_CLK_MUX1_CAN3_MUX_Msk (0xc0UL) /*!< CAN3_MUX (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX1_PCT_MUX_Pos (12UL) /*!< PCT_MUX (Bit 12) */ +#define CKGEN_PERI_CLK_MUX1_PCT_MUX_Msk (0x7000UL) /*!< PCT_MUX (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_MUX1_EIO_MUX_Pos (16UL) /*!< EIO_MUX (Bit 16) */ +#define CKGEN_PERI_CLK_MUX1_EIO_MUX_Msk (0x70000UL) /*!< EIO_MUX (Bitfield-Mask: 0x07) */ +/* ===================================================== PERI_CLK_MUX2 ===================================================== */ +#define CKGEN_PERI_CLK_MUX2_UART0_MUX_Pos (0UL) /*!< UART0_MUX (Bit 0) */ +#define CKGEN_PERI_CLK_MUX2_UART0_MUX_Msk (0x7UL) /*!< UART0_MUX (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_MUX2_UART1_MUX_Pos (4UL) /*!< UART1_MUX (Bit 4) */ +#define CKGEN_PERI_CLK_MUX2_UART1_MUX_Msk (0x70UL) /*!< UART1_MUX (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_MUX2_UART2_MUX_Pos (8UL) /*!< UART2_MUX (Bit 8) */ +#define CKGEN_PERI_CLK_MUX2_UART2_MUX_Msk (0x700UL) /*!< UART2_MUX (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_MUX2_UART3_MUX_Pos (12UL) /*!< UART3_MUX (Bit 12) */ +#define CKGEN_PERI_CLK_MUX2_UART3_MUX_Msk (0x7000UL) /*!< UART3_MUX (Bitfield-Mask: 0x07) */ +/* ===================================================== PERI_CLK_MUX3 ===================================================== */ +#define CKGEN_PERI_CLK_MUX3_PWM0_EXT_Pos (0UL) /*!< PWM0_EXT (Bit 0) */ +#define CKGEN_PERI_CLK_MUX3_PWM0_EXT_Msk (0x3UL) /*!< PWM0_EXT (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX3_PWM0_INT_Pos (2UL) /*!< PWM0_INT (Bit 2) */ +#define CKGEN_PERI_CLK_MUX3_PWM0_INT_Msk (0xcUL) /*!< PWM0_INT (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX3_PWM0_EXT_IN_Pos (4UL) /*!< PWM0_EXT_IN (Bit 4) */ +#define CKGEN_PERI_CLK_MUX3_PWM0_EXT_IN_Msk (0x10UL) /*!< PWM0_EXT_IN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_MUX3_PWM1_EXT_Pos (5UL) /*!< PWM1_EXT (Bit 5) */ +#define CKGEN_PERI_CLK_MUX3_PWM1_EXT_Msk (0x60UL) /*!< PWM1_EXT (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX3_PWM1_INT_Pos (7UL) /*!< PWM1_INT (Bit 7) */ +#define CKGEN_PERI_CLK_MUX3_PWM1_INT_Msk (0x180UL) /*!< PWM1_INT (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX3_PWM1_EXT_IN_Pos (9UL) /*!< PWM1_EXT_IN (Bit 9) */ +#define CKGEN_PERI_CLK_MUX3_PWM1_EXT_IN_Msk (0x200UL) /*!< PWM1_EXT_IN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_MUX3_PWM2_EXT_Pos (10UL) /*!< PWM2_EXT (Bit 10) */ +#define CKGEN_PERI_CLK_MUX3_PWM2_EXT_Msk (0xc00UL) /*!< PWM2_EXT (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX3_PWM2_INT_Pos (12UL) /*!< PWM2_INT (Bit 12) */ +#define CKGEN_PERI_CLK_MUX3_PWM2_INT_Msk (0x3000UL) /*!< PWM2_INT (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX3_PWM2_EXT_IN_Pos (14UL) /*!< PWM2_EXT_IN (Bit 14) */ +#define CKGEN_PERI_CLK_MUX3_PWM2_EXT_IN_Msk (0x4000UL) /*!< PWM2_EXT_IN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_MUX3_PWM3_EXT_Pos (15UL) /*!< PWM3_EXT (Bit 15) */ +#define CKGEN_PERI_CLK_MUX3_PWM3_EXT_Msk (0x18000UL) /*!< PWM3_EXT (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX3_PWM3_INT_Pos (17UL) /*!< PWM3_INT (Bit 17) */ +#define CKGEN_PERI_CLK_MUX3_PWM3_INT_Msk (0x60000UL) /*!< PWM3_INT (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX3_PWM3_EXT_IN_Pos (19UL) /*!< PWM3_EXT_IN (Bit 19) */ +#define CKGEN_PERI_CLK_MUX3_PWM3_EXT_IN_Msk (0x80000UL) /*!< PWM3_EXT_IN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_MUX3_PWM4_EXT_Pos (20UL) /*!< PWM4_EXT (Bit 20) */ +#define CKGEN_PERI_CLK_MUX3_PWM4_EXT_Msk (0x300000UL) /*!< PWM4_EXT (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX3_PWM4_INT_Pos (22UL) /*!< PWM4_INT (Bit 22) */ +#define CKGEN_PERI_CLK_MUX3_PWM4_INT_Msk (0xc00000UL) /*!< PWM4_INT (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX3_PWM4_EXT_IN_Pos (24UL) /*!< PWM4_EXT_IN (Bit 24) */ +#define CKGEN_PERI_CLK_MUX3_PWM4_EXT_IN_Msk (0x1000000UL) /*!< PWM4_EXT_IN (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_MUX3_PWM5_EXT_Pos (25UL) /*!< PWM5_EXT (Bit 25) */ +#define CKGEN_PERI_CLK_MUX3_PWM5_EXT_Msk (0x6000000UL) /*!< PWM5_EXT (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX3_PWM5_INT_Pos (27UL) /*!< PWM5_INT (Bit 27) */ +#define CKGEN_PERI_CLK_MUX3_PWM5_INT_Msk (0x18000000UL) /*!< PWM5_INT (Bitfield-Mask: 0x03) */ +#define CKGEN_PERI_CLK_MUX3_PWM5_EXT_IN_Pos (29UL) /*!< PWM5_EXT_IN (Bit 29) */ +#define CKGEN_PERI_CLK_MUX3_PWM5_EXT_IN_Msk (0x20000000UL) /*!< PWM5_EXT_IN (Bitfield-Mask: 0x01) */ +/* ====================================================== CLK_OUT_CFG ====================================================== */ +#define CKGEN_CLK_OUT_CFG_MUX1_Pos (0UL) /*!< MUX1 (Bit 0) */ +#define CKGEN_CLK_OUT_CFG_MUX1_Msk (0x7UL) /*!< MUX1 (Bitfield-Mask: 0x07) */ +#define CKGEN_CLK_OUT_CFG_MUX2_Pos (4UL) /*!< MUX2 (Bit 4) */ +#define CKGEN_CLK_OUT_CFG_MUX2_Msk (0xf0UL) /*!< MUX2 (Bitfield-Mask: 0x0f) */ +#define CKGEN_CLK_OUT_CFG_DIV_Pos (8UL) /*!< DIV (Bit 8) */ +#define CKGEN_CLK_OUT_CFG_DIV_Msk (0x700UL) /*!< DIV (Bitfield-Mask: 0x07) */ +#define CKGEN_CLK_OUT_CFG_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */ +#define CKGEN_CLK_OUT_CFG_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ===================================================== PERI_CLK_DIV ====================================================== */ +#define CKGEN_PERI_CLK_DIV_CAN0_DIV_Pos (0UL) /*!< CAN0_DIV (Bit 0) */ +#define CKGEN_PERI_CLK_DIV_CAN0_DIV_Msk (0x1UL) /*!< CAN0_DIV (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_DIV_CAN1_DIV_Pos (1UL) /*!< CAN1_DIV (Bit 1) */ +#define CKGEN_PERI_CLK_DIV_CAN1_DIV_Msk (0x2UL) /*!< CAN1_DIV (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_DIV_CAN2_DIV_Pos (2UL) /*!< CAN2_DIV (Bit 2) */ +#define CKGEN_PERI_CLK_DIV_CAN2_DIV_Msk (0x4UL) /*!< CAN2_DIV (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_DIV_CAN3_DIV_Pos (3UL) /*!< CAN3_DIV (Bit 3) */ +#define CKGEN_PERI_CLK_DIV_CAN3_DIV_Msk (0x8UL) /*!< CAN3_DIV (Bitfield-Mask: 0x01) */ +#define CKGEN_PERI_CLK_DIV_CAN0_TS_DIV_Pos (6UL) /*!< CAN0_TS_DIV (Bit 6) */ +#define CKGEN_PERI_CLK_DIV_CAN0_TS_DIV_Msk (0x1c0UL) /*!< CAN0_TS_DIV (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_DIV_CAN1_TS_DIV_Pos (9UL) /*!< CAN1_TS_DIV (Bit 9) */ +#define CKGEN_PERI_CLK_DIV_CAN1_TS_DIV_Msk (0xe00UL) /*!< CAN1_TS_DIV (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_DIV_CAN2_TS_DIV_Pos (12UL) /*!< CAN2_TS_DIV (Bit 12) */ +#define CKGEN_PERI_CLK_DIV_CAN2_TS_DIV_Msk (0x7000UL) /*!< CAN2_TS_DIV (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_DIV_CAN3_TS_DIV_Pos (15UL) /*!< CAN3_TS_DIV (Bit 15) */ +#define CKGEN_PERI_CLK_DIV_CAN3_TS_DIV_Msk (0x38000UL) /*!< CAN3_TS_DIV (Bitfield-Mask: 0x07) */ +#define CKGEN_PERI_CLK_DIV_PCT_DIV_Pos (24UL) /*!< PCT_DIV (Bit 24) */ +#define CKGEN_PERI_CLK_DIV_PCT_DIV_Msk (0xf000000UL) /*!< PCT_DIV (Bitfield-Mask: 0x0f) */ +#define CKGEN_PERI_CLK_DIV_TPIU_DIV_Pos (28UL) /*!< TPIU_DIV (Bit 28) */ +#define CKGEN_PERI_CLK_DIV_TPIU_DIV_Msk (0xf0000000UL) /*!< TPIU_DIV (Bitfield-Mask: 0x0f) */ + + +/* =========================================================================================================================== */ +/* ================ PBR ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= MPR_CORE ======================================================== */ +#define PBR_MPR_CORE_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define PBR_MPR_CORE_MPL_Msk (0x1UL) /*!< MPL (Bitfield-Mask: 0x01) */ +#define PBR_MPR_CORE_MTW_Pos (1UL) /*!< MTW (Bit 1) */ +#define PBR_MPR_CORE_MTW_Msk (0x2UL) /*!< MTW (Bitfield-Mask: 0x01) */ +#define PBR_MPR_CORE_MTR_Pos (2UL) /*!< MTR (Bit 2) */ +#define PBR_MPR_CORE_MTR_Msk (0x4UL) /*!< MTR (Bitfield-Mask: 0x01) */ +/* ======================================================= MPR_DEBUG ======================================================= */ +#define PBR_MPR_DEBUG_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define PBR_MPR_DEBUG_MPL_Msk (0x1UL) /*!< MPL (Bitfield-Mask: 0x01) */ +#define PBR_MPR_DEBUG_MTW_Pos (1UL) /*!< MTW (Bit 1) */ +#define PBR_MPR_DEBUG_MTW_Msk (0x2UL) /*!< MTW (Bitfield-Mask: 0x01) */ +#define PBR_MPR_DEBUG_MTR_Pos (2UL) /*!< MTR (Bit 2) */ +#define PBR_MPR_DEBUG_MTR_Msk (0x4UL) /*!< MTR (Bitfield-Mask: 0x01) */ +/* ======================================================== MPR_DMA ======================================================== */ +#define PBR_MPR_DMA_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define PBR_MPR_DMA_MPL_Msk (0x1UL) /*!< MPL (Bitfield-Mask: 0x01) */ +#define PBR_MPR_DMA_MTW_Pos (1UL) /*!< MTW (Bit 1) */ +#define PBR_MPR_DMA_MTW_Msk (0x2UL) /*!< MTW (Bitfield-Mask: 0x01) */ +#define PBR_MPR_DMA_MTR_Pos (2UL) /*!< MTR (Bit 2) */ +#define PBR_MPR_DMA_MTR_Msk (0x4UL) /*!< MTR (Bitfield-Mask: 0x01) */ +/* ========================================================= PACRA ========================================================= */ +#define PBR_PACRA_PWM0_TP_Pos (0UL) /*!< PWM0_TP (Bit 0) */ +#define PBR_PACRA_PWM0_TP_Msk (0x1UL) /*!< PWM0_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM0_WP_Pos (1UL) /*!< PWM0_WP (Bit 1) */ +#define PBR_PACRA_PWM0_WP_Msk (0x2UL) /*!< PWM0_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM0_SP_Pos (2UL) /*!< PWM0_SP (Bit 2) */ +#define PBR_PACRA_PWM0_SP_Msk (0x4UL) /*!< PWM0_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM1_TP_Pos (4UL) /*!< PWM1_TP (Bit 4) */ +#define PBR_PACRA_PWM1_TP_Msk (0x10UL) /*!< PWM1_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM1_WP_Pos (5UL) /*!< PWM1_WP (Bit 5) */ +#define PBR_PACRA_PWM1_WP_Msk (0x20UL) /*!< PWM1_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM1_SP_Pos (6UL) /*!< PWM1_SP (Bit 6) */ +#define PBR_PACRA_PWM1_SP_Msk (0x40UL) /*!< PWM1_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM2_TP_Pos (8UL) /*!< PWM2_TP (Bit 8) */ +#define PBR_PACRA_PWM2_TP_Msk (0x100UL) /*!< PWM2_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM2_WP_Pos (9UL) /*!< PWM2_WP (Bit 9) */ +#define PBR_PACRA_PWM2_WP_Msk (0x200UL) /*!< PWM2_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM2_SP_Pos (10UL) /*!< PWM2_SP (Bit 10) */ +#define PBR_PACRA_PWM2_SP_Msk (0x400UL) /*!< PWM2_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM3_TP_Pos (12UL) /*!< PWM3_TP (Bit 12) */ +#define PBR_PACRA_PWM3_TP_Msk (0x1000UL) /*!< PWM3_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM3_WP_Pos (13UL) /*!< PWM3_WP (Bit 13) */ +#define PBR_PACRA_PWM3_WP_Msk (0x2000UL) /*!< PWM3_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM3_SP_Pos (14UL) /*!< PWM3_SP (Bit 14) */ +#define PBR_PACRA_PWM3_SP_Msk (0x4000UL) /*!< PWM3_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM4_TP_Pos (16UL) /*!< PWM4_TP (Bit 16) */ +#define PBR_PACRA_PWM4_TP_Msk (0x10000UL) /*!< PWM4_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM4_WP_Pos (17UL) /*!< PWM4_WP (Bit 17) */ +#define PBR_PACRA_PWM4_WP_Msk (0x20000UL) /*!< PWM4_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM4_SP_Pos (18UL) /*!< PWM4_SP (Bit 18) */ +#define PBR_PACRA_PWM4_SP_Msk (0x40000UL) /*!< PWM4_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM5_TP_Pos (20UL) /*!< PWM5_TP (Bit 20) */ +#define PBR_PACRA_PWM5_TP_Msk (0x100000UL) /*!< PWM5_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM5_WP_Pos (21UL) /*!< PWM5_WP (Bit 21) */ +#define PBR_PACRA_PWM5_WP_Msk (0x200000UL) /*!< PWM5_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRA_PWM5_SP_Pos (22UL) /*!< PWM5_SP (Bit 22) */ +#define PBR_PACRA_PWM5_SP_Msk (0x400000UL) /*!< PWM5_SP (Bitfield-Mask: 0x01) */ +/* ========================================================= PACRB ========================================================= */ +#define PBR_PACRB_CRC_TP_Pos (0UL) /*!< CRC_TP (Bit 0) */ +#define PBR_PACRB_CRC_TP_Msk (0x1UL) /*!< CRC_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_CRC_WP_Pos (1UL) /*!< CRC_WP (Bit 1) */ +#define PBR_PACRB_CRC_WP_Msk (0x2UL) /*!< CRC_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_CRC_SP_Pos (2UL) /*!< CRC_SP (Bit 2) */ +#define PBR_PACRB_CRC_SP_Msk (0x4UL) /*!< CRC_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_GPIO_TP_Pos (4UL) /*!< GPIO_TP (Bit 4) */ +#define PBR_PACRB_GPIO_TP_Msk (0x10UL) /*!< GPIO_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_GPIO_WP_Pos (5UL) /*!< GPIO_WP (Bit 5) */ +#define PBR_PACRB_GPIO_WP_Msk (0x20UL) /*!< GPIO_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_GPIO_SP_Pos (6UL) /*!< GPIO_SP (Bit 6) */ +#define PBR_PACRB_GPIO_SP_Msk (0x40UL) /*!< GPIO_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_PDT0_TP_Pos (8UL) /*!< PDT0_TP (Bit 8) */ +#define PBR_PACRB_PDT0_TP_Msk (0x100UL) /*!< PDT0_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_PDT0_WP_Pos (9UL) /*!< PDT0_WP (Bit 9) */ +#define PBR_PACRB_PDT0_WP_Msk (0x200UL) /*!< PDT0_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_PDT0_SP_Pos (10UL) /*!< PDT0_SP (Bit 10) */ +#define PBR_PACRB_PDT0_SP_Msk (0x400UL) /*!< PDT0_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_PDT1_TP_Pos (12UL) /*!< PDT1_TP (Bit 12) */ +#define PBR_PACRB_PDT1_TP_Msk (0x1000UL) /*!< PDT1_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_PDT1_WP_Pos (13UL) /*!< PDT1_WP (Bit 13) */ +#define PBR_PACRB_PDT1_WP_Msk (0x2000UL) /*!< PDT1_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_PDT1_SP_Pos (14UL) /*!< PDT1_SP (Bit 14) */ +#define PBR_PACRB_PDT1_SP_Msk (0x4000UL) /*!< PDT1_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_MPU_TP_Pos (16UL) /*!< MPU_TP (Bit 16) */ +#define PBR_PACRB_MPU_TP_Msk (0x10000UL) /*!< MPU_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_MPU_WP_Pos (17UL) /*!< MPU_WP (Bit 17) */ +#define PBR_PACRB_MPU_WP_Msk (0x20000UL) /*!< MPU_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_MPU_SP_Pos (18UL) /*!< MPU_SP (Bit 18) */ +#define PBR_PACRB_MPU_SP_Msk (0x40000UL) /*!< MPU_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_EIM_TP_Pos (20UL) /*!< EIM_TP (Bit 20) */ +#define PBR_PACRB_EIM_TP_Msk (0x100000UL) /*!< EIM_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_EIM_WP_Pos (21UL) /*!< EIM_WP (Bit 21) */ +#define PBR_PACRB_EIM_WP_Msk (0x200000UL) /*!< EIM_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_EIM_SP_Pos (22UL) /*!< EIM_SP (Bit 22) */ +#define PBR_PACRB_EIM_SP_Msk (0x400000UL) /*!< EIM_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_SMU_TP_Pos (24UL) /*!< SMU_TP (Bit 24) */ +#define PBR_PACRB_SMU_TP_Msk (0x1000000UL) /*!< SMU_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_SMU_WP_Pos (25UL) /*!< SMU_WP (Bit 25) */ +#define PBR_PACRB_SMU_WP_Msk (0x2000000UL) /*!< SMU_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRB_SMU_SP_Pos (26UL) /*!< SMU_SP (Bit 26) */ +#define PBR_PACRB_SMU_SP_Msk (0x4000000UL) /*!< SMU_SP (Bitfield-Mask: 0x01) */ +/* ========================================================= PACRC ========================================================= */ +#define PBR_PACRC_CLK_TP_Pos (0UL) /*!< CLK_TP (Bit 0) */ +#define PBR_PACRC_CLK_TP_Msk (0x1UL) /*!< CLK_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_CLK_WP_Pos (1UL) /*!< CLK_WP (Bit 1) */ +#define PBR_PACRC_CLK_WP_Msk (0x2UL) /*!< CLK_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_CLK_SP_Pos (2UL) /*!< CLK_SP (Bit 2) */ +#define PBR_PACRC_CLK_SP_Msk (0x4UL) /*!< CLK_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_FLASH_TP_Pos (8UL) /*!< FLASH_TP (Bit 8) */ +#define PBR_PACRC_FLASH_TP_Msk (0x100UL) /*!< FLASH_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_FLASH_WP_Pos (9UL) /*!< FLASH_WP (Bit 9) */ +#define PBR_PACRC_FLASH_WP_Msk (0x200UL) /*!< FLASH_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_FLASH_SP_Pos (10UL) /*!< FLASH_SP (Bit 10) */ +#define PBR_PACRC_FLASH_SP_Msk (0x400UL) /*!< FLASH_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_ADC0_TP_Pos (12UL) /*!< ADC0_TP (Bit 12) */ +#define PBR_PACRC_ADC0_TP_Msk (0x1000UL) /*!< ADC0_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_ADC0_WP_Pos (13UL) /*!< ADC0_WP (Bit 13) */ +#define PBR_PACRC_ADC0_WP_Msk (0x2000UL) /*!< ADC0_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_ADC0_SP_Pos (14UL) /*!< ADC0_SP (Bit 14) */ +#define PBR_PACRC_ADC0_SP_Msk (0x4000UL) /*!< ADC0_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_ADC1_TP_Pos (16UL) /*!< ADC1_TP (Bit 16) */ +#define PBR_PACRC_ADC1_TP_Msk (0x10000UL) /*!< ADC1_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_ADC1_WP_Pos (17UL) /*!< ADC1_WP (Bit 17) */ +#define PBR_PACRC_ADC1_WP_Msk (0x20000UL) /*!< ADC1_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_ADC1_SP_Pos (18UL) /*!< ADC1_SP (Bit 18) */ +#define PBR_PACRC_ADC1_SP_Msk (0x40000UL) /*!< ADC1_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_ACMP_TP_Pos (20UL) /*!< ACMP_TP (Bit 20) */ +#define PBR_PACRC_ACMP_TP_Msk (0x100000UL) /*!< ACMP_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_ACMP_WP_Pos (21UL) /*!< ACMP_WP (Bit 21) */ +#define PBR_PACRC_ACMP_WP_Msk (0x200000UL) /*!< ACMP_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_ACMP_SP_Pos (22UL) /*!< ACMP_SP (Bit 22) */ +#define PBR_PACRC_ACMP_SP_Msk (0x400000UL) /*!< ACMP_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_CTU_TP_Pos (24UL) /*!< CTU_TP (Bit 24) */ +#define PBR_PACRC_CTU_TP_Msk (0x1000000UL) /*!< CTU_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_CTU_WP_Pos (25UL) /*!< CTU_WP (Bit 25) */ +#define PBR_PACRC_CTU_WP_Msk (0x2000000UL) /*!< CTU_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_CTU_SP_Pos (26UL) /*!< CTU_SP (Bit 26) */ +#define PBR_PACRC_CTU_SP_Msk (0x4000000UL) /*!< CTU_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_CAN0_TP_Pos (28UL) /*!< CAN0_TP (Bit 28) */ +#define PBR_PACRC_CAN0_TP_Msk (0x10000000UL) /*!< CAN0_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_CAN0_WP_Pos (29UL) /*!< CAN0_WP (Bit 29) */ +#define PBR_PACRC_CAN0_WP_Msk (0x20000000UL) /*!< CAN0_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRC_CAN0_SP_Pos (30UL) /*!< CAN0_SP (Bit 30) */ +#define PBR_PACRC_CAN0_SP_Msk (0x40000000UL) /*!< CAN0_SP (Bitfield-Mask: 0x01) */ +/* ========================================================= PACRD ========================================================= */ +#define PBR_PACRD_CAN1_TP_Pos (0UL) /*!< CAN1_TP (Bit 0) */ +#define PBR_PACRD_CAN1_TP_Msk (0x1UL) /*!< CAN1_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_CAN1_WP_Pos (1UL) /*!< CAN1_WP (Bit 1) */ +#define PBR_PACRD_CAN1_WP_Msk (0x2UL) /*!< CAN1_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_CAN1_SP_Pos (2UL) /*!< CAN1_SP (Bit 2) */ +#define PBR_PACRD_CAN1_SP_Msk (0x4UL) /*!< CAN1_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_CAN2_TP_Pos (4UL) /*!< CAN2_TP (Bit 4) */ +#define PBR_PACRD_CAN2_TP_Msk (0x10UL) /*!< CAN2_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_CAN2_WP_Pos (5UL) /*!< CAN2_WP (Bit 5) */ +#define PBR_PACRD_CAN2_WP_Msk (0x20UL) /*!< CAN2_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_CAN2_SP_Pos (6UL) /*!< CAN2_SP (Bit 6) */ +#define PBR_PACRD_CAN2_SP_Msk (0x40UL) /*!< CAN2_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_CAN3_TP_Pos (8UL) /*!< CAN3_TP (Bit 8) */ +#define PBR_PACRD_CAN3_TP_Msk (0x100UL) /*!< CAN3_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_CAN3_WP_Pos (9UL) /*!< CAN3_WP (Bit 9) */ +#define PBR_PACRD_CAN3_WP_Msk (0x200UL) /*!< CAN3_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_CAN3_SP_Pos (10UL) /*!< CAN3_SP (Bit 10) */ +#define PBR_PACRD_CAN3_SP_Msk (0x400UL) /*!< CAN3_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_SPM_TP_Pos (20UL) /*!< SPM_TP (Bit 20) */ +#define PBR_PACRD_SPM_TP_Msk (0x100000UL) /*!< SPM_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_SPM_WP_Pos (21UL) /*!< SPM_WP (Bit 21) */ +#define PBR_PACRD_SPM_WP_Msk (0x200000UL) /*!< SPM_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_SPM_SP_Pos (22UL) /*!< SPM_SP (Bit 22) */ +#define PBR_PACRD_SPM_SP_Msk (0x400000UL) /*!< SPM_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_RTC_TP_Pos (24UL) /*!< RTC_TP (Bit 24) */ +#define PBR_PACRD_RTC_TP_Msk (0x1000000UL) /*!< RTC_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_RTC_WP_Pos (25UL) /*!< RTC_WP (Bit 25) */ +#define PBR_PACRD_RTC_WP_Msk (0x2000000UL) /*!< RTC_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_RTC_SP_Pos (26UL) /*!< RTC_SP (Bit 26) */ +#define PBR_PACRD_RTC_SP_Msk (0x4000000UL) /*!< RTC_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_EIO_TP_Pos (28UL) /*!< EIO_TP (Bit 28) */ +#define PBR_PACRD_EIO_TP_Msk (0x10000000UL) /*!< EIO_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_EIO_WP_Pos (29UL) /*!< EIO_WP (Bit 29) */ +#define PBR_PACRD_EIO_WP_Msk (0x20000000UL) /*!< EIO_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRD_EIO_SP_Pos (30UL) /*!< EIO_SP (Bit 30) */ +#define PBR_PACRD_EIO_SP_Msk (0x40000000UL) /*!< EIO_SP (Bitfield-Mask: 0x01) */ +/* ========================================================= PACRE ========================================================= */ +#define PBR_PACRE_WDG_TP_Pos (0UL) /*!< WDG_TP (Bit 0) */ +#define PBR_PACRE_WDG_TP_Msk (0x1UL) /*!< WDG_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_WDG_WP_Pos (1UL) /*!< WDG_WP (Bit 1) */ +#define PBR_PACRE_WDG_WP_Msk (0x2UL) /*!< WDG_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_WDG_SP_Pos (2UL) /*!< WDG_SP (Bit 2) */ +#define PBR_PACRE_WDG_SP_Msk (0x4UL) /*!< WDG_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_EWDG_TP_Pos (4UL) /*!< EWDG_TP (Bit 4) */ +#define PBR_PACRE_EWDG_TP_Msk (0x10UL) /*!< EWDG_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_EWDG_WP_Pos (5UL) /*!< EWDG_WP (Bit 5) */ +#define PBR_PACRE_EWDG_WP_Msk (0x20UL) /*!< EWDG_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_EWDG_SP_Pos (6UL) /*!< EWDG_SP (Bit 6) */ +#define PBR_PACRE_EWDG_SP_Msk (0x40UL) /*!< EWDG_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_SPI0_TP_Pos (8UL) /*!< SPI0_TP (Bit 8) */ +#define PBR_PACRE_SPI0_TP_Msk (0x100UL) /*!< SPI0_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_SPI0_WP_Pos (9UL) /*!< SPI0_WP (Bit 9) */ +#define PBR_PACRE_SPI0_WP_Msk (0x200UL) /*!< SPI0_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_SPI0_SP_Pos (10UL) /*!< SPI0_SP (Bit 10) */ +#define PBR_PACRE_SPI0_SP_Msk (0x400UL) /*!< SPI0_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_SPI1_TP_Pos (12UL) /*!< SPI1_TP (Bit 12) */ +#define PBR_PACRE_SPI1_TP_Msk (0x1000UL) /*!< SPI1_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_SPI1_WP_Pos (13UL) /*!< SPI1_WP (Bit 13) */ +#define PBR_PACRE_SPI1_WP_Msk (0x2000UL) /*!< SPI1_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_SPI1_SP_Pos (14UL) /*!< SPI1_SP (Bit 14) */ +#define PBR_PACRE_SPI1_SP_Msk (0x4000UL) /*!< SPI1_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_SPI2_TP_Pos (16UL) /*!< SPI2_TP (Bit 16) */ +#define PBR_PACRE_SPI2_TP_Msk (0x10000UL) /*!< SPI2_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_SPI2_WP_Pos (17UL) /*!< SPI2_WP (Bit 17) */ +#define PBR_PACRE_SPI2_WP_Msk (0x20000UL) /*!< SPI2_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_SPI2_SP_Pos (18UL) /*!< SPI2_SP (Bit 18) */ +#define PBR_PACRE_SPI2_SP_Msk (0x40000UL) /*!< SPI2_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_I2C0_TP_Pos (24UL) /*!< I2C0_TP (Bit 24) */ +#define PBR_PACRE_I2C0_TP_Msk (0x1000000UL) /*!< I2C0_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_I2C0_WP_Pos (25UL) /*!< I2C0_WP (Bit 25) */ +#define PBR_PACRE_I2C0_WP_Msk (0x2000000UL) /*!< I2C0_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRE_I2C0_SP_Pos (26UL) /*!< I2C0_SP (Bit 26) */ +#define PBR_PACRE_I2C0_SP_Msk (0x4000000UL) /*!< I2C0_SP (Bitfield-Mask: 0x01) */ +/* ========================================================= PACRF ========================================================= */ +#define PBR_PACRF_TIMER_TP_Pos (0UL) /*!< TIMER_TP (Bit 0) */ +#define PBR_PACRF_TIMER_TP_Msk (0x1UL) /*!< TIMER_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_TIMER_WP_Pos (1UL) /*!< TIMER_WP (Bit 1) */ +#define PBR_PACRF_TIMER_WP_Msk (0x2UL) /*!< TIMER_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_TIMER_SP_Pos (2UL) /*!< TIMER_SP (Bit 2) */ +#define PBR_PACRF_TIMER_SP_Msk (0x4UL) /*!< TIMER_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_DMA_TP_Pos (4UL) /*!< DMA_TP (Bit 4) */ +#define PBR_PACRF_DMA_TP_Msk (0x10UL) /*!< DMA_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_DMA_WP_Pos (5UL) /*!< DMA_WP (Bit 5) */ +#define PBR_PACRF_DMA_WP_Msk (0x20UL) /*!< DMA_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_DMA_SP_Pos (6UL) /*!< DMA_SP (Bit 6) */ +#define PBR_PACRF_DMA_SP_Msk (0x40UL) /*!< DMA_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_UART0_TP_Pos (8UL) /*!< UART0_TP (Bit 8) */ +#define PBR_PACRF_UART0_TP_Msk (0x100UL) /*!< UART0_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_UART0_WP_Pos (9UL) /*!< UART0_WP (Bit 9) */ +#define PBR_PACRF_UART0_WP_Msk (0x200UL) /*!< UART0_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_UART0_SP_Pos (10UL) /*!< UART0_SP (Bit 10) */ +#define PBR_PACRF_UART0_SP_Msk (0x400UL) /*!< UART0_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_UART1_TP_Pos (12UL) /*!< UART1_TP (Bit 12) */ +#define PBR_PACRF_UART1_TP_Msk (0x1000UL) /*!< UART1_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_UART1_WP_Pos (13UL) /*!< UART1_WP (Bit 13) */ +#define PBR_PACRF_UART1_WP_Msk (0x2000UL) /*!< UART1_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_UART1_SP_Pos (14UL) /*!< UART1_SP (Bit 14) */ +#define PBR_PACRF_UART1_SP_Msk (0x4000UL) /*!< UART1_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_UART2_TP_Pos (16UL) /*!< UART2_TP (Bit 16) */ +#define PBR_PACRF_UART2_TP_Msk (0x10000UL) /*!< UART2_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_UART2_WP_Pos (17UL) /*!< UART2_WP (Bit 17) */ +#define PBR_PACRF_UART2_WP_Msk (0x20000UL) /*!< UART2_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_UART2_SP_Pos (18UL) /*!< UART2_SP (Bit 18) */ +#define PBR_PACRF_UART2_SP_Msk (0x40000UL) /*!< UART2_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_UART3_TP_Pos (20UL) /*!< UART3_TP (Bit 20) */ +#define PBR_PACRF_UART3_TP_Msk (0x100000UL) /*!< UART3_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_UART3_WP_Pos (21UL) /*!< UART3_WP (Bit 21) */ +#define PBR_PACRF_UART3_WP_Msk (0x200000UL) /*!< UART3_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRF_UART3_SP_Pos (22UL) /*!< UART3_SP (Bit 22) */ +#define PBR_PACRF_UART3_SP_Msk (0x400000UL) /*!< UART3_SP (Bitfield-Mask: 0x01) */ +/* ========================================================= PACRG ========================================================= */ +#define PBR_PACRG_PCT_TP_Pos (0UL) /*!< PCT_TP (Bit 0) */ +#define PBR_PACRG_PCT_TP_Msk (0x1UL) /*!< PCT_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRG_PCT_WP_Pos (1UL) /*!< PCT_WP (Bit 1) */ +#define PBR_PACRG_PCT_WP_Msk (0x2UL) /*!< PCT_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRG_PCT_SP_Pos (2UL) /*!< PCT_SP (Bit 2) */ +#define PBR_PACRG_PCT_SP_Msk (0x4UL) /*!< PCT_SP (Bitfield-Mask: 0x01) */ +#define PBR_PACRG_CMU_TP_Pos (4UL) /*!< CMU_TP (Bit 4) */ +#define PBR_PACRG_CMU_TP_Msk (0x10UL) /*!< CMU_TP (Bitfield-Mask: 0x01) */ +#define PBR_PACRG_CMU_WP_Pos (5UL) /*!< CMU_WP (Bit 5) */ +#define PBR_PACRG_CMU_WP_Msk (0x20UL) /*!< CMU_WP (Bitfield-Mask: 0x01) */ +#define PBR_PACRG_CMU_SP_Pos (6UL) /*!< CMU_SP (Bit 6) */ +#define PBR_PACRG_CMU_SP_Msk (0x40UL) /*!< CMU_SP (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ SPM ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== PWR_MGR_CFG0 ====================================================== */ +#define SPM_PWR_MGR_CFG0_PWR_EN_Pos (0UL) /*!< PWR_EN (Bit 0) */ +#define SPM_PWR_MGR_CFG0_PWR_EN_Msk (0x1UL) /*!< PWR_EN (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG0_AWIC_EN_Pos (1UL) /*!< AWIC_EN (Bit 1) */ +#define SPM_PWR_MGR_CFG0_AWIC_EN_Msk (0x2UL) /*!< AWIC_EN (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG0_ACK_TIMEOUT_ACTION_Pos (4UL) /*!< ACK_TIMEOUT_ACTION (Bit 4) */ +#define SPM_PWR_MGR_CFG0_ACK_TIMEOUT_ACTION_Msk (0x10UL) /*!< ACK_TIMEOUT_ACTION (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG0_POWER_MODE_Pos (8UL) /*!< POWER_MODE (Bit 8) */ +#define SPM_PWR_MGR_CFG0_POWER_MODE_Msk (0x700UL) /*!< POWER_MODE (Bitfield-Mask: 0x07) */ +#define SPM_PWR_MGR_CFG0_RESET_MASK_Pos (16UL) /*!< RESET_MASK (Bit 16) */ +#define SPM_PWR_MGR_CFG0_RESET_MASK_Msk (0x10000UL) /*!< RESET_MASK (Bitfield-Mask: 0x01) */ +/* ===================================================== PWR_MGR_CFG1 ====================================================== */ +#define SPM_PWR_MGR_CFG1_LVR_THRESHOLD_Pos (0UL) /*!< LVR_THRESHOLD (Bit 0) */ +#define SPM_PWR_MGR_CFG1_LVR_THRESHOLD_Msk (0x1UL) /*!< LVR_THRESHOLD (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG1_LVD_THRESHOLD_Pos (1UL) /*!< LVD_THRESHOLD (Bit 1) */ +#define SPM_PWR_MGR_CFG1_LVD_THRESHOLD_Msk (0x2UL) /*!< LVD_THRESHOLD (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG1_HSI_EN_VLPS_Pos (8UL) /*!< HSI_EN_VLPS (Bit 8) */ +#define SPM_PWR_MGR_CFG1_HSI_EN_VLPS_Msk (0x100UL) /*!< HSI_EN_VLPS (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG1_HSI_EN_NORMAL_Pos (9UL) /*!< HSI_EN_NORMAL (Bit 9) */ +#define SPM_PWR_MGR_CFG1_HSI_EN_NORMAL_Msk (0x200UL) /*!< HSI_EN_NORMAL (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG1_VHSI_EN_Pos (10UL) /*!< VHSI_EN (Bit 10) */ +#define SPM_PWR_MGR_CFG1_VHSI_EN_Msk (0x400UL) /*!< VHSI_EN (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG1_SPLL_RDY_Pos (23UL) /*!< SPLL_RDY (Bit 23) */ +#define SPM_PWR_MGR_CFG1_SPLL_RDY_Msk (0x800000UL) /*!< SPLL_RDY (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG1_HSI_RDY_Pos (24UL) /*!< HSI_RDY (Bit 24) */ +#define SPM_PWR_MGR_CFG1_HSI_RDY_Msk (0x1000000UL) /*!< HSI_RDY (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG1_VHSI_RDY_Pos (25UL) /*!< VHSI_RDY (Bit 25) */ +#define SPM_PWR_MGR_CFG1_VHSI_RDY_Msk (0x2000000UL) /*!< VHSI_RDY (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG1_XOSC_RDY_Pos (26UL) /*!< XOSC_RDY (Bit 26) */ +#define SPM_PWR_MGR_CFG1_XOSC_RDY_Msk (0x4000000UL) /*!< XOSC_RDY (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG1_SPLL_EN_Pos (27UL) /*!< SPLL_EN (Bit 27) */ +#define SPM_PWR_MGR_CFG1_SPLL_EN_Msk (0x8000000UL) /*!< SPLL_EN (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Pos (28UL) /*!< XOSC_HSEBYP (Bit 28) */ +#define SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Msk (0x10000000UL) /*!< XOSC_HSEBYP (Bitfield-Mask: 0x01) */ +#define SPM_PWR_MGR_CFG1_XOSC_HSEEN_Pos (29UL) /*!< XOSC_HSEEN (Bit 29) */ +#define SPM_PWR_MGR_CFG1_XOSC_HSEEN_Msk (0x20000000UL) /*!< XOSC_HSEEN (Bitfield-Mask: 0x01) */ +/* ================================================ PERIPH_SLEEP_ACK_STATUS ================================================ */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_I2C0_Pos (0UL) /*!< I2C0 (Bit 0) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_I2C0_Msk (0x1UL) /*!< I2C0 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI0_Pos (2UL) /*!< SPI0 (Bit 2) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI0_Msk (0x4UL) /*!< SPI0 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI1_Pos (3UL) /*!< SPI1 (Bit 3) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI1_Msk (0x8UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI2_Pos (4UL) /*!< SPI2 (Bit 4) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI2_Msk (0x10UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN0_Pos (5UL) /*!< CAN0 (Bit 5) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN0_Msk (0x20UL) /*!< CAN0 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN1_Pos (6UL) /*!< CAN1 (Bit 6) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN1_Msk (0x40UL) /*!< CAN1 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN2_Pos (7UL) /*!< CAN2 (Bit 7) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN2_Msk (0x80UL) /*!< CAN2 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN3_Pos (8UL) /*!< CAN3 (Bit 8) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN3_Msk (0x100UL) /*!< CAN3 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_UART0_Pos (11UL) /*!< UART0 (Bit 11) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_UART0_Msk (0x800UL) /*!< UART0 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_UART1_Pos (12UL) /*!< UART1 (Bit 12) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_UART1_Msk (0x1000UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_UART2_Pos (13UL) /*!< UART2 (Bit 13) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_UART2_Msk (0x2000UL) /*!< UART2 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_UART3_Pos (14UL) /*!< UART3 (Bit 14) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_UART3_Msk (0x4000UL) /*!< UART3 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_DMA0_Pos (17UL) /*!< DMA0 (Bit 17) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_DMA0_Msk (0x20000UL) /*!< DMA0 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_EIO_Pos (18UL) /*!< EIO (Bit 18) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_EIO_Msk (0x40000UL) /*!< EIO (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_FLASH_Pos (19UL) /*!< FLASH (Bit 19) */ +#define SPM_PERIPH_SLEEP_ACK_STATUS_FLASH_Msk (0x80000UL) /*!< FLASH (Bitfield-Mask: 0x01) */ +/* ================================================== PERIPH_SLEEP_ACK_EN ================================================== */ +#define SPM_PERIPH_SLEEP_ACK_EN_I2C0_Pos (0UL) /*!< I2C0 (Bit 0) */ +#define SPM_PERIPH_SLEEP_ACK_EN_I2C0_Msk (0x1UL) /*!< I2C0 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_SPI0_Pos (2UL) /*!< SPI0 (Bit 2) */ +#define SPM_PERIPH_SLEEP_ACK_EN_SPI0_Msk (0x4UL) /*!< SPI0 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_SPI1_Pos (3UL) /*!< SPI1 (Bit 3) */ +#define SPM_PERIPH_SLEEP_ACK_EN_SPI1_Msk (0x8UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_SPI2_Pos (4UL) /*!< SPI2 (Bit 4) */ +#define SPM_PERIPH_SLEEP_ACK_EN_SPI2_Msk (0x10UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_CAN0_Pos (5UL) /*!< CAN0 (Bit 5) */ +#define SPM_PERIPH_SLEEP_ACK_EN_CAN0_Msk (0x20UL) /*!< CAN0 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_CAN1_Pos (6UL) /*!< CAN1 (Bit 6) */ +#define SPM_PERIPH_SLEEP_ACK_EN_CAN1_Msk (0x40UL) /*!< CAN1 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_CAN2_Pos (7UL) /*!< CAN2 (Bit 7) */ +#define SPM_PERIPH_SLEEP_ACK_EN_CAN2_Msk (0x80UL) /*!< CAN2 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_CAN3_Pos (8UL) /*!< CAN3 (Bit 8) */ +#define SPM_PERIPH_SLEEP_ACK_EN_CAN3_Msk (0x100UL) /*!< CAN3 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_UART0_Pos (11UL) /*!< UART0 (Bit 11) */ +#define SPM_PERIPH_SLEEP_ACK_EN_UART0_Msk (0x800UL) /*!< UART0 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_UART1_Pos (12UL) /*!< UART1 (Bit 12) */ +#define SPM_PERIPH_SLEEP_ACK_EN_UART1_Msk (0x1000UL) /*!< UART1 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_UART2_Pos (13UL) /*!< UART2 (Bit 13) */ +#define SPM_PERIPH_SLEEP_ACK_EN_UART2_Msk (0x2000UL) /*!< UART2 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_UART3_Pos (14UL) /*!< UART3 (Bit 14) */ +#define SPM_PERIPH_SLEEP_ACK_EN_UART3_Msk (0x4000UL) /*!< UART3 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_DMA0_Pos (17UL) /*!< DMA0 (Bit 17) */ +#define SPM_PERIPH_SLEEP_ACK_EN_DMA0_Msk (0x20000UL) /*!< DMA0 (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_EIO_Pos (18UL) /*!< EIO (Bit 18) */ +#define SPM_PERIPH_SLEEP_ACK_EN_EIO_Msk (0x40000UL) /*!< EIO (Bitfield-Mask: 0x01) */ +#define SPM_PERIPH_SLEEP_ACK_EN_FLASH_Pos (19UL) /*!< FLASH (Bit 19) */ +#define SPM_PERIPH_SLEEP_ACK_EN_FLASH_Msk (0x80000UL) /*!< FLASH (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ +#define SPM_STATUS_CURR_POWER_MODE_Pos (0UL) /*!< CURR_POWER_MODE (Bit 0) */ +#define SPM_STATUS_CURR_POWER_MODE_Msk (0x7UL) /*!< CURR_POWER_MODE (Bitfield-Mask: 0x07) */ +#define SPM_STATUS_ACK_TIMEOUT_FLAG_Pos (4UL) /*!< ACK_TIMEOUT_FLAG (Bit 4) */ +#define SPM_STATUS_ACK_TIMEOUT_FLAG_Msk (0x10UL) /*!< ACK_TIMEOUT_FLAG (Bitfield-Mask: 0x01) */ +/* ======================================================= STB_WP_EN ======================================================= */ +#define SPM_STB_WP_EN_PA12_Pos (0UL) /*!< PA12 (Bit 0) */ +#define SPM_STB_WP_EN_PA12_Msk (0x3UL) /*!< PA12 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PB8_Pos (2UL) /*!< PB8 (Bit 2) */ +#define SPM_STB_WP_EN_PB8_Msk (0xcUL) /*!< PB8 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PB1_Pos (4UL) /*!< PB1 (Bit 4) */ +#define SPM_STB_WP_EN_PB1_Msk (0x30UL) /*!< PB1 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PB12_Pos (6UL) /*!< PB12 (Bit 6) */ +#define SPM_STB_WP_EN_PB12_Msk (0xc0UL) /*!< PB12 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PD3_Pos (8UL) /*!< PD3 (Bit 8) */ +#define SPM_STB_WP_EN_PD3_Msk (0x300UL) /*!< PD3 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PC2_Pos (10UL) /*!< PC2 (Bit 10) */ +#define SPM_STB_WP_EN_PC2_Msk (0xc00UL) /*!< PC2 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PC3_Pos (12UL) /*!< PC3 (Bit 12) */ +#define SPM_STB_WP_EN_PC3_Msk (0x3000UL) /*!< PC3 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PC6_Pos (14UL) /*!< PC6 (Bit 14) */ +#define SPM_STB_WP_EN_PC6_Msk (0xc000UL) /*!< PC6 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PC7_Pos (16UL) /*!< PC7 (Bit 16) */ +#define SPM_STB_WP_EN_PC7_Msk (0x30000UL) /*!< PC7 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PC16_Pos (18UL) /*!< PC16 (Bit 18) */ +#define SPM_STB_WP_EN_PC16_Msk (0xc0000UL) /*!< PC16 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PC17_Pos (20UL) /*!< PC17 (Bit 20) */ +#define SPM_STB_WP_EN_PC17_Msk (0x300000UL) /*!< PC17 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PD6_Pos (22UL) /*!< PD6 (Bit 22) */ +#define SPM_STB_WP_EN_PD6_Msk (0xc00000UL) /*!< PD6 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PD7_Pos (24UL) /*!< PD7 (Bit 24) */ +#define SPM_STB_WP_EN_PD7_Msk (0x3000000UL) /*!< PD7 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PE4_Pos (26UL) /*!< PE4 (Bit 26) */ +#define SPM_STB_WP_EN_PE4_Msk (0xc000000UL) /*!< PE4 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_PE5_Pos (28UL) /*!< PE5 (Bit 28) */ +#define SPM_STB_WP_EN_PE5_Msk (0x30000000UL) /*!< PE5 (Bitfield-Mask: 0x03) */ +#define SPM_STB_WP_EN_RTC_Pos (30UL) /*!< RTC (Bit 30) */ +#define SPM_STB_WP_EN_RTC_Msk (0xc0000000UL) /*!< RTC (Bitfield-Mask: 0x03) */ +/* ===================================================== STB_WP_STATUS ===================================================== */ +#define SPM_STB_WP_STATUS_PA12_Pos (0UL) /*!< PA12 (Bit 0) */ +#define SPM_STB_WP_STATUS_PA12_Msk (0x1UL) /*!< PA12 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PB0_Pos (1UL) /*!< PB0 (Bit 1) */ +#define SPM_STB_WP_STATUS_PB0_Msk (0x2UL) /*!< PB0 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PB1_Pos (2UL) /*!< PB1 (Bit 2) */ +#define SPM_STB_WP_STATUS_PB1_Msk (0x4UL) /*!< PB1 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PB12_Pos (3UL) /*!< PB12 (Bit 3) */ +#define SPM_STB_WP_STATUS_PB12_Msk (0x8UL) /*!< PB12 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PD3_Pos (4UL) /*!< PD3 (Bit 4) */ +#define SPM_STB_WP_STATUS_PD3_Msk (0x10UL) /*!< PD3 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PC2_Pos (5UL) /*!< PC2 (Bit 5) */ +#define SPM_STB_WP_STATUS_PC2_Msk (0x20UL) /*!< PC2 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PC3_Pos (6UL) /*!< PC3 (Bit 6) */ +#define SPM_STB_WP_STATUS_PC3_Msk (0x40UL) /*!< PC3 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PC6_Pos (7UL) /*!< PC6 (Bit 7) */ +#define SPM_STB_WP_STATUS_PC6_Msk (0x80UL) /*!< PC6 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PC7_Pos (8UL) /*!< PC7 (Bit 8) */ +#define SPM_STB_WP_STATUS_PC7_Msk (0x100UL) /*!< PC7 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PC16_Pos (9UL) /*!< PC16 (Bit 9) */ +#define SPM_STB_WP_STATUS_PC16_Msk (0x200UL) /*!< PC16 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PC17_Pos (10UL) /*!< PC17 (Bit 10) */ +#define SPM_STB_WP_STATUS_PC17_Msk (0x400UL) /*!< PC17 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PD6_Pos (11UL) /*!< PD6 (Bit 11) */ +#define SPM_STB_WP_STATUS_PD6_Msk (0x800UL) /*!< PD6 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PD7_Pos (12UL) /*!< PD7 (Bit 12) */ +#define SPM_STB_WP_STATUS_PD7_Msk (0x1000UL) /*!< PD7 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PE4_Pos (13UL) /*!< PE4 (Bit 13) */ +#define SPM_STB_WP_STATUS_PE4_Msk (0x2000UL) /*!< PE4 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_PE5_Pos (14UL) /*!< PE5 (Bit 14) */ +#define SPM_STB_WP_STATUS_PE5_Msk (0x4000UL) /*!< PE5 (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_RTC_Pos (15UL) /*!< RTC (Bit 15) */ +#define SPM_STB_WP_STATUS_RTC_Msk (0x8000UL) /*!< RTC (Bitfield-Mask: 0x01) */ +#define SPM_STB_WP_STATUS_STB_WP_FLG_Pos (16UL) /*!< STB_WP_FLG (Bit 16) */ +#define SPM_STB_WP_STATUS_STB_WP_FLG_Msk (0x10000UL) /*!< STB_WP_FLG (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PODR ========================================================== */ +#define GPIO_PODR_PODR0_Pos (0UL) /*!< PODR0 (Bit 0) */ +#define GPIO_PODR_PODR0_Msk (0x1UL) /*!< PODR0 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR1_Pos (1UL) /*!< PODR1 (Bit 1) */ +#define GPIO_PODR_PODR1_Msk (0x2UL) /*!< PODR1 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR2_Pos (2UL) /*!< PODR2 (Bit 2) */ +#define GPIO_PODR_PODR2_Msk (0x4UL) /*!< PODR2 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR3_Pos (3UL) /*!< PODR3 (Bit 3) */ +#define GPIO_PODR_PODR3_Msk (0x8UL) /*!< PODR3 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR4_Pos (4UL) /*!< PODR4 (Bit 4) */ +#define GPIO_PODR_PODR4_Msk (0x10UL) /*!< PODR4 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR5_Pos (5UL) /*!< PODR5 (Bit 5) */ +#define GPIO_PODR_PODR5_Msk (0x20UL) /*!< PODR5 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR6_Pos (6UL) /*!< PODR6 (Bit 6) */ +#define GPIO_PODR_PODR6_Msk (0x40UL) /*!< PODR6 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR7_Pos (7UL) /*!< PODR7 (Bit 7) */ +#define GPIO_PODR_PODR7_Msk (0x80UL) /*!< PODR7 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR8_Pos (8UL) /*!< PODR8 (Bit 8) */ +#define GPIO_PODR_PODR8_Msk (0x100UL) /*!< PODR8 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR9_Pos (9UL) /*!< PODR9 (Bit 9) */ +#define GPIO_PODR_PODR9_Msk (0x200UL) /*!< PODR9 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR10_Pos (10UL) /*!< PODR10 (Bit 10) */ +#define GPIO_PODR_PODR10_Msk (0x400UL) /*!< PODR10 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR11_Pos (11UL) /*!< PODR11 (Bit 11) */ +#define GPIO_PODR_PODR11_Msk (0x800UL) /*!< PODR11 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR12_Pos (12UL) /*!< PODR12 (Bit 12) */ +#define GPIO_PODR_PODR12_Msk (0x1000UL) /*!< PODR12 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR13_Pos (13UL) /*!< PODR13 (Bit 13) */ +#define GPIO_PODR_PODR13_Msk (0x2000UL) /*!< PODR13 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR14_Pos (14UL) /*!< PODR14 (Bit 14) */ +#define GPIO_PODR_PODR14_Msk (0x4000UL) /*!< PODR14 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR15_Pos (15UL) /*!< PODR15 (Bit 15) */ +#define GPIO_PODR_PODR15_Msk (0x8000UL) /*!< PODR15 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR16_Pos (16UL) /*!< PODR16 (Bit 16) */ +#define GPIO_PODR_PODR16_Msk (0x10000UL) /*!< PODR16 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR17_Pos (17UL) /*!< PODR17 (Bit 17) */ +#define GPIO_PODR_PODR17_Msk (0x20000UL) /*!< PODR17 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR18_Pos (18UL) /*!< PODR18 (Bit 18) */ +#define GPIO_PODR_PODR18_Msk (0x40000UL) /*!< PODR18 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR19_Pos (19UL) /*!< PODR19 (Bit 19) */ +#define GPIO_PODR_PODR19_Msk (0x80000UL) /*!< PODR19 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR20_Pos (20UL) /*!< PODR20 (Bit 20) */ +#define GPIO_PODR_PODR20_Msk (0x100000UL) /*!< PODR20 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR21_Pos (21UL) /*!< PODR21 (Bit 21) */ +#define GPIO_PODR_PODR21_Msk (0x200000UL) /*!< PODR21 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR22_Pos (22UL) /*!< PODR22 (Bit 22) */ +#define GPIO_PODR_PODR22_Msk (0x400000UL) /*!< PODR22 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR23_Pos (23UL) /*!< PODR23 (Bit 23) */ +#define GPIO_PODR_PODR23_Msk (0x800000UL) /*!< PODR23 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR24_Pos (24UL) /*!< PODR24 (Bit 24) */ +#define GPIO_PODR_PODR24_Msk (0x1000000UL) /*!< PODR24 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR25_Pos (25UL) /*!< PODR25 (Bit 25) */ +#define GPIO_PODR_PODR25_Msk (0x2000000UL) /*!< PODR25 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR26_Pos (26UL) /*!< PODR26 (Bit 26) */ +#define GPIO_PODR_PODR26_Msk (0x4000000UL) /*!< PODR26 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR27_Pos (27UL) /*!< PODR27 (Bit 27) */ +#define GPIO_PODR_PODR27_Msk (0x8000000UL) /*!< PODR27 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR28_Pos (28UL) /*!< PODR28 (Bit 28) */ +#define GPIO_PODR_PODR28_Msk (0x10000000UL) /*!< PODR28 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR29_Pos (29UL) /*!< PODR29 (Bit 29) */ +#define GPIO_PODR_PODR29_Msk (0x20000000UL) /*!< PODR29 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR30_Pos (30UL) /*!< PODR30 (Bit 30) */ +#define GPIO_PODR_PODR30_Msk (0x40000000UL) /*!< PODR30 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_PODR31_Pos (31UL) /*!< PODR31 (Bit 31) */ +#define GPIO_PODR_PODR31_Msk (0x80000000UL) /*!< PODR31 (Bitfield-Mask: 0x01) */ +#define GPIO_PODR_Pos(x) ((uint32_t)x) /*!< PODRx (Bit x) */ +#define GPIO_PODR_Msk(x) (0x01UL<_DRV_GetVersionInfo() function. +*/ +typedef struct +{ + uint16_t moduleID; /**< @brief module ID */ + uint8_t majorVersion; /**< @brief module software major version */ + uint8_t minorVersion; /**< @brief module software minor version */ + uint8_t patchVersion; /**< @brief module software patch version */ +} Drv_VersionInfo_Type; + +#ifdef __cplusplus +} +#endif + +#endif /* AC7840X_H */ + + +/** @} */ /* End of group AC7840x */ + +/** @} */ /* End of group AutoChips */ diff --git a/inc/ac7840x_features.h b/inc/ac7840x_features.h new file mode 100644 index 0000000..ba12360 --- /dev/null +++ b/inc/ac7840x_features.h @@ -0,0 +1,1236 @@ +/* Copyright Statement: + * + * This software/firmware and related documentation ("AutoChips Software") are + * protected under relevant copyright laws. The information contained herein is + * confidential and proprietary to AutoChips Inc. and/or its licensors. Without + * the prior written permission of AutoChips inc. and/or its licensors, any + * reproduction, modification, use or disclosure of AutoChips Software, and + * information contained herein, in whole or in part, shall be strictly + * prohibited. + * + * AutoChips Inc. (C) 2021. All rights reserved. + * + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE") + * RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER + * ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL + * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR + * NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH + * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, + * INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES + * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. + * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO + * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS + * SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE + * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S + * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE + * RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE + * AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE + * CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE. + */ + +/*! + * @file ac7840x_features.h + * + * @brief This file provides chip specific module features. + * + */ + +#ifndef AC7840X_FEATURES_H +#define AC7840X_FEATURES_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* =========================================================================================================================== */ +/* ================ MCM ================ */ +/* =========================================================================================================================== */ +/*! + * @brief Core interrupt type. + */ +typedef enum +{ + FIOC_IRQ = MCM_MISCR_FIOC_Msk, /*!< FPU invalid operation cumulative exception. */ + FDZC_IRQ = MCM_MISCR_FDZC_Msk, /*!< FPU division by zero cumulative exception. */ + FOFC_IRQ = MCM_MISCR_FOFC_Msk, /*!< FPU overflow cumulative exception. */ + FUFC_IRQ = MCM_MISCR_FUFC_Msk, /*!< FPU underflow cumulative exception. */ + FIXC_IRQ = MCM_MISCR_FIXC_Msk, /*!< FPU inexact cumulative exception. */ + FIDC_IRQ = MCM_MISCR_FIDC_Msk, /*!< FPU input denormal cumulative exception. */ +} Core_InterruptType; + +/*! + * @brief Bist type. + */ +typedef enum +{ + BIST_ABIST, /*!< Analog BIST. */ + BIST_MBIST /*!< Memory BIST. */ +} Core_BistType; + +/*! + * @brief Bist execute status type. + */ +typedef enum +{ + BIST_NORUN = 0x00U, /*!< BIST is not run. */ + BIST_OK = 0x01U, /*!< BIST is ok. */ + BIST_BUSY = 0x02U, /*!< BIST is busy. */ + BIST_ERROR = 0x03U, /*!< BIST is error. */ +} Core_BistStatusType; + +/* =========================================================================================================================== */ +/* ================ CKGEN ================ */ +/* =========================================================================================================================== */ +/*!< HSI clock frequency(8MHz) */ +#define CKGEN_HSI_FREQ (8000000UL) + +/*!< VHSI clock frequency(48MHz) */ +#define CKGEN_VHSI_FREQ (48000000UL) + +/*!< Auto select HSI clock for SPLL when enable XOSC is fail */ +#define CKGEN_AUTO_SEL_HSI (0UL) + +/*!< Auto change SPLL reference clock to HSI clock when XOSC is detected loss(just for XOSC=8MHz); + Auto change system clock to VHSI clock when SPLL is detected unlock; + This function needs to enable the corresponding interrupt and disable trigger reset */ +#define CKGEN_AUTO_CHANGE_CLK (0UL) + +/*!< Auto test clock */ +#define CKGEN_AUTO_TEST_CLK (1UL) + +/*!< Peripheral clock base number */ +#define CKGEN_PERI_CLK_BASE (256UL) + +/*!< Clock out mux2 base number */ +#define CKGEN_CLK_OUT_MUX2_BASE (8UL) + +/*!< Advanced optimization */ +#define ADVANCED_OPTIMIZATION_SET (((READ_MEM32(0x201824UL) & 0xFFUL) == 0x08UL) || ((READ_MEM32(0x201824UL) & 0xFFUL) == 0x09UL)) + +/*! + * @brief Define the enum of the clock names for setting or getting clock frequency. + */ +typedef enum { + /* Main clocks */ + CORE_CLK = 0U, /*!< Core/System clock */ + BUS_CLK = 1U, /*!< Bus clock */ + CLKOUT_CLK = 2U, /*!< CLKOUT clock */ + + /* Other internal clocks used by peripherals. */ + HSI_CLK = 3U, /*!< HSI clock */ + VHSI_CLK = 4U, /*!< VHSI clock */ + HSE_CLK = 5U, /*!< HSE clock */ + SPLL_CLK = 6U, /*!< SPLL clock */ + RTC_CLKIN_CLK = 7U, /*!< RTC_CLKIN clock */ + CKGEN_CLKOUT_CLK = 8U, /*!< CLK_OUT clock from mux1 */ + + HSEDIV1_CLK = 9U, /*!< HSEDIV1 functional clock */ + HSIDIV1_CLK = 10U, /*!< HSIDIV1 functional clock */ + VHSIDIV1_CLK = 11U, /*!< VHSIDIV1 functional clock */ + SPLLDIV1_CLK = 12U, /*!< SPLLDIV1 functional clock */ + + HSEDIV2_CLK = 13U, /*!< HSEDIV2 functional clock */ + HSIDIV2_CLK = 14U, /*!< HSIDIV2 functional clock */ + VHSIDIV2_CLK = 15U, /*!< VHSIDIV2 functional clock */ + SPLLDIV2_CLK = 16U, /*!< SPLLDIV2 functional clock */ + + CKGEN_END_OF_CLOCKS = 17U, /*!< End of ckgen clocks */ + + TCLK0_CLK = 18U, /*!< PWM external clock: TCLK0 */ + TCLK1_CLK = 19U, /*!< PWM external clock: TCLK1 */ + TCLK2_CLK = 20U, /*!< PWM external clock: TCLK2 */ + TCLK3_CLK = 21U, /*!< PWM external clock: TCLK3 */ + + PWM0_EXT_CLK = 22U, /*!< PWM0 external clock source */ + PWM1_EXT_CLK = 23U, /*!< PWM1 external clock source */ + PWM2_EXT_CLK = 24U, /*!< PWM2 external clock source */ + PWM3_EXT_CLK = 25U, /*!< PWM3 external clock source */ + PWM4_EXT_CLK = 26U, /*!< PWM4 external clock source */ + PWM5_EXT_CLK = 27U, /*!< PWM5 external clock source */ + + /* CLK OUT */ + CLKOUTSEL = 28U, /*!< CLKOUT Select fo pin */ + + /* RTC and LSI */ + RTC_CLK = 29U, /*!< RTCCLK clock */ + LSI_CLK = 30U, /*!< LSI clock */ + LSI_1K_CLK = 31U, /*!< LSI 1KHz clock */ + LSI_32K_CLK = 32U, /*!< LSI 32KHz clock */ + LSI_128K_CLK = 33U, /*!< LSI 128KHz clock */ + + SIM_END_OF_CLOCKS = 34U, /*!< End of sim clocks */ + + /* Peripheral clock mux0 */ + I2C0_CLK = CKGEN_PERI_CLK_BASE + 0U, /*!< I2C0 clock source */ + TIMER_CLK = CKGEN_PERI_CLK_BASE + 2U, /*!< TIMER clock source */ + SPI0_CLK = CKGEN_PERI_CLK_BASE + 3U, /*!< SPI0 clock source */ + SPI1_CLK = CKGEN_PERI_CLK_BASE + 4U, /*!< SPI1 clock source */ + SPI2_CLK = CKGEN_PERI_CLK_BASE + 5U, /*!< SPI2 clock source */ + ADC0_CLK = CKGEN_PERI_CLK_BASE + 6U, /*!< ADC0 clock source */ + ADC1_CLK = CKGEN_PERI_CLK_BASE + 7U, /*!< ADC1 clock source */ + + /* Peripheral clock mux1 */ + CAN0_CLK = CKGEN_PERI_CLK_BASE + 8U, /*!< CAN0 clock source */ + CAN1_CLK = CKGEN_PERI_CLK_BASE + 9U, /*!< CAN1 clock source */ + CAN2_CLK = CKGEN_PERI_CLK_BASE + 10U, /*!< CAN2 clock source */ + CAN3_CLK = CKGEN_PERI_CLK_BASE + 11U, /*!< CAN3 clock source */ + PCT_CLK = CKGEN_PERI_CLK_BASE + 14U, /*!< PCT clock source */ + EIO_CLK = CKGEN_PERI_CLK_BASE + 15U, /*!< EIO clock source */ + + /* Peripheral clock mux2 */ + UART0_CLK = CKGEN_PERI_CLK_BASE + 16U, /*!< UART0 clock source */ + UART1_CLK = CKGEN_PERI_CLK_BASE + 17U, /*!< UART1 clock source */ + UART2_CLK = CKGEN_PERI_CLK_BASE + 18U, /*!< UART2 clock source */ + UART3_CLK = CKGEN_PERI_CLK_BASE + 19U, /*!< UART3 clock source */ + + /* Peripheral clock mux3 */ + PWM0_CLK = CKGEN_PERI_CLK_BASE + 24U, /*!< PWM0 clock source */ + PWM1_CLK = CKGEN_PERI_CLK_BASE + 25U, /*!< PWM1 clock source */ + PWM2_CLK = CKGEN_PERI_CLK_BASE + 26U, /*!< PWM2 clock source */ + PWM3_CLK = CKGEN_PERI_CLK_BASE + 27U, /*!< PWM3 clock source */ + PWM4_CLK = CKGEN_PERI_CLK_BASE + 28U, /*!< PWM4 clock source */ + PWM5_CLK = CKGEN_PERI_CLK_BASE + 29U, /*!< PWM5 clock source */ + + PCC_END_OF_CLOCKS = CKGEN_PERI_CLK_BASE + 30U, /*!< End of pcc clocks */ + PERI_CLK_OFF = CKGEN_PERI_CLK_BASE + 255U, /*!< peripheral clock off */ + + CLOCK_NAME_COUNT = CKGEN_PERI_CLK_BASE + 84U, /*!< The total number of entries */ +} clock_names_t; + +/*! + * @brief Define the enum of the module for setting module bus clock. + */ +typedef enum +{ + /* PERI_CLK_EN0 */ + CLK_UART0 = 0U, + CLK_UART1, + CLK_UART2, + CLK_UART3, + CLK_RESERVE4, + CLK_RESERVE5, + CLK_SPI0, + CLK_SPI1, + CLK_SPI2, + CLK_I2C0, + CLK_RESERVE10, + CLK_PCT, + CLK_RESERVE12, + CLK_RESERVE13, + CLK_RESERVE14, + CLK_PWM0, + CLK_PWM1, + CLK_PWM2, + CLK_PWM3, + CLK_PWM4, + CLK_PWM5, + + /* PERI_CLK_EN1 */ + CLK_RESERVE32 = 32U + 0U, + CLK_RTC, + CLK_DMA0, + CLK_RESERVE35, + CLK_RESERVE36, + CLK_GPIO, + CLK_WDG, + CLK_EWDG, + CLK_CRC, + CLK_CAN0, + CLK_CAN1, + CLK_CAN2, + CLK_CAN3, + + /* PERI_CLK_EN2 */ + CLK_RESERVE64 = 32U + 32U, + CLK_CTU, + CLK_RESERVE66, + CLK_RESERVE67, + CLK_RESERVE68, + CLK_RESERVE69, + CLK_RESERVE70, + CLK_RESERVE71, + CLK_ACMP0, + CLK_PDT0, + CLK_PDT1, + CLK_ADC0, + CLK_ADC1, + CLK_TIMER, + CLK_EIO, + CLK_RESERVE79, + CLK_SMU = 83U, + CLK_MODULE_NUM +} ckgen_clock_t; + +/*! + * @brief Define the enum of the module for setting module at reset state or realse from reset state. + */ +typedef enum +{ + /* PERI_SFT_RST0 */ + SRST_UART0 = 0U, + SRST_UART1, + SRST_UART2, + SRST_UART3, + SRST_RESERVE4, + SRST_RESERVE5, + SRST_SPI0, + SRST_SPI1, + SRST_SPI2, + SRST_I2C0, + SRST_RESERVE10, + SRST_PCT, + SRST_RESERVE12, + SRST_RESERVE13, + SRST_RESERVE14, + SRST_PWM0, + SRST_PWM1, + SRST_PWM2, + SRST_PWM3, + SRST_PWM4, + SRST_PWM5, + + /* PERI_SFT_RST1 */ + SRST_RESERVE32 = 32U + 0U, + SRST_RESERVE33, + SRST_DMA0, + SRST_RESERVE35, + SRST_RESERVE36, + SRST_GPIO, + SRST_WDG, + SRST_EWDG, + SRST_CRC, + SRST_CAN0, + SRST_CAN1, + SRST_CAN2, + SRST_CAN3, + + /* PERI_SFT_RST2 */ + SRST_RESERVE64 = 32U + 32U, + SRST_CTU, + SRST_RESERVE66, + SRST_RESERVE67, + SRST_RESERVE68, + SRST_RESERVE69, + SRST_RESERVE70, + SRST_RESERVE71, + SRST_ACMP0, + SRST_PDT0, + SRST_PDT1, + SRST_ADC0, + SRST_ADC1, + SRST_TIMER, + SRST_EIO, + SRST_MODULE_NUM +} ckgen_softreset_t; + +/* =========================================================================================================================== */ +/* ================ MPU ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the MPU module */ +#define MPU_INSTANCE_MAX (1UL) + +/*!< Has process identifier support. */ +#define MPU_HAS_PROCESS_IDENTIFIER (1UL) + +/*!< Specifies total number of slaves. */ +#define MPU_SLAVE_COUNT (3UL) + +/*!< Specifies total number of masters. */ +#define MPU_MASTER_COUNT (3UL) + +/*!< The MPU Logical Bus Master Number for core bus master. */ +#define MPU_MASTER_CORE (0UL) +/*!< The MPU Logical Bus Master Number for Debugger master. */ +#define MPU_MASTER_DEBUGGER (1UL) +/*!< The MPU Logical Bus Master Number for DMA master. */ +#define MPU_MASTER_DMA (2UL) + +/*!< Specifies master number. */ +#define MPU_MASTER \ +{ \ + MPU_MASTER_CORE, \ + MPU_MASTER_DEBUGGER, \ + MPU_MASTER_DMA, \ +} + +/*!< Array of mpu base addresses */ +#define MPU_BASE_PTRS {MPU} + +/** @brief generate attribution order by user and super permission*/ +#define MPU_PERMISSION_VALUE(MasterId, UserPermission, SuperPermission) \ + ((UserPermission << (MasterId * 6U)) | \ + (SuperPermission << ((MasterId * 6U) + 3U))) + +typedef enum +{ + MPU_SLAVE_FLASH = 0U, + MPU_SLAVE_SRAM_L = 1U, + MPU_SLAVE_SRAM_U = 2U, + MPU_SLAVE_MAX +} Mpu_SlaveType; + +typedef enum +{ + MPU_REGION_ID_0 = 0U, + MPU_REGION_ID_1 = 1U, + MPU_REGION_ID_2 = 2U, + MPU_REGION_ID_3 = 3U, + MPU_REGION_ID_4 = 4U, + MPU_REGION_ID_5 = 5U, + MPU_REGION_ID_6 = 6U, + MPU_REGION_ID_7 = 7U, + MPU_REGION_ID_MAX +} Mpu_RegionIdType; + +/*! + * @brief MPU attribute enumeration. + */ +typedef enum +{ + MPU_ATTR_NONE = 0U, /*!< None permission */ + MPU_ATTR_X = 1U, /*!< Executable permission */ + MPU_ATTR_R = 2U, /*!< Readable permission */ + MPU_ATTR_RX = 3U, /*!< Readable and Executable permission */ + MPU_ATTR_W = 4U, /*!< Writeable permission */ + MPU_ATTR_WX = 5U, /*!< Writeable and Executable permission */ + MPU_ATTR_RW = 6U, /*!< Readable and Writeable permission */ + MPU_ATTR_RWX = 7U /*!< Readable, Writeable and Writeable permission */ +} Mpu_PermissionType; +/* =========================================================================================================================== */ +/* ================ PBR ================ */ +/* =========================================================================================================================== */ +/*! + * @brief PBR master module. + */ +typedef enum +{ + PBR_MASTER_CORE = 0U, + PBR_MASTER_DEBUGGER = 1U, + PBR_MASTER_DMA = 2U, + PBR_MASTER_MAX +} pbr_master_t; + +/*! + * @brief PBR peripheral module. + */ +typedef enum +{ + PBR_PWM0 = 0U, + PBR_PWM1, + PBR_PWM2, + PBR_PWM3, + PBR_PWM4, + PBR_PWM5, + PBR_RESERVE6, + PBR_RESERVE7, + + PBR_CRC = 8U, + PBR_GPIO, + PBR_PDT0, + PBR_PDT1, + PBR_MPU, + PBR_EIM, + PBR_SMU, + PBR_RESERVE15, + + PBR_CKGEN_RCM = 32U, + PBR_RESERVE33, + PBR_FLASH, + PBR_ADC0, + PBR_ADC1, + PBR_ACMP0, + PBR_CTU, + PBR_CAN0, + + PBR_CAN1 = 40U, + PBR_CAN2, + PBR_CAN3, + PBR_RESERVE43, + PBR_RESERVE44, + PBR_SPM, + PBR_RTC, + PBR_EIO, + + PBR_WDG = 48U, + PBR_EWDG, + PBR_SPI0, + PBR_SPI1, + PBR_SPI2, + PBR_RESERVE53, + PBR_I2C0, + PBR_RESERVE55, + + PBR_TIMER = 64U, + PBR_DMA, + PBR_UART0, + PBR_UART1, + PBR_UART2, + PBR_UART3, + PBR_RESERVE70, + PBR_RESERVE71, + + PBR_PCT = 72U, + PBR_CMU, + + PBR_PERI_MAX +} pbr_peripheral_t; + +/* =========================================================================================================================== */ +/* ================ CMU ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the CMU module */ +#define CMU_INSTANCE_MAX (3UL) +/*!< Array of CMU base addresses */ +#define CMU_BASE_PTRS {CMU_VHSI, CMU_HSE, CMU_PLL} + +/* =========================================================================================================================== */ +/* ================ SPM ================ */ +/* =========================================================================================================================== */ +/*!< Periph sleep ack status define */ +#define SPM_SLEEP_ACK_I2C0 (0x00000001UL) +#define SPM_SLEEP_ACK_SPI0 (0x00000004UL) +#define SPM_SLEEP_ACK_SPI1 (0x00000008UL) +#define SPM_SLEEP_ACK_SPI2 (0x00000010UL) +#define SPM_SLEEP_ACK_CAN0 (0x00000020UL) +#define SPM_SLEEP_ACK_CAN1 (0x00000040UL) +#define SPM_SLEEP_ACK_CAN2 (0x00000080UL) +#define SPM_SLEEP_ACK_CAN3 (0x00000100UL) +#define SPM_SLEEP_ACK_UART0 (0x00000800UL) +#define SPM_SLEEP_ACK_UART1 (0x00001000UL) +#define SPM_SLEEP_ACK_UART2 (0x00002000UL) +#define SPM_SLEEP_ACK_UART3 (0x00004000UL) +#define SPM_SLEEP_ACK_DMA0 (0x00020000UL) +#define SPM_SLEEP_ACK_EIO (0x00040000UL) +#define SPM_SLEEP_ACK_FLASH (0x00080000UL) + +/*! + * @brief SPM peripheral sleep ack enum. + */ +typedef enum +{ + SPM_PERI_SLEEP_ACK_I2C0 = 0U, + SPM_PERI_SLEEP_ACK_SPI0 = 2U, + SPM_PERI_SLEEP_ACK_SPI1 = 3U, + SPM_PERI_SLEEP_ACK_SPI2 = 4U, + SPM_PERI_SLEEP_ACK_CAN0 = 5U, + SPM_PERI_SLEEP_ACK_CAN1 = 6U, + SPM_PERI_SLEEP_ACK_CAN2 = 7U, + SPM_PERI_SLEEP_ACK_CAN3 = 8U, + SPM_PERI_SLEEP_ACK_UART0 = 11U, + SPM_PERI_SLEEP_ACK_UART1 = 12U, + SPM_PERI_SLEEP_ACK_UART2 = 13U, + SPM_PERI_SLEEP_ACK_UART3 = 14U, + SPM_PERI_SLEEP_ACK_DMA0 = 17U, + SPM_PERI_SLEEP_ACK_EIO = 18U, + SPM_PERI_SLEEP_ACK_FLASH = 19U +} spm_peri_sleep_ack_t; + +/* =========================================================================================================================== */ +/* ================ SMU ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the SMU module */ +#define SMU_INSTANCE_COUNT (1U) +/*!< Array of SMU base addresses */ +#define SMU_BASE_PTRS {SMU} +/*!< Array of SMU IRQs */ +#define SMU_IRQS {SMU_IRQn} +/*!< Array of SMU ckgen interface clocks */ +#define SMU_CKGEN_CLOCKS {CLK_SMU} +/*!< SMU unlock key */ +#define SMU_UNLOCK_FIRST_VALUE (0xA5U) +#define SMU_UNLOCK_SECOND_VALUE (0x5AU) + +/*!< Number of the SMU reset count threshold. */ +#define SMU_RESET_THRESHOLD (15U) + +/*! + * @brief SMU fault type. + */ +typedef enum +{ + SMU_HWSPF, /*!< Hardware single point fault types. */ + SMU_HWLF, /*!< Hardware latent fault types. */ + SMU_SWSPF, /*!< Software single point fault types. */ + SMU_SWLF /*!< Software latent fault types. */ +} Smu_FaultType; + +/*! + * @brief SMU hardware single point fault type. + */ +typedef enum +{ + SMU_HWSPF_PLL_UNLOCK, /*!< Analog pll unlock */ + SMU_HWSPF_CMU_PLL, /*!< CMU detected System PLL unlock */ + SMU_HWSPF_CMU_HSE, /*!< CMU detected HSE unlock */ + SMU_HWSPF_CMU_VHSI, /*!< CMU detected VHSI unlock */ + SMU_HWSPF_SRAM_1BIT, /*!< SRAM ECC 1 bit error */ + SMU_HWSPF_SRAM_2BITS, /*!< SRAM ECC 2 bits error */ + SMU_HWSPF_E2E, /*!< E2E parity error */ + SMU_HWSPF_DMA_ECC, /*!< DMA parity error */ + SMU_HWSPF_FLASH_ECC, /*!< Flash ECC error */ + SMU_HWSPF_PDT1, /*!< PDT1, the number of triggers is inconsisten with the cofigured numher error */ + SMU_HWSPF_PDT0, /*!< PDT0, the number of triggers is inconsisten with the cofigured numher error */ + SMU_HWSPF_WDG, /*!< Watchdog timeout */ + SMU_HWSPF_LVD, /*!< Low voltage detection of VVDD after MTCMOS long chain */ + SMU_HWSPF_DIGLDO, /*!< Low voltage detection of digital LDO */ + SMU_HWSPF_FLHLDO, /*!< Low voltage detection of flash LDO */ + SMU_HWSPF_CACHE, /*!< Cache parity error */ + SMU_HWSPF_CPU, /*!< Cpu lock up */ + SMU_HWSPF_FLEX_ECC, /*!< Flex SRAM ECC error */ + SMU_HWSPF_MAX /*!< Max number of SMU supported hardward single point fault */ +} Smu_HwSpfType; + +/*! + * @brief SMU hardware latent fault type. + */ +typedef enum +{ + SMU_HWLF_SRAM_EIM2BITS, /*!< SRAM EIM 2 bits ECC error */ + SMU_HWLF_SRAM_EIM1BIT, /*!< SRAM EIM 1 bit ECC error */ + SMU_HWLF_FLASH_EIM2BITS, /*!< Flash EIM ECC error */ + SMU_HWLF_ABIST, /*!< ABIST error */ + SMU_HWLF_MBIST, /*!< MBIST error */ + SMU_HWLF_MAX /*!< Max number of SMU supported hardward latent fault */ +} Smu_HwLfType; + +/*! + * @brief SMU software single point fault type. + */ +typedef enum +{ + SMU_SWSPF_CHANNEL_0, /*!< Not defined Software single point fault */ + SMU_SWSPF_CHANNEL_1, /*!< Not defined Software single point fault */ + SMU_SWSPF_CHANNEL_2, /*!< Not defined Software single point fault */ + SMU_SWSPF_CHANNEL_3, /*!< Not defined Software single point fault */ + SMU_SWSPF_CHANNEL_4, /*!< Not defined Software single point fault */ + SMU_SWSPF_CHANNEL_5, /*!< Not defined Software single point fault */ + SMU_SWSPF_CHANNEL_6, /*!< Not defined Software single point fault */ + SMU_SWSPF_CHANNEL_7, /*!< Not defined Software single point fault */ + SMU_SWSPF_MAX +} Smu_SwSpfType; + +/*! + * @brief SMU software latent fault type. + */ +typedef enum +{ + SMU_SWLF_CHANNEL_0, /*!< Not defined Software latent fault */ + SMU_SWLF_CHANNEL_1, /*!< Not defined Software latent fault */ + SMU_SWLF_CHANNEL_2, /*!< Not defined Software latent fault */ + SMU_SWLF_CHANNEL_3, /*!< Not defined Software latent fault */ + SMU_SWLF_CHANNEL_4, /*!< Not defined Software latent fault */ + SMU_SWLF_CHANNEL_5, /*!< Not defined Software latent fault */ + SMU_SWLF_CHANNEL_6, /*!< Not defined Software latent fault */ + SMU_SWLF_CHANNEL_7, /*!< Not defined Software latent fault */ + SMU_SWLF_MAX +} Smu_SwLfType; + + +/* =========================================================================================================================== */ +/* ================ SRAM ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the SRAM module */ +#define SRAM_INSTANCE_COUNT (1UL) +/*!< Channel Number of SRAM module */ +#define SRAM_CHANNEL_MAX (2UL) +/*!< Array of SRAM IRQs */ +#define SRAM_IRQS {ECC_1BIT_ERROR_IRQn, ECC_2BIT_ERROR_IRQn} +/*!< SRAM L start address */ +#define SRAM_L_START_ADDRESS (0x1FFF0000UL) +/*!< SRAM L end address */ +#define SRAM_L_END_ADDRESS (0x1FFFFFFFUL) +/*!< SRAM U start address */ +#define SRAM_U_START_ADDRESS (0x20000000UL) +/*!< SRAM U end address */ +#define SRAM_U_END_ADDRESS (0x2000EFFFUL) +/*!< SRAM retention size */ +#define SRAM_RETENTION_SIZE (0x8000UL) + +/*!< Number of instances of the ESM module */ +#define ESM_INSTANCE_COUNT (1U) +/*!< Array of ESM IRQs */ +#define ESM_IRQS SRAM_IRQS +/*!< 1 bit ESM IRQs */ +#define ESM_1BIT_IRQS ((uint32)ESM_CHANNEL0_1BIT_IRQ | (uint32)ESM_CHANNEL1_1BIT_IRQ) +/*!< 2 bits ESM IRQs */ +#define ESM_2BIT_IRQS ((uint32)ESM_CHANNEL0_2BIT_IRQ | (uint32)ESM_CHANNEL1_2BIT_IRQ) + +/*! + * @brief ESM channel type. + */ +typedef enum +{ + ESM_CHANNEL_SRAML, /*!< Sram_L Channel. */ + ESM_CHANNEL_SRAMU, /*!< Sram_U Channel. */ + ESM_CHANNEL_MAX /*!< Channel Number of ESM module */ +} Esm_ChannelType; + +/*! + * @brief ESM interrupt source type. + */ +typedef enum +{ + ESM_CHANNEL0_1BIT_IRQ = ECC_SRAM_ECC_ERR_CTRL_ECC0_1BIT_IRQ_EN_Msk, /*!< Sram_L Channel 1bit ECC error. */ + ESM_CHANNEL0_2BIT_IRQ = ECC_SRAM_ECC_ERR_CTRL_ECC0_2BIT_IRQ_EN_Msk, /*!< Sram_L Channel 2bit ECC error. */ + ESM_CHANNEL1_1BIT_IRQ = ECC_SRAM_ECC_ERR_CTRL_ECC1_1BIT_IRQ_EN_Msk, /*!< Sram_U Channel 1bit ECC error. */ + ESM_CHANNEL1_2BIT_IRQ = ECC_SRAM_ECC_ERR_CTRL_ECC1_2BIT_IRQ_EN_Msk, /*!< Sram_U Channel 2bit ECC error. */ +} Esm_InterruptType; + +/* =========================================================================================================================== */ +/* ================ EIM ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the EIM module */ +#define EIM_INSTANCE_COUNT (1UL) +/*!< Array of EIM base addresses */ +#define EIM_BASE_PTRS {EIM_CHANNEL0, EIM_CHANNEL1} + +/*! + * @brief EIM channel type. + */ +typedef enum +{ + EIM_CHANNEL_SRAML, /*!< Sram_L Channel. */ + EIM_CHANNEL_SRAMU, /*!< Sram_U Channel. */ + EIM_CHANNEL_MAX /*!< Channel Number of EIM module */ +} Eim_ChannelType; + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ +/*!< FLASH controler unlock key */ +#define FLASH_UNLOCK_KEY1 (0xac7840UL) +#define FLASH_UNLOCK_KEY2 (0x01234567UL) +/*!< Based address of P-FLASH */ +#define PFLASH_BASE_ADDRESS (0x00000000UL) +/*!< Based address of D-FLASH */ +#define DFLASH_BASE_ADDRESS (0x01000000UL) +/*!< Based address of FlexRAM area */ +#define FLEXRAM_BASE_ADDRESS (0x14000000UL) +/*!< P-Flash size in byte */ +#define PFLASH_BLOCK_SIZE (1024UL*1024UL) +/*!< D-Flash size in byte */ +#define DFLASH_BLOCK_SIZE (128UL*1024UL) +/*!< FlexRAM size in byte */ +#define FLEX_RAM_SIZE (4UL*1024UL) +/*!< P-Flash page size in byte */ +#define PFLASH_PAGE_SIZE (0x00000800UL) +/*!< D-Flash page size in byte */ +#define DFLASH_PAGE_SIZE (0x00000800UL) +/*!< P-Flash program unit size */ +#define PFLASH_WRITE_UNIT_SIZE (8UL) +/*!< D-Flash program unit size */ +#define DFLASH_WRITE_UNIT_SIZE (8UL) + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the GPIO module */ +#define GPIO_INSTANCE_MAX (5UL) +/*!< Array of GPIO base addresses */ +#define GPIO_BASE_PTRS {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE} + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ +/*!< Array of GPIO port base addresses */ +#define GPIO_PORT_BASE_PTRS {PORTA, PORTB, PORTC, PORTD, PORTE} + +/* =========================================================================================================================== */ +/* ================ CAN ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the CAN module */ +#define CAN_INSTANCE_MAX (4UL) +/*!< Array of CAN base addresses */ +#define CAN_BASE_PTRS {CAN0, CAN1, CAN2, CAN3} +/*!< Array of CAN IRQs */ +#define CAN_IRQS {CAN0_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn} +/*!< Array of CAN wakeup IRQs */ +#define CAN_WAKEUP_IRQS {CAN0_WAKEUP_IRQn, CAN1_WAKEUP_IRQn, CAN2_WAKEUP_IRQn, CAN3_WAKEUP_IRQn} +/*!< Array of CAN ckgen interface clocks */ +#define CAN_CKGEN_CLOCKS {CLK_CAN0, CLK_CAN1, CLK_CAN2, CLK_CAN3} +/*!< Array of CAN soft resets */ +#define CAN_SOFT_RESETS {SRST_CAN0, SRST_CAN1, SRST_CAN2, SRST_CAN3} +/*!< Array of CAN clock names */ +#define CAN_CLOCK_NAMES {CAN0_CLK, CAN1_CLK, CAN2_CLK, CAN3_CLK} +/*!< CAN receive fifo count */ +#define CAN_RECEIVE_FIFO_COUNT (13UL) +/*!< CAN transmit secondary buffer count (6 STB) */ +#define CAN_TRANSMIT_FIFO_COUNT (6UL) +/*!< CAN max filter number */ +#define CAN_FILTER_NUM_MAX (60UL) + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the UART module */ +#define UART_INSTANCE_MAX (4UL) +/*!< Array of UART base addresses */ +#define UART_BASE_PTRS {UART0, UART1, UART2, UART3} +/*!< Array of UART IRQs */ +#define UART_IRQS {UART0_IRQn, UART1_IRQn, UART2_IRQn, UART3_IRQn} +/*!< Array of UART ckgen interface clocks */ +#define UART_CKGEN_CLOCKS {CLK_UART0, CLK_UART1, CLK_UART2, CLK_UART3} +/*!< Array of UART soft resets */ +#define UART_SOFT_RESETS {SRST_UART0, SRST_UART1, SRST_UART2, SRST_UART3} +/*!< Array of UART clock names */ +#define UART_CLOCK_NAMES {UART0_CLK, UART1_CLK, UART2_CLK, UART3_CLK} + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the I2C module */ +#define I2C_INSTANCE_MAX (1UL) +/*!< Array of I2C base addresses */ +#define I2C_BASE_PTRS {I2C0} +/*!< Array of I2C IRQs */ +#define I2C_IRQS {I2C0_IRQn} +/*!< Array of I2C ckgen interface clocks */ +#define I2C_CKGEN_CLOCKS {CLK_I2C0} +/*!< Array of I2C soft resets */ +#define I2C_SOFT_RESETS {SRST_I2C0} +/*!< Array of I2C clock names */ +#define I2C_CLOCK_NAMES {I2C0_CLK} + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the SPI module */ +#define SPI_INSTANCE_MAX (3UL) +/*!< Array of SPI base addresses */ +#define SPI_BASE_PTRS {SPI0, SPI1, SPI2} +/*!< Array of SPI IRQs */ +#define SPI_IRQS {SPI0_IRQn, SPI1_IRQn, SPI2_IRQn} +/*!< Array of SPI ckgen interface clocks */ +#define SPI_CKGEN_CLOCKS {CLK_SPI0, CLK_SPI1, CLK_SPI2} +/*!< Array of SPI soft resets */ +#define SPI_SOFT_RESETS {SRST_SPI0, SRST_SPI1, SRST_SPI2} +/*!< Array of SPI clock names */ +#define SPI_CLOCK_NAMES {SPI0_CLK, SPI1_CLK, SPI2_CLK} + +/* =========================================================================================================================== */ +/* ================ EIO ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the EIO module */ +#define EIO_INSTANCE_COUNT (1UL) + +/*!< Define the maximum number of shifters for any EIO instance. */ +#define EIO_MAX_SHIFTER_COUNT (4UL) + +/*!< Array of EIO IRQs */ +#define EIO_IRQS {EIO_IRQn} + +/*!< Array of EIO clock names */ +#define EIO_CLOCK_NAMES {EIO_CLK} + +/*!< Array of EIO base addresses */ +#define EIO_BASE_PTRS {EIO} + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the CRC module */ +#define CRC_INSTANCE_MAX (1UL) +/*!< Array of CRC base addresses */ +#define CRC_BASE_PTRS {CRC} +/*!< Array of CRC ckgen interface clocks */ +#define CRC_CKGEN_CLOCKS {CLK_CRC} +/*!< Array of CRC soft resets */ +#define CRC_SOFT_RESETS {SRST_CRC} + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the RTC module */ +#define RTC_INSTANCE_MAX (1UL) +/*!< Array of RTC base addresses */ +#define RTC_BASE_PTRS {RTC} +/*!< Array of RTC IRQs */ +#define RTC_IRQS {RTC_IRQn} +/*!< Array of RTC ckgen interface clocks */ +#define RTC_CKGEN_CLOCKS {CLK_RTC} + +/* =========================================================================================================================== */ +/* ================ WDG ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the WDG module */ +#define WDG_INSTANCE_MAX (1UL) +/*!< Array of WDG base addresses */ +#define WDG_BASE_PTRS {WDG} +/*!< Array of WDG IRQs */ +#define WDG_IRQS {WDG_IRQn} +/*!< Array of WDG ckgen interface clocks */ +#define WDG_CKGEN_CLOCKS {CLK_WDG} +/*!< Array of WDG soft resets */ +#define WDG_SOFT_RESETS {SRST_WDG} +/* The reset value of the wdg window register */ +#define WDG_WIN_RESET_DEFALUT_VALUE (0x0UL) +/* The reset value of the wdg timeout register */ +#define WDG_TIMEOUT_RESET_DEFAULT_VALUE (0x5000UL) +/* The first 32-bit value used for unlocking the wdg */ +#define WDG_UNLOCK_FIRST_VALUE (0xE064D987UL) +/* The second 32-bit value used for unlocking the wdg */ +#define WDG_UNLOCK_SECOND_VALUE (0x868A8478UL) +/* The first 32-bit value used for feed the wdg */ +#define WDG_FEED_FIRST_VALUE (0x7908AD15UL) +/* The second 32-bit value used for feed the wdg */ +#define WDG_FEED_SECOND_VALUE (0x5AD5A879UL) +/* The default reset value of WDG CS0 register */ +#define WDG_CS0_RESET_VALUE (0x20UL) +/* The default reset value of WDG CS1 register */ +#define WDG_CS1_RESET_VALUE (0x0UL) +/* The default reset value of WDG TOVAL register */ +#define WDG_TOVAL_RESET_VALUE (0x5000UL) +/* The default reset value of WDG WIN register */ +#define WDG_WIN_RESET_VALUE (0x0UL) + +/* =========================================================================================================================== */ +/* ================ EWDG ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the EWDG module */ +#define EWDG_INSTANCE_MAX (1UL) +/*!< Array of EWDG IRQs */ +#define EWDG_BASE_PTRS {EWDG} +/*!< Array of EWDG IRQs */ +#define EWDG_IRQS {EWDG_IRQn} +/*!< Array of EWDG ckgen interface clocks */ +#define EWDG_CKGEN_CLOCKS {CLK_EWDG} +/*!< Array of EWDG soft resets */ +#define EWDG_SOFT_RESETS {SRST_EWDG} +/*!< EWDG refresh key values */ +#define EWDG_KEY_FIRST_BYTE (0xB4UL) +#define EWDG_KEY_SECOND_BYTE (0x2CUL) +/*!< EWDG CMPH CMPL limit values */ +#define EWDG_CMPH_MAX_VALUE (0xFEUL) +#define EWDG_CMPL_MIN_VALUE (0x00UL) + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the DMA module */ +#define DMA_INSTANCE_MAX (1UL) +/*!< Number of channel of the DMA module */ +#define DMA_CH_MAX (16UL) +/*!< Number of virtual channel of all DMA module */ +#define DMA_VIRTUAL_CH_MAX (DMA_CH_MAX * DMA_INSTANCE_MAX) +/*!< Array of DMA channel base addresses */ +#define DMA_VIRTUAL_CH_BASE_PTRS {DMA0_CHANNEL0, DMA0_CHANNEL1, DMA0_CHANNEL2, DMA0_CHANNEL3, \ + DMA0_CHANNEL4, DMA0_CHANNEL5, DMA0_CHANNEL6, DMA0_CHANNEL7, \ + DMA0_CHANNEL8, DMA0_CHANNEL9, DMA0_CHANNEL10, DMA0_CHANNEL11, \ + DMA0_CHANNEL12, DMA0_CHANNEL13, DMA0_CHANNEL14, DMA0_CHANNEL15} +/*!< Array of DMA ckgen interface clocks */ +#define DMA_CKGEN_CLOCKS {CLK_DMA0} +/*!< Array of DMA soft resets */ +#define DMA_SOFT_RESETS {SRST_DMA0} + +/*! + * @brief DMA request for the DMA channel. + */ +typedef enum +{ + DMA_REQ_DISABLE = 0U, + DMA_REQ_UART0_RX = 1U, + DMA_REQ_UART0_TX = 2U, + DMA_REQ_UART1_RX = 3U, + DMA_REQ_UART1_TX = 4U, + DMA_REQ_UART2_RX = 5U, + DMA_REQ_UART2_TX = 6U, + DMA_REQ_UART3_RX = 7U, + DMA_REQ_UART3_TX = 8U, + DMA_REQ_EIO_SHIFTER0 = 13U, + DMA_REQ_EIO_SHIFTER1 = 14U, + DMA_REQ_EIO_SHIFTER2 = 15U, + DMA_REQ_EIO_SHIFTER3 = 16U, + DMA_REQ_PWM1_CHANNEL_0 = 17U, + DMA_REQ_PWM1_CHANNEL_1 = 18U, + DMA_REQ_PWM1_CHANNEL_2 = 19U, + DMA_REQ_PWM1_CHANNEL_3 = 20U, + DMA_REQ_PWM1_CHANNEL_4 = 21U, + DMA_REQ_PWM1_CHANNEL_5 = 22U, + DMA_REQ_PWM1_CHANNEL_6 = 23U, + DMA_REQ_PWM1_CHANNEL_7 = 24U, + DMA_REQ_PWM1_UNDER_OR_OVER_FLOW = 25U, + DMA_REQ_PWM2_CHANNEL_0 = 26U, + DMA_REQ_PWM2_CHANNEL_1 = 27U, + DMA_REQ_PWM2_CHANNEL_2 = 28U, + DMA_REQ_PWM2_CHANNEL_3 = 29U, + DMA_REQ_PWM2_CHANNEL_4 = 30U, + DMA_REQ_PWM2_CHANNEL_5 = 31U, + DMA_REQ_PWM2_CHANNEL_6 = 32U, + DMA_REQ_PWM2_CHANNEL_7 = 33U, + DMA_REQ_PWM2_UNDER_OR_OVER_FLOW = 34U, + DMA_REQ_PWM0_OR_CH0_CH7 = 35U, + DMA_REQ_PWM0_UNDER_OR_OVER_FLOW = 36U, + DMA_REQ_PWM3_OR_CH0_CH7 = 37U, + DMA_REQ_PWM3_UNDER_OR_OVER_FLOW = 38U, + DMA_REQ_PWM4_OR_CH0_CH7 = 39U, + DMA_REQ_PWM4_UNDER_OR_OVER_FLOW = 40U, + DMA_REQ_PWM5_OR_CH0_CH7 = 41U, + DMA_REQ_PWM5_UNDER_OR_OVER_FLOW = 42U, + DMA_REQ_SPI0_RX = 47U, + DMA_REQ_SPI0_TX = 48U, + DMA_REQ_SPI1_RX = 49U, + DMA_REQ_SPI1_TX = 50U, + DMA_REQ_SPI2_RX = 51U, + DMA_REQ_SPI2_TX = 52U, + DMA_REQ_ADC0 = 53U, + DMA_REQ_ADC1 = 54U, + DMA_REQ_I2C0_RX = 55U, + DMA_REQ_I2C0_TX = 56U, + DMA_REQ_PORTA = 59U, + DMA_REQ_PORTB = 60U, + DMA_REQ_PORTC = 61U, + DMA_REQ_PORTD = 62U, + DMA_REQ_PORTE = 63U, + DMA_REQ_CAN0_RX = 64U, + DMA_REQ_CAN1_RX = 65U, + DMA_REQ_CAN2_RX = 66U, + DMA_REQ_CAN3_RX = 67U, + DMA_REQ_ALWAYS_ENABLED = 72U +}dma_request_source_t; + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the ADC module */ +#define ADC_INSTANCE_MAX (2UL) +/*!< Arrays of ADC base address */ +#define ADC_BASE_PTRS {ADC0, ADC1} +/*!< Arrays of ADC ckgen interface clocks */ +#define ADC_CKGEN_CLOCKS {CLK_ADC0, CLK_ADC1} +/*!< Arrays of ADC soft resets */ +#define ADC_SOFT_RESETS {SRST_ADC0, SRST_ADC1} +/*!< Array of ADC IRQs */ +#define ADC_IRQS {ADC0_IRQn, ADC1_IRQn} +/*!< Array of ADC DMA requests */ +#define ADC_DMA_REQEUSTS {DMA_REQ_ADC0, DMA_REQ_ADC1} +/*!< Array of ADC clock names */ +#define ADC_CLOCK_NAMES {ADC0_CLK, ADC1_CLK} +/*!< Max clock frequence of ADC function clock */ +#define ADC_CLOCK_FREQ_MAX_RUNTIME (30000000UL) + +/* =========================================================================================================================== */ +/* ================ ACMP ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the ACMP module */ +#define ACMP_INSTANCE_MAX (1UL) +/*!< Arrays of ACMP base address */ +#define ACMP_BASE_PTRS {ACMP0} +/*!< Arrays of ACMP ckgen interface clocks */ +#define ACMP_CKGEN_CLOCKS {CLK_ACMP0} +/*!< Arrays of ACMP soft resets */ +#define ACMP_SOFT_RESETS {SRST_ACMP0} +/*!< Array of ACMP IRQs */ +#define ACMP_IRQS {ACMP0_IRQn} + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the PWM module */ +#define PWM_INSTANCE_MAX (6UL) +/*!< Array of PWM base addresses */ +#define PWM_BASE_PTRS {PWM0, PWM1, PWM2, PWM3, PWM4, PWM5} +/*!< Array of PWM Overflow IRQs */ +#define PWM_OVERFLOW_IRQS {PWM0_OVERFLOW_IRQn, PWM1_OVERFLOW_IRQn, PWM2_OVERFLOW_IRQn, PWM3_OVERFLOW_IRQn, PWM4_OVERFLOW_IRQn, PWM5_OVERFLOW_IRQn} +/*!< Array of PWM Channel IRQs */ +#define PWM_CHANNEL_IRQS {PWM0_CHANNEL_IRQn, PWM1_CHANNEL_IRQn, PWM2_CHANNEL_IRQn, PWM3_CHANNEL_IRQn, PWM4_CHANNEL_IRQn, PWM5_CHANNEL_IRQn} +/*!< Array of PWM Fault IRQs */ +#define PWM_FAULT_IRQS {PWM0_FAULT_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn, PWM5_FAULT_IRQn} +/*!< Array of PWM ckgen interface clocks */ +#define PWM_CKGEN_CLOCKS {CLK_PWM0, CLK_PWM1, CLK_PWM2, CLK_PWM3, CLK_PWM4, CLK_PWM5} +/*!< Array of PWM soft resets */ +#define PWM_SOFT_RESETS {SRST_PWM0, SRST_PWM1, SRST_PWM2, SRST_PWM3, SRST_PWM4, SRST_PWM5} + +/* =========================================================================================================================== */ +/* ================ PDT ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the PDT module */ +#define PDT_INSTANCE_MAX (2UL) +/*!< Array of PDT base addresses */ +#define PDT_BASE_PTRS {PDT0, PDT1} +/*!< Array of PDT IRQs */ +#define PDT_IRQS {PDT0_IRQn, PDT1_IRQn} +/*!< Array of PDT ckgen interface clocks */ +#define PDT_CKGEN_CLOCKS {CLK_PDT0, CLK_PDT1} +/*!< Array of PDT soft resets */ +#define PDT_SOFT_RESETS {SRST_PDT0, SRST_PDT1} + +/* =========================================================================================================================== */ +/* ================ TIMER ================ */ +/* =========================================================================================================================== */ +/*!< Channel Number of timer module */ +#define TIMER_CHANNEL_MAX (4UL) +/*!< Number of instances of the timer module */ +#define TIMER_INSTANCE_COUNT (1UL) +/*!< Array of timer base addresses */ +#define TIMER_BASE_PTRS {TIMER_CHANNEL0, TIMER_CHANNEL1, TIMER_CHANNEL2, TIMER_CHANNEL3} +/*!< Array of timer IRQs */ +#define TIMER_IRQS {TIMER_CHANNEL0_IRQn, TIMER_CHANNEL1_IRQn, TIMER_CHANNEL2_IRQn, TIMER_CHANNEL3_IRQn} +/*!< Array of timer clock names */ +#define TIMER_CLOCK_NAMES {TIMER_CLK} + +/* =========================================================================================================================== */ +/* ================ PCT ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the PCT module */ +#define PCT_INSTANCE_COUNT (1UL) +/*!< Array of PCT base addresses */ +#define PCT_BASE_PTRS {PCT} +/*!< Array of PCT IRQs */ +#define PCT_IRQS {PCT_IRQn} +/*!< Array of PCT clock names */ +#define PCT_CLOCK_NAMES {PCT_CLK} + +/* =========================================================================================================================== */ +/* ================ CTU ================ */ +/* =========================================================================================================================== */ +/*!< Number of instances of the CTU module */ +#define CTU_INSTANCE_MAX (1UL) +/*!< Array of CTU base addresses */ +#define CTU_BASE_PTRS {CTU} +/*!< Array of CTU ckgen interface clocks */ +#define CTU_CKGEN_CLOCKS {CLK_CTU} +/*!< Array of CTU soft resets */ +#define CTU_SOFT_RESETS {SRST_CTU} + +/*! + * @brief Enumeration for trigger source of the trgmux. + */ +typedef enum +{ + TRGMUX_TRIG_SOURCE_DISABLE = 0U, /*!< Trigger source of disable */ + TRGMUX_TRIG_SOURCE_ENABLE = 1U, /*!< Trigger source of enable */ + TRGMUX_TRIG_SOURCE_EXT_IN0 = 2U, /*!< Trigger source of ext_in0 */ + TRGMUX_TRIG_SOURCE_EXT_IN1 = 3U, /*!< Trigger source of ext_in1 */ + TRGMUX_TRIG_SOURCE_EXT_IN2 = 4U, /*!< Trigger source of ext_in2 */ + TRGMUX_TRIG_SOURCE_EXT_IN3 = 5U, /*!< Trigger source of ext_in3 */ + TRGMUX_TRIG_SOURCE_EXT_IN4 = 6U, /*!< Trigger source of ext_in4 */ + TRGMUX_TRIG_SOURCE_EXT_IN5 = 7U, /*!< Trigger source of ext_in5 */ + TRGMUX_TRIG_SOURCE_EXT_IN6 = 8U, /*!< Trigger source of ext_in6 */ + TRGMUX_TRIG_SOURCE_EXT_IN7 = 9U, /*!< Trigger source of ext_in7 */ + TRGMUX_TRIG_SOURCE_EXT_IN8 = 10U, /*!< Trigger source of ext_in8 */ + TRGMUX_TRIG_SOURCE_EXT_IN9 = 11U, /*!< Trigger source of ext_in9 */ + TRGMUX_TRIG_SOURCE_EXT_IN10 = 12U, /*!< Trigger source of ext_in10 */ + TRGMUX_TRIG_SOURCE_EXT_IN11 = 13U, /*!< Trigger source of ext_in11 */ + TRGMUX_TRIG_SOURCE_ACMP0_OUT = 14U, /*!< Trigger source of acmp0_out */ + TRGMUX_TRIG_SOURCE_TIMER_CH0 = 16U, /*!< Trigger source of timer_ch0 */ + TRGMUX_TRIG_SOURCE_TIMER_CH1 = 17U, /*!< Trigger source of timer_Ch1 */ + TRGMUX_TRIG_SOURCE_TIMER_CH2 = 18U, /*!< Trigger source of timer_ch2 */ + TRGMUX_TRIG_SOURCE_TIMER_CH3 = 19U, /*!< Trigger source of timer_ch3 */ + TRGMUX_TRIG_SOURCE_PCT0_TRIG = 20U, /*!< Trigger source of pct0_trig */ + TRGMUX_TRIG_SOURCE_PWM0_INIT_TRIG = 21U, /*!< Trigger source of pwm0_init_trig */ + TRGMUX_TRIG_SOURCE_PWM0_MATCH_TRIG = 22U, /*!< Trigger source of pwm0_match_trig */ + TRGMUX_TRIG_SOURCE_PWM0_MAX_TRIG = 23U, /*!< Trigger source of pwm0_max_trig */ + TRGMUX_TRIG_SOURCE_PWM1_INIT_TRIG = 24U, /*!< Trigger source of pwm1_init_trig */ + TRGMUX_TRIG_SOURCE_PWM1_MATCH_TRIG = 25U, /*!< Trigger source of pwm1_match_trig */ + TRGMUX_TRIG_SOURCE_PWM1_MAX_TRIG = 26U, /*!< Trigger source of pwm1_max_trig */ + TRGMUX_TRIG_SOURCE_PWM2_INIT_TRIG = 27U, /*!< Trigger source of pwm2_init_trig */ + TRGMUX_TRIG_SOURCE_PWM2_MATCH_TRIG = 28U, /*!< Trigger source of pwm2_match_trig */ + TRGMUX_TRIG_SOURCE_PWM2_MAX_TRIG = 29U, /*!< Trigger source of pwm2_max_trig */ + TRGMUX_TRIG_SOURCE_PWM3_INIT_TRIG = 30U, /*!< Trigger source of pwm3_init_trig */ + TRGMUX_TRIG_SOURCE_PWM3_MATCH_TRIG = 31U, /*!< Trigger source of pwm3_match_trig */ + TRGMUX_TRIG_SOURCE_PWM3_MAX_TRIG = 32U, /*!< Trigger source of pwm3_max_trig */ + TRGMUX_TRIG_SOURCE_PWM4_INIT_TRIG = 33U, /*!< Trigger source of pwm4_init_trig */ + TRGMUX_TRIG_SOURCE_PWM4_MATCH_TRIG = 34U, /*!< Trigger source of pwm4_match_trig */ + TRGMUX_TRIG_SOURCE_PWM4_MAX_TRIG = 35U, /*!< Trigger source of pwm4_max_trig */ + TRGMUX_TRIG_SOURCE_PWM5_INIT_TRIG = 36U, /*!< Trigger source of pwm5_init_trig */ + TRGMUX_TRIG_SOURCE_PWM5_MATCH_TRIG = 37U, /*!< Trigger source of pwm5_match_trig */ + TRGMUX_TRIG_SOURCE_PWM5_MAX_TRIG = 38U, /*!< Trigger source of pwm5_max_trig */ + TRGMUX_TRIG_SOURCE_ADC0_EOC = 45U, /*!< Trigger source of adc0_eoc */ + TRGMUX_TRIG_SOURCE_ADC0_IEOC = 46U, /*!< Trigger source of adc0_ieoc */ + TRGMUX_TRIG_SOURCE_ADC0_AMO = 47U, /*!< Trigger source of adc0_amo */ + TRGMUX_TRIG_SOURCE_ADC1_EOC = 48U, /*!< Trigger source of adc1_eoc */ + TRGMUX_TRIG_SOURCE_ADC1_IEOC = 49U, /*!< Trigger source of adc1_ieoc */ + TRGMUX_TRIG_SOURCE_ADC1_AMO = 50U, /*!< Trigger source of adc1_amo */ + TRGMUX_TRIG_SOURCE_PDT0_TRIG = 51U, /*!< Trigger source of pdt0_trig */ + TRGMUX_TRIG_SOURCE_PDT0_PULSE_OUT = 52U, /*!< Trigger source of pdt0_pulse_out */ + TRGMUX_TRIG_SOURCE_PDT1_TRIG = 53U, /*!< Trigger source of pdt1_trig */ + TRGMUX_TRIG_SOURCE_PDT1_PULSE_OUT = 54U, /*!< Trigger source of pdt1_pulse_out */ + TRGMUX_TRIG_SOURCE_RTC_ALARM_TRIG = 55U, /*!< Trigger source of rtc_alarm_trig */ + TRGMUX_TRIG_SOURCE_RTC_PRESCALER_TRIG = 56U, /*!< Trigger source of rtc_prescaler_trig */ + TRGMUX_TRIG_SOURCE_EIO_TRIG0 = 57U, /*!< Trigger source of eio_trig0 */ + TRGMUX_TRIG_SOURCE_EIO_TRIG1 = 58U, /*!< Trigger source of eio_trig1 */ + TRGMUX_TRIG_SOURCE_EIO_TRIG2 = 59U, /*!< Trigger source of eio_trig2 */ + TRGMUX_TRIG_SOURCE_EIO_TRIG3 = 60U, /*!< Trigger source of eio_trig3 */ + TRGMUX_TRIG_SOURCE_SW_TRIG0 = 61U, /*!< Trigger source of sw_trig0 */ + TRGMUX_TRIG_SOURCE_SW_TRIG1 = 62U, /*!< Trigger source of sw_trig1 */ + TRGMUX_TRIG_SOURCE_SW_TRIG2 = 63U, /*!< Trigger source of sw_trig2 */ + TRGMUX_TRIG_SOURCE_SW_TRIG3 = 64U /*!< Trigger source of sw_trig3 */ +} trgmux_trigger_source_t; + +/*! + * @brief Enumeration for target module of the trgmux. + */ +typedef enum +{ + TRGMUX_TARGET_MODULE_DMA_CH0 = 0U, /*!< Target module of dma_ch0 */ + TRGMUX_TARGET_MODULE_DMA_CH1 = 1U, /*!< Target module of dma_ch1 */ + TRGMUX_TARGET_MODULE_DMA_CH2 = 2U, /*!< Target module of dma_ch2 */ + TRGMUX_TARGET_MODULE_DMA_CH3 = 3U, /*!< Target module of dma_ch3 */ + TRGMUX_TARGET_MODULE_EXT_OUT0 = 4U, /*!< Target module of ext_out0 */ + TRGMUX_TARGET_MODULE_EXT_OUT1 = 5U, /*!< Target module of ext_out1 */ + TRGMUX_TARGET_MODULE_EXT_OUT2 = 6U, /*!< Target module of ext_out2 */ + TRGMUX_TARGET_MODULE_EXT_OUT3 = 7U, /*!< Target module of ext_out3 */ + TRGMUX_TARGET_MODULE_EXT_OUT4 = 8U, /*!< Target module of ext_out4 */ + TRGMUX_TARGET_MODULE_EXT_OUT5 = 9U, /*!< Target module of ext_out5 */ + TRGMUX_TARGET_MODULE_EXT_OUT6 = 10U, /*!< Target module of ext_out6 */ + TRGMUX_TARGET_MODULE_EXT_OUT7 = 11U, /*!< Target module of ext_out7 */ + TRGMUX_TARGET_MODULE_ADC0_REGULAR0 = 12U, /*!< Target module of adc0_regular0 */ + TRGMUX_TARGET_MODULE_ADC0_REGULAR1 = 13U, /*!< Target module of adc0_regular1 */ + TRGMUX_TARGET_MODULE_ADC0_REGULAR2 = 14U, /*!< Target module of adc0_regular2 */ + TRGMUX_TARGET_MODULE_ADC0_REGULAR3 = 15U, /*!< Target module of adc0_regular3 */ + TRGMUX_TARGET_MODULE_ADC0_INJECTION0 = 16U, /*!< Target module of adc0_injection0 */ + TRGMUX_TARGET_MODULE_ADC0_INJECTION1 = 17U, /*!< Target module of adc0_injection1 */ + TRGMUX_TARGET_MODULE_ADC0_INJECTION2 = 18U, /*!< Target module of adc0_injection2 */ + TRGMUX_TARGET_MODULE_ADC0_INJECTION3 = 19U, /*!< Target module of adc0_injection3 */ + TRGMUX_TARGET_MODULE_ADC1_REGULAR0 = 20U, /*!< Target module of adc1_regular0 */ + TRGMUX_TARGET_MODULE_ADC1_REGULAR1 = 21U, /*!< Target module of adc1_regular1 */ + TRGMUX_TARGET_MODULE_ADC1_REGULAR2 = 22U, /*!< Target module of adc1_regular2 */ + TRGMUX_TARGET_MODULE_ADC1_REGULAR3 = 23U, /*!< Target module of adc1_regular3 */ + TRGMUX_TARGET_MODULE_ADC1_INJECTION0 = 24U, /*!< Target module of adc1_injection0 */ + TRGMUX_TARGET_MODULE_ADC1_INJECTION1 = 25U, /*!< Target module of adc1_injection1 */ + TRGMUX_TARGET_MODULE_ADC1_INJECTION2 = 26U, /*!< Target module of adc1_injection2 */ + TRGMUX_TARGET_MODULE_ADC1_INJECTION3 = 27U, /*!< Target module of adc1_injection3 */ + TRGMUX_TARGET_MODULE_ACMP0_TR = 28U, /*!< Target module of acmp0_tr */ + TRGMUX_TARGET_MODULE_PWM0_TRIG0 = 32U, /*!< Target module of pwm0_trig0 */ + TRGMUX_TARGET_MODULE_PWM0_FAULT0 = 33U, /*!< Target module of pwm0_fault0 */ + TRGMUX_TARGET_MODULE_PWM0_FAULT1 = 34U, /*!< Target module of pwm0_fault1 */ + TRGMUX_TARGET_MODULE_PWM0_FAULT2 = 35U, /*!< Target module of pwm0_fault2 */ + TRGMUX_TARGET_MODULE_PWM1_TRIG0 = 36U, /*!< Target module of pwm1_trig0 */ + TRGMUX_TARGET_MODULE_PWM1_FAULT0 = 37U, /*!< Target module of pwm1_fault0 */ + TRGMUX_TARGET_MODULE_PWM1_FAULT1 = 38U, /*!< Target module of pwm1_fault1 */ + TRGMUX_TARGET_MODULE_PWM1_FAULT2 = 39U, /*!< Target module of pwm1_fault2 */ + TRGMUX_TARGET_MODULE_PWM2_TRIG0 = 40U, /*!< Target module of pwm2_trig0 */ + TRGMUX_TARGET_MODULE_PWM2_FAULT0 = 41U, /*!< Target module of pwm2_fault0 */ + TRGMUX_TARGET_MODULE_PWM2_FAULT1 = 42U, /*!< Target module of pwm2_fault1 */ + TRGMUX_TARGET_MODULE_PWM2_FAULT2 = 43U, /*!< Target module of pwm2_fault2 */ + TRGMUX_TARGET_MODULE_PWM3_TRIG0 = 44U, /*!< Target module of pwm3_trig0 */ + TRGMUX_TARGET_MODULE_PWM3_FAULT0 = 45U, /*!< Target module of pwm3_fault0 */ + TRGMUX_TARGET_MODULE_PWM3_FAULT1 = 46U, /*!< Target module of pwm3_fault1 */ + TRGMUX_TARGET_MODULE_PWM3_FAULT2 = 47U, /*!< Target module of pwm3_fault2 */ + TRGMUX_TARGET_MODULE_PWM4_TRIG0 = 48U, /*!< Target module of pwm4_trig0 */ + TRGMUX_TARGET_MODULE_PWM5_TRIG0 = 52U, /*!< Target module of pwm5_trig0 */ + TRGMUX_TARGET_MODULE_TIMER_CH0 = 64U, /*!< Target module of timer_ch0 */ + TRGMUX_TARGET_MODULE_TIMER_CH1 = 65U, /*!< Target module of timer_ch1 */ + TRGMUX_TARGET_MODULE_TIMER_CH2 = 66U, /*!< Target module of timer_ch2 */ + TRGMUX_TARGET_MODULE_TIMER_CH3 = 67U, /*!< Target module of timer_ch3 */ + TRGMUX_TARGET_MODULE_PCT0 = 68U, /*!< Target module of pct0 */ + TRGMUX_TARGET_MODULE_UART0 = 72U, /*!< Target module of uart0 */ + TRGMUX_TARGET_MODULE_UART1 = 76U, /*!< Target module of uart1 */ + TRGMUX_TARGET_MODULE_PDT0 = 80U, /*!< Target module of pdt0 */ + TRGMUX_TARGET_MODULE_PDT1 = 84U, /*!< Target module of pdt1 */ + TRGMUX_TARGET_MODULE_EIO_TIMR0 = 88U, /*!< Target module of eio_timer0 */ + TRGMUX_TARGET_MODULE_EIO_TIMR1 = 89U, /*!< Target module of eio_timer1 */ + TRGMUX_TARGET_MODULE_EIO_TIMR2 = 90U, /*!< Target module of eio_timer2 */ + TRGMUX_TARGET_MODULE_EIO_TIMR3 = 91U /*!< Target module of eio_timer3 */ +} trgmux_target_module_t; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* AC7840X_FEATURES_H */ + +/* ============================================= EOF ============================================== */ diff --git a/inc/device_assert.h b/inc/device_assert.h new file mode 100644 index 0000000..338ef2b --- /dev/null +++ b/inc/device_assert.h @@ -0,0 +1,81 @@ +/* Copyright Statement: + * + * This software/firmware and related documentation ("AutoChips Software") are + * protected under relevant copyright laws. The information contained herein is + * confidential and proprietary to AutoChips Inc. and/or its licensors. Without + * the prior written permission of AutoChips inc. and/or its licensors, any + * reproduction, modification, use or disclosure of AutoChips Software, and + * information contained herein, in whole or in part, shall be strictly + * prohibited. + * + * AutoChips Inc. (C) 2021. All rights reserved. + * + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE") + * RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER + * ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL + * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR + * NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH + * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, + * INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES + * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. + * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO + * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS + * SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE + * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S + * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE + * RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE + * AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE + * CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE. + */ + +/*! + * @file device_assert.h + * + * @brief This file provides assert functions. + * + */ + +#ifndef DEVICE_ASSERT_H +#define DEVICE_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* =========================================== Includes =========================================== */ + +/* ============================================ Define ============================================ */ +/*! + * @brief The assert_param macro is used for function's check. + * + * @param expr: If x is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If x is true, it returns no value. + * @retval none + */ +#ifdef ATC_DEVICE_ASSERT + #define DEVICE_ASSERT(x) ((x) ? (void)0 : (void)printf("[ASSERT]Detect error on %s %d\n", __FILE__, __LINE__) ) +#elif defined(CUSTOM_DEVICE_ASSERT) + /* If the CUSTOM_DEVICE_ASSERT symbol is defined, then add the custom implementation */ +#else + #define DEVICE_ASSERT(x) ((void)0) +#endif + +/* =========================================== Typedef ============================================ */ + +/* ========================================== Variables =========================================== */ + +/* ==================================== Functions declaration ===================================== */ + +/* ====================================== Functions define ======================================== */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* DEVICE_ASSERT_H */ + +/* ============================================= EOF ============================================== */ diff --git a/inc/device_register.h b/inc/device_register.h new file mode 100644 index 0000000..5d68dea --- /dev/null +++ b/inc/device_register.h @@ -0,0 +1,60 @@ +/* Copyright Statement: + * + * This software/firmware and related documentation ("AutoChips Software") are + * protected under relevant copyright laws. The information contained herein is + * confidential and proprietary to AutoChips Inc. and/or its licensors. Without + * the prior written permission of AutoChips inc. and/or its licensors, any + * reproduction, modification, use or disclosure of AutoChips Software, and + * information contained herein, in whole or in part, shall be strictly + * prohibited. + * + * AutoChips Inc. (C) 2021. All rights reserved. + * + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE") + * RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER + * ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL + * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR + * NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH + * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, + * INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES + * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. + * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO + * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS + * SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE + * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S + * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE + * RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE + * AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE + * CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE. + */ + +/*! + * @file device_register.h + * + * @brief This file provides include the cpu specific register header files. + * + */ + +#ifndef DEVICE_REGISTER_H +#define DEVICE_REGISTER_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ac7840x.h" +#include "device_assert.h" +#include "ac7840x_features.h" + +void nvic_system_reset(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* DEVICE_REGISTER_H */ + +/* ============================================= EOF ============================================== */ diff --git a/inc/device_status.h b/inc/device_status.h new file mode 100644 index 0000000..db43ffb --- /dev/null +++ b/inc/device_status.h @@ -0,0 +1,120 @@ +/* Copyright Statement: + * + * This software/firmware and related documentation ("AutoChips Software") are + * protected under relevant copyright laws. The information contained herein is + * confidential and proprietary to AutoChips Inc. and/or its licensors. Without + * the prior written permission of AutoChips inc. and/or its licensors, any + * reproduction, modification, use or disclosure of AutoChips Software, and + * information contained herein, in whole or in part, shall be strictly + * prohibited. + * + * AutoChips Inc. (C) 2021. All rights reserved. + * + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE") + * RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER + * ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL + * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR + * NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH + * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, + * INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES + * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. + * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO + * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS + * SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE + * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S + * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE + * RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE + * AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE + * CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE. + */ + +/*! + * @file device_status.h + * + * @brief This file provides all device status enum. + * + */ + +#ifndef DEVICE_STATUS_H +#define DEVICE_STATUS_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef enum +{ + /* Generic error codes */ + STATUS_SUCCESS = 0x000U, /*!< Generic operation success status */ + STATUS_ERROR = 0x001U, /*!< Generic operation failure status */ + STATUS_BUSY = 0x002U, /*!< Generic operation busy status */ + STATUS_TIMEOUT = 0x003U, /*!< Generic operation timeout status */ + STATUS_UNSUPPORTED = 0x004U, /*!< Generic operation unsupported status */ + /* MCU specific error codes */ + STATUS_MCU_GATED_OFF = 0x100U, /*!< Module is gated off */ + STATUS_MCU_TRANSITION_FAILED = 0x101U, /*!< Error occurs during transition. */ + STATUS_MCU_INVALID_STATE = 0x102U, /*!< Unsupported in current state. */ + STATUS_MCU_NOTIFY_BEFORE_ERROR = 0x103U, /*!< Error occurs during send "BEFORE" notification. */ + STATUS_MCU_NOTIFY_AFTER_ERROR = 0x104U, /*!< Error occurs during send "AFTER" notification. */ + /* I2C specific error codes */ + STATUS_I2C_RECEIVED_NACK = 0x200U, /*!< NACK signal received */ + STATUS_I2C_TX_UNDERRUN = 0x201U, /*!< TX underrun error */ + STATUS_I2C_RX_OVERRUN = 0x202U, /*!< RX overrun error */ + STATUS_I2C_ARBITRATION_LOST = 0x203U, /*!< Arbitration lost */ + STATUS_I2C_ABORTED = 0x204U, /*!< A transfer was aborted */ + STATUS_I2C_BUS_BUSY = 0x205U, /*!< I2C bus is busy, cannot start transfer */ + /* Security specific error codes */ + STATUS_SEC_SEQUENCE_ERROR = 0x402U, /*!< The sequence of commands or subcommands is out of + sequence */ + STATUS_SEC_KEY_NOT_AVAILABLE = 0x403U, /*!< A key is locked due to failed boot measurement or + an active debugger */ + STATUS_SEC_KEY_INVALID = 0x404U, /*!< A function is called to perform an operation with + a key that is not allowed for the given operation */ + STATUS_SEC_KEY_EMPTY = 0x405U, /*!< Attempt to use a key that has not been initialized yet */ + STATUS_SEC_NO_SECURE_BOOT = 0x406U, /*!< The conditions for a secure boot process are not met */ + STATUS_SEC_KEY_WRITE_PROTECTED = 0x407U, /*!< Request for updating a write protected key slot, + or activating debugger with write protected key(s) */ + STATUS_SEC_KEY_UPDATE_ERROR = 0x408U, /*!< Key update did not succeed due to errors in + verification of the messages */ + STATUS_SEC_RNG_SEED = 0x409U, /*!< Returned by CMD_RND and CMD_DEBUG if the seed has not + been initialized before */ + STATUS_SEC_NO_DEBUGGING = 0x40AU, /*!< DEBUG command authentication failed */ + STATUS_SEC_MEMORY_FAILURE = 0x40CU, /*!< General memory technology failure + (multibit ECC error, common fault detected) */ + STATUS_SEC_HSM_INTERNAL_MEMORY_ERROR = 0x410U, /*!< An internal memory error encountered while + executing the command */ + STATUS_SEC_INVALID_COMMAND = 0x411U, /*!< Command value out of range */ + STATUS_SEC_TRNG_ERROR = 0x412U, /*!< One or more statistical tests run on the TRNG output failed */ + STATUS_SEC_HSM_FLASH_BLOCK_ERROR = 0x413U, /*!< Error reading, programming or erasing one of the HSM flash blocks */ + STATUS_SEC_INTERNAL_CMD_ERROR = 0x414U, /*!< An internal command processor error while executing a command */ + STATUS_SEC_MAC_LENGTH_ERROR = 0x415U, /*!< MAC/Message length out of range */ + STATUS_SEC_INVALID_ARG = 0x421U, /*!< Invalid command argument */ + STATUS_SEC_TRNG_CLOCK_ERROR = 0x423U, /*!< TRNG not provided with a stable clock */ + /* SPI specific error codes */ + STATUS_SPI_TX_UNDERRUN = 0x500U, /*!< TX underrun error */ + STATUS_SPI_RX_OVERRUN = 0x501U, /*!< RX overrun error */ + STATUS_SPI_ABORTED = 0x502U, /*!< A transfer was aborted */ + /* UART specific error codes */ + STATUS_UART_TX_UNDERRUN = 0x600U, /*!< TX underrun error */ + STATUS_UART_RX_OVERRUN = 0x601U, /*!< RX overrun error */ + STATUS_UART_ABORTED = 0x602U, /*!< A transfer was aborted */ + STATUS_UART_FRAMING_ERROR = 0x603U, /*!< Framing error */ + STATUS_UART_PARITY_ERROR = 0x604U, /*!< Parity error */ + STATUS_UART_BREAK_ERROR = 0x605U, /*!< Break error */ + STATUS_UART_NOISE_ERROR = 0x606U, /*!< Noise error */ + /* I2S specific error codes */ + STATUS_I2S_TX_UNDERRUN = 0x700U, /*!< TX underrun error */ + STATUS_I2S_RX_OVERRUN = 0x701U, /*!< RX overrun error */ + STATUS_I2S_ABORTED = 0x702U, /*!< A transfer was aborted */ +} status_t; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* DEVICE_STATUS_H */ + +/* ============================================= EOF ============================================== */ diff --git a/inc/system_ac7840x.h b/inc/system_ac7840x.h new file mode 100644 index 0000000..1c9e9ed --- /dev/null +++ b/inc/system_ac7840x.h @@ -0,0 +1,197 @@ +/* Copyright Statement: + * + * This software/firmware and related documentation ("AutoChips Software") are + * protected under relevant copyright laws. The information contained herein is + * confidential and proprietary to AutoChips Inc. and/or its licensors. Without + * the prior written permission of AutoChips inc. and/or its licensors, any + * reproduction, modification, use or disclosure of AutoChips Software, and + * information contained herein, in whole or in part, shall be strictly + * prohibited. + * + * AutoChips Inc. (C) 2021. All rights reserved. + * + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE") + * RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER + * ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL + * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR + * NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH + * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, + * INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES + * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. + * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO + * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS + * SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE + * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S + * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE + * RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE + * AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE + * CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE. + */ + +/*! + * @file system_ac7840x.h + * + * @brief This file provides system clock config integration functions interfaces. + * + */ + +#ifndef SYSTEM_AC7840X_H +#define SYSTEM_AC7840X_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* =========================================== Includes =========================================== */ +#include + +/* ============================================ Define ============================================ */ +#define STARTUP_HAL_MODULE_ID (13U) +#define STARTUP_HAL_SW_MAJOR_VERSION (3U) +#define STARTUP_HAL_SW_MINOR_VERSION (0U) +#define STARTUP_HAL_SW_PATCH_VERSION (5U) + +/* ============================================ Define ============================================ */ +/*!< Sram ECC read enable */ +#define SRAM_ECC_READ_ENABLE (1UL) + +/*!< Sram ECC 2bit error reset enable */ +#define SRAM_ECC_ERR_RST_ENABLE (0UL) + +/*!< Watchdog disable */ +#ifndef WDG_DISABLE + #define WDG_DISABLE (1UL) +#endif + +/*!< Don't initialize sram after reset except power on, lvr and standby wakeup */ +#define NOT_INIT_SRAM_AFTER_RESET (1UL) + +/*!< Default system clock */ +#define DEFAULT_SYSTEM_CLOCK (48000000UL) + +/*!< Default HSE(XOSC) frequency or user define */ +#define CKGEN_HSE_FREQ (8000000UL) + +/*!< System clock uses ckgen driver */ +#define SYSTEM_USE_CKGEN (0UL) + +/* PRQA S 3006,1006,3387 ++ */ /* assembler used. */ +/*!< Global interrupt control */ +extern volatile uint8_t s_disIrqReqTimes; +#define EnableInterrupts \ + do { \ + if (s_disIrqReqTimes > 0U) s_disIrqReqTimes--; \ + if (s_disIrqReqTimes == 0U) __asm("CPSIE i"); \ + } while(0) + +#define DisableInterrupts \ + do { \ + if (s_disIrqReqTimes == 0U) __asm("CPSID i"); \ + s_disIrqReqTimes++; \ + } while(0) + +/*!< Global fault control */ +extern volatile uint8_t s_disIrqFltTimes; +#define EnableFatules \ + do { \ + if (s_disIrqFltTimes > 0U) s_disIrqFltTimes--; \ + if (s_disIrqFltTimes == 0U) __asm("CPSIE F"); \ + } while(0) +#define DisableFatules \ + do { \ + if (s_disIrqFltTimes == 0U) __asm("CPSID F"); \ + s_disIrqFltTimes++; \ + } while(0) + +/* PRQA S 3006,1006,3387 -- */ + +/* =========================================== Typedef ============================================ */ + +/* ========================================== Variables =========================================== */ + +/* ==================================== Functions declaration ===================================== */ +/*! + * @brief Initialize SPLL then set system clock to the SPLL clock + * (just support SPLL refer clock 4/8/12/16/30MHz, others need to modify). + * + * @param[in] refClk: 0: HSI clock, 1: HSE clock + * @param[in] freq: SPLL out frequency (16 - 120) + * @return status 0: success others: error + */ +uint32_t SetSysClkToSPLL(uint8_t refClk, uint8_t freq); + +/*! + * @brief Initialize VHSI then set system clock to the VHSI clock. + * + * @param[in] none + * @return status 0: success others: error + */ +uint32_t SetSysClkToVHSI(void); + +/*! + * @brief Initialize HSE then set system clock to the HSE clock. + * + * @param[in] bypass: 0: disable, 1: enable + * @return status 0: success others: error + */ +uint32_t SetSysClkToHSE(uint8_t bypass); + +/*! + * @brief Initialize HSI then set system clock to the HSI clock. + * + * @param[in] none + * @return status 0: success others: error + */ +uint32_t SetSysClkToHSI(void); + +/*! + * @brief Get UUID from devie + * + * @param[out] uuidBuffer: UUID buffer + * @return none + */ +void GetUUID(uint32_t *uuidBuffer); + +/*! + * @brief Setup the microcontroller system. Initialize the System. + * + * @param[in] none + * @return none + */ +void SystemInit(void); + +/*! + * @brief Initialize the SRAM to 0 for ECC. + * + * @param[in] StackBase: Main stack start address. + * @param[in] StackEnd: Main stack end address. + * @return none + */ +void InitSram(uint32_t StackBase, uint32_t StackEnd); + +/*! + * @brief Update system clock frequence. + * + * @param[in] none + * @return none + */ +void SystemCoreClockUpdate(void); + +/*! + * @brief Enable NMI, after set pinmux. + * + * @param[in] enable: enable state + * @return none + */ +void EnableNMI(uint8_t enable); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* SYSTEM_AC7840X_H */ + +/* ============================================= EOF ============================================== */ diff --git a/modular.json b/modular.json new file mode 100644 index 0000000..94181f5 --- /dev/null +++ b/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "inc" + ], + "srcs": [ + "src/**.c" + ] + } +} \ No newline at end of file diff --git a/src/system_ac7840x.c b/src/system_ac7840x.c new file mode 100644 index 0000000..ca5096d --- /dev/null +++ b/src/system_ac7840x.c @@ -0,0 +1,681 @@ +/* Copyright Statement: + * + * This software/firmware and related documentation ("AutoChips Software") are + * protected under relevant copyright laws. The information contained herein is + * confidential and proprietary to AutoChips Inc. and/or its licensors. Without + * the prior written permission of AutoChips inc. and/or its licensors, any + * reproduction, modification, use or disclosure of AutoChips Software, and + * information contained herein, in whole or in part, shall be strictly + * prohibited. + * + * AutoChips Inc. (C) 2021. All rights reserved. + * + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE") + * RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER + * ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL + * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR + * NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH + * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, + * INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES + * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. + * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO + * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS + * SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE + * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S + * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE + * RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE + * AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE + * CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE. + */ + +/*! + * @file system_ac7840x.c + * + * @brief This file provides system clock config integration functions. + * + */ + +/* PRQA S 0380 EOF */ /* Number of macro definitions exceeds 4095 */ +/* PRQA S 0306,0303 EOF */ /* Type conversion. */ +/* PRQA S 2889 EOF */ /* More than one 'return'. */ +/* PRQA S 3415 EOF */ /* with persistent side effects. */ +/* PRQA S 1503,1505,3408 EOF */ /* Is defined but not used. */ + +/* =========================================== Includes =========================================== */ +#include "device_register.h" +#if SYSTEM_USE_CKGEN +#include "ckgen_drv.h" +#endif + +/* ============================================ Define ============================================ */ +/** @brief Standby retention base address. */ +#define SRAM_RETENTION_BASE (SRAM_U_START_ADDRESS - SRAM_RETENTION_SIZE) + +/* =========================================== Typedef ============================================ */ + +/* ========================================== Variables =========================================== */ +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; /* System/core clock */ + +volatile uint8_t s_disIrqReqTimes = 0U; +volatile uint8_t s_disIrqFltTimes = 0U; +/* ==================================== Functions declaration ===================================== */ +/* Externals declaration */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +extern uint32_t __Vectors; +#endif + +/* ====================================== Functions define ======================================== */ +/*! + * @brief Initialize SPLL then set system clock to the SPLL clock + * (just support SPLL refer clock 4/8/12/16/30MHz, others need to modify). + * + * @param[in] refClk: 0: HSI clock, 1: HSE clock + * @param[in] freq: SPLL out frequency (16 - 120) + * @return status 0: success others: error + */ +uint32_t SetSysClkToSPLL(uint8_t refClk, uint8_t freq) +{ + uint32_t ret = 0U, status, outFreq = freq; + uint32_t timeout = 100000U, posdiv, fbkdiv, prediv; + + if (outFreq > 120U) + { + outFreq = 120U; + } + if (outFreq < 16U) + { + outFreq = 16U; + } + + if (refClk != 0U) + { + /* Set XOSC bypass mode */ + MODIFY_REG32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Msk, SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Pos, 0U); + /* XOSC enable */ + SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_HSEEN_Msk); + do + { + status = READ_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_RDY_Msk); + --timeout; + } while ((0U == status) && (timeout != 0U)); + + if (0U == timeout) + { + ret = 1U; + } + + /* SPLL configuration outFreq = (srcFreq / (prediv + 1)) * fbkdiv / (posdiv * 2) */ +#if (CKGEN_HSE_FREQ == 30000000U) /* For HSE frequency 30MHz */ + if (outFreq == 120U) + { + posdiv = 5U; + fbkdiv = 160U; + } + else if (outFreq == 96U) + { + posdiv = 5U; + fbkdiv = 128U; + } + else if (outFreq == 80U) + { + posdiv = 6U; + fbkdiv = 128U; + } + else /* Output frequency 48MHz */ + { + posdiv = 10U; + fbkdiv = 128U; + outFreq = 48U; + } + prediv = 3U; +#elif (CKGEN_HSE_FREQ == 16000000U) /* For HSE frequency 16MHz */ + if (outFreq > 64U) + { + posdiv = 4U; + fbkdiv = outFreq; + } + else if (outFreq > 32U) + { + posdiv = 8U; + fbkdiv = outFreq * 2U; + } + else + { + posdiv = 16U; + fbkdiv = outFreq * 4U; + } + prediv = 1U; +#elif (CKGEN_HSE_FREQ == 12000000U) /* For HSE frequency 12MHz */ + if (outFreq > 62U) + { + posdiv = 6U; + fbkdiv = outFreq; + } + else if (outFreq > 31U) + { + posdiv = 12U; + fbkdiv = outFreq * 2U; + } + else + { + posdiv = 24U; + fbkdiv = outFreq * 4U; + } + prediv = 0U; +#elif (CKGEN_HSE_FREQ == 4000000U) /* For HSE frequency 4MHz */ + if (outFreq > 64U) + { + posdiv = 4U; + fbkdiv = outFreq * 2; + } + else if (outFreq > 32U) + { + posdiv = 8U; + fbkdiv = outFreq * 4U; + } + else + { + posdiv = 16U; + fbkdiv = outFreq * 8U; + } + prediv = 0U; +#else /* For default HSE 8MHz */ + if (outFreq > 64U) + { + posdiv = 4U; + fbkdiv = outFreq; + } + else if (outFreq > 32U) + { + posdiv = 8U; + fbkdiv = outFreq * 2U; + } + else + { + posdiv = 16U; + fbkdiv = outFreq * 4U; + } + prediv = 0U; +#endif + } + else + { + /* HSI enable */ + SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_HSI_EN_NORMAL_Msk); + timeout = 1000U; + do + { + status = READ_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_HSI_RDY_Msk); + --timeout; + } while ((0U == status) && (timeout != 0U)); + + if (0U == timeout) + { + ret = 2U; + } + + /* For HSI 8MHz */ + if (outFreq > 64U) + { + posdiv = 4U; + fbkdiv = outFreq; + } + else if (outFreq > 32U) + { + posdiv = 8U; + fbkdiv = outFreq * 2U; + } + else + { + posdiv = 16U; + fbkdiv = outFreq * 4U; + } + prediv = 0U; + } + + if (0U == ret) + { + CLEAR_BIT32(CKGEN->CTRL, CKGEN_CTRL_LOCK_Msk); + /* Configure SPLL */ + if (refClk != 0U) + { + SET_BIT32(CKGEN->CTRL, CKGEN_CTRL_PLL_REF_SEL_Msk); + } + else + { + CLEAR_BIT32(CKGEN->CTRL, CKGEN_CTRL_PLL_REF_SEL_Msk); + } + MODIFY_REG32(ANA->SPLL_CFG0, ANA_SPLL_CFG0_POSDIV_Msk, ANA_SPLL_CFG0_POSDIV_Pos, posdiv); + MODIFY_REG32(ANA->SPLL_CFG0, ANA_SPLL_CFG0_FBKDIV_Msk, ANA_SPLL_CFG0_FBKDIV_Pos, fbkdiv); + MODIFY_REG32(ANA->SPLL_CFG0, ANA_SPLL_CFG0_PREDIV_Msk, ANA_SPLL_CFG0_PREDIV_Pos, prediv); + MODIFY_REG32(ANA->SPLL_CFG1, ANA_SPLL_CFG1_LD_DLY_SEL_Msk, ANA_SPLL_CFG1_LD_DLY_SEL_Pos, 3U); + /* SPLL enable */ + SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_SPLL_EN_Msk); + timeout = 10000U; + do + { + status = READ_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_SPLL_RDY_Msk); + --timeout; + } while ((0U == status) && (timeout != 0U)); + + if (0U == timeout) + { + ret = 3U; + } + } + + if (0U == ret) + { + /* Unlock and set flash clock frequency */ + WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY1); + WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY2); + MODIFY_REG32(FLASH->CNFG, FLASH_CNFG_CLKFREQ_Msk, FLASH_CNFG_CLKFREQ_Pos, outFreq); + /* Switch system clock to spll */ + MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos, 3U); + /* Set divider, default sysdiv is 1 divider and busdiv is 2 divider */ + MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_DIV_Msk, CKGEN_CTRL_SYSCLK_DIV_Pos, 0U); + MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_BUS_CLK_DIV_RUN_Msk, CKGEN_CTRL_BUS_CLK_DIV_RUN_Pos, 1U); + /* Check current system clock */ + if (3U != ((CKGEN->CTRL & CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk) >> CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos)) + { + ret = 4U; + } + } + + return ret; +} + +/*! + * @brief Initialize VHSI then set system clock to the VHSI clock. + * + * @param[in] none + * @return status 0: success others: error + */ +uint32_t SetSysClkToVHSI(void) +{ + uint32_t ret = 0U, status, timeout = 100U; + + /* VHSI enable */ + SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_VHSI_EN_Msk); + do + { + status = READ_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_VHSI_RDY_Msk); + --timeout; + } while ((0U == status) && (timeout != 0U)); + + if (0U == timeout) + { + ret = 1U; + } + + if (0U == ret) + { + CLEAR_BIT32(CKGEN->CTRL, CKGEN_CTRL_LOCK_Msk); + /* Unlock and set flash clock frequency */ + WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY1); + WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY2); + MODIFY_REG32(FLASH->CNFG, FLASH_CNFG_CLKFREQ_Msk, FLASH_CNFG_CLKFREQ_Pos, 48U); + /* Switch system clock to vhsi */ + MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos, 0U); + /* Set divider, default sysdiv is 1 divider and busdiv is 2 divider */ + MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_DIV_Msk, CKGEN_CTRL_SYSCLK_DIV_Pos, 0U); + MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_BUS_CLK_DIV_RUN_Msk, CKGEN_CTRL_BUS_CLK_DIV_RUN_Pos, 1U); + /* Check current system clock */ + if (0U != ((CKGEN->CTRL & CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk) >> CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos)) + { + ret = 2U; + } + } + + return ret; +} + +/*! + * @brief Initialize HSE then set system clock to the HSE clock. + * + * @param[in] bypass: 0: disable, 1: enable + * @return status 0: success others: error + */ +uint32_t SetSysClkToHSE(uint8_t bypass) +{ + uint32_t ret = 0U, status, timeout = 100000U; + + /* Set XOSC bypass mode */ + if (bypass != 0U) + { + SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Msk); + } + else + { + CLEAR_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Msk); + } + /* XOSC enable */ + SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_HSEEN_Msk); + do + { + status = READ_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_XOSC_RDY_Msk); + --timeout; + } while ((0U == status) && (timeout != 0U)); + + if (0U == timeout) + { + ret = 1U; + } + + if (0U == ret) + { + CLEAR_BIT32(CKGEN->CTRL, CKGEN_CTRL_LOCK_Msk); + /* Unlock and set flash clock frequency */ + WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY1); + WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY2); + MODIFY_REG32(FLASH->CNFG, FLASH_CNFG_CLKFREQ_Msk, FLASH_CNFG_CLKFREQ_Pos, CKGEN_HSE_FREQ / 1000000U); + /* Switch system clock to hse */ + MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos, 1U); + /* Set divider, default sysdiv is 1 divider and busdiv is 2 divider */ + MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_DIV_Msk, CKGEN_CTRL_SYSCLK_DIV_Pos, 0U); + MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_BUS_CLK_DIV_RUN_Msk, CKGEN_CTRL_BUS_CLK_DIV_RUN_Pos, 1U); + /* Check current system clock */ + if (1U != ((CKGEN->CTRL & CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk) >> CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos)) + { + ret = 2U; + } + } + + return ret; +} + +/*! + * @brief Initialize HSI then set system clock to the HSI clock. + * + * @param[in] none + * @return status 0: success others: error + */ +uint32_t SetSysClkToHSI(void) +{ + uint32_t ret = 0U, status, timeout = 100U; + + /* HSI enable */ + SET_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_HSI_EN_NORMAL_Msk); + do + { + status = READ_BIT32(SPM->PWR_MGR_CFG1, SPM_PWR_MGR_CFG1_HSI_RDY_Msk); + --timeout; + } while ((0U == status) && (timeout != 0U)); + + if (0U == timeout) + { + ret = 1U; + } + + if (0U == ret) + { + CLEAR_BIT32(CKGEN->CTRL, CKGEN_CTRL_LOCK_Msk); + /* Unlock and set flash clock frequency */ + WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY1); + WRITE_REG32(FLASH->KEYUNLK, FLASH_UNLOCK_KEY2); + MODIFY_REG32(FLASH->CNFG, FLASH_CNFG_CLKFREQ_Msk, FLASH_CNFG_CLKFREQ_Pos, 8U); + /* Switch system clock to hsi */ + MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk, CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos, 2U); + /* Set divider, default sysdiv is 1 divider and busdiv is 2 divider */ + MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_SYSCLK_DIV_Msk, CKGEN_CTRL_SYSCLK_DIV_Pos, 0U); + MODIFY_REG32(CKGEN->CTRL, CKGEN_CTRL_BUS_CLK_DIV_RUN_Msk, CKGEN_CTRL_BUS_CLK_DIV_RUN_Pos, 1U); + /* Check current system clock */ + if (2U != ((CKGEN->CTRL & CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk) >> CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos)) + { + ret = 2U; + } + } + + return ret; +} + +/* PRQA S 3408 ++ */ +/*! + * @brief Get MCU CPUID. + * + * @param[in] none + * @return MCU CPUID + */ +uint32_t GetCPUID(void) +{ + return SCB->CPUID; +} +/* PRQA S 3408 -- */ + +/*! + * @brief Get UUID from device. + * + * @param[out] uuidBuffer: UUID buffer + * @return none + */ +void GetUUID(uint32_t *uuidBuffer) +{ +#define UUID_BASE_ADDRESS 0x00201800U + + uint32_t i; + + if (uuidBuffer != NULL) + { + for (i = 0U; i < 4U; i++) + { + uuidBuffer[i] = (*(__IO uint32_t *)(UUID_BASE_ADDRESS + (i * 4U))); + } + } +} + +/*! + * @brief Setup the microcontroller system. Initialize the System. + * + * @param[in] none + * @return none + */ +void SystemInit(void) +{ + /* Sram L&U ECC read enable */ +#if (SRAM_ECC_READ_ENABLE) + MCM->MLMDR0 |= MCM_MLMDR0_LREEN_Msk | MCM_MLMDR0_UREEN_Msk; + /* Sram ECC 2bit error reset disable */ +#if !(SRAM_ECC_ERR_RST_ENABLE) + CKGEN->RCM_EN &= ~CKGEN_RCM_EN_ECC2_ERR_RST_EN_Msk; +#endif +#endif + + /* Set CP10 and CP11 Full Access */ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << (10U * 2U)) | (3U << (11U * 2U))); +#endif + + /* Disable watchdog */ +#if (WDG_DISABLE) +#define WDG_UNLOCK_VALUE1 0xE064D987U +#define WDG_UNLOCK_VALUE2 0x868A8478U + WDG->CNT = (uint32_t)WDG_UNLOCK_VALUE1; + WDG->CNT = (uint32_t)WDG_UNLOCK_VALUE2; + WDG->CS0 &= ~WDG_CS0_EN_Msk; +#endif + + /* Relocate vector table */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if 0//NOT_INIT_SRAM_AFTER_RESET + /* Clear reset status, user can clear status in main when user need to read the reset status */ + CKGEN->RCM_STATUS |= CKGEN_RCM_STATUS_RST_STATUS_CLR_Msk; +#endif +} + +/*! + * @brief Initialize the SRAM to value. + * + * @param[in] Start: Main stack start address. + * @param[in] End: Main stack end address. + * @param[in] Val: Main stack end address. + * @return none + */ +/** @brief Initialize RAM from [start] to [end] with [val]. */ +static void SystemInitRamInternal(uint32_t Start, uint32_t End, uint32_t Val) +{ + uint32_t Addr = Start; + + while (Addr < End) + { + *(__IO uint32_t *)(Addr) = Val; + *(__IO uint32_t *)(Addr + 4U) = Val; + Addr += 8U; + } +} + +/*! + * @brief Initialize the SRAM to 0 for ECC. + * + * @param[in] StackBase: Main stack start address. + * @param[in] StackEnd: Main stack end address. + * @return none + */ +void InitSram(uint32_t StackBase, uint32_t StackEnd) +{ +#if NOT_INIT_SRAM_AFTER_RESET + /* When the status is power on, lvr or standby wakeup, init SRAM */ + if ((0U == (CKGEN->RCM_STATUS & (CKGEN_RCM_STATUS_POR_RST_FLAG_Msk | CKGEN_RCM_STATUS_LVR_RST_FLAG_Msk))) + && (0U == (SPM->STB_WP_STATUS & 0x1FFFFU))) + { + return; + } +#endif + + /* Initialize SRAM. */ + if (0U == (SPM->STB_WP_STATUS & 0x1FFFFU)) /* POR. */ + { + SystemInitRamInternal(SRAM_L_START_ADDRESS, StackBase, 0U); + SystemInitRamInternal(StackEnd, SRAM_U_END_ADDRESS, 0U); + } + else /* Standby wakeup skip the retention SRAM. */ + { + if (StackEnd <= SRAM_RETENTION_BASE) + { /* Stack locate in SRAM_L but not in retention. */ + SystemInitRamInternal(SRAM_L_START_ADDRESS, StackBase, 0U); + SystemInitRamInternal(StackEnd, SRAM_RETENTION_BASE, 0U); + SystemInitRamInternal(SRAM_U_START_ADDRESS, SRAM_U_END_ADDRESS, 0U); + } + else if (StackBase >= SRAM_U_START_ADDRESS) + { /* Stack locate in SRAM_U. */ + SystemInitRamInternal(SRAM_L_START_ADDRESS, SRAM_RETENTION_BASE, 0U); + SystemInitRamInternal(SRAM_U_START_ADDRESS, StackBase, 0U); + SystemInitRamInternal(StackEnd, SRAM_U_END_ADDRESS, 0U); + } + else if ((StackBase < SRAM_RETENTION_BASE) && (StackEnd > SRAM_RETENTION_BASE)) + { /* Stack location in SRAM_L and retention. */ + SystemInitRamInternal(SRAM_L_START_ADDRESS, StackBase, 0U); + SystemInitRamInternal(SRAM_U_START_ADDRESS, SRAM_U_END_ADDRESS, 0U); + } + else if ((StackBase < SRAM_U_START_ADDRESS) && (StackEnd > SRAM_U_START_ADDRESS)) + { /* Stack location in SRAM_U and retention. */ + SystemInitRamInternal(SRAM_L_START_ADDRESS, SRAM_RETENTION_BASE, 0U); + SystemInitRamInternal(StackEnd, SRAM_U_END_ADDRESS, 0U); + } + else + { /* Stack location in retention fullly. */ + SystemInitRamInternal(SRAM_L_START_ADDRESS, SRAM_RETENTION_BASE, 0U); + SystemInitRamInternal(SRAM_U_START_ADDRESS, SRAM_U_END_ADDRESS, 0U); + } + } + + /* Initialize FlexRAM if not used by CSE. */ + if (READ_BIT32(FLASH->PART, FLASH_PART_EPART_Msk) == FLASH_PART_EPART_Msk) + { + SystemInitRamInternal(FLEXRAM_BASE_ADDRESS, (FLEXRAM_BASE_ADDRESS + FLEX_RAM_SIZE), 0U); + } +} + +/*! + * @brief Update system clock frequence. + * + * @param[in] none + * @return none + */ +void SystemCoreClockUpdate(void) +{ +#if SYSTEM_USE_CKGEN + (void)CKGEN_DRV_GetFreq(CORE_CLK, &SystemCoreClock); +#else + uint32_t runMode, clkSrc, sysDiv, prediv, fbkdiv, postdiv, srcFreq; + + runMode = SPM->STATUS & SPM_STATUS_CURR_POWER_MODE_Msk; + if (1U == runMode) /* VLPR mode */ + { + sysDiv = (CKGEN->CTRL & CKGEN_CTRL_SYSCLK_DIV_VLPR_Msk) >> CKGEN_CTRL_SYSCLK_DIV_VLPR_Pos; + srcFreq = CKGEN_HSI_FREQ; + } + else /* RUN mode */ + { + sysDiv = (CKGEN->CTRL & CKGEN_CTRL_SYSCLK_DIV_Msk) >> CKGEN_CTRL_SYSCLK_DIV_Pos; + clkSrc = (CKGEN->CTRL & CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk) >> CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos; + switch (clkSrc) + { + case 1U: /* HSE clock, user define */ + srcFreq = CKGEN_HSE_FREQ; + break; + + case 2U: /* HSI clock */ + srcFreq = CKGEN_HSI_FREQ; + break; + + case 3U: /* SPLL clock */ + prediv = (ANA->SPLL_CFG0 & ANA_SPLL_CFG0_PREDIV_Msk) >> ANA_SPLL_CFG0_PREDIV_Pos; + fbkdiv = (ANA->SPLL_CFG0 & ANA_SPLL_CFG0_FBKDIV_Msk) >> ANA_SPLL_CFG0_FBKDIV_Pos; + postdiv = (ANA->SPLL_CFG0 & ANA_SPLL_CFG0_POSDIV_Msk) >> ANA_SPLL_CFG0_POSDIV_Pos; + /* Get reference clock */ + if (0U == ((CKGEN->CTRL & CKGEN_CTRL_PLL_REF_SEL_Msk) >> CKGEN_CTRL_PLL_REF_SEL_Pos)) + { + srcFreq = CKGEN_HSI_FREQ; + } + else + { + srcFreq = CKGEN_HSE_FREQ; + } + /* Calculate SPLL frequency */ + if (postdiv != 0U) + { + srcFreq = (srcFreq / (prediv + 1U)) * fbkdiv / (postdiv * 2U); + } + break; + + default: /* VHSI clock */ + srcFreq = CKGEN_VHSI_FREQ; + break; + } + } + + SystemCoreClock = srcFreq / (sysDiv + 1U); +#endif +} + +/*! + * @brief Enable NMI, after set pinmux. + * + * @param[in] enable: enable state + * @return none + */ +void EnableNMI(uint8_t enable) +{ + if (enable != 0U) + { + SET_BIT32(MCM->MNCR, MCM_MNCR_NMI_EN_Msk); + } + else + { + CLEAR_BIT32(MCM->MNCR, MCM_MNCR_NMI_EN_Msk); + } +} + +void nvic_system_reset(void) +{ + NVIC_SystemReset(); +} + + +/* ============================================= EOF ============================================== */