6937 lines
789 KiB
C
6937 lines
789 KiB
C
/*
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* Copyright Statement:
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*
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* This software/firmware and related documentation ("AutoChips Software") are
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* protected under relevant copyright laws. The information contained herein is
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* confidential and proprietary to AutoChips Inc. and/or its licensors. Without
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* the prior written permission of AutoChips inc. and/or its licensors, any
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* reproduction, modification, use or disclosure of AutoChips Software, and
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* information contained herein, in whole or in part, shall be strictly
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* prohibited.
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*
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* AutoChips Inc. (C) 2021. All rights reserved.
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*
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* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
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* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE")
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* RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
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* ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL
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* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
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* NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH
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* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
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* INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES
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* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
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* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
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* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS
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* SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE
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* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
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* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S
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* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE
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* RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE
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* AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
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* CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE.
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*
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* @file AC7840x.h
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* @brief CMSIS HeaderFile
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* @version 1.0
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* @date 02. June 2021
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* @note Generated by SVDConv V3.3.27 on Wednesday, 02.06.2021 14:09:31
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* from File 'ac7840x.svd',
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* last modified on Wednesday, 02.06.2021 06:05:59
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*/
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/** @addtogroup AutoChips
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* @{
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*/
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/** @addtogroup AC7840x
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* @{
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*/
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#ifndef AC7840X_H
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#define AC7840X_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup Configuration_of_CMSIS
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* @{
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*/
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/* PRQA S 3630 EOF */ /* The implementation of the object should be hidden, Maybe use by app. */
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/* PRQA S 1535 EOF */ /* A project should not contain unused type declarations, Maybe use by app. */
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/* PRQA S 0791 EOF */ /* Macro identifiers shall be distinct */
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/* PRQA S 0602 EOF */
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/* PRQA S 0603 EOF */
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/* =========================================================================================================================== */
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/* ================ Interrupt Number Definition ================ */
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/* =========================================================================================================================== */
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typedef enum {
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/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
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NonMaskableInt_IRQn = -14, /*!< -14 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
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/* =========================================== AC7840x Specific Interrupt Numbers ========================================== */
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DMA0_CHANNEL0_IRQn = 0, /*!< 0 DMA0 channel 0 interrupt */
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DMA0_CHANNEL1_IRQn = 1, /*!< 1 DMA0 channel 1 interrupt */
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DMA0_CHANNEL2_IRQn = 2, /*!< 2 DMA0 channel 2 interrupt */
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DMA0_CHANNEL3_IRQn = 3, /*!< 3 DMA0 channel 3 interrupt */
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DMA0_CHANNEL4_IRQn = 4, /*!< 4 DMA0 channel 4 interrupt */
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DMA0_CHANNEL5_IRQn = 5, /*!< 5 DMA0 channel 5 interrupt */
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DMA0_CHANNEL6_IRQn = 6, /*!< 6 DMA0 channel 6 interrupt */
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DMA0_CHANNEL7_IRQn = 7, /*!< 7 DMA0 channel 7 interrupt */
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DMA0_CHANNEL8_IRQn = 8, /*!< 8 DMA0 channel 8 interrupt */
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DMA0_CHANNEL9_IRQn = 9, /*!< 9 DMA0 channel 9 interrupt */
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DMA0_CHANNEL10_IRQn = 10, /*!< 10 DMA0 channel 10 interrupt */
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DMA0_CHANNEL11_IRQn = 11, /*!< 11 DMA0 channel 11 interrupt */
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DMA0_CHANNEL12_IRQn = 12, /*!< 12 DMA0 channel 12 interrupt */
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DMA0_CHANNEL13_IRQn = 13, /*!< 13 DMA0 channel 13 interrupt */
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DMA0_CHANNEL14_IRQn = 14, /*!< 14 DMA0 channel 14 interrupt */
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DMA0_CHANNEL15_IRQn = 15, /*!< 15 DMA0 channel 15 interrupt */
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PORTA_IRQn = 16, /*!< 16 PORTA interrupt */
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PORTB_IRQn = 17, /*!< 17 PORTB interrupt */
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PORTC_IRQn = 18, /*!< 18 PORTC interrupt */
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PORTD_IRQn = 19, /*!< 19 PORTD interrupt */
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PORTE_IRQn = 20, /*!< 20 PORTE interrupt */
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UART0_IRQn = 21, /*!< 21 UART0 interrupt */
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UART1_IRQn = 22, /*!< 22 UART1 interrupt */
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UART2_IRQn = 23, /*!< 23 UART2 interrupt */
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UART3_IRQn = 24, /*!< 24 UART3 interrupt */
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SPI0_IRQn = 27, /*!< 27 SPI0 interrupt */
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SPI1_IRQn = 28, /*!< 28 SPI1 interrupt */
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SPI2_IRQn = 29, /*!< 29 SPI2 interrupt */
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I2C0_IRQn = 31, /*!< 31 I2C0 interrupt */
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EIO_IRQn = 33, /*!< 33 EIO interrupt */
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CAN0_IRQn = 34, /*!< 34 CAN0 interrupt */
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CAN0_WAKEUP_IRQn = 35, /*!< 35 CAN0 wakeup interrupt */
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CAN1_IRQn = 36, /*!< 36 CAN1 interrupt */
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CAN1_WAKEUP_IRQn = 37, /*!< 37 CAN1 wakeup interrupt */
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CAN2_IRQn = 38, /*!< 38 CAN2 interrupt */
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CAN2_WAKEUP_IRQn = 39, /*!< 39 CAN2 wakeup interrupt */
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CAN3_IRQn = 40, /*!< 40 CAN3 interrupt */
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CAN3_WAKEUP_IRQn = 41, /*!< 41 CAN3 wakeup interrupt */
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PDT0_IRQn = 46, /*!< 46 PDT0 interrupt */
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PDT1_IRQn = 47, /*!< 47 PDT1 interrupt */
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ADC0_IRQn = 48, /*!< 48 ADC0 interrupt */
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ADC1_IRQn = 49, /*!< 49 ADC1 interrupt */
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ACMP0_IRQn = 50, /*!< 50 ACMP0 interrupt */
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WDG_IRQn = 51, /*!< 51 WDG interrupt */
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EWDG_IRQn = 52, /*!< 52 EWDG interrupt */
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MCM_IRQn = 53, /*!< 53 MCM interrupt */
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LVD_IRQn = 54, /*!< 54 LVD interrupt */
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SPM_IRQn = 55, /*!< 55 SPM interrupt */
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RCM_IRQn = 56, /*!< 56 RCM interrupt */
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PWM0_OVERFLOW_IRQn = 57, /*!< 57 PWM0 Overflow interrupt */
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PWM0_CHANNEL_IRQn = 58, /*!< 58 PWM0 Channel interrupt */
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PWM0_FAULT_IRQn = 59, /*!< 59 PWM0 Fault interrupt */
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PWM1_OVERFLOW_IRQn = 60, /*!< 60 PWM1 Overflow interrupt */
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PWM1_CHANNEL_IRQn = 61, /*!< 61 PWM1 Channel interrupt */
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PWM1_FAULT_IRQn = 62, /*!< 62 PWM1 Fault interrupt */
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PWM2_OVERFLOW_IRQn = 63, /*!< 63 PWM2 Overflow interrupt */
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PWM2_CHANNEL_IRQn = 64, /*!< 64 PWM2 Channel interrupt */
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PWM2_FAULT_IRQn = 65, /*!< 65 PWM2 Fault interrupt */
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PWM3_OVERFLOW_IRQn = 66, /*!< 66 PWM3 Overflow interrupt */
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PWM3_CHANNEL_IRQn = 67, /*!< 67 PWM3 Channel interrupt */
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PWM3_FAULT_IRQn = 68, /*!< 68 PWM3 Fault interrupt */
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PWM4_OVERFLOW_IRQn = 69, /*!< 69 PWM4 Overflow interrupt */
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PWM4_CHANNEL_IRQn = 70, /*!< 70 PWM4 Channel interrupt */
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PWM4_FAULT_IRQn = 71, /*!< 71 PWM4 Fault interrupt */
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PWM5_OVERFLOW_IRQn = 72, /*!< 72 PWM5 Overflow interrupt */
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PWM5_CHANNEL_IRQn = 73, /*!< 73 PWM5 Channel interrupt */
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PWM5_FAULT_IRQn = 74, /*!< 74 PWM5 Fault interrupt */
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RTC_IRQn = 81, /*!< 81 RTC interrupt */
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PCT_IRQn = 82, /*!< 82 PCT interrupt */
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TIMER_CHANNEL0_IRQn = 83, /*!< 83 TIMER channel 0 interrupt */
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TIMER_CHANNEL1_IRQn = 84, /*!< 84 TIMER channel 1 interrupt */
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TIMER_CHANNEL2_IRQn = 85, /*!< 85 TIMER channel 2 interrupt */
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TIMER_CHANNEL3_IRQn = 86, /*!< 86 TIMER channel 3 interrupt */
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CSE_IRQn = 87, /*!< 87 CSE interrupt */
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FLASH_ECC_IRQn = 88, /*!< 88 FLASH ECC 2-bit interrupt */
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FLASH_IRQn = 89, /*!< 89 FLASH command complete interrupt */
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FLASH_COLLISION_IRQn = 90, /*!< 90 FLASH collision interrupt */
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ECC_1BIT_ERROR_IRQn = 91, /*!< 91 ECC 1bit error interrupt */
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ECC_2BIT_ERROR_IRQn = 92, /*!< 92 ECC 2bit error interrupt */
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MAX_IRQn = 93 /*!< 93 Max interrupt */
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} IRQn_Type;
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/**
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* @brief setting bits macro.
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*/
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#ifndef SET_BIT32
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#define SET_BIT32(reg, mask) ((reg) |= (uint32_t)(mask))
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#endif
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/**
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* @brief clearing bits macro.
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*/
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#ifndef CLEAR_BIT32
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#define CLEAR_BIT32(reg, mask) ((reg) &= (~((uint32_t)(mask))))
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#endif
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/**
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* @brief read bits macro.
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*/
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#ifndef READ_BIT32
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#define READ_BIT32(reg, mask) ((reg) & ((uint32_t)(mask)))
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#endif
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/**
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* @brief write register macro.
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*/
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#ifndef WRITE_REG32
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#define WRITE_REG32(reg, value) ((reg) = (uint32_t)(value))
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#endif
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/**
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* @brief clear bits and set with new value.
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*/
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#ifndef MODIFY_REG32
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#define MODIFY_REG32(reg, mask, pos, value) (WRITE_REG32((reg), (((reg) & (~((uint32_t)(mask)))) | (((uint32_t)(value)) << (pos)))))
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#endif
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/**
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* @brief read register parameter macro.
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*/
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#ifndef READ_PARAM32
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#define READ_PARAM32(reg, mask, pos) (((reg) & ((uint32_t)(mask))) >> (pos))
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#endif
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/**
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* @brief read 32 bits memory macro.
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*/
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#ifndef READ_MEM32
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#define READ_MEM32(address) (*(volatile uint32_t *)(address))
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#endif
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/**
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* @brief write 32 bits memory macro.
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*/
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#ifndef WRITE_MEM32
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#define WRITE_MEM32(address, value) ((*(volatile uint32_t *)(address))= (uint32_t)(value))
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#endif
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/**
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* @brief clear bits and set with new value for memory.
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*/
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#ifndef MODIFY_MEM32
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#define MODIFY_MEM32(address, mask, pos, value) (WRITE_MEM32((address), ((READ_MEM32(address) & (~((uint32_t)(mask)))) | (((uint32_t)(value)) << (pos)))))
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#endif
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#include <stdint.h>
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#include <stdio.h>
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#include <stdbool.h>
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/* PRQA S 1535,2052,4548 ++ */ /* This type maybe use by app. */
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/**
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* @brief global enumeration.
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*/
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typedef enum {DISABLE = 0U, ENABLE = !DISABLE} ACTION_Type;
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typedef enum {ERROR = 0U, SUCCESS = !ERROR} ERROR_Type;
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/* PRQA S 1535,2052,4548 -- */
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/* =========================================================================================================================== */
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/* ================ Processor and Core Peripheral Section ================ */
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/* =========================================================================================================================== */
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/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
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#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
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#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
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#define __MPU_PRESENT 0 /*!< MPU present */
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#define __FPU_PRESENT 1 /*!< FPU present */
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/** @} */ /* End of group Configuration_of_CMSIS */
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#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
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#include "device_status.h" /*!< device status */
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#include "system_ac7840x.h" /*!< AC7840x System */
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#ifndef __IM /*!< Fallback for older CMSIS versions */
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#define __IM __I
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#endif
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#ifndef __OM /*!< Fallback for older CMSIS versions */
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#define __OM __O
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#endif
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#ifndef __IOM /*!< Fallback for older CMSIS versions */
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#define __IOM __IO
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#endif
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/* =========================================================================================================================== */
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/* ================ Device Specific Peripheral Section ================ */
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/* =========================================================================================================================== */
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/* PRQA S 3638 ++ */
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/* --------------------------------------------- section using anonymous unions ------------------------------------------- */
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#if defined(__CC_ARM)
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#pragma anon_unions
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#elif defined(CCARM__)
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#pragma language=extended
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#elif defined (__ICCARM__)
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/* anonymous unions are enabled by default */
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#elif (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
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/* anonymous unions are enabled by default */
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined(__ghs__)
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/* anonymous unions are enabled by default */
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#elif defined(__TASKING__)
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#pragma warning 586
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#else
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#error Not supported compiler type
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#endif
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/* PRQA S 3638 -- */
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/** @addtogroup Device_Peripheral_peripherals
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* @{
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*/
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/* =========================================================================================================================== */
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/* ================ MCM ================ */
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/* =========================================================================================================================== */
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/**
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* @brief Core Platform Miscellaneous Control Module (MCM)
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*/
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typedef struct { /*!< (@ 0xE008000C) MCM Structure */
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__IOM uint32_t MCPCR; /*!< (@ 0x00000000) MCM Core Platform Control Register */
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__IOM uint32_t MISCR; /*!< (@ 0x00000004) MCM Interrupt Status and Control Register */
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__IM uint32_t RESERVED[251];
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__IOM uint32_t MLMDR0; /*!< (@ 0x000003F4) MCM Local MCM Local Memory Descriptor Register0 */
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__IM uint32_t MBIST; /*!< (@ 0x000003F8) MCM Local Memory BIST Register */
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__IOM uint32_t MLMDR1; /*!< (@ 0x000003FC) MCM Local MCM Local Memory Descriptor Register1 */
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__IOM uint32_t LMPECR; /*!< (@ 0x00000400) MCM Local Memory Cache ECC Enable Control Register */
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__IOM uint32_t LMPEIR; /*!< (@ 0x00000404) MCM Local Memory Cache ECC Error Status Register */
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__IM uint32_t LMFAR; /*!< (@ 0x00000408) MCM Local Memory Cache ECC Error Address Register */
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__IOM uint32_t MCCR; /*!< (@ 0x0000040C) MCM Cache Control Register */
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__IM uint32_t RESERVED1[25];
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__IOM uint32_t MNCR; /*!< (@ 0x00000474) MCM NMI Control Register */
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} MCM_Type; /*!< Size = 1144 (0x478) */
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/* =========================================================================================================================== */
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/* ================ MPU ================ */
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/* =========================================================================================================================== */
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/**
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* @brief Memory protection unit (MPU)
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*/
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/* MPU - Size of Registers Arrays */
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#define MPU_EAR_EDR_COUNT (3UL)
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#define MPU_RGD_COUNT (8UL)
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#define MPU_RGDAAC_COUNT (8UL)
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typedef struct { /*!< (@ 0x40006000) MPU Structure */
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__IOM uint32_t CESR; /*!< (@ 0x00000000) Control/Error Status Register */
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__IOM uint32_t EAR[MPU_EAR_EDR_COUNT];
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__IOM uint32_t EDR[MPU_EAR_EDR_COUNT];
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__IOM uint32_t MPID;
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__IOM uint32_t WORD0_RGD[MPU_RGD_COUNT];
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__IOM uint32_t WORD1_RGD[MPU_RGD_COUNT];
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__IOM uint32_t WORD2_RGD[MPU_RGD_COUNT];
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__IOM uint32_t WORD3_RGD[MPU_RGD_COUNT];
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__IOM uint32_t RESERVED[216];
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__IOM uint32_t RGDAAC[MPU_RGDAAC_COUNT]; /*!< (@ 0x0000008C) Region Descriptor Alternate Access Control n */
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} MPU_Type; /*!< Size = 1056 (0x420) */
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/* =========================================================================================================================== */
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/* ================ CKGEN ================ */
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/* =========================================================================================================================== */
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/**
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* @brief Clock Generator (CKGEN)
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*/
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typedef struct { /*!< (@ 0x40000000) CKGEN Structure */
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__IOM uint32_t CTRL; /*!< (@ 0x00000000) CKGEN Control Register */
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__IOM uint32_t LP_CLK_MUX; /*!< (@ 0x00000004) RTC LSI Clock Mux */
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__IOM uint32_t PERI_CLK_EN0; /*!< (@ 0x00000008) Periph Clock Enable Control 0 */
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__IOM uint32_t PERI_CLK_EN1; /*!< (@ 0x0000000C) Periph Clock Enable Control 1 */
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__IOM uint32_t PERI_CLK_EN2; /*!< (@ 0x00000010) Periph Clock Enable Control 2 */
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__IOM uint32_t RCM_CTRL; /*!< (@ 0x00000014) MCU Reset Control */
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__IOM uint32_t RCM_EN; /*!< (@ 0x00000018) MCU Reset Enable Control */
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__IOM uint32_t RCM_STATUS; /*!< (@ 0x0000001C) MCU Reset Status */
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__IOM uint32_t PERI_SFT_RST0; /*!< (@ 0x00000020) Periph Software Reset Control 0 */
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__IOM uint32_t PERI_SFT_RST1; /*!< (@ 0x00000024) Periph Software Reset Control 1 */
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__IOM uint32_t PERI_SFT_RST2; /*!< (@ 0x00000028) Periph Software Reset Control 2 */
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__IOM uint32_t CLK_DIV1; /*!< (@ 0x0000002C) Clock Divider 1 */
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__IOM uint32_t CLK_DIV2; /*!< (@ 0x00000030) Clock Divider 2 */
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__IOM uint32_t PERI_CLK_MUX0; /*!< (@ 0x00000034) Peripheral Clock MUX0 Register */
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__IOM uint32_t PERI_CLK_MUX1; /*!< (@ 0x00000038) Peripheral Clock MUX1 Register */
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__IOM uint32_t PERI_CLK_MUX2; /*!< (@ 0x0000003C) Peripheral Clock MUX2 Register */
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__IOM uint32_t PERI_CLK_MUX3; /*!< (@ 0x00000040) Peripheral Clock MUX3 Register */
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__IM uint32_t RESERVED;
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__IOM uint32_t CLK_OUT_CFG; /*!< (@ 0x00000048) Clock Out Configure */
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__IOM uint32_t PERI_CLK_DIV; /*!< (@ 0x0000004C) Peripheral Clock Divider */
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} CKGEN_Type; /*!< Size = 80 (0x50) */
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/* =========================================================================================================================== */
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/* ================ PBR ================ */
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/* =========================================================================================================================== */
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/**
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* @brief Peripheral Bridge (PBR)
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*/
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typedef struct { /*!< (@ 0x4008A000) PBR Structure */
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__IOM uint32_t MPR_CORE; /*!< (@ 0x00000000) Master Core Privilege Configure Register */
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__IOM uint32_t MPR_DEBUG; /*!< (@ 0x00000004) Master Debugger Privilege Configure Register */
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__IOM uint32_t MPR_DMA; /*!< (@ 0x00000008) Master DMA Privilege Configure Register */
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__IM uint32_t RESERVED;
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__IOM uint32_t PACRA; /*!< (@ 0x00000010) Peripheral Access Control Register A */
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__IOM uint32_t PACRB; /*!< (@ 0x00000014) Peripheral Access Control Register B */
|
|
__IM uint32_t RESERVED1[2];
|
|
__IOM uint32_t PACRC; /*!< (@ 0x00000020) Peripheral Access Control Register C */
|
|
__IOM uint32_t PACRD; /*!< (@ 0x00000024) Peripheral Access Control Register D */
|
|
__IOM uint32_t PACRE; /*!< (@ 0x00000028) Peripheral Access Control Register E */
|
|
__IM uint32_t RESERVED2;
|
|
__IOM uint32_t PACRF; /*!< (@ 0x00000030) Peripheral Access Control Register F */
|
|
__IOM uint32_t PACRG; /*!< (@ 0x00000034) Peripheral Access Control Register G */
|
|
} PBR_Type; /*!< Size = 56 (0x38) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ SPM ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief System Power Manage (SPM)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40008000) SPM Structure */
|
|
__IOM uint32_t PWR_MGR_CFG0; /*!< (@ 0x00000000) Power Manage Config Register 0 */
|
|
__IOM uint32_t PWR_MGR_CFG1; /*!< (@ 0x00000004) Power Manage Config Register 1 */
|
|
__IM uint32_t RESERVED;
|
|
__IM uint32_t PERIPH_SLEEP_ACK_STATUS; /*!< (@ 0x0000000C) Periph Sleep Ack Status Register */
|
|
__IOM uint32_t PERIPH_SLEEP_ACK_EN; /*!< (@ 0x00000010) Periph Sleep Ack Enable Register */
|
|
__IOM uint32_t STATUS; /*!< (@ 0x00000014) Status Register */
|
|
__IM uint32_t RESERVED2[4];
|
|
__IOM uint32_t STB_WP_EN; /*!< (@ 0x00000028) Standby Wakeup Enable Register */
|
|
__IOM uint32_t STB_WP_STATUS; /*!< (@ 0x0000002C) Standby Wakeup Status Register */
|
|
} SPM_Type; /*!< Size = 48 (0x30) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ GPIO ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* PRQA S 3630 ++ */ /* May be use by app. */
|
|
/**
|
|
* @brief General Purpose Input/Output (GPIO)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40084000) GPIO Structure */
|
|
__IOM uint32_t PODR; /*!< (@ 0x00000000) PORT Output Data Register */
|
|
__IOM uint32_t PSOR; /*!< (@ 0x00000004) PORT Set Output Register */
|
|
__IOM uint32_t PROR; /*!< (@ 0x00000008) PORT Reset Output Register */
|
|
__IOM uint32_t PIOR; /*!< (@ 0x0000000C) PORT Invert Output Register */
|
|
__IOM uint32_t PIDR; /*!< (@ 0x00000010) PORT Input Data Register */
|
|
__IOM uint32_t POER; /*!< (@ 0x00000014) PORT Output Enable Register */
|
|
__IOM uint32_t PIER; /*!< (@ 0x00000018) PORT Input Enable Register */
|
|
} GPIO_Type; /*!< Size = 28 (0x1c) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ PORT ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
#define PORT_PCR_COUNT (32UL) /*!< PORT - size of registers array */
|
|
|
|
/**
|
|
* @brief Pin Control and Interrupts (PORT)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40084200) PORT Structure */
|
|
__IOM uint32_t PCR[PORT_PCR_COUNT]; /*!< (@ 0x00000000~0x0000007C) Pin Control Register n */
|
|
__IM uint32_t RESERVED[8];
|
|
__IOM uint32_t ISFR; /*!< (@ 0x000000A0) Interrupt Status Flag Register */
|
|
__IM uint32_t RESERVED1[7];
|
|
__IOM uint32_t DFER; /*!< (@ 0x000000C0) Digital Filter Enable Register */
|
|
__IOM uint32_t DFCR; /*!< (@ 0x000000C4) Digital Filter Clock Register */
|
|
__IOM uint32_t DFWR; /*!< (@ 0x000000C8) Digital Filter Width Register */
|
|
} PORT_Type; /*!< Size = 204 (0xcc) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ CAN ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Controller Area Network (CAN)
|
|
*/
|
|
|
|
#define CAN_BUF_LENGTH (64 / 4) /*!< CAN buffer length */
|
|
|
|
/**
|
|
* @brief CAN receive buffer register define structure
|
|
*/
|
|
|
|
typedef struct
|
|
{
|
|
__IO uint32_t ID_ESI; /*!< [0:28]: Identifier (ID), [30]: Transmit time-stamp enable (TTSEN) */
|
|
/*!< [31]: Error state indicator (ESI) */
|
|
__IO uint32_t CTRL; /*!< [0:3]: Data length code (DLC), [4]: Bit rate switch (BRS) */
|
|
/*!< [5]: FD format indicator (FDF), [6]: Remote transmission request (RTR) */
|
|
/*!< [7]: Identifier extension (IDE), [12]: For lookback mode (TX) */
|
|
/*!< [13:15]: Kind of error (KOER) */
|
|
__IO uint32_t DATA[CAN_BUF_LENGTH]; /*!< Buffer data */
|
|
__IM uint32_t TS[2]; /*!< Receive or transmission time stamp */
|
|
} CAN_BufType;
|
|
|
|
typedef struct { /*!< (@ 0x40007800) CAN structure */
|
|
CAN_BufType RBUF; /*!< (@ 0x00000000) Receive buffer */
|
|
CAN_BufType TBUF; /*!< (@ 0x00000050) Transmit buffer */
|
|
__IOM uint32_t CTRL0; /*!< (@ 0x000000A0) Config state and transmit/receive control register 0 */
|
|
__IOM uint32_t CTRL1; /*!< (@ 0x000000A4) Interrupt enable and flag control register 1 */
|
|
__IOM uint32_t SBITRATE; /*!< (@ 0x000000A8) CAN normal bitrate configuration register */
|
|
__IOM uint32_t FBITRATE; /*!< (@ 0x000000AC) CAN FD data bitrate configuration register */
|
|
__IOM uint32_t ERRINFO; /*!< (@ 0x000000B0) Error type and error counter register */
|
|
__IOM uint32_t ACFCTRL0; /*!< (@ 0x000000B4) Acceptance filter control register 0 */
|
|
__IOM uint32_t ACFCTRL1; /*!< (@ 0x000000B8) Acceptance filter control register 1 */
|
|
__IOM uint32_t ACFCTRL2; /*!< (@ 0x000000BC) Acceptance filter control register 2 */
|
|
__IOM uint32_t ACF; /*!< (@ 0x000000C0) Acceptance code register */
|
|
__IOM uint32_t VERMEM; /*!< (@ 0x000000C4) Version and memory protection register */
|
|
__IOM uint32_t MEMES; /*!< (@ 0x000000C8) Memory error simulation register */
|
|
__IOM uint32_t WAKEUP; /*!< (@ 0x000000CC) Wakeup configuration register */
|
|
} CAN_Type; /*!< Size = 208 (0xd0) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ UART ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Universal Asynchronous Receiver/Transmitter (UART)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40018000) UART Structure */
|
|
__IOM uint32_t RBR; /*!< (@ 0x00000000) RX/TX Data Register */
|
|
__IOM uint32_t DIV_L; /*!< (@ 0x00000004) Divisor low 8 bits register */
|
|
__IOM uint32_t DIV_H; /*!< (@ 0x00000008) Divisor high 8 bits register */
|
|
__IOM uint32_t LCR0; /*!< (@ 0x0000000C) UART control register 0 */
|
|
__IOM uint32_t LCR1; /*!< (@ 0x00000010) UART control register 1 */
|
|
__IOM uint32_t FCR; /*!< (@ 0x00000014) FIFO Control Register */
|
|
__IOM uint32_t EFR; /*!< (@ 0x00000018) hardware flow control register */
|
|
__IOM uint32_t IER; /*!< (@ 0x0000001C) Interrupt Enable register */
|
|
__IOM uint32_t LSR0; /*!< (@ 0x00000020) Line Status Register 0 */
|
|
__IOM uint32_t LSR1; /*!< (@ 0x00000024) Line Status Register 1 */
|
|
__IOM uint32_t SMP_CNT; /*!< (@ 0x00000028) UART sample counter register */
|
|
__IOM uint32_t ADDR; /*!< (@ 0x0000002C) UART match address register */
|
|
__IOM uint32_t DATA; /*!< (@ 0x00000030) UART match data register */
|
|
__IOM uint32_t GUARD; /*!< (@ 0x00000034) UART guard time register */
|
|
__IM uint32_t RESERVED;
|
|
__IOM uint32_t SLEEP_EN; /*!< (@ 0x0000003C) UART sleep enable register */
|
|
__IOM uint32_t DMA_EN; /*!< (@ 0x00000040) UART DMA enable register */
|
|
__IOM uint32_t DIV_FRAC; /*!< (@ 0x00000044) Uart Fractional Divider Address */
|
|
__IOM uint32_t MTCHCR; /*!< (@ 0x00000048) Uart match fucntion enable */
|
|
__IOM uint32_t RS485CR; /*!< (@ 0x0000004C) Uart RS485 control register */
|
|
__IM uint32_t RESERVED1;
|
|
__IOM uint32_t CNTR; /*!< (@ 0x00000054) Uart Counter time delay in RS485 mode */
|
|
__IOM uint32_t IDLE; /*!< (@ 0x00000058) Uart IDLE register */
|
|
__IOM uint32_t LINCR; /*!< (@ 0x0000005C) LIN Control register */
|
|
__IOM uint32_t BRKLGH; /*!< (@ 0x00000060) LIN Break Length Select Register */
|
|
__IOM uint32_t PMIN0; /*!< (@ 0x00000064) IrDA mode pulse minimum pulse */
|
|
__IOM uint32_t PMIN1; /*!< (@ 0x00000068) IrDA mode pulse minimum pulse */
|
|
} UART_Type; /*!< Size = 108 (0x6c) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ I2C ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Inter-Integrated Circuit (I2C)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x4000E000) I2C Structure */
|
|
__IOM uint32_t ADDR0; /*!< (@ 0x00000000) Address Register 0 */
|
|
__IOM uint32_t ADDR1; /*!< (@ 0x00000004) Address register 1 */
|
|
__IOM uint32_t SAMPLE_CNT; /*!< (@ 0x00000008) SAMPLE CNT Register */
|
|
__IOM uint32_t STEP_CNT; /*!< (@ 0x0000000C) STEP CNT Register */
|
|
__IOM uint32_t CTRL0; /*!< (@ 0x00000010) Control Register 0 */
|
|
__IOM uint32_t CTRL1; /*!< (@ 0x00000014) Control Register 1 */
|
|
__IOM uint32_t CTRL2; /*!< (@ 0x00000018) Control Register 2 */
|
|
__IOM uint32_t CTRL3; /*!< (@ 0x0000001C) Control Register 3 */
|
|
__IOM uint32_t STATUS0; /*!< (@ 0x00000020) Status Register 0 */
|
|
__IOM uint32_t STATUS1; /*!< (@ 0x00000024) Status Register 1 */
|
|
__IOM uint32_t DGLCFG; /*!< (@ 0x00000028) Deglitch Configuration Register */
|
|
__IOM uint32_t DATA; /*!< (@ 0x0000002C) Data Register */
|
|
__IOM uint32_t STARTSTOP; /*!< (@ 0x00000030) START_STOP Register */
|
|
} I2C_Type; /*!< Size = 52 (0x34) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ SPI ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Serial Peripheral Interface (SPI)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x4000C000) SPI Structure */
|
|
__IOM uint32_t CFG0; /*!< (@ 0x00000000) SPI Configuration Register 0 */
|
|
__IOM uint32_t CFG1; /*!< (@ 0x00000004) SPI Configuration Register 1 */
|
|
__IOM uint32_t CMD; /*!< (@ 0x00000008) SPI Command Register */
|
|
__IOM uint32_t STATUS; /*!< (@ 0x0000000C) SPI Status Register */
|
|
__IOM uint32_t DATA; /*!< (@ 0x00000010) SPI Data Register */
|
|
__IOM uint32_t CFG2; /*!< (@ 0x00000014) SPI configuration register 2 */
|
|
__IM uint32_t RESERVED[2];
|
|
__IOM uint32_t DMV; /*!< (@ 0x00000020) SPI data match register */
|
|
} SPI_Type; /*!< Size = 36 (0x24) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ ANA ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Analog Control Registers (ANA)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40008800) ANA Structure */
|
|
__IM uint32_t RESERVED[20];
|
|
__IOM uint32_t ACMPDAC_CFG; /*!< (@ 0x00000050) ACMPDAC Configuration Register */
|
|
__IM uint32_t RESERVED1[3];
|
|
__IOM uint32_t AUXADC_CFG0; /*!< (@ 0x00000060) AUXADC Configuration Register0 */
|
|
__IOM uint32_t AUXADC_CFG1; /*!< (@ 0x00000064) AUXADC Configuration Register1 */
|
|
__IM uint32_t RESERVED2[2];
|
|
__IOM uint32_t AUXADC_CFG4; /*!< (@ 0x00000070) AUXADC Configuration Register4 */
|
|
__IOM uint32_t AUXADC_CFG5; /*!< (@ 0x00000074) AUXADC Configuration Register5 */
|
|
__IM uint32_t RESERVED3[18];
|
|
__IOM uint32_t SPLL_CFG0; /*!< (@ 0x000000C0) System PLL Config 0 */
|
|
__IOM uint32_t SPLL_CFG1; /*!< (@ 0x000000C4) System PLL Config 1 */
|
|
} ANA_Type; /*!< Size = 200 (0xc8) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ ADC ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
#define ADC_REGULAR_SEQ_NUM (24U)
|
|
#define ADC_INJECT_SEQ_NUM (4U)
|
|
#define ADC_SAMPLE_REG_NUM (4U)
|
|
|
|
/**
|
|
* @brief Analog to Digital Converter (ADC)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40003000) ADC Structure */
|
|
__IOM uint32_t STR; /*!< (@ 0x00000000) ADC status Register */
|
|
__IOM uint32_t CTRL0; /*!< (@ 0x00000004) ADC Control Register 0 */
|
|
__IOM uint32_t CTRL1; /*!< (@ 0x00000008) ADC Control Register 1 */
|
|
__IOM uint32_t IOFR[ADC_INJECT_SEQ_NUM]; /*!< (@ 0x0000000C) ADC Injection Group Offset Register */
|
|
__IOM uint32_t AMOHR; /*!< (@ 0x0000001C) AMO High threshold and offset register */
|
|
__IOM uint32_t AMOLR; /*!< (@ 0x00000020) AMO Low threshold and offset register */
|
|
__IOM uint32_t SPT[ADC_SAMPLE_REG_NUM]; /*!< (@ 0x00000024) ADC Sample time setting register(n) */
|
|
__IOM uint32_t RSQR[ADC_REGULAR_SEQ_NUM]; /*!< (@ 0x00000034) ADC regular group sequence configure register(n) */
|
|
__IM uint32_t RESERVED1[8];
|
|
__IOM uint32_t ISQR[ADC_INJECT_SEQ_NUM]; /*!< (@ 0x000000B4) ADC injected group sequence configure register(n) */
|
|
__IOM uint32_t SQL; /*!< (@ 0x000000C4) Sequence length of group configure register */
|
|
__IOM uint32_t CALI0; /*!< (@ 0x000000C8) ADC Calibration Register 0 */
|
|
__IOM uint32_t CALI1; /*!< (@ 0x000000CC) ADC Calibration Register 1 */
|
|
__IM uint32_t RESERVED2[6];
|
|
__IM uint32_t RDR[ADC_REGULAR_SEQ_NUM]; /*!< (@ 0x000000E8) ADC Regular Group data Register(n) */
|
|
__IM uint32_t RESERVED3[8];
|
|
__IM uint32_t IDR[ADC_INJECT_SEQ_NUM]; /*!< (@ 0x00000168) ADC Injected Group data Register(n) */
|
|
} ADC_Type; /*!< Size = 376 (0x178) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ ACMP ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Analog comparator (ACMP)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40005000) ACMP Structure */
|
|
__IOM uint32_t CR0; /*!< (@ 0x00000000) ACMP Configuration Register 0 */
|
|
__IOM uint32_t CR1; /*!< (@ 0x00000004) ACMP Configuration Register 1 */
|
|
__IOM uint32_t CR2; /*!< (@ 0x00000008) ACMP configuration register 2 */
|
|
__IOM uint32_t CR3; /*!< (@ 0x0000000C) ACMP configuration register 3 */
|
|
__IOM uint32_t CR4; /*!< (@ 0x00000010) ACMP configuration register 4 */
|
|
__IM uint32_t DR; /*!< (@ 0x00000014) ACMP data output register 0 */
|
|
__IOM uint32_t SR; /*!< (@ 0x00000018) ACMP status register 0 */
|
|
__IOM uint32_t FD; /*!< (@ 0x0000001C) ACMP polling frequency divider register */
|
|
__IOM uint32_t OPA; /*!< (@ 0x00000020) ACMP hall output A set register */
|
|
__IOM uint32_t OPB; /*!< (@ 0x00000024) ACMP hall output B set register */
|
|
__IOM uint32_t OPC; /*!< (@ 0x00000028) ACMP hall output C set register */
|
|
__IM uint32_t RESERVED[7];
|
|
__IOM uint32_t CLK; /*!< (@ 0x00000048) ACMP clock register */
|
|
} ACMP_Type; /*!< Size = 76 (0x4c) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ PWM ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Pulse Width Modulation (PWM)
|
|
*/
|
|
|
|
#define PWM_CHANNEL_MAX (8UL) /*!< Number of channel of the PWM module */
|
|
typedef struct { /*!< (@ 0x40080000) PWM Structure */
|
|
__IOM uint32_t INIT; /*!< (@ 0x00000000) PWM Initialize, Include Clock and Prescale Setting */
|
|
__IOM uint32_t CNT; /*!< (@ 0x00000004) PWM Counter Value */
|
|
__IOM uint32_t MCVR; /*!< (@ 0x00000008) PWM Counter Max Count Value Register */
|
|
struct {
|
|
__IOM uint32_t CHnSCR; /*!< (@ 0x0000000C + 0x8 * n) Channel (n) Status And Control Register */
|
|
__IOM uint32_t CHnV; /*!< (@ 0x00000010 + 0x8 * n) Channel (n) Value */
|
|
} CHANNELS[PWM_CHANNEL_MAX];
|
|
__IOM uint32_t CNTIN; /*!< (@ 0x0000004C) Counter Initial Value */
|
|
__IOM uint32_t STR; /*!< (@ 0x00000050) Status Register */
|
|
__IOM uint32_t FUNCSEL; /*!< (@ 0x00000054) PWM Features(Functions) Mode Selection Register */
|
|
__IOM uint32_t SYNC; /*!< (@ 0x00000058) Synchronization */
|
|
__IOM uint32_t OUTINIT; /*!< (@ 0x0000005C) Initial State For Channels Output */
|
|
__IOM uint32_t OMCR; /*!< (@ 0x00000060) Output Mask Control Register */
|
|
__IOM uint32_t MODESEL; /*!< (@ 0x00000064) PWM Function Mode Selection */
|
|
__IOM uint32_t DTSET0; /*!< (@ 0x00000068) Deadtime Insertion Control 0 */
|
|
__IOM uint32_t DTSET1; /*!< (@ 0x0000006C) Deadtime Insertion Control 1 */
|
|
__IOM uint32_t EXTTRIG; /*!< (@ 0x00000070) PWM External Trigger */
|
|
__IOM uint32_t CHOPOLCR; /*!< (@ 0x00000074) Channel Output Polarity Register */
|
|
__IOM uint32_t FDSR; /*!< (@ 0x00000078) Fault Detect Status Register */
|
|
__IOM uint32_t CAPFILTER; /*!< (@ 0x0000007C) Input Capture Filter Control */
|
|
__IOM uint32_t FFAFER; /*!< (@ 0x00000080) Fault Filter and Fault Enable Register */
|
|
__IOM uint32_t QDI; /*!< (@ 0x00000084) Quadrature Decoder Interface Configuration Register */
|
|
__IOM uint32_t CONF; /*!< (@ 0x00000088) Configuration */
|
|
__IOM uint32_t FLTPOL; /*!< (@ 0x0000008C) PWM Fault Input Polarity */
|
|
__IOM uint32_t SYNCONF; /*!< (@ 0x00000090) Synchronization Configuration */
|
|
__IOM uint32_t INVCR; /*!< (@ 0x00000094) PWM Inverse Control Register */
|
|
__IOM uint32_t CHOSWCR; /*!< (@ 0x00000098) PWM CHannel Software Output Control Register */
|
|
__IOM uint32_t DITHER0; /*!< (@ 0x0000009C) Dither function register 0 */
|
|
__IOM uint32_t DITHER1; /*!< (@ 0x000000A0) Dither function register 1 */
|
|
__IOM uint32_t DITHER2; /*!< (@ 0x000000A4) Dither function register 2 */
|
|
__IOM uint32_t DMACTRL; /*!< (@ 0x000000A8) DMA Control Register */
|
|
} PWM_Type; /*!< Size = 172 (0xac) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ PDT ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Programmable Delay Timer (PDT)
|
|
*/
|
|
#define PDT_DLY_MAX (8UL) /*!< Number of channel of PDT DLY */
|
|
typedef struct { /*!< (@ 0x40086000) PDT Structure */
|
|
__IOM uint32_t SC; /*!< (@ 0x00000000) PDT Config Register1 */
|
|
__IOM uint32_t MOD; /*!< (@ 0x00000004) PDT Config Register2 */
|
|
struct {
|
|
__IOM uint32_t DLY; /*!< (@ 0x00000008 ~ 0x00000024) PDT Config Register3 ~ 10 */
|
|
} DLY[PDT_DLY_MAX];
|
|
__IOM uint32_t IDLY; /*!< (@ 0x00000028) PDT Config Register11 */
|
|
union {
|
|
__IOM uint32_t PODLY; /*!< (@ 0x0000002C) PDT Config Register12 */
|
|
struct
|
|
{
|
|
__IOM uint16_t DLY1;
|
|
__IOM uint16_t DLY2;
|
|
}ACCESS16BIT;
|
|
}PULSE;
|
|
__IOM uint32_t DLYn_EN; /*!< (@ 0x00000030) Delay Enable Register */
|
|
__IOM uint32_t POEN; /*!< (@ 0x00000034) Pulse-Out Enable register */
|
|
__IOM uint32_t CNT; /*!< (@ 0x00000038) Counter register */
|
|
} PDT_Type; /*!< Size = 60 (0x3c) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ TIMER_CTRL ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Timer Control (TIMER_CTRL)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40011000) TIMER_CTRL Structure */
|
|
__IOM uint32_t CR; /*!< (@ 0x00000000) Timer Control Regitser */
|
|
__IOM uint32_t SR; /*!< (@ 0x00000004) Timer Status Regitser */
|
|
__IOM uint32_t IER; /*!< (@ 0x00000008) TIMER Interrupt Enable Register */
|
|
__IOM uint32_t ENR; /*!< (@ 0x0000000C) TIMER Enable Register */
|
|
} TIMER_CTRL_Type; /*!< Size = 16 (0x10) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ TIMER_CHANNEL ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Timer channel (TIMER_CHANNEL)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40011010) TIMER_CHANNEL Structure */
|
|
__IOM uint32_t TVAL; /*!< (@ 0x00000000) Timer Load Value Register */
|
|
__IOM uint32_t CVAL; /*!< (@ 0x00000004) Timer Current Count Value Register */
|
|
__IOM uint32_t CTRL; /*!< (@ 0x00000008) Timer channel Control Register */
|
|
} TIMER_CHANNEL_Type; /*!< Size = 12 (0xc) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ PCT ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Pulse Count Timer (PCT)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40019000) PCT Structure */
|
|
__IOM uint32_t CSR; /*!< (@ 0x00000000) PCT Control Status Register */
|
|
__IOM uint32_t PSR; /*!< (@ 0x00000004) PCT prescaler Register */
|
|
__IOM uint32_t CMR; /*!< (@ 0x00000008) PCT Compare Register */
|
|
__IOM uint32_t CNR; /*!< (@ 0x0000000C) PCT Counter Register */
|
|
} PCT_Type; /*!< Size = 16 (0x10) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ CTU ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Connect Unit Module (CTU)
|
|
*/
|
|
#define TRGMUX_MODULE_NUM (23UL)
|
|
typedef struct { /*!< (@ 0x40006000) CTU Structure */
|
|
union {
|
|
struct {
|
|
__IOM uint32_t TRGMUX_DMA; /*!< (@ 0x00000000) TRGMUX Config Register1 */
|
|
__IOM uint32_t TRGMUX_EXTOUT0; /*!< (@ 0x00000004) TRGMUX Config Register2 */
|
|
__IOM uint32_t TRGMUX_EXTOUT1; /*!< (@ 0x00000008) TRGMUX Config Register3 */
|
|
__IOM uint32_t TRGMUX_ADC0_REG; /*!< (@ 0x0000000C) TRGMUX Config Register4 */
|
|
__IOM uint32_t TRGMUX_ADC0_INJ; /*!< (@ 0x00000010) TRGMUX Config Register5 */
|
|
__IOM uint32_t TRGMUX_ADC1_REG; /*!< (@ 0x00000014) TRGMUX Config Register6 */
|
|
__IOM uint32_t TRGMUX_ADC1_INJ; /*!< (@ 0x00000018) TRGMUX Config Register7 */
|
|
__IOM uint32_t TRGMUX_ACMP; /*!< (@ 0x0000001C) TRGMUX Config Register8 */
|
|
__IOM uint32_t TRGMUX_PWM0; /*!< (@ 0x00000020) TRGMUX Config Register9 */
|
|
__IOM uint32_t TRGMUX_PWM1; /*!< (@ 0x00000024) TRGMUX Config Register10 */
|
|
__IOM uint32_t TRGMUX_PWM2; /*!< (@ 0x00000028) TRGMUX Config Register11 */
|
|
__IOM uint32_t TRGMUX_PWM3; /*!< (@ 0x0000002C) TRGMUX Config Register12 */
|
|
__IOM uint32_t TRGMUX_PWM4; /*!< (@ 0x00000030) TRGMUX Config Register13 */
|
|
__IOM uint32_t TRGMUX_PWM5; /*!< (@ 0x00000034) TRGMUX Config Register14 */
|
|
__IM uint32_t RESERVED[2];
|
|
__IOM uint32_t TRGMUX_TIMER; /*!< (@ 0x00000040) TRGMUX Config Register15 */
|
|
__IOM uint32_t TRGMUX_PCT; /*!< (@ 0x00000044) TRGMUX Config Register16 */
|
|
__IOM uint32_t TRGMUX_UART0; /*!< (@ 0x00000048) TRGMUX Config Register17 */
|
|
__IOM uint32_t TRGMUX_UART1; /*!< (@ 0x0000004C) TRGMUX Config Register18 */
|
|
__IOM uint32_t TRGMUX_PDT0; /*!< (@ 0x00000050) TRGMUX Config Register19 */
|
|
__IOM uint32_t TRGMUX_PDT1; /*!< (@ 0x00000054) TRGMUX Config Register20 */
|
|
__IOM uint32_t TRGMUX_EIO; /*!< (@ 0x00000058) TRGMUX Config Register21 */
|
|
} TRGMUX_MODULE;
|
|
__IOM uint32_t TRGMUXn[TRGMUX_MODULE_NUM];
|
|
} TRGMUX;
|
|
__IOM uint32_t CTU_CFG; /*!< (@ 0x0000005C) CTU Config Register */
|
|
__IOM uint32_t CTU_SW; /*!< (@ 0x00000060) CTU Config2 Register */
|
|
__IOM uint32_t PWM_MODULATION; /*!< (@ 0x00000064) CTU Config3 Register */
|
|
__IOM uint32_t ADC_SYNC; /*!< (@ 0x00000068) CTU ADC Interleave and Simultaneous Mode Register */
|
|
} CTU_Type; /*!< Size = 108 (0x6c) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ DMA0_TOP_RST ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief DMA0 All Channnels Share The Registers (DMA0_TOP_RST)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40012000) DMA0_TOP_RST Structure */
|
|
__IOM uint32_t TOP_RST; /*!< (@ 0x00000000) TOP_RST Register */
|
|
} DMA_TopRstType; /*!< Size = 4 (0x4) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ DMA0_Channel ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief DMA channel (DMA0_Channel)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40012040) DMA0_Channel Structure */
|
|
__IOM uint32_t STATUS; /*!< (@ 0x00000000) Status Register */
|
|
__IOM uint32_t INTEN; /*!< (@ 0x00000004) Interrupt Enable Register */
|
|
__IOM uint32_t RST; /*!< (@ 0x00000008) Reset Register */
|
|
__IOM uint32_t STOP; /*!< (@ 0x0000000C) Stop Register */
|
|
__IOM uint32_t CONFIG; /*!< (@ 0x00000010) DMA Config Register */
|
|
__IOM uint32_t CHAN_LENGTH; /*!< (@ 0x00000014) Channel Length Register */
|
|
__IOM uint32_t SSTART_ADDR; /*!< (@ 0x00000018) Source Start Address Register */
|
|
__IOM uint32_t SEND_ADDR; /*!< (@ 0x0000001C) Source End Address Register */
|
|
__IOM uint32_t DSTART_ADDR; /*!< (@ 0x00000020) Destination Start Address Register */
|
|
__IOM uint32_t CHAN_ENABLE; /*!< (@ 0x00000024) Channel Enable Register */
|
|
__IOM uint32_t DATA_TRANS_NUM; /*!< (@ 0x00000028) Data Transfer Number Register */
|
|
__IOM uint32_t FIFO_LEFT_NUM; /*!< (@ 0x0000002C) Internal FIFO Data Left Number Register */
|
|
__IOM uint32_t DEND_ADDR; /*!< (@ 0x00000030) Destination End Address Register */
|
|
__IOM uint32_t ADDR_OFFSET; /*!< (@ 0x00000034) Address Offset Register */
|
|
__IOM uint32_t DMAMUX_CFG; /*!< (@ 0x00000038) DMAMUX Configuration Register */
|
|
} DMA_ChannelType; /*!< Size = 60 (0x3c) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ WDG ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Watchdog (WDG)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x4000B000) WDG Structure */
|
|
__IOM uint32_t CS0; /*!< (@ 0x00000000) Watchdog Control and Status Register 0 */
|
|
__IOM uint32_t CS1; /*!< (@ 0x00000004) Watchdog Control and Status Register 1 */
|
|
__IOM uint32_t CNT; /*!< (@ 0x00000008) Watchdog Counter Value */
|
|
__IOM uint32_t TOVAL; /*!< (@ 0x0000000C) Watchdog Timeout Value Register */
|
|
__IOM uint32_t WIN; /*!< (@ 0x00000010) Watchdog Window Register */
|
|
} WDG_Type; /*!< Size = 20 (0x14) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ RTC ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Real-time counter (RTC)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40009800) RTC Structure */
|
|
__IOM uint32_t CTRL; /*!< (@ 0x00000000) RTC Control Register */
|
|
__IOM uint32_t TAR; /*!< (@ 0x00000004) RTC Time Alarm Register */
|
|
__IOM uint32_t TC; /*!< (@ 0x00000008) RTC Time Counter */
|
|
__IOM uint32_t PSR; /*!< (@ 0x0000000C) RTC Prescaler Register */
|
|
__IM uint32_t PSC; /*!< (@ 0x00000010) RTC Prescaler Counter Register */
|
|
__IOM uint32_t SR; /*!< (@ 0x00000014) RTC Status Register */
|
|
__IOM uint32_t LR; /*!< (@ 0x00000018) RTC Lock Register */
|
|
} RTC_Type; /*!< Size = 28 (0x1c) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ CRC ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief CRC Cyclic redundancy check (CRC)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40084000) CRC Structure */
|
|
union {
|
|
__IOM uint32_t DATA32; /*!< (@ 0x00000000) DATA Register */
|
|
struct {
|
|
__IOM uint16_t L; /*!< (@ 0x00000000) DATA L Register */
|
|
__IOM uint16_t H; /*!< (@ 0x00000002) DATA H Register */
|
|
} DATA16;
|
|
struct {
|
|
__IOM uint8_t LL; /*!< (@ 0x00000000) DATA LL Register */
|
|
__IOM uint8_t LU; /*!< (@ 0x00000001) DATA LU Register */
|
|
__IOM uint8_t HL; /*!< (@ 0x00000002) DATA HL Register */
|
|
__IOM uint8_t HU; /*!< (@ 0x00000003) DATA HU Register */
|
|
} DATA8;
|
|
} DATAn;
|
|
__IOM uint32_t POLY; /*!< (@ 0x00000004) Poly Register */
|
|
__IOM uint32_t CTRL; /*!< (@ 0x00000008) Control Register */
|
|
} CRC_Type; /*!< Size = 12 (0xc) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ EIM_CTRL ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief GLB_EN (EIM_CTRL)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40088000) EIM_CTRL Structure */
|
|
__IOM uint32_t EIM_GLB_ENABLE; /*!< (@ 0x00000000) EIM global enable */
|
|
__IOM uint32_t EIM_CHEN; /*!< (@ 0x00000004) EIM channel enable control */
|
|
} EIM_CTRL_Type; /*!< Size = 8 (0x8) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ EIM_CHANNEL ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief SRAM Error Injection Bit Control (EIM_CHANNEL)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40088010) EIM_CHANNEL Structure */
|
|
__IOM uint32_t EIM_INJ_DATA; /*!< (@ 0x00000000) SRAML data injection control */
|
|
__IOM uint32_t EIM_INJ_ADDR; /*!< (@ 0x00000004) SRAML address injection control */
|
|
__IOM uint32_t EIM_INJ_ECC; /*!< (@ 0x00000008) SRAML ECC code injection control */
|
|
} EIM_CHANNEL_Type; /*!< Size = 12 (0xc) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ ECC_SRAM ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief SRAM Error ctrl (ECC_SRAM)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40088100) ECC_SRAM Structure */
|
|
__IM uint32_t CH0_STATUS0; /*!< (@ 0x00000000) SRAM ECC CH0 status and addr0 register */
|
|
__IM uint32_t CH0_STATUS1; /*!< (@ 0x00000004) ECC CH0 2bit error addr */
|
|
__IM uint32_t CH1_STATUS0; /*!< (@ 0x00000008) SRAM ECC CH1 status and addr0 register */
|
|
__IM uint32_t CH1_STATUS1; /*!< (@ 0x0000000C) ECC CH1 2bit error addr */
|
|
__IOM uint32_t ECC_ERR_CTRL; /*!< (@ 0x00000010) ECC Error status control registers */
|
|
} ECC_SRAM_Type; /*!< Size = 20 (0x14) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ FLASH ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Embedded Flash (FLASH)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40002000) FLASH Structure */
|
|
__IOM uint32_t STAT; /*!< (@ 0x00000000) Flash status register */
|
|
__IM uint32_t SEC; /*!< (@ 0x00000004) MCU secure register */
|
|
__IOM uint32_t CSESTAT; /*!< (@ 0x00000008) CSE status register */
|
|
__IOM uint32_t KEYUNLK; /*!< (@ 0x0000000C) Flash unlock register */
|
|
__IOM uint32_t CNFG; /*!< (@ 0x00000010) Flash configure register */
|
|
__IOM uint32_t CMD; /*!< (@ 0x00000014) Flash command ID register */
|
|
__IOM uint32_t ADDR; /*!< (@ 0x00000018) Flash address register */
|
|
__IOM uint32_t DATA0; /*!< (@ 0x0000001C) Flash data register 0 */
|
|
__IOM uint32_t DATA1; /*!< (@ 0x00000020) Flash data register 1 */
|
|
__IOM uint32_t LEN; /*!< (@ 0x00000024) Flash length register */
|
|
__IM uint32_t RESERVED[2];
|
|
__IOM uint32_t CST; /*!< (@ 0x00000030) Flash command start register */
|
|
__IOM uint32_t PPROT; /*!< (@ 0x00000034) P-Flash write protection register */
|
|
__IOM uint32_t DPROT; /*!< (@ 0x00000038) D-Flash write protection register */
|
|
__IM uint32_t RESERVED1;
|
|
__IOM uint32_t DFADR; /*!< (@ 0x00000040) Flash ECC 2-bit error address register */
|
|
__IM uint32_t RESERVED2;
|
|
__IM uint32_t PART; /*!< (@ 0x00000048) CSE partition information register */
|
|
} FLASH_Type; /*!< Size = 76 (0x4c) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ CSE ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
#define CSE_PRAM_RAMn_COUNT (32UL) /*!< Size of PRMA Registers Arrays */
|
|
#define CSE_PRAM_INSTANCE_COUNT (1UL) /*!< Number of instances of the CSE_PRAM module */
|
|
|
|
/**
|
|
* @brief CSE
|
|
*/
|
|
typedef struct {
|
|
union { /*!< offset: 0x0, array step: 0x4 */
|
|
__IO uint32_t DATA_32; /*!< CSE PRAM 0 Register..CSE PRAM 31 Register, array offset: 0x0, array step: 0x4 */
|
|
struct { /*!< offset: 0x0, array step: 0x4 */
|
|
__IO uint8_t DATA_8LL; /*!< CSE PRAM0LL register...CSE PRAM31LL register., array offset: 0x0, array step: 0x4 */
|
|
__IO uint8_t DATA_8LU; /*!< CSE PRAM0LU register...CSE PRAM31LU register., array offset: 0x1, array step: 0x4 */
|
|
__IO uint8_t DATA_8HL; /*!< CSE PRAM0HL register...CSE PRAM31HL register., array offset: 0x2, array step: 0x4 */
|
|
__IO uint8_t DATA_8HU; /*!< CSE PRAM0HU register...CSE PRAM31HU register., array offset: 0x3, array step: 0x4 */
|
|
} ACCESS8BIT;
|
|
} RAMn[CSE_PRAM_RAMn_COUNT];
|
|
} CSE_PRAM_Type, *CSE_PRAM_MemMapPtr;
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ EIO ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief The EIO Memory Map/Register Definition can be found here. (EIO)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x4000A000) EIO Structure */
|
|
__IOM uint32_t CTRL; /*!< (@ 0x00000000) EIO Control Register */
|
|
__IM uint32_t PIN; /*!< (@ 0x00000004) Pin State Register */
|
|
__IOM uint32_t SHIFTSTAT; /*!< (@ 0x00000008) Shifter Status Register */
|
|
__IOM uint32_t SHIFTERR; /*!< (@ 0x0000000C) Shifter Error Register */
|
|
__IOM uint32_t TIMSTAT; /*!< (@ 0x00000010) Timer Status Register */
|
|
__IOM uint32_t SHIFTSIEN; /*!< (@ 0x00000014) Shifter Status Interrupt Enable */
|
|
__IOM uint32_t SHIFTEIEN; /*!< (@ 0x00000018) Shifter Error Interrupt Enable */
|
|
__IOM uint32_t TIMIEN; /*!< (@ 0x0000001C) Timer Interrupt Enable Register */
|
|
__IOM uint32_t SHIFTSDEN; /*!< (@ 0x00000020) Shifter Status DMA Enable */
|
|
__IM uint32_t RESERVED[3];
|
|
__IOM uint32_t SHIFTCTL[4]; /*!< (@ 0x00000030) Shifter Control N Register */
|
|
__IOM uint32_t SHIFTCFG[4]; /*!< (@ 0x00000040) Shifter Configuration N Register */
|
|
__IOM uint32_t SHIFTBUF[4]; /*!< (@ 0x00000050) Shifter Buffer N Register */
|
|
__IOM uint32_t SHIFTBUFBIS[4]; /*!< (@ 0x00000060) Shifter Buffer N Bit Swapped Register */
|
|
__IOM uint32_t SHIFTBUFBYS[4]; /*!< (@ 0x00000070) Shifter Buffer N Byte Swapped Register */
|
|
__IOM uint32_t SHIFTBUFBBS[4]; /*!< (@ 0x00000080) Shifter Buffer N Bit Byte Swapped Register */
|
|
__IOM uint32_t TIMCTL[4]; /*!< (@ 0x00000090) Timer Control N Register */
|
|
__IOM uint32_t TIMCFG[4]; /*!< (@ 0x000000A0) Timer Configuration N Register */
|
|
__IOM uint32_t TIMCMP[4]; /*!< (@ 0x000000B0) Timer Compare N Register */
|
|
} EIO_Type; /*!< Size = 192 (0xc0) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ EWDG ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief External Watchdog Timer (EWDG)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x4000B400) EWDG Structure */
|
|
__IOM uint32_t CTRL; /*!< (@ 0x00000000) Control Register */
|
|
__IOM uint32_t SERV; /*!< (@ 0x00000004) Service Register */
|
|
__IOM uint32_t CMPL; /*!< (@ 0x00000008) Compare Low Register */
|
|
__IOM uint32_t CMPH; /*!< (@ 0x0000000C) Compare High Register */
|
|
__IOM uint32_t CLKPRESCALER; /*!< (@ 0x00000010) Clock Prescaler Register */
|
|
} EWDG_Type; /*!< Size = 20 (0x14) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ AC784X_SysTick ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief The AC784X_SysTick Memory Map/Register Definition can be found here. (AC784X_SysTick)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0xE000E010) AC784X_SysTick Structure */
|
|
__IOM uint32_t CSR; /*!< (@ 0x00000000) SysTick Control and Status Register, offset: 0x0 */
|
|
__IOM uint32_t RVR; /*!< (@ 0x00000004) SysTick Reload Value Register, offset: 0x4 */
|
|
__IOM uint32_t CVR; /*!< (@ 0x00000008) SysTick Current Value Register, offset: 0x8 */
|
|
__IOM uint32_t CALIB; /*!< (@ 0x0000000C) SysTick Calibration Value Register, offset: 0xC */
|
|
} AC784X_SysTickType; /*!< Size = 16 (0x10) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ SMU ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Safety Management Uint (SMU)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40089000) SMU Structure */
|
|
__IOM uint32_t SFES; /*!< (@ 0x00000000) Single Point Fault Error Status Register */
|
|
__IOM uint32_t SFESS; /*!< (@ 0x00000004) Single Point Fault Error Status Shadow Register */
|
|
__IOM uint32_t LFES; /*!< (@ 0x00000008) Latent Fault Error Status Register */
|
|
__IOM uint32_t LFESS; /*!< (@ 0x0000000C) Latent Fault Error Status Shadow Register */
|
|
__IOM uint32_t LKSEQ0; /*!< (@ 0x00000010) Lock Sequence for Single Point Fault Path */
|
|
__IOM uint32_t LKSEQ1; /*!< (@ 0x00000014) Lock Sequence for Latent Fault Path */
|
|
__IOM uint32_t SWSFE; /*!< (@ 0x00000018) Software Single Point Fault Enable Register */
|
|
__IOM uint32_t SWSFES; /*!< (@ 0x0000001C) Software Single Point Fault Enable Shadow Register */
|
|
__IOM uint32_t SWLFE; /*!< (@ 0x00000020) Software Latent Fault Enable Register */
|
|
__IOM uint32_t SWLFES; /*!< (@ 0x00000024) Software Latent Fault Enable Shadow Register */
|
|
__IM uint32_t RESERVED[2];
|
|
__IOM uint32_t SFRSTEN; /*!< (@ 0x00000030) Single Point Fault Reset Enable Register */
|
|
__IOM uint32_t LFRSTEN; /*!< (@ 0x00000034) Latent Fault Reset Request Enable Register */
|
|
__IOM uint32_t SRSTCNTVAL; /*!< (@ 0x00000038) System Reset Request Counter Threshold Register */
|
|
__IOM uint32_t SRSTCNT; /*!< (@ 0x0000003C) System Reset Request Counter Register */
|
|
__IOM uint32_t SRSTCNTS; /*!< (@ 0x00000040) System Reset Request Counter Shadow Register */
|
|
__IOM uint32_t PATHCHK0; /*!< (@ 0x00000044) Path Check for Single Point Fault Path Register */
|
|
__IOM uint32_t PATHCHK1; /*!< (@ 0x00000048) Path Check for Latent Fault Error Path Register */
|
|
} SMU_Type; /*!< Size = 76 (0x4c) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ CMU ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/**
|
|
* @brief Clock Monitor Uint (CMU)
|
|
*/
|
|
|
|
typedef struct { /*!< (@ 0x40000800) CMU Structure */
|
|
__IOM uint32_t CR; /*!< (@ 0x00000000) Configure Register */
|
|
__IOM uint32_t RCCR; /*!< (@ 0x00000004) Reference Count Configure Register */
|
|
__IOM uint32_t HTCR; /*!< (@ 0x00000008) High Threshold Configure Register */
|
|
__IOM uint32_t LTCR; /*!< (@ 0x0000000C) Low Threshold Configure Register */
|
|
__IM uint32_t RESERVED[2];
|
|
__IOM uint32_t SR; /*!< (@ 0x00000018) Status Register */
|
|
__IOM uint32_t MON_A7; /*!< (@ 0x0000001C) Monitor Register */
|
|
__IOM uint32_t MON_A8; /*!< (@ 0x00000020) Monitor Register */
|
|
} CMU_Type; /*!< Size = 36 (0x24) */
|
|
|
|
|
|
/** @} */ /* End of group Device_Peripheral_peripherals */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ Device Specific Peripheral Address Map ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/** @addtogroup Device_Peripheral_peripheralAddr
|
|
* @{
|
|
*/
|
|
|
|
#define CKGEN_BASE 0x40000000UL
|
|
#define PBR_BASE 0x4008A000UL
|
|
#define SPM_BASE 0x40008000UL
|
|
#define GPIOA_BASE 0x40085000UL
|
|
#define GPIOB_BASE 0x40085040UL
|
|
#define GPIOC_BASE 0x40085080UL
|
|
#define GPIOD_BASE 0x400850C0UL
|
|
#define GPIOE_BASE 0x40085100UL
|
|
#define PORTA_BASE 0x40085200UL
|
|
#define PORTB_BASE 0x40085300UL
|
|
#define PORTC_BASE 0x40085400UL
|
|
#define PORTD_BASE 0x40085500UL
|
|
#define PORTE_BASE 0x40085600UL
|
|
#define CAN0_BASE 0x40007000UL
|
|
#define CAN1_BASE 0x40007200UL
|
|
#define CAN2_BASE 0x40007400UL
|
|
#define CAN3_BASE 0x40007600UL
|
|
#define UART0_BASE 0x40018000UL
|
|
#define UART1_BASE 0x40018200UL
|
|
#define UART2_BASE 0x40018400UL
|
|
#define UART3_BASE 0x40018600UL
|
|
#define I2C0_BASE 0x4000E000UL
|
|
#define SPI0_BASE 0x4000C000UL
|
|
#define SPI1_BASE 0x4000C800UL
|
|
#define SPI2_BASE 0x4000D000UL
|
|
#define ANA_BASE 0x40008800UL
|
|
#define ADC0_BASE 0x40003000UL
|
|
#define ADC1_BASE 0x40004000UL
|
|
#define ACMP0_BASE 0x40005000UL
|
|
#define PWM0_BASE 0x40080000UL
|
|
#define PWM1_BASE 0x40080800UL
|
|
#define PWM2_BASE 0x40081000UL
|
|
#define PWM3_BASE 0x40081800UL
|
|
#define PWM4_BASE 0x40082000UL
|
|
#define PWM5_BASE 0x40082800UL
|
|
#define PDT0_BASE 0x40086000UL
|
|
#define PDT1_BASE 0x40086800UL
|
|
#define TIMER_CTRL_BASE 0x40011000UL
|
|
#define TIMER_CHANNEL0_BASE 0x40011010UL
|
|
#define TIMER_CHANNEL1_BASE 0x40011020UL
|
|
#define TIMER_CHANNEL2_BASE 0x40011030UL
|
|
#define TIMER_CHANNEL3_BASE 0x40011040UL
|
|
#define PCT_BASE 0x40019000UL
|
|
#define CTU_BASE 0x40006000UL
|
|
#define DMA0_TOP_RST_BASE 0x40012000UL
|
|
#define DMA0_CHANNEL0_BASE 0x40012040UL
|
|
#define DMA0_CHANNEL1_BASE 0x40012080UL
|
|
#define DMA0_CHANNEL2_BASE 0x400120C0UL
|
|
#define DMA0_CHANNEL3_BASE 0x40012100UL
|
|
#define DMA0_CHANNEL4_BASE 0x40012140UL
|
|
#define DMA0_CHANNEL5_BASE 0x40012180UL
|
|
#define DMA0_CHANNEL6_BASE 0x400121C0UL
|
|
#define DMA0_CHANNEL7_BASE 0x40012200UL
|
|
#define DMA0_CHANNEL8_BASE 0x40012240UL
|
|
#define DMA0_CHANNEL9_BASE 0x40012280UL
|
|
#define DMA0_CHANNEL10_BASE 0x400122C0UL
|
|
#define DMA0_CHANNEL11_BASE 0x40012300UL
|
|
#define DMA0_CHANNEL12_BASE 0x40012340UL
|
|
#define DMA0_CHANNEL13_BASE 0x40012380UL
|
|
#define DMA0_CHANNEL14_BASE 0x400123C0UL
|
|
#define DMA0_CHANNEL15_BASE 0x40012400UL
|
|
#define WDG_BASE 0x4000B000UL
|
|
#define RTC_BASE 0x40009800UL
|
|
#define CRC_BASE 0x40084000UL
|
|
#define EIM_CTRL_BASE 0x40088000UL
|
|
#define EIM_CHANNEL0_BASE 0x40088010UL
|
|
#define EIM_CHANNEL1_BASE 0x40088080UL
|
|
#define ECC_SRAM_BASE 0x40088100UL
|
|
#define FLASH_BASE 0x40002000UL
|
|
#define EIO_BASE 0x4000A000UL
|
|
#define EWDG_BASE 0x4000B400UL
|
|
#define AC784X_SYSTICK_BASE 0xE000E010UL
|
|
#define MCM_BASE 0xE008000CUL
|
|
#define MPU_BASE 0x40087000UL
|
|
#define SMU_BASE 0x40089000UL
|
|
#define CMU_VHSI_BASE 0x40000800UL
|
|
#define CMU_HSE_BASE 0x40000A00UL
|
|
#define CMU_PLL_BASE 0x40000C00UL
|
|
#define CSE_PRAM_BASE 0x14001000UL
|
|
|
|
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ Peripheral declaration ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/** @addtogroup Device_Peripheral_declaration
|
|
* @{
|
|
*/
|
|
|
|
#define CKGEN ((CKGEN_Type*) CKGEN_BASE)
|
|
#define PBR ((PBR_Type*) PBR_BASE)
|
|
#define SPM ((SPM_Type*) SPM_BASE)
|
|
#define GPIOA ((GPIO_Type*) GPIOA_BASE)
|
|
#define GPIOB ((GPIO_Type*) GPIOB_BASE)
|
|
#define GPIOC ((GPIO_Type*) GPIOC_BASE)
|
|
#define GPIOD ((GPIO_Type*) GPIOD_BASE)
|
|
#define GPIOE ((GPIO_Type*) GPIOE_BASE)
|
|
#define PORTA ((PORT_Type*) PORTA_BASE)
|
|
#define PORTB ((PORT_Type*) PORTB_BASE)
|
|
#define PORTC ((PORT_Type*) PORTC_BASE)
|
|
#define PORTD ((PORT_Type*) PORTD_BASE)
|
|
#define PORTE ((PORT_Type*) PORTE_BASE)
|
|
#define CAN0 ((CAN_Type*) CAN0_BASE)
|
|
#define CAN1 ((CAN_Type*) CAN1_BASE)
|
|
#define CAN2 ((CAN_Type*) CAN2_BASE)
|
|
#define CAN3 ((CAN_Type*) CAN3_BASE)
|
|
#define UART0 ((UART_Type*) UART0_BASE)
|
|
#define UART1 ((UART_Type*) UART1_BASE)
|
|
#define UART2 ((UART_Type*) UART2_BASE)
|
|
#define UART3 ((UART_Type*) UART3_BASE)
|
|
#define I2C0 ((I2C_Type*) I2C0_BASE)
|
|
#define SPI0 ((SPI_Type*) SPI0_BASE)
|
|
#define SPI1 ((SPI_Type*) SPI1_BASE)
|
|
#define SPI2 ((SPI_Type*) SPI2_BASE)
|
|
#define ANA ((ANA_Type*) ANA_BASE)
|
|
#define ADC0 ((ADC_Type*) ADC0_BASE)
|
|
#define ADC1 ((ADC_Type*) ADC1_BASE)
|
|
#define ACMP0 ((ACMP_Type*) ACMP0_BASE)
|
|
#define PWM0 ((PWM_Type*) PWM0_BASE)
|
|
#define PWM1 ((PWM_Type*) PWM1_BASE)
|
|
#define PWM2 ((PWM_Type*) PWM2_BASE)
|
|
#define PWM3 ((PWM_Type*) PWM3_BASE)
|
|
#define PWM4 ((PWM_Type*) PWM4_BASE)
|
|
#define PWM5 ((PWM_Type*) PWM5_BASE)
|
|
#define PDT0 ((PDT_Type*) PDT0_BASE)
|
|
#define PDT1 ((PDT_Type*) PDT1_BASE)
|
|
#define TIMER_CTRL ((TIMER_CTRL_Type*) TIMER_CTRL_BASE)
|
|
#define TIMER_CHANNEL0 ((TIMER_CHANNEL_Type*) TIMER_CHANNEL0_BASE)
|
|
#define TIMER_CHANNEL1 ((TIMER_CHANNEL_Type*) TIMER_CHANNEL1_BASE)
|
|
#define TIMER_CHANNEL2 ((TIMER_CHANNEL_Type*) TIMER_CHANNEL2_BASE)
|
|
#define TIMER_CHANNEL3 ((TIMER_CHANNEL_Type*) TIMER_CHANNEL3_BASE)
|
|
#define PCT ((PCT_Type*) PCT_BASE)
|
|
#define CTU ((CTU_Type*) CTU_BASE)
|
|
#define DMA0_TOP_RST ((DMA_TopRstType*) DMA0_TOP_RST_BASE)
|
|
#define DMA0_CHANNEL0 ((DMA_ChannelType*) DMA0_CHANNEL0_BASE)
|
|
#define DMA0_CHANNEL1 ((DMA_ChannelType*) DMA0_CHANNEL1_BASE)
|
|
#define DMA0_CHANNEL2 ((DMA_ChannelType*) DMA0_CHANNEL2_BASE)
|
|
#define DMA0_CHANNEL3 ((DMA_ChannelType*) DMA0_CHANNEL3_BASE)
|
|
#define DMA0_CHANNEL4 ((DMA_ChannelType*) DMA0_CHANNEL4_BASE)
|
|
#define DMA0_CHANNEL5 ((DMA_ChannelType*) DMA0_CHANNEL5_BASE)
|
|
#define DMA0_CHANNEL6 ((DMA_ChannelType*) DMA0_CHANNEL6_BASE)
|
|
#define DMA0_CHANNEL7 ((DMA_ChannelType*) DMA0_CHANNEL7_BASE)
|
|
#define DMA0_CHANNEL8 ((DMA_ChannelType*) DMA0_CHANNEL8_BASE)
|
|
#define DMA0_CHANNEL9 ((DMA_ChannelType*) DMA0_CHANNEL9_BASE)
|
|
#define DMA0_CHANNEL10 ((DMA_ChannelType*) DMA0_CHANNEL10_BASE)
|
|
#define DMA0_CHANNEL11 ((DMA_ChannelType*) DMA0_CHANNEL11_BASE)
|
|
#define DMA0_CHANNEL12 ((DMA_ChannelType*) DMA0_CHANNEL12_BASE)
|
|
#define DMA0_CHANNEL13 ((DMA_ChannelType*) DMA0_CHANNEL13_BASE)
|
|
#define DMA0_CHANNEL14 ((DMA_ChannelType*) DMA0_CHANNEL14_BASE)
|
|
#define DMA0_CHANNEL15 ((DMA_ChannelType*) DMA0_CHANNEL15_BASE)
|
|
#define WDG ((WDG_Type*) WDG_BASE)
|
|
#define RTC ((RTC_Type*) RTC_BASE)
|
|
#define CRC ((CRC_Type*) CRC_BASE)
|
|
#define EIM_CTRL ((EIM_CTRL_Type*) EIM_CTRL_BASE)
|
|
#define EIM_CHANNEL0 ((EIM_CHANNEL_Type*) EIM_CHANNEL0_BASE)
|
|
#define EIM_CHANNEL1 ((EIM_CHANNEL_Type*) EIM_CHANNEL1_BASE)
|
|
#define ECC_SRAM ((ECC_SRAM_Type*) ECC_SRAM_BASE)
|
|
#define FLASH ((FLASH_Type*) FLASH_BASE)
|
|
#define EIO ((EIO_Type*) EIO_BASE)
|
|
#define EWDG ((EWDG_Type*) EWDG_BASE)
|
|
#define AC784X_SYSTICK ((AC784X_SysTickType*) AC784X_SYSTICK_BASE)
|
|
#define MCM ((MCM_Type*) MCM_BASE)
|
|
#define MPU ((MPU_Type*) MPU_BASE)
|
|
#define SMU ((SMU_Type*) SMU_BASE)
|
|
#define CMU_VHSI ((CMU_Type*) CMU_VHSI_BASE)
|
|
#define CMU_HSE ((CMU_Type*) CMU_HSE_BASE)
|
|
#define CMU_PLL ((CMU_Type*) CMU_PLL_BASE)
|
|
#define CSE_PRAM ((CSE_PRAM_Type *) CSE_PRAM_BASE)
|
|
|
|
|
|
/** @} */ /* End of group Device_Peripheral_declaration */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ Pos/Mask Peripheral Section ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
|
|
/** @addtogroup PosMask_peripherals
|
|
* @{
|
|
*/
|
|
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ MCM ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================= MCPCR ========================================================= */
|
|
#define MCM_MCPCR_SAPU_Pos (24UL) /*!< SAPU (Bit 24) */
|
|
#define MCM_MCPCR_SAPU_Msk (0x3000000UL) /*!< SAPU (Bitfield-Mask: 0x03) */
|
|
#define MCM_MCPCR_SWPU_Pos (26UL) /*!< SWPU (Bit 26) */
|
|
#define MCM_MCPCR_SWPU_Msk (0x4000000UL) /*!< SWPU (Bitfield-Mask: 0x01) */
|
|
#define MCM_MCPCR_SAPL_Pos (28UL) /*!< SAPL (Bit 28) */
|
|
#define MCM_MCPCR_SAPL_Msk (0x30000000UL) /*!< SAPL (Bitfield-Mask: 0x03) */
|
|
#define MCM_MCPCR_SWPL_Pos (30UL) /*!< SWPL (Bit 30) */
|
|
#define MCM_MCPCR_SWPL_Msk (0x40000000UL) /*!< SWPL (Bitfield-Mask: 0x01) */
|
|
/* ========================================================= MISCR ========================================================= */
|
|
#define MCM_MISCR_FIOC_Pos (8UL) /*!< FIOC (Bit 8) */
|
|
#define MCM_MISCR_FIOC_Msk (0x100UL) /*!< FIOC (Bitfield-Mask: 0x01) */
|
|
#define MCM_MISCR_FDZC_Pos (9UL) /*!< FDZC (Bit 9) */
|
|
#define MCM_MISCR_FDZC_Msk (0x200UL) /*!< FDZC (Bitfield-Mask: 0x01) */
|
|
#define MCM_MISCR_FOFC_Pos (10UL) /*!< FOFC (Bit 10) */
|
|
#define MCM_MISCR_FOFC_Msk (0x400UL) /*!< FOFC (Bitfield-Mask: 0x01) */
|
|
#define MCM_MISCR_FUFC_Pos (11UL) /*!< FUFC (Bit 11) */
|
|
#define MCM_MISCR_FUFC_Msk (0x800UL) /*!< FUFC (Bitfield-Mask: 0x01) */
|
|
#define MCM_MISCR_FIXC_Pos (12UL) /*!< FIXC (Bit 12) */
|
|
#define MCM_MISCR_FIXC_Msk (0x1000UL) /*!< FIXC (Bitfield-Mask: 0x01) */
|
|
#define MCM_MISCR_FIDC_Pos (15UL) /*!< FIDC (Bit 15) */
|
|
#define MCM_MISCR_FIDC_Msk (0x8000UL) /*!< FIDC (Bitfield-Mask: 0x01) */
|
|
#define MCM_MISCR_FIOCEN_Pos (24UL) /*!< FIOCEN (Bit 24) */
|
|
#define MCM_MISCR_FIOCEN_Msk (0x1000000UL) /*!< FIOCEN (Bitfield-Mask: 0x01) */
|
|
#define MCM_MISCR_FDZCEN_Pos (25UL) /*!< FDZCEN (Bit 25) */
|
|
#define MCM_MISCR_FDZCEN_Msk (0x2000000UL) /*!< FDZCEN (Bitfield-Mask: 0x01) */
|
|
#define MCM_MISCR_FOFCEN_Pos (26UL) /*!< FOFCEN (Bit 26) */
|
|
#define MCM_MISCR_FOFCEN_Msk (0x4000000UL) /*!< FOFCEN (Bitfield-Mask: 0x01) */
|
|
#define MCM_MISCR_FUFCEN_Pos (27UL) /*!< FUFCEN (Bit 27) */
|
|
#define MCM_MISCR_FUFCEN_Msk (0x8000000UL) /*!< FUFCEN (Bitfield-Mask: 0x01) */
|
|
#define MCM_MISCR_FIXCEN_Pos (28UL) /*!< FIXCEN (Bit 28) */
|
|
#define MCM_MISCR_FIXCEN_Msk (0x10000000UL) /*!< FIXCEN (Bitfield-Mask: 0x01) */
|
|
#define MCM_MISCR_FIDCEN_Pos (31UL) /*!< FIDCEN (Bit 31) */
|
|
#define MCM_MISCR_FIDCEN_Msk (0x80000000UL) /*!< FIDCEN (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== MLMDR0 ========================================================= */
|
|
#define MCM_MLMDR0_LREEN_Pos (1UL) /*!< LREEN (Bit 1) */
|
|
#define MCM_MLMDR0_LREEN_Msk (0x2UL) /*!< LREEN (Bitfield-Mask: 0x01) */
|
|
#define MCM_MLMDR0_UREEN_Pos (3UL) /*!< UREEN (Bit 3) */
|
|
#define MCM_MLMDR0_UREEN_Msk (0x8UL) /*!< UREEN (Bitfield-Mask: 0x01) */
|
|
#define MCM_MLMDR0_LOCK_Pos (16UL) /*!< LOCK (Bit 16) */
|
|
#define MCM_MLMDR0_LOCK_Msk (0x10000UL) /*!< LOCK (Bitfield-Mask: 0x01) */
|
|
#define MCM_MLMDR0_LMSZ_Pos (24UL) /*!< LMSZ (Bit 24) */
|
|
#define MCM_MLMDR0_LMSZ_Msk (0x7000000UL) /*!< LMSZ (Bitfield-Mask: 0x07) */
|
|
/* ========================================================= MBIST ========================================================= */
|
|
/* ======================================================== MLMDR1 ========================================================= */
|
|
#define MCM_MLMDR1_CPDE_Pos (5UL) /*!< CPDE (Bit 5) */
|
|
#define MCM_MLMDR1_CPDE_Msk (0x20UL) /*!< CPDE (Bitfield-Mask: 0x01) */
|
|
#define MCM_MLMDR1_CPFE_Pos (7UL) /*!< CPFE (Bit 7) */
|
|
#define MCM_MLMDR1_CPFE_Msk (0x80UL) /*!< CPFE (Bitfield-Mask: 0x01) */
|
|
#define MCM_MLMDR1_LOCK_Pos (16UL) /*!< LOCK (Bit 16) */
|
|
#define MCM_MLMDR1_LOCK_Msk (0x10000UL) /*!< LOCK (Bitfield-Mask: 0x01) */
|
|
#define MCM_MLMDR1_CASZ_Pos (24UL) /*!< CASZ (Bit 24) */
|
|
#define MCM_MLMDR1_CASZ_Msk (0xf000000UL) /*!< CASZ (Bitfield-Mask: 0x0f) */
|
|
/* ======================================================== LMPECR ========================================================= */
|
|
#define MCM_LMPECR_CPEIEN_Pos (20UL) /*!< CPEIEN (Bit 20) */
|
|
#define MCM_LMPECR_CPEIEN_Msk (0x100000UL) /*!< CPEIEN (Bitfield-Mask: 0x01) */
|
|
/* ======================================================== LMPEIR ========================================================= */
|
|
/* ========================================================= LMFAR ========================================================= */
|
|
/* ========================================================= MCCR ========================================================== */
|
|
#define MCM_MCCR_CADIS_Pos (0UL) /*!< CADIS (Bit 0) */
|
|
#define MCM_MCCR_CADIS_Msk (0x1UL) /*!< CADIS (Bitfield-Mask: 0x01) */
|
|
#define MCM_MCCR_CACL_Pos (1UL) /*!< CACL (Bit 1) */
|
|
#define MCM_MCCR_CACL_Msk (0x2UL) /*!< CACL (Bitfield-Mask: 0x01) */
|
|
/* ========================================================= MNCR ========================================================== */
|
|
#define MCM_MNCR_NMI_EN_Pos (0UL) /*!< NMI_EN (Bit 0) */
|
|
#define MCM_MNCR_NMI_EN_Msk (0x1UL) /*!< NMI_EN (Bitfield-Mask: 0x01) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ MPU ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================= CESR ========================================================== */
|
|
#define MPU_CESR_VLD_Pos (0UL) /*!< VLD (Bit 0) */
|
|
#define MPU_CESR_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */
|
|
#define MPU_CESR_SPERR0_Pos (29UL) /*!< SPERR0 (Bit 29) */
|
|
#define MPU_CESR_SPERR0_Msk (0x20000000UL) /*!< SPERR0 (Bitfield-Mask: 0x01) */
|
|
#define MPU_CESR_SPERR1_Pos (30UL) /*!< SPERR1 (Bit 30) */
|
|
#define MPU_CESR_SPERR1_Msk (0x40000000UL) /*!< SPERR1 (Bitfield-Mask: 0x01) */
|
|
#define MPU_CESR_SPERR2_Pos (31UL) /*!< SPERR2 (Bit 31) */
|
|
#define MPU_CESR_SPERR2_Msk (0x80000000UL) /*!< SPERR2 (Bitfield-Mask: 0x01) */
|
|
/* ========================================================= EAR0 ========================================================== */
|
|
#define MPU_EAR0_EADDR_Pos (0UL) /*!< EADDR (Bit 0) */
|
|
#define MPU_EAR0_EADDR_Msk (0xffffffffUL) /*!< EADDR (Bitfield-Mask: 0xffffffff) */
|
|
/* ========================================================= EAR1 ========================================================== */
|
|
#define MPU_EAR1_EADDR_Pos (0UL) /*!< EADDR (Bit 0) */
|
|
#define MPU_EAR1_EADDR_Msk (0xffffffffUL) /*!< EADDR (Bitfield-Mask: 0xffffffff) */
|
|
/* ========================================================= EAR2 ========================================================== */
|
|
#define MPU_EAR2_EADDR_Pos (0UL) /*!< EADDR (Bit 0) */
|
|
#define MPU_EAR2_EADDR_Msk (0xffffffffUL) /*!< EADDR (Bitfield-Mask: 0xffffffff) */
|
|
/* ========================================================= EDR0 ========================================================== */
|
|
#define MPU_EDR0_ERW_Pos (0UL) /*!< ERW (Bit 0) */
|
|
#define MPU_EDR0_ERW_Msk (0x1UL) /*!< ERW (Bitfield-Mask: 0x01) */
|
|
#define MPU_EDR0_EATTR_Pos (1UL) /*!< EATTR (Bit 1) */
|
|
#define MPU_EDR0_EATTR_Msk (0x1eUL) /*!< EATTR (Bitfield-Mask: 0x0f) */
|
|
#define MPU_EDR0_EMN_Pos (5UL) /*!< EMN (Bit 5) */
|
|
#define MPU_EDR0_EMN_Msk (0xe0UL) /*!< EMN (Bitfield-Mask: 0x07) */
|
|
#define MPU_EDR0_EPID_Pos (8UL) /*!< EPID (Bit 8) */
|
|
#define MPU_EDR0_EPID_Msk (0xff00UL) /*!< EPID (Bitfield-Mask: 0xff) */
|
|
#define MPU_EDR0_EACD_Pos (16UL) /*!< EACD (Bit 16) */
|
|
#define MPU_EDR0_EACD_Msk (0xff0000UL) /*!< EACD (Bitfield-Mask: 0xff) */
|
|
#define MPU_EDR0_EFLG_Pos (31UL) /*!< EFLG (Bit 31) */
|
|
#define MPU_EDR0_EFLG_Msk (0x80000000UL) /*!< EFLG (Bitfield-Mask: 0x01) */
|
|
/* ========================================================= EDR1 ========================================================== */
|
|
#define MPU_EDR1_ERW_Pos (0UL) /*!< ERW (Bit 0) */
|
|
#define MPU_EDR1_ERW_Msk (0x1UL) /*!< ERW (Bitfield-Mask: 0x01) */
|
|
#define MPU_EDR1_EATTR_Pos (1UL) /*!< EATTR (Bit 1) */
|
|
#define MPU_EDR1_EATTR_Msk (0x1eUL) /*!< EATTR (Bitfield-Mask: 0x0f) */
|
|
#define MPU_EDR1_EMN_Pos (5UL) /*!< EMN (Bit 5) */
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#define MPU_EDR1_EMN_Msk (0xe0UL) /*!< EMN (Bitfield-Mask: 0x07) */
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#define MPU_EDR1_EPID_Pos (8UL) /*!< EPID (Bit 8) */
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#define MPU_EDR1_EPID_Msk (0xff00UL) /*!< EPID (Bitfield-Mask: 0xff) */
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#define MPU_EDR1_EACD_Pos (16UL) /*!< EACD (Bit 16) */
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#define MPU_EDR1_EACD_Msk (0xff0000UL) /*!< EACD (Bitfield-Mask: 0xff) */
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#define MPU_EDR1_EFLG_Pos (31UL) /*!< EFLG (Bit 31) */
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#define MPU_EDR1_EFLG_Msk (0x80000000UL) /*!< EFLG (Bitfield-Mask: 0x01) */
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/* ========================================================= EDR2 ========================================================== */
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#define MPU_EDR2_ERW_Pos (0UL) /*!< ERW (Bit 0) */
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#define MPU_EDR2_ERW_Msk (0x1UL) /*!< ERW (Bitfield-Mask: 0x01) */
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#define MPU_EDR2_EATTR_Pos (1UL) /*!< EATTR (Bit 1) */
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#define MPU_EDR2_EATTR_Msk (0x1eUL) /*!< EATTR (Bitfield-Mask: 0x0f) */
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#define MPU_EDR2_EMN_Pos (5UL) /*!< EMN (Bit 5) */
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#define MPU_EDR2_EMN_Msk (0xe0UL) /*!< EMN (Bitfield-Mask: 0x07) */
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#define MPU_EDR2_EPID_Pos (8UL) /*!< EPID (Bit 8) */
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#define MPU_EDR2_EPID_Msk (0xff00UL) /*!< EPID (Bitfield-Mask: 0xff) */
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#define MPU_EDR2_EACD_Pos (16UL) /*!< EACD (Bit 16) */
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#define MPU_EDR2_EACD_Msk (0xff0000UL) /*!< EACD (Bitfield-Mask: 0xff) */
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#define MPU_EDR2_EFLG_Pos (31UL) /*!< EFLG (Bit 31) */
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#define MPU_EDR2_EFLG_Msk (0x80000000UL) /*!< EFLG (Bitfield-Mask: 0x01) */
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/* ========================================================= MPID ========================================================== */
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#define MPU_MPID_M0PID_Pos (0UL) /*!< M0PID (Bit 0) */
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#define MPU_MPID_M0PID_Msk (0xffUL) /*!< M0PID (Bitfield-Mask: 0xff) */
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#define MPU_MPID_M1PID_Pos (8UL) /*!< M1PID (Bit 8) */
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#define MPU_MPID_M1PID_Msk (0xff00UL) /*!< M1PID (Bitfield-Mask: 0xff) */
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/* ====================================================== RGD0_WORD0 ======================================================= */
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#define MPU_RGD0_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */
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#define MPU_RGD0_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD0_WORD1 ======================================================= */
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#define MPU_RGD0_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */
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#define MPU_RGD0_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD0_WORD2 ======================================================= */
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#define MPU_RGD0_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGD0_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGD0_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGD0_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGD0_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGD0_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGD0_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGD0_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGD0_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGD0_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGD0_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGD0_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGD0_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGD0_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGD0_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGD0_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGD0_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGD0_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ====================================================== RGD0_WORD3 ======================================================= */
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|
#define MPU_RGD0_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */
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#define MPU_RGD0_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */
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#define MPU_RGD0_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */
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#define MPU_RGD0_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */
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#define MPU_RGD0_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */
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#define MPU_RGD0_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */
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/* ====================================================== RGD1_WORD0 ======================================================= */
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|
#define MPU_RGD1_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */
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#define MPU_RGD1_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD1_WORD1 ======================================================= */
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#define MPU_RGD1_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */
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#define MPU_RGD1_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD1_WORD2 ======================================================= */
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#define MPU_RGD1_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGD1_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGD1_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGD1_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGD1_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGD1_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGD1_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGD1_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGD1_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGD1_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGD1_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGD1_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGD1_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGD1_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGD1_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGD1_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGD1_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGD1_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ====================================================== RGD1_WORD3 ======================================================= */
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#define MPU_RGD1_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */
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#define MPU_RGD1_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */
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#define MPU_RGD1_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */
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#define MPU_RGD1_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */
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#define MPU_RGD1_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */
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#define MPU_RGD1_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */
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/* ====================================================== RGD2_WORD0 ======================================================= */
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#define MPU_RGD2_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */
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#define MPU_RGD2_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD2_WORD1 ======================================================= */
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#define MPU_RGD2_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */
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#define MPU_RGD2_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD2_WORD2 ======================================================= */
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#define MPU_RGD2_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGD2_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGD2_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGD2_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGD2_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGD2_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGD2_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGD2_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGD2_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGD2_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGD2_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGD2_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGD2_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGD2_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGD2_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGD2_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGD2_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGD2_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ====================================================== RGD2_WORD3 ======================================================= */
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#define MPU_RGD2_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */
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#define MPU_RGD2_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */
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#define MPU_RGD2_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */
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#define MPU_RGD2_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */
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#define MPU_RGD2_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */
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#define MPU_RGD2_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */
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/* ====================================================== RGD3_WORD0 ======================================================= */
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#define MPU_RGD3_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */
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#define MPU_RGD3_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD3_WORD1 ======================================================= */
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|
#define MPU_RGD3_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */
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#define MPU_RGD3_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD3_WORD2 ======================================================= */
|
|
#define MPU_RGD3_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGD3_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGD3_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGD3_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGD3_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGD3_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGD3_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGD3_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGD3_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGD3_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGD3_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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|
#define MPU_RGD3_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGD3_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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|
#define MPU_RGD3_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGD3_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGD3_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGD3_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGD3_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGD3_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGD3_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ====================================================== RGD3_WORD3 ======================================================= */
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#define MPU_RGD3_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */
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#define MPU_RGD3_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */
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#define MPU_RGD3_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */
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#define MPU_RGD3_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */
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#define MPU_RGD3_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */
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#define MPU_RGD3_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */
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/* ====================================================== RGD4_WORD0 ======================================================= */
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#define MPU_RGD4_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */
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#define MPU_RGD4_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD4_WORD1 ======================================================= */
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#define MPU_RGD4_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */
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#define MPU_RGD4_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD4_WORD2 ======================================================= */
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#define MPU_RGD4_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGD4_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGD4_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGD4_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGD4_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGD4_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGD4_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGD4_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGD4_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGD4_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGD4_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGD4_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGD4_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGD4_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGD4_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGD4_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGD4_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGD4_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ====================================================== RGD4_WORD3 ======================================================= */
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#define MPU_RGD4_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */
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#define MPU_RGD4_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */
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#define MPU_RGD4_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */
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#define MPU_RGD4_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */
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#define MPU_RGD4_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */
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#define MPU_RGD4_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */
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/* ====================================================== RGD5_WORD0 ======================================================= */
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#define MPU_RGD5_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */
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#define MPU_RGD5_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD5_WORD1 ======================================================= */
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#define MPU_RGD5_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */
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#define MPU_RGD5_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD5_WORD2 ======================================================= */
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#define MPU_RGD5_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGD5_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGD5_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGD5_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGD5_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGD5_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGD5_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGD5_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGD5_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGD5_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGD5_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGD5_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGD5_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGD5_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGD5_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGD5_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGD5_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGD5_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ====================================================== RGD5_WORD3 ======================================================= */
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#define MPU_RGD5_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */
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#define MPU_RGD5_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */
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#define MPU_RGD5_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */
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#define MPU_RGD5_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */
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#define MPU_RGD5_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */
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#define MPU_RGD5_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */
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/* ====================================================== RGD6_WORD0 ======================================================= */
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#define MPU_RGD6_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */
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#define MPU_RGD6_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD6_WORD1 ======================================================= */
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#define MPU_RGD6_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */
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#define MPU_RGD6_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD6_WORD2 ======================================================= */
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#define MPU_RGD6_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGD6_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGD6_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGD6_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGD6_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGD6_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGD6_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGD6_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGD6_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGD6_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGD6_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGD6_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGD6_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGD6_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGD6_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGD6_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGD6_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGD6_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ====================================================== RGD6_WORD3 ======================================================= */
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#define MPU_RGD6_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */
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#define MPU_RGD6_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */
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#define MPU_RGD6_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */
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#define MPU_RGD6_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */
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#define MPU_RGD6_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */
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#define MPU_RGD6_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */
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/* ====================================================== RGD7_WORD0 ======================================================= */
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#define MPU_RGD7_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */
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#define MPU_RGD7_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD7_WORD1 ======================================================= */
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#define MPU_RGD7_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */
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#define MPU_RGD7_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */
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/* ====================================================== RGD7_WORD2 ======================================================= */
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#define MPU_RGD7_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGD7_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGD7_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGD7_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGD7_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGD7_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGD7_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGD7_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGD7_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGD7_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGD7_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGD7_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGD7_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGD7_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGD7_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGD7_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGD7_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGD7_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ====================================================== RGD7_WORD3 ======================================================= */
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#define MPU_RGD7_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */
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#define MPU_RGD7_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */
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#define MPU_RGD7_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */
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#define MPU_RGD7_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */
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#define MPU_RGD7_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */
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#define MPU_RGD7_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */
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/* ======================================================== RGDAAC0 ======================================================== */
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#define MPU_RGDAAC0_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGDAAC0_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGDAAC0_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGDAAC0_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGDAAC0_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGDAAC0_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGDAAC0_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGDAAC0_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGDAAC0_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGDAAC0_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGDAAC0_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGDAAC0_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGDAAC0_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGDAAC0_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGDAAC0_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGDAAC0_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGDAAC0_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC0_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGDAAC0_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ======================================================== RGDAAC1 ======================================================== */
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#define MPU_RGDAAC1_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGDAAC1_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGDAAC1_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGDAAC1_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGDAAC1_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGDAAC1_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGDAAC1_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGDAAC1_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGDAAC1_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGDAAC1_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGDAAC1_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGDAAC1_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGDAAC1_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGDAAC1_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGDAAC1_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGDAAC1_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGDAAC1_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC1_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGDAAC1_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ======================================================== RGDAAC2 ======================================================== */
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#define MPU_RGDAAC2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGDAAC2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGDAAC2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGDAAC2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGDAAC2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGDAAC2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGDAAC2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGDAAC2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGDAAC2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGDAAC2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGDAAC2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGDAAC2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGDAAC2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGDAAC2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGDAAC2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGDAAC2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGDAAC2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGDAAC2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ======================================================== RGDAAC3 ======================================================== */
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#define MPU_RGDAAC3_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGDAAC3_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGDAAC3_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGDAAC3_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGDAAC3_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGDAAC3_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGDAAC3_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGDAAC3_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGDAAC3_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGDAAC3_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGDAAC3_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGDAAC3_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGDAAC3_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGDAAC3_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGDAAC3_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGDAAC3_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGDAAC3_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC3_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGDAAC3_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ======================================================== RGDAAC4 ======================================================== */
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#define MPU_RGDAAC4_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGDAAC4_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGDAAC4_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGDAAC4_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGDAAC4_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGDAAC4_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGDAAC4_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGDAAC4_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGDAAC4_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGDAAC4_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGDAAC4_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGDAAC4_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGDAAC4_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGDAAC4_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGDAAC4_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGDAAC4_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGDAAC4_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC4_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGDAAC4_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ======================================================== RGDAAC5 ======================================================== */
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#define MPU_RGDAAC5_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGDAAC5_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGDAAC5_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGDAAC5_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGDAAC5_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGDAAC5_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGDAAC5_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGDAAC5_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGDAAC5_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGDAAC5_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGDAAC5_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGDAAC5_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGDAAC5_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGDAAC5_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGDAAC5_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGDAAC5_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGDAAC5_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC5_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGDAAC5_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ======================================================== RGDAAC6 ======================================================== */
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#define MPU_RGDAAC6_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGDAAC6_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGDAAC6_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGDAAC6_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGDAAC6_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGDAAC6_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGDAAC6_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGDAAC6_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGDAAC6_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGDAAC6_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGDAAC6_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGDAAC6_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGDAAC6_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGDAAC6_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGDAAC6_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGDAAC6_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGDAAC6_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC6_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGDAAC6_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* ======================================================== RGDAAC7 ======================================================== */
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#define MPU_RGDAAC7_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */
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#define MPU_RGDAAC7_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */
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#define MPU_RGDAAC7_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */
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#define MPU_RGDAAC7_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */
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#define MPU_RGDAAC7_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */
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#define MPU_RGDAAC7_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */
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#define MPU_RGDAAC7_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */
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#define MPU_RGDAAC7_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */
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#define MPU_RGDAAC7_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */
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#define MPU_RGDAAC7_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */
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#define MPU_RGDAAC7_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */
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#define MPU_RGDAAC7_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */
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#define MPU_RGDAAC7_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */
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#define MPU_RGDAAC7_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */
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#define MPU_RGDAAC7_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */
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#define MPU_RGDAAC7_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */
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#define MPU_RGDAAC7_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */
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#define MPU_RGDAAC7_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */
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#define MPU_RGDAAC7_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ CKGEN ================ */
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/* =========================================================================================================================== */
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/* ========================================================= CTRL ========================================================== */
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#define CKGEN_CTRL_BUS_CLK_DIV_VLPR_Pos (0UL) /*!< BUS_CLK_DIV_VLPR (Bit 0) */
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#define CKGEN_CTRL_BUS_CLK_DIV_VLPR_Msk (0xfUL) /*!< BUS_CLK_DIV_VLPR (Bitfield-Mask: 0x0f) */
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#define CKGEN_CTRL_BUS_CLK_DIV_RUN_Pos (4UL) /*!< BUS_CLK_DIV_RUN (Bit 4) */
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#define CKGEN_CTRL_BUS_CLK_DIV_RUN_Msk (0xf0UL) /*!< BUS_CLK_DIV_RUN (Bitfield-Mask: 0x0f) */
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#define CKGEN_CTRL_SYSCLK_DIV_VLPR_Pos (12UL) /*!< SYSCLK_DIV_VLPR (Bit 12) */
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#define CKGEN_CTRL_SYSCLK_DIV_VLPR_Msk (0xf000UL) /*!< SYSCLK_DIV_VLPR (Bitfield-Mask: 0x0f) */
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#define CKGEN_CTRL_SYSCLK_DIV_Pos (16UL) /*!< SYSCLK_DIV (Bit 16) */
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#define CKGEN_CTRL_SYSCLK_DIV_Msk (0xf0000UL) /*!< SYSCLK_DIV (Bitfield-Mask: 0x0f) */
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#define CKGEN_CTRL_PLL_REF_SEL_Pos (20UL) /*!< PLL_REF_SEL (Bit 20) */
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#define CKGEN_CTRL_PLL_REF_SEL_Msk (0x100000UL) /*!< PLL_REF_SEL (Bitfield-Mask: 0x01) */
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#define CKGEN_CTRL_XOSC_MON_EN_Pos (21UL) /*!< XOSC_MON_EN (Bit 21) */
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#define CKGEN_CTRL_XOSC_MON_EN_Msk (0x200000UL) /*!< XOSC_MON_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos (22UL) /*!< SYSCLK_SRC_SEL_RUN (Bit 22) */
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#define CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk (0x3c00000UL) /*!< SYSCLK_SRC_SEL_RUN (Bitfield-Mask: 0x0f) */
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#define CKGEN_CTRL_SYSCLK_SRC_SEL_VLPR_Pos (26UL) /*!< SYSCLK_SRC_SEL_VLPR (Bit 26) */
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#define CKGEN_CTRL_SYSCLK_SRC_SEL_VLPR_Msk (0x3c000000UL) /*!< SYSCLK_SRC_SEL_VLPR (Bitfield-Mask: 0x0f) */
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#define CKGEN_CTRL_LOCK_Pos (31UL) /*!< LOCK (Bit 31) */
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#define CKGEN_CTRL_LOCK_Msk (0x80000000UL) /*!< LOCK (Bitfield-Mask: 0x01) */
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/* ====================================================== LP_CLK_MUX ======================================================= */
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#define CKGEN_LP_CLK_MUX_LSI_CLK_MUX_Pos (0UL) /*!< LSI_CLK_MUX (Bit 0) */
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#define CKGEN_LP_CLK_MUX_LSI_CLK_MUX_Msk (0x3UL) /*!< LSI_CLK_MUX (Bitfield-Mask: 0x03) */
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#define CKGEN_LP_CLK_MUX_RTC_CLK_MUX_Pos (2UL) /*!< RTC_CLK_MUX (Bit 2) */
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#define CKGEN_LP_CLK_MUX_RTC_CLK_MUX_Msk (0xcUL) /*!< RTC_CLK_MUX (Bitfield-Mask: 0x03) */
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/* ===================================================== PERI_CLK_EN0 ====================================================== */
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#define CKGEN_PERI_CLK_EN0_UART0_EN_Pos (0UL) /*!< UART0_EN (Bit 0) */
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#define CKGEN_PERI_CLK_EN0_UART0_EN_Msk (0x1UL) /*!< UART0_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_UART1_EN_Pos (1UL) /*!< UART1_EN (Bit 1) */
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#define CKGEN_PERI_CLK_EN0_UART1_EN_Msk (0x2UL) /*!< UART1_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_UART2_EN_Pos (2UL) /*!< UART2_EN (Bit 2) */
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#define CKGEN_PERI_CLK_EN0_UART2_EN_Msk (0x4UL) /*!< UART2_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_UART3_EN_Pos (3UL) /*!< UART3_EN (Bit 3) */
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#define CKGEN_PERI_CLK_EN0_UART3_EN_Msk (0x8UL) /*!< UART3_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_SPI0_EN_Pos (6UL) /*!< SPI0_EN (Bit 6) */
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#define CKGEN_PERI_CLK_EN0_SPI0_EN_Msk (0x40UL) /*!< SPI0_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_SPI1_EN_Pos (7UL) /*!< SPI1_EN (Bit 7) */
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#define CKGEN_PERI_CLK_EN0_SPI1_EN_Msk (0x80UL) /*!< SPI1_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_SPI2_EN_Pos (8UL) /*!< SPI2_EN (Bit 8) */
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#define CKGEN_PERI_CLK_EN0_SPI2_EN_Msk (0x100UL) /*!< SPI2_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_I2C0_EN_Pos (9UL) /*!< I2C0_EN (Bit 9) */
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#define CKGEN_PERI_CLK_EN0_I2C0_EN_Msk (0x200UL) /*!< I2C0_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_PCT_EN_Pos (11UL) /*!< PCT_EN (Bit 11) */
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#define CKGEN_PERI_CLK_EN0_PCT_EN_Msk (0x800UL) /*!< PCT_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_PWM0_EN_Pos (15UL) /*!< PWM0_EN (Bit 15) */
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#define CKGEN_PERI_CLK_EN0_PWM0_EN_Msk (0x8000UL) /*!< PWM0_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_PWM1_EN_Pos (16UL) /*!< PWM1_EN (Bit 16) */
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#define CKGEN_PERI_CLK_EN0_PWM1_EN_Msk (0x10000UL) /*!< PWM1_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_PWM2_EN_Pos (17UL) /*!< PWM2_EN (Bit 17) */
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#define CKGEN_PERI_CLK_EN0_PWM2_EN_Msk (0x20000UL) /*!< PWM2_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_PWM3_EN_Pos (18UL) /*!< PWM3_EN (Bit 18) */
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#define CKGEN_PERI_CLK_EN0_PWM3_EN_Msk (0x40000UL) /*!< PWM3_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_PWM4_EN_Pos (19UL) /*!< PWM4_EN (Bit 19) */
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#define CKGEN_PERI_CLK_EN0_PWM4_EN_Msk (0x80000UL) /*!< PWM4_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN0_PWM5_EN_Pos (20UL) /*!< PWM5_EN (Bit 20) */
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#define CKGEN_PERI_CLK_EN0_PWM5_EN_Msk (0x100000UL) /*!< PWM5_EN (Bitfield-Mask: 0x01) */
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/* ===================================================== PERI_CLK_EN1 ====================================================== */
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#define CKGEN_PERI_CLK_EN1_RTC_EN_Pos (1UL) /*!< RTC_EN (Bit 1) */
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#define CKGEN_PERI_CLK_EN1_RTC_EN_Msk (0x2UL) /*!< RTC_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN1_DMA_EN_Pos (2UL) /*!< DMA_EN (Bit 2) */
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#define CKGEN_PERI_CLK_EN1_DMA_EN_Msk (0x4UL) /*!< DMA_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN1_GPIO_EN_Pos (5UL) /*!< GPIO_EN (Bit 5) */
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#define CKGEN_PERI_CLK_EN1_GPIO_EN_Msk (0x20UL) /*!< GPIO_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN1_WDG_EN_Pos (6UL) /*!< WDG_EN (Bit 6) */
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#define CKGEN_PERI_CLK_EN1_WDG_EN_Msk (0x40UL) /*!< WDG_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN1_EWDG_EN_Pos (7UL) /*!< EWDG_EN (Bit 7) */
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#define CKGEN_PERI_CLK_EN1_EWDG_EN_Msk (0x80UL) /*!< EWDG_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN1_CRC_EN_Pos (8UL) /*!< CRC_EN (Bit 8) */
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#define CKGEN_PERI_CLK_EN1_CRC_EN_Msk (0x100UL) /*!< CRC_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN1_CAN0_EN_Pos (9UL) /*!< CAN0_EN (Bit 9) */
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#define CKGEN_PERI_CLK_EN1_CAN0_EN_Msk (0x200UL) /*!< CAN0_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN1_CAN1_EN_Pos (10UL) /*!< CAN1_EN (Bit 10) */
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#define CKGEN_PERI_CLK_EN1_CAN1_EN_Msk (0x400UL) /*!< CAN1_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN1_CAN2_EN_Pos (11UL) /*!< CAN2_EN (Bit 11) */
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#define CKGEN_PERI_CLK_EN1_CAN2_EN_Msk (0x800UL) /*!< CAN2_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN1_CAN3_EN_Pos (12UL) /*!< CAN3_EN (Bit 12) */
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#define CKGEN_PERI_CLK_EN1_CAN3_EN_Msk (0x1000UL) /*!< CAN3_EN (Bitfield-Mask: 0x01) */
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/* ===================================================== PERI_CLK_EN2 ====================================================== */
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#define CKGEN_PERI_CLK_EN2_CTU_EN_Pos (1UL) /*!< CTU_EN (Bit 1) */
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#define CKGEN_PERI_CLK_EN2_CTU_EN_Msk (0x2UL) /*!< CTU_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN2_ACMP_EN_Pos (8UL) /*!< ACMP_EN (Bit 8) */
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#define CKGEN_PERI_CLK_EN2_ACMP_EN_Msk (0x100UL) /*!< ACMP_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN2_PDT0_EN_Pos (9UL) /*!< PDT0_EN (Bit 9) */
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#define CKGEN_PERI_CLK_EN2_PDT0_EN_Msk (0x200UL) /*!< PDT0_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN2_PDT1_EN_Pos (10UL) /*!< PDT1_EN (Bit 10) */
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#define CKGEN_PERI_CLK_EN2_PDT1_EN_Msk (0x400UL) /*!< PDT1_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN2_ADC0_EN_Pos (11UL) /*!< ADC0_EN (Bit 11) */
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#define CKGEN_PERI_CLK_EN2_ADC0_EN_Msk (0x800UL) /*!< ADC0_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN2_ADC1_EN_Pos (12UL) /*!< ADC1_EN (Bit 12) */
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#define CKGEN_PERI_CLK_EN2_ADC1_EN_Msk (0x1000UL) /*!< ADC1_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN2_TIMER_EN_Pos (13UL) /*!< TIMER_EN (Bit 13) */
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#define CKGEN_PERI_CLK_EN2_TIMER_EN_Msk (0x2000UL) /*!< TIMER_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN2_EIO_EN_Pos (14UL) /*!< EIO_EN (Bit 14) */
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#define CKGEN_PERI_CLK_EN2_EIO_EN_Msk (0x4000UL) /*!< EIO_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_EN2_SMU_EN_Pos (19UL) /*!< SMU_EN (Bit 19) */
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#define CKGEN_PERI_CLK_EN2_SMU_EN_Msk (0x80000UL) /*!< SMU_EN (Bitfield-Mask: 0x01) */
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/* ======================================================= RCM_CTRL ======================================================== */
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#define CKGEN_RCM_CTRL_EXT_RST_FILTER_EN_Pos (0UL) /*!< EXT_RST_FILTER_EN (Bit 0) */
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#define CKGEN_RCM_CTRL_EXT_RST_FILTER_EN_Msk (0x1UL) /*!< EXT_RST_FILTER_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_CTRL_EXT_RST_FILTER_VAL_Pos (1UL) /*!< EXT_RST_FILTER_VAL (Bit 1) */
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#define CKGEN_RCM_CTRL_EXT_RST_FILTER_VAL_Msk (0xfeUL) /*!< EXT_RST_FILTER_VAL (Bitfield-Mask: 0x7f) */
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#define CKGEN_RCM_CTRL_RST_DLY_TIME_Pos (8UL) /*!< RST_DLY_TIME (Bit 8) */
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#define CKGEN_RCM_CTRL_RST_DLY_TIME_Msk (0x300UL) /*!< RST_DLY_TIME (Bitfield-Mask: 0x03) */
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#define CKGEN_RCM_CTRL_SW_RST_INT_EN_Pos (10UL) /*!< SW_RST_INT_EN (Bit 10) */
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#define CKGEN_RCM_CTRL_SW_RST_INT_EN_Msk (0x400UL) /*!< SW_RST_INT_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_CTRL_LOCKUP_RST_INT_EN_Pos (11UL) /*!< LOCKUP_RST_INT_EN (Bit 11) */
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#define CKGEN_RCM_CTRL_LOCKUP_RST_INT_EN_Msk (0x800UL) /*!< LOCKUP_RST_INT_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_CTRL_ACK_ERR_RST_INT_EN_Pos (12UL) /*!< ACK_ERR_RST_INT_EN (Bit 12) */
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#define CKGEN_RCM_CTRL_ACK_ERR_RST_INT_EN_Msk (0x1000UL) /*!< ACK_ERR_RST_INT_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_CTRL_WDG_RST_INT_EN_Pos (13UL) /*!< WDG_RST_INT_EN (Bit 13) */
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#define CKGEN_RCM_CTRL_WDG_RST_INT_EN_Msk (0x2000UL) /*!< WDG_RST_INT_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_CTRL_XOSC_LOSS_RST_INT_EN_Pos (15UL) /*!< XOSC_LOSS_RST_INT_EN (Bit 15) */
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#define CKGEN_RCM_CTRL_XOSC_LOSS_RST_INT_EN_Msk (0x8000UL) /*!< XOSC_LOSS_RST_INT_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_CTRL_PLL_UNLOCK_RST_INT_EN_Pos (16UL) /*!< PLL_UNLOCK_RST_INT_EN (Bit 16) */
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#define CKGEN_RCM_CTRL_PLL_UNLOCK_RST_INT_EN_Msk (0x10000UL) /*!< PLL_UNLOCK_RST_INT_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_CTRL_VHSI_LOSS_RST_INT_EN_Pos (17UL) /*!< VHSI_LOSS_RST_INT_EN (Bit 17) */
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#define CKGEN_RCM_CTRL_VHSI_LOSS_RST_INT_EN_Msk (0x20000UL) /*!< VHSI_LOSS_RST_INT_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_CTRL_SMU_ERR_RST_INT_EN_Pos (19UL) /*!< SMU_ERR_RST_INT_EN (Bit 19) */
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#define CKGEN_RCM_CTRL_SMU_ERR_RST_INT_EN_Msk (0x80000UL) /*!< SMU_ERR_RST_INT_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_CTRL_ECC2_ERR_RST_INT_EN_Pos (20UL) /*!< ECC2_ERR_RST_INT_EN (Bit 20) */
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#define CKGEN_RCM_CTRL_ECC2_ERR_RST_INT_EN_Msk (0x100000UL) /*!< ECC2_ERR_RST_INT_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_CTRL_RST_CLK_SEL_Pos (22UL) /*!< RST_CLK_SEL (Bit 22) */
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#define CKGEN_RCM_CTRL_RST_CLK_SEL_Msk (0x400000UL) /*!< RST_CLK_SEL (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_CTRL_RST_GLB_INT_EN_Pos (23UL) /*!< RST_GLB_INT_EN (Bit 23) */
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#define CKGEN_RCM_CTRL_RST_GLB_INT_EN_Msk (0x800000UL) /*!< RST_GLB_INT_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_CTRL_RST_CLK_AUTO_SEL_Pos (31UL) /*!< RST_CLK_AUTO_SEL (Bit 31) */
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#define CKGEN_RCM_CTRL_RST_CLK_AUTO_SEL_Msk (0x80000000UL) /*!< RST_CLK_AUTO_SEL (Bitfield-Mask: 0x01) */
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/* ======================================================== RCM_EN ========================================================= */
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#define CKGEN_RCM_EN_SW_RST_EN_Pos (0UL) /*!< SW_RST_EN (Bit 0) */
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#define CKGEN_RCM_EN_SW_RST_EN_Msk (0x1UL) /*!< SW_RST_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_EN_LOCKUP_RST_EN_Pos (1UL) /*!< LOCKUP_RST_EN (Bit 1) */
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#define CKGEN_RCM_EN_LOCKUP_RST_EN_Msk (0x2UL) /*!< LOCKUP_RST_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_EN_ACK_ERR_RST_EN_Pos (2UL) /*!< ACK_ERR_RST_EN (Bit 2) */
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#define CKGEN_RCM_EN_ACK_ERR_RST_EN_Msk (0x4UL) /*!< ACK_ERR_RST_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_EN_WDG_RST_EN_Pos (3UL) /*!< WDG_RST_EN (Bit 3) */
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#define CKGEN_RCM_EN_WDG_RST_EN_Msk (0x8UL) /*!< WDG_RST_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_EN_XOSC_LOSS_RST_EN_Pos (5UL) /*!< XOSC_LOSS_RST_EN (Bit 5) */
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#define CKGEN_RCM_EN_XOSC_LOSS_RST_EN_Msk (0x20UL) /*!< XOSC_LOSS_RST_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_EN_PLL_UNLOCK_RST_EN_Pos (6UL) /*!< PLL_UNLOCK_RST_EN (Bit 6) */
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#define CKGEN_RCM_EN_PLL_UNLOCK_RST_EN_Msk (0x40UL) /*!< PLL_UNLOCK_RST_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_EN_VHSI_LOSS_RST_EN_Pos (7UL) /*!< VHSI_LOSS_RST_EN (Bit 7) */
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#define CKGEN_RCM_EN_VHSI_LOSS_RST_EN_Msk (0x80UL) /*!< VHSI_LOSS_RST_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_EN_EXT_RST_EN_Pos (8UL) /*!< EXT_RST_EN (Bit 8) */
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#define CKGEN_RCM_EN_EXT_RST_EN_Msk (0x100UL) /*!< EXT_RST_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_EN_SMU_ERR_RST_EN_Pos (9UL) /*!< SMU_ERR_RST_EN (Bit 9) */
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#define CKGEN_RCM_EN_SMU_ERR_RST_EN_Msk (0x200UL) /*!< SMU_ERR_RST_EN (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_EN_ECC2_ERR_RST_EN_Pos (10UL) /*!< ECC2_ERR_RST_EN (Bit 10) */
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#define CKGEN_RCM_EN_ECC2_ERR_RST_EN_Msk (0x400UL) /*!< ECC2_ERR_RST_EN (Bitfield-Mask: 0x01) */
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/* ====================================================== RCM_STATUS ======================================================= */
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#define CKGEN_RCM_STATUS_SW_RST_INT_FLAG_Pos (0UL) /*!< SW_RST_INT_FLAG (Bit 0) */
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#define CKGEN_RCM_STATUS_SW_RST_INT_FLAG_Msk (0x1UL) /*!< SW_RST_INT_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_LOCKUP_RST_INT_FLAG_Pos (1UL) /*!< LOCKUP_RST_INT_FLAG (Bit 1) */
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#define CKGEN_RCM_STATUS_LOCKUP_RST_INT_FLAG_Msk (0x2UL) /*!< LOCKUP_RST_INT_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_ACK_ERR_RST_INT_FLAG_Pos (2UL) /*!< ACK_ERR_RST_INT_FLAG (Bit 2) */
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#define CKGEN_RCM_STATUS_ACK_ERR_RST_INT_FLAG_Msk (0x4UL) /*!< ACK_ERR_RST_INT_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_WDG_RST_INT_FLAG_Pos (3UL) /*!< WDG_RST_INT_FLAG (Bit 3) */
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#define CKGEN_RCM_STATUS_WDG_RST_INT_FLAG_Msk (0x8UL) /*!< WDG_RST_INT_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_XOSC_LOSS_RST_INT_FLAG_Pos (5UL) /*!< XOSC_LOSS_RST_INT_FLAG (Bit 5) */
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#define CKGEN_RCM_STATUS_XOSC_LOSS_RST_INT_FLAG_Msk (0x20UL) /*!< XOSC_LOSS_RST_INT_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_PLL_UNLOCK_RST_INT_FLAG_Pos (6UL) /*!< PLL_UNLOCK_RST_INT_FLAG (Bit 6) */
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#define CKGEN_RCM_STATUS_PLL_UNLOCK_RST_INT_FLAG_Msk (0x40UL) /*!< PLL_UNLOCK_RST_INT_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_VHSI_LOSS_RST_INT_FLAG_Pos (7UL) /*!< VHSI_LOSS_RST_INT_FLAG (Bit 7) */
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#define CKGEN_RCM_STATUS_VHSI_LOSS_RST_INT_FLAG_Msk (0x80UL) /*!< VHSI_LOSS_RST_INT_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_SMU_ERR_RST_INT_FLAG_Pos (9UL) /*!< SMU_ERR_RST_INT_FLAG (Bit 9) */
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#define CKGEN_RCM_STATUS_SMU_ERR_RST_INT_FLAG_Msk (0x200UL) /*!< SMU_ERR_RST_INT_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_ECC2_ERR_RST_INT_FLAG_Pos (10UL) /*!< ECC2_ERR_RST_INT_FLAG (Bit 10) */
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#define CKGEN_RCM_STATUS_ECC2_ERR_RST_INT_FLAG_Msk (0x400UL) /*!< ECC2_ERR_RST_INT_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_RST_INT_STATUS_CLR_Pos (15UL) /*!< RST_INT_STATUS_CLR (Bit 15) */
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#define CKGEN_RCM_STATUS_RST_INT_STATUS_CLR_Msk (0x8000UL) /*!< RST_INT_STATUS_CLR (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_POR_RST_FLAG_Pos (16UL) /*!< POR_RST_FLAG (Bit 16) */
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#define CKGEN_RCM_STATUS_POR_RST_FLAG_Msk (0x10000UL) /*!< POR_RST_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_LVR_RST_FLAG_Pos (17UL) /*!< LVR_RST_FLAG (Bit 17) */
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#define CKGEN_RCM_STATUS_LVR_RST_FLAG_Msk (0x20000UL) /*!< LVR_RST_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_SW_RST_FLAG_Pos (18UL) /*!< SW_RST_FLAG (Bit 18) */
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#define CKGEN_RCM_STATUS_SW_RST_FLAG_Msk (0x40000UL) /*!< SW_RST_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_LOCKUP_RST_FLAG_Pos (19UL) /*!< LOCKUP_RST_FLAG (Bit 19) */
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#define CKGEN_RCM_STATUS_LOCKUP_RST_FLAG_Msk (0x80000UL) /*!< LOCKUP_RST_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_ACK_ERR_RST_FLAG_Pos (20UL) /*!< ACK_ERR_RST_FLAG (Bit 20) */
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#define CKGEN_RCM_STATUS_ACK_ERR_RST_FLAG_Msk (0x100000UL) /*!< ACK_ERR_RST_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_WDG_RST_FLAG_Pos (21UL) /*!< WDG_RST_FLAG (Bit 21) */
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#define CKGEN_RCM_STATUS_WDG_RST_FLAG_Msk (0x200000UL) /*!< WDG_RST_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_XOSC_LOSS_RST_FLAG_Pos (23UL) /*!< XOSC_LOSS_RST_FLAG (Bit 23) */
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#define CKGEN_RCM_STATUS_XOSC_LOSS_RST_FLAG_Msk (0x800000UL) /*!< XOSC_LOSS_RST_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_PLL_UNLOCK_RST_FLAG_Pos (24UL) /*!< PLL_UNLOCK_RST_FLAG (Bit 24) */
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#define CKGEN_RCM_STATUS_PLL_UNLOCK_RST_FLAG_Msk (0x1000000UL) /*!< PLL_UNLOCK_RST_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_VHSI_LOSS_RST_FLAG_Pos (25UL) /*!< VHSI_LOSS_RST_FLAG (Bit 25) */
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#define CKGEN_RCM_STATUS_VHSI_LOSS_RST_FLAG_Msk (0x2000000UL) /*!< VHSI_LOSS_RST_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_EXT_RST_FLAG_Pos (26UL) /*!< EXT_RST_FLAG (Bit 26) */
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#define CKGEN_RCM_STATUS_EXT_RST_FLAG_Msk (0x4000000UL) /*!< EXT_RST_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_SMU_ERR_RST_FLAG_Pos (27UL) /*!< SMU_ERR_RST_FLAG (Bit 27) */
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#define CKGEN_RCM_STATUS_SMU_ERR_RST_FLAG_Msk (0x8000000UL) /*!< SMU_ERR_RST_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_ECC2_ERR_RST_FLAG_Pos (28UL) /*!< ECC2_ERR_RST_FLAG (Bit 28) */
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#define CKGEN_RCM_STATUS_ECC2_ERR_RST_FLAG_Msk (0x10000000UL) /*!< ECC2_ERR_RST_FLAG (Bitfield-Mask: 0x01) */
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#define CKGEN_RCM_STATUS_RST_STATUS_CLR_Pos (31UL) /*!< RST_STATUS_CLR (Bit 31) */
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#define CKGEN_RCM_STATUS_RST_STATUS_CLR_Msk (0x80000000UL) /*!< RST_STATUS_CLR (Bitfield-Mask: 0x01) */
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/* ===================================================== PERI_SFT_RST0 ===================================================== */
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#define CKGEN_PERI_SFT_RST0_SRST_UART0_Pos (0UL) /*!< SRST_UART0 (Bit 0) */
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#define CKGEN_PERI_SFT_RST0_SRST_UART0_Msk (0x1UL) /*!< SRST_UART0 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_UART1_Pos (1UL) /*!< SRST_UART1 (Bit 1) */
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#define CKGEN_PERI_SFT_RST0_SRST_UART1_Msk (0x2UL) /*!< SRST_UART1 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_UART2_Pos (2UL) /*!< SRST_UART2 (Bit 2) */
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#define CKGEN_PERI_SFT_RST0_SRST_UART2_Msk (0x4UL) /*!< SRST_UART2 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_UART3_Pos (3UL) /*!< SRST_UART3 (Bit 3) */
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#define CKGEN_PERI_SFT_RST0_SRST_UART3_Msk (0x8UL) /*!< SRST_UART3 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_SPI0_Pos (6UL) /*!< SRST_SPI0 (Bit 6) */
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#define CKGEN_PERI_SFT_RST0_SRST_SPI0_Msk (0x40UL) /*!< SRST_SPI0 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_SPI1_Pos (7UL) /*!< SRST_SPI1 (Bit 7) */
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#define CKGEN_PERI_SFT_RST0_SRST_SPI1_Msk (0x80UL) /*!< SRST_SPI1 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_SPI2_Pos (8UL) /*!< SRST_SPI2 (Bit 8) */
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#define CKGEN_PERI_SFT_RST0_SRST_SPI2_Msk (0x100UL) /*!< SRST_SPI2 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_I2C0_Pos (9UL) /*!< SRST_I2C0 (Bit 9) */
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#define CKGEN_PERI_SFT_RST0_SRST_I2C0_Msk (0x200UL) /*!< SRST_I2C0 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_PCT_Pos (11UL) /*!< SRST_PCT (Bit 11) */
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#define CKGEN_PERI_SFT_RST0_SRST_PCT_Msk (0x800UL) /*!< SRST_PCT (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_PWM0_Pos (15UL) /*!< SRST_PWM0 (Bit 15) */
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#define CKGEN_PERI_SFT_RST0_SRST_PWM0_Msk (0x8000UL) /*!< SRST_PWM0 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_PWM1_Pos (16UL) /*!< SRST_PWM1 (Bit 16) */
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#define CKGEN_PERI_SFT_RST0_SRST_PWM1_Msk (0x10000UL) /*!< SRST_PWM1 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_PWM2_Pos (17UL) /*!< SRST_PWM2 (Bit 17) */
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#define CKGEN_PERI_SFT_RST0_SRST_PWM2_Msk (0x20000UL) /*!< SRST_PWM2 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_PWM3_Pos (18UL) /*!< SRST_PWM3 (Bit 18) */
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#define CKGEN_PERI_SFT_RST0_SRST_PWM3_Msk (0x40000UL) /*!< SRST_PWM3 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_PWM4_Pos (19UL) /*!< SRST_PWM4 (Bit 19) */
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#define CKGEN_PERI_SFT_RST0_SRST_PWM4_Msk (0x80000UL) /*!< SRST_PWM4 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST0_SRST_PWM5_Pos (20UL) /*!< SRST_PWM5 (Bit 20) */
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#define CKGEN_PERI_SFT_RST0_SRST_PWM5_Msk (0x100000UL) /*!< SRST_PWM5 (Bitfield-Mask: 0x01) */
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/* ===================================================== PERI_SFT_RST1 ===================================================== */
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#define CKGEN_PERI_SFT_RST1_SRST_DMA_Pos (2UL) /*!< SRST_DMA (Bit 2) */
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#define CKGEN_PERI_SFT_RST1_SRST_DMA_Msk (0x4UL) /*!< SRST_DMA (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST1_SRST_GPIO_Pos (5UL) /*!< SRST_GPIO (Bit 5) */
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#define CKGEN_PERI_SFT_RST1_SRST_GPIO_Msk (0x20UL) /*!< SRST_GPIO (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST1_SRST_WDG_Pos (6UL) /*!< SRST_WDG (Bit 6) */
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#define CKGEN_PERI_SFT_RST1_SRST_WDG_Msk (0x40UL) /*!< SRST_WDG (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST1_SRST_EWDG_Pos (7UL) /*!< SRST_EWDG (Bit 7) */
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#define CKGEN_PERI_SFT_RST1_SRST_EWDG_Msk (0x80UL) /*!< SRST_EWDG (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST1_SRST_CRC_Pos (8UL) /*!< SRST_CRC (Bit 8) */
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#define CKGEN_PERI_SFT_RST1_SRST_CRC_Msk (0x100UL) /*!< SRST_CRC (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST1_SRST_CAN0_Pos (9UL) /*!< SRST_CAN0 (Bit 9) */
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#define CKGEN_PERI_SFT_RST1_SRST_CAN0_Msk (0x200UL) /*!< SRST_CAN0 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST1_SRST_CAN1_Pos (10UL) /*!< SRST_CAN1 (Bit 10) */
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#define CKGEN_PERI_SFT_RST1_SRST_CAN1_Msk (0x400UL) /*!< SRST_CAN1 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST1_SRST_CAN2_Pos (11UL) /*!< SRST_CAN2 (Bit 11) */
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#define CKGEN_PERI_SFT_RST1_SRST_CAN2_Msk (0x800UL) /*!< SRST_CAN2 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST1_SRST_CAN3_Pos (12UL) /*!< SRST_CAN3 (Bit 12) */
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#define CKGEN_PERI_SFT_RST1_SRST_CAN3_Msk (0x1000UL) /*!< SRST_CAN3 (Bitfield-Mask: 0x01) */
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/* ===================================================== PERI_SFT_RST2 ===================================================== */
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#define CKGEN_PERI_SFT_RST2_SRST_CTU_Pos (1UL) /*!< SRST_CTU (Bit 1) */
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#define CKGEN_PERI_SFT_RST2_SRST_CTU_Msk (0x2UL) /*!< SRST_CTU (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST2_SRST_ACMP_Pos (8UL) /*!< SRST_ACMP (Bit 8) */
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#define CKGEN_PERI_SFT_RST2_SRST_ACMP_Msk (0x100UL) /*!< SRST_ACMP (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST2_SRST_PDT0_Pos (9UL) /*!< SRST_PDT0 (Bit 9) */
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#define CKGEN_PERI_SFT_RST2_SRST_PDT0_Msk (0x200UL) /*!< SRST_PDT0 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST2_SRST_PDT1_Pos (10UL) /*!< SRST_PDT1 (Bit 10) */
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#define CKGEN_PERI_SFT_RST2_SRST_PDT1_Msk (0x400UL) /*!< SRST_PDT1 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST2_SRST_ADC0_Pos (11UL) /*!< SRST_ADC0 (Bit 11) */
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#define CKGEN_PERI_SFT_RST2_SRST_ADC0_Msk (0x800UL) /*!< SRST_ADC0 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST2_SRST_ADC1_Pos (12UL) /*!< SRST_ADC1 (Bit 12) */
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#define CKGEN_PERI_SFT_RST2_SRST_ADC1_Msk (0x1000UL) /*!< SRST_ADC1 (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST2_SRST_TIMER_Pos (13UL) /*!< SRST_TIMER (Bit 13) */
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#define CKGEN_PERI_SFT_RST2_SRST_TIMER_Msk (0x2000UL) /*!< SRST_TIMER (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_SFT_RST2_SRST_EIO_Pos (14UL) /*!< SRST_EIO (Bit 14) */
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#define CKGEN_PERI_SFT_RST2_SRST_EIO_Msk (0x4000UL) /*!< SRST_EIO (Bitfield-Mask: 0x01) */
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/* ======================================================= CLK_DIV1 ======================================================== */
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#define CKGEN_CLK_DIV1_SPLL_DIV1_Pos (0UL) /*!< SPLL_DIV1 (Bit 0) */
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#define CKGEN_CLK_DIV1_SPLL_DIV1_Msk (0x3fUL) /*!< SPLL_DIV1 (Bitfield-Mask: 0x3f) */
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#define CKGEN_CLK_DIV1_VHSI_DIV1_Pos (6UL) /*!< VHSI_DIV1 (Bit 6) */
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#define CKGEN_CLK_DIV1_VHSI_DIV1_Msk (0xfc0UL) /*!< VHSI_DIV1 (Bitfield-Mask: 0x3f) */
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#define CKGEN_CLK_DIV1_HSI_DIV1_Pos (12UL) /*!< HSI_DIV1 (Bit 12) */
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#define CKGEN_CLK_DIV1_HSI_DIV1_Msk (0x3f000UL) /*!< HSI_DIV1 (Bitfield-Mask: 0x3f) */
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#define CKGEN_CLK_DIV1_HSE_DIV1_Pos (18UL) /*!< HSE_DIV1 (Bit 18) */
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#define CKGEN_CLK_DIV1_HSE_DIV1_Msk (0xfc0000UL) /*!< HSE_DIV1 (Bitfield-Mask: 0x3f) */
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/* ======================================================= CLK_DIV2 ======================================================== */
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#define CKGEN_CLK_DIV2_SPLL_DIV2_Pos (0UL) /*!< SPLL_DIV2 (Bit 0) */
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#define CKGEN_CLK_DIV2_SPLL_DIV2_Msk (0x3fUL) /*!< SPLL_DIV2 (Bitfield-Mask: 0x3f) */
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#define CKGEN_CLK_DIV2_VHSI_DIV2_Pos (6UL) /*!< VHSI_DIV2 (Bit 6) */
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#define CKGEN_CLK_DIV2_VHSI_DIV2_Msk (0xfc0UL) /*!< VHSI_DIV2 (Bitfield-Mask: 0x3f) */
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#define CKGEN_CLK_DIV2_HSI_DIV2_Pos (12UL) /*!< HSI_DIV2 (Bit 12) */
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#define CKGEN_CLK_DIV2_HSI_DIV2_Msk (0x3f000UL) /*!< HSI_DIV2 (Bitfield-Mask: 0x3f) */
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#define CKGEN_CLK_DIV2_HSE_DIV2_Pos (18UL) /*!< HSE_DIV2 (Bit 18) */
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#define CKGEN_CLK_DIV2_HSE_DIV2_Msk (0xfc0000UL) /*!< HSE_DIV2 (Bitfield-Mask: 0x3f) */
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/* ===================================================== PERI_CLK_MUX0 ===================================================== */
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#define CKGEN_PERI_CLK_MUX0_I2C0_MUX_Pos (0UL) /*!< I2C0_MUX (Bit 0) */
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#define CKGEN_PERI_CLK_MUX0_I2C0_MUX_Msk (0x7UL) /*!< I2C0_MUX (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_MUX0_TIMER_MUX_Pos (8UL) /*!< TIMER_MUX (Bit 8) */
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#define CKGEN_PERI_CLK_MUX0_TIMER_MUX_Msk (0x700UL) /*!< TIMER_MUX (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_MUX0_SPI0_MUX_Pos (12UL) /*!< SPI0_MUX (Bit 12) */
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#define CKGEN_PERI_CLK_MUX0_SPI0_MUX_Msk (0x7000UL) /*!< SPI0_MUX (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_MUX0_SPI1_MUX_Pos (16UL) /*!< SPI1_MUX (Bit 16) */
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#define CKGEN_PERI_CLK_MUX0_SPI1_MUX_Msk (0x70000UL) /*!< SPI1_MUX (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_MUX0_SPI2_MUX_Pos (20UL) /*!< SPI2_MUX (Bit 20) */
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#define CKGEN_PERI_CLK_MUX0_SPI2_MUX_Msk (0x700000UL) /*!< SPI2_MUX (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_MUX0_ADC0_MUX_Pos (24UL) /*!< ADC0_MUX (Bit 24) */
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#define CKGEN_PERI_CLK_MUX0_ADC0_MUX_Msk (0x7000000UL) /*!< ADC0_MUX (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_MUX0_ADC1_MUX_Pos (28UL) /*!< ADC1_MUX (Bit 28) */
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#define CKGEN_PERI_CLK_MUX0_ADC1_MUX_Msk (0x70000000UL) /*!< ADC1_MUX (Bitfield-Mask: 0x07) */
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/* ===================================================== PERI_CLK_MUX1 ===================================================== */
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#define CKGEN_PERI_CLK_MUX1_CAN0_MUX_Pos (0UL) /*!< CAN0_MUX (Bit 0) */
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#define CKGEN_PERI_CLK_MUX1_CAN0_MUX_Msk (0x3UL) /*!< CAN0_MUX (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX1_CAN1_MUX_Pos (2UL) /*!< CAN1_MUX (Bit 2) */
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#define CKGEN_PERI_CLK_MUX1_CAN1_MUX_Msk (0xcUL) /*!< CAN1_MUX (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX1_CAN2_MUX_Pos (4UL) /*!< CAN2_MUX (Bit 4) */
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#define CKGEN_PERI_CLK_MUX1_CAN2_MUX_Msk (0x30UL) /*!< CAN2_MUX (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX1_CAN3_MUX_Pos (6UL) /*!< CAN3_MUX (Bit 6) */
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#define CKGEN_PERI_CLK_MUX1_CAN3_MUX_Msk (0xc0UL) /*!< CAN3_MUX (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX1_PCT_MUX_Pos (12UL) /*!< PCT_MUX (Bit 12) */
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#define CKGEN_PERI_CLK_MUX1_PCT_MUX_Msk (0x7000UL) /*!< PCT_MUX (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_MUX1_EIO_MUX_Pos (16UL) /*!< EIO_MUX (Bit 16) */
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#define CKGEN_PERI_CLK_MUX1_EIO_MUX_Msk (0x70000UL) /*!< EIO_MUX (Bitfield-Mask: 0x07) */
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/* ===================================================== PERI_CLK_MUX2 ===================================================== */
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#define CKGEN_PERI_CLK_MUX2_UART0_MUX_Pos (0UL) /*!< UART0_MUX (Bit 0) */
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#define CKGEN_PERI_CLK_MUX2_UART0_MUX_Msk (0x7UL) /*!< UART0_MUX (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_MUX2_UART1_MUX_Pos (4UL) /*!< UART1_MUX (Bit 4) */
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#define CKGEN_PERI_CLK_MUX2_UART1_MUX_Msk (0x70UL) /*!< UART1_MUX (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_MUX2_UART2_MUX_Pos (8UL) /*!< UART2_MUX (Bit 8) */
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#define CKGEN_PERI_CLK_MUX2_UART2_MUX_Msk (0x700UL) /*!< UART2_MUX (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_MUX2_UART3_MUX_Pos (12UL) /*!< UART3_MUX (Bit 12) */
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#define CKGEN_PERI_CLK_MUX2_UART3_MUX_Msk (0x7000UL) /*!< UART3_MUX (Bitfield-Mask: 0x07) */
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/* ===================================================== PERI_CLK_MUX3 ===================================================== */
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#define CKGEN_PERI_CLK_MUX3_PWM0_EXT_Pos (0UL) /*!< PWM0_EXT (Bit 0) */
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#define CKGEN_PERI_CLK_MUX3_PWM0_EXT_Msk (0x3UL) /*!< PWM0_EXT (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX3_PWM0_INT_Pos (2UL) /*!< PWM0_INT (Bit 2) */
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#define CKGEN_PERI_CLK_MUX3_PWM0_INT_Msk (0xcUL) /*!< PWM0_INT (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX3_PWM0_EXT_IN_Pos (4UL) /*!< PWM0_EXT_IN (Bit 4) */
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#define CKGEN_PERI_CLK_MUX3_PWM0_EXT_IN_Msk (0x10UL) /*!< PWM0_EXT_IN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_MUX3_PWM1_EXT_Pos (5UL) /*!< PWM1_EXT (Bit 5) */
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#define CKGEN_PERI_CLK_MUX3_PWM1_EXT_Msk (0x60UL) /*!< PWM1_EXT (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX3_PWM1_INT_Pos (7UL) /*!< PWM1_INT (Bit 7) */
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#define CKGEN_PERI_CLK_MUX3_PWM1_INT_Msk (0x180UL) /*!< PWM1_INT (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX3_PWM1_EXT_IN_Pos (9UL) /*!< PWM1_EXT_IN (Bit 9) */
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#define CKGEN_PERI_CLK_MUX3_PWM1_EXT_IN_Msk (0x200UL) /*!< PWM1_EXT_IN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_MUX3_PWM2_EXT_Pos (10UL) /*!< PWM2_EXT (Bit 10) */
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#define CKGEN_PERI_CLK_MUX3_PWM2_EXT_Msk (0xc00UL) /*!< PWM2_EXT (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX3_PWM2_INT_Pos (12UL) /*!< PWM2_INT (Bit 12) */
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#define CKGEN_PERI_CLK_MUX3_PWM2_INT_Msk (0x3000UL) /*!< PWM2_INT (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX3_PWM2_EXT_IN_Pos (14UL) /*!< PWM2_EXT_IN (Bit 14) */
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#define CKGEN_PERI_CLK_MUX3_PWM2_EXT_IN_Msk (0x4000UL) /*!< PWM2_EXT_IN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_MUX3_PWM3_EXT_Pos (15UL) /*!< PWM3_EXT (Bit 15) */
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#define CKGEN_PERI_CLK_MUX3_PWM3_EXT_Msk (0x18000UL) /*!< PWM3_EXT (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX3_PWM3_INT_Pos (17UL) /*!< PWM3_INT (Bit 17) */
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#define CKGEN_PERI_CLK_MUX3_PWM3_INT_Msk (0x60000UL) /*!< PWM3_INT (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX3_PWM3_EXT_IN_Pos (19UL) /*!< PWM3_EXT_IN (Bit 19) */
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#define CKGEN_PERI_CLK_MUX3_PWM3_EXT_IN_Msk (0x80000UL) /*!< PWM3_EXT_IN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_MUX3_PWM4_EXT_Pos (20UL) /*!< PWM4_EXT (Bit 20) */
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#define CKGEN_PERI_CLK_MUX3_PWM4_EXT_Msk (0x300000UL) /*!< PWM4_EXT (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX3_PWM4_INT_Pos (22UL) /*!< PWM4_INT (Bit 22) */
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#define CKGEN_PERI_CLK_MUX3_PWM4_INT_Msk (0xc00000UL) /*!< PWM4_INT (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX3_PWM4_EXT_IN_Pos (24UL) /*!< PWM4_EXT_IN (Bit 24) */
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#define CKGEN_PERI_CLK_MUX3_PWM4_EXT_IN_Msk (0x1000000UL) /*!< PWM4_EXT_IN (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_MUX3_PWM5_EXT_Pos (25UL) /*!< PWM5_EXT (Bit 25) */
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#define CKGEN_PERI_CLK_MUX3_PWM5_EXT_Msk (0x6000000UL) /*!< PWM5_EXT (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX3_PWM5_INT_Pos (27UL) /*!< PWM5_INT (Bit 27) */
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#define CKGEN_PERI_CLK_MUX3_PWM5_INT_Msk (0x18000000UL) /*!< PWM5_INT (Bitfield-Mask: 0x03) */
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#define CKGEN_PERI_CLK_MUX3_PWM5_EXT_IN_Pos (29UL) /*!< PWM5_EXT_IN (Bit 29) */
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#define CKGEN_PERI_CLK_MUX3_PWM5_EXT_IN_Msk (0x20000000UL) /*!< PWM5_EXT_IN (Bitfield-Mask: 0x01) */
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/* ====================================================== CLK_OUT_CFG ====================================================== */
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#define CKGEN_CLK_OUT_CFG_MUX1_Pos (0UL) /*!< MUX1 (Bit 0) */
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#define CKGEN_CLK_OUT_CFG_MUX1_Msk (0x7UL) /*!< MUX1 (Bitfield-Mask: 0x07) */
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#define CKGEN_CLK_OUT_CFG_MUX2_Pos (4UL) /*!< MUX2 (Bit 4) */
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#define CKGEN_CLK_OUT_CFG_MUX2_Msk (0xf0UL) /*!< MUX2 (Bitfield-Mask: 0x0f) */
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#define CKGEN_CLK_OUT_CFG_DIV_Pos (8UL) /*!< DIV (Bit 8) */
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#define CKGEN_CLK_OUT_CFG_DIV_Msk (0x700UL) /*!< DIV (Bitfield-Mask: 0x07) */
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#define CKGEN_CLK_OUT_CFG_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */
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#define CKGEN_CLK_OUT_CFG_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
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/* ===================================================== PERI_CLK_DIV ====================================================== */
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#define CKGEN_PERI_CLK_DIV_CAN0_DIV_Pos (0UL) /*!< CAN0_DIV (Bit 0) */
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#define CKGEN_PERI_CLK_DIV_CAN0_DIV_Msk (0x1UL) /*!< CAN0_DIV (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_DIV_CAN1_DIV_Pos (1UL) /*!< CAN1_DIV (Bit 1) */
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#define CKGEN_PERI_CLK_DIV_CAN1_DIV_Msk (0x2UL) /*!< CAN1_DIV (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_DIV_CAN2_DIV_Pos (2UL) /*!< CAN2_DIV (Bit 2) */
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#define CKGEN_PERI_CLK_DIV_CAN2_DIV_Msk (0x4UL) /*!< CAN2_DIV (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_DIV_CAN3_DIV_Pos (3UL) /*!< CAN3_DIV (Bit 3) */
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#define CKGEN_PERI_CLK_DIV_CAN3_DIV_Msk (0x8UL) /*!< CAN3_DIV (Bitfield-Mask: 0x01) */
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#define CKGEN_PERI_CLK_DIV_CAN0_TS_DIV_Pos (6UL) /*!< CAN0_TS_DIV (Bit 6) */
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#define CKGEN_PERI_CLK_DIV_CAN0_TS_DIV_Msk (0x1c0UL) /*!< CAN0_TS_DIV (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_DIV_CAN1_TS_DIV_Pos (9UL) /*!< CAN1_TS_DIV (Bit 9) */
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#define CKGEN_PERI_CLK_DIV_CAN1_TS_DIV_Msk (0xe00UL) /*!< CAN1_TS_DIV (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_DIV_CAN2_TS_DIV_Pos (12UL) /*!< CAN2_TS_DIV (Bit 12) */
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#define CKGEN_PERI_CLK_DIV_CAN2_TS_DIV_Msk (0x7000UL) /*!< CAN2_TS_DIV (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_DIV_CAN3_TS_DIV_Pos (15UL) /*!< CAN3_TS_DIV (Bit 15) */
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#define CKGEN_PERI_CLK_DIV_CAN3_TS_DIV_Msk (0x38000UL) /*!< CAN3_TS_DIV (Bitfield-Mask: 0x07) */
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#define CKGEN_PERI_CLK_DIV_PCT_DIV_Pos (24UL) /*!< PCT_DIV (Bit 24) */
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#define CKGEN_PERI_CLK_DIV_PCT_DIV_Msk (0xf000000UL) /*!< PCT_DIV (Bitfield-Mask: 0x0f) */
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#define CKGEN_PERI_CLK_DIV_TPIU_DIV_Pos (28UL) /*!< TPIU_DIV (Bit 28) */
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#define CKGEN_PERI_CLK_DIV_TPIU_DIV_Msk (0xf0000000UL) /*!< TPIU_DIV (Bitfield-Mask: 0x0f) */
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/* =========================================================================================================================== */
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/* ================ PBR ================ */
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/* =========================================================================================================================== */
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/* ======================================================= MPR_CORE ======================================================== */
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#define PBR_MPR_CORE_MPL_Pos (0UL) /*!< MPL (Bit 0) */
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#define PBR_MPR_CORE_MPL_Msk (0x1UL) /*!< MPL (Bitfield-Mask: 0x01) */
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#define PBR_MPR_CORE_MTW_Pos (1UL) /*!< MTW (Bit 1) */
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#define PBR_MPR_CORE_MTW_Msk (0x2UL) /*!< MTW (Bitfield-Mask: 0x01) */
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#define PBR_MPR_CORE_MTR_Pos (2UL) /*!< MTR (Bit 2) */
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#define PBR_MPR_CORE_MTR_Msk (0x4UL) /*!< MTR (Bitfield-Mask: 0x01) */
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/* ======================================================= MPR_DEBUG ======================================================= */
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#define PBR_MPR_DEBUG_MPL_Pos (0UL) /*!< MPL (Bit 0) */
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#define PBR_MPR_DEBUG_MPL_Msk (0x1UL) /*!< MPL (Bitfield-Mask: 0x01) */
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#define PBR_MPR_DEBUG_MTW_Pos (1UL) /*!< MTW (Bit 1) */
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#define PBR_MPR_DEBUG_MTW_Msk (0x2UL) /*!< MTW (Bitfield-Mask: 0x01) */
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#define PBR_MPR_DEBUG_MTR_Pos (2UL) /*!< MTR (Bit 2) */
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#define PBR_MPR_DEBUG_MTR_Msk (0x4UL) /*!< MTR (Bitfield-Mask: 0x01) */
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/* ======================================================== MPR_DMA ======================================================== */
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#define PBR_MPR_DMA_MPL_Pos (0UL) /*!< MPL (Bit 0) */
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#define PBR_MPR_DMA_MPL_Msk (0x1UL) /*!< MPL (Bitfield-Mask: 0x01) */
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#define PBR_MPR_DMA_MTW_Pos (1UL) /*!< MTW (Bit 1) */
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#define PBR_MPR_DMA_MTW_Msk (0x2UL) /*!< MTW (Bitfield-Mask: 0x01) */
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#define PBR_MPR_DMA_MTR_Pos (2UL) /*!< MTR (Bit 2) */
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#define PBR_MPR_DMA_MTR_Msk (0x4UL) /*!< MTR (Bitfield-Mask: 0x01) */
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/* ========================================================= PACRA ========================================================= */
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#define PBR_PACRA_PWM0_TP_Pos (0UL) /*!< PWM0_TP (Bit 0) */
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#define PBR_PACRA_PWM0_TP_Msk (0x1UL) /*!< PWM0_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM0_WP_Pos (1UL) /*!< PWM0_WP (Bit 1) */
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#define PBR_PACRA_PWM0_WP_Msk (0x2UL) /*!< PWM0_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM0_SP_Pos (2UL) /*!< PWM0_SP (Bit 2) */
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#define PBR_PACRA_PWM0_SP_Msk (0x4UL) /*!< PWM0_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM1_TP_Pos (4UL) /*!< PWM1_TP (Bit 4) */
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#define PBR_PACRA_PWM1_TP_Msk (0x10UL) /*!< PWM1_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM1_WP_Pos (5UL) /*!< PWM1_WP (Bit 5) */
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#define PBR_PACRA_PWM1_WP_Msk (0x20UL) /*!< PWM1_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM1_SP_Pos (6UL) /*!< PWM1_SP (Bit 6) */
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#define PBR_PACRA_PWM1_SP_Msk (0x40UL) /*!< PWM1_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM2_TP_Pos (8UL) /*!< PWM2_TP (Bit 8) */
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#define PBR_PACRA_PWM2_TP_Msk (0x100UL) /*!< PWM2_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM2_WP_Pos (9UL) /*!< PWM2_WP (Bit 9) */
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#define PBR_PACRA_PWM2_WP_Msk (0x200UL) /*!< PWM2_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM2_SP_Pos (10UL) /*!< PWM2_SP (Bit 10) */
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#define PBR_PACRA_PWM2_SP_Msk (0x400UL) /*!< PWM2_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM3_TP_Pos (12UL) /*!< PWM3_TP (Bit 12) */
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#define PBR_PACRA_PWM3_TP_Msk (0x1000UL) /*!< PWM3_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM3_WP_Pos (13UL) /*!< PWM3_WP (Bit 13) */
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#define PBR_PACRA_PWM3_WP_Msk (0x2000UL) /*!< PWM3_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM3_SP_Pos (14UL) /*!< PWM3_SP (Bit 14) */
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#define PBR_PACRA_PWM3_SP_Msk (0x4000UL) /*!< PWM3_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM4_TP_Pos (16UL) /*!< PWM4_TP (Bit 16) */
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#define PBR_PACRA_PWM4_TP_Msk (0x10000UL) /*!< PWM4_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM4_WP_Pos (17UL) /*!< PWM4_WP (Bit 17) */
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#define PBR_PACRA_PWM4_WP_Msk (0x20000UL) /*!< PWM4_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM4_SP_Pos (18UL) /*!< PWM4_SP (Bit 18) */
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#define PBR_PACRA_PWM4_SP_Msk (0x40000UL) /*!< PWM4_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM5_TP_Pos (20UL) /*!< PWM5_TP (Bit 20) */
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#define PBR_PACRA_PWM5_TP_Msk (0x100000UL) /*!< PWM5_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM5_WP_Pos (21UL) /*!< PWM5_WP (Bit 21) */
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#define PBR_PACRA_PWM5_WP_Msk (0x200000UL) /*!< PWM5_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRA_PWM5_SP_Pos (22UL) /*!< PWM5_SP (Bit 22) */
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#define PBR_PACRA_PWM5_SP_Msk (0x400000UL) /*!< PWM5_SP (Bitfield-Mask: 0x01) */
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/* ========================================================= PACRB ========================================================= */
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#define PBR_PACRB_CRC_TP_Pos (0UL) /*!< CRC_TP (Bit 0) */
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#define PBR_PACRB_CRC_TP_Msk (0x1UL) /*!< CRC_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_CRC_WP_Pos (1UL) /*!< CRC_WP (Bit 1) */
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#define PBR_PACRB_CRC_WP_Msk (0x2UL) /*!< CRC_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_CRC_SP_Pos (2UL) /*!< CRC_SP (Bit 2) */
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#define PBR_PACRB_CRC_SP_Msk (0x4UL) /*!< CRC_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_GPIO_TP_Pos (4UL) /*!< GPIO_TP (Bit 4) */
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#define PBR_PACRB_GPIO_TP_Msk (0x10UL) /*!< GPIO_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_GPIO_WP_Pos (5UL) /*!< GPIO_WP (Bit 5) */
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#define PBR_PACRB_GPIO_WP_Msk (0x20UL) /*!< GPIO_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_GPIO_SP_Pos (6UL) /*!< GPIO_SP (Bit 6) */
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#define PBR_PACRB_GPIO_SP_Msk (0x40UL) /*!< GPIO_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_PDT0_TP_Pos (8UL) /*!< PDT0_TP (Bit 8) */
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#define PBR_PACRB_PDT0_TP_Msk (0x100UL) /*!< PDT0_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_PDT0_WP_Pos (9UL) /*!< PDT0_WP (Bit 9) */
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#define PBR_PACRB_PDT0_WP_Msk (0x200UL) /*!< PDT0_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_PDT0_SP_Pos (10UL) /*!< PDT0_SP (Bit 10) */
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#define PBR_PACRB_PDT0_SP_Msk (0x400UL) /*!< PDT0_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_PDT1_TP_Pos (12UL) /*!< PDT1_TP (Bit 12) */
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#define PBR_PACRB_PDT1_TP_Msk (0x1000UL) /*!< PDT1_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_PDT1_WP_Pos (13UL) /*!< PDT1_WP (Bit 13) */
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#define PBR_PACRB_PDT1_WP_Msk (0x2000UL) /*!< PDT1_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_PDT1_SP_Pos (14UL) /*!< PDT1_SP (Bit 14) */
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#define PBR_PACRB_PDT1_SP_Msk (0x4000UL) /*!< PDT1_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_MPU_TP_Pos (16UL) /*!< MPU_TP (Bit 16) */
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#define PBR_PACRB_MPU_TP_Msk (0x10000UL) /*!< MPU_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_MPU_WP_Pos (17UL) /*!< MPU_WP (Bit 17) */
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#define PBR_PACRB_MPU_WP_Msk (0x20000UL) /*!< MPU_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_MPU_SP_Pos (18UL) /*!< MPU_SP (Bit 18) */
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#define PBR_PACRB_MPU_SP_Msk (0x40000UL) /*!< MPU_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_EIM_TP_Pos (20UL) /*!< EIM_TP (Bit 20) */
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#define PBR_PACRB_EIM_TP_Msk (0x100000UL) /*!< EIM_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_EIM_WP_Pos (21UL) /*!< EIM_WP (Bit 21) */
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#define PBR_PACRB_EIM_WP_Msk (0x200000UL) /*!< EIM_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_EIM_SP_Pos (22UL) /*!< EIM_SP (Bit 22) */
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#define PBR_PACRB_EIM_SP_Msk (0x400000UL) /*!< EIM_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_SMU_TP_Pos (24UL) /*!< SMU_TP (Bit 24) */
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#define PBR_PACRB_SMU_TP_Msk (0x1000000UL) /*!< SMU_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_SMU_WP_Pos (25UL) /*!< SMU_WP (Bit 25) */
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#define PBR_PACRB_SMU_WP_Msk (0x2000000UL) /*!< SMU_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRB_SMU_SP_Pos (26UL) /*!< SMU_SP (Bit 26) */
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#define PBR_PACRB_SMU_SP_Msk (0x4000000UL) /*!< SMU_SP (Bitfield-Mask: 0x01) */
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/* ========================================================= PACRC ========================================================= */
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#define PBR_PACRC_CLK_TP_Pos (0UL) /*!< CLK_TP (Bit 0) */
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#define PBR_PACRC_CLK_TP_Msk (0x1UL) /*!< CLK_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_CLK_WP_Pos (1UL) /*!< CLK_WP (Bit 1) */
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#define PBR_PACRC_CLK_WP_Msk (0x2UL) /*!< CLK_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_CLK_SP_Pos (2UL) /*!< CLK_SP (Bit 2) */
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#define PBR_PACRC_CLK_SP_Msk (0x4UL) /*!< CLK_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_FLASH_TP_Pos (8UL) /*!< FLASH_TP (Bit 8) */
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#define PBR_PACRC_FLASH_TP_Msk (0x100UL) /*!< FLASH_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_FLASH_WP_Pos (9UL) /*!< FLASH_WP (Bit 9) */
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#define PBR_PACRC_FLASH_WP_Msk (0x200UL) /*!< FLASH_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_FLASH_SP_Pos (10UL) /*!< FLASH_SP (Bit 10) */
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#define PBR_PACRC_FLASH_SP_Msk (0x400UL) /*!< FLASH_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_ADC0_TP_Pos (12UL) /*!< ADC0_TP (Bit 12) */
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#define PBR_PACRC_ADC0_TP_Msk (0x1000UL) /*!< ADC0_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_ADC0_WP_Pos (13UL) /*!< ADC0_WP (Bit 13) */
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#define PBR_PACRC_ADC0_WP_Msk (0x2000UL) /*!< ADC0_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_ADC0_SP_Pos (14UL) /*!< ADC0_SP (Bit 14) */
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#define PBR_PACRC_ADC0_SP_Msk (0x4000UL) /*!< ADC0_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_ADC1_TP_Pos (16UL) /*!< ADC1_TP (Bit 16) */
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#define PBR_PACRC_ADC1_TP_Msk (0x10000UL) /*!< ADC1_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_ADC1_WP_Pos (17UL) /*!< ADC1_WP (Bit 17) */
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#define PBR_PACRC_ADC1_WP_Msk (0x20000UL) /*!< ADC1_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_ADC1_SP_Pos (18UL) /*!< ADC1_SP (Bit 18) */
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#define PBR_PACRC_ADC1_SP_Msk (0x40000UL) /*!< ADC1_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_ACMP_TP_Pos (20UL) /*!< ACMP_TP (Bit 20) */
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#define PBR_PACRC_ACMP_TP_Msk (0x100000UL) /*!< ACMP_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_ACMP_WP_Pos (21UL) /*!< ACMP_WP (Bit 21) */
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#define PBR_PACRC_ACMP_WP_Msk (0x200000UL) /*!< ACMP_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_ACMP_SP_Pos (22UL) /*!< ACMP_SP (Bit 22) */
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#define PBR_PACRC_ACMP_SP_Msk (0x400000UL) /*!< ACMP_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_CTU_TP_Pos (24UL) /*!< CTU_TP (Bit 24) */
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#define PBR_PACRC_CTU_TP_Msk (0x1000000UL) /*!< CTU_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_CTU_WP_Pos (25UL) /*!< CTU_WP (Bit 25) */
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#define PBR_PACRC_CTU_WP_Msk (0x2000000UL) /*!< CTU_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_CTU_SP_Pos (26UL) /*!< CTU_SP (Bit 26) */
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#define PBR_PACRC_CTU_SP_Msk (0x4000000UL) /*!< CTU_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_CAN0_TP_Pos (28UL) /*!< CAN0_TP (Bit 28) */
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#define PBR_PACRC_CAN0_TP_Msk (0x10000000UL) /*!< CAN0_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_CAN0_WP_Pos (29UL) /*!< CAN0_WP (Bit 29) */
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#define PBR_PACRC_CAN0_WP_Msk (0x20000000UL) /*!< CAN0_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRC_CAN0_SP_Pos (30UL) /*!< CAN0_SP (Bit 30) */
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#define PBR_PACRC_CAN0_SP_Msk (0x40000000UL) /*!< CAN0_SP (Bitfield-Mask: 0x01) */
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/* ========================================================= PACRD ========================================================= */
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#define PBR_PACRD_CAN1_TP_Pos (0UL) /*!< CAN1_TP (Bit 0) */
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#define PBR_PACRD_CAN1_TP_Msk (0x1UL) /*!< CAN1_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_CAN1_WP_Pos (1UL) /*!< CAN1_WP (Bit 1) */
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#define PBR_PACRD_CAN1_WP_Msk (0x2UL) /*!< CAN1_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_CAN1_SP_Pos (2UL) /*!< CAN1_SP (Bit 2) */
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#define PBR_PACRD_CAN1_SP_Msk (0x4UL) /*!< CAN1_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_CAN2_TP_Pos (4UL) /*!< CAN2_TP (Bit 4) */
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#define PBR_PACRD_CAN2_TP_Msk (0x10UL) /*!< CAN2_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_CAN2_WP_Pos (5UL) /*!< CAN2_WP (Bit 5) */
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#define PBR_PACRD_CAN2_WP_Msk (0x20UL) /*!< CAN2_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_CAN2_SP_Pos (6UL) /*!< CAN2_SP (Bit 6) */
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#define PBR_PACRD_CAN2_SP_Msk (0x40UL) /*!< CAN2_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_CAN3_TP_Pos (8UL) /*!< CAN3_TP (Bit 8) */
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#define PBR_PACRD_CAN3_TP_Msk (0x100UL) /*!< CAN3_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_CAN3_WP_Pos (9UL) /*!< CAN3_WP (Bit 9) */
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#define PBR_PACRD_CAN3_WP_Msk (0x200UL) /*!< CAN3_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_CAN3_SP_Pos (10UL) /*!< CAN3_SP (Bit 10) */
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#define PBR_PACRD_CAN3_SP_Msk (0x400UL) /*!< CAN3_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_SPM_TP_Pos (20UL) /*!< SPM_TP (Bit 20) */
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#define PBR_PACRD_SPM_TP_Msk (0x100000UL) /*!< SPM_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_SPM_WP_Pos (21UL) /*!< SPM_WP (Bit 21) */
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#define PBR_PACRD_SPM_WP_Msk (0x200000UL) /*!< SPM_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_SPM_SP_Pos (22UL) /*!< SPM_SP (Bit 22) */
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#define PBR_PACRD_SPM_SP_Msk (0x400000UL) /*!< SPM_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_RTC_TP_Pos (24UL) /*!< RTC_TP (Bit 24) */
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#define PBR_PACRD_RTC_TP_Msk (0x1000000UL) /*!< RTC_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_RTC_WP_Pos (25UL) /*!< RTC_WP (Bit 25) */
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#define PBR_PACRD_RTC_WP_Msk (0x2000000UL) /*!< RTC_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_RTC_SP_Pos (26UL) /*!< RTC_SP (Bit 26) */
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#define PBR_PACRD_RTC_SP_Msk (0x4000000UL) /*!< RTC_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_EIO_TP_Pos (28UL) /*!< EIO_TP (Bit 28) */
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#define PBR_PACRD_EIO_TP_Msk (0x10000000UL) /*!< EIO_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_EIO_WP_Pos (29UL) /*!< EIO_WP (Bit 29) */
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#define PBR_PACRD_EIO_WP_Msk (0x20000000UL) /*!< EIO_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRD_EIO_SP_Pos (30UL) /*!< EIO_SP (Bit 30) */
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#define PBR_PACRD_EIO_SP_Msk (0x40000000UL) /*!< EIO_SP (Bitfield-Mask: 0x01) */
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/* ========================================================= PACRE ========================================================= */
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#define PBR_PACRE_WDG_TP_Pos (0UL) /*!< WDG_TP (Bit 0) */
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#define PBR_PACRE_WDG_TP_Msk (0x1UL) /*!< WDG_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_WDG_WP_Pos (1UL) /*!< WDG_WP (Bit 1) */
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#define PBR_PACRE_WDG_WP_Msk (0x2UL) /*!< WDG_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_WDG_SP_Pos (2UL) /*!< WDG_SP (Bit 2) */
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#define PBR_PACRE_WDG_SP_Msk (0x4UL) /*!< WDG_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_EWDG_TP_Pos (4UL) /*!< EWDG_TP (Bit 4) */
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#define PBR_PACRE_EWDG_TP_Msk (0x10UL) /*!< EWDG_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_EWDG_WP_Pos (5UL) /*!< EWDG_WP (Bit 5) */
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#define PBR_PACRE_EWDG_WP_Msk (0x20UL) /*!< EWDG_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_EWDG_SP_Pos (6UL) /*!< EWDG_SP (Bit 6) */
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#define PBR_PACRE_EWDG_SP_Msk (0x40UL) /*!< EWDG_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_SPI0_TP_Pos (8UL) /*!< SPI0_TP (Bit 8) */
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#define PBR_PACRE_SPI0_TP_Msk (0x100UL) /*!< SPI0_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_SPI0_WP_Pos (9UL) /*!< SPI0_WP (Bit 9) */
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#define PBR_PACRE_SPI0_WP_Msk (0x200UL) /*!< SPI0_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_SPI0_SP_Pos (10UL) /*!< SPI0_SP (Bit 10) */
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#define PBR_PACRE_SPI0_SP_Msk (0x400UL) /*!< SPI0_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_SPI1_TP_Pos (12UL) /*!< SPI1_TP (Bit 12) */
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#define PBR_PACRE_SPI1_TP_Msk (0x1000UL) /*!< SPI1_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_SPI1_WP_Pos (13UL) /*!< SPI1_WP (Bit 13) */
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#define PBR_PACRE_SPI1_WP_Msk (0x2000UL) /*!< SPI1_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_SPI1_SP_Pos (14UL) /*!< SPI1_SP (Bit 14) */
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#define PBR_PACRE_SPI1_SP_Msk (0x4000UL) /*!< SPI1_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_SPI2_TP_Pos (16UL) /*!< SPI2_TP (Bit 16) */
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#define PBR_PACRE_SPI2_TP_Msk (0x10000UL) /*!< SPI2_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_SPI2_WP_Pos (17UL) /*!< SPI2_WP (Bit 17) */
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#define PBR_PACRE_SPI2_WP_Msk (0x20000UL) /*!< SPI2_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_SPI2_SP_Pos (18UL) /*!< SPI2_SP (Bit 18) */
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#define PBR_PACRE_SPI2_SP_Msk (0x40000UL) /*!< SPI2_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_I2C0_TP_Pos (24UL) /*!< I2C0_TP (Bit 24) */
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#define PBR_PACRE_I2C0_TP_Msk (0x1000000UL) /*!< I2C0_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_I2C0_WP_Pos (25UL) /*!< I2C0_WP (Bit 25) */
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#define PBR_PACRE_I2C0_WP_Msk (0x2000000UL) /*!< I2C0_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRE_I2C0_SP_Pos (26UL) /*!< I2C0_SP (Bit 26) */
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#define PBR_PACRE_I2C0_SP_Msk (0x4000000UL) /*!< I2C0_SP (Bitfield-Mask: 0x01) */
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/* ========================================================= PACRF ========================================================= */
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#define PBR_PACRF_TIMER_TP_Pos (0UL) /*!< TIMER_TP (Bit 0) */
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#define PBR_PACRF_TIMER_TP_Msk (0x1UL) /*!< TIMER_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_TIMER_WP_Pos (1UL) /*!< TIMER_WP (Bit 1) */
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#define PBR_PACRF_TIMER_WP_Msk (0x2UL) /*!< TIMER_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_TIMER_SP_Pos (2UL) /*!< TIMER_SP (Bit 2) */
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#define PBR_PACRF_TIMER_SP_Msk (0x4UL) /*!< TIMER_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_DMA_TP_Pos (4UL) /*!< DMA_TP (Bit 4) */
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#define PBR_PACRF_DMA_TP_Msk (0x10UL) /*!< DMA_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_DMA_WP_Pos (5UL) /*!< DMA_WP (Bit 5) */
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#define PBR_PACRF_DMA_WP_Msk (0x20UL) /*!< DMA_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_DMA_SP_Pos (6UL) /*!< DMA_SP (Bit 6) */
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#define PBR_PACRF_DMA_SP_Msk (0x40UL) /*!< DMA_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_UART0_TP_Pos (8UL) /*!< UART0_TP (Bit 8) */
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#define PBR_PACRF_UART0_TP_Msk (0x100UL) /*!< UART0_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_UART0_WP_Pos (9UL) /*!< UART0_WP (Bit 9) */
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#define PBR_PACRF_UART0_WP_Msk (0x200UL) /*!< UART0_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_UART0_SP_Pos (10UL) /*!< UART0_SP (Bit 10) */
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#define PBR_PACRF_UART0_SP_Msk (0x400UL) /*!< UART0_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_UART1_TP_Pos (12UL) /*!< UART1_TP (Bit 12) */
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#define PBR_PACRF_UART1_TP_Msk (0x1000UL) /*!< UART1_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_UART1_WP_Pos (13UL) /*!< UART1_WP (Bit 13) */
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#define PBR_PACRF_UART1_WP_Msk (0x2000UL) /*!< UART1_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_UART1_SP_Pos (14UL) /*!< UART1_SP (Bit 14) */
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#define PBR_PACRF_UART1_SP_Msk (0x4000UL) /*!< UART1_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_UART2_TP_Pos (16UL) /*!< UART2_TP (Bit 16) */
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#define PBR_PACRF_UART2_TP_Msk (0x10000UL) /*!< UART2_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_UART2_WP_Pos (17UL) /*!< UART2_WP (Bit 17) */
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#define PBR_PACRF_UART2_WP_Msk (0x20000UL) /*!< UART2_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_UART2_SP_Pos (18UL) /*!< UART2_SP (Bit 18) */
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#define PBR_PACRF_UART2_SP_Msk (0x40000UL) /*!< UART2_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_UART3_TP_Pos (20UL) /*!< UART3_TP (Bit 20) */
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#define PBR_PACRF_UART3_TP_Msk (0x100000UL) /*!< UART3_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_UART3_WP_Pos (21UL) /*!< UART3_WP (Bit 21) */
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#define PBR_PACRF_UART3_WP_Msk (0x200000UL) /*!< UART3_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRF_UART3_SP_Pos (22UL) /*!< UART3_SP (Bit 22) */
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#define PBR_PACRF_UART3_SP_Msk (0x400000UL) /*!< UART3_SP (Bitfield-Mask: 0x01) */
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/* ========================================================= PACRG ========================================================= */
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#define PBR_PACRG_PCT_TP_Pos (0UL) /*!< PCT_TP (Bit 0) */
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#define PBR_PACRG_PCT_TP_Msk (0x1UL) /*!< PCT_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRG_PCT_WP_Pos (1UL) /*!< PCT_WP (Bit 1) */
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#define PBR_PACRG_PCT_WP_Msk (0x2UL) /*!< PCT_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRG_PCT_SP_Pos (2UL) /*!< PCT_SP (Bit 2) */
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#define PBR_PACRG_PCT_SP_Msk (0x4UL) /*!< PCT_SP (Bitfield-Mask: 0x01) */
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#define PBR_PACRG_CMU_TP_Pos (4UL) /*!< CMU_TP (Bit 4) */
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#define PBR_PACRG_CMU_TP_Msk (0x10UL) /*!< CMU_TP (Bitfield-Mask: 0x01) */
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#define PBR_PACRG_CMU_WP_Pos (5UL) /*!< CMU_WP (Bit 5) */
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#define PBR_PACRG_CMU_WP_Msk (0x20UL) /*!< CMU_WP (Bitfield-Mask: 0x01) */
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#define PBR_PACRG_CMU_SP_Pos (6UL) /*!< CMU_SP (Bit 6) */
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#define PBR_PACRG_CMU_SP_Msk (0x40UL) /*!< CMU_SP (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ SPM ================ */
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/* =========================================================================================================================== */
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/* ===================================================== PWR_MGR_CFG0 ====================================================== */
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#define SPM_PWR_MGR_CFG0_PWR_EN_Pos (0UL) /*!< PWR_EN (Bit 0) */
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#define SPM_PWR_MGR_CFG0_PWR_EN_Msk (0x1UL) /*!< PWR_EN (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG0_AWIC_EN_Pos (1UL) /*!< AWIC_EN (Bit 1) */
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#define SPM_PWR_MGR_CFG0_AWIC_EN_Msk (0x2UL) /*!< AWIC_EN (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG0_ACK_TIMEOUT_ACTION_Pos (4UL) /*!< ACK_TIMEOUT_ACTION (Bit 4) */
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#define SPM_PWR_MGR_CFG0_ACK_TIMEOUT_ACTION_Msk (0x10UL) /*!< ACK_TIMEOUT_ACTION (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG0_POWER_MODE_Pos (8UL) /*!< POWER_MODE (Bit 8) */
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#define SPM_PWR_MGR_CFG0_POWER_MODE_Msk (0x700UL) /*!< POWER_MODE (Bitfield-Mask: 0x07) */
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#define SPM_PWR_MGR_CFG0_RESET_MASK_Pos (16UL) /*!< RESET_MASK (Bit 16) */
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#define SPM_PWR_MGR_CFG0_RESET_MASK_Msk (0x10000UL) /*!< RESET_MASK (Bitfield-Mask: 0x01) */
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/* ===================================================== PWR_MGR_CFG1 ====================================================== */
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#define SPM_PWR_MGR_CFG1_LVR_THRESHOLD_Pos (0UL) /*!< LVR_THRESHOLD (Bit 0) */
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#define SPM_PWR_MGR_CFG1_LVR_THRESHOLD_Msk (0x1UL) /*!< LVR_THRESHOLD (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG1_LVD_THRESHOLD_Pos (1UL) /*!< LVD_THRESHOLD (Bit 1) */
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#define SPM_PWR_MGR_CFG1_LVD_THRESHOLD_Msk (0x2UL) /*!< LVD_THRESHOLD (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG1_HSI_EN_VLPS_Pos (8UL) /*!< HSI_EN_VLPS (Bit 8) */
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#define SPM_PWR_MGR_CFG1_HSI_EN_VLPS_Msk (0x100UL) /*!< HSI_EN_VLPS (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG1_HSI_EN_NORMAL_Pos (9UL) /*!< HSI_EN_NORMAL (Bit 9) */
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#define SPM_PWR_MGR_CFG1_HSI_EN_NORMAL_Msk (0x200UL) /*!< HSI_EN_NORMAL (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG1_VHSI_EN_Pos (10UL) /*!< VHSI_EN (Bit 10) */
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#define SPM_PWR_MGR_CFG1_VHSI_EN_Msk (0x400UL) /*!< VHSI_EN (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG1_SPLL_RDY_Pos (23UL) /*!< SPLL_RDY (Bit 23) */
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#define SPM_PWR_MGR_CFG1_SPLL_RDY_Msk (0x800000UL) /*!< SPLL_RDY (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG1_HSI_RDY_Pos (24UL) /*!< HSI_RDY (Bit 24) */
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#define SPM_PWR_MGR_CFG1_HSI_RDY_Msk (0x1000000UL) /*!< HSI_RDY (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG1_VHSI_RDY_Pos (25UL) /*!< VHSI_RDY (Bit 25) */
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#define SPM_PWR_MGR_CFG1_VHSI_RDY_Msk (0x2000000UL) /*!< VHSI_RDY (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG1_XOSC_RDY_Pos (26UL) /*!< XOSC_RDY (Bit 26) */
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#define SPM_PWR_MGR_CFG1_XOSC_RDY_Msk (0x4000000UL) /*!< XOSC_RDY (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG1_SPLL_EN_Pos (27UL) /*!< SPLL_EN (Bit 27) */
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#define SPM_PWR_MGR_CFG1_SPLL_EN_Msk (0x8000000UL) /*!< SPLL_EN (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Pos (28UL) /*!< XOSC_HSEBYP (Bit 28) */
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#define SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Msk (0x10000000UL) /*!< XOSC_HSEBYP (Bitfield-Mask: 0x01) */
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#define SPM_PWR_MGR_CFG1_XOSC_HSEEN_Pos (29UL) /*!< XOSC_HSEEN (Bit 29) */
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#define SPM_PWR_MGR_CFG1_XOSC_HSEEN_Msk (0x20000000UL) /*!< XOSC_HSEEN (Bitfield-Mask: 0x01) */
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/* ================================================ PERIPH_SLEEP_ACK_STATUS ================================================ */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_I2C0_Pos (0UL) /*!< I2C0 (Bit 0) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_I2C0_Msk (0x1UL) /*!< I2C0 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI0_Pos (2UL) /*!< SPI0 (Bit 2) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI0_Msk (0x4UL) /*!< SPI0 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI1_Pos (3UL) /*!< SPI1 (Bit 3) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI1_Msk (0x8UL) /*!< SPI1 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI2_Pos (4UL) /*!< SPI2 (Bit 4) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI2_Msk (0x10UL) /*!< SPI2 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN0_Pos (5UL) /*!< CAN0 (Bit 5) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN0_Msk (0x20UL) /*!< CAN0 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN1_Pos (6UL) /*!< CAN1 (Bit 6) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN1_Msk (0x40UL) /*!< CAN1 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN2_Pos (7UL) /*!< CAN2 (Bit 7) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN2_Msk (0x80UL) /*!< CAN2 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN3_Pos (8UL) /*!< CAN3 (Bit 8) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN3_Msk (0x100UL) /*!< CAN3 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_UART0_Pos (11UL) /*!< UART0 (Bit 11) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_UART0_Msk (0x800UL) /*!< UART0 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_UART1_Pos (12UL) /*!< UART1 (Bit 12) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_UART1_Msk (0x1000UL) /*!< UART1 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_UART2_Pos (13UL) /*!< UART2 (Bit 13) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_UART2_Msk (0x2000UL) /*!< UART2 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_UART3_Pos (14UL) /*!< UART3 (Bit 14) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_UART3_Msk (0x4000UL) /*!< UART3 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_DMA0_Pos (17UL) /*!< DMA0 (Bit 17) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_DMA0_Msk (0x20000UL) /*!< DMA0 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_EIO_Pos (18UL) /*!< EIO (Bit 18) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_EIO_Msk (0x40000UL) /*!< EIO (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_FLASH_Pos (19UL) /*!< FLASH (Bit 19) */
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#define SPM_PERIPH_SLEEP_ACK_STATUS_FLASH_Msk (0x80000UL) /*!< FLASH (Bitfield-Mask: 0x01) */
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/* ================================================== PERIPH_SLEEP_ACK_EN ================================================== */
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#define SPM_PERIPH_SLEEP_ACK_EN_I2C0_Pos (0UL) /*!< I2C0 (Bit 0) */
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#define SPM_PERIPH_SLEEP_ACK_EN_I2C0_Msk (0x1UL) /*!< I2C0 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_SPI0_Pos (2UL) /*!< SPI0 (Bit 2) */
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#define SPM_PERIPH_SLEEP_ACK_EN_SPI0_Msk (0x4UL) /*!< SPI0 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_SPI1_Pos (3UL) /*!< SPI1 (Bit 3) */
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#define SPM_PERIPH_SLEEP_ACK_EN_SPI1_Msk (0x8UL) /*!< SPI1 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_SPI2_Pos (4UL) /*!< SPI2 (Bit 4) */
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#define SPM_PERIPH_SLEEP_ACK_EN_SPI2_Msk (0x10UL) /*!< SPI2 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_CAN0_Pos (5UL) /*!< CAN0 (Bit 5) */
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#define SPM_PERIPH_SLEEP_ACK_EN_CAN0_Msk (0x20UL) /*!< CAN0 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_CAN1_Pos (6UL) /*!< CAN1 (Bit 6) */
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#define SPM_PERIPH_SLEEP_ACK_EN_CAN1_Msk (0x40UL) /*!< CAN1 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_CAN2_Pos (7UL) /*!< CAN2 (Bit 7) */
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#define SPM_PERIPH_SLEEP_ACK_EN_CAN2_Msk (0x80UL) /*!< CAN2 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_CAN3_Pos (8UL) /*!< CAN3 (Bit 8) */
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#define SPM_PERIPH_SLEEP_ACK_EN_CAN3_Msk (0x100UL) /*!< CAN3 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_UART0_Pos (11UL) /*!< UART0 (Bit 11) */
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#define SPM_PERIPH_SLEEP_ACK_EN_UART0_Msk (0x800UL) /*!< UART0 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_UART1_Pos (12UL) /*!< UART1 (Bit 12) */
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#define SPM_PERIPH_SLEEP_ACK_EN_UART1_Msk (0x1000UL) /*!< UART1 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_UART2_Pos (13UL) /*!< UART2 (Bit 13) */
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#define SPM_PERIPH_SLEEP_ACK_EN_UART2_Msk (0x2000UL) /*!< UART2 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_UART3_Pos (14UL) /*!< UART3 (Bit 14) */
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#define SPM_PERIPH_SLEEP_ACK_EN_UART3_Msk (0x4000UL) /*!< UART3 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_DMA0_Pos (17UL) /*!< DMA0 (Bit 17) */
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#define SPM_PERIPH_SLEEP_ACK_EN_DMA0_Msk (0x20000UL) /*!< DMA0 (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_EIO_Pos (18UL) /*!< EIO (Bit 18) */
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#define SPM_PERIPH_SLEEP_ACK_EN_EIO_Msk (0x40000UL) /*!< EIO (Bitfield-Mask: 0x01) */
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#define SPM_PERIPH_SLEEP_ACK_EN_FLASH_Pos (19UL) /*!< FLASH (Bit 19) */
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#define SPM_PERIPH_SLEEP_ACK_EN_FLASH_Msk (0x80000UL) /*!< FLASH (Bitfield-Mask: 0x01) */
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/* ======================================================== STATUS ========================================================= */
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#define SPM_STATUS_CURR_POWER_MODE_Pos (0UL) /*!< CURR_POWER_MODE (Bit 0) */
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#define SPM_STATUS_CURR_POWER_MODE_Msk (0x7UL) /*!< CURR_POWER_MODE (Bitfield-Mask: 0x07) */
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#define SPM_STATUS_ACK_TIMEOUT_FLAG_Pos (4UL) /*!< ACK_TIMEOUT_FLAG (Bit 4) */
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#define SPM_STATUS_ACK_TIMEOUT_FLAG_Msk (0x10UL) /*!< ACK_TIMEOUT_FLAG (Bitfield-Mask: 0x01) */
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/* ======================================================= STB_WP_EN ======================================================= */
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#define SPM_STB_WP_EN_PA12_Pos (0UL) /*!< PA12 (Bit 0) */
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#define SPM_STB_WP_EN_PA12_Msk (0x3UL) /*!< PA12 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PB8_Pos (2UL) /*!< PB8 (Bit 2) */
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#define SPM_STB_WP_EN_PB8_Msk (0xcUL) /*!< PB8 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PB1_Pos (4UL) /*!< PB1 (Bit 4) */
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#define SPM_STB_WP_EN_PB1_Msk (0x30UL) /*!< PB1 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PB12_Pos (6UL) /*!< PB12 (Bit 6) */
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#define SPM_STB_WP_EN_PB12_Msk (0xc0UL) /*!< PB12 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PD3_Pos (8UL) /*!< PD3 (Bit 8) */
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#define SPM_STB_WP_EN_PD3_Msk (0x300UL) /*!< PD3 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PC2_Pos (10UL) /*!< PC2 (Bit 10) */
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#define SPM_STB_WP_EN_PC2_Msk (0xc00UL) /*!< PC2 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PC3_Pos (12UL) /*!< PC3 (Bit 12) */
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#define SPM_STB_WP_EN_PC3_Msk (0x3000UL) /*!< PC3 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PC6_Pos (14UL) /*!< PC6 (Bit 14) */
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#define SPM_STB_WP_EN_PC6_Msk (0xc000UL) /*!< PC6 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PC7_Pos (16UL) /*!< PC7 (Bit 16) */
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#define SPM_STB_WP_EN_PC7_Msk (0x30000UL) /*!< PC7 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PC16_Pos (18UL) /*!< PC16 (Bit 18) */
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#define SPM_STB_WP_EN_PC16_Msk (0xc0000UL) /*!< PC16 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PC17_Pos (20UL) /*!< PC17 (Bit 20) */
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#define SPM_STB_WP_EN_PC17_Msk (0x300000UL) /*!< PC17 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PD6_Pos (22UL) /*!< PD6 (Bit 22) */
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#define SPM_STB_WP_EN_PD6_Msk (0xc00000UL) /*!< PD6 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PD7_Pos (24UL) /*!< PD7 (Bit 24) */
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#define SPM_STB_WP_EN_PD7_Msk (0x3000000UL) /*!< PD7 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PE4_Pos (26UL) /*!< PE4 (Bit 26) */
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#define SPM_STB_WP_EN_PE4_Msk (0xc000000UL) /*!< PE4 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_PE5_Pos (28UL) /*!< PE5 (Bit 28) */
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#define SPM_STB_WP_EN_PE5_Msk (0x30000000UL) /*!< PE5 (Bitfield-Mask: 0x03) */
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#define SPM_STB_WP_EN_RTC_Pos (30UL) /*!< RTC (Bit 30) */
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#define SPM_STB_WP_EN_RTC_Msk (0xc0000000UL) /*!< RTC (Bitfield-Mask: 0x03) */
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/* ===================================================== STB_WP_STATUS ===================================================== */
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#define SPM_STB_WP_STATUS_PA12_Pos (0UL) /*!< PA12 (Bit 0) */
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#define SPM_STB_WP_STATUS_PA12_Msk (0x1UL) /*!< PA12 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PB0_Pos (1UL) /*!< PB0 (Bit 1) */
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#define SPM_STB_WP_STATUS_PB0_Msk (0x2UL) /*!< PB0 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PB1_Pos (2UL) /*!< PB1 (Bit 2) */
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#define SPM_STB_WP_STATUS_PB1_Msk (0x4UL) /*!< PB1 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PB12_Pos (3UL) /*!< PB12 (Bit 3) */
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#define SPM_STB_WP_STATUS_PB12_Msk (0x8UL) /*!< PB12 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PD3_Pos (4UL) /*!< PD3 (Bit 4) */
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#define SPM_STB_WP_STATUS_PD3_Msk (0x10UL) /*!< PD3 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PC2_Pos (5UL) /*!< PC2 (Bit 5) */
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#define SPM_STB_WP_STATUS_PC2_Msk (0x20UL) /*!< PC2 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PC3_Pos (6UL) /*!< PC3 (Bit 6) */
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#define SPM_STB_WP_STATUS_PC3_Msk (0x40UL) /*!< PC3 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PC6_Pos (7UL) /*!< PC6 (Bit 7) */
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#define SPM_STB_WP_STATUS_PC6_Msk (0x80UL) /*!< PC6 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PC7_Pos (8UL) /*!< PC7 (Bit 8) */
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#define SPM_STB_WP_STATUS_PC7_Msk (0x100UL) /*!< PC7 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PC16_Pos (9UL) /*!< PC16 (Bit 9) */
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#define SPM_STB_WP_STATUS_PC16_Msk (0x200UL) /*!< PC16 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PC17_Pos (10UL) /*!< PC17 (Bit 10) */
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#define SPM_STB_WP_STATUS_PC17_Msk (0x400UL) /*!< PC17 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PD6_Pos (11UL) /*!< PD6 (Bit 11) */
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#define SPM_STB_WP_STATUS_PD6_Msk (0x800UL) /*!< PD6 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PD7_Pos (12UL) /*!< PD7 (Bit 12) */
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#define SPM_STB_WP_STATUS_PD7_Msk (0x1000UL) /*!< PD7 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PE4_Pos (13UL) /*!< PE4 (Bit 13) */
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#define SPM_STB_WP_STATUS_PE4_Msk (0x2000UL) /*!< PE4 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_PE5_Pos (14UL) /*!< PE5 (Bit 14) */
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#define SPM_STB_WP_STATUS_PE5_Msk (0x4000UL) /*!< PE5 (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_RTC_Pos (15UL) /*!< RTC (Bit 15) */
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#define SPM_STB_WP_STATUS_RTC_Msk (0x8000UL) /*!< RTC (Bitfield-Mask: 0x01) */
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#define SPM_STB_WP_STATUS_STB_WP_FLG_Pos (16UL) /*!< STB_WP_FLG (Bit 16) */
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#define SPM_STB_WP_STATUS_STB_WP_FLG_Msk (0x10000UL) /*!< STB_WP_FLG (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ GPIO ================ */
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/* =========================================================================================================================== */
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/* ========================================================= PODR ========================================================== */
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#define GPIO_PODR_PODR0_Pos (0UL) /*!< PODR0 (Bit 0) */
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#define GPIO_PODR_PODR0_Msk (0x1UL) /*!< PODR0 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR1_Pos (1UL) /*!< PODR1 (Bit 1) */
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#define GPIO_PODR_PODR1_Msk (0x2UL) /*!< PODR1 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR2_Pos (2UL) /*!< PODR2 (Bit 2) */
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#define GPIO_PODR_PODR2_Msk (0x4UL) /*!< PODR2 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR3_Pos (3UL) /*!< PODR3 (Bit 3) */
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#define GPIO_PODR_PODR3_Msk (0x8UL) /*!< PODR3 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR4_Pos (4UL) /*!< PODR4 (Bit 4) */
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#define GPIO_PODR_PODR4_Msk (0x10UL) /*!< PODR4 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR5_Pos (5UL) /*!< PODR5 (Bit 5) */
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#define GPIO_PODR_PODR5_Msk (0x20UL) /*!< PODR5 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR6_Pos (6UL) /*!< PODR6 (Bit 6) */
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#define GPIO_PODR_PODR6_Msk (0x40UL) /*!< PODR6 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR7_Pos (7UL) /*!< PODR7 (Bit 7) */
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#define GPIO_PODR_PODR7_Msk (0x80UL) /*!< PODR7 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR8_Pos (8UL) /*!< PODR8 (Bit 8) */
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#define GPIO_PODR_PODR8_Msk (0x100UL) /*!< PODR8 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR9_Pos (9UL) /*!< PODR9 (Bit 9) */
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#define GPIO_PODR_PODR9_Msk (0x200UL) /*!< PODR9 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR10_Pos (10UL) /*!< PODR10 (Bit 10) */
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#define GPIO_PODR_PODR10_Msk (0x400UL) /*!< PODR10 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR11_Pos (11UL) /*!< PODR11 (Bit 11) */
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#define GPIO_PODR_PODR11_Msk (0x800UL) /*!< PODR11 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR12_Pos (12UL) /*!< PODR12 (Bit 12) */
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#define GPIO_PODR_PODR12_Msk (0x1000UL) /*!< PODR12 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR13_Pos (13UL) /*!< PODR13 (Bit 13) */
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#define GPIO_PODR_PODR13_Msk (0x2000UL) /*!< PODR13 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR14_Pos (14UL) /*!< PODR14 (Bit 14) */
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#define GPIO_PODR_PODR14_Msk (0x4000UL) /*!< PODR14 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR15_Pos (15UL) /*!< PODR15 (Bit 15) */
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#define GPIO_PODR_PODR15_Msk (0x8000UL) /*!< PODR15 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR16_Pos (16UL) /*!< PODR16 (Bit 16) */
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#define GPIO_PODR_PODR16_Msk (0x10000UL) /*!< PODR16 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR17_Pos (17UL) /*!< PODR17 (Bit 17) */
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#define GPIO_PODR_PODR17_Msk (0x20000UL) /*!< PODR17 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR18_Pos (18UL) /*!< PODR18 (Bit 18) */
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#define GPIO_PODR_PODR18_Msk (0x40000UL) /*!< PODR18 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR19_Pos (19UL) /*!< PODR19 (Bit 19) */
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#define GPIO_PODR_PODR19_Msk (0x80000UL) /*!< PODR19 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR20_Pos (20UL) /*!< PODR20 (Bit 20) */
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#define GPIO_PODR_PODR20_Msk (0x100000UL) /*!< PODR20 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR21_Pos (21UL) /*!< PODR21 (Bit 21) */
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#define GPIO_PODR_PODR21_Msk (0x200000UL) /*!< PODR21 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR22_Pos (22UL) /*!< PODR22 (Bit 22) */
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#define GPIO_PODR_PODR22_Msk (0x400000UL) /*!< PODR22 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR23_Pos (23UL) /*!< PODR23 (Bit 23) */
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#define GPIO_PODR_PODR23_Msk (0x800000UL) /*!< PODR23 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR24_Pos (24UL) /*!< PODR24 (Bit 24) */
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#define GPIO_PODR_PODR24_Msk (0x1000000UL) /*!< PODR24 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR25_Pos (25UL) /*!< PODR25 (Bit 25) */
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#define GPIO_PODR_PODR25_Msk (0x2000000UL) /*!< PODR25 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR26_Pos (26UL) /*!< PODR26 (Bit 26) */
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#define GPIO_PODR_PODR26_Msk (0x4000000UL) /*!< PODR26 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR27_Pos (27UL) /*!< PODR27 (Bit 27) */
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#define GPIO_PODR_PODR27_Msk (0x8000000UL) /*!< PODR27 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR28_Pos (28UL) /*!< PODR28 (Bit 28) */
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#define GPIO_PODR_PODR28_Msk (0x10000000UL) /*!< PODR28 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR29_Pos (29UL) /*!< PODR29 (Bit 29) */
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#define GPIO_PODR_PODR29_Msk (0x20000000UL) /*!< PODR29 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR30_Pos (30UL) /*!< PODR30 (Bit 30) */
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#define GPIO_PODR_PODR30_Msk (0x40000000UL) /*!< PODR30 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_PODR31_Pos (31UL) /*!< PODR31 (Bit 31) */
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#define GPIO_PODR_PODR31_Msk (0x80000000UL) /*!< PODR31 (Bitfield-Mask: 0x01) */
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#define GPIO_PODR_Pos(x) ((uint32_t)x) /*!< PODRx (Bit x) */
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#define GPIO_PODR_Msk(x) (0x01UL<<GPIO_PODR_Pos(x)) /*!< PODRx (Bitfield-Mask: 0x01) */
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/* ========================================================= PSOR ========================================================== */
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#define GPIO_PSOR_PSOR0_Pos (0UL) /*!< PSOR0 (Bit 0) */
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#define GPIO_PSOR_PSOR0_Msk (0x1UL) /*!< PSOR0 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR1_Pos (1UL) /*!< PSOR1 (Bit 1) */
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#define GPIO_PSOR_PSOR1_Msk (0x2UL) /*!< PSOR1 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR2_Pos (2UL) /*!< PSOR2 (Bit 2) */
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#define GPIO_PSOR_PSOR2_Msk (0x4UL) /*!< PSOR2 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR3_Pos (3UL) /*!< PSOR3 (Bit 3) */
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#define GPIO_PSOR_PSOR3_Msk (0x8UL) /*!< PSOR3 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR4_Pos (4UL) /*!< PSOR4 (Bit 4) */
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#define GPIO_PSOR_PSOR4_Msk (0x10UL) /*!< PSOR4 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR5_Pos (5UL) /*!< PSOR5 (Bit 5) */
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#define GPIO_PSOR_PSOR5_Msk (0x20UL) /*!< PSOR5 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR6_Pos (6UL) /*!< PSOR6 (Bit 6) */
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#define GPIO_PSOR_PSOR6_Msk (0x40UL) /*!< PSOR6 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR7_Pos (7UL) /*!< PSOR7 (Bit 7) */
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#define GPIO_PSOR_PSOR7_Msk (0x80UL) /*!< PSOR7 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR8_Pos (8UL) /*!< PSOR8 (Bit 8) */
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#define GPIO_PSOR_PSOR8_Msk (0x100UL) /*!< PSOR8 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR9_Pos (9UL) /*!< PSOR9 (Bit 9) */
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#define GPIO_PSOR_PSOR9_Msk (0x200UL) /*!< PSOR9 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR10_Pos (10UL) /*!< PSOR10 (Bit 10) */
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#define GPIO_PSOR_PSOR10_Msk (0x400UL) /*!< PSOR10 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR11_Pos (11UL) /*!< PSOR11 (Bit 11) */
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#define GPIO_PSOR_PSOR11_Msk (0x800UL) /*!< PSOR11 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR12_Pos (12UL) /*!< PSOR12 (Bit 12) */
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#define GPIO_PSOR_PSOR12_Msk (0x1000UL) /*!< PSOR12 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR13_Pos (13UL) /*!< PSOR13 (Bit 13) */
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#define GPIO_PSOR_PSOR13_Msk (0x2000UL) /*!< PSOR13 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR14_Pos (14UL) /*!< PSOR14 (Bit 14) */
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#define GPIO_PSOR_PSOR14_Msk (0x4000UL) /*!< PSOR14 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR15_Pos (15UL) /*!< PSOR15 (Bit 15) */
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#define GPIO_PSOR_PSOR15_Msk (0x8000UL) /*!< PSOR15 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR16_Pos (16UL) /*!< PSOR16 (Bit 16) */
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#define GPIO_PSOR_PSOR16_Msk (0x10000UL) /*!< PSOR16 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR17_Pos (17UL) /*!< PSOR17 (Bit 17) */
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#define GPIO_PSOR_PSOR17_Msk (0x20000UL) /*!< PSOR17 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR18_Pos (18UL) /*!< PSOR18 (Bit 18) */
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#define GPIO_PSOR_PSOR18_Msk (0x40000UL) /*!< PSOR18 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR19_Pos (19UL) /*!< PSOR19 (Bit 19) */
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#define GPIO_PSOR_PSOR19_Msk (0x80000UL) /*!< PSOR19 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR20_Pos (20UL) /*!< PSOR20 (Bit 20) */
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#define GPIO_PSOR_PSOR20_Msk (0x100000UL) /*!< PSOR20 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR21_Pos (21UL) /*!< PSOR21 (Bit 21) */
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#define GPIO_PSOR_PSOR21_Msk (0x200000UL) /*!< PSOR21 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR22_Pos (22UL) /*!< PSOR22 (Bit 22) */
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#define GPIO_PSOR_PSOR22_Msk (0x400000UL) /*!< PSOR22 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR23_Pos (23UL) /*!< PSOR23 (Bit 23) */
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#define GPIO_PSOR_PSOR23_Msk (0x800000UL) /*!< PSOR23 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR24_Pos (24UL) /*!< PSOR24 (Bit 24) */
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#define GPIO_PSOR_PSOR24_Msk (0x1000000UL) /*!< PSOR24 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR25_Pos (25UL) /*!< PSOR25 (Bit 25) */
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#define GPIO_PSOR_PSOR25_Msk (0x2000000UL) /*!< PSOR25 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR26_Pos (26UL) /*!< PSOR26 (Bit 26) */
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#define GPIO_PSOR_PSOR26_Msk (0x4000000UL) /*!< PSOR26 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR27_Pos (27UL) /*!< PSOR27 (Bit 27) */
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#define GPIO_PSOR_PSOR27_Msk (0x8000000UL) /*!< PSOR27 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR28_Pos (28UL) /*!< PSOR28 (Bit 28) */
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#define GPIO_PSOR_PSOR28_Msk (0x10000000UL) /*!< PSOR28 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR29_Pos (29UL) /*!< PSOR29 (Bit 29) */
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#define GPIO_PSOR_PSOR29_Msk (0x20000000UL) /*!< PSOR29 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PSOR30_Pos (30UL) /*!< PSOR30 (Bit 30) */
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#define GPIO_PSOR_PSOR30_Msk (0x40000000UL) /*!< PSOR30 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_PODR31_Pos (31UL) /*!< PODR31 (Bit 31) */
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#define GPIO_PSOR_PODR31_Msk (0x80000000UL) /*!< PODR31 (Bitfield-Mask: 0x01) */
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#define GPIO_PSOR_Pos(x) ((uint32_t)x) /*!< PSORx (Bit x) */
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#define GPIO_PSOR_Msk(x) (0x01UL<<GPIO_PSOR_Pos(x)) /*!< PSORx (Bitfield-Mask: 0x01) */
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/* ========================================================= PROR ========================================================== */
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#define GPIO_PROR_PROR0_Pos (0UL) /*!< PROR0 (Bit 0) */
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#define GPIO_PROR_PROR0_Msk (0x1UL) /*!< PROR0 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR1_Pos (1UL) /*!< PROR1 (Bit 1) */
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#define GPIO_PROR_PROR1_Msk (0x2UL) /*!< PROR1 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR2_Pos (2UL) /*!< PROR2 (Bit 2) */
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#define GPIO_PROR_PROR2_Msk (0x4UL) /*!< PROR2 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR3_Pos (3UL) /*!< PROR3 (Bit 3) */
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#define GPIO_PROR_PROR3_Msk (0x8UL) /*!< PROR3 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR4_Pos (4UL) /*!< PROR4 (Bit 4) */
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#define GPIO_PROR_PROR4_Msk (0x10UL) /*!< PROR4 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR5_Pos (5UL) /*!< PROR5 (Bit 5) */
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#define GPIO_PROR_PROR5_Msk (0x20UL) /*!< PROR5 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR6_Pos (6UL) /*!< PROR6 (Bit 6) */
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#define GPIO_PROR_PROR6_Msk (0x40UL) /*!< PROR6 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR7_Pos (7UL) /*!< PROR7 (Bit 7) */
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#define GPIO_PROR_PROR7_Msk (0x80UL) /*!< PROR7 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR8_Pos (8UL) /*!< PROR8 (Bit 8) */
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#define GPIO_PROR_PROR8_Msk (0x100UL) /*!< PROR8 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR9_Pos (9UL) /*!< PROR9 (Bit 9) */
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#define GPIO_PROR_PROR9_Msk (0x200UL) /*!< PROR9 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR10_Pos (10UL) /*!< PROR10 (Bit 10) */
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#define GPIO_PROR_PROR10_Msk (0x400UL) /*!< PROR10 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR11_Pos (11UL) /*!< PROR11 (Bit 11) */
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#define GPIO_PROR_PROR11_Msk (0x800UL) /*!< PROR11 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR12_Pos (12UL) /*!< PROR12 (Bit 12) */
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#define GPIO_PROR_PROR12_Msk (0x1000UL) /*!< PROR12 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR13_Pos (13UL) /*!< PROR13 (Bit 13) */
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#define GPIO_PROR_PROR13_Msk (0x2000UL) /*!< PROR13 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR14_Pos (14UL) /*!< PROR14 (Bit 14) */
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#define GPIO_PROR_PROR14_Msk (0x4000UL) /*!< PROR14 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR15_Pos (15UL) /*!< PROR15 (Bit 15) */
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#define GPIO_PROR_PROR15_Msk (0x8000UL) /*!< PROR15 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR16_Pos (16UL) /*!< PROR16 (Bit 16) */
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#define GPIO_PROR_PROR16_Msk (0x10000UL) /*!< PROR16 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR17_Pos (17UL) /*!< PROR17 (Bit 17) */
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#define GPIO_PROR_PROR17_Msk (0x20000UL) /*!< PROR17 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR18_Pos (18UL) /*!< PROR18 (Bit 18) */
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#define GPIO_PROR_PROR18_Msk (0x40000UL) /*!< PROR18 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR19_Pos (19UL) /*!< PROR19 (Bit 19) */
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#define GPIO_PROR_PROR19_Msk (0x80000UL) /*!< PROR19 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR20_Pos (20UL) /*!< PROR20 (Bit 20) */
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#define GPIO_PROR_PROR20_Msk (0x100000UL) /*!< PROR20 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR21_Pos (21UL) /*!< PROR21 (Bit 21) */
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#define GPIO_PROR_PROR21_Msk (0x200000UL) /*!< PROR21 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR22_Pos (22UL) /*!< PROR22 (Bit 22) */
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#define GPIO_PROR_PROR22_Msk (0x400000UL) /*!< PROR22 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR23_Pos (23UL) /*!< PROR23 (Bit 23) */
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#define GPIO_PROR_PROR23_Msk (0x800000UL) /*!< PROR23 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR24_Pos (24UL) /*!< PROR24 (Bit 24) */
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#define GPIO_PROR_PROR24_Msk (0x1000000UL) /*!< PROR24 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR25_Pos (25UL) /*!< PROR25 (Bit 25) */
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#define GPIO_PROR_PROR25_Msk (0x2000000UL) /*!< PROR25 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR26_Pos (26UL) /*!< PROR26 (Bit 26) */
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#define GPIO_PROR_PROR26_Msk (0x4000000UL) /*!< PROR26 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR27_Pos (27UL) /*!< PROR27 (Bit 27) */
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#define GPIO_PROR_PROR27_Msk (0x8000000UL) /*!< PROR27 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR28_Pos (28UL) /*!< PROR28 (Bit 28) */
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#define GPIO_PROR_PROR28_Msk (0x10000000UL) /*!< PROR28 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR29_Pos (29UL) /*!< PROR29 (Bit 29) */
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#define GPIO_PROR_PROR29_Msk (0x20000000UL) /*!< PROR29 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PROR30_Pos (30UL) /*!< PROR30 (Bit 30) */
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#define GPIO_PROR_PROR30_Msk (0x40000000UL) /*!< PROR30 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_PODR31_Pos (31UL) /*!< PODR31 (Bit 31) */
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#define GPIO_PROR_PODR31_Msk (0x80000000UL) /*!< PODR31 (Bitfield-Mask: 0x01) */
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#define GPIO_PROR_Pos(x) ((uint32_t)x) /*!< PRORx (Bit x) */
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#define GPIO_PROR_Msk(x) (0x01UL<<GPIO_PROR_Pos(x)) /*!< PRORx (Bitfield-Mask: 0x01) */
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/* ========================================================= PIOR ========================================================== */
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#define GPIO_PIOR_PIOR0_Pos (0UL) /*!< PIOR0 (Bit 0) */
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#define GPIO_PIOR_PIOR0_Msk (0x1UL) /*!< PIOR0 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR1_Pos (1UL) /*!< PIOR1 (Bit 1) */
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#define GPIO_PIOR_PIOR1_Msk (0x2UL) /*!< PIOR1 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR2_Pos (2UL) /*!< PIOR2 (Bit 2) */
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#define GPIO_PIOR_PIOR2_Msk (0x4UL) /*!< PIOR2 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR3_Pos (3UL) /*!< PIOR3 (Bit 3) */
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#define GPIO_PIOR_PIOR3_Msk (0x8UL) /*!< PIOR3 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR4_Pos (4UL) /*!< PIOR4 (Bit 4) */
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#define GPIO_PIOR_PIOR4_Msk (0x10UL) /*!< PIOR4 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR5_Pos (5UL) /*!< PIOR5 (Bit 5) */
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#define GPIO_PIOR_PIOR5_Msk (0x20UL) /*!< PIOR5 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR6_Pos (6UL) /*!< PIOR6 (Bit 6) */
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#define GPIO_PIOR_PIOR6_Msk (0x40UL) /*!< PIOR6 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR7_Pos (7UL) /*!< PIOR7 (Bit 7) */
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#define GPIO_PIOR_PIOR7_Msk (0x80UL) /*!< PIOR7 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR8_Pos (8UL) /*!< PIOR8 (Bit 8) */
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#define GPIO_PIOR_PIOR8_Msk (0x100UL) /*!< PIOR8 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR9_Pos (9UL) /*!< PIOR9 (Bit 9) */
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#define GPIO_PIOR_PIOR9_Msk (0x200UL) /*!< PIOR9 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR10_Pos (10UL) /*!< PIOR10 (Bit 10) */
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#define GPIO_PIOR_PIOR10_Msk (0x400UL) /*!< PIOR10 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR11_Pos (11UL) /*!< PIOR11 (Bit 11) */
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#define GPIO_PIOR_PIOR11_Msk (0x800UL) /*!< PIOR11 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR12_Pos (12UL) /*!< PIOR12 (Bit 12) */
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#define GPIO_PIOR_PIOR12_Msk (0x1000UL) /*!< PIOR12 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR13_Pos (13UL) /*!< PIOR13 (Bit 13) */
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#define GPIO_PIOR_PIOR13_Msk (0x2000UL) /*!< PIOR13 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR14_Pos (14UL) /*!< PIOR14 (Bit 14) */
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#define GPIO_PIOR_PIOR14_Msk (0x4000UL) /*!< PIOR14 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR15_Pos (15UL) /*!< PIOR15 (Bit 15) */
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#define GPIO_PIOR_PIOR15_Msk (0x8000UL) /*!< PIOR15 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR16_Pos (16UL) /*!< PIOR16 (Bit 16) */
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#define GPIO_PIOR_PIOR16_Msk (0x10000UL) /*!< PIOR16 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR17_Pos (17UL) /*!< PIOR17 (Bit 17) */
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#define GPIO_PIOR_PIOR17_Msk (0x20000UL) /*!< PIOR17 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR18_Pos (18UL) /*!< PIOR18 (Bit 18) */
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#define GPIO_PIOR_PIOR18_Msk (0x40000UL) /*!< PIOR18 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR19_Pos (19UL) /*!< PIOR19 (Bit 19) */
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#define GPIO_PIOR_PIOR19_Msk (0x80000UL) /*!< PIOR19 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR20_Pos (20UL) /*!< PIOR20 (Bit 20) */
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#define GPIO_PIOR_PIOR20_Msk (0x100000UL) /*!< PIOR20 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR21_Pos (21UL) /*!< PIOR21 (Bit 21) */
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#define GPIO_PIOR_PIOR21_Msk (0x200000UL) /*!< PIOR21 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR22_Pos (22UL) /*!< PIOR22 (Bit 22) */
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#define GPIO_PIOR_PIOR22_Msk (0x400000UL) /*!< PIOR22 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR23_Pos (23UL) /*!< PIOR23 (Bit 23) */
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#define GPIO_PIOR_PIOR23_Msk (0x800000UL) /*!< PIOR23 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR24_Pos (24UL) /*!< PIOR24 (Bit 24) */
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#define GPIO_PIOR_PIOR24_Msk (0x1000000UL) /*!< PIOR24 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR25_Pos (25UL) /*!< PIOR25 (Bit 25) */
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#define GPIO_PIOR_PIOR25_Msk (0x2000000UL) /*!< PIOR25 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR26_Pos (26UL) /*!< PIOR26 (Bit 26) */
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#define GPIO_PIOR_PIOR26_Msk (0x4000000UL) /*!< PIOR26 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR27_Pos (27UL) /*!< PIOR27 (Bit 27) */
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#define GPIO_PIOR_PIOR27_Msk (0x8000000UL) /*!< PIOR27 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR28_Pos (28UL) /*!< PIOR28 (Bit 28) */
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#define GPIO_PIOR_PIOR28_Msk (0x10000000UL) /*!< PIOR28 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR29_Pos (29UL) /*!< PIOR29 (Bit 29) */
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#define GPIO_PIOR_PIOR29_Msk (0x20000000UL) /*!< PIOR29 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR30_Pos (30UL) /*!< PIOR30 (Bit 30) */
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#define GPIO_PIOR_PIOR30_Msk (0x40000000UL) /*!< PIOR30 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_PIOR31_Pos (31UL) /*!< PIOR31 (Bit 31) */
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#define GPIO_PIOR_PIOR31_Msk (0x80000000UL) /*!< PIOR31 (Bitfield-Mask: 0x01) */
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#define GPIO_PIOR_Pos(x) ((uint32_t)x) /*!< PRORx (Bit x) */
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#define GPIO_PIOR_Msk(x) (0x01UL<<GPIO_PIOR_Pos(x)) /*!< PRORx (Bitfield-Mask: 0x01) */
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/* ========================================================= PIDR ========================================================== */
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#define GPIO_PIDR_PIDR0_Pos (0UL) /*!< PIDR0 (Bit 0) */
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#define GPIO_PIDR_PIDR0_Msk (0x1UL) /*!< PIDR0 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR1_Pos (1UL) /*!< PIDR1 (Bit 1) */
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#define GPIO_PIDR_PIDR1_Msk (0x2UL) /*!< PIDR1 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR2_Pos (2UL) /*!< PIDR2 (Bit 2) */
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#define GPIO_PIDR_PIDR2_Msk (0x4UL) /*!< PIDR2 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR3_Pos (3UL) /*!< PIDR3 (Bit 3) */
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#define GPIO_PIDR_PIDR3_Msk (0x8UL) /*!< PIDR3 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR4_Pos (4UL) /*!< PIDR4 (Bit 4) */
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#define GPIO_PIDR_PIDR4_Msk (0x10UL) /*!< PIDR4 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR5_Pos (5UL) /*!< PIDR5 (Bit 5) */
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#define GPIO_PIDR_PIDR5_Msk (0x20UL) /*!< PIDR5 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR6_Pos (6UL) /*!< PIDR6 (Bit 6) */
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#define GPIO_PIDR_PIDR6_Msk (0x40UL) /*!< PIDR6 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR7_Pos (7UL) /*!< PIDR7 (Bit 7) */
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#define GPIO_PIDR_PIDR7_Msk (0x80UL) /*!< PIDR7 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR8_Pos (8UL) /*!< PIDR8 (Bit 8) */
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#define GPIO_PIDR_PIDR8_Msk (0x100UL) /*!< PIDR8 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR9_Pos (9UL) /*!< PIDR9 (Bit 9) */
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#define GPIO_PIDR_PIDR9_Msk (0x200UL) /*!< PIDR9 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR10_Pos (10UL) /*!< PIDR10 (Bit 10) */
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#define GPIO_PIDR_PIDR10_Msk (0x400UL) /*!< PIDR10 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR11_Pos (11UL) /*!< PIDR11 (Bit 11) */
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#define GPIO_PIDR_PIDR11_Msk (0x800UL) /*!< PIDR11 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR12_Pos (12UL) /*!< PIDR12 (Bit 12) */
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#define GPIO_PIDR_PIDR12_Msk (0x1000UL) /*!< PIDR12 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR13_Pos (13UL) /*!< PIDR13 (Bit 13) */
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#define GPIO_PIDR_PIDR13_Msk (0x2000UL) /*!< PIDR13 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR14_Pos (14UL) /*!< PIDR14 (Bit 14) */
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#define GPIO_PIDR_PIDR14_Msk (0x4000UL) /*!< PIDR14 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR15_Pos (15UL) /*!< PIDR15 (Bit 15) */
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#define GPIO_PIDR_PIDR15_Msk (0x8000UL) /*!< PIDR15 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR16_Pos (16UL) /*!< PIDR16 (Bit 16) */
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#define GPIO_PIDR_PIDR16_Msk (0x10000UL) /*!< PIDR16 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR17_Pos (17UL) /*!< PIDR17 (Bit 17) */
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#define GPIO_PIDR_PIDR17_Msk (0x20000UL) /*!< PIDR17 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR18_Pos (18UL) /*!< PIDR18 (Bit 18) */
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#define GPIO_PIDR_PIDR18_Msk (0x40000UL) /*!< PIDR18 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR19_Pos (19UL) /*!< PIDR19 (Bit 19) */
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#define GPIO_PIDR_PIDR19_Msk (0x80000UL) /*!< PIDR19 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR20_Pos (20UL) /*!< PIDR20 (Bit 20) */
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#define GPIO_PIDR_PIDR20_Msk (0x100000UL) /*!< PIDR20 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR21_Pos (21UL) /*!< PIDR21 (Bit 21) */
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#define GPIO_PIDR_PIDR21_Msk (0x200000UL) /*!< PIDR21 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR22_Pos (22UL) /*!< PIDR22 (Bit 22) */
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#define GPIO_PIDR_PIDR22_Msk (0x400000UL) /*!< PIDR22 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR23_Pos (23UL) /*!< PIDR23 (Bit 23) */
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#define GPIO_PIDR_PIDR23_Msk (0x800000UL) /*!< PIDR23 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR24_Pos (24UL) /*!< PIDR24 (Bit 24) */
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#define GPIO_PIDR_PIDR24_Msk (0x1000000UL) /*!< PIDR24 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR25_Pos (25UL) /*!< PIDR25 (Bit 25) */
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#define GPIO_PIDR_PIDR25_Msk (0x2000000UL) /*!< PIDR25 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR26_Pos (26UL) /*!< PIDR26 (Bit 26) */
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#define GPIO_PIDR_PIDR26_Msk (0x4000000UL) /*!< PIDR26 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR27_Pos (27UL) /*!< PIDR27 (Bit 27) */
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#define GPIO_PIDR_PIDR27_Msk (0x8000000UL) /*!< PIDR27 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR28_Pos (28UL) /*!< PIDR28 (Bit 28) */
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#define GPIO_PIDR_PIDR28_Msk (0x10000000UL) /*!< PIDR28 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR29_Pos (29UL) /*!< PIDR29 (Bit 29) */
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#define GPIO_PIDR_PIDR29_Msk (0x20000000UL) /*!< PIDR29 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR30_Pos (30UL) /*!< PIDR30 (Bit 30) */
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#define GPIO_PIDR_PIDR30_Msk (0x40000000UL) /*!< PIDR30 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_PIDR31_Pos (31UL) /*!< PIDR31 (Bit 31) */
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#define GPIO_PIDR_PIDR31_Msk (0x80000000UL) /*!< PIDR31 (Bitfield-Mask: 0x01) */
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#define GPIO_PIDR_Pos(x) ((uint32_t)x) /*!< PIDRx (Bit x) */
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#define GPIO_PIDR_Msk(x) (0x01UL<<GPIO_PIDR_Pos(x)) /*!< PIDRx (Bitfield-Mask: 0x01) */
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/* ========================================================= POER ========================================================== */
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#define GPIO_POER_POER0_Pos (0UL) /*!< POER0 (Bit 0) */
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#define GPIO_POER_POER0_Msk (0x1UL) /*!< POER0 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER1_Pos (1UL) /*!< POER1 (Bit 1) */
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#define GPIO_POER_POER1_Msk (0x2UL) /*!< POER1 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER2_Pos (2UL) /*!< POER2 (Bit 2) */
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#define GPIO_POER_POER2_Msk (0x4UL) /*!< POER2 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER3_Pos (3UL) /*!< POER3 (Bit 3) */
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#define GPIO_POER_POER3_Msk (0x8UL) /*!< POER3 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER4_Pos (4UL) /*!< POER4 (Bit 4) */
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#define GPIO_POER_POER4_Msk (0x10UL) /*!< POER4 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER5_Pos (5UL) /*!< POER5 (Bit 5) */
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#define GPIO_POER_POER5_Msk (0x20UL) /*!< POER5 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER6_Pos (6UL) /*!< POER6 (Bit 6) */
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#define GPIO_POER_POER6_Msk (0x40UL) /*!< POER6 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER7_Pos (7UL) /*!< POER7 (Bit 7) */
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#define GPIO_POER_POER7_Msk (0x80UL) /*!< POER7 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER8_Pos (8UL) /*!< POER8 (Bit 8) */
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#define GPIO_POER_POER8_Msk (0x100UL) /*!< POER8 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER9_Pos (9UL) /*!< POER9 (Bit 9) */
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#define GPIO_POER_POER9_Msk (0x200UL) /*!< POER9 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER10_Pos (10UL) /*!< POER10 (Bit 10) */
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#define GPIO_POER_POER10_Msk (0x400UL) /*!< POER10 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER11_Pos (11UL) /*!< POER11 (Bit 11) */
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#define GPIO_POER_POER11_Msk (0x800UL) /*!< POER11 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER12_Pos (12UL) /*!< POER12 (Bit 12) */
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#define GPIO_POER_POER12_Msk (0x1000UL) /*!< POER12 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER13_Pos (13UL) /*!< POER13 (Bit 13) */
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#define GPIO_POER_POER13_Msk (0x2000UL) /*!< POER13 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER14_Pos (14UL) /*!< POER14 (Bit 14) */
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#define GPIO_POER_POER14_Msk (0x4000UL) /*!< POER14 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER15_Pos (15UL) /*!< POER15 (Bit 15) */
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#define GPIO_POER_POER15_Msk (0x8000UL) /*!< POER15 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER16_Pos (16UL) /*!< POER16 (Bit 16) */
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#define GPIO_POER_POER16_Msk (0x10000UL) /*!< POER16 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER17_Pos (17UL) /*!< POER17 (Bit 17) */
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#define GPIO_POER_POER17_Msk (0x20000UL) /*!< POER17 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER18_Pos (18UL) /*!< POER18 (Bit 18) */
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#define GPIO_POER_POER18_Msk (0x40000UL) /*!< POER18 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER19_Pos (19UL) /*!< POER19 (Bit 19) */
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#define GPIO_POER_POER19_Msk (0x80000UL) /*!< POER19 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER20_Pos (20UL) /*!< POER20 (Bit 20) */
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#define GPIO_POER_POER20_Msk (0x100000UL) /*!< POER20 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER21_Pos (21UL) /*!< POER21 (Bit 21) */
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#define GPIO_POER_POER21_Msk (0x200000UL) /*!< POER21 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER22_Pos (22UL) /*!< POER22 (Bit 22) */
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#define GPIO_POER_POER22_Msk (0x400000UL) /*!< POER22 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER23_Pos (23UL) /*!< POER23 (Bit 23) */
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#define GPIO_POER_POER23_Msk (0x800000UL) /*!< POER23 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER24_Pos (24UL) /*!< POER24 (Bit 24) */
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#define GPIO_POER_POER24_Msk (0x1000000UL) /*!< POER24 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER25_Pos (25UL) /*!< POER25 (Bit 25) */
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#define GPIO_POER_POER25_Msk (0x2000000UL) /*!< POER25 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER26_Pos (26UL) /*!< POER26 (Bit 26) */
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#define GPIO_POER_POER26_Msk (0x4000000UL) /*!< POER26 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER27_Pos (27UL) /*!< POER27 (Bit 27) */
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#define GPIO_POER_POER27_Msk (0x8000000UL) /*!< POER27 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER28_Pos (28UL) /*!< POER28 (Bit 28) */
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#define GPIO_POER_POER28_Msk (0x10000000UL) /*!< POER28 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER29_Pos (29UL) /*!< POER29 (Bit 29) */
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#define GPIO_POER_POER29_Msk (0x20000000UL) /*!< POER29 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER30_Pos (30UL) /*!< POER30 (Bit 30) */
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#define GPIO_POER_POER30_Msk (0x40000000UL) /*!< POER30 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_POER31_Pos (31UL) /*!< POER31 (Bit 31) */
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#define GPIO_POER_POER31_Msk (0x80000000UL) /*!< POER31 (Bitfield-Mask: 0x01) */
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#define GPIO_POER_Pos(x) ((uint32_t)x) /*!< POERx (Bit x) */
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#define GPIO_POER_Msk(x) (0x01UL<<GPIO_POER_Pos(x)) /*!< POERx (Bitfield-Mask: 0x01) */
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/* ========================================================= PIER ========================================================== */
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#define GPIO_PIER_PIER0_Pos (0UL) /*!< PIER0 (Bit 0) */
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#define GPIO_PIER_PIER0_Msk (0x1UL) /*!< PIER0 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER1_Pos (1UL) /*!< PIER1 (Bit 1) */
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#define GPIO_PIER_PIER1_Msk (0x2UL) /*!< PIER1 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER2_Pos (2UL) /*!< PIER2 (Bit 2) */
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#define GPIO_PIER_PIER2_Msk (0x4UL) /*!< PIER2 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER3_Pos (3UL) /*!< PIER3 (Bit 3) */
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#define GPIO_PIER_PIER3_Msk (0x8UL) /*!< PIER3 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER4_Pos (4UL) /*!< PIER4 (Bit 4) */
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#define GPIO_PIER_PIER4_Msk (0x10UL) /*!< PIER4 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER5_Pos (5UL) /*!< PIER5 (Bit 5) */
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#define GPIO_PIER_PIER5_Msk (0x20UL) /*!< PIER5 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER6_Pos (6UL) /*!< PIER6 (Bit 6) */
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#define GPIO_PIER_PIER6_Msk (0x40UL) /*!< PIER6 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER7_Pos (7UL) /*!< PIER7 (Bit 7) */
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#define GPIO_PIER_PIER7_Msk (0x80UL) /*!< PIER7 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER8_Pos (8UL) /*!< PIER8 (Bit 8) */
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#define GPIO_PIER_PIER8_Msk (0x100UL) /*!< PIER8 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER9_Pos (9UL) /*!< PIER9 (Bit 9) */
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#define GPIO_PIER_PIER9_Msk (0x200UL) /*!< PIER9 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER10_Pos (10UL) /*!< PIER10 (Bit 10) */
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#define GPIO_PIER_PIER10_Msk (0x400UL) /*!< PIER10 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER11_Pos (11UL) /*!< PIER11 (Bit 11) */
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#define GPIO_PIER_PIER11_Msk (0x800UL) /*!< PIER11 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER12_Pos (12UL) /*!< PIER12 (Bit 12) */
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#define GPIO_PIER_PIER12_Msk (0x1000UL) /*!< PIER12 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER13_Pos (13UL) /*!< PIER13 (Bit 13) */
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#define GPIO_PIER_PIER13_Msk (0x2000UL) /*!< PIER13 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER14_Pos (14UL) /*!< PIER14 (Bit 14) */
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#define GPIO_PIER_PIER14_Msk (0x4000UL) /*!< PIER14 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER15_Pos (15UL) /*!< PIER15 (Bit 15) */
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#define GPIO_PIER_PIER15_Msk (0x8000UL) /*!< PIER15 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER16_Pos (16UL) /*!< PIER16 (Bit 16) */
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#define GPIO_PIER_PIER16_Msk (0x10000UL) /*!< PIER16 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER17_Pos (17UL) /*!< PIER17 (Bit 17) */
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#define GPIO_PIER_PIER17_Msk (0x20000UL) /*!< PIER17 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER18_Pos (18UL) /*!< PIER18 (Bit 18) */
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#define GPIO_PIER_PIER18_Msk (0x40000UL) /*!< PIER18 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER19_Pos (19UL) /*!< PIER19 (Bit 19) */
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#define GPIO_PIER_PIER19_Msk (0x80000UL) /*!< PIER19 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER20_Pos (20UL) /*!< PIER20 (Bit 20) */
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#define GPIO_PIER_PIER20_Msk (0x100000UL) /*!< PIER20 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER21_Pos (21UL) /*!< PIER21 (Bit 21) */
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#define GPIO_PIER_PIER21_Msk (0x200000UL) /*!< PIER21 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER22_Pos (22UL) /*!< PIER22 (Bit 22) */
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#define GPIO_PIER_PIER22_Msk (0x400000UL) /*!< PIER22 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER23_Pos (23UL) /*!< PIER23 (Bit 23) */
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#define GPIO_PIER_PIER23_Msk (0x800000UL) /*!< PIER23 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER24_Pos (24UL) /*!< PIER24 (Bit 24) */
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#define GPIO_PIER_PIER24_Msk (0x1000000UL) /*!< PIER24 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER25_Pos (25UL) /*!< PIER25 (Bit 25) */
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#define GPIO_PIER_PIER25_Msk (0x2000000UL) /*!< PIER25 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER26_Pos (26UL) /*!< PIER26 (Bit 26) */
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#define GPIO_PIER_PIER26_Msk (0x4000000UL) /*!< PIER26 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER27_Pos (27UL) /*!< PIER27 (Bit 27) */
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#define GPIO_PIER_PIER27_Msk (0x8000000UL) /*!< PIER27 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER28_Pos (28UL) /*!< PIER28 (Bit 28) */
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#define GPIO_PIER_PIER28_Msk (0x10000000UL) /*!< PIER28 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER29_Pos (29UL) /*!< PIER29 (Bit 29) */
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#define GPIO_PIER_PIER29_Msk (0x20000000UL) /*!< PIER29 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER30_Pos (30UL) /*!< PIER30 (Bit 30) */
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#define GPIO_PIER_PIER30_Msk (0x40000000UL) /*!< PIER30 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_PIER31_Pos (31UL) /*!< PIER31 (Bit 31) */
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#define GPIO_PIER_PIER31_Msk (0x80000000UL) /*!< PIER31 (Bitfield-Mask: 0x01) */
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#define GPIO_PIER_Pos(x) ((uint32_t)x) /*!< PIERx (Bit x) */
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#define GPIO_PIER_Msk(x) (0x01UL<<GPIO_PIER_Pos(x)) /*!< PIERx (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ PORTA ================ */
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/* =========================================================================================================================== */
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/* ========================================================= PCR =========================================================== */
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#define PORT_PCR_PU_Pos (0UL) /*!< PU (Bit 0) */
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#define PORT_PCR_PU_Msk (0x1UL) /*!< PU (Bitfield-Mask: 0x01) */
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#define PORT_PCR_PD_Pos (1UL) /*!< PD (Bit 1) */
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#define PORT_PCR_PD_Msk (0x2UL) /*!< PD (Bitfield-Mask: 0x01) */
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#define PORT_PCR_PFE_Pos (4UL) /*!< PFE (Bit 4) */
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#define PORT_PCR_PFE_Msk (0x10UL) /*!< PFE (Bitfield-Mask: 0x01) */
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#define PORT_PCR_DSE_Pos (6UL) /*!< DSE (Bit 6) */
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#define PORT_PCR_DSE_Msk (0x40UL) /*!< DSE (Bitfield-Mask: 0x01) */
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#define PORT_PCR_MUX_Pos (8UL) /*!< MUX (Bit 8) */
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#define PORT_PCR_MUX_Msk (0x700UL) /*!< MUX (Bitfield-Mask: 0x07) */
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#define PORT_PCR_TDSEL_Pos (11UL) /*!< TDSEL (Bit 11) */
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#define PORT_PCR_TDSEL_Msk (0x7800UL) /*!< TDSEL (Bitfield-Mask: 0x0f) */
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#define PORT_PCR_LK_Pos (15UL) /*!< LK (Bit 15) */
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#define PORT_PCR_LK_Msk (0x8000UL) /*!< LK (Bitfield-Mask: 0x01) */
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#define PORT_PCR_IRQC_Pos (16UL) /*!< IRQC (Bit 16) */
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#define PORT_PCR_IRQC_Msk (0xf0000UL) /*!< IRQC (Bitfield-Mask: 0x0f) */
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#define PORT_PCR_ISF_Pos (24UL) /*!< ISF (Bit 24) */
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#define PORT_PCR_ISF_Msk (0x1000000UL) /*!< ISF (Bitfield-Mask: 0x01) */
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/* ========================================================= ISFR ========================================================== */
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#define PORT_ISFR_ISF0_Pos (0UL) /*!< ISF0 (Bit 0) */
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#define PORT_ISFR_ISF0_Msk (0x1UL) /*!< ISF0 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF1_Pos (1UL) /*!< ISF1 (Bit 1) */
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#define PORT_ISFR_ISF1_Msk (0x2UL) /*!< ISF1 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF2_Pos (2UL) /*!< ISF2 (Bit 2) */
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#define PORT_ISFR_ISF2_Msk (0x4UL) /*!< ISF2 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF3_Pos (3UL) /*!< ISF3 (Bit 3) */
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#define PORT_ISFR_ISF3_Msk (0x8UL) /*!< ISF3 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF4_Pos (4UL) /*!< ISF4 (Bit 4) */
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#define PORT_ISFR_ISF4_Msk (0x10UL) /*!< ISF4 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF5_Pos (5UL) /*!< ISF5 (Bit 5) */
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#define PORT_ISFR_ISF5_Msk (0x20UL) /*!< ISF5 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF6_Pos (6UL) /*!< ISF6 (Bit 6) */
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#define PORT_ISFR_ISF6_Msk (0x40UL) /*!< ISF6 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF7_Pos (7UL) /*!< ISF7 (Bit 7) */
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#define PORT_ISFR_ISF7_Msk (0x80UL) /*!< ISF7 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF8_Pos (8UL) /*!< ISF8 (Bit 8) */
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#define PORT_ISFR_ISF8_Msk (0x100UL) /*!< ISF8 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF9_Pos (9UL) /*!< ISF9 (Bit 9) */
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#define PORT_ISFR_ISF9_Msk (0x200UL) /*!< ISF9 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF10_Pos (10UL) /*!< ISF10 (Bit 10) */
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#define PORT_ISFR_ISF10_Msk (0x400UL) /*!< ISF10 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF11_Pos (11UL) /*!< ISF11 (Bit 11) */
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#define PORT_ISFR_ISF11_Msk (0x800UL) /*!< ISF11 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF12_Pos (12UL) /*!< ISF12 (Bit 12) */
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#define PORT_ISFR_ISF12_Msk (0x1000UL) /*!< ISF12 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF13_Pos (13UL) /*!< ISF13 (Bit 13) */
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#define PORT_ISFR_ISF13_Msk (0x2000UL) /*!< ISF13 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF14_Pos (14UL) /*!< ISF14 (Bit 14) */
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#define PORT_ISFR_ISF14_Msk (0x4000UL) /*!< ISF14 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF15_Pos (15UL) /*!< ISF15 (Bit 15) */
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#define PORT_ISFR_ISF15_Msk (0x8000UL) /*!< ISF15 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF16_Pos (16UL) /*!< ISF16 (Bit 16) */
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#define PORT_ISFR_ISF16_Msk (0x10000UL) /*!< ISF16 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF17_Pos (17UL) /*!< ISF17 (Bit 17) */
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#define PORT_ISFR_ISF17_Msk (0x20000UL) /*!< ISF17 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF18_Pos (18UL) /*!< ISF18 (Bit 18) */
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#define PORT_ISFR_ISF18_Msk (0x40000UL) /*!< ISF18 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF19_Pos (19UL) /*!< ISF19 (Bit 19) */
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#define PORT_ISFR_ISF19_Msk (0x80000UL) /*!< ISF19 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF20_Pos (20UL) /*!< ISF20 (Bit 20) */
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#define PORT_ISFR_ISF20_Msk (0x100000UL) /*!< ISF20 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF21_Pos (21UL) /*!< ISF21 (Bit 21) */
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#define PORT_ISFR_ISF21_Msk (0x200000UL) /*!< ISF21 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF22_Pos (22UL) /*!< ISF22 (Bit 22) */
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#define PORT_ISFR_ISF22_Msk (0x400000UL) /*!< ISF22 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF23_Pos (23UL) /*!< ISF23 (Bit 23) */
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#define PORT_ISFR_ISF23_Msk (0x800000UL) /*!< ISF23 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF24_Pos (24UL) /*!< ISF24 (Bit 24) */
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#define PORT_ISFR_ISF24_Msk (0x1000000UL) /*!< ISF24 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF25_Pos (25UL) /*!< ISF25 (Bit 25) */
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#define PORT_ISFR_ISF25_Msk (0x2000000UL) /*!< ISF25 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF26_Pos (26UL) /*!< ISF26 (Bit 26) */
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#define PORT_ISFR_ISF26_Msk (0x4000000UL) /*!< ISF26 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF27_Pos (27UL) /*!< ISF27 (Bit 27) */
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#define PORT_ISFR_ISF27_Msk (0x8000000UL) /*!< ISF27 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF28_Pos (28UL) /*!< ISF28 (Bit 28) */
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#define PORT_ISFR_ISF28_Msk (0x10000000UL) /*!< ISF28 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF29_Pos (29UL) /*!< ISF29 (Bit 29) */
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#define PORT_ISFR_ISF29_Msk (0x20000000UL) /*!< ISF29 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF30_Pos (30UL) /*!< ISF30 (Bit 30) */
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#define PORT_ISFR_ISF30_Msk (0x40000000UL) /*!< ISF30 (Bitfield-Mask: 0x01) */
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#define PORT_ISFR_ISF31_Pos (31UL) /*!< ISF31 (Bit 31) */
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#define PORT_ISFR_ISF31_Msk (0x80000000UL) /*!< ISF31 (Bitfield-Mask: 0x01) */
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#define GPIO_ISFR_Pos(x) ((uint32_t)x) /*!< PIERx (Bit x) */
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#define GPIO_ISFR_Msk(x) (0x01UL<<GPIO_ISFR_Pos(x)) /*!< PIERx (Bitfield-Mask: 0x01) */
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/* ========================================================= DFER ========================================================== */
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#define PORT_DFER_DFE0_Pos (0UL) /*!< DFE0 (Bit 0) */
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#define PORT_DFER_DFE0_Msk (0x1UL) /*!< DFE0 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE1_Pos (1UL) /*!< DFE1 (Bit 1) */
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#define PORT_DFER_DFE1_Msk (0x2UL) /*!< DFE1 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE2_Pos (2UL) /*!< DFE2 (Bit 2) */
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#define PORT_DFER_DFE2_Msk (0x4UL) /*!< DFE2 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE3_Pos (3UL) /*!< DFE3 (Bit 3) */
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#define PORT_DFER_DFE3_Msk (0x8UL) /*!< DFE3 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE4_Pos (4UL) /*!< DFE4 (Bit 4) */
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#define PORT_DFER_DFE4_Msk (0x10UL) /*!< DFE4 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE5_Pos (5UL) /*!< DFE5 (Bit 5) */
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#define PORT_DFER_DFE5_Msk (0x20UL) /*!< DFE5 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE6_Pos (6UL) /*!< DFE6 (Bit 6) */
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#define PORT_DFER_DFE6_Msk (0x40UL) /*!< DFE6 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE7_Pos (7UL) /*!< DFE7 (Bit 7) */
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#define PORT_DFER_DFE7_Msk (0x80UL) /*!< DFE7 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE8_Pos (8UL) /*!< DFE8 (Bit 8) */
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#define PORT_DFER_DFE8_Msk (0x100UL) /*!< DFE8 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE9_Pos (9UL) /*!< DFE9 (Bit 9) */
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#define PORT_DFER_DFE9_Msk (0x200UL) /*!< DFE9 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE10_Pos (10UL) /*!< DFE10 (Bit 10) */
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#define PORT_DFER_DFE10_Msk (0x400UL) /*!< DFE10 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE11_Pos (11UL) /*!< DFE11 (Bit 11) */
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#define PORT_DFER_DFE11_Msk (0x800UL) /*!< DFE11 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE12_Pos (12UL) /*!< DFE12 (Bit 12) */
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#define PORT_DFER_DFE12_Msk (0x1000UL) /*!< DFE12 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE13_Pos (13UL) /*!< DFE13 (Bit 13) */
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#define PORT_DFER_DFE13_Msk (0x2000UL) /*!< DFE13 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE14_Pos (14UL) /*!< DFE14 (Bit 14) */
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#define PORT_DFER_DFE14_Msk (0x4000UL) /*!< DFE14 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE15_Pos (15UL) /*!< DFE15 (Bit 15) */
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#define PORT_DFER_DFE15_Msk (0x8000UL) /*!< DFE15 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE16_Pos (16UL) /*!< DFE16 (Bit 16) */
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#define PORT_DFER_DFE16_Msk (0x10000UL) /*!< DFE16 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE17_Pos (17UL) /*!< DFE17 (Bit 17) */
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#define PORT_DFER_DFE17_Msk (0x20000UL) /*!< DFE17 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE18_Pos (18UL) /*!< DFE18 (Bit 18) */
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#define PORT_DFER_DFE18_Msk (0x40000UL) /*!< DFE18 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE19_Pos (19UL) /*!< DFE19 (Bit 19) */
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#define PORT_DFER_DFE19_Msk (0x80000UL) /*!< DFE19 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE20_Pos (20UL) /*!< DFE20 (Bit 20) */
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#define PORT_DFER_DFE20_Msk (0x100000UL) /*!< DFE20 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE21_Pos (21UL) /*!< DFE21 (Bit 21) */
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#define PORT_DFER_DFE21_Msk (0x200000UL) /*!< DFE21 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE22_Pos (22UL) /*!< DFE22 (Bit 22) */
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#define PORT_DFER_DFE22_Msk (0x400000UL) /*!< DFE22 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE23_Pos (23UL) /*!< DFE23 (Bit 23) */
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#define PORT_DFER_DFE23_Msk (0x800000UL) /*!< DFE23 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE24_Pos (24UL) /*!< DFE24 (Bit 24) */
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#define PORT_DFER_DFE24_Msk (0x1000000UL) /*!< DFE24 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE25_Pos (25UL) /*!< DFE25 (Bit 25) */
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#define PORT_DFER_DFE25_Msk (0x2000000UL) /*!< DFE25 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE26_Pos (26UL) /*!< DFE26 (Bit 26) */
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#define PORT_DFER_DFE26_Msk (0x4000000UL) /*!< DFE26 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE27_Pos (27UL) /*!< DFE27 (Bit 27) */
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#define PORT_DFER_DFE27_Msk (0x8000000UL) /*!< DFE27 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE28_Pos (28UL) /*!< DFE28 (Bit 28) */
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#define PORT_DFER_DFE28_Msk (0x10000000UL) /*!< DFE28 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE29_Pos (29UL) /*!< DFE29 (Bit 29) */
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#define PORT_DFER_DFE29_Msk (0x20000000UL) /*!< DFE29 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE30_Pos (30UL) /*!< DFE30 (Bit 30) */
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#define PORT_DFER_DFE30_Msk (0x40000000UL) /*!< DFE30 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_DFE31_Pos (31UL) /*!< DFE31 (Bit 31) */
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#define PORT_DFER_DFE31_Msk (0x80000000UL) /*!< DFE31 (Bitfield-Mask: 0x01) */
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#define PORT_DFER_Pos(x) ((uint32_t)x) /*!< DFERx (Bit x) */
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#define PORT_DFER_Msk(x) (0x01UL<<PORT_DFER_Pos(x)) /*!< DFERx (Bitfield-Mask: 0x01) */
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/* ========================================================= DFCR ========================================================== */
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#define PORT_DFCR_CS_Pos (0UL) /*!< CS (Bit 0) */
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#define PORT_DFCR_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */
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/* ========================================================= DFWR ========================================================== */
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#define PORT_DFWR_FILT_Pos (0UL) /*!< FILT (Bit 0) */
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#define PORT_DFWR_FILT_Msk (0x1fUL) /*!< FILT (Bitfield-Mask: 0x1f) */
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/* =========================================================================================================================== */
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/* ================ CAN ================ */
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/* =========================================================================================================================== */
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/* ======================================================= TBUF/RBUF ======================================================= */
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#define CAN_INFO_ID_Pos (0UL) /*!< ID (Bit 0) */
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#define CAN_INFO_ID_Msk (0x1FFFFFFFUL) /*!< ID (Bitfield-Mask: 0x1FFFFFFF) */
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#define CAN_INFO_TTSEN_Pos (30UL) /*!< TTSEN (Bit 30) */
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#define CAN_INFO_TTSEN_Msk (0x40000000UL) /*!< TTSEN (Bitfield-Mask: 0x01) */
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#define CAN_INFO_ESI_Pos (31UL) /*!< ESI (Bit 31) */
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#define CAN_INFO_ESI_Msk (0x80000000UL) /*!< ESI (Bitfield-Mask: 0x01) */
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#define CAN_INFO_DLC_Pos (0UL) /*!< DLC (Bit 0) */
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#define CAN_INFO_DLC_Msk (0x0FUL) /*!< DLC (Bitfield-Mask: 0x0F) */
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#define CAN_INFO_BRS_Pos (4UL) /*!< BRS (Bit 4) */
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#define CAN_INFO_BRS_Msk (0x10UL) /*!< BRS (Bitfield-Mask: 0x01) */
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#define CAN_INFO_FDF_Pos (5UL) /*!< FDF (Bit 5) */
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#define CAN_INFO_FDF_Msk (0x20UL) /*!< FDF (Bitfield-Mask: 0x01) */
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#define CAN_INFO_RTR_Pos (6UL) /*!< RTR (Bit 6) */
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#define CAN_INFO_RTR_Msk (0x40UL) /*!< RTR (Bitfield-Mask: 0x01) */
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#define CAN_INFO_IDE_Pos (7UL) /*!< IDE (Bit 7) */
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#define CAN_INFO_IDE_Msk (0x80UL) /*!< IDE (Bitfield-Mask: 0x01) */
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#define CAN_INFO_TX_Pos (12UL) /*!< TX (Bit 12) */
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#define CAN_INFO_TX_Msk (0x1000UL) /*!< TX (Bitfield-Mask: 0x01) */
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#define CAN_INFO_KOER_Pos (13UL) /*!< KOER (Bit 13) */
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#define CAN_INFO_KOER_Msk (0xE000UL) /*!< KOER (Bitfield-Mask: 0x07) */
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/* ========================================================= CTRL0 ========================================================= */
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#define CAN_CTRL0_BUSOFF_Pos (0UL) /*!< BUSOFF (Bit 0) */
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#define CAN_CTRL0_BUSOFF_Msk (0x1UL) /*!< BUSOFF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_TACTIVE_Pos (1UL) /*!< TACTIVE (Bit 1) */
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#define CAN_CTRL0_TACTIVE_Msk (0x2UL) /*!< TACTIVE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_RACTIVE_Pos (2UL) /*!< RACTIVE (Bit 2) */
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#define CAN_CTRL0_RACTIVE_Msk (0x4UL) /*!< RACTIVE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_TSSS_Pos (3UL) /*!< TSSS (Bit 3) */
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#define CAN_CTRL0_TSSS_Msk (0x8UL) /*!< TSSS (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_TPSS_Pos (4UL) /*!< TPSS (Bit 4) */
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#define CAN_CTRL0_TPSS_Msk (0x10UL) /*!< TPSS (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_LBMI_Pos (5UL) /*!< LBMI (Bit 5) */
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#define CAN_CTRL0_LBMI_Msk (0x20UL) /*!< LBMI (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_LBME_Pos (6UL) /*!< LBME (Bit 6) */
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#define CAN_CTRL0_LBME_Msk (0x40UL) /*!< LBME (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_RESET_Pos (7UL) /*!< RESET (Bit 7) */
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#define CAN_CTRL0_RESET_Msk (0x80UL) /*!< RESET (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_TSA_Pos (8UL) /*!< TSA (Bit 8) */
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#define CAN_CTRL0_TSA_Msk (0x100UL) /*!< TSA (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_TSALL_Pos (9UL) /*!< TSALL (Bit 9) */
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#define CAN_CTRL0_TSALL_Msk (0x200UL) /*!< TSALL (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_TSONE_Pos (10UL) /*!< TSONE (Bit 10) */
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#define CAN_CTRL0_TSONE_Msk (0x400UL) /*!< TSONE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_TPA_Pos (11UL) /*!< TPA (Bit 11) */
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#define CAN_CTRL0_TPA_Msk (0x800UL) /*!< TPA (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_TPE_Pos (12UL) /*!< TPE (Bit 12) */
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#define CAN_CTRL0_TPE_Msk (0x1000UL) /*!< TPE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_STBY_Pos (13UL) /*!< STBY (Bit 13) */
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#define CAN_CTRL0_STBY_Msk (0x2000UL) /*!< STBY (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_LOM_Pos (14UL) /*!< LOM (Bit 14) */
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#define CAN_CTRL0_LOM_Msk (0x4000UL) /*!< LOM (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_TBSEL_Pos (15UL) /*!< TBSEL (Bit 15) */
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#define CAN_CTRL0_TBSEL_Msk (0x8000UL) /*!< TBSEL (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_TSSTAT_Pos (16UL) /*!< TSSTAT (Bit 16) */
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#define CAN_CTRL0_TSSTAT_Msk (0x30000UL) /*!< TSSTAT (Bitfield-Mask: 0x03) */
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#define CAN_CTRL0_IDLE_Pos (18UL) /*!< IDLE (Bit 18) */
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#define CAN_CTRL0_IDLE_Msk (0x40000UL) /*!< IDLE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_BOREC_Pos (19UL) /*!< BOREC (Bit 19) */
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#define CAN_CTRL0_BOREC_Msk (0x80000UL) /*!< BOREC (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_TSMODE_Pos (21UL) /*!< TSMODE (Bit 21) */
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#define CAN_CTRL0_TSMODE_Msk (0x200000UL) /*!< TSMODE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_TSNEXT_Pos (22UL) /*!< TSNEXT (Bit 22) */
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#define CAN_CTRL0_TSNEXT_Msk (0x400000UL) /*!< TSNEXT (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_FDISO_Pos (23UL) /*!< FDISO (Bit 23) */
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#define CAN_CTRL0_FDISO_Msk (0x800000UL) /*!< FDISO (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_RSTAT_Pos (24UL) /*!< RSTAT (Bit 24) */
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#define CAN_CTRL0_RSTAT_Msk (0x3000000UL) /*!< RSTAT (Bitfield-Mask: 0x03) */
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#define CAN_CTRL0_DREN_Pos (26UL) /*!< DREN (Bit 26) */
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#define CAN_CTRL0_DREN_Msk (0x4000000UL) /*!< DREN (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_RBALL_Pos (27UL) /*!< RBALL (Bit 27) */
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#define CAN_CTRL0_RBALL_Msk (0x8000000UL) /*!< RBALL (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_RREL_Pos (28UL) /*!< RREL (Bit 28) */
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#define CAN_CTRL0_RREL_Msk (0x10000000UL) /*!< RREL (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_ROV_Pos (29UL) /*!< ROV (Bit 29) */
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#define CAN_CTRL0_ROV_Msk (0x20000000UL) /*!< ROV (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_ROM_Pos (30UL) /*!< ROM (Bit 30) */
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#define CAN_CTRL0_ROM_Msk (0x40000000UL) /*!< ROM (Bitfield-Mask: 0x01) */
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#define CAN_CTRL0_SACK_Pos (31UL) /*!< SACK (Bit 31) */
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#define CAN_CTRL0_SACK_Msk (0x80000000UL) /*!< SACK (Bitfield-Mask: 0x01) */
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/* ========================================================= CTRL1 ========================================================= */
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#define CAN_CTRL1_TSFF_Pos (0UL) /*!< TSFF (Bit 0) */
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#define CAN_CTRL1_TSFF_Msk (0x1UL) /*!< TSFF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_EIE_Pos (1UL) /*!< EIE (Bit 1) */
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#define CAN_CTRL1_EIE_Msk (0x2UL) /*!< EIE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_TSIE_Pos (2UL) /*!< TSIE (Bit 2) */
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#define CAN_CTRL1_TSIE_Msk (0x4UL) /*!< TSIE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_TPIE_Pos (3UL) /*!< TPIE (Bit 3) */
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#define CAN_CTRL1_TPIE_Msk (0x8UL) /*!< TPIE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_RAFIE_Pos (4UL) /*!< RAFIE (Bit 4) */
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#define CAN_CTRL1_RAFIE_Msk (0x10UL) /*!< RAFIE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_RFIE_Pos (5UL) /*!< RFIE (Bit 5) */
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#define CAN_CTRL1_RFIE_Msk (0x20UL) /*!< RFIE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_ROIE_Pos (6UL) /*!< ROIE (Bit 6) */
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#define CAN_CTRL1_ROIE_Msk (0x40UL) /*!< ROIE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_RIE_Pos (7UL) /*!< RIE (Bit 7) */
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#define CAN_CTRL1_RIE_Msk (0x80UL) /*!< RIE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_AIF_Pos (8UL) /*!< AIF (Bit 8) */
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#define CAN_CTRL1_AIF_Msk (0x100UL) /*!< AIF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_EIF_Pos (9UL) /*!< EIF (Bit 9) */
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#define CAN_CTRL1_EIF_Msk (0x200UL) /*!< EIF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_TSIF_Pos (10UL) /*!< TSIF (Bit 10) */
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#define CAN_CTRL1_TSIF_Msk (0x400UL) /*!< TSIF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_TPIF_Pos (11UL) /*!< TPIF (Bit 11) */
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#define CAN_CTRL1_TPIF_Msk (0x800UL) /*!< TPIF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_RAFIF_Pos (12UL) /*!< RAFIF (Bit 12) */
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#define CAN_CTRL1_RAFIF_Msk (0x1000UL) /*!< RAFIF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_RFIF_Pos (13UL) /*!< RFIF (Bit 13) */
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#define CAN_CTRL1_RFIF_Msk (0x2000UL) /*!< RFIF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_ROIF_Pos (14UL) /*!< ROIF (Bit 14) */
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#define CAN_CTRL1_ROIF_Msk (0x4000UL) /*!< ROIF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_RIF_Pos (15UL) /*!< RIF (Bit 15) */
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#define CAN_CTRL1_RIF_Msk (0x8000UL) /*!< RIF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_BEIF_Pos (16UL) /*!< BEIF (Bit 16) */
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#define CAN_CTRL1_BEIF_Msk (0x10000UL) /*!< BEIF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_BEIE_Pos (17UL) /*!< BEIE (Bit 17) */
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#define CAN_CTRL1_BEIE_Msk (0x20000UL) /*!< BEIE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_ALIF_Pos (18UL) /*!< ALIF (Bit 18) */
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#define CAN_CTRL1_ALIF_Msk (0x40000UL) /*!< ALIF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_ALIE_Pos (19UL) /*!< ALIE (Bit 19) */
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#define CAN_CTRL1_ALIE_Msk (0x80000UL) /*!< ALIE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_EPIF_Pos (20UL) /*!< EPIF (Bit 20) */
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#define CAN_CTRL1_EPIF_Msk (0x100000UL) /*!< EPIF (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_EPIE_Pos (21UL) /*!< EPIE (Bit 21) */
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#define CAN_CTRL1_EPIE_Msk (0x200000UL) /*!< EPIE (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_EPASS_Pos (22UL) /*!< EPASS (Bit 22) */
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#define CAN_CTRL1_EPASS_Msk (0x400000UL) /*!< EPASS (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_EWARN_Pos (23UL) /*!< EWARN (Bit 23) */
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#define CAN_CTRL1_EWARN_Msk (0x800000UL) /*!< EWARN (Bitfield-Mask: 0x01) */
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#define CAN_CTRL1_EWL_Pos (24UL) /*!< EWL (Bit 24) */
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#define CAN_CTRL1_EWL_Msk (0xf000000UL) /*!< EWL (Bitfield-Mask: 0x0f) */
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#define CAN_CTRL1_AFWL_Pos (28UL) /*!< AFWL (Bit 28) */
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#define CAN_CTRL1_AFWL_Msk (0xf0000000UL) /*!< AFWL (Bitfield-Mask: 0x0f) */
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/* ======================================================= SBITRATE ======================================================== */
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#define CAN_SBITRATE_S_SEG_1_Pos (0UL) /*!< S_SEG_1 (Bit 0) */
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#define CAN_SBITRATE_S_SEG_1_Msk (0xffUL) /*!< S_SEG_1 (Bitfield-Mask: 0xff) */
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#define CAN_SBITRATE_S_SEG_2_Pos (8UL) /*!< S_SEG_2 (Bit 8) */
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#define CAN_SBITRATE_S_SEG_2_Msk (0x7f00UL) /*!< S_SEG_2 (Bitfield-Mask: 0x7f) */
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#define CAN_SBITRATE_S_SJW_Pos (16UL) /*!< S_SJW (Bit 16) */
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#define CAN_SBITRATE_S_SJW_Msk (0x7f0000UL) /*!< S_SJW (Bitfield-Mask: 0x7f) */
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#define CAN_SBITRATE_S_PRESC_Pos (24UL) /*!< S_PRESC (Bit 24) */
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#define CAN_SBITRATE_S_PRESC_Msk (0xff000000UL) /*!< S_PRESC (Bitfield-Mask: 0xff) */
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/* ======================================================= FBITRATE ======================================================== */
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#define CAN_FBITRATE_F_SEG_1_Pos (0UL) /*!< F_SEG_1 (Bit 0) */
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#define CAN_FBITRATE_F_SEG_1_Msk (0x1fUL) /*!< F_SEG_1 (Bitfield-Mask: 0x1f) */
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#define CAN_FBITRATE_F_SEG_2_Pos (8UL) /*!< F_SEG_2 (Bit 8) */
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#define CAN_FBITRATE_F_SEG_2_Msk (0xf00UL) /*!< F_SEG_2 (Bitfield-Mask: 0xf) */
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#define CAN_FBITRATE_F_SJW_Pos (16UL) /*!< F_SJW (Bit 16) */
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#define CAN_FBITRATE_F_SJW_Msk (0xf0000UL) /*!< F_SJW (Bitfield-Mask: 0xf) */
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#define CAN_FBITRATE_F_PRESC_Pos (24UL) /*!< F_PRESC (Bit 24) */
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#define CAN_FBITRATE_F_PRESC_Msk (0xff000000UL) /*!< F_PRESC (Bitfield-Mask: 0xff) */
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/* ======================================================== ERRINFO ======================================================== */
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#define CAN_ERRINFO_ALC_Pos (0UL) /*!< ALC (Bit 0) */
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#define CAN_ERRINFO_ALC_Msk (0x1fUL) /*!< ALC (Bitfield-Mask: 0x1f) */
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#define CAN_ERRINFO_KOER_Pos (5UL) /*!< KOER (Bit 5) */
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#define CAN_ERRINFO_KOER_Msk (0xe0UL) /*!< KOER (Bitfield-Mask: 0x07) */
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#define CAN_ERRINFO_SSPOFF_Pos (8UL) /*!< SSPOFF (Bit 8) */
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#define CAN_ERRINFO_SSPOFF_Msk (0x7f00UL) /*!< SSPOFF (Bitfield-Mask: 0x7f) */
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#define CAN_ERRINFO_TDCEN_Pos (15UL) /*!< TDCEN (Bit 15) */
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#define CAN_ERRINFO_TDCEN_Msk (0x8000UL) /*!< TDCEN (Bitfield-Mask: 0x01) */
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#define CAN_ERRINFO_RECNT_Pos (16UL) /*!< RECNT (Bit 16) */
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#define CAN_ERRINFO_RECNT_Msk (0xff0000UL) /*!< RECNT (Bitfield-Mask: 0xff) */
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#define CAN_ERRINFO_TECNT_Pos (24UL) /*!< TECNT (Bit 24) */
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#define CAN_ERRINFO_TECNT_Msk (0xff000000UL) /*!< TECNT (Bitfield-Mask: 0xff) */
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/* ======================================================= ACFCTRL0 ======================================================== */
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#define CAN_ACFCTRL0_ACFADR_Pos (0UL) /*!< ACFADR (Bit 0) */
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#define CAN_ACFCTRL0_ACFADR_Msk (0x3fUL) /*!< ACFADR (Bitfield-Mask: 0x3f) */
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#define CAN_ACFCTRL0_SELMASK_Pos (6UL) /*!< SELMASK (Bit 6) */
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#define CAN_ACFCTRL0_SELMASK_Msk (0x40UL) /*!< SELMASK (Bitfield-Mask: 0x01) */
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#define CAN_ACFCTRL0_TIMEEN_Pos (8UL) /*!< TIMEEN (Bit 8) */
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#define CAN_ACFCTRL0_TIMEEN_Msk (0x100UL) /*!< TIMEEN (Bitfield-Mask: 0x01) */
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#define CAN_ACFCTRL0_TIMEPOS_Pos (9UL) /*!< TIMEPOS (Bit 9) */
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#define CAN_ACFCTRL0_TIMEPOS_Msk (0x200UL) /*!< TIMEPOS (Bitfield-Mask: 0x01) */
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#define CAN_ACFCTRL0_TCEN_Pos (10UL) /*!< TCEN (Bit 10) */
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#define CAN_ACFCTRL0_TCEN_Msk (0x400UL) /*!< TCEN (Bitfield-Mask: 0x01) */
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#define CAN_ACFCTRL0_TCSS_Pos (11UL) /*!< TCSS (Bit 11) */
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#define CAN_ACFCTRL0_TCSS_Msk (0x800UL) /*!< TCSS (Bitfield-Mask: 0x01) */
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#define CAN_ACFCTRL0_ACFEN_Pos (16UL) /*!< ACFEN (Bit 16) */
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#define CAN_ACFCTRL0_ACFEN_Msk (0xffff0000UL) /*!< ACFEN (Bitfield-Mask: 0xffff) */
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/* ======================================================= ACFCTRL1 ======================================================== */
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#define CAN_ACFCTRL1_ACFEN_Pos (0UL) /*!< ACFEN (Bit 0) */
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#define CAN_ACFCTRL1_ACFEN_Msk (0xffffffffUL) /*!< ACFEN (Bitfield-Mask: 0xffffffff) */
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/* ======================================================= ACFCTRL2 ======================================================== */
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#define CAN_ACFCTRL2_ACFEN_Pos (0UL) /*!< ACFEN (Bit 0) */
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#define CAN_ACFCTRL2_ACFEN_Msk (0xfffUL) /*!< ACFEN (Bitfield-Mask: 0xfff) */
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/* ========================================================== ACF ========================================================== */
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#define CAN_ACF_ACODE_Pos (0UL) /*!< ACODE (Bit 0) */
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#define CAN_ACF_ACODE_Msk (0x1fffffffUL) /*!< ACODE (Bitfield-Mask: 0x1fffffff) */
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#define CAN_ACF_AIDE_Pos (29UL) /*!< AIDE (Bit 29) */
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#define CAN_ACF_AIDE_Msk (0x20000000UL) /*!< AIDE (Bitfield-Mask: 0x01) */
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#define CAN_ACF_AIDEE_Pos (30UL) /*!< AIDEE (Bit 30) */
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#define CAN_ACF_AIDEE_Msk (0x40000000UL) /*!< AIDEE (Bitfield-Mask: 0x01) */
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/* ======================================================== VERMEM ========================================================= */
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#define CAN_VERMEM_VERSION_Pos (0UL) /*!< VERSION (Bit 0) */
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#define CAN_VERMEM_VERSION_Msk (0xffffUL) /*!< VERSION (Bitfield-Mask: 0xffff) */
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#define CAN_VERMEM_MEEN_Pos (16UL) /*!< MEEN (Bit 16) */
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#define CAN_VERMEM_MEEN_Msk (0x10000UL) /*!< MEEN (Bitfield-Mask: 0x01) */
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#define CAN_VERMEM_MDWIE_Pos (17UL) /*!< MDWIE (Bit 17) */
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#define CAN_VERMEM_MDWIE_Msk (0x20000UL) /*!< MDWIE (Bitfield-Mask: 0x01) */
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#define CAN_VERMEM_MDWIF_Pos (18UL) /*!< MDWIF (Bit 18) */
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#define CAN_VERMEM_MDWIF_Msk (0x40000UL) /*!< MDWIF (Bitfield-Mask: 0x01) */
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#define CAN_VERMEM_MDEIE_Pos (19UL) /*!< MDEIE (Bit 19) */
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#define CAN_VERMEM_MDEIE_Msk (0x80000UL) /*!< MDEIE (Bitfield-Mask: 0x01) */
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#define CAN_VERMEM_MDEIF_Pos (20UL) /*!< MDEIF (Bit 20) */
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#define CAN_VERMEM_MDEIF_Msk (0x100000UL) /*!< MDEIF (Bitfield-Mask: 0x01) */
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#define CAN_VERMEM_MEID_Pos (23UL) /*!< MEID (Bit 23) */
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#define CAN_VERMEM_MEID_Msk (0x800000UL) /*!< MEID (Bitfield-Mask: 0x01) */
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#define CAN_VERMEM_ACFA_Pos (24UL) /*!< ACFA (Bit 24) */
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#define CAN_VERMEM_ACFA_Msk (0x1000000UL) /*!< ACFA (Bitfield-Mask: 0x01) */
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#define CAN_VERMEM_TXS_Pos (25UL) /*!< TXS (Bit 25) */
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#define CAN_VERMEM_TXS_Msk (0x2000000UL) /*!< TXS (Bitfield-Mask: 0x01) */
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#define CAN_VERMEM_HELOC_Pos (27UL) /*!< HELOC (Bit 27) */
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#define CAN_VERMEM_HELOC_Msk (0x18000000UL) /*!< HELOC (Bitfield-Mask: 0x03) */
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/* ========================================================= MEMES ========================================================= */
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#define CAN_MEMES_MEBP1_Pos (0UL) /*!< MEBP1 (Bit 0) */
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#define CAN_MEMES_MEBP1_Msk (0x3fUL) /*!< MEBP1 (Bitfield-Mask: 0x3f) */
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#define CAN_MEMES_ME1EE_Pos (6UL) /*!< ME1EE (Bit 6) */
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#define CAN_MEMES_ME1EE_Msk (0x40UL) /*!< ME1EE (Bitfield-Mask: 0x01) */
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#define CAN_MEMES_MEBP2_Pos (8UL) /*!< MEBP2 (Bit 8) */
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#define CAN_MEMES_MEBP2_Msk (0x3f00UL) /*!< MEBP2 (Bitfield-Mask: 0x3f) */
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#define CAN_MEMES_ME2EE_Pos (14UL) /*!< ME2EE (Bit 14) */
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#define CAN_MEMES_ME2EE_Msk (0x4000UL) /*!< ME2EE (Bitfield-Mask: 0x01) */
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#define CAN_MEMES_MEEEC_Pos (16UL) /*!< MEEEC (Bit 16) */
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#define CAN_MEMES_MEEEC_Msk (0xf0000UL) /*!< MEEEC (Bitfield-Mask: 0x0f) */
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#define CAN_MEMES_MENEC_Pos (20UL) /*!< MENEC (Bit 20) */
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#define CAN_MEMES_MENEC_Msk (0xf00000UL) /*!< MENEC (Bitfield-Mask: 0x0f) */
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#define CAN_MEMES_MEL_Pos (24UL) /*!< MEL (Bit 24) */
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#define CAN_MEMES_MEL_Msk (0x3000000UL) /*!< MEL (Bitfield-Mask: 0x03) */
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#define CAN_MEMES_MES_Pos (26UL) /*!< MES (Bit 26) */
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#define CAN_MEMES_MES_Msk (0x4000000UL) /*!< MES (Bitfield-Mask: 0x01) */
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/* ========================================================= WAKEUP ======================================================== */
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#define CAN_WAKEUP_LPFEN_Pos (0UL) /*!< LPFEN (Bit 0) */
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#define CAN_WAKEUP_LPFEN_Msk (0x1UL) /*!< LPFEN (Bitfield-Mask: 0x1) */
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#define CAN_WAKEUP_WUEN_Pos (1UL) /*!< WUEN (Bit 1) */
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#define CAN_WAKEUP_WUEN_Msk (0x2UL) /*!< WUEN (Bitfield-Mask: 0x1) */
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/* =========================================================================================================================== */
|
|
/* ================ UART ================ */
|
|
/* =========================================================================================================================== */
|
|
|
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/* ========================================================== RBR ========================================================== */
|
|
#define UART_RBR_RBR_THR_Pos (0UL) /*!< RBR_THR (Bit 0) */
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#define UART_RBR_RBR_THR_Msk (0x1ffUL) /*!< RBR_THR (Bitfield-Mask: 0x1ff) */
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/* ========================================================= DIV_L ========================================================= */
|
|
#define UART_DIV_L_DIV_L_Pos (0UL) /*!< DIV_L (Bit 0) */
|
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#define UART_DIV_L_DIV_L_Msk (0xffUL) /*!< DIV_L (Bitfield-Mask: 0xff) */
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/* ========================================================= DIV_H ========================================================= */
|
|
#define UART_DIV_H_DIV_H_Pos (0UL) /*!< DIV_H (Bit 0) */
|
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#define UART_DIV_H_DIV_H_Msk (0xffUL) /*!< DIV_H (Bitfield-Mask: 0xff) */
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/* ========================================================= LCR0 ========================================================== */
|
|
#define UART_LCR0_WLS1_WLS0_Pos (0UL) /*!< WLS1_WLS0 (Bit 0) */
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#define UART_LCR0_WLS1_WLS0_Msk (0x3UL) /*!< WLS1_WLS0 (Bitfield-Mask: 0x03) */
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#define UART_LCR0_STB_Pos (2UL) /*!< STB (Bit 2) */
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#define UART_LCR0_STB_Msk (0x4UL) /*!< STB (Bitfield-Mask: 0x01) */
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#define UART_LCR0_PEN_Pos (3UL) /*!< PEN (Bit 3) */
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#define UART_LCR0_PEN_Msk (0x8UL) /*!< PEN (Bitfield-Mask: 0x01) */
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#define UART_LCR0_EPS_Pos (4UL) /*!< EPS (Bit 4) */
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#define UART_LCR0_EPS_Msk (0x10UL) /*!< EPS (Bitfield-Mask: 0x01) */
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#define UART_LCR0_SP_Pos (5UL) /*!< SP (Bit 5) */
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#define UART_LCR0_SP_Msk (0x20UL) /*!< SP (Bitfield-Mask: 0x01) */
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#define UART_LCR0_SB_Pos (6UL) /*!< SB (Bit 6) */
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#define UART_LCR0_SB_Msk (0x40UL) /*!< SB (Bitfield-Mask: 0x01) */
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/* ========================================================= LCR1 ========================================================== */
|
|
#define UART_LCR1_RXEN_Pos (0UL) /*!< RXEN (Bit 0) */
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#define UART_LCR1_RXEN_Msk (0x1UL) /*!< RXEN (Bitfield-Mask: 0x01) */
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#define UART_LCR1_TXEN_Pos (1UL) /*!< TXEN (Bit 1) */
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#define UART_LCR1_TXEN_Msk (0x2UL) /*!< TXEN (Bitfield-Mask: 0x01) */
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#define UART_LCR1_RSRC_Pos (2UL) /*!< RSRC (Bit 2) */
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#define UART_LCR1_RSRC_Msk (0x4UL) /*!< RSRC (Bitfield-Mask: 0x01) */
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#define UART_LCR1_TXDIR_Pos (3UL) /*!< TXDIR (Bit 3) */
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#define UART_LCR1_TXDIR_Msk (0x8UL) /*!< TXDIR (Bitfield-Mask: 0x01) */
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#define UART_LCR1_LOOP_Pos (4UL) /*!< LOOP (Bit 4) */
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#define UART_LCR1_LOOP_Msk (0x10UL) /*!< LOOP (Bitfield-Mask: 0x01) */
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#define UART_LCR1_IREN_Pos (5UL) /*!< IREN (Bit 5) */
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#define UART_LCR1_IREN_Msk (0x20UL) /*!< IREN (Bitfield-Mask: 0x01) */
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#define UART_LCR1_INVRX_Pos (6UL) /*!< INVRX (Bit 6) */
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#define UART_LCR1_INVRX_Msk (0x40UL) /*!< INVRX (Bitfield-Mask: 0x01) */
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#define UART_LCR1_INVTX_Pos (7UL) /*!< INVTX (Bit 7) */
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#define UART_LCR1_INVTX_Msk (0x80UL) /*!< INVTX (Bitfield-Mask: 0x01) */
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/* ========================================================== FCR ========================================================== */
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#define UART_FCR_FIFOE_Pos (0UL) /*!< FIFOE (Bit 0) */
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#define UART_FCR_FIFOE_Msk (0x1UL) /*!< FIFOE (Bitfield-Mask: 0x01) */
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/* ========================================================== EFR ========================================================== */
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#define UART_EFR_AUTO_RTS_Pos (6UL) /*!< AUTO_RTS (Bit 6) */
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#define UART_EFR_AUTO_RTS_Msk (0x40UL) /*!< AUTO_RTS (Bitfield-Mask: 0x01) */
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#define UART_EFR_AUTO_CTS_Pos (7UL) /*!< AUTO_CTS (Bit 7) */
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#define UART_EFR_AUTO_CTS_Msk (0x80UL) /*!< AUTO_CTS (Bitfield-Mask: 0x01) */
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/* ========================================================== IER ========================================================== */
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#define UART_IER_ERXNE_Pos (0UL) /*!< ERXNE (Bit 0) */
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#define UART_IER_ERXNE_Msk (0x1UL) /*!< ERXNE (Bitfield-Mask: 0x01) */
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#define UART_IER_ETXNF_Pos (1UL) /*!< ETXNF (Bit 1) */
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#define UART_IER_ETXNF_Msk (0x2UL) /*!< ETXNF (Bitfield-Mask: 0x01) */
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#define UART_IER_ETC_Pos (2UL) /*!< ETC (Bit 2) */
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#define UART_IER_ETC_Msk (0x4UL) /*!< ETC (Bitfield-Mask: 0x01) */
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#define UART_IER_EPE_Pos (3UL) /*!< EPE (Bit 3) */
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#define UART_IER_EPE_Msk (0x8UL) /*!< EPE (Bitfield-Mask: 0x01) */
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#define UART_IER_EFE_Pos (4UL) /*!< EFE (Bit 4) */
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#define UART_IER_EFE_Msk (0x10UL) /*!< EFE (Bitfield-Mask: 0x01) */
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#define UART_IER_ENE_Pos (5UL) /*!< ENE (Bit 5) */
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#define UART_IER_ENE_Msk (0x20UL) /*!< ENE (Bitfield-Mask: 0x01) */
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#define UART_IER_EOEBI_Pos (6UL) /*!< EOEBI (Bit 6) */
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#define UART_IER_EOEBI_Msk (0x40UL) /*!< EOEBI (Bitfield-Mask: 0x01) */
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#define UART_IER_EDCTS_Pos (7UL) /*!< EDCTS (Bit 7) */
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#define UART_IER_EDCTS_Msk (0x80UL) /*!< EDCTS (Bitfield-Mask: 0x01) */
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#define UART_IER_ETXDF_Pos (8UL) /*!< ETXDF (Bit 8) */
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#define UART_IER_ETXDF_Msk (0x100UL) /*!< ETXDF (Bitfield-Mask: 0x01) */
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/* ========================================================= LSR0 ========================================================== */
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#define UART_LSR0_DR_Pos (0UL) /*!< DR (Bit 0) */
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#define UART_LSR0_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */
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#define UART_LSR0_OE_Pos (1UL) /*!< OE (Bit 1) */
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#define UART_LSR0_OE_Msk (0x2UL) /*!< OE (Bitfield-Mask: 0x01) */
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#define UART_LSR0_PE_Pos (2UL) /*!< PE (Bit 2) */
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#define UART_LSR0_PE_Msk (0x4UL) /*!< PE (Bitfield-Mask: 0x01) */
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#define UART_LSR0_FE_Pos (3UL) /*!< FE (Bit 3) */
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#define UART_LSR0_FE_Msk (0x8UL) /*!< FE (Bitfield-Mask: 0x01) */
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#define UART_LSR0_BI_Pos (4UL) /*!< BI (Bit 4) */
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#define UART_LSR0_BI_Msk (0x10UL) /*!< BI (Bitfield-Mask: 0x01) */
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#define UART_LSR0_TXNF_Pos (5UL) /*!< TXNF (Bit 5) */
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#define UART_LSR0_TXNF_Msk (0x20UL) /*!< TXNF (Bitfield-Mask: 0x01) */
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#define UART_LSR0_TC_Pos (6UL) /*!< TC (Bit 6) */
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#define UART_LSR0_TC_Msk (0x40UL) /*!< TC (Bitfield-Mask: 0x01) */
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#define UART_LSR0_NE_Pos (7UL) /*!< NE (Bit 7) */
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#define UART_LSR0_NE_Msk (0x80UL) /*!< NE (Bitfield-Mask: 0x01) */
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#define UART_LSR0_TXDF_Pos (8UL) /*!< TXDF (Bit 8) */
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#define UART_LSR0_TXDF_Msk (0x100UL) /*!< TXDF (Bitfield-Mask: 0x01) */
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/* ========================================================= LSR1 ========================================================== */
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#define UART_LSR1_IDLE_Pos (0UL) /*!< IDLE (Bit 0) */
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#define UART_LSR1_IDLE_Msk (0x1UL) /*!< IDLE (Bitfield-Mask: 0x01) */
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#define UART_LSR1_SYNERR_Pos (1UL) /*!< SYNERR (Bit 1) */
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#define UART_LSR1_SYNERR_Msk (0x2UL) /*!< SYNERR (Bitfield-Mask: 0x01) */
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#define UART_LSR1_FBRK_Pos (2UL) /*!< FBRK (Bit 2) */
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#define UART_LSR1_FBRK_Msk (0x4UL) /*!< FBRK (Bitfield-Mask: 0x01) */
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#define UART_LSR1_DCTS_Pos (3UL) /*!< DCTS (Bit 3) */
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#define UART_LSR1_DCTS_Msk (0x8UL) /*!< DCTS (Bitfield-Mask: 0x01) */
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#define UART_LSR1_LINWAK_Pos (4UL) /*!< LINWAK (Bit 4) */
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#define UART_LSR1_LINWAK_Msk (0x10UL) /*!< LINWAK (Bitfield-Mask: 0x01) */
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#define UART_LSR1_UART_IDLE_Pos (5UL) /*!< UART_IDLE (Bit 5) */
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#define UART_LSR1_UART_IDLE_Msk (0x20UL) /*!< UART_IDLE (Bitfield-Mask: 0x01) */
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#define UART_LSR1_CTS_Pos (6UL) /*!< CTS (Bit 6) */
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#define UART_LSR1_CTS_Msk (0x40UL) /*!< CTS (Bitfield-Mask: 0x01) */
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#define UART_LSR1_RTS_Pos (7UL) /*!< RTS (Bit 7) */
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#define UART_LSR1_RTS_Msk (0x80UL) /*!< RTS (Bitfield-Mask: 0x01) */
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#define UART_LSR1_DTMTCH_Pos (8UL) /*!< DTMTCH (Bit 8) */
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#define UART_LSR1_DTMTCH_Msk (0x100UL) /*!< DTMTCH (Bitfield-Mask: 0x01) */
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#define UART_LSR1_ADDMTCH_Pos (9UL) /*!< ADDMTCH (Bit 9) */
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#define UART_LSR1_ADDMTCH_Msk (0x200UL) /*!< ADDMTCH (Bitfield-Mask: 0x01) */
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/* ======================================================== SMP_CNT ======================================================== */
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#define UART_SMP_CNT_SMP_CNT_Pos (0UL) /*!< SMP_CNT (Bit 0) */
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#define UART_SMP_CNT_SMP_CNT_Msk (0x3UL) /*!< SMP_CNT (Bitfield-Mask: 0x03) */
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/* ========================================================= ADDR ========================================================== */
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#define UART_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
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#define UART_ADDR_ADDR_Msk (0x1ffUL) /*!< ADDR (Bitfield-Mask: 0x1ff) */
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/* ========================================================= DATA ========================================================== */
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#define UART_DATA_DATA_Pos (0UL) /*!< DATA (Bit 0) */
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#define UART_DATA_DATA_Msk (0x1ffUL) /*!< DATA (Bitfield-Mask: 0x1ff) */
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/* ========================================================= GUARD ========================================================= */
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#define UART_GUARD_GUARD_CNT_Pos (0UL) /*!< GUARD_CNT (Bit 0) */
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#define UART_GUARD_GUARD_CNT_Msk (0xfUL) /*!< GUARD_CNT (Bitfield-Mask: 0x0f) */
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#define UART_GUARD_GUARD_EN_Pos (4UL) /*!< GUARD_EN (Bit 4) */
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#define UART_GUARD_GUARD_EN_Msk (0x10UL) /*!< GUARD_EN (Bitfield-Mask: 0x01) */
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/* ======================================================= SLEEP_EN ======================================================== */
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#define UART_SLEEP_EN_SLEEP_EN_Pos (0UL) /*!< SLEEP_EN (Bit 0) */
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#define UART_SLEEP_EN_SLEEP_EN_Msk (0x1UL) /*!< SLEEP_EN (Bitfield-Mask: 0x01) */
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/* ======================================================== DMA_EN ========================================================= */
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#define UART_DMA_EN_RX_DMA_EN_Pos (0UL) /*!< RX_DMA_EN (Bit 0) */
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#define UART_DMA_EN_RX_DMA_EN_Msk (0x1UL) /*!< RX_DMA_EN (Bitfield-Mask: 0x01) */
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#define UART_DMA_EN_TX_DMA_EN_Pos (1UL) /*!< TX_DMA_EN (Bit 1) */
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#define UART_DMA_EN_TX_DMA_EN_Msk (0x2UL) /*!< TX_DMA_EN (Bitfield-Mask: 0x01) */
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/* ======================================================= DIV_FRAC ======================================================== */
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#define UART_DIV_FRAC_DIV_FRAC_Pos (0UL) /*!< DIV_FRAC (Bit 0) */
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#define UART_DIV_FRAC_DIV_FRAC_Msk (0xffUL) /*!< DIV_FRAC (Bitfield-Mask: 0xff) */
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/* ======================================================== MTCHCR ========================================================= */
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#define UART_MTCHCR_DTMTCH_EN_Pos (0UL) /*!< DTMTCH_EN (Bit 0) */
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#define UART_MTCHCR_DTMTCH_EN_Msk (0x1UL) /*!< DTMTCH_EN (Bitfield-Mask: 0x01) */
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#define UART_MTCHCR_ADDMTCH_EN_Pos (1UL) /*!< ADDMTCH_EN (Bit 1) */
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#define UART_MTCHCR_ADDMTCH_EN_Msk (0x2UL) /*!< ADDMTCH_EN (Bitfield-Mask: 0x01) */
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#define UART_MTCHCR_MTCHIE_Pos (2UL) /*!< MTCHIE (Bit 2) */
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#define UART_MTCHCR_MTCHIE_Msk (0x4UL) /*!< MTCHIE (Bitfield-Mask: 0x01) */
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/* ======================================================== RS485CR ======================================================== */
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#define UART_RS485CR_DLYEN_Pos (4UL) /*!< DLYEN (Bit 4) */
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#define UART_RS485CR_DLYEN_Msk (0x10UL) /*!< DLYEN (Bitfield-Mask: 0x01) */
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#define UART_RS485CR_INVPOL_Pos (5UL) /*!< INVPOL (Bit 5) */
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#define UART_RS485CR_INVPOL_Msk (0x20UL) /*!< INVPOL (Bitfield-Mask: 0x01) */
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#define UART_RS485CR_RS485EN_Pos (7UL) /*!< RS485EN (Bit 7) */
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#define UART_RS485CR_RS485EN_Msk (0x80UL) /*!< RS485EN (Bitfield-Mask: 0x01) */
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/* ========================================================= CNTR ========================================================== */
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#define UART_CNTR_CNTR_Pos (0UL) /*!< CNTR (Bit 0) */
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#define UART_CNTR_CNTR_Msk (0xffUL) /*!< CNTR (Bitfield-Mask: 0xff) */
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/* ========================================================= IDLE ========================================================== */
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#define UART_IDLE_IDLEIE_Pos (4UL) /*!< IDLEIE (Bit 4) */
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#define UART_IDLE_IDLEIE_Msk (0x10UL) /*!< IDLEIE (Bitfield-Mask: 0x01) */
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#define UART_IDLE_IDLEEN_Pos (7UL) /*!< IDLEEN (Bit 7) */
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#define UART_IDLE_IDLEEN_Msk (0x80UL) /*!< IDLEEN (Bitfield-Mask: 0x01) */
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/* ========================================================= LINCR ========================================================= */
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#define UART_LINCR_LINSLP_Pos (0UL) /*!< LINSLP Bit 0) */
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#define UART_LINCR_LINSLP_Msk (0x1UL) /*!< LINSLP (Bitfield-Mask: 0x01) */
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#define UART_LINCR_LINWAKIE_Pos (1UL) /*!< LINWAKIE (Bit 1) */
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#define UART_LINCR_LINWAKIE_Msk (0x2UL) /*!< LINWAKIE (Bitfield-Mask: 0x01) */
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#define UART_LINCR_SYNERRIE_Pos (2UL) /*!< SYNERRIE (Bit 2) */
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#define UART_LINCR_SYNERRIE_Msk (0x4UL) /*!< SYNERRIE (Bitfield-Mask: 0x01) */
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#define UART_LINCR_LABAUDEN_Pos (3UL) /*!< LABAUDEN (Bit 3) */
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#define UART_LINCR_LABAUDEN_Msk (0x8UL) /*!< LABAUDEN (Bitfield-Mask: 0x01) */
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#define UART_LINCR_SDBRK_Pos (4UL) /*!< SDBRK (Bit 4) */
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#define UART_LINCR_SDBRK_Msk (0x10UL) /*!< SDBRK (Bitfield-Mask: 0x01) */
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#define UART_LINCR_LBRKDL_Pos (5UL) /*!< LBRKDL (Bit 5) */
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#define UART_LINCR_LBRKDL_Msk (0x20UL) /*!< LBRKDL (Bitfield-Mask: 0x01) */
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#define UART_LINCR_LBRKIE_Pos (6UL) /*!< LBRKIE (Bit 6) */
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#define UART_LINCR_LBRKIE_Msk (0x40UL) /*!< LBRKIE (Bitfield-Mask: 0x01) */
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#define UART_LINCR_LINEN_Pos (7UL) /*!< LINEN (Bit 7) */
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#define UART_LINCR_LINEN_Msk (0x80UL) /*!< LINEN (Bitfield-Mask: 0x01) */
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/* ======================================================== BRKLGH ========================================================= */
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#define UART_BRKLGH_BRKLGH_Pos (0UL) /*!< BRKLGH (Bit 0) */
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#define UART_BRKLGH_BRKLGH_Msk (0xfUL) /*!< BRKLGH (Bitfield-Mask: 0x0f) */
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/* ========================================================= PMIN0 ========================================================= */
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#define UART_PMIN0_PMIN0_Pos (0UL) /*!< PMIN0 (Bit 0) */
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#define UART_PMIN0_PMIN0_Msk (0xffUL) /*!< PMIN0 (Bitfield-Mask: 0xff) */
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/* ========================================================= PMIN1 ========================================================= */
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#define UART_PMIN1_PMIN1_Pos (0UL) /*!< PMIN1 (Bit 0) */
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#define UART_PMIN1_PMIN1_Msk (0xffUL) /*!< PMIN1 (Bitfield-Mask: 0xff) */
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/* =========================================================================================================================== */
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/* ================ I2C ================ */
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/* =========================================================================================================================== */
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/* ========================================================= ADDR0 ========================================================= */
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#define I2C_ADDR0_AD_Pos (1UL) /*!< AD (Bit 1) */
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#define I2C_ADDR0_AD_Msk (0xfeUL) /*!< AD (Bitfield-Mask: 0x7f) */
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/* ========================================================= ADDR1 ========================================================= */
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#define I2C_ADDR1_AD_Pos (0UL) /*!< AD (Bit 0) */
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#define I2C_ADDR1_AD_Msk (0x7UL) /*!< AD (Bitfield-Mask: 0x07) */
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#define I2C_ADDR1_RAD_Pos (4UL) /*!< RAD (Bit 4) */
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#define I2C_ADDR1_RAD_Msk (0x7f0UL) /*!< RAD (Bitfield-Mask: 0x7f) */
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#define I2C_ADDR1_RMEN_Pos (12UL) /*!< RMEN (Bit 12) */
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#define I2C_ADDR1_RMEN_Msk (0x1000UL) /*!< RMEN (Bitfield-Mask: 0x01) */
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/* ====================================================== SAMPLE_CNT ======================================================= */
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#define I2C_SAMPLE_CNT_DIV_Pos (0UL) /*!< DIV (Bit 0) */
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#define I2C_SAMPLE_CNT_DIV_Msk (0xffUL) /*!< DIV (Bitfield-Mask: 0xff) */
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/* ======================================================= STEP_CNT ======================================================== */
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#define I2C_STEP_CNT_DIV_Pos (0UL) /*!< DIV (Bit 0) */
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#define I2C_STEP_CNT_DIV_Msk (0xffUL) /*!< DIV (Bitfield-Mask: 0xff) */
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/* ========================================================= CTRL0 ========================================================= */
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#define I2C_CTRL0_SRST_Pos (0UL) /*!< SRST (Bit 0) */
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#define I2C_CTRL0_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */
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#define I2C_CTRL0_DBGEN_Pos (1UL) /*!< DBGEN (Bit 1) */
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#define I2C_CTRL0_DBGEN_Msk (0x2UL) /*!< DBGEN (Bitfield-Mask: 0x01) */
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#define I2C_CTRL0_WUEN_Pos (2UL) /*!< WUEN (Bit 2) */
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#define I2C_CTRL0_WUEN_Msk (0x4UL) /*!< WUEN (Bitfield-Mask: 0x01) */
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#define I2C_CTRL0_TACK_Pos (3UL) /*!< TACK (Bit 3) */
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#define I2C_CTRL0_TACK_Msk (0x8UL) /*!< TACK (Bitfield-Mask: 0x01) */
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#define I2C_CTRL0_TX_Pos (4UL) /*!< TX (Bit 4) */
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#define I2C_CTRL0_TX_Msk (0x10UL) /*!< TX (Bitfield-Mask: 0x01) */
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#define I2C_CTRL0_MSTR_Pos (5UL) /*!< MSTR (Bit 5) */
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#define I2C_CTRL0_MSTR_Msk (0x20UL) /*!< MSTR (Bitfield-Mask: 0x01) */
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#define I2C_CTRL0_IICIE_Pos (6UL) /*!< IICIE (Bit 6) */
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#define I2C_CTRL0_IICIE_Msk (0x40UL) /*!< IICIE (Bitfield-Mask: 0x01) */
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#define I2C_CTRL0_IICEN_Pos (7UL) /*!< IICEN (Bit 7) */
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#define I2C_CTRL0_IICEN_Msk (0x80UL) /*!< IICEN (Bitfield-Mask: 0x01) */
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/* ========================================================= CTRL1 ========================================================= */
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#define I2C_CTRL1_STREN_Pos (0UL) /*!< STREN (Bit 0) */
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#define I2C_CTRL1_STREN_Msk (0x1UL) /*!< STREN (Bitfield-Mask: 0x01) */
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#define I2C_CTRL1_SAEN_Pos (1UL) /*!< SAEN (Bit 1) */
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#define I2C_CTRL1_SAEN_Msk (0x2UL) /*!< SAEN (Bitfield-Mask: 0x01) */
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#define I2C_CTRL1_ARBEN_Pos (3UL) /*!< ARBEN (Bit 3) */
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#define I2C_CTRL1_ARBEN_Msk (0x8UL) /*!< ARBEN (Bitfield-Mask: 0x01) */
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#define I2C_CTRL1_SYNCEN_Pos (4UL) /*!< SYNCEN (Bit 4) */
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#define I2C_CTRL1_SYNCEN_Msk (0x10UL) /*!< SYNCEN (Bitfield-Mask: 0x01) */
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#define I2C_CTRL1_ADEXT_Pos (6UL) /*!< ADEXT (Bit 6) */
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#define I2C_CTRL1_ADEXT_Msk (0x40UL) /*!< ADEXT (Bitfield-Mask: 0x01) */
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#define I2C_CTRL1_GCAEN_Pos (7UL) /*!< GCAEN (Bit 7) */
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#define I2C_CTRL1_GCAEN_Msk (0x80UL) /*!< GCAEN (Bitfield-Mask: 0x01) */
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/* ========================================================= CTRL2 ========================================================= */
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#define I2C_CTRL2_MNTEN_Pos (0UL) /*!< MNTEN (Bit 0) */
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#define I2C_CTRL2_MNTEN_Msk (0x1UL) /*!< MNTEN (Bitfield-Mask: 0x01) */
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#define I2C_CTRL2_NACKIE_Pos (1UL) /*!< NACKIE (Bit 1) */
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#define I2C_CTRL2_NACKIE_Msk (0x2UL) /*!< NACKIE (Bitfield-Mask: 0x01) */
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#define I2C_CTRL2_PLTIE_Pos (2UL) /*!< PLTIE (Bit 2) */
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#define I2C_CTRL2_PLTIE_Msk (0x4UL) /*!< PLTIE (Bitfield-Mask: 0x01) */
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#define I2C_CTRL2_BND_DMA_IE_Pos (3UL) /*!< BND_DMA_IE (Bit 3) */
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#define I2C_CTRL2_BND_DMA_IE_Msk (0x8UL) /*!< BND_DMA_IE (Bitfield-Mask: 0x01) */
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#define I2C_CTRL2_TXEIE_Pos (4UL) /*!< TXEIE (Bit 4) */
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#define I2C_CTRL2_TXEIE_Msk (0x10UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
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#define I2C_CTRL2_RXFIE_Pos (5UL) /*!< RXFIE (Bit 5) */
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#define I2C_CTRL2_RXFIE_Msk (0x20UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
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#define I2C_CTRL2_TXUFIE_Pos (6UL) /*!< TXUFIE (Bit 6) */
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#define I2C_CTRL2_TXUFIE_Msk (0x40UL) /*!< TXUFIE (Bitfield-Mask: 0x01) */
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#define I2C_CTRL2_RXOFIE_Pos (7UL) /*!< RXOFIE (Bit 7) */
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#define I2C_CTRL2_RXOFIE_Msk (0x80UL) /*!< RXOFIE (Bitfield-Mask: 0x01) */
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/* ========================================================= CTRL3 ========================================================= */
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#define I2C_CTRL3_DMATXEN_Pos (0UL) /*!< DMATXEN (Bit 0) */
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#define I2C_CTRL3_DMATXEN_Msk (0x1UL) /*!< DMATXEN (Bitfield-Mask: 0x01) */
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#define I2C_CTRL3_DMARXEN_Pos (1UL) /*!< DMARXEN (Bit 1) */
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#define I2C_CTRL3_DMARXEN_Msk (0x2UL) /*!< DMARXEN (Bitfield-Mask: 0x01) */
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#define I2C_CTRL3_TIMECFG_Pos (2UL) /*!< TIMECFG (Bit 2) */
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#define I2C_CTRL3_TIMECFG_Msk (0x4UL) /*!< TIMECFG (Bitfield-Mask: 0x01) */
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#define I2C_CTRL3_PINLOW_Pos (3UL) /*!< PINLOW (Bit 3) */
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#define I2C_CTRL3_PINLOW_Msk (0xfff8UL) /*!< PINLOW (Bitfield-Mask: 0x1fff) */
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/* ======================================================== STATUS0 ======================================================== */
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#define I2C_STATUS0_RACK_Pos (0UL) /*!< RACK (Bit 0) */
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#define I2C_STATUS0_RACK_Msk (0x1UL) /*!< RACK (Bitfield-Mask: 0x01) */
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#define I2C_STATUS0_A10MF_Pos (1UL) /*!< A10MF (Bit 1) */
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#define I2C_STATUS0_A10MF_Msk (0x2UL) /*!< A10MF (Bitfield-Mask: 0x01) */
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#define I2C_STATUS0_SRW_Pos (2UL) /*!< SRW (Bit 2) */
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#define I2C_STATUS0_SRW_Msk (0x4UL) /*!< SRW (Bitfield-Mask: 0x01) */
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#define I2C_STATUS0_READY_Pos (3UL) /*!< READY (Bit 3) */
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#define I2C_STATUS0_READY_Msk (0x8UL) /*!< READY (Bitfield-Mask: 0x01) */
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#define I2C_STATUS0_ARBLOST_Pos (4UL) /*!< ARBLOST (Bit 4) */
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#define I2C_STATUS0_ARBLOST_Msk (0x10UL) /*!< ARBLOST (Bitfield-Mask: 0x01) */
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#define I2C_STATUS0_BUSY_Pos (5UL) /*!< BUSY (Bit 5) */
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#define I2C_STATUS0_BUSY_Msk (0x20UL) /*!< BUSY (Bitfield-Mask: 0x01) */
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#define I2C_STATUS0_SAMF_Pos (6UL) /*!< SAMF (Bit 6) */
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#define I2C_STATUS0_SAMF_Msk (0x40UL) /*!< SAMF (Bitfield-Mask: 0x01) */
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#define I2C_STATUS0_BND_Pos (7UL) /*!< BND (Bit 7) */
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#define I2C_STATUS0_BND_Msk (0x80UL) /*!< BND (Bitfield-Mask: 0x01) */
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/* ======================================================== STATUS1 ======================================================== */
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#define I2C_STATUS1_TXEF_Pos (0UL) /*!< TXEF (Bit 0) */
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#define I2C_STATUS1_TXEF_Msk (0x1UL) /*!< TXEF (Bitfield-Mask: 0x01) */
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#define I2C_STATUS1_RXFF_Pos (1UL) /*!< RXFF (Bit 1) */
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#define I2C_STATUS1_RXFF_Msk (0x2UL) /*!< RXFF (Bitfield-Mask: 0x01) */
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#define I2C_STATUS1_TXUF_Pos (2UL) /*!< TXUF (Bit 2) */
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#define I2C_STATUS1_TXUF_Msk (0x4UL) /*!< TXUF (Bitfield-Mask: 0x01) */
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#define I2C_STATUS1_RXOF_Pos (3UL) /*!< RXOF (Bit 3) */
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#define I2C_STATUS1_RXOF_Msk (0x8UL) /*!< RXOF (Bitfield-Mask: 0x01) */
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#define I2C_STATUS1_GCMF_Pos (4UL) /*!< GCMF (Bit 4) */
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#define I2C_STATUS1_GCMF_Msk (0x10UL) /*!< GCMF (Bitfield-Mask: 0x01) */
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#define I2C_STATUS1_PLTF_Pos (5UL) /*!< PLTF (Bit 5) */
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#define I2C_STATUS1_PLTF_Msk (0x20UL) /*!< PLTF (Bitfield-Mask: 0x01) */
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#define I2C_STATUS1_SARF_Pos (6UL) /*!< SARF (Bit 6) */
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#define I2C_STATUS1_SARF_Msk (0x40UL) /*!< SARF (Bitfield-Mask: 0x01) */
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/* ======================================================== DGLCFG ========================================================= */
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#define I2C_DGLCFG_DGL_CNT_Pos (0UL) /*!< DGL_CNT (Bit 0) */
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#define I2C_DGLCFG_DGL_CNT_Msk (0xfUL) /*!< DGL_CNT (Bitfield-Mask: 0x0f) */
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#define I2C_DGLCFG_STARTF_Pos (4UL) /*!< STARTF (Bit 4) */
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#define I2C_DGLCFG_STARTF_Msk (0x10UL) /*!< STARTF (Bitfield-Mask: 0x01) */
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#define I2C_DGLCFG_SSIE_Pos (5UL) /*!< SSIE (Bit 5) */
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#define I2C_DGLCFG_SSIE_Msk (0x20UL) /*!< SSIE (Bitfield-Mask: 0x01) */
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#define I2C_DGLCFG_STOPF_Pos (6UL) /*!< STOPF (Bit 6) */
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#define I2C_DGLCFG_STOPF_Msk (0x40UL) /*!< STOPF (Bitfield-Mask: 0x01) */
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#define I2C_DGLCFG_DGLEN_Pos (7UL) /*!< DGLEN (Bit 7) */
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#define I2C_DGLCFG_DGLEN_Msk (0x80UL) /*!< DGLEN (Bitfield-Mask: 0x01) */
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/* ========================================================= DATA ========================================================== */
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#define I2C_DATA_DATA_Pos (0UL) /*!< DATA (Bit 0) */
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#define I2C_DATA_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */
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#define I2C_DATA_MAK_Pos (8UL) /*!< MAK (Bit 8) */
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#define I2C_DATA_MAK_Msk (0x100UL) /*!< MAK (Bitfield-Mask: 0x01) */
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/* ======================================================= STARTSTOP ======================================================= */
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#define I2C_STARTSTOP_START_Pos (0UL) /*!< START (Bit 0) */
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#define I2C_STARTSTOP_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
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#define I2C_STARTSTOP_STOP_Pos (1UL) /*!< STOP (Bit 1) */
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#define I2C_STARTSTOP_STOP_Msk (0x2UL) /*!< STOP (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ SPI ================ */
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/* =========================================================================================================================== */
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/* ========================================================= CFG0 ========================================================== */
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#define SPI_CFG0_SCK_HIGH_Pos (0UL) /*!< SCK_HIGH (Bit 0) */
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#define SPI_CFG0_SCK_HIGH_Msk (0xffUL) /*!< SCK_HIGH (Bitfield-Mask: 0xff) */
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#define SPI_CFG0_SCK_LOW_Pos (8UL) /*!< SCK_LOW (Bit 8) */
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#define SPI_CFG0_SCK_LOW_Msk (0xff00UL) /*!< SCK_LOW (Bitfield-Mask: 0xff) */
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#define SPI_CFG0_CS_HOLD_Pos (16UL) /*!< CS_HOLD (Bit 16) */
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#define SPI_CFG0_CS_HOLD_Msk (0xff0000UL) /*!< CS_HOLD (Bitfield-Mask: 0xff) */
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#define SPI_CFG0_CS_SETUP_Pos (24UL) /*!< CS_SETUP (Bit 24) */
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#define SPI_CFG0_CS_SETUP_Msk (0xff000000UL) /*!< CS_SETUP (Bitfield-Mask: 0xff) */
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/* ========================================================= CFG1 ========================================================== */
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#define SPI_CFG1_CS_IDLE_Pos (0UL) /*!< CS_IDLE (Bit 0) */
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#define SPI_CFG1_CS_IDLE_Msk (0xffUL) /*!< CS_IDLE (Bitfield-Mask: 0xff) */
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#define SPI_CFG1_TXEIE_Pos (8UL) /*!< TXEIE (Bit 8) */
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#define SPI_CFG1_TXEIE_Msk (0x100UL) /*!< TXEIE (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_RXFIE_Pos (9UL) /*!< RXFIE (Bit 9) */
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#define SPI_CFG1_RXFIE_Msk (0x200UL) /*!< RXFIE (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_TXUIE_Pos (10UL) /*!< TXUIE (Bit 10) */
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#define SPI_CFG1_TXUIE_Msk (0x400UL) /*!< TXUIE (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_RXOIE_Pos (11UL) /*!< RXOIE (Bit 11) */
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#define SPI_CFG1_RXOIE_Msk (0x800UL) /*!< RXOIE (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_MSTR_Pos (12UL) /*!< MSTR (Bit 12) */
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#define SPI_CFG1_MSTR_Msk (0x1000UL) /*!< MSTR (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_MODFIE_Pos (13UL) /*!< MODFIE (Bit 13) */
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#define SPI_CFG1_MODFIE_Msk (0x2000UL) /*!< MODFIE (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_DMATXEN_Pos (14UL) /*!< DMATXEN (Bit 14) */
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#define SPI_CFG1_DMATXEN_Msk (0x4000UL) /*!< DMATXEN (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_DMARXEN_Pos (15UL) /*!< DMARXEN (Bit 15) */
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#define SPI_CFG1_DMARXEN_Msk (0x8000UL) /*!< DMARXEN (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_CPOL_Pos (16UL) /*!< CPOL (Bit 16) */
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#define SPI_CFG1_CPOL_Msk (0x10000UL) /*!< CPOL (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_CPHA_Pos (17UL) /*!< CPHA (Bit 17) */
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#define SPI_CFG1_CPHA_Msk (0x20000UL) /*!< CPHA (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_MSBF_Pos (18UL) /*!< MSBF (Bit 18) */
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#define SPI_CFG1_MSBF_Msk (0x40000UL) /*!< MSBF (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_RMSBF_Pos (19UL) /*!< RMSBF (Bit 19) */
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#define SPI_CFG1_RMSBF_Msk (0x80000UL) /*!< RMSBF (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_FRMSIZE_Pos (20UL) /*!< FRMSIZE (Bit 20) */
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#define SPI_CFG1_FRMSIZE_Msk (0x1f00000UL) /*!< FRMSIZE (Bitfield-Mask: 0x1f) */
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#define SPI_CFG1_CSOE_Pos (25UL) /*!< CSOE (Bit 25) */
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#define SPI_CFG1_CSOE_Msk (0x2000000UL) /*!< CSOE (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_MODFEN_Pos (26UL) /*!< MODFEN (Bit 26) */
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#define SPI_CFG1_MODFEN_Msk (0x4000000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_PINCFG_Pos (27UL) /*!< PINCFG (Bit 27) */
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#define SPI_CFG1_PINCFG_Msk (0x8000000UL) /*!< PINCFG (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_CONT_CS_Pos (28UL) /*!< CONT_CS (Bit 28) */
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#define SPI_CFG1_CONT_CS_Msk (0x10000000UL) /*!< CONT_CS (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_WKUEN_Pos (30UL) /*!< WKUEN (Bit 30) */
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#define SPI_CFG1_WKUEN_Msk (0x40000000UL) /*!< WKUEN (Bitfield-Mask: 0x01) */
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#define SPI_CFG1_DMIE_Pos (31UL) /*!< DMIE (Bit 31) */
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#define SPI_CFG1_DMIE_Msk (0x80000000UL) /*!< DMIE (Bitfield-Mask: 0x01) */
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/* ========================================================== CMD ========================================================== */
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#define SPI_CMD_SPIEN_Pos (0UL) /*!< SPIEN (Bit 0) */
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#define SPI_CMD_SPIEN_Msk (0x1UL) /*!< SPIEN (Bitfield-Mask: 0x01) */
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#define SPI_CMD_SWRST_Pos (4UL) /*!< SWRST (Bit 4) */
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#define SPI_CMD_SWRST_Msk (0x10UL) /*!< SWRST (Bitfield-Mask: 0x01) */
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#define SPI_CMD_CSRLS_Pos (5UL) /*!< CSRLS (Bit 5) */
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#define SPI_CMD_CSRLS_Msk (0x20UL) /*!< CSRLS (Bitfield-Mask: 0x01) */
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#define SPI_CMD_ROTRIG_Pos (6UL) /*!< ROTRIG (Bit 6) */
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#define SPI_CMD_ROTRIG_Msk (0x40UL) /*!< ROTRIG (Bitfield-Mask: 0x01) */
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/* ======================================================== STATUS ========================================================= */
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#define SPI_STATUS_TXEF_Pos (0UL) /*!< TXEF (Bit 0) */
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#define SPI_STATUS_TXEF_Msk (0x1UL) /*!< TXEF (Bitfield-Mask: 0x01) */
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#define SPI_STATUS_RXFF_Pos (1UL) /*!< RXFF (Bit 1) */
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#define SPI_STATUS_RXFF_Msk (0x2UL) /*!< RXFF (Bitfield-Mask: 0x01) */
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#define SPI_STATUS_TXUF_Pos (2UL) /*!< TXUF (Bit 2) */
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#define SPI_STATUS_TXUF_Msk (0x4UL) /*!< TXUF (Bitfield-Mask: 0x01) */
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#define SPI_STATUS_RXOF_Pos (3UL) /*!< RXOF (Bit 3) */
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#define SPI_STATUS_RXOF_Msk (0x8UL) /*!< RXOF (Bitfield-Mask: 0x01) */
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#define SPI_STATUS_MODEF_Pos (4UL) /*!< MODEF (Bit 4) */
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#define SPI_STATUS_MODEF_Msk (0x10UL) /*!< MODEF (Bitfield-Mask: 0x01) */
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#define SPI_STATUS_RDMF_Pos (5UL) /*!< RDMF (Bit 5) */
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#define SPI_STATUS_RDMF_Msk (0x20UL) /*!< RDMF (Bitfield-Mask: 0x01) */
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#define SPI_STATUS_MEBY_Pos (7UL) /*!< MEBY (Bit 7) */
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#define SPI_STATUS_MEBY_Msk (0x80UL) /*!< MEBY (Bitfield-Mask: 0x01) */
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#define SPI_STATUS_IDLEF_Pos (8UL) /*!< IDLEF (Bit 8) */
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#define SPI_STATUS_IDLEF_Msk (0x100UL) /*!< IDLEF (Bitfield-Mask: 0x01) */
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/* ========================================================= DATA ========================================================== */
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#define SPI_DATA_DATA_Pos (0UL) /*!< DATA (Bit 0) */
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#define SPI_DATA_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= CFG2 ========================================================== */
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#define SPI_CFG2_MNOV_Pos (1UL) /*!< MNOV (Bit 1) */
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#define SPI_CFG2_MNOV_Msk (0x2UL) /*!< MNOV (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_TOEN_Pos (2UL) /*!< TOEN (Bit 2) */
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#define SPI_CFG2_TOEN_Msk (0x4UL) /*!< TOEN (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_ROEN_Pos (3UL) /*!< ROEN (Bit 3) */
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#define SPI_CFG2_ROEN_Msk (0x8UL) /*!< ROEN (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_WIDTH_Pos (4UL) /*!< WIDTH (Bit 4) */
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#define SPI_CFG2_WIDTH_Msk (0x30UL) /*!< WIDTH (Bitfield-Mask: 0x03) */
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#define SPI_CFG2_HRPOL_Pos (6UL) /*!< HRPOL (Bit 6) */
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#define SPI_CFG2_HRPOL_Msk (0x40UL) /*!< HRPOL (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_HREN_Pos (7UL) /*!< HREN (Bit 7) */
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#define SPI_CFG2_HREN_Msk (0x80UL) /*!< HREN (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_PCSCFG_Pos (8UL) /*!< PCSCFG (Bit 8) */
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#define SPI_CFG2_PCSCFG_Msk (0x300UL) /*!< PCSCFG (Bitfield-Mask: 0x03) */
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#define SPI_CFG2_PCS0POL_Pos (10UL) /*!< PCS0POL (Bit 10) */
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#define SPI_CFG2_PCS0POL_Msk (0x400UL) /*!< PCS0POL (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_PCS1POL_Pos (11UL) /*!< PCS1POL (Bit 11) */
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#define SPI_CFG2_PCS1POL_Msk (0x800UL) /*!< PCS1POL (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_PCS2POL_Pos (12UL) /*!< PCS2POL (Bit 12) */
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#define SPI_CFG2_PCS2POL_Msk (0x1000UL) /*!< PCS2POL (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_PCS3POL_Pos (13UL) /*!< PCS3POL (Bit 13) */
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#define SPI_CFG2_PCS3POL_Msk (0x2000UL) /*!< PCS3POL (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_DBGEN_Pos (16UL) /*!< DBGEN (Bit 16) */
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#define SPI_CFG2_DBGEN_Msk (0x10000UL) /*!< DBGEN (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_CS0DETEN_Pos (20UL) /*!< CS0DETEN (Bit 20) */
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#define SPI_CFG2_CS0DETEN_Msk (0x100000UL) /*!< CS0DETEN (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_CS1DETEN_Pos (21UL) /*!< CS1DETEN (Bit 21) */
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#define SPI_CFG2_CS1DETEN_Msk (0x200000UL) /*!< CS1DETEN (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_CS2DETEN_Pos (22UL) /*!< CS2DETEN (Bit 22) */
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#define SPI_CFG2_CS2DETEN_Msk (0x400000UL) /*!< CS2DETEN (Bitfield-Mask: 0x01) */
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#define SPI_CFG2_CS3DETEN_Pos (23UL) /*!< CS3DETEN (Bit 23) */
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#define SPI_CFG2_CS3DETEN_Msk (0x800000UL) /*!< CS3DETEN (Bitfield-Mask: 0x01) */
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/* ========================================================== DMV ========================================================== */
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#define SPI_DMV_DMV_Pos (0UL) /*!< DMV (Bit 0) */
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#define SPI_DMV_DMV_Msk (0xffffffffUL) /*!< DMV (Bitfield-Mask: 0xffffffff) */
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/* =========================================================================================================================== */
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/* ================ ANA ================ */
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/* =========================================================================================================================== */
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/* ====================================================== ACMPDAC_CFG ====================================================== */
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#define ANA_ACMPDAC_CFG_RG_MCU_ACMPDAC_LP_EN_Pos (16UL) /*!< RG_MCU_ACMPDAC_LP_EN (Bit 16) */
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#define ANA_ACMPDAC_CFG_RG_MCU_ACMPDAC_LP_EN_Msk (0x10000UL) /*!< RG_MCU_ACMPDAC_LP_EN (Bitfield-Mask: 0x01) */
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/* ====================================================== AUXADC_CFG0 ====================================================== */
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#define ANA_AUXADC_CFG0_RG_ADC0_CHANNEL_SEL_Pos (4UL) /*!< RG_ADC0_CHANNEL_SEL (Bit 4) */
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#define ANA_AUXADC_CFG0_RG_ADC0_CHANNEL_SEL_Msk (0x3f0UL) /*!< RG_ADC0_CHANNEL_SEL (Bitfield-Mask: 0x3f) */
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#define ANA_AUXADC_CFG0_RG_ADC0_EN_Pos (14UL) /*!< RG_ADC0_EN (Bit 14) */
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#define ANA_AUXADC_CFG0_RG_ADC0_EN_Msk (0x4000UL) /*!< RG_ADC0_EN (Bitfield-Mask: 0x01) */
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#define ANA_AUXADC_CFG0_RG_ADC0_RGMODE_EN_Pos (19UL) /*!< RG_ADC0_RGMODE_EN (Bit 19) */
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#define ANA_AUXADC_CFG0_RG_ADC0_RGMODE_EN_Msk (0x80000UL) /*!< RG_ADC0_RGMODE_EN (Bitfield-Mask: 0x01) */
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#define ANA_AUXADC_CFG0_RG_ADC0_VREFGEN_EN_Pos (20UL) /*!< RG_ADC0_VREFGEN_EN (Bit 20) */
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#define ANA_AUXADC_CFG0_RG_ADC0_VREFGEN_EN_Msk (0x100000UL) /*!< RG_ADC0_VREFGEN_EN (Bitfield-Mask: 0x01) */
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#define ANA_AUXADC_CFG0_RG_ADC0_LDO_EN_Pos (21UL) /*!< RG_ADC0_LDO_EN (Bit 21) */
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#define ANA_AUXADC_CFG0_RG_ADC0_LDO_EN_Msk (0x200000UL) /*!< RG_ADC0_LDO_EN (Bitfield-Mask: 0x01) */
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/* ====================================================== AUXADC_CFG1 ====================================================== */
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#define ANA_AUXADC_CFG1_RG_ADC0_GEOECAL_VIN_SEL_Pos (5UL) /*!< RG_ADC0_GEOECAL_VIN_SEL (Bit 5) */
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#define ANA_AUXADC_CFG1_RG_ADC0_GEOECAL_VIN_SEL_Msk (0xe0UL) /*!< RG_ADC0_GEOECAL_VIN_SEL (Bitfield-Mask: 0x07) */
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#define ANA_AUXADC_CFG1_RG_ADC0_GEOECAL_VIN_EN_Pos (8UL) /*!< RG_ADC0_GEOECAL_VIN_EN (Bit 8) */
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#define ANA_AUXADC_CFG1_RG_ADC0_GEOECAL_VIN_EN_Msk (0x100UL) /*!< RG_ADC0_GEOECAL_VIN_EN (Bitfield-Mask: 0x01) */
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/* ====================================================== AUXADC_CFG4 ====================================================== */
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#define ANA_AUXADC_CFG4_RG_ADC1_CHANNEL_SEL_Pos (14UL) /*!< RG_ADC1_CHANNEL_SEL (Bit 14) */
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#define ANA_AUXADC_CFG4_RG_ADC1_CHANNEL_SEL_Msk (0xfc000UL) /*!< RG_ADC1_CHANNEL_SEL (Bitfield-Mask: 0x3f) */
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#define ANA_AUXADC_CFG4_RG_ADC1_EN_Pos (24UL) /*!< RG_ADC1_EN (Bit 24) */
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#define ANA_AUXADC_CFG4_RG_ADC1_EN_Msk (0x1000000UL) /*!< RG_ADC1_EN (Bitfield-Mask: 0x01) */
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#define ANA_AUXADC_CFG4_RG_ADC1_RGMODE_EN_Pos (29UL) /*!< RG_ADC1_RGMODE_EN (Bit 29) */
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#define ANA_AUXADC_CFG4_RG_ADC1_RGMODE_EN_Msk (0x20000000UL) /*!< RG_ADC1_RGMODE_EN (Bitfield-Mask: 0x01) */
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#define ANA_AUXADC_CFG4_RG_ADC1_VREFGEN_EN_Pos (30UL) /*!< RG_ADC1_VREFGEN_EN (Bit 30) */
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#define ANA_AUXADC_CFG4_RG_ADC1_VREFGEN_EN_Msk (0x40000000UL) /*!< RG_ADC1_VREFGEN_EN (Bitfield-Mask: 0x01) */
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#define ANA_AUXADC_CFG4_RG_ADC1_LDO_EN_Pos (31UL) /*!< RG_ADC1_LDO_EN (Bit 31) */
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#define ANA_AUXADC_CFG4_RG_ADC1_LDO_EN_Msk (0x80000000UL) /*!< RG_ADC1_LDO_EN (Bitfield-Mask: 0x01) */
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/* ====================================================== AUXADC_CFG5 ====================================================== */
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#define ANA_AUXADC_CFG5_RG_ADC1_GEOECAL_VIN_SEL_Pos (5UL) /*!< RG_ADC1_GEOECAL_VIN_SEL (Bit 5) */
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#define ANA_AUXADC_CFG5_RG_ADC1_GEOECAL_VIN_SEL_Msk (0xe0UL) /*!< RG_ADC1_GEOECAL_VIN_SEL (Bitfield-Mask: 0x07) */
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#define ANA_AUXADC_CFG5_RG_ADC1_GEOECAL_VIN_EN_Pos (8UL) /*!< RG_ADC1_GEOECAL_VIN_EN (Bit 8) */
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#define ANA_AUXADC_CFG5_RG_ADC1_GEOECAL_VIN_EN_Msk (0x100UL) /*!< RG_ADC1_GEOECAL_VIN_EN (Bitfield-Mask: 0x01) */
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/* ======================================================= SPLL_CFG0 ======================================================= */
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#define ANA_SPLL_CFG0_FBKDIV_Pos (15UL) /*!< FBKDIV (Bit 15) */
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#define ANA_SPLL_CFG0_FBKDIV_Msk (0x7f8000UL) /*!< FBKDIV (Bitfield-Mask: 0xff) */
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#define ANA_SPLL_CFG0_POSDIV_Pos (25UL) /*!< POSDIV (Bit 25) */
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#define ANA_SPLL_CFG0_POSDIV_Msk (0x3e000000UL) /*!< POSDIV (Bitfield-Mask: 0x1f) */
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#define ANA_SPLL_CFG0_PREDIV_Pos (30UL) /*!< PREDIV (Bit 30) */
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#define ANA_SPLL_CFG0_PREDIV_Msk (0xc0000000UL) /*!< PREDIV (Bitfield-Mask: 0x03) */
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/* ======================================================= SPLL_CFG1 ======================================================= */
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#define ANA_SPLL_CFG1_LD_DLY_SEL_Pos (1UL) /*!< LD_DLY_SEL (Bit 1) */
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#define ANA_SPLL_CFG1_LD_DLY_SEL_Msk (0xeUL) /*!< LD_DLY_SEL (Bitfield-Mask: 0x07) */
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#define ANA_SPLL_CFG1_LD_SAMP1_EN_Pos (6UL) /*!< LD_SAMP1_EN (Bit 6) */
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#define ANA_SPLL_CFG1_LD_SAMP1_EN_Msk (0x40UL) /*!< LD_SAMP1_EN (Bitfield-Mask: 0x01) */
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#define ANA_SPLL_CFG1_LD_SAMP0_EN_Pos (7UL) /*!< LD_SAMP0_EN (Bit 7) */
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#define ANA_SPLL_CFG1_LD_SAMP0_EN_Msk (0x80UL) /*!< LD_SAMP0_EN (Bitfield-Mask: 0x01) */
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#define ANA_SPLL_CFG1_LD_EN_Pos (8UL) /*!< LD_EN (Bit 8) */
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#define ANA_SPLL_CFG1_LD_EN_Msk (0x100UL) /*!< LD_EN (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* =============== ADC ================= */
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/* =========================================================================================================================== */
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/* ========================================================= STR =========================================================== */
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#define ADC_STR_AMO_Pos (0UL) /*!< AMO (Bit 0) */
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#define ADC_STR_AMO_Msk (0x1UL) /*!< AMO (Bitfield-Mask: 0x01) */
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#define ADC_STR_IDLE_Pos (4UL) /*!< IDLE (Bit 4) */
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#define ADC_STR_IDLE_Msk (0x10UL) /*!< IDLE (Bitfield-Mask: 0x01) */
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#define ADC_STR_NAMO_Pos (5UL) /*!< NAMO (Bit 5) */
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#define ADC_STR_NAMO_Msk (0x20UL) /*!< NAMO (Bitfield-Mask: 0x01) */
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#define ADC_STR_AAMO_Pos (6UL) /*!< AAMO (Bit 6) */
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#define ADC_STR_AAMO_Msk (0x40UL) /*!< AAMO (Bitfield-Mask: 0x01) */
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#define ADC_STR_COVCFT_Pos (9UL) /*!< COVCFT (Bit 9) */
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#define ADC_STR_COVCFT_Msk (0x200UL) /*!< COVCFT (Bitfield-Mask: 0x01) */
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/* ========================================================= CTRL0 ========================================================= */
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#define ADC_CTRL0_AMOCH_Pos (0UL) /*!< AMOCH (Bit 0) */
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#define ADC_CTRL0_AMOCH_Msk (0x3fUL) /*!< AMOCH (Bitfield-Mask: 0x3f) */
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#define ADC_CTRL0_AMOSGL_Pos (6UL) /*!< AMOSGL (Bit 6) */
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#define ADC_CTRL0_AMOSGL_Msk (0x40UL) /*!< AMOSGL (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_IAMOEN_Pos (7UL) /*!< IAMOEN (Bit 7) */
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#define ADC_CTRL0_IAMOEN_Msk (0x80UL) /*!< IAMOEN (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_AMOEN_Pos (8UL) /*!< AMOEN (Bit 8) */
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#define ADC_CTRL0_AMOEN_Msk (0x100UL) /*!< AMOEN (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_DISCNUM_Pos (9UL) /*!< DISCNUM (Bit 9) */
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#define ADC_CTRL0_DISCNUM_Msk (0xe00UL) /*!< DISCNUM (Bitfield-Mask: 0x07) */
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#define ADC_CTRL0_IAUTO_Pos (12UL) /*!< IAUTO (Bit 12) */
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#define ADC_CTRL0_IAUTO_Msk (0x1000UL) /*!< IAUTO (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_IDISCEN_Pos (13UL) /*!< IDISCEN (Bit 13) */
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#define ADC_CTRL0_IDISCEN_Msk (0x2000UL) /*!< IDISCEN (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_DISCEN_Pos (14UL) /*!< DISCEN (Bit 14) */
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#define ADC_CTRL0_DISCEN_Msk (0x4000UL) /*!< DISCEN (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_CONT_Pos (15UL) /*!< CONT (Bit 15) */
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#define ADC_CTRL0_CONT_Msk (0x8000UL) /*!< CONT (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_SCAN_Pos (16UL) /*!< SCAN (Bit 16) */
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#define ADC_CTRL0_SCAN_Msk (0x10000UL) /*!< SCAN (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_AMOIE_Pos (19UL) /*!< AMOIE (Bit 19) */
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#define ADC_CTRL0_AMOIE_Msk (0x80000UL) /*!< AMOIE (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_DMAEN_Pos (20UL) /*!< DMAEN (Bit 20) */
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#define ADC_CTRL0_DMAEN_Msk (0x100000UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_EXTTRIG_Pos (21UL) /*!< EXTTRIG (Bit 21) */
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#define ADC_CTRL0_EXTTRIG_Msk (0x200000UL) /*!< EXTTRIG (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_IEXTTRIG_Pos (22UL) /*!< IEXTTRIG (Bit 22) */
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#define ADC_CTRL0_IEXTTRIG_Msk (0x400000UL) /*!< IEXTTRIG (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_ALIGN_Pos (23UL) /*!< ALIGN (Bit 23) */
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#define ADC_CTRL0_ALIGN_Msk (0x800000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_AMOMODE_Pos (24UL) /*!< AMOMODE (Bit 24) */
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#define ADC_CTRL0_AMOMODE_Msk (0x1000000UL) /*!< AMOMODE (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_INTERVAL_Pos (25UL) /*!< INTERVAL (Bit 25) */
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#define ADC_CTRL0_INTERVAL_Msk (0x2000000UL) /*!< INTERVAL (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_ISWSTART_Pos (30UL) /*!< ISWSTART (Bit 30) */
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#define ADC_CTRL0_ISWSTART_Msk (0x40000000UL) /*!< ISWSTART (Bitfield-Mask: 0x01) */
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#define ADC_CTRL0_SWSTART_Pos (31UL) /*!< SWSTART (Bit 31) */
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#define ADC_CTRL0_SWSTART_Msk (0x80000000UL) /*!< SWSTART (Bitfield-Mask: 0x01) */
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/* ========================================================= CTRL1 ========================================================= */
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#define ADC_CTRL1_ADON_Pos (0UL) /*!< ADON (Bit 0) */
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#define ADC_CTRL1_ADON_Msk (0x1UL) /*!< ADON (Bitfield-Mask: 0x01) */
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#define ADC_CTRL1_CALEN_Pos (1UL) /*!< CALEN (Bit 1) */
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#define ADC_CTRL1_CALEN_Msk (0x2UL) /*!< CALEN (Bitfield-Mask: 0x01) */
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#define ADC_CTRL1_AVGS_Pos (8UL) /*!< AVGS (Bit 8) */
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#define ADC_CTRL1_AVGS_Msk (0x300UL) /*!< AVGS (Bitfield-Mask: 0x03) */
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#define ADC_CTRL1_AVGE_Pos (10UL) /*!< AVGE (Bit 10) */
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#define ADC_CTRL1_AVGE_Msk (0x400UL) /*!< AVGE (Bitfield-Mask: 0x01) */
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#define ADC_CTRL1_PSC_Pos (12UL) /*!< PSC (Bit 12) */
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#define ADC_CTRL1_PSC_Msk (0xf000UL) /*!< PSC (Bitfield-Mask: 0x0f) */
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#define ADC_CTRL1_RESL_Pos (16UL) /*!< RESL (Bit 16) */
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#define ADC_CTRL1_RESL_Msk (0x30000UL) /*!< RESL (Bitfield-Mask: 0x03) */
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/* ========================================================= IOFR ========================================================== */
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#define ADC_IOFR_IOFR_Pos (0UL) /*!< IOFR (Bit 0) */
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#define ADC_IOFR_IOFR_Msk (0xfffUL) /*!< IOFR (Bitfield-Mask: 0xfff) */
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/* ========================================================= AMOHR ========================================================= */
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#define ADC_AMOHR_AMOHT_Pos (0UL) /*!< AMOHT (Bit 0) */
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#define ADC_AMOHR_AMOHT_Msk (0xfffUL) /*!< AMOHT (Bitfield-Mask: 0xfff) */
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#define ADC_AMOHR_AMOHO_Pos (16UL) /*!< AMOHO (Bit 16) */
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#define ADC_AMOHR_AMOHO_Msk (0xfff0000UL) /*!< AMOHO (Bitfield-Mask: 0xfff) */
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/* ========================================================= AMOLR ========================================================= */
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#define ADC_AMOLR_AMOLT_Pos (0UL) /*!< AMOLT (Bit 0) */
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#define ADC_AMOLR_AMOLT_Msk (0xfffUL) /*!< AMOLT (Bitfield-Mask: 0xfff) */
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#define ADC_AMOLR_AMOLO_Pos (16UL) /*!< AMOLO (Bit 16) */
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#define ADC_AMOLR_AMOLO_Msk (0xfff0000UL) /*!< AMOLO (Bitfield-Mask: 0xfff) */
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/* ========================================================= SPT ========================================================== */
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#define ADC_SPT_Msk (0x7UL) /*!< SPT (Bitfield-Mask: 0x07) */
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#define ADC_SPT_Width (3UL) /*!< SPT width (3bit) */
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/* ========================================================= SQR ========================================================= */
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#define ADC_SQR_SEQ_Pos (0UL) /*!< SEQ (Bit 0) */
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#define ADC_SQR_SEQ_Msk (0x3fUL) /*!< SEQ (Bitfield-Mask: 0x3f) */
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#define ADC_SQR_IE_Pos (6UL) /*!< IE (Bit 6) */
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#define ADC_SQR_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
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#define ADC_SQR_EOC_Pos (7UL) /*!< EOC (Bit 7) */
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#define ADC_SQR_EOC_Msk (0x80UL) /*!< EOC (Bitfield-Mask: 0x01) */
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/* ========================================================== SQL ========================================================== */
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#define ADC_SQL_RSQL_Pos (0UL) /*!< RSQL (Bit 0) */
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#define ADC_SQL_RSQL_Msk (0x3fUL) /*!< RSQL (Bitfield-Mask: 0x3f) */
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#define ADC_SQL_ISQL_Pos (8UL) /*!< ISQL (Bit 8) */
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#define ADC_SQL_ISQL_Msk (0x300UL) /*!< ISQL (Bitfield-Mask: 0x03) */
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#define ADC_SQL_SUPPLY_Pos (16UL) /*!< SUPPLY (Bit 16) */
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#define ADC_SQL_SUPPLY_Msk (0x70000UL) /*!< SUPPLY (Bitfield-Mask: 0x07) */
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#define ADC_SQL_REFSEL_Pos (24UL) /*!< REFSEL (Bit 24) */
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#define ADC_SQL_REFSEL_Msk (0x3000000UL) /*!< REFSEL (Bitfield-Mask: 0x03) */
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/* ========================================================= CALI0 ========================================================= */
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#define ADC_CALI0_GE0_Pos (0UL) /*!< GE0 (Bit 0) */
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#define ADC_CALI0_GE0_Msk (0x1fffUL) /*!< GE0 (Bitfield-Mask: 0x1fff) */
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#define ADC_CALI0_GE1_Pos (16UL) /*!< GE1 (Bit 16) */
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#define ADC_CALI0_GE1_Msk (0x1fff0000UL) /*!< GE1 (Bitfield-Mask: 0x1fff) */
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/* ========================================================= CALI1 ========================================================= */
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#define ADC_CALI1_OE0_Pos (0UL) /*!< OE0 (Bit 0) */
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#define ADC_CALI1_OE0_Msk (0x7ffUL) /*!< OE0 (Bitfield-Mask: 0x7ff) */
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#define ADC_CALI1_OE1_Pos (16UL) /*!< OE1 (Bit 16) */
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#define ADC_CALI1_OE1_Msk (0x7ff0000UL) /*!< OE1 (Bitfield-Mask: 0x7ff) */
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/* ======================================================== RDR/IDR ======================================================== */
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#define ADC_DR_DATA_Pos (0UL) /*!< DR (Bit 0) */
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#define ADC_DR_DATA_Msk (0xffffUL) /*!< DR (Bitfield-Mask: 0xfff) */
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#define ADC_DR_CH_Pos (16UL) /*!< CH (Bit 16) */
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#define ADC_DR_CH_Msk (0x3f0000UL) /*!< CH (Bitfield-Mask: 0x3f) */
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#define ADC_DR_EVEN_PARITY_Pos (22UL) /*!< EVEN_PARITY (Bit 22) */
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#define ADC_DR_EVEN_PARITY_Msk (0x400000UL) /*!< EVEN_PARITY (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ ACMP ================ */
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/* =========================================================================================================================== */
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/* ========================================================== CR0 ========================================================== */
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#define ACMP_CR0_MOD_Pos (0UL) /*!< MOD (Bit 0) */
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#define ACMP_CR0_MOD_Msk (0x3UL) /*!< MOD (Bitfield-Mask: 0x03) */
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#define ACMP_CR0_OPE_Pos (2UL) /*!< OPE (Bit 2) */
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#define ACMP_CR0_OPE_Msk (0x4UL) /*!< OPE (Bitfield-Mask: 0x01) */
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#define ACMP_CR0_OUTEN_Pos (3UL) /*!< OUTEN (Bit 3) */
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#define ACMP_CR0_OUTEN_Msk (0x8UL) /*!< OUTEN (Bitfield-Mask: 0x01) */
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#define ACMP_CR0_IE_Pos (4UL) /*!< IE (Bit 4) */
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#define ACMP_CR0_IE_Msk (0x10UL) /*!< IE (Bitfield-Mask: 0x01) */
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#define ACMP_CR0_HYSTVOL_Pos (6UL) /*!< HYSTVOL (Bit 6) */
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#define ACMP_CR0_HYSTVOL_Msk (0xc0UL) /*!< HYSTVOL (Bitfield-Mask: 0x03) */
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#define ACMP_CR0_HYSTMOD_Pos (8UL) /*!< HYSTMOD (Bit 8) */
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#define ACMP_CR0_HYSTMOD_Msk (0x100UL) /*!< HYSTMOD (Bitfield-Mask: 0x01) */
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#define ACMP_CR0_EN_Pos (9UL) /*!< EN (Bit 9) */
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#define ACMP_CR0_EN_Msk (0x200UL) /*!< EN (Bitfield-Mask: 0x01) */
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#define ACMP_CR0_LPF_Pos (10UL) /*!< LPF (Bit 10) */
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#define ACMP_CR0_LPF_Msk (0xc00UL) /*!< LPF (Bitfield-Mask: 0x03) */
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#define ACMP_CR0_LSICLK_EN_Pos (12UL) /*!< LSICLK_EN (Bit 12) */
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#define ACMP_CR0_LSICLK_EN_Msk (0x1000UL) /*!< LSICLK_EN (Bitfield-Mask: 0x01) */
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#define ACMP_CR0_FILTEN_Pos (16UL) /*!< FILTEN (Bit 16) */
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#define ACMP_CR0_FILTEN_Msk (0x10000UL) /*!< FILTEN (Bitfield-Mask: 0x01) */
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#define ACMP_CR0_WINEN_Pos (17UL) /*!< WINEN (Bit 17) */
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#define ACMP_CR0_WINEN_Msk (0x20000UL) /*!< WINEN (Bitfield-Mask: 0x01) */
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#define ACMP_CR0_INVT_Pos (18UL) /*!< INVT (Bit 18) */
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#define ACMP_CR0_INVT_Msk (0x40000UL) /*!< INVT (Bitfield-Mask: 0x01) */
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#define ACMP_CR0_FILTER_CNT_Pos (19UL) /*!< FILTER_CNT (Bit 19) */
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#define ACMP_CR0_FILTER_CNT_Msk (0x7f80000UL) /*!< FILTER_CNT (Bitfield-Mask: 0xff) */
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#define ACMP_CR0_COS_Pos (27UL) /*!< COS (Bit 27) */
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#define ACMP_CR0_COS_Msk (0x8000000UL) /*!< COS (Bitfield-Mask: 0x01) */
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/* ========================================================== CR1 ========================================================== */
|
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#define ACMP_CR1_NSEL_Pos (0UL) /*!< NSEL (Bit 0) */
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#define ACMP_CR1_NSEL_Msk (0xfUL) /*!< NSEL (Bitfield-Mask: 0x0f) */
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#define ACMP_CR1_PSEL_Pos (4UL) /*!< PSEL (Bit 4) */
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#define ACMP_CR1_PSEL_Msk (0xf0UL) /*!< PSEL (Bitfield-Mask: 0x0f) */
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/* ========================================================== CR2 ========================================================== */
|
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#define ACMP_CR2_DACVAL_Pos (0UL) /*!< DACVAL (Bit 0) */
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#define ACMP_CR2_DACVAL_Msk (0xffUL) /*!< DACVAL (Bitfield-Mask: 0xff) */
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#define ACMP_CR2_DACEN_Pos (8UL) /*!< DACEN (Bit 8) */
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#define ACMP_CR2_DACEN_Msk (0x100UL) /*!< DACEN (Bitfield-Mask: 0x01) */
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#define ACMP_CR2_DACREF_Pos (9UL) /*!< DACREF (Bit 9) */
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#define ACMP_CR2_DACREF_Msk (0x200UL) /*!< DACREF (Bitfield-Mask: 0x01) */
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/* ========================================================== CR3 ========================================================== */
|
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#define ACMP_CR3_NSPLEN_Pos (3UL) /*!< NSPLEN (Bit 3) */
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#define ACMP_CR3_NSPLEN_Msk (0x8UL) /*!< NSPLEN (Bitfield-Mask: 0x01) */
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#define ACMP_CR3_PSPLEN_Pos (7UL) /*!< PSPLEN (Bit 7) */
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#define ACMP_CR3_PSPLEN_Msk (0x80UL) /*!< PSPLEN (Bitfield-Mask: 0x01) */
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/* ========================================================== CR4 ========================================================== */
|
|
#define ACMP_CR4_PLSEQ_Pos (0UL) /*!< PLSEQ (Bit 0) */
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#define ACMP_CR4_PLSEQ_Msk (0x1ffUL) /*!< PLSEQ (Bitfield-Mask: 0x1ff) */
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/* ========================================================== DR =========================================================== */
|
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#define ACMP_DR_O0_Pos (0UL) /*!< O0 (Bit 0) */
|
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#define ACMP_DR_O0_Msk (0x1UL) /*!< O0 (Bitfield-Mask: 0x01) */
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#define ACMP_DR_O1_Pos (1UL) /*!< O1 (Bit 1) */
|
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#define ACMP_DR_O1_Msk (0x2UL) /*!< O1 (Bitfield-Mask: 0x01) */
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#define ACMP_DR_O2_Pos (2UL) /*!< O2 (Bit 2) */
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#define ACMP_DR_O2_Msk (0x4UL) /*!< O2 (Bitfield-Mask: 0x01) */
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#define ACMP_DR_O3_Pos (3UL) /*!< O3 (Bit 3) */
|
|
#define ACMP_DR_O3_Msk (0x8UL) /*!< O3 (Bitfield-Mask: 0x01) */
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#define ACMP_DR_O4_Pos (4UL) /*!< O4 (Bit 4) */
|
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#define ACMP_DR_O4_Msk (0x10UL) /*!< O4 (Bitfield-Mask: 0x01) */
|
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#define ACMP_DR_O5_Pos (5UL) /*!< O5 (Bit 5) */
|
|
#define ACMP_DR_O5_Msk (0x20UL) /*!< O5 (Bitfield-Mask: 0x01) */
|
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#define ACMP_DR_O6_Pos (6UL) /*!< O6 (Bit 6) */
|
|
#define ACMP_DR_O6_Msk (0x40UL) /*!< O6 (Bitfield-Mask: 0x01) */
|
|
#define ACMP_DR_O7_Pos (7UL) /*!< O7 (Bit 7) */
|
|
#define ACMP_DR_O7_Msk (0x80UL) /*!< O7 (Bitfield-Mask: 0x01) */
|
|
#define ACMP_DR_O8_Pos (8UL) /*!< O8 (Bit 8) */
|
|
#define ACMP_DR_O8_Msk (0x100UL) /*!< O8 (Bitfield-Mask: 0x01) */
|
|
#define ACMP_DR_O_Pos (9UL) /*!< O (Bit 9) */
|
|
#define ACMP_DR_O_Msk (0x200UL) /*!< O (Bitfield-Mask: 0x01) */
|
|
#define ACMP_DR_POLLING_O_Msk (0x1ffUL) /*!< POLLING O (Bitfield-Mask: 0x1ff) */
|
|
/* ========================================================== SR =========================================================== */
|
|
#define ACMP_SR_F0_Pos (0UL) /*!< F0 (Bit 0) */
|
|
#define ACMP_SR_F0_Msk (0x1UL) /*!< F0 (Bitfield-Mask: 0x01) */
|
|
#define ACMP_SR_F1_Pos (1UL) /*!< F1 (Bit 1) */
|
|
#define ACMP_SR_F1_Msk (0x2UL) /*!< F1 (Bitfield-Mask: 0x01) */
|
|
#define ACMP_SR_F2_Pos (2UL) /*!< F2 (Bit 2) */
|
|
#define ACMP_SR_F2_Msk (0x4UL) /*!< F2 (Bitfield-Mask: 0x01) */
|
|
#define ACMP_SR_F3_Pos (3UL) /*!< F3 (Bit 3) */
|
|
#define ACMP_SR_F3_Msk (0x8UL) /*!< F3 (Bitfield-Mask: 0x01) */
|
|
#define ACMP_SR_F4_Pos (4UL) /*!< F4 (Bit 4) */
|
|
#define ACMP_SR_F4_Msk (0x10UL) /*!< F4 (Bitfield-Mask: 0x01) */
|
|
#define ACMP_SR_F5_Pos (5UL) /*!< F5 (Bit 5) */
|
|
#define ACMP_SR_F5_Msk (0x20UL) /*!< F5 (Bitfield-Mask: 0x01) */
|
|
#define ACMP_SR_F6_Pos (6UL) /*!< F6 (Bit 6) */
|
|
#define ACMP_SR_F6_Msk (0x40UL) /*!< F6 (Bitfield-Mask: 0x01) */
|
|
#define ACMP_SR_F7_Pos (7UL) /*!< F7 (Bit 7) */
|
|
#define ACMP_SR_F7_Msk (0x80UL) /*!< F7 (Bitfield-Mask: 0x01) */
|
|
#define ACMP_SR_F8_Pos (8UL) /*!< F8 (Bit 8) */
|
|
#define ACMP_SR_F8_Msk (0x100UL) /*!< F8 (Bitfield-Mask: 0x01) */
|
|
#define ACMP_SR_F_Pos (9UL) /*!< F (Bit 9) */
|
|
#define ACMP_SR_F_Msk (0x200UL) /*!< F (Bitfield-Mask: 0x01) */
|
|
#define ACMP_SR_POLLING_F_Msk (0x1FFUL) /*!< POLLING STATUS (Bitfield-Mask: 0x1ff) */
|
|
/* ========================================================== FD =========================================================== */
|
|
#define ACMP_FD_PLFD_Pos (0UL) /*!< PLFD (Bit 0) */
|
|
#define ACMP_FD_PLFD_Msk (0x3UL) /*!< PLFD (Bitfield-Mask: 0x03) */
|
|
/* ========================================================== OPA ========================================================== */
|
|
#define ACMP_OPA_OPASEL_Pos (0UL) /*!< OPASEL (Bit 0) */
|
|
#define ACMP_OPA_OPASEL_Msk (0x7UL) /*!< OPASEL (Bitfield-Mask: 0x07) */
|
|
/* ========================================================== OPB ========================================================== */
|
|
#define ACMP_OPB_OPBSEL_Pos (0UL) /*!< OPBSEL (Bit 0) */
|
|
#define ACMP_OPB_OPBSEL_Msk (0x7UL) /*!< OPBSEL (Bitfield-Mask: 0x07) */
|
|
/* ========================================================== OPC ========================================================== */
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#define ACMP_OPC_OPCSEL_Pos (0UL) /*!< OPCSEL (Bit 0) */
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#define ACMP_OPC_OPCSEL_Msk (0x7UL) /*!< OPCSEL (Bitfield-Mask: 0x07) */
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/* ========================================================== CLK ========================================================== */
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#define ACMP_CLK_PSC_Pos (0UL) /*!< PSC (Bit 0) */
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#define ACMP_CLK_PSC_Msk (0x7UL) /*!< PSC (Bitfield-Mask: 0x07) */
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/* =========================================================================================================================== */
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/* =============== PWM ================= */
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/* =========================================================================================================================== */
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/* ========================================================= INIT ========================================================== */
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#define PWM_INIT_COFE_Pos (0UL) /*!< COFE (Bit 0) */
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#define PWM_INIT_COFE_Msk (0x1UL) /*!< COFE (Bitfield-Mask: 0x01) */
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#define PWM_INIT_CUVE_Pos (1UL) /*!< CUVE (Bit 1) */
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#define PWM_INIT_CUVE_Msk (0x2UL) /*!< CUVE (Bitfield-Mask: 0x01) */
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#define PWM_INIT_OFDIR_Pos (2UL) /*!< OFDIR (Bit 2) */
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#define PWM_INIT_OFDIR_Msk (0x4UL) /*!< OFDIR (Bitfield-Mask: 0x01) */
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#define PWM_INIT_CLKSRC_Pos (3UL) /*!< CLKSRC (Bit 3) */
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#define PWM_INIT_CLKSRC_Msk (0x18UL) /*!< CLKSRC (Bitfield-Mask: 0x03) */
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#define PWM_INIT_CNTMODE_Pos (5UL) /*!< CNTMODE (Bit 5) */
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#define PWM_INIT_CNTMODE_Msk (0x20UL) /*!< CNTMODE (Bitfield-Mask: 0x01) */
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#define PWM_INIT_CNTOIE_Pos (6UL) /*!< CNTOIE (Bit 6) */
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#define PWM_INIT_CNTOIE_Msk (0x40UL) /*!< CNTOIE (Bitfield-Mask: 0x01) */
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#define PWM_INIT_CNTOF_Pos (7UL) /*!< CNTOF (Bit 7) */
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#define PWM_INIT_CNTOF_Msk (0x80UL) /*!< CNTOF (Bitfield-Mask: 0x01) */
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#define PWM_INIT_CLKPSC_Pos (8UL) /*!< CLKPSC (Bit 8) */
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#define PWM_INIT_CLKPSC_Msk (0xffff00UL) /*!< CLKPSC (Bitfield-Mask: 0xffff) */
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#define PWM_INIT_OFUFDMAEN_Pos (28UL) /*!< OFUFDMAEN (Bit 28) */
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#define PWM_INIT_OFUFDMAEN_Msk (0x10000000UL) /*!< OFUFDMAEN (Bitfield-Mask: 0x01) */
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/* ========================================================== CNT ========================================================== */
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#define PWM_CNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */
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#define PWM_CNT_COUNT_Msk (0xffffUL) /*!< COUNT (Bitfield-Mask: 0xffff) */
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/* ========================================================= MCVR ========================================================== */
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#define PWM_MCVR_MCVR_Pos (0UL) /*!< MCVR (Bit 0) */
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#define PWM_MCVR_MCVR_Msk (0xffffUL) /*!< MCVR (Bitfield-Mask: 0xffff) */
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/* ======================================================== CH0SCR ========================================================= */
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#define PWM_CH0SCR_CHRSTEN_Pos (0UL) /*!< CHRSTEN (Bit 0) */
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#define PWM_CH0SCR_CHRSTEN_Msk (0x1UL) /*!< CHRSTEN (Bitfield-Mask: 0x01) */
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#define PWM_CH0SCR_DIR_Pos (1UL) /*!< DIR (Bit 1) */
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#define PWM_CH0SCR_DIR_Msk (0x2UL) /*!< DIR (Bitfield-Mask: 0x01) */
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#define PWM_CH0SCR_ELSR0_Pos (2UL) /*!< ELSR0 (Bit 2) */
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#define PWM_CH0SCR_ELSR0_Msk (0x4UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH0SCR_ELSR1_Pos (3UL) /*!< ELSR1 (Bit 3) */
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#define PWM_CH0SCR_ELSR1_Msk (0x8UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH0SCR_MSR0_Pos (4UL) /*!< MSR0 (Bit 4) */
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#define PWM_CH0SCR_MSR0_Msk (0x10UL) /*!< MSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH0SCR_MSR1_Pos (5UL) /*!< MSR1 (Bit 5) */
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#define PWM_CH0SCR_MSR1_Msk (0x20UL) /*!< MSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH0SCR_CHIE_Pos (6UL) /*!< CHIE (Bit 6) */
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#define PWM_CH0SCR_CHIE_Msk (0x40UL) /*!< CHIE (Bitfield-Mask: 0x01) */
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#define PWM_CH0SCR_CHIF_Pos (7UL) /*!< CHIF (Bit 7) */
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#define PWM_CH0SCR_CHIF_Msk (0x80UL) /*!< CHIF (Bitfield-Mask: 0x01) */
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#define PWM_CH0SCR_DMAEN_Pos (8UL) /*!< DMAEN (Bit 8) */
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#define PWM_CH0SCR_DMAEN_Msk (0x100UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
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/* ======================================================== CH1SCR ========================================================= */
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#define PWM_CH1SCR_CHRSTEN_Pos (0UL) /*!< CHRSTEN (Bit 0) */
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#define PWM_CH1SCR_CHRSTEN_Msk (0x1UL) /*!< CHRSTEN (Bitfield-Mask: 0x01) */
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#define PWM_CH1SCR_DIR_Pos (1UL) /*!< DIR (Bit 1) */
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#define PWM_CH1SCR_DIR_Msk (0x2UL) /*!< DIR (Bitfield-Mask: 0x01) */
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#define PWM_CH1SCR_ELSR0_Pos (2UL) /*!< ELSR0 (Bit 2) */
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#define PWM_CH1SCR_ELSR0_Msk (0x4UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH1SCR_ELSR1_Pos (3UL) /*!< ELSR1 (Bit 3) */
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#define PWM_CH1SCR_ELSR1_Msk (0x8UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH1SCR_MSR0_Pos (4UL) /*!< MSR0 (Bit 4) */
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#define PWM_CH1SCR_MSR0_Msk (0x10UL) /*!< MSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH1SCR_MSR1_Pos (5UL) /*!< MSR1 (Bit 5) */
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#define PWM_CH1SCR_MSR1_Msk (0x20UL) /*!< MSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH1SCR_CHIE_Pos (6UL) /*!< CHIE (Bit 6) */
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#define PWM_CH1SCR_CHIE_Msk (0x40UL) /*!< CHIE (Bitfield-Mask: 0x01) */
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#define PWM_CH1SCR_CHIF_Pos (7UL) /*!< CHIF (Bit 7) */
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#define PWM_CH1SCR_CHIF_Msk (0x80UL) /*!< CHIF (Bitfield-Mask: 0x01) */
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#define PWM_CH1SCR_DMAEN_Pos (8UL) /*!< DMAEN (Bit 8) */
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#define PWM_CH1SCR_DMAEN_Msk (0x100UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
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/* ======================================================== CH2SCR ========================================================= */
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#define PWM_CH2SCR_CHRSTEN_Pos (0UL) /*!< CHRSTEN (Bit 0) */
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#define PWM_CH2SCR_CHRSTEN_Msk (0x1UL) /*!< CHRSTEN (Bitfield-Mask: 0x01) */
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#define PWM_CH2SCR_DIR_Pos (1UL) /*!< DIR (Bit 1) */
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#define PWM_CH2SCR_DIR_Msk (0x2UL) /*!< DIR (Bitfield-Mask: 0x01) */
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#define PWM_CH2SCR_ELSR0_Pos (2UL) /*!< ELSR0 (Bit 2) */
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#define PWM_CH2SCR_ELSR0_Msk (0x4UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH2SCR_ELSR1_Pos (3UL) /*!< ELSR1 (Bit 3) */
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#define PWM_CH2SCR_ELSR1_Msk (0x8UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH2SCR_MSR0_Pos (4UL) /*!< MSR0 (Bit 4) */
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#define PWM_CH2SCR_MSR0_Msk (0x10UL) /*!< MSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH2SCR_MSR1_Pos (5UL) /*!< MSR1 (Bit 5) */
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#define PWM_CH2SCR_MSR1_Msk (0x20UL) /*!< MSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH2SCR_CHIE_Pos (6UL) /*!< CHIE (Bit 6) */
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#define PWM_CH2SCR_CHIE_Msk (0x40UL) /*!< CHIE (Bitfield-Mask: 0x01) */
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#define PWM_CH2SCR_CHIF_Pos (7UL) /*!< CHIF (Bit 7) */
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#define PWM_CH2SCR_CHIF_Msk (0x80UL) /*!< CHIF (Bitfield-Mask: 0x01) */
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#define PWM_CH2SCR_DMAEN_Pos (8UL) /*!< DMAEN (Bit 8) */
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#define PWM_CH2SCR_DMAEN_Msk (0x100UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
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/* ======================================================== CH3SCR ========================================================= */
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#define PWM_CH3SCR_CHRSTEN_Pos (0UL) /*!< CHRSTEN (Bit 0) */
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#define PWM_CH3SCR_CHRSTEN_Msk (0x1UL) /*!< CHRSTEN (Bitfield-Mask: 0x01) */
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#define PWM_CH3SCR_DIR_Pos (1UL) /*!< DIR (Bit 1) */
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#define PWM_CH3SCR_DIR_Msk (0x2UL) /*!< DIR (Bitfield-Mask: 0x01) */
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#define PWM_CH3SCR_ELSR0_Pos (2UL) /*!< ELSR0 (Bit 2) */
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#define PWM_CH3SCR_ELSR0_Msk (0x4UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH3SCR_ELSR1_Pos (3UL) /*!< ELSR1 (Bit 3) */
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#define PWM_CH3SCR_ELSR1_Msk (0x8UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH3SCR_MSR0_Pos (4UL) /*!< MSR0 (Bit 4) */
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#define PWM_CH3SCR_MSR0_Msk (0x10UL) /*!< MSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH3SCR_MSR1_Pos (5UL) /*!< MSR1 (Bit 5) */
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#define PWM_CH3SCR_MSR1_Msk (0x20UL) /*!< MSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH3SCR_CHIE_Pos (6UL) /*!< CHIE (Bit 6) */
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#define PWM_CH3SCR_CHIE_Msk (0x40UL) /*!< CHIE (Bitfield-Mask: 0x01) */
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#define PWM_CH3SCR_CHIF_Pos (7UL) /*!< CHIF (Bit 7) */
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#define PWM_CH3SCR_CHIF_Msk (0x80UL) /*!< CHIF (Bitfield-Mask: 0x01) */
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#define PWM_CH3SCR_DMAEN_Pos (8UL) /*!< DMAEN (Bit 8) */
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#define PWM_CH3SCR_DMAEN_Msk (0x100UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
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/* ======================================================== CH4SCR ========================================================= */
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#define PWM_CH4SCR_CHRSTEN_Pos (0UL) /*!< CHRSTEN (Bit 0) */
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#define PWM_CH4SCR_CHRSTEN_Msk (0x1UL) /*!< CHRSTEN (Bitfield-Mask: 0x01) */
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#define PWM_CH4SCR_DIR_Pos (1UL) /*!< DIR (Bit 1) */
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#define PWM_CH4SCR_DIR_Msk (0x2UL) /*!< DIR (Bitfield-Mask: 0x01) */
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#define PWM_CH4SCR_ELSR0_Pos (2UL) /*!< ELSR0 (Bit 2) */
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#define PWM_CH4SCR_ELSR0_Msk (0x4UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH4SCR_ELSR1_Pos (3UL) /*!< ELSR1 (Bit 3) */
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#define PWM_CH4SCR_ELSR1_Msk (0x8UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH4SCR_MSR0_Pos (4UL) /*!< MSR0 (Bit 4) */
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#define PWM_CH4SCR_MSR0_Msk (0x10UL) /*!< MSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH4SCR_MSR1_Pos (5UL) /*!< MSR1 (Bit 5) */
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#define PWM_CH4SCR_MSR1_Msk (0x20UL) /*!< MSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH4SCR_CHIE_Pos (6UL) /*!< CHIE (Bit 6) */
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#define PWM_CH4SCR_CHIE_Msk (0x40UL) /*!< CHIE (Bitfield-Mask: 0x01) */
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#define PWM_CH4SCR_CHIF_Pos (7UL) /*!< CHIF (Bit 7) */
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#define PWM_CH4SCR_CHIF_Msk (0x80UL) /*!< CHIF (Bitfield-Mask: 0x01) */
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#define PWM_CH4SCR_DMAEN_Pos (8UL) /*!< DMAEN (Bit 8) */
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#define PWM_CH4SCR_DMAEN_Msk (0x100UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
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/* ======================================================== CH5SCR ========================================================= */
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#define PWM_CH5SCR_CHRSTEN_Pos (0UL) /*!< CHRSTEN (Bit 0) */
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#define PWM_CH5SCR_CHRSTEN_Msk (0x1UL) /*!< CHRSTEN (Bitfield-Mask: 0x01) */
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#define PWM_CH5SCR_DIR_Pos (1UL) /*!< DIR (Bit 1) */
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#define PWM_CH5SCR_DIR_Msk (0x2UL) /*!< DIR (Bitfield-Mask: 0x01) */
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#define PWM_CH5SCR_ELSR0_Pos (2UL) /*!< ELSR0 (Bit 2) */
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#define PWM_CH5SCR_ELSR0_Msk (0x4UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH5SCR_ELSR1_Pos (3UL) /*!< ELSR1 (Bit 3) */
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#define PWM_CH5SCR_ELSR1_Msk (0x8UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH5SCR_MSR0_Pos (4UL) /*!< MSR0 (Bit 4) */
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#define PWM_CH5SCR_MSR0_Msk (0x10UL) /*!< MSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH5SCR_MSR1_Pos (5UL) /*!< MSR1 (Bit 5) */
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#define PWM_CH5SCR_MSR1_Msk (0x20UL) /*!< MSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH5SCR_CHIE_Pos (6UL) /*!< CHIE (Bit 6) */
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#define PWM_CH5SCR_CHIE_Msk (0x40UL) /*!< CHIE (Bitfield-Mask: 0x01) */
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#define PWM_CH5SCR_CHIF_Pos (7UL) /*!< CHIF (Bit 7) */
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#define PWM_CH5SCR_CHIF_Msk (0x80UL) /*!< CHIF (Bitfield-Mask: 0x01) */
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#define PWM_CH5SCR_DMAEN_Pos (8UL) /*!< DMAEN (Bit 8) */
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#define PWM_CH5SCR_DMAEN_Msk (0x100UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
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/* ======================================================== CH6SCR ========================================================= */
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#define PWM_CH6SCR_CHRSTEN_Pos (0UL) /*!< CHRSTEN (Bit 0) */
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#define PWM_CH6SCR_CHRSTEN_Msk (0x1UL) /*!< CHRSTEN (Bitfield-Mask: 0x01) */
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#define PWM_CH6SCR_DIR_Pos (1UL) /*!< DIR (Bit 1) */
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#define PWM_CH6SCR_DIR_Msk (0x2UL) /*!< DIR (Bitfield-Mask: 0x01) */
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#define PWM_CH6SCR_ELSR0_Pos (2UL) /*!< ELSR0 (Bit 2) */
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#define PWM_CH6SCR_ELSR0_Msk (0x4UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH6SCR_ELSR1_Pos (3UL) /*!< ELSR1 (Bit 3) */
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#define PWM_CH6SCR_ELSR1_Msk (0x8UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH6SCR_MSR0_Pos (4UL) /*!< MSR0 (Bit 4) */
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#define PWM_CH6SCR_MSR0_Msk (0x10UL) /*!< MSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH6SCR_MSR1_Pos (5UL) /*!< MSR1 (Bit 5) */
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#define PWM_CH6SCR_MSR1_Msk (0x20UL) /*!< MSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH6SCR_CHIE_Pos (6UL) /*!< CHIE (Bit 6) */
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#define PWM_CH6SCR_CHIE_Msk (0x40UL) /*!< CHIE (Bitfield-Mask: 0x01) */
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#define PWM_CH6SCR_CHIF_Pos (7UL) /*!< CHIF (Bit 7) */
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#define PWM_CH6SCR_CHIF_Msk (0x80UL) /*!< CHIF (Bitfield-Mask: 0x01) */
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#define PWM_CH6SCR_DMAEN_Pos (8UL) /*!< DMAEN (Bit 8) */
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#define PWM_CH6SCR_DMAEN_Msk (0x100UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
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/* ======================================================== CH7SCR ========================================================= */
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#define PWM_CH7SCR_CHRSTEN_Pos (0UL) /*!< CHRSTEN (Bit 0) */
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#define PWM_CH7SCR_CHRSTEN_Msk (0x1UL) /*!< CHRSTEN (Bitfield-Mask: 0x01) */
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#define PWM_CH7SCR_DIR_Pos (1UL) /*!< DIR (Bit 1) */
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#define PWM_CH7SCR_DIR_Msk (0x2UL) /*!< DIR (Bitfield-Mask: 0x01) */
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#define PWM_CH7SCR_ELSR0_Pos (2UL) /*!< ELSR0 (Bit 2) */
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#define PWM_CH7SCR_ELSR0_Msk (0x4UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH7SCR_ELSR1_Pos (3UL) /*!< ELSR1 (Bit 3) */
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#define PWM_CH7SCR_ELSR1_Msk (0x8UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH7SCR_MSR0_Pos (4UL) /*!< MSR0 (Bit 4) */
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#define PWM_CH7SCR_MSR0_Msk (0x10UL) /*!< MSR0 (Bitfield-Mask: 0x01) */
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#define PWM_CH7SCR_MSR1_Pos (5UL) /*!< MSR1 (Bit 5) */
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#define PWM_CH7SCR_MSR1_Msk (0x20UL) /*!< MSR1 (Bitfield-Mask: 0x01) */
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#define PWM_CH7SCR_CHIE_Pos (6UL) /*!< CHIE (Bit 6) */
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#define PWM_CH7SCR_CHIE_Msk (0x40UL) /*!< CHIE (Bitfield-Mask: 0x01) */
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#define PWM_CH7SCR_CHIF_Pos (7UL) /*!< CHIF (Bit 7) */
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#define PWM_CH7SCR_CHIF_Msk (0x80UL) /*!< CHIF (Bitfield-Mask: 0x01) */
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#define PWM_CH7SCR_DMAEN_Pos (8UL) /*!< DMAEN (Bit 8) */
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#define PWM_CH7SCR_DMAEN_Msk (0x100UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
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/* ========================================================= CH0V ========================================================== */
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#define PWM_CH0V_CHCVAL_Pos (0UL) /*!< CHCVAL (Bit 0) */
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#define PWM_CH0V_CHCVAL_Msk (0xffffUL) /*!< CHCVAL (Bitfield-Mask: 0xffff) */
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/* ========================================================= CH1V ========================================================== */
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#define PWM_CH1V_CHCVAL_Pos (0UL) /*!< CHCVAL (Bit 0) */
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#define PWM_CH1V_CHCVAL_Msk (0xffffUL) /*!< CHCVAL (Bitfield-Mask: 0xffff) */
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/* ========================================================= CH2V ========================================================== */
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#define PWM_CH2V_CHCVAL_Pos (0UL) /*!< CHCVAL (Bit 0) */
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#define PWM_CH2V_CHCVAL_Msk (0xffffUL) /*!< CHCVAL (Bitfield-Mask: 0xffff) */
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/* ========================================================= CH3V ========================================================== */
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#define PWM_CH3V_CHCVAL_Pos (0UL) /*!< CHCVAL (Bit 0) */
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#define PWM_CH3V_CHCVAL_Msk (0xffffUL) /*!< CHCVAL (Bitfield-Mask: 0xffff) */
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/* ========================================================= CH4V ========================================================== */
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#define PWM_CH4V_CHCVAL_Pos (0UL) /*!< CHCVAL (Bit 0) */
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#define PWM_CH4V_CHCVAL_Msk (0xffffUL) /*!< CHCVAL (Bitfield-Mask: 0xffff) */
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/* ========================================================= CH5V ========================================================== */
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#define PWM_CH5V_CHCVAL_Pos (0UL) /*!< CHCVAL (Bit 0) */
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#define PWM_CH5V_CHCVAL_Msk (0xffffUL) /*!< CHCVAL (Bitfield-Mask: 0xffff) */
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/* ========================================================= CH6V ========================================================== */
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#define PWM_CH6V_CHCVAL_Pos (0UL) /*!< CHCVAL (Bit 0) */
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#define PWM_CH6V_CHCVAL_Msk (0xffffUL) /*!< CHCVAL (Bitfield-Mask: 0xffff) */
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/* ========================================================= CH7V ========================================================== */
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#define PWM_CH7V_CHCVAL_Pos (0UL) /*!< CHCVAL (Bit 0) */
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#define PWM_CH7V_CHCVAL_Msk (0xffffUL) /*!< CHCVAL (Bitfield-Mask: 0xffff) */
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/* ========================================================= CNTIN ========================================================= */
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#define PWM_CNTIN_CNTINIT_Pos (0UL) /*!< CNTINIT (Bit 0) */
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#define PWM_CNTIN_CNTINIT_Msk (0xffffUL) /*!< CNTINIT (Bitfield-Mask: 0xffff) */
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/* ========================================================== STR ========================================================== */
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#define PWM_STR_CH0SF_Pos (0UL) /*!< CH0SF (Bit 0) */
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#define PWM_STR_CH0SF_Msk (0x1UL) /*!< CH0SF (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH1SF_Pos (1UL) /*!< CH1SF (Bit 1) */
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#define PWM_STR_CH1SF_Msk (0x2UL) /*!< CH1SF (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH2SF_Pos (2UL) /*!< CH2SF (Bit 2) */
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#define PWM_STR_CH2SF_Msk (0x4UL) /*!< CH2SF (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH3SF_Pos (3UL) /*!< CH3SF (Bit 3) */
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#define PWM_STR_CH3SF_Msk (0x8UL) /*!< CH3SF (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH4SF_Pos (4UL) /*!< CH4SF (Bit 4) */
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#define PWM_STR_CH4SF_Msk (0x10UL) /*!< CH4SF (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH5SF_Pos (5UL) /*!< CH5SF (Bit 5) */
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#define PWM_STR_CH5SF_Msk (0x20UL) /*!< CH5SF (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH6SF_Pos (6UL) /*!< CH6SF (Bit 6) */
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#define PWM_STR_CH6SF_Msk (0x40UL) /*!< CH6SF (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH7SF_Pos (7UL) /*!< CH7SF (Bit 7) */
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#define PWM_STR_CH7SF_Msk (0x80UL) /*!< CH7SF (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH0STS_Pos (16UL) /*!< CH0STS (Bit 16) */
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#define PWM_STR_CH0STS_Msk (0x10000UL) /*!< CH0STS (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH1STS_Pos (17UL) /*!< CH1STS (Bit 17) */
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#define PWM_STR_CH1STS_Msk (0x20000UL) /*!< CH1STS (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH2STS_Pos (18UL) /*!< CH2STS (Bit 18) */
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#define PWM_STR_CH2STS_Msk (0x40000UL) /*!< CH2STS (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH3STS_Pos (19UL) /*!< CH3STS (Bit 19) */
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#define PWM_STR_CH3STS_Msk (0x80000UL) /*!< CH3STS (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH4STS_Pos (20UL) /*!< CH4STS (Bit 20) */
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#define PWM_STR_CH4STS_Msk (0x100000UL) /*!< CH4STS (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH5STS_Pos (21UL) /*!< CH5STS (Bit 21) */
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#define PWM_STR_CH5STS_Msk (0x200000UL) /*!< CH5STS (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH6STS_Pos (22UL) /*!< CH6STS (Bit 22) */
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#define PWM_STR_CH6STS_Msk (0x400000UL) /*!< CH6STS (Bitfield-Mask: 0x01) */
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#define PWM_STR_CH7STS_Pos (23UL) /*!< CH7STS (Bit 23) */
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#define PWM_STR_CH7STS_Msk (0x800000UL) /*!< CH7STS (Bitfield-Mask: 0x01) */
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#define PWM_STR_HALL_STATUS_Pos (24UL) /*!< HALL_STATUS (Bit 24) */
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#define PWM_STR_HALL_STATUS_Msk (0x7000000UL) /*!< HALL_STATUS (Bitfield-Mask: 0x07) */
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#define PWM_STR_CH_EVENT_Msk (0xFFUL) /*!< PWM EVENT STATUS */
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#define PWM_STR_CH_INPUT_Msk (0xFF0000UL) /*!< PWM EVENT STATUS */
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/* ======================================================== FUNCSEL ======================================================== */
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#define PWM_FUNCSEL_PWMSYNCEN_Pos (0UL) /*!< PWMSYNCEN (Bit 0) */
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#define PWM_FUNCSEL_PWMSYNCEN_Msk (0x1UL) /*!< PWMSYNCEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_INIT_Pos (1UL) /*!< INIT (Bit 1) */
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#define PWM_FUNCSEL_INIT_Msk (0x2UL) /*!< INIT (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_WPDIS_Pos (2UL) /*!< WPDIS (Bit 2) */
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#define PWM_FUNCSEL_WPDIS_Msk (0x4UL) /*!< WPDIS (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_PWMSYNC_Pos (3UL) /*!< PWMSYNC (Bit 3) */
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#define PWM_FUNCSEL_PWMSYNC_Msk (0x8UL) /*!< PWMSYNC (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_FAULTMODE_Pos (5UL) /*!< FAULTMODE (Bit 5) */
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#define PWM_FUNCSEL_FAULTMODE_Msk (0x60UL) /*!< FAULTMODE (Bitfield-Mask: 0x03) */
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#define PWM_FUNCSEL_FAULTIE_Pos (7UL) /*!< FAULTIE (Bit 7) */
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#define PWM_FUNCSEL_FAULTIE_Msk (0x80UL) /*!< FAULTIE (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_FAULTHIZEN_Pos (8UL) /*!< FAULTHIZEN (Bit 8) */
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#define PWM_FUNCSEL_FAULTHIZEN_Msk (0x100UL) /*!< FAULTHIZEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_HALLEN_Pos (9UL) /*!< HALLEN (Bit 9) */
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#define PWM_FUNCSEL_HALLEN_Msk (0x200UL) /*!< HALLEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_CHP0PNWEN_Pos (12UL) /*!< CHP0PNWEN (Bit 12) */
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#define PWM_FUNCSEL_CHP0PNWEN_Msk (0x1000UL) /*!< CHP0PNWEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_CHP1PNWEN_Pos (13UL) /*!< CHP1PNWEN (Bit 13) */
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#define PWM_FUNCSEL_CHP1PNWEN_Msk (0x2000UL) /*!< CHP1PNWEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_CHP2PNWEN_Pos (14UL) /*!< CHP2PNWEN (Bit 14) */
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#define PWM_FUNCSEL_CHP2PNWEN_Msk (0x4000UL) /*!< CHP2PNWEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_CHP3PNWEN_Pos (15UL) /*!< CHP3PNWEN (Bit 15) */
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#define PWM_FUNCSEL_CHP3PNWEN_Msk (0x8000UL) /*!< CHP3PNWEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_CH0HIZEN_Pos (16UL) /*!< CH0HIZEN (Bit 16) */
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#define PWM_FUNCSEL_CH0HIZEN_Msk (0x10000UL) /*!< CH0HIZEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_CH1HIZEN_Pos (17UL) /*!< CH1HIZEN (Bit 17) */
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#define PWM_FUNCSEL_CH1HIZEN_Msk (0x20000UL) /*!< CH1HIZEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_CH2HIZEN_Pos (18UL) /*!< CH2HIZEN (Bit 18) */
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#define PWM_FUNCSEL_CH2HIZEN_Msk (0x40000UL) /*!< CH2HIZEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_CH3HIZEN_Pos (19UL) /*!< CH3HIZEN (Bit 19) */
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#define PWM_FUNCSEL_CH3HIZEN_Msk (0x80000UL) /*!< CH3HIZEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_CH4HIZEN_Pos (20UL) /*!< CH4HIZEN (Bit 20) */
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#define PWM_FUNCSEL_CH4HIZEN_Msk (0x100000UL) /*!< CH4HIZEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_CH5HIZEN_Pos (21UL) /*!< CH5HIZEN (Bit 21) */
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#define PWM_FUNCSEL_CH5HIZEN_Msk (0x200000UL) /*!< CH5HIZEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_CH6HIZEN_Pos (22UL) /*!< CH6HIZEN (Bit 22) */
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#define PWM_FUNCSEL_CH6HIZEN_Msk (0x400000UL) /*!< CH6HIZEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_CH7HIZEN_Pos (23UL) /*!< CH7HIZEN (Bit 23) */
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#define PWM_FUNCSEL_CH7HIZEN_Msk (0x800000UL) /*!< CH7HIZEN (Bitfield-Mask: 0x01) */
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#define PWM_FUNCSEL_PDYTPEN_Pos (24UL) /*!< PDYTPEN (Bit 24) */
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#define PWM_FUNCSEL_PDYTPEN_Msk (0x1000000UL) /*!< PDYTPEN (Bitfield-Mask: 0x01) */
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/* ========================================================= SYNC ========================================================== */
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#define PWM_SYNC_MINSYNCP_Pos (0UL) /*!< MINSYNCP (Bit 0) */
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#define PWM_SYNC_MINSYNCP_Msk (0x1UL) /*!< MINSYNCP (Bitfield-Mask: 0x01) */
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#define PWM_SYNC_MAXSYNCP_Pos (1UL) /*!< MAXSYNCP (Bit 1) */
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#define PWM_SYNC_MAXSYNCP_Msk (0x2UL) /*!< MAXSYNCP (Bitfield-Mask: 0x01) */
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#define PWM_SYNC_OMSYNCP_Pos (3UL) /*!< OMSYNCP (Bit 3) */
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#define PWM_SYNC_OMSYNCP_Msk (0x8UL) /*!< OMSYNCP (Bitfield-Mask: 0x01) */
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#define PWM_SYNC_TRIG0_Pos (4UL) /*!< TRIG0 (Bit 4) */
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#define PWM_SYNC_TRIG0_Msk (0x10UL) /*!< TRIG0 (Bitfield-Mask: 0x01) */
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#define PWM_SYNC_TRIG1_Pos (5UL) /*!< TRIG1 (Bit 5) */
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#define PWM_SYNC_TRIG1_Msk (0x20UL) /*!< TRIG1 (Bitfield-Mask: 0x01) */
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#define PWM_SYNC_TRIG2_Pos (6UL) /*!< TRIG2 (Bit 6) */
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#define PWM_SYNC_TRIG2_Msk (0x40UL) /*!< TRIG2 (Bitfield-Mask: 0x01) */
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#define PWM_SYNC_SWSYNC_Pos (7UL) /*!< SWSYNC (Bit 7) */
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#define PWM_SYNC_SWSYNC_Msk (0x80UL) /*!< SWSYNC (Bitfield-Mask: 0x01) */
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#define PWM_SYNC_PWM_SYNCPOL_Pos (11UL) /*!< PWM_SYNCPOL (Bit 11) */
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#define PWM_SYNC_PWM_SYNCPOL_Msk (0x800UL) /*!< PWM_SYNCPOL (Bitfield-Mask: 0x01) */
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#define PWM_SYNC_PWM_SYNC_BYPEN_Pos (16UL) /*!< PWM_SYNC_BYPEN (Bit 16) */
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#define PWM_SYNC_PWM_SYNC_BYPEN_Msk (0x10000UL) /*!< PWM_SYNC_BYPEN (Bitfield-Mask: 0x01) */
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#define PWM_SYNC_PWM_BFRGCHSEN_Pos (17UL) /*!< PWM_BFRGCHSEN (Bit 17) */
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#define PWM_SYNC_PWM_BFRGCHSEN_Msk (0x20000UL) /*!< PWM_BFRGCHSEN (Bitfield-Mask: 0x01) */
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/* ======================================================== OUTINIT ======================================================== */
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#define PWM_OUTINIT_CH0OIV_Pos (0UL) /*!< CH0OIV (Bit 0) */
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#define PWM_OUTINIT_CH0OIV_Msk (0x1UL) /*!< CH0OIV (Bitfield-Mask: 0x01) */
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#define PWM_OUTINIT_CH1OIV_Pos (1UL) /*!< CH1OIV (Bit 1) */
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#define PWM_OUTINIT_CH1OIV_Msk (0x2UL) /*!< CH1OIV (Bitfield-Mask: 0x01) */
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#define PWM_OUTINIT_CH2OIV_Pos (2UL) /*!< CH2OIV (Bit 2) */
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#define PWM_OUTINIT_CH2OIV_Msk (0x4UL) /*!< CH2OIV (Bitfield-Mask: 0x01) */
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#define PWM_OUTINIT_CH3OIV_Pos (3UL) /*!< CH3OIV (Bit 3) */
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#define PWM_OUTINIT_CH3OIV_Msk (0x8UL) /*!< CH3OIV (Bitfield-Mask: 0x01) */
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#define PWM_OUTINIT_CH4OIV_Pos (4UL) /*!< CH4OIV (Bit 4) */
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#define PWM_OUTINIT_CH4OIV_Msk (0x10UL) /*!< CH4OIV (Bitfield-Mask: 0x01) */
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#define PWM_OUTINIT_CH5OIV_Pos (5UL) /*!< CH5OIV (Bit 5) */
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#define PWM_OUTINIT_CH5OIV_Msk (0x20UL) /*!< CH5OIV (Bitfield-Mask: 0x01) */
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#define PWM_OUTINIT_CH6OIV_Pos (6UL) /*!< CH6OIV (Bit 6) */
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#define PWM_OUTINIT_CH6OIV_Msk (0x40UL) /*!< CH6OIV (Bitfield-Mask: 0x01) */
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#define PWM_OUTINIT_CH7OIV_Pos (7UL) /*!< CH7OIV (Bit 7) */
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#define PWM_OUTINIT_CH7OIV_Msk (0x80UL) /*!< CH7OIV (Bitfield-Mask: 0x01) */
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/* ========================================================= OMCR ========================================================== */
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#define PWM_OMCR_CH0OMEN_Pos (0UL) /*!< CH0OMEN (Bit 0) */
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#define PWM_OMCR_CH0OMEN_Msk (0x1UL) /*!< CH0OMEN (Bitfield-Mask: 0x01) */
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#define PWM_OMCR_CH1OMEN_Pos (1UL) /*!< CH1OMEN (Bit 1) */
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#define PWM_OMCR_CH1OMEN_Msk (0x2UL) /*!< CH1OMEN (Bitfield-Mask: 0x01) */
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#define PWM_OMCR_CH2OMEN_Pos (2UL) /*!< CH2OMEN (Bit 2) */
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#define PWM_OMCR_CH2OMEN_Msk (0x4UL) /*!< CH2OMEN (Bitfield-Mask: 0x01) */
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#define PWM_OMCR_CH3OMEN_Pos (3UL) /*!< CH3OMEN (Bit 3) */
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#define PWM_OMCR_CH3OMEN_Msk (0x8UL) /*!< CH3OMEN (Bitfield-Mask: 0x01) */
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#define PWM_OMCR_CH4OMEN_Pos (4UL) /*!< CH4OMEN (Bit 4) */
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#define PWM_OMCR_CH4OMEN_Msk (0x10UL) /*!< CH4OMEN (Bitfield-Mask: 0x01) */
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#define PWM_OMCR_CH5OMEN_Pos (5UL) /*!< CH5OMEN (Bit 5) */
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#define PWM_OMCR_CH5OMEN_Msk (0x20UL) /*!< CH5OMEN (Bitfield-Mask: 0x01) */
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#define PWM_OMCR_CH6OMEN_Pos (6UL) /*!< CH6OMEN (Bit 6) */
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#define PWM_OMCR_CH6OMEN_Msk (0x40UL) /*!< CH6OMEN (Bitfield-Mask: 0x01) */
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#define PWM_OMCR_CH7OMEN_Pos (7UL) /*!< CH7OMEN (Bit 7) */
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#define PWM_OMCR_CH7OMEN_Msk (0x80UL) /*!< CH7OMEN (Bitfield-Mask: 0x01) */
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#define PWM_OMCR_CH_Msk (0xFFUL) /*!< ALL CH Mask */
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/* ======================================================== MODESEL ======================================================== */
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#define PWM_MODESEL_PAIR0COMBINEN_Pos (0UL) /*!< PAIR0COMBINEN (Bit 0) */
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#define PWM_MODESEL_PAIR0COMBINEN_Msk (0x1UL) /*!< PAIR0COMBINEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR0COMPEN_Pos (1UL) /*!< PAIR0COMPEN (Bit 1) */
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#define PWM_MODESEL_PAIR0COMPEN_Msk (0x2UL) /*!< PAIR0COMPEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR0DECAPEN_Pos (2UL) /*!< PAIR0DECAPEN (Bit 2) */
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#define PWM_MODESEL_PAIR0DECAPEN_Msk (0x4UL) /*!< PAIR0DECAPEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR0DECAP_Pos (3UL) /*!< PAIR0DECAP (Bit 3) */
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#define PWM_MODESEL_PAIR0DECAP_Msk (0x8UL) /*!< PAIR0DECAP (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR0DTEN_Pos (4UL) /*!< PAIR0DTEN (Bit 4) */
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#define PWM_MODESEL_PAIR0DTEN_Msk (0x10UL) /*!< PAIR0DTEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR0SYNCEN_Pos (5UL) /*!< PAIR0SYNCEN (Bit 5) */
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#define PWM_MODESEL_PAIR0SYNCEN_Msk (0x20UL) /*!< PAIR0SYNCEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR0FAULTEN_Pos (6UL) /*!< PAIR0FAULTEN (Bit 6) */
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#define PWM_MODESEL_PAIR0FAULTEN_Msk (0x40UL) /*!< PAIR0FAULTEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR0SYMEN_Pos (7UL) /*!< PAIR0SYMEN (Bit 7) */
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#define PWM_MODESEL_PAIR0SYMEN_Msk (0x80UL) /*!< PAIR0SYMEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR1COMBINEN_Pos (8UL) /*!< PAIR1COMBINEN (Bit 8) */
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#define PWM_MODESEL_PAIR1COMBINEN_Msk (0x100UL) /*!< PAIR1COMBINEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR1COMPEN_Pos (9UL) /*!< PAIR1COMPEN (Bit 9) */
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#define PWM_MODESEL_PAIR1COMPEN_Msk (0x200UL) /*!< PAIR1COMPEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR1DECAPEN_Pos (10UL) /*!< PAIR1DECAPEN (Bit 10) */
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#define PWM_MODESEL_PAIR1DECAPEN_Msk (0x400UL) /*!< PAIR1DECAPEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR1DECAP_Pos (11UL) /*!< PAIR1DECAP (Bit 11) */
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#define PWM_MODESEL_PAIR1DECAP_Msk (0x800UL) /*!< PAIR1DECAP (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR1DTEN_Pos (12UL) /*!< PAIR1DTEN (Bit 12) */
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#define PWM_MODESEL_PAIR1DTEN_Msk (0x1000UL) /*!< PAIR1DTEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR1SYNCEN_Pos (13UL) /*!< PAIR1SYNCEN (Bit 13) */
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#define PWM_MODESEL_PAIR1SYNCEN_Msk (0x2000UL) /*!< PAIR1SYNCEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR1FAULTEN_Pos (14UL) /*!< PAIR1FAULTEN (Bit 14) */
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#define PWM_MODESEL_PAIR1FAULTEN_Msk (0x4000UL) /*!< PAIR1FAULTEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR1SYMEN_Pos (15UL) /*!< PAIR1SYMEN (Bit 15) */
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#define PWM_MODESEL_PAIR1SYMEN_Msk (0x8000UL) /*!< PAIR1SYMEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR2COMBINEN_Pos (16UL) /*!< PAIR2COMBINEN (Bit 16) */
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#define PWM_MODESEL_PAIR2COMBINEN_Msk (0x10000UL) /*!< PAIR2COMBINEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR2COMPEN_Pos (17UL) /*!< PAIR2COMPEN (Bit 17) */
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#define PWM_MODESEL_PAIR2COMPEN_Msk (0x20000UL) /*!< PAIR2COMPEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR2DECAPEN_Pos (18UL) /*!< PAIR2DECAPEN (Bit 18) */
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#define PWM_MODESEL_PAIR2DECAPEN_Msk (0x40000UL) /*!< PAIR2DECAPEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR2DECAP_Pos (19UL) /*!< PAIR2DECAP (Bit 19) */
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#define PWM_MODESEL_PAIR2DECAP_Msk (0x80000UL) /*!< PAIR2DECAP (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR2DTEN_Pos (20UL) /*!< PAIR2DTEN (Bit 20) */
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#define PWM_MODESEL_PAIR2DTEN_Msk (0x100000UL) /*!< PAIR2DTEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR2SYNCEN_Pos (21UL) /*!< PAIR2SYNCEN (Bit 21) */
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#define PWM_MODESEL_PAIR2SYNCEN_Msk (0x200000UL) /*!< PAIR2SYNCEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR2FAULTEN_Pos (22UL) /*!< PAIR2FAULTEN (Bit 22) */
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#define PWM_MODESEL_PAIR2FAULTEN_Msk (0x400000UL) /*!< PAIR2FAULTEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR2SYMEN_Pos (23UL) /*!< PAIR2SYMEN (Bit 23) */
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#define PWM_MODESEL_PAIR2SYMEN_Msk (0x800000UL) /*!< PAIR2SYMEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR3COMBINEN_Pos (24UL) /*!< PAIR3COMBINEN (Bit 24) */
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#define PWM_MODESEL_PAIR3COMBINEN_Msk (0x1000000UL) /*!< PAIR3COMBINEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR3COMPEN_Pos (25UL) /*!< PAIR3COMPEN (Bit 25) */
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#define PWM_MODESEL_PAIR3COMPEN_Msk (0x2000000UL) /*!< PAIR3COMPEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR3DECAPEN_Pos (26UL) /*!< PAIR3DECAPEN (Bit 26) */
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#define PWM_MODESEL_PAIR3DECAPEN_Msk (0x4000000UL) /*!< PAIR3DECAPEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR3DECAP_Pos (27UL) /*!< PAIR3DECAP (Bit 27) */
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#define PWM_MODESEL_PAIR3DECAP_Msk (0x8000000UL) /*!< PAIR3DECAP (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR3DTEN_Pos (28UL) /*!< PAIR3DTEN (Bit 28) */
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#define PWM_MODESEL_PAIR3DTEN_Msk (0x10000000UL) /*!< PAIR3DTEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR3SYNCEN_Pos (29UL) /*!< PAIR3SYNCEN (Bit 29) */
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#define PWM_MODESEL_PAIR3SYNCEN_Msk (0x20000000UL) /*!< PAIR3SYNCEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR3FAULTEN_Pos (30UL) /*!< PAIR3FAULTEN (Bit 30) */
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#define PWM_MODESEL_PAIR3FAULTEN_Msk (0x40000000UL) /*!< PAIR3FAULTEN (Bitfield-Mask: 0x01) */
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#define PWM_MODESEL_PAIR3SYMEN_Pos (31UL) /*!< PAIR3SYMEN (Bit 31) */
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#define PWM_MODESEL_PAIR3SYMEN_Msk (0x80000000UL) /*!< PAIR3SYMEN (Bitfield-Mask: 0x01) */
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#define PWM_COMBINE_PAIR_CONFIG_WIDTH (8UL) /*!< PAIRCONFIG */
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/* ======================================================== DTSET0 ========================================================= */
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#define PWM_DTSET0_DTVAL0_Pos (0UL) /*!< DTVAL0 (Bit 0) */
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#define PWM_DTSET0_DTVAL0_Msk (0x3ffUL) /*!< DTVAL0 (Bitfield-Mask: 0x3ff) */
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#define PWM_DTSET0_DTPSC0_Pos (10UL) /*!< DTPSC0 (Bit 10) */
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#define PWM_DTSET0_DTPSC0_Msk (0xc00UL) /*!< DTPSC0 (Bitfield-Mask: 0x03) */
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#define PWM_DTSET0_DTVAL1_Pos (16UL) /*!< DTVAL1 (Bit 16) */
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#define PWM_DTSET0_DTVAL1_Msk (0x3ff0000UL) /*!< DTVAL1 (Bitfield-Mask: 0x3ff) */
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#define PWM_DTSET0_DTPSC1_Pos (26UL) /*!< DTPSC1 (Bit 26) */
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#define PWM_DTSET0_DTPSC1_Msk (0xc000000UL) /*!< DTPSC1 (Bitfield-Mask: 0x03) */
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#define PWM_DTSET_CONFIG_WIDTH (16UL) /*!< deadtime Config Width */
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/* ======================================================== DTSET1 ========================================================= */
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#define PWM_DTSET1_DTVAL2_Pos (0UL) /*!< DTVAL2 (Bit 0) */
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#define PWM_DTSET1_DTVAL2_Msk (0x3ffUL) /*!< DTVAL2 (Bitfield-Mask: 0x3ff) */
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#define PWM_DTSET1_DTPS2_Pos (10UL) /*!< DTPS2 (Bit 10) */
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#define PWM_DTSET1_DTPS2_Msk (0xc00UL) /*!< DTPS2 (Bitfield-Mask: 0x03) */
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#define PWM_DTSET1_DTVAL3_Pos (16UL) /*!< DTVAL3 (Bit 16) */
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#define PWM_DTSET1_DTVAL3_Msk (0x3ff0000UL) /*!< DTVAL3 (Bitfield-Mask: 0x3ff) */
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#define PWM_DTSET1_DTPS3_Pos (26UL) /*!< DTPS3 (Bit 26) */
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#define PWM_DTSET1_DTPS3_Msk (0xc000000UL) /*!< DTPS3 (Bitfield-Mask: 0x03) */
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/* ======================================================== EXTTRIG ======================================================== */
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#define PWM_EXTTRIG_CH0TRIG_Pos (0UL) /*!< CH0TRIG (Bit 0) */
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#define PWM_EXTTRIG_CH0TRIG_Msk (0x1UL) /*!< CH0TRIG (Bitfield-Mask: 0x01) */
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#define PWM_EXTTRIG_CH1TRIG_Pos (1UL) /*!< CH1TRIG (Bit 1) */
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#define PWM_EXTTRIG_CH1TRIG_Msk (0x2UL) /*!< CH1TRIG (Bitfield-Mask: 0x01) */
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#define PWM_EXTTRIG_CH2TRIG_Pos (2UL) /*!< CH2TRIG (Bit 2) */
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#define PWM_EXTTRIG_CH2TRIG_Msk (0x4UL) /*!< CH2TRIG (Bitfield-Mask: 0x01) */
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#define PWM_EXTTRIG_CH3TRIG_Pos (3UL) /*!< CH3TRIG (Bit 3) */
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#define PWM_EXTTRIG_CH3TRIG_Msk (0x8UL) /*!< CH3TRIG (Bitfield-Mask: 0x01) */
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#define PWM_EXTTRIG_CH4TRIG_Pos (4UL) /*!< CH4TRIG (Bit 4) */
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#define PWM_EXTTRIG_CH4TRIG_Msk (0x10UL) /*!< CH4TRIG (Bitfield-Mask: 0x01) */
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#define PWM_EXTTRIG_CH5TRIG_Pos (5UL) /*!< CH5TRIG (Bit 5) */
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#define PWM_EXTTRIG_CH5TRIG_Msk (0x20UL) /*!< CH5TRIG (Bitfield-Mask: 0x01) */
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#define PWM_EXTTRIG_CH6TRIG_Pos (6UL) /*!< CH6TRIG (Bit 6) */
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#define PWM_EXTTRIG_CH6TRIG_Msk (0x40UL) /*!< CH6TRIG (Bitfield-Mask: 0x01) */
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#define PWM_EXTTRIG_CH7TRIG_Pos (7UL) /*!< CH7TRIG (Bit 7) */
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#define PWM_EXTTRIG_CH7TRIG_Msk (0x80UL) /*!< CH7TRIG (Bitfield-Mask: 0x01) */
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#define PWM_EXTTRIG_INITTRIGEN_Pos (8UL) /*!< INITTRIGEN (Bit 8) */
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#define PWM_EXTTRIG_INITTRIGEN_Msk (0x100UL) /*!< INITTRIGEN (Bitfield-Mask: 0x01) */
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#define PWM_EXTTRIG_TRIGF_Pos (9UL) /*!< TRIGF (Bit 9) */
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#define PWM_EXTTRIG_TRIGF_Msk (0x200UL) /*!< TRIGF (Bitfield-Mask: 0x01) */
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#define PWM_EXTTRIG_MAXTRIGEN_Pos (10UL) /*!< MAXTRIGEN (Bit 10) */
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#define PWM_EXTTRIG_MAXTRIGEN_Msk (0x400UL) /*!< MAXTRIGEN (Bitfield-Mask: 0x01) */
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#define PWM_EXTTRIG_TRIGRATIO_Pos (12UL) /*!< TRIGRATIO (Bit 12) */
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#define PWM_EXTTRIG_TRIGRATIO_Msk (0x7000UL) /*!< TRIGRATIO (Bitfield-Mask: 0x07) */
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/* ======================================================= CHOPOLCR ======================================================== */
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#define PWM_CHOPOLCR_CH0POL_Pos (0UL) /*!< CH0POL (Bit 0) */
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#define PWM_CHOPOLCR_CH0POL_Msk (0x1UL) /*!< CH0POL (Bitfield-Mask: 0x01) */
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#define PWM_CHOPOLCR_CH1POL_Pos (1UL) /*!< CH1POL (Bit 1) */
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#define PWM_CHOPOLCR_CH1POL_Msk (0x2UL) /*!< CH1POL (Bitfield-Mask: 0x01) */
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#define PWM_CHOPOLCR_CH2POL_Pos (2UL) /*!< CH2POL (Bit 2) */
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#define PWM_CHOPOLCR_CH2POL_Msk (0x4UL) /*!< CH2POL (Bitfield-Mask: 0x01) */
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#define PWM_CHOPOLCR_CH3POL_Pos (3UL) /*!< CH3POL (Bit 3) */
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#define PWM_CHOPOLCR_CH3POL_Msk (0x8UL) /*!< CH3POL (Bitfield-Mask: 0x01) */
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#define PWM_CHOPOLCR_CH4POL_Pos (4UL) /*!< CH4POL (Bit 4) */
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#define PWM_CHOPOLCR_CH4POL_Msk (0x10UL) /*!< CH4POL (Bitfield-Mask: 0x01) */
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#define PWM_CHOPOLCR_CH5POL_Pos (5UL) /*!< CH5POL (Bit 5) */
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#define PWM_CHOPOLCR_CH5POL_Msk (0x20UL) /*!< CH5POL (Bitfield-Mask: 0x01) */
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#define PWM_CHOPOLCR_CH6POL_Pos (6UL) /*!< CH6POL (Bit 6) */
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#define PWM_CHOPOLCR_CH6POL_Msk (0x40UL) /*!< CH6POL (Bitfield-Mask: 0x01) */
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#define PWM_CHOPOLCR_CH7POL_Pos (7UL) /*!< CH7POL (Bit 7) */
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#define PWM_CHOPOLCR_CH7POL_Msk (0x80UL) /*!< CH7POL (Bitfield-Mask: 0x01) */
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/* ========================================================= FDSR ========================================================== */
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#define PWM_FDSR_FAULTDF0_Pos (0UL) /*!< FAULTDF0 (Bit 0) */
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#define PWM_FDSR_FAULTDF0_Msk (0x1UL) /*!< FAULTDF0 (Bitfield-Mask: 0x01) */
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#define PWM_FDSR_FAULTDF1_Pos (1UL) /*!< FAULTDF1 (Bit 1) */
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#define PWM_FDSR_FAULTDF1_Msk (0x2UL) /*!< FAULTDF1 (Bitfield-Mask: 0x01) */
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#define PWM_FDSR_FAULTDF2_Pos (2UL) /*!< FAULTDF2 (Bit 2) */
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#define PWM_FDSR_FAULTDF2_Msk (0x4UL) /*!< FAULTDF2 (Bitfield-Mask: 0x01) */
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#define PWM_FDSR_FAULTDF3_Pos (3UL) /*!< FAULTDF3 (Bit 3) */
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#define PWM_FDSR_FAULTDF3_Msk (0x8UL) /*!< FAULTDF3 (Bitfield-Mask: 0x01) */
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#define PWM_FDSR_FAULTIN_Pos (5UL) /*!< FAULTIN (Bit 5) */
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#define PWM_FDSR_FAULTIN_Msk (0x20UL) /*!< FAULTIN (Bitfield-Mask: 0x01) */
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#define PWM_FDSR_WPEN_Pos (6UL) /*!< WPEN (Bit 6) */
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#define PWM_FDSR_WPEN_Msk (0x40UL) /*!< WPEN (Bitfield-Mask: 0x01) */
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#define PWM_FDSR_FAULTDF_Pos (7UL) /*!< FAULTDF (Bit 7) */
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#define PWM_FDSR_FAULTDF_Msk (0x80UL) /*!< FAULTDF (Bitfield-Mask: 0x01) */
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/* ======================================================= CAPFILTER ======================================================= */
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#define PWM_CAPFILTER_CH0CAPFVAL_Pos (0UL) /*!< CH0CAPFVAL (Bit 0) */
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#define PWM_CAPFILTER_CH0CAPFVAL_Msk (0xfUL) /*!< CH0CAPFVAL (Bitfield-Mask: 0x0f) */
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#define PWM_CAPFILTER_CH1CAPFVAL_Pos (5UL) /*!< CH1CAPFVAL (Bit 5) */
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#define PWM_CAPFILTER_CH1CAPFVAL_Msk (0x1e0UL) /*!< CH1CAPFVAL (Bitfield-Mask: 0x0f) */
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#define PWM_CAPFILTER_CH2CAPFVAL_Pos (10UL) /*!< CH2CAPFVAL (Bit 10) */
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#define PWM_CAPFILTER_CH2CAPFVAL_Msk (0x3c00UL) /*!< CH2CAPFVAL (Bitfield-Mask: 0x0f) */
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#define PWM_CAPFILTER_CH3CAPFVAL_Pos (15UL) /*!< CH3CAPFVAL (Bit 15) */
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#define PWM_CAPFILTER_CH3CAPFVAL_Msk (0x78000UL) /*!< CH3CAPFVAL (Bitfield-Mask: 0x0f) */
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#define PWM_CAPFILTER_CAPFPSC_Pos (24UL) /*!< CAPFPSC (Bit 24) */
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#define PWM_CAPFILTER_CAPFPSC_Msk (0xf000000UL) /*!< CAPFPSC (Bitfield-Mask: 0x0f) */
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#define PWM_CAPFILTER_WIDTH (5UL) /*!< Channel input filter width */
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/* ======================================================== FFAFER ========================================================= */
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#define PWM_FFAFER_FER0EN_Pos (0UL) /*!< FER0EN (Bit 0) */
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#define PWM_FFAFER_FER0EN_Msk (0x1UL) /*!< FER0EN (Bitfield-Mask: 0x01) */
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#define PWM_FFAFER_FER1EN_Pos (1UL) /*!< FER1EN (Bit 1) */
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#define PWM_FFAFER_FER1EN_Msk (0x2UL) /*!< FER1EN (Bitfield-Mask: 0x01) */
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#define PWM_FFAFER_FER2EN_Pos (2UL) /*!< FER2EN (Bit 2) */
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#define PWM_FFAFER_FER2EN_Msk (0x4UL) /*!< FER2EN (Bitfield-Mask: 0x01) */
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#define PWM_FFAFER_FER3EN_Pos (3UL) /*!< FER3EN (Bit 3) */
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#define PWM_FFAFER_FER3EN_Msk (0x8UL) /*!< FER3EN (Bitfield-Mask: 0x01) */
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#define PWM_FFAFER_FF0EN_Pos (4UL) /*!< FF0EN (Bit 4) */
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#define PWM_FFAFER_FF0EN_Msk (0x10UL) /*!< FF0EN (Bitfield-Mask: 0x01) */
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#define PWM_FFAFER_FF1EN_Pos (5UL) /*!< FF1EN (Bit 5) */
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#define PWM_FFAFER_FF1EN_Msk (0x20UL) /*!< FF1EN (Bitfield-Mask: 0x01) */
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#define PWM_FFAFER_FF2EN_Pos (6UL) /*!< FF2EN (Bit 6) */
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#define PWM_FFAFER_FF2EN_Msk (0x40UL) /*!< FF2EN (Bitfield-Mask: 0x01) */
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#define PWM_FFAFER_FF3EN_Pos (7UL) /*!< FF3EN (Bit 7) */
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#define PWM_FFAFER_FF3EN_Msk (0x80UL) /*!< FF3EN (Bitfield-Mask: 0x01) */
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#define PWM_FFAFER_FFVAL_Pos (8UL) /*!< FFVAL (Bit 8) */
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#define PWM_FFAFER_FFVAL_Msk (0xf00UL) /*!< FFVAL (Bitfield-Mask: 0x0f) */
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/* ========================================================== QDI ========================================================== */
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#define PWM_QDI_QDIEN_Pos (0UL) /*!< QDIEN (Bit 0) */
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#define PWM_QDI_QDIEN_Msk (0x1UL) /*!< QDIEN (Bitfield-Mask: 0x01) */
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#define PWM_QDI_CNTOFDIR_Pos (1UL) /*!< CNTOFDIR (Bit 1) */
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#define PWM_QDI_CNTOFDIR_Msk (0x2UL) /*!< CNTOFDIR (Bitfield-Mask: 0x01) */
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#define PWM_QDI_QUADIR_Pos (2UL) /*!< QUADIR (Bit 2) */
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#define PWM_QDI_QUADIR_Msk (0x4UL) /*!< QUADIR (Bitfield-Mask: 0x01) */
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#define PWM_QDI_QUADMODE_Pos (3UL) /*!< QUADMODE (Bit 3) */
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#define PWM_QDI_QUADMODE_Msk (0x8UL) /*!< QUADMODE (Bitfield-Mask: 0x01) */
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#define PWM_QDI_PHBPOL_Pos (4UL) /*!< PHBPOL (Bit 4) */
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#define PWM_QDI_PHBPOL_Msk (0x10UL) /*!< PHBPOL (Bitfield-Mask: 0x01) */
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#define PWM_QDI_PHAPOL_Pos (5UL) /*!< PHAPOL (Bit 5) */
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#define PWM_QDI_PHAPOL_Msk (0x20UL) /*!< PHAPOL (Bitfield-Mask: 0x01) */
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#define PWM_QDI_PHZRSTEN_Pos (8UL) /*!< PHZRSTEN (Bit 8) */
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#define PWM_QDI_PHZRSTEN_Msk (0x100UL) /*!< PHZRSTEN (Bitfield-Mask: 0x01) */
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#define PWM_QDI_PHZPOL_Pos (9UL) /*!< PHZPOL (Bit 9) */
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#define PWM_QDI_PHZPOL_Msk (0x200UL) /*!< PHZPOL (Bitfield-Mask: 0x01) */
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#define PWM_QDI_PHZSTS_Pos (11UL) /*!< PHZSTS (Bit 11) */
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#define PWM_QDI_PHZSTS_Msk (0x800UL) /*!< PHZSTS (Bitfield-Mask: 0x01) */
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/* ========================================================= CONF ========================================================== */
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#define PWM_CONF_CNTOFNUM_Pos (0UL) /*!< CNTOFNUM (Bit 0) */
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#define PWM_CONF_CNTOFNUM_Msk (0x1fUL) /*!< CNTOFNUM (Bitfield-Mask: 0x1f) */
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#define PWM_CONF_GTBEEN_Pos (9UL) /*!< GTBEEN (Bit 9) */
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#define PWM_CONF_GTBEEN_Msk (0x200UL) /*!< GTBEEN (Bitfield-Mask: 0x01) */
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#define PWM_CONF_GTBEOUT_Pos (10UL) /*!< GTBEOUT (Bit 10) */
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#define PWM_CONF_GTBEOUT_Msk (0x400UL) /*!< GTBEOUT (Bitfield-Mask: 0x01) */
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#define PWM_CONF_EVENT0_PSC_Pos (16UL) /*!< EVENT0_PSC (Bit 16) */
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#define PWM_CONF_EVENT0_PSC_Msk (0x30000UL) /*!< EVENT0_PSC (Bitfield-Mask: 0x03) */
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#define PWM_CONF_EVENT1_PSC_Pos (18UL) /*!< EVENT1_PSC (Bit 18) */
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#define PWM_CONF_EVENT1_PSC_Msk (0xc0000UL) /*!< EVENT1_PSC (Bitfield-Mask: 0x03) */
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#define PWM_CONF_EVENT2_PSC_Pos (20UL) /*!< EVENT2_PSC (Bit 20) */
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#define PWM_CONF_EVENT2_PSC_Msk (0x300000UL) /*!< EVENT2_PSC (Bitfield-Mask: 0x03) */
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#define PWM_CONF_EVENT3_PSC_Pos (22UL) /*!< EVENT3_PSC (Bit 22) */
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#define PWM_CONF_EVENT3_PSC_Msk (0xc00000UL) /*!< EVENT3_PSC (Bitfield-Mask: 0x03) */
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#define PWM_CONF_EVENT4_PSC_Pos (24UL) /*!< EVENT4_PSC (Bit 24) */
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#define PWM_CONF_EVENT4_PSC_Msk (0x3000000UL) /*!< EVENT4_PSC (Bitfield-Mask: 0x03) */
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#define PWM_CONF_EVENT5_PSC_Pos (26UL) /*!< EVENT5_PSC (Bit 26) */
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#define PWM_CONF_EVENT5_PSC_Msk (0xc000000UL) /*!< EVENT5_PSC (Bitfield-Mask: 0x03) */
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#define PWM_CONF_EVENT6_PSC_Pos (28UL) /*!< EVENT6_PSC (Bit 28) */
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#define PWM_CONF_EVENT6_PSC_Msk (0x30000000UL) /*!< EVENT6_PSC (Bitfield-Mask: 0x03) */
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#define PWM_CONF_EVENT7_PSC_Pos (30UL) /*!< EVENT7_PSC (Bit 30) */
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#define PWM_CONF_EVENT7_PSC_Msk (0xc0000000UL) /*!< EVENT7_PSC (Bitfield-Mask: 0x03) */
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#define PWM_CONF_EVENTPSC_WIDTH (2UL) /*!< EVENTPSC (Bitfield-Mask: 0x03) */
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/* ======================================================== FLTPOL ========================================================= */
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#define PWM_FLTPOL_FLT0POL_Pos (0UL) /*!< FLT0POL (Bit 0) */
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#define PWM_FLTPOL_FLT0POL_Msk (0x1UL) /*!< FLT0POL (Bitfield-Mask: 0x01) */
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#define PWM_FLTPOL_FLT1POL_Pos (1UL) /*!< FLT1POL (Bit 1) */
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#define PWM_FLTPOL_FLT1POL_Msk (0x2UL) /*!< FLT1POL (Bitfield-Mask: 0x01) */
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#define PWM_FLTPOL_FLT2POL_Pos (2UL) /*!< FLT2POL (Bit 2) */
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#define PWM_FLTPOL_FLT2POL_Msk (0x4UL) /*!< FLT2POL (Bitfield-Mask: 0x01) */
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#define PWM_FLTPOL_FLT3POL_Pos (3UL) /*!< FLT3POL (Bit 3) */
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#define PWM_FLTPOL_FLT3POL_Msk (0x8UL) /*!< FLT3POL (Bitfield-Mask: 0x01) */
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/* ======================================================== SYNCONF ======================================================== */
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#define PWM_SYNCONF_HWTRIGMODE_Pos (0UL) /*!< HWTRIGMODE (Bit 0) */
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#define PWM_SYNCONF_HWTRIGMODE_Msk (0x1UL) /*!< HWTRIGMODE (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_CNTINC_Pos (2UL) /*!< CNTINC (Bit 2) */
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#define PWM_SYNCONF_CNTINC_Msk (0x4UL) /*!< CNTINC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_INVC_Pos (4UL) /*!< INVC (Bit 4) */
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#define PWM_SYNCONF_INVC_Msk (0x10UL) /*!< INVC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_SWOC_Pos (5UL) /*!< SWOC (Bit 5) */
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#define PWM_SYNCONF_SWOC_Msk (0x20UL) /*!< SWOC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_SYNCMODE_Pos (7UL) /*!< SYNCMODE (Bit 7) */
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#define PWM_SYNCONF_SYNCMODE_Msk (0x80UL) /*!< SYNCMODE (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_CNTVSWSYNC_Pos (8UL) /*!< CNTVSWSYNC (Bit 8) */
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#define PWM_SYNCONF_CNTVSWSYNC_Msk (0x100UL) /*!< CNTVSWSYNC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_PWMSVSWSYNC_Pos (9UL) /*!< PWMSVSWSYNC (Bit 9) */
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#define PWM_SYNCONF_PWMSVSWSYNC_Msk (0x200UL) /*!< PWMSVSWSYNC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_OMVSWSYNC_Pos (10UL) /*!< OMVSWSYNC (Bit 10) */
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#define PWM_SYNCONF_OMVSWSYNC_Msk (0x400UL) /*!< OMVSWSYNC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_INVSWSYNC_Pos (11UL) /*!< INVSWSYNC (Bit 11) */
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#define PWM_SYNCONF_INVSWSYNC_Msk (0x800UL) /*!< INVSWSYNC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_SWVSWSYNC_Pos (12UL) /*!< SWVSWSYNC (Bit 12) */
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#define PWM_SYNCONF_SWVSWSYNC_Msk (0x1000UL) /*!< SWVSWSYNC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_CNTVHWSYNC_Pos (16UL) /*!< CNTVHWSYNC (Bit 16) */
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#define PWM_SYNCONF_CNTVHWSYNC_Msk (0x10000UL) /*!< CNTVHWSYNC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_PWMSVHWSYNC_Pos (17UL) /*!< PWMSVHWSYNC (Bit 17) */
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#define PWM_SYNCONF_PWMSVHWSYNC_Msk (0x20000UL) /*!< PWMSVHWSYNC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_OMVHWSYNC_Pos (18UL) /*!< OMVHWSYNC (Bit 18) */
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#define PWM_SYNCONF_OMVHWSYNC_Msk (0x40000UL) /*!< OMVHWSYNC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_INVHWSYNC_Pos (19UL) /*!< INVHWSYNC (Bit 19) */
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#define PWM_SYNCONF_INVHWSYNC_Msk (0x80000UL) /*!< INVHWSYNC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_SWVHWSYNC_Pos (20UL) /*!< SWVHWSYNC (Bit 20) */
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#define PWM_SYNCONF_SWVHWSYNC_Msk (0x100000UL) /*!< SWVHWSYNC (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_SWPOL_Pos (21UL) /*!< SWPOL (Bit 21) */
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#define PWM_SYNCONF_SWPOL_Msk (0x200000UL) /*!< SWPOL (Bitfield-Mask: 0x01) */
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#define PWM_SYNCONF_HWPOL_Pos (22UL) /*!< HWPOL (Bit 22) */
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#define PWM_SYNCONF_HWPOL_Msk (0x400000UL) /*!< HWPOL (Bitfield-Mask: 0x01) */
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/* ========================================================= INVCR ========================================================= */
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#define PWM_INVCR_PAIR0INVEN_Pos (0UL) /*!< PAIR0INVEN (Bit 0) */
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#define PWM_INVCR_PAIR0INVEN_Msk (0x1UL) /*!< PAIR0INVEN (Bitfield-Mask: 0x01) */
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#define PWM_INVCR_PAIR1INVEN_Pos (1UL) /*!< PAIR1INVEN (Bit 1) */
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#define PWM_INVCR_PAIR1INVEN_Msk (0x2UL) /*!< PAIR1INVEN (Bitfield-Mask: 0x01) */
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#define PWM_INVCR_PAIR2INVEN_Pos (2UL) /*!< PAIR2INVEN (Bit 2) */
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#define PWM_INVCR_PAIR2INVEN_Msk (0x4UL) /*!< PAIR2INVEN (Bitfield-Mask: 0x01) */
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#define PWM_INVCR_PAIR3INVEN_Pos (3UL) /*!< PAIR3INVEN (Bit 3) */
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#define PWM_INVCR_PAIR3INVEN_Msk (0x8UL) /*!< PAIR3INVEN (Bitfield-Mask: 0x01) */
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/* ======================================================== CHOSWCR ======================================================== */
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#define PWM_CHOSWCR_CHNSWEN_MASK (0xFFUL) /*!< Channnel output enable Mask */
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#define PWM_CHOSWCR_CH0SWEN_Pos (0UL) /*!< CH0SWEN (Bit 0) */
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#define PWM_CHOSWCR_CH0SWEN_Msk (0x1UL) /*!< CH0SWEN (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH1SWEN_Pos (1UL) /*!< CH1SWEN (Bit 1) */
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#define PWM_CHOSWCR_CH1SWEN_Msk (0x2UL) /*!< CH1SWEN (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH2SWEN_Pos (2UL) /*!< CH2SWEN (Bit 2) */
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#define PWM_CHOSWCR_CH2SWEN_Msk (0x4UL) /*!< CH2SWEN (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH3SWEN_Pos (3UL) /*!< CH3SWEN (Bit 3) */
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#define PWM_CHOSWCR_CH3SWEN_Msk (0x8UL) /*!< CH3SWEN (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH4SWEN_Pos (4UL) /*!< CH4SWEN (Bit 4) */
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#define PWM_CHOSWCR_CH4SWEN_Msk (0x10UL) /*!< CH4SWEN (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH5SWEN_Pos (5UL) /*!< CH5SWEN (Bit 5) */
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#define PWM_CHOSWCR_CH5SWEN_Msk (0x20UL) /*!< CH5SWEN (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH6SWEN_Pos (6UL) /*!< CH6SWEN (Bit 6) */
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#define PWM_CHOSWCR_CH6SWEN_Msk (0x40UL) /*!< CH6SWEN (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH7SWEN_Pos (7UL) /*!< CH7SWEN (Bit 7) */
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#define PWM_CHOSWCR_CH7SWEN_Msk (0x80UL) /*!< CH7SWEN (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH0SWCV_Pos (8UL) /*!< CH0SWCV (Bit 8) */
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#define PWM_CHOSWCR_CH0SWCV_Msk (0x100UL) /*!< CH0SWCV (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH1SWCV_Pos (9UL) /*!< CH1SWCV (Bit 9) */
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#define PWM_CHOSWCR_CH1SWCV_Msk (0x200UL) /*!< CH1SWCV (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH2SWCV_Pos (10UL) /*!< CH2SWCV (Bit 10) */
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#define PWM_CHOSWCR_CH2SWCV_Msk (0x400UL) /*!< CH2SWCV (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH3SWCV_Pos (11UL) /*!< CH3SWCV (Bit 11) */
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#define PWM_CHOSWCR_CH3SWCV_Msk (0x800UL) /*!< CH3SWCV (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH4SWCV_Pos (12UL) /*!< CH4SWCV (Bit 12) */
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#define PWM_CHOSWCR_CH4SWCV_Msk (0x1000UL) /*!< CH4SWCV (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH5SWCV_Pos (13UL) /*!< CH5SWCV (Bit 13) */
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#define PWM_CHOSWCR_CH5SWCV_Msk (0x2000UL) /*!< CH5SWCV (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH6SWCV_Pos (14UL) /*!< CH6SWCV (Bit 14) */
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#define PWM_CHOSWCR_CH6SWCV_Msk (0x4000UL) /*!< CH6SWCV (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CH7SWCV_Pos (15UL) /*!< CH7SWCV (Bit 15) */
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#define PWM_CHOSWCR_CH7SWCV_Msk (0x8000UL) /*!< CH7SWCV (Bitfield-Mask: 0x01) */
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#define PWM_CHOSWCR_CHNSWCV_MASK (0xFF00UL) /*!< Channnel outut value Mask */
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/* ======================================================== DITHER0 ======================================================== */
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#define PWM_DITHER0_C0DHR_Pos (0UL) /*!< C0DHR (Bit 0) */
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#define PWM_DITHER0_C0DHR_Msk (0x1fUL) /*!< C0DHR (Bitfield-Mask: 0x1f) */
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#define PWM_DITHER0_C1DHR_Pos (8UL) /*!< C1DHR (Bit 8) */
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#define PWM_DITHER0_C1DHR_Msk (0x1f00UL) /*!< C1DHR (Bitfield-Mask: 0x1f) */
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#define PWM_DITHER0_C2DHR_Pos (16UL) /*!< C2DHR (Bit 16) */
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#define PWM_DITHER0_C2DHR_Msk (0x1f0000UL) /*!< C2DHR (Bitfield-Mask: 0x1f) */
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#define PWM_DITHER0_C3DHR_Pos (24UL) /*!< C3DHR (Bit 24) */
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#define PWM_DITHER0_C3DHR_Msk (0x1f000000UL) /*!< C3DHR (Bitfield-Mask: 0x1f) */
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#define PWM_DITHER_VALUE_WIDTH (8UL) /*!< Channel Dither Value */
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/* ======================================================== DITHER1 ======================================================== */
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#define PWM_DITHER1_C4DHR_Pos (0UL) /*!< C4DHR (Bit 0) */
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#define PWM_DITHER1_C4DHR_Msk (0x1fUL) /*!< C4DHR (Bitfield-Mask: 0x1f) */
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#define PWM_DITHER1_C5DHR_Pos (8UL) /*!< C5DHR (Bit 8) */
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#define PWM_DITHER1_C5DHR_Msk (0x1f00UL) /*!< C5DHR (Bitfield-Mask: 0x1f) */
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#define PWM_DITHER1_C6DHR_Pos (16UL) /*!< C6DHR (Bit 16) */
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#define PWM_DITHER1_C6DHR_Msk (0x1f0000UL) /*!< C6DHR (Bitfield-Mask: 0x1f) */
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#define PWM_DITHER1_C7DHR_Pos (24UL) /*!< C7DHR (Bit 24) */
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#define PWM_DITHER1_C7DHR_Msk (0x1f000000UL) /*!< C7DHR (Bitfield-Mask: 0x1f) */
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/* ======================================================== DITHER2 ======================================================== */
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#define PWM_DITHER2_PDHR_Pos (0UL) /*!< PDHR (Bit 0) */
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#define PWM_DITHER2_PDHR_Msk (0x1fUL) /*!< PDHR (Bitfield-Mask: 0x1f) */
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#define PWM_DITHER2_DEBUGCTRL_Pos (30UL) /*!< DEBUGCTRL (Bit 30) */
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#define PWM_DITHER2_DEBUGCTRL_Msk (0xc0000000UL) /*!< DEBUGCTRL (Bitfield-Mask: 0x03) */
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/* ======================================================== DMACTRL ======================================================== */
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#define PWM_DMACTRL_TRANS_LEN_Pos (0UL) /*!< TRANS_LEN (Bit 0) */
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#define PWM_DMACTRL_TRANS_LEN_Msk (0x1fUL) /*!< TRANS_LEN (Bitfield-Mask: 0x1f) */
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#define PWM_DMACTRL_TRANS_EN_Pos (7UL) /*!< TRANS_EN (Bit 7) */
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#define PWM_DMACTRL_TRANS_EN_Msk (0x80UL) /*!< TRANS_EN (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
|
|
/* ================ PDT ================ */
|
|
/* =========================================================================================================================== */
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|
|
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/* ========================================================== SC =========================================================== */
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|
#define PDT_SC_MULT_Pos (0UL) /*!< MULT (Bit 0) */
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#define PDT_SC_MULT_Msk (0x3UL) /*!< MULT (Bitfield-Mask: 0x03) */
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#define PDT_SC_PRE_Pos (2UL) /*!< PRE (Bit 2) */
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#define PDT_SC_PRE_Msk (0x1cUL) /*!< PRE (Bitfield-Mask: 0x07) */
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#define PDT_SC_CONT_Pos (5UL) /*!< CONT (Bit 5) */
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#define PDT_SC_CONT_Msk (0x20UL) /*!< CONT (Bitfield-Mask: 0x01) */
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#define PDT_SC_LDOK_Pos (6UL) /*!< LDOK (Bit 6) */
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#define PDT_SC_LDOK_Msk (0x40UL) /*!< LDOK (Bitfield-Mask: 0x01) */
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#define PDT_SC_LDMOD_Pos (7UL) /*!< LDMOD (Bit 7) */
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#define PDT_SC_LDMOD_Msk (0x180UL) /*!< LDMOD (Bitfield-Mask: 0x03) */
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#define PDT_SC_PDTIE_Pos (9UL) /*!< PDTIE (Bit 9) */
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#define PDT_SC_PDTIE_Msk (0x200UL) /*!< PDTIE (Bitfield-Mask: 0x01) */
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#define PDT_SC_PDTIF_Pos (10UL) /*!< PDTIF (Bit 10) */
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#define PDT_SC_PDTIF_Msk (0x400UL) /*!< PDTIF (Bitfield-Mask: 0x01) */
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#define PDT_SC_PDTEN_Pos (11UL) /*!< PDTEN (Bit 11) */
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#define PDT_SC_PDTEN_Msk (0x800UL) /*!< PDTEN (Bitfield-Mask: 0x01) */
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#define PDT_SC_SWTRIG_Pos (12UL) /*!< SWTRIG (Bit 12) */
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#define PDT_SC_SWTRIG_Msk (0x1000UL) /*!< SWTRIG (Bitfield-Mask: 0x01) */
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#define PDT_SC_TRGSEL_Pos (13UL) /*!< TRGSEL (Bit 13) */
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#define PDT_SC_TRGSEL_Msk (0x2000UL) /*!< TRGSEL (Bitfield-Mask: 0x01) */
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#define PDT_SC_Bypass_En_Pos (14UL) /*!< Bypass_En (Bit 14) */
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#define PDT_SC_Bypass_En_Msk (0x4000UL) /*!< Bypass_En (Bitfield-Mask: 0x01) */
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/* ========================================================== MOD ========================================================== */
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|
#define PDT_MOD_MOD_Pos (0UL) /*!< MOD (Bit 0) */
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#define PDT_MOD_MOD_Msk (0xffffUL) /*!< MOD (Bitfield-Mask: 0xffff) */
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/* ========================================================= DLY0 ========================================================== */
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|
#define PDT_DLY0_DLY0_Pos (0UL) /*!< DLY0 (Bit 0) */
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#define PDT_DLY0_DLY0_Msk (0xffffUL) /*!< DLY0 (Bitfield-Mask: 0xffff) */
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/* ========================================================= DLY1 ========================================================== */
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|
#define PDT_DLY1_DLY1_Pos (0UL) /*!< DLY1 (Bit 0) */
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#define PDT_DLY1_DLY1_Msk (0xffffUL) /*!< DLY1 (Bitfield-Mask: 0xffff) */
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/* ========================================================= DLY2 ========================================================== */
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|
#define PDT_DLY2_DLY2_Pos (0UL) /*!< DLY2 (Bit 0) */
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#define PDT_DLY2_DLY2_Msk (0xffffUL) /*!< DLY2 (Bitfield-Mask: 0xffff) */
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/* ========================================================= DLY3 ========================================================== */
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#define PDT_DLY3_DLY3_Pos (0UL) /*!< DLY3 (Bit 0) */
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#define PDT_DLY3_DLY3_Msk (0xffffUL) /*!< DLY3 (Bitfield-Mask: 0xffff) */
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/* ========================================================= DLY4 ========================================================== */
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#define PDT_DLY4_DLY4_Pos (0UL) /*!< DLY4 (Bit 0) */
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#define PDT_DLY4_DLY4_Msk (0xffffUL) /*!< DLY4 (Bitfield-Mask: 0xffff) */
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/* ========================================================= DLY5 ========================================================== */
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#define PDT_DLY5_DLY5_Pos (0UL) /*!< DLY5 (Bit 0) */
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#define PDT_DLY5_DLY5_Msk (0xffffUL) /*!< DLY5 (Bitfield-Mask: 0xffff) */
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/* ========================================================= DLY6 ========================================================== */
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#define PDT_DLY6_DLY6_Pos (0UL) /*!< DLY6 (Bit 0) */
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#define PDT_DLY6_DLY6_Msk (0xffffUL) /*!< DLY6 (Bitfield-Mask: 0xffff) */
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/* ========================================================= DLY7 ========================================================== */
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#define PDT_DLY7_DLY7_Pos (0UL) /*!< DLY7 (Bit 0) */
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#define PDT_DLY7_DLY7_Msk (0xffffUL) /*!< DLY7 (Bitfield-Mask: 0xffff) */
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/* ========================================================= IDLY ========================================================== */
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#define PDT_IDLY_IDLY_Pos (0UL) /*!< IDLY (Bit 0) */
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#define PDT_IDLY_IDLY_Msk (0xffffUL) /*!< IDLY (Bitfield-Mask: 0xffff) */
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/* ========================================================= PODLY ========================================================= */
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#define PDT_PODLY_PODLY1_Pos (0UL) /*!< PODLY1 (Bit 0) */
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#define PDT_PODLY_PODLY1_Msk (0xffffUL) /*!< PODLY1 (Bitfield-Mask: 0xffff) */
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#define PDT_PODLY_PODLY2_Pos (16UL) /*!< PODLY2 (Bit 16) */
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#define PDT_PODLY_PODLY2_Msk (0xffff0000UL) /*!< PODLY2 (Bitfield-Mask: 0xffff) */
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/* ======================================================== DLYn_EN ======================================================== */
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#define PDT_DLYn_EN_DLY0_En_Pos (0UL) /*!< DLY0_En (Bit 0) */
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#define PDT_DLYn_EN_DLY0_En_Msk (0x1UL) /*!< DLY0_En (Bitfield-Mask: 0x01) */
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#define PDT_DLYn_EN_DLY1_En_Pos (1UL) /*!< DLY1_En (Bit 1) */
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#define PDT_DLYn_EN_DLY1_En_Msk (0x2UL) /*!< DLY1_En (Bitfield-Mask: 0x01) */
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#define PDT_DLYn_EN_DLY2_En_Pos (2UL) /*!< DLY2_En (Bit 2) */
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#define PDT_DLYn_EN_DLY2_En_Msk (0x4UL) /*!< DLY2_En (Bitfield-Mask: 0x01) */
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#define PDT_DLYn_EN_DLY3_En_Pos (3UL) /*!< DLY3_En (Bit 3) */
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#define PDT_DLYn_EN_DLY3_En_Msk (0x8UL) /*!< DLY3_En (Bitfield-Mask: 0x01) */
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#define PDT_DLYn_EN_DLY4_En_Pos (4UL) /*!< DLY4_En (Bit 4) */
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#define PDT_DLYn_EN_DLY4_En_Msk (0x10UL) /*!< DLY4_En (Bitfield-Mask: 0x01) */
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#define PDT_DLYn_EN_DLY5_En_Pos (5UL) /*!< DLY5_En (Bit 5) */
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#define PDT_DLYn_EN_DLY5_En_Msk (0x20UL) /*!< DLY5_En (Bitfield-Mask: 0x01) */
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#define PDT_DLYn_EN_DLY6_En_Pos (6UL) /*!< DLY6_En (Bit 6) */
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#define PDT_DLYn_EN_DLY6_En_Msk (0x40UL) /*!< DLY6_En (Bitfield-Mask: 0x01) */
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#define PDT_DLYn_EN_DLY7_En_Pos (7UL) /*!< DLY7_En (Bit 7) */
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#define PDT_DLYn_EN_DLY7_En_Msk (0x80UL) /*!< DLY7_En (Bitfield-Mask: 0x01) */
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#define PDT_DLY_EN_Msk (0xFFUL) /*!< DLY_En (Bitfield-Mask: 0xFF) */
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/* ========================================================= POEN ========================================================== */
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#define PDT_POEN_POEN_Pos (0UL) /*!< POEN (Bit 0) */
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#define PDT_POEN_POEN_Msk (0x1UL) /*!< POEN (Bitfield-Mask: 0x01) */
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/* ========================================================== CNT ========================================================== */
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#define PDT_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */
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#define PDT_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */
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/* =========================================================================================================================== */
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/* ================ TIMER_CTRL ================ */
|
|
/* =========================================================================================================================== */
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|
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/* ========================================================== MCR ========================================================== */
|
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#define TIMER_CTRL_CR_MC_EN_Pos (0UL) /*!< MC_EN (Bit 0) */
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#define TIMER_CTRL_CR_MC_EN_Msk (0x1UL) /*!< MC_EN (Bitfield-Mask: 0x01) */
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#define TIMER_CTRL_CR_DBG_EN_Pos (1UL) /*!< DBG_EN (Bit 1) */
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#define TIMER_CTRL_CR_DBG_EN_Msk (0x2UL) /*!< DBG_EN (Bitfield-Mask: 0x01) */
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#define TIMER_CTRL_CR_TBUS_EN_Pos (4UL) /*!< TBUS_EN (Bit 4) */
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#define TIMER_CTRL_CR_TBUS_EN_Msk (0x10UL) /*!< TBUS_EN (Bitfield-Mask: 0x01) */
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/* ========================================================== SR =========================================================== */
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#define TIMER_CTRL_SR_TIF0_Pos (0UL) /*!< TIF0 (Bit 0) */
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#define TIMER_CTRL_SR_TIF0_Msk (0x1UL) /*!< TIF0 (Bitfield-Mask: 0x01) */
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#define TIMER_CTRL_SR_TIF1_Pos (1UL) /*!< TIF1 (Bit 1) */
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#define TIMER_CTRL_SR_TIF1_Msk (0x2UL) /*!< TIF1 (Bitfield-Mask: 0x01) */
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#define TIMER_CTRL_SR_TIF2_Pos (2UL) /*!< TIF2 (Bit 2) */
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#define TIMER_CTRL_SR_TIF2_Msk (0x4UL) /*!< TIF2 (Bitfield-Mask: 0x01) */
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#define TIMER_CTRL_SR_TIF3_Pos (3UL) /*!< TIF3 (Bit 3) */
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#define TIMER_CTRL_SR_TIF3_Msk (0x8UL) /*!< TIF3 (Bitfield-Mask: 0x01) */
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/* ========================================================== IER ========================================================== */
|
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#define TIMER_CTRL_IER_TIE0_Pos (0UL) /*!< TIE0 (Bit 0) */
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#define TIMER_CTRL_IER_TIE0_Msk (0x1UL) /*!< TIE0 (Bitfield-Mask: 0x01) */
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#define TIMER_CTRL_IER_TIE1_Pos (1UL) /*!< TIE1 (Bit 1) */
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#define TIMER_CTRL_IER_TIE1_Msk (0x2UL) /*!< TIE1 (Bitfield-Mask: 0x01) */
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#define TIMER_CTRL_IER_TIE2_Pos (2UL) /*!< TIE2 (Bit 2) */
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#define TIMER_CTRL_IER_TIE2_Msk (0x4UL) /*!< TIE2 (Bitfield-Mask: 0x01) */
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#define TIMER_CTRL_IER_TIE3_Pos (3UL) /*!< TIE3 (Bit 3) */
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#define TIMER_CTRL_IER_TIE3_Msk (0x8UL) /*!< TIE3 (Bitfield-Mask: 0x01) */
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/* ========================================================== ENR ========================================================== */
|
|
#define TIMER_CTRL_ENR_TEN0_Pos (0UL) /*!< TEN0 (Bit 0) */
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#define TIMER_CTRL_ENR_TEN0_Msk (0x1UL) /*!< TEN0 (Bitfield-Mask: 0x01) */
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#define TIMER_CTRL_ENR_TEN1_Pos (1UL) /*!< TEN1 (Bit 1) */
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#define TIMER_CTRL_ENR_TEN1_Msk (0x2UL) /*!< TEN1 (Bitfield-Mask: 0x01) */
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#define TIMER_CTRL_ENR_TEN2_Pos (2UL) /*!< TEN2 (Bit 2) */
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#define TIMER_CTRL_ENR_TEN2_Msk (0x4UL) /*!< TEN2 (Bitfield-Mask: 0x01) */
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#define TIMER_CTRL_ENR_TEN3_Pos (3UL) /*!< TEN3 (Bit 3) */
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#define TIMER_CTRL_ENR_TEN3_Msk (0x8UL) /*!< TEN3 (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
|
|
/* ================ TIMER_CHANNEL ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================= TVAL ========================================================== */
|
|
#define TIMER_CHANNEL_TVAL_TVAL_Pos (0UL) /*!< TVAL (Bit 0) */
|
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#define TIMER_CHANNEL_TVAL_TVAL_Msk (0xffffffffUL) /*!< TVAL (Bitfield-Mask: 0xffffffff) */
|
|
/* ========================================================= CVAL ========================================================== */
|
|
#define TIMER_CHANNEL_CVAL_CVAL_Pos (0UL) /*!< CVAL (Bit 0) */
|
|
#define TIMER_CHANNEL_CVAL_CVAL_Msk (0xffffffffUL) /*!< CVAL (Bitfield-Mask: 0xffffffff) */
|
|
/* ========================================================= CTRL ========================================================== */
|
|
#define TIMER_CHANNEL_CTRL_CHN_EN_Pos (0UL) /*!< CHN_EN (Bit 0) */
|
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#define TIMER_CHANNEL_CTRL_CHN_EN_Msk (0x1UL) /*!< CHN_EN (Bitfield-Mask: 0x01) */
|
|
#define TIMER_CHANNEL_CTRL_TVAL_UP_Pos (1UL) /*!< TVAL_UP (Bit 1) */
|
|
#define TIMER_CHANNEL_CTRL_TVAL_UP_Msk (0x2UL) /*!< TVAL_UP (Bitfield-Mask: 0x01) */
|
|
#define TIMER_CHANNEL_CTRL_CVAL_SEL_Pos (2UL) /*!< CVAL_SEL (Bit 2) */
|
|
#define TIMER_CHANNEL_CTRL_CVAL_SEL_Msk (0xcUL) /*!< CVAL_SEL (Bitfield-Mask: 0x03) */
|
|
#define TIMER_CHANNEL_CTRL_MODE_Pos (4UL) /*!< MODE (Bit 4) */
|
|
#define TIMER_CHANNEL_CTRL_MODE_Msk (0x30UL) /*!< MODE (Bitfield-Mask: 0x03) */
|
|
#define TIMER_CHANNEL_CTRL_TSOT_Pos (8UL) /*!< TSOT (Bit 8) */
|
|
#define TIMER_CHANNEL_CTRL_TSOT_Msk (0x100UL) /*!< TSOT (Bitfield-Mask: 0x01) */
|
|
#define TIMER_CHANNEL_CTRL_TSOI_Pos (9UL) /*!< TSOI (Bit 9) */
|
|
#define TIMER_CHANNEL_CTRL_TSOI_Msk (0x200UL) /*!< TSOI (Bitfield-Mask: 0x01) */
|
|
#define TIMER_CHANNEL_CTRL_TROT_Pos (10UL) /*!< TROT (Bit 10) */
|
|
#define TIMER_CHANNEL_CTRL_TROT_Msk (0x400UL) /*!< TROT (Bitfield-Mask: 0x01) */
|
|
#define TIMER_CHANNEL_CTRL_TTRG_SEL_Pos (12UL) /*!< TTRG_SEL (Bit 12) */
|
|
#define TIMER_CHANNEL_CTRL_TTRG_SEL_Msk (0xf000UL) /*!< TTRG_SEL (Bitfield-Mask: 0x0f) */
|
|
#define TIMER_CHANNEL_CTRL_TRG_SRC_Pos (16UL) /*!< TRG_SRC (Bit 16) */
|
|
#define TIMER_CHANNEL_CTRL_TRG_SRC_Msk (0x10000UL) /*!< TRG_SRC (Bitfield-Mask: 0x01) */
|
|
|
|
|
|
/* =========================================================================================================================== */
|
|
/* ================ PCT ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================== CSR ========================================================== */
|
|
#define PCT_CSR_PCT_EN_Pos (0UL) /*!< PCT_EN (Bit 0) */
|
|
#define PCT_CSR_PCT_EN_Msk (0x1UL) /*!< PCT_EN (Bitfield-Mask: 0x01) */
|
|
#define PCT_CSR_MS_Pos (1UL) /*!< MS (Bit 1) */
|
|
#define PCT_CSR_MS_Msk (0x2UL) /*!< MS (Bitfield-Mask: 0x01) */
|
|
#define PCT_CSR_FRE_Pos (2UL) /*!< FRE (Bit 2) */
|
|
#define PCT_CSR_FRE_Msk (0x4UL) /*!< FRE (Bitfield-Mask: 0x01) */
|
|
#define PCT_CSR_PPS_Pos (3UL) /*!< PPS (Bit 3) */
|
|
#define PCT_CSR_PPS_Msk (0x8UL) /*!< PPS (Bitfield-Mask: 0x01) */
|
|
#define PCT_CSR_IPS_Pos (4UL) /*!< IPS (Bit 4) */
|
|
#define PCT_CSR_IPS_Msk (0x30UL) /*!< IPS (Bitfield-Mask: 0x03) */
|
|
#define PCT_CSR_CIE_Pos (6UL) /*!< CIE (Bit 6) */
|
|
#define PCT_CSR_CIE_Msk (0x40UL) /*!< CIE (Bitfield-Mask: 0x01) */
|
|
#define PCT_CSR_TB_EN_Pos (7UL) /*!< TB_EN (Bit 7) */
|
|
#define PCT_CSR_TB_EN_Msk (0x80UL) /*!< TB_EN (Bitfield-Mask: 0x01) */
|
|
#define PCT_CSR_CF_Pos (8UL) /*!< CF (Bit 8) */
|
|
#define PCT_CSR_CF_Msk (0x100UL) /*!< CF (Bitfield-Mask: 0x01) */
|
|
/* ========================================================== PSR ========================================================== */
|
|
#define PCT_PSR_PCS_Pos (0UL) /*!< PCS (Bit 0) */
|
|
#define PCT_PSR_PCS_Msk (0x3UL) /*!< PCS (Bitfield-Mask: 0x03) */
|
|
#define PCT_PSR_CVAL_SEL_Pos (2UL) /*!< CVAL_SEL (Bit 2) */
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#define PCT_PSR_CVAL_SEL_Msk (0xcUL) /*!< CVAL_SEL (Bitfield-Mask: 0x03) */
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#define PCT_PSR_PS_VAL_Pos (4UL) /*!< PS_VAL (Bit 4) */
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#define PCT_PSR_PS_VAL_Msk (0xf0UL) /*!< PS_VAL (Bitfield-Mask: 0x0f) */
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#define PCT_PSR_BYP_Pos (8UL) /*!< BYP (Bit 8) */
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#define PCT_PSR_BYP_Msk (0x100UL) /*!< BYP (Bitfield-Mask: 0x01) */
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/* ========================================================== CMR ========================================================== */
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#define PCT_CMR_CMR_Pos (0UL) /*!< CMR (Bit 0) */
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#define PCT_CMR_CMR_Msk (0xffffUL) /*!< CMR (Bitfield-Mask: 0xffff) */
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/* ========================================================== CNR ========================================================== */
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#define PCT_CNR_CNR_Pos (0UL) /*!< CNR (Bit 0) */
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#define PCT_CNR_CNR_Msk (0xffffUL) /*!< CNR (Bitfield-Mask: 0xffff) */
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/* =========================================================================================================================== */
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/* ================ CTU ================ */
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/* =========================================================================================================================== */
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#define CTU_TRGMUX_SEL_Msk (0x7fUL)
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#define CTU_TRGMUX_SEL_SHIFT (8UL)
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/* ====================================================== TRGMUX_DMA ======================================================= */
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#define CTU_TRGMUX_DMA_SEL_DMA_CH0_Pos (0UL) /*!< SEL_DMA_CH0 (Bit 0) */
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#define CTU_TRGMUX_DMA_SEL_DMA_CH0_Msk (0x7fUL) /*!< SEL_DMA_CH0 (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_DMA_SEL_DMA_CH1_Pos (8UL) /*!< SEL_DMA_CH1 (Bit 8) */
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#define CTU_TRGMUX_DMA_SEL_DMA_CH1_Msk (0x7f00UL) /*!< SEL_DMA_CH1 (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_DMA_SEL_DMA_CH2_Pos (16UL) /*!< SEL_DMA_CH2 (Bit 16) */
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#define CTU_TRGMUX_DMA_SEL_DMA_CH2_Msk (0x7f0000UL) /*!< SEL_DMA_CH2 (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_DMA_SEL_DMA_CH3_Pos (24UL) /*!< SEL_DMA_CH3 (Bit 24) */
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#define CTU_TRGMUX_DMA_SEL_DMA_CH3_Msk (0x7f000000UL) /*!< SEL_DMA_CH3 (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_DMA_LK1_Pos (31UL) /*!< LK1 (Bit 31) */
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#define CTU_TRGMUX_DMA_LK1_Msk (0x80000000UL) /*!< LK1 (Bitfield-Mask: 0x01) */
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/* ==================================================== TRGMUX_EXTOUT0 ===================================================== */
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#define CTU_TRGMUX_EXTOUT0_SEL_EXT_OUT0_TR_Pos (0UL) /*!< SEL_EXT_OUT0_TR (Bit 0) */
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#define CTU_TRGMUX_EXTOUT0_SEL_EXT_OUT0_TR_Msk (0x7fUL) /*!< SEL_EXT_OUT0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_EXTOUT0_SEL_EXT_OUT1_TR_Pos (8UL) /*!< SEL_EXT_OUT1_TR (Bit 8) */
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#define CTU_TRGMUX_EXTOUT0_SEL_EXT_OUT1_TR_Msk (0x7f00UL) /*!< SEL_EXT_OUT1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_EXTOUT0_SEL_EXT_OUT2_TR_Pos (16UL) /*!< SEL_EXT_OUT2_TR (Bit 16) */
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#define CTU_TRGMUX_EXTOUT0_SEL_EXT_OUT2_TR_Msk (0x7f0000UL) /*!< SEL_EXT_OUT2_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_EXTOUT0_SEL_EXT_OUT3_TR_Pos (24UL) /*!< SEL_EXT_OUT3_TR (Bit 24) */
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#define CTU_TRGMUX_EXTOUT0_SEL_EXT_OUT3_TR_Msk (0x7f000000UL) /*!< SEL_EXT_OUT3_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_EXTOUT0_LK2_Pos (31UL) /*!< LK2 (Bit 31) */
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#define CTU_TRGMUX_EXTOUT0_LK2_Msk (0x80000000UL) /*!< LK2 (Bitfield-Mask: 0x01) */
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/* ==================================================== TRGMUX_EXTOUT1 ===================================================== */
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#define CTU_TRGMUX_EXTOUT1_SEL_EXT_OUT4_TR_Pos (0UL) /*!< SEL_EXT_OUT4_TR (Bit 0) */
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#define CTU_TRGMUX_EXTOUT1_SEL_EXT_OUT4_TR_Msk (0x7fUL) /*!< SEL_EXT_OUT4_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_EXTOUT1_SEL_EXT_OUT5_TR_Pos (8UL) /*!< SEL_EXT_OUT5_TR (Bit 8) */
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#define CTU_TRGMUX_EXTOUT1_SEL_EXT_OUT5_TR_Msk (0x7f00UL) /*!< SEL_EXT_OUT5_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_EXTOUT1_SEL_EXT_OUT6_TR_Pos (16UL) /*!< SEL_EXT_OUT6_TR (Bit 16) */
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#define CTU_TRGMUX_EXTOUT1_SEL_EXT_OUT6_TR_Msk (0x7f0000UL) /*!< SEL_EXT_OUT6_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_EXTOUT1_SEL_EXT_OUT7_TR_Pos (24UL) /*!< SEL_EXT_OUT7_TR (Bit 24) */
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#define CTU_TRGMUX_EXTOUT1_SEL_EXT_OUT7_TR_Msk (0x7f000000UL) /*!< SEL_EXT_OUT7_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_EXTOUT1_LK3_Pos (31UL) /*!< LK3 (Bit 31) */
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#define CTU_TRGMUX_EXTOUT1_LK3_Msk (0x80000000UL) /*!< LK3 (Bitfield-Mask: 0x01) */
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/* ==================================================== TRGMUX_ADC0_REG ==================================================== */
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#define CTU_TRGMUX_ADC0_REG_SEL_ADC0_REGULAR0_TR_Pos (0UL) /*!< SEL_ADC0_REGULAR0_TR (Bit 0) */
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#define CTU_TRGMUX_ADC0_REG_SEL_ADC0_REGULAR0_TR_Msk (0x7fUL) /*!< SEL_ADC0_REGULAR0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC0_REG_SEL_ADC0_REGULAR1_TR_Pos (8UL) /*!< SEL_ADC0_REGULAR1_TR (Bit 8) */
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#define CTU_TRGMUX_ADC0_REG_SEL_ADC0_REGULAR1_TR_Msk (0x7f00UL) /*!< SEL_ADC0_REGULAR1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC0_REG_SEL_ADC0_REGULAR2_TR_Pos (16UL) /*!< SEL_ADC0_REGULAR2_TR (Bit 16) */
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#define CTU_TRGMUX_ADC0_REG_SEL_ADC0_REGULAR2_TR_Msk (0x7f0000UL) /*!< SEL_ADC0_REGULAR2_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC0_REG_SEL_ADC0_REGULAR3_TR_Pos (24UL) /*!< SEL_ADC0_REGULAR3_TR (Bit 24) */
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#define CTU_TRGMUX_ADC0_REG_SEL_ADC0_REGULAR3_TR_Msk (0x7f000000UL) /*!< SEL_ADC0_REGULAR3_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC0_REG_LK4_Pos (31UL) /*!< LK4 (Bit 31) */
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#define CTU_TRGMUX_ADC0_REG_LK4_Msk (0x80000000UL) /*!< LK4 (Bitfield-Mask: 0x01) */
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/* ==================================================== TRGMUX_ADC0_INJ ==================================================== */
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#define CTU_TRGMUX_ADC0_INJ_SEL_ADC0_INJECTION0_TR_Pos (0UL) /*!< SEL_ADC0_INJECTION0_TR (Bit 0) */
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#define CTU_TRGMUX_ADC0_INJ_SEL_ADC0_INJECTION0_TR_Msk (0x7fUL) /*!< SEL_ADC0_INJECTION0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC0_INJ_SEL_ADC0_INJECTION1_TR_Pos (8UL) /*!< SEL_ADC0_INJECTION1_TR (Bit 8) */
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#define CTU_TRGMUX_ADC0_INJ_SEL_ADC0_INJECTION1_TR_Msk (0x7f00UL) /*!< SEL_ADC0_INJECTION1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC0_INJ_SEL_ADC0_INJECTION2_TR_Pos (16UL) /*!< SEL_ADC0_INJECTION2_TR (Bit 16) */
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#define CTU_TRGMUX_ADC0_INJ_SEL_ADC0_INJECTION2_TR_Msk (0x7f0000UL) /*!< SEL_ADC0_INJECTION2_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC0_INJ_SEL_ADC0_INJECTION3_TR_Pos (24UL) /*!< SEL_ADC0_INJECTION3_TR (Bit 24) */
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#define CTU_TRGMUX_ADC0_INJ_SEL_ADC0_INJECTION3_TR_Msk (0x7f000000UL) /*!< SEL_ADC0_INJECTION3_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC0_INJ_LK5_Pos (31UL) /*!< LK5 (Bit 31) */
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#define CTU_TRGMUX_ADC0_INJ_LK5_Msk (0x80000000UL) /*!< LK5 (Bitfield-Mask: 0x01) */
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/* ==================================================== TRGMUX_ADC1_REG ==================================================== */
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#define CTU_TRGMUX_ADC1_REG_SEL_ADC1_REGULAR0_TR_Pos (0UL) /*!< SEL_ADC1_REGULAR0_TR (Bit 0) */
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#define CTU_TRGMUX_ADC1_REG_SEL_ADC1_REGULAR0_TR_Msk (0x7fUL) /*!< SEL_ADC1_REGULAR0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC1_REG_SEL_ADC1_REGULAR1_TR_Pos (8UL) /*!< SEL_ADC1_REGULAR1_TR (Bit 8) */
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#define CTU_TRGMUX_ADC1_REG_SEL_ADC1_REGULAR1_TR_Msk (0x7f00UL) /*!< SEL_ADC1_REGULAR1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC1_REG_SEL_ADC1_REGULAR2_TR_Pos (16UL) /*!< SEL_ADC1_REGULAR2_TR (Bit 16) */
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#define CTU_TRGMUX_ADC1_REG_SEL_ADC1_REGULAR2_TR_Msk (0x7f0000UL) /*!< SEL_ADC1_REGULAR2_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC1_REG_SEL_ADC1_REGULAR3_TR_Pos (24UL) /*!< SEL_ADC1_REGULAR3_TR (Bit 24) */
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#define CTU_TRGMUX_ADC1_REG_SEL_ADC1_REGULAR3_TR_Msk (0x7f000000UL) /*!< SEL_ADC1_REGULAR3_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC1_REG_LK6_Pos (31UL) /*!< LK6 (Bit 31) */
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#define CTU_TRGMUX_ADC1_REG_LK6_Msk (0x80000000UL) /*!< LK6 (Bitfield-Mask: 0x01) */
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/* ==================================================== TRGMUX_ADC1_INJ ==================================================== */
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#define CTU_TRGMUX_ADC1_INJ_SEL_ADC1_INJECTION0_TR_Pos (0UL) /*!< SEL_ADC1_INJECTION0_TR (Bit 0) */
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#define CTU_TRGMUX_ADC1_INJ_SEL_ADC1_INJECTION0_TR_Msk (0x7fUL) /*!< SEL_ADC1_INJECTION0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC1_INJ_SEL_ADC1_INJECTION1_TR_Pos (8UL) /*!< SEL_ADC1_INJECTION1_TR (Bit 8) */
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#define CTU_TRGMUX_ADC1_INJ_SEL_ADC1_INJECTION1_TR_Msk (0x7f00UL) /*!< SEL_ADC1_INJECTION1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC1_INJ_SEL_ADC1_INJECTION2_TR_Pos (16UL) /*!< SEL_ADC1_INJECTION2_TR (Bit 16) */
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#define CTU_TRGMUX_ADC1_INJ_SEL_ADC1_INJECTION2_TR_Msk (0x7f0000UL) /*!< SEL_ADC1_INJECTION2_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC1_INJ_SEL_ADC1_INJECTION3_TR_Pos (24UL) /*!< SEL_ADC1_INJECTION3_TR (Bit 24) */
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#define CTU_TRGMUX_ADC1_INJ_SEL_ADC1_INJECTION3_TR_Msk (0x7f000000UL) /*!< SEL_ADC1_INJECTION3_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_ADC1_INJ_LK7_Pos (31UL) /*!< LK7 (Bit 31) */
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#define CTU_TRGMUX_ADC1_INJ_LK7_Msk (0x80000000UL) /*!< LK7 (Bitfield-Mask: 0x01) */
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/* ====================================================== TRGMUX_ACMP ====================================================== */
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#define CTU_TRGMUX_ACMP_SEL_ACMP0_TR_Pos (0UL) /*!< SEL_ACMP0_TR (Bit 0) */
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#define CTU_TRGMUX_ACMP_SEL_ACMP0_TR_Msk (0x7fUL) /*!< SEL_ACMP0_TR (Bitfield-Mask: 0x7f) */
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/* ====================================================== TRGMUX_PWM0 ====================================================== */
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#define CTU_TRGMUX_PWM0_SEL_PWM0_TRIG0_TR_Pos (0UL) /*!< SEL_PWM0_TRIG0_TR (Bit 0) */
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#define CTU_TRGMUX_PWM0_SEL_PWM0_TRIG0_TR_Msk (0x7fUL) /*!< SEL_PWM0_TRIG0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM0_SEL_PWM0_FAULT0_TR_Pos (8UL) /*!< SEL_PWM0_FAULT0_TR (Bit 8) */
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#define CTU_TRGMUX_PWM0_SEL_PWM0_FAULT0_TR_Msk (0x7f00UL) /*!< SEL_PWM0_FAULT0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM0_SEL_PWM0_FAULT1_TR_Pos (16UL) /*!< SEL_PWM0_FAULT1_TR (Bit 16) */
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#define CTU_TRGMUX_PWM0_SEL_PWM0_FAULT1_TR_Msk (0x7f0000UL) /*!< SEL_PWM0_FAULT1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM0_SEL_PWM0_FAULT2_TR_Pos (24UL) /*!< SEL_PWM0_FAULT2_TR (Bit 24) */
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#define CTU_TRGMUX_PWM0_SEL_PWM0_FAULT2_TR_Msk (0x7f000000UL) /*!< SEL_PWM0_FAULT2_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM0_LK9_Pos (31UL) /*!< LK9 (Bit 31) */
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#define CTU_TRGMUX_PWM0_LK9_Msk (0x80000000UL) /*!< LK9 (Bitfield-Mask: 0x01) */
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/* ====================================================== TRGMUX_PWM1 ====================================================== */
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#define CTU_TRGMUX_PWM1_SEL_PWM1_TRIG0_TR_Pos (0UL) /*!< SEL_PWM1_TRIG0_TR (Bit 0) */
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#define CTU_TRGMUX_PWM1_SEL_PWM1_TRIG0_TR_Msk (0x7fUL) /*!< SEL_PWM1_TRIG0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM1_SEL_PWM1_FAULT0_TR_Pos (8UL) /*!< SEL_PWM1_FAULT0_TR (Bit 8) */
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#define CTU_TRGMUX_PWM1_SEL_PWM1_FAULT0_TR_Msk (0x7f00UL) /*!< SEL_PWM1_FAULT0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM1_SEL_PWM1_FAULT1_TR_Pos (16UL) /*!< SEL_PWM1_FAULT1_TR (Bit 16) */
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#define CTU_TRGMUX_PWM1_SEL_PWM1_FAULT1_TR_Msk (0x7f0000UL) /*!< SEL_PWM1_FAULT1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM1_SEL_PWM1_FAULT2_TR_Pos (24UL) /*!< SEL_PWM1_FAULT2_TR (Bit 24) */
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#define CTU_TRGMUX_PWM1_SEL_PWM1_FAULT2_TR_Msk (0x7f000000UL) /*!< SEL_PWM1_FAULT2_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM1_LK10_Pos (31UL) /*!< LK10 (Bit 31) */
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#define CTU_TRGMUX_PWM1_LK10_Msk (0x80000000UL) /*!< LK10 (Bitfield-Mask: 0x01) */
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/* ====================================================== TRGMUX_PWM2 ====================================================== */
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#define CTU_TRGMUX_PWM2_SEL_PWM2_TRIG0_TR_Pos (0UL) /*!< SEL_PWM2_TRIG0_TR (Bit 0) */
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#define CTU_TRGMUX_PWM2_SEL_PWM2_TRIG0_TR_Msk (0x7fUL) /*!< SEL_PWM2_TRIG0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM2_SEL_PWM2_FAULT0_TR_Pos (8UL) /*!< SEL_PWM2_FAULT0_TR (Bit 8) */
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#define CTU_TRGMUX_PWM2_SEL_PWM2_FAULT0_TR_Msk (0x7f00UL) /*!< SEL_PWM2_FAULT0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM2_SEL_PWM2_FAULT1_TR_Pos (16UL) /*!< SEL_PWM2_FAULT1_TR (Bit 16) */
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#define CTU_TRGMUX_PWM2_SEL_PWM2_FAULT1_TR_Msk (0x7f0000UL) /*!< SEL_PWM2_FAULT1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM2_SEL_PWM2_FAULT2_TR_Pos (24UL) /*!< SEL_PWM2_FAULT2_TR (Bit 24) */
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#define CTU_TRGMUX_PWM2_SEL_PWM2_FAULT2_TR_Msk (0x7f000000UL) /*!< SEL_PWM2_FAULT2_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM2_LK11_Pos (31UL) /*!< LK11 (Bit 31) */
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#define CTU_TRGMUX_PWM2_LK11_Msk (0x80000000UL) /*!< LK11 (Bitfield-Mask: 0x01) */
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/* ====================================================== TRGMUX_PWM3 ====================================================== */
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#define CTU_TRGMUX_PWM3_SEL_PWM3_TRIG0_TR_Pos (0UL) /*!< SEL_PWM3_TRIG0_TR (Bit 0) */
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#define CTU_TRGMUX_PWM3_SEL_PWM3_TRIG0_TR_Msk (0x7fUL) /*!< SEL_PWM3_TRIG0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM3_SEL_PWM3_FAULT0_TR_Pos (8UL) /*!< SEL_PWM3_FAULT0_TR (Bit 8) */
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#define CTU_TRGMUX_PWM3_SEL_PWM3_FAULT0_TR_Msk (0x7f00UL) /*!< SEL_PWM3_FAULT0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM3_SEL_PWM3_FAULT1_TR_Pos (16UL) /*!< SEL_PWM3_FAULT1_TR (Bit 16) */
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#define CTU_TRGMUX_PWM3_SEL_PWM3_FAULT1_TR_Msk (0x7f0000UL) /*!< SEL_PWM3_FAULT1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM3_SEL_PWM3_FAULT2_TR_Pos (24UL) /*!< SEL_PWM3_FAULT2_TR (Bit 24) */
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#define CTU_TRGMUX_PWM3_SEL_PWM3_FAULT2_TR_Msk (0x7f000000UL) /*!< SEL_PWM3_FAULT2_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM3_LK12_Pos (31UL) /*!< LK12 (Bit 31) */
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#define CTU_TRGMUX_PWM3_LK12_Msk (0x80000000UL) /*!< LK12 (Bitfield-Mask: 0x01) */
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/* ====================================================== TRGMUX_PWM4 ====================================================== */
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#define CTU_TRGMUX_PWM4_SEL_PWM4_TRIG0_TR_Pos (0UL) /*!< SEL_PWM4_TRIG0_TR (Bit 0) */
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#define CTU_TRGMUX_PWM4_SEL_PWM4_TRIG0_TR_Msk (0x7fUL) /*!< SEL_PWM4_TRIG0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM4_LK13_Pos (31UL) /*!< LK13 (Bit 31) */
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#define CTU_TRGMUX_PWM4_LK13_Msk (0x80000000UL) /*!< LK13 (Bitfield-Mask: 0x01) */
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/* ====================================================== TRGMUX_PWM5 ====================================================== */
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#define CTU_TRGMUX_PWM5_SEL_PWM5_TRIG0_TR_Pos (0UL) /*!< SEL_PWM5_TRIG0_TR (Bit 0) */
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#define CTU_TRGMUX_PWM5_SEL_PWM5_TRIG0_TR_Msk (0x7fUL) /*!< SEL_PWM5_TRIG0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PWM5_LK14_Pos (31UL) /*!< LK14 (Bit 31) */
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#define CTU_TRGMUX_PWM5_LK14_Msk (0x80000000UL) /*!< LK14 (Bitfield-Mask: 0x01) */
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/* ===================================================== TRGMUX_TIMER ====================================================== */
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#define CTU_TRGMUX_TIMER_SEL_TIMER_CH0_TR_Pos (0UL) /*!< SEL_TIMER_CH0_TR (Bit 0) */
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#define CTU_TRGMUX_TIMER_SEL_TIMER_CH0_TR_Msk (0x7fUL) /*!< SEL_TIMER_CH0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_TIMER_SEL_TIMER_CH1_TR_Pos (8UL) /*!< SEL_TIMER_CH1_TR (Bit 8) */
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#define CTU_TRGMUX_TIMER_SEL_TIMER_CH1_TR_Msk (0x7f00UL) /*!< SEL_TIMER_CH1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_TIMER_SEL_TIMER_CH2_TR_Pos (16UL) /*!< SEL_TIMER_CH2_TR (Bit 16) */
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#define CTU_TRGMUX_TIMER_SEL_TIMER_CH2_TR_Msk (0x7f0000UL) /*!< SEL_TIMER_CH2_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_TIMER_SEL_TIMER_CH3_TR_Pos (24UL) /*!< SEL_TIMER_CH3_TR (Bit 24) */
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#define CTU_TRGMUX_TIMER_SEL_TIMER_CH3_TR_Msk (0x7f000000UL) /*!< SEL_TIMER_CH3_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_TIMER_LK15_Pos (31UL) /*!< LK15 (Bit 31) */
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#define CTU_TRGMUX_TIMER_LK15_Msk (0x80000000UL) /*!< LK15 (Bitfield-Mask: 0x01) */
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/* ====================================================== TRGMUX_PCT ======================================================= */
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#define CTU_TRGMUX_PCT_SEL_PCT0_TR_Pos (0UL) /*!< SEL_PCT0_TR (Bit 0) */
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#define CTU_TRGMUX_PCT_SEL_PCT0_TR_Msk (0x7fUL) /*!< SEL_PCT0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PCT_LK16_Pos (31UL) /*!< LK16 (Bit 31) */
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#define CTU_TRGMUX_PCT_LK16_Msk (0x80000000UL) /*!< LK16 (Bitfield-Mask: 0x01) */
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/* ===================================================== TRGMUX_UART0 ====================================================== */
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#define CTU_TRGMUX_UART0_SEL_UART0_TR_Pos (0UL) /*!< SEL_UART0_TR (Bit 0) */
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#define CTU_TRGMUX_UART0_SEL_UART0_TR_Msk (0x7fUL) /*!< SEL_UART0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_UART0_LK17_Pos (31UL) /*!< LK17 (Bit 31) */
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#define CTU_TRGMUX_UART0_LK17_Msk (0x80000000UL) /*!< LK17 (Bitfield-Mask: 0x01) */
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/* ===================================================== TRGMUX_UART1 ====================================================== */
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#define CTU_TRGMUX_UART1_SEL_UART1_TR_Pos (0UL) /*!< SEL_UART1_TR (Bit 0) */
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#define CTU_TRGMUX_UART1_SEL_UART1_TR_Msk (0x7fUL) /*!< SEL_UART1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_UART1_LK18_Pos (31UL) /*!< LK18 (Bit 31) */
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#define CTU_TRGMUX_UART1_LK18_Msk (0x80000000UL) /*!< LK18 (Bitfield-Mask: 0x01) */
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/* ====================================================== TRGMUX_PDT0 ====================================================== */
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#define CTU_TRGMUX_PDT0_SEL_PDT0_TR_Pos (0UL) /*!< SEL_PDT0_TR (Bit 0) */
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#define CTU_TRGMUX_PDT0_SEL_PDT0_TR_Msk (0x7fUL) /*!< SEL_PDT0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PDT0_LK19_Pos (31UL) /*!< LK19 (Bit 31) */
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#define CTU_TRGMUX_PDT0_LK19_Msk (0x80000000UL) /*!< LK19 (Bitfield-Mask: 0x01) */
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/* ====================================================== TRGMUX_PDT1 ====================================================== */
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#define CTU_TRGMUX_PDT1_SEL_PDT1_TR_Pos (0UL) /*!< SEL_PDT1_TR (Bit 0) */
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#define CTU_TRGMUX_PDT1_SEL_PDT1_TR_Msk (0x7fUL) /*!< SEL_PDT1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_PDT1_LK20_Pos (31UL) /*!< LK20 (Bit 31) */
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#define CTU_TRGMUX_PDT1_LK20_Msk (0x80000000UL) /*!< LK20 (Bitfield-Mask: 0x01) */
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/* ====================================================== TRGMUX_EIO ======================================================= */
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#define CTU_TRGMUX_EIO_SEL_EIO_TIMER0_TR_Pos (0UL) /*!< SEL_EIO_TIMER0_TR (Bit 0) */
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#define CTU_TRGMUX_EIO_SEL_EIO_TIMER0_TR_Msk (0x7fUL) /*!< SEL_EIO_TIMER0_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_EIO_SEL_EIO_TIMER1_TR_Pos (8UL) /*!< SEL_EIO_TIMER1_TR (Bit 8) */
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#define CTU_TRGMUX_EIO_SEL_EIO_TIMER1_TR_Msk (0x7f00UL) /*!< SEL_EIO_TIMER1_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_EIO_SEL_EIO_TIMER2_TR_Pos (16UL) /*!< SEL_EIO_TIMER2_TR (Bit 16) */
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#define CTU_TRGMUX_EIO_SEL_EIO_TIMER2_TR_Msk (0x7f0000UL) /*!< SEL_EIO_TIMER2_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_EIO_SEL_EIO_TIMER3_TR_Pos (24UL) /*!< SEL_EIO_TIMER3_TR (Bit 24) */
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#define CTU_TRGMUX_EIO_SEL_EIO_TIMER3_TR_Msk (0x7f000000UL) /*!< SEL_EIO_TIMER3_TR (Bitfield-Mask: 0x7f) */
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#define CTU_TRGMUX_EIO_LK21_Pos (31UL) /*!< LK21 (Bit 31) */
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#define CTU_TRGMUX_EIO_LK21_Msk (0x80000000UL) /*!< LK21 (Bitfield-Mask: 0x01) */
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/* ======================================================== CTU_CFG ======================================================== */
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#define CTU_CTU_CFG_SEL_UART0_Pos (0UL) /*!< SEL_UART0 (Bit 0) */
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#define CTU_CTU_CFG_SEL_UART0_Msk (0x1UL) /*!< SEL_UART0 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_UART1_Pos (1UL) /*!< SEL_UART1 (Bit 1) */
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#define CTU_CTU_CFG_SEL_UART1_Msk (0x2UL) /*!< SEL_UART1 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_UART0_TX_Pos (2UL) /*!< SEL_UART0_TX (Bit 2) */
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#define CTU_CTU_CFG_SEL_UART0_TX_Msk (0x4UL) /*!< SEL_UART0_TX (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_UART1_TX_Pos (3UL) /*!< SEL_UART1_TX (Bit 3) */
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#define CTU_CTU_CFG_SEL_UART1_TX_Msk (0x8UL) /*!< SEL_UART1_TX (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM1_CH0_Pos (4UL) /*!< SEL_PWM1_CH0 (Bit 4) */
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#define CTU_CTU_CFG_SEL_PWM1_CH0_Msk (0x10UL) /*!< SEL_PWM1_CH0 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM3_CH0_Pos (5UL) /*!< SEL_PWM3_CH0 (Bit 5) */
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#define CTU_CTU_CFG_SEL_PWM3_CH0_Msk (0x20UL) /*!< SEL_PWM3_CH0 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM2_HALL_Pos (6UL) /*!< SEL_PWM2_HALL (Bit 6) */
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#define CTU_CTU_CFG_SEL_PWM2_HALL_Msk (0x40UL) /*!< SEL_PWM2_HALL (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM0SYNC_Pos (9UL) /*!< SEL_PWM0SYNC (Bit 9) */
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#define CTU_CTU_CFG_SEL_PWM0SYNC_Msk (0x200UL) /*!< SEL_PWM0SYNC (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM1SYNC_Pos (10UL) /*!< SEL_PWM1SYNC (Bit 10) */
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#define CTU_CTU_CFG_SEL_PWM1SYNC_Msk (0x400UL) /*!< SEL_PWM1SYNC (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM2SYNC_Pos (11UL) /*!< SEL_PWM2SYNC (Bit 11) */
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#define CTU_CTU_CFG_SEL_PWM2SYNC_Msk (0x800UL) /*!< SEL_PWM2SYNC (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM3SYNC_Pos (12UL) /*!< SEL_PWM3SYNC (Bit 12) */
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#define CTU_CTU_CFG_SEL_PWM3SYNC_Msk (0x1000UL) /*!< SEL_PWM3SYNC (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM4SYNC_Pos (13UL) /*!< SEL_PWM4SYNC (Bit 13) */
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#define CTU_CTU_CFG_SEL_PWM4SYNC_Msk (0x2000UL) /*!< SEL_PWM4SYNC (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM5SYNC_Pos (14UL) /*!< SEL_PWM5SYNC (Bit 14) */
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#define CTU_CTU_CFG_SEL_PWM5SYNC_Msk (0x4000UL) /*!< SEL_PWM5SYNC (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM0_FAULT0_Pos (15UL) /*!< SEL_PWM0_FAULT0 (Bit 15) */
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#define CTU_CTU_CFG_SEL_PWM0_FAULT0_Msk (0x8000UL) /*!< SEL_PWM0_FAULT0 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM0_FAULT1_Pos (16UL) /*!< SEL_PWM0_FAULT1 (Bit 16) */
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#define CTU_CTU_CFG_SEL_PWM0_FAULT1_Msk (0x10000UL) /*!< SEL_PWM0_FAULT1 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM0_FAULT2_Pos (17UL) /*!< SEL_PWM0_FAULT2 (Bit 17) */
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#define CTU_CTU_CFG_SEL_PWM0_FAULT2_Msk (0x20000UL) /*!< SEL_PWM0_FAULT2 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM1_FAULT0_Pos (19UL) /*!< SEL_PWM1_FAULT0 (Bit 19) */
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#define CTU_CTU_CFG_SEL_PWM1_FAULT0_Msk (0x80000UL) /*!< SEL_PWM1_FAULT0 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM1_FAULT1_Pos (20UL) /*!< SEL_PWM1_FAULT1 (Bit 20) */
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#define CTU_CTU_CFG_SEL_PWM1_FAULT1_Msk (0x100000UL) /*!< SEL_PWM1_FAULT1 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM1_FAULT2_Pos (21UL) /*!< SEL_PWM1_FAULT2 (Bit 21) */
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#define CTU_CTU_CFG_SEL_PWM1_FAULT2_Msk (0x200000UL) /*!< SEL_PWM1_FAULT2 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM2_FAULT0_Pos (23UL) /*!< SEL_PWM2_FAULT0 (Bit 23) */
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#define CTU_CTU_CFG_SEL_PWM2_FAULT0_Msk (0x800000UL) /*!< SEL_PWM2_FAULT0 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM2_FAULT1_Pos (24UL) /*!< SEL_PWM2_FAULT1 (Bit 24) */
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#define CTU_CTU_CFG_SEL_PWM2_FAULT1_Msk (0x1000000UL) /*!< SEL_PWM2_FAULT1 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM2_FAULT2_Pos (25UL) /*!< SEL_PWM2_FAULT2 (Bit 25) */
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#define CTU_CTU_CFG_SEL_PWM2_FAULT2_Msk (0x2000000UL) /*!< SEL_PWM2_FAULT2 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM3_FAULT0_Pos (27UL) /*!< SEL_PWM3_FAULT0 (Bit 27) */
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#define CTU_CTU_CFG_SEL_PWM3_FAULT0_Msk (0x8000000UL) /*!< SEL_PWM3_FAULT0 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM3_FAULT1_Pos (28UL) /*!< SEL_PWM3_FAULT1 (Bit 28) */
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#define CTU_CTU_CFG_SEL_PWM3_FAULT1_Msk (0x10000000UL) /*!< SEL_PWM3_FAULT1 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_SEL_PWM3_FAULT2_Pos (29UL) /*!< SEL_PWM3_FAULT2 (Bit 29) */
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#define CTU_CTU_CFG_SEL_PWM3_FAULT2_Msk (0x20000000UL) /*!< SEL_PWM3_FAULT2 (Bitfield-Mask: 0x01) */
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#define CTU_CTU_CFG_RTC_CLK_CAP_Pos (31UL) /*!< RTC_CLK_CAP (Bit 31) */
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#define CTU_CTU_CFG_RTC_CLK_CAP_Msk (0x80000000UL) /*!< RTC_CLK_CAP (Bitfield-Mask: 0x01) */
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/* ======================================================== CTU_SW ========================================================= */
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#define CTU_CTU_SW_SW_TRIG1_TS_Pos (0UL) /*!< SW_TRIG1_TS (Bit 0) */
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#define CTU_CTU_SW_SW_TRIG1_TS_Msk (0x1UL) /*!< SW_TRIG1_TS (Bitfield-Mask: 0x01) */
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#define CTU_CTU_SW_SW_TRIG2_TS_Pos (1UL) /*!< SW_TRIG2_TS (Bit 1) */
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#define CTU_CTU_SW_SW_TRIG2_TS_Msk (0x2UL) /*!< SW_TRIG2_TS (Bitfield-Mask: 0x01) */
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#define CTU_CTU_SW_SW_TRIG3_TS_Pos (2UL) /*!< SW_TRIG3_TS (Bit 2) */
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#define CTU_CTU_SW_SW_TRIG3_TS_Msk (0x4UL) /*!< SW_TRIG3_TS (Bitfield-Mask: 0x01) */
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#define CTU_CTU_SW_SW_TRIG4_TS_Pos (3UL) /*!< SW_TRIG4_TS (Bit 3) */
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#define CTU_CTU_SW_SW_TRIG4_TS_Msk (0x8UL) /*!< SW_TRIG4_TS (Bitfield-Mask: 0x01) */
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/* ==================================================== PWM_MODULATION ===================================================== */
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#define CTU_PWM_MODULATION_PWM0_OUTSEL_Pos (0UL) /*!< PWM0_OUTSEL (Bit 0) */
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#define CTU_PWM_MODULATION_PWM0_OUTSEL_Msk (0xffUL) /*!< PWM0_OUTSEL (Bitfield-Mask: 0xff) */
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#define CTU_PWM_MODULATION_PWM3_OUTSEL_Pos (8UL) /*!< PWM3_OUTSEL (Bit 8) */
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#define CTU_PWM_MODULATION_PWM3_OUTSEL_Msk (0xff00UL) /*!< PWM3_OUTSEL (Bitfield-Mask: 0xff) */
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/* ======================================================= ADC_SYNC ======================================================== */
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#define CTU_ADC_SYNC_SIMU_REG_Pos (0UL) /*!< SIMU_REG (Bit 0) */
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#define CTU_ADC_SYNC_SIMU_REG_Msk (0x1UL) /*!< SIMU_REG (Bitfield-Mask: 0x01) */
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#define CTU_ADC_SYNC_SIMU_INJ_Pos (1UL) /*!< SIMU_INJ (Bit 1) */
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#define CTU_ADC_SYNC_SIMU_INJ_Msk (0x2UL) /*!< SIMU_INJ (Bitfield-Mask: 0x01) */
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#define CTU_ADC_SYNC_ADC0_INTER_Pos (8UL) /*!< ADC0_INTER (Bit 8) */
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#define CTU_ADC_SYNC_ADC0_INTER_Msk (0xf00UL) /*!< ADC0_INTER (Bitfield-Mask: 0x0f) */
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#define CTU_ADC_SYNC_ADC1_INTER_Pos (12UL) /*!< ADC1_INTER (Bit 12) */
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#define CTU_ADC_SYNC_ADC1_INTER_Msk (0xf000UL) /*!< ADC1_INTER (Bitfield-Mask: 0x0f) */
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/* =========================================================================================================================== */
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/* ================ DMA ================ */
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/* =========================================================================================================================== */
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/* ======================================================== TOP_RST ======================================================== */
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#define DMA_TOP_RST_WARM_RST_Pos (0UL) /*!< WARM_RST (Bit 0) */
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#define DMA_TOP_RST_WARM_RST_Msk (0x1UL) /*!< WARM_RST (Bitfield-Mask: 0x01) */
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#define DMA_TOP_RST_HARD_RST_Pos (1UL) /*!< HARD_RST (Bit 1) */
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#define DMA_TOP_RST_HARD_RST_Msk (0x2UL) /*!< HARD_RST (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ DMA_Channel ================ */
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/* =========================================================================================================================== */
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/* ======================================================== STATUS ========================================================= */
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#define DMA_CHANNEL_STATUS_FINISH_Pos (0UL) /*!< FINISH (Bit 0) */
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#define DMA_CHANNEL_STATUS_FINISH_Msk (0x1UL) /*!< FINISH (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_STATUS_HALF_FINISH_Pos (1UL) /*!< HALF_FINISH (Bit 1) */
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#define DMA_CHANNEL_STATUS_HALF_FINISH_Msk (0x2UL) /*!< HALF_FINISH (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_STATUS_DBE_Pos (2UL) /*!< DBE (Bit 2) */
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#define DMA_CHANNEL_STATUS_DBE_Msk (0x4UL) /*!< DBE (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_STATUS_SBE_Pos (3UL) /*!< SBE (Bit 3) */
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#define DMA_CHANNEL_STATUS_SBE_Msk (0x8UL) /*!< SBE (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_STATUS_DOE_Pos (4UL) /*!< DOE (Bit 4) */
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#define DMA_CHANNEL_STATUS_DOE_Msk (0x10UL) /*!< DOE (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_STATUS_SOE_Pos (5UL) /*!< SOE (Bit 5) */
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#define DMA_CHANNEL_STATUS_SOE_Msk (0x20UL) /*!< SOE (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_STATUS_DAE_Pos (6UL) /*!< DAE (Bit 6) */
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#define DMA_CHANNEL_STATUS_DAE_Msk (0x40UL) /*!< DAE (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_STATUS_SAE_Pos (7UL) /*!< SAE (Bit 7) */
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#define DMA_CHANNEL_STATUS_SAE_Msk (0x80UL) /*!< SAE (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_STATUS_CLE_Pos (8UL) /*!< CLE (Bit 8) */
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#define DMA_CHANNEL_STATUS_CLE_Msk (0x100UL) /*!< CLE (Bitfield-Mask: 0x01) */
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/* ========================================================= INTEN ========================================================= */
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#define DMA_CHANNEL_INTEN_FINISH_INTERRUPT_ENABLE_Pos (0UL) /*!< FINISH_INTERRUPT_ENABLE (Bit 0) */
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#define DMA_CHANNEL_INTEN_FINISH_INTERRUPT_ENABLE_Msk (0x1UL) /*!< FINISH_INTERRUPT_ENABLE (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_INTEN_TRANS_ERROR_INTERRUPT_ENABLE_Pos (2UL) /*!< TRANS_ERROR_INTERRUPT_ENABLE (Bit 2) */
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#define DMA_CHANNEL_INTEN_TRANS_ERROR_INTERRUPT_ENABLE_Msk (0x4UL) /*!< TRANS_ERROR_INTERRUPT_ENABLE (Bitfield-Mask: 0x01) */
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/* ========================================================== RST ========================================================== */
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#define DMA_CHANNEL_RST_WARM_RST_Pos (0UL) /*!< WARM_RST (Bit 0) */
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#define DMA_CHANNEL_RST_WARM_RST_Msk (0x1UL) /*!< WARM_RST (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_RST_HARD_RST_Pos (1UL) /*!< HARD_RST (Bit 1) */
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#define DMA_CHANNEL_RST_HARD_RST_Msk (0x2UL) /*!< HARD_RST (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_RST_FLUSH_Pos (2UL) /*!< FLUSH (Bit 2) */
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#define DMA_CHANNEL_RST_FLUSH_Msk (0x4UL) /*!< FLUSH (Bitfield-Mask: 0x01) */
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/* ========================================================= STOP ========================================================== */
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#define DMA_CHANNEL_STOP_STOP_Pos (0UL) /*!< STOP (Bit 0) */
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#define DMA_CHANNEL_STOP_STOP_Msk (0x1UL) /*!< STOP (Bitfield-Mask: 0x01) */
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/* ======================================================== CONFIG ========================================================= */
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#define DMA_CHANNEL_CONFIG_CHAN_PRIORITY_Pos (0UL) /*!< CHAN_PRIORITY (Bit 0) */
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#define DMA_CHANNEL_CONFIG_CHAN_PRIORITY_Msk (0x3UL) /*!< CHAN_PRIORITY (Bitfield-Mask: 0x03) */
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#define DMA_CHANNEL_CONFIG_SSIZE_Pos (2UL) /*!< SSIZE (Bit 2) */
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#define DMA_CHANNEL_CONFIG_SSIZE_Msk (0xcUL) /*!< SSIZE (Bitfield-Mask: 0x03) */
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#define DMA_CHANNEL_CONFIG_DSIZE_Pos (4UL) /*!< DSIZE (Bit 4) */
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#define DMA_CHANNEL_CONFIG_DSIZE_Msk (0x30UL) /*!< DSIZE (Bitfield-Mask: 0x03) */
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#define DMA_CHANNEL_CONFIG_CHAN_CIRCULAR_Pos (6UL) /*!< CHAN_CIRCULAR (Bit 6) */
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#define DMA_CHANNEL_CONFIG_CHAN_CIRCULAR_Msk (0x40UL) /*!< CHAN_CIRCULAR (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_CONFIG_CHAN_DIR_Pos (7UL) /*!< CHAN_DIR (Bit 7) */
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#define DMA_CHANNEL_CONFIG_CHAN_DIR_Msk (0x80UL) /*!< CHAN_DIR (Bitfield-Mask: 0x01) */
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/* ====================================================== CHAN_LENGTH ====================================================== */
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#define DMA_CHANNEL_CHAN_LENGTH_CHAN_LENGTH_Pos (0UL) /*!< CHAN_LENGTH (Bit 0) */
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#define DMA_CHANNEL_CHAN_LENGTH_CHAN_LENGTH_Msk (0xffffUL) /*!< CHAN_LENGTH (Bitfield-Mask: 0xffff) */
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/* ====================================================== SSTART_ADDR ====================================================== */
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#define DMA_CHANNEL_SSTART_ADDR_SSTART_ADDR_Pos (0UL) /*!< SSTART_ADDR (Bit 0) */
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#define DMA_CHANNEL_SSTART_ADDR_SSTART_ADDR_Msk (0xffffffffUL) /*!< SSTART_ADDR (Bitfield-Mask: 0xffffffff) */
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/* ======================================================= SEND_ADDR ======================================================= */
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#define DMA_CHANNEL_SEND_ADDR_SEND_ADDR_Pos (0UL) /*!< SEND_ADDR (Bit 0) */
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#define DMA_CHANNEL_SEND_ADDR_SEND_ADDR_Msk (0xffffffffUL) /*!< SEND_ADDR (Bitfield-Mask: 0xffffffff) */
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/* ====================================================== DSTART_ADDR ====================================================== */
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#define DMA_CHANNEL_DSTART_ADDR_DSTART_ADDR_Pos (0UL) /*!< DSTART_ADDR (Bit 0) */
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#define DMA_CHANNEL_DSTART_ADDR_DSTART_ADDR_Msk (0xffffffffUL) /*!< DSTART_ADDR (Bitfield-Mask: 0xffffffff) */
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/* ====================================================== CHAN_ENABLE ====================================================== */
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#define DMA_CHANNEL_CHAN_ENABLE_CHAN_ENABLE_Pos (0UL) /*!< CHAN_ENABLE (Bit 0) */
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#define DMA_CHANNEL_CHAN_ENABLE_CHAN_ENABLE_Msk (0x1UL) /*!< CHAN_ENABLE (Bitfield-Mask: 0x01) */
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#define DMA_CHANNEL_CHAN_ENABLE_EDBG_Pos (1UL) /*!< EDBG (Bit 1) */
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#define DMA_CHANNEL_CHAN_ENABLE_EDBG_Msk (0x2UL) /*!< EDBG (Bitfield-Mask: 0x01) */
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/* ==================================================== DATA_TRANS_NUM ===================================================== */
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#define DMA_CHANNEL_DATA_TRANS_NUM_DATA_TRANS_NUM_Pos (0UL) /*!< DATA_TRANS_NUM (Bit 0) */
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#define DMA_CHANNEL_DATA_TRANS_NUM_DATA_TRANS_NUM_Msk (0xffffUL) /*!< DATA_TRANS_NUM (Bitfield-Mask: 0xffff) */
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/* ===================================================== FIFO_LEFT_NUM ===================================================== */
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#define DMA_CHANNEL_FIFO_LEFT_NUM_FIFO_LEFT_NUM_Pos (0UL) /*!< FIFO_LEFT_NUM (Bit 0) */
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#define DMA_CHANNEL_FIFO_LEFT_NUM_FIFO_LEFT_NUM_Msk (0x3fUL) /*!< FIFO_LEFT_NUM (Bitfield-Mask: 0x3f) */
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/* ======================================================= DEND_ADDR ======================================================= */
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#define DMA_CHANNEL_DEND_ADDR_DEND_ADDR_Pos (0UL) /*!< DEND_ADDR (Bit 0) */
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#define DMA_CHANNEL_DEND_ADDR_DEND_ADDR_Msk (0xffffffffUL) /*!< DEND_ADDR (Bitfield-Mask: 0xffffffff) */
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/* ====================================================== ADDR_OFFSET ====================================================== */
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#define DMA_CHANNEL_ADDR_OFFSET_SOFFSET_Pos (0UL) /*!< SOFFSET (Bit 0) */
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#define DMA_CHANNEL_ADDR_OFFSET_SOFFSET_Msk (0xffffUL) /*!< SOFFSET (Bitfield-Mask: 0xffff) */
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#define DMA_CHANNEL_ADDR_OFFSET_DOFFSET_Pos (16UL) /*!< DOFFSET (Bit 16) */
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#define DMA_CHANNEL_ADDR_OFFSET_DOFFSET_Msk (0xffff0000UL) /*!< DOFFSET (Bitfield-Mask: 0xffff) */
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/* ====================================================== DMAMUX_CFG ======================================================= */
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#define DMA_CHANNEL_DMAMUX_CFG_REQ_ID_Pos (0UL) /*!< REQ_ID (Bit 0) */
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#define DMA_CHANNEL_DMAMUX_CFG_REQ_ID_Msk (0x7fUL) /*!< REQ_ID (Bitfield-Mask: 0x7f) */
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#define DMA_CHANNEL_DMAMUX_CFG_TRIG_EN_Pos (7UL) /*!< TRIG_EN (Bit 7) */
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#define DMA_CHANNEL_DMAMUX_CFG_TRIG_EN_Msk (0x80UL) /*!< TRIG_EN (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ WDG ================ */
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/* =========================================================================================================================== */
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/* ========================================================== CS0 ========================================================== */
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#define WDG_CS0_STOP_Pos (0UL) /*!< STOP (Bit 0) */
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#define WDG_CS0_STOP_Msk (0x1UL) /*!< STOP (Bitfield-Mask: 0x01) */
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#define WDG_CS0_DBG_Pos (1UL) /*!< DBG (Bit 1) */
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#define WDG_CS0_DBG_Msk (0x2UL) /*!< DBG (Bitfield-Mask: 0x01) */
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#define WDG_CS0_ULK_Pos (2UL) /*!< ULK (Bit 2) */
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#define WDG_CS0_ULK_Msk (0x4UL) /*!< ULK (Bitfield-Mask: 0x01) */
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#define WDG_CS0_TST_Pos (3UL) /*!< TST (Bit 3) */
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#define WDG_CS0_TST_Msk (0x18UL) /*!< TST (Bitfield-Mask: 0x03) */
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#define WDG_CS0_UPDATE_Pos (5UL) /*!< UPDATE (Bit 5) */
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#define WDG_CS0_UPDATE_Msk (0x20UL) /*!< UPDATE (Bitfield-Mask: 0x01) */
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#define WDG_CS0_INT_Pos (6UL) /*!< INT (Bit 6) */
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#define WDG_CS0_INT_Msk (0x40UL) /*!< INT (Bitfield-Mask: 0x01) */
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#define WDG_CS0_EN_Pos (7UL) /*!< EN (Bit 7) */
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#define WDG_CS0_EN_Msk (0x80UL) /*!< EN (Bitfield-Mask: 0x01) */
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/* ========================================================== CS1 ========================================================== */
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#define WDG_CS1_CLK_Pos (0UL) /*!< CLK (Bit 0) */
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#define WDG_CS1_CLK_Msk (0x3UL) /*!< CLK (Bitfield-Mask: 0x03) */
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#define WDG_CS1_PRES_Pos (4UL) /*!< PRES (Bit 4) */
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#define WDG_CS1_PRES_Msk (0x10UL) /*!< PRES (Bitfield-Mask: 0x01) */
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#define WDG_CS1_FLG_Pos (6UL) /*!< FLG (Bit 6) */
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#define WDG_CS1_FLG_Msk (0x40UL) /*!< FLG (Bitfield-Mask: 0x01) */
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#define WDG_CS1_WIN_Pos (7UL) /*!< WIN (Bit 7) */
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#define WDG_CS1_WIN_Msk (0x80UL) /*!< WIN (Bitfield-Mask: 0x01) */
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/* ========================================================== CNT ========================================================== */
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#define WDG_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */
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#define WDG_CNT_CNT_Msk (0xffffffffUL) /*!< CNT (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= TOVAL ========================================================= */
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#define WDG_TOVAL_TOVAL_Pos (0UL) /*!< TOVAL (Bit 0) */
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#define WDG_TOVAL_TOVAL_Msk (0xffffUL) /*!< TOVAL (Bitfield-Mask: 0xffff) */
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/* ========================================================== WIN ========================================================== */
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#define WDG_WIN_WIN_Pos (0UL) /*!< WIN (Bit 0) */
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#define WDG_WIN_WIN_Msk (0xffffUL) /*!< WIN (Bitfield-Mask: 0xffff) */
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/* =========================================================================================================================== */
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/* ================ RTC ================ */
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/* =========================================================================================================================== */
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/* ========================================================= CTRL ========================================================== */
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#define RTC_CTRL_SWR_Pos (0UL) /*!< SWR (Bit 0) */
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#define RTC_CTRL_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */
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#define RTC_CTRL_UPM_Pos (1UL) /*!< UPM (Bit 1) */
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#define RTC_CTRL_UPM_Msk (0x2UL) /*!< UPM (Bitfield-Mask: 0x01) */
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#define RTC_CTRL_COS_Pos (2UL) /*!< COS (Bit 2) */
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#define RTC_CTRL_COS_Msk (0x4UL) /*!< COS (Bitfield-Mask: 0x01) */
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#define RTC_CTRL_COE_Pos (3UL) /*!< COE (Bit 3) */
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#define RTC_CTRL_COE_Msk (0x8UL) /*!< COE (Bitfield-Mask: 0x01) */
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#define RTC_CTRL_TIIE_Pos (4UL) /*!< TIIE (Bit 4) */
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#define RTC_CTRL_TIIE_Msk (0x10UL) /*!< TIIE (Bitfield-Mask: 0x01) */
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#define RTC_CTRL_POIE_Pos (5UL) /*!< POIE (Bit 5) */
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#define RTC_CTRL_POIE_Msk (0x20UL) /*!< POIE (Bitfield-Mask: 0x01) */
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#define RTC_CTRL_TOIE_Pos (6UL) /*!< TOIE (Bit 6) */
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#define RTC_CTRL_TOIE_Msk (0x40UL) /*!< TOIE (Bitfield-Mask: 0x01) */
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#define RTC_CTRL_TAIE_Pos (7UL) /*!< TAIE (Bit 7) */
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#define RTC_CTRL_TAIE_Msk (0x80UL) /*!< TAIE (Bitfield-Mask: 0x01) */
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#define RTC_CTRL_CLKSEL_Pos (16UL) /*!< CLKSEL (Bit 16) */
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#define RTC_CTRL_CLKSEL_Msk (0x30000UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */
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/* ========================================================== TAR ========================================================== */
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#define RTC_TAR_TAR_Pos (0UL) /*!< TAR (Bit 0) */
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#define RTC_TAR_TAR_Msk (0xffffffffUL) /*!< TAR (Bitfield-Mask: 0xffffffff) */
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/* ========================================================== TC =========================================================== */
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#define RTC_TC_CT_Pos (0UL) /*!< CT (Bit 0) */
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#define RTC_TC_CT_Msk (0xffffffffUL) /*!< CT (Bitfield-Mask: 0xffffffff) */
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/* ========================================================== PSR ========================================================== */
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#define RTC_PSR_PSR_Pos (0UL) /*!< PSR (Bit 0) */
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#define RTC_PSR_PSR_Msk (0xfffffUL) /*!< PSR (Bitfield-Mask: 0xfffff) */
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/* ========================================================== PSC ========================================================== */
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#define RTC_PSC_PSC_Pos (0UL) /*!< PSC (Bit 0) */
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#define RTC_PSC_PSC_Msk (0xfffffUL) /*!< PSC (Bitfield-Mask: 0xfffff) */
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/* ========================================================== SR =========================================================== */
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#define RTC_SR_TIF_Pos (0UL) /*!< TIF (Bit 0) */
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#define RTC_SR_TIF_Msk (0x1UL) /*!< TIF (Bitfield-Mask: 0x01) */
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#define RTC_SR_POF_Pos (1UL) /*!< POF (Bit 1) */
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#define RTC_SR_POF_Msk (0x2UL) /*!< POF (Bitfield-Mask: 0x01) */
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#define RTC_SR_TOF_Pos (2UL) /*!< TOF (Bit 2) */
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#define RTC_SR_TOF_Msk (0x4UL) /*!< TOF (Bitfield-Mask: 0x01) */
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#define RTC_SR_TAF_Pos (3UL) /*!< TAF (Bit 3) */
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#define RTC_SR_TAF_Msk (0x8UL) /*!< TAF (Bitfield-Mask: 0x01) */
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#define RTC_SR_TCE_Pos (4UL) /*!< TCE (Bit 4) */
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#define RTC_SR_TCE_Msk (0x10UL) /*!< TCE (Bitfield-Mask: 0x01) */
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/* ========================================================== LR =========================================================== */
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#define RTC_LR_CRL_Pos (0UL) /*!< CRL (Bit 0) */
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#define RTC_LR_CRL_Msk (0x1UL) /*!< CRL (Bitfield-Mask: 0x01) */
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#define RTC_LR_SRL_Pos (1UL) /*!< SRL (Bit 1) */
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#define RTC_LR_SRL_Msk (0x2UL) /*!< SRL (Bitfield-Mask: 0x01) */
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#define RTC_LR_LRL_Pos (2UL) /*!< LRL (Bit 2) */
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#define RTC_LR_LRL_Msk (0x4UL) /*!< LRL (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ CRC ================ */
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/* =========================================================================================================================== */
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/* ======================================================== DATA32 ========================================================= */
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#define CRC_DATA32_Data_Pos (0UL) /*!< Data (Bit 0) */
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#define CRC_DATA32_Data_Msk (0xffffffffUL) /*!< Data (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= POLY ========================================================== */
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#define CRC_POLY_Polynomial_Pos (0UL) /*!< Polynomial (Bit 0) */
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#define CRC_POLY_Polynomial_Msk (0xffffffffUL) /*!< Polynomial (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= CTRL ========================================================== */
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#define CRC_CTRL_TCRC_Pos (0UL) /*!< TCRC (Bit 0) */
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#define CRC_CTRL_TCRC_Msk (0x1UL) /*!< TCRC (Bitfield-Mask: 0x01) */
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#define CRC_CTRL_WAS_Pos (1UL) /*!< WAS (Bit 1) */
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#define CRC_CTRL_WAS_Msk (0x2UL) /*!< WAS (Bitfield-Mask: 0x01) */
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#define CRC_CTRL_FXOR_Pos (2UL) /*!< FXOR (Bit 2) */
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#define CRC_CTRL_FXOR_Msk (0x4UL) /*!< FXOR (Bitfield-Mask: 0x01) */
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#define CRC_CTRL_TOTR_Pos (4UL) /*!< TOTR (Bit 4) */
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#define CRC_CTRL_TOTR_Msk (0x30UL) /*!< TOTR (Bitfield-Mask: 0x03) */
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#define CRC_CTRL_TOTW_Pos (6UL) /*!< TOTW (Bit 6) */
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#define CRC_CTRL_TOTW_Msk (0xc0UL) /*!< TOTW (Bitfield-Mask: 0x03) */
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/* =========================================================================================================================== */
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/* ================ EIM_CTRL ================ */
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/* =========================================================================================================================== */
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/* ==================================================== EIM_GLB_ENABLE ===================================================== */
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#define EIM_CTRL_EIM_GLB_ENABLE_GLB_EN_Pos (0UL) /*!< GLB_EN (Bit 0) */
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#define EIM_CTRL_EIM_GLB_ENABLE_GLB_EN_Msk (0x1UL) /*!< GLB_EN (Bitfield-Mask: 0x01) */
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/* ======================================================= EIM_CHEN ======================================================== */
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#define EIM_CTRL_EIM_CHEN_EIM0_EN_Pos (0UL) /*!< EIM0_EN (Bit 0) */
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#define EIM_CTRL_EIM_CHEN_EIM0_EN_Msk (0x1UL) /*!< EIM0_EN (Bitfield-Mask: 0x01) */
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#define EIM_CTRL_EIM_CHEN_EIM1_EN_Pos (1UL) /*!< EIM1_EN (Bit 1) */
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#define EIM_CTRL_EIM_CHEN_EIM1_EN_Msk (0x2UL) /*!< EIM1_EN (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ EIM_CHANNEL ================ */
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/* =========================================================================================================================== */
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/* ===================================================== EIM_INJ_DATA ====================================================== */
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#define EIM_CHANNEL_EIM_INJ_DATA_EIM_DATA_INJ_Pos (0UL) /*!< EIM_DATA_INJ (Bit 0) */
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#define EIM_CHANNEL_EIM_INJ_DATA_EIM_DATA_INJ_Msk (0xffffffffUL) /*!< EIM_DATA_INJ (Bitfield-Mask: 0xffffffff) */
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/* ===================================================== EIM_INJ_ADDR ====================================================== */
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#define EIM_CHANNEL_EIM_INJ_ADDR_EIM_ADDR_INJ_Pos (0UL) /*!< EIM_ADDR_INJ (Bit 0) */
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#define EIM_CHANNEL_EIM_INJ_ADDR_EIM_ADDR_INJ_Msk (0x3fffUL) /*!< EIM_ADDR_INJ (Bitfield-Mask: 0x3fff) */
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/* ===================================================== EIM_INJ_ECC ======================================================= */
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#define EIM_CHANNEL_EIM_INJ_ECC_EIM_ECC_INJ_Pos (0UL) /*!< EIM_ECC_INJ (Bit 0) */
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#define EIM_CHANNEL_EIM_INJ_ECC_EIM_ECC_INJ_Msk (0x7fUL) /*!< EIM_ECC_INJ (Bitfield-Mask: 0x7f) */
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/* =========================================================================================================================== */
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/* ================ ECC_SRAM ================ */
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/* =========================================================================================================================== */
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/* ====================================================== CH0_STATUS0 ====================================================== */
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#define ECC_SRAM_CH0_STATUS0_ERR_ADDR0_Pos (0UL) /*!< ERR_ADDR0 (Bit 0) */
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#define ECC_SRAM_CH0_STATUS0_ERR_ADDR0_Msk (0x3fffUL) /*!< ERR_ADDR0 (Bitfield-Mask: 0x3fff) */
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#define ECC_SRAM_CH0_STATUS0_ERR_ST_Pos (16UL) /*!< ERR_ST (Bit 16) */
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#define ECC_SRAM_CH0_STATUS0_ERR_ST_Msk (0x70000UL) /*!< ERR_ST (Bitfield-Mask: 0x07) */
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/* ====================================================== CH0_STATUS1 ====================================================== */
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#define ECC_SRAM_CH0_STATUS1_ERR_ADDR1_Pos (0UL) /*!< ERR_ADDR1 (Bit 0) */
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#define ECC_SRAM_CH0_STATUS1_ERR_ADDR1_Msk (0x3fffUL) /*!< ERR_ADDR1 (Bitfield-Mask: 0x3fff) */
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#define ECC_SRAM_CH0_STATUS1_ERR_STS0_Pos (16UL) /*!< ERR_STS0 (Bit 16) */
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#define ECC_SRAM_CH0_STATUS1_ERR_STS0_Msk (0x10000UL) /*!< ERR_STS0 (Bitfield-Mask: 0x01) */
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#define ECC_SRAM_CH0_STATUS1_ERR_STS1_Pos (17UL) /*!< ERR_STS1 (Bit 17) */
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#define ECC_SRAM_CH0_STATUS1_ERR_STS1_Msk (0x20000UL) /*!< ERR_STS1 (Bitfield-Mask: 0x01) */
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/* ====================================================== CH1_STATUS0 ====================================================== */
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#define ECC_SRAM_CH1_STATUS0_ERR_ADDR0_Pos (0UL) /*!< ERR_ADDR0 (Bit 0) */
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#define ECC_SRAM_CH1_STATUS0_ERR_ADDR0_Msk (0x3fffUL) /*!< ERR_ADDR0 (Bitfield-Mask: 0x3fff) */
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#define ECC_SRAM_CH1_STATUS0_ERR_ST_Pos (16UL) /*!< ERR_ST (Bit 16) */
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#define ECC_SRAM_CH1_STATUS0_ERR_ST_Msk (0x70000UL) /*!< ERR_ST (Bitfield-Mask: 0x07) */
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/* ====================================================== CH1_STATUS1 ====================================================== */
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#define ECC_SRAM_CH1_STATUS1_ERR_ADDR1_Pos (0UL) /*!< ERR_ADDR1 (Bit 0) */
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#define ECC_SRAM_CH1_STATUS1_ERR_ADDR1_Msk (0x3fffUL) /*!< ERR_ADDR1 (Bitfield-Mask: 0x3fff) */
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#define ECC_SRAM_CH1_STATUS1_ERR_STS0_Pos (16UL) /*!< ERR_STS0 (Bit 16) */
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#define ECC_SRAM_CH1_STATUS1_ERR_STS0_Msk (0x10000UL) /*!< ERR_STS0 (Bitfield-Mask: 0x01) */
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#define ECC_SRAM_CH1_STATUS1_ERR_STS1_Pos (17UL) /*!< ERR_STS1 (Bit 17) */
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#define ECC_SRAM_CH1_STATUS1_ERR_STS1_Msk (0x20000UL) /*!< ERR_STS1 (Bitfield-Mask: 0x01) */
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/* ===================================================== ECC_ERR_CTRL ====================================================== */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC0_1BIT_IRQ_EN_Pos (0UL) /*!< ECC0_1BIT_IRQ_EN (Bit 0) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC0_1BIT_IRQ_EN_Msk (0x1UL) /*!< ECC0_1BIT_IRQ_EN (Bitfield-Mask: 0x01) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC0_2BIT_IRQ_EN_Pos (1UL) /*!< ECC0_2BIT_IRQ_EN (Bit 1) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC0_2BIT_IRQ_EN_Msk (0x2UL) /*!< ECC0_2BIT_IRQ_EN (Bitfield-Mask: 0x01) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC0_ST_CLR1_Pos (2UL) /*!< ECC0_ST_CLR1 (Bit 2) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC0_ST_CLR1_Msk (0x4UL) /*!< ECC0_ST_CLR1 (Bitfield-Mask: 0x01) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC0_ST_CLR2_Pos (3UL) /*!< ECC0_ST_CLR2 (Bit 3) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC0_ST_CLR2_Msk (0x8UL) /*!< ECC0_ST_CLR2 (Bitfield-Mask: 0x01) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC1_1BIT_IRQ_EN_Pos (8UL) /*!< ECC1_1BIT_IRQ_EN (Bit 8) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC1_1BIT_IRQ_EN_Msk (0x100UL) /*!< ECC1_1BIT_IRQ_EN (Bitfield-Mask: 0x01) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC1_2BIT_IRQ_EN_Pos (9UL) /*!< ECC1_2BIT_IRQ_EN (Bit 9) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC1_2BIT_IRQ_EN_Msk (0x200UL) /*!< ECC1_2BIT_IRQ_EN (Bitfield-Mask: 0x01) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC1_ST_CLR1_Pos (10UL) /*!< ECC1_ST_CLR1 (Bit 10) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC1_ST_CLR1_Msk (0x400UL) /*!< ECC1_ST_CLR1 (Bitfield-Mask: 0x01) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC1_ST_CLR2_Pos (11UL) /*!< ECC1_ST_CLR2 (Bit 11) */
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#define ECC_SRAM_ECC_ERR_CTRL_ECC1_ST_CLR2_Msk (0x800UL) /*!< ECC1_ST_CLR2 (Bitfield-Mask: 0x01) */
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|
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/* =========================================================================================================================== */
|
|
/* ================ FLASH ================ */
|
|
/* =========================================================================================================================== */
|
|
|
|
/* ========================================================= STAT ========================================================== */
|
|
#define FLASH_STAT_PRDY_Pos (0UL) /*!< PRDY (Bit 0) */
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|
#define FLASH_STAT_PRDY_Msk (0x1UL) /*!< PRDY (Bitfield-Mask: 0x01) */
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#define FLASH_STAT_RAMRDY_Pos (1UL) /*!< RAMRDY (Bit 1) */
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|
#define FLASH_STAT_RAMRDY_Msk (0x2UL) /*!< RAMRDY (Bitfield-Mask: 0x01) */
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#define FLASH_STAT_BDKERR_Pos (2UL) /*!< BDKERR (Bit 2) */
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|
#define FLASH_STAT_BDKERR_Msk (0x4UL) /*!< BDKERR (Bitfield-Mask: 0x01) */
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#define FLASH_STAT_DFRDY_Pos (3UL) /*!< DFRDY (Bit 3) */
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#define FLASH_STAT_DFRDY_Msk (0x8UL) /*!< DFRDY (Bitfield-Mask: 0x01) */
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|
#define FLASH_STAT_FRAMECC1F_Pos (6UL) /*!< FRAMECC1F (Bit 6) */
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|
#define FLASH_STAT_FRAMECC1F_Msk (0x40UL) /*!< FRAMECC1F (Bitfield-Mask: 0x01) */
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#define FLASH_STAT_FRAMECC2F_Pos (7UL) /*!< FRAMECC2F (Bit 7) */
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|
#define FLASH_STAT_FRAMECC2F_Msk (0x80UL) /*!< FRAMECC2F (Bitfield-Mask: 0x01) */
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|
#define FLASH_STAT_DFDIF_Pos (8UL) /*!< DFDIF (Bit 8) */
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|
#define FLASH_STAT_DFDIF_Msk (0x100UL) /*!< DFDIF (Bitfield-Mask: 0x01) */
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|
#define FLASH_STAT_PVIOLF_Pos (9UL) /*!< PVIOLF (Bit 9) */
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|
#define FLASH_STAT_PVIOLF_Msk (0x200UL) /*!< PVIOLF (Bitfield-Mask: 0x01) */
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|
#define FLASH_STAT_VERIFYERR_Pos (10UL) /*!< VERIFYERR (Bit 10) */
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|
#define FLASH_STAT_VERIFYERR_Msk (0x400UL) /*!< VERIFYERR (Bitfield-Mask: 0x01) */
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|
#define FLASH_STAT_ACCERRF_Pos (11UL) /*!< ACCERRF (Bit 11) */
|
|
#define FLASH_STAT_ACCERRF_Msk (0x800UL) /*!< ACCERRF (Bitfield-Mask: 0x01) */
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|
#define FLASH_STAT_COLLERRF_Pos (12UL) /*!< COLLERRF (Bit 12) */
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|
#define FLASH_STAT_COLLERRF_Msk (0x1000UL) /*!< COLLERRF (Bitfield-Mask: 0x01) */
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|
#define FLASH_STAT_CCIF_Pos (13UL) /*!< CCIF (Bit 13) */
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|
#define FLASH_STAT_CCIF_Msk (0x2000UL) /*!< CCIF (Bitfield-Mask: 0x01) */
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|
#define FLASH_STAT_LOCK_Pos (14UL) /*!< LOCK (Bit 14) */
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|
#define FLASH_STAT_LOCK_Msk (0x4000UL) /*!< LOCK (Bitfield-Mask: 0x01) */
|
|
/* ========================================================== SEC ========================================================== */
|
|
#define FLASH_SEC_RDPROT_Pos (8UL) /*!< RDPROT (Bit 8) */
|
|
#define FLASH_SEC_RDPROT_Msk (0x300UL) /*!< RDPROT (Bitfield-Mask: 0x03) */
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|
#define FLASH_SEC_EAUEN_Pos (10UL) /*!< EAUEN (Bit 10) */
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|
#define FLASH_SEC_EAUEN_Msk (0xc00UL) /*!< EAUEN (Bitfield-Mask: 0x03) */
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|
#define FLASH_SEC_BDKEN_Pos (12UL) /*!< BDKEN (Bit 12) */
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|
#define FLASH_SEC_BDKEN_Msk (0x3000UL) /*!< BDKEN (Bitfield-Mask: 0x03) */
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|
#define FLASH_SEC_GRANTKEYEN_Pos (14UL) /*!< GRANTKEYEN (Bit 14) */
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|
#define FLASH_SEC_GRANTKEYEN_Msk (0xc000UL) /*!< GRANTKEYEN (Bitfield-Mask: 0x03) */
|
|
/* ======================================================== CSESTAT ======================================================== */
|
|
#define FLASH_CSESTAT_BSY_Pos (0UL) /*!< BSY (Bit 0) */
|
|
#define FLASH_CSESTAT_BSY_Msk (0x1U) /*!< BSY (Bitfield-Mask: 0x01) */
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|
#define FLASH_CSESTAT_SB_Pos (1UL) /*!< SB (Bit 1) */
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|
#define FLASH_CSESTAT_SB_Msk (0x2UL) /*!< SB (Bitfield-Mask: 0x01) */
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|
#define FLASH_CSESTAT_Bin_Pos (2UL) /*!< Bin (Bit 2) */
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#define FLASH_CSESTAT_Bin_Msk (0x4UL) /*!< Bin (Bitfield-Mask: 0x01) */
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#define FLASH_CSESTAT_BFN_Pos (3UL) /*!< BFN (Bit 3) */
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#define FLASH_CSESTAT_BFN_Msk (0x8UL) /*!< BFN (Bitfield-Mask: 0x01) */
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#define FLASH_CSESTAT_BOK_Pos (4UL) /*!< BOK (Bit 4) */
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#define FLASH_CSESTAT_BOK_Msk (0x10UL) /*!< BOK (Bitfield-Mask: 0x01) */
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#define FLASH_CSESTAT_RIN_Pos (5UL) /*!< RIN (Bit 5) */
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#define FLASH_CSESTAT_RIN_Msk (0x20UL) /*!< RIN (Bitfield-Mask: 0x01) */
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#define FLASH_CSESTAT_EDB_Pos (6UL) /*!< EDB (Bit 6) */
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#define FLASH_CSESTAT_EDB_Msk (0x40UL) /*!< EDB (Bitfield-Mask: 0x01) */
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#define FLASH_CSESTAT_IDB_Pos (7UL) /*!< IDB (Bit 7) */
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#define FLASH_CSESTAT_IDB_Msk (0x80UL) /*!< IDB (Bitfield-Mask: 0x01) */
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#define FLASH_CSESTAT_CCIF_Pos (8UL) /*!< CCIF (Bit 8) */
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#define FLASH_CSESTAT_CCIF_Msk (0x100UL) /*!< CCIF (Bitfield-Mask: 0x01) */
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/* ======================================================== KEYUNLK ======================================================== */
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#define FLASH_KEYUNLK_KEY_Pos (0UL) /*!< KEY (Bit 0) */
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#define FLASH_KEYUNLK_KEY_Msk (0xffffffffUL) /*!< KEY (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= CNFG ========================================================== */
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#define FLASH_CNFG_DFDIE_Pos (0UL) /*!< DFDIE (Bit 0) */
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#define FLASH_CNFG_DFDIE_Msk (0x1UL) /*!< DFDIE (Bitfield-Mask: 0x01) */
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#define FLASH_CNFG_COLLE_Pos (1UL) /*!< COLLE (Bit 1) */
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#define FLASH_CNFG_COLLE_Msk (0x2UL) /*!< COLLE (Bitfield-Mask: 0x01) */
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#define FLASH_CNFG_CCIE_Pos (2UL) /*!< CCIE (Bit 2) */
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#define FLASH_CNFG_CCIE_Msk (0x4UL) /*!< CCIE (Bitfield-Mask: 0x01) */
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#define FLASH_CNFG_CSECCIE_Pos (3UL) /*!< CSECCIE (Bit 3) */
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#define FLASH_CNFG_CSECCIE_Msk (0x8UL) /*!< CSECCIE (Bitfield-Mask: 0x01) */
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#define FLASH_CNFG_EMDFIE_Pos (4UL) /*!< EMDFIE (Bit 4) */
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#define FLASH_CNFG_EMDFIE_Msk (0x10UL) /*!< EMDFIE (Bitfield-Mask: 0x01) */
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#define FLASH_CNFG_LVDDETEN_Pos (5UL) /*!< LVDDETEN (Bit 5) */
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#define FLASH_CNFG_LVDDETEN_Msk (0x20UL) /*!< LVDDETEN (Bitfield-Mask: 0x01) */
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#define FLASH_CNFG_PERABORT_Pos (7UL) /*!< PERABORT (Bit 7) */
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#define FLASH_CNFG_PERABORT_Msk (0x80UL) /*!< PERABORT (Bitfield-Mask: 0x01) */
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#define FLASH_CNFG_CLKFREQ_Pos (8UL) /*!< CLKFREQ (Bit 8) */
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#define FLASH_CNFG_CLKFREQ_Msk (0xff00UL) /*!< CLKFREQ (Bitfield-Mask: 0xff) */
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/* ========================================================== CMD ========================================================== */
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#define FLASH_CMD_CMD_Pos (0UL) /*!< CMD (Bit 0) */
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#define FLASH_CMD_CMD_Msk (0xffffffffUL) /*!< CMD (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= ADDR ========================================================== */
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#define FLASH_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
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#define FLASH_ADDR_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= DATA0 ========================================================= */
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#define FLASH_DATA0_DATA0_Pos (0UL) /*!< DATA0 (Bit 0) */
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#define FLASH_DATA0_DATA0_Msk (0xffffffffUL) /*!< DATA0 (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= DATA1 ========================================================= */
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#define FLASH_DATA1_DATA1_Pos (0UL) /*!< DATA1 (Bit 0) */
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#define FLASH_DATA1_DATA1_Msk (0xffffffffUL) /*!< DATA1 (Bitfield-Mask: 0xffffffff) */
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/* ========================================================== LEN ========================================================== */
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#define FLASH_LEN_LEN_Pos (0UL) /*!< LEN (Bit 0) */
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#define FLASH_LEN_LEN_Msk (0xffffffffUL) /*!< LEN (Bitfield-Mask: 0xffffffff) */
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/* ========================================================== CST ========================================================== */
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#define FLASH_CST_START_Pos (0UL) /*!< START (Bit 0) */
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#define FLASH_CST_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
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/* ========================================================= PPROT ========================================================= */
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|
#define FLASH_PPROT_PPROT_Pos (0UL) /*!< PPROT (Bit 0) */
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#define FLASH_PPROT_PPROT_Msk (0xffffffffUL) /*!< PPROT (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= DPROT ========================================================= */
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#define FLASH_DPROT_DPROT_Pos (0UL) /*!< DPROT (Bit 0) */
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#define FLASH_DPROT_DPROT_Msk (0xffUL) /*!< DPROT (Bitfield-Mask: 0xff) */
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/* ========================================================= DFADR ========================================================= */
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|
#define FLASH_DFADR_DFADR_Pos (0UL) /*!< DFADR (Bit 0) */
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#define FLASH_DFADR_DFADR_Msk (0xffffffffUL) /*!< DFADR (Bitfield-Mask: 0xffffffff) */
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/* ========================================================= PART ========================================================== */
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|
#define FLASH_PART_DPART_Pos (0UL) /*!< DPART (Bit 0) */
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#define FLASH_PART_DPART_Msk (0xfUL) /*!< DPART (Bitfield-Mask: 0x0f) */
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#define FLASH_PART_EPART_Pos (4UL) /*!< EPART (Bit 4) */
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#define FLASH_PART_EPART_Msk (0xf0UL) /*!< EPART (Bitfield-Mask: 0x0f) */
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#define FLASH_PART_SFE_Pos (8UL) /*!< SFE (Bit 8) */
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|
#define FLASH_PART_SFE_Msk (0xff00UL) /*!< SFE (Bitfield-Mask: 0xff) */
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#define FLASH_PART_CSEKEYSIZE_Pos (16UL) /*!< CSEKEYSIZE (Bit 16) */
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#define FLASH_PART_CSEKEYSIZE_Msk (0x30000UL) /*!< CSEKEYSIZE (Bitfield-Mask: 0x03) */
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|
|
|
/* =========================================================================================================================== */
|
|
/* ================ EIO ================ */
|
|
/* =========================================================================================================================== */
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|
|
|
/* ======================================================= EIO_CTRL ======================================================== */
|
|
#define EIO_CTRL_ENHANCED_EN_Pos (0UL) /*!< ENHANCED_EN (Bit 0) */
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|
#define EIO_CTRL_ENHANCED_EN_Msk (0x1UL) /*!< ENHANCED_EN (Bitfield-Mask: 0x01) */
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|
#define EIO_CTRL_SWRST_Pos (1UL) /*!< SWRST (Bit 1) */
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|
#define EIO_CTRL_SWRST_Msk (0x2UL) /*!< SWRST (Bitfield-Mask: 0x01) */
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#define EIO_CTRL_DBGE_Pos (2UL) /*!< DBGE (Bit 2) */
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|
#define EIO_CTRL_DBGE_Msk (0x4UL) /*!< DBGE (Bitfield-Mask: 0x01) */
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/* ======================================================== EIO_PIN ======================================================== */
|
|
#define EIO_PIN_PDI_Pos (0UL) /*!< PDI (Bit 0) */
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|
#define EIO_PIN_PDI_Msk (0xffUL) /*!< PDI (Bitfield-Mask: 0xff) */
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/* ===================================================== EIO_SHIFTSTAT ===================================================== */
|
|
#define EIO_SHIFTSTAT_SSF_Pos (0UL) /*!< SSF (Bit 0) */
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|
#define EIO_SHIFTSTAT_SSF_Msk (0xfUL) /*!< SSF (Bitfield-Mask: 0x0f) */
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|
/* ===================================================== EIO_SHIFTERR ====================================================== */
|
|
#define EIO_SHIFTERR_SEF_Pos (0UL) /*!< SEF (Bit 0) */
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#define EIO_SHIFTERR_SEF_Msk (0xfUL) /*!< SEF (Bitfield-Mask: 0x0f) */
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/* ====================================================== EIO_TIMSTAT ====================================================== */
|
|
#define EIO_TIMSTAT_TSF_Pos (0UL) /*!< TSF (Bit 0) */
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|
#define EIO_TIMSTAT_TSF_Msk (0xfUL) /*!< TSF (Bitfield-Mask: 0x0f) */
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/* ===================================================== EIO_SHIFTSIEN ===================================================== */
|
|
#define EIO_SHIFTSIEN_SSIE_Pos (0UL) /*!< SSIE (Bit 0) */
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|
#define EIO_SHIFTSIEN_SSIE_Msk (0xfUL) /*!< SSIE (Bitfield-Mask: 0x0f) */
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/* ===================================================== EIO_SHIFTEIEN ===================================================== */
|
|
#define EIO_SHIFTEIEN_SEIE_Pos (0UL) /*!< SEIE (Bit 0) */
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#define EIO_SHIFTEIEN_SEIE_Msk (0xfUL) /*!< SEIE (Bitfield-Mask: 0x0f) */
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/* ====================================================== EIO_TIMIEN ======================================================= */
|
|
#define EIO_TIMIEN_TEIE_Pos (0UL) /*!< TEIE (Bit 0) */
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|
#define EIO_TIMIEN_TEIE_Msk (0xfUL) /*!< TEIE (Bitfield-Mask: 0x0f) */
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/* ===================================================== EIO_SHIFTSDEN ===================================================== */
|
|
#define EIO_SHIFTSDEN_SSDE_Pos (0UL) /*!< SSDE (Bit 0) */
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#define EIO_SHIFTSDEN_SSDE_Msk (0xfUL) /*!< SSDE (Bitfield-Mask: 0x0f) */
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/* ===================================================== EIO_SHIFTCTL0 ===================================================== */
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|
#define EIO_SHIFTCTL0_SMOD_Pos (0UL) /*!< SMOD (Bit 0) */
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#define EIO_SHIFTCTL0_SMOD_Msk (0x7UL) /*!< SMOD (Bitfield-Mask: 0x07) */
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#define EIO_SHIFTCTL0_PINPOL_Pos (7UL) /*!< PINPOL (Bit 7) */
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#define EIO_SHIFTCTL0_PINPOL_Msk (0x80UL) /*!< PINPOL (Bitfield-Mask: 0x01) */
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#define EIO_SHIFTCTL0_PINSEL_Pos (8UL) /*!< PINSEL (Bit 8) */
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#define EIO_SHIFTCTL0_PINSEL_Msk (0x700UL) /*!< PINSEL (Bitfield-Mask: 0x07) */
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#define EIO_SHIFTCTL0_PINCFG_Pos (16UL) /*!< PINCFG (Bit 16) */
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#define EIO_SHIFTCTL0_PINCFG_Msk (0x30000UL) /*!< PINCFG (Bitfield-Mask: 0x03) */
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#define EIO_SHIFTCTL0_TIMPOL_Pos (23UL) /*!< TIMPOL (Bit 23) */
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#define EIO_SHIFTCTL0_TIMPOL_Msk (0x800000UL) /*!< TIMPOL (Bitfield-Mask: 0x01) */
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#define EIO_SHIFTCTL0_TIMSEL_Pos (24UL) /*!< TIMSEL (Bit 24) */
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#define EIO_SHIFTCTL0_TIMSEL_Msk (0x3000000UL) /*!< TIMSEL (Bitfield-Mask: 0x03) */
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/* ===================================================== EIO_SHIFTCTL1 ===================================================== */
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#define EIO_SHIFTCTL1_SMOD_Pos (0UL) /*!< SMOD (Bit 0) */
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#define EIO_SHIFTCTL1_SMOD_Msk (0x7UL) /*!< SMOD (Bitfield-Mask: 0x07) */
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#define EIO_SHIFTCTL1_PINPOL_Pos (7UL) /*!< PINPOL (Bit 7) */
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#define EIO_SHIFTCTL1_PINPOL_Msk (0x80UL) /*!< PINPOL (Bitfield-Mask: 0x01) */
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#define EIO_SHIFTCTL1_PINSEL_Pos (8UL) /*!< PINSEL (Bit 8) */
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#define EIO_SHIFTCTL1_PINSEL_Msk (0x700UL) /*!< PINSEL (Bitfield-Mask: 0x07) */
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#define EIO_SHIFTCTL1_PINCFG_Pos (16UL) /*!< PINCFG (Bit 16) */
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#define EIO_SHIFTCTL1_PINCFG_Msk (0x30000UL) /*!< PINCFG (Bitfield-Mask: 0x03) */
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#define EIO_SHIFTCTL1_TIMPOL_Pos (23UL) /*!< TIMPOL (Bit 23) */
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#define EIO_SHIFTCTL1_TIMPOL_Msk (0x800000UL) /*!< TIMPOL (Bitfield-Mask: 0x01) */
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#define EIO_SHIFTCTL1_TIMSEL_Pos (24UL) /*!< TIMSEL (Bit 24) */
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#define EIO_SHIFTCTL1_TIMSEL_Msk (0x3000000UL) /*!< TIMSEL (Bitfield-Mask: 0x03) */
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/* ===================================================== EIO_SHIFTCTL2 ===================================================== */
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#define EIO_SHIFTCTL2_SMOD_Pos (0UL) /*!< SMOD (Bit 0) */
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#define EIO_SHIFTCTL2_SMOD_Msk (0x7UL) /*!< SMOD (Bitfield-Mask: 0x07) */
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#define EIO_SHIFTCTL2_PINPOL_Pos (7UL) /*!< PINPOL (Bit 7) */
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#define EIO_SHIFTCTL2_PINPOL_Msk (0x80UL) /*!< PINPOL (Bitfield-Mask: 0x01) */
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#define EIO_SHIFTCTL2_PINSEL_Pos (8UL) /*!< PINSEL (Bit 8) */
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#define EIO_SHIFTCTL2_PINSEL_Msk (0x700UL) /*!< PINSEL (Bitfield-Mask: 0x07) */
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#define EIO_SHIFTCTL2_PINCFG_Pos (16UL) /*!< PINCFG (Bit 16) */
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#define EIO_SHIFTCTL2_PINCFG_Msk (0x30000UL) /*!< PINCFG (Bitfield-Mask: 0x03) */
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#define EIO_SHIFTCTL2_TIMPOL_Pos (23UL) /*!< TIMPOL (Bit 23) */
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#define EIO_SHIFTCTL2_TIMPOL_Msk (0x800000UL) /*!< TIMPOL (Bitfield-Mask: 0x01) */
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#define EIO_SHIFTCTL2_TIMSEL_Pos (24UL) /*!< TIMSEL (Bit 24) */
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#define EIO_SHIFTCTL2_TIMSEL_Msk (0x3000000UL) /*!< TIMSEL (Bitfield-Mask: 0x03) */
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/* ===================================================== EIO_SHIFTCTL3 ===================================================== */
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#define EIO_SHIFTCTL3_SMOD_Pos (0UL) /*!< SMOD (Bit 0) */
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#define EIO_SHIFTCTL3_SMOD_Msk (0x7UL) /*!< SMOD (Bitfield-Mask: 0x07) */
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#define EIO_SHIFTCTL3_PINPOL_Pos (7UL) /*!< PINPOL (Bit 7) */
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#define EIO_SHIFTCTL3_PINPOL_Msk (0x80UL) /*!< PINPOL (Bitfield-Mask: 0x01) */
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#define EIO_SHIFTCTL3_PINSEL_Pos (8UL) /*!< PINSEL (Bit 8) */
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#define EIO_SHIFTCTL3_PINSEL_Msk (0x700UL) /*!< PINSEL (Bitfield-Mask: 0x07) */
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#define EIO_SHIFTCTL3_PINCFG_Pos (16UL) /*!< PINCFG (Bit 16) */
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#define EIO_SHIFTCTL3_PINCFG_Msk (0x30000UL) /*!< PINCFG (Bitfield-Mask: 0x03) */
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#define EIO_SHIFTCTL3_TIMPOL_Pos (23UL) /*!< TIMPOL (Bit 23) */
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#define EIO_SHIFTCTL3_TIMPOL_Msk (0x800000UL) /*!< TIMPOL (Bitfield-Mask: 0x01) */
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#define EIO_SHIFTCTL3_TIMSEL_Pos (24UL) /*!< TIMSEL (Bit 24) */
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#define EIO_SHIFTCTL3_TIMSEL_Msk (0x3000000UL) /*!< TIMSEL (Bitfield-Mask: 0x03) */
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/* ===================================================== EIO_SHIFTCFG0 ===================================================== */
|
|
#define EIO_SHIFTCFG0_SSTART_Pos (0UL) /*!< SSTART (Bit 0) */
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#define EIO_SHIFTCFG0_SSTART_Msk (0x3UL) /*!< SSTART (Bitfield-Mask: 0x03) */
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#define EIO_SHIFTCFG0_SSTOP_Pos (4UL) /*!< SSTOP (Bit 4) */
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#define EIO_SHIFTCFG0_SSTOP_Msk (0x30UL) /*!< SSTOP (Bitfield-Mask: 0x03) */
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#define EIO_SHIFTCFG0_INSRC_Pos (8UL) /*!< INSRC (Bit 8) */
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#define EIO_SHIFTCFG0_INSRC_Msk (0x100UL) /*!< INSRC (Bitfield-Mask: 0x01) */
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/* ===================================================== EIO_SHIFTCFG1 ===================================================== */
|
|
#define EIO_SHIFTCFG1_SSTART_Pos (0UL) /*!< SSTART (Bit 0) */
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#define EIO_SHIFTCFG1_SSTART_Msk (0x3UL) /*!< SSTART (Bitfield-Mask: 0x03) */
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#define EIO_SHIFTCFG1_SSTOP_Pos (4UL) /*!< SSTOP (Bit 4) */
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#define EIO_SHIFTCFG1_SSTOP_Msk (0x30UL) /*!< SSTOP (Bitfield-Mask: 0x03) */
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#define EIO_SHIFTCFG1_INSRC_Pos (8UL) /*!< INSRC (Bit 8) */
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#define EIO_SHIFTCFG1_INSRC_Msk (0x100UL) /*!< INSRC (Bitfield-Mask: 0x01) */
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|
/* ===================================================== EIO_SHIFTCFG2 ===================================================== */
|
|
#define EIO_SHIFTCFG2_SSTART_Pos (0UL) /*!< SSTART (Bit 0) */
|
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#define EIO_SHIFTCFG2_SSTART_Msk (0x3UL) /*!< SSTART (Bitfield-Mask: 0x03) */
|
|
#define EIO_SHIFTCFG2_SSTOP_Pos (4UL) /*!< SSTOP (Bit 4) */
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#define EIO_SHIFTCFG2_SSTOP_Msk (0x30UL) /*!< SSTOP (Bitfield-Mask: 0x03) */
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|
#define EIO_SHIFTCFG2_INSRC_Pos (8UL) /*!< INSRC (Bit 8) */
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|
#define EIO_SHIFTCFG2_INSRC_Msk (0x100UL) /*!< INSRC (Bitfield-Mask: 0x01) */
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|
/* ===================================================== EIO_SHIFTCFG3 ===================================================== */
|
|
#define EIO_SHIFTCFG3_SSTART_Pos (0UL) /*!< SSTART (Bit 0) */
|
|
#define EIO_SHIFTCFG3_SSTART_Msk (0x3UL) /*!< SSTART (Bitfield-Mask: 0x03) */
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#define EIO_SHIFTCFG3_SSTOP_Pos (4UL) /*!< SSTOP (Bit 4) */
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#define EIO_SHIFTCFG3_SSTOP_Msk (0x30UL) /*!< SSTOP (Bitfield-Mask: 0x03) */
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#define EIO_SHIFTCFG3_INSRC_Pos (8UL) /*!< INSRC (Bit 8) */
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#define EIO_SHIFTCFG3_INSRC_Msk (0x100UL) /*!< INSRC (Bitfield-Mask: 0x01) */
|
|
/* ===================================================== EIO_SHIFTBUF0 ===================================================== */
|
|
#define EIO_SHIFTBUF0_SHIFTBUF_Pos (0UL) /*!< SHIFTBUF (Bit 0) */
|
|
#define EIO_SHIFTBUF0_SHIFTBUF_Msk (0xffffffffUL) /*!< SHIFTBUF (Bitfield-Mask: 0xffffffff) */
|
|
/* ===================================================== EIO_SHIFTBUF1 ===================================================== */
|
|
#define EIO_SHIFTBUF1_SHIFTBUF_Pos (0UL) /*!< SHIFTBUF (Bit 0) */
|
|
#define EIO_SHIFTBUF1_SHIFTBUF_Msk (0xffffffffUL) /*!< SHIFTBUF (Bitfield-Mask: 0xffffffff) */
|
|
/* ===================================================== EIO_SHIFTBUF2 ===================================================== */
|
|
#define EIO_SHIFTBUF2_SHIFTBUF_Pos (0UL) /*!< SHIFTBUF (Bit 0) */
|
|
#define EIO_SHIFTBUF2_SHIFTBUF_Msk (0xffffffffUL) /*!< SHIFTBUF (Bitfield-Mask: 0xffffffff) */
|
|
/* ===================================================== EIO_SHIFTBUF3 ===================================================== */
|
|
#define EIO_SHIFTBUF3_SHIFTBUF_Pos (0UL) /*!< SHIFTBUF (Bit 0) */
|
|
#define EIO_SHIFTBUF3_SHIFTBUF_Msk (0xffffffffUL) /*!< SHIFTBUF (Bitfield-Mask: 0xffffffff) */
|
|
/* =================================================== EIO_SHIFTBUFBIS0 ==================================================== */
|
|
#define EIO_SHIFTBUFBIS0_SHIFTBUFBIS_Pos (0UL) /*!< SHIFTBUFBIS (Bit 0) */
|
|
#define EIO_SHIFTBUFBIS0_SHIFTBUFBIS_Msk (0xffffffffUL) /*!< SHIFTBUFBIS (Bitfield-Mask: 0xffffffff) */
|
|
/* =================================================== EIO_SHIFTBUFBIS1 ==================================================== */
|
|
#define EIO_SHIFTBUFBIS1_SHIFTBUFBIS_Pos (0UL) /*!< SHIFTBUFBIS (Bit 0) */
|
|
#define EIO_SHIFTBUFBIS1_SHIFTBUFBIS_Msk (0xffffffffUL) /*!< SHIFTBUFBIS (Bitfield-Mask: 0xffffffff) */
|
|
/* =================================================== EIO_SHIFTBUFBIS2 ==================================================== */
|
|
#define EIO_SHIFTBUFBIS2_SHIFTBUFBIS_Pos (0UL) /*!< SHIFTBUFBIS (Bit 0) */
|
|
#define EIO_SHIFTBUFBIS2_SHIFTBUFBIS_Msk (0xffffffffUL) /*!< SHIFTBUFBIS (Bitfield-Mask: 0xffffffff) */
|
|
/* =================================================== EIO_SHIFTBUFBIS3 ==================================================== */
|
|
#define EIO_SHIFTBUFBIS3_SHIFTBUFBIS_Pos (0UL) /*!< SHIFTBUFBIS (Bit 0) */
|
|
#define EIO_SHIFTBUFBIS3_SHIFTBUFBIS_Msk (0xffffffffUL) /*!< SHIFTBUFBIS (Bitfield-Mask: 0xffffffff) */
|
|
/* =================================================== EIO_SHIFTBUFBYS0 ==================================================== */
|
|
#define EIO_SHIFTBUFBYS0_SHIFTBUFBYS_Pos (0UL) /*!< SHIFTBUFBYS (Bit 0) */
|
|
#define EIO_SHIFTBUFBYS0_SHIFTBUFBYS_Msk (0xffffffffUL) /*!< SHIFTBUFBYS (Bitfield-Mask: 0xffffffff) */
|
|
/* =================================================== EIO_SHIFTBUFBYS1 ==================================================== */
|
|
#define EIO_SHIFTBUFBYS1_SHIFTBUFBYS_Pos (0UL) /*!< SHIFTBUFBYS (Bit 0) */
|
|
#define EIO_SHIFTBUFBYS1_SHIFTBUFBYS_Msk (0xffffffffUL) /*!< SHIFTBUFBYS (Bitfield-Mask: 0xffffffff) */
|
|
/* =================================================== EIO_SHIFTBUFBYS2 ==================================================== */
|
|
#define EIO_SHIFTBUFBYS2_SHIFTBUFBYS_Pos (0UL) /*!< SHIFTBUFBYS (Bit 0) */
|
|
#define EIO_SHIFTBUFBYS2_SHIFTBUFBYS_Msk (0xffffffffUL) /*!< SHIFTBUFBYS (Bitfield-Mask: 0xffffffff) */
|
|
/* =================================================== EIO_SHIFTBUFBYS3 ==================================================== */
|
|
#define EIO_SHIFTBUFBYS3_SHIFTBUFBYS_Pos (0UL) /*!< SHIFTBUFBYS (Bit 0) */
|
|
#define EIO_SHIFTBUFBYS3_SHIFTBUFBYS_Msk (0xffffffffUL) /*!< SHIFTBUFBYS (Bitfield-Mask: 0xffffffff) */
|
|
/* =================================================== EIO_SHIFTBUFBBS0 ==================================================== */
|
|
#define EIO_SHIFTBUFBBS0_SHIFTBUFBBS_Pos (0UL) /*!< SHIFTBUFBBS (Bit 0) */
|
|
#define EIO_SHIFTBUFBBS0_SHIFTBUFBBS_Msk (0xffffffffUL) /*!< SHIFTBUFBBS (Bitfield-Mask: 0xffffffff) */
|
|
/* =================================================== EIO_SHIFTBUFBBS1 ==================================================== */
|
|
#define EIO_SHIFTBUFBBS1_SHIFTBUFBBS_Pos (0UL) /*!< SHIFTBUFBBS (Bit 0) */
|
|
#define EIO_SHIFTBUFBBS1_SHIFTBUFBBS_Msk (0xffffffffUL) /*!< SHIFTBUFBBS (Bitfield-Mask: 0xffffffff) */
|
|
/* =================================================== EIO_SHIFTBUFBBS2 ==================================================== */
|
|
#define EIO_SHIFTBUFBBS2_SHIFTBUFBBS_Pos (0UL) /*!< SHIFTBUFBBS (Bit 0) */
|
|
#define EIO_SHIFTBUFBBS2_SHIFTBUFBBS_Msk (0xffffffffUL) /*!< SHIFTBUFBBS (Bitfield-Mask: 0xffffffff) */
|
|
/* =================================================== EIO_SHIFTBUFBBS3 ==================================================== */
|
|
#define EIO_SHIFTBUFBBS3_SHIFTBUFBBS_Pos (0UL) /*!< SHIFTBUFBBS (Bit 0) */
|
|
#define EIO_SHIFTBUFBBS3_SHIFTBUFBBS_Msk (0xffffffffUL) /*!< SHIFTBUFBBS (Bitfield-Mask: 0xffffffff) */
|
|
/* ====================================================== EIO_TIMCTL0 ====================================================== */
|
|
#define EIO_TIMCTL0_TIMOD_Pos (0UL) /*!< TIMOD (Bit 0) */
|
|
#define EIO_TIMCTL0_TIMOD_Msk (0x3UL) /*!< TIMOD (Bitfield-Mask: 0x03) */
|
|
#define EIO_TIMCTL0_PINPOL_Pos (7UL) /*!< PINPOL (Bit 7) */
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#define EIO_TIMCTL0_PINPOL_Msk (0x80UL) /*!< PINPOL (Bitfield-Mask: 0x01) */
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#define EIO_TIMCTL0_PINSEL_Pos (8UL) /*!< PINSEL (Bit 8) */
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#define EIO_TIMCTL0_PINSEL_Msk (0x700UL) /*!< PINSEL (Bitfield-Mask: 0x07) */
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#define EIO_TIMCTL0_PINCFG_Pos (16UL) /*!< PINCFG (Bit 16) */
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#define EIO_TIMCTL0_PINCFG_Msk (0x30000UL) /*!< PINCFG (Bitfield-Mask: 0x03) */
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#define EIO_TIMCTL0_TRGSRC_Pos (22UL) /*!< TRGSRC (Bit 22) */
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#define EIO_TIMCTL0_TRGSRC_Msk (0x400000UL) /*!< TRGSRC (Bitfield-Mask: 0x01) */
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#define EIO_TIMCTL0_TRGPOL_Pos (23UL) /*!< TRGPOL (Bit 23) */
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#define EIO_TIMCTL0_TRGPOL_Msk (0x800000UL) /*!< TRGPOL (Bitfield-Mask: 0x01) */
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#define EIO_TIMCTL0_TRGSEL_Pos (24UL) /*!< TRGSEL (Bit 24) */
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#define EIO_TIMCTL0_TRGSEL_Msk (0xf000000UL) /*!< TRGSEL (Bitfield-Mask: 0x0f) */
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/* ====================================================== EIO_TIMCTL1 ====================================================== */
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#define EIO_TIMCTL1_TIMOD_Pos (0UL) /*!< TIMOD (Bit 0) */
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#define EIO_TIMCTL1_TIMOD_Msk (0x3UL) /*!< TIMOD (Bitfield-Mask: 0x03) */
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#define EIO_TIMCTL1_PINPOL_Pos (7UL) /*!< PINPOL (Bit 7) */
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#define EIO_TIMCTL1_PINPOL_Msk (0x80UL) /*!< PINPOL (Bitfield-Mask: 0x01) */
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#define EIO_TIMCTL1_PINSEL_Pos (8UL) /*!< PINSEL (Bit 8) */
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#define EIO_TIMCTL1_PINSEL_Msk (0x700UL) /*!< PINSEL (Bitfield-Mask: 0x07) */
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#define EIO_TIMCTL1_PINCFG_Pos (16UL) /*!< PINCFG (Bit 16) */
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#define EIO_TIMCTL1_PINCFG_Msk (0x30000UL) /*!< PINCFG (Bitfield-Mask: 0x03) */
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#define EIO_TIMCTL1_TRGSRC_Pos (22UL) /*!< TRGSRC (Bit 22) */
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#define EIO_TIMCTL1_TRGSRC_Msk (0x400000UL) /*!< TRGSRC (Bitfield-Mask: 0x01) */
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#define EIO_TIMCTL1_TRGPOL_Pos (23UL) /*!< TRGPOL (Bit 23) */
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#define EIO_TIMCTL1_TRGPOL_Msk (0x800000UL) /*!< TRGPOL (Bitfield-Mask: 0x01) */
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#define EIO_TIMCTL1_TRGSEL_Pos (24UL) /*!< TRGSEL (Bit 24) */
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#define EIO_TIMCTL1_TRGSEL_Msk (0xf000000UL) /*!< TRGSEL (Bitfield-Mask: 0x0f) */
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/* ====================================================== EIO_TIMCTL2 ====================================================== */
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#define EIO_TIMCTL2_TIMOD_Pos (0UL) /*!< TIMOD (Bit 0) */
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#define EIO_TIMCTL2_TIMOD_Msk (0x3UL) /*!< TIMOD (Bitfield-Mask: 0x03) */
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#define EIO_TIMCTL2_PINPOL_Pos (7UL) /*!< PINPOL (Bit 7) */
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#define EIO_TIMCTL2_PINPOL_Msk (0x80UL) /*!< PINPOL (Bitfield-Mask: 0x01) */
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#define EIO_TIMCTL2_PINSEL_Pos (8UL) /*!< PINSEL (Bit 8) */
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#define EIO_TIMCTL2_PINSEL_Msk (0x700UL) /*!< PINSEL (Bitfield-Mask: 0x07) */
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#define EIO_TIMCTL2_PINCFG_Pos (16UL) /*!< PINCFG (Bit 16) */
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#define EIO_TIMCTL2_PINCFG_Msk (0x30000UL) /*!< PINCFG (Bitfield-Mask: 0x03) */
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#define EIO_TIMCTL2_TRGSRC_Pos (22UL) /*!< TRGSRC (Bit 22) */
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#define EIO_TIMCTL2_TRGSRC_Msk (0x400000UL) /*!< TRGSRC (Bitfield-Mask: 0x01) */
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#define EIO_TIMCTL2_TRGPOL_Pos (23UL) /*!< TRGPOL (Bit 23) */
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#define EIO_TIMCTL2_TRGPOL_Msk (0x800000UL) /*!< TRGPOL (Bitfield-Mask: 0x01) */
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#define EIO_TIMCTL2_TRGSEL_Pos (24UL) /*!< TRGSEL (Bit 24) */
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#define EIO_TIMCTL2_TRGSEL_Msk (0xf000000UL) /*!< TRGSEL (Bitfield-Mask: 0x0f) */
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/* ====================================================== EIO_TIMCTL3 ====================================================== */
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#define EIO_TIMCTL3_TIMOD_Pos (0UL) /*!< TIMOD (Bit 0) */
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#define EIO_TIMCTL3_TIMOD_Msk (0x3UL) /*!< TIMOD (Bitfield-Mask: 0x03) */
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#define EIO_TIMCTL3_PINPOL_Pos (7UL) /*!< PINPOL (Bit 7) */
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#define EIO_TIMCTL3_PINPOL_Msk (0x80UL) /*!< PINPOL (Bitfield-Mask: 0x01) */
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#define EIO_TIMCTL3_PINSEL_Pos (8UL) /*!< PINSEL (Bit 8) */
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#define EIO_TIMCTL3_PINSEL_Msk (0x700UL) /*!< PINSEL (Bitfield-Mask: 0x07) */
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#define EIO_TIMCTL3_PINCFG_Pos (16UL) /*!< PINCFG (Bit 16) */
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#define EIO_TIMCTL3_PINCFG_Msk (0x30000UL) /*!< PINCFG (Bitfield-Mask: 0x03) */
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#define EIO_TIMCTL3_TRGSRC_Pos (22UL) /*!< TRGSRC (Bit 22) */
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#define EIO_TIMCTL3_TRGSRC_Msk (0x400000UL) /*!< TRGSRC (Bitfield-Mask: 0x01) */
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#define EIO_TIMCTL3_TRGPOL_Pos (23UL) /*!< TRGPOL (Bit 23) */
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#define EIO_TIMCTL3_TRGPOL_Msk (0x800000UL) /*!< TRGPOL (Bitfield-Mask: 0x01) */
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#define EIO_TIMCTL3_TRGSEL_Pos (24UL) /*!< TRGSEL (Bit 24) */
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#define EIO_TIMCTL3_TRGSEL_Msk (0xf000000UL) /*!< TRGSEL (Bitfield-Mask: 0x0f) */
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/* ====================================================== EIO_TIMCFG0 ====================================================== */
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#define EIO_TIMCFG0_TSTART_Pos (1UL) /*!< TSTART (Bit 1) */
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#define EIO_TIMCFG0_TSTART_Msk (0x2UL) /*!< TSTART (Bitfield-Mask: 0x01) */
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#define EIO_TIMCFG0_TSTOP_Pos (4UL) /*!< TSTOP (Bit 4) */
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#define EIO_TIMCFG0_TSTOP_Msk (0x30UL) /*!< TSTOP (Bitfield-Mask: 0x03) */
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#define EIO_TIMCFG0_TIMENA_Pos (8UL) /*!< TIMENA (Bit 8) */
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#define EIO_TIMCFG0_TIMENA_Msk (0x700UL) /*!< TIMENA (Bitfield-Mask: 0x07) */
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#define EIO_TIMCFG0_TIMDIS_Pos (12UL) /*!< TIMDIS (Bit 12) */
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#define EIO_TIMCFG0_TIMDIS_Msk (0x7000UL) /*!< TIMDIS (Bitfield-Mask: 0x07) */
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#define EIO_TIMCFG0_TIMRST_Pos (16UL) /*!< TIMRST (Bit 16) */
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#define EIO_TIMCFG0_TIMRST_Msk (0x70000UL) /*!< TIMRST (Bitfield-Mask: 0x07) */
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#define EIO_TIMCFG0_TIMDEC_Pos (20UL) /*!< TIMDEC (Bit 20) */
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#define EIO_TIMCFG0_TIMDEC_Msk (0x300000UL) /*!< TIMDEC (Bitfield-Mask: 0x03) */
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#define EIO_TIMCFG0_TIMOUT_Pos (24UL) /*!< TIMOUT (Bit 24) */
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#define EIO_TIMCFG0_TIMOUT_Msk (0x3000000UL) /*!< TIMOUT (Bitfield-Mask: 0x03) */
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/* ====================================================== EIO_TIMCFG1 ====================================================== */
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#define EIO_TIMCFG1_TSTART_Pos (1UL) /*!< TSTART (Bit 1) */
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#define EIO_TIMCFG1_TSTART_Msk (0x2UL) /*!< TSTART (Bitfield-Mask: 0x01) */
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#define EIO_TIMCFG1_TSTOP_Pos (4UL) /*!< TSTOP (Bit 4) */
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#define EIO_TIMCFG1_TSTOP_Msk (0x30UL) /*!< TSTOP (Bitfield-Mask: 0x03) */
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#define EIO_TIMCFG1_TIMENA_Pos (8UL) /*!< TIMENA (Bit 8) */
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#define EIO_TIMCFG1_TIMENA_Msk (0x700UL) /*!< TIMENA (Bitfield-Mask: 0x07) */
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#define EIO_TIMCFG1_TIMDIS_Pos (12UL) /*!< TIMDIS (Bit 12) */
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#define EIO_TIMCFG1_TIMDIS_Msk (0x7000UL) /*!< TIMDIS (Bitfield-Mask: 0x07) */
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#define EIO_TIMCFG1_TIMRST_Pos (16UL) /*!< TIMRST (Bit 16) */
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#define EIO_TIMCFG1_TIMRST_Msk (0x70000UL) /*!< TIMRST (Bitfield-Mask: 0x07) */
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#define EIO_TIMCFG1_TIMDEC_Pos (20UL) /*!< TIMDEC (Bit 20) */
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#define EIO_TIMCFG1_TIMDEC_Msk (0x300000UL) /*!< TIMDEC (Bitfield-Mask: 0x03) */
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#define EIO_TIMCFG1_TIMOUT_Pos (24UL) /*!< TIMOUT (Bit 24) */
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#define EIO_TIMCFG1_TIMOUT_Msk (0x3000000UL) /*!< TIMOUT (Bitfield-Mask: 0x03) */
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/* ====================================================== EIO_TIMCFG2 ====================================================== */
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#define EIO_TIMCFG2_TSTART_Pos (1UL) /*!< TSTART (Bit 1) */
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#define EIO_TIMCFG2_TSTART_Msk (0x2UL) /*!< TSTART (Bitfield-Mask: 0x01) */
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#define EIO_TIMCFG2_TSTOP_Pos (4UL) /*!< TSTOP (Bit 4) */
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#define EIO_TIMCFG2_TSTOP_Msk (0x30UL) /*!< TSTOP (Bitfield-Mask: 0x03) */
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#define EIO_TIMCFG2_TIMENA_Pos (8UL) /*!< TIMENA (Bit 8) */
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#define EIO_TIMCFG2_TIMENA_Msk (0x700UL) /*!< TIMENA (Bitfield-Mask: 0x07) */
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#define EIO_TIMCFG2_TIMDIS_Pos (12UL) /*!< TIMDIS (Bit 12) */
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#define EIO_TIMCFG2_TIMDIS_Msk (0x7000UL) /*!< TIMDIS (Bitfield-Mask: 0x07) */
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#define EIO_TIMCFG2_TIMRST_Pos (16UL) /*!< TIMRST (Bit 16) */
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#define EIO_TIMCFG2_TIMRST_Msk (0x70000UL) /*!< TIMRST (Bitfield-Mask: 0x07) */
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#define EIO_TIMCFG2_TIMDEC_Pos (20UL) /*!< TIMDEC (Bit 20) */
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#define EIO_TIMCFG2_TIMDEC_Msk (0x300000UL) /*!< TIMDEC (Bitfield-Mask: 0x03) */
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#define EIO_TIMCFG2_TIMOUT_Pos (24UL) /*!< TIMOUT (Bit 24) */
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#define EIO_TIMCFG2_TIMOUT_Msk (0x3000000UL) /*!< TIMOUT (Bitfield-Mask: 0x03) */
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/* ====================================================== EIO_TIMCFG3 ====================================================== */
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#define EIO_TIMCFG3_TSTART_Pos (1UL) /*!< TSTART (Bit 1) */
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#define EIO_TIMCFG3_TSTART_Msk (0x2UL) /*!< TSTART (Bitfield-Mask: 0x01) */
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#define EIO_TIMCFG3_TSTOP_Pos (4UL) /*!< TSTOP (Bit 4) */
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#define EIO_TIMCFG3_TSTOP_Msk (0x30UL) /*!< TSTOP (Bitfield-Mask: 0x03) */
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#define EIO_TIMCFG3_TIMENA_Pos (8UL) /*!< TIMENA (Bit 8) */
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#define EIO_TIMCFG3_TIMENA_Msk (0x700UL) /*!< TIMENA (Bitfield-Mask: 0x07) */
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#define EIO_TIMCFG3_TIMDIS_Pos (12UL) /*!< TIMDIS (Bit 12) */
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#define EIO_TIMCFG3_TIMDIS_Msk (0x7000UL) /*!< TIMDIS (Bitfield-Mask: 0x07) */
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#define EIO_TIMCFG3_TIMRST_Pos (16UL) /*!< TIMRST (Bit 16) */
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#define EIO_TIMCFG3_TIMRST_Msk (0x70000UL) /*!< TIMRST (Bitfield-Mask: 0x07) */
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#define EIO_TIMCFG3_TIMDEC_Pos (20UL) /*!< TIMDEC (Bit 20) */
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#define EIO_TIMCFG3_TIMDEC_Msk (0x300000UL) /*!< TIMDEC (Bitfield-Mask: 0x03) */
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#define EIO_TIMCFG3_TIMOUT_Pos (24UL) /*!< TIMOUT (Bit 24) */
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#define EIO_TIMCFG3_TIMOUT_Msk (0x3000000UL) /*!< TIMOUT (Bitfield-Mask: 0x03) */
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/* ====================================================== EIO_TIMCMP0 ====================================================== */
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#define EIO_TIMCMP0_CMP_Pos (0UL) /*!< CMP (Bit 0) */
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#define EIO_TIMCMP0_CMP_Msk (0xffffUL) /*!< CMP (Bitfield-Mask: 0xffff) */
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/* ====================================================== EIO_TIMCMP1 ====================================================== */
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#define EIO_TIMCMP1_CMP_Pos (0UL) /*!< CMP (Bit 0) */
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#define EIO_TIMCMP1_CMP_Msk (0xffffUL) /*!< CMP (Bitfield-Mask: 0xffff) */
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/* ====================================================== EIO_TIMCMP2 ====================================================== */
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#define EIO_TIMCMP2_CMP_Pos (0UL) /*!< CMP (Bit 0) */
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#define EIO_TIMCMP2_CMP_Msk (0xffffUL) /*!< CMP (Bitfield-Mask: 0xffff) */
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/* ====================================================== EIO_TIMCMP3 ====================================================== */
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#define EIO_TIMCMP3_CMP_Pos (0UL) /*!< CMP (Bit 0) */
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#define EIO_TIMCMP3_CMP_Msk (0xffffUL) /*!< CMP (Bitfield-Mask: 0xffff) */
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/* =========================================================================================================================== */
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/* ================ EWDG ================ */
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/* =========================================================================================================================== */
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/* ========================================================= CTRL ========================================================== */
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#define EWDG_CTRL_EWDGEN_Pos (0UL) /*!< EWDGEN (Bit 0) */
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#define EWDG_CTRL_EWDGEN_Msk (0x1UL) /*!< EWDGEN (Bitfield-Mask: 0x01) */
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#define EWDG_CTRL_ASSIN_Pos (1UL) /*!< ASSIN (Bit 1) */
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#define EWDG_CTRL_ASSIN_Msk (0x2UL) /*!< ASSIN (Bitfield-Mask: 0x01) */
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#define EWDG_CTRL_INEN_Pos (2UL) /*!< INEN (Bit 2) */
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#define EWDG_CTRL_INEN_Msk (0x4UL) /*!< INEN (Bitfield-Mask: 0x01) */
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#define EWDG_CTRL_INTEN_Pos (3UL) /*!< INTEN (Bit 3) */
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#define EWDG_CTRL_INTEN_Msk (0x8UL) /*!< INTEN (Bitfield-Mask: 0x01) */
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/* ========================================================= SERV ========================================================== */
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#define EWDG_SERV_SERVICE_Pos (0UL) /*!< SERVICE (Bit 0) */
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#define EWDG_SERV_SERVICE_Msk (0xffUL) /*!< SERVICE (Bitfield-Mask: 0xff) */
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/* ========================================================= CMPL ========================================================== */
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#define EWDG_CMPL_COMPAREL_Pos (0UL) /*!< COMPAREL (Bit 0) */
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#define EWDG_CMPL_COMPAREL_Msk (0xffUL) /*!< COMPAREL (Bitfield-Mask: 0xff) */
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/* ========================================================= CMPH ========================================================== */
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#define EWDG_CMPH_COMPAREH_Pos (0UL) /*!< COMPAREH (Bit 0) */
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#define EWDG_CMPH_COMPAREH_Msk (0xffUL) /*!< COMPAREH (Bitfield-Mask: 0xff) */
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/* ===================================================== CLKPRESCALER ====================================================== */
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#define EWDG_CLKPRESCALER_CLK_DIV_Pos (0UL) /*!< CLK_DIV (Bit 0) */
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#define EWDG_CLKPRESCALER_CLK_DIV_Msk (0xffUL) /*!< CLK_DIV (Bitfield-Mask: 0xff) */
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/* =========================================================================================================================== */
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/* ================ AC784X_SysTick ================ */
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/* =========================================================================================================================== */
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/* ======================================================= AC784X_SysTick_CSR ============================================== */
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#define AC784X_SysTick_CSR_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
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#define AC784X_SysTick_CSR_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
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#define AC784X_SysTick_CSR_TICKINT_Pos (1UL) /*!< TICKINT (Bit 1) */
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#define AC784X_SysTick_CSR_TICKINT_Msk (0x2UL) /*!< TICKINT (Bitfield-Mask: 0x01) */
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#define AC784X_SysTick_CSR_CLKSOURCE_Pos (2UL) /*!< CLKSOURCE (Bit 2) */
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#define AC784X_SysTick_CSR_CLKSOURCE_Msk (0x4UL) /*!< CLKSOURCE (Bitfield-Mask: 0x01) */
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#define AC784X_SysTick_CSR_COUNTFLAG_Pos (16UL) /*!< COUNTFLAG (Bit 16) */
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#define AC784X_SysTick_CSR_COUNTFLAG_Msk (0x0x10000UL) /*!< COUNTFLAG (Bitfield-Mask: 0x01) */
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/* ======================================================= AC784X_SysTick_RVR ============================================== */
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#define AC784X_SysTick_RVR_RELOAD_Pos (0UL) /*!< RELOAD (Bit 0) */
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#define AC784X_SysTick_RVR_RELOAD_Msk (0xFFFFFFUL) /*!< RELOAD (Bitfield-Mask: 0xFFFFFF) */
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/* ======================================================= AC784X_SysTick_CVR ============================================== */
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#define AC784X_SysTick_CVR_CURRENT_Pos (0UL) /*!< CURRENT (Bit 0) */
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#define AC784X_SysTick_CVR_CURRENT_Msk (0xFFFFFFUL) /*!< CURRENT (Bitfield-Mask: 0xFFFFFF) */
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/* ======================================================= AC784X_SysTick_CALIB ============================================ */
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#define AC784X_SysTick_CALIB_TENMS_Pos (0UL) /*!< TENMS (Bit 0) */
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#define AC784X_SysTick_CALIB_TENMS_Msk (0xFFFFFFUL) /*!< TENMS (Bitfield-Mask: 0x0FFFFFF) */
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#define AC784X_SysTick_CALIB_SKEW_Pos (30UL) /*!< SKEW (Bit 30) */
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#define AC784X_SysTick_CALIB_SKEW_Msk (0x40000000L) /*!< SKEW (Bitfield-Mask: 0x01) */
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#define AC784X_SysTick_CALIB_NOREF_Pos (31UL) /*!< NOREF (Bit 31) */
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#define AC784X_SysTick_CALIB_NOREF_Msk (0x80000000UL) /*!< NOREF (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ SMU ================ */
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/* =========================================================================================================================== */
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/* ========================================================= SFES ========================================================== */
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#define SMU_SFES_HWSFES0_Pos (0UL) /*!< HWSFES0 (Bit 0) */
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#define SMU_SFES_HWSFES0_Msk (0x1UL) /*!< HWSFES0 (Bitfield-Mask: 0x01) */
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#define SMU_SFES_HWSFES1_Pos (1UL) /*!< HWSFES1 (Bit 1) */
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#define SMU_SFES_HWSFES1_Msk (0x2UL) /*!< HWSFES1 (Bitfield-Mask: 0x01) */
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#define SMU_SFES_HWSFES2_Pos (2UL) /*!< HWSFES2 (Bit 2) */
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#define SMU_SFES_HWSFES2_Msk (0x4UL) /*!< HWSFES2 (Bitfield-Mask: 0x01) */
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#define SMU_SFES_HWSFES3_Pos (3UL) /*!< HWSFES3 (Bit 3) */
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#define SMU_SFES_HWSFES3_Msk (0x8UL) /*!< HWSFES3 (Bitfield-Mask: 0x01) */
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#define SMU_SFES_HWSFES4_Pos (4UL) /*!< HWSFES4 (Bit 4) */
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#define SMU_SFES_HWSFES4_Msk (0x10UL) /*!< HWSFES4 (Bitfield-Mask: 0x01) */
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#define SMU_SFES_HWSFES5_Pos (5UL) /*!< HWSFES5 (Bit 5) */
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#define SMU_SFES_HWSFES5_Msk (0x20UL) /*!< HWSFES5 (Bitfield-Mask: 0x01) */
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#define SMU_SFES_HWSFES6_Pos (6UL) /*!< HWSFES6 (Bit 6) */
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#define SMU_SFES_HWSFES6_Msk (0x40UL) /*!< HWSFES6 (Bitfield-Mask: 0x01) */
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#define SMU_SFES_HWSFES7_Pos (7UL) /*!< HWSFES7 (Bit 7) */
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|
#define SMU_SFES_HWSFES7_Msk (0x80UL) /*!< HWSFES7 (Bitfield-Mask: 0x01) */
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#define SMU_SFES_HWSFES8_Pos (8UL) /*!< HWSFES8 (Bit 8) */
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|
#define SMU_SFES_HWSFES8_Msk (0x100UL) /*!< HWSFES8 (Bitfield-Mask: 0x01) */
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|
#define SMU_SFES_HWSFES9_Pos (9UL) /*!< HWSFES9 (Bit 9) */
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|
#define SMU_SFES_HWSFES9_Msk (0x200UL) /*!< HWSFES9 (Bitfield-Mask: 0x01) */
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|
#define SMU_SFES_HWSFES10_Pos (10UL) /*!< HWSFES10 (Bit 10) */
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|
#define SMU_SFES_HWSFES10_Msk (0x400UL) /*!< HWSFES10 (Bitfield-Mask: 0x01) */
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|
#define SMU_SFES_HWSFES11_Pos (11UL) /*!< HWSFES11 (Bit 11) */
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|
#define SMU_SFES_HWSFES11_Msk (0x800UL) /*!< HWSFES11 (Bitfield-Mask: 0x01) */
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|
#define SMU_SFES_HWSFES12_Pos (12UL) /*!< HWSFES12 (Bit 12) */
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|
#define SMU_SFES_HWSFES12_Msk (0x1000UL) /*!< HWSFES12 (Bitfield-Mask: 0x01) */
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|
#define SMU_SFES_HWSFES13_Pos (13UL) /*!< HWSFES13 (Bit 13) */
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|
#define SMU_SFES_HWSFES13_Msk (0x2000UL) /*!< HWSFES13 (Bitfield-Mask: 0x01) */
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|
#define SMU_SFES_HWSFES14_Pos (14UL) /*!< HWSFES14 (Bit 14) */
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|
#define SMU_SFES_HWSFES14_Msk (0x4000UL) /*!< HWSFES14 (Bitfield-Mask: 0x01) */
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|
#define SMU_SFES_HWSFES15_Pos (15UL) /*!< HWSFES15 (Bit 15) */
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|
#define SMU_SFES_HWSFES15_Msk (0x8000UL) /*!< HWSFES15 (Bitfield-Mask: 0x01) */
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|
#define SMU_SFES_HWSFES16_Pos (16UL) /*!< HWSFES16 (Bit 16) */
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|
#define SMU_SFES_HWSFES16_Msk (0x10000UL) /*!< HWSFES16 (Bitfield-Mask: 0x01) */
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|
#define SMU_SFES_HWSFES17_Pos (17UL) /*!< HWSFES17 (Bit 17) */
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|
#define SMU_SFES_HWSFES17_Msk (0x20000UL) /*!< HWSFES17 (Bitfield-Mask: 0x01) */
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|
#define SMU_SFES_SWSFES_Pos (18UL) /*!< SWSFES (Bit 18) */
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|
#define SMU_SFES_SWSFES_Msk (0x40000UL) /*!< SWSFES (Bitfield-Mask: 0x01) */
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|
/* ========================================================= SFESS ========================================================= */
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#define SMU_SFESS_HWSFES0_Pos (0UL) /*!< HWSFES0 (Bit 0) */
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#define SMU_SFESS_HWSFES0_Msk (0x1UL) /*!< HWSFES0 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES1_Pos (1UL) /*!< HWSFES1 (Bit 1) */
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#define SMU_SFESS_HWSFES1_Msk (0x2UL) /*!< HWSFES1 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES2_Pos (2UL) /*!< HWSFES2 (Bit 2) */
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#define SMU_SFESS_HWSFES2_Msk (0x4UL) /*!< HWSFES2 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES3_Pos (3UL) /*!< HWSFES3 (Bit 3) */
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#define SMU_SFESS_HWSFES3_Msk (0x8UL) /*!< HWSFES3 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES4_Pos (4UL) /*!< HWSFES4 (Bit 4) */
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#define SMU_SFESS_HWSFES4_Msk (0x10UL) /*!< HWSFES4 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES5_Pos (5UL) /*!< HWSFES5 (Bit 5) */
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#define SMU_SFESS_HWSFES5_Msk (0x20UL) /*!< HWSFES5 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES6_Pos (6UL) /*!< HWSFES6 (Bit 6) */
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#define SMU_SFESS_HWSFES6_Msk (0x40UL) /*!< HWSFES6 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES7_Pos (7UL) /*!< HWSFES7 (Bit 7) */
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#define SMU_SFESS_HWSFES7_Msk (0x80UL) /*!< HWSFES7 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES8_Pos (8UL) /*!< HWSFES8 (Bit 8) */
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#define SMU_SFESS_HWSFES8_Msk (0x100UL) /*!< HWSFES8 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES9_Pos (9UL) /*!< HWSFES9 (Bit 9) */
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#define SMU_SFESS_HWSFES9_Msk (0x200UL) /*!< HWSFES9 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES10_Pos (10UL) /*!< HWSFES10 (Bit 10) */
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#define SMU_SFESS_HWSFES10_Msk (0x400UL) /*!< HWSFES10 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES11_Pos (11UL) /*!< HWSFES11 (Bit 11) */
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#define SMU_SFESS_HWSFES11_Msk (0x800UL) /*!< HWSFES11 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES12_Pos (12UL) /*!< HWSFES12 (Bit 12) */
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#define SMU_SFESS_HWSFES12_Msk (0x1000UL) /*!< HWSFES12 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES13_Pos (13UL) /*!< HWSFES13 (Bit 13) */
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#define SMU_SFESS_HWSFES13_Msk (0x2000UL) /*!< HWSFES13 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES14_Pos (14UL) /*!< HWSFES14 (Bit 14) */
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#define SMU_SFESS_HWSFES14_Msk (0x4000UL) /*!< HWSFES14 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES15_Pos (15UL) /*!< HWSFES15 (Bit 15) */
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#define SMU_SFESS_HWSFES15_Msk (0x8000UL) /*!< HWSFES15 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES16_Pos (16UL) /*!< HWSFES16 (Bit 16) */
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#define SMU_SFESS_HWSFES16_Msk (0x10000UL) /*!< HWSFES16 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_HWSFES17_Pos (17UL) /*!< HWSFES17 (Bit 17) */
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#define SMU_SFESS_HWSFES17_Msk (0x20000UL) /*!< HWSFES17 (Bitfield-Mask: 0x01) */
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#define SMU_SFESS_SWSFES_Pos (18UL) /*!< SWSFES (Bit 18) */
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#define SMU_SFESS_SWSFES_Msk (0x40000UL) /*!< SWSFES (Bitfield-Mask: 0x01) */
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/* ========================================================= LFES ========================================================== */
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#define SMU_LFES_HWLFES0_Pos (0UL) /*!< HWLFES0 (Bit 0) */
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#define SMU_LFES_HWLFES0_Msk (0x1UL) /*!< HWLFES0 (Bitfield-Mask: 0x01) */
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#define SMU_LFES_HWLFES1_Pos (1UL) /*!< HWLFES1 (Bit 1) */
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#define SMU_LFES_HWLFES1_Msk (0x2UL) /*!< HWLFES1 (Bitfield-Mask: 0x01) */
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#define SMU_LFES_HWLFES2_Pos (2UL) /*!< HWLFES2 (Bit 2) */
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#define SMU_LFES_HWLFES2_Msk (0x4UL) /*!< HWLFES2 (Bitfield-Mask: 0x01) */
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#define SMU_LFES_HWLFES3_Pos (3UL) /*!< HWLFES3 (Bit 3) */
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#define SMU_LFES_HWLFES3_Msk (0x8UL) /*!< HWLFES3 (Bitfield-Mask: 0x01) */
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#define SMU_LFES_HWLFES4_Pos (4UL) /*!< HWLFES4 (Bit 4) */
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#define SMU_LFES_HWLFES4_Msk (0x10UL) /*!< HWLFES4 (Bitfield-Mask: 0x01) */
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#define SMU_LFES_SWLFES_Pos (5UL) /*!< SWLFES (Bit 5) */
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#define SMU_LFES_SWLFES_Msk (0x20UL) /*!< SWLFES (Bitfield-Mask: 0x01) */
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/* ========================================================= LFESS ========================================================= */
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#define SMU_LFESS_HWLFES0_Pos (0UL) /*!< HWLFES0 (Bit 0) */
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#define SMU_LFESS_HWLFES0_Msk (0x1UL) /*!< HWLFES0 (Bitfield-Mask: 0x01) */
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#define SMU_LFESS_HWLFES1_Pos (1UL) /*!< HWLFES1 (Bit 1) */
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#define SMU_LFESS_HWLFES1_Msk (0x2UL) /*!< HWLFES1 (Bitfield-Mask: 0x01) */
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#define SMU_LFESS_HWLFES2_Pos (2UL) /*!< HWLFES2 (Bit 2) */
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#define SMU_LFESS_HWLFES2_Msk (0x4UL) /*!< HWLFES2 (Bitfield-Mask: 0x01) */
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#define SMU_LFESS_HWLFES3_Pos (3UL) /*!< HWLFES3 (Bit 3) */
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#define SMU_LFESS_HWLFES3_Msk (0x8UL) /*!< HWLFES3 (Bitfield-Mask: 0x01) */
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#define SMU_LFESS_HWLFES4_Pos (4UL) /*!< HWLFES4 (Bit 4) */
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#define SMU_LFESS_HWLFES4_Msk (0x10UL) /*!< HWLFES4 (Bitfield-Mask: 0x01) */
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#define SMU_LFESS_SWLFES_Pos (5UL) /*!< SWLFES (Bit 5) */
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#define SMU_LFESS_SWLFES_Msk (0x20UL) /*!< SWLFES (Bitfield-Mask: 0x01) */
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/* ======================================================== LKSEQ0 ========================================================= */
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#define SMU_LKSEQ0_LKSEQ0_Pos (0UL) /*!< LKSEQ0 (Bit 0) */
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#define SMU_LKSEQ0_LKSEQ0_Msk (0xffUL) /*!< LKSEQ0 (Bitfield-Mask: 0xff) */
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/* ======================================================== LKSEQ1 ========================================================= */
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#define SMU_LKSEQ1_LKSEQ1_Pos (0UL) /*!< LKSEQ1 (Bit 0) */
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#define SMU_LKSEQ1_LKSEQ1_Msk (0xffUL) /*!< LKSEQ1 (Bitfield-Mask: 0xff) */
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/* ========================================================= SWSFE ========================================================= */
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#define SMU_SWSFE_SWSFE0_Pos (0UL) /*!< SWSFE0 (Bit 0) */
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#define SMU_SWSFE_SWSFE0_Msk (0x1UL) /*!< SWSFE0 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFE_SWSFE1_Pos (1UL) /*!< SWSFE1 (Bit 1) */
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#define SMU_SWSFE_SWSFE1_Msk (0x2UL) /*!< SWSFE1 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFE_SWSFE2_Pos (2UL) /*!< SWSFE2 (Bit 2) */
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#define SMU_SWSFE_SWSFE2_Msk (0x4UL) /*!< SWSFE2 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFE_SWSFE3_Pos (3UL) /*!< SWSFE3 (Bit 3) */
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#define SMU_SWSFE_SWSFE3_Msk (0x8UL) /*!< SWSFE3 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFE_SWSFE4_Pos (4UL) /*!< SWSFE4 (Bit 4) */
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#define SMU_SWSFE_SWSFE4_Msk (0x10UL) /*!< SWSFE4 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFE_SWSFE5_Pos (5UL) /*!< SWSFE5 (Bit 5) */
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#define SMU_SWSFE_SWSFE5_Msk (0x20UL) /*!< SWSFE5 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFE_SWSFE6_Pos (6UL) /*!< SWSFE6 (Bit 6) */
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#define SMU_SWSFE_SWSFE6_Msk (0x40UL) /*!< SWSFE6 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFE_SWSFE7_Pos (7UL) /*!< SWSFE7 (Bit 7) */
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#define SMU_SWSFE_SWSFE7_Msk (0x80UL) /*!< SWSFE7 (Bitfield-Mask: 0x01) */
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/* ======================================================== SWSFES ========================================================= */
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#define SMU_SWSFES_SWSFES0_Pos (0UL) /*!< SWSFES0 (Bit 0) */
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#define SMU_SWSFES_SWSFES0_Msk (0x1UL) /*!< SWSFES0 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFES_SWSFES1_Pos (1UL) /*!< SWSFES1 (Bit 1) */
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#define SMU_SWSFES_SWSFES1_Msk (0x2UL) /*!< SWSFES1 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFES_SWSFES2_Pos (2UL) /*!< SWSFES2 (Bit 2) */
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#define SMU_SWSFES_SWSFES2_Msk (0x4UL) /*!< SWSFES2 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFES_SWSFES3_Pos (3UL) /*!< SWSFES3 (Bit 3) */
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#define SMU_SWSFES_SWSFES3_Msk (0x8UL) /*!< SWSFES3 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFES_SWSFES4_Pos (4UL) /*!< SWSFES4 (Bit 4) */
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#define SMU_SWSFES_SWSFES4_Msk (0x10UL) /*!< SWSFES4 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFES_SWSFES5_Pos (5UL) /*!< SWSFES5 (Bit 5) */
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#define SMU_SWSFES_SWSFES5_Msk (0x20UL) /*!< SWSFES5 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFES_SWSFES6_Pos (6UL) /*!< SWSFES6 (Bit 6) */
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#define SMU_SWSFES_SWSFES6_Msk (0x40UL) /*!< SWSFES6 (Bitfield-Mask: 0x01) */
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#define SMU_SWSFES_SWSFES7_Pos (7UL) /*!< SWSFES7 (Bit 7) */
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#define SMU_SWSFES_SWSFES7_Msk (0x80UL) /*!< SWSFES7 (Bitfield-Mask: 0x01) */
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/* ========================================================= SWLFE ========================================================= */
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#define SMU_SWLFE_SWLFE0_Pos (0UL) /*!< SWLFE0 (Bit 0) */
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#define SMU_SWLFE_SWLFE0_Msk (0x1UL) /*!< SWLFE0 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFE_SWSLE1_Pos (1UL) /*!< SWSLE1 (Bit 1) */
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#define SMU_SWLFE_SWSLE1_Msk (0x2UL) /*!< SWSLE1 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFE_SWLFE2_Pos (2UL) /*!< SWLFE2 (Bit 2) */
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#define SMU_SWLFE_SWLFE2_Msk (0x4UL) /*!< SWLFE2 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFE_SWLFE3_Pos (3UL) /*!< SWLFE3 (Bit 3) */
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#define SMU_SWLFE_SWLFE3_Msk (0x8UL) /*!< SWLFE3 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFE_SWLFE4_Pos (4UL) /*!< SWLFE4 (Bit 4) */
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#define SMU_SWLFE_SWLFE4_Msk (0x10UL) /*!< SWLFE4 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFE_SWLFE5_Pos (5UL) /*!< SWLFE5 (Bit 5) */
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#define SMU_SWLFE_SWLFE5_Msk (0x20UL) /*!< SWLFE5 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFE_SWLFE6_Pos (6UL) /*!< SWLFE6 (Bit 6) */
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#define SMU_SWLFE_SWLFE6_Msk (0x40UL) /*!< SWLFE6 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFE_SWLFE7_Pos (7UL) /*!< SWLFE7 (Bit 7) */
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#define SMU_SWLFE_SWLFE7_Msk (0x80UL) /*!< SWLFE7 (Bitfield-Mask: 0x01) */
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/* ======================================================== SWLFES ========================================================= */
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#define SMU_SWLFES_SWLFES0_Pos (0UL) /*!< SWLFES0 (Bit 0) */
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#define SMU_SWLFES_SWLFES0_Msk (0x1UL) /*!< SWLFES0 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFES_SWLFES1_Pos (1UL) /*!< SWLFES1 (Bit 1) */
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#define SMU_SWLFES_SWLFES1_Msk (0x2UL) /*!< SWLFES1 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFES_SWLFES2_Pos (2UL) /*!< SWLFES2 (Bit 2) */
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#define SMU_SWLFES_SWLFES2_Msk (0x4UL) /*!< SWLFES2 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFES_SWLFES3_Pos (3UL) /*!< SWLFES3 (Bit 3) */
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#define SMU_SWLFES_SWLFES3_Msk (0x8UL) /*!< SWLFES3 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFES_SWLFES4_Pos (4UL) /*!< SWLFES4 (Bit 4) */
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#define SMU_SWLFES_SWLFES4_Msk (0x10UL) /*!< SWLFES4 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFES_SWLFES5_Pos (5UL) /*!< SWLFES5 (Bit 5) */
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#define SMU_SWLFES_SWLFES5_Msk (0x20UL) /*!< SWLFES5 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFES_SWLFES6_Pos (6UL) /*!< SWLFES6 (Bit 6) */
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#define SMU_SWLFES_SWLFES6_Msk (0x40UL) /*!< SWLFES6 (Bitfield-Mask: 0x01) */
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#define SMU_SWLFES_SWSFES7_Pos (7UL) /*!< SWSFES7 (Bit 7) */
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#define SMU_SWLFES_SWSFES7_Msk (0x80UL) /*!< SWSFES7 (Bitfield-Mask: 0x01) */
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/* ======================================================== SFRSTEN ======================================================== */
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#define SMU_SFRSTEN_HWSFRSTE0_Pos (0UL) /*!< HWSFRSTE0 (Bit 0) */
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#define SMU_SFRSTEN_HWSFRSTE0_Msk (0x1UL) /*!< HWSFRSTE0 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE1_Pos (1UL) /*!< HWSFRSTE1 (Bit 1) */
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#define SMU_SFRSTEN_HWSFRSTE1_Msk (0x2UL) /*!< HWSFRSTE1 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE2_Pos (2UL) /*!< HWSFRSTE2 (Bit 2) */
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#define SMU_SFRSTEN_HWSFRSTE2_Msk (0x4UL) /*!< HWSFRSTE2 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE3_Pos (3UL) /*!< HWSFRSTE3 (Bit 3) */
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#define SMU_SFRSTEN_HWSFRSTE3_Msk (0x8UL) /*!< HWSFRSTE3 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE4_Pos (4UL) /*!< HWSFRSTE4 (Bit 4) */
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#define SMU_SFRSTEN_HWSFRSTE4_Msk (0x10UL) /*!< HWSFRSTE4 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE5_Pos (5UL) /*!< HWSFRSTE5 (Bit 5) */
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#define SMU_SFRSTEN_HWSFRSTE5_Msk (0x20UL) /*!< HWSFRSTE5 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE6_Pos (6UL) /*!< HWSFRSTE6 (Bit 6) */
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#define SMU_SFRSTEN_HWSFRSTE6_Msk (0x40UL) /*!< HWSFRSTE6 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE7_Pos (7UL) /*!< HWSFRSTE7 (Bit 7) */
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#define SMU_SFRSTEN_HWSFRSTE7_Msk (0x80UL) /*!< HWSFRSTE7 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE8_Pos (8UL) /*!< HWSFRSTE8 (Bit 8) */
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#define SMU_SFRSTEN_HWSFRSTE8_Msk (0x100UL) /*!< HWSFRSTE8 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE9_Pos (9UL) /*!< HWSFRSTE9 (Bit 9) */
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#define SMU_SFRSTEN_HWSFRSTE9_Msk (0x200UL) /*!< HWSFRSTE9 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE10_Pos (10UL) /*!< HWSFRSTE10 (Bit 10) */
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#define SMU_SFRSTEN_HWSFRSTE10_Msk (0x400UL) /*!< HWSFRSTE10 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE11_Pos (11UL) /*!< HWSFRSTE11 (Bit 11) */
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#define SMU_SFRSTEN_HWSFRSTE11_Msk (0x800UL) /*!< HWSFRSTE11 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE12_Pos (12UL) /*!< HWSFRSTE12 (Bit 12) */
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#define SMU_SFRSTEN_HWSFRSTE12_Msk (0x1000UL) /*!< HWSFRSTE12 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE13_Pos (13UL) /*!< HWSFRSTE13 (Bit 13) */
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#define SMU_SFRSTEN_HWSFRSTE13_Msk (0x2000UL) /*!< HWSFRSTE13 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE14_Pos (14UL) /*!< HWSFRSTE14 (Bit 14) */
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#define SMU_SFRSTEN_HWSFRSTE14_Msk (0x4000UL) /*!< HWSFRSTE14 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE15_Pos (15UL) /*!< HWSFRSTE15 (Bit 15) */
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#define SMU_SFRSTEN_HWSFRSTE15_Msk (0x8000UL) /*!< HWSFRSTE15 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE16_Pos (16UL) /*!< HWSFRSTE16 (Bit 16) */
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#define SMU_SFRSTEN_HWSFRSTE16_Msk (0x10000UL) /*!< HWSFRSTE16 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_HWSFRSTE17_Pos (17UL) /*!< HWSFRSTE17 (Bit 17) */
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#define SMU_SFRSTEN_HWSFRSTE17_Msk (0x20000UL) /*!< HWSFRSTE17 (Bitfield-Mask: 0x01) */
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#define SMU_SFRSTEN_SWSFRSTE_Pos (18UL) /*!< SWSFRSTE (Bit 18) */
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#define SMU_SFRSTEN_SWSFRSTE_Msk (0x40000UL) /*!< SWSFRSTE (Bitfield-Mask: 0x01) */
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/* ======================================================== LFRSTEN ======================================================== */
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#define SMU_LFRSTEN_HWLFRSTE0_Pos (0UL) /*!< HWLFRSTE0 (Bit 0) */
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#define SMU_LFRSTEN_HWLFRSTE0_Msk (0x1UL) /*!< HWLFRSTE0 (Bitfield-Mask: 0x01) */
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#define SMU_LFRSTEN_HWLFRSTE1_Pos (1UL) /*!< HWLFRSTE1 (Bit 1) */
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#define SMU_LFRSTEN_HWLFRSTE1_Msk (0x2UL) /*!< HWLFRSTE1 (Bitfield-Mask: 0x01) */
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#define SMU_LFRSTEN_HWLFRSTE2_Pos (2UL) /*!< HWLFRSTE2 (Bit 2) */
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#define SMU_LFRSTEN_HWLFRSTE2_Msk (0x4UL) /*!< HWLFRSTE2 (Bitfield-Mask: 0x01) */
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#define SMU_LFRSTEN_HWLFRSTE3_Pos (3UL) /*!< HWLFRSTE3 (Bit 3) */
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#define SMU_LFRSTEN_HWLFRSTE3_Msk (0x8UL) /*!< HWLFRSTE3 (Bitfield-Mask: 0x01) */
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#define SMU_LFRSTEN_HWLFRSTE4_Pos (4UL) /*!< HWLFRSTE4 (Bit 4) */
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#define SMU_LFRSTEN_HWLFRSTE4_Msk (0x10UL) /*!< HWLFRSTE4 (Bitfield-Mask: 0x01) */
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#define SMU_LFRSTEN_SWLFRSTE_Pos (5UL) /*!< SWLFRSTE (Bit 5) */
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#define SMU_LFRSTEN_SWLFRSTE_Msk (0x20UL) /*!< SWLFRSTE (Bitfield-Mask: 0x01) */
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/* ====================================================== SRSTCNTVAL ======================================================= */
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#define SMU_SRSTCNTVAL_SRSTCNTVAL_Pos (0UL) /*!< SRSTCNTVAL (Bit 0) */
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#define SMU_SRSTCNTVAL_SRSTCNTVAL_Msk (0xfUL) /*!< SRSTCNTVAL (Bitfield-Mask: 0x0f) */
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/* ======================================================== SRSTCNT ======================================================== */
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#define SMU_SRSTCNT_SRSTCNT_Pos (0UL) /*!< SRSTCNT (Bit 0) */
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#define SMU_SRSTCNT_SRSTCNT_Msk (0xfUL) /*!< SRSTCNT (Bitfield-Mask: 0x0f) */
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/* ======================================================= SRSTCNTS ======================================================== */
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#define SMU_SRSTCNTS_SRSTCNTS_Pos (0UL) /*!< SRSTCNTS (Bit 0) */
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#define SMU_SRSTCNTS_SRSTCNTS_Msk (0xfUL) /*!< SRSTCNTS (Bitfield-Mask: 0x0f) */
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/* ======================================================= PATHCHK0 ======================================================== */
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#define SMU_PATHCHK0_SEL0_Pos (0UL) /*!< SEL0 (Bit 0) */
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#define SMU_PATHCHK0_SEL0_Msk (0x1UL) /*!< SEL0 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL1_Pos (1UL) /*!< SEL1 (Bit 1) */
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#define SMU_PATHCHK0_SEL1_Msk (0x2UL) /*!< SEL1 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL2_Pos (2UL) /*!< SEL2 (Bit 2) */
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#define SMU_PATHCHK0_SEL2_Msk (0x4UL) /*!< SEL2 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL3_Pos (3UL) /*!< SEL3 (Bit 3) */
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#define SMU_PATHCHK0_SEL3_Msk (0x8UL) /*!< SEL3 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL4_Pos (4UL) /*!< SEL4 (Bit 4) */
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#define SMU_PATHCHK0_SEL4_Msk (0x10UL) /*!< SEL4 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL5_Pos (5UL) /*!< SEL5 (Bit 5) */
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#define SMU_PATHCHK0_SEL5_Msk (0x20UL) /*!< SEL5 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL6_Pos (6UL) /*!< SEL6 (Bit 6) */
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#define SMU_PATHCHK0_SEL6_Msk (0x40UL) /*!< SEL6 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL7_Pos (7UL) /*!< SEL7 (Bit 7) */
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#define SMU_PATHCHK0_SEL7_Msk (0x80UL) /*!< SEL7 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL8_Pos (8UL) /*!< SEL8 (Bit 8) */
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#define SMU_PATHCHK0_SEL8_Msk (0x100UL) /*!< SEL8 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL9_Pos (9UL) /*!< SEL9 (Bit 9) */
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#define SMU_PATHCHK0_SEL9_Msk (0x200UL) /*!< SEL9 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL10_Pos (10UL) /*!< SEL10 (Bit 10) */
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#define SMU_PATHCHK0_SEL10_Msk (0x400UL) /*!< SEL10 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL11_Pos (11UL) /*!< SEL11 (Bit 11) */
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#define SMU_PATHCHK0_SEL11_Msk (0x800UL) /*!< SEL11 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL12_Pos (12UL) /*!< SEL12 (Bit 12) */
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#define SMU_PATHCHK0_SEL12_Msk (0x1000UL) /*!< SEL12 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL13_Pos (13UL) /*!< SEL13 (Bit 13) */
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#define SMU_PATHCHK0_SEL13_Msk (0x2000UL) /*!< SEL13 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL14_Pos (14UL) /*!< SEL14 (Bit 14) */
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#define SMU_PATHCHK0_SEL14_Msk (0x4000UL) /*!< SEL14 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL15_Pos (15UL) /*!< SEL15 (Bit 15) */
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#define SMU_PATHCHK0_SEL15_Msk (0x8000UL) /*!< SEL15 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL16_Pos (16UL) /*!< SEL16 (Bit 16) */
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#define SMU_PATHCHK0_SEL16_Msk (0x10000UL) /*!< SEL16 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_SEL17_Pos (17UL) /*!< SEL17 (Bit 17) */
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#define SMU_PATHCHK0_SEL17_Msk (0x20000UL) /*!< SEL17 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK0_EN_Pos (28UL) /*!< EN (Bit 28) */
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#define SMU_PATHCHK0_EN_Msk (0xf0000000UL) /*!< EN (Bitfield-Mask: 0x0f) */
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/* ======================================================= PATHCHK1 ======================================================== */
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#define SMU_PATHCHK1_SEL0_Pos (0UL) /*!< SEL0 (Bit 0) */
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#define SMU_PATHCHK1_SEL0_Msk (0x1UL) /*!< SEL0 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK1_SEL1_Pos (1UL) /*!< SEL1 (Bit 1) */
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#define SMU_PATHCHK1_SEL1_Msk (0x2UL) /*!< SEL1 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK1_SEL2_Pos (2UL) /*!< SEL2 (Bit 2) */
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#define SMU_PATHCHK1_SEL2_Msk (0x4UL) /*!< SEL2 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK1_SEL3_Pos (3UL) /*!< SEL3 (Bit 3) */
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#define SMU_PATHCHK1_SEL3_Msk (0x8UL) /*!< SEL3 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK1_SEL4_Pos (4UL) /*!< SEL4 (Bit 4) */
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#define SMU_PATHCHK1_SEL4_Msk (0x10UL) /*!< SEL4 (Bitfield-Mask: 0x01) */
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#define SMU_PATHCHK1_EN_Pos (28UL) /*!< EN (Bit 28) */
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#define SMU_PATHCHK1_EN_Msk (0xf0000000UL) /*!< EN (Bitfield-Mask: 0x0f) */
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/* =========================================================================================================================== */
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/* ================ CMU ================ */
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/* =========================================================================================================================== */
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/* ========================================================== CR =========================================================== */
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#define CMU_CR_MONE_Pos (0UL) /*!< MONE (Bit 0) */
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#define CMU_CR_MONE_Msk (0x7UL) /*!< MONE (Bitfield-Mask: 0x07) */
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/* ========================================================= RCCR ========================================================== */
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#define CMU_RCCR_WINLEN_Pos (0UL) /*!< WINLEN (Bit 0) */
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#define CMU_RCCR_WINLEN_Msk (0xffffUL) /*!< WINLEN (Bitfield-Mask: 0xffff) */
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/* ========================================================= HTCR ========================================================== */
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#define CMU_HTCR_HIGHTHR_Pos (0UL) /*!< HIGHTHR (Bit 0) */
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#define CMU_HTCR_HIGHTHR_Msk (0xffffffUL) /*!< HIGHTHR (Bitfield-Mask: 0xffffff) */
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/* ========================================================= LTCR ========================================================== */
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#define CMU_LTCR_LOWTHR_Pos (0UL) /*!< LOWTHR (Bit 0) */
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#define CMU_LTCR_LOWTHR_Msk (0xffffffUL) /*!< LOWTHR (Bitfield-Mask: 0xffffff) */
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/* ========================================================== SR =========================================================== */
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#define CMU_SR_FLL_Pos (0UL) /*!< FLL (Bit 0) */
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#define CMU_SR_FLL_Msk (0x1UL) /*!< FLL (Bitfield-Mask: 0x01) */
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#define CMU_SR_FHH_Pos (1UL) /*!< FHH (Bit 1) */
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#define CMU_SR_FHH_Msk (0x2UL) /*!< FHH (Bitfield-Mask: 0x01) */
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#define CMU_SR_CLKLOSS_Pos (2UL) /*!< CLKLOSS (Bit 2) */
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#define CMU_SR_CLKLOSS_Msk (0x4UL) /*!< CLKLOSS (Bitfield-Mask: 0x01) */
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#define CMU_SR_WORK_Pos (4UL) /*!< WORK (Bit 4) */
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#define CMU_SR_WORK_Msk (0x10UL) /*!< WORK (Bitfield-Mask: 0x01) */
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/* =========================================================================================================================== */
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/* ================ CSE ================ */
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/* =========================================================================================================================== */
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#define CSE_PRAM_RAMn_DATA_32_BYTE_3_MASK (0xFFUL)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_3_SHIFT (0UL)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_3_WIDTH (8UL)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_3_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_3_MASK)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_2_MASK (0xFF00UL)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_2_SHIFT (8UL)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_2_WIDTH (8UL)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_2_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_2_MASK)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_1_MASK (0xFF0000UL)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_1_SHIFT (16UL)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_1_WIDTH (8UL)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_1_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_1_MASK)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_0_MASK (0xFF000000UL)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_0_SHIFT (24UL)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_0_WIDTH (8UL)
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#define CSE_PRAM_RAMn_DATA_32_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_0_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_0_MASK)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_MASK (0xFFUL)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_SHIFT (0UL)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_WIDTH (8UL)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_MASK)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_MASK (0xFFUL)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_SHIFT (0UL)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_WIDTH (8UL)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_MASK)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_MASK (0xFFUL)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_SHIFT (0UL)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_WIDTH (8UL)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_MASK)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_MASK (0xFFUL)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_SHIFT (0UL)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_WIDTH (8UL)
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#define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_MASK)
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/** @} */ /* End of group PosMask_peripherals */
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/**
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* @brief This type shall be used to request the version of a module using the
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* <ModuleName>_DRV_GetVersionInfo() function.
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*/
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typedef struct
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{
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uint16_t moduleID; /**< @brief module ID */
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uint8_t majorVersion; /**< @brief module software major version */
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uint8_t minorVersion; /**< @brief module software minor version */
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uint8_t patchVersion; /**< @brief module software patch version */
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} Drv_VersionInfo_Type;
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#ifdef __cplusplus
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}
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#endif
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#endif /* AC7840X_H */
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/** @} */ /* End of group AC7840x */
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/** @} */ /* End of group AutoChips */
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