/* * Copyright Statement: * * This software/firmware and related documentation ("AutoChips Software") are * protected under relevant copyright laws. The information contained herein is * confidential and proprietary to AutoChips Inc. and/or its licensors. Without * the prior written permission of AutoChips inc. and/or its licensors, any * reproduction, modification, use or disclosure of AutoChips Software, and * information contained herein, in whole or in part, shall be strictly * prohibited. * * AutoChips Inc. (C) 2021. All rights reserved. * * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE") * RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER * ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR * NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, * INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS * SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE * RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE * AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE * CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE. * * @file AC7840x.h * @brief CMSIS HeaderFile * @version 1.0 * @date 02. June 2021 * @note Generated by SVDConv V3.3.27 on Wednesday, 02.06.2021 14:09:31 * from File 'ac7840x.svd', * last modified on Wednesday, 02.06.2021 06:05:59 */ /** @addtogroup AutoChips * @{ */ /** @addtogroup AC7840x * @{ */ #ifndef AC7840X_H #define AC7840X_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup Configuration_of_CMSIS * @{ */ /* PRQA S 3630 EOF */ /* The implementation of the object should be hidden, Maybe use by app. */ /* PRQA S 1535 EOF */ /* A project should not contain unused type declarations, Maybe use by app. */ /* PRQA S 0791 EOF */ /* Macro identifiers shall be distinct */ /* PRQA S 0602 EOF */ /* PRQA S 0603 EOF */ /* =========================================================================================================================== */ /* ================ Interrupt Number Definition ================ */ /* =========================================================================================================================== */ typedef enum { /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ NonMaskableInt_IRQn = -14, /*!< -14 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ /* =========================================== AC7840x Specific Interrupt Numbers ========================================== */ DMA0_CHANNEL0_IRQn = 0, /*!< 0 DMA0 channel 0 interrupt */ DMA0_CHANNEL1_IRQn = 1, /*!< 1 DMA0 channel 1 interrupt */ DMA0_CHANNEL2_IRQn = 2, /*!< 2 DMA0 channel 2 interrupt */ DMA0_CHANNEL3_IRQn = 3, /*!< 3 DMA0 channel 3 interrupt */ DMA0_CHANNEL4_IRQn = 4, /*!< 4 DMA0 channel 4 interrupt */ DMA0_CHANNEL5_IRQn = 5, /*!< 5 DMA0 channel 5 interrupt */ DMA0_CHANNEL6_IRQn = 6, /*!< 6 DMA0 channel 6 interrupt */ DMA0_CHANNEL7_IRQn = 7, /*!< 7 DMA0 channel 7 interrupt */ DMA0_CHANNEL8_IRQn = 8, /*!< 8 DMA0 channel 8 interrupt */ DMA0_CHANNEL9_IRQn = 9, /*!< 9 DMA0 channel 9 interrupt */ DMA0_CHANNEL10_IRQn = 10, /*!< 10 DMA0 channel 10 interrupt */ DMA0_CHANNEL11_IRQn = 11, /*!< 11 DMA0 channel 11 interrupt */ DMA0_CHANNEL12_IRQn = 12, /*!< 12 DMA0 channel 12 interrupt */ DMA0_CHANNEL13_IRQn = 13, /*!< 13 DMA0 channel 13 interrupt */ DMA0_CHANNEL14_IRQn = 14, /*!< 14 DMA0 channel 14 interrupt */ DMA0_CHANNEL15_IRQn = 15, /*!< 15 DMA0 channel 15 interrupt */ PORTA_IRQn = 16, /*!< 16 PORTA interrupt */ PORTB_IRQn = 17, /*!< 17 PORTB interrupt */ PORTC_IRQn = 18, /*!< 18 PORTC interrupt */ PORTD_IRQn = 19, /*!< 19 PORTD interrupt */ PORTE_IRQn = 20, /*!< 20 PORTE interrupt */ UART0_IRQn = 21, /*!< 21 UART0 interrupt */ UART1_IRQn = 22, /*!< 22 UART1 interrupt */ UART2_IRQn = 23, /*!< 23 UART2 interrupt */ UART3_IRQn = 24, /*!< 24 UART3 interrupt */ SPI0_IRQn = 27, /*!< 27 SPI0 interrupt */ SPI1_IRQn = 28, /*!< 28 SPI1 interrupt */ SPI2_IRQn = 29, /*!< 29 SPI2 interrupt */ I2C0_IRQn = 31, /*!< 31 I2C0 interrupt */ EIO_IRQn = 33, /*!< 33 EIO interrupt */ CAN0_IRQn = 34, /*!< 34 CAN0 interrupt */ CAN0_WAKEUP_IRQn = 35, /*!< 35 CAN0 wakeup interrupt */ CAN1_IRQn = 36, /*!< 36 CAN1 interrupt */ CAN1_WAKEUP_IRQn = 37, /*!< 37 CAN1 wakeup interrupt */ CAN2_IRQn = 38, /*!< 38 CAN2 interrupt */ CAN2_WAKEUP_IRQn = 39, /*!< 39 CAN2 wakeup interrupt */ CAN3_IRQn = 40, /*!< 40 CAN3 interrupt */ CAN3_WAKEUP_IRQn = 41, /*!< 41 CAN3 wakeup interrupt */ PDT0_IRQn = 46, /*!< 46 PDT0 interrupt */ PDT1_IRQn = 47, /*!< 47 PDT1 interrupt */ ADC0_IRQn = 48, /*!< 48 ADC0 interrupt */ ADC1_IRQn = 49, /*!< 49 ADC1 interrupt */ ACMP0_IRQn = 50, /*!< 50 ACMP0 interrupt */ WDG_IRQn = 51, /*!< 51 WDG interrupt */ EWDG_IRQn = 52, /*!< 52 EWDG interrupt */ MCM_IRQn = 53, /*!< 53 MCM interrupt */ LVD_IRQn = 54, /*!< 54 LVD interrupt */ SPM_IRQn = 55, /*!< 55 SPM interrupt */ RCM_IRQn = 56, /*!< 56 RCM interrupt */ PWM0_OVERFLOW_IRQn = 57, /*!< 57 PWM0 Overflow interrupt */ PWM0_CHANNEL_IRQn = 58, /*!< 58 PWM0 Channel interrupt */ PWM0_FAULT_IRQn = 59, /*!< 59 PWM0 Fault interrupt */ PWM1_OVERFLOW_IRQn = 60, /*!< 60 PWM1 Overflow interrupt */ PWM1_CHANNEL_IRQn = 61, /*!< 61 PWM1 Channel interrupt */ PWM1_FAULT_IRQn = 62, /*!< 62 PWM1 Fault interrupt */ PWM2_OVERFLOW_IRQn = 63, /*!< 63 PWM2 Overflow interrupt */ PWM2_CHANNEL_IRQn = 64, /*!< 64 PWM2 Channel interrupt */ PWM2_FAULT_IRQn = 65, /*!< 65 PWM2 Fault interrupt */ PWM3_OVERFLOW_IRQn = 66, /*!< 66 PWM3 Overflow interrupt */ PWM3_CHANNEL_IRQn = 67, /*!< 67 PWM3 Channel interrupt */ PWM3_FAULT_IRQn = 68, /*!< 68 PWM3 Fault interrupt */ PWM4_OVERFLOW_IRQn = 69, /*!< 69 PWM4 Overflow interrupt */ PWM4_CHANNEL_IRQn = 70, /*!< 70 PWM4 Channel interrupt */ PWM4_FAULT_IRQn = 71, /*!< 71 PWM4 Fault interrupt */ PWM5_OVERFLOW_IRQn = 72, /*!< 72 PWM5 Overflow interrupt */ PWM5_CHANNEL_IRQn = 73, /*!< 73 PWM5 Channel interrupt */ PWM5_FAULT_IRQn = 74, /*!< 74 PWM5 Fault interrupt */ RTC_IRQn = 81, /*!< 81 RTC interrupt */ PCT_IRQn = 82, /*!< 82 PCT interrupt */ TIMER_CHANNEL0_IRQn = 83, /*!< 83 TIMER channel 0 interrupt */ TIMER_CHANNEL1_IRQn = 84, /*!< 84 TIMER channel 1 interrupt */ TIMER_CHANNEL2_IRQn = 85, /*!< 85 TIMER channel 2 interrupt */ TIMER_CHANNEL3_IRQn = 86, /*!< 86 TIMER channel 3 interrupt */ CSE_IRQn = 87, /*!< 87 CSE interrupt */ FLASH_ECC_IRQn = 88, /*!< 88 FLASH ECC 2-bit interrupt */ FLASH_IRQn = 89, /*!< 89 FLASH command complete interrupt */ FLASH_COLLISION_IRQn = 90, /*!< 90 FLASH collision interrupt */ ECC_1BIT_ERROR_IRQn = 91, /*!< 91 ECC 1bit error interrupt */ ECC_2BIT_ERROR_IRQn = 92, /*!< 92 ECC 2bit error interrupt */ MAX_IRQn = 93 /*!< 93 Max interrupt */ } IRQn_Type; /** * @brief setting bits macro. */ #ifndef SET_BIT32 #define SET_BIT32(reg, mask) ((reg) |= (uint32_t)(mask)) #endif /** * @brief clearing bits macro. */ #ifndef CLEAR_BIT32 #define CLEAR_BIT32(reg, mask) ((reg) &= (~((uint32_t)(mask)))) #endif /** * @brief read bits macro. */ #ifndef READ_BIT32 #define READ_BIT32(reg, mask) ((reg) & ((uint32_t)(mask))) #endif /** * @brief write register macro. */ #ifndef WRITE_REG32 #define WRITE_REG32(reg, value) ((reg) = (uint32_t)(value)) #endif /** * @brief clear bits and set with new value. */ #ifndef MODIFY_REG32 #define MODIFY_REG32(reg, mask, pos, value) (WRITE_REG32((reg), (((reg) & (~((uint32_t)(mask)))) | (((uint32_t)(value)) << (pos))))) #endif /** * @brief read register parameter macro. */ #ifndef READ_PARAM32 #define READ_PARAM32(reg, mask, pos) (((reg) & ((uint32_t)(mask))) >> (pos)) #endif /** * @brief read 32 bits memory macro. */ #ifndef READ_MEM32 #define READ_MEM32(address) (*(volatile uint32_t *)(address)) #endif /** * @brief write 32 bits memory macro. */ #ifndef WRITE_MEM32 #define WRITE_MEM32(address, value) ((*(volatile uint32_t *)(address))= (uint32_t)(value)) #endif /** * @brief clear bits and set with new value for memory. */ #ifndef MODIFY_MEM32 #define MODIFY_MEM32(address, mask, pos, value) (WRITE_MEM32((address), ((READ_MEM32(address) & (~((uint32_t)(mask)))) | (((uint32_t)(value)) << (pos))))) #endif #include #include #include /* PRQA S 1535,2052,4548 ++ */ /* This type maybe use by app. */ /** * @brief global enumeration. */ typedef enum {DISABLE = 0U, ENABLE = !DISABLE} ACTION_Type; typedef enum {ERROR = 0U, SUCCESS = !ERROR} ERROR_Type; /* PRQA S 1535,2052,4548 -- */ /* =========================================================================================================================== */ /* ================ Processor and Core Peripheral Section ================ */ /* =========================================================================================================================== */ /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ #define __MPU_PRESENT 0 /*!< MPU present */ #define __FPU_PRESENT 1 /*!< FPU present */ /** @} */ /* End of group Configuration_of_CMSIS */ #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ #include "device_status.h" /*!< device status */ #include "system_ac7840x.h" /*!< AC7840x System */ #ifndef __IM /*!< Fallback for older CMSIS versions */ #define __IM __I #endif #ifndef __OM /*!< Fallback for older CMSIS versions */ #define __OM __O #endif #ifndef __IOM /*!< Fallback for older CMSIS versions */ #define __IOM __IO #endif /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Section ================ */ /* =========================================================================================================================== */ /* PRQA S 3638 ++ */ /* --------------------------------------------- section using anonymous unions ------------------------------------------- */ #if defined(__CC_ARM) #pragma anon_unions #elif defined(CCARM__) #pragma language=extended #elif defined (__ICCARM__) /* anonymous unions are enabled by default */ #elif (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* anonymous unions are enabled by default */ #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__TMS470__) /* anonymous unions are enabled by default */ #elif defined(__ghs__) /* anonymous unions are enabled by default */ #elif defined(__TASKING__) #pragma warning 586 #else #error Not supported compiler type #endif /* PRQA S 3638 -- */ /** @addtogroup Device_Peripheral_peripherals * @{ */ /* =========================================================================================================================== */ /* ================ MCM ================ */ /* =========================================================================================================================== */ /** * @brief Core Platform Miscellaneous Control Module (MCM) */ typedef struct { /*!< (@ 0xE008000C) MCM Structure */ __IOM uint32_t MCPCR; /*!< (@ 0x00000000) MCM Core Platform Control Register */ __IOM uint32_t MISCR; /*!< (@ 0x00000004) MCM Interrupt Status and Control Register */ __IM uint32_t RESERVED[251]; __IOM uint32_t MLMDR0; /*!< (@ 0x000003F4) MCM Local MCM Local Memory Descriptor Register0 */ __IM uint32_t MBIST; /*!< (@ 0x000003F8) MCM Local Memory BIST Register */ __IOM uint32_t MLMDR1; /*!< (@ 0x000003FC) MCM Local MCM Local Memory Descriptor Register1 */ __IOM uint32_t LMPECR; /*!< (@ 0x00000400) MCM Local Memory Cache ECC Enable Control Register */ __IOM uint32_t LMPEIR; /*!< (@ 0x00000404) MCM Local Memory Cache ECC Error Status Register */ __IM uint32_t LMFAR; /*!< (@ 0x00000408) MCM Local Memory Cache ECC Error Address Register */ __IOM uint32_t MCCR; /*!< (@ 0x0000040C) MCM Cache Control Register */ __IM uint32_t RESERVED1[25]; __IOM uint32_t MNCR; /*!< (@ 0x00000474) MCM NMI Control Register */ } MCM_Type; /*!< Size = 1144 (0x478) */ /* =========================================================================================================================== */ /* ================ MPU ================ */ /* =========================================================================================================================== */ /** * @brief Memory protection unit (MPU) */ /* MPU - Size of Registers Arrays */ #define MPU_EAR_EDR_COUNT (3UL) #define MPU_RGD_COUNT (8UL) #define MPU_RGDAAC_COUNT (8UL) typedef struct { /*!< (@ 0x40006000) MPU Structure */ __IOM uint32_t CESR; /*!< (@ 0x00000000) Control/Error Status Register */ __IOM uint32_t EAR[MPU_EAR_EDR_COUNT]; __IOM uint32_t EDR[MPU_EAR_EDR_COUNT]; __IOM uint32_t MPID; __IOM uint32_t WORD0_RGD[MPU_RGD_COUNT]; __IOM uint32_t WORD1_RGD[MPU_RGD_COUNT]; __IOM uint32_t WORD2_RGD[MPU_RGD_COUNT]; __IOM uint32_t WORD3_RGD[MPU_RGD_COUNT]; __IOM uint32_t RESERVED[216]; __IOM uint32_t RGDAAC[MPU_RGDAAC_COUNT]; /*!< (@ 0x0000008C) Region Descriptor Alternate Access Control n */ } MPU_Type; /*!< Size = 1056 (0x420) */ /* =========================================================================================================================== */ /* ================ CKGEN ================ */ /* =========================================================================================================================== */ /** * @brief Clock Generator (CKGEN) */ typedef struct { /*!< (@ 0x40000000) CKGEN Structure */ __IOM uint32_t CTRL; /*!< (@ 0x00000000) CKGEN Control Register */ __IOM uint32_t LP_CLK_MUX; /*!< (@ 0x00000004) RTC LSI Clock Mux */ __IOM uint32_t PERI_CLK_EN0; /*!< (@ 0x00000008) Periph Clock Enable Control 0 */ __IOM uint32_t PERI_CLK_EN1; /*!< (@ 0x0000000C) Periph Clock Enable Control 1 */ __IOM uint32_t PERI_CLK_EN2; /*!< (@ 0x00000010) Periph Clock Enable Control 2 */ __IOM uint32_t RCM_CTRL; /*!< (@ 0x00000014) MCU Reset Control */ __IOM uint32_t RCM_EN; /*!< (@ 0x00000018) MCU Reset Enable Control */ __IOM uint32_t RCM_STATUS; /*!< (@ 0x0000001C) MCU Reset Status */ __IOM uint32_t PERI_SFT_RST0; /*!< (@ 0x00000020) Periph Software Reset Control 0 */ __IOM uint32_t PERI_SFT_RST1; /*!< (@ 0x00000024) Periph Software Reset Control 1 */ __IOM uint32_t PERI_SFT_RST2; /*!< (@ 0x00000028) Periph Software Reset Control 2 */ __IOM uint32_t CLK_DIV1; /*!< (@ 0x0000002C) Clock Divider 1 */ __IOM uint32_t CLK_DIV2; /*!< (@ 0x00000030) Clock Divider 2 */ __IOM uint32_t PERI_CLK_MUX0; /*!< (@ 0x00000034) Peripheral Clock MUX0 Register */ __IOM uint32_t PERI_CLK_MUX1; /*!< (@ 0x00000038) Peripheral Clock MUX1 Register */ __IOM uint32_t PERI_CLK_MUX2; /*!< (@ 0x0000003C) Peripheral Clock MUX2 Register */ __IOM uint32_t PERI_CLK_MUX3; /*!< (@ 0x00000040) Peripheral Clock MUX3 Register */ __IM uint32_t RESERVED; __IOM uint32_t CLK_OUT_CFG; /*!< (@ 0x00000048) Clock Out Configure */ __IOM uint32_t PERI_CLK_DIV; /*!< (@ 0x0000004C) Peripheral Clock Divider */ } CKGEN_Type; /*!< Size = 80 (0x50) */ /* =========================================================================================================================== */ /* ================ PBR ================ */ /* =========================================================================================================================== */ /** * @brief Peripheral Bridge (PBR) */ typedef struct { /*!< (@ 0x4008A000) PBR Structure */ __IOM uint32_t MPR_CORE; /*!< (@ 0x00000000) Master Core Privilege Configure Register */ __IOM uint32_t MPR_DEBUG; /*!< (@ 0x00000004) Master Debugger Privilege Configure Register */ __IOM uint32_t MPR_DMA; /*!< (@ 0x00000008) Master DMA Privilege Configure Register */ __IM uint32_t RESERVED; __IOM uint32_t PACRA; /*!< (@ 0x00000010) Peripheral Access Control Register A */ __IOM uint32_t PACRB; /*!< (@ 0x00000014) Peripheral Access Control Register B */ __IM uint32_t RESERVED1[2]; __IOM uint32_t PACRC; /*!< (@ 0x00000020) Peripheral Access Control Register C */ __IOM uint32_t PACRD; /*!< (@ 0x00000024) Peripheral Access Control Register D */ __IOM uint32_t PACRE; /*!< (@ 0x00000028) Peripheral Access Control Register E */ __IM uint32_t RESERVED2; __IOM uint32_t PACRF; /*!< (@ 0x00000030) Peripheral Access Control Register F */ __IOM uint32_t PACRG; /*!< (@ 0x00000034) Peripheral Access Control Register G */ } PBR_Type; /*!< Size = 56 (0x38) */ /* =========================================================================================================================== */ /* ================ SPM ================ */ /* =========================================================================================================================== */ /** * @brief System Power Manage (SPM) */ typedef struct { /*!< (@ 0x40008000) SPM Structure */ __IOM uint32_t PWR_MGR_CFG0; /*!< (@ 0x00000000) Power Manage Config Register 0 */ __IOM uint32_t PWR_MGR_CFG1; /*!< (@ 0x00000004) Power Manage Config Register 1 */ __IM uint32_t RESERVED; __IM uint32_t PERIPH_SLEEP_ACK_STATUS; /*!< (@ 0x0000000C) Periph Sleep Ack Status Register */ __IOM uint32_t PERIPH_SLEEP_ACK_EN; /*!< (@ 0x00000010) Periph Sleep Ack Enable Register */ __IOM uint32_t STATUS; /*!< (@ 0x00000014) Status Register */ __IM uint32_t RESERVED2[4]; __IOM uint32_t STB_WP_EN; /*!< (@ 0x00000028) Standby Wakeup Enable Register */ __IOM uint32_t STB_WP_STATUS; /*!< (@ 0x0000002C) Standby Wakeup Status Register */ } SPM_Type; /*!< Size = 48 (0x30) */ /* =========================================================================================================================== */ /* ================ GPIO ================ */ /* =========================================================================================================================== */ /* PRQA S 3630 ++ */ /* May be use by app. */ /** * @brief General Purpose Input/Output (GPIO) */ typedef struct { /*!< (@ 0x40084000) GPIO Structure */ __IOM uint32_t PODR; /*!< (@ 0x00000000) PORT Output Data Register */ __IOM uint32_t PSOR; /*!< (@ 0x00000004) PORT Set Output Register */ __IOM uint32_t PROR; /*!< (@ 0x00000008) PORT Reset Output Register */ __IOM uint32_t PIOR; /*!< (@ 0x0000000C) PORT Invert Output Register */ __IOM uint32_t PIDR; /*!< (@ 0x00000010) PORT Input Data Register */ __IOM uint32_t POER; /*!< (@ 0x00000014) PORT Output Enable Register */ __IOM uint32_t PIER; /*!< (@ 0x00000018) PORT Input Enable Register */ } GPIO_Type; /*!< Size = 28 (0x1c) */ /* =========================================================================================================================== */ /* ================ PORT ================ */ /* =========================================================================================================================== */ #define PORT_PCR_COUNT (32UL) /*!< PORT - size of registers array */ /** * @brief Pin Control and Interrupts (PORT) */ typedef struct { /*!< (@ 0x40084200) PORT Structure */ __IOM uint32_t PCR[PORT_PCR_COUNT]; /*!< (@ 0x00000000~0x0000007C) Pin Control Register n */ __IM uint32_t RESERVED[8]; __IOM uint32_t ISFR; /*!< (@ 0x000000A0) Interrupt Status Flag Register */ __IM uint32_t RESERVED1[7]; __IOM uint32_t DFER; /*!< (@ 0x000000C0) Digital Filter Enable Register */ __IOM uint32_t DFCR; /*!< (@ 0x000000C4) Digital Filter Clock Register */ __IOM uint32_t DFWR; /*!< (@ 0x000000C8) Digital Filter Width Register */ } PORT_Type; /*!< Size = 204 (0xcc) */ /* =========================================================================================================================== */ /* ================ CAN ================ */ /* =========================================================================================================================== */ /** * @brief Controller Area Network (CAN) */ #define CAN_BUF_LENGTH (64 / 4) /*!< CAN buffer length */ /** * @brief CAN receive buffer register define structure */ typedef struct { __IO uint32_t ID_ESI; /*!< [0:28]: Identifier (ID), [30]: Transmit time-stamp enable (TTSEN) */ /*!< [31]: Error state indicator (ESI) */ __IO uint32_t CTRL; /*!< [0:3]: Data length code (DLC), [4]: Bit rate switch (BRS) */ /*!< [5]: FD format indicator (FDF), [6]: Remote transmission request (RTR) */ /*!< [7]: Identifier extension (IDE), [12]: For lookback mode (TX) */ /*!< [13:15]: Kind of error (KOER) */ __IO uint32_t DATA[CAN_BUF_LENGTH]; /*!< Buffer data */ __IM uint32_t TS[2]; /*!< Receive or transmission time stamp */ } CAN_BufType; typedef struct { /*!< (@ 0x40007800) CAN structure */ CAN_BufType RBUF; /*!< (@ 0x00000000) Receive buffer */ CAN_BufType TBUF; /*!< (@ 0x00000050) Transmit buffer */ __IOM uint32_t CTRL0; /*!< (@ 0x000000A0) Config state and transmit/receive control register 0 */ __IOM uint32_t CTRL1; /*!< (@ 0x000000A4) Interrupt enable and flag control register 1 */ __IOM uint32_t SBITRATE; /*!< (@ 0x000000A8) CAN normal bitrate configuration register */ __IOM uint32_t FBITRATE; /*!< (@ 0x000000AC) CAN FD data bitrate configuration register */ __IOM uint32_t ERRINFO; /*!< (@ 0x000000B0) Error type and error counter register */ __IOM uint32_t ACFCTRL0; /*!< (@ 0x000000B4) Acceptance filter control register 0 */ __IOM uint32_t ACFCTRL1; /*!< (@ 0x000000B8) Acceptance filter control register 1 */ __IOM uint32_t ACFCTRL2; /*!< (@ 0x000000BC) Acceptance filter control register 2 */ __IOM uint32_t ACF; /*!< (@ 0x000000C0) Acceptance code register */ __IOM uint32_t VERMEM; /*!< (@ 0x000000C4) Version and memory protection register */ __IOM uint32_t MEMES; /*!< (@ 0x000000C8) Memory error simulation register */ __IOM uint32_t WAKEUP; /*!< (@ 0x000000CC) Wakeup configuration register */ } CAN_Type; /*!< Size = 208 (0xd0) */ /* =========================================================================================================================== */ /* ================ UART ================ */ /* =========================================================================================================================== */ /** * @brief Universal Asynchronous Receiver/Transmitter (UART) */ typedef struct { /*!< (@ 0x40018000) UART Structure */ __IOM uint32_t RBR; /*!< (@ 0x00000000) RX/TX Data Register */ __IOM uint32_t DIV_L; /*!< (@ 0x00000004) Divisor low 8 bits register */ __IOM uint32_t DIV_H; /*!< (@ 0x00000008) Divisor high 8 bits register */ __IOM uint32_t LCR0; /*!< (@ 0x0000000C) UART control register 0 */ __IOM uint32_t LCR1; /*!< (@ 0x00000010) UART control register 1 */ __IOM uint32_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ __IOM uint32_t EFR; /*!< (@ 0x00000018) hardware flow control register */ __IOM uint32_t IER; /*!< (@ 0x0000001C) Interrupt Enable register */ __IOM uint32_t LSR0; /*!< (@ 0x00000020) Line Status Register 0 */ __IOM uint32_t LSR1; /*!< (@ 0x00000024) Line Status Register 1 */ __IOM uint32_t SMP_CNT; /*!< (@ 0x00000028) UART sample counter register */ __IOM uint32_t ADDR; /*!< (@ 0x0000002C) UART match address register */ __IOM uint32_t DATA; /*!< (@ 0x00000030) UART match data register */ __IOM uint32_t GUARD; /*!< (@ 0x00000034) UART guard time register */ __IM uint32_t RESERVED; __IOM uint32_t SLEEP_EN; /*!< (@ 0x0000003C) UART sleep enable register */ __IOM uint32_t DMA_EN; /*!< (@ 0x00000040) UART DMA enable register */ __IOM uint32_t DIV_FRAC; /*!< (@ 0x00000044) Uart Fractional Divider Address */ __IOM uint32_t MTCHCR; /*!< (@ 0x00000048) Uart match fucntion enable */ __IOM uint32_t RS485CR; /*!< (@ 0x0000004C) Uart RS485 control register */ __IM uint32_t RESERVED1; __IOM uint32_t CNTR; /*!< (@ 0x00000054) Uart Counter time delay in RS485 mode */ __IOM uint32_t IDLE; /*!< (@ 0x00000058) Uart IDLE register */ __IOM uint32_t LINCR; /*!< (@ 0x0000005C) LIN Control register */ __IOM uint32_t BRKLGH; /*!< (@ 0x00000060) LIN Break Length Select Register */ __IOM uint32_t PMIN0; /*!< (@ 0x00000064) IrDA mode pulse minimum pulse */ __IOM uint32_t PMIN1; /*!< (@ 0x00000068) IrDA mode pulse minimum pulse */ } UART_Type; /*!< Size = 108 (0x6c) */ /* =========================================================================================================================== */ /* ================ I2C ================ */ /* =========================================================================================================================== */ /** * @brief Inter-Integrated Circuit (I2C) */ typedef struct { /*!< (@ 0x4000E000) I2C Structure */ __IOM uint32_t ADDR0; /*!< (@ 0x00000000) Address Register 0 */ __IOM uint32_t ADDR1; /*!< (@ 0x00000004) Address register 1 */ __IOM uint32_t SAMPLE_CNT; /*!< (@ 0x00000008) SAMPLE CNT Register */ __IOM uint32_t STEP_CNT; /*!< (@ 0x0000000C) STEP CNT Register */ __IOM uint32_t CTRL0; /*!< (@ 0x00000010) Control Register 0 */ __IOM uint32_t CTRL1; /*!< (@ 0x00000014) Control Register 1 */ __IOM uint32_t CTRL2; /*!< (@ 0x00000018) Control Register 2 */ __IOM uint32_t CTRL3; /*!< (@ 0x0000001C) Control Register 3 */ __IOM uint32_t STATUS0; /*!< (@ 0x00000020) Status Register 0 */ __IOM uint32_t STATUS1; /*!< (@ 0x00000024) Status Register 1 */ __IOM uint32_t DGLCFG; /*!< (@ 0x00000028) Deglitch Configuration Register */ __IOM uint32_t DATA; /*!< (@ 0x0000002C) Data Register */ __IOM uint32_t STARTSTOP; /*!< (@ 0x00000030) START_STOP Register */ } I2C_Type; /*!< Size = 52 (0x34) */ /* =========================================================================================================================== */ /* ================ SPI ================ */ /* =========================================================================================================================== */ /** * @brief Serial Peripheral Interface (SPI) */ typedef struct { /*!< (@ 0x4000C000) SPI Structure */ __IOM uint32_t CFG0; /*!< (@ 0x00000000) SPI Configuration Register 0 */ __IOM uint32_t CFG1; /*!< (@ 0x00000004) SPI Configuration Register 1 */ __IOM uint32_t CMD; /*!< (@ 0x00000008) SPI Command Register */ __IOM uint32_t STATUS; /*!< (@ 0x0000000C) SPI Status Register */ __IOM uint32_t DATA; /*!< (@ 0x00000010) SPI Data Register */ __IOM uint32_t CFG2; /*!< (@ 0x00000014) SPI configuration register 2 */ __IM uint32_t RESERVED[2]; __IOM uint32_t DMV; /*!< (@ 0x00000020) SPI data match register */ } SPI_Type; /*!< Size = 36 (0x24) */ /* =========================================================================================================================== */ /* ================ ANA ================ */ /* =========================================================================================================================== */ /** * @brief Analog Control Registers (ANA) */ typedef struct { /*!< (@ 0x40008800) ANA Structure */ __IM uint32_t RESERVED[20]; __IOM uint32_t ACMPDAC_CFG; /*!< (@ 0x00000050) ACMPDAC Configuration Register */ __IM uint32_t RESERVED1[3]; __IOM uint32_t AUXADC_CFG0; /*!< (@ 0x00000060) AUXADC Configuration Register0 */ __IOM uint32_t AUXADC_CFG1; /*!< (@ 0x00000064) AUXADC Configuration Register1 */ __IM uint32_t RESERVED2[2]; __IOM uint32_t AUXADC_CFG4; /*!< (@ 0x00000070) AUXADC Configuration Register4 */ __IOM uint32_t AUXADC_CFG5; /*!< (@ 0x00000074) AUXADC Configuration Register5 */ __IM uint32_t RESERVED3[18]; __IOM uint32_t SPLL_CFG0; /*!< (@ 0x000000C0) System PLL Config 0 */ __IOM uint32_t SPLL_CFG1; /*!< (@ 0x000000C4) System PLL Config 1 */ } ANA_Type; /*!< Size = 200 (0xc8) */ /* =========================================================================================================================== */ /* ================ ADC ================ */ /* =========================================================================================================================== */ #define ADC_REGULAR_SEQ_NUM (24U) #define ADC_INJECT_SEQ_NUM (4U) #define ADC_SAMPLE_REG_NUM (4U) /** * @brief Analog to Digital Converter (ADC) */ typedef struct { /*!< (@ 0x40003000) ADC Structure */ __IOM uint32_t STR; /*!< (@ 0x00000000) ADC status Register */ __IOM uint32_t CTRL0; /*!< (@ 0x00000004) ADC Control Register 0 */ __IOM uint32_t CTRL1; /*!< (@ 0x00000008) ADC Control Register 1 */ __IOM uint32_t IOFR[ADC_INJECT_SEQ_NUM]; /*!< (@ 0x0000000C) ADC Injection Group Offset Register */ __IOM uint32_t AMOHR; /*!< (@ 0x0000001C) AMO High threshold and offset register */ __IOM uint32_t AMOLR; /*!< (@ 0x00000020) AMO Low threshold and offset register */ __IOM uint32_t SPT[ADC_SAMPLE_REG_NUM]; /*!< (@ 0x00000024) ADC Sample time setting register(n) */ __IOM uint32_t RSQR[ADC_REGULAR_SEQ_NUM]; /*!< (@ 0x00000034) ADC regular group sequence configure register(n) */ __IM uint32_t RESERVED1[8]; __IOM uint32_t ISQR[ADC_INJECT_SEQ_NUM]; /*!< (@ 0x000000B4) ADC injected group sequence configure register(n) */ __IOM uint32_t SQL; /*!< (@ 0x000000C4) Sequence length of group configure register */ __IOM uint32_t CALI0; /*!< (@ 0x000000C8) ADC Calibration Register 0 */ __IOM uint32_t CALI1; /*!< (@ 0x000000CC) ADC Calibration Register 1 */ __IM uint32_t RESERVED2[6]; __IM uint32_t RDR[ADC_REGULAR_SEQ_NUM]; /*!< (@ 0x000000E8) ADC Regular Group data Register(n) */ __IM uint32_t RESERVED3[8]; __IM uint32_t IDR[ADC_INJECT_SEQ_NUM]; /*!< (@ 0x00000168) ADC Injected Group data Register(n) */ } ADC_Type; /*!< Size = 376 (0x178) */ /* =========================================================================================================================== */ /* ================ ACMP ================ */ /* =========================================================================================================================== */ /** * @brief Analog comparator (ACMP) */ typedef struct { /*!< (@ 0x40005000) ACMP Structure */ __IOM uint32_t CR0; /*!< (@ 0x00000000) ACMP Configuration Register 0 */ __IOM uint32_t CR1; /*!< (@ 0x00000004) ACMP Configuration Register 1 */ __IOM uint32_t CR2; /*!< (@ 0x00000008) ACMP configuration register 2 */ __IOM uint32_t CR3; /*!< (@ 0x0000000C) ACMP configuration register 3 */ __IOM uint32_t CR4; /*!< (@ 0x00000010) ACMP configuration register 4 */ __IM uint32_t DR; /*!< (@ 0x00000014) ACMP data output register 0 */ __IOM uint32_t SR; /*!< (@ 0x00000018) ACMP status register 0 */ __IOM uint32_t FD; /*!< (@ 0x0000001C) ACMP polling frequency divider register */ __IOM uint32_t OPA; /*!< (@ 0x00000020) ACMP hall output A set register */ __IOM uint32_t OPB; /*!< (@ 0x00000024) ACMP hall output B set register */ __IOM uint32_t OPC; /*!< (@ 0x00000028) ACMP hall output C set register */ __IM uint32_t RESERVED[7]; __IOM uint32_t CLK; /*!< (@ 0x00000048) ACMP clock register */ } ACMP_Type; /*!< Size = 76 (0x4c) */ /* =========================================================================================================================== */ /* ================ PWM ================ */ /* =========================================================================================================================== */ /** * @brief Pulse Width Modulation (PWM) */ #define PWM_CHANNEL_MAX (8UL) /*!< Number of channel of the PWM module */ typedef struct { /*!< (@ 0x40080000) PWM Structure */ __IOM uint32_t INIT; /*!< (@ 0x00000000) PWM Initialize, Include Clock and Prescale Setting */ __IOM uint32_t CNT; /*!< (@ 0x00000004) PWM Counter Value */ __IOM uint32_t MCVR; /*!< (@ 0x00000008) PWM Counter Max Count Value Register */ struct { __IOM uint32_t CHnSCR; /*!< (@ 0x0000000C + 0x8 * n) Channel (n) Status And Control Register */ __IOM uint32_t CHnV; /*!< (@ 0x00000010 + 0x8 * n) Channel (n) Value */ } CHANNELS[PWM_CHANNEL_MAX]; __IOM uint32_t CNTIN; /*!< (@ 0x0000004C) Counter Initial Value */ __IOM uint32_t STR; /*!< (@ 0x00000050) Status Register */ __IOM uint32_t FUNCSEL; /*!< (@ 0x00000054) PWM Features(Functions) Mode Selection Register */ __IOM uint32_t SYNC; /*!< (@ 0x00000058) Synchronization */ __IOM uint32_t OUTINIT; /*!< (@ 0x0000005C) Initial State For Channels Output */ __IOM uint32_t OMCR; /*!< (@ 0x00000060) Output Mask Control Register */ __IOM uint32_t MODESEL; /*!< (@ 0x00000064) PWM Function Mode Selection */ __IOM uint32_t DTSET0; /*!< (@ 0x00000068) Deadtime Insertion Control 0 */ __IOM uint32_t DTSET1; /*!< (@ 0x0000006C) Deadtime Insertion Control 1 */ __IOM uint32_t EXTTRIG; /*!< (@ 0x00000070) PWM External Trigger */ __IOM uint32_t CHOPOLCR; /*!< (@ 0x00000074) Channel Output Polarity Register */ __IOM uint32_t FDSR; /*!< (@ 0x00000078) Fault Detect Status Register */ __IOM uint32_t CAPFILTER; /*!< (@ 0x0000007C) Input Capture Filter Control */ __IOM uint32_t FFAFER; /*!< (@ 0x00000080) Fault Filter and Fault Enable Register */ __IOM uint32_t QDI; /*!< (@ 0x00000084) Quadrature Decoder Interface Configuration Register */ __IOM uint32_t CONF; /*!< (@ 0x00000088) Configuration */ __IOM uint32_t FLTPOL; /*!< (@ 0x0000008C) PWM Fault Input Polarity */ __IOM uint32_t SYNCONF; /*!< (@ 0x00000090) Synchronization Configuration */ __IOM uint32_t INVCR; /*!< (@ 0x00000094) PWM Inverse Control Register */ __IOM uint32_t CHOSWCR; /*!< (@ 0x00000098) PWM CHannel Software Output Control Register */ __IOM uint32_t DITHER0; /*!< (@ 0x0000009C) Dither function register 0 */ __IOM uint32_t DITHER1; /*!< (@ 0x000000A0) Dither function register 1 */ __IOM uint32_t DITHER2; /*!< (@ 0x000000A4) Dither function register 2 */ __IOM uint32_t DMACTRL; /*!< (@ 0x000000A8) DMA Control Register */ } PWM_Type; /*!< Size = 172 (0xac) */ /* =========================================================================================================================== */ /* ================ PDT ================ */ /* =========================================================================================================================== */ /** * @brief Programmable Delay Timer (PDT) */ #define PDT_DLY_MAX (8UL) /*!< Number of channel of PDT DLY */ typedef struct { /*!< (@ 0x40086000) PDT Structure */ __IOM uint32_t SC; /*!< (@ 0x00000000) PDT Config Register1 */ __IOM uint32_t MOD; /*!< (@ 0x00000004) PDT Config Register2 */ struct { __IOM uint32_t DLY; /*!< (@ 0x00000008 ~ 0x00000024) PDT Config Register3 ~ 10 */ } DLY[PDT_DLY_MAX]; __IOM uint32_t IDLY; /*!< (@ 0x00000028) PDT Config Register11 */ union { __IOM uint32_t PODLY; /*!< (@ 0x0000002C) PDT Config Register12 */ struct { __IOM uint16_t DLY1; __IOM uint16_t DLY2; }ACCESS16BIT; }PULSE; __IOM uint32_t DLYn_EN; /*!< (@ 0x00000030) Delay Enable Register */ __IOM uint32_t POEN; /*!< (@ 0x00000034) Pulse-Out Enable register */ __IOM uint32_t CNT; /*!< (@ 0x00000038) Counter register */ } PDT_Type; /*!< Size = 60 (0x3c) */ /* =========================================================================================================================== */ /* ================ TIMER_CTRL ================ */ /* =========================================================================================================================== */ /** * @brief Timer Control (TIMER_CTRL) */ typedef struct { /*!< (@ 0x40011000) TIMER_CTRL Structure */ __IOM uint32_t CR; /*!< (@ 0x00000000) Timer Control Regitser */ __IOM uint32_t SR; /*!< (@ 0x00000004) Timer Status Regitser */ __IOM uint32_t IER; /*!< (@ 0x00000008) TIMER Interrupt Enable Register */ __IOM uint32_t ENR; /*!< (@ 0x0000000C) TIMER Enable Register */ } TIMER_CTRL_Type; /*!< Size = 16 (0x10) */ /* =========================================================================================================================== */ /* ================ TIMER_CHANNEL ================ */ /* =========================================================================================================================== */ /** * @brief Timer channel (TIMER_CHANNEL) */ typedef struct { /*!< (@ 0x40011010) TIMER_CHANNEL Structure */ __IOM uint32_t TVAL; /*!< (@ 0x00000000) Timer Load Value Register */ __IOM uint32_t CVAL; /*!< (@ 0x00000004) Timer Current Count Value Register */ __IOM uint32_t CTRL; /*!< (@ 0x00000008) Timer channel Control Register */ } TIMER_CHANNEL_Type; /*!< Size = 12 (0xc) */ /* =========================================================================================================================== */ /* ================ PCT ================ */ /* =========================================================================================================================== */ /** * @brief Pulse Count Timer (PCT) */ typedef struct { /*!< (@ 0x40019000) PCT Structure */ __IOM uint32_t CSR; /*!< (@ 0x00000000) PCT Control Status Register */ __IOM uint32_t PSR; /*!< (@ 0x00000004) PCT prescaler Register */ __IOM uint32_t CMR; /*!< (@ 0x00000008) PCT Compare Register */ __IOM uint32_t CNR; /*!< (@ 0x0000000C) PCT Counter Register */ } PCT_Type; /*!< Size = 16 (0x10) */ /* =========================================================================================================================== */ /* ================ CTU ================ */ /* =========================================================================================================================== */ /** * @brief Connect Unit Module (CTU) */ #define TRGMUX_MODULE_NUM (23UL) typedef struct { /*!< (@ 0x40006000) CTU Structure */ union { struct { __IOM uint32_t TRGMUX_DMA; /*!< (@ 0x00000000) TRGMUX Config Register1 */ __IOM uint32_t TRGMUX_EXTOUT0; /*!< (@ 0x00000004) TRGMUX Config Register2 */ __IOM uint32_t TRGMUX_EXTOUT1; /*!< (@ 0x00000008) TRGMUX Config Register3 */ __IOM uint32_t TRGMUX_ADC0_REG; /*!< (@ 0x0000000C) TRGMUX Config Register4 */ __IOM uint32_t TRGMUX_ADC0_INJ; /*!< (@ 0x00000010) TRGMUX Config Register5 */ __IOM uint32_t TRGMUX_ADC1_REG; /*!< (@ 0x00000014) TRGMUX Config Register6 */ __IOM uint32_t TRGMUX_ADC1_INJ; /*!< (@ 0x00000018) TRGMUX Config Register7 */ __IOM uint32_t TRGMUX_ACMP; /*!< (@ 0x0000001C) TRGMUX Config Register8 */ __IOM uint32_t TRGMUX_PWM0; /*!< (@ 0x00000020) TRGMUX Config Register9 */ __IOM uint32_t TRGMUX_PWM1; /*!< (@ 0x00000024) TRGMUX Config Register10 */ __IOM uint32_t TRGMUX_PWM2; /*!< (@ 0x00000028) TRGMUX Config Register11 */ __IOM uint32_t TRGMUX_PWM3; /*!< (@ 0x0000002C) TRGMUX Config Register12 */ __IOM uint32_t TRGMUX_PWM4; /*!< (@ 0x00000030) TRGMUX Config Register13 */ __IOM uint32_t TRGMUX_PWM5; /*!< (@ 0x00000034) TRGMUX Config Register14 */ __IM uint32_t RESERVED[2]; __IOM uint32_t TRGMUX_TIMER; /*!< (@ 0x00000040) TRGMUX Config Register15 */ __IOM uint32_t TRGMUX_PCT; /*!< (@ 0x00000044) TRGMUX Config Register16 */ __IOM uint32_t TRGMUX_UART0; /*!< (@ 0x00000048) TRGMUX Config Register17 */ __IOM uint32_t TRGMUX_UART1; /*!< (@ 0x0000004C) TRGMUX Config Register18 */ __IOM uint32_t TRGMUX_PDT0; /*!< (@ 0x00000050) TRGMUX Config Register19 */ __IOM uint32_t TRGMUX_PDT1; /*!< (@ 0x00000054) TRGMUX Config Register20 */ __IOM uint32_t TRGMUX_EIO; /*!< (@ 0x00000058) TRGMUX Config Register21 */ } TRGMUX_MODULE; __IOM uint32_t TRGMUXn[TRGMUX_MODULE_NUM]; } TRGMUX; __IOM uint32_t CTU_CFG; /*!< (@ 0x0000005C) CTU Config Register */ __IOM uint32_t CTU_SW; /*!< (@ 0x00000060) CTU Config2 Register */ __IOM uint32_t PWM_MODULATION; /*!< (@ 0x00000064) CTU Config3 Register */ __IOM uint32_t ADC_SYNC; /*!< (@ 0x00000068) CTU ADC Interleave and Simultaneous Mode Register */ } CTU_Type; /*!< Size = 108 (0x6c) */ /* =========================================================================================================================== */ /* ================ DMA0_TOP_RST ================ */ /* =========================================================================================================================== */ /** * @brief DMA0 All Channnels Share The Registers (DMA0_TOP_RST) */ typedef struct { /*!< (@ 0x40012000) DMA0_TOP_RST Structure */ __IOM uint32_t TOP_RST; /*!< (@ 0x00000000) TOP_RST Register */ } DMA_TopRstType; /*!< Size = 4 (0x4) */ /* =========================================================================================================================== */ /* ================ DMA0_Channel ================ */ /* =========================================================================================================================== */ /** * @brief DMA channel (DMA0_Channel) */ typedef struct { /*!< (@ 0x40012040) DMA0_Channel Structure */ __IOM uint32_t STATUS; /*!< (@ 0x00000000) Status Register */ __IOM uint32_t INTEN; /*!< (@ 0x00000004) Interrupt Enable Register */ __IOM uint32_t RST; /*!< (@ 0x00000008) Reset Register */ __IOM uint32_t STOP; /*!< (@ 0x0000000C) Stop Register */ __IOM uint32_t CONFIG; /*!< (@ 0x00000010) DMA Config Register */ __IOM uint32_t CHAN_LENGTH; /*!< (@ 0x00000014) Channel Length Register */ __IOM uint32_t SSTART_ADDR; /*!< (@ 0x00000018) Source Start Address Register */ __IOM uint32_t SEND_ADDR; /*!< (@ 0x0000001C) Source End Address Register */ __IOM uint32_t DSTART_ADDR; /*!< (@ 0x00000020) Destination Start Address Register */ __IOM uint32_t CHAN_ENABLE; /*!< (@ 0x00000024) Channel Enable Register */ __IOM uint32_t DATA_TRANS_NUM; /*!< (@ 0x00000028) Data Transfer Number Register */ __IOM uint32_t FIFO_LEFT_NUM; /*!< (@ 0x0000002C) Internal FIFO Data Left Number Register */ __IOM uint32_t DEND_ADDR; /*!< (@ 0x00000030) Destination End Address Register */ __IOM uint32_t ADDR_OFFSET; /*!< (@ 0x00000034) Address Offset Register */ __IOM uint32_t DMAMUX_CFG; /*!< (@ 0x00000038) DMAMUX Configuration Register */ } DMA_ChannelType; /*!< Size = 60 (0x3c) */ /* =========================================================================================================================== */ /* ================ WDG ================ */ /* =========================================================================================================================== */ /** * @brief Watchdog (WDG) */ typedef struct { /*!< (@ 0x4000B000) WDG Structure */ __IOM uint32_t CS0; /*!< (@ 0x00000000) Watchdog Control and Status Register 0 */ __IOM uint32_t CS1; /*!< (@ 0x00000004) Watchdog Control and Status Register 1 */ __IOM uint32_t CNT; /*!< (@ 0x00000008) Watchdog Counter Value */ __IOM uint32_t TOVAL; /*!< (@ 0x0000000C) Watchdog Timeout Value Register */ __IOM uint32_t WIN; /*!< (@ 0x00000010) Watchdog Window Register */ } WDG_Type; /*!< Size = 20 (0x14) */ /* =========================================================================================================================== */ /* ================ RTC ================ */ /* =========================================================================================================================== */ /** * @brief Real-time counter (RTC) */ typedef struct { /*!< (@ 0x40009800) RTC Structure */ __IOM uint32_t CTRL; /*!< (@ 0x00000000) RTC Control Register */ __IOM uint32_t TAR; /*!< (@ 0x00000004) RTC Time Alarm Register */ __IOM uint32_t TC; /*!< (@ 0x00000008) RTC Time Counter */ __IOM uint32_t PSR; /*!< (@ 0x0000000C) RTC Prescaler Register */ __IM uint32_t PSC; /*!< (@ 0x00000010) RTC Prescaler Counter Register */ __IOM uint32_t SR; /*!< (@ 0x00000014) RTC Status Register */ __IOM uint32_t LR; /*!< (@ 0x00000018) RTC Lock Register */ } RTC_Type; /*!< Size = 28 (0x1c) */ /* =========================================================================================================================== */ /* ================ CRC ================ */ /* =========================================================================================================================== */ /** * @brief CRC Cyclic redundancy check (CRC) */ typedef struct { /*!< (@ 0x40084000) CRC Structure */ union { __IOM uint32_t DATA32; /*!< (@ 0x00000000) DATA Register */ struct { __IOM uint16_t L; /*!< (@ 0x00000000) DATA L Register */ __IOM uint16_t H; /*!< (@ 0x00000002) DATA H Register */ } DATA16; struct { __IOM uint8_t LL; /*!< (@ 0x00000000) DATA LL Register */ __IOM uint8_t LU; /*!< (@ 0x00000001) DATA LU Register */ __IOM uint8_t HL; /*!< (@ 0x00000002) DATA HL Register */ __IOM uint8_t HU; /*!< (@ 0x00000003) DATA HU Register */ } DATA8; } DATAn; __IOM uint32_t POLY; /*!< (@ 0x00000004) Poly Register */ __IOM uint32_t CTRL; /*!< (@ 0x00000008) Control Register */ } CRC_Type; /*!< Size = 12 (0xc) */ /* =========================================================================================================================== */ /* ================ EIM_CTRL ================ */ /* =========================================================================================================================== */ /** * @brief GLB_EN (EIM_CTRL) */ typedef struct { /*!< (@ 0x40088000) EIM_CTRL Structure */ __IOM uint32_t EIM_GLB_ENABLE; /*!< (@ 0x00000000) EIM global enable */ __IOM uint32_t EIM_CHEN; /*!< (@ 0x00000004) EIM channel enable control */ } EIM_CTRL_Type; /*!< Size = 8 (0x8) */ /* =========================================================================================================================== */ /* ================ EIM_CHANNEL ================ */ /* =========================================================================================================================== */ /** * @brief SRAM Error Injection Bit Control (EIM_CHANNEL) */ typedef struct { /*!< (@ 0x40088010) EIM_CHANNEL Structure */ __IOM uint32_t EIM_INJ_DATA; /*!< (@ 0x00000000) SRAML data injection control */ __IOM uint32_t EIM_INJ_ADDR; /*!< (@ 0x00000004) SRAML address injection control */ __IOM uint32_t EIM_INJ_ECC; /*!< (@ 0x00000008) SRAML ECC code injection control */ } EIM_CHANNEL_Type; /*!< Size = 12 (0xc) */ /* =========================================================================================================================== */ /* ================ ECC_SRAM ================ */ /* =========================================================================================================================== */ /** * @brief SRAM Error ctrl (ECC_SRAM) */ typedef struct { /*!< (@ 0x40088100) ECC_SRAM Structure */ __IM uint32_t CH0_STATUS0; /*!< (@ 0x00000000) SRAM ECC CH0 status and addr0 register */ __IM uint32_t CH0_STATUS1; /*!< (@ 0x00000004) ECC CH0 2bit error addr */ __IM uint32_t CH1_STATUS0; /*!< (@ 0x00000008) SRAM ECC CH1 status and addr0 register */ __IM uint32_t CH1_STATUS1; /*!< (@ 0x0000000C) ECC CH1 2bit error addr */ __IOM uint32_t ECC_ERR_CTRL; /*!< (@ 0x00000010) ECC Error status control registers */ } ECC_SRAM_Type; /*!< Size = 20 (0x14) */ /* =========================================================================================================================== */ /* ================ FLASH ================ */ /* =========================================================================================================================== */ /** * @brief Embedded Flash (FLASH) */ typedef struct { /*!< (@ 0x40002000) FLASH Structure */ __IOM uint32_t STAT; /*!< (@ 0x00000000) Flash status register */ __IM uint32_t SEC; /*!< (@ 0x00000004) MCU secure register */ __IOM uint32_t CSESTAT; /*!< (@ 0x00000008) CSE status register */ __IOM uint32_t KEYUNLK; /*!< (@ 0x0000000C) Flash unlock register */ __IOM uint32_t CNFG; /*!< (@ 0x00000010) Flash configure register */ __IOM uint32_t CMD; /*!< (@ 0x00000014) Flash command ID register */ __IOM uint32_t ADDR; /*!< (@ 0x00000018) Flash address register */ __IOM uint32_t DATA0; /*!< (@ 0x0000001C) Flash data register 0 */ __IOM uint32_t DATA1; /*!< (@ 0x00000020) Flash data register 1 */ __IOM uint32_t LEN; /*!< (@ 0x00000024) Flash length register */ __IM uint32_t RESERVED[2]; __IOM uint32_t CST; /*!< (@ 0x00000030) Flash command start register */ __IOM uint32_t PPROT; /*!< (@ 0x00000034) P-Flash write protection register */ __IOM uint32_t DPROT; /*!< (@ 0x00000038) D-Flash write protection register */ __IM uint32_t RESERVED1; __IOM uint32_t DFADR; /*!< (@ 0x00000040) Flash ECC 2-bit error address register */ __IM uint32_t RESERVED2; __IM uint32_t PART; /*!< (@ 0x00000048) CSE partition information register */ } FLASH_Type; /*!< Size = 76 (0x4c) */ /* =========================================================================================================================== */ /* ================ CSE ================ */ /* =========================================================================================================================== */ #define CSE_PRAM_RAMn_COUNT (32UL) /*!< Size of PRMA Registers Arrays */ #define CSE_PRAM_INSTANCE_COUNT (1UL) /*!< Number of instances of the CSE_PRAM module */ /** * @brief CSE */ typedef struct { union { /*!< offset: 0x0, array step: 0x4 */ __IO uint32_t DATA_32; /*!< CSE PRAM 0 Register..CSE PRAM 31 Register, array offset: 0x0, array step: 0x4 */ struct { /*!< offset: 0x0, array step: 0x4 */ __IO uint8_t DATA_8LL; /*!< CSE PRAM0LL register...CSE PRAM31LL register., array offset: 0x0, array step: 0x4 */ __IO uint8_t DATA_8LU; /*!< CSE PRAM0LU register...CSE PRAM31LU register., array offset: 0x1, array step: 0x4 */ __IO uint8_t DATA_8HL; /*!< CSE PRAM0HL register...CSE PRAM31HL register., array offset: 0x2, array step: 0x4 */ __IO uint8_t DATA_8HU; /*!< CSE PRAM0HU register...CSE PRAM31HU register., array offset: 0x3, array step: 0x4 */ } ACCESS8BIT; } RAMn[CSE_PRAM_RAMn_COUNT]; } CSE_PRAM_Type, *CSE_PRAM_MemMapPtr; /* =========================================================================================================================== */ /* ================ EIO ================ */ /* =========================================================================================================================== */ /** * @brief The EIO Memory Map/Register Definition can be found here. (EIO) */ typedef struct { /*!< (@ 0x4000A000) EIO Structure */ __IOM uint32_t CTRL; /*!< (@ 0x00000000) EIO Control Register */ __IM uint32_t PIN; /*!< (@ 0x00000004) Pin State Register */ __IOM uint32_t SHIFTSTAT; /*!< (@ 0x00000008) Shifter Status Register */ __IOM uint32_t SHIFTERR; /*!< (@ 0x0000000C) Shifter Error Register */ __IOM uint32_t TIMSTAT; /*!< (@ 0x00000010) Timer Status Register */ __IOM uint32_t SHIFTSIEN; /*!< (@ 0x00000014) Shifter Status Interrupt Enable */ __IOM uint32_t SHIFTEIEN; /*!< (@ 0x00000018) Shifter Error Interrupt Enable */ __IOM uint32_t TIMIEN; /*!< (@ 0x0000001C) Timer Interrupt Enable Register */ __IOM uint32_t SHIFTSDEN; /*!< (@ 0x00000020) Shifter Status DMA Enable */ __IM uint32_t RESERVED[3]; __IOM uint32_t SHIFTCTL[4]; /*!< (@ 0x00000030) Shifter Control N Register */ __IOM uint32_t SHIFTCFG[4]; /*!< (@ 0x00000040) Shifter Configuration N Register */ __IOM uint32_t SHIFTBUF[4]; /*!< (@ 0x00000050) Shifter Buffer N Register */ __IOM uint32_t SHIFTBUFBIS[4]; /*!< (@ 0x00000060) Shifter Buffer N Bit Swapped Register */ __IOM uint32_t SHIFTBUFBYS[4]; /*!< (@ 0x00000070) Shifter Buffer N Byte Swapped Register */ __IOM uint32_t SHIFTBUFBBS[4]; /*!< (@ 0x00000080) Shifter Buffer N Bit Byte Swapped Register */ __IOM uint32_t TIMCTL[4]; /*!< (@ 0x00000090) Timer Control N Register */ __IOM uint32_t TIMCFG[4]; /*!< (@ 0x000000A0) Timer Configuration N Register */ __IOM uint32_t TIMCMP[4]; /*!< (@ 0x000000B0) Timer Compare N Register */ } EIO_Type; /*!< Size = 192 (0xc0) */ /* =========================================================================================================================== */ /* ================ EWDG ================ */ /* =========================================================================================================================== */ /** * @brief External Watchdog Timer (EWDG) */ typedef struct { /*!< (@ 0x4000B400) EWDG Structure */ __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control Register */ __IOM uint32_t SERV; /*!< (@ 0x00000004) Service Register */ __IOM uint32_t CMPL; /*!< (@ 0x00000008) Compare Low Register */ __IOM uint32_t CMPH; /*!< (@ 0x0000000C) Compare High Register */ __IOM uint32_t CLKPRESCALER; /*!< (@ 0x00000010) Clock Prescaler Register */ } EWDG_Type; /*!< Size = 20 (0x14) */ /* =========================================================================================================================== */ /* ================ AC784X_SysTick ================ */ /* =========================================================================================================================== */ /** * @brief The AC784X_SysTick Memory Map/Register Definition can be found here. (AC784X_SysTick) */ typedef struct { /*!< (@ 0xE000E010) AC784X_SysTick Structure */ __IOM uint32_t CSR; /*!< (@ 0x00000000) SysTick Control and Status Register, offset: 0x0 */ __IOM uint32_t RVR; /*!< (@ 0x00000004) SysTick Reload Value Register, offset: 0x4 */ __IOM uint32_t CVR; /*!< (@ 0x00000008) SysTick Current Value Register, offset: 0x8 */ __IOM uint32_t CALIB; /*!< (@ 0x0000000C) SysTick Calibration Value Register, offset: 0xC */ } AC784X_SysTickType; /*!< Size = 16 (0x10) */ /* =========================================================================================================================== */ /* ================ SMU ================ */ /* =========================================================================================================================== */ /** * @brief Safety Management Uint (SMU) */ typedef struct { /*!< (@ 0x40089000) SMU Structure */ __IOM uint32_t SFES; /*!< (@ 0x00000000) Single Point Fault Error Status Register */ __IOM uint32_t SFESS; /*!< (@ 0x00000004) Single Point Fault Error Status Shadow Register */ __IOM uint32_t LFES; /*!< (@ 0x00000008) Latent Fault Error Status Register */ __IOM uint32_t LFESS; /*!< (@ 0x0000000C) Latent Fault Error Status Shadow Register */ __IOM uint32_t LKSEQ0; /*!< (@ 0x00000010) Lock Sequence for Single Point Fault Path */ __IOM uint32_t LKSEQ1; /*!< (@ 0x00000014) Lock Sequence for Latent Fault Path */ __IOM uint32_t SWSFE; /*!< (@ 0x00000018) Software Single Point Fault Enable Register */ __IOM uint32_t SWSFES; /*!< (@ 0x0000001C) Software Single Point Fault Enable Shadow Register */ __IOM uint32_t SWLFE; /*!< (@ 0x00000020) Software Latent Fault Enable Register */ __IOM uint32_t SWLFES; /*!< (@ 0x00000024) Software Latent Fault Enable Shadow Register */ __IM uint32_t RESERVED[2]; __IOM uint32_t SFRSTEN; /*!< (@ 0x00000030) Single Point Fault Reset Enable Register */ __IOM uint32_t LFRSTEN; /*!< (@ 0x00000034) Latent Fault Reset Request Enable Register */ __IOM uint32_t SRSTCNTVAL; /*!< (@ 0x00000038) System Reset Request Counter Threshold Register */ __IOM uint32_t SRSTCNT; /*!< (@ 0x0000003C) System Reset Request Counter Register */ __IOM uint32_t SRSTCNTS; /*!< (@ 0x00000040) System Reset Request Counter Shadow Register */ __IOM uint32_t PATHCHK0; /*!< (@ 0x00000044) Path Check for Single Point Fault Path Register */ __IOM uint32_t PATHCHK1; /*!< (@ 0x00000048) Path Check for Latent Fault Error Path Register */ } SMU_Type; /*!< Size = 76 (0x4c) */ /* =========================================================================================================================== */ /* ================ CMU ================ */ /* =========================================================================================================================== */ /** * @brief Clock Monitor Uint (CMU) */ typedef struct { /*!< (@ 0x40000800) CMU Structure */ __IOM uint32_t CR; /*!< (@ 0x00000000) Configure Register */ __IOM uint32_t RCCR; /*!< (@ 0x00000004) Reference Count Configure Register */ __IOM uint32_t HTCR; /*!< (@ 0x00000008) High Threshold Configure Register */ __IOM uint32_t LTCR; /*!< (@ 0x0000000C) Low Threshold Configure Register */ __IM uint32_t RESERVED[2]; __IOM uint32_t SR; /*!< (@ 0x00000018) Status Register */ __IOM uint32_t MON_A7; /*!< (@ 0x0000001C) Monitor Register */ __IOM uint32_t MON_A8; /*!< (@ 0x00000020) Monitor Register */ } CMU_Type; /*!< Size = 36 (0x24) */ /** @} */ /* End of group Device_Peripheral_peripherals */ /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Address Map ================ */ /* =========================================================================================================================== */ /** @addtogroup Device_Peripheral_peripheralAddr * @{ */ #define CKGEN_BASE 0x40000000UL #define PBR_BASE 0x4008A000UL #define SPM_BASE 0x40008000UL #define GPIOA_BASE 0x40085000UL #define GPIOB_BASE 0x40085040UL #define GPIOC_BASE 0x40085080UL #define GPIOD_BASE 0x400850C0UL #define GPIOE_BASE 0x40085100UL #define PORTA_BASE 0x40085200UL #define PORTB_BASE 0x40085300UL #define PORTC_BASE 0x40085400UL #define PORTD_BASE 0x40085500UL #define PORTE_BASE 0x40085600UL #define CAN0_BASE 0x40007000UL #define CAN1_BASE 0x40007200UL #define CAN2_BASE 0x40007400UL #define CAN3_BASE 0x40007600UL #define UART0_BASE 0x40018000UL #define UART1_BASE 0x40018200UL #define UART2_BASE 0x40018400UL #define UART3_BASE 0x40018600UL #define I2C0_BASE 0x4000E000UL #define SPI0_BASE 0x4000C000UL #define SPI1_BASE 0x4000C800UL #define SPI2_BASE 0x4000D000UL #define ANA_BASE 0x40008800UL #define ADC0_BASE 0x40003000UL #define ADC1_BASE 0x40004000UL #define ACMP0_BASE 0x40005000UL #define PWM0_BASE 0x40080000UL #define PWM1_BASE 0x40080800UL #define PWM2_BASE 0x40081000UL #define PWM3_BASE 0x40081800UL #define PWM4_BASE 0x40082000UL #define PWM5_BASE 0x40082800UL #define PDT0_BASE 0x40086000UL #define PDT1_BASE 0x40086800UL #define TIMER_CTRL_BASE 0x40011000UL #define TIMER_CHANNEL0_BASE 0x40011010UL #define TIMER_CHANNEL1_BASE 0x40011020UL #define TIMER_CHANNEL2_BASE 0x40011030UL #define TIMER_CHANNEL3_BASE 0x40011040UL #define PCT_BASE 0x40019000UL #define CTU_BASE 0x40006000UL #define DMA0_TOP_RST_BASE 0x40012000UL #define DMA0_CHANNEL0_BASE 0x40012040UL #define DMA0_CHANNEL1_BASE 0x40012080UL #define DMA0_CHANNEL2_BASE 0x400120C0UL #define DMA0_CHANNEL3_BASE 0x40012100UL #define DMA0_CHANNEL4_BASE 0x40012140UL #define DMA0_CHANNEL5_BASE 0x40012180UL #define DMA0_CHANNEL6_BASE 0x400121C0UL #define DMA0_CHANNEL7_BASE 0x40012200UL #define DMA0_CHANNEL8_BASE 0x40012240UL #define DMA0_CHANNEL9_BASE 0x40012280UL #define DMA0_CHANNEL10_BASE 0x400122C0UL #define DMA0_CHANNEL11_BASE 0x40012300UL #define DMA0_CHANNEL12_BASE 0x40012340UL #define DMA0_CHANNEL13_BASE 0x40012380UL #define DMA0_CHANNEL14_BASE 0x400123C0UL #define DMA0_CHANNEL15_BASE 0x40012400UL #define WDG_BASE 0x4000B000UL #define RTC_BASE 0x40009800UL #define CRC_BASE 0x40084000UL #define EIM_CTRL_BASE 0x40088000UL #define EIM_CHANNEL0_BASE 0x40088010UL #define EIM_CHANNEL1_BASE 0x40088080UL #define ECC_SRAM_BASE 0x40088100UL #define FLASH_BASE 0x40002000UL #define EIO_BASE 0x4000A000UL #define EWDG_BASE 0x4000B400UL #define AC784X_SYSTICK_BASE 0xE000E010UL #define MCM_BASE 0xE008000CUL #define MPU_BASE 0x40087000UL #define SMU_BASE 0x40089000UL #define CMU_VHSI_BASE 0x40000800UL #define CMU_HSE_BASE 0x40000A00UL #define CMU_PLL_BASE 0x40000C00UL #define CSE_PRAM_BASE 0x14001000UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ /* =========================================================================================================================== */ /* ================ Peripheral declaration ================ */ /* =========================================================================================================================== */ /** @addtogroup Device_Peripheral_declaration * @{ */ #define CKGEN ((CKGEN_Type*) CKGEN_BASE) #define PBR ((PBR_Type*) PBR_BASE) #define SPM ((SPM_Type*) SPM_BASE) #define GPIOA ((GPIO_Type*) GPIOA_BASE) #define GPIOB ((GPIO_Type*) GPIOB_BASE) #define GPIOC ((GPIO_Type*) GPIOC_BASE) #define GPIOD ((GPIO_Type*) GPIOD_BASE) #define GPIOE ((GPIO_Type*) GPIOE_BASE) #define PORTA ((PORT_Type*) PORTA_BASE) #define PORTB ((PORT_Type*) PORTB_BASE) #define PORTC ((PORT_Type*) PORTC_BASE) #define PORTD ((PORT_Type*) PORTD_BASE) #define PORTE ((PORT_Type*) PORTE_BASE) #define CAN0 ((CAN_Type*) CAN0_BASE) #define CAN1 ((CAN_Type*) CAN1_BASE) #define CAN2 ((CAN_Type*) CAN2_BASE) #define CAN3 ((CAN_Type*) CAN3_BASE) #define UART0 ((UART_Type*) UART0_BASE) #define UART1 ((UART_Type*) UART1_BASE) #define UART2 ((UART_Type*) UART2_BASE) #define UART3 ((UART_Type*) UART3_BASE) #define I2C0 ((I2C_Type*) I2C0_BASE) #define SPI0 ((SPI_Type*) SPI0_BASE) #define SPI1 ((SPI_Type*) SPI1_BASE) #define SPI2 ((SPI_Type*) SPI2_BASE) #define ANA ((ANA_Type*) ANA_BASE) #define ADC0 ((ADC_Type*) ADC0_BASE) #define ADC1 ((ADC_Type*) ADC1_BASE) #define ACMP0 ((ACMP_Type*) ACMP0_BASE) #define PWM0 ((PWM_Type*) PWM0_BASE) #define PWM1 ((PWM_Type*) PWM1_BASE) #define PWM2 ((PWM_Type*) PWM2_BASE) #define PWM3 ((PWM_Type*) PWM3_BASE) #define PWM4 ((PWM_Type*) PWM4_BASE) #define PWM5 ((PWM_Type*) PWM5_BASE) #define PDT0 ((PDT_Type*) PDT0_BASE) #define PDT1 ((PDT_Type*) PDT1_BASE) #define TIMER_CTRL ((TIMER_CTRL_Type*) TIMER_CTRL_BASE) #define TIMER_CHANNEL0 ((TIMER_CHANNEL_Type*) TIMER_CHANNEL0_BASE) #define TIMER_CHANNEL1 ((TIMER_CHANNEL_Type*) TIMER_CHANNEL1_BASE) #define TIMER_CHANNEL2 ((TIMER_CHANNEL_Type*) TIMER_CHANNEL2_BASE) #define TIMER_CHANNEL3 ((TIMER_CHANNEL_Type*) TIMER_CHANNEL3_BASE) #define PCT ((PCT_Type*) PCT_BASE) #define CTU ((CTU_Type*) CTU_BASE) #define DMA0_TOP_RST ((DMA_TopRstType*) DMA0_TOP_RST_BASE) #define DMA0_CHANNEL0 ((DMA_ChannelType*) DMA0_CHANNEL0_BASE) #define DMA0_CHANNEL1 ((DMA_ChannelType*) DMA0_CHANNEL1_BASE) #define DMA0_CHANNEL2 ((DMA_ChannelType*) DMA0_CHANNEL2_BASE) #define DMA0_CHANNEL3 ((DMA_ChannelType*) DMA0_CHANNEL3_BASE) #define DMA0_CHANNEL4 ((DMA_ChannelType*) DMA0_CHANNEL4_BASE) #define DMA0_CHANNEL5 ((DMA_ChannelType*) DMA0_CHANNEL5_BASE) #define DMA0_CHANNEL6 ((DMA_ChannelType*) DMA0_CHANNEL6_BASE) #define DMA0_CHANNEL7 ((DMA_ChannelType*) DMA0_CHANNEL7_BASE) #define DMA0_CHANNEL8 ((DMA_ChannelType*) DMA0_CHANNEL8_BASE) #define DMA0_CHANNEL9 ((DMA_ChannelType*) DMA0_CHANNEL9_BASE) #define DMA0_CHANNEL10 ((DMA_ChannelType*) DMA0_CHANNEL10_BASE) #define DMA0_CHANNEL11 ((DMA_ChannelType*) DMA0_CHANNEL11_BASE) #define DMA0_CHANNEL12 ((DMA_ChannelType*) DMA0_CHANNEL12_BASE) #define DMA0_CHANNEL13 ((DMA_ChannelType*) DMA0_CHANNEL13_BASE) #define DMA0_CHANNEL14 ((DMA_ChannelType*) DMA0_CHANNEL14_BASE) #define DMA0_CHANNEL15 ((DMA_ChannelType*) DMA0_CHANNEL15_BASE) #define WDG ((WDG_Type*) WDG_BASE) #define RTC ((RTC_Type*) RTC_BASE) #define CRC ((CRC_Type*) CRC_BASE) #define EIM_CTRL ((EIM_CTRL_Type*) EIM_CTRL_BASE) #define EIM_CHANNEL0 ((EIM_CHANNEL_Type*) EIM_CHANNEL0_BASE) #define EIM_CHANNEL1 ((EIM_CHANNEL_Type*) EIM_CHANNEL1_BASE) #define ECC_SRAM ((ECC_SRAM_Type*) ECC_SRAM_BASE) #define FLASH ((FLASH_Type*) FLASH_BASE) #define EIO ((EIO_Type*) EIO_BASE) #define EWDG ((EWDG_Type*) EWDG_BASE) #define AC784X_SYSTICK ((AC784X_SysTickType*) AC784X_SYSTICK_BASE) #define MCM ((MCM_Type*) MCM_BASE) #define MPU ((MPU_Type*) MPU_BASE) #define SMU ((SMU_Type*) SMU_BASE) #define CMU_VHSI ((CMU_Type*) CMU_VHSI_BASE) #define CMU_HSE ((CMU_Type*) CMU_HSE_BASE) #define CMU_PLL ((CMU_Type*) CMU_PLL_BASE) #define CSE_PRAM ((CSE_PRAM_Type *) CSE_PRAM_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ /* =========================================================================================================================== */ /* ================ Pos/Mask Peripheral Section ================ */ /* =========================================================================================================================== */ /** @addtogroup PosMask_peripherals * @{ */ /* =========================================================================================================================== */ /* ================ MCM ================ */ /* =========================================================================================================================== */ /* ========================================================= MCPCR ========================================================= */ #define MCM_MCPCR_SAPU_Pos (24UL) /*!< SAPU (Bit 24) */ #define MCM_MCPCR_SAPU_Msk (0x3000000UL) /*!< SAPU (Bitfield-Mask: 0x03) */ #define MCM_MCPCR_SWPU_Pos (26UL) /*!< SWPU (Bit 26) */ #define MCM_MCPCR_SWPU_Msk (0x4000000UL) /*!< SWPU (Bitfield-Mask: 0x01) */ #define MCM_MCPCR_SAPL_Pos (28UL) /*!< SAPL (Bit 28) */ #define MCM_MCPCR_SAPL_Msk (0x30000000UL) /*!< SAPL (Bitfield-Mask: 0x03) */ #define MCM_MCPCR_SWPL_Pos (30UL) /*!< SWPL (Bit 30) */ #define MCM_MCPCR_SWPL_Msk (0x40000000UL) /*!< SWPL (Bitfield-Mask: 0x01) */ /* ========================================================= MISCR ========================================================= */ #define MCM_MISCR_FIOC_Pos (8UL) /*!< FIOC (Bit 8) */ #define MCM_MISCR_FIOC_Msk (0x100UL) /*!< FIOC (Bitfield-Mask: 0x01) */ #define MCM_MISCR_FDZC_Pos (9UL) /*!< FDZC (Bit 9) */ #define MCM_MISCR_FDZC_Msk (0x200UL) /*!< FDZC (Bitfield-Mask: 0x01) */ #define MCM_MISCR_FOFC_Pos (10UL) /*!< FOFC (Bit 10) */ #define MCM_MISCR_FOFC_Msk (0x400UL) /*!< FOFC (Bitfield-Mask: 0x01) */ #define MCM_MISCR_FUFC_Pos (11UL) /*!< FUFC (Bit 11) */ #define MCM_MISCR_FUFC_Msk (0x800UL) /*!< FUFC (Bitfield-Mask: 0x01) */ #define MCM_MISCR_FIXC_Pos (12UL) /*!< FIXC (Bit 12) */ #define MCM_MISCR_FIXC_Msk (0x1000UL) /*!< FIXC (Bitfield-Mask: 0x01) */ #define MCM_MISCR_FIDC_Pos (15UL) /*!< FIDC (Bit 15) */ #define MCM_MISCR_FIDC_Msk (0x8000UL) /*!< FIDC (Bitfield-Mask: 0x01) */ #define MCM_MISCR_FIOCEN_Pos (24UL) /*!< FIOCEN (Bit 24) */ #define MCM_MISCR_FIOCEN_Msk (0x1000000UL) /*!< FIOCEN (Bitfield-Mask: 0x01) */ #define MCM_MISCR_FDZCEN_Pos (25UL) /*!< FDZCEN (Bit 25) */ #define MCM_MISCR_FDZCEN_Msk (0x2000000UL) /*!< FDZCEN (Bitfield-Mask: 0x01) */ #define MCM_MISCR_FOFCEN_Pos (26UL) /*!< FOFCEN (Bit 26) */ #define MCM_MISCR_FOFCEN_Msk (0x4000000UL) /*!< FOFCEN (Bitfield-Mask: 0x01) */ #define MCM_MISCR_FUFCEN_Pos (27UL) /*!< FUFCEN (Bit 27) */ #define MCM_MISCR_FUFCEN_Msk (0x8000000UL) /*!< FUFCEN (Bitfield-Mask: 0x01) */ #define MCM_MISCR_FIXCEN_Pos (28UL) /*!< FIXCEN (Bit 28) */ #define MCM_MISCR_FIXCEN_Msk (0x10000000UL) /*!< FIXCEN (Bitfield-Mask: 0x01) */ #define MCM_MISCR_FIDCEN_Pos (31UL) /*!< FIDCEN (Bit 31) */ #define MCM_MISCR_FIDCEN_Msk (0x80000000UL) /*!< FIDCEN (Bitfield-Mask: 0x01) */ /* ======================================================== MLMDR0 ========================================================= */ #define MCM_MLMDR0_LREEN_Pos (1UL) /*!< LREEN (Bit 1) */ #define MCM_MLMDR0_LREEN_Msk (0x2UL) /*!< LREEN (Bitfield-Mask: 0x01) */ #define MCM_MLMDR0_UREEN_Pos (3UL) /*!< UREEN (Bit 3) */ #define MCM_MLMDR0_UREEN_Msk (0x8UL) /*!< UREEN (Bitfield-Mask: 0x01) */ #define MCM_MLMDR0_LOCK_Pos (16UL) /*!< LOCK (Bit 16) */ #define MCM_MLMDR0_LOCK_Msk (0x10000UL) /*!< LOCK (Bitfield-Mask: 0x01) */ #define MCM_MLMDR0_LMSZ_Pos (24UL) /*!< LMSZ (Bit 24) */ #define MCM_MLMDR0_LMSZ_Msk (0x7000000UL) /*!< LMSZ (Bitfield-Mask: 0x07) */ /* ========================================================= MBIST ========================================================= */ /* ======================================================== MLMDR1 ========================================================= */ #define MCM_MLMDR1_CPDE_Pos (5UL) /*!< CPDE (Bit 5) */ #define MCM_MLMDR1_CPDE_Msk (0x20UL) /*!< CPDE (Bitfield-Mask: 0x01) */ #define MCM_MLMDR1_CPFE_Pos (7UL) /*!< CPFE (Bit 7) */ #define MCM_MLMDR1_CPFE_Msk (0x80UL) /*!< CPFE (Bitfield-Mask: 0x01) */ #define MCM_MLMDR1_LOCK_Pos (16UL) /*!< LOCK (Bit 16) */ #define MCM_MLMDR1_LOCK_Msk (0x10000UL) /*!< LOCK (Bitfield-Mask: 0x01) */ #define MCM_MLMDR1_CASZ_Pos (24UL) /*!< CASZ (Bit 24) */ #define MCM_MLMDR1_CASZ_Msk (0xf000000UL) /*!< CASZ (Bitfield-Mask: 0x0f) */ /* ======================================================== LMPECR ========================================================= */ #define MCM_LMPECR_CPEIEN_Pos (20UL) /*!< CPEIEN (Bit 20) */ #define MCM_LMPECR_CPEIEN_Msk (0x100000UL) /*!< CPEIEN (Bitfield-Mask: 0x01) */ /* ======================================================== LMPEIR ========================================================= */ /* ========================================================= LMFAR ========================================================= */ /* ========================================================= MCCR ========================================================== */ #define MCM_MCCR_CADIS_Pos (0UL) /*!< CADIS (Bit 0) */ #define MCM_MCCR_CADIS_Msk (0x1UL) /*!< CADIS (Bitfield-Mask: 0x01) */ #define MCM_MCCR_CACL_Pos (1UL) /*!< CACL (Bit 1) */ #define MCM_MCCR_CACL_Msk (0x2UL) /*!< CACL (Bitfield-Mask: 0x01) */ /* ========================================================= MNCR ========================================================== */ #define MCM_MNCR_NMI_EN_Pos (0UL) /*!< NMI_EN (Bit 0) */ #define MCM_MNCR_NMI_EN_Msk (0x1UL) /*!< NMI_EN (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ MPU ================ */ /* =========================================================================================================================== */ /* ========================================================= CESR ========================================================== */ #define MPU_CESR_VLD_Pos (0UL) /*!< VLD (Bit 0) */ #define MPU_CESR_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ #define MPU_CESR_SPERR0_Pos (29UL) /*!< SPERR0 (Bit 29) */ #define MPU_CESR_SPERR0_Msk (0x20000000UL) /*!< SPERR0 (Bitfield-Mask: 0x01) */ #define MPU_CESR_SPERR1_Pos (30UL) /*!< SPERR1 (Bit 30) */ #define MPU_CESR_SPERR1_Msk (0x40000000UL) /*!< SPERR1 (Bitfield-Mask: 0x01) */ #define MPU_CESR_SPERR2_Pos (31UL) /*!< SPERR2 (Bit 31) */ #define MPU_CESR_SPERR2_Msk (0x80000000UL) /*!< SPERR2 (Bitfield-Mask: 0x01) */ /* ========================================================= EAR0 ========================================================== */ #define MPU_EAR0_EADDR_Pos (0UL) /*!< EADDR (Bit 0) */ #define MPU_EAR0_EADDR_Msk (0xffffffffUL) /*!< EADDR (Bitfield-Mask: 0xffffffff) */ /* ========================================================= EAR1 ========================================================== */ #define MPU_EAR1_EADDR_Pos (0UL) /*!< EADDR (Bit 0) */ #define MPU_EAR1_EADDR_Msk (0xffffffffUL) /*!< EADDR (Bitfield-Mask: 0xffffffff) */ /* ========================================================= EAR2 ========================================================== */ #define MPU_EAR2_EADDR_Pos (0UL) /*!< EADDR (Bit 0) */ #define MPU_EAR2_EADDR_Msk (0xffffffffUL) /*!< EADDR (Bitfield-Mask: 0xffffffff) */ /* ========================================================= EDR0 ========================================================== */ #define MPU_EDR0_ERW_Pos (0UL) /*!< ERW (Bit 0) */ #define MPU_EDR0_ERW_Msk (0x1UL) /*!< ERW (Bitfield-Mask: 0x01) */ #define MPU_EDR0_EATTR_Pos (1UL) /*!< EATTR (Bit 1) */ #define MPU_EDR0_EATTR_Msk (0x1eUL) /*!< EATTR (Bitfield-Mask: 0x0f) */ #define MPU_EDR0_EMN_Pos (5UL) /*!< EMN (Bit 5) */ #define MPU_EDR0_EMN_Msk (0xe0UL) /*!< EMN (Bitfield-Mask: 0x07) */ #define MPU_EDR0_EPID_Pos (8UL) /*!< EPID (Bit 8) */ #define MPU_EDR0_EPID_Msk (0xff00UL) /*!< EPID (Bitfield-Mask: 0xff) */ #define MPU_EDR0_EACD_Pos (16UL) /*!< EACD (Bit 16) */ #define MPU_EDR0_EACD_Msk (0xff0000UL) /*!< EACD (Bitfield-Mask: 0xff) */ #define MPU_EDR0_EFLG_Pos (31UL) /*!< EFLG (Bit 31) */ #define MPU_EDR0_EFLG_Msk (0x80000000UL) /*!< EFLG (Bitfield-Mask: 0x01) */ /* ========================================================= EDR1 ========================================================== */ #define MPU_EDR1_ERW_Pos (0UL) /*!< ERW (Bit 0) */ #define MPU_EDR1_ERW_Msk (0x1UL) /*!< ERW (Bitfield-Mask: 0x01) */ #define MPU_EDR1_EATTR_Pos (1UL) /*!< EATTR (Bit 1) */ #define MPU_EDR1_EATTR_Msk (0x1eUL) /*!< EATTR (Bitfield-Mask: 0x0f) */ #define MPU_EDR1_EMN_Pos (5UL) /*!< EMN (Bit 5) */ #define MPU_EDR1_EMN_Msk (0xe0UL) /*!< EMN (Bitfield-Mask: 0x07) */ #define MPU_EDR1_EPID_Pos (8UL) /*!< EPID (Bit 8) */ #define MPU_EDR1_EPID_Msk (0xff00UL) /*!< EPID (Bitfield-Mask: 0xff) */ #define MPU_EDR1_EACD_Pos (16UL) /*!< EACD (Bit 16) */ #define MPU_EDR1_EACD_Msk (0xff0000UL) /*!< EACD (Bitfield-Mask: 0xff) */ #define MPU_EDR1_EFLG_Pos (31UL) /*!< EFLG (Bit 31) */ #define MPU_EDR1_EFLG_Msk (0x80000000UL) /*!< EFLG (Bitfield-Mask: 0x01) */ /* ========================================================= EDR2 ========================================================== */ #define MPU_EDR2_ERW_Pos (0UL) /*!< ERW (Bit 0) */ #define MPU_EDR2_ERW_Msk (0x1UL) /*!< ERW (Bitfield-Mask: 0x01) */ #define MPU_EDR2_EATTR_Pos (1UL) /*!< EATTR (Bit 1) */ #define MPU_EDR2_EATTR_Msk (0x1eUL) /*!< EATTR (Bitfield-Mask: 0x0f) */ #define MPU_EDR2_EMN_Pos (5UL) /*!< EMN (Bit 5) */ #define MPU_EDR2_EMN_Msk (0xe0UL) /*!< EMN (Bitfield-Mask: 0x07) */ #define MPU_EDR2_EPID_Pos (8UL) /*!< EPID (Bit 8) */ #define MPU_EDR2_EPID_Msk (0xff00UL) /*!< EPID (Bitfield-Mask: 0xff) */ #define MPU_EDR2_EACD_Pos (16UL) /*!< EACD (Bit 16) */ #define MPU_EDR2_EACD_Msk (0xff0000UL) /*!< EACD (Bitfield-Mask: 0xff) */ #define MPU_EDR2_EFLG_Pos (31UL) /*!< EFLG (Bit 31) */ #define MPU_EDR2_EFLG_Msk (0x80000000UL) /*!< EFLG (Bitfield-Mask: 0x01) */ /* ========================================================= MPID ========================================================== */ #define MPU_MPID_M0PID_Pos (0UL) /*!< M0PID (Bit 0) */ #define MPU_MPID_M0PID_Msk (0xffUL) /*!< M0PID (Bitfield-Mask: 0xff) */ #define MPU_MPID_M1PID_Pos (8UL) /*!< M1PID (Bit 8) */ #define MPU_MPID_M1PID_Msk (0xff00UL) /*!< M1PID (Bitfield-Mask: 0xff) */ /* ====================================================== RGD0_WORD0 ======================================================= */ #define MPU_RGD0_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ #define MPU_RGD0_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD0_WORD1 ======================================================= */ #define MPU_RGD0_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ #define MPU_RGD0_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD0_WORD2 ======================================================= */ #define MPU_RGD0_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGD0_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGD0_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGD0_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGD0_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGD0_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGD0_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGD0_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGD0_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGD0_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGD0_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGD0_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGD0_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGD0_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGD0_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGD0_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGD0_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGD0_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ====================================================== RGD0_WORD3 ======================================================= */ #define MPU_RGD0_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ #define MPU_RGD0_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ #define MPU_RGD0_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ #define MPU_RGD0_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ #define MPU_RGD0_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ #define MPU_RGD0_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ /* ====================================================== RGD1_WORD0 ======================================================= */ #define MPU_RGD1_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ #define MPU_RGD1_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD1_WORD1 ======================================================= */ #define MPU_RGD1_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ #define MPU_RGD1_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD1_WORD2 ======================================================= */ #define MPU_RGD1_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGD1_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGD1_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGD1_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGD1_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGD1_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGD1_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGD1_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGD1_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGD1_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGD1_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGD1_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGD1_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGD1_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGD1_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGD1_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGD1_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGD1_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ====================================================== RGD1_WORD3 ======================================================= */ #define MPU_RGD1_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ #define MPU_RGD1_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ #define MPU_RGD1_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ #define MPU_RGD1_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ #define MPU_RGD1_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ #define MPU_RGD1_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ /* ====================================================== RGD2_WORD0 ======================================================= */ #define MPU_RGD2_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ #define MPU_RGD2_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD2_WORD1 ======================================================= */ #define MPU_RGD2_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ #define MPU_RGD2_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD2_WORD2 ======================================================= */ #define MPU_RGD2_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGD2_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGD2_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGD2_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGD2_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGD2_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGD2_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGD2_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGD2_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGD2_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGD2_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGD2_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGD2_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGD2_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGD2_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGD2_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGD2_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGD2_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ====================================================== RGD2_WORD3 ======================================================= */ #define MPU_RGD2_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ #define MPU_RGD2_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ #define MPU_RGD2_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ #define MPU_RGD2_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ #define MPU_RGD2_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ #define MPU_RGD2_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ /* ====================================================== RGD3_WORD0 ======================================================= */ #define MPU_RGD3_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ #define MPU_RGD3_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD3_WORD1 ======================================================= */ #define MPU_RGD3_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ #define MPU_RGD3_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD3_WORD2 ======================================================= */ #define MPU_RGD3_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGD3_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGD3_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGD3_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGD3_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGD3_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGD3_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGD3_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGD3_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGD3_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGD3_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGD3_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGD3_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGD3_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGD3_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGD3_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGD3_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGD3_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ====================================================== RGD3_WORD3 ======================================================= */ #define MPU_RGD3_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ #define MPU_RGD3_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ #define MPU_RGD3_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ #define MPU_RGD3_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ #define MPU_RGD3_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ #define MPU_RGD3_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ /* ====================================================== RGD4_WORD0 ======================================================= */ #define MPU_RGD4_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ #define MPU_RGD4_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD4_WORD1 ======================================================= */ #define MPU_RGD4_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ #define MPU_RGD4_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD4_WORD2 ======================================================= */ #define MPU_RGD4_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGD4_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGD4_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGD4_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGD4_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGD4_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGD4_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGD4_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGD4_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGD4_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGD4_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGD4_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGD4_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGD4_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGD4_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGD4_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGD4_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGD4_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ====================================================== RGD4_WORD3 ======================================================= */ #define MPU_RGD4_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ #define MPU_RGD4_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ #define MPU_RGD4_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ #define MPU_RGD4_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ #define MPU_RGD4_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ #define MPU_RGD4_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ /* ====================================================== RGD5_WORD0 ======================================================= */ #define MPU_RGD5_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ #define MPU_RGD5_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD5_WORD1 ======================================================= */ #define MPU_RGD5_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ #define MPU_RGD5_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD5_WORD2 ======================================================= */ #define MPU_RGD5_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGD5_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGD5_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGD5_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGD5_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGD5_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGD5_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGD5_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGD5_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGD5_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGD5_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGD5_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGD5_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGD5_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGD5_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGD5_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGD5_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGD5_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ====================================================== RGD5_WORD3 ======================================================= */ #define MPU_RGD5_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ #define MPU_RGD5_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ #define MPU_RGD5_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ #define MPU_RGD5_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ #define MPU_RGD5_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ #define MPU_RGD5_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ /* ====================================================== RGD6_WORD0 ======================================================= */ #define MPU_RGD6_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ #define MPU_RGD6_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD6_WORD1 ======================================================= */ #define MPU_RGD6_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ #define MPU_RGD6_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD6_WORD2 ======================================================= */ #define MPU_RGD6_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGD6_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGD6_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGD6_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGD6_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGD6_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGD6_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGD6_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGD6_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGD6_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGD6_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGD6_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGD6_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGD6_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGD6_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGD6_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGD6_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGD6_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ====================================================== RGD6_WORD3 ======================================================= */ #define MPU_RGD6_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ #define MPU_RGD6_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ #define MPU_RGD6_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ #define MPU_RGD6_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ #define MPU_RGD6_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ #define MPU_RGD6_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ /* ====================================================== RGD7_WORD0 ======================================================= */ #define MPU_RGD7_WORD0_SRTADDR_Pos (5UL) /*!< SRTADDR (Bit 5) */ #define MPU_RGD7_WORD0_SRTADDR_Msk (0xffffffe0UL) /*!< SRTADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD7_WORD1 ======================================================= */ #define MPU_RGD7_WORD1_ENDADDR_Pos (5UL) /*!< ENDADDR (Bit 5) */ #define MPU_RGD7_WORD1_ENDADDR_Msk (0xffffffe0UL) /*!< ENDADDR (Bitfield-Mask: 0x7ffffff) */ /* ====================================================== RGD7_WORD2 ======================================================= */ #define MPU_RGD7_WORD2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGD7_WORD2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGD7_WORD2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGD7_WORD2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGD7_WORD2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGD7_WORD2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGD7_WORD2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGD7_WORD2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGD7_WORD2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGD7_WORD2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGD7_WORD2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGD7_WORD2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGD7_WORD2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGD7_WORD2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGD7_WORD2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGD7_WORD2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGD7_WORD2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGD7_WORD2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ====================================================== RGD7_WORD3 ======================================================= */ #define MPU_RGD7_WORD3_VLD_Pos (0UL) /*!< VLD (Bit 0) */ #define MPU_RGD7_WORD3_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */ #define MPU_RGD7_WORD3_PIDMASK_Pos (16UL) /*!< PIDMASK (Bit 16) */ #define MPU_RGD7_WORD3_PIDMASK_Msk (0xff0000UL) /*!< PIDMASK (Bitfield-Mask: 0xff) */ #define MPU_RGD7_WORD3_PID_Pos (24UL) /*!< PID (Bit 24) */ #define MPU_RGD7_WORD3_PID_Msk (0xff000000UL) /*!< PID (Bitfield-Mask: 0xff) */ /* ======================================================== RGDAAC0 ======================================================== */ #define MPU_RGDAAC0_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGDAAC0_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGDAAC0_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGDAAC0_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGDAAC0_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGDAAC0_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGDAAC0_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGDAAC0_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGDAAC0_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGDAAC0_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGDAAC0_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGDAAC0_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGDAAC0_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGDAAC0_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGDAAC0_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGDAAC0_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGDAAC0_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC0_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGDAAC0_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ======================================================== RGDAAC1 ======================================================== */ #define MPU_RGDAAC1_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGDAAC1_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGDAAC1_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGDAAC1_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGDAAC1_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGDAAC1_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGDAAC1_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGDAAC1_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGDAAC1_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGDAAC1_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGDAAC1_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGDAAC1_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGDAAC1_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGDAAC1_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGDAAC1_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGDAAC1_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGDAAC1_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC1_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGDAAC1_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ======================================================== RGDAAC2 ======================================================== */ #define MPU_RGDAAC2_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGDAAC2_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGDAAC2_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGDAAC2_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGDAAC2_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGDAAC2_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGDAAC2_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGDAAC2_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGDAAC2_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGDAAC2_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGDAAC2_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGDAAC2_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGDAAC2_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGDAAC2_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGDAAC2_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGDAAC2_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGDAAC2_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC2_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGDAAC2_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ======================================================== RGDAAC3 ======================================================== */ #define MPU_RGDAAC3_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGDAAC3_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGDAAC3_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGDAAC3_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGDAAC3_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGDAAC3_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGDAAC3_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGDAAC3_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGDAAC3_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGDAAC3_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGDAAC3_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGDAAC3_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGDAAC3_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGDAAC3_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGDAAC3_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGDAAC3_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGDAAC3_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC3_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGDAAC3_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ======================================================== RGDAAC4 ======================================================== */ #define MPU_RGDAAC4_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGDAAC4_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGDAAC4_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGDAAC4_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGDAAC4_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGDAAC4_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGDAAC4_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGDAAC4_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGDAAC4_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGDAAC4_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGDAAC4_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGDAAC4_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGDAAC4_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGDAAC4_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGDAAC4_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGDAAC4_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGDAAC4_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC4_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGDAAC4_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ======================================================== RGDAAC5 ======================================================== */ #define MPU_RGDAAC5_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGDAAC5_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGDAAC5_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGDAAC5_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGDAAC5_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGDAAC5_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGDAAC5_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGDAAC5_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGDAAC5_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGDAAC5_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGDAAC5_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGDAAC5_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGDAAC5_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGDAAC5_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGDAAC5_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGDAAC5_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGDAAC5_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC5_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGDAAC5_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ======================================================== RGDAAC6 ======================================================== */ #define MPU_RGDAAC6_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGDAAC6_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGDAAC6_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGDAAC6_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGDAAC6_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGDAAC6_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGDAAC6_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGDAAC6_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGDAAC6_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGDAAC6_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGDAAC6_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGDAAC6_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGDAAC6_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGDAAC6_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGDAAC6_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGDAAC6_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGDAAC6_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC6_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGDAAC6_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* ======================================================== RGDAAC7 ======================================================== */ #define MPU_RGDAAC7_M0UX_Pos (0UL) /*!< M0UX (Bit 0) */ #define MPU_RGDAAC7_M0UX_Msk (0x1UL) /*!< M0UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M0UR_Pos (1UL) /*!< M0UR (Bit 1) */ #define MPU_RGDAAC7_M0UR_Msk (0x2UL) /*!< M0UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M0UW_Pos (2UL) /*!< M0UW (Bit 2) */ #define MPU_RGDAAC7_M0UW_Msk (0x4UL) /*!< M0UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M0SX_Pos (3UL) /*!< M0SX (Bit 3) */ #define MPU_RGDAAC7_M0SX_Msk (0x8UL) /*!< M0SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M0SR_Pos (4UL) /*!< M0SR (Bit 4) */ #define MPU_RGDAAC7_M0SR_Msk (0x10UL) /*!< M0SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M0SW_Pos (5UL) /*!< M0SW (Bit 5) */ #define MPU_RGDAAC7_M0SW_Msk (0x20UL) /*!< M0SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M1UX_Pos (6UL) /*!< M1UX (Bit 6) */ #define MPU_RGDAAC7_M1UX_Msk (0x40UL) /*!< M1UX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M1UR_Pos (7UL) /*!< M1UR (Bit 7) */ #define MPU_RGDAAC7_M1UR_Msk (0x80UL) /*!< M1UR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M1UW_Pos (8UL) /*!< M1UW (Bit 8) */ #define MPU_RGDAAC7_M1UW_Msk (0x100UL) /*!< M1UW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M1SX_Pos (9UL) /*!< M1SX (Bit 9) */ #define MPU_RGDAAC7_M1SX_Msk (0x200UL) /*!< M1SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M1SR_Pos (10UL) /*!< M1SR (Bit 10) */ #define MPU_RGDAAC7_M1SR_Msk (0x400UL) /*!< M1SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M1SW_Pos (11UL) /*!< M1SW (Bit 11) */ #define MPU_RGDAAC7_M1SW_Msk (0x800UL) /*!< M1SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M2SX_Pos (15UL) /*!< M2SX (Bit 15) */ #define MPU_RGDAAC7_M2SX_Msk (0x8000UL) /*!< M2SX (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M2SR_Pos (16UL) /*!< M2SR (Bit 16) */ #define MPU_RGDAAC7_M2SR_Msk (0x10000UL) /*!< M2SR (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M2SW_Pos (17UL) /*!< M2SW (Bit 17) */ #define MPU_RGDAAC7_M2SW_Msk (0x20000UL) /*!< M2SW (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M0PE_Pos (31UL) /*!< M0PE (Bit 31) */ #define MPU_RGDAAC7_M0PE_Msk (0x80000000UL) /*!< M0PE (Bitfield-Mask: 0x01) */ #define MPU_RGDAAC7_M1PE_Pos (30UL) /*!< M1PE (Bit 30) */ #define MPU_RGDAAC7_M1PE_Msk (0x40000000UL) /*!< M1PE (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ CKGEN ================ */ /* =========================================================================================================================== */ /* ========================================================= CTRL ========================================================== */ #define CKGEN_CTRL_BUS_CLK_DIV_VLPR_Pos (0UL) /*!< BUS_CLK_DIV_VLPR (Bit 0) */ #define CKGEN_CTRL_BUS_CLK_DIV_VLPR_Msk (0xfUL) /*!< BUS_CLK_DIV_VLPR (Bitfield-Mask: 0x0f) */ #define CKGEN_CTRL_BUS_CLK_DIV_RUN_Pos (4UL) /*!< BUS_CLK_DIV_RUN (Bit 4) */ #define CKGEN_CTRL_BUS_CLK_DIV_RUN_Msk (0xf0UL) /*!< BUS_CLK_DIV_RUN (Bitfield-Mask: 0x0f) */ #define CKGEN_CTRL_SYSCLK_DIV_VLPR_Pos (12UL) /*!< SYSCLK_DIV_VLPR (Bit 12) */ #define CKGEN_CTRL_SYSCLK_DIV_VLPR_Msk (0xf000UL) /*!< SYSCLK_DIV_VLPR (Bitfield-Mask: 0x0f) */ #define CKGEN_CTRL_SYSCLK_DIV_Pos (16UL) /*!< SYSCLK_DIV (Bit 16) */ #define CKGEN_CTRL_SYSCLK_DIV_Msk (0xf0000UL) /*!< SYSCLK_DIV (Bitfield-Mask: 0x0f) */ #define CKGEN_CTRL_PLL_REF_SEL_Pos (20UL) /*!< PLL_REF_SEL (Bit 20) */ #define CKGEN_CTRL_PLL_REF_SEL_Msk (0x100000UL) /*!< PLL_REF_SEL (Bitfield-Mask: 0x01) */ #define CKGEN_CTRL_XOSC_MON_EN_Pos (21UL) /*!< XOSC_MON_EN (Bit 21) */ #define CKGEN_CTRL_XOSC_MON_EN_Msk (0x200000UL) /*!< XOSC_MON_EN (Bitfield-Mask: 0x01) */ #define CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Pos (22UL) /*!< SYSCLK_SRC_SEL_RUN (Bit 22) */ #define CKGEN_CTRL_SYSCLK_SRC_SEL_RUN_Msk (0x3c00000UL) /*!< SYSCLK_SRC_SEL_RUN (Bitfield-Mask: 0x0f) */ #define CKGEN_CTRL_SYSCLK_SRC_SEL_VLPR_Pos (26UL) /*!< SYSCLK_SRC_SEL_VLPR (Bit 26) */ #define CKGEN_CTRL_SYSCLK_SRC_SEL_VLPR_Msk (0x3c000000UL) /*!< SYSCLK_SRC_SEL_VLPR (Bitfield-Mask: 0x0f) */ #define CKGEN_CTRL_LOCK_Pos (31UL) /*!< LOCK (Bit 31) */ #define CKGEN_CTRL_LOCK_Msk (0x80000000UL) /*!< LOCK (Bitfield-Mask: 0x01) */ /* ====================================================== LP_CLK_MUX ======================================================= */ #define CKGEN_LP_CLK_MUX_LSI_CLK_MUX_Pos (0UL) /*!< LSI_CLK_MUX (Bit 0) */ #define CKGEN_LP_CLK_MUX_LSI_CLK_MUX_Msk (0x3UL) /*!< LSI_CLK_MUX (Bitfield-Mask: 0x03) */ #define CKGEN_LP_CLK_MUX_RTC_CLK_MUX_Pos (2UL) /*!< RTC_CLK_MUX (Bit 2) */ #define CKGEN_LP_CLK_MUX_RTC_CLK_MUX_Msk (0xcUL) /*!< RTC_CLK_MUX (Bitfield-Mask: 0x03) */ /* ===================================================== PERI_CLK_EN0 ====================================================== */ #define CKGEN_PERI_CLK_EN0_UART0_EN_Pos (0UL) /*!< UART0_EN (Bit 0) */ #define CKGEN_PERI_CLK_EN0_UART0_EN_Msk (0x1UL) /*!< UART0_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_UART1_EN_Pos (1UL) /*!< UART1_EN (Bit 1) */ #define CKGEN_PERI_CLK_EN0_UART1_EN_Msk (0x2UL) /*!< UART1_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_UART2_EN_Pos (2UL) /*!< UART2_EN (Bit 2) */ #define CKGEN_PERI_CLK_EN0_UART2_EN_Msk (0x4UL) /*!< UART2_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_UART3_EN_Pos (3UL) /*!< UART3_EN (Bit 3) */ #define CKGEN_PERI_CLK_EN0_UART3_EN_Msk (0x8UL) /*!< UART3_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_SPI0_EN_Pos (6UL) /*!< SPI0_EN (Bit 6) */ #define CKGEN_PERI_CLK_EN0_SPI0_EN_Msk (0x40UL) /*!< SPI0_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_SPI1_EN_Pos (7UL) /*!< SPI1_EN (Bit 7) */ #define CKGEN_PERI_CLK_EN0_SPI1_EN_Msk (0x80UL) /*!< SPI1_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_SPI2_EN_Pos (8UL) /*!< SPI2_EN (Bit 8) */ #define CKGEN_PERI_CLK_EN0_SPI2_EN_Msk (0x100UL) /*!< SPI2_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_I2C0_EN_Pos (9UL) /*!< I2C0_EN (Bit 9) */ #define CKGEN_PERI_CLK_EN0_I2C0_EN_Msk (0x200UL) /*!< I2C0_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_PCT_EN_Pos (11UL) /*!< PCT_EN (Bit 11) */ #define CKGEN_PERI_CLK_EN0_PCT_EN_Msk (0x800UL) /*!< PCT_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_PWM0_EN_Pos (15UL) /*!< PWM0_EN (Bit 15) */ #define CKGEN_PERI_CLK_EN0_PWM0_EN_Msk (0x8000UL) /*!< PWM0_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_PWM1_EN_Pos (16UL) /*!< PWM1_EN (Bit 16) */ #define CKGEN_PERI_CLK_EN0_PWM1_EN_Msk (0x10000UL) /*!< PWM1_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_PWM2_EN_Pos (17UL) /*!< PWM2_EN (Bit 17) */ #define CKGEN_PERI_CLK_EN0_PWM2_EN_Msk (0x20000UL) /*!< PWM2_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_PWM3_EN_Pos (18UL) /*!< PWM3_EN (Bit 18) */ #define CKGEN_PERI_CLK_EN0_PWM3_EN_Msk (0x40000UL) /*!< PWM3_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_PWM4_EN_Pos (19UL) /*!< PWM4_EN (Bit 19) */ #define CKGEN_PERI_CLK_EN0_PWM4_EN_Msk (0x80000UL) /*!< PWM4_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN0_PWM5_EN_Pos (20UL) /*!< PWM5_EN (Bit 20) */ #define CKGEN_PERI_CLK_EN0_PWM5_EN_Msk (0x100000UL) /*!< PWM5_EN (Bitfield-Mask: 0x01) */ /* ===================================================== PERI_CLK_EN1 ====================================================== */ #define CKGEN_PERI_CLK_EN1_RTC_EN_Pos (1UL) /*!< RTC_EN (Bit 1) */ #define CKGEN_PERI_CLK_EN1_RTC_EN_Msk (0x2UL) /*!< RTC_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN1_DMA_EN_Pos (2UL) /*!< DMA_EN (Bit 2) */ #define CKGEN_PERI_CLK_EN1_DMA_EN_Msk (0x4UL) /*!< DMA_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN1_GPIO_EN_Pos (5UL) /*!< GPIO_EN (Bit 5) */ #define CKGEN_PERI_CLK_EN1_GPIO_EN_Msk (0x20UL) /*!< GPIO_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN1_WDG_EN_Pos (6UL) /*!< WDG_EN (Bit 6) */ #define CKGEN_PERI_CLK_EN1_WDG_EN_Msk (0x40UL) /*!< WDG_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN1_EWDG_EN_Pos (7UL) /*!< EWDG_EN (Bit 7) */ #define CKGEN_PERI_CLK_EN1_EWDG_EN_Msk (0x80UL) /*!< EWDG_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN1_CRC_EN_Pos (8UL) /*!< CRC_EN (Bit 8) */ #define CKGEN_PERI_CLK_EN1_CRC_EN_Msk (0x100UL) /*!< CRC_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN1_CAN0_EN_Pos (9UL) /*!< CAN0_EN (Bit 9) */ #define CKGEN_PERI_CLK_EN1_CAN0_EN_Msk (0x200UL) /*!< CAN0_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN1_CAN1_EN_Pos (10UL) /*!< CAN1_EN (Bit 10) */ #define CKGEN_PERI_CLK_EN1_CAN1_EN_Msk (0x400UL) /*!< CAN1_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN1_CAN2_EN_Pos (11UL) /*!< CAN2_EN (Bit 11) */ #define CKGEN_PERI_CLK_EN1_CAN2_EN_Msk (0x800UL) /*!< CAN2_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN1_CAN3_EN_Pos (12UL) /*!< CAN3_EN (Bit 12) */ #define CKGEN_PERI_CLK_EN1_CAN3_EN_Msk (0x1000UL) /*!< CAN3_EN (Bitfield-Mask: 0x01) */ /* ===================================================== PERI_CLK_EN2 ====================================================== */ #define CKGEN_PERI_CLK_EN2_CTU_EN_Pos (1UL) /*!< CTU_EN (Bit 1) */ #define CKGEN_PERI_CLK_EN2_CTU_EN_Msk (0x2UL) /*!< CTU_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN2_ACMP_EN_Pos (8UL) /*!< ACMP_EN (Bit 8) */ #define CKGEN_PERI_CLK_EN2_ACMP_EN_Msk (0x100UL) /*!< ACMP_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN2_PDT0_EN_Pos (9UL) /*!< PDT0_EN (Bit 9) */ #define CKGEN_PERI_CLK_EN2_PDT0_EN_Msk (0x200UL) /*!< PDT0_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN2_PDT1_EN_Pos (10UL) /*!< PDT1_EN (Bit 10) */ #define CKGEN_PERI_CLK_EN2_PDT1_EN_Msk (0x400UL) /*!< PDT1_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN2_ADC0_EN_Pos (11UL) /*!< ADC0_EN (Bit 11) */ #define CKGEN_PERI_CLK_EN2_ADC0_EN_Msk (0x800UL) /*!< ADC0_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN2_ADC1_EN_Pos (12UL) /*!< ADC1_EN (Bit 12) */ #define CKGEN_PERI_CLK_EN2_ADC1_EN_Msk (0x1000UL) /*!< ADC1_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN2_TIMER_EN_Pos (13UL) /*!< TIMER_EN (Bit 13) */ #define CKGEN_PERI_CLK_EN2_TIMER_EN_Msk (0x2000UL) /*!< TIMER_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN2_EIO_EN_Pos (14UL) /*!< EIO_EN (Bit 14) */ #define CKGEN_PERI_CLK_EN2_EIO_EN_Msk (0x4000UL) /*!< EIO_EN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_EN2_SMU_EN_Pos (19UL) /*!< SMU_EN (Bit 19) */ #define CKGEN_PERI_CLK_EN2_SMU_EN_Msk (0x80000UL) /*!< SMU_EN (Bitfield-Mask: 0x01) */ /* ======================================================= RCM_CTRL ======================================================== */ #define CKGEN_RCM_CTRL_EXT_RST_FILTER_EN_Pos (0UL) /*!< EXT_RST_FILTER_EN (Bit 0) */ #define CKGEN_RCM_CTRL_EXT_RST_FILTER_EN_Msk (0x1UL) /*!< EXT_RST_FILTER_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_CTRL_EXT_RST_FILTER_VAL_Pos (1UL) /*!< EXT_RST_FILTER_VAL (Bit 1) */ #define CKGEN_RCM_CTRL_EXT_RST_FILTER_VAL_Msk (0xfeUL) /*!< EXT_RST_FILTER_VAL (Bitfield-Mask: 0x7f) */ #define CKGEN_RCM_CTRL_RST_DLY_TIME_Pos (8UL) /*!< RST_DLY_TIME (Bit 8) */ #define CKGEN_RCM_CTRL_RST_DLY_TIME_Msk (0x300UL) /*!< RST_DLY_TIME (Bitfield-Mask: 0x03) */ #define CKGEN_RCM_CTRL_SW_RST_INT_EN_Pos (10UL) /*!< SW_RST_INT_EN (Bit 10) */ #define CKGEN_RCM_CTRL_SW_RST_INT_EN_Msk (0x400UL) /*!< SW_RST_INT_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_CTRL_LOCKUP_RST_INT_EN_Pos (11UL) /*!< LOCKUP_RST_INT_EN (Bit 11) */ #define CKGEN_RCM_CTRL_LOCKUP_RST_INT_EN_Msk (0x800UL) /*!< LOCKUP_RST_INT_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_CTRL_ACK_ERR_RST_INT_EN_Pos (12UL) /*!< ACK_ERR_RST_INT_EN (Bit 12) */ #define CKGEN_RCM_CTRL_ACK_ERR_RST_INT_EN_Msk (0x1000UL) /*!< ACK_ERR_RST_INT_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_CTRL_WDG_RST_INT_EN_Pos (13UL) /*!< WDG_RST_INT_EN (Bit 13) */ #define CKGEN_RCM_CTRL_WDG_RST_INT_EN_Msk (0x2000UL) /*!< WDG_RST_INT_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_CTRL_XOSC_LOSS_RST_INT_EN_Pos (15UL) /*!< XOSC_LOSS_RST_INT_EN (Bit 15) */ #define CKGEN_RCM_CTRL_XOSC_LOSS_RST_INT_EN_Msk (0x8000UL) /*!< XOSC_LOSS_RST_INT_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_CTRL_PLL_UNLOCK_RST_INT_EN_Pos (16UL) /*!< PLL_UNLOCK_RST_INT_EN (Bit 16) */ #define CKGEN_RCM_CTRL_PLL_UNLOCK_RST_INT_EN_Msk (0x10000UL) /*!< PLL_UNLOCK_RST_INT_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_CTRL_VHSI_LOSS_RST_INT_EN_Pos (17UL) /*!< VHSI_LOSS_RST_INT_EN (Bit 17) */ #define CKGEN_RCM_CTRL_VHSI_LOSS_RST_INT_EN_Msk (0x20000UL) /*!< VHSI_LOSS_RST_INT_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_CTRL_SMU_ERR_RST_INT_EN_Pos (19UL) /*!< SMU_ERR_RST_INT_EN (Bit 19) */ #define CKGEN_RCM_CTRL_SMU_ERR_RST_INT_EN_Msk (0x80000UL) /*!< SMU_ERR_RST_INT_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_CTRL_ECC2_ERR_RST_INT_EN_Pos (20UL) /*!< ECC2_ERR_RST_INT_EN (Bit 20) */ #define CKGEN_RCM_CTRL_ECC2_ERR_RST_INT_EN_Msk (0x100000UL) /*!< ECC2_ERR_RST_INT_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_CTRL_RST_CLK_SEL_Pos (22UL) /*!< RST_CLK_SEL (Bit 22) */ #define CKGEN_RCM_CTRL_RST_CLK_SEL_Msk (0x400000UL) /*!< RST_CLK_SEL (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_CTRL_RST_GLB_INT_EN_Pos (23UL) /*!< RST_GLB_INT_EN (Bit 23) */ #define CKGEN_RCM_CTRL_RST_GLB_INT_EN_Msk (0x800000UL) /*!< RST_GLB_INT_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_CTRL_RST_CLK_AUTO_SEL_Pos (31UL) /*!< RST_CLK_AUTO_SEL (Bit 31) */ #define CKGEN_RCM_CTRL_RST_CLK_AUTO_SEL_Msk (0x80000000UL) /*!< RST_CLK_AUTO_SEL (Bitfield-Mask: 0x01) */ /* ======================================================== RCM_EN ========================================================= */ #define CKGEN_RCM_EN_SW_RST_EN_Pos (0UL) /*!< SW_RST_EN (Bit 0) */ #define CKGEN_RCM_EN_SW_RST_EN_Msk (0x1UL) /*!< SW_RST_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_EN_LOCKUP_RST_EN_Pos (1UL) /*!< LOCKUP_RST_EN (Bit 1) */ #define CKGEN_RCM_EN_LOCKUP_RST_EN_Msk (0x2UL) /*!< LOCKUP_RST_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_EN_ACK_ERR_RST_EN_Pos (2UL) /*!< ACK_ERR_RST_EN (Bit 2) */ #define CKGEN_RCM_EN_ACK_ERR_RST_EN_Msk (0x4UL) /*!< ACK_ERR_RST_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_EN_WDG_RST_EN_Pos (3UL) /*!< WDG_RST_EN (Bit 3) */ #define CKGEN_RCM_EN_WDG_RST_EN_Msk (0x8UL) /*!< WDG_RST_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_EN_XOSC_LOSS_RST_EN_Pos (5UL) /*!< XOSC_LOSS_RST_EN (Bit 5) */ #define CKGEN_RCM_EN_XOSC_LOSS_RST_EN_Msk (0x20UL) /*!< XOSC_LOSS_RST_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_EN_PLL_UNLOCK_RST_EN_Pos (6UL) /*!< PLL_UNLOCK_RST_EN (Bit 6) */ #define CKGEN_RCM_EN_PLL_UNLOCK_RST_EN_Msk (0x40UL) /*!< PLL_UNLOCK_RST_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_EN_VHSI_LOSS_RST_EN_Pos (7UL) /*!< VHSI_LOSS_RST_EN (Bit 7) */ #define CKGEN_RCM_EN_VHSI_LOSS_RST_EN_Msk (0x80UL) /*!< VHSI_LOSS_RST_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_EN_EXT_RST_EN_Pos (8UL) /*!< EXT_RST_EN (Bit 8) */ #define CKGEN_RCM_EN_EXT_RST_EN_Msk (0x100UL) /*!< EXT_RST_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_EN_SMU_ERR_RST_EN_Pos (9UL) /*!< SMU_ERR_RST_EN (Bit 9) */ #define CKGEN_RCM_EN_SMU_ERR_RST_EN_Msk (0x200UL) /*!< SMU_ERR_RST_EN (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_EN_ECC2_ERR_RST_EN_Pos (10UL) /*!< ECC2_ERR_RST_EN (Bit 10) */ #define CKGEN_RCM_EN_ECC2_ERR_RST_EN_Msk (0x400UL) /*!< ECC2_ERR_RST_EN (Bitfield-Mask: 0x01) */ /* ====================================================== RCM_STATUS ======================================================= */ #define CKGEN_RCM_STATUS_SW_RST_INT_FLAG_Pos (0UL) /*!< SW_RST_INT_FLAG (Bit 0) */ #define CKGEN_RCM_STATUS_SW_RST_INT_FLAG_Msk (0x1UL) /*!< SW_RST_INT_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_LOCKUP_RST_INT_FLAG_Pos (1UL) /*!< LOCKUP_RST_INT_FLAG (Bit 1) */ #define CKGEN_RCM_STATUS_LOCKUP_RST_INT_FLAG_Msk (0x2UL) /*!< LOCKUP_RST_INT_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_ACK_ERR_RST_INT_FLAG_Pos (2UL) /*!< ACK_ERR_RST_INT_FLAG (Bit 2) */ #define CKGEN_RCM_STATUS_ACK_ERR_RST_INT_FLAG_Msk (0x4UL) /*!< ACK_ERR_RST_INT_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_WDG_RST_INT_FLAG_Pos (3UL) /*!< WDG_RST_INT_FLAG (Bit 3) */ #define CKGEN_RCM_STATUS_WDG_RST_INT_FLAG_Msk (0x8UL) /*!< WDG_RST_INT_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_XOSC_LOSS_RST_INT_FLAG_Pos (5UL) /*!< XOSC_LOSS_RST_INT_FLAG (Bit 5) */ #define CKGEN_RCM_STATUS_XOSC_LOSS_RST_INT_FLAG_Msk (0x20UL) /*!< XOSC_LOSS_RST_INT_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_PLL_UNLOCK_RST_INT_FLAG_Pos (6UL) /*!< PLL_UNLOCK_RST_INT_FLAG (Bit 6) */ #define CKGEN_RCM_STATUS_PLL_UNLOCK_RST_INT_FLAG_Msk (0x40UL) /*!< PLL_UNLOCK_RST_INT_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_VHSI_LOSS_RST_INT_FLAG_Pos (7UL) /*!< VHSI_LOSS_RST_INT_FLAG (Bit 7) */ #define CKGEN_RCM_STATUS_VHSI_LOSS_RST_INT_FLAG_Msk (0x80UL) /*!< VHSI_LOSS_RST_INT_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_SMU_ERR_RST_INT_FLAG_Pos (9UL) /*!< SMU_ERR_RST_INT_FLAG (Bit 9) */ #define CKGEN_RCM_STATUS_SMU_ERR_RST_INT_FLAG_Msk (0x200UL) /*!< SMU_ERR_RST_INT_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_ECC2_ERR_RST_INT_FLAG_Pos (10UL) /*!< ECC2_ERR_RST_INT_FLAG (Bit 10) */ #define CKGEN_RCM_STATUS_ECC2_ERR_RST_INT_FLAG_Msk (0x400UL) /*!< ECC2_ERR_RST_INT_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_RST_INT_STATUS_CLR_Pos (15UL) /*!< RST_INT_STATUS_CLR (Bit 15) */ #define CKGEN_RCM_STATUS_RST_INT_STATUS_CLR_Msk (0x8000UL) /*!< RST_INT_STATUS_CLR (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_POR_RST_FLAG_Pos (16UL) /*!< POR_RST_FLAG (Bit 16) */ #define CKGEN_RCM_STATUS_POR_RST_FLAG_Msk (0x10000UL) /*!< POR_RST_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_LVR_RST_FLAG_Pos (17UL) /*!< LVR_RST_FLAG (Bit 17) */ #define CKGEN_RCM_STATUS_LVR_RST_FLAG_Msk (0x20000UL) /*!< LVR_RST_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_SW_RST_FLAG_Pos (18UL) /*!< SW_RST_FLAG (Bit 18) */ #define CKGEN_RCM_STATUS_SW_RST_FLAG_Msk (0x40000UL) /*!< SW_RST_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_LOCKUP_RST_FLAG_Pos (19UL) /*!< LOCKUP_RST_FLAG (Bit 19) */ #define CKGEN_RCM_STATUS_LOCKUP_RST_FLAG_Msk (0x80000UL) /*!< LOCKUP_RST_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_ACK_ERR_RST_FLAG_Pos (20UL) /*!< ACK_ERR_RST_FLAG (Bit 20) */ #define CKGEN_RCM_STATUS_ACK_ERR_RST_FLAG_Msk (0x100000UL) /*!< ACK_ERR_RST_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_WDG_RST_FLAG_Pos (21UL) /*!< WDG_RST_FLAG (Bit 21) */ #define CKGEN_RCM_STATUS_WDG_RST_FLAG_Msk (0x200000UL) /*!< WDG_RST_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_XOSC_LOSS_RST_FLAG_Pos (23UL) /*!< XOSC_LOSS_RST_FLAG (Bit 23) */ #define CKGEN_RCM_STATUS_XOSC_LOSS_RST_FLAG_Msk (0x800000UL) /*!< XOSC_LOSS_RST_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_PLL_UNLOCK_RST_FLAG_Pos (24UL) /*!< PLL_UNLOCK_RST_FLAG (Bit 24) */ #define CKGEN_RCM_STATUS_PLL_UNLOCK_RST_FLAG_Msk (0x1000000UL) /*!< PLL_UNLOCK_RST_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_VHSI_LOSS_RST_FLAG_Pos (25UL) /*!< VHSI_LOSS_RST_FLAG (Bit 25) */ #define CKGEN_RCM_STATUS_VHSI_LOSS_RST_FLAG_Msk (0x2000000UL) /*!< VHSI_LOSS_RST_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_EXT_RST_FLAG_Pos (26UL) /*!< EXT_RST_FLAG (Bit 26) */ #define CKGEN_RCM_STATUS_EXT_RST_FLAG_Msk (0x4000000UL) /*!< EXT_RST_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_SMU_ERR_RST_FLAG_Pos (27UL) /*!< SMU_ERR_RST_FLAG (Bit 27) */ #define CKGEN_RCM_STATUS_SMU_ERR_RST_FLAG_Msk (0x8000000UL) /*!< SMU_ERR_RST_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_ECC2_ERR_RST_FLAG_Pos (28UL) /*!< ECC2_ERR_RST_FLAG (Bit 28) */ #define CKGEN_RCM_STATUS_ECC2_ERR_RST_FLAG_Msk (0x10000000UL) /*!< ECC2_ERR_RST_FLAG (Bitfield-Mask: 0x01) */ #define CKGEN_RCM_STATUS_RST_STATUS_CLR_Pos (31UL) /*!< RST_STATUS_CLR (Bit 31) */ #define CKGEN_RCM_STATUS_RST_STATUS_CLR_Msk (0x80000000UL) /*!< RST_STATUS_CLR (Bitfield-Mask: 0x01) */ /* ===================================================== PERI_SFT_RST0 ===================================================== */ #define CKGEN_PERI_SFT_RST0_SRST_UART0_Pos (0UL) /*!< SRST_UART0 (Bit 0) */ #define CKGEN_PERI_SFT_RST0_SRST_UART0_Msk (0x1UL) /*!< SRST_UART0 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_UART1_Pos (1UL) /*!< SRST_UART1 (Bit 1) */ #define CKGEN_PERI_SFT_RST0_SRST_UART1_Msk (0x2UL) /*!< SRST_UART1 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_UART2_Pos (2UL) /*!< SRST_UART2 (Bit 2) */ #define CKGEN_PERI_SFT_RST0_SRST_UART2_Msk (0x4UL) /*!< SRST_UART2 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_UART3_Pos (3UL) /*!< SRST_UART3 (Bit 3) */ #define CKGEN_PERI_SFT_RST0_SRST_UART3_Msk (0x8UL) /*!< SRST_UART3 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_SPI0_Pos (6UL) /*!< SRST_SPI0 (Bit 6) */ #define CKGEN_PERI_SFT_RST0_SRST_SPI0_Msk (0x40UL) /*!< SRST_SPI0 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_SPI1_Pos (7UL) /*!< SRST_SPI1 (Bit 7) */ #define CKGEN_PERI_SFT_RST0_SRST_SPI1_Msk (0x80UL) /*!< SRST_SPI1 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_SPI2_Pos (8UL) /*!< SRST_SPI2 (Bit 8) */ #define CKGEN_PERI_SFT_RST0_SRST_SPI2_Msk (0x100UL) /*!< SRST_SPI2 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_I2C0_Pos (9UL) /*!< SRST_I2C0 (Bit 9) */ #define CKGEN_PERI_SFT_RST0_SRST_I2C0_Msk (0x200UL) /*!< SRST_I2C0 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_PCT_Pos (11UL) /*!< SRST_PCT (Bit 11) */ #define CKGEN_PERI_SFT_RST0_SRST_PCT_Msk (0x800UL) /*!< SRST_PCT (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_PWM0_Pos (15UL) /*!< SRST_PWM0 (Bit 15) */ #define CKGEN_PERI_SFT_RST0_SRST_PWM0_Msk (0x8000UL) /*!< SRST_PWM0 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_PWM1_Pos (16UL) /*!< SRST_PWM1 (Bit 16) */ #define CKGEN_PERI_SFT_RST0_SRST_PWM1_Msk (0x10000UL) /*!< SRST_PWM1 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_PWM2_Pos (17UL) /*!< SRST_PWM2 (Bit 17) */ #define CKGEN_PERI_SFT_RST0_SRST_PWM2_Msk (0x20000UL) /*!< SRST_PWM2 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_PWM3_Pos (18UL) /*!< SRST_PWM3 (Bit 18) */ #define CKGEN_PERI_SFT_RST0_SRST_PWM3_Msk (0x40000UL) /*!< SRST_PWM3 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_PWM4_Pos (19UL) /*!< SRST_PWM4 (Bit 19) */ #define CKGEN_PERI_SFT_RST0_SRST_PWM4_Msk (0x80000UL) /*!< SRST_PWM4 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST0_SRST_PWM5_Pos (20UL) /*!< SRST_PWM5 (Bit 20) */ #define CKGEN_PERI_SFT_RST0_SRST_PWM5_Msk (0x100000UL) /*!< SRST_PWM5 (Bitfield-Mask: 0x01) */ /* ===================================================== PERI_SFT_RST1 ===================================================== */ #define CKGEN_PERI_SFT_RST1_SRST_DMA_Pos (2UL) /*!< SRST_DMA (Bit 2) */ #define CKGEN_PERI_SFT_RST1_SRST_DMA_Msk (0x4UL) /*!< SRST_DMA (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST1_SRST_GPIO_Pos (5UL) /*!< SRST_GPIO (Bit 5) */ #define CKGEN_PERI_SFT_RST1_SRST_GPIO_Msk (0x20UL) /*!< SRST_GPIO (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST1_SRST_WDG_Pos (6UL) /*!< SRST_WDG (Bit 6) */ #define CKGEN_PERI_SFT_RST1_SRST_WDG_Msk (0x40UL) /*!< SRST_WDG (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST1_SRST_EWDG_Pos (7UL) /*!< SRST_EWDG (Bit 7) */ #define CKGEN_PERI_SFT_RST1_SRST_EWDG_Msk (0x80UL) /*!< SRST_EWDG (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST1_SRST_CRC_Pos (8UL) /*!< SRST_CRC (Bit 8) */ #define CKGEN_PERI_SFT_RST1_SRST_CRC_Msk (0x100UL) /*!< SRST_CRC (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST1_SRST_CAN0_Pos (9UL) /*!< SRST_CAN0 (Bit 9) */ #define CKGEN_PERI_SFT_RST1_SRST_CAN0_Msk (0x200UL) /*!< SRST_CAN0 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST1_SRST_CAN1_Pos (10UL) /*!< SRST_CAN1 (Bit 10) */ #define CKGEN_PERI_SFT_RST1_SRST_CAN1_Msk (0x400UL) /*!< SRST_CAN1 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST1_SRST_CAN2_Pos (11UL) /*!< SRST_CAN2 (Bit 11) */ #define CKGEN_PERI_SFT_RST1_SRST_CAN2_Msk (0x800UL) /*!< SRST_CAN2 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST1_SRST_CAN3_Pos (12UL) /*!< SRST_CAN3 (Bit 12) */ #define CKGEN_PERI_SFT_RST1_SRST_CAN3_Msk (0x1000UL) /*!< SRST_CAN3 (Bitfield-Mask: 0x01) */ /* ===================================================== PERI_SFT_RST2 ===================================================== */ #define CKGEN_PERI_SFT_RST2_SRST_CTU_Pos (1UL) /*!< SRST_CTU (Bit 1) */ #define CKGEN_PERI_SFT_RST2_SRST_CTU_Msk (0x2UL) /*!< SRST_CTU (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST2_SRST_ACMP_Pos (8UL) /*!< SRST_ACMP (Bit 8) */ #define CKGEN_PERI_SFT_RST2_SRST_ACMP_Msk (0x100UL) /*!< SRST_ACMP (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST2_SRST_PDT0_Pos (9UL) /*!< SRST_PDT0 (Bit 9) */ #define CKGEN_PERI_SFT_RST2_SRST_PDT0_Msk (0x200UL) /*!< SRST_PDT0 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST2_SRST_PDT1_Pos (10UL) /*!< SRST_PDT1 (Bit 10) */ #define CKGEN_PERI_SFT_RST2_SRST_PDT1_Msk (0x400UL) /*!< SRST_PDT1 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST2_SRST_ADC0_Pos (11UL) /*!< SRST_ADC0 (Bit 11) */ #define CKGEN_PERI_SFT_RST2_SRST_ADC0_Msk (0x800UL) /*!< SRST_ADC0 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST2_SRST_ADC1_Pos (12UL) /*!< SRST_ADC1 (Bit 12) */ #define CKGEN_PERI_SFT_RST2_SRST_ADC1_Msk (0x1000UL) /*!< SRST_ADC1 (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST2_SRST_TIMER_Pos (13UL) /*!< SRST_TIMER (Bit 13) */ #define CKGEN_PERI_SFT_RST2_SRST_TIMER_Msk (0x2000UL) /*!< SRST_TIMER (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_SFT_RST2_SRST_EIO_Pos (14UL) /*!< SRST_EIO (Bit 14) */ #define CKGEN_PERI_SFT_RST2_SRST_EIO_Msk (0x4000UL) /*!< SRST_EIO (Bitfield-Mask: 0x01) */ /* ======================================================= CLK_DIV1 ======================================================== */ #define CKGEN_CLK_DIV1_SPLL_DIV1_Pos (0UL) /*!< SPLL_DIV1 (Bit 0) */ #define CKGEN_CLK_DIV1_SPLL_DIV1_Msk (0x3fUL) /*!< SPLL_DIV1 (Bitfield-Mask: 0x3f) */ #define CKGEN_CLK_DIV1_VHSI_DIV1_Pos (6UL) /*!< VHSI_DIV1 (Bit 6) */ #define CKGEN_CLK_DIV1_VHSI_DIV1_Msk (0xfc0UL) /*!< VHSI_DIV1 (Bitfield-Mask: 0x3f) */ #define CKGEN_CLK_DIV1_HSI_DIV1_Pos (12UL) /*!< HSI_DIV1 (Bit 12) */ #define CKGEN_CLK_DIV1_HSI_DIV1_Msk (0x3f000UL) /*!< HSI_DIV1 (Bitfield-Mask: 0x3f) */ #define CKGEN_CLK_DIV1_HSE_DIV1_Pos (18UL) /*!< HSE_DIV1 (Bit 18) */ #define CKGEN_CLK_DIV1_HSE_DIV1_Msk (0xfc0000UL) /*!< HSE_DIV1 (Bitfield-Mask: 0x3f) */ /* ======================================================= CLK_DIV2 ======================================================== */ #define CKGEN_CLK_DIV2_SPLL_DIV2_Pos (0UL) /*!< SPLL_DIV2 (Bit 0) */ #define CKGEN_CLK_DIV2_SPLL_DIV2_Msk (0x3fUL) /*!< SPLL_DIV2 (Bitfield-Mask: 0x3f) */ #define CKGEN_CLK_DIV2_VHSI_DIV2_Pos (6UL) /*!< VHSI_DIV2 (Bit 6) */ #define CKGEN_CLK_DIV2_VHSI_DIV2_Msk (0xfc0UL) /*!< VHSI_DIV2 (Bitfield-Mask: 0x3f) */ #define CKGEN_CLK_DIV2_HSI_DIV2_Pos (12UL) /*!< HSI_DIV2 (Bit 12) */ #define CKGEN_CLK_DIV2_HSI_DIV2_Msk (0x3f000UL) /*!< HSI_DIV2 (Bitfield-Mask: 0x3f) */ #define CKGEN_CLK_DIV2_HSE_DIV2_Pos (18UL) /*!< HSE_DIV2 (Bit 18) */ #define CKGEN_CLK_DIV2_HSE_DIV2_Msk (0xfc0000UL) /*!< HSE_DIV2 (Bitfield-Mask: 0x3f) */ /* ===================================================== PERI_CLK_MUX0 ===================================================== */ #define CKGEN_PERI_CLK_MUX0_I2C0_MUX_Pos (0UL) /*!< I2C0_MUX (Bit 0) */ #define CKGEN_PERI_CLK_MUX0_I2C0_MUX_Msk (0x7UL) /*!< I2C0_MUX (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_MUX0_TIMER_MUX_Pos (8UL) /*!< TIMER_MUX (Bit 8) */ #define CKGEN_PERI_CLK_MUX0_TIMER_MUX_Msk (0x700UL) /*!< TIMER_MUX (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_MUX0_SPI0_MUX_Pos (12UL) /*!< SPI0_MUX (Bit 12) */ #define CKGEN_PERI_CLK_MUX0_SPI0_MUX_Msk (0x7000UL) /*!< SPI0_MUX (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_MUX0_SPI1_MUX_Pos (16UL) /*!< SPI1_MUX (Bit 16) */ #define CKGEN_PERI_CLK_MUX0_SPI1_MUX_Msk (0x70000UL) /*!< SPI1_MUX (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_MUX0_SPI2_MUX_Pos (20UL) /*!< SPI2_MUX (Bit 20) */ #define CKGEN_PERI_CLK_MUX0_SPI2_MUX_Msk (0x700000UL) /*!< SPI2_MUX (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_MUX0_ADC0_MUX_Pos (24UL) /*!< ADC0_MUX (Bit 24) */ #define CKGEN_PERI_CLK_MUX0_ADC0_MUX_Msk (0x7000000UL) /*!< ADC0_MUX (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_MUX0_ADC1_MUX_Pos (28UL) /*!< ADC1_MUX (Bit 28) */ #define CKGEN_PERI_CLK_MUX0_ADC1_MUX_Msk (0x70000000UL) /*!< ADC1_MUX (Bitfield-Mask: 0x07) */ /* ===================================================== PERI_CLK_MUX1 ===================================================== */ #define CKGEN_PERI_CLK_MUX1_CAN0_MUX_Pos (0UL) /*!< CAN0_MUX (Bit 0) */ #define CKGEN_PERI_CLK_MUX1_CAN0_MUX_Msk (0x3UL) /*!< CAN0_MUX (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX1_CAN1_MUX_Pos (2UL) /*!< CAN1_MUX (Bit 2) */ #define CKGEN_PERI_CLK_MUX1_CAN1_MUX_Msk (0xcUL) /*!< CAN1_MUX (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX1_CAN2_MUX_Pos (4UL) /*!< CAN2_MUX (Bit 4) */ #define CKGEN_PERI_CLK_MUX1_CAN2_MUX_Msk (0x30UL) /*!< CAN2_MUX (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX1_CAN3_MUX_Pos (6UL) /*!< CAN3_MUX (Bit 6) */ #define CKGEN_PERI_CLK_MUX1_CAN3_MUX_Msk (0xc0UL) /*!< CAN3_MUX (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX1_PCT_MUX_Pos (12UL) /*!< PCT_MUX (Bit 12) */ #define CKGEN_PERI_CLK_MUX1_PCT_MUX_Msk (0x7000UL) /*!< PCT_MUX (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_MUX1_EIO_MUX_Pos (16UL) /*!< EIO_MUX (Bit 16) */ #define CKGEN_PERI_CLK_MUX1_EIO_MUX_Msk (0x70000UL) /*!< EIO_MUX (Bitfield-Mask: 0x07) */ /* ===================================================== PERI_CLK_MUX2 ===================================================== */ #define CKGEN_PERI_CLK_MUX2_UART0_MUX_Pos (0UL) /*!< UART0_MUX (Bit 0) */ #define CKGEN_PERI_CLK_MUX2_UART0_MUX_Msk (0x7UL) /*!< UART0_MUX (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_MUX2_UART1_MUX_Pos (4UL) /*!< UART1_MUX (Bit 4) */ #define CKGEN_PERI_CLK_MUX2_UART1_MUX_Msk (0x70UL) /*!< UART1_MUX (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_MUX2_UART2_MUX_Pos (8UL) /*!< UART2_MUX (Bit 8) */ #define CKGEN_PERI_CLK_MUX2_UART2_MUX_Msk (0x700UL) /*!< UART2_MUX (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_MUX2_UART3_MUX_Pos (12UL) /*!< UART3_MUX (Bit 12) */ #define CKGEN_PERI_CLK_MUX2_UART3_MUX_Msk (0x7000UL) /*!< UART3_MUX (Bitfield-Mask: 0x07) */ /* ===================================================== PERI_CLK_MUX3 ===================================================== */ #define CKGEN_PERI_CLK_MUX3_PWM0_EXT_Pos (0UL) /*!< PWM0_EXT (Bit 0) */ #define CKGEN_PERI_CLK_MUX3_PWM0_EXT_Msk (0x3UL) /*!< PWM0_EXT (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX3_PWM0_INT_Pos (2UL) /*!< PWM0_INT (Bit 2) */ #define CKGEN_PERI_CLK_MUX3_PWM0_INT_Msk (0xcUL) /*!< PWM0_INT (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX3_PWM0_EXT_IN_Pos (4UL) /*!< PWM0_EXT_IN (Bit 4) */ #define CKGEN_PERI_CLK_MUX3_PWM0_EXT_IN_Msk (0x10UL) /*!< PWM0_EXT_IN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_MUX3_PWM1_EXT_Pos (5UL) /*!< PWM1_EXT (Bit 5) */ #define CKGEN_PERI_CLK_MUX3_PWM1_EXT_Msk (0x60UL) /*!< PWM1_EXT (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX3_PWM1_INT_Pos (7UL) /*!< PWM1_INT (Bit 7) */ #define CKGEN_PERI_CLK_MUX3_PWM1_INT_Msk (0x180UL) /*!< PWM1_INT (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX3_PWM1_EXT_IN_Pos (9UL) /*!< PWM1_EXT_IN (Bit 9) */ #define CKGEN_PERI_CLK_MUX3_PWM1_EXT_IN_Msk (0x200UL) /*!< PWM1_EXT_IN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_MUX3_PWM2_EXT_Pos (10UL) /*!< PWM2_EXT (Bit 10) */ #define CKGEN_PERI_CLK_MUX3_PWM2_EXT_Msk (0xc00UL) /*!< PWM2_EXT (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX3_PWM2_INT_Pos (12UL) /*!< PWM2_INT (Bit 12) */ #define CKGEN_PERI_CLK_MUX3_PWM2_INT_Msk (0x3000UL) /*!< PWM2_INT (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX3_PWM2_EXT_IN_Pos (14UL) /*!< PWM2_EXT_IN (Bit 14) */ #define CKGEN_PERI_CLK_MUX3_PWM2_EXT_IN_Msk (0x4000UL) /*!< PWM2_EXT_IN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_MUX3_PWM3_EXT_Pos (15UL) /*!< PWM3_EXT (Bit 15) */ #define CKGEN_PERI_CLK_MUX3_PWM3_EXT_Msk (0x18000UL) /*!< PWM3_EXT (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX3_PWM3_INT_Pos (17UL) /*!< PWM3_INT (Bit 17) */ #define CKGEN_PERI_CLK_MUX3_PWM3_INT_Msk (0x60000UL) /*!< PWM3_INT (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX3_PWM3_EXT_IN_Pos (19UL) /*!< PWM3_EXT_IN (Bit 19) */ #define CKGEN_PERI_CLK_MUX3_PWM3_EXT_IN_Msk (0x80000UL) /*!< PWM3_EXT_IN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_MUX3_PWM4_EXT_Pos (20UL) /*!< PWM4_EXT (Bit 20) */ #define CKGEN_PERI_CLK_MUX3_PWM4_EXT_Msk (0x300000UL) /*!< PWM4_EXT (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX3_PWM4_INT_Pos (22UL) /*!< PWM4_INT (Bit 22) */ #define CKGEN_PERI_CLK_MUX3_PWM4_INT_Msk (0xc00000UL) /*!< PWM4_INT (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX3_PWM4_EXT_IN_Pos (24UL) /*!< PWM4_EXT_IN (Bit 24) */ #define CKGEN_PERI_CLK_MUX3_PWM4_EXT_IN_Msk (0x1000000UL) /*!< PWM4_EXT_IN (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_MUX3_PWM5_EXT_Pos (25UL) /*!< PWM5_EXT (Bit 25) */ #define CKGEN_PERI_CLK_MUX3_PWM5_EXT_Msk (0x6000000UL) /*!< PWM5_EXT (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX3_PWM5_INT_Pos (27UL) /*!< PWM5_INT (Bit 27) */ #define CKGEN_PERI_CLK_MUX3_PWM5_INT_Msk (0x18000000UL) /*!< PWM5_INT (Bitfield-Mask: 0x03) */ #define CKGEN_PERI_CLK_MUX3_PWM5_EXT_IN_Pos (29UL) /*!< PWM5_EXT_IN (Bit 29) */ #define CKGEN_PERI_CLK_MUX3_PWM5_EXT_IN_Msk (0x20000000UL) /*!< PWM5_EXT_IN (Bitfield-Mask: 0x01) */ /* ====================================================== CLK_OUT_CFG ====================================================== */ #define CKGEN_CLK_OUT_CFG_MUX1_Pos (0UL) /*!< MUX1 (Bit 0) */ #define CKGEN_CLK_OUT_CFG_MUX1_Msk (0x7UL) /*!< MUX1 (Bitfield-Mask: 0x07) */ #define CKGEN_CLK_OUT_CFG_MUX2_Pos (4UL) /*!< MUX2 (Bit 4) */ #define CKGEN_CLK_OUT_CFG_MUX2_Msk (0xf0UL) /*!< MUX2 (Bitfield-Mask: 0x0f) */ #define CKGEN_CLK_OUT_CFG_DIV_Pos (8UL) /*!< DIV (Bit 8) */ #define CKGEN_CLK_OUT_CFG_DIV_Msk (0x700UL) /*!< DIV (Bitfield-Mask: 0x07) */ #define CKGEN_CLK_OUT_CFG_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */ #define CKGEN_CLK_OUT_CFG_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ /* ===================================================== PERI_CLK_DIV ====================================================== */ #define CKGEN_PERI_CLK_DIV_CAN0_DIV_Pos (0UL) /*!< CAN0_DIV (Bit 0) */ #define CKGEN_PERI_CLK_DIV_CAN0_DIV_Msk (0x1UL) /*!< CAN0_DIV (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_DIV_CAN1_DIV_Pos (1UL) /*!< CAN1_DIV (Bit 1) */ #define CKGEN_PERI_CLK_DIV_CAN1_DIV_Msk (0x2UL) /*!< CAN1_DIV (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_DIV_CAN2_DIV_Pos (2UL) /*!< CAN2_DIV (Bit 2) */ #define CKGEN_PERI_CLK_DIV_CAN2_DIV_Msk (0x4UL) /*!< CAN2_DIV (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_DIV_CAN3_DIV_Pos (3UL) /*!< CAN3_DIV (Bit 3) */ #define CKGEN_PERI_CLK_DIV_CAN3_DIV_Msk (0x8UL) /*!< CAN3_DIV (Bitfield-Mask: 0x01) */ #define CKGEN_PERI_CLK_DIV_CAN0_TS_DIV_Pos (6UL) /*!< CAN0_TS_DIV (Bit 6) */ #define CKGEN_PERI_CLK_DIV_CAN0_TS_DIV_Msk (0x1c0UL) /*!< CAN0_TS_DIV (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_DIV_CAN1_TS_DIV_Pos (9UL) /*!< CAN1_TS_DIV (Bit 9) */ #define CKGEN_PERI_CLK_DIV_CAN1_TS_DIV_Msk (0xe00UL) /*!< CAN1_TS_DIV (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_DIV_CAN2_TS_DIV_Pos (12UL) /*!< CAN2_TS_DIV (Bit 12) */ #define CKGEN_PERI_CLK_DIV_CAN2_TS_DIV_Msk (0x7000UL) /*!< CAN2_TS_DIV (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_DIV_CAN3_TS_DIV_Pos (15UL) /*!< CAN3_TS_DIV (Bit 15) */ #define CKGEN_PERI_CLK_DIV_CAN3_TS_DIV_Msk (0x38000UL) /*!< CAN3_TS_DIV (Bitfield-Mask: 0x07) */ #define CKGEN_PERI_CLK_DIV_PCT_DIV_Pos (24UL) /*!< PCT_DIV (Bit 24) */ #define CKGEN_PERI_CLK_DIV_PCT_DIV_Msk (0xf000000UL) /*!< PCT_DIV (Bitfield-Mask: 0x0f) */ #define CKGEN_PERI_CLK_DIV_TPIU_DIV_Pos (28UL) /*!< TPIU_DIV (Bit 28) */ #define CKGEN_PERI_CLK_DIV_TPIU_DIV_Msk (0xf0000000UL) /*!< TPIU_DIV (Bitfield-Mask: 0x0f) */ /* =========================================================================================================================== */ /* ================ PBR ================ */ /* =========================================================================================================================== */ /* ======================================================= MPR_CORE ======================================================== */ #define PBR_MPR_CORE_MPL_Pos (0UL) /*!< MPL (Bit 0) */ #define PBR_MPR_CORE_MPL_Msk (0x1UL) /*!< MPL (Bitfield-Mask: 0x01) */ #define PBR_MPR_CORE_MTW_Pos (1UL) /*!< MTW (Bit 1) */ #define PBR_MPR_CORE_MTW_Msk (0x2UL) /*!< MTW (Bitfield-Mask: 0x01) */ #define PBR_MPR_CORE_MTR_Pos (2UL) /*!< MTR (Bit 2) */ #define PBR_MPR_CORE_MTR_Msk (0x4UL) /*!< MTR (Bitfield-Mask: 0x01) */ /* ======================================================= MPR_DEBUG ======================================================= */ #define PBR_MPR_DEBUG_MPL_Pos (0UL) /*!< MPL (Bit 0) */ #define PBR_MPR_DEBUG_MPL_Msk (0x1UL) /*!< MPL (Bitfield-Mask: 0x01) */ #define PBR_MPR_DEBUG_MTW_Pos (1UL) /*!< MTW (Bit 1) */ #define PBR_MPR_DEBUG_MTW_Msk (0x2UL) /*!< MTW (Bitfield-Mask: 0x01) */ #define PBR_MPR_DEBUG_MTR_Pos (2UL) /*!< MTR (Bit 2) */ #define PBR_MPR_DEBUG_MTR_Msk (0x4UL) /*!< MTR (Bitfield-Mask: 0x01) */ /* ======================================================== MPR_DMA ======================================================== */ #define PBR_MPR_DMA_MPL_Pos (0UL) /*!< MPL (Bit 0) */ #define PBR_MPR_DMA_MPL_Msk (0x1UL) /*!< MPL (Bitfield-Mask: 0x01) */ #define PBR_MPR_DMA_MTW_Pos (1UL) /*!< MTW (Bit 1) */ #define PBR_MPR_DMA_MTW_Msk (0x2UL) /*!< MTW (Bitfield-Mask: 0x01) */ #define PBR_MPR_DMA_MTR_Pos (2UL) /*!< MTR (Bit 2) */ #define PBR_MPR_DMA_MTR_Msk (0x4UL) /*!< MTR (Bitfield-Mask: 0x01) */ /* ========================================================= PACRA ========================================================= */ #define PBR_PACRA_PWM0_TP_Pos (0UL) /*!< PWM0_TP (Bit 0) */ #define PBR_PACRA_PWM0_TP_Msk (0x1UL) /*!< PWM0_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM0_WP_Pos (1UL) /*!< PWM0_WP (Bit 1) */ #define PBR_PACRA_PWM0_WP_Msk (0x2UL) /*!< PWM0_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM0_SP_Pos (2UL) /*!< PWM0_SP (Bit 2) */ #define PBR_PACRA_PWM0_SP_Msk (0x4UL) /*!< PWM0_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM1_TP_Pos (4UL) /*!< PWM1_TP (Bit 4) */ #define PBR_PACRA_PWM1_TP_Msk (0x10UL) /*!< PWM1_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM1_WP_Pos (5UL) /*!< PWM1_WP (Bit 5) */ #define PBR_PACRA_PWM1_WP_Msk (0x20UL) /*!< PWM1_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM1_SP_Pos (6UL) /*!< PWM1_SP (Bit 6) */ #define PBR_PACRA_PWM1_SP_Msk (0x40UL) /*!< PWM1_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM2_TP_Pos (8UL) /*!< PWM2_TP (Bit 8) */ #define PBR_PACRA_PWM2_TP_Msk (0x100UL) /*!< PWM2_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM2_WP_Pos (9UL) /*!< PWM2_WP (Bit 9) */ #define PBR_PACRA_PWM2_WP_Msk (0x200UL) /*!< PWM2_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM2_SP_Pos (10UL) /*!< PWM2_SP (Bit 10) */ #define PBR_PACRA_PWM2_SP_Msk (0x400UL) /*!< PWM2_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM3_TP_Pos (12UL) /*!< PWM3_TP (Bit 12) */ #define PBR_PACRA_PWM3_TP_Msk (0x1000UL) /*!< PWM3_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM3_WP_Pos (13UL) /*!< PWM3_WP (Bit 13) */ #define PBR_PACRA_PWM3_WP_Msk (0x2000UL) /*!< PWM3_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM3_SP_Pos (14UL) /*!< PWM3_SP (Bit 14) */ #define PBR_PACRA_PWM3_SP_Msk (0x4000UL) /*!< PWM3_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM4_TP_Pos (16UL) /*!< PWM4_TP (Bit 16) */ #define PBR_PACRA_PWM4_TP_Msk (0x10000UL) /*!< PWM4_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM4_WP_Pos (17UL) /*!< PWM4_WP (Bit 17) */ #define PBR_PACRA_PWM4_WP_Msk (0x20000UL) /*!< PWM4_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM4_SP_Pos (18UL) /*!< PWM4_SP (Bit 18) */ #define PBR_PACRA_PWM4_SP_Msk (0x40000UL) /*!< PWM4_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM5_TP_Pos (20UL) /*!< PWM5_TP (Bit 20) */ #define PBR_PACRA_PWM5_TP_Msk (0x100000UL) /*!< PWM5_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM5_WP_Pos (21UL) /*!< PWM5_WP (Bit 21) */ #define PBR_PACRA_PWM5_WP_Msk (0x200000UL) /*!< PWM5_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRA_PWM5_SP_Pos (22UL) /*!< PWM5_SP (Bit 22) */ #define PBR_PACRA_PWM5_SP_Msk (0x400000UL) /*!< PWM5_SP (Bitfield-Mask: 0x01) */ /* ========================================================= PACRB ========================================================= */ #define PBR_PACRB_CRC_TP_Pos (0UL) /*!< CRC_TP (Bit 0) */ #define PBR_PACRB_CRC_TP_Msk (0x1UL) /*!< CRC_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_CRC_WP_Pos (1UL) /*!< CRC_WP (Bit 1) */ #define PBR_PACRB_CRC_WP_Msk (0x2UL) /*!< CRC_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_CRC_SP_Pos (2UL) /*!< CRC_SP (Bit 2) */ #define PBR_PACRB_CRC_SP_Msk (0x4UL) /*!< CRC_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_GPIO_TP_Pos (4UL) /*!< GPIO_TP (Bit 4) */ #define PBR_PACRB_GPIO_TP_Msk (0x10UL) /*!< GPIO_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_GPIO_WP_Pos (5UL) /*!< GPIO_WP (Bit 5) */ #define PBR_PACRB_GPIO_WP_Msk (0x20UL) /*!< GPIO_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_GPIO_SP_Pos (6UL) /*!< GPIO_SP (Bit 6) */ #define PBR_PACRB_GPIO_SP_Msk (0x40UL) /*!< GPIO_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_PDT0_TP_Pos (8UL) /*!< PDT0_TP (Bit 8) */ #define PBR_PACRB_PDT0_TP_Msk (0x100UL) /*!< PDT0_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_PDT0_WP_Pos (9UL) /*!< PDT0_WP (Bit 9) */ #define PBR_PACRB_PDT0_WP_Msk (0x200UL) /*!< PDT0_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_PDT0_SP_Pos (10UL) /*!< PDT0_SP (Bit 10) */ #define PBR_PACRB_PDT0_SP_Msk (0x400UL) /*!< PDT0_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_PDT1_TP_Pos (12UL) /*!< PDT1_TP (Bit 12) */ #define PBR_PACRB_PDT1_TP_Msk (0x1000UL) /*!< PDT1_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_PDT1_WP_Pos (13UL) /*!< PDT1_WP (Bit 13) */ #define PBR_PACRB_PDT1_WP_Msk (0x2000UL) /*!< PDT1_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_PDT1_SP_Pos (14UL) /*!< PDT1_SP (Bit 14) */ #define PBR_PACRB_PDT1_SP_Msk (0x4000UL) /*!< PDT1_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_MPU_TP_Pos (16UL) /*!< MPU_TP (Bit 16) */ #define PBR_PACRB_MPU_TP_Msk (0x10000UL) /*!< MPU_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_MPU_WP_Pos (17UL) /*!< MPU_WP (Bit 17) */ #define PBR_PACRB_MPU_WP_Msk (0x20000UL) /*!< MPU_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_MPU_SP_Pos (18UL) /*!< MPU_SP (Bit 18) */ #define PBR_PACRB_MPU_SP_Msk (0x40000UL) /*!< MPU_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_EIM_TP_Pos (20UL) /*!< EIM_TP (Bit 20) */ #define PBR_PACRB_EIM_TP_Msk (0x100000UL) /*!< EIM_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_EIM_WP_Pos (21UL) /*!< EIM_WP (Bit 21) */ #define PBR_PACRB_EIM_WP_Msk (0x200000UL) /*!< EIM_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_EIM_SP_Pos (22UL) /*!< EIM_SP (Bit 22) */ #define PBR_PACRB_EIM_SP_Msk (0x400000UL) /*!< EIM_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_SMU_TP_Pos (24UL) /*!< SMU_TP (Bit 24) */ #define PBR_PACRB_SMU_TP_Msk (0x1000000UL) /*!< SMU_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_SMU_WP_Pos (25UL) /*!< SMU_WP (Bit 25) */ #define PBR_PACRB_SMU_WP_Msk (0x2000000UL) /*!< SMU_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRB_SMU_SP_Pos (26UL) /*!< SMU_SP (Bit 26) */ #define PBR_PACRB_SMU_SP_Msk (0x4000000UL) /*!< SMU_SP (Bitfield-Mask: 0x01) */ /* ========================================================= PACRC ========================================================= */ #define PBR_PACRC_CLK_TP_Pos (0UL) /*!< CLK_TP (Bit 0) */ #define PBR_PACRC_CLK_TP_Msk (0x1UL) /*!< CLK_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_CLK_WP_Pos (1UL) /*!< CLK_WP (Bit 1) */ #define PBR_PACRC_CLK_WP_Msk (0x2UL) /*!< CLK_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_CLK_SP_Pos (2UL) /*!< CLK_SP (Bit 2) */ #define PBR_PACRC_CLK_SP_Msk (0x4UL) /*!< CLK_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_FLASH_TP_Pos (8UL) /*!< FLASH_TP (Bit 8) */ #define PBR_PACRC_FLASH_TP_Msk (0x100UL) /*!< FLASH_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_FLASH_WP_Pos (9UL) /*!< FLASH_WP (Bit 9) */ #define PBR_PACRC_FLASH_WP_Msk (0x200UL) /*!< FLASH_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_FLASH_SP_Pos (10UL) /*!< FLASH_SP (Bit 10) */ #define PBR_PACRC_FLASH_SP_Msk (0x400UL) /*!< FLASH_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_ADC0_TP_Pos (12UL) /*!< ADC0_TP (Bit 12) */ #define PBR_PACRC_ADC0_TP_Msk (0x1000UL) /*!< ADC0_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_ADC0_WP_Pos (13UL) /*!< ADC0_WP (Bit 13) */ #define PBR_PACRC_ADC0_WP_Msk (0x2000UL) /*!< ADC0_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_ADC0_SP_Pos (14UL) /*!< ADC0_SP (Bit 14) */ #define PBR_PACRC_ADC0_SP_Msk (0x4000UL) /*!< ADC0_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_ADC1_TP_Pos (16UL) /*!< ADC1_TP (Bit 16) */ #define PBR_PACRC_ADC1_TP_Msk (0x10000UL) /*!< ADC1_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_ADC1_WP_Pos (17UL) /*!< ADC1_WP (Bit 17) */ #define PBR_PACRC_ADC1_WP_Msk (0x20000UL) /*!< ADC1_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_ADC1_SP_Pos (18UL) /*!< ADC1_SP (Bit 18) */ #define PBR_PACRC_ADC1_SP_Msk (0x40000UL) /*!< ADC1_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_ACMP_TP_Pos (20UL) /*!< ACMP_TP (Bit 20) */ #define PBR_PACRC_ACMP_TP_Msk (0x100000UL) /*!< ACMP_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_ACMP_WP_Pos (21UL) /*!< ACMP_WP (Bit 21) */ #define PBR_PACRC_ACMP_WP_Msk (0x200000UL) /*!< ACMP_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_ACMP_SP_Pos (22UL) /*!< ACMP_SP (Bit 22) */ #define PBR_PACRC_ACMP_SP_Msk (0x400000UL) /*!< ACMP_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_CTU_TP_Pos (24UL) /*!< CTU_TP (Bit 24) */ #define PBR_PACRC_CTU_TP_Msk (0x1000000UL) /*!< CTU_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_CTU_WP_Pos (25UL) /*!< CTU_WP (Bit 25) */ #define PBR_PACRC_CTU_WP_Msk (0x2000000UL) /*!< CTU_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_CTU_SP_Pos (26UL) /*!< CTU_SP (Bit 26) */ #define PBR_PACRC_CTU_SP_Msk (0x4000000UL) /*!< CTU_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_CAN0_TP_Pos (28UL) /*!< CAN0_TP (Bit 28) */ #define PBR_PACRC_CAN0_TP_Msk (0x10000000UL) /*!< CAN0_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_CAN0_WP_Pos (29UL) /*!< CAN0_WP (Bit 29) */ #define PBR_PACRC_CAN0_WP_Msk (0x20000000UL) /*!< CAN0_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRC_CAN0_SP_Pos (30UL) /*!< CAN0_SP (Bit 30) */ #define PBR_PACRC_CAN0_SP_Msk (0x40000000UL) /*!< CAN0_SP (Bitfield-Mask: 0x01) */ /* ========================================================= PACRD ========================================================= */ #define PBR_PACRD_CAN1_TP_Pos (0UL) /*!< CAN1_TP (Bit 0) */ #define PBR_PACRD_CAN1_TP_Msk (0x1UL) /*!< CAN1_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_CAN1_WP_Pos (1UL) /*!< CAN1_WP (Bit 1) */ #define PBR_PACRD_CAN1_WP_Msk (0x2UL) /*!< CAN1_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_CAN1_SP_Pos (2UL) /*!< CAN1_SP (Bit 2) */ #define PBR_PACRD_CAN1_SP_Msk (0x4UL) /*!< CAN1_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_CAN2_TP_Pos (4UL) /*!< CAN2_TP (Bit 4) */ #define PBR_PACRD_CAN2_TP_Msk (0x10UL) /*!< CAN2_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_CAN2_WP_Pos (5UL) /*!< CAN2_WP (Bit 5) */ #define PBR_PACRD_CAN2_WP_Msk (0x20UL) /*!< CAN2_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_CAN2_SP_Pos (6UL) /*!< CAN2_SP (Bit 6) */ #define PBR_PACRD_CAN2_SP_Msk (0x40UL) /*!< CAN2_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_CAN3_TP_Pos (8UL) /*!< CAN3_TP (Bit 8) */ #define PBR_PACRD_CAN3_TP_Msk (0x100UL) /*!< CAN3_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_CAN3_WP_Pos (9UL) /*!< CAN3_WP (Bit 9) */ #define PBR_PACRD_CAN3_WP_Msk (0x200UL) /*!< CAN3_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_CAN3_SP_Pos (10UL) /*!< CAN3_SP (Bit 10) */ #define PBR_PACRD_CAN3_SP_Msk (0x400UL) /*!< CAN3_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_SPM_TP_Pos (20UL) /*!< SPM_TP (Bit 20) */ #define PBR_PACRD_SPM_TP_Msk (0x100000UL) /*!< SPM_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_SPM_WP_Pos (21UL) /*!< SPM_WP (Bit 21) */ #define PBR_PACRD_SPM_WP_Msk (0x200000UL) /*!< SPM_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_SPM_SP_Pos (22UL) /*!< SPM_SP (Bit 22) */ #define PBR_PACRD_SPM_SP_Msk (0x400000UL) /*!< SPM_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_RTC_TP_Pos (24UL) /*!< RTC_TP (Bit 24) */ #define PBR_PACRD_RTC_TP_Msk (0x1000000UL) /*!< RTC_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_RTC_WP_Pos (25UL) /*!< RTC_WP (Bit 25) */ #define PBR_PACRD_RTC_WP_Msk (0x2000000UL) /*!< RTC_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_RTC_SP_Pos (26UL) /*!< RTC_SP (Bit 26) */ #define PBR_PACRD_RTC_SP_Msk (0x4000000UL) /*!< RTC_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_EIO_TP_Pos (28UL) /*!< EIO_TP (Bit 28) */ #define PBR_PACRD_EIO_TP_Msk (0x10000000UL) /*!< EIO_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_EIO_WP_Pos (29UL) /*!< EIO_WP (Bit 29) */ #define PBR_PACRD_EIO_WP_Msk (0x20000000UL) /*!< EIO_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRD_EIO_SP_Pos (30UL) /*!< EIO_SP (Bit 30) */ #define PBR_PACRD_EIO_SP_Msk (0x40000000UL) /*!< EIO_SP (Bitfield-Mask: 0x01) */ /* ========================================================= PACRE ========================================================= */ #define PBR_PACRE_WDG_TP_Pos (0UL) /*!< WDG_TP (Bit 0) */ #define PBR_PACRE_WDG_TP_Msk (0x1UL) /*!< WDG_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_WDG_WP_Pos (1UL) /*!< WDG_WP (Bit 1) */ #define PBR_PACRE_WDG_WP_Msk (0x2UL) /*!< WDG_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_WDG_SP_Pos (2UL) /*!< WDG_SP (Bit 2) */ #define PBR_PACRE_WDG_SP_Msk (0x4UL) /*!< WDG_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_EWDG_TP_Pos (4UL) /*!< EWDG_TP (Bit 4) */ #define PBR_PACRE_EWDG_TP_Msk (0x10UL) /*!< EWDG_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_EWDG_WP_Pos (5UL) /*!< EWDG_WP (Bit 5) */ #define PBR_PACRE_EWDG_WP_Msk (0x20UL) /*!< EWDG_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_EWDG_SP_Pos (6UL) /*!< EWDG_SP (Bit 6) */ #define PBR_PACRE_EWDG_SP_Msk (0x40UL) /*!< EWDG_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_SPI0_TP_Pos (8UL) /*!< SPI0_TP (Bit 8) */ #define PBR_PACRE_SPI0_TP_Msk (0x100UL) /*!< SPI0_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_SPI0_WP_Pos (9UL) /*!< SPI0_WP (Bit 9) */ #define PBR_PACRE_SPI0_WP_Msk (0x200UL) /*!< SPI0_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_SPI0_SP_Pos (10UL) /*!< SPI0_SP (Bit 10) */ #define PBR_PACRE_SPI0_SP_Msk (0x400UL) /*!< SPI0_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_SPI1_TP_Pos (12UL) /*!< SPI1_TP (Bit 12) */ #define PBR_PACRE_SPI1_TP_Msk (0x1000UL) /*!< SPI1_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_SPI1_WP_Pos (13UL) /*!< SPI1_WP (Bit 13) */ #define PBR_PACRE_SPI1_WP_Msk (0x2000UL) /*!< SPI1_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_SPI1_SP_Pos (14UL) /*!< SPI1_SP (Bit 14) */ #define PBR_PACRE_SPI1_SP_Msk (0x4000UL) /*!< SPI1_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_SPI2_TP_Pos (16UL) /*!< SPI2_TP (Bit 16) */ #define PBR_PACRE_SPI2_TP_Msk (0x10000UL) /*!< SPI2_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_SPI2_WP_Pos (17UL) /*!< SPI2_WP (Bit 17) */ #define PBR_PACRE_SPI2_WP_Msk (0x20000UL) /*!< SPI2_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_SPI2_SP_Pos (18UL) /*!< SPI2_SP (Bit 18) */ #define PBR_PACRE_SPI2_SP_Msk (0x40000UL) /*!< SPI2_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_I2C0_TP_Pos (24UL) /*!< I2C0_TP (Bit 24) */ #define PBR_PACRE_I2C0_TP_Msk (0x1000000UL) /*!< I2C0_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_I2C0_WP_Pos (25UL) /*!< I2C0_WP (Bit 25) */ #define PBR_PACRE_I2C0_WP_Msk (0x2000000UL) /*!< I2C0_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRE_I2C0_SP_Pos (26UL) /*!< I2C0_SP (Bit 26) */ #define PBR_PACRE_I2C0_SP_Msk (0x4000000UL) /*!< I2C0_SP (Bitfield-Mask: 0x01) */ /* ========================================================= PACRF ========================================================= */ #define PBR_PACRF_TIMER_TP_Pos (0UL) /*!< TIMER_TP (Bit 0) */ #define PBR_PACRF_TIMER_TP_Msk (0x1UL) /*!< TIMER_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_TIMER_WP_Pos (1UL) /*!< TIMER_WP (Bit 1) */ #define PBR_PACRF_TIMER_WP_Msk (0x2UL) /*!< TIMER_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_TIMER_SP_Pos (2UL) /*!< TIMER_SP (Bit 2) */ #define PBR_PACRF_TIMER_SP_Msk (0x4UL) /*!< TIMER_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_DMA_TP_Pos (4UL) /*!< DMA_TP (Bit 4) */ #define PBR_PACRF_DMA_TP_Msk (0x10UL) /*!< DMA_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_DMA_WP_Pos (5UL) /*!< DMA_WP (Bit 5) */ #define PBR_PACRF_DMA_WP_Msk (0x20UL) /*!< DMA_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_DMA_SP_Pos (6UL) /*!< DMA_SP (Bit 6) */ #define PBR_PACRF_DMA_SP_Msk (0x40UL) /*!< DMA_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_UART0_TP_Pos (8UL) /*!< UART0_TP (Bit 8) */ #define PBR_PACRF_UART0_TP_Msk (0x100UL) /*!< UART0_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_UART0_WP_Pos (9UL) /*!< UART0_WP (Bit 9) */ #define PBR_PACRF_UART0_WP_Msk (0x200UL) /*!< UART0_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_UART0_SP_Pos (10UL) /*!< UART0_SP (Bit 10) */ #define PBR_PACRF_UART0_SP_Msk (0x400UL) /*!< UART0_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_UART1_TP_Pos (12UL) /*!< UART1_TP (Bit 12) */ #define PBR_PACRF_UART1_TP_Msk (0x1000UL) /*!< UART1_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_UART1_WP_Pos (13UL) /*!< UART1_WP (Bit 13) */ #define PBR_PACRF_UART1_WP_Msk (0x2000UL) /*!< UART1_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_UART1_SP_Pos (14UL) /*!< UART1_SP (Bit 14) */ #define PBR_PACRF_UART1_SP_Msk (0x4000UL) /*!< UART1_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_UART2_TP_Pos (16UL) /*!< UART2_TP (Bit 16) */ #define PBR_PACRF_UART2_TP_Msk (0x10000UL) /*!< UART2_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_UART2_WP_Pos (17UL) /*!< UART2_WP (Bit 17) */ #define PBR_PACRF_UART2_WP_Msk (0x20000UL) /*!< UART2_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_UART2_SP_Pos (18UL) /*!< UART2_SP (Bit 18) */ #define PBR_PACRF_UART2_SP_Msk (0x40000UL) /*!< UART2_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_UART3_TP_Pos (20UL) /*!< UART3_TP (Bit 20) */ #define PBR_PACRF_UART3_TP_Msk (0x100000UL) /*!< UART3_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_UART3_WP_Pos (21UL) /*!< UART3_WP (Bit 21) */ #define PBR_PACRF_UART3_WP_Msk (0x200000UL) /*!< UART3_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRF_UART3_SP_Pos (22UL) /*!< UART3_SP (Bit 22) */ #define PBR_PACRF_UART3_SP_Msk (0x400000UL) /*!< UART3_SP (Bitfield-Mask: 0x01) */ /* ========================================================= PACRG ========================================================= */ #define PBR_PACRG_PCT_TP_Pos (0UL) /*!< PCT_TP (Bit 0) */ #define PBR_PACRG_PCT_TP_Msk (0x1UL) /*!< PCT_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRG_PCT_WP_Pos (1UL) /*!< PCT_WP (Bit 1) */ #define PBR_PACRG_PCT_WP_Msk (0x2UL) /*!< PCT_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRG_PCT_SP_Pos (2UL) /*!< PCT_SP (Bit 2) */ #define PBR_PACRG_PCT_SP_Msk (0x4UL) /*!< PCT_SP (Bitfield-Mask: 0x01) */ #define PBR_PACRG_CMU_TP_Pos (4UL) /*!< CMU_TP (Bit 4) */ #define PBR_PACRG_CMU_TP_Msk (0x10UL) /*!< CMU_TP (Bitfield-Mask: 0x01) */ #define PBR_PACRG_CMU_WP_Pos (5UL) /*!< CMU_WP (Bit 5) */ #define PBR_PACRG_CMU_WP_Msk (0x20UL) /*!< CMU_WP (Bitfield-Mask: 0x01) */ #define PBR_PACRG_CMU_SP_Pos (6UL) /*!< CMU_SP (Bit 6) */ #define PBR_PACRG_CMU_SP_Msk (0x40UL) /*!< CMU_SP (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ SPM ================ */ /* =========================================================================================================================== */ /* ===================================================== PWR_MGR_CFG0 ====================================================== */ #define SPM_PWR_MGR_CFG0_PWR_EN_Pos (0UL) /*!< PWR_EN (Bit 0) */ #define SPM_PWR_MGR_CFG0_PWR_EN_Msk (0x1UL) /*!< PWR_EN (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG0_AWIC_EN_Pos (1UL) /*!< AWIC_EN (Bit 1) */ #define SPM_PWR_MGR_CFG0_AWIC_EN_Msk (0x2UL) /*!< AWIC_EN (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG0_ACK_TIMEOUT_ACTION_Pos (4UL) /*!< ACK_TIMEOUT_ACTION (Bit 4) */ #define SPM_PWR_MGR_CFG0_ACK_TIMEOUT_ACTION_Msk (0x10UL) /*!< ACK_TIMEOUT_ACTION (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG0_POWER_MODE_Pos (8UL) /*!< POWER_MODE (Bit 8) */ #define SPM_PWR_MGR_CFG0_POWER_MODE_Msk (0x700UL) /*!< POWER_MODE (Bitfield-Mask: 0x07) */ #define SPM_PWR_MGR_CFG0_RESET_MASK_Pos (16UL) /*!< RESET_MASK (Bit 16) */ #define SPM_PWR_MGR_CFG0_RESET_MASK_Msk (0x10000UL) /*!< RESET_MASK (Bitfield-Mask: 0x01) */ /* ===================================================== PWR_MGR_CFG1 ====================================================== */ #define SPM_PWR_MGR_CFG1_LVR_THRESHOLD_Pos (0UL) /*!< LVR_THRESHOLD (Bit 0) */ #define SPM_PWR_MGR_CFG1_LVR_THRESHOLD_Msk (0x1UL) /*!< LVR_THRESHOLD (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG1_LVD_THRESHOLD_Pos (1UL) /*!< LVD_THRESHOLD (Bit 1) */ #define SPM_PWR_MGR_CFG1_LVD_THRESHOLD_Msk (0x2UL) /*!< LVD_THRESHOLD (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG1_HSI_EN_VLPS_Pos (8UL) /*!< HSI_EN_VLPS (Bit 8) */ #define SPM_PWR_MGR_CFG1_HSI_EN_VLPS_Msk (0x100UL) /*!< HSI_EN_VLPS (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG1_HSI_EN_NORMAL_Pos (9UL) /*!< HSI_EN_NORMAL (Bit 9) */ #define SPM_PWR_MGR_CFG1_HSI_EN_NORMAL_Msk (0x200UL) /*!< HSI_EN_NORMAL (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG1_VHSI_EN_Pos (10UL) /*!< VHSI_EN (Bit 10) */ #define SPM_PWR_MGR_CFG1_VHSI_EN_Msk (0x400UL) /*!< VHSI_EN (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG1_SPLL_RDY_Pos (23UL) /*!< SPLL_RDY (Bit 23) */ #define SPM_PWR_MGR_CFG1_SPLL_RDY_Msk (0x800000UL) /*!< SPLL_RDY (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG1_HSI_RDY_Pos (24UL) /*!< HSI_RDY (Bit 24) */ #define SPM_PWR_MGR_CFG1_HSI_RDY_Msk (0x1000000UL) /*!< HSI_RDY (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG1_VHSI_RDY_Pos (25UL) /*!< VHSI_RDY (Bit 25) */ #define SPM_PWR_MGR_CFG1_VHSI_RDY_Msk (0x2000000UL) /*!< VHSI_RDY (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG1_XOSC_RDY_Pos (26UL) /*!< XOSC_RDY (Bit 26) */ #define SPM_PWR_MGR_CFG1_XOSC_RDY_Msk (0x4000000UL) /*!< XOSC_RDY (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG1_SPLL_EN_Pos (27UL) /*!< SPLL_EN (Bit 27) */ #define SPM_PWR_MGR_CFG1_SPLL_EN_Msk (0x8000000UL) /*!< SPLL_EN (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Pos (28UL) /*!< XOSC_HSEBYP (Bit 28) */ #define SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Msk (0x10000000UL) /*!< XOSC_HSEBYP (Bitfield-Mask: 0x01) */ #define SPM_PWR_MGR_CFG1_XOSC_HSEEN_Pos (29UL) /*!< XOSC_HSEEN (Bit 29) */ #define SPM_PWR_MGR_CFG1_XOSC_HSEEN_Msk (0x20000000UL) /*!< XOSC_HSEEN (Bitfield-Mask: 0x01) */ /* ================================================ PERIPH_SLEEP_ACK_STATUS ================================================ */ #define SPM_PERIPH_SLEEP_ACK_STATUS_I2C0_Pos (0UL) /*!< I2C0 (Bit 0) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_I2C0_Msk (0x1UL) /*!< I2C0 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_SPI0_Pos (2UL) /*!< SPI0 (Bit 2) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_SPI0_Msk (0x4UL) /*!< SPI0 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_SPI1_Pos (3UL) /*!< SPI1 (Bit 3) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_SPI1_Msk (0x8UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_SPI2_Pos (4UL) /*!< SPI2 (Bit 4) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_SPI2_Msk (0x10UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_CAN0_Pos (5UL) /*!< CAN0 (Bit 5) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_CAN0_Msk (0x20UL) /*!< CAN0 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_CAN1_Pos (6UL) /*!< CAN1 (Bit 6) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_CAN1_Msk (0x40UL) /*!< CAN1 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_CAN2_Pos (7UL) /*!< CAN2 (Bit 7) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_CAN2_Msk (0x80UL) /*!< CAN2 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_CAN3_Pos (8UL) /*!< CAN3 (Bit 8) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_CAN3_Msk (0x100UL) /*!< CAN3 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_UART0_Pos (11UL) /*!< UART0 (Bit 11) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_UART0_Msk (0x800UL) /*!< UART0 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_UART1_Pos (12UL) /*!< UART1 (Bit 12) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_UART1_Msk (0x1000UL) /*!< UART1 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_UART2_Pos (13UL) /*!< UART2 (Bit 13) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_UART2_Msk (0x2000UL) /*!< UART2 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_UART3_Pos (14UL) /*!< UART3 (Bit 14) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_UART3_Msk (0x4000UL) /*!< UART3 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_DMA0_Pos (17UL) /*!< DMA0 (Bit 17) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_DMA0_Msk (0x20000UL) /*!< DMA0 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_EIO_Pos (18UL) /*!< EIO (Bit 18) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_EIO_Msk (0x40000UL) /*!< EIO (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_FLASH_Pos (19UL) /*!< FLASH (Bit 19) */ #define SPM_PERIPH_SLEEP_ACK_STATUS_FLASH_Msk (0x80000UL) /*!< FLASH (Bitfield-Mask: 0x01) */ /* ================================================== PERIPH_SLEEP_ACK_EN ================================================== */ #define SPM_PERIPH_SLEEP_ACK_EN_I2C0_Pos (0UL) /*!< I2C0 (Bit 0) */ #define SPM_PERIPH_SLEEP_ACK_EN_I2C0_Msk (0x1UL) /*!< I2C0 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_SPI0_Pos (2UL) /*!< SPI0 (Bit 2) */ #define SPM_PERIPH_SLEEP_ACK_EN_SPI0_Msk (0x4UL) /*!< SPI0 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_SPI1_Pos (3UL) /*!< SPI1 (Bit 3) */ #define SPM_PERIPH_SLEEP_ACK_EN_SPI1_Msk (0x8UL) /*!< SPI1 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_SPI2_Pos (4UL) /*!< SPI2 (Bit 4) */ #define SPM_PERIPH_SLEEP_ACK_EN_SPI2_Msk (0x10UL) /*!< SPI2 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_CAN0_Pos (5UL) /*!< CAN0 (Bit 5) */ #define SPM_PERIPH_SLEEP_ACK_EN_CAN0_Msk (0x20UL) /*!< CAN0 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_CAN1_Pos (6UL) /*!< CAN1 (Bit 6) */ #define SPM_PERIPH_SLEEP_ACK_EN_CAN1_Msk (0x40UL) /*!< CAN1 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_CAN2_Pos (7UL) /*!< CAN2 (Bit 7) */ #define SPM_PERIPH_SLEEP_ACK_EN_CAN2_Msk (0x80UL) /*!< CAN2 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_CAN3_Pos (8UL) /*!< CAN3 (Bit 8) */ #define SPM_PERIPH_SLEEP_ACK_EN_CAN3_Msk (0x100UL) /*!< CAN3 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_UART0_Pos (11UL) /*!< UART0 (Bit 11) */ #define SPM_PERIPH_SLEEP_ACK_EN_UART0_Msk (0x800UL) /*!< UART0 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_UART1_Pos (12UL) /*!< UART1 (Bit 12) */ #define SPM_PERIPH_SLEEP_ACK_EN_UART1_Msk (0x1000UL) /*!< UART1 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_UART2_Pos (13UL) /*!< UART2 (Bit 13) */ #define SPM_PERIPH_SLEEP_ACK_EN_UART2_Msk (0x2000UL) /*!< UART2 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_UART3_Pos (14UL) /*!< UART3 (Bit 14) */ #define SPM_PERIPH_SLEEP_ACK_EN_UART3_Msk (0x4000UL) /*!< UART3 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_DMA0_Pos (17UL) /*!< DMA0 (Bit 17) */ #define SPM_PERIPH_SLEEP_ACK_EN_DMA0_Msk (0x20000UL) /*!< DMA0 (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_EIO_Pos (18UL) /*!< EIO (Bit 18) */ #define SPM_PERIPH_SLEEP_ACK_EN_EIO_Msk (0x40000UL) /*!< EIO (Bitfield-Mask: 0x01) */ #define SPM_PERIPH_SLEEP_ACK_EN_FLASH_Pos (19UL) /*!< FLASH (Bit 19) */ #define SPM_PERIPH_SLEEP_ACK_EN_FLASH_Msk (0x80000UL) /*!< FLASH (Bitfield-Mask: 0x01) */ /* ======================================================== STATUS ========================================================= */ #define SPM_STATUS_CURR_POWER_MODE_Pos (0UL) /*!< CURR_POWER_MODE (Bit 0) */ #define SPM_STATUS_CURR_POWER_MODE_Msk (0x7UL) /*!< CURR_POWER_MODE (Bitfield-Mask: 0x07) */ #define SPM_STATUS_ACK_TIMEOUT_FLAG_Pos (4UL) /*!< ACK_TIMEOUT_FLAG (Bit 4) */ #define SPM_STATUS_ACK_TIMEOUT_FLAG_Msk (0x10UL) /*!< ACK_TIMEOUT_FLAG (Bitfield-Mask: 0x01) */ /* ======================================================= STB_WP_EN ======================================================= */ #define SPM_STB_WP_EN_PA12_Pos (0UL) /*!< PA12 (Bit 0) */ #define SPM_STB_WP_EN_PA12_Msk (0x3UL) /*!< PA12 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PB8_Pos (2UL) /*!< PB8 (Bit 2) */ #define SPM_STB_WP_EN_PB8_Msk (0xcUL) /*!< PB8 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PB1_Pos (4UL) /*!< PB1 (Bit 4) */ #define SPM_STB_WP_EN_PB1_Msk (0x30UL) /*!< PB1 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PB12_Pos (6UL) /*!< PB12 (Bit 6) */ #define SPM_STB_WP_EN_PB12_Msk (0xc0UL) /*!< PB12 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PD3_Pos (8UL) /*!< PD3 (Bit 8) */ #define SPM_STB_WP_EN_PD3_Msk (0x300UL) /*!< PD3 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PC2_Pos (10UL) /*!< PC2 (Bit 10) */ #define SPM_STB_WP_EN_PC2_Msk (0xc00UL) /*!< PC2 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PC3_Pos (12UL) /*!< PC3 (Bit 12) */ #define SPM_STB_WP_EN_PC3_Msk (0x3000UL) /*!< PC3 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PC6_Pos (14UL) /*!< PC6 (Bit 14) */ #define SPM_STB_WP_EN_PC6_Msk (0xc000UL) /*!< PC6 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PC7_Pos (16UL) /*!< PC7 (Bit 16) */ #define SPM_STB_WP_EN_PC7_Msk (0x30000UL) /*!< PC7 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PC16_Pos (18UL) /*!< PC16 (Bit 18) */ #define SPM_STB_WP_EN_PC16_Msk (0xc0000UL) /*!< PC16 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PC17_Pos (20UL) /*!< PC17 (Bit 20) */ #define SPM_STB_WP_EN_PC17_Msk (0x300000UL) /*!< PC17 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PD6_Pos (22UL) /*!< PD6 (Bit 22) */ #define SPM_STB_WP_EN_PD6_Msk (0xc00000UL) /*!< PD6 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PD7_Pos (24UL) /*!< PD7 (Bit 24) */ #define SPM_STB_WP_EN_PD7_Msk (0x3000000UL) /*!< PD7 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PE4_Pos (26UL) /*!< PE4 (Bit 26) */ #define SPM_STB_WP_EN_PE4_Msk (0xc000000UL) /*!< PE4 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_PE5_Pos (28UL) /*!< PE5 (Bit 28) */ #define SPM_STB_WP_EN_PE5_Msk (0x30000000UL) /*!< PE5 (Bitfield-Mask: 0x03) */ #define SPM_STB_WP_EN_RTC_Pos (30UL) /*!< RTC (Bit 30) */ #define SPM_STB_WP_EN_RTC_Msk (0xc0000000UL) /*!< RTC (Bitfield-Mask: 0x03) */ /* ===================================================== STB_WP_STATUS ===================================================== */ #define SPM_STB_WP_STATUS_PA12_Pos (0UL) /*!< PA12 (Bit 0) */ #define SPM_STB_WP_STATUS_PA12_Msk (0x1UL) /*!< PA12 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PB0_Pos (1UL) /*!< PB0 (Bit 1) */ #define SPM_STB_WP_STATUS_PB0_Msk (0x2UL) /*!< PB0 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PB1_Pos (2UL) /*!< PB1 (Bit 2) */ #define SPM_STB_WP_STATUS_PB1_Msk (0x4UL) /*!< PB1 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PB12_Pos (3UL) /*!< PB12 (Bit 3) */ #define SPM_STB_WP_STATUS_PB12_Msk (0x8UL) /*!< PB12 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PD3_Pos (4UL) /*!< PD3 (Bit 4) */ #define SPM_STB_WP_STATUS_PD3_Msk (0x10UL) /*!< PD3 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PC2_Pos (5UL) /*!< PC2 (Bit 5) */ #define SPM_STB_WP_STATUS_PC2_Msk (0x20UL) /*!< PC2 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PC3_Pos (6UL) /*!< PC3 (Bit 6) */ #define SPM_STB_WP_STATUS_PC3_Msk (0x40UL) /*!< PC3 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PC6_Pos (7UL) /*!< PC6 (Bit 7) */ #define SPM_STB_WP_STATUS_PC6_Msk (0x80UL) /*!< PC6 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PC7_Pos (8UL) /*!< PC7 (Bit 8) */ #define SPM_STB_WP_STATUS_PC7_Msk (0x100UL) /*!< PC7 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PC16_Pos (9UL) /*!< PC16 (Bit 9) */ #define SPM_STB_WP_STATUS_PC16_Msk (0x200UL) /*!< PC16 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PC17_Pos (10UL) /*!< PC17 (Bit 10) */ #define SPM_STB_WP_STATUS_PC17_Msk (0x400UL) /*!< PC17 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PD6_Pos (11UL) /*!< PD6 (Bit 11) */ #define SPM_STB_WP_STATUS_PD6_Msk (0x800UL) /*!< PD6 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PD7_Pos (12UL) /*!< PD7 (Bit 12) */ #define SPM_STB_WP_STATUS_PD7_Msk (0x1000UL) /*!< PD7 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PE4_Pos (13UL) /*!< PE4 (Bit 13) */ #define SPM_STB_WP_STATUS_PE4_Msk (0x2000UL) /*!< PE4 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_PE5_Pos (14UL) /*!< PE5 (Bit 14) */ #define SPM_STB_WP_STATUS_PE5_Msk (0x4000UL) /*!< PE5 (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_RTC_Pos (15UL) /*!< RTC (Bit 15) */ #define SPM_STB_WP_STATUS_RTC_Msk (0x8000UL) /*!< RTC (Bitfield-Mask: 0x01) */ #define SPM_STB_WP_STATUS_STB_WP_FLG_Pos (16UL) /*!< STB_WP_FLG (Bit 16) */ #define SPM_STB_WP_STATUS_STB_WP_FLG_Msk (0x10000UL) /*!< STB_WP_FLG (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ GPIO ================ */ /* =========================================================================================================================== */ /* ========================================================= PODR ========================================================== */ #define GPIO_PODR_PODR0_Pos (0UL) /*!< PODR0 (Bit 0) */ #define GPIO_PODR_PODR0_Msk (0x1UL) /*!< PODR0 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR1_Pos (1UL) /*!< PODR1 (Bit 1) */ #define GPIO_PODR_PODR1_Msk (0x2UL) /*!< PODR1 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR2_Pos (2UL) /*!< PODR2 (Bit 2) */ #define GPIO_PODR_PODR2_Msk (0x4UL) /*!< PODR2 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR3_Pos (3UL) /*!< PODR3 (Bit 3) */ #define GPIO_PODR_PODR3_Msk (0x8UL) /*!< PODR3 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR4_Pos (4UL) /*!< PODR4 (Bit 4) */ #define GPIO_PODR_PODR4_Msk (0x10UL) /*!< PODR4 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR5_Pos (5UL) /*!< PODR5 (Bit 5) */ #define GPIO_PODR_PODR5_Msk (0x20UL) /*!< PODR5 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR6_Pos (6UL) /*!< PODR6 (Bit 6) */ #define GPIO_PODR_PODR6_Msk (0x40UL) /*!< PODR6 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR7_Pos (7UL) /*!< PODR7 (Bit 7) */ #define GPIO_PODR_PODR7_Msk (0x80UL) /*!< PODR7 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR8_Pos (8UL) /*!< PODR8 (Bit 8) */ #define GPIO_PODR_PODR8_Msk (0x100UL) /*!< PODR8 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR9_Pos (9UL) /*!< PODR9 (Bit 9) */ #define GPIO_PODR_PODR9_Msk (0x200UL) /*!< PODR9 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR10_Pos (10UL) /*!< PODR10 (Bit 10) */ #define GPIO_PODR_PODR10_Msk (0x400UL) /*!< PODR10 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR11_Pos (11UL) /*!< PODR11 (Bit 11) */ #define GPIO_PODR_PODR11_Msk (0x800UL) /*!< PODR11 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR12_Pos (12UL) /*!< PODR12 (Bit 12) */ #define GPIO_PODR_PODR12_Msk (0x1000UL) /*!< PODR12 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR13_Pos (13UL) /*!< PODR13 (Bit 13) */ #define GPIO_PODR_PODR13_Msk (0x2000UL) /*!< PODR13 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR14_Pos (14UL) /*!< PODR14 (Bit 14) */ #define GPIO_PODR_PODR14_Msk (0x4000UL) /*!< PODR14 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR15_Pos (15UL) /*!< PODR15 (Bit 15) */ #define GPIO_PODR_PODR15_Msk (0x8000UL) /*!< PODR15 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR16_Pos (16UL) /*!< PODR16 (Bit 16) */ #define GPIO_PODR_PODR16_Msk (0x10000UL) /*!< PODR16 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR17_Pos (17UL) /*!< PODR17 (Bit 17) */ #define GPIO_PODR_PODR17_Msk (0x20000UL) /*!< PODR17 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR18_Pos (18UL) /*!< PODR18 (Bit 18) */ #define GPIO_PODR_PODR18_Msk (0x40000UL) /*!< PODR18 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR19_Pos (19UL) /*!< PODR19 (Bit 19) */ #define GPIO_PODR_PODR19_Msk (0x80000UL) /*!< PODR19 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR20_Pos (20UL) /*!< PODR20 (Bit 20) */ #define GPIO_PODR_PODR20_Msk (0x100000UL) /*!< PODR20 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR21_Pos (21UL) /*!< PODR21 (Bit 21) */ #define GPIO_PODR_PODR21_Msk (0x200000UL) /*!< PODR21 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR22_Pos (22UL) /*!< PODR22 (Bit 22) */ #define GPIO_PODR_PODR22_Msk (0x400000UL) /*!< PODR22 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR23_Pos (23UL) /*!< PODR23 (Bit 23) */ #define GPIO_PODR_PODR23_Msk (0x800000UL) /*!< PODR23 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR24_Pos (24UL) /*!< PODR24 (Bit 24) */ #define GPIO_PODR_PODR24_Msk (0x1000000UL) /*!< PODR24 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR25_Pos (25UL) /*!< PODR25 (Bit 25) */ #define GPIO_PODR_PODR25_Msk (0x2000000UL) /*!< PODR25 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR26_Pos (26UL) /*!< PODR26 (Bit 26) */ #define GPIO_PODR_PODR26_Msk (0x4000000UL) /*!< PODR26 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR27_Pos (27UL) /*!< PODR27 (Bit 27) */ #define GPIO_PODR_PODR27_Msk (0x8000000UL) /*!< PODR27 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR28_Pos (28UL) /*!< PODR28 (Bit 28) */ #define GPIO_PODR_PODR28_Msk (0x10000000UL) /*!< PODR28 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR29_Pos (29UL) /*!< PODR29 (Bit 29) */ #define GPIO_PODR_PODR29_Msk (0x20000000UL) /*!< PODR29 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR30_Pos (30UL) /*!< PODR30 (Bit 30) */ #define GPIO_PODR_PODR30_Msk (0x40000000UL) /*!< PODR30 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_PODR31_Pos (31UL) /*!< PODR31 (Bit 31) */ #define GPIO_PODR_PODR31_Msk (0x80000000UL) /*!< PODR31 (Bitfield-Mask: 0x01) */ #define GPIO_PODR_Pos(x) ((uint32_t)x) /*!< PODRx (Bit x) */ #define GPIO_PODR_Msk(x) (0x01UL<_DRV_GetVersionInfo() function. */ typedef struct { uint16_t moduleID; /**< @brief module ID */ uint8_t majorVersion; /**< @brief module software major version */ uint8_t minorVersion; /**< @brief module software minor version */ uint8_t patchVersion; /**< @brief module software patch version */ } Drv_VersionInfo_Type; #ifdef __cplusplus } #endif #endif /* AC7840X_H */ /** @} */ /* End of group AC7840x */ /** @} */ /* End of group AutoChips */