Init Mono
This commit is contained in:
cfif
commit
3511d68eb9
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#include "Clock.h"
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/* ################################################################################## */
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/* ################################### Type define ################################## */
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/* PCBA external oscillator value, these macro is user defined. */
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/* FOSC/SOSC clock need to manually configuration according to PCBA XTAL value
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* in SOSC/FOSc configuration.
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* Current default value is the XTAL value on EVB board. */
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/* ################################################################################## */
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/* ########################### Local Prototype Functions ############################ */
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static void Bsp_SCG_Init(void);
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static void Bsp_PCC_Init(void);
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/* ################################################################################## */
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/* ################################ Local Functions ################################# */
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/**
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* @brief Local SCG initial
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*
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*/
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// Ядро процессора: 240 МГц
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// Системная шина: 120 МГц
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// Медленная периферия: 120 МГц
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// PLL0/PLL1: 240 МГц
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// FOSC: 24 МГц
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// SIRC: 12 МГц
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static void Bsp_SCG_Init(void) {
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SCG_Deinit();
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/* Enable FOSC, frequency is 24M, DIVH=DIV1(24M), DIVM=DIV1(24M), DIVL=DIV2(12M)*/
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// FOSC - Внешний кварцевый генератор (Базовый источник 24 МГц)
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SCG_FoscType tFoscStruct =
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{
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.bLock = false,
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.bCm = false,
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.bCmre = false,
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.bSten = false,
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.bBypass = false,
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.eDivH = SCG_ASYNCCLOCKDIV_BY1,
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.eDivM = SCG_ASYNCCLOCKDIV_BY1,
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.eDivL = SCG_ASYNCCLOCKDIV_BY2,
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};
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SCG_EnableFOSC(&tFoscStruct);
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/* Enable PLL0, frequency is 240M, DIVH=DIV2(120M), DIVM=DIV2(120M), DIVL=DIV4(60M), src=FOSC*/
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/* The value of multiplier factor(FOSC/u8Prediv) between 2 ~ 4 is better*/
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// FOSC = 24 МГц
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// После предделителя: 24 МГц / (11 + 1) = 24 МГц / 12 = 2 МГц
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// После умножения: 2 МГц × (239 + 1) = 2 МГц × 240 = 480 МГц
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// После постделителя: 480 МГц / 2 = 240 МГц
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SCG_PllType tPll0Struct =
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{
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.bLock = false,
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.bCm = false,
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.bCmre = false,
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.bSten = false,
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.eDivH = SCG_ASYNCCLOCKDIV_BY2,
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.eDivM = SCG_ASYNCCLOCKDIV_BY2,
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.eDivL = SCG_ASYNCCLOCKDIV_BY4,
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.u8Prediv = 11U,
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.ePstDiv = SCG_PLLPSTDIV_BY2,
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.u16Mult = 239U,
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.eSrc = SCG_PLLSOURCE_FOSC
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};
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SCG_EnablePLL(SCG_PLL0, &tPll0Struct);
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/* Enable PLL1, frequency is 240M, DIVH=DIV2(120M), DIVM=DIV2(120M), DIVL=DIV4(60M), src=FOSC*/
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/* The value of multiplier factor(FOSC/u8Prediv) between 2 ~ 4 is better*/
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// Аналогична PLL0, также 240 МГц
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// Обычно используется для периферии
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SCG_PllType tPll1Struct =
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{
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.bLock = false,
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.bCm = false,
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.bCmre = false,
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.bSten = false,
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.eDivH = SCG_ASYNCCLOCKDIV_BY2,
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.eDivM = SCG_ASYNCCLOCKDIV_BY2,
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.eDivL = SCG_ASYNCCLOCKDIV_BY4,
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.u8Prediv = 11U,
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.ePstDiv = SCG_PLLPSTDIV_BY2,
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.u16Mult = 239U,
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.eSrc = SCG_PLLSOURCE_FOSC
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};
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SCG_EnablePLL(SCG_PLL1, &tPll1Struct);
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/* Enable SIRC DIV, DIVH=DIV1(12M), DIVM=DIV1(12M), DIVL=DIV2(6M) */
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// Резервный источник тактирования
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// Меньшая точность, но быстрый запуск
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SCG_SircType tSircStruct =
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{
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.bLock = false,
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.bCm = false,
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.bTrEn = false,
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.bLpen = false,
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.bSten = false,
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.eDivH = SCG_ASYNCCLOCKDIV_BY1,
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.eDivM = SCG_ASYNCCLOCKDIV_BY1,
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.eDivL = SCG_ASYNCCLOCKDIV_BY2,
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.u8TrimSrc = 0U
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};
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SCG_SetSIRC(&tSircStruct);
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/* Set core clock source from PLL0, DIV_CORE=DIV1(240M), DIV_BUS=DIV2(120M), DIV_SLOW=DIV4(60M)*/
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// Системное тактирование
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//.eSrc = PLL0, // Источник - PLL0 (240 МГц)
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//.eDivCore = DIV1, // Ядро: 240 МГц
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//.eDivBus = DIV2, // Шина: 120 МГц
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//.eDivSlow = DIV2 // Медленная периферия: 120 МГц
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SCG_ClockCtrlType tClockStruct =
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{
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.bSysClkMonitor = false,
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.eSrc = SCG_CLOCK_SRC_PLL0,
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.eDivSlow = SCG_CLOCK_DIV_BY2,
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.eDivBus = SCG_CLOCK_DIV_BY2,
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.eDivCore = SCG_CLOCK_DIV_BY1
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};
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SCG_SetClkCtrl(&tClockStruct);
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}
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/**
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* @brief Local PCC Initial
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*
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*/
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static void Bsp_PCC_Init(void) {
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PCC_CtrlType bSP_PCC_Config;
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// UART 0 (LIN)
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bSP_PCC_Config.eClockName = PCC_CLK_FCUART0;
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bSP_PCC_Config.bEn = true;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
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PCC_SetPcc(&bSP_PCC_Config);
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// UART 1 (DBG)
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bSP_PCC_Config.eClockName = PCC_CLK_FCUART1;
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bSP_PCC_Config.bEn = true;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
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PCC_SetPcc(&bSP_PCC_Config);
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// UART 2 (LIN)
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bSP_PCC_Config.eClockName = PCC_CLK_FCUART2;
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bSP_PCC_Config.bEn = true;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
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PCC_SetPcc(&bSP_PCC_Config);
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// UART 3 (LIN)
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bSP_PCC_Config.eClockName = PCC_CLK_FCUART3;
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bSP_PCC_Config.bEn = true;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
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PCC_SetPcc(&bSP_PCC_Config);
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// UART 4 (LIN)
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bSP_PCC_Config.eClockName = PCC_CLK_FCUART4;
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bSP_PCC_Config.bEn = true;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
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PCC_SetPcc(&bSP_PCC_Config);
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// UART 5 (LIN)
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bSP_PCC_Config.eClockName = PCC_CLK_FCUART5;
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bSP_PCC_Config.bEn = true;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
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PCC_SetPcc(&bSP_PCC_Config);
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// CAN 0
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bSP_PCC_Config.eClockName = PCC_CLK_FLEXCAN0;
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bSP_PCC_Config.bEn = TRUE;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_DIV_BY1;
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PCC_SetPcc(&bSP_PCC_Config);
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// CAN 1
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bSP_PCC_Config.eClockName = PCC_CLK_FLEXCAN1;
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bSP_PCC_Config.bEn = TRUE;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_DIV_BY1;
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PCC_SetPcc(&bSP_PCC_Config);
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// ADC 0
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bSP_PCC_Config.eClockName = PCC_CLK_ADC0;
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bSP_PCC_Config.bEn = TRUE;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_DIV_BY1;
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PCC_SetPcc(&bSP_PCC_Config);
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// ADC 1
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bSP_PCC_Config.eClockName = PCC_CLK_ADC1;
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bSP_PCC_Config.bEn = TRUE;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_DIV_BY1;
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PCC_SetPcc(&bSP_PCC_Config);
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// DMA 0
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bSP_PCC_Config.eClockName = PCC_CLK_DMA0;
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bSP_PCC_Config.bEn = true;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
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PCC_SetPcc(&bSP_PCC_Config);
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// DMAMUX 0
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bSP_PCC_Config.eClockName = PCC_CLK_DMAMUX0;
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bSP_PCC_Config.bEn = true;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
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PCC_SetPcc(&bSP_PCC_Config);
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// CRC
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bSP_PCC_Config.eClockName = PCC_CLK_CRC0;
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bSP_PCC_Config.bEn = true;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_PLL0DIV;
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bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
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PCC_SetPcc(&bSP_PCC_Config);
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// PCC_CLK_WKU0
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bSP_PCC_Config.eClockName = PCC_CLK_WKU0;
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bSP_PCC_Config.bEn = true;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_UNINVOLVED;
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bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
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PCC_SetPcc(&bSP_PCC_Config);
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}
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void Bsp_Systick_Init(void)
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{
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uint32_t u32ReloadVal;
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uint32_t SystemCoreClock;
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SystemCoreClock = SCG_GetScgClockFreq(SCG_CORE_CLK);
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while(SystemCoreClock == 0){};
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u32ReloadVal = SystemCoreClock / 1000;
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Core_SysTick_Config(u32ReloadVal);
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NVIC_SetPriority(SysTick_IRQn, 0);
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Core_SysTick_Enable();
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}
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/* ################################################################################## */
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/* ################################# Global Functions ############################### */
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/**
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* @brief General Clock Initial
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*
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*/
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void Bsp_CLOCK_Init(void) {
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CSC0_ClkoutType tCSCClkOutCfg = {0};
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/* Configure CSC(clock out configuration) */
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tCSCClkOutCfg.bEnable = true;
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tCSCClkOutCfg.eClkOutSrc = CSC0_CLKOUT_BUS_CLK;
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tCSCClkOutCfg.eDivider = CSC0_CLKOUT_DIV_BY4;
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SCG_Deinit();
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Bsp_SCG_Init();
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Bsp_PCC_Init();
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/* Set clock out */
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SCG_SetClkOut(SCG_CLOCKOUT_SRC_FOSC);
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CSC0_SetClockOut(&tCSCClkOutCfg, false);
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Bsp_Systick_Init();
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}
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@ -0,0 +1,20 @@
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#ifndef INCLUDE_BSP_CLOCK_H_
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#define INCLUDE_BSP_CLOCK_H_
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#include "fc7xxx_driver_fcuart.h"
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#include "fc7xxx_driver_pcc.h"
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#include "fc7xxx_driver_port.h"
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#include "fc7xxx_driver_scg.h"
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#include "fc7xxx_driver_gpio.h"
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#include "fc7xxx_driver_dma.h"
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#include "fc7xxx_driver_csc.h"
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#include "interrupt_manager.h"
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#include "fc7xxx_driver_systick.h"
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/**
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* @brief General Clock Initial
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*
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*/
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void Bsp_CLOCK_Init(void);
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#endif /* INCLUDE_BSP_CLOCK_H_ */
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@ -0,0 +1,253 @@
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/* Entry Point */
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ENTRY(Reset_Handler)
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M_VECTOR_RAM_SIZE = 0x0400;
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_BootloaderSize = 64K;
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_BootloaderBegin = 0x01000000; /* BANK1 */
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_FirmwareSize = 704K;
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_MetadataSize = 256;
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_FirmwareSize_CALIB = 256K;
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_FirmwareMainBegin = _BootloaderBegin + _BootloaderSize;
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_FirmwareMetaBegin = _FirmwareMainBegin + _FirmwareSize - _MetadataSize;
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_FirmwareCalibBegin = _FirmwareMainBegin + _FirmwareSize;
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_FirmwareMetaCalibBegin = _FirmwareCalibBegin + _FirmwareSize_CALIB - _MetadataSize;
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_FirmwareRecoveryBegin = 0x01100000; /* BANK2 */
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_FirmwareRecoveryMetaBegin = _FirmwareRecoveryBegin + _FirmwareSize - _MetadataSize;
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_FirmwareRecoveryCalibBegin = _FirmwareRecoveryBegin + _FirmwareSize;
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_FirmwareRecoveryMetaCalibBegin = _FirmwareRecoveryCalibBegin + _FirmwareSize_CALIB - _MetadataSize;
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/* Specify the memory areas */
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MEMORY
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{
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ITCM (RW) : ORIGIN = 0x00000000, LENGTH = 0x00008000 /* 32KB */
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SRAM0 (RW) : ORIGIN = 0x21000000, LENGTH = 0x00010000 /* 64KB */
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SRAM1 (RW) : ORIGIN = 0x21010000, LENGTH = 0x00008000 /* 32KB */
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PFLASH_BOOT (RW) : ORIGIN = _BootloaderBegin, LENGTH = _BootloaderSize /* 64K */
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PFLASH_MAIN (RW) : ORIGIN = _FirmwareMainBegin, LENGTH = _FirmwareSize /* 704K */
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PFLASH_MAIN_META (RW) : ORIGIN = _FirmwareMetaBegin, LENGTH = _MetadataSize /* 256 */
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PFLASH_CALIB (RW) : ORIGIN = _FirmwareCalibBegin, LENGTH = _FirmwareSize_CALIB /* 256K */
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PFLASH_CALIB_META (RW) : ORIGIN = _FirmwareMetaCalibBegin, LENGTH = _MetadataSize /* 256 */
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PFLASH_R_MAIN (RW) : ORIGIN = _FirmwareRecoveryBegin, LENGTH = _FirmwareSize /* 704K */
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PFLASH_R_MAIN_META (RW) : ORIGIN = _FirmwareRecoveryMetaBegin, LENGTH = _MetadataSize /* 256 */
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PFLASH_R_CALIB (RW) : ORIGIN = _FirmwareRecoveryCalibBegin, LENGTH = _FirmwareSize_CALIB /* 192K */
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PFLASH_R_CALIB_META (RW) : ORIGIN = _FirmwareRecoveryMetaCalibBegin, LENGTH = _FirmwareSize_CALIB /* 256 */
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DFLASH (RW) : ORIGIN = 0x04000000, LENGTH = 0x00020000 /* 128KB */
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NVR0 (RW) : ORIGIN = 0x04400000, LENGTH = 0x00004000 /* 16KB */
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NVR1 (RW) : ORIGIN = 0x04408000, LENGTH = 0x00004000 /* 16KB */
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NVR2 (RW) : ORIGIN = 0x04410000, LENGTH = 0x00002000 /* 8KB */
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/* DTCM */
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DTCM (RW) : ORIGIN = 0x20000000, LENGTH = 0x0001FA00 /* 128K - 0x600 */
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DTCM_STACK (RW) : ORIGIN = 0x2001FA00, LENGTH = 0x00000600 /* 0x600 */
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}
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/* Define output sections */
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SECTIONS
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{
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/* The program code and other data goes into internal flash */
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.text :
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{
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. = ALIGN(1024); /* VTOR must be align to 1K */
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__vector_table = .;
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__interrupts_start__ = .;
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. = ALIGN(4);
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KEEP(*(.isr_vector))
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__interrupts_end__ = .;
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. = ALIGN(4);
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KEEP(*(.version_section))
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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*(.init) /* section used in crti.o files */
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*(.fini) /* section used in crti.o files */
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*(.eh_frame) /* section used in crtbegin.o files */
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. = ALIGN(4);
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} > PFLASH_MAIN
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.meta_main : SUBALIGN(1)
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{
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/* LONG(_FirmwareSize - 4) ;*/ /* word with firmware_size */
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KEEP(*(.meta_fw_name_size))
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KEEP(*(.meta_fw_name))
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||||
|
||||
KEEP(*(.meta_internal_hw_year))
|
||||
KEEP(*(.meta_internal_hw_month))
|
||||
KEEP(*(.meta_internal_hw_day))
|
||||
KEEP(*(.meta_internal_hw_rev))
|
||||
|
||||
KEEP(*(.meta_internal_sw_year))
|
||||
KEEP(*(.meta_internal_sw_month))
|
||||
KEEP(*(.meta_internal_sw_day))
|
||||
KEEP(*(.meta_internal_sw_rev))
|
||||
|
||||
KEEP(*(.meta_internal_mdb_year))
|
||||
KEEP(*(.meta_internal_mdb_month))
|
||||
KEEP(*(.meta_internal_mdb_day))
|
||||
KEEP(*(.meta_internal_mdb_rev))
|
||||
|
||||
KEEP(*(.meta_finger_module))
|
||||
KEEP(*(.meta_finger_tester_serial))
|
||||
KEEP(*(.meta_finger_year))
|
||||
KEEP(*(.meta_finger_month))
|
||||
KEEP(*(.meta_finger_day))
|
||||
|
||||
. = ALIGN(256);
|
||||
} > PFLASH_MAIN_META
|
||||
|
||||
|
||||
.caltext : SUBALIGN(2)
|
||||
{
|
||||
__caltext_start = .;
|
||||
KEEP(*(.caltext))
|
||||
__caltext_end = .;
|
||||
. = ALIGN(4);
|
||||
} > PFLASH_CALIB
|
||||
|
||||
.meta_main : SUBALIGN(3)
|
||||
{
|
||||
LONG(0) ; /* word with firmware_size */
|
||||
|
||||
. = ALIGN(256);
|
||||
} > PFLASH_CALIB_META
|
||||
|
||||
|
||||
.data :
|
||||
{
|
||||
__ram_data_start = .;
|
||||
. = ALIGN(4);
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__ram_data_end = .;
|
||||
|
||||
} > DTCM AT > PFLASH_MAIN
|
||||
|
||||
/* Non-cache RAM section with data initialization */
|
||||
.ncache_data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__ram_ncache_data_start = .;
|
||||
*(.nocacheable_data*)
|
||||
__ram_ncache_data_end = .;
|
||||
. = ALIGN(4);
|
||||
} > SRAM1 AT > PFLASH_MAIN
|
||||
|
||||
|
||||
.cals_data(NOLOAD) :
|
||||
{
|
||||
__itcm_start = .;
|
||||
|
||||
/* Начало .caldata */
|
||||
__caldata_start = .;
|
||||
KEEP(*(.caldata))
|
||||
. = ALIGN(4);
|
||||
|
||||
/* Проверяем и резервируем 20K */
|
||||
__caldata_actual_size = . - __caldata_start;
|
||||
ASSERT(__caldata_actual_size <= 20K, "Ошибка: .caldata превышает 20K!");
|
||||
|
||||
/* Если данные меньше 20K, резервируем оставшееся пространство */
|
||||
. = __caldata_start + 20K;
|
||||
|
||||
KEEP(*(.nvmdata))
|
||||
|
||||
__itcm_end = .;
|
||||
. = ALIGN(4);
|
||||
} > ITCM
|
||||
|
||||
.xcp_data(NOLOAD) :
|
||||
{
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.save_data))
|
||||
. = ALIGN(4);
|
||||
|
||||
__xcp_start = .;
|
||||
KEEP(*(.xcpdata))
|
||||
__xcp_end = .;
|
||||
. = ALIGN(4);
|
||||
} > SRAM0
|
||||
|
||||
|
||||
|
||||
.bss(NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
|
||||
|
||||
*HVAC_model.c.obj(.bss .bss*)
|
||||
. = ALIGN(4);
|
||||
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end = .;
|
||||
. = ALIGN(4);
|
||||
} > DTCM
|
||||
|
||||
/* Non-cache RAM section with no initialization */
|
||||
.ncache_bss(NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__ncache_bss_start = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.stack_data))
|
||||
. = ALIGN(4);
|
||||
|
||||
*(.nocacheable_bss*)
|
||||
__ncache_bss_end = .;
|
||||
. = ALIGN(4);
|
||||
} > SRAM1
|
||||
|
||||
__HeapBegin = ORIGIN(DTCM_STACK);
|
||||
__HeapLimit = ORIGIN(DTCM_STACK) + 0x200 - 8;
|
||||
|
||||
__StackLimit = ORIGIN(DTCM_STACK)+0x200;
|
||||
__StackTop = ORIGIN(DTCM_STACK) + LENGTH(DTCM_STACK) - 8;
|
||||
|
||||
__rom_data_start = LOADADDR(.data);
|
||||
__rom_ncache_data_start = LOADADDR(.ncache_data);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
/* USER CODE BEGIN Header */
|
||||
/*
|
||||
* FreeRTOS Kernel V10.3.1
|
||||
* Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* These parameters and more are described within the 'configuration' section of the
|
||||
* FreeRTOS API documentation available on the FreeRTOS.org web site.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
/* USER CODE BEGIN Includes */
|
||||
/* Section where include file can be added */
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Ensure definitions are only used by the compiler, and not by the assembler. */
|
||||
#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock;
|
||||
#endif
|
||||
|
||||
//#ifndef CMSIS_device_header
|
||||
//#define CMSIS_device_header "niietcm4.h"
|
||||
//#define CMSIS_device_header "at32f435_437.h"
|
||||
//#endif /* CMSIS_device_header */
|
||||
//#include "niietcm4.h"
|
||||
//#include "at32f435_437.h"
|
||||
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 1
|
||||
|
||||
#define configENABLE_FPU 1
|
||||
#define configENABLE_MPU 0
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configSUPPORT_STATIC_ALLOCATION 1
|
||||
#define configSUPPORT_DYNAMIC_ALLOCATION 1
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configCPU_CLOCK_HZ ( 240000000 )
|
||||
#define configTICK_RATE_HZ ((TickType_t)1000)
|
||||
#define configMAX_PRIORITIES ( 56 )
|
||||
#define configMINIMAL_STACK_SIZE ((uint16_t)64)
|
||||
#define configTOTAL_HEAP_SIZE ((size_t)20 * 1024)
|
||||
#define configMAX_TASK_NAME_LEN ( 16 )
|
||||
#define configUSE_TRACE_FACILITY 1
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configUSE_MUTEXES 1
|
||||
#define configQUEUE_REGISTRY_SIZE 8
|
||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
#define configUSE_COUNTING_SEMAPHORES 1
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
|
||||
/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
|
||||
/* Defaults to size_t for backward compatibility, but can be changed
|
||||
if lengths will always be less than the number of bytes in a size_t. */
|
||||
#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
|
||||
/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */
|
||||
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
|
||||
|
||||
/* Software timer definitions. */
|
||||
#define configUSE_TIMERS 1
|
||||
#define configTIMER_TASK_PRIORITY ( 2 )
|
||||
#define configTIMER_QUEUE_LENGTH 10
|
||||
#define configTIMER_TASK_STACK_DEPTH 128
|
||||
|
||||
/* CMSIS-RTOS V2 flags */
|
||||
#define configUSE_OS2_THREAD_SUSPEND_RESUME 1
|
||||
#define configUSE_OS2_THREAD_ENUMERATE 1
|
||||
#define configUSE_OS2_EVENTFLAGS_FROM_ISR 1
|
||||
#define configUSE_OS2_THREAD_FLAGS 1
|
||||
#define configUSE_OS2_TIMER 1
|
||||
#define configUSE_OS2_MUTEX 1
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 1
|
||||
#define INCLUDE_vTaskDelete 1
|
||||
#define INCLUDE_vTaskCleanUpResources 0
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_xTaskGetSchedulerState 1
|
||||
#define INCLUDE_xTimerPendFunctionCall 1
|
||||
#define INCLUDE_xQueueGetMutexHolder 1
|
||||
#define INCLUDE_uxTaskGetStackHighWaterMark 1
|
||||
#define INCLUDE_xTaskGetCurrentTaskHandle 1
|
||||
#define INCLUDE_eTaskGetState 1
|
||||
|
||||
/*
|
||||
* The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used
|
||||
* by the application thus the correct define need to be enabled below
|
||||
*/
|
||||
#define USE_FreeRTOS_HEAP_4
|
||||
|
||||
/* Cortex-M specific definitions. */
|
||||
#ifdef __NVIC_PRIO_BITS
|
||||
/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
|
||||
#define configPRIO_BITS __NVIC_PRIO_BITS
|
||||
#else
|
||||
#define configPRIO_BITS 3U
|
||||
#endif
|
||||
|
||||
/* The lowest interrupt priority that can be used in a call to a "set priority"
|
||||
function. */
|
||||
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 7 // 15
|
||||
|
||||
/* The highest interrupt priority that can be used by any interrupt service
|
||||
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
|
||||
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
|
||||
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
|
||||
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 1 // 5
|
||||
|
||||
/* Interrupt priorities used by the kernel port layer itself. These are generic
|
||||
to all Cortex-M ports, and do not rely on any particular library functions. */
|
||||
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
|
||||
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
|
||||
|
||||
/* Normal assert() semantics without relying on the provision of an assert.h
|
||||
header file. */
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
//#define configASSERT(x) if ((x) == 0) {nvic_system_reset();}
|
||||
#define configASSERT(x) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
|
||||
/* USER CODE END 1 */
|
||||
|
||||
/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
|
||||
standard names. */
|
||||
#define vPortSVCHandler SVC_Handler
|
||||
#define xPortPendSVHandler PendSV_Handler
|
||||
|
||||
/* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */
|
||||
|
||||
#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0
|
||||
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
//
|
||||
// Created by cfif on 22.09.2025.
|
||||
//
|
||||
#include "Clock.h"
|
||||
#include "cmsis_os.h"
|
||||
#include "MainModesArbiter.h"
|
||||
#include "LoggerInterface.h"
|
||||
#include "PeripheralInterfaces.h"
|
||||
|
||||
//#define BOOT_AREA_LENGTH (256 * 1024)
|
||||
//#define FIRMWARE_MAIN_ADDR (0x01000000 + BOOT_AREA_LENGTH)
|
||||
//#define FIRMWARE_MAIN_RECOVERY_ADDR (FIRMWARE_MAIN_ADDR + FIRMWARE_MAIN_AREA_LENGTH)
|
||||
|
||||
tMma MAIN_ENV;
|
||||
|
||||
//deep sleep 98 116 197 264
|
||||
|
||||
|
||||
//int _write(int fd, char* ptr, int len) {
|
||||
|
||||
// MAIN_ENV.serialPorts->cliVirtualPortOut_Io.transmit(MAIN_ENV.serialPorts->cliVirtualPortOut_Io.env, (uint8_t *)ptr, len, 0);
|
||||
|
||||
// return len;
|
||||
//return 0;
|
||||
//}
|
||||
|
||||
#define LOGGER &MAIN_ENV.slog.logger
|
||||
#define LOG_SIGN "Model"
|
||||
|
||||
char buffer_printf[1024];
|
||||
|
||||
int printf(const char *format, ...) {
|
||||
|
||||
return 0;
|
||||
|
||||
va_list args;
|
||||
va_start(args, format);
|
||||
int ret = vsnprintf(buffer_printf, sizeof(buffer_printf), format, args);
|
||||
va_end(args);
|
||||
|
||||
if (ret > 0) {
|
||||
|
||||
// if (buffer_printf[ret - 1] == '\n') {
|
||||
// buffer_printf[ret - 1] = ' ';
|
||||
// }
|
||||
|
||||
LoggerCnInfo(LOGGER, LOG_SIGN, buffer_printf, ret)
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
_Noreturn void stop() {
|
||||
while (1) {
|
||||
asm("nop");
|
||||
}
|
||||
}
|
||||
|
||||
#define STOP stop();
|
||||
|
||||
#if (configCHECK_FOR_STACK_OVERFLOW > 0)
|
||||
|
||||
void vApplicationStackOverflowHook(TaskHandle_t xTask, const char *pcTaskName) {
|
||||
PROCESS_UNUSED_VAR(xTask);
|
||||
PROCESS_UNUSED_VAR(pcTaskName);
|
||||
STOP
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void FirmwareStopThread() {
|
||||
ModelTask_StopThread(&MAIN_ENV.ModelTask);
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
|
||||
Bsp_CLOCK_Init();
|
||||
|
||||
NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUP_4);
|
||||
|
||||
osKernelInitialize();
|
||||
|
||||
Mma_Init(&MAIN_ENV, &GPIOS, &ADCS, &SERIAL_PORTS, &LIN_PORTS, &CAN_PORTS, &NVM_STORAGE, &PWMS, &RTCS);
|
||||
|
||||
Mma_StartThread(&MAIN_ENV);
|
||||
|
||||
osKernelStart();
|
||||
|
||||
STOP
|
||||
}
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
{
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"./",
|
||||
"./clock",
|
||||
"./int"
|
||||
],
|
||||
"srcs": [
|
||||
"./**.c",
|
||||
"./clock/**.c",
|
||||
"./int/**.c",
|
||||
"./**.s"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,480 @@
|
|||
/* ================================================================================================== */
|
||||
/* BRIEF : Startup - Startup file for FC7240 */
|
||||
/* PERIPHERAL : N/A */
|
||||
/* PLATFORM : Flagchip FC7240 */
|
||||
/* SOFTWARE VERSION : 0.1.0 */
|
||||
/* VENDOR : Flagchip */
|
||||
/* Copyright 2024 Flagchip Semiconductors Co., Ltd. */
|
||||
/* All Rights Reserved. */
|
||||
/* ================================================================================================== */
|
||||
/* ================================================================================================== */
|
||||
/* Revision History */
|
||||
/* Version Date Initials CR# Descriptions */
|
||||
/* --------- ---------- ------------- ---------- --------------- */
|
||||
/* 0.1.0 2024-01-12 qxw0030 N/A Initial version */
|
||||
/* ================================================================================================== */
|
||||
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.extern __StackTop
|
||||
.extern __StackLimit
|
||||
|
||||
/* ================================================================================================== */
|
||||
/* Set vector table */
|
||||
/* ================================================================================================== */
|
||||
.section .isr_vector
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
|
||||
/* vector table */
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External Interrupts*/
|
||||
.long DMA0_IRQHandler /* DMA channel 0 transfer complete */
|
||||
.long DMA1_IRQHandler /* DMA channel 1 transfer complete */
|
||||
.long DMA2_IRQHandler /* DMA channel 2 transfer complete */
|
||||
.long DMA3_IRQHandler /* DMA channel 3 transfer complete */
|
||||
.long DMA4_IRQHandler /* DMA channel 4 transfer complete */
|
||||
.long DMA5_IRQHandler /* DMA channel 5 transfer complete */
|
||||
.long DMA6_IRQHandler /* DMA channel 6 transfer complete */
|
||||
.long DMA7_IRQHandler /* DMA channel 7 transfer complete */
|
||||
.long DMA8_IRQHandler /* DMA channel 8 transfer complete */
|
||||
.long DMA9_IRQHandler /* DMA channel 9 transfer complete */
|
||||
.long DMA10_IRQHandler /* DMA channel 10 transfer complete */
|
||||
.long DMA11_IRQHandler /* DMA channel 11 transfer complete */
|
||||
.long DMA12_IRQHandler /* DMA channel 12 transfer complete */
|
||||
.long DMA13_IRQHandler /* DMA channel 13 transfer complete */
|
||||
.long DMA14_IRQHandler /* DMA channel 14 transfer complete */
|
||||
.long DMA15_IRQHandler /* DMA channel 15 transfer complete */
|
||||
.long DMA_Error_IRQHandler /* DMA error interrupt channels 0-31 */
|
||||
.long CPM_IRQHandler /* FPU etc. interrupt */
|
||||
.long FC_IRQHandler /* FC Command complete */
|
||||
.long PMC_IRQHandler /* HVD/LVD etc. interrupt */
|
||||
.long TMU_IRQHandler /* Temperature Monitor Unit interrupt */
|
||||
.long WDOG0_IRQHandler /* interrupt request out before wdg reset out */
|
||||
.long WDOG1_IRQHandler /* interrupt request out before wdg reset out */
|
||||
.long FCSMU0_IRQHandler /* Fault Control and Safety Manage Unit */
|
||||
.long STCU0_IRQHandler /* Safety Control Unit interrupt */
|
||||
.long ERM_fault_IRQHandler /* ERM single/double bit error correction */
|
||||
.long MAM0_IRQHandler /* Matrix Access Monitor interrupt */
|
||||
.long RGM_Pre_IRQHandler /* RGM pre-reset Interrupt */
|
||||
.long INTM0_IRQHandler /* INTM alarm interrupt */
|
||||
.long ISM0_IRQHandler /* ISM0 interrupt */
|
||||
.long MB_IRQHandler /* Mail Box interrupt */
|
||||
.long SCG_IRQHandler /* SCG bus interrupt request */
|
||||
.long CMU0_IRQHandler /* CMU0 interrupt */
|
||||
.long CMU1_IRQHandler /* CMU1 interrupt */
|
||||
.long CMU2_IRQHandler /* CMU2 interrupt */
|
||||
.long CMU3_IRQHandler /* CMU3 interrupt */
|
||||
.long CMU4_IRQHandler /* CMU4 interrupt */
|
||||
.long TSTMP0_IRQHandler /* TimerStamp0 interrupt */
|
||||
.long TSTMP1_IRQHandler /* TimerStamp1 interrupt */
|
||||
.long CORDIC_IRQHandler /* CORDIC Accelerator interrupt */
|
||||
.long HSM0_IRQHandler /* HSM error interrupt */
|
||||
.long FCPIT0_IRQHandler /* FCPIT0 interrupt */
|
||||
.long RTC_IRQHandler /* RTC alarm or seconds interrupt */
|
||||
.long AONTIMER_IRQHandler /* AONTIMER interrupt request */
|
||||
.long SWI_IRQHandler /* Software interrupt */
|
||||
.long FREQM_IRQHandler /* FREQM interrupt */
|
||||
.long ADC0_IRQHandler /* ADC0 interrupt request. */
|
||||
.long ADC1_IRQHandler /* ADC1 interrupt request. */
|
||||
.long PTIMER0_IRQHandler /* PTIMER0 interrupt */
|
||||
.long PTIMER1_IRQHandler /* PTIMER1 interrupt */
|
||||
.long CAN0_IRQHandler /* CAN0 Interrupt */
|
||||
.long CAN1_IRQHandler /* CAN1 Interrupt */
|
||||
.long CAN2_IRQHandler /* CAN2 Interrupt */
|
||||
.long CAN3_IRQHandler /* CAN3 Interrupt */
|
||||
.long FCIIC0_IRQHandler /* FCIIC0 Interrupt */
|
||||
.long FCIIC1_IRQHandler /* FCIIC1 Interrupt */
|
||||
.long FCSPI0_IRQHandler /* FCSPI0 Interrupt */
|
||||
.long FCSPI1_IRQHandler /* FCSPI1 Interrupt */
|
||||
.long FCSPI2_IRQHandler /* FCSPI2 Interrupt */
|
||||
.long FCSPI3_IRQHandler /* FCSPI3 Interrupt */
|
||||
.long FCSPI4_IRQHandler /* FCSPI4 Interrupt */
|
||||
.long FCSPI5_IRQHandler /* FCSPI5 Interrupt */
|
||||
.long FCUART0_RxTx_IRQHandler /* FCUART0 Transmit / Receive Interrupt */
|
||||
.long FCUART1_RxTx_IRQHandler /* FCUART1 Transmit / Receive Interrupt */
|
||||
.long FCUART2_RxTx_IRQHandler /* FCUART2 Transmit / Receive Interrupt */
|
||||
.long FCUART3_RxTx_IRQHandler /* FCUART3 Transmit / Receive Interrupt */
|
||||
.long FCUART4_RxTx_IRQHandler /* FCUART4 Transmit / Receive Interrupt */
|
||||
.long FCUART5_RxTx_IRQHandler /* FCUART5 Transmit / Receive Interrupt */
|
||||
.long FCUART6_RxTx_IRQHandler /* FCUART6 Transmit / Receive Interrupt */
|
||||
.long FCUART7_RxTx_IRQHandler /* FCUART7 Transmit / Receive Interrupt */
|
||||
.long FTU0_IRQHandler /* FTU0 all source interrupt */
|
||||
.long FTU1_IRQHandler /* FTU1 all source interrupt */
|
||||
.long FTU2_IRQHandler /* FTU2 all source interrupt */
|
||||
.long FTU3_IRQHandler /* FTU3 all source interrupt */
|
||||
.long FTU4_IRQHandler /* FTU4 all source interrupt */
|
||||
.long FTU5_IRQHandler /* FTU5 all source interrupt */
|
||||
.long FTU6_IRQHandler /* FTU6 all source interrupt */
|
||||
.long FTU7_IRQHandler /* FTU7 all source interrupt */
|
||||
.long CMP0_IRQHandler /* CMP0 interrupt request */
|
||||
.long CMP1_IRQHandler /* CMP1 interrupt request */
|
||||
.long PORTA_IRQHandler /* Port A pin detect interrupt */
|
||||
.long PORTB_IRQHandler /* Port B pin detect interrupt */
|
||||
.long PORTC_IRQHandler /* Port C pin detect interrupt */
|
||||
.long PORTD_IRQHandler /* Port D pin detect interrupt */
|
||||
.long PORTE_IRQHandler /* Port E pin detect interrupt */
|
||||
.long MSC0_IRQHandler /* MSC interrupt */
|
||||
.long SENT0_IRQHandler /* SENT all interrupt (fast or slow) */
|
||||
.long TPU0_CH0_7_IRQHandler /* TPU0 CH0-7 interrupt */
|
||||
.long TPU0_CH8_15_IRQHandler /* TPU0 CH8-15 interrupt */
|
||||
.long TPU0_CH16_23_IRQHandler /* TPU0 CH16-23 interrupt */
|
||||
.long TPU0_CH24_31_IRQHandler /* TPU0 CH24-31 interrupt */
|
||||
.long HSM0_CRYPTO_IRQHandler /* HSM crypto interrupt */
|
||||
.long DefaultISR /* 108 */
|
||||
.long DefaultISR /* 109 */
|
||||
.long DefaultISR /* 110 */
|
||||
.long DefaultISR /* 111 */
|
||||
.long DefaultISR /* 112 */
|
||||
.long DefaultISR /* 113 */
|
||||
.long DefaultISR /* 114 */
|
||||
.long DefaultISR /* 115 */
|
||||
.long DefaultISR /* 116 */
|
||||
.long DefaultISR /* 117 */
|
||||
.long DefaultISR /* 118 */
|
||||
.long DefaultISR /* 119 */
|
||||
.long DefaultISR /* 120 */
|
||||
.long DefaultISR /* 121 */
|
||||
.long DefaultISR /* 122 */
|
||||
.long DefaultISR /* 123 */
|
||||
.long DefaultISR /* 124 */
|
||||
.long DefaultISR /* 125 */
|
||||
.long DefaultISR /* 126 */
|
||||
.long DefaultISR /* 127 */
|
||||
.long DefaultISR /* 128 */
|
||||
.long DefaultISR /* 129 */
|
||||
.long DefaultISR /* 130 */
|
||||
.long DefaultISR /* 131 */
|
||||
.long DefaultISR /* 132 */
|
||||
.long DefaultISR /* 133 */
|
||||
.long DefaultISR /* 134 */
|
||||
.long DefaultISR /* 135 */
|
||||
.long DefaultISR /* 136 */
|
||||
.long DefaultISR /* 137 */
|
||||
.long DefaultISR /* 138 */
|
||||
.long DefaultISR /* 139 */
|
||||
.long DefaultISR /* 140 */
|
||||
.long DefaultISR /* 141 */
|
||||
.long DefaultISR /* 142 */
|
||||
.long DefaultISR /* 143 */
|
||||
.long DefaultISR /* 144 */
|
||||
.long DefaultISR /* 145 */
|
||||
.long DefaultISR /* 146 */
|
||||
.long DefaultISR /* 147 */
|
||||
.long DefaultISR /* 148 */
|
||||
.long DefaultISR /* 149 */
|
||||
.long DefaultISR /* 150 */
|
||||
.long DefaultISR /* 151 */
|
||||
.long DefaultISR /* 152 */
|
||||
.long DefaultISR /* 153 */
|
||||
.long DefaultISR /* 154 */
|
||||
.long DefaultISR /* 155 */
|
||||
.long DefaultISR /* 156 */
|
||||
.long DefaultISR /* 157 */
|
||||
.long DefaultISR /* 158 */
|
||||
.long DefaultISR /* 159 */
|
||||
.long DefaultISR /* 160 */
|
||||
.long DefaultISR /* 161 */
|
||||
.long DefaultISR /* 162 */
|
||||
.long DefaultISR /* 163 */
|
||||
.long DefaultISR /* 164 */
|
||||
.long DefaultISR /* 165 */
|
||||
.long DefaultISR /* 166 */
|
||||
.long DefaultISR /* 167 */
|
||||
.long DefaultISR /* 168 */
|
||||
.long DefaultISR /* 169 */
|
||||
.long DefaultISR /* 170 */
|
||||
.long DefaultISR /* 171 */
|
||||
.long DefaultISR /* 172 */
|
||||
.long DefaultISR /* 173 */
|
||||
.long DefaultISR /* 174 */
|
||||
.long DefaultISR /* 175 */
|
||||
.long DefaultISR /* 176 */
|
||||
.long DefaultISR /* 177 */
|
||||
.long DefaultISR /* 178 */
|
||||
.long DefaultISR /* 179 */
|
||||
.long DefaultISR /* 180 */
|
||||
.long DefaultISR /* 181 */
|
||||
.long DefaultISR /* 182 */
|
||||
.long DefaultISR /* 183 */
|
||||
.long DefaultISR /* 184 */
|
||||
.long DefaultISR /* 185 */
|
||||
.long DefaultISR /* 186 */
|
||||
.long DefaultISR /* 187 */
|
||||
.long DefaultISR /* 188 */
|
||||
.long DefaultISR /* 189 */
|
||||
.long DefaultISR /* 190 */
|
||||
.long DefaultISR /* 191 */
|
||||
.long DefaultISR /* 192 */
|
||||
.long DefaultISR /* 193 */
|
||||
.long DefaultISR /* 194 */
|
||||
.long DefaultISR /* 195 */
|
||||
.long DefaultISR /* 196 */
|
||||
.long DefaultISR /* 197 */
|
||||
.long DefaultISR /* 198 */
|
||||
.long DefaultISR /* 199 */
|
||||
.long DefaultISR /* 200 */
|
||||
.long DefaultISR /* 201 */
|
||||
.long DefaultISR /* 202 */
|
||||
.long DefaultISR /* 203 */
|
||||
.long DefaultISR /* 204 */
|
||||
.long DefaultISR /* 205 */
|
||||
.long DefaultISR /* 206 */
|
||||
.long DefaultISR /* 207 */
|
||||
.long DefaultISR /* 208 */
|
||||
.long DefaultISR /* 209 */
|
||||
.long DefaultISR /* 210 */
|
||||
.long DefaultISR /* 211 */
|
||||
.long DefaultISR /* 212 */
|
||||
.long DefaultISR /* 213 */
|
||||
.long DefaultISR /* 214 */
|
||||
.long DefaultISR /* 215 */
|
||||
.long DefaultISR /* 216 */
|
||||
.long DefaultISR /* 217 */
|
||||
.long DefaultISR /* 218 */
|
||||
.long DefaultISR /* 219 */
|
||||
.long DefaultISR /* 220 */
|
||||
.long DefaultISR /* 221 */
|
||||
.long DefaultISR /* 222 */
|
||||
.long DefaultISR /* 223 */
|
||||
.long DefaultISR /* 224 */
|
||||
.long DefaultISR /* 225 */
|
||||
.long DefaultISR /* 226 */
|
||||
.long DefaultISR /* 227 */
|
||||
.long DefaultISR /* 228 */
|
||||
.long DefaultISR /* 229 */
|
||||
.long DefaultISR /* 230 */
|
||||
.long DefaultISR /* 231 */
|
||||
.long DefaultISR /* 232 */
|
||||
.long DefaultISR /* 233 */
|
||||
.long DefaultISR /* 234 */
|
||||
.long DefaultISR /* 235 */
|
||||
.long DefaultISR /* 236 */
|
||||
.long DefaultISR /* 237 */
|
||||
.long DefaultISR /* 238 */
|
||||
.long DefaultISR /* 239 */
|
||||
.long DefaultISR /* 240 */
|
||||
.long DefaultISR /* 241 */
|
||||
.long DefaultISR /* 242 */
|
||||
.long DefaultISR /* 243 */
|
||||
.long DefaultISR /* 244 */
|
||||
.long DefaultISR /* 245 */
|
||||
.long DefaultISR /* 246 */
|
||||
.long DefaultISR /* 247 */
|
||||
.long DefaultISR /* 248 */
|
||||
.long DefaultISR /* 249 */
|
||||
.long DefaultISR /* 250 */
|
||||
.long DefaultISR /* 251 */
|
||||
.long DefaultISR /* 252 */
|
||||
.long DefaultISR /* 253 */
|
||||
.long DefaultISR /* 254 */
|
||||
.long 0xFFFFFFFF /* Reserved for user TRIM value */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
|
||||
/**************************************************************/
|
||||
/************************ set other ***************************/
|
||||
.text
|
||||
.thumb
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
|
||||
Reset_Handler:
|
||||
cpsid i /* Mask interrupts */
|
||||
|
||||
/* Init the rest of the registers */
|
||||
ldr r1,=0
|
||||
ldr r2,=0
|
||||
ldr r3,=0
|
||||
ldr r4,=0
|
||||
ldr r5,=0
|
||||
ldr r6,=0
|
||||
ldr r7,=0
|
||||
mov r8,r7
|
||||
mov r9,r7
|
||||
mov r10,r7
|
||||
mov r11,r7
|
||||
mov r12,r7
|
||||
|
||||
ldr r0, =0xE000ED08
|
||||
ldr r1, =__vector_table
|
||||
str r1, [r0]
|
||||
|
||||
/* Initialize the stack pointer */
|
||||
ldr r0,=__StackTop
|
||||
mov sp,r0 ; sp=r13
|
||||
|
||||
/* Clear Stack */
|
||||
ldr r2, =__StackLimit
|
||||
ldr r4, =__StackTop
|
||||
movs r3, #0
|
||||
b LoopFillZero_STACK
|
||||
|
||||
FillZero_STACK:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZero_STACK:
|
||||
cmp r2, r4
|
||||
bcc FillZero_STACK
|
||||
|
||||
/* System Initialization */
|
||||
ldr r0,=System_Init
|
||||
blx r0
|
||||
|
||||
/* Initialize .data and .bss sections */
|
||||
ldr r0,=Data_Init
|
||||
blx r0
|
||||
|
||||
cpsie i /* Unmask interrupts */
|
||||
bl main
|
||||
JumpToSelf:
|
||||
b JumpToSelf
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DefaultISR
|
||||
.type DefaultISR, %function
|
||||
DefaultISR:
|
||||
b DefaultISR
|
||||
.size DefaultISR, . - DefaultISR
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, DefaultISR
|
||||
.endm
|
||||
|
||||
/* Exception Handlers */
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler DMA0_IRQHandler
|
||||
def_irq_handler DMA1_IRQHandler
|
||||
def_irq_handler DMA2_IRQHandler
|
||||
def_irq_handler DMA3_IRQHandler
|
||||
def_irq_handler DMA4_IRQHandler
|
||||
def_irq_handler DMA5_IRQHandler
|
||||
def_irq_handler DMA6_IRQHandler
|
||||
def_irq_handler DMA7_IRQHandler
|
||||
def_irq_handler DMA8_IRQHandler
|
||||
def_irq_handler DMA9_IRQHandler
|
||||
def_irq_handler DMA10_IRQHandler
|
||||
def_irq_handler DMA11_IRQHandler
|
||||
def_irq_handler DMA12_IRQHandler
|
||||
def_irq_handler DMA13_IRQHandler
|
||||
def_irq_handler DMA14_IRQHandler
|
||||
def_irq_handler DMA15_IRQHandler
|
||||
def_irq_handler DMA_Error_IRQHandler
|
||||
def_irq_handler CPM_IRQHandler
|
||||
def_irq_handler FC_IRQHandler
|
||||
def_irq_handler PMC_IRQHandler
|
||||
def_irq_handler TMU_IRQHandler
|
||||
def_irq_handler WDOG0_IRQHandler
|
||||
def_irq_handler WDOG1_IRQHandler
|
||||
def_irq_handler FCSMU0_IRQHandler
|
||||
def_irq_handler STCU0_IRQHandler
|
||||
def_irq_handler ERM_fault_IRQHandler
|
||||
def_irq_handler MAM0_IRQHandler
|
||||
def_irq_handler RGM_Pre_IRQHandler
|
||||
def_irq_handler INTM0_IRQHandler
|
||||
def_irq_handler ISM0_IRQHandler
|
||||
def_irq_handler MB_IRQHandler
|
||||
def_irq_handler SCG_IRQHandler
|
||||
def_irq_handler CMU0_IRQHandler
|
||||
def_irq_handler CMU1_IRQHandler
|
||||
def_irq_handler CMU2_IRQHandler
|
||||
def_irq_handler CMU3_IRQHandler
|
||||
def_irq_handler CMU4_IRQHandler
|
||||
def_irq_handler TSTMP0_IRQHandler
|
||||
def_irq_handler TSTMP1_IRQHandler
|
||||
def_irq_handler CORDIC_IRQHandler
|
||||
def_irq_handler HSM0_IRQHandler
|
||||
def_irq_handler FCPIT0_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
def_irq_handler AONTIMER_IRQHandler
|
||||
def_irq_handler SWI_IRQHandler
|
||||
def_irq_handler FREQM_IRQHandler
|
||||
def_irq_handler ADC0_IRQHandler
|
||||
def_irq_handler ADC1_IRQHandler
|
||||
def_irq_handler PTIMER0_IRQHandler
|
||||
def_irq_handler PTIMER1_IRQHandler
|
||||
def_irq_handler CAN0_IRQHandler
|
||||
def_irq_handler CAN1_IRQHandler
|
||||
def_irq_handler CAN2_IRQHandler
|
||||
def_irq_handler CAN3_IRQHandler
|
||||
def_irq_handler FCIIC0_IRQHandler
|
||||
def_irq_handler FCIIC1_IRQHandler
|
||||
def_irq_handler FCSPI0_IRQHandler
|
||||
def_irq_handler FCSPI1_IRQHandler
|
||||
def_irq_handler FCSPI2_IRQHandler
|
||||
def_irq_handler FCSPI3_IRQHandler
|
||||
def_irq_handler FCSPI4_IRQHandler
|
||||
def_irq_handler FCSPI5_IRQHandler
|
||||
def_irq_handler FCUART0_RxTx_IRQHandler
|
||||
def_irq_handler FCUART1_RxTx_IRQHandler
|
||||
def_irq_handler FCUART2_RxTx_IRQHandler
|
||||
def_irq_handler FCUART3_RxTx_IRQHandler
|
||||
def_irq_handler FCUART4_RxTx_IRQHandler
|
||||
def_irq_handler FCUART5_RxTx_IRQHandler
|
||||
def_irq_handler FCUART6_RxTx_IRQHandler
|
||||
def_irq_handler FCUART7_RxTx_IRQHandler
|
||||
def_irq_handler FTU0_IRQHandler
|
||||
def_irq_handler FTU1_IRQHandler
|
||||
def_irq_handler FTU2_IRQHandler
|
||||
def_irq_handler FTU3_IRQHandler
|
||||
def_irq_handler FTU4_IRQHandler
|
||||
def_irq_handler FTU5_IRQHandler
|
||||
def_irq_handler FTU6_IRQHandler
|
||||
def_irq_handler FTU7_IRQHandler
|
||||
def_irq_handler CMP0_IRQHandler
|
||||
def_irq_handler CMP1_IRQHandler
|
||||
def_irq_handler PORTA_IRQHandler
|
||||
def_irq_handler PORTB_IRQHandler
|
||||
def_irq_handler PORTC_IRQHandler
|
||||
def_irq_handler PORTD_IRQHandler
|
||||
def_irq_handler PORTE_IRQHandler
|
||||
def_irq_handler MSC0_IRQHandler
|
||||
def_irq_handler SENT0_IRQHandler
|
||||
def_irq_handler TPU0_CH0_7_IRQHandler
|
||||
def_irq_handler TPU0_CH8_15_IRQHandler
|
||||
def_irq_handler TPU0_CH16_23_IRQHandler
|
||||
def_irq_handler TPU0_CH24_31_IRQHandler
|
||||
def_irq_handler HSM0_CRYPTO_IRQHandler
|
||||
.end
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
#if (defined(__ICCARM__))
|
||||
|
||||
#elif defined(__ARMCC_VERSION)
|
||||
|
||||
#elif defined __GNUC__
|
||||
#include "sys/types.h"
|
||||
#include "sys/stat.h"
|
||||
#endif
|
||||
|
||||
static uint32_t s_u32Current_heap_end;
|
||||
|
||||
#if (defined(__ICCARM__))
|
||||
extern uint32_t __HeapBegin[1]; // Defined by the linker.
|
||||
extern uint32_t __HeapLimit[1]; // Defined by the linker.
|
||||
#elif defined __GNUC__
|
||||
extern uint32_t __HeapBegin[1]; // Defined by the linker.
|
||||
extern uint32_t __HeapLimit[1]; // Defined by the linker.
|
||||
#endif
|
||||
|
||||
|
||||
#if (defined(__ICCARM__))
|
||||
/**
|
||||
* TODO: something can be done to make sure the start address used in heap is defined heap start
|
||||
*/
|
||||
#elif defined(__ARMCC_VERSION)
|
||||
|
||||
#elif defined __GNUC__
|
||||
extern caddr_t _sbrk(int incr);
|
||||
|
||||
/**
|
||||
* \brief Replacement of C library of _sbrk
|
||||
*/
|
||||
caddr_t _sbrk(int incr)
|
||||
{
|
||||
if (s_u32Current_heap_end == 0U)
|
||||
{
|
||||
#if (defined(__ICCARM__))
|
||||
s_u32Current_heap_end = (uint32_t)__HeapBegin;
|
||||
#elif defined __GNUC__
|
||||
s_u32Current_heap_end = (uint32_t)__HeapBegin;
|
||||
#endif
|
||||
}
|
||||
|
||||
// Need to align heap to word boundary, else will get
|
||||
// hard faults on Cortex-M0. So we assume that heap starts on
|
||||
// word boundary, hence make sure we always add a multiple of
|
||||
// 4 to it.
|
||||
incr = (incr + 3) & (~3); // align value to 4
|
||||
#if (defined(__ICCARM__))
|
||||
if ( (s_u32Current_heap_end + incr) > (uint32_t)__HeapLimit )
|
||||
#elif defined __GNUC__
|
||||
if ( (s_u32Current_heap_end + incr) > (uint32_t)__HeapLimit )
|
||||
#endif
|
||||
{
|
||||
// Some of the libstdc++-v3 tests rely upon detecting
|
||||
// out of memory errors, so do not abort here.
|
||||
#if 0
|
||||
extern void abort(void);
|
||||
|
||||
_write(1, "_sbrk: Heap and stack collision\n", 32);
|
||||
|
||||
abort();
|
||||
#else
|
||||
return (caddr_t) - 1;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
s_u32Current_heap_end+= incr;
|
||||
}
|
||||
|
||||
return (caddr_t) s_u32Current_heap_end;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
* @file system_init.c
|
||||
* @author Flagchip
|
||||
* @brief interrupt configuration
|
||||
* @version 0.1.0
|
||||
* @date 2024-01-12
|
||||
*
|
||||
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/* ********************************************************************************
|
||||
* Revision History:
|
||||
*
|
||||
* Version Date Author Descriptions
|
||||
* --------- ---------- ------------ ---------------
|
||||
* 0.1.0 2024-01-12 Flagchip038 First version for gcc, iar, keil, ghs data init
|
||||
******************************************************************************** */
|
||||
|
||||
|
||||
#include "system_init.h"
|
||||
#include "fc7xxx_driver_fpu.h"
|
||||
|
||||
static void data_clear(uint32_t u32StartAddr, uint32_t u32EndAddr);
|
||||
static void data_copy(uint32_t u32SourceAddr, uint32_t u32DestAddr, uint32_t u32DestEndAddr);
|
||||
|
||||
/**
|
||||
* \brief System Initialization
|
||||
*
|
||||
*/
|
||||
void System_Init(void)
|
||||
{
|
||||
/* disable wdog 0 */
|
||||
*(volatile uint32 *)0x40022004 = 0x08181982;
|
||||
while (0U == (0x800u & *(volatile uint32 *)0x40022000));
|
||||
*(volatile uint32 *)0x40022000 = 0x2920;
|
||||
*(volatile uint32 *)0x40022008 = 0xF000;
|
||||
while (0U == (0x400u & *(volatile uint32 *)0x40022000));
|
||||
|
||||
/* disable wdog 1 */
|
||||
*(volatile uint32 *)0x40433004 = 0x08181982;
|
||||
while (0U == (0x800u & *(volatile uint32 *)0x40433000));
|
||||
*(volatile uint32 *)0x40433000 = 0x2920;
|
||||
*(volatile uint32 *)0x40433008 = 0xF000;
|
||||
while (0U == (0x400u & *(volatile uint32 *)0x40433000));
|
||||
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
FPU_Enable(); /* Enable FPU */
|
||||
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
|
||||
|
||||
}
|
||||
|
||||
void Data_Init(void)
|
||||
{
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
extern uint32_t Load$$RW_m_dtcm$$Base;
|
||||
extern uint32_t Image$$RW_m_dtcm$$Base;
|
||||
extern uint32_t Image$$RW_m_dtcm$$Limit;
|
||||
|
||||
extern uint32_t Image$$RW_m_dtcm$$ZI$$Limit;
|
||||
extern uint32_t Image$$RW_m_dtcm$$ZI$$Base;
|
||||
|
||||
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base;
|
||||
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Limit;
|
||||
|
||||
/* data/bss/heap clear */
|
||||
data_clear((uint32_t)&Image$$RW_m_dtcm$$Base, (uint32_t)&Image$$RW_m_dtcm$$Limit);
|
||||
data_clear((uint32_t)&Image$$RW_m_dtcm$$ZI$$Base, (uint32_t)&Image$$RW_m_dtcm$$ZI$$Limit);
|
||||
data_clear((uint32_t)&Image$$ARM_LIB_HEAP$$ZI$$Base, (uint32_t)&Image$$ARM_LIB_HEAP$$ZI$$Limit);
|
||||
|
||||
/* data */
|
||||
data_copy((uint32_t)&Load$$RW_m_dtcm$$Base, (uint32_t)&Image$$RW_m_dtcm$$Base, (uint32_t)&Image$$RW_m_dtcm$$Limit);
|
||||
|
||||
#elif defined(__GNUC__) || defined(__ghs__)
|
||||
extern uint32 __rom_data_start[];
|
||||
extern uint32 __ram_data_start[];
|
||||
extern uint32 __ram_data_end[];
|
||||
extern uint32 __bss_start[];
|
||||
extern uint32 __bss_end[];
|
||||
extern uint32 __rom_ncache_data_start[];
|
||||
extern uint32 __ram_ncache_data_start[];
|
||||
extern uint32 __ram_ncache_data_end[];
|
||||
extern uint32 __ncache_bss_start[];
|
||||
extern uint32 __ncache_bss_end[];
|
||||
|
||||
extern uint32_t __itcm_start[];
|
||||
extern uint32_t __itcm_end[];
|
||||
|
||||
|
||||
extern uint32_t __xcp_start[];
|
||||
extern uint32_t __xcp_end[];
|
||||
|
||||
|
||||
/* data clear */
|
||||
data_clear((uint32_t)__ram_data_start, (uint32_t)__ram_data_end);
|
||||
data_clear((uint32_t)__bss_start, (uint32_t)__bss_end);
|
||||
data_clear((uint32_t)__ram_ncache_data_start, (uint32_t)__ram_ncache_data_end);
|
||||
data_clear((uint32_t)__ncache_bss_start, (uint32_t)__ncache_bss_end);
|
||||
|
||||
data_clear((uint32_t)__itcm_start, (uint32_t)__itcm_end);
|
||||
data_clear((uint32_t)__xcp_start, (uint32_t)__xcp_end);
|
||||
|
||||
/* data copy */
|
||||
data_copy((uint32_t)__rom_data_start, (uint32_t)__ram_data_start, (uint32_t)__ram_data_end);
|
||||
data_copy((uint32_t)__rom_ncache_data_start, (uint32_t)__ram_ncache_data_start, (uint32_t)__ram_ncache_data_end);
|
||||
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma section=".data"
|
||||
#pragma section=".data_init"
|
||||
#pragma section=".ncsram"
|
||||
#pragma section=".ncsram_init"
|
||||
#pragma section=".bss"
|
||||
#pragma section="RAM_VECTOR"
|
||||
#pragma section=".intvec"
|
||||
|
||||
data_clear((uint32_t)__section_begin(".bss"), (uint32_t)__section_end(".bss"));
|
||||
|
||||
data_copy((uint32_t)__section_begin(".data_init"), (uint32_t)__section_begin(".data"), (uint32_t)__section_end(".data"));
|
||||
|
||||
data_copy((uint32_t)__section_begin(".ncsram_init"), (uint32_t)__section_begin(".ncsram"), (uint32_t)__section_end(".ncsram"));
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/* to avoid ecc issue, FC7240 clear ram with 64bits once after power on reset */
|
||||
static void data_clear(uint32_t u32StartAddr, uint32_t u32EndAddr)
|
||||
{
|
||||
/* 64 bits align */
|
||||
uint32_t u32AlignStart = u32StartAddr & 0xFFFFFFF8;
|
||||
uint32_t u32AlignEnd = (u32EndAddr - u32AlignStart);
|
||||
volatile uint64_t *pData = (uint64_t *)u32AlignStart;
|
||||
|
||||
/* 32 word Align */
|
||||
uint32_t u32LeftCount = u32AlignEnd & 0x1Fu;
|
||||
u32AlignEnd = u32EndAddr - u32LeftCount;
|
||||
|
||||
while ((uint32_t)pData < u32AlignEnd)
|
||||
{
|
||||
*pData++ = 0u;
|
||||
*pData++ = 0u;
|
||||
*pData++ = 0u;
|
||||
*pData++ = 0u;
|
||||
}
|
||||
|
||||
while ((uint32_t)pData < u32EndAddr)
|
||||
{
|
||||
*pData++ = 0u;
|
||||
}
|
||||
}
|
||||
|
||||
static void data_copy(uint32_t u32SourceAddr, uint32_t u32DestAddr, uint32_t u32DestEndAddr)
|
||||
{
|
||||
uint32_t *pSource = (uint32_t *)u32SourceAddr;
|
||||
uint32_t *pDest = (uint32_t *)u32DestAddr;
|
||||
|
||||
while ((uint32_t)pDest < u32DestEndAddr)
|
||||
{
|
||||
*pDest = *pSource;
|
||||
pDest++;
|
||||
pSource++;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/**
|
||||
* @file system_init.h
|
||||
* @author Flagchip
|
||||
* @brief interrupt configuration
|
||||
* @version 0.1.0
|
||||
* @date 2024-01-12
|
||||
*
|
||||
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
|
||||
*
|
||||
*/
|
||||
#if !defined(SYSTEM_INIT_H)
|
||||
#define SYSTEM_INIT_H
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
|
||||
#include "device_header.h"
|
||||
|
||||
void System_Init(void);
|
||||
|
||||
void Data_Init(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
|
||||
|
||||
#endif /* SYSTEM_INIT_H */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
.cals_data(NOLOAD) :
|
||||
{
|
||||
__itcm_start = .;
|
||||
|
||||
/* Резервируем ровно 20K для .caldata */
|
||||
.caldata : {
|
||||
KEEP(*(.caldata))
|
||||
. = ALIGN(4);
|
||||
} > ITCM
|
||||
|
||||
/* Проверяем размер и заполняем до 20K */
|
||||
__caldata_end = .;
|
||||
__caldata_start = ADDR(.caldata);
|
||||
__caldata_size = SIZEOF(.caldata);
|
||||
|
||||
/* Если .caldata меньше 20K, добавляем пустое пространство */
|
||||
. = __caldata_start + 20K;
|
||||
|
||||
/* Проверяем, что не превысили размер */
|
||||
ASSERT((. - __caldata_start) >= 20K, "Зарезервировано менее 20K для .caldata");
|
||||
ASSERT(__caldata_size <= 20K, "Раздел .caldata превышает 20K!");
|
||||
|
||||
KEEP(*(.nvmdata))
|
||||
. = ALIGN(4);
|
||||
*Model_actuator.c.obj(.bss .bss*)
|
||||
__itcm_end = .;
|
||||
. = ALIGN(4);
|
||||
} > ITCM
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
#-- Service --------------------------------------------------------------------
|
||||
SET(CMAKE_TOOLCHAIN_FILE ${CMAKE_SOURCE_DIR}/MODULES/CmakeConfig_GCC_CortexM7/gcc_cm7f.cmake)
|
||||
ENABLE_LANGUAGE(ASM)
|
||||
CMAKE_MINIMUM_REQUIRED(VERSION 3.8.0)
|
||||
|
||||
set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O0")
|
||||
set(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -O0")
|
||||
|
||||
IF (${CMAKE_SOURCE_DIR} STREQUAL ${CMAKE_BINARY_DIR})
|
||||
MESSAGE(
|
||||
FATAL_ERROR
|
||||
"In-source builds not allowed.
|
||||
Please make a new directory (called a build directory) and run CMake from there.
|
||||
You may need to remove CMakeCache.txt."
|
||||
)
|
||||
ENDIF ()
|
||||
|
||||
SET(CMAKE_EXPORT_COMPILE_COMMANDS ON)
|
||||
#-- Project config -------------------------------------------------------------
|
||||
PROJECT(HVAC_M7) # Project name
|
||||
|
||||
|
||||
SET(INTERNAL_HW_YEAR 26)
|
||||
SET(INTERNAL_HW_MONTH 8)
|
||||
SET(INTERNAL_HW_DAY 19)
|
||||
SET(INTERNAL_HW_REV 1)
|
||||
|
||||
SET(INTERNAL_SW_YEAR 26)
|
||||
SET(INTERNAL_SW_MONTH 8)
|
||||
SET(INTERNAL_SW_DAY 18)
|
||||
SET(INTERNAL_SW_REV 3)
|
||||
|
||||
SET(INTERNAL_MDB_YEAR 26)
|
||||
SET(INTERNAL_MDB_MONTH 8)
|
||||
SET(INTERNAL_MDB_DAY 21)
|
||||
SET(INTERNAL_MDB_REV 6)
|
||||
|
||||
SET(FINGER_MODULE 0x01)
|
||||
SET(FINGER_YEAR 0x26)
|
||||
SET(FINGER_MONTH 0x08)
|
||||
SET(FINGER_DAY 0x16)
|
||||
SET(FINGER_TESTER_SERIAL \"M\")
|
||||
|
||||
|
||||
SET(VECT_TAB_OFFSET "0x00000")
|
||||
|
||||
|
||||
|
||||
#-- Defines --------------------------------------------------------------------
|
||||
|
||||
|
||||
ADD_DEFINITIONS(-DINTERNAL_HW_YEAR=${INTERNAL_HW_YEAR})
|
||||
ADD_DEFINITIONS(-DINTERNAL_HW_MONTH=${INTERNAL_HW_MONTH})
|
||||
ADD_DEFINITIONS(-DINTERNAL_HW_DAY=${INTERNAL_HW_DAY})
|
||||
ADD_DEFINITIONS(-DINTERNAL_HW_REV=${INTERNAL_HW_REV})
|
||||
|
||||
ADD_DEFINITIONS(-DINTERNAL_SW_YEAR=${INTERNAL_SW_YEAR})
|
||||
ADD_DEFINITIONS(-DINTERNAL_SW_MONTH=${INTERNAL_SW_MONTH})
|
||||
ADD_DEFINITIONS(-DINTERNAL_SW_DAY=${INTERNAL_SW_DAY})
|
||||
ADD_DEFINITIONS(-DINTERNAL_SW_REV=${INTERNAL_SW_REV})
|
||||
|
||||
ADD_DEFINITIONS(-DINTERNAL_MDB_YEAR=${INTERNAL_MDB_YEAR})
|
||||
ADD_DEFINITIONS(-DINTERNAL_MDB_MONTH=${INTERNAL_MDB_MONTH})
|
||||
ADD_DEFINITIONS(-DINTERNAL_MDB_DAY=${INTERNAL_MDB_DAY})
|
||||
ADD_DEFINITIONS(-DINTERNAL_MDB_REV=${INTERNAL_MDB_REV})
|
||||
|
||||
ADD_DEFINITIONS(-DFINGER_MODULE=${FINGER_MODULE})
|
||||
ADD_DEFINITIONS(-DFINGER_YEAR=${FINGER_YEAR})
|
||||
ADD_DEFINITIONS(-DFINGER_MONTH=${FINGER_MONTH})
|
||||
ADD_DEFINITIONS(-DFINGER_DAY=${FINGER_DAY})
|
||||
ADD_DEFINITIONS(-DFINGER_TESTER_SERIAL=${FINGER_TESTER_SERIAL})
|
||||
|
||||
ADD_DEFINITIONS(-DUSING_OS_FREERTOS)
|
||||
|
||||
ADD_DEFINITIONS(-DVERSION_SEDANL_Y=25)
|
||||
ADD_DEFINITIONS(-DVERSION_SEDANL_M=10)
|
||||
ADD_DEFINITIONS(-DVERSION_SEDANL_D=29)
|
||||
|
||||
ADD_DEFINITIONS(-DVERSION_SEDANH_Y=25)
|
||||
ADD_DEFINITIONS(-DVERSION_SEDANH_M=10)
|
||||
ADD_DEFINITIONS(-DVERSION_SEDANH_D=29)
|
||||
|
||||
ADD_DEFINITIONS(-DVERSION_LIMO_Y=25)
|
||||
ADD_DEFINITIONS(-DVERSION_LIMO_M=10)
|
||||
ADD_DEFINITIONS(-DVERSION_LIMO_D=29)
|
||||
|
||||
ADD_DEFINITIONS(-DVERSION_SUV_Y=25)
|
||||
ADD_DEFINITIONS(-DVERSION_SUV_M=10)
|
||||
ADD_DEFINITIONS(-DVERSION_SUV_D=29)
|
||||
|
||||
ADD_DEFINITIONS(-DVERSION_MPV_Y=25)
|
||||
ADD_DEFINITIONS(-DVERSION_MPV_M=10)
|
||||
ADD_DEFINITIONS(-DVERSION_MPV_D=29)
|
||||
|
||||
ADD_DEFINITIONS(-DVECT_TAB_OFFSET=${VECT_TAB_OFFSET})
|
||||
ADD_DEFINITIONS(-DHEXT_VALUE=${HEXT_VALUE})
|
||||
ADD_DEFINITIONS(-DCMSIS_device_header="interrupt_manager.h")
|
||||
|
||||
ADD_DEFINITIONS(-DFLASH_PAGE_D_SIZE=2048)
|
||||
ADD_DEFINITIONS(-DFLASH_PAGE_P_SIZE=4096)
|
||||
ADD_DEFINITIONS(-DCOM_INT_BIG_BUFFERS)
|
||||
ADD_DEFINITIONS(-DVARIABLE_TABLE_WITH_ID)
|
||||
ADD_DEFINITIONS(-DLFS_THREADSAFE=1)
|
||||
ADD_DEFINITIONS(-DHALF_DUPLEX_NO_DELAY=1)
|
||||
ADD_DEFINITIONS(-DACCESS_ADC=1)
|
||||
ADD_DEFINITIONS(-DACCESS_RTC=1)
|
||||
ADD_DEFINITIONS(-DSTORAGE_ARTERY_CHECK_CLEAR=1)
|
||||
|
||||
#ADD_DEFINITIONS(-DSTORAGE_ARTERY_CHECK_WRITE_SECTORS=1) # Включение записи по секторам (Тестово, закоментированно)
|
||||
|
||||
#-- Project paths, Include dirs, Sources list ---------------------------------
|
||||
#ADD_FILES(SOURCES "MODULES/DeviceStartup_ARTERY_AT32F437ZMT7/ld/startup_at32f435_437.s")
|
||||
include(modular.cmake)
|
||||
|
||||
|
||||
#-- Options --------------------------------------------------------------------
|
||||
#IF (PRINTF_FLOAT STREQUAL "1")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -u_printf_float")
|
||||
#ENDIF ()
|
||||
IF (SCANF_FLOAT STREQUAL "1")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -u_scanf_float")
|
||||
ENDIF ()
|
||||
|
||||
#-- Linker script --------------------------------------------------------------
|
||||
SET(LDSCRIPT ${CMAKE_SOURCE_DIR}/APP/FC7240_flash.ld)
|
||||
SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T ${LDSCRIPT} -Wl,-Map=${CMAKE_BINARY_DIR}/${PROJECT_NAME}.map -Wl,--print-memory-usage")
|
||||
|
||||
#-- Random BuildId Generation ------------------------------------------------------------
|
||||
SET(RANDOM_BUILD_ID_GEN_FILE ${CMAKE_SOURCE_DIR}/MODULES/CmakeConfig_RandomBuildIdGenerator/version.cmake)
|
||||
add_custom_target(GEN_RANDOM_BUILD_ID)
|
||||
ADD_CUSTOM_COMMAND(TARGET GEN_RANDOM_BUILD_ID POST_BUILD
|
||||
COMMAND ${CMAKE_COMMAND} -P ${RANDOM_BUILD_ID_GEN_FILE})
|
||||
|
||||
#-- Project linking ------------------------------------------------------------
|
||||
ADD_EXECUTABLE(${PROJECT_NAME}.elf ${SOURCES})
|
||||
TARGET_LINK_LIBRARIES(${PROJECT_NAME}.elf m)
|
||||
add_dependencies(${PROJECT_NAME}.elf GEN_RANDOM_BUILD_ID)
|
||||
|
||||
#-- Custom commands ------------------------------------------------------------
|
||||
ADD_CUSTOM_COMMAND(TARGET ${PROJECT_NAME}.elf POST_BUILD
|
||||
COMMAND ${CMAKE_OBJCOPY} "-Oihex" ${PROJECT_NAME}.elf ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.hex
|
||||
COMMAND ${CMAKE_OBJCOPY} "-Obinary" ${PROJECT_NAME}.elf ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.bin
|
||||
# COMMAND ${CMAKE_OBJDUMP} "-DS" ${PROJECT_NAME}.elf > ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.dasm
|
||||
COMMAND ${CMAKE_SIZE} ${PROJECT_NAME}.elf)
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
//
|
||||
// Created by cfif on 11.09.22.
|
||||
//
|
||||
|
||||
#ifndef ADC_H
|
||||
#define ADC_H
|
||||
|
||||
#include "AdcIO.h"
|
||||
|
||||
uint8_t AdcGet(tAdcIO *io, uint32_t *buf, uint32_t timeout);
|
||||
|
||||
#endif //ADC_H
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
//
|
||||
// Created by cfif on 17.11.22.
|
||||
//
|
||||
|
||||
#include "Adc.h"
|
||||
#include "SystemDelayInterface.h"
|
||||
|
||||
uint8_t AdcGet(tAdcIO *io, uint32_t *buf, uint32_t timeout) {
|
||||
return io->get(io->env, buf, timeout);
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
{
|
||||
"dep": [
|
||||
{
|
||||
"type": "local",
|
||||
|
||||
"dir": "./MODULES/AdcInterface"
|
||||
}
|
||||
],
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
],
|
||||
"srcs": [
|
||||
"Src/**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
//
|
||||
// Created by cfif on 17.11.22.
|
||||
//
|
||||
|
||||
#ifndef MODULE_ADCIO_H
|
||||
#define MODULE_ADCIO_H
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
typedef uint32_t (*AdcIOTransaction )(void *env, uint32_t *buf, uint32_t timeout);
|
||||
|
||||
typedef struct {
|
||||
void *env;
|
||||
AdcIOTransaction get;
|
||||
} tAdcIO;
|
||||
|
||||
|
||||
#endif //MODULE_ADCIO_H
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
{
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
//
|
||||
// Created by cfif on 17.11.22.
|
||||
//
|
||||
|
||||
#ifndef ADC_FLAGCHIP_H
|
||||
#define ADC_FLAGCHIP_H
|
||||
|
||||
#include "Adc.h"
|
||||
#include "cmsis_os2.h"
|
||||
#include "fc7xxx_driver_adc.h"
|
||||
#include "fc7xxx_driver_pcc.h"
|
||||
#include "interrupt_manager.h"
|
||||
|
||||
typedef struct {
|
||||
ADC_InstanceType ADCx;
|
||||
uint8_t num_aChannels;
|
||||
uint32_t *DMA_BUF;
|
||||
|
||||
int32_t offset;
|
||||
double mux;
|
||||
double div;
|
||||
|
||||
osMessageQueueId_t txAccessQueue;
|
||||
|
||||
ADC_InitType s_tAdcInitCfg;
|
||||
ADC_DmaType s_tAdcDmaCfg;
|
||||
|
||||
float pVoltageBuffer[32];
|
||||
|
||||
} tAdcFlagchip;
|
||||
|
||||
void ADC_Initial(
|
||||
tAdcFlagchip *env,
|
||||
|
||||
ADC_InstanceType ADCx, // ADC_INSTANCE_0, ADC_INSTANCE_1
|
||||
|
||||
DMA_ChannelType ADC_DMA_CHANNEL, // DMA_CHANNEL_0 .. DMA_CHANNEL_15
|
||||
|
||||
IRQn_Type IRQ_DMA,
|
||||
uint8_t IRQ_DMA_PRIORITY,
|
||||
uint8_t IRQ_DMA_CHANNEL_PRIORITY,
|
||||
|
||||
const uint32_t *DMA_BUF,
|
||||
|
||||
uint8_t num_aChannels,
|
||||
ADC_ChannelCfgType *s_aChannels,
|
||||
|
||||
int32_t offset,
|
||||
double mux,
|
||||
double div,
|
||||
|
||||
ADC_ConvCompleteCallbackType Bsp_ADC_HandleResult
|
||||
);
|
||||
|
||||
tAdcIO vAdcGetIo(tAdcFlagchip *env);
|
||||
void Get_ADC_Result(tAdcFlagchip *env);
|
||||
|
||||
#endif //ADC_FLAGCHIP_H
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
//
|
||||
// Created by cfif on 07.09.22.
|
||||
//
|
||||
#include <SystemDelayInterface.h>
|
||||
#include "AdcFlagchip.h"
|
||||
|
||||
#define VREF 5.0F
|
||||
|
||||
static const uint8_t DUMMY_BYTE = 0xFF;
|
||||
|
||||
void Get_ADC_Result(tAdcFlagchip *env) {
|
||||
osMessageQueuePut(env->txAccessQueue, &DUMMY_BYTE, 0, 0);
|
||||
}
|
||||
|
||||
void ADC_Initial(
|
||||
tAdcFlagchip *env,
|
||||
ADC_InstanceType ADCx, // ADC_INSTANCE_0, ADC_INSTANCE_1
|
||||
|
||||
DMA_ChannelType ADC_DMA_CHANNEL, // DMA_CHANNEL_0 .. DMA_CHANNEL_15
|
||||
|
||||
IRQn_Type IRQ_DMA,
|
||||
uint8_t IRQ_DMA_PRIORITY,
|
||||
uint8_t IRQ_DMA_CHANNEL_PRIORITY,
|
||||
|
||||
const uint32_t *DMA_BUF,
|
||||
|
||||
uint8_t num_aChannels,
|
||||
ADC_ChannelCfgType *s_aChannels,
|
||||
|
||||
int32_t offset,
|
||||
double mux,
|
||||
double div,
|
||||
|
||||
ADC_ConvCompleteCallbackType Bsp_ADC_HandleResult
|
||||
) {
|
||||
|
||||
|
||||
env->ADCx = ADCx;
|
||||
env->DMA_BUF = (uint32_t *) DMA_BUF;
|
||||
env->offset = offset;
|
||||
env->div = div;
|
||||
env->mux = mux;
|
||||
env->num_aChannels = num_aChannels;
|
||||
env->txAccessQueue = osMessageQueueNew(1, 1, NULL);
|
||||
|
||||
env->s_tAdcInitCfg.eResolution = ADC_RESOLUTION_12_BIT, //!< 12 bit resolution
|
||||
env->s_tAdcInitCfg.eAlign = ADC_ALIGN_RIGHT, //!< Align right
|
||||
env->s_tAdcInitCfg.eTriggerMode = ADC_TRIGMODE_SW, //!< Software trigger
|
||||
env->s_tAdcInitCfg.bWaitEnable = false; //!< Disable wait conversion mode
|
||||
env->s_tAdcInitCfg.bCalEnable = false;
|
||||
env->s_tAdcInitCfg.s32CalOffset = 0U;
|
||||
env->s_tAdcInitCfg.s32CalGain = 0U;
|
||||
env->s_tAdcInitCfg.bSequenceGroupModeEnable = false; //!< Disable sequence group mode
|
||||
env->s_tAdcInitCfg.eTrgLatchUnitPri = TRG_LATCH_UNIT_PRI_ROUND_ROBIN; //!< Round robin priority
|
||||
env->s_tAdcInitCfg.eClockDivider = ADC_CLOCK_DIV_1; //!< Adc clock divided by 1
|
||||
env->s_tAdcInitCfg.eSequenceMode = ADC_SEQMODE_SINGLE; //!< Single sequence mode
|
||||
env->s_tAdcInitCfg.eOverrunMode = ADC_OVERRUN_MODE_PRESERVE; //!< When overrun occurred, the old conversion data are preserved
|
||||
env->s_tAdcInitCfg.eVoltageRef = ADC_REF_INTERNAL; //!< Use internal reference
|
||||
env->s_tAdcInitCfg.bHwAvgEnable = true; //!< Disable averaging functionality
|
||||
env->s_tAdcInitCfg.eHwAverage = ADC_AVERAGE_32; //!< Selection for number of samples used for averaging
|
||||
env->s_tAdcInitCfg.aSampleTimes[0] = 4U;
|
||||
env->s_tAdcInitCfg.aSampleTimes[1] = 10U;
|
||||
env->s_tAdcInitCfg.aSampleTimes[2] = 40U;
|
||||
env->s_tAdcInitCfg.aSampleTimes[3] = 80U;
|
||||
|
||||
ADC_Init(ADCx, &env->s_tAdcInitCfg);
|
||||
ADC_InitChannel(ADCx, s_aChannels, num_aChannels);
|
||||
|
||||
//начало-----------------------------------DMA-RX-------------------------------------------------------------------
|
||||
//начало-----------------------------------DMA-RX-------------------------------------------------------------------
|
||||
//начало-----------------------------------DMA-RX-------------------------------------------------------------------
|
||||
|
||||
env->s_tAdcDmaCfg.bDmaEnable = true;
|
||||
env->s_tAdcDmaCfg.eSeqGroupIndex = ADC_SEQUENCE_GROUP_0;
|
||||
env->s_tAdcDmaCfg.eDmaInstance = DMA_INSTANCE_0;
|
||||
env->s_tAdcDmaCfg.eDmaChannel = ADC_DMA_CHANNEL;
|
||||
env->s_tAdcDmaCfg.u8ChannelPriority = IRQ_DMA_CHANNEL_PRIORITY;
|
||||
env->s_tAdcDmaCfg.pResultBuffer = (void *) ((uint32_t) DMA_BUF);
|
||||
env->s_tAdcDmaCfg.pConvCompleteNotify = Bsp_ADC_HandleResult;
|
||||
|
||||
ADC_InitDmaChannel(ADCx, &env->s_tAdcDmaCfg);
|
||||
ADC_Enable(ADCx);
|
||||
|
||||
NVIC_SetPriority(IRQ_DMA, IRQ_DMA_PRIORITY);
|
||||
NVIC_EnableIRQ(IRQ_DMA);
|
||||
|
||||
DMA_StartChannel(DMA_INSTANCE_0, ADC_DMA_CHANNEL);
|
||||
|
||||
//конец-----------------------------------DMA-RX-------------------------------------------------------------------
|
||||
//конец-----------------------------------DMA-RX-------------------------------------------------------------------
|
||||
//конец-----------------------------------DMA-RX-------------------------------------------------------------------
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
//static void vAdcStart(tAdcFlagchip *env) {
|
||||
// ADC_Start(env->ADCx);
|
||||
//}
|
||||
|
||||
static uint32_t vAdcGet(tAdcFlagchip *env, uint32_t *buf, uint32_t timeout) {
|
||||
|
||||
ADC_Start(env->ADCx);
|
||||
|
||||
uint8_t res;
|
||||
|
||||
uint16_t sent = osMessageQueueGet(env->txAccessQueue, &res, 0, timeout);
|
||||
|
||||
// if (sent == osOK) {
|
||||
// for (uint8_t i = 0; i < env->num_aChannels; ++i) {
|
||||
// env->pVoltageBuffer[i] = (float) env->DMA_BUF[i] / ((1U << 12U) - 1U) * VREF;
|
||||
// }
|
||||
// }
|
||||
|
||||
// return env->pVoltageBuffer;
|
||||
*buf = (uint32_t) env->DMA_BUF;
|
||||
|
||||
if (sent == osOK) {
|
||||
return env->num_aChannels;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
tAdcIO vAdcGetIo(tAdcFlagchip *env) {
|
||||
tAdcIO io = {
|
||||
.env = env,
|
||||
.get = (AdcIOTransaction) vAdcGet,
|
||||
};
|
||||
return io;
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
{
|
||||
"dep": [
|
||||
{
|
||||
"type": "local",
|
||||
|
||||
"dir": "./MODULES/Adc"
|
||||
}
|
||||
],
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
],
|
||||
"srcs": [
|
||||
"Src/**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
//
|
||||
// Created by CFIF on 06.09.22.
|
||||
//
|
||||
|
||||
#ifndef ASCIISTRINGASSMEBLINGUTILS_ASCIISTRINGASSMEBLINGUTILS_H
|
||||
#define ASCIISTRINGASSMEBLINGUTILS_ASCIISTRINGASSMEBLINGUTILS_H
|
||||
|
||||
#include "stdint.h"
|
||||
#include "stddef.h"
|
||||
|
||||
void vAsciiStringAdd(char *string, size_t *stringLen, char *addString, size_t addStringLen);
|
||||
|
||||
uint8_t vAsciiStringDecimalIntToChar(uint8_t number_0_9);
|
||||
|
||||
void vAsciiStringAddChar(char *string, size_t *stringLen, uint8_t singleChar);
|
||||
|
||||
#define vAsciiStringAddStatic(string, stringLen, staticString)\
|
||||
vAsciiStringAdd(string, stringLen, staticString, sizeof(staticString)-1)
|
||||
|
||||
void vAsciiStringClean(char *string, size_t *stringLen);
|
||||
|
||||
void vAsciiStringInit(char *string, size_t *stringLen, size_t fullLen);
|
||||
|
||||
void vAsciiStringAddDecimalInt(char *string, size_t *stringLen, uint8_t number, uint8_t digits);
|
||||
|
||||
void vAsciiStringAddDecimalInt64(char *string, size_t *stringLen, uint64_t number, uint8_t digits);
|
||||
|
||||
void vAsciiStringAddDecimalIntWithLimit(char *string, size_t *stringLen, int64_t number, uint8_t digitsLimit);
|
||||
|
||||
void vAsciiStringAddByteAsHex(char *str, size_t *stringLen, uint8_t number);
|
||||
|
||||
void vAsciiStringAddBytesAsHex(char *str, size_t *stringLen, uint8_t *bytesData, size_t bytesCount);
|
||||
|
||||
void vAsciiStringAddDecimalFloatWithLimit(
|
||||
char *string,
|
||||
size_t *stringLen,
|
||||
double number,
|
||||
uint8_t intDigits,
|
||||
uint8_t fractionalDigits
|
||||
);
|
||||
|
||||
#endif //ASCIISTRINGASSMEBLINGUTILS_ASCIISTRINGASSMEBLINGUTILS_H
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
//
|
||||
// Created by CFIF on 06.09.22.
|
||||
//
|
||||
|
||||
#include <memory.h>
|
||||
#include <math.h>
|
||||
#include "AsciiStringAssmeblingUtils.h"
|
||||
|
||||
static const char ASCII_STRING_HEX_CHAR[] = "0123456789ABCDEF";
|
||||
|
||||
static const uint64_t ASCII_STRING_DEC_POW[] = {
|
||||
1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000, 10000000000, 100000000000
|
||||
};
|
||||
static const uint8_t ASCII_STRING_DEC_POW_LEN = (sizeof(ASCII_STRING_DEC_POW) / sizeof(uint64_t));
|
||||
|
||||
uint8_t vAsciiStringDecimalIntToChar(uint8_t number_0_9) {
|
||||
number_0_9 = number_0_9 % 10; //cutoff digits more 1 (numbers between 0 and 9)
|
||||
return ('0' + number_0_9); //return char of number('0' is base number in ascii)
|
||||
}
|
||||
|
||||
void vAsciiStringAdd(char *string, size_t *stringLen, char *addString, size_t addStringLen) {
|
||||
memcpy(string + (*stringLen), addString, addStringLen);
|
||||
*stringLen += addStringLen;
|
||||
}
|
||||
|
||||
void vAsciiStringAddChar(char *string, size_t *stringLen, uint8_t singleChar) {
|
||||
string[*stringLen] = singleChar;
|
||||
++(*stringLen);
|
||||
}
|
||||
|
||||
void vAsciiStringInit(char *string, size_t *stringLen, size_t fullLen) {
|
||||
memset(string, 0, fullLen);
|
||||
*stringLen = 0;
|
||||
}
|
||||
|
||||
void vAsciiStringClean(char *string, size_t *stringLen) {
|
||||
if (*stringLen == 0)return;
|
||||
memset(string, 0, *stringLen);
|
||||
*stringLen = 0;
|
||||
}
|
||||
|
||||
void vAsciiStringAddDecimalInt(char *string, size_t *stringLen, uint8_t number, uint8_t digits) {
|
||||
for (uint8_t reverse_digit = 1; reverse_digit <= digits; ++reverse_digit) {
|
||||
string[*stringLen + digits - reverse_digit] = vAsciiStringDecimalIntToChar(number);
|
||||
number /= 10;
|
||||
}
|
||||
*stringLen += digits;
|
||||
}
|
||||
|
||||
void vAsciiStringAddDecimalInt64(char *string, size_t *stringLen, uint64_t number, uint8_t digits) {
|
||||
for (uint8_t reverse_digit = 1; reverse_digit <= digits; ++reverse_digit) {
|
||||
string[*stringLen + digits - reverse_digit] = vAsciiStringDecimalIntToChar(number % 10);
|
||||
number /= 10;
|
||||
}
|
||||
*stringLen += digits;
|
||||
}
|
||||
|
||||
void vAsciiStringSpitChars(char *one, char *two) {
|
||||
char tmp;
|
||||
tmp = *one;
|
||||
*one = *two;
|
||||
*two = tmp;
|
||||
}
|
||||
|
||||
void vAsciiStringAddDecimalIntWithLimit(char *string, size_t *stringLen, int64_t number, uint8_t digitsLimit) {
|
||||
|
||||
if (number < 0) {
|
||||
*(string + (*stringLen)) = '-';
|
||||
++(*stringLen);
|
||||
number = -number;
|
||||
}
|
||||
|
||||
uint32_t cutoffNumber = 1;
|
||||
|
||||
for (uint8_t scale = 0; scale < digitsLimit; ++scale) {
|
||||
cutoffNumber *= 10;
|
||||
}
|
||||
number = number % cutoffNumber;
|
||||
|
||||
if (number == 0) {
|
||||
string[*stringLen] = '0';
|
||||
(*stringLen) += 1;
|
||||
}
|
||||
|
||||
uint8_t digits = 0;
|
||||
|
||||
for (; (digits < digitsLimit) && (number != 0); ++digits) {
|
||||
string[(*stringLen) + digits] = vAsciiStringDecimalIntToChar(number % 10);
|
||||
number /= 10;
|
||||
}
|
||||
|
||||
uint8_t reverses = digits / 2;
|
||||
|
||||
for (uint8_t reverse_digit = 0; reverse_digit < reverses; ++reverse_digit) {
|
||||
vAsciiStringSpitChars(string + *stringLen + reverse_digit, string + *stringLen + digits - 1 - reverse_digit);
|
||||
}
|
||||
|
||||
*stringLen += digits;
|
||||
}
|
||||
|
||||
void vAsciiStringAddByteAsHex(char *str, size_t *stringLen, uint8_t number) {
|
||||
str[*stringLen + 0] = ASCII_STRING_HEX_CHAR[(number >> 4) & 0xF];
|
||||
str[*stringLen + 1] = ASCII_STRING_HEX_CHAR[(number & 0xF)];
|
||||
*stringLen += 2;
|
||||
}
|
||||
|
||||
void vAsciiStringAddBytesAsHex(char *str, size_t *stringLen, uint8_t *bytesData, size_t bytesCount) {
|
||||
uint8_t *end = bytesData + bytesCount;
|
||||
while (end > bytesData) {
|
||||
vAsciiStringAddByteAsHex(str, stringLen, *bytesData);
|
||||
++bytesData;
|
||||
}
|
||||
}
|
||||
|
||||
static inline uint64_t get_dec_pow(uint8_t value) {
|
||||
if (value < ASCII_STRING_DEC_POW_LEN) {
|
||||
return ASCII_STRING_DEC_POW[value];
|
||||
}
|
||||
|
||||
uint64_t mux = ASCII_STRING_DEC_POW[ASCII_STRING_DEC_POW_LEN - 1];
|
||||
|
||||
for (uint8_t scale = ASCII_STRING_DEC_POW_LEN; scale < value; ++scale) {
|
||||
mux *= 10;
|
||||
}
|
||||
|
||||
return mux;
|
||||
}
|
||||
|
||||
|
||||
void vAsciiStringAddDecimalFloatWithLimit(
|
||||
char *string,
|
||||
size_t *stringLen,
|
||||
double number,
|
||||
uint8_t intDigits,
|
||||
uint8_t fractionalDigits
|
||||
) {
|
||||
uint64_t dec_mux = get_dec_pow(fractionalDigits);
|
||||
|
||||
uint64_t intPart = (uint64_t) number;
|
||||
double fractional = round(number * dec_mux) / dec_mux - intPart;
|
||||
uint64_t fractionalPartInInteger = (uint64_t) (fractional * dec_mux);
|
||||
|
||||
|
||||
vAsciiStringAddDecimalIntWithLimit(string, stringLen, intPart, intDigits);
|
||||
vAsciiStringAddChar(string, stringLen, '.');
|
||||
vAsciiStringAddDecimalInt64(string, stringLen, fractionalPartInInteger, fractionalDigits);
|
||||
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
{
|
||||
"dep": [
|
||||
],
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
],
|
||||
"srcs": [
|
||||
"Src/**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
//
|
||||
// Created by CFIF on 10.09.22.
|
||||
//
|
||||
|
||||
#ifndef ASCIISTRINGPARSINGUTILS_ASCIISTRINGPARSINGUTILS_H
|
||||
#define ASCIISTRINGPARSINGUTILS_ASCIISTRINGPARSINGUTILS_H
|
||||
|
||||
#include <stddef.h>
|
||||
#include "stdint.h"
|
||||
|
||||
int64_t iAsciiStringParseSignedLongDecimalNumber(char *str, const char *strEnd);
|
||||
|
||||
uint64_t iAsciiStringParseUnsignedLongDecimalNumber(char *str, const char *strEnd);
|
||||
|
||||
double dAsciiStringParseDouble(char *str, const char *strEnd);
|
||||
|
||||
char *xAsciiStringSkipChar(char *str, char const *strEnd, char symbol);
|
||||
|
||||
#define xAsciiStringSkipSpace(STR, STR_END) xAsciiStringSkipChar(STR,STR_END,' ')
|
||||
|
||||
char *xAsciiStringSeekChar(char *str, char const *strEnd, char symbol);
|
||||
|
||||
uint8_t iAsciiStringMoveToNextParsingBlock(char **blockBeginPos, char **blockDividerPos, char *strEnd, char divider);
|
||||
|
||||
uint8_t iAsciiStringParseHexByte(const char *str);
|
||||
|
||||
size_t iAsciiStringParseHexBytes(uint8_t *bytesData, char *str, size_t stringLen);
|
||||
|
||||
#define BIN_FROM_HEX(DATA,LEN,HEX_STRING) \
|
||||
uint8_t DATA[(sizeof(HEX_STRING)-1)/2]; \
|
||||
size_t LEN = iAsciiStringParseHexBytes(DATA, HEX_STRING, sizeof(HEX_STRING) - 1);
|
||||
|
||||
#endif //ASCIISTRINGPARSINGUTILS_ASCIISTRINGPARSINGUTILS_H
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
//
|
||||
// Created by CFIF on 10.09.22.
|
||||
//
|
||||
|
||||
#include "AsciiStringParsingUtils.h"
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
uint8_t iAsciiStringParseCharToDecimalInt(char symbol) {
|
||||
return (symbol - '0'); // return overvalue if not a decimal number
|
||||
}
|
||||
|
||||
uint8_t iAsciiStringParseHexCharToInt(char symbol) {
|
||||
if (symbol >= '0' && symbol <= '9') {
|
||||
return iAsciiStringParseCharToDecimalInt(symbol);
|
||||
} else if (symbol >= 'a' && symbol <= 'f') {
|
||||
return 0xA + symbol - 'a';
|
||||
} else if (symbol >= 'A' && symbol <= 'F') {
|
||||
return 0xA + (symbol - 'A');
|
||||
} else {
|
||||
return 0x10; //not a hex number, return overvalue
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
uint8_t iAsciiStringParseHexByte(const char *str) {
|
||||
return iAsciiStringParseHexCharToInt(*str) * 0x10 + iAsciiStringParseHexCharToInt(*(str + 1));
|
||||
}
|
||||
|
||||
size_t iAsciiStringParseHexBytes(uint8_t *bytesData, char *str, size_t stringLen) {
|
||||
char *end = str + stringLen;
|
||||
|
||||
size_t dataLen = stringLen / 2;
|
||||
|
||||
while (end > str) {
|
||||
|
||||
*bytesData = iAsciiStringParseHexByte(str);
|
||||
|
||||
str += 2;
|
||||
++bytesData;
|
||||
}
|
||||
|
||||
return dataLen;
|
||||
}
|
||||
|
||||
uint64_t iAsciiStringParseUIntDecimalNumberWhitEnd(char **str, const char *strEnd) {
|
||||
|
||||
|
||||
uint32_t value = 0;
|
||||
uint8_t digit;
|
||||
|
||||
while ((*str) < strEnd) {
|
||||
digit = iAsciiStringParseCharToDecimalInt(**str);
|
||||
if (digit > 9) {
|
||||
return value;
|
||||
} else {
|
||||
value = (value * 10) + digit;
|
||||
}
|
||||
++(*str);
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
int64_t iAsciiStringParseSignedLongDecimalNumber(char *str, const char *strEnd) {
|
||||
int8_t sign = 1;
|
||||
if (*str == '-') {
|
||||
sign = -1;
|
||||
++str;
|
||||
}
|
||||
|
||||
return iAsciiStringParseUIntDecimalNumberWhitEnd(&str, strEnd) * sign;
|
||||
}
|
||||
|
||||
uint64_t iAsciiStringParseUnsignedLongDecimalNumber(char *str, const char *strEnd) {
|
||||
return iAsciiStringParseUIntDecimalNumberWhitEnd(&str, strEnd);
|
||||
}
|
||||
|
||||
|
||||
char *xAsciiStringSkipChar(char *utcString, char const *utcStringEnd, char symbol) {
|
||||
while ((utcString < utcStringEnd) && (*utcString == symbol)) {
|
||||
++utcString;
|
||||
}
|
||||
return utcString;
|
||||
}
|
||||
|
||||
char *xAsciiStringSeekChar(char *utcString, char const *utcStringEnd, char symbol) {
|
||||
while ((utcString < utcStringEnd) && (*utcString != symbol)) {
|
||||
++utcString;
|
||||
}
|
||||
return utcString;
|
||||
}
|
||||
|
||||
double dAsciiStringParseDouble(char *str, const char *strEnd) {
|
||||
double sign = 1;
|
||||
if (str[0] == '-') {
|
||||
sign = -1;
|
||||
++str;
|
||||
}
|
||||
char *dividerSymbol = xAsciiStringSeekChar(str, strEnd, '.');
|
||||
|
||||
double result = iAsciiStringParseUnsignedLongDecimalNumber(str, dividerSymbol);
|
||||
|
||||
if (dividerSymbol < (strEnd - 1)) {
|
||||
++dividerSymbol;
|
||||
char *fractionalStr = dividerSymbol;
|
||||
double fractional = iAsciiStringParseUIntDecimalNumberWhitEnd(&fractionalStr, strEnd);
|
||||
|
||||
for (; dividerSymbol < fractionalStr; ++dividerSymbol) {
|
||||
fractional /= 10;
|
||||
}
|
||||
result += fractional;
|
||||
}
|
||||
|
||||
|
||||
return result * sign;
|
||||
}
|
||||
|
||||
uint8_t iAsciiStringMoveToNextParsingBlock(char **blockBeginPos, char **blockDividerPos, char *strEnd, char divider) {
|
||||
*blockBeginPos = xAsciiStringSkipSpace((*blockDividerPos + 1), strEnd);
|
||||
*blockDividerPos = xAsciiStringSeekChar(*blockBeginPos, strEnd, divider);
|
||||
return *blockDividerPos - *blockBeginPos; //return block length
|
||||
}
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
cmake_minimum_required(VERSION 3.17)
|
||||
PROJECT(test)
|
||||
|
||||
set(CMAKE_CXX_STANDARD 17)
|
||||
|
||||
include(modular.cmake)
|
||||
|
||||
add_executable(test ${SOURCES})
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
//
|
||||
// Created by CFIF on 10.09.22.
|
||||
//
|
||||
#include "AsciiStringParsingUtils.h"
|
||||
#include "printf.h"
|
||||
|
||||
int main() {
|
||||
char srt[] = "22341.233adfa";
|
||||
|
||||
|
||||
int32_t si = iAsciiStringParseSignedLongDecimalNumber(srt, srt + 10);
|
||||
double dbl = dAsciiStringParseDouble(srt, srt + 10);
|
||||
|
||||
printf("short unsigned %i %f\n", si, dbl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
{
|
||||
"dep": [
|
||||
{
|
||||
"type": "local",
|
||||
"dir": "../"
|
||||
}
|
||||
],
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
],
|
||||
"srcs": [
|
||||
"Src/**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
{
|
||||
"dep": [
|
||||
],
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
],
|
||||
"srcs": [
|
||||
"Src/**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
//
|
||||
// Created by cfif on 13.10.22.
|
||||
//
|
||||
|
||||
#ifndef BASETYPES_H
|
||||
#define BASETYPES_H
|
||||
|
||||
#include "BaseTypes/String.h"
|
||||
#include "BaseTypes/Strings.h"
|
||||
|
||||
#endif //BASETYPES_H
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
//
|
||||
// Created by CFIF on 10.11.22.
|
||||
//
|
||||
|
||||
#ifndef UVEOS_ON_NATION_STRING_H
|
||||
#define UVEOS_ON_NATION_STRING_H
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
typedef struct {
|
||||
uint8_t length;
|
||||
uint8_t max_length;
|
||||
uint8_t readonly;
|
||||
char str[32];
|
||||
} tString;
|
||||
|
||||
|
||||
uint8_t getStrLen(char *str);
|
||||
|
||||
void vInitStringOnlyLength(tString *tstr, uint8_t length);
|
||||
|
||||
void vInitString(tString *tstr, void *str, uint8_t length, uint8_t max_length, uint8_t readonly);
|
||||
|
||||
#endif //UVEOS_ON_NATION_STRING_H
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
//
|
||||
// Created by CFIF on 10.11.22.
|
||||
//
|
||||
|
||||
#ifndef UVEOS_ON_NATION_STRINGS_H
|
||||
#define UVEOS_ON_NATION_STRINGS_H
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
#define tString(T) \
|
||||
typedef struct { \
|
||||
uint8_t length; \
|
||||
char data[T]; \
|
||||
} tString##T;
|
||||
|
||||
tString(8)
|
||||
tString(16)
|
||||
tString(32)
|
||||
tString(64)
|
||||
tString(128)
|
||||
tString(255)
|
||||
|
||||
typedef struct {
|
||||
uint8_t length;
|
||||
char *data;
|
||||
} tStringStatic;
|
||||
|
||||
typedef struct {
|
||||
uint8_t *length;
|
||||
char *data;
|
||||
} tStringLink;
|
||||
|
||||
|
||||
#define StringGetLinkTemplateD(T) \
|
||||
tStringLink String##T##GetLink(tString##T *string);
|
||||
|
||||
StringGetLinkTemplateD(8)
|
||||
|
||||
StringGetLinkTemplateD(16)
|
||||
|
||||
StringGetLinkTemplateD(32)
|
||||
|
||||
StringGetLinkTemplateD(64)
|
||||
|
||||
StringGetLinkTemplateD(128)
|
||||
|
||||
StringGetLinkTemplateD(255)
|
||||
|
||||
StringGetLinkTemplateD(Static)
|
||||
|
||||
|
||||
#define StringStaticInit(STR) (tStringStatic){.data = (char*)(STR), .length = sizeof(STR)-1}
|
||||
#define StringArrInit(STR) (tStringStatic){.data = (char*)(STR), .length = sizeof(STR)}
|
||||
|
||||
|
||||
#define StringCopyTD(T) \
|
||||
void String##T##Copy(tString##T *dest, char *source, uint8_t sourceLen);
|
||||
|
||||
StringCopyTD(8)
|
||||
|
||||
StringCopyTD(16)
|
||||
|
||||
StringCopyTD(32)
|
||||
|
||||
StringCopyTD(64)
|
||||
|
||||
StringCopyTD(128)
|
||||
|
||||
StringCopyTD(255)
|
||||
|
||||
#define StringCopyStaticTemplate(T) \
|
||||
String##T##Copy(DEST,STR,sizeof(STR)-1)
|
||||
|
||||
#define String8CopyStatic(DEST, STR) String8Copy(DEST,STR,sizeof(STR)-1)
|
||||
#define String16CopyStatic(DEST, STR) String16Copy(DEST,STR,sizeof(STR)-1)
|
||||
#define String32CopyStatic(DEST, STR) String32Copy(DEST,STR,sizeof(STR)-1)
|
||||
#define String64CopyStatic(DEST, STR) String64Copy(DEST,STR,sizeof(STR)-1)
|
||||
#define String128CopyStatic(DEST, STR) String128Copy(DEST,STR,sizeof(STR)-1)
|
||||
#define String255CopyStatic(DEST, STR) String128Copy(DEST,STR,sizeof(STR)-1)
|
||||
|
||||
#endif //UVEOS_ON_NATION_STRINGS_H
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
//
|
||||
// Created by cfif on 13.10.22.
|
||||
//
|
||||
|
||||
#include <string.h>
|
||||
#include "BaseTypes.h"
|
||||
|
||||
uint8_t getStrLen(char *str) {
|
||||
uint8_t len = 0;
|
||||
while (str[len]) {
|
||||
++len;
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
void vInitString(tString *tstr, void *str, uint8_t length, uint8_t max_length, uint8_t readonly) {
|
||||
|
||||
tstr->length = length;
|
||||
tstr->max_length = max_length;
|
||||
tstr->readonly = readonly;
|
||||
memcpy(tstr->str, str, length);
|
||||
|
||||
}
|
||||
|
||||
void vInitStringOnlyLength(tString *tstr, uint8_t length) {
|
||||
tstr->length = length;
|
||||
}
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
//
|
||||
// Created by CFIF on 11.11.22.
|
||||
//
|
||||
|
||||
#include "BaseTypes/Strings.h"
|
||||
#include "memory.h"
|
||||
|
||||
#define StringGetLinkTemplate(T) \
|
||||
tStringLink String##T##GetLink(tString##T *string) { \
|
||||
return (tStringLink) {.length = &string->length, .data = string->data}; \
|
||||
}
|
||||
|
||||
StringGetLinkTemplate(8)
|
||||
|
||||
StringGetLinkTemplate(16)
|
||||
|
||||
StringGetLinkTemplate(32)
|
||||
|
||||
StringGetLinkTemplate(64)
|
||||
|
||||
StringGetLinkTemplate(128)
|
||||
|
||||
StringGetLinkTemplate(Static)
|
||||
|
||||
|
||||
//#define StringStaticInit(STR) (tStringStatic){.data = STR, .length = sizeof(STR)-1}
|
||||
|
||||
|
||||
#define StringCopyT(T) \
|
||||
void String##T##Copy(tString##T *dest, char *source, uint8_t sourceLen) { \
|
||||
dest->length = sourceLen > T ? T : sourceLen; \
|
||||
memcpy(dest->data, source, dest->length); \
|
||||
}
|
||||
|
||||
StringCopyT(8)
|
||||
|
||||
StringCopyT(16)
|
||||
|
||||
StringCopyT(32)
|
||||
|
||||
StringCopyT(64)
|
||||
|
||||
StringCopyT(128)
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
{
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
],
|
||||
"srcs": [
|
||||
"Src/**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
//
|
||||
// Created by cfif on 02.11.22.
|
||||
//
|
||||
|
||||
#ifndef HVAC_ON_CHIP_BOOTLOADER_JUMP_H
|
||||
#define HVAC_ON_CHIP_BOOTLOADER_JUMP_H
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
void BootFastJumpToAddress(const uint32_t address);
|
||||
void BootJumpToAddress(const uint32_t address);
|
||||
void Reset();
|
||||
|
||||
#endif //HVAC_ON_CHIP_BOOTLOADER_JUMP_H
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
//
|
||||
// Created by cfif on 02.11.22.
|
||||
//
|
||||
#include CMSIS_device_header
|
||||
#include "fc7xxx_driver_dma.h"
|
||||
#include "fc7xxx_driver_fcuart.h"
|
||||
#include "fc7240_fcuart_regs.h"
|
||||
#include "fc7xxx_driver_pcc.h"
|
||||
#include "fc7xxx_driver_adc.h"
|
||||
#include "fc7xxx_driver_flexcan.h"
|
||||
#include "fc7xxx_driver_tpu.h"
|
||||
|
||||
|
||||
|
||||
typedef void (*pFunction)(void);
|
||||
|
||||
#define EnablePrivilegedMode() __asm("SVC #0")
|
||||
|
||||
|
||||
void DeInitAll() {
|
||||
// 1. ГЛОБАЛЬНО отключаем прерывания (первое, что делаем)
|
||||
__disable_irq();
|
||||
|
||||
// 2. Отключаем ВСЕ прерывания в NVIC
|
||||
for (int i = 0; i < 8; i++) { // Обычно достаточно 8 банков для всех прерываний
|
||||
NVIC->ICER[i] = 0xFFFFFFFF;
|
||||
NVIC->ICPR[i] = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
// 3. Останавливаем SysTick и сбрасываем
|
||||
SysTick->CTRL = 0;
|
||||
SysTick->LOAD = 0;
|
||||
SysTick->VAL = 0;
|
||||
|
||||
// 4. Сбрасываем все pending-флаги
|
||||
SCB->ICSR |= SCB_ICSR_PENDSVCLR_Msk | SCB_ICSR_PENDSTCLR_Msk;
|
||||
|
||||
// 5. Отключаем периферию, которая может генерировать прерывания
|
||||
|
||||
// 5.1. DMA
|
||||
DMA_DeInit(DMA_INSTANCE_0);
|
||||
|
||||
// 5.2. UART
|
||||
for (uint8_t i = 0; i < FCUART_INSTANCE_COUNT; ++i) {
|
||||
FCUART_DeInit(i);
|
||||
}
|
||||
|
||||
// 5.3. CAN
|
||||
for (uint8_t i = 0; i < FLEXCAN_INSTANCE_COUNT; ++i) {
|
||||
FLEXCAN_DeInit(i);
|
||||
}
|
||||
|
||||
// 5.4. ADC
|
||||
for (uint8_t i = 0; i < ADC_INSTANCE_COUNT; ++i) {
|
||||
ADC_DeInit(i);
|
||||
}
|
||||
|
||||
// 5.5. TPU
|
||||
TPU_DeInit();
|
||||
|
||||
|
||||
// 5.6 RESET CLK
|
||||
PCC_GenPeripheralReset(PCC_CLK_DMA0);
|
||||
PCC_GenPeripheralReset(PCC_CLK_DMAMUX0);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FLEXCAN0);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FLEXCAN1);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FLEXCAN2);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FLEXCAN3);
|
||||
PCC_GenPeripheralReset(PCC_CLK_ADC0);
|
||||
PCC_GenPeripheralReset(PCC_CLK_ADC1);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART0);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART1);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART2);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART3);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART4);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART5);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART6);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART7);
|
||||
|
||||
}
|
||||
|
||||
void BootJumpToAddress(const uint32_t address) {
|
||||
|
||||
// 1. ГЛОБАЛЬНО отключаем прерывания (первое, что делаем)
|
||||
__disable_irq();
|
||||
|
||||
// 2. Отключаем ВСЕ прерывания в NVIC
|
||||
for (int i = 0; i < 8; i++) { // Обычно достаточно 8 банков для всех прерываний
|
||||
NVIC->ICER[i] = 0xFFFFFFFF;
|
||||
NVIC->ICPR[i] = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
// 3. Останавливаем SysTick и сбрасываем
|
||||
SysTick->CTRL = 0;
|
||||
SysTick->LOAD = 0;
|
||||
SysTick->VAL = 0;
|
||||
|
||||
// 4. Сбрасываем все pending-флаги
|
||||
SCB->ICSR |= SCB_ICSR_PENDSVCLR_Msk | SCB_ICSR_PENDSTCLR_Msk;
|
||||
|
||||
// 5. Отключаем периферию, которая может генерировать прерывания
|
||||
|
||||
// 5.1. DMA
|
||||
DMA_DeInit(DMA_INSTANCE_0);
|
||||
|
||||
// 5.2. UART
|
||||
for (uint8_t i = 0; i < FCUART_INSTANCE_COUNT; ++i) {
|
||||
FCUART_DeInit(i);
|
||||
}
|
||||
|
||||
// 5.3 RESET CLK
|
||||
PCC_GenPeripheralReset(PCC_CLK_DMA0);
|
||||
PCC_GenPeripheralReset(PCC_CLK_DMAMUX0);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART0);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART1);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART2);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART3);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART4);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART5);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART6);
|
||||
PCC_GenPeripheralReset(PCC_CLK_FCUART7);
|
||||
|
||||
|
||||
// 6. Подготовка процессора
|
||||
if (CONTROL_nPRIV_Msk & __get_CONTROL()) {
|
||||
EnablePrivilegedMode();
|
||||
}
|
||||
|
||||
if (CONTROL_SPSEL_Msk & __get_CONTROL()) {
|
||||
__set_MSP(__get_PSP());
|
||||
__set_CONTROL(__get_CONTROL() & ~CONTROL_SPSEL_Msk);
|
||||
}
|
||||
|
||||
// 7. Получаем стек и точку входа приложения
|
||||
uint32_t appStack = *((__IO uint32_t *) address);
|
||||
pFunction appEntry = (pFunction) *((__IO uint32_t *) (address + 4));
|
||||
|
||||
// 8. Устанавливаем VTOR и стек
|
||||
SCB->VTOR = address;
|
||||
__set_MSP(appStack);
|
||||
|
||||
// 9. Очищаем регистры, которые могут содержать данные загрузчика
|
||||
__ISB(); // Instruction Synchronization Barrier
|
||||
__DSB(); // Data Synchronization Barrier
|
||||
|
||||
// 10. Переход БЕЗ включения прерываний!
|
||||
// Приложение само должно включить прерывания после инициализации
|
||||
appEntry();
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
|
||||
void BootFastJumpToAddress(const uint32_t address) {
|
||||
|
||||
|
||||
// 1. Подготовка процессора
|
||||
if (CONTROL_nPRIV_Msk & __get_CONTROL()) {
|
||||
EnablePrivilegedMode();
|
||||
}
|
||||
|
||||
if (CONTROL_SPSEL_Msk & __get_CONTROL()) {
|
||||
__set_MSP(__get_PSP());
|
||||
__set_CONTROL(__get_CONTROL() & ~CONTROL_SPSEL_Msk);
|
||||
}
|
||||
|
||||
// 2. Получаем стек и точку входа приложения
|
||||
uint32_t appStack = *((__IO uint32_t *) address);
|
||||
pFunction appEntry = (pFunction) *((__IO uint32_t *) (address + 4));
|
||||
|
||||
// 3. Устанавливаем VTOR и стек
|
||||
SCB->VTOR = address;
|
||||
__set_MSP(appStack);
|
||||
|
||||
// 4. Очищаем регистры, которые могут содержать данные загрузчика
|
||||
__ISB(); // Instruction Synchronization Barrier
|
||||
__DSB(); // Data Synchronization Barrier
|
||||
|
||||
// 5. Переход БЕЗ включения прерываний!
|
||||
// Приложение само должно включить прерывания после инициализации
|
||||
appEntry();
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
|
||||
void Reset() {
|
||||
|
||||
// DeInitAll();
|
||||
|
||||
NVIC_SystemReset();
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
{
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
],
|
||||
"srcs": [
|
||||
"Src/**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
//
|
||||
// Created by cfif on 16.03.2024.
|
||||
//
|
||||
|
||||
#ifndef FLAGCHIP_CAN_MODULE_CAN_FRAME_H
|
||||
#define FLAGCHIP_CAN_MODULE_CAN_FRAME_H
|
||||
|
||||
#include "SerialPortFrameIO.h"
|
||||
#include "cmsis_os2.h"
|
||||
#include "stdbool.h"
|
||||
|
||||
|
||||
#include "device_header.h"
|
||||
#include "interrupt_manager.h"
|
||||
|
||||
#include "fc7xxx_driver_flexcan.h"
|
||||
#include "fc7xxx_driver_pcc.h"
|
||||
#include "fc7xxx_driver_dma.h"
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t standard_id; /*!< specifies the 11 bits standard identifier
|
||||
this parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
|
||||
this parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
FLEXCAN_IdType id_type; /*!< specifies identifier type for the receive message.*/
|
||||
|
||||
FLEXCAN_DataType frame_type; /*!< specifies frame type for the receive message.*/
|
||||
|
||||
uint8_t dlc; /*!< specifies the frame data length that will be received.
|
||||
this parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t data[8]; /*!< contains the receive data. it ranges from 0 to 0xFF.*/
|
||||
|
||||
uint8_t filter_index; /*!< specifies the message stored in which filter
|
||||
this parameter can be a value between 0 to 0xFF */
|
||||
} can_rx_message_type;
|
||||
|
||||
#define COUNT_TX_CAN0_HANDLER 8
|
||||
#define COUNT_TX_CAN1_HANDLER 16
|
||||
|
||||
#define COUNT_QUEUE 4
|
||||
|
||||
typedef struct {
|
||||
FLEXCAN_IdType eRxFrameType; /**< FLEXCAN ID type, 0 STD, 1 EXT */
|
||||
uint32_t u32RxCanId; /**< FLEXCAN received ID */
|
||||
uint32_t u32RxCanIdMask;
|
||||
uint8_t filter;
|
||||
} FilterTo_FLEXCAN_RxMbFilterType;
|
||||
|
||||
typedef struct {
|
||||
|
||||
FLEXCAN_Type *can;
|
||||
|
||||
uint8_t CAN_INDEX;
|
||||
|
||||
uint32_t id;
|
||||
uint32_t id1;
|
||||
FLEXCAN_IdType canTypeFrame;
|
||||
bool canFilterEnable;
|
||||
|
||||
bool reInitOne;
|
||||
|
||||
uint8_t CountHardSoftFilter_RX;
|
||||
|
||||
FLEXCAN_BaudType canBaudRate;
|
||||
|
||||
uint32_t g_u32RxDataIndex;
|
||||
|
||||
FLEXCAN_RxMbFilterType pRxMbFilterList[32];
|
||||
FLEXCAN_RxMbFilterType pRxFilterFifoList[32];
|
||||
|
||||
osMessageQueueId_t rxDataQueue[COUNT_QUEUE];
|
||||
osMessageQueueId_t rxDataSnifferQueue[COUNT_QUEUE];
|
||||
|
||||
osMutexId_t access;
|
||||
|
||||
DMA_InitType dmaInitCfg_RX;
|
||||
DMA_ChannelCfgType chnCfg_RX;
|
||||
DMA_InterruptCfgType interruptCfg_RX;
|
||||
|
||||
FLEXCAN_InitType tInitCfg;
|
||||
FLEXCAN_MBConfigType tMbCfg;
|
||||
FLEXCAN_InterruptType tIntCfg;
|
||||
|
||||
uint8_t DMA_BUF_LEN_RX;
|
||||
uint8_t pBufCounter;
|
||||
|
||||
FilterTo_FLEXCAN_RxMbFilterType *IdHardSoftFilter_RX;
|
||||
|
||||
can_rx_message_type rx_message_struct;
|
||||
|
||||
IRQn_Type IRQ_CAN;
|
||||
|
||||
FLEXCAN_ErrorInterruptCallBackType CAN_ErrorInterrupt_CallBack;
|
||||
FLEXCAN_RxInterruptCallBackType CAN_RxInterrupt_CallBack;
|
||||
FLEXCAN_RxInterruptCallBackType CAN_RxFifoInterrupt_CallBack;
|
||||
FLEXCAN_TxInterruptCallBackType CAN_TxInterrupt_CallBack;
|
||||
DMA_TransferCompleteCallbackType DMA_TransferCompleteCallback;
|
||||
DMA_TransferErrorCallbackType DMA_ErrorCallback;
|
||||
|
||||
} tCanSerialPortFrameFlagchip;
|
||||
|
||||
bool vCanSerialPortFrameDMAInit(
|
||||
tCanSerialPortFrameFlagchip *env,
|
||||
FLEXCAN_Type *CANx, // FLEXCAN0
|
||||
uint8 CAN_INDEX, // CAN0 = 0 ... CAN3 = 3
|
||||
IRQn_Type IRQ_CAN, // FlexCAN0_IRQn ... FlexCAN3_IRQn
|
||||
uint8 CAN_PRIORITY,
|
||||
|
||||
DMA_ChannelType DMA_CHANNEL_RX,
|
||||
DMA_RequestSourceType DMA_CHANNEL_REQ_RX, // DMA_REQ_FLEXCAN0
|
||||
const uint8_t *DMA_BUF_RX,
|
||||
uint8_t DMA_BUF_LEN_RX,
|
||||
|
||||
const FilterTo_FLEXCAN_RxMbFilterType *IdHardSoftFilter_RX,
|
||||
uint8_t CountHardSoftFilter_RX,
|
||||
|
||||
const FLEXCAN_RxMbFilterType *IdFilterFifo_RX,
|
||||
uint8_t CountFilterFifo_RX,
|
||||
|
||||
IRQn_Type IRQ_DMA_RX,
|
||||
uint8_t IRQ_DMA_PRIORITY_RX,
|
||||
uint8_t IRQ_DMA_CHANNEL_PRIORITY_RX,
|
||||
|
||||
FLEXCAN_BaudType canBaudRate,
|
||||
FLEXCAN_IdType canTypeFrame,
|
||||
uint32_t canId,
|
||||
FLEXCAN_ErrorInterruptCallBackType CAN_ErrorInterrupt_CallBack,
|
||||
FLEXCAN_RxInterruptCallBackType CAN_RxInterrupt_CallBack,
|
||||
FLEXCAN_RxInterruptCallBackType CAN_RxFifoInterrupt_CallBack,
|
||||
FLEXCAN_TxInterruptCallBackType CAN_TxInterrupt_CallBack,
|
||||
|
||||
DMA_TransferCompleteCallbackType DMA_TransferCompleteCallback,
|
||||
DMA_TransferErrorCallbackType DMA_ErrorCallback
|
||||
);
|
||||
|
||||
bool vCanSerialPortFrameMbInit(
|
||||
tCanSerialPortFrameFlagchip *env,
|
||||
FLEXCAN_Type *CANx, // FLEXCAN0
|
||||
uint8 CAN_INDEX, // CAN0 = 0 ... CAN3 = 3
|
||||
IRQn_Type IRQ_CAN, // FlexCAN0_IRQn ... FlexCAN3_IRQn
|
||||
uint8 CAN_PRIORITY,
|
||||
|
||||
const FilterTo_FLEXCAN_RxMbFilterType *IdHardSoftFilter_RX,
|
||||
uint8_t CountHardSoftFilter_RX,
|
||||
|
||||
FLEXCAN_BaudType canBaudRate,
|
||||
FLEXCAN_IdType canTypeFrame,
|
||||
uint32_t canId,
|
||||
FLEXCAN_ErrorInterruptCallBackType CAN_ErrorInterrupt_CallBack,
|
||||
FLEXCAN_RxInterruptCallBackType CAN_RxInterrupt_CallBack,
|
||||
FLEXCAN_RxInterruptCallBackType CAN_RxFifoInterrupt_CallBack,
|
||||
FLEXCAN_TxInterruptCallBackType CAN_TxInterrupt_CallBack
|
||||
|
||||
);
|
||||
|
||||
|
||||
void CAN_RxInterrupt_CallBack_Handler(tCanSerialPortFrameFlagchip *env, uint8_t u8CanIndex, FLEXCAN_RxMsgType *pRxCfg);
|
||||
|
||||
void CanSerialPortFrameIrqRxProcessing(tCanSerialPortFrameFlagchip *env, uint32_t *pBuf);
|
||||
|
||||
void CanSerialPortFrameIrqRxProcessingNO_DMA(tCanSerialPortFrameFlagchip *env, FLEXCAN_RxMsgType *pRxCfg);
|
||||
|
||||
void CanSerialPortFrameSetId(tCanSerialPortFrameFlagchip *env, uint32_t id);
|
||||
|
||||
void CanSerialPortFrameSetType(tCanSerialPortFrameFlagchip *env, FLEXCAN_IdType canTypeFrame);
|
||||
|
||||
tSerialPortFrameIO CanPortFrame_GetIo(tCanSerialPortFrameFlagchip *env);
|
||||
|
||||
tSerialPortFrameIO CanPortFrame_GetSnifferIo(tCanSerialPortFrameFlagchip *env);
|
||||
|
||||
bool vCanSerialPortSetMaskCount(tCanSerialPortFrameFlagchip *env, uint8_t maskCount);
|
||||
|
||||
#endif //FLAGCHIP_CAN_MODULE_CAN_FRAME_H
|
||||
|
|
@ -0,0 +1,920 @@
|
|||
//
|
||||
// Created by cfif on 16.03.2024.
|
||||
//
|
||||
#include <SystemDelayInterface.h>
|
||||
#include "CanSerialPortFrame.h"
|
||||
#include "memory.h"
|
||||
#include "candb.h"
|
||||
#include "CanPorts.h"
|
||||
|
||||
#define CAN_USED_NUM 2U // Количество CAN
|
||||
#define CAN_RECEIVE_MB_NUM 128 // Количество mailbox на один CAN
|
||||
|
||||
static FLEXCAN_RxMsgType s_aaRxDataBuf[CAN_USED_NUM][CAN_RECEIVE_MB_NUM];
|
||||
|
||||
#define CAN_GET_BUFFER(index) (FLEXCAN_RxMsgType*)s_aaRxDataBuf[index]
|
||||
|
||||
static const PCC_ClkSrcType s_ePccCanTable[] =
|
||||
{
|
||||
PCC_CLK_FLEXCAN0,
|
||||
PCC_CLK_FLEXCAN1,
|
||||
PCC_CLK_FLEXCAN2,
|
||||
PCC_CLK_FLEXCAN3
|
||||
};
|
||||
|
||||
static void BSP_CAN_INIT_CFG(FLEXCAN_InitType *pCfg) {
|
||||
pCfg->bListenOnly = 0U;
|
||||
pCfg->bEnBrs = 0;
|
||||
pCfg->bEnDma = 0;
|
||||
pCfg->bEnFd = 0;
|
||||
pCfg->bEnRxFifo = 0;
|
||||
pCfg->eBaudrate = FLEXCAN_BAUD_100K;
|
||||
pCfg->eClkSrcHz = FLEXCAN_BAUDCLK_HZ_8M;
|
||||
pCfg->eClkSrcSel = FLEXCAN_CLOCK_FUNCTION;
|
||||
pCfg->eDataBaud = FLEXCAN_BAUD_100K;
|
||||
pCfg->eMbDataWidth = FLEXCAN_DATAWIDTH_8;
|
||||
pCfg->u8EnhancedFifoDmaWM = 0;
|
||||
pCfg->eDirect = FLEXCAN_DIR_DISABLE;
|
||||
}
|
||||
|
||||
static void BSP_CAN_INIT_MBConfig(FLEXCAN_MBConfigType *pMbCfg) {
|
||||
pMbCfg->pRxFilterFifoList = NULL;
|
||||
pMbCfg->u8RxFilterFifoCnt = 0;
|
||||
pMbCfg->pRxFilterMBList = NULL;
|
||||
pMbCfg->u8RxFilterMBCnt = 0;
|
||||
pMbCfg->u8TxMsgCnt = 0;
|
||||
pMbCfg->pRxBuf = NULL;
|
||||
}
|
||||
|
||||
void CanSerialPortFrameSetId(tCanSerialPortFrameFlagchip *env, uint32_t id) {
|
||||
env->id = id;
|
||||
}
|
||||
|
||||
void CanSerialPortFrameSetType(tCanSerialPortFrameFlagchip *env, FLEXCAN_IdType canTypeFrame) {
|
||||
env->canTypeFrame = canTypeFrame;
|
||||
}
|
||||
|
||||
static void
|
||||
vCanSerialPortFrameInitStructure(tCanSerialPortFrameFlagchip *env, uint16_t rxDataLength, uint16_t rxSnifferLength) {
|
||||
|
||||
for (uint8_t i = 0; i < COUNT_QUEUE; ++i) {
|
||||
env->rxDataQueue[i] = osMessageQueueNew(rxDataLength, sizeof(can_rx_message_type), NULL);
|
||||
if (rxSnifferLength) {
|
||||
env->rxDataSnifferQueue[i] = osMessageQueueNew(rxSnifferLength, sizeof(can_rx_message_type), NULL);
|
||||
} else {
|
||||
env->rxDataSnifferQueue[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
bool vCanSerialPortFrameDMAInit(
|
||||
tCanSerialPortFrameFlagchip *env,
|
||||
FLEXCAN_Type *CANx, // FLEXCAN0
|
||||
uint8 CAN_INDEX, // CAN0 = 0 ... CAN3 = 3
|
||||
IRQn_Type IRQ_CAN, // FlexCAN0_IRQn ... FlexCAN3_IRQn
|
||||
uint8 CAN_PRIORITY,
|
||||
|
||||
DMA_ChannelType DMA_CHANNEL_RX,
|
||||
DMA_RequestSourceType DMA_CHANNEL_REQ_RX, // DMA_REQ_FLEXCAN0
|
||||
const uint8_t *DMA_BUF_RX,
|
||||
uint8_t DMA_BUF_LEN_RX,
|
||||
|
||||
const FilterTo_FLEXCAN_RxMbFilterType *IdHardSoftFilter_RX,
|
||||
uint8_t CountHardSoftFilter_RX,
|
||||
|
||||
const FLEXCAN_RxMbFilterType *IdFilterFifo_RX,
|
||||
uint8_t CountFilterFifo_RX,
|
||||
|
||||
IRQn_Type IRQ_DMA_RX,
|
||||
uint8_t IRQ_DMA_PRIORITY_RX,
|
||||
uint8_t IRQ_DMA_CHANNEL_PRIORITY_RX,
|
||||
|
||||
FLEXCAN_BaudType canBaudRate,
|
||||
FLEXCAN_IdType canTypeFrame,
|
||||
uint32_t canId,
|
||||
FLEXCAN_ErrorInterruptCallBackType CAN_ErrorInterrupt_CallBack,
|
||||
FLEXCAN_RxInterruptCallBackType CAN_RxInterrupt_CallBack,
|
||||
FLEXCAN_RxInterruptCallBackType CAN_RxFifoInterrupt_CallBack,
|
||||
FLEXCAN_TxInterruptCallBackType CAN_TxInterrupt_CallBack,
|
||||
|
||||
DMA_TransferCompleteCallbackType DMA_TransferCompleteCallback,
|
||||
DMA_TransferErrorCallbackType DMA_ErrorCallback
|
||||
) {
|
||||
env->g_u32RxDataIndex = 0;
|
||||
env->can = CANx;
|
||||
env->CAN_INDEX = CAN_INDEX;
|
||||
env->DMA_BUF_LEN_RX = DMA_BUF_LEN_RX;
|
||||
env->IdHardSoftFilter_RX = (FilterTo_FLEXCAN_RxMbFilterType *) IdHardSoftFilter_RX;
|
||||
env->CountHardSoftFilter_RX = CountHardSoftFilter_RX;
|
||||
env->canBaudRate = canBaudRate;
|
||||
env->IRQ_CAN = IRQ_CAN;
|
||||
|
||||
env->CAN_ErrorInterrupt_CallBack = CAN_ErrorInterrupt_CallBack;
|
||||
env->CAN_RxInterrupt_CallBack = CAN_RxInterrupt_CallBack;
|
||||
env->CAN_RxFifoInterrupt_CallBack = CAN_RxFifoInterrupt_CallBack;
|
||||
env->CAN_TxInterrupt_CallBack = CAN_TxInterrupt_CallBack;
|
||||
env->DMA_TransferCompleteCallback = DMA_TransferCompleteCallback;
|
||||
env->DMA_ErrorCallback = DMA_ErrorCallback;
|
||||
|
||||
//начало-----------------------------------DMA-RX-------------------------------------------------------------------
|
||||
//начало-----------------------------------DMA-RX-------------------------------------------------------------------
|
||||
//начало-----------------------------------DMA-RX-------------------------------------------------------------------
|
||||
|
||||
uint32_t u32TargetAddr = (uint32_t)(DMA_BUF_RX);
|
||||
|
||||
env->chnCfg_RX.pSrcBuffer = &(CANx->RAM[0]);
|
||||
env->chnCfg_RX.pDestBuffer = (void *) (u32TargetAddr);
|
||||
env->chnCfg_RX.u32BlockSize = DMA_BUF_LEN_RX;
|
||||
env->chnCfg_RX.u16BlockCount = 1U;
|
||||
env->chnCfg_RX.u8ChannelPriority = IRQ_DMA_CHANNEL_PRIORITY_RX;
|
||||
env->chnCfg_RX.eSrcDataSize = DMA_TRANSFER_SIZE_4B;
|
||||
env->chnCfg_RX.eDestDataSize = DMA_TRANSFER_SIZE_4B;
|
||||
env->chnCfg_RX.eSrcIncMode = DMA_INCREMENT_DATA_SIZE;
|
||||
env->chnCfg_RX.eDestIncMode = DMA_INCREMENT_DATA_SIZE;
|
||||
env->chnCfg_RX.bSrcBlockOffsetEn = 0U;
|
||||
env->chnCfg_RX.bDestBlockOffsetEn = 0U;
|
||||
env->chnCfg_RX.s32BlockOffset = 0;
|
||||
env->chnCfg_RX.bSrcAddrLoopbackEn = 1U;
|
||||
env->chnCfg_RX.bDestAddrLoopbackEn = false;
|
||||
env->chnCfg_RX.bAutoStop = 0U;
|
||||
env->chnCfg_RX.bSrcCircularBufferEn = false;
|
||||
env->chnCfg_RX.u32SrcCircBufferSize = DMA_CIRCULAR_BUFFER_SIZE_1B;
|
||||
env->chnCfg_RX.bDestCircularBufferEn = true;
|
||||
env->chnCfg_RX.u32DestCircBufferSize = 256U;
|
||||
env->chnCfg_RX.eTriggerSrc = DMA_CHANNEL_REQ_RX;
|
||||
DMA_InitChannel(DMA_INSTANCE_0, (DMA_ChannelType) DMA_CHANNEL_RX, &env->chnCfg_RX);
|
||||
|
||||
env->interruptCfg_RX.bTransferCompleteIntEn = 1;
|
||||
env->interruptCfg_RX.pTransferCompleteNotify = DMA_TransferCompleteCallback;
|
||||
env->interruptCfg_RX.bTransferErrorIntEn = 1;
|
||||
env->interruptCfg_RX.pTransferErrorNotify = DMA_ErrorCallback;
|
||||
|
||||
DMA_InitChannelInterrupt(DMA_INSTANCE_0, (DMA_ChannelType) DMA_CHANNEL_RX, &env->interruptCfg_RX);
|
||||
|
||||
NVIC_SetPriority(IRQ_DMA_RX, IRQ_DMA_PRIORITY_RX);
|
||||
NVIC_EnableIRQ(IRQ_DMA_RX);
|
||||
|
||||
DMA_StartChannel(DMA_INSTANCE_0, (DMA_ChannelType) DMA_CHANNEL_RX);
|
||||
|
||||
|
||||
//конец-----------------------------------DMA-RX--------------------------------------------------------------------
|
||||
//конец-----------------------------------DMA-RX--------------------------------------------------------------------
|
||||
//конец-----------------------------------DMA-RX--------------------------------------------------------------------
|
||||
|
||||
|
||||
//начало------------------------------------CAN---------------------------------------------------------------------
|
||||
//начало------------------------------------CAN---------------------------------------------------------------------
|
||||
//начало------------------------------------CAN---------------------------------------------------------------------
|
||||
|
||||
FLEXCAN_ErrorType tRetVal;
|
||||
uint32_t u32FuncClk;
|
||||
|
||||
tRetVal = FLEXCAN_DeInit(CAN_INDEX);
|
||||
|
||||
BSP_CAN_INIT_CFG(&env->tInitCfg);
|
||||
BSP_CAN_INIT_MBConfig(&env->tMbCfg);
|
||||
|
||||
env->tInitCfg.eBaudrate = canBaudRate;
|
||||
env->tInitCfg.eDataBaud = canBaudRate;
|
||||
env->tInitCfg.bEnRxFifo = TRUE;
|
||||
// env->tInitCfg.bEnRxFifo = FALSE;
|
||||
|
||||
env->tInitCfg.bEnDma = TRUE;
|
||||
// env->tInitCfg.bEnDma = FALSE;
|
||||
|
||||
env->tInitCfg.bEnFd = FALSE;
|
||||
env->tInitCfg.bEnBrs = FALSE;
|
||||
env->tInitCfg.eMbDataWidth = FLEXCAN_DATAWIDTH_8;
|
||||
|
||||
u32FuncClk = PCC_GetPccFunctionClock(s_ePccCanTable[CAN_INDEX]);
|
||||
|
||||
env->tInitCfg.eClkSrcSel = FLEXCAN_CLOCK_FUNCTION; // functional clock
|
||||
env->tInitCfg.eClkSrcHz = (FLEXCAN_BaudClkType) u32FuncClk; // function clock frequency
|
||||
|
||||
env->tInitCfg.eDirect = FLEXCAN_DIR_ENABLE_WITHOUT_TRIG;
|
||||
|
||||
tRetVal = FLEXCAN_Init(CAN_INDEX, &env->tInitCfg);
|
||||
|
||||
if (tRetVal == FLEXCAN_ERROR_OK) {
|
||||
|
||||
|
||||
env->tMbCfg.pRxFilterMBList = NULL;
|
||||
env->tMbCfg.u8RxFilterMBCnt = 0;
|
||||
|
||||
for (uint8_t i = 0; i < CountFilterFifo_RX; ++i) {
|
||||
env->pRxFilterFifoList[i].eRxFrameType = IdFilterFifo_RX[i].eRxFrameType;
|
||||
env->pRxFilterFifoList[i].u32RxCanId = IdFilterFifo_RX[i].u32RxCanId;
|
||||
env->pRxFilterFifoList[i].u32RxCanIdMask = IdFilterFifo_RX[i].u32RxCanIdMask;
|
||||
}
|
||||
|
||||
env->tMbCfg.pRxFilterFifoList = env->pRxFilterFifoList;
|
||||
env->tMbCfg.u8RxFilterFifoCnt = CountFilterFifo_RX;
|
||||
|
||||
env->tMbCfg.pRxBuf = CAN_GET_BUFFER(CAN_INDEX);
|
||||
|
||||
// tx config
|
||||
if (CAN_INDEX == 0) {
|
||||
env->tMbCfg.u8TxMsgCnt = COUNT_TX_CAN0_HANDLER; // tx occupy 3 mb
|
||||
}
|
||||
|
||||
if (CAN_INDEX == 1) {
|
||||
env->tMbCfg.u8TxMsgCnt = COUNT_TX_CAN1_HANDLER; // tx occupy 3 mb
|
||||
}
|
||||
|
||||
tRetVal = FLEXCAN_RxFilterConfig(CAN_INDEX, &env->tMbCfg);
|
||||
|
||||
if (CAN_ErrorInterrupt_CallBack == NULL) {
|
||||
env->tIntCfg.bEnErrorInterrupt = 0U;
|
||||
env->tIntCfg.pErrorNotify = NULL;
|
||||
} else {
|
||||
env->tIntCfg.bEnErrorInterrupt = 1U;
|
||||
env->tIntCfg.pErrorNotify = CAN_ErrorInterrupt_CallBack;
|
||||
}
|
||||
|
||||
if (CAN_TxInterrupt_CallBack == NULL) {
|
||||
env->tIntCfg.bEnTxMBInterrupt = 0U;
|
||||
env->tIntCfg.pTxMBNotify = NULL;
|
||||
} else {
|
||||
env->tIntCfg.bEnTxMBInterrupt = 1U;
|
||||
env->tIntCfg.pTxMBNotify = CAN_TxInterrupt_CallBack;
|
||||
}
|
||||
|
||||
if (CAN_RxInterrupt_CallBack == NULL) {
|
||||
env->tIntCfg.bEnRxMBInterrupt = 0U;
|
||||
env->tIntCfg.pRxMBNotify = NULL;
|
||||
} else {
|
||||
env->tIntCfg.bEnRxMBInterrupt = 1U;
|
||||
env->tIntCfg.pRxMBNotify = CAN_RxInterrupt_CallBack;
|
||||
}
|
||||
|
||||
if (CAN_RxFifoInterrupt_CallBack == NULL) {
|
||||
env->tIntCfg.bEnRxFifoInterrupt = 0U;
|
||||
env->tIntCfg.pRxFifoNotify = NULL;
|
||||
} else {
|
||||
env->tIntCfg.bEnRxFifoInterrupt = 1U;
|
||||
env->tIntCfg.pRxFifoNotify = CAN_RxFifoInterrupt_CallBack;
|
||||
}
|
||||
|
||||
if ((env->tIntCfg.bEnErrorInterrupt) ||
|
||||
(env->tIntCfg.bEnTxMBInterrupt) ||
|
||||
(env->tIntCfg.bEnRxMBInterrupt) ||
|
||||
(env->tIntCfg.bEnRxFifoInterrupt)) {
|
||||
|
||||
NVIC_SetPriority(IRQ_CAN, CAN_PRIORITY);
|
||||
NVIC_EnableIRQ(IRQ_CAN);
|
||||
|
||||
FLEXCAN_SetInterrupt(CAN_INDEX, &env->tIntCfg);
|
||||
|
||||
}
|
||||
|
||||
if (!env->reInitOne) {
|
||||
|
||||
env->reInitOne = true;
|
||||
|
||||
// for (uint8_t i = 0; i < COUNT_TX_HANDLER; ++i) {
|
||||
// env->access[i] = osMutexNew(NULL);
|
||||
// env->txDataQueueCan[i] = osMessageQueueNew(1, 1, NULL);
|
||||
// }
|
||||
env->access = osMutexNew(NULL);
|
||||
vCanSerialPortFrameInitStructure(env, 10, 0);
|
||||
|
||||
CanSerialPortFrameSetType(env, canTypeFrame);
|
||||
CanSerialPortFrameSetId(env, canId);
|
||||
|
||||
env->canBaudRate = canBaudRate;
|
||||
}
|
||||
|
||||
FLEXCAN_Start(CAN_INDEX); // Start CAN
|
||||
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
return true;
|
||||
//конец------------------------------------CAN----------------------------------------------------------------------
|
||||
//конец------------------------------------CAN----------------------------------------------------------------------
|
||||
//конец------------------------------------CAN----------------------------------------------------------------------
|
||||
}
|
||||
|
||||
|
||||
bool vCanSerialPortFrameMbInit(
|
||||
tCanSerialPortFrameFlagchip *env,
|
||||
FLEXCAN_Type *CANx, // FLEXCAN0
|
||||
uint8 CAN_INDEX, // CAN0 = 0 ... CAN3 = 3
|
||||
IRQn_Type IRQ_CAN, // FlexCAN0_IRQn ... FlexCAN3_IRQn
|
||||
uint8 CAN_PRIORITY,
|
||||
|
||||
const FilterTo_FLEXCAN_RxMbFilterType *IdHardSoftFilter_RX,
|
||||
uint8_t CountHardSoftFilter_RX,
|
||||
|
||||
FLEXCAN_BaudType canBaudRate,
|
||||
FLEXCAN_IdType canTypeFrame,
|
||||
uint32_t canId,
|
||||
FLEXCAN_ErrorInterruptCallBackType CAN_ErrorInterrupt_CallBack,
|
||||
FLEXCAN_RxInterruptCallBackType CAN_RxInterrupt_CallBack,
|
||||
FLEXCAN_RxInterruptCallBackType CAN_RxFifoInterrupt_CallBack,
|
||||
FLEXCAN_TxInterruptCallBackType CAN_TxInterrupt_CallBack
|
||||
|
||||
) {
|
||||
|
||||
env->g_u32RxDataIndex = 0;
|
||||
env->can = CANx;
|
||||
env->CAN_INDEX = CAN_INDEX;
|
||||
// env->DMA_BUF_LEN_RX = DMA_BUF_LEN_RX;
|
||||
env->IdHardSoftFilter_RX = (FilterTo_FLEXCAN_RxMbFilterType *) IdHardSoftFilter_RX;
|
||||
env->CountHardSoftFilter_RX = CountHardSoftFilter_RX;
|
||||
env->canBaudRate = canBaudRate;
|
||||
env->IRQ_CAN = IRQ_CAN;
|
||||
|
||||
env->CAN_ErrorInterrupt_CallBack = CAN_ErrorInterrupt_CallBack;
|
||||
env->CAN_RxInterrupt_CallBack = CAN_RxInterrupt_CallBack;
|
||||
env->CAN_RxFifoInterrupt_CallBack = CAN_RxFifoInterrupt_CallBack;
|
||||
env->CAN_TxInterrupt_CallBack = CAN_TxInterrupt_CallBack;
|
||||
// env->DMA_TransferCompleteCallback = DMA_TransferCompleteCallback;
|
||||
// env->DMA_ErrorCallback = DMA_ErrorCallback;
|
||||
|
||||
|
||||
//начало------------------------------------CAN---------------------------------------------------------------------
|
||||
//начало------------------------------------CAN---------------------------------------------------------------------
|
||||
//начало------------------------------------CAN---------------------------------------------------------------------
|
||||
|
||||
FLEXCAN_ErrorType tRetVal;
|
||||
uint32_t u32FuncClk;
|
||||
|
||||
tRetVal = FLEXCAN_DeInit(CAN_INDEX);
|
||||
|
||||
BSP_CAN_INIT_CFG(&env->tInitCfg);
|
||||
BSP_CAN_INIT_MBConfig(&env->tMbCfg);
|
||||
|
||||
env->tInitCfg.eBaudrate = canBaudRate;
|
||||
env->tInitCfg.eDataBaud = canBaudRate;
|
||||
// env->tInitCfg.bEnRxFifo = TRUE;
|
||||
env->tInitCfg.bEnRxFifo = FALSE;
|
||||
|
||||
// env->tInitCfg.bEnDma = TRUE;
|
||||
env->tInitCfg.bEnDma = FALSE;
|
||||
|
||||
env->tInitCfg.bEnFd = FALSE;
|
||||
env->tInitCfg.bEnBrs = FALSE;
|
||||
env->tInitCfg.eMbDataWidth = FLEXCAN_DATAWIDTH_8;
|
||||
|
||||
u32FuncClk = PCC_GetPccFunctionClock(s_ePccCanTable[CAN_INDEX]);
|
||||
|
||||
env->tInitCfg.eClkSrcSel = FLEXCAN_CLOCK_FUNCTION; // functional clock
|
||||
env->tInitCfg.eClkSrcHz = (FLEXCAN_BaudClkType) u32FuncClk; // function clock frequency
|
||||
|
||||
tRetVal = FLEXCAN_Init(CAN_INDEX, &env->tInitCfg);
|
||||
|
||||
if (tRetVal == FLEXCAN_ERROR_OK) {
|
||||
|
||||
for (uint8_t i = 0; i < CountHardSoftFilter_RX; ++i) {
|
||||
env->pRxMbFilterList[i].eRxFrameType = IdHardSoftFilter_RX[i].eRxFrameType;
|
||||
env->pRxMbFilterList[i].u32RxCanId = IdHardSoftFilter_RX[i].u32RxCanId;
|
||||
env->pRxMbFilterList[i].u32RxCanIdMask = IdHardSoftFilter_RX[i].u32RxCanIdMask;
|
||||
}
|
||||
|
||||
env->tMbCfg.pRxFilterMBList = env->pRxMbFilterList;
|
||||
env->tMbCfg.u8RxFilterMBCnt = CountHardSoftFilter_RX;
|
||||
|
||||
env->tMbCfg.pRxFilterFifoList = NULL;
|
||||
env->tMbCfg.u8RxFilterFifoCnt = 0;
|
||||
|
||||
env->tMbCfg.pRxBuf = CAN_GET_BUFFER(CAN_INDEX);
|
||||
|
||||
// tx config
|
||||
if (CAN_INDEX == 0) {
|
||||
env->tMbCfg.u8TxMsgCnt = COUNT_TX_CAN0_HANDLER; // tx occupy 3 mb
|
||||
}
|
||||
|
||||
if (CAN_INDEX == 1) {
|
||||
env->tMbCfg.u8TxMsgCnt = COUNT_TX_CAN1_HANDLER; // tx occupy 3 mb
|
||||
}
|
||||
|
||||
tRetVal = FLEXCAN_RxFilterConfig(CAN_INDEX, &env->tMbCfg);
|
||||
|
||||
if (CAN_ErrorInterrupt_CallBack == NULL) {
|
||||
env->tIntCfg.bEnErrorInterrupt = 0U;
|
||||
env->tIntCfg.pErrorNotify = NULL;
|
||||
} else {
|
||||
env->tIntCfg.bEnErrorInterrupt = 1U;
|
||||
env->tIntCfg.pErrorNotify = CAN_ErrorInterrupt_CallBack;
|
||||
}
|
||||
|
||||
if (CAN_TxInterrupt_CallBack == NULL) {
|
||||
env->tIntCfg.bEnTxMBInterrupt = 0U;
|
||||
env->tIntCfg.pTxMBNotify = NULL;
|
||||
} else {
|
||||
env->tIntCfg.bEnTxMBInterrupt = 1U;
|
||||
env->tIntCfg.pTxMBNotify = CAN_TxInterrupt_CallBack;
|
||||
}
|
||||
|
||||
if (CAN_RxInterrupt_CallBack == NULL) {
|
||||
env->tIntCfg.bEnRxMBInterrupt = 0U;
|
||||
env->tIntCfg.pRxMBNotify = NULL;
|
||||
} else {
|
||||
env->tIntCfg.bEnRxMBInterrupt = 1U;
|
||||
env->tIntCfg.pRxMBNotify = CAN_RxInterrupt_CallBack;
|
||||
}
|
||||
|
||||
if (CAN_RxFifoInterrupt_CallBack == NULL) {
|
||||
env->tIntCfg.bEnRxFifoInterrupt = 0U;
|
||||
env->tIntCfg.pRxFifoNotify = NULL;
|
||||
} else {
|
||||
env->tIntCfg.bEnRxFifoInterrupt = 1U;
|
||||
env->tIntCfg.pRxFifoNotify = CAN_RxFifoInterrupt_CallBack;
|
||||
}
|
||||
|
||||
|
||||
if ((env->tIntCfg.bEnErrorInterrupt) ||
|
||||
(env->tIntCfg.bEnTxMBInterrupt) ||
|
||||
(env->tIntCfg.bEnRxMBInterrupt) ||
|
||||
(env->tIntCfg.bEnRxFifoInterrupt)) {
|
||||
|
||||
NVIC_SetPriority(IRQ_CAN, CAN_PRIORITY);
|
||||
NVIC_EnableIRQ(IRQ_CAN);
|
||||
|
||||
FLEXCAN_SetInterrupt(CAN_INDEX, &env->tIntCfg);
|
||||
|
||||
}
|
||||
|
||||
if (!env->reInitOne) {
|
||||
env->reInitOne = true;
|
||||
|
||||
// for (uint8_t i = 0; i < COUNT_TX_HANDLER; ++i) {
|
||||
// env->access[i] = osMutexNew(NULL);
|
||||
// env->txDataQueueCan[i] = osMessageQueueNew(1, 1, NULL);
|
||||
// }
|
||||
|
||||
env->access = osMutexNew(NULL);
|
||||
vCanSerialPortFrameInitStructure(env, 10, 0);
|
||||
|
||||
CanSerialPortFrameSetType(env, canTypeFrame);
|
||||
CanSerialPortFrameSetId(env, canId);
|
||||
|
||||
env->canBaudRate = canBaudRate;
|
||||
}
|
||||
|
||||
FLEXCAN_Start(CAN_INDEX); // Start CAN
|
||||
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
return true;
|
||||
//конец------------------------------------CAN----------------------------------------------------------------------
|
||||
//конец------------------------------------CAN----------------------------------------------------------------------
|
||||
//конец------------------------------------CAN----------------------------------------------------------------------
|
||||
}
|
||||
|
||||
|
||||
bool vCanSerialPortSetMaskCount(tCanSerialPortFrameFlagchip *env, uint8_t maskCount) {
|
||||
FLEXCAN_ErrorType tRetVal;
|
||||
uint8_t i;
|
||||
|
||||
|
||||
// Отключаем прерывания CAN
|
||||
NVIC_DisableIRQ(env->IRQ_CAN);
|
||||
|
||||
// Останавливаем CAN модуль (переводим в режим заморозки)
|
||||
tRetVal = FLEXCAN_Stop(env->CAN_INDEX);
|
||||
if (tRetVal != FLEXCAN_ERROR_OK) {
|
||||
NVIC_EnableIRQ(env->IRQ_CAN);
|
||||
return false;
|
||||
}
|
||||
|
||||
// Обновляем список фильтров в рабочем буфере (первые maskCount элементов)
|
||||
for (i = 0; i < maskCount; i++) {
|
||||
env->pRxMbFilterList[i].eRxFrameType = env->IdHardSoftFilter_RX[i].eRxFrameType;
|
||||
env->pRxMbFilterList[i].u32RxCanId = env->IdHardSoftFilter_RX[i].u32RxCanId;
|
||||
env->pRxMbFilterList[i].u32RxCanIdMask = env->IdHardSoftFilter_RX[i].u32RxCanIdMask;
|
||||
}
|
||||
|
||||
for (i = maskCount; i < 32; i++) {
|
||||
env->pRxMbFilterList[i].eRxFrameType = env->IdHardSoftFilter_RX[0].eRxFrameType;
|
||||
env->pRxMbFilterList[i].u32RxCanId = env->IdHardSoftFilter_RX[0].u32RxCanId;
|
||||
env->pRxMbFilterList[i].u32RxCanIdMask = env->IdHardSoftFilter_RX[0].u32RxCanIdMask;
|
||||
}
|
||||
|
||||
|
||||
// Обновляем конфигурационную структуру для драйвера
|
||||
// env->CountHardSoftFilter_RX = maskCount;
|
||||
env->tMbCfg.pRxFilterMBList = env->pRxMbFilterList;
|
||||
// env->tMbCfg.u8RxFilterMBCnt = maskCount;
|
||||
|
||||
// Убеждаемся, что в tMbCfg сохранены правильные настройки TX
|
||||
// (они были установлены при инициализации и не должны измениться)
|
||||
// Если нужно, можно перечитать их из глобальной таблицы драйвера
|
||||
// но обычно они уже корректны.
|
||||
|
||||
// Переконфигурируем фильтры (без полной деинициализации CAN)
|
||||
tRetVal = FLEXCAN_RxFilterConfig(env->CAN_INDEX, &env->tMbCfg);
|
||||
|
||||
if (tRetVal != FLEXCAN_ERROR_OK) {
|
||||
// В случае ошибки пытаемся восстановить предыдущее состояние
|
||||
// (можно также попробовать перечитать старые фильтры)
|
||||
FLEXCAN_Start(env->CAN_INDEX);
|
||||
NVIC_EnableIRQ(env->IRQ_CAN);
|
||||
return false;
|
||||
}
|
||||
|
||||
// Запускаем CAN снова (выход из режима заморозки)
|
||||
tRetVal = FLEXCAN_Start(env->CAN_INDEX);
|
||||
if (tRetVal != FLEXCAN_ERROR_OK) {
|
||||
NVIC_EnableIRQ(env->IRQ_CAN);
|
||||
return false;
|
||||
}
|
||||
|
||||
// Включаем прерывания обратно
|
||||
NVIC_EnableIRQ(env->IRQ_CAN);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
static void CanSerialPortFrameAddDataQueue(tCanSerialPortFrameFlagchip *env, can_rx_message_type *rx_message_struct,
|
||||
uint8_t filter) {
|
||||
osStatus_t status = osMessageQueuePut(env->rxDataQueue[filter], rx_message_struct, 0x0, 0U);
|
||||
|
||||
if (status != osOK) {
|
||||
asm("nop");
|
||||
}
|
||||
|
||||
if (env->rxDataSnifferQueue[filter]) {
|
||||
status = osMessageQueuePut(env->rxDataSnifferQueue[filter], rx_message_struct, 0x0, 0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void CanSerialPortFrameIrqRxProcessingNO_DMA(tCanSerialPortFrameFlagchip *env, FLEXCAN_RxMsgType *pRxCfg) {
|
||||
if (pRxCfg->eDataType != FLEXCAN_FRAME_DATA) {
|
||||
return; // Ранний выход
|
||||
}
|
||||
|
||||
// Копируем основные данные один раз
|
||||
const uint32_t rx_id = pRxCfg->u32CanId;
|
||||
const uint8_t dlc = pRxCfg->u32DataLen;
|
||||
const FLEXCAN_IdType id_type = pRxCfg->eFrameType;
|
||||
|
||||
// Заполняем структуру
|
||||
can_rx_message_type *pMsg = &env->rx_message_struct;
|
||||
pMsg->dlc = dlc;
|
||||
pMsg->id_type = id_type;
|
||||
|
||||
if (id_type == FLEXCAN_ID_STD) {
|
||||
pMsg->standard_id = rx_id;
|
||||
} else {
|
||||
pMsg->extended_id = rx_id;
|
||||
}
|
||||
|
||||
// Быстрый поиск по ID (можно использовать switch или бинарный поиск)
|
||||
uint8_t filter_index = 0xFF;
|
||||
const uint8_t count = env->CountHardSoftFilter_RX;
|
||||
|
||||
// Линейный поиск ID
|
||||
for (uint8_t i = 0; i < count; i++) {
|
||||
if (rx_id == env->IdHardSoftFilter_RX[i].u32RxCanId) {
|
||||
filter_index = env->IdHardSoftFilter_RX[i].filter;
|
||||
pMsg->filter_index = filter_index;
|
||||
|
||||
if (i > 2) {
|
||||
asm("nop");
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Если ID найден или фильтров нет
|
||||
if (filter_index != 0xFF || count == 0) {
|
||||
|
||||
memcpy(pMsg->data, pRxCfg->aData, dlc);
|
||||
CanSerialPortFrameAddDataQueue(env, pMsg, filter_index != 0xFF ? filter_index : 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void CanSerialPortFrameIrqRxProcessing(tCanSerialPortFrameFlagchip *env, uint32_t *pBuf) {
|
||||
|
||||
// message buffer 1th word
|
||||
uint32_t u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&pBuf[env->pBufCounter << 2], 0U, 8U, 0U);
|
||||
|
||||
uint32_t dlc = FLEXCAN_MB_DLC_GET(u32TempAddr);
|
||||
env->rx_message_struct.dlc = FLEXCAN_DlcToDataLen(dlc);
|
||||
|
||||
env->rx_message_struct.id_type = FLEXCAN_MB_IDE_GET(u32TempAddr);
|
||||
|
||||
// message buffer 2th word
|
||||
u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&pBuf[env->pBufCounter << 2], 0U, 8U, 4U);
|
||||
|
||||
if (env->rx_message_struct.id_type == FLEXCAN_ID_STD) {
|
||||
env->rx_message_struct.standard_id = FLEXCAN_MB_STDID_GET(u32TempAddr);
|
||||
} else {
|
||||
env->rx_message_struct.extended_id = FLEXCAN_MB_EXTID_GET(u32TempAddr);
|
||||
}
|
||||
|
||||
uint8_t index = 0xFF;
|
||||
|
||||
for (uint8_t i = 0; i < env->CountHardSoftFilter_RX; ++i) {
|
||||
|
||||
if ((env->rx_message_struct.id_type == FLEXCAN_ID_STD) &&
|
||||
(env->IdHardSoftFilter_RX[i].eRxFrameType == FLEXCAN_ID_STD)) {
|
||||
|
||||
if (env->rx_message_struct.standard_id == env->IdHardSoftFilter_RX[i].u32RxCanId) {
|
||||
env->rx_message_struct.filter_index = env->IdHardSoftFilter_RX[i].filter;
|
||||
index = i;
|
||||
break;
|
||||
}
|
||||
|
||||
} else {
|
||||
|
||||
if (env->rx_message_struct.extended_id == env->IdHardSoftFilter_RX[i].u32RxCanId) {
|
||||
|
||||
if (env->rx_message_struct.extended_id == env->IdHardSoftFilter_RX[i].u32RxCanId) {
|
||||
env->rx_message_struct.filter_index = env->IdHardSoftFilter_RX[i].filter;
|
||||
index = i;
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
if (index != 0xFF) {
|
||||
|
||||
// message buffer 3th word
|
||||
uint32_t *pSrc = (uint32_t * )FLEXCAN_MB_WORDN_ADDR(&pBuf[env->pBufCounter << 2], 0U, 8U, 8U);
|
||||
uint32_t *pDest = (uint32_t * ) & env->rx_message_struct.data[0];
|
||||
|
||||
uint32_t u32WordLen = env->rx_message_struct.dlc / 4U + (env->rx_message_struct.dlc % 4U > 0U ? 1U : 0U);
|
||||
|
||||
for (uint32_t u8Index = 0U; u8Index < u32WordLen; ++u8Index) {
|
||||
REV_BYTES_32(pSrc[u8Index], pDest[u8Index]);
|
||||
}
|
||||
|
||||
CanSerialPortFrameAddDataQueue(env, &env->rx_message_struct, env->IdHardSoftFilter_RX[index].filter);
|
||||
|
||||
}
|
||||
|
||||
if (env->CountHardSoftFilter_RX == 0) {
|
||||
// message buffer 3th word
|
||||
uint32_t *pSrc = (uint32_t * )FLEXCAN_MB_WORDN_ADDR(&pBuf[env->pBufCounter << 2], 0U, 8U, 8U);
|
||||
uint32_t *pDest = (uint32_t * ) & env->rx_message_struct.data[0];
|
||||
|
||||
uint32_t u32WordLen = env->rx_message_struct.dlc / 4U + (env->rx_message_struct.dlc % 4U > 0U ? 1U : 0U);
|
||||
|
||||
for (uint32_t u8Index = 0U; u8Index < u32WordLen; ++u8Index) {
|
||||
REV_BYTES_32(pSrc[u8Index], pDest[u8Index]);
|
||||
}
|
||||
|
||||
CanSerialPortFrameAddDataQueue(env, &env->rx_message_struct, 0);
|
||||
}
|
||||
|
||||
++env->pBufCounter;
|
||||
|
||||
if (env->pBufCounter >= env->DMA_BUF_LEN_RX) {
|
||||
env->pBufCounter = 0;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static uint16_t vSerialPortFrameReceiveQueue(
|
||||
tCanSerialPortFrameFlagchip *env, uint8_t *data, uint16_t size, uint32_t timeout, osMessageQueueId_t queueId
|
||||
) {
|
||||
uint16_t received = 0;
|
||||
|
||||
if (timeout) {
|
||||
uint32_t endMs = SystemGetMs() + timeout;
|
||||
uint32_t leftMs;
|
||||
|
||||
while (size && ((timeout == SystemWaitForever) || (endMs > SystemGetMs()))) {
|
||||
leftMs = endMs - SystemGetMs();
|
||||
if (osMessageQueueGet(queueId, data, NULL, leftMs) == osOK) {
|
||||
--size;
|
||||
++received;
|
||||
++data;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
while (size) {
|
||||
if (osMessageQueueGet(queueId, data, NULL, 0) == osOK) {
|
||||
--size;
|
||||
++received;
|
||||
++data;
|
||||
} else {
|
||||
return received;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return received;
|
||||
}
|
||||
|
||||
static uint16_t
|
||||
vCanSerialPortFrameReceive(tCanSerialPortFrameFlagchip *env, uint8_t idFilter, uint8_t *data, uint16_t size,
|
||||
uint32_t timeout) {
|
||||
return vSerialPortFrameReceiveQueue(env, data, size, timeout, env->rxDataQueue[idFilter]);
|
||||
}
|
||||
|
||||
//static uint16_t
|
||||
//vCanSerialPortFrameReceiveSniffer(tCanSerialPortFrameFlagchip *env, uint8_t idFilter, uint8_t *data, uint16_t size,
|
||||
// uint32_t timeout) {
|
||||
|
||||
// return env->rxDataSnifferQueue
|
||||
// ? vSerialPortFrameReceiveQueue(env, data, size, timeout, env->rxDataSnifferQueue[idFilter])
|
||||
// : 0;
|
||||
//}
|
||||
|
||||
#define TRANSMIT_MULTI_FRAME_TX 1
|
||||
|
||||
//#define TRANSMIT_MULTI_FRAME_DBG_TX 1
|
||||
|
||||
#ifdef TRANSMIT_MULTI_FRAME_DBG_TX
|
||||
uint8_t max0_i =0;
|
||||
uint8_t max1_i =0;
|
||||
|
||||
uint8_t handler_0[1000];
|
||||
uint16_t handler_0_cnt = 0;
|
||||
|
||||
uint8_t handler_1[1000];
|
||||
uint16_t handler_1_cnt = 0;
|
||||
|
||||
#endif
|
||||
|
||||
static FLEXCAN_ErrorType SendToCan(tCanSerialPortFrameFlagchip *env, FLEXCAN_TxMsgType *const pTxMsg, uint32_t timeout) {
|
||||
FLEXCAN_ErrorType tRetval = FLEXCAN_ERROR_TIMEOUT;
|
||||
|
||||
#ifdef TRANSMIT_MULTI_FRAME_TX
|
||||
uint8_t ready = 0;
|
||||
|
||||
uint32_t endMs = SystemGetMs() + timeout;
|
||||
|
||||
while ((ready == 0) && (endMs > SystemGetMs())) {
|
||||
|
||||
if (env->CAN_INDEX == 0) {
|
||||
for (uint8_t i = 0; i < COUNT_TX_CAN0_HANDLER; ++i) {
|
||||
ready = IsTxBufferFree_ByCode(env->CAN_INDEX, i);
|
||||
|
||||
if (ready) {
|
||||
pTxMsg->u8TxHandler = i;
|
||||
break;
|
||||
} else {
|
||||
#ifdef TRANSMIT_MULTI_FRAME_DBG_TX
|
||||
handler_0[handler_0_cnt] = i;
|
||||
handler_0_cnt++;
|
||||
if (handler_0_cnt >= 1000) {
|
||||
handler_0_cnt = 0;
|
||||
}
|
||||
|
||||
if (i > max0_i) {
|
||||
max0_i = i;
|
||||
}
|
||||
|
||||
if (max0_i >= COUNT_TX_CAN0_HANDLER) {
|
||||
asm("nop");
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
if (env->CAN_INDEX == 1) {
|
||||
for (uint8_t i = 0; i < COUNT_TX_CAN1_HANDLER; ++i) {
|
||||
ready = IsTxBufferFree_ByCode(env->CAN_INDEX, i);
|
||||
|
||||
if (ready) {
|
||||
pTxMsg->u8TxHandler = i;
|
||||
break;
|
||||
} else {
|
||||
#ifdef TRANSMIT_MULTI_FRAME_DBG_TX
|
||||
handler_1[handler_1_cnt] = i;
|
||||
handler_1_cnt++;
|
||||
if (handler_1_cnt >= 1000) {
|
||||
handler_1_cnt = 0;
|
||||
}
|
||||
|
||||
if (i > max1_i) {
|
||||
max1_i = i;
|
||||
}
|
||||
|
||||
if (max1_i >= COUNT_TX_CAN1_HANDLER) {
|
||||
asm("nop");
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
pTxMsg->bWaitTxCompleted = 0;
|
||||
|
||||
tRetval = FLEXCAN_TransmitData(env->CAN_INDEX, pTxMsg);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#ifndef TRANSMIT_MULTI_FRAME_TX
|
||||
tRetval = FLEXCAN_TransmitData(env->CAN_INDEX, pTxMsg);
|
||||
if (tRetval != FLEXCAN_ERROR_OK) {
|
||||
FLEXCAN_TransmitAbort(env->CAN_INDEX, pTxMsg->u8TxHandler);
|
||||
} else {
|
||||
FLEXCAN_TransmitProcess(env->CAN_INDEX, pTxMsg->u8TxHandler);
|
||||
}
|
||||
#endif
|
||||
|
||||
return tRetval;
|
||||
}
|
||||
|
||||
|
||||
uint16_t vCanSerialPortFrameTransmit(tCanSerialPortFrameFlagchip *env, uint8_t *data, uint16_t size, uint32_t adr,
|
||||
uint8_t canType, uint32_t timeout) {
|
||||
|
||||
|
||||
timeout = 5;
|
||||
|
||||
uint16_t sent = 0;
|
||||
|
||||
if (osMutexAcquire(env->access, 1000) == osOK) {
|
||||
|
||||
env->id = adr;
|
||||
env->canTypeFrame = canType;
|
||||
|
||||
uint16_t fullSize = size / 8;
|
||||
uint8_t tailSize = size % 8;
|
||||
|
||||
FLEXCAN_TxMsgType tTxMsg = {0};
|
||||
FLEXCAN_ErrorType tRetval;
|
||||
|
||||
tTxMsg.u32CanId = env->id;
|
||||
tTxMsg.u8TxHandler = 0U;
|
||||
|
||||
tTxMsg.bEnFd = FALSE;
|
||||
tTxMsg.bEnBrs = FALSE;
|
||||
tTxMsg.u32DataLen = 8;
|
||||
|
||||
tTxMsg.eDataType = FLEXCAN_FRAME_DATA;
|
||||
tTxMsg.eFrameType = (FLEXCAN_IdType) env->canTypeFrame;
|
||||
tTxMsg.bWaitTxCompleted = 1U;
|
||||
tTxMsg.u16WaitTxTimeout = 500000U;
|
||||
|
||||
|
||||
uint16_t len = 0;
|
||||
for (uint16_t i = 0; i < fullSize; ++i) {
|
||||
|
||||
FCFUNC_FcOwnMemcpy(tTxMsg.aData, &data[len], 8, NULL);
|
||||
len += 8;
|
||||
|
||||
tRetval = SendToCan(env, &tTxMsg, timeout);
|
||||
|
||||
sent += 8;
|
||||
size -= 8;
|
||||
}
|
||||
|
||||
if (tailSize) {
|
||||
tTxMsg.u32DataLen = tailSize;
|
||||
|
||||
FCFUNC_FcOwnMemcpy(tTxMsg.aData, &data[len], tailSize, NULL);
|
||||
|
||||
tRetval = SendToCan(env, &tTxMsg, timeout);
|
||||
|
||||
sent += tailSize;
|
||||
size -= tailSize;
|
||||
}
|
||||
|
||||
osMutexRelease(env->access);
|
||||
}
|
||||
|
||||
return sent;
|
||||
}
|
||||
|
||||
|
||||
tSerialPortFrameIO CanPortFrame_GetIo(tCanSerialPortFrameFlagchip *env) {
|
||||
tSerialPortFrameIO io = {
|
||||
.env = env,
|
||||
.receive = (SerialPortFrameReceivedTransaction) vCanSerialPortFrameReceive,
|
||||
.transmit = (SerialPortFrameTransmitTransaction) vCanSerialPortFrameTransmit
|
||||
};
|
||||
return io;
|
||||
}
|
||||
|
||||
tSerialPortFrameIO CanPort_GetSnifferIo(tCanSerialPortFrameFlagchip *env) {
|
||||
tSerialPortFrameIO io = {
|
||||
.env = env,
|
||||
.receive = (SerialPortFrameReceivedTransaction) vCanSerialPortFrameReceive,
|
||||
.transmit = (SerialPortFrameTransmitTransaction) vCanSerialPortFrameTransmit
|
||||
};
|
||||
return io;
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
{
|
||||
"dep": [
|
||||
{
|
||||
"type": "local",
|
||||
|
||||
"dir": "./MODULES/SerialPort"
|
||||
},
|
||||
{
|
||||
"type": "local",
|
||||
|
||||
"dir": "./MODULES/SerialPortFrameInterface"
|
||||
}
|
||||
],
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
],
|
||||
"srcs": [
|
||||
"Src/**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,155 @@
|
|||
//
|
||||
// Created by cfif on 16.03.2024.
|
||||
//
|
||||
|
||||
#ifndef CAN_MODULE_CAN_FRAME_UDS_H
|
||||
#define CAN_MODULE_CAN_FRAME_UDS_H
|
||||
|
||||
#include "SerialPortFrameIO.h"
|
||||
#include "CanSerialPortFrame.h"
|
||||
#include "LoggerToSerialPort.h"
|
||||
#include "CmsisRtosThreadUtils.h"
|
||||
#include "SystemMutexCmsis.h"
|
||||
|
||||
#define LOG_UDS_TP 0
|
||||
|
||||
#define TP_FRAME_PADDING 0xAA
|
||||
|
||||
#define WAIT_FC_FRAME_TIMEOUT 2000
|
||||
#define WAIT_FF_FRAME_TIMEOUT 2000
|
||||
|
||||
#define WAIT_FRAME_WRITE 100
|
||||
|
||||
#define LEN_DEBUG_TP_BUFF 128
|
||||
|
||||
#define timeout_StMin 50 // Сепаратор между многокадровыми сообщениями
|
||||
#define timeout_Br 10 // Перед отправкой FlowControl (для получения остальных данных)
|
||||
|
||||
typedef enum {
|
||||
TP_TYPE_FRAME_SF = 0,
|
||||
TP_TYPE_FRAME_FF = 1,
|
||||
TP_TYPE_FRAME_CF = 2,
|
||||
TP_TYPE_FRAME_FC = 3
|
||||
} eTpTypeFrame;
|
||||
|
||||
typedef enum {
|
||||
TP_RECEIVED_DATA = 0,
|
||||
TP_RECEIVED_FC_DATA = 1,
|
||||
TP_ERROR_FS_ERROR_SIZE = 2,
|
||||
TP_ERROR_FC_TIMEOUT = 3,
|
||||
TP_ERROR_FC_ERROR = 4,
|
||||
TP_ERROR_FF_ERROR = 5,
|
||||
TP_ERROR_FF_ERROR_SIZE = 6,
|
||||
TP_ERROR_FF_ERROR_TIMEOUT = 7,
|
||||
TP_ERROR_CF_ERROR = 8,
|
||||
TP_ERROR_CF_ERROR_SIZE = 9,
|
||||
TP_ERROR_CF_ERROR_SN = 10,
|
||||
TP_ERROR_WRONG_ADDRESS= 11,
|
||||
TP_STANDBY = 12,
|
||||
TP_ERROR_SF_ERROR = 13
|
||||
|
||||
} eTpResult;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eTpTypeFrame typeFrame: 4;
|
||||
} eTpFrameHead;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
uint8_t dl: 4;
|
||||
eTpTypeFrame typeFrame: 4;
|
||||
uint8_t data[7];
|
||||
} eTpFrameSF;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
uint8_t dlM: 4;
|
||||
eTpTypeFrame typeFrame: 4;
|
||||
uint8_t dlL;
|
||||
uint8_t data[6];
|
||||
} eTpFrameFF;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
uint8_t sn: 4;
|
||||
eTpTypeFrame typeFrame: 4;
|
||||
uint8_t data[7];
|
||||
} eTpFrameCF;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
uint8_t status: 4;
|
||||
eTpTypeFrame typeFrame: 4;
|
||||
uint8_t blockSize;
|
||||
uint8_t timeST;
|
||||
} eTpFrameFC;
|
||||
|
||||
typedef struct {
|
||||
uint32_t adrCan;
|
||||
uint16_t len;
|
||||
uint8_t data[4096];
|
||||
} tCanTP_data;
|
||||
|
||||
typedef void (*tReceivedTP_func)(void *arg, tCanTP_data *data);
|
||||
typedef bool (*tReceivedCan_func)(void *arg, can_rx_message_type *data);
|
||||
|
||||
typedef struct {
|
||||
tSerialPortFrameIO *ioCanFrame;
|
||||
tLoggerInterface *logger;
|
||||
char hexString[LEN_DEBUG_TP_BUFF];
|
||||
bool isFlowControl;
|
||||
|
||||
uint32_t timeoutFF;
|
||||
|
||||
tCanTP_data *dataBuf;
|
||||
uint16_t dataBufMaxSize;
|
||||
uint16_t dataBufWorkLen;
|
||||
uint16_t dataBufLen;
|
||||
|
||||
uint16_t dataReceivedConsecutiveFrameLen;
|
||||
uint8_t sn;
|
||||
|
||||
tReceivedCan_func ReceivedCan_func;
|
||||
void *callback_argCan;
|
||||
|
||||
tReceivedTP_func receivedTP_func;
|
||||
void *callback_argTp;
|
||||
|
||||
uint8_t filterIdCount;
|
||||
uint32_t *filterReqId;
|
||||
uint32_t *filterRespId;
|
||||
uint8_t *filterDirReq;
|
||||
|
||||
struct {
|
||||
osThreadId_t id;
|
||||
uint32_t stack[384];
|
||||
StaticTask_t controlBlock;
|
||||
osThreadAttr_t attr;
|
||||
} threadCanListener;
|
||||
|
||||
// tStaticThreadBlock(384) T_can_Listener;
|
||||
} tCanSerialPortFrameTp;
|
||||
|
||||
void CanSerialPortFrameTpInit(
|
||||
tCanSerialPortFrameTp *env,
|
||||
|
||||
|
||||
tReceivedCan_func receivedCan_func,
|
||||
void *callback_argCan,
|
||||
|
||||
tReceivedTP_func receivedTP_func,
|
||||
void *callback_argTp,
|
||||
|
||||
tSerialPortFrameIO *ioCanFrame,
|
||||
tCanTP_data *dataBuf,
|
||||
uint16_t dataBufMaxSize,
|
||||
tLoggerInterface *logger,
|
||||
|
||||
uint8_t filterIdCount,
|
||||
uint32_t *filterReqId,
|
||||
uint32_t *filterRespId,
|
||||
uint8_t *filterDirReq
|
||||
);
|
||||
|
||||
void CanSerialPortFrameTp_Start(tCanSerialPortFrameTp *env);
|
||||
|
||||
bool
|
||||
CanSerialPortFrameTpTransmit(tCanSerialPortFrameTp *env, uint8_t *data, uint16_t size, uint32_t id, uint32_t timeout);
|
||||
|
||||
#endif //CAN_MODULE_CAN_FRAME_UDS_H
|
||||
|
|
@ -0,0 +1,535 @@
|
|||
//
|
||||
// Created by cfif on 16.03.2024.
|
||||
//
|
||||
#include <SystemDelayInterface.h>
|
||||
#include "CanSerialPortFrameTP.h"
|
||||
#include "memory.h"
|
||||
#include "AsciiStringAssmeblingUtils.h"
|
||||
#include "SystemMutexCmsis.h"
|
||||
#include "CanPorts.h"
|
||||
#include <stdio.h>
|
||||
|
||||
#define LOG_SIGN "CAN_TP"
|
||||
#define LOGGER env->logger
|
||||
|
||||
|
||||
static char strPrintfDebug_TP[80];
|
||||
|
||||
static void PrintfDebug(uint8_t *data, uint8_t dlc) {
|
||||
|
||||
switch (dlc) {
|
||||
|
||||
case 0:
|
||||
sprintf(strPrintfDebug_TP, " ");
|
||||
break;
|
||||
case 1:
|
||||
sprintf(strPrintfDebug_TP, "%02X", data[0]);
|
||||
break;
|
||||
case 2:
|
||||
sprintf(strPrintfDebug_TP, "%02X:%02X", data[0], data[1]);
|
||||
break;
|
||||
case 3:
|
||||
sprintf(strPrintfDebug_TP, "%02X:%02X:%02X", data[0], data[1], data[2]);
|
||||
break;
|
||||
case 4:
|
||||
sprintf(strPrintfDebug_TP, "%02X:%02X:%02X:%02X", data[0], data[1], data[2], data[3]);
|
||||
break;
|
||||
case 5:
|
||||
sprintf(strPrintfDebug_TP, "%02X:%02X:%02X:%02X:%02X", data[0], data[1], data[2], data[3],
|
||||
data[4]);
|
||||
break;
|
||||
case 6:
|
||||
sprintf(strPrintfDebug_TP, "%02X:%02X:%02X:%02X:%02X:%02X", data[0], data[1], data[2], data[3],
|
||||
data[4], data[5]);
|
||||
break;
|
||||
case 7:
|
||||
sprintf(strPrintfDebug_TP, "%02X:%02X:%02X:%02X:%02X:%02X:%02X", data[0], data[1], data[2],
|
||||
data[3], data[4],
|
||||
data[5], data[6]);
|
||||
break;
|
||||
case 8:
|
||||
sprintf(strPrintfDebug_TP, "%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X ", data[0], data[1],
|
||||
data[2], data[3], data[4],
|
||||
data[5], data[6], data[7]);
|
||||
break;
|
||||
default:
|
||||
sprintf(strPrintfDebug_TP, " ");
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
char *sendLogCanTpHex(tCanSerialPortFrameTp *env, uint8_t *data, size_t size) {
|
||||
memset(env->hexString, 0, sizeof(env->hexString));
|
||||
size_t len = 0;
|
||||
|
||||
|
||||
uint8_t full = size / 8;
|
||||
uint8_t tail = size % 8;
|
||||
|
||||
for (uint8_t i = 0; i < full; ++i) {
|
||||
PrintfDebug(&data[i * 8], 8);
|
||||
|
||||
if ((len + strlen(strPrintfDebug_TP)) < LEN_DEBUG_TP_BUFF) {
|
||||
memcpy(&env->hexString[len], strPrintfDebug_TP, strlen(strPrintfDebug_TP));
|
||||
len += strlen(strPrintfDebug_TP);
|
||||
} else {
|
||||
return env->hexString;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (tail > 0) {
|
||||
PrintfDebug(&data[full * 8], tail);
|
||||
|
||||
if ((len + strlen(strPrintfDebug_TP)) < LEN_DEBUG_TP_BUFF) {
|
||||
memcpy(&env->hexString[len], strPrintfDebug_TP, strlen(strPrintfDebug_TP));
|
||||
len += strlen(strPrintfDebug_TP);
|
||||
} else {
|
||||
return env->hexString;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return env->hexString;
|
||||
}
|
||||
|
||||
uint16_t sendFlowFrame(tCanSerialPortFrameTp *env, uint32_t id, uint32_t timeout) {
|
||||
uint8_t dataTpFrame[8];
|
||||
|
||||
memset(dataTpFrame, TP_FRAME_PADDING, sizeof(dataTpFrame));
|
||||
|
||||
eTpFrameFC *frame = (eTpFrameFC *) dataTpFrame;
|
||||
frame->typeFrame = TP_TYPE_FRAME_FC;
|
||||
frame->status = 0;
|
||||
frame->blockSize = 0;
|
||||
frame->timeST = 0;
|
||||
|
||||
// SystemDelayMs(timeout_Br);
|
||||
uint16_t sent = env->ioCanFrame->transmit(env->ioCanFrame->env, (uint8_t *) frame, 8, id,
|
||||
PROTOCOL_CAN_TYPE_UDS, timeout);
|
||||
|
||||
return sent;
|
||||
}
|
||||
|
||||
|
||||
uint16_t sendSingleFrame(tCanSerialPortFrameTp *env, uint8_t *data, uint16_t size, uint32_t id, uint32_t timeout) {
|
||||
uint8_t dataTpFrame[8];
|
||||
|
||||
memset(dataTpFrame, TP_FRAME_PADDING, sizeof(dataTpFrame));
|
||||
|
||||
eTpFrameSF *frame = (eTpFrameSF *) dataTpFrame;
|
||||
frame->typeFrame = TP_TYPE_FRAME_SF;
|
||||
frame->dl = size;
|
||||
|
||||
memcpy(&frame->data[0], data, size);
|
||||
|
||||
// SystemDelayMs(timeout_Br); // ??
|
||||
uint16_t sent = env->ioCanFrame->transmit(env->ioCanFrame->env, (uint8_t *) frame, 8, id,
|
||||
PROTOCOL_CAN_TYPE_UDS, timeout);
|
||||
|
||||
return sent;
|
||||
}
|
||||
|
||||
uint16_t sendConsecutiveFrame(tCanSerialPortFrameTp *env, uint8_t *data, uint16_t size, uint32_t id, uint8_t sn,
|
||||
uint32_t timeout) {
|
||||
|
||||
uint8_t dataTpFrame[8];
|
||||
memset(dataTpFrame, TP_FRAME_PADDING, sizeof(dataTpFrame));
|
||||
|
||||
eTpFrameCF *frame = (eTpFrameCF *) dataTpFrame;
|
||||
frame->typeFrame = TP_TYPE_FRAME_CF;
|
||||
frame->sn = sn;
|
||||
|
||||
memcpy(&frame->data[0], data, size);
|
||||
|
||||
SystemDelayMs(timeout_StMin);
|
||||
|
||||
uint16_t sent = env->ioCanFrame->transmit(env->ioCanFrame->env, (uint8_t *) frame, 8, id,
|
||||
PROTOCOL_CAN_TYPE_UDS, timeout);
|
||||
|
||||
|
||||
return sent;
|
||||
|
||||
}
|
||||
|
||||
eTpResult vCanSerialPortFrameTpReceive(tCanSerialPortFrameTp *env, uint32_t timeout) {
|
||||
can_rx_message_type canFrame;
|
||||
|
||||
if ((env->timeoutFF > 0) && (env->timeoutFF < SystemGetMs())) {
|
||||
env->timeoutFF = 0;
|
||||
env->dataReceivedConsecutiveFrameLen = 0;
|
||||
env->dataBufLen = 0;
|
||||
env->dataBufWorkLen = 0;
|
||||
|
||||
return TP_ERROR_FF_ERROR_TIMEOUT;
|
||||
}
|
||||
|
||||
uint16_t recv = 0;
|
||||
|
||||
recv = env->ioCanFrame->receive(env->ioCanFrame->env, PROTOCOL_CAN_UDS, (uint8_t *) &canFrame, 1, timeout);
|
||||
|
||||
if (recv == 0)
|
||||
return TP_STANDBY;
|
||||
|
||||
bool isTesterPresent = env->ReceivedCan_func(env->callback_argCan, &canFrame);
|
||||
|
||||
if (isTesterPresent) {
|
||||
return TP_STANDBY;
|
||||
}
|
||||
|
||||
bool isFilterFind = false;
|
||||
uint32_t reqId = 0;
|
||||
for (uint8_t i = 0; i < env->filterIdCount; ++i) {
|
||||
if (canFrame.standard_id == env->filterReqId[i]) {
|
||||
|
||||
reqId = env->filterRespId[i];
|
||||
|
||||
isFilterFind = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!isFilterFind) {
|
||||
return TP_ERROR_WRONG_ADDRESS;
|
||||
}
|
||||
|
||||
|
||||
if ((recv > 0) && (canFrame.dlc == 8)) {
|
||||
|
||||
// Flow control Frame – FC – фрейм управления потоком
|
||||
if ((canFrame.data[0] >> 4) == TP_TYPE_FRAME_FC) {
|
||||
eTpFrameFC *frame = (eTpFrameFC *) canFrame.data;
|
||||
|
||||
if (frame->status == 0)
|
||||
return TP_RECEIVED_FC_DATA;
|
||||
|
||||
return TP_ERROR_FC_ERROR;
|
||||
}
|
||||
|
||||
// Single Frame SF – Однократный фрейм
|
||||
if ((canFrame.data[0] >> 4) == TP_TYPE_FRAME_SF) {
|
||||
|
||||
if (env->dataReceivedConsecutiveFrameLen) {
|
||||
return TP_ERROR_SF_ERROR;
|
||||
}
|
||||
|
||||
eTpFrameSF *frame = (eTpFrameSF *) canFrame.data;
|
||||
|
||||
if (frame->dl < env->dataBufMaxSize) {
|
||||
//memcpy(env->dataBuf, &canFrame.data[1], frame->dl);
|
||||
env->dataBufLen = frame->dl;
|
||||
|
||||
memcpy(env->dataBuf->data, &canFrame.data[1], frame->dl);
|
||||
env->dataBuf->len = env->dataBufLen;
|
||||
env->dataBuf->adrCan = canFrame.standard_id;
|
||||
|
||||
env->dataBufWorkLen = 0;
|
||||
return TP_RECEIVED_DATA;
|
||||
} else {
|
||||
env->dataBufWorkLen = 0;
|
||||
return TP_ERROR_FS_ERROR_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
// First Frame FF – Первый фрейм из серии фреймов
|
||||
if ((canFrame.data[0] >> 4) == TP_TYPE_FRAME_FF) {
|
||||
if (env->dataReceivedConsecutiveFrameLen) {
|
||||
return TP_ERROR_FF_ERROR;
|
||||
}
|
||||
|
||||
eTpFrameFF *frame = (eTpFrameFF *) canFrame.data;
|
||||
|
||||
if (env->dataBufWorkLen + (frame->dlL | (frame->dlM << 8)) > env->dataBufMaxSize) {
|
||||
return TP_ERROR_FF_ERROR_SIZE;
|
||||
}
|
||||
|
||||
uint16_t dll = frame->dlL | (frame->dlM << 8);
|
||||
if (dll > 100) {
|
||||
asm("nop");
|
||||
}
|
||||
|
||||
env->timeoutFF = SystemGetMs() + WAIT_FF_FRAME_TIMEOUT;
|
||||
|
||||
env->sn = 1;
|
||||
env->dataBufWorkLen = 0;
|
||||
env->dataReceivedConsecutiveFrameLen = (frame->dlL | (frame->dlM << 8));
|
||||
|
||||
for (uint8_t j = 2; j < 8; ++j) {
|
||||
//env->dataBuf[env->dataBufWorkLen] = canFrame.data[j];
|
||||
env->dataBuf->data[env->dataBufWorkLen] = canFrame.data[j];
|
||||
|
||||
++env->dataBufWorkLen;
|
||||
if (env->dataBufWorkLen > env->dataBufMaxSize) {
|
||||
env->timeoutFF = 0;
|
||||
env->dataReceivedConsecutiveFrameLen = 0;
|
||||
env->dataBufWorkLen = 0;
|
||||
return TP_ERROR_CF_ERROR_SIZE;
|
||||
}
|
||||
|
||||
--env->dataReceivedConsecutiveFrameLen;
|
||||
}
|
||||
|
||||
sendFlowFrame(env, reqId, WAIT_FRAME_WRITE);
|
||||
}
|
||||
|
||||
// Consecutive Frame CF – последующий фрейм.
|
||||
if ((canFrame.data[0] >> 4) == TP_TYPE_FRAME_CF) {
|
||||
|
||||
if (env->dataReceivedConsecutiveFrameLen == 0) {
|
||||
return TP_ERROR_CF_ERROR;
|
||||
}
|
||||
|
||||
eTpFrameCF *frame = (eTpFrameCF *) canFrame.data;
|
||||
|
||||
if (frame->sn != env->sn) {
|
||||
env->timeoutFF = 0;
|
||||
env->dataReceivedConsecutiveFrameLen = 0;
|
||||
env->dataBufWorkLen = 0;
|
||||
return TP_ERROR_CF_ERROR_SN;
|
||||
}
|
||||
|
||||
++env->sn;
|
||||
if (env->sn > 15)
|
||||
env->sn = 0;
|
||||
|
||||
for (uint8_t j = 1; j < 8; ++j) {
|
||||
//env->dataBuf[env->dataBufWorkLen] = canFrame.data[j];
|
||||
env->dataBuf->data[env->dataBufWorkLen] = canFrame.data[j];
|
||||
|
||||
++env->dataBufWorkLen;
|
||||
if (env->dataBufWorkLen > env->dataBufMaxSize) {
|
||||
env->timeoutFF = 0;
|
||||
env->dataReceivedConsecutiveFrameLen = 0;
|
||||
env->dataBufWorkLen = 0;
|
||||
return TP_ERROR_CF_ERROR_SIZE;
|
||||
}
|
||||
|
||||
--env->dataReceivedConsecutiveFrameLen;
|
||||
if (env->dataReceivedConsecutiveFrameLen == 0) {
|
||||
env->timeoutFF = 0;
|
||||
env->dataBufLen = env->dataBufWorkLen;
|
||||
|
||||
env->dataBuf->len = env->dataBufLen;
|
||||
env->dataBuf->adrCan = canFrame.standard_id;
|
||||
|
||||
env->dataBufWorkLen = 0;
|
||||
return TP_RECEIVED_DATA;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return TP_ERROR_FC_TIMEOUT;
|
||||
}
|
||||
|
||||
|
||||
bool waitFlowControl(tCanSerialPortFrameTp *env) {
|
||||
|
||||
env->isFlowControl = true;
|
||||
|
||||
eTpResult result = vCanSerialPortFrameTpReceive(env, WAIT_FC_FRAME_TIMEOUT);
|
||||
|
||||
if (result == TP_RECEIVED_FC_DATA) {
|
||||
if (env->isFlowControl) {
|
||||
env->isFlowControl = false;
|
||||
// LoggerStrInfoStatic(LOGGER, LOG_SIGN, "Flow control frame accepted");
|
||||
} else {
|
||||
LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: An unexpected Flow Control Frame was received");
|
||||
}
|
||||
}
|
||||
|
||||
if (env->isFlowControl) {
|
||||
LoggerStrInfoStatic(LOGGER, LOG_SIGN, "Flow control frame timeout");
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool sendFirstFrame(tCanSerialPortFrameTp *env, uint8_t *data, uint16_t size, uint32_t id, uint32_t timeout) {
|
||||
uint8_t dataTpFrame[8];
|
||||
uint16_t pDataLen = 0;
|
||||
|
||||
memset(dataTpFrame, TP_FRAME_PADDING, sizeof(dataTpFrame));
|
||||
|
||||
eTpFrameFF *frame = (eTpFrameFF *) dataTpFrame;
|
||||
frame->typeFrame = TP_TYPE_FRAME_FF;
|
||||
frame->dlL = size;
|
||||
frame->dlM = (size >> 8);
|
||||
|
||||
memcpy(&frame->data[0], &data[pDataLen], 6);
|
||||
pDataLen += 6;
|
||||
|
||||
// SystemDelayMs(timeout_Br); // ??
|
||||
env->ioCanFrame->transmit(env->ioCanFrame->env, (uint8_t *) frame, 8, id,
|
||||
PROTOCOL_CAN_TYPE_UDS, timeout);
|
||||
|
||||
bool result = waitFlowControl(env);
|
||||
if (!result)
|
||||
return false;
|
||||
|
||||
uint16_t countPacketFull = (size - 6) / 7;
|
||||
uint16_t sizePacketTail = (size - 6) % 7;
|
||||
|
||||
uint8_t sn = 1;
|
||||
|
||||
for (uint16_t i = 0; i < countPacketFull; ++i) {
|
||||
|
||||
sendConsecutiveFrame(env, &data[pDataLen], 7, id, sn, timeout);
|
||||
pDataLen += 7;
|
||||
|
||||
++sn;
|
||||
if (sn > 15) {
|
||||
sn = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (sizePacketTail) {
|
||||
sendConsecutiveFrame(env, &data[pDataLen], sizePacketTail, id, sn, timeout);
|
||||
pDataLen += sizePacketTail;
|
||||
}
|
||||
|
||||
return true;
|
||||
|
||||
}
|
||||
|
||||
bool
|
||||
CanSerialPortFrameTpTransmit(tCanSerialPortFrameTp *env, uint8_t *data, uint16_t size, uint32_t id, uint32_t timeout) {
|
||||
bool result;
|
||||
|
||||
// Single Frame SF
|
||||
if (size <= 7) {
|
||||
result = sendSingleFrame(env, data, size, id, timeout);
|
||||
} else {
|
||||
result = sendFirstFrame(env, data, size, id, timeout);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
_Noreturn void CanTpProcessing_ListenerTask(tCanSerialPortFrameTp *env) {
|
||||
while (1) {
|
||||
eTpResult result = vCanSerialPortFrameTpReceive(env, 1000);
|
||||
|
||||
if (result == TP_RECEIVED_FC_DATA) {
|
||||
LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: An unexpected Flow Control Frame was received (listener)");
|
||||
}
|
||||
|
||||
if (result == TP_RECEIVED_DATA) {
|
||||
|
||||
#if (LOG_UDS_TP == 1)
|
||||
sendLogCanTpHex(env, env->dataBuf->data, env->dataBuf->len);
|
||||
LoggerFormatInfo(LOGGER, LOG_SIGN, "Data received: %s", env->hexString)
|
||||
#endif
|
||||
env->receivedTP_func(env->callback_argTp, env->dataBuf);
|
||||
|
||||
}
|
||||
|
||||
if (result == TP_ERROR_FS_ERROR_SIZE) {
|
||||
LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: Receive buffer overflow (1)");
|
||||
}
|
||||
|
||||
if (result == TP_ERROR_FC_ERROR) {
|
||||
LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: An error status was set in the Flow Control Frame");
|
||||
}
|
||||
|
||||
if (result == TP_ERROR_FF_ERROR) {
|
||||
LoggerErrorStatic(LOGGER, LOG_SIGN,
|
||||
"Error: First Frame FF received, but Consecutive Frame reception is not yet complete");
|
||||
}
|
||||
|
||||
|
||||
if (result == TP_ERROR_FF_ERROR_SIZE) {
|
||||
LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: Receive buffer overflow (2)");
|
||||
}
|
||||
|
||||
if (result == TP_ERROR_CF_ERROR) {
|
||||
LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: Unexpected Consecutive Frame received");
|
||||
}
|
||||
|
||||
if (result == TP_ERROR_CF_ERROR_SIZE) {
|
||||
LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: Receive buffer overflow (3)");
|
||||
}
|
||||
|
||||
if (result == TP_ERROR_CF_ERROR_SN) {
|
||||
LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: SN counter mismatch in Consecutive Frame");
|
||||
}
|
||||
|
||||
if (result == TP_ERROR_FF_ERROR_TIMEOUT) {
|
||||
LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: The Consecutive Frame timed out");
|
||||
}
|
||||
|
||||
if (result == TP_ERROR_SF_ERROR) {
|
||||
// LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: Single Frame SF received, but Consecutive Frame reception is not yet complete");
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void CanSerialPortFrameTp_Start(tCanSerialPortFrameTp *env) {
|
||||
// ThreadBlock_Start(env->T_can_Listener, env, CanTpProcessing_ListenerTask);
|
||||
|
||||
if (!env->threadCanListener.id) {
|
||||
env->threadCanListener.id = osThreadNew((osThreadFunc_t) (CanTpProcessing_ListenerTask), (void *) (env), &env->threadCanListener.attr);
|
||||
SystemDelayMs(10);
|
||||
}
|
||||
}
|
||||
|
||||
void CanSerialPortFrameTpInit(
|
||||
tCanSerialPortFrameTp *env,
|
||||
|
||||
tReceivedCan_func receivedCan_func,
|
||||
void *callback_argCan,
|
||||
|
||||
tReceivedTP_func receivedTP_func,
|
||||
void *callback_arg,
|
||||
|
||||
tSerialPortFrameIO *ioCanFrame,
|
||||
tCanTP_data *dataBuf,
|
||||
uint16_t dataBufMaxSize,
|
||||
tLoggerInterface *logger,
|
||||
|
||||
uint8_t filterIdCount,
|
||||
uint32_t *filterReqId,
|
||||
uint32_t *filterRespId,
|
||||
uint8_t *filterDirReq
|
||||
|
||||
) {
|
||||
env->ioCanFrame = ioCanFrame;
|
||||
|
||||
env->dataBuf = dataBuf;
|
||||
env->dataBufMaxSize = dataBufMaxSize;
|
||||
env->dataBufLen = 0;
|
||||
env->dataBufWorkLen = 0;
|
||||
env->isFlowControl = false;
|
||||
|
||||
env->filterIdCount = filterIdCount;
|
||||
env->filterReqId = filterReqId;
|
||||
env->filterRespId = filterRespId;
|
||||
env->filterDirReq = filterDirReq;
|
||||
|
||||
env->dataReceivedConsecutiveFrameLen = 0;
|
||||
|
||||
|
||||
env->ReceivedCan_func = receivedCan_func;
|
||||
env->callback_argCan = callback_argCan;
|
||||
|
||||
|
||||
env->receivedTP_func = receivedTP_func;
|
||||
env->callback_argTp = callback_arg;
|
||||
|
||||
env->timeoutFF = 0;
|
||||
|
||||
env->logger = logger;
|
||||
|
||||
// InitThreadBlock(env->T_can_Listener, "CanTpUds", osPriorityNormal);
|
||||
InitThreadAtrStatic(&env->threadCanListener.attr, "CanTpUds", env->threadCanListener.controlBlock, env->threadCanListener.stack,
|
||||
osPriorityNormal);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
{
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
],
|
||||
"srcs": [
|
||||
"Src/**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,693 @@
|
|||
//
|
||||
// Created by cfif on 16.03.2024.
|
||||
//
|
||||
|
||||
#ifndef CAN_MODULE_CAN_FRAME_XCP_H
|
||||
#define CAN_MODULE_CAN_FRAME_XCP_H20
|
||||
|
||||
#include "SerialPortFrameIO.h"
|
||||
#include "CanSerialPortFrame.h"
|
||||
#include "LoggerToSerialPort.h"
|
||||
#include "CmsisRtosThreadUtils.h"
|
||||
#include "SystemMutexCmsis.h"
|
||||
#include "VarsTabDumpObserver.h"
|
||||
|
||||
|
||||
typedef enum {
|
||||
XCP_ERR_CMD_SYNCH = 0x00,
|
||||
XCP_ERR_CMD_BUSY = 0x10,
|
||||
XCP_ERR_DAQ_ACTIVE = 0x11,
|
||||
XCP_ERR_PGM_ACTIVE = 0x12,
|
||||
XCP_ERR_CMD_UNKNOWN = 0x20,
|
||||
XCP_ERR_CMD_SYNTAX = 0x21,
|
||||
XCP_ERR_OUT_OF_RANGE = 0x22,
|
||||
XCP_ERR_WRITE_PROTECTED = 0x23,
|
||||
XCP_ERR_ACCESS_DENIED = 0x24,
|
||||
XCP_ERR_ACCESS_LOCKED = 0x25,
|
||||
XCP_ERR_PAGE_NOT_VALID = 0x26,
|
||||
XCP_ERR_MODE_NOT_VALID = 0x27,
|
||||
XCP_ERR_SEGMENT_NOT_VALID = 0x28,
|
||||
XCP_ERR_SEQUENCE = 0x29,
|
||||
XCP_ERR_DAQ_CONFIG = 0x2A,
|
||||
XCP_ERR_MEMORY_OVERFLOW = 0x30,
|
||||
XCP_ERR_GENERIC = 0x31,
|
||||
XCP_ERR_VERIFY = 0x32,
|
||||
XCP_ERR_RESOURCE_TEMPORARY_NOT_ACCESSIBLE = 0x33,
|
||||
XCP_ERR_SUBCMD_UNKNOWN = 0x34
|
||||
} eXcpError;
|
||||
|
||||
typedef enum {
|
||||
XCP_COMMAND_CONNECT = 0xFF,
|
||||
XCP_COMMAND_DISCONNECT = 0xFE,
|
||||
XCP_COMMAND_GET_STATUS = 0xFD,
|
||||
XCP_COMMAND_SYNCH = 0xFC,
|
||||
XCP_GET_COMM_MODE_INFO = 0xFB,
|
||||
|
||||
XCP_GET_SEED = 0xF8,
|
||||
XCP_UNLOCK = 0xF7,
|
||||
|
||||
XCP_COMMAND_SET_MTA = 0xF6,
|
||||
|
||||
XCP_COMMAND_UPLOAD = 0xF5,
|
||||
XCP_COMMAND_SHORT_UPLOAD = 0xF4,
|
||||
|
||||
XCP_COMMAND_DOWNLOAD = 0xF0,
|
||||
XCP_COMMAND_DOWNLOAD_NEXT = 0xEF,
|
||||
XCP_COMMAND_DOWNLOAD_MAX = 0xEE,
|
||||
|
||||
XCP_CLEAR_DAQ_LIST = 0xE3,
|
||||
XCP_GET_DAQ_LIST_INFO = 0xD8,
|
||||
|
||||
XCP_FREE_DAQ = 0xD6,
|
||||
XCP_ALLOC_DAQ = 0xD5,
|
||||
XCP_ALLOC_ODT = 0xD4,
|
||||
XCP_ALLOC_ODT_ENTRY = 0xD3,
|
||||
|
||||
XCP_SET_DAQ_PTR = 0xE2,
|
||||
XCP_WRITE_DAQ = 0xE1,
|
||||
XCP_SET_DAQ_LIST_MODE = 0xE0,
|
||||
XCP_START_STOP_DAQ_LIST = 0xDE,
|
||||
XCP_START_STOP_SYNCH = 0xDD,
|
||||
|
||||
} eXcpTypeCommand;
|
||||
|
||||
typedef enum {
|
||||
XCP_PROTECT_CAL_PAG = 0x01,
|
||||
XCP_PROTECT_DAQ = 0x04,
|
||||
XCP_PROTECT_STM = 0x08,
|
||||
XCP_PROTECT_PGM = 0x10
|
||||
} eTypeProtect;
|
||||
|
||||
typedef enum {
|
||||
XCP_STOP = 0,
|
||||
XCP_START = 1,
|
||||
XCP_SELECT = 2
|
||||
|
||||
} eXcpDAQ_Mode;
|
||||
|
||||
typedef enum {
|
||||
XCP_SYNC_STOP_ALL = 0,
|
||||
XCP_SYNC_START_SEL = 1,
|
||||
XCP_SYNC_STOP_SEL = 2
|
||||
|
||||
} eXcpDAQ_Sync_Mode;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
|
||||
uint8_t CAL_PAG: 1; // CALibration and PAGing
|
||||
uint8_t reserve1: 1;
|
||||
uint8_t DAQ: 1; // DAQ lists supported
|
||||
uint8_t STIM: 1; // STIMulation
|
||||
uint8_t PGM: 1; // Flash programming
|
||||
uint8_t reserve2: 1;
|
||||
uint8_t reserve3: 1;
|
||||
uint8_t reserve4: 1;
|
||||
|
||||
uint8_t BYTE__ORDER: 1; // 0 - Intel
|
||||
uint8_t ADDRESS_GRANULARITY_0: 1;
|
||||
uint8_t ADDRESS_GRANULARITY_1: 1;
|
||||
uint8_t reserve5: 1;
|
||||
uint8_t reserve6: 1;
|
||||
uint8_t reserve7: 1;
|
||||
uint8_t _SLAVE_BLOCK_MODE: 1;
|
||||
uint8_t OPTIONAL: 1;
|
||||
|
||||
uint8_t MAX_CTO_;
|
||||
uint16_t MAX_DTO_;
|
||||
|
||||
uint8_t XCP_PROTOCOL_VER;
|
||||
uint8_t XCP_TRANSPORT_VER;
|
||||
|
||||
} eXcpCommand_CONNECT;
|
||||
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
|
||||
uint8_t STORE_CAL_REQ: 1;
|
||||
uint8_t reserve1: 1;
|
||||
uint8_t STORE_DAQ_REQ: 1;
|
||||
uint8_t CLEAR_DAQ_REQ: 1;
|
||||
uint8_t reserve2: 1;
|
||||
uint8_t reserve3: 1;
|
||||
uint8_t DAQ_RUNNING: 1;
|
||||
uint8_t RESUME: 1;
|
||||
|
||||
uint8_t CAL_PAG: 1;
|
||||
uint8_t reserve5: 1;
|
||||
uint8_t DAQ: 1;
|
||||
uint8_t STIM: 1;
|
||||
uint8_t PGM: 1;
|
||||
uint8_t reserve6: 1;
|
||||
uint8_t reserve7: 1;
|
||||
uint8_t reserve8: 1;
|
||||
|
||||
uint8_t STATE_NUMBER;
|
||||
|
||||
uint16_t SESSION_CONFIGURATION_ID;
|
||||
|
||||
|
||||
} eXcpCommand_GET_STATUS;
|
||||
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
|
||||
uint8_t RESERVED1;
|
||||
|
||||
uint8_t _MASTER_BLOCK_MODE: 1;
|
||||
uint8_t INTERLEAVED_MODE: 1;
|
||||
uint8_t RESERVED2: 6;
|
||||
|
||||
uint8_t RESERVED3;
|
||||
uint8_t MAX_BS;
|
||||
uint8_t MIN_ST;
|
||||
uint8_t QUEUE_SIZE;
|
||||
uint8_t VERSION;
|
||||
} eXcpCommand_GET_COMM_MODE_INFO;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t COUNT;
|
||||
} eXcpCommand_Upload;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t COUNT;
|
||||
uint8_t RESERVED;
|
||||
uint8_t ADR_EX;
|
||||
uint32_t ADR;
|
||||
} eXcpCommand_SHORT_UPLOAD;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t MODE;
|
||||
uint8_t RESOURCE;
|
||||
} eXcpCommand_REQ_GET_SEED;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t LEN;
|
||||
uint32_t KEY;
|
||||
} eXcpCommand_GET_SEED;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t LEN;
|
||||
uint32_t KEY;
|
||||
} eXcpCommand_REQ_UNLOCK;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint16_t RESERVED;
|
||||
uint8_t ADR_EX;
|
||||
uint32_t ADR;
|
||||
} eXcpCommand_SET_MTA;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t COUNT;
|
||||
} eXcpCommand_Download;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint16_t DAQ_LIST_NUMBER;
|
||||
} eXcpCommand_Get_DAQ_List_Info_Request;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t RESERVED;
|
||||
uint16_t DAQ_LIST_NUMBER;
|
||||
uint8_t ODT_NUMBER;
|
||||
uint8_t ODT_ENTRY_NUMBER;
|
||||
} eXcpCommand_SET_DAQ_PTR;
|
||||
|
||||
#define LOG_XCP 0
|
||||
|
||||
#define PROTECT_CAL_PAG 0
|
||||
#define PROTECT_DAQ 0
|
||||
#define PROTECT_STIM 0
|
||||
#define PROTECT_PGM 0
|
||||
|
||||
#define SECT_SRAM_XCP __attribute__((section (".xcpdata")))
|
||||
|
||||
#define MASTER_BLOCK_MODE 0
|
||||
#define SLAVE_BLOCK_MODE 0
|
||||
|
||||
#define PROGRAM_MASTER_BLOCK_MODE 1
|
||||
#define PROGRAM_MAX_SECTOR 8
|
||||
#define PROGRAM_MAX_BUF 256
|
||||
|
||||
#define MAX_CTO 8
|
||||
#define MAX_DTO 8
|
||||
|
||||
#define BODY_MAX_LEN (MAX_DTO - 2)
|
||||
|
||||
#define MAX_DAO 10
|
||||
#define MAX_ODT 255
|
||||
#define MAX_ODT_ENTRIES_SIZE_DAQ 1
|
||||
#define MAX_EVENT_CHANNEL 4
|
||||
|
||||
typedef struct {
|
||||
uint8_t DATA[BODY_MAX_LEN];
|
||||
} tXCP_DATA_STIM;
|
||||
|
||||
typedef struct {
|
||||
uint8_t ODT_ENTRIES_COUNT;
|
||||
|
||||
uint8_t DATA_STM_COUNTER;
|
||||
tXCP_DATA_STIM DATA_STM[MAX_ODT_ENTRIES_SIZE_DAQ];
|
||||
|
||||
uint8_t BIT_OFFSET[MAX_ODT_ENTRIES_SIZE_DAQ];
|
||||
uint8_t ADR_EXT[MAX_ODT_ENTRIES_SIZE_DAQ];
|
||||
uint8_t ODT_ENTRIES_SIZE[MAX_ODT_ENTRIES_SIZE_DAQ];
|
||||
uint32_t ODT_ENTRIES_ADR[MAX_ODT_ENTRIES_SIZE_DAQ];
|
||||
} tXCP_ODT_ENTRIES;
|
||||
|
||||
//typedef struct {
|
||||
// uint8_t ALTERNATING;
|
||||
// uint8_t DIRECTION;
|
||||
// uint8_t DTO_CTR;
|
||||
// uint8_t TIMESTAMP;
|
||||
// uint8_t PID_OFF;
|
||||
// uint8_t TRANSMISSION_RATE_PRESCALER;
|
||||
// uint8_t DAQ_LIST_PRIORITY;
|
||||
|
||||
// uint8_t COUNTER;
|
||||
|
||||
//} tXCP_EVENT_CHANNEL;
|
||||
|
||||
typedef struct {
|
||||
uint8_t SELECTED;
|
||||
uint8_t RUNNING;
|
||||
uint8_t ODT_COUNT;
|
||||
uint16_t EVENT_CHANNEL;
|
||||
|
||||
uint8_t ALTERNATING;
|
||||
uint8_t DIRECTION;
|
||||
uint8_t DTO_CTR;
|
||||
uint8_t TIMESTAMP;
|
||||
uint8_t PID_OFF;
|
||||
uint8_t TRANSMISSION_RATE_PRESCALER;
|
||||
uint8_t DAQ_LIST_PRIORITY;
|
||||
|
||||
uint8_t PRESCALER_COUNTER;
|
||||
|
||||
uint8_t IS_STIM_RECEIVED;
|
||||
tXCP_ODT_ENTRIES ODT_NUMBER[MAX_ODT];
|
||||
} tXCP_DAQ;
|
||||
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
|
||||
uint8_t PREDEFINED: 1;
|
||||
uint8_t EVENT_FIXED: 1;
|
||||
uint8_t DAQ: 1;
|
||||
uint8_t STIM: 1;
|
||||
uint8_t RESERVER: 4;
|
||||
|
||||
uint8_t MAX_ODT_;
|
||||
uint8_t MAX_ODT_ENTRIES_;
|
||||
uint16_t FIXED_EVENT;
|
||||
|
||||
} eXcpCommand_Get_DAQ_List_Info;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t RESERVED;
|
||||
uint16_t DAQ_LIST_NUMBER;
|
||||
uint8_t ODT_NUMBER;
|
||||
uint8_t ODT_ENTRIES_COUNT;
|
||||
} eXcpCommand_DAQ_Alloc_ODR_Entry;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t BIT_OFFSET;
|
||||
uint8_t ODT_ENTRY_SIZE;
|
||||
uint8_t ADR_EXT;
|
||||
uint32_t ADR;
|
||||
} eXcpCommand_WRITE_DAQ;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
|
||||
uint8_t ALTERNATING: 1;
|
||||
uint8_t DIRECTION: 1;
|
||||
uint8_t RESERVED1: 1;
|
||||
uint8_t DTO_CTR: 1;
|
||||
uint8_t TIMESTAMP: 1;
|
||||
uint8_t PID_OFF: 1;
|
||||
uint8_t RESERVED2: 1;
|
||||
uint8_t RESERVED3: 1;
|
||||
|
||||
uint16_t DAQ_LIST_NUMBER;
|
||||
uint16_t EVENT_CHANNEL_NUMBER;
|
||||
uint8_t TRANSMISSION_RATE_PRESCALER;
|
||||
uint8_t DAQ_LIST_PRIORITY;
|
||||
} eXcpCommand_SET_DAQ_LIST_MODE;
|
||||
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
eXcpDAQ_Mode MODE;
|
||||
uint16_t DAQ_LIST_NUMBER;
|
||||
} eXcpCommand_START_STOP_DAQ_LIST;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
eXcpDAQ_Sync_Mode MODE;
|
||||
} eXcpCommand_START_STOP_SYNCH;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t RESERVED;
|
||||
uint16_t DAQ_COUNT;
|
||||
} eXcpCommand_ALLOC_DAQ;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t RESERVED;
|
||||
uint16_t DAQ_LIST_NUMBER;
|
||||
uint8_t ODT_COUNT;
|
||||
} eXcpCommand_ALLOC_ODT;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t RESERVED;
|
||||
uint16_t DAQ_LIST_NUMBER;
|
||||
uint8_t ODT_NUMBER;
|
||||
uint8_t ODT_ENTRIES_COUNT;
|
||||
} eXcpCommand_ALLOC_ODT_ENTRY;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
|
||||
uint8_t DAQ_CONFIG_TYPE: 1;
|
||||
uint8_t PRESCALER_SUPPORTED: 1;
|
||||
uint8_t RESUME_SUPPORTED: 1;
|
||||
uint8_t BIT_STIM_SUPPORTED: 1;
|
||||
uint8_t TIMESTAMP_SUPPORTED: 1;
|
||||
uint8_t PID_OFF_SUPPORTED: 1;
|
||||
uint8_t OVERLOAD_MSB: 1;
|
||||
uint8_t OVERLOAD_EVENT: 1;
|
||||
|
||||
uint16_t MAX_DAQ;
|
||||
uint16_t MAX_EVENT_CHANNEL_;
|
||||
uint8_t MIN_DAQ;
|
||||
|
||||
uint8_t Optimisation_Type_0: 1;
|
||||
uint8_t Optimisation_Type_1: 1;
|
||||
uint8_t Optimisation_Type_2: 1;
|
||||
uint8_t Optimisation_Type_3: 1;
|
||||
uint8_t Address_Extension_ODT: 1;
|
||||
uint8_t Address_Extension_DAQ: 1;
|
||||
uint8_t Identification_Field_Type_0: 1;
|
||||
uint8_t Identification_Field_Type_1: 1;
|
||||
|
||||
} eXcpCommand_GET_DAQ_PROCESSOR_INFO;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t GRANULARITY_ODT_ENTRY_SIZE_DAQ;
|
||||
uint8_t MAX_ODT_ENTRY_SIZE_DAQ;
|
||||
uint8_t GRANULARITY_ODT_ENTRY_SIZE_STIM;
|
||||
uint8_t MAX_ODT_ENTRY_SIZE_STIM;
|
||||
uint8_t TIMESTAMP_MODE;
|
||||
uint16_t TIMESTAMP_TICKS;
|
||||
} eXcpCommand_GET_DAQ_RESOLUTION_INFO;
|
||||
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t RESERVED;
|
||||
uint16_t DAQ_LIST_NUMBER;
|
||||
} eXcpCommand_GET_DAQ_LIST_MODE_GET;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
|
||||
uint8_t SELECTED: 1;
|
||||
uint8_t DIRECTION: 1;
|
||||
uint8_t RESERVED1: 1;
|
||||
uint8_t DTO_CTR: 1;
|
||||
uint8_t TIMESTAMP: 1;
|
||||
uint8_t PID_OFF: 1;
|
||||
uint8_t RUNNING: 1;
|
||||
uint8_t RESUME: 1;
|
||||
|
||||
uint16_t RESERVED2;
|
||||
uint16_t CURRENT_EVENT_CHANNEL_NUMBER;
|
||||
uint8_t CURRENT_PRESCALER;
|
||||
uint8_t CURRENT_DAQ_LIST_PRIORITY;
|
||||
|
||||
} eXcpCommand_GET_DAQ_LIST_MODE;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t RESERVED;
|
||||
uint16_t EVENT_CHANNEL_NUMBER;
|
||||
} eXcpCommand_GET_DAQ_EVENT_INFO_GET;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
uint8_t ODT;
|
||||
uint8_t DAQ;
|
||||
} eXcpCommand_GET_DAQ_STM;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
|
||||
uint8_t RESERVED1: 1;
|
||||
uint8_t RESERVED2: 1;
|
||||
uint8_t DAQ: 1;
|
||||
uint8_t STM: 1;
|
||||
uint8_t RESERVED3: 1;
|
||||
uint8_t RESERVED4: 1;
|
||||
uint8_t CONSISTENCY_DAQ: 1;
|
||||
uint8_t CONSISTENCY_EVENT: 1;
|
||||
|
||||
uint8_t MAX_DAQ_LIST;
|
||||
uint8_t EVENT_CHANNEL_NAME_LENGTH;
|
||||
uint8_t EVENT_CHANNEL_TIME_CYCLE;
|
||||
uint8_t EVENT_CHANNEL_TIME_UNIT;
|
||||
uint8_t EVENT_CHANNEL_PRIORITY;
|
||||
|
||||
} eXcpCommand_GET_DAQ_EVENT_INFO;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t RESERVED1;
|
||||
|
||||
uint8_t _MASTER_BLOCK_MODE: 1;
|
||||
uint8_t INTERLEAVED_MODE: 1;
|
||||
uint8_t RESERVED2: 1;
|
||||
uint8_t RESERVED3: 1;
|
||||
uint8_t RESERVED4: 1;
|
||||
uint8_t RESERVED5: 1;
|
||||
uint8_t _SLAVE_BLOCK_MODE: 1;
|
||||
uint8_t RESERVED6: 1;
|
||||
|
||||
uint8_t MAX_CTO_PGM;
|
||||
uint8_t MAX_BS_PGM;
|
||||
uint8_t MIN_ST_PGM;
|
||||
uint8_t QUEUE_SIZE_PGM;
|
||||
} eXcpCommand_PROGRAM_START;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t MODE;
|
||||
uint16_t RESERVED;
|
||||
uint32_t CLEAR_RANGE;
|
||||
} eXcpCommand_XCP_PROGRAM_CLEAR_D1;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t COUNT;
|
||||
} eXcpCommand_Program_ProgramNext_D0_CA;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t RESERVED;
|
||||
uint16_t CODESIZE;
|
||||
} eXcpCommand_Program_Prepare_CC;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t COMPRESSION_METHOD;
|
||||
uint8_t ENCRYPTION_METHOD;
|
||||
uint8_t PROGRAM_METHOD;
|
||||
uint8_t ACCESS_METHOD;
|
||||
} eXcpCommand_Program_Format_CB;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
|
||||
uint8_t ABSOLUTE_MODE: 1;
|
||||
uint8_t FUNCTIONAL_MODE: 1;
|
||||
uint8_t COMPRESSION_SUPPORTED: 1;
|
||||
uint8_t COMPRESSION_REQUIRED: 1;
|
||||
uint8_t ENCRYPTION_SUPPORTED: 1;
|
||||
uint8_t ENCRYPTION_REQUIRED: 1;
|
||||
uint8_t NON_SEQ_PGM_SUPPORTED: 1;
|
||||
uint8_t NON_SEQ_PGM_REQUIRED: 1;
|
||||
|
||||
uint8_t MAX_SECTOR;
|
||||
|
||||
} eXcpCommand_PGM_PROCESSOR_INFO_CE;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t MODE;
|
||||
uint8_t SECTOR_NUMBER;
|
||||
} eXcpCommand_REQ_GET_SECTOR_INFO_CD;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t CLEAR_SEQUENCE_NUMBER;
|
||||
uint8_t PROGRAM_SEQUENCE_NUMBER;
|
||||
|
||||
uint8_t ABSOLUTE_MODE: 1;
|
||||
uint8_t FUNCTIONAL_MODE: 1;
|
||||
uint8_t PAGED_MODE: 1;
|
||||
uint8_t SEQUENTIAL_ONLY: 1;
|
||||
uint8_t ERASE_BEFORE_WRITE: 1;
|
||||
uint8_t VERIFY_AFTER_WRITE: 1;
|
||||
uint8_t RESERVED1: 1;
|
||||
uint8_t RESERVED2: 1;
|
||||
|
||||
uint32_t SECTOR_INFO;
|
||||
} eXcpCommand_RESP_GET_SECTOR_INFO_CD;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
|
||||
uint8_t ECU: 1;
|
||||
uint8_t XCP: 1;
|
||||
uint8_t RESERVED1: 1;
|
||||
uint8_t RESERVED2: 1;
|
||||
uint8_t RESERVED3: 1;
|
||||
uint8_t RESERVED4: 1;
|
||||
uint8_t RESERVED5: 1;
|
||||
uint8_t ALL: 1;
|
||||
|
||||
uint8_t SEGMENT;
|
||||
uint8_t PAGE;
|
||||
|
||||
} eXcpCommand_SET_CALIBRATION_PAGE_EB;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t VERIFICATION_MODE;
|
||||
uint16_t VERIFICATION_TYPE;
|
||||
uint32_t VERIFICATION_VALUE;
|
||||
} eXcpCommand_Program_Verify_C8;
|
||||
|
||||
typedef struct __attribute__ ((packed)) {
|
||||
eXcpTypeCommand COM;
|
||||
uint8_t ACCESS_MODE;
|
||||
uint8_t LOGICAL_DATA_SEGMENT_NUMBER;
|
||||
} eXcpCommand_XCP_GET_CAL_PAGE_EA;
|
||||
|
||||
|
||||
typedef bool (xcp_clear_flash_func)(uint32_t firstPageAddr, uint32_t totalSize, void *wdTriggerFct,
|
||||
void *wdTriggerFct_env);
|
||||
|
||||
typedef bool (xcp_write_flash_func)(uint32_t beginPageAddr, void *sourceRamAddr, uint32_t size);
|
||||
|
||||
|
||||
typedef struct {
|
||||
tSerialPortFrameIO *ioCanFrame;
|
||||
tLoggerInterface *logger;
|
||||
tVarsTabDumpObserver *varsTabDumpObserver;
|
||||
|
||||
eTypeProtect RESOURCE;
|
||||
uint8_t ADR_EXT;
|
||||
uint32_t ADR_MTA;
|
||||
uint8_t PAGE_ID;
|
||||
|
||||
bool PROTECT[4];
|
||||
|
||||
can_rx_message_type canFrame;
|
||||
uint8_t downloadRemaining;
|
||||
uint8_t response[8];
|
||||
|
||||
uint8_t DATA[MAX_ODT_ENTRIES_SIZE_DAQ * BODY_MAX_LEN];
|
||||
|
||||
//tXCP_DAQ DAQ[MAX_DAO];
|
||||
|
||||
struct {
|
||||
uint8_t STORE_CAL_REQ; // ожидает сохранения в энергонезависимую память
|
||||
uint8_t STORE_DAQ_REQ; // требуется сохранить DAQ-листы
|
||||
uint8_t CLEAR_DAQ_REQ; // требуется очистить все DAQ-листы
|
||||
uint8_t DAQ_RUNNING; // минимум один DAQ-лист запущен и работает
|
||||
uint8_t RESUME; // устройство в режиме RESUME
|
||||
} STATE;
|
||||
|
||||
struct {
|
||||
uint16_t DAQ_LIST_NUMBER;
|
||||
uint8_t ODT_NUMBER;
|
||||
uint8_t ODT_ENTRY_NUMBER;
|
||||
uint16_t DAQ_COUNT;
|
||||
} SETUP;
|
||||
|
||||
tXCP_DAQ *DAQ;
|
||||
|
||||
|
||||
tRtcIO *rtcIO;
|
||||
|
||||
osMutexId_t access;
|
||||
|
||||
uint32_t startRamAdr;
|
||||
uint32_t endRamAdr;
|
||||
|
||||
uint32_t startFlashAdr;
|
||||
uint32_t endFlashAdr;
|
||||
xcp_clear_flash_func *clear_flash_func;
|
||||
|
||||
xcp_write_flash_func *write_flash_func;
|
||||
|
||||
uint8_t bufWriteFlash[PROGRAM_MAX_BUF];
|
||||
uint16_t bufWriteFlashCount;
|
||||
uint32_t bufWriteFlashAdr;
|
||||
|
||||
struct {
|
||||
osThreadId_t id;
|
||||
uint32_t stack[384];
|
||||
StaticTask_t controlBlock;
|
||||
osThreadAttr_t attr;
|
||||
} thread_Listener_XCP;
|
||||
|
||||
// tStaticThreadBlock(384) T_can_Listener_XCP;
|
||||
// tStaticThreadBlock(512) T_can_Listener_Dto_Stim_XCP;
|
||||
// tStaticThreadBlock(512) T_can_Listener_Dto_Daq_10_XCP;
|
||||
// tStaticThreadBlock(512) T_can_Listener_Dto_Daq_100_XCP;
|
||||
// tStaticThreadBlock(512) T_can_Listener_Dto_Daq_1000_XCP;
|
||||
|
||||
} tCanSerialPortFrameXCP;
|
||||
|
||||
|
||||
typedef uint8_t (*xcp_func_ptr)(tCanSerialPortFrameXCP *env);
|
||||
|
||||
typedef struct {
|
||||
xcp_func_ptr func;
|
||||
char *desc;
|
||||
} eXcp_com;
|
||||
|
||||
void CanSerialPortFrameXcpInit(
|
||||
tCanSerialPortFrameXCP *env,
|
||||
tSerialPortFrameIO *ioCanFrame,
|
||||
tRtcIO *rtcIO,
|
||||
uint32_t startRamAddr,
|
||||
uint32_t endRamAdr,
|
||||
uint32_t startFlashAdr,
|
||||
uint32_t endFlashAdr,
|
||||
xcp_clear_flash_func *clear_flash_func,
|
||||
xcp_write_flash_func *write_flash_func,
|
||||
tVarsTabDumpObserver *varsTabDumpObserver,
|
||||
tLoggerInterface *logger
|
||||
);
|
||||
|
||||
void CanXcpProcessing_Listener_Start(tCanSerialPortFrameXCP *env);
|
||||
|
||||
#endif //CAN_MODULE_CAN_FRAME_XCP_H
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,10 @@
|
|||
{
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
],
|
||||
"srcs": [
|
||||
"Src/**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
//
|
||||
// Created by CFIF on 14.11.22.
|
||||
//
|
||||
|
||||
#ifndef UVEOS_ON_NATION_CLICMD_H
|
||||
#define UVEOS_ON_NATION_CLICMD_H
|
||||
|
||||
#include "SerialPort.h"
|
||||
#include "stdbool.h"
|
||||
#include "stddef.h"
|
||||
#include "LoggerToSerialPort.h"
|
||||
|
||||
typedef struct {
|
||||
struct {
|
||||
char *data;
|
||||
size_t limit;
|
||||
char *begin;
|
||||
size_t length;
|
||||
} rxLine;
|
||||
|
||||
tSerialPortIO *serialCommandPortIn;
|
||||
tSerialPortIO *serialCommandPortOut;
|
||||
tLoggerToSerialPort *loggerToSerialPort;
|
||||
|
||||
} tCliCmd;
|
||||
|
||||
void CliCmd_Init(tCliCmd *env, tLoggerToSerialPort *loggerToSerialPort, tSerialPortIO *io_in, tSerialPortIO *io_out,
|
||||
uint8_t *data, size_t dataLen);
|
||||
|
||||
#define CliCmd_InitStatic(ENV, LOGGER, IO_IN, IO_OUT, DATA) CliCmd_Init(ENV, LOGGER, IO_IN,IO_OUT,DATA,sizeof(DATA));
|
||||
|
||||
void CliCmd_WaitLine(tCliCmd *env);
|
||||
|
||||
void CliCmd_Print(tCliCmd *cli, char *text, uint16_t len);
|
||||
|
||||
void CliCmd_PrintHex(tCliCmd *cli, uint8_t *data, uint16_t byteLen);
|
||||
|
||||
char *CliCmd_RxLineBegin(tCliCmd *cli);
|
||||
|
||||
char *CliCmd_RxLineEnd(tCliCmd *cli);
|
||||
|
||||
size_t CliCmd_RxLineLength(tCliCmd *cli);
|
||||
|
||||
char *CliCmd_RxStartsWith(tCliCmd *cli, char *text, uint16_t len);
|
||||
|
||||
void CliCmd_RxSkipSpace(tCliCmd *cli);
|
||||
|
||||
void CliCmd_RxSkipTo(tCliCmd *cli, char *next);
|
||||
|
||||
void CliCmd_WaitLineDelay(tCliCmd *env, uint32_t delay);
|
||||
|
||||
void CliCmd_RxSkip(tCliCmd *cli, size_t len);
|
||||
|
||||
#define CliCmd_PrintStatic(CLI, STR) CliCmd_Print(CLI,STR,sizeof(STR)-1)
|
||||
|
||||
#define CliCmd_PrintLnStatic(CLI, STR) CliCmd_PrintStatic(CLI,(STR "\r\n"))
|
||||
|
||||
#define CliCmd_PrintSpStatic(CLI, STR) CliCmd_PrintStatic(CLI,(STR " "))
|
||||
|
||||
// 1 если STR присутствует первым блоком в cli->data
|
||||
#define CliCmd_RxStartsWithStatic(CLI, STR) CliCmd_RxStartsWith(CLI,(STR),sizeof(STR) - 1)
|
||||
|
||||
#endif //UVEOS_ON_NATION_CLICMD_H
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
//
|
||||
// Created by CFIF on 14.11.22.
|
||||
//
|
||||
#include <string.h>
|
||||
#include "CliCmd.h"
|
||||
#include "AsciiStringParsingUtils.h"
|
||||
#include "AsciiStringAssmeblingUtils.h"
|
||||
#include "SystemDelayInterface.h"
|
||||
#include "LoggerToSerialPort.h"
|
||||
|
||||
void CliCmd_Init(tCliCmd *env, tLoggerToSerialPort *loggerToSerialPort, tSerialPortIO *io_in, tSerialPortIO *io_out,
|
||||
uint8_t *data, size_t dataLen) {
|
||||
env->loggerToSerialPort = loggerToSerialPort;
|
||||
env->serialCommandPortIn = io_in;
|
||||
env->serialCommandPortOut = io_out;
|
||||
env->rxLine.limit = dataLen;
|
||||
env->rxLine.data = (char *) data;
|
||||
vAsciiStringInit(env->rxLine.data, &env->rxLine.length, env->rxLine.limit);
|
||||
env->rxLine.begin = env->rxLine.data;
|
||||
}
|
||||
|
||||
void CliCmd_WaitLine(tCliCmd *env) {
|
||||
//чистим буфер
|
||||
//получаем строку
|
||||
//печатаем ее в ответ
|
||||
|
||||
SerialPortClearRxBuffer(env->serialCommandPortIn);
|
||||
vAsciiStringClean(env->rxLine.data, &env->rxLine.length);
|
||||
|
||||
env->rxLine.length = SerialPortReceiveTo(
|
||||
env->serialCommandPortIn,
|
||||
(uint8_t *) env->rxLine.data,
|
||||
env->rxLine.limit,
|
||||
'\n',
|
||||
SystemWaitForever
|
||||
);
|
||||
|
||||
env->rxLine.begin = env->rxLine.data;
|
||||
if (env->rxLine.length && (*(CliCmd_RxLineEnd(env) - 2) == '\n')) {
|
||||
--env->rxLine.length;
|
||||
}
|
||||
CliCmd_Print(env, CliCmd_RxLineBegin(env), CliCmd_RxLineLength(env));
|
||||
}
|
||||
|
||||
void CliCmd_WaitLineDelay(tCliCmd *env, uint32_t delay) {
|
||||
//чистим буфер
|
||||
//получаем строку
|
||||
//печатаем ее в ответ
|
||||
|
||||
SerialPortClearRxBuffer(env->serialCommandPortIn);
|
||||
vAsciiStringClean(env->rxLine.data, &env->rxLine.length);
|
||||
|
||||
env->rxLine.length = SerialPortReceiveTo(
|
||||
env->serialCommandPortIn,
|
||||
(uint8_t *) env->rxLine.data,
|
||||
env->rxLine.limit,
|
||||
'\n',
|
||||
delay
|
||||
);
|
||||
|
||||
env->rxLine.begin = env->rxLine.data;
|
||||
if (env->rxLine.length && (*(CliCmd_RxLineEnd(env) - 2) == '\n')) {
|
||||
--env->rxLine.length;
|
||||
}
|
||||
CliCmd_Print(env, CliCmd_RxLineBegin(env), CliCmd_RxLineLength(env));
|
||||
}
|
||||
|
||||
void CliCmd_ClearRx(tCliCmd *env) {
|
||||
SerialPortClearRxBuffer(env->serialCommandPortIn);
|
||||
vAsciiStringClean(env->rxLine.data, &env->rxLine.length);
|
||||
}
|
||||
|
||||
bool CliCmd_HasCompleteLine(tCliCmd *env) {
|
||||
|
||||
env->rxLine.length = SerialPortReceiveTo(
|
||||
env->serialCommandPortIn,
|
||||
(uint8_t *) env->rxLine.begin,
|
||||
env->rxLine.limit,
|
||||
'\n',
|
||||
0
|
||||
);
|
||||
|
||||
env->rxLine.begin = env->rxLine.data;
|
||||
if (env->rxLine.length && (*(CliCmd_RxLineEnd(env) - 2) == '\n')) {
|
||||
--env->rxLine.length;
|
||||
}
|
||||
CliCmd_Print(env, CliCmd_RxLineBegin(env), CliCmd_RxLineLength(env));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void CliCmd_Print(tCliCmd *cli, char *text, uint16_t len) {
|
||||
|
||||
// SerialPortTransmit(cli->serialCommandPortOut, (uint8_t *) text, len, SystemWaitForever);
|
||||
LoggerToSerialPort_Cmd(cli->loggerToSerialPort, text, len);
|
||||
|
||||
}
|
||||
|
||||
void CliCmd_PrintHex(tCliCmd *cli, uint8_t *data, uint16_t byteLen) {
|
||||
char hexString[byteLen * 2];
|
||||
size_t len = 0;
|
||||
vAsciiStringAddBytesAsHex(hexString, &len, data, byteLen);
|
||||
CliCmd_Print(cli, hexString, len);
|
||||
}
|
||||
|
||||
char *CliCmd_RxLineBegin(tCliCmd *cli) {
|
||||
return cli->rxLine.begin;
|
||||
}
|
||||
|
||||
char *CliCmd_RxLineEnd(tCliCmd *cli) {
|
||||
return cli->rxLine.data + cli->rxLine.length;
|
||||
}
|
||||
|
||||
size_t CliCmd_RxLineLength(tCliCmd *cli) {
|
||||
return CliCmd_RxLineEnd(cli) - CliCmd_RxLineBegin(cli);
|
||||
}
|
||||
|
||||
char *CliCmd_RxStartsWith(tCliCmd *cli, char *text, uint16_t len) {
|
||||
//смотрим что у нас в начале буфера
|
||||
return strnstr(CliCmd_RxLineBegin(cli), text, len);
|
||||
}
|
||||
|
||||
void CliCmd_RxSkipTo(tCliCmd *cli, char *next) {
|
||||
if ((next < CliCmd_RxLineEnd(cli)) && (next > CliCmd_RxLineBegin(cli))) {
|
||||
cli->rxLine.begin = next;
|
||||
}
|
||||
}
|
||||
|
||||
void CliCmd_RxSkip(tCliCmd *cli, size_t len) {
|
||||
cli->rxLine.begin += len;
|
||||
}
|
||||
|
||||
void CliCmd_RxSkipSpace(tCliCmd *cli) {
|
||||
char *end = CliCmd_RxLineEnd(cli);
|
||||
for (; cli->rxLine.begin < end && *cli->rxLine.begin == ' '; ++cli->rxLine.begin) {}
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
{
|
||||
"dep": [
|
||||
{
|
||||
"type": "local",
|
||||
|
||||
"dir": "./MODULES/SerialPort"
|
||||
},
|
||||
{
|
||||
"type": "local",
|
||||
|
||||
"dir": "./MODULES/AsciiStringParsingUtils"
|
||||
},
|
||||
{
|
||||
"type": "local",
|
||||
|
||||
"dir": "./MODULES/AsciiStringAssemblingUtils"
|
||||
}
|
||||
],
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
],
|
||||
"srcs": [
|
||||
"Src/**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
//
|
||||
// Created by cfif on 15.11.22.
|
||||
//
|
||||
#include "CliRedirectTable.h"
|
||||
|
||||
|
||||
bool CliRedirectionTable_RecAdd(tCliRedirectTable *baseTable, char *cmdStatic, uint8_t cmdLen, cliCall mtd, void *env) {
|
||||
if (baseTable->count >= baseTable->itemsLimit) {
|
||||
return false;
|
||||
}
|
||||
|
||||
baseTable->items[baseTable->count].cmd.data = cmdStatic;
|
||||
baseTable->items[baseTable->count].cmd.length = cmdLen;
|
||||
baseTable->items[baseTable->count].method = mtd;
|
||||
baseTable->items[baseTable->count].env = env;
|
||||
|
||||
++baseTable->count;
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
void CliRedirectionTable_Init(tCliRedirectTable *baseTable, tCliRedirectItem *mem, uint16_t itemsLimit) {
|
||||
baseTable->count = 0;
|
||||
baseTable->itemsLimit = itemsLimit;
|
||||
baseTable->items = mem;
|
||||
}
|
||||
|
||||
int32_t CliRedirectionTable_ProcessCmd(tCliRedirectTable *env, tCliCmd *cmd) {
|
||||
for (uint16_t id = 0; id < env->count; ++id) {
|
||||
tCliRedirectItem *item = env->items + id;
|
||||
char *cmdName = CliCmd_RxStartsWith(cmd, item->cmd.data, item->cmd.length);
|
||||
if (cmdName) {
|
||||
CliCmd_RxSkip(cmd, item->cmd.length);
|
||||
CliCmd_RxSkipSpace(cmd);
|
||||
return item->method(item->env, cmd);
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
int32_t CliRedirectionTable_ListCmd(tCliRedirectTable *env, tCliCmd *cmd, char divider) {
|
||||
for (uint16_t id = 0; id < env->count; ++id) {
|
||||
tCliRedirectItem *item = env->items + id;
|
||||
CliCmd_Print(cmd, item->cmd.data, item->cmd.length);
|
||||
if (divider) {
|
||||
CliCmd_Print(cmd, ÷r, 1);
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
//
|
||||
// Created by cfif on 11.11.22.
|
||||
//
|
||||
|
||||
#ifndef UVEOS_ON_NATION_CLIREDIRECTTABLE_H
|
||||
#define UVEOS_ON_NATION_CLIREDIRECTTABLE_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "CliCmd.h"
|
||||
#include "BaseTypes.h"
|
||||
|
||||
typedef int32_t (*cliCall)(void *env, tCliCmd *cli);
|
||||
|
||||
typedef struct {
|
||||
tStringStatic cmd;
|
||||
cliCall method;
|
||||
void *env;
|
||||
} tCliRedirectItem;
|
||||
|
||||
typedef struct {
|
||||
tCliRedirectItem *items;
|
||||
uint16_t count;
|
||||
uint16_t itemsLimit;
|
||||
} tCliRedirectTable;
|
||||
|
||||
void CliRedirectionTable_Init(tCliRedirectTable *baseTable, tCliRedirectItem *mem, uint16_t itemsLimit);
|
||||
|
||||
#define CliRedirectionTable_InitStatic(TAB, MEM) CliRedirectionTable_Init(TAB,MEM,sizeof(MEM)/sizeof(tCliRedirectItem))
|
||||
|
||||
bool CliRedirectionTable_RecAdd(tCliRedirectTable *baseTable, char *cmdStatic, uint8_t cmdLen, cliCall mtd, void *env);
|
||||
|
||||
#define CliRedirectionTable_RecAddStatic(TAB, CMD, CALL, ENV) CliRedirectionTable_RecAdd(TAB,CMD,sizeof (CMD)-1,CALL,ENV)
|
||||
|
||||
int32_t CliRedirectionTable_ProcessCmd(tCliRedirectTable *env, tCliCmd *cmd);
|
||||
|
||||
int32_t CliRedirectionTable_ListCmd(tCliRedirectTable *env, tCliCmd *cmd, char divider);
|
||||
|
||||
#endif //UVEOS_ON_NATION_CLIREDIRECTTABLE_H
|
||||
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
{
|
||||
"dep": [
|
||||
{
|
||||
"type": "local",
|
||||
|
||||
"dir": "./MODULES/BaseTypes"
|
||||
},
|
||||
{
|
||||
"type": "local",
|
||||
|
||||
"dir": "./MODULES/CliCmd"
|
||||
}
|
||||
],
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"./"
|
||||
],
|
||||
"srcs": [
|
||||
"./**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
#-- System ---------------------------------------------------------------------
|
||||
SET(CMAKE_SYSTEM_NAME Generic)
|
||||
SET(CMAKE_SYSTEM_PROCESSOR arm)
|
||||
|
||||
#-- Toolchain ------------------------------------------------------------------
|
||||
SET(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
|
||||
IF(WIN32)
|
||||
SET(TOOL_EXECUTABLE_SUFFIX ".exe")
|
||||
ELSE()
|
||||
SET(TOOL_EXECUTABLE_SUFFIX "")
|
||||
ENDIF()
|
||||
SET(CMAKE_C_COMPILER "arm-none-eabi-gcc${TOOL_EXECUTABLE_SUFFIX}")
|
||||
SET(CMAKE_CXX_COMPILER "arm-none-eabi-g++${TOOL_EXECUTABLE_SUFFIX}")
|
||||
SET(CMAKE_ASM_COMPILER "arm-none-eabi-gcc${TOOL_EXECUTABLE_SUFFIX}")
|
||||
SET(CMAKE_OBJCOPY "arm-none-eabi-objcopy${TOOL_EXECUTABLE_SUFFIX}" CACHE STRING "objcopy tool")
|
||||
SET(CMAKE_OBJDUMP "arm-none-eabi-objdump${TOOL_EXECUTABLE_SUFFIX}" CACHE STRING "objdump tool")
|
||||
SET(CMAKE_SIZE "arm-none-eabi-size${TOOL_EXECUTABLE_SUFFIX}" CACHE STRING "size tool")
|
||||
|
||||
#-- Common flags ---------------------------------------------------------------
|
||||
SET(COMPILER_COMMON_FLAGS "-mthumb -mcpu=cortex-m7 -mfloat-abi=soft -mfpu=fpv5-sp-d16 -Wall -Wextra -ffunction-sections -fdata-sections -mlong-calls")
|
||||
SET(CMAKE_C_FLAGS "${COMPILER_COMMON_FLAGS} -std=gnu99" CACHE STRING "c compiler flags")
|
||||
SET(CMAKE_CXX_FLAGS "${COMPILER_COMMON_FLAGS} -std=c++11" CACHE STRING "c++ compiler flags")
|
||||
SET(CMAKE_ASM_FLAGS "-mthumb -mcpu=cortex-m7" CACHE STRING "assembler compiler flags")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS "-mthumb -mcpu=cortex-m7 -mfloat-abi=soft -mfpu=fpv5-sp-d16 -mlong-calls -Wl,--gc-sections -specs=nosys.specs -specs=nano.specs -lgcc -lc" CACHE STRING "executable linker flags")
|
||||
SET(CMAKE_MODULE_LINKER_FLAGS "-mthumb -mcpu=cortex-m7 -mfloat-abi=soft -mfpu=fpv5-sp-d16" CACHE STRING "module linker flags")
|
||||
SET(CMAKE_SHARED_LINKER_FLAGS "-mthumb -mcpu=cortex-m7 -mfloat-abi=soft -mfpu=fpv5-sp-d16" CACHE STRING "shared linker flags")
|
||||
|
||||
#-- Debug flags ----------------------------------------------------------------
|
||||
SET(CMAKE_C_FLAGS_DEBUG "-g -Og -DDEBUG" CACHE STRING "c compiler flags debug")
|
||||
SET(CMAKE_CXX_FLAGS_DEBUG "-g -Og -DDEBUG" CACHE STRING "c++ compiler flags debug")
|
||||
SET(CMAKE_ASM_FLAGS_DEBUG "-g" CACHE STRING "assembler compiler flags debug")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "" CACHE STRING "linker flags debug")
|
||||
|
||||
#-- Release flags ----------------------------------------------------------------
|
||||
SET(CMAKE_C_FLAGS_RELEASE "-O2 " CACHE STRING "c compiler flags release")
|
||||
SET(CMAKE_CXX_FLAGS_RELEASE "-O2" CACHE STRING "c++ compiler flags release")
|
||||
SET(CMAKE_ASM_FLAGS_RELEASE "" CACHE STRING "assembler compiler flags release")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_RELEASE "" CACHE STRING "linker flags release")
|
||||
|
||||
#-- Release with debug info flags ----------------------------------------------------------------
|
||||
SET(CMAKE_C_FLAGS_RELWITHDEBINFO "-g -O2" CACHE STRING "c compiler flags release with debug info")
|
||||
SET(CMAKE_CXX_FLAGS_RELWITHDEBINFO "-g -O2" CACHE STRING "c++ compiler flags release with debug info")
|
||||
SET(CMAKE_ASM_FLAGS_RELWITHDEBINFO "" CACHE STRING "assembler compiler flags release with debug info")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO "" CACHE STRING "linker flags release with debug info")
|
||||
|
||||
#-- Minimum size release flags ----------------------------------------------------------------
|
||||
SET(CMAKE_C_FLAGS_MINSIZEREL "-Os -flto -ffat-lto-objects" CACHE STRING "c compiler flags minimum size release")
|
||||
SET(CMAKE_CXX_FLAGS_MINSIZEREL "-Os -flto -ffat-lto-objects" CACHE STRING "c++ compiler flags minimum size release")
|
||||
SET(CMAKE_ASM_FLAGS_MINSIZEREL "" CACHE STRING "assembler compiler flags minimum size release")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_MINSIZEREL "-flto" CACHE STRING "linker flags minimum size release")
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
#-- System ---------------------------------------------------------------------
|
||||
SET(CMAKE_SYSTEM_NAME Generic)
|
||||
SET(CMAKE_SYSTEM_PROCESSOR arm)
|
||||
|
||||
#-- Toolchain ------------------------------------------------------------------
|
||||
SET(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
|
||||
IF(WIN32)
|
||||
SET(TOOL_EXECUTABLE_SUFFIX ".exe")
|
||||
ELSE()
|
||||
SET(TOOL_EXECUTABLE_SUFFIX "")
|
||||
ENDIF()
|
||||
SET(CMAKE_C_COMPILER "arm-none-eabi-gcc${TOOL_EXECUTABLE_SUFFIX}")
|
||||
SET(CMAKE_CXX_COMPILER "arm-none-eabi-g++${TOOL_EXECUTABLE_SUFFIX}")
|
||||
SET(CMAKE_ASM_COMPILER "arm-none-eabi-gcc${TOOL_EXECUTABLE_SUFFIX}")
|
||||
SET(CMAKE_OBJCOPY "arm-none-eabi-objcopy${TOOL_EXECUTABLE_SUFFIX}" CACHE STRING "objcopy tool")
|
||||
SET(CMAKE_OBJDUMP "arm-none-eabi-objdump${TOOL_EXECUTABLE_SUFFIX}" CACHE STRING "objdump tool")
|
||||
SET(CMAKE_SIZE "arm-none-eabi-size${TOOL_EXECUTABLE_SUFFIX}" CACHE STRING "size tool")
|
||||
|
||||
#-- Common flags ---------------------------------------------------------------
|
||||
SET(COMPILER_COMMON_FLAGS "-mcpu=cortex-m7 -march=armv7e-m+fp -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 -Wall -Wextra -ffunction-sections -fdata-sections -mlong-calls -Wno-unused-function -Wno-unused-variable -Wno-unused-parameter -fno-builtin -fno-builtin-printf")
|
||||
SET(CMAKE_C_FLAGS "${COMPILER_COMMON_FLAGS} -std=gnu99" CACHE STRING "c compiler flags")
|
||||
SET(CMAKE_CXX_FLAGS "${COMPILER_COMMON_FLAGS} -std=c++11" CACHE STRING "c++ compiler flags")
|
||||
SET(CMAKE_ASM_FLAGS "-mthumb -mcpu=cortex-m7" CACHE STRING "assembler compiler flags")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS "-mcpu=cortex-m7 -march=armv7e-m+fp -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 -mlong-calls -Wl,--gc-sections -specs=nosys.specs -specs=nano.specs -lgcc -lc" CACHE STRING "executable linker flags")
|
||||
SET(CMAKE_MODULE_LINKER_FLAGS "-mcpu=cortex-m7 -march=armv7e-m+fp -mthumb -mfloat-abi=soft -mfpu=fpv5-sp-d16" CACHE STRING "module linker flags")
|
||||
SET(CMAKE_SHARED_LINKER_FLAGS "-mcpu=cortex-m7 -march=armv7e-m+fp -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16" CACHE STRING "shared linker flags")
|
||||
|
||||
#-- Debug flags ----------------------------------------------------------------
|
||||
SET(CMAKE_C_FLAGS_DEBUG "-g -Og -DDEBUG" CACHE STRING "c compiler flags debug")
|
||||
SET(CMAKE_CXX_FLAGS_DEBUG "-g -Og -DDEBUG" CACHE STRING "c++ compiler flags debug")
|
||||
SET(CMAKE_ASM_FLAGS_DEBUG "-g" CACHE STRING "assembler compiler flags debug")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "" CACHE STRING "linker flags debug")
|
||||
|
||||
#-- Release flags ----------------------------------------------------------------
|
||||
SET(CMAKE_C_FLAGS_RELEASE "-O2 " CACHE STRING "c compiler flags release")
|
||||
SET(CMAKE_CXX_FLAGS_RELEASE "-O2" CACHE STRING "c++ compiler flags release")
|
||||
SET(CMAKE_ASM_FLAGS_RELEASE "" CACHE STRING "assembler compiler flags release")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_RELEASE "" CACHE STRING "linker flags release")
|
||||
|
||||
#-- Release with debug info flags ----------------------------------------------------------------
|
||||
SET(CMAKE_C_FLAGS_RELWITHDEBINFO "-g -O2" CACHE STRING "c compiler flags release with debug info")
|
||||
SET(CMAKE_CXX_FLAGS_RELWITHDEBINFO "-g -O2" CACHE STRING "c++ compiler flags release with debug info")
|
||||
SET(CMAKE_ASM_FLAGS_RELWITHDEBINFO "" CACHE STRING "assembler compiler flags release with debug info")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO "" CACHE STRING "linker flags release with debug info")
|
||||
|
||||
#-- Minimum size release flags ----------------------------------------------------------------
|
||||
SET(CMAKE_C_FLAGS_MINSIZEREL "-Os -flto -ffat-lto-objects" CACHE STRING "c compiler flags minimum size release")
|
||||
SET(CMAKE_CXX_FLAGS_MINSIZEREL "-Os -flto -ffat-lto-objects" CACHE STRING "c++ compiler flags minimum size release")
|
||||
SET(CMAKE_ASM_FLAGS_MINSIZEREL "" CACHE STRING "assembler compiler flags minimum size release")
|
||||
SET(CMAKE_EXE_LINKER_FLAGS_MINSIZEREL "-flto" CACHE STRING "linker flags minimum size release")
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
{
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
],
|
||||
"srcs": [
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1 @@
|
|||
#define VERSION_RANDOM_BUILD_IDENTIFIER "RPcyf"
|
||||
|
|
@ -0,0 +1 @@
|
|||
#define VERSION_RANDOM_BUILD_IDENTIFIER "${VRS_BUILD_RND}"
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
{
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"./"
|
||||
],
|
||||
"srcs": [
|
||||
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
set(WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR})
|
||||
|
||||
string(RANDOM VRS_BUILD_RND)
|
||||
configure_file(${WORKING_DIRECTORY}/VersionRandID.h.in ${WORKING_DIRECTORY}/VersionRandID.h)
|
||||
|
||||
message(STATUS "New build identifier: " \"${VRS_BUILD_RND}\")
|
||||
|
|
@ -0,0 +1,846 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* ----------------------------------------------------------------------
|
||||
*
|
||||
* $Date: 10. January 2017
|
||||
* $Revision: V2.1.0
|
||||
*
|
||||
* Project: CMSIS-RTOS API
|
||||
* Title: cmsis_os.h FreeRTOS header file
|
||||
*
|
||||
* Version 0.02
|
||||
* Initial Proposal Phase
|
||||
* Version 0.03
|
||||
* osKernelStart added, optional feature: main started as thread
|
||||
* osSemaphores have standard behavior
|
||||
* osTimerCreate does not start the timer, added osTimerStart
|
||||
* osThreadPass is renamed to osThreadYield
|
||||
* Version 1.01
|
||||
* Support for C++ interface
|
||||
* - const attribute removed from the osXxxxDef_t typedefs
|
||||
* - const attribute added to the osXxxxDef macros
|
||||
* Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
|
||||
* Added: osKernelInitialize
|
||||
* Version 1.02
|
||||
* Control functions for short timeouts in microsecond resolution:
|
||||
* Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
|
||||
* Removed: osSignalGet
|
||||
* Version 2.0.0
|
||||
* OS objects creation without macros (dynamic creation and resource allocation):
|
||||
* - added: osXxxxNew functions which replace osXxxxCreate
|
||||
* - added: osXxxxAttr_t structures
|
||||
* - deprecated: osXxxxCreate functions, osXxxxDef_t structures
|
||||
* - deprecated: osXxxxDef and osXxxx macros
|
||||
* osStatus codes simplified and renamed to osStatus_t
|
||||
* osEvent return structure deprecated
|
||||
* Kernel:
|
||||
* - added: osKernelInfo_t and osKernelGetInfo
|
||||
* - added: osKernelState_t and osKernelGetState (replaces osKernelRunning)
|
||||
* - added: osKernelLock, osKernelUnlock
|
||||
* - added: osKernelSuspend, osKernelResume
|
||||
* - added: osKernelGetTickCount, osKernelGetTickFreq
|
||||
* - renamed osKernelSysTick to osKernelGetSysTimerCount
|
||||
* - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq
|
||||
* - deprecated osKernelSysTickMicroSec
|
||||
* Thread:
|
||||
* - extended number of thread priorities
|
||||
* - renamed osPrioriry to osPrioriry_t
|
||||
* - replaced osThreadCreate with osThreadNew
|
||||
* - added: osThreadGetName
|
||||
* - added: osThreadState_t and osThreadGetState
|
||||
* - added: osThreadGetStackSize, osThreadGetStackSpace
|
||||
* - added: osThreadSuspend, osThreadResume
|
||||
* - added: osThreadJoin, osThreadDetach, osThreadExit
|
||||
* - added: osThreadGetCount, osThreadEnumerate
|
||||
* - added: Thread Flags (moved from Signals)
|
||||
* Signals:
|
||||
* - renamed osSignals to osThreadFlags (moved to Thread Flags)
|
||||
* - changed return value of Set/Clear/Wait functions
|
||||
* - Clear function limited to current running thread
|
||||
* - extended Wait function (options)
|
||||
* - added: osThreadFlagsGet
|
||||
* Event Flags:
|
||||
* - added new independent object for handling Event Flags
|
||||
* Delay and Wait functions:
|
||||
* - added: osDelayUntil
|
||||
* - deprecated: osWait
|
||||
* Timer:
|
||||
* - replaced osTimerCreate with osTimerNew
|
||||
* - added: osTimerGetName, osTimerIsRunning
|
||||
* Mutex:
|
||||
* - extended: attributes (Recursive, Priority Inherit, Robust)
|
||||
* - replaced osMutexCreate with osMutexNew
|
||||
* - renamed osMutexWait to osMutexAcquire
|
||||
* - added: osMutexGetName, osMutexGetOwner
|
||||
* Semaphore:
|
||||
* - extended: maximum and initial token count
|
||||
* - replaced osSemaphoreCreate with osSemaphoreNew
|
||||
* - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value)
|
||||
* - added: osSemaphoreGetName, osSemaphoreGetCount
|
||||
* Memory Pool:
|
||||
* - using osMemoryPool prefix instead of osPool
|
||||
* - replaced osPoolCreate with osMemoryPoolNew
|
||||
* - extended osMemoryPoolAlloc (timeout)
|
||||
* - added: osMemoryPoolGetName
|
||||
* - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize
|
||||
* - added: osMemoryPoolGetCount, osMemoryPoolGetSpace
|
||||
* - added: osMemoryPoolDelete
|
||||
* - deprecated: osPoolCAlloc
|
||||
* Message Queue:
|
||||
* - extended: fixed size message instead of a single 32-bit value
|
||||
* - using osMessageQueue prefix instead of osMessage
|
||||
* - replaced osMessageCreate with osMessageQueueNew
|
||||
* - updated: osMessageQueuePut, osMessageQueueGet
|
||||
* - added: osMessageQueueGetName
|
||||
* - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize
|
||||
* - added: osMessageQueueGetCount, osMessageQueueGetSpace
|
||||
* - added: osMessageQueueReset, osMessageQueueDelete
|
||||
* Mail Queue:
|
||||
* - deprecated (superseded by extended Message Queue functionality)
|
||||
* Version 2.1.0
|
||||
* Support for critical and uncritical sections (nesting safe):
|
||||
* - updated: osKernelLock, osKernelUnlock
|
||||
* - added: osKernelRestoreLock
|
||||
* Updated Thread and Event Flags:
|
||||
* - changed flags parameter and return type from int32_t to uint32_t
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef CMSIS_OS_H_
|
||||
#define CMSIS_OS_H_
|
||||
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
#define RTOS_ID_n ((tskKERNEL_VERSION_MAJOR << 16) | (tskKERNEL_VERSION_MINOR))
|
||||
#define RTOS_ID_s ("FreeRTOS " tskKERNEL_VERSION_NUMBER)
|
||||
|
||||
#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0])
|
||||
|
||||
#define osCMSIS_FreeRTOS RTOS_ID_n ///< RTOS identification and version (main[31:16].sub[15:0])
|
||||
|
||||
#define osKernelSystemId RTOS_ID_s ///< RTOS identification string
|
||||
|
||||
#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available
|
||||
#define osFeature_Signals 24U ///< maximum number of Signal Flags available per thread
|
||||
#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function
|
||||
#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available
|
||||
#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available
|
||||
#define osFeature_Pool 0 ///< Memory Pools: 1=available, 0=not available
|
||||
#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available
|
||||
#define osFeature_MailQ 0 ///< Mail Queues: 1=available, 0=not available
|
||||
|
||||
#if defined(__CC_ARM)
|
||||
#define os_InRegs __value_in_regs
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define os_InRegs __attribute__((value_in_regs))
|
||||
#else
|
||||
#define os_InRegs
|
||||
#endif
|
||||
|
||||
#include "cmsis_os2.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
// ==== Enumerations, structures, defines ====
|
||||
|
||||
/// Priority values.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef enum {
|
||||
osPriorityIdle = -3, ///< Priority: idle (lowest)
|
||||
osPriorityLow = -2, ///< Priority: low
|
||||
osPriorityBelowNormal = -1, ///< Priority: below normal
|
||||
osPriorityNormal = 0, ///< Priority: normal (default)
|
||||
osPriorityAboveNormal = +1, ///< Priority: above normal
|
||||
osPriorityHigh = +2, ///< Priority: high
|
||||
osPriorityRealtime = +3, ///< Priority: realtime (highest)
|
||||
osPriorityError = 0x84, ///< System cannot determine priority or illegal priority.
|
||||
osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
|
||||
} osPriority;
|
||||
#else
|
||||
#define osPriority osPriority_t
|
||||
#endif
|
||||
|
||||
/// Entry point of a thread.
|
||||
typedef void (*os_pthread) (void const *argument);
|
||||
|
||||
/// Entry point of a timer call back function.
|
||||
typedef void (*os_ptimer) (void const *argument);
|
||||
|
||||
/// Timer type.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef enum {
|
||||
osTimerOnce = 0, ///< One-shot timer.
|
||||
osTimerPeriodic = 1 ///< Repeating timer.
|
||||
} os_timer_type;
|
||||
#else
|
||||
#define os_timer_type osTimerType_t
|
||||
#endif
|
||||
|
||||
/// Timeout value.
|
||||
#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value.
|
||||
|
||||
/// Status code values returned by CMSIS-RTOS functions.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef enum {
|
||||
osOK = 0, ///< Function completed; no error or event occurred.
|
||||
osEventSignal = 0x08, ///< Function completed; signal event occurred.
|
||||
osEventMessage = 0x10, ///< Function completed; message event occurred.
|
||||
osEventMail = 0x20, ///< Function completed; mail event occurred.
|
||||
osEventTimeout = 0x40, ///< Function completed; timeout occurred.
|
||||
osErrorParameter = 0x80, ///< Parameter error: a mandatory parameter was missing or specified an incorrect object.
|
||||
osErrorResource = 0x81, ///< Resource not available: a specified resource was not available.
|
||||
osErrorTimeoutResource = 0xC1, ///< Resource not available within given time: a specified resource was not available within the timeout period.
|
||||
osErrorISR = 0x82, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
|
||||
osErrorISRRecursive = 0x83, ///< Function called multiple times from ISR with same object.
|
||||
osErrorPriority = 0x84, ///< System cannot determine priority or thread has illegal priority.
|
||||
osErrorNoMemory = 0x85, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
|
||||
osErrorValue = 0x86, ///< Value of a parameter is out of range.
|
||||
osErrorOS = 0xFF, ///< Unspecified RTOS error: run-time error but no other error message fits.
|
||||
osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
|
||||
} osStatus;
|
||||
#else
|
||||
typedef int32_t osStatus;
|
||||
#define osEventSignal (0x08)
|
||||
#define osEventMessage (0x10)
|
||||
#define osEventMail (0x20)
|
||||
#define osEventTimeout (0x40)
|
||||
#define osErrorOS osError
|
||||
#define osErrorTimeoutResource osErrorTimeout
|
||||
#define osErrorISRRecursive (-126)
|
||||
#define osErrorValue (-127)
|
||||
#define osErrorPriority (-128)
|
||||
#endif
|
||||
|
||||
|
||||
// >>> the following data type definitions may be adapted towards a specific RTOS
|
||||
|
||||
/// Thread ID identifies the thread.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef void *osThreadId;
|
||||
#else
|
||||
#define osThreadId osThreadId_t
|
||||
#endif
|
||||
|
||||
/// Timer ID identifies the timer.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef void *osTimerId;
|
||||
#else
|
||||
#define osTimerId osTimerId_t
|
||||
#endif
|
||||
|
||||
/// Mutex ID identifies the mutex.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef void *osMutexId;
|
||||
#else
|
||||
#define osMutexId osMutexId_t
|
||||
#endif
|
||||
|
||||
/// Semaphore ID identifies the semaphore.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef void *osSemaphoreId;
|
||||
#else
|
||||
#define osSemaphoreId osSemaphoreId_t
|
||||
#endif
|
||||
|
||||
/// Pool ID identifies the memory pool.
|
||||
typedef void *osPoolId;
|
||||
|
||||
/// Message ID identifies the message queue.
|
||||
typedef void *osMessageQId;
|
||||
|
||||
/// Mail ID identifies the mail queue.
|
||||
typedef void *osMailQId;
|
||||
|
||||
|
||||
/// Thread Definition structure contains startup information of a thread.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef struct os_thread_def {
|
||||
os_pthread pthread; ///< start address of thread function
|
||||
osPriority tpriority; ///< initial thread priority
|
||||
uint32_t instances; ///< maximum number of instances of that thread function
|
||||
uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size
|
||||
} osThreadDef_t;
|
||||
#else
|
||||
typedef struct os_thread_def {
|
||||
os_pthread pthread; ///< start address of thread function
|
||||
osThreadAttr_t attr; ///< thread attributes
|
||||
} osThreadDef_t;
|
||||
#endif
|
||||
|
||||
/// Timer Definition structure contains timer parameters.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef struct os_timer_def {
|
||||
os_ptimer ptimer; ///< start address of a timer function
|
||||
} osTimerDef_t;
|
||||
#else
|
||||
typedef struct os_timer_def {
|
||||
os_ptimer ptimer; ///< start address of a timer function
|
||||
osTimerAttr_t attr; ///< timer attributes
|
||||
} osTimerDef_t;
|
||||
#endif
|
||||
|
||||
/// Mutex Definition structure contains setup information for a mutex.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef struct os_mutex_def {
|
||||
uint32_t dummy; ///< dummy value
|
||||
} osMutexDef_t;
|
||||
#else
|
||||
#define osMutexDef_t osMutexAttr_t
|
||||
#endif
|
||||
|
||||
/// Semaphore Definition structure contains setup information for a semaphore.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef struct os_semaphore_def {
|
||||
uint32_t dummy; ///< dummy value
|
||||
} osSemaphoreDef_t;
|
||||
#else
|
||||
#define osSemaphoreDef_t osSemaphoreAttr_t
|
||||
#endif
|
||||
|
||||
/// Definition structure for memory block allocation.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef struct os_pool_def {
|
||||
uint32_t pool_sz; ///< number of items (elements) in the pool
|
||||
uint32_t item_sz; ///< size of an item
|
||||
void *pool; ///< pointer to memory for pool
|
||||
} osPoolDef_t;
|
||||
#else
|
||||
typedef struct os_pool_def {
|
||||
uint32_t pool_sz; ///< number of items (elements) in the pool
|
||||
uint32_t item_sz; ///< size of an item
|
||||
osMemoryPoolAttr_t attr; ///< memory pool attributes
|
||||
} osPoolDef_t;
|
||||
#endif
|
||||
|
||||
/// Definition structure for message queue.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef struct os_messageQ_def {
|
||||
uint32_t queue_sz; ///< number of elements in the queue
|
||||
void *pool; ///< memory array for messages
|
||||
} osMessageQDef_t;
|
||||
#else
|
||||
typedef struct os_messageQ_def {
|
||||
uint32_t queue_sz; ///< number of elements in the queue
|
||||
osMessageQueueAttr_t attr; ///< message queue attributes
|
||||
} osMessageQDef_t;
|
||||
#endif
|
||||
|
||||
/// Definition structure for mail queue.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
typedef struct os_mailQ_def {
|
||||
uint32_t queue_sz; ///< number of elements in the queue
|
||||
uint32_t item_sz; ///< size of an item
|
||||
void *pool; ///< memory array for mail
|
||||
} osMailQDef_t;
|
||||
#else
|
||||
typedef struct os_mailQ_def {
|
||||
uint32_t queue_sz; ///< number of elements in the queue
|
||||
uint32_t item_sz; ///< size of an item
|
||||
void *mail; ///< pointer to mail
|
||||
osMemoryPoolAttr_t mp_attr; ///< memory pool attributes
|
||||
osMessageQueueAttr_t mq_attr; ///< message queue attributes
|
||||
} osMailQDef_t;
|
||||
#endif
|
||||
|
||||
|
||||
/// Event structure contains detailed information about an event.
|
||||
typedef struct {
|
||||
osStatus status; ///< status code: event or error information
|
||||
union {
|
||||
uint32_t v; ///< message as 32-bit value
|
||||
void *p; ///< message or mail as void pointer
|
||||
int32_t signals; ///< signal flags
|
||||
} value; ///< event value
|
||||
union {
|
||||
osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
|
||||
osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
|
||||
} def; ///< event definition
|
||||
} osEvent;
|
||||
|
||||
|
||||
// ==== Kernel Management Functions ====
|
||||
|
||||
/// Initialize the RTOS Kernel for creating objects.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osKernelInitialize (void);
|
||||
#endif
|
||||
|
||||
/// Start the RTOS Kernel scheduler.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osKernelStart (void);
|
||||
#endif
|
||||
|
||||
/// Check if the RTOS kernel is already started.
|
||||
/// \return 0 RTOS is not started, 1 RTOS is started.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
int32_t osKernelRunning(void);
|
||||
#endif
|
||||
|
||||
#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
|
||||
|
||||
/// Get the RTOS kernel system timer counter.
|
||||
/// \return RTOS kernel system timer as 32-bit value
|
||||
#if (osCMSIS < 0x20000U)
|
||||
uint32_t osKernelSysTick (void);
|
||||
#else
|
||||
#define osKernelSysTick osKernelGetSysTimerCount
|
||||
#endif
|
||||
|
||||
/// The RTOS kernel system timer frequency in Hz.
|
||||
/// \note Reflects the system timer setting and is typically defined in a configuration file.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
#define osKernelSysTickFrequency 100000000
|
||||
#endif
|
||||
|
||||
/// Convert a microseconds value to a RTOS kernel system timer value.
|
||||
/// \param microsec time value in microseconds.
|
||||
/// \return time value normalized to the \ref osKernelSysTickFrequency
|
||||
#if (osCMSIS < 0x20000U)
|
||||
#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
|
||||
#else
|
||||
#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000)
|
||||
#endif
|
||||
|
||||
#endif // System Timer available
|
||||
|
||||
|
||||
// ==== Thread Management Functions ====
|
||||
|
||||
/// Create a Thread Definition with function, priority, and stack requirements.
|
||||
/// \param name name of the thread function.
|
||||
/// \param priority initial priority of the thread function.
|
||||
/// \param instances number of possible thread instances.
|
||||
/// \param stacksz stack size (in bytes) requirements for the thread function.
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osThreadDef(name, priority, instances, stacksz) \
|
||||
extern const osThreadDef_t os_thread_def_##name
|
||||
#else // define the object
|
||||
#define osThreadDef(name, priority, instances, stacksz) \
|
||||
static uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1]; \
|
||||
static StaticTask_t os_thread_cb_##name; \
|
||||
const osThreadDef_t os_thread_def_##name = \
|
||||
{ (name), \
|
||||
{ NULL, osThreadDetached, \
|
||||
(instances == 1) ? (&os_thread_cb_##name) : NULL,\
|
||||
(instances == 1) ? sizeof(StaticTask_t) : 0U, \
|
||||
((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \
|
||||
8*((stacksz+7)/8), \
|
||||
(priority), 0U, 0U } }
|
||||
#endif
|
||||
|
||||
/// Access a Thread definition.
|
||||
/// \param name name of the thread definition object.
|
||||
#define osThread(name) \
|
||||
&os_thread_def_##name
|
||||
|
||||
/// Create a thread and add it to Active Threads and set it to state READY.
|
||||
/// \param[in] thread_def thread definition referenced with \ref osThread.
|
||||
/// \param[in] argument pointer that is passed to the thread function as start argument.
|
||||
/// \return thread ID for reference by other functions or NULL in case of error.
|
||||
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
|
||||
|
||||
/// Return the thread ID of the current running thread.
|
||||
/// \return thread ID for reference by other functions or NULL in case of error.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osThreadId osThreadGetId (void);
|
||||
#endif
|
||||
|
||||
/// Change priority of a thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
|
||||
/// \param[in] priority new priority value for the thread function.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
|
||||
#endif
|
||||
|
||||
/// Get current priority of a thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
|
||||
/// \return current priority value of the specified thread.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osPriority osThreadGetPriority (osThreadId thread_id);
|
||||
#endif
|
||||
|
||||
/// Pass control to next thread that is in state \b READY.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osThreadYield (void);
|
||||
#endif
|
||||
|
||||
/// Terminate execution of a thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osThreadTerminate (osThreadId thread_id);
|
||||
#endif
|
||||
|
||||
|
||||
// ==== Signal Management ====
|
||||
|
||||
/// Set the specified Signal Flags of an active thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
|
||||
/// \param[in] signals specifies the signal flags of the thread that should be set.
|
||||
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
|
||||
int32_t osSignalSet (osThreadId thread_id, int32_t signals);
|
||||
|
||||
/// Clear the specified Signal Flags of an active thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
|
||||
/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
|
||||
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
|
||||
int32_t osSignalClear (osThreadId thread_id, int32_t signals);
|
||||
|
||||
/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
|
||||
/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return event flag information or error code.
|
||||
os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);
|
||||
|
||||
|
||||
// ==== Generic Wait Functions ====
|
||||
|
||||
/// Wait for Timeout (Time Delay).
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osDelay (uint32_t millisec);
|
||||
#endif
|
||||
|
||||
#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
|
||||
|
||||
/// Wait for Signal, Message, Mail, or Timeout.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
|
||||
/// \return event that contains signal, message, or mail information or error code.
|
||||
os_InRegs osEvent osWait (uint32_t millisec);
|
||||
|
||||
#endif // Generic Wait available
|
||||
|
||||
|
||||
// ==== Timer Management Functions ====
|
||||
|
||||
/// Define a Timer object.
|
||||
/// \param name name of the timer object.
|
||||
/// \param function name of the timer call back function.
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osTimerDef(name, function) \
|
||||
extern const osTimerDef_t os_timer_def_##name
|
||||
#else // define the object
|
||||
#define osTimerDef(name, function) \
|
||||
static StaticTimer_t os_timer_cb_##name; \
|
||||
const osTimerDef_t os_timer_def_##name = \
|
||||
{ (function), { NULL, 0U, (&os_timer_cb_##name), sizeof(StaticTimer_t) } }
|
||||
#endif
|
||||
|
||||
/// Access a Timer definition.
|
||||
/// \param name name of the timer object.
|
||||
#define osTimer(name) \
|
||||
&os_timer_def_##name
|
||||
|
||||
/// Create and Initialize a timer.
|
||||
/// \param[in] timer_def timer object referenced with \ref osTimer.
|
||||
/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
|
||||
/// \param[in] argument argument to the timer call back function.
|
||||
/// \return timer ID for reference by other functions or NULL in case of error.
|
||||
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
|
||||
|
||||
/// Start or restart a timer.
|
||||
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
|
||||
#endif
|
||||
|
||||
/// Stop a timer.
|
||||
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osTimerStop (osTimerId timer_id);
|
||||
#endif
|
||||
|
||||
/// Delete a timer.
|
||||
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osTimerDelete (osTimerId timer_id);
|
||||
#endif
|
||||
|
||||
|
||||
// ==== Mutex Management Functions ====
|
||||
|
||||
/// Define a Mutex.
|
||||
/// \param name name of the mutex object.
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osMutexDef(name) \
|
||||
extern const osMutexDef_t os_mutex_def_##name
|
||||
#else // define the object
|
||||
#define osMutexDef(name) \
|
||||
static StaticSemaphore_t os_mutex_cb_##name; \
|
||||
const osMutexDef_t os_mutex_def_##name = \
|
||||
{ NULL, osMutexRecursive | osMutexPrioInherit, (&os_mutex_cb_##name), sizeof(StaticSemaphore_t) }
|
||||
#endif
|
||||
|
||||
/// Access a Mutex definition.
|
||||
/// \param name name of the mutex object.
|
||||
#define osMutex(name) \
|
||||
&os_mutex_def_##name
|
||||
|
||||
/// Create and Initialize a Mutex object.
|
||||
/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
|
||||
/// \return mutex ID for reference by other functions or NULL in case of error.
|
||||
osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
|
||||
|
||||
/// Wait until a Mutex becomes available.
|
||||
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
|
||||
#else
|
||||
#define osMutexWait osMutexAcquire
|
||||
#endif
|
||||
|
||||
/// Release a Mutex that was obtained by \ref osMutexWait.
|
||||
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osMutexRelease (osMutexId mutex_id);
|
||||
#endif
|
||||
|
||||
/// Delete a Mutex object.
|
||||
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osMutexDelete (osMutexId mutex_id);
|
||||
#endif
|
||||
|
||||
|
||||
// ==== Semaphore Management Functions ====
|
||||
|
||||
#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available
|
||||
|
||||
/// Define a Semaphore object.
|
||||
/// \param name name of the semaphore object.
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osSemaphoreDef(name) \
|
||||
extern const osSemaphoreDef_t os_semaphore_def_##name
|
||||
#else // define the object
|
||||
#define osSemaphoreDef(name) \
|
||||
static StaticSemaphore_t os_semaphore_cb_##name; \
|
||||
const osSemaphoreDef_t os_semaphore_def_##name = \
|
||||
{ NULL, 0U, (&os_semaphore_cb_##name), sizeof(StaticSemaphore_t) }
|
||||
#endif
|
||||
|
||||
/// Access a Semaphore definition.
|
||||
/// \param name name of the semaphore object.
|
||||
#define osSemaphore(name) \
|
||||
&os_semaphore_def_##name
|
||||
|
||||
/// Create and Initialize a Semaphore object.
|
||||
/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
|
||||
/// \param[in] count maximum and initial number of available tokens.
|
||||
/// \return semaphore ID for reference by other functions or NULL in case of error.
|
||||
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
|
||||
|
||||
/// Wait until a Semaphore token becomes available.
|
||||
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return number of available tokens, or -1 in case of incorrect parameters.
|
||||
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
|
||||
|
||||
/// Release a Semaphore token.
|
||||
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
|
||||
#endif
|
||||
|
||||
/// Delete a Semaphore object.
|
||||
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
#if (osCMSIS < 0x20000U)
|
||||
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
|
||||
#endif
|
||||
|
||||
#endif // Semaphore available
|
||||
|
||||
|
||||
// ==== Memory Pool Management Functions ====
|
||||
|
||||
#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available
|
||||
|
||||
/// \brief Define a Memory Pool.
|
||||
/// \param name name of the memory pool.
|
||||
/// \param no maximum number of blocks (objects) in the memory pool.
|
||||
/// \param type data type of a single block (object).
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osPoolDef(name, no, type) \
|
||||
extern const osPoolDef_t os_pool_def_##name
|
||||
#else // define the object
|
||||
#define osPoolDef(name, no, type) \
|
||||
const osPoolDef_t os_pool_def_##name = \
|
||||
{ (no), sizeof(type), {NULL} }
|
||||
#endif
|
||||
|
||||
/// \brief Access a Memory Pool definition.
|
||||
/// \param name name of the memory pool
|
||||
#define osPool(name) \
|
||||
&os_pool_def_##name
|
||||
|
||||
/// Create and Initialize a Memory Pool object.
|
||||
/// \param[in] pool_def memory pool definition referenced with \ref osPool.
|
||||
/// \return memory pool ID for reference by other functions or NULL in case of error.
|
||||
osPoolId osPoolCreate (const osPoolDef_t *pool_def);
|
||||
|
||||
/// Allocate a memory block from a Memory Pool.
|
||||
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
|
||||
/// \return address of the allocated memory block or NULL in case of no memory available.
|
||||
void *osPoolAlloc (osPoolId pool_id);
|
||||
|
||||
/// Allocate a memory block from a Memory Pool and set memory block to zero.
|
||||
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
|
||||
/// \return address of the allocated memory block or NULL in case of no memory available.
|
||||
void *osPoolCAlloc (osPoolId pool_id);
|
||||
|
||||
/// Return an allocated memory block back to a Memory Pool.
|
||||
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
|
||||
/// \param[in] block address of the allocated memory block to be returned to the memory pool.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus osPoolFree (osPoolId pool_id, void *block);
|
||||
|
||||
#endif // Memory Pool available
|
||||
|
||||
|
||||
// ==== Message Queue Management Functions ====
|
||||
|
||||
#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available
|
||||
|
||||
/// \brief Create a Message Queue Definition.
|
||||
/// \param name name of the queue.
|
||||
/// \param queue_sz maximum number of messages in the queue.
|
||||
/// \param type data type of a single message element (for debugger).
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osMessageQDef(name, queue_sz, type) \
|
||||
extern const osMessageQDef_t os_messageQ_def_##name
|
||||
#else // define the object
|
||||
#define osMessageQDef(name, queue_sz, type) \
|
||||
static StaticQueue_t os_mq_cb_##name; \
|
||||
static uint32_t os_mq_data_##name[(queue_sz) * sizeof(type)]; \
|
||||
const osMessageQDef_t os_messageQ_def_##name = \
|
||||
{ (queue_sz), \
|
||||
{ NULL, 0U, (&os_mq_cb_##name), sizeof(StaticQueue_t), \
|
||||
(&os_mq_data_##name), sizeof(os_mq_data_##name) } }
|
||||
#endif
|
||||
|
||||
/// \brief Access a Message Queue Definition.
|
||||
/// \param name name of the queue
|
||||
#define osMessageQ(name) \
|
||||
&os_messageQ_def_##name
|
||||
|
||||
/// Create and Initialize a Message Queue object.
|
||||
/// \param[in] queue_def message queue definition referenced with \ref osMessageQ.
|
||||
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
|
||||
/// \return message queue ID for reference by other functions or NULL in case of error.
|
||||
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
|
||||
|
||||
/// Put a Message to a Queue.
|
||||
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
|
||||
/// \param[in] info message information.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
|
||||
|
||||
/// Get a Message from a Queue or timeout if Queue is empty.
|
||||
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return event information that includes status code.
|
||||
os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
|
||||
|
||||
#endif // Message Queue available
|
||||
|
||||
|
||||
// ==== Mail Queue Management Functions ====
|
||||
|
||||
#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available
|
||||
|
||||
/// \brief Create a Mail Queue Definition.
|
||||
/// \param name name of the queue.
|
||||
/// \param queue_sz maximum number of mails in the queue.
|
||||
/// \param type data type of a single mail element.
|
||||
#if defined (osObjectsExternal) // object is external
|
||||
#define osMailQDef(name, queue_sz, type) \
|
||||
extern const osMailQDef_t os_mailQ_def_##name
|
||||
#else // define the object
|
||||
#define osMailQDef(name, queue_sz, type) \
|
||||
const osMailQDef_t os_mailQ_def_##name = \
|
||||
{ (queue_sz), sizeof(type), NULL }
|
||||
#endif
|
||||
|
||||
/// \brief Access a Mail Queue Definition.
|
||||
/// \param name name of the queue
|
||||
#define osMailQ(name) \
|
||||
&os_mailQ_def_##name
|
||||
|
||||
/// Create and Initialize a Mail Queue object.
|
||||
/// \param[in] queue_def mail queue definition referenced with \ref osMailQ.
|
||||
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
|
||||
/// \return mail queue ID for reference by other functions or NULL in case of error.
|
||||
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
|
||||
|
||||
/// Allocate a memory block for mail from a mail memory pool.
|
||||
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
|
||||
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
|
||||
void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
|
||||
|
||||
/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.
|
||||
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
|
||||
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
|
||||
void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
|
||||
|
||||
/// Put a Mail into a Queue.
|
||||
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
|
||||
/// \param[in] mail pointer to memory with mail to put into a queue.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus osMailPut (osMailQId queue_id, const void *mail);
|
||||
|
||||
/// Get a Mail from a Queue or timeout if Queue is empty.
|
||||
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
|
||||
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return event information that includes status code.
|
||||
os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
|
||||
|
||||
/// Free a memory block by returning it to a mail memory pool.
|
||||
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
|
||||
/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus osMailFree (osMailQId queue_id, void *mail);
|
||||
|
||||
#endif // Mail Queue available
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // CMSIS_OS_H_
|
||||
|
|
@ -0,0 +1,736 @@
|
|||
/* --------------------------------------------------------------------------
|
||||
* Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved.
|
||||
* Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
* --------------------------------------------------------------------------
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* Name: cmsis_os2.h
|
||||
* Purpose: CMSIS RTOS2 wrapper for FreeRTOS
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef CMSIS_OS2_H_
|
||||
#define CMSIS_OS2_H_
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#if defined(__CC_ARM)
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#elif defined(__GNUC__)
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#elif defined(__ICCARM__)
|
||||
#define __NO_RETURN __noreturn
|
||||
#else
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
// ==== Enumerations, structures, defines ====
|
||||
|
||||
/// Version information.
|
||||
typedef struct {
|
||||
uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec).
|
||||
uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec).
|
||||
} osVersion_t;
|
||||
|
||||
/// Kernel state.
|
||||
typedef enum {
|
||||
osKernelInactive = 0, ///< Inactive.
|
||||
osKernelReady = 1, ///< Ready.
|
||||
osKernelRunning = 2, ///< Running.
|
||||
osKernelLocked = 3, ///< Locked.
|
||||
osKernelSuspended = 4, ///< Suspended.
|
||||
osKernelError = -1, ///< Error.
|
||||
osKernelReserved = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization.
|
||||
} osKernelState_t;
|
||||
|
||||
/// Thread state.
|
||||
typedef enum {
|
||||
osThreadInactive = 0, ///< Inactive.
|
||||
osThreadReady = 1, ///< Ready.
|
||||
osThreadRunning = 2, ///< Running.
|
||||
osThreadBlocked = 3, ///< Blocked.
|
||||
osThreadTerminated = 4, ///< Terminated.
|
||||
osThreadError = -1, ///< Error.
|
||||
osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
|
||||
} osThreadState_t;
|
||||
|
||||
/// Priority values.
|
||||
typedef enum {
|
||||
osPriorityNone = 0, ///< No priority (not initialized).
|
||||
osPriorityIdle = 1, ///< Reserved for Idle thread.
|
||||
osPriorityLow = 8, ///< Priority: low
|
||||
osPriorityLow1 = 8+1, ///< Priority: low + 1
|
||||
osPriorityLow2 = 8+2, ///< Priority: low + 2
|
||||
osPriorityLow3 = 8+3, ///< Priority: low + 3
|
||||
osPriorityLow4 = 8+4, ///< Priority: low + 4
|
||||
osPriorityLow5 = 8+5, ///< Priority: low + 5
|
||||
osPriorityLow6 = 8+6, ///< Priority: low + 6
|
||||
osPriorityLow7 = 8+7, ///< Priority: low + 7
|
||||
osPriorityBelowNormal = 16, ///< Priority: below normal
|
||||
osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1
|
||||
osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2
|
||||
osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3
|
||||
osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4
|
||||
osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5
|
||||
osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6
|
||||
osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7
|
||||
osPriorityNormal = 24, ///< Priority: normal
|
||||
osPriorityNormal1 = 24+1, ///< Priority: normal + 1
|
||||
osPriorityNormal2 = 24+2, ///< Priority: normal + 2
|
||||
osPriorityNormal3 = 24+3, ///< Priority: normal + 3
|
||||
osPriorityNormal4 = 24+4, ///< Priority: normal + 4
|
||||
osPriorityNormal5 = 24+5, ///< Priority: normal + 5
|
||||
osPriorityNormal6 = 24+6, ///< Priority: normal + 6
|
||||
osPriorityNormal7 = 24+7, ///< Priority: normal + 7
|
||||
osPriorityAboveNormal = 32, ///< Priority: above normal
|
||||
osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1
|
||||
osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2
|
||||
osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3
|
||||
osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4
|
||||
osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5
|
||||
osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6
|
||||
osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7
|
||||
osPriorityHigh = 40, ///< Priority: high
|
||||
osPriorityHigh1 = 40+1, ///< Priority: high + 1
|
||||
osPriorityHigh2 = 40+2, ///< Priority: high + 2
|
||||
osPriorityHigh3 = 40+3, ///< Priority: high + 3
|
||||
osPriorityHigh4 = 40+4, ///< Priority: high + 4
|
||||
osPriorityHigh5 = 40+5, ///< Priority: high + 5
|
||||
osPriorityHigh6 = 40+6, ///< Priority: high + 6
|
||||
osPriorityHigh7 = 40+7, ///< Priority: high + 7
|
||||
osPriorityRealtime = 48, ///< Priority: realtime
|
||||
osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1
|
||||
osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2
|
||||
osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3
|
||||
osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4
|
||||
osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5
|
||||
osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6
|
||||
osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7
|
||||
osPriorityISR = 56, ///< Reserved for ISR deferred thread.
|
||||
osPriorityError = -1, ///< System cannot determine priority or illegal priority.
|
||||
osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
|
||||
} osPriority_t;
|
||||
|
||||
/// Entry point of a thread.
|
||||
typedef void (*osThreadFunc_t) (void *argument);
|
||||
|
||||
/// Timer callback function.
|
||||
typedef void (*osTimerFunc_t) (void *argument);
|
||||
|
||||
/// Timer type.
|
||||
typedef enum {
|
||||
osTimerOnce = 0, ///< One-shot timer.
|
||||
osTimerPeriodic = 1 ///< Repeating timer.
|
||||
} osTimerType_t;
|
||||
|
||||
// Timeout value.
|
||||
#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value.
|
||||
|
||||
// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait).
|
||||
#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default).
|
||||
#define osFlagsWaitAll 0x00000001U ///< Wait for all flags.
|
||||
#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for.
|
||||
|
||||
// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).
|
||||
#define osFlagsError 0x80000000U ///< Error indicator.
|
||||
#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1).
|
||||
#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2).
|
||||
#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3).
|
||||
#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4).
|
||||
#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6).
|
||||
|
||||
// Thread attributes (attr_bits in \ref osThreadAttr_t).
|
||||
#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default)
|
||||
#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode
|
||||
|
||||
// Mutex attributes (attr_bits in \ref osMutexAttr_t).
|
||||
#define osMutexRecursive 0x00000001U ///< Recursive mutex.
|
||||
#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol.
|
||||
#define osMutexRobust 0x00000008U ///< Robust mutex.
|
||||
|
||||
/// Status code values returned by CMSIS-RTOS functions.
|
||||
typedef enum {
|
||||
osOK = 0, ///< Operation completed successfully.
|
||||
osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits.
|
||||
osErrorTimeout = -2, ///< Operation not completed within the timeout period.
|
||||
osErrorResource = -3, ///< Resource not available.
|
||||
osErrorParameter = -4, ///< Parameter error.
|
||||
osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
|
||||
osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
|
||||
osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
|
||||
} osStatus_t;
|
||||
|
||||
|
||||
/// \details Thread ID identifies the thread.
|
||||
typedef void *osThreadId_t;
|
||||
|
||||
/// \details Timer ID identifies the timer.
|
||||
typedef void *osTimerId_t;
|
||||
|
||||
/// \details Event Flags ID identifies the event flags.
|
||||
typedef void *osEventFlagsId_t;
|
||||
|
||||
/// \details Mutex ID identifies the mutex.
|
||||
typedef void *osMutexId_t;
|
||||
|
||||
/// \details Semaphore ID identifies the semaphore.
|
||||
typedef void *osSemaphoreId_t;
|
||||
|
||||
/// \details Memory Pool ID identifies the memory pool.
|
||||
typedef void *osMemoryPoolId_t;
|
||||
|
||||
/// \details Message Queue ID identifies the message queue.
|
||||
typedef void *osMessageQueueId_t;
|
||||
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
|
||||
/// Attributes structure for thread.
|
||||
typedef struct {
|
||||
const char *name; ///< name of the thread
|
||||
uint32_t attr_bits; ///< attribute bits
|
||||
void *cb_mem; ///< memory for control block
|
||||
uint32_t cb_size; ///< size of provided memory for control block
|
||||
void *stack_mem; ///< memory for stack
|
||||
uint32_t stack_size; ///< size of stack
|
||||
osPriority_t priority; ///< initial thread priority (default: osPriorityNormal)
|
||||
TZ_ModuleId_t tz_module; ///< TrustZone module identifier
|
||||
uint32_t reserved; ///< reserved (must be 0)
|
||||
uint8_t pinToCore;
|
||||
uint8_t core;
|
||||
} osThreadAttr_t;
|
||||
|
||||
/// Attributes structure for timer.
|
||||
typedef struct {
|
||||
const char *name; ///< name of the timer
|
||||
uint32_t attr_bits; ///< attribute bits
|
||||
void *cb_mem; ///< memory for control block
|
||||
uint32_t cb_size; ///< size of provided memory for control block
|
||||
} osTimerAttr_t;
|
||||
|
||||
/// Attributes structure for event flags.
|
||||
typedef struct {
|
||||
const char *name; ///< name of the event flags
|
||||
uint32_t attr_bits; ///< attribute bits
|
||||
void *cb_mem; ///< memory for control block
|
||||
uint32_t cb_size; ///< size of provided memory for control block
|
||||
} osEventFlagsAttr_t;
|
||||
|
||||
/// Attributes structure for mutex.
|
||||
typedef struct {
|
||||
const char *name; ///< name of the mutex
|
||||
uint32_t attr_bits; ///< attribute bits
|
||||
void *cb_mem; ///< memory for control block
|
||||
uint32_t cb_size; ///< size of provided memory for control block
|
||||
} osMutexAttr_t;
|
||||
|
||||
/// Attributes structure for semaphore.
|
||||
typedef struct {
|
||||
const char *name; ///< name of the semaphore
|
||||
uint32_t attr_bits; ///< attribute bits
|
||||
void *cb_mem; ///< memory for control block
|
||||
uint32_t cb_size; ///< size of provided memory for control block
|
||||
} osSemaphoreAttr_t;
|
||||
|
||||
/// Attributes structure for memory pool.
|
||||
typedef struct {
|
||||
const char *name; ///< name of the memory pool
|
||||
uint32_t attr_bits; ///< attribute bits
|
||||
void *cb_mem; ///< memory for control block
|
||||
uint32_t cb_size; ///< size of provided memory for control block
|
||||
void *mp_mem; ///< memory for data storage
|
||||
uint32_t mp_size; ///< size of provided memory for data storage
|
||||
} osMemoryPoolAttr_t;
|
||||
|
||||
/// Attributes structure for message queue.
|
||||
typedef struct {
|
||||
const char *name; ///< name of the message queue
|
||||
uint32_t attr_bits; ///< attribute bits
|
||||
void *cb_mem; ///< memory for control block
|
||||
uint32_t cb_size; ///< size of provided memory for control block
|
||||
void *mq_mem; ///< memory for data storage
|
||||
uint32_t mq_size; ///< size of provided memory for data storage
|
||||
} osMessageQueueAttr_t;
|
||||
|
||||
|
||||
// ==== Kernel Management Functions ====
|
||||
|
||||
/// Initialize the RTOS Kernel.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osKernelInitialize (void);
|
||||
|
||||
/// Get RTOS Kernel Information.
|
||||
/// \param[out] version pointer to buffer for retrieving version information.
|
||||
/// \param[out] id_buf pointer to buffer for retrieving kernel identification string.
|
||||
/// \param[in] id_size size of buffer for kernel identification string.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);
|
||||
|
||||
/// Get the current RTOS Kernel state.
|
||||
/// \return current RTOS Kernel state.
|
||||
osKernelState_t osKernelGetState (void);
|
||||
|
||||
/// Start the RTOS Kernel scheduler.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osKernelStart (void);
|
||||
|
||||
/// Lock the RTOS Kernel scheduler.
|
||||
/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
|
||||
int32_t osKernelLock (void);
|
||||
|
||||
/// Unlock the RTOS Kernel scheduler.
|
||||
/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
|
||||
int32_t osKernelUnlock (void);
|
||||
|
||||
/// Restore the RTOS Kernel scheduler lock state.
|
||||
/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock.
|
||||
/// \return new lock state (1 - locked, 0 - not locked, error code if negative).
|
||||
int32_t osKernelRestoreLock (int32_t lock);
|
||||
|
||||
/// Suspend the RTOS Kernel scheduler.
|
||||
/// \return time in ticks, for how long the system can sleep or power-down.
|
||||
uint32_t osKernelSuspend (void);
|
||||
|
||||
/// Resume the RTOS Kernel scheduler.
|
||||
/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode.
|
||||
void osKernelResume (uint32_t sleep_ticks);
|
||||
|
||||
/// Get the RTOS kernel tick count.
|
||||
/// \return RTOS kernel current tick count.
|
||||
uint32_t osKernelGetTickCount (void);
|
||||
|
||||
/// Get the RTOS kernel tick frequency.
|
||||
/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second.
|
||||
uint32_t osKernelGetTickFreq (void);
|
||||
|
||||
/// Get the RTOS kernel system timer count.
|
||||
/// \return RTOS kernel current system timer count as 32-bit value.
|
||||
uint32_t osKernelGetSysTimerCount (void);
|
||||
|
||||
/// Get the RTOS kernel system timer frequency.
|
||||
/// \return frequency of the system timer in hertz, i.e. timer ticks per second.
|
||||
uint32_t osKernelGetSysTimerFreq (void);
|
||||
|
||||
|
||||
// ==== Thread Management Functions ====
|
||||
|
||||
/// Create a thread and add it to Active Threads.
|
||||
/// \param[in] func thread function.
|
||||
/// \param[in] argument pointer that is passed to the thread function as start argument.
|
||||
/// \param[in] attr thread attributes; NULL: default values.
|
||||
/// \return thread ID for reference by other functions or NULL in case of error.
|
||||
osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);
|
||||
|
||||
/// Get name of a thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
|
||||
/// \return name as NULL terminated string.
|
||||
const char *osThreadGetName (osThreadId_t thread_id);
|
||||
|
||||
/// Return the thread ID of the current running thread.
|
||||
/// \return thread ID for reference by other functions or NULL in case of error.
|
||||
osThreadId_t osThreadGetId (void);
|
||||
|
||||
/// Get current thread state of a thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
|
||||
/// \return current thread state of the specified thread.
|
||||
osThreadState_t osThreadGetState (osThreadId_t thread_id);
|
||||
|
||||
/// Get stack size of a thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
|
||||
/// \return stack size in bytes.
|
||||
uint32_t osThreadGetStackSize (osThreadId_t thread_id);
|
||||
|
||||
/// Get available stack space of a thread based on stack watermark recording during execution.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
|
||||
/// \return remaining stack space in bytes.
|
||||
uint32_t osThreadGetStackSpace (osThreadId_t thread_id);
|
||||
|
||||
/// Change priority of a thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
|
||||
/// \param[in] priority new priority value for the thread function.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);
|
||||
|
||||
/// Get current priority of a thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
|
||||
/// \return current priority value of the specified thread.
|
||||
osPriority_t osThreadGetPriority (osThreadId_t thread_id);
|
||||
|
||||
/// Pass control to next thread that is in state \b READY.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osThreadYield (void);
|
||||
|
||||
/// Suspend execution of a thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osThreadSuspend (osThreadId_t thread_id);
|
||||
|
||||
/// Resume execution of a thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osThreadResume (osThreadId_t thread_id);
|
||||
|
||||
/// Detach a thread (thread storage can be reclaimed when thread terminates).
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osThreadDetach (osThreadId_t thread_id);
|
||||
|
||||
/// Wait for specified thread to terminate.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osThreadJoin (osThreadId_t thread_id);
|
||||
|
||||
/// Terminate execution of current running thread.
|
||||
__NO_RETURN void osThreadExit (void);
|
||||
|
||||
/// Terminate execution of a thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osThreadTerminate (osThreadId_t thread_id);
|
||||
|
||||
/// Get number of active threads.
|
||||
/// \return number of active threads.
|
||||
uint32_t osThreadGetCount (void);
|
||||
|
||||
/// Enumerate active threads.
|
||||
/// \param[out] thread_array pointer to array for retrieving thread IDs.
|
||||
/// \param[in] array_items maximum number of items in array for retrieving thread IDs.
|
||||
/// \return number of enumerated threads.
|
||||
uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);
|
||||
|
||||
|
||||
// ==== Thread Flags Functions ====
|
||||
|
||||
/// Set the specified Thread Flags of a thread.
|
||||
/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
|
||||
/// \param[in] flags specifies the flags of the thread that shall be set.
|
||||
/// \return thread flags after setting or error code if highest bit set.
|
||||
uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);
|
||||
|
||||
/// Clear the specified Thread Flags of current running thread.
|
||||
/// \param[in] flags specifies the flags of the thread that shall be cleared.
|
||||
/// \return thread flags before clearing or error code if highest bit set.
|
||||
uint32_t osThreadFlagsClear (uint32_t flags);
|
||||
|
||||
/// Get the current Thread Flags of current running thread.
|
||||
/// \return current thread flags.
|
||||
uint32_t osThreadFlagsGet (void);
|
||||
|
||||
/// Wait for one or more Thread Flags of the current running thread to become signaled.
|
||||
/// \param[in] flags specifies the flags to wait for.
|
||||
/// \param[in] options specifies flags options (osFlagsXxxx).
|
||||
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return thread flags before clearing or error code if highest bit set.
|
||||
uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);
|
||||
|
||||
|
||||
// ==== Generic Wait Functions ====
|
||||
|
||||
/// Wait for Timeout (Time Delay).
|
||||
/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osDelay (uint32_t ticks);
|
||||
|
||||
/// Wait until specified time.
|
||||
/// \param[in] ticks absolute time in ticks
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osDelayUntil (uint32_t ticks);
|
||||
|
||||
|
||||
// ==== Timer Management Functions ====
|
||||
|
||||
/// Create and Initialize a timer.
|
||||
/// \param[in] func function pointer to callback function.
|
||||
/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior.
|
||||
/// \param[in] argument argument to the timer callback function.
|
||||
/// \param[in] attr timer attributes; NULL: default values.
|
||||
/// \return timer ID for reference by other functions or NULL in case of error.
|
||||
osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
|
||||
|
||||
/// Get name of a timer.
|
||||
/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
|
||||
/// \return name as NULL terminated string.
|
||||
const char *osTimerGetName (osTimerId_t timer_id);
|
||||
|
||||
/// Start or restart a timer.
|
||||
/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
|
||||
/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);
|
||||
|
||||
/// Stop a timer.
|
||||
/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osTimerStop (osTimerId_t timer_id);
|
||||
|
||||
/// Check if a timer is running.
|
||||
/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
|
||||
/// \return 0 not running, 1 running.
|
||||
uint32_t osTimerIsRunning (osTimerId_t timer_id);
|
||||
|
||||
/// Delete a timer.
|
||||
/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osTimerDelete (osTimerId_t timer_id);
|
||||
|
||||
|
||||
// ==== Event Flags Management Functions ====
|
||||
|
||||
/// Create and Initialize an Event Flags object.
|
||||
/// \param[in] attr event flags attributes; NULL: default values.
|
||||
/// \return event flags ID for reference by other functions or NULL in case of error.
|
||||
osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);
|
||||
|
||||
/// Get name of an Event Flags object.
|
||||
/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
|
||||
/// \return name as NULL terminated string.
|
||||
const char *osEventFlagsGetName (osEventFlagsId_t ef_id);
|
||||
|
||||
/// Set the specified Event Flags.
|
||||
/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
|
||||
/// \param[in] flags specifies the flags that shall be set.
|
||||
/// \return event flags after setting or error code if highest bit set.
|
||||
uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);
|
||||
|
||||
/// Clear the specified Event Flags.
|
||||
/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
|
||||
/// \param[in] flags specifies the flags that shall be cleared.
|
||||
/// \return event flags before clearing or error code if highest bit set.
|
||||
uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);
|
||||
|
||||
/// Get the current Event Flags.
|
||||
/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
|
||||
/// \return current event flags.
|
||||
uint32_t osEventFlagsGet (osEventFlagsId_t ef_id);
|
||||
|
||||
/// Wait for one or more Event Flags to become signaled.
|
||||
/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
|
||||
/// \param[in] flags specifies the flags to wait for.
|
||||
/// \param[in] options specifies flags options (osFlagsXxxx).
|
||||
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return event flags before clearing or error code if highest bit set.
|
||||
uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
|
||||
|
||||
/// Delete an Event Flags object.
|
||||
/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);
|
||||
|
||||
|
||||
// ==== Mutex Management Functions ====
|
||||
|
||||
/// Create and Initialize a Mutex object.
|
||||
/// \param[in] attr mutex attributes; NULL: default values.
|
||||
/// \return mutex ID for reference by other functions or NULL in case of error.
|
||||
osMutexId_t osMutexNew (const osMutexAttr_t *attr);
|
||||
|
||||
/// Get name of a Mutex object.
|
||||
/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
|
||||
/// \return name as NULL terminated string.
|
||||
const char *osMutexGetName (osMutexId_t mutex_id);
|
||||
|
||||
/// Acquire a Mutex or timeout if it is locked.
|
||||
/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
|
||||
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);
|
||||
|
||||
/// Release a Mutex that was acquired by \ref osMutexAcquire.
|
||||
/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osMutexRelease (osMutexId_t mutex_id);
|
||||
|
||||
/// Get Thread which owns a Mutex object.
|
||||
/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
|
||||
/// \return thread ID of owner thread or NULL when mutex was not acquired.
|
||||
osThreadId_t osMutexGetOwner (osMutexId_t mutex_id);
|
||||
|
||||
/// Delete a Mutex object.
|
||||
/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osMutexDelete (osMutexId_t mutex_id);
|
||||
|
||||
|
||||
// ==== Semaphore Management Functions ====
|
||||
|
||||
/// Create and Initialize a Semaphore object.
|
||||
/// \param[in] max_count maximum number of available tokens.
|
||||
/// \param[in] initial_count initial number of available tokens.
|
||||
/// \param[in] attr semaphore attributes; NULL: default values.
|
||||
/// \return semaphore ID for reference by other functions or NULL in case of error.
|
||||
osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
|
||||
|
||||
/// Get name of a Semaphore object.
|
||||
/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
|
||||
/// \return name as NULL terminated string.
|
||||
const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);
|
||||
|
||||
/// Acquire a Semaphore token or timeout if no tokens are available.
|
||||
/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
|
||||
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
|
||||
|
||||
/// Release a Semaphore token up to the initial maximum count.
|
||||
/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);
|
||||
|
||||
/// Get current Semaphore token count.
|
||||
/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
|
||||
/// \return number of tokens available.
|
||||
uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);
|
||||
|
||||
/// Delete a Semaphore object.
|
||||
/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);
|
||||
|
||||
|
||||
// ==== Memory Pool Management Functions ====
|
||||
|
||||
/// Create and Initialize a Memory Pool object.
|
||||
/// \param[in] block_count maximum number of memory blocks in memory pool.
|
||||
/// \param[in] block_size memory block size in bytes.
|
||||
/// \param[in] attr memory pool attributes; NULL: default values.
|
||||
/// \return memory pool ID for reference by other functions or NULL in case of error.
|
||||
osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);
|
||||
|
||||
/// Get name of a Memory Pool object.
|
||||
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
|
||||
/// \return name as NULL terminated string.
|
||||
const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);
|
||||
|
||||
/// Allocate a memory block from a Memory Pool.
|
||||
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
|
||||
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return address of the allocated memory block or NULL in case of no memory is available.
|
||||
void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);
|
||||
|
||||
/// Return an allocated memory block back to a Memory Pool.
|
||||
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
|
||||
/// \param[in] block address of the allocated memory block to be returned to the memory pool.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);
|
||||
|
||||
/// Get maximum number of memory blocks in a Memory Pool.
|
||||
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
|
||||
/// \return maximum number of memory blocks.
|
||||
uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);
|
||||
|
||||
/// Get memory block size in a Memory Pool.
|
||||
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
|
||||
/// \return memory block size in bytes.
|
||||
uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);
|
||||
|
||||
/// Get number of memory blocks used in a Memory Pool.
|
||||
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
|
||||
/// \return number of memory blocks used.
|
||||
uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);
|
||||
|
||||
/// Get number of memory blocks available in a Memory Pool.
|
||||
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
|
||||
/// \return number of memory blocks available.
|
||||
uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);
|
||||
|
||||
/// Delete a Memory Pool object.
|
||||
/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);
|
||||
|
||||
|
||||
// ==== Message Queue Management Functions ====
|
||||
|
||||
/// Create and Initialize a Message Queue object.
|
||||
/// \param[in] msg_count maximum number of messages in queue.
|
||||
/// \param[in] msg_size maximum message size in bytes.
|
||||
/// \param[in] attr message queue attributes; NULL: default values.
|
||||
/// \return message queue ID for reference by other functions or NULL in case of error.
|
||||
osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
|
||||
|
||||
/// Get name of a Message Queue object.
|
||||
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
|
||||
/// \return name as NULL terminated string.
|
||||
const char *osMessageQueueGetName (osMessageQueueId_t mq_id);
|
||||
|
||||
/// Put a Message into a Queue or timeout if Queue is full.
|
||||
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
|
||||
/// \param[in] msg_ptr pointer to buffer with message to put into a queue.
|
||||
/// \param[in] msg_prio message priority.
|
||||
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);
|
||||
|
||||
/// Get a Message from a Queue or timeout if Queue is empty.
|
||||
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
|
||||
/// \param[out] msg_ptr pointer to buffer for message to get from a queue.
|
||||
/// \param[out] msg_prio pointer to buffer for message priority or NULL.
|
||||
/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
|
||||
|
||||
/// Get maximum number of messages in a Message Queue.
|
||||
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
|
||||
/// \return maximum number of messages.
|
||||
uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);
|
||||
|
||||
/// Get maximum message size in a Memory Pool.
|
||||
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
|
||||
/// \return maximum message size in bytes.
|
||||
uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);
|
||||
|
||||
/// Get number of queued messages in a Message Queue.
|
||||
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
|
||||
/// \return number of queued messages.
|
||||
uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);
|
||||
|
||||
/// Get number of available slots for messages in a Message Queue.
|
||||
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
|
||||
/// \return number of available slots for messages.
|
||||
uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);
|
||||
|
||||
/// Reset a Message Queue to initial empty state.
|
||||
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);
|
||||
|
||||
/// Delete a Message Queue object.
|
||||
/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
|
||||
/// \return status code that indicates the execution status of the function.
|
||||
osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // CMSIS_OS2_H_
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
{
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
//
|
||||
// Created by CFIF on 23.11.22.
|
||||
//
|
||||
|
||||
#include "CmsisRtosThreadUtils.h"
|
||||
|
||||
void InitThreadAtr(
|
||||
osThreadAttr_t *attr,
|
||||
const char *name, ///< name of the thread
|
||||
|
||||
void *cb_mem, ///< memory for control block
|
||||
uint32_t cb_size, ///< size of provided memory for control block
|
||||
|
||||
void *stack_mem, ///< memory for stack
|
||||
uint32_t stack_size, ///< size of stack
|
||||
|
||||
osPriority_t priority ///< initial thread priority (default: osPriorityNormal)
|
||||
) {
|
||||
|
||||
attr->name = name;
|
||||
|
||||
attr->cb_mem = cb_mem;
|
||||
attr->cb_size = cb_size;
|
||||
|
||||
attr->stack_mem = stack_mem;
|
||||
attr->stack_size = stack_size;
|
||||
|
||||
attr->priority = priority;
|
||||
|
||||
attr->tz_module = 0;
|
||||
attr->reserved = 0;
|
||||
}
|
||||
|
||||
void InitQueueAtr(
|
||||
osMessageQueueAttr_t *attr,
|
||||
const char *name, ///< name of the thread
|
||||
|
||||
void *cb_mem, ///< memory for control block
|
||||
uint32_t cb_size, ///< size of provided memory for control block
|
||||
|
||||
void *mem, ///< memory for data
|
||||
uint32_t mem_size ///< size of mem
|
||||
) {
|
||||
|
||||
attr->name = name;
|
||||
|
||||
attr->cb_mem = cb_mem;
|
||||
attr->cb_size = cb_size;
|
||||
|
||||
attr->mq_mem = mem;
|
||||
attr->mq_size = mem_size;
|
||||
}
|
||||
|
||||
void utils_thread_block_start(void *env, osThreadId_t *id, osThreadAttr_t *attr, osThreadFunc_t func) {
|
||||
if (!*id) {
|
||||
*id = osThreadNew((osThreadFunc_t) func, (void *) (env), attr);
|
||||
} else {
|
||||
osThreadResume(*id);
|
||||
}
|
||||
}
|
||||
|
||||
void utils_thread_block_pause(osThreadId_t id) {
|
||||
if (id) {
|
||||
osThreadSuspend(id);
|
||||
}
|
||||
}
|
||||
|
||||
void utils_thread_block_stop(osThreadId_t *id) {
|
||||
if (*id) {
|
||||
if (osThreadTerminate(*id) == osOK) {
|
||||
*id = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
//
|
||||
// Created by CFIF on 08.09.22.
|
||||
//
|
||||
|
||||
#ifndef CMSISRTOSTHREADSUTILS_CMSISRTOSTHREADSUTILS_H
|
||||
#define CMSISRTOSTHREADSUTILS_CMSISRTOSTHREADSUTILS_H
|
||||
|
||||
#include "cmsis_os.h"
|
||||
|
||||
typedef struct {
|
||||
osThreadId_t id;
|
||||
StaticTask_t controlBlock;
|
||||
} tThreadData;
|
||||
|
||||
#define tStaticThreadBlock(WORDS_LEN) struct { osThreadId_t id; osThreadAttr_t attr; StaticTask_t controlBlock; uint32_t stack[WORDS_LEN]; }
|
||||
#define tStaticThreadDynBlock struct { osThreadId_t id; osThreadAttr_t attr; }
|
||||
|
||||
#define THREAD_ATTR_CREATE(PRIORITY, TASK_NAME) osThreadAttr_t TASK_NAME##TaskAttr ={ \
|
||||
.name = #TASK_NAME, \
|
||||
.cb_mem = &threads.TASK_NAME.controlBlock, \
|
||||
.cb_size = sizeof(threads.TASK_NAME.controlBlock), \
|
||||
\
|
||||
.stack_mem = &threadsBuffers.TASK_NAME[0], \
|
||||
.stack_size = sizeof(threadsBuffers.TASK_NAME), \
|
||||
\
|
||||
.priority = (osPriority_t) (PRIORITY) \
|
||||
}
|
||||
|
||||
#define THREAD_ADD(THREAD_NAME, ENV, FUNC) threads.THREAD_NAME.id = osThreadNew((osThreadFunc_t)(FUNC), (void *) (ENV), &THREAD_NAME##TaskAttr)
|
||||
|
||||
|
||||
void InitThreadAtr(
|
||||
osThreadAttr_t *attr,
|
||||
const char *name, ///< name of the thread
|
||||
|
||||
void *cb_mem, ///< memory for control block
|
||||
uint32_t cb_size, ///< size of provided memory for control block
|
||||
|
||||
void *stack_mem, ///< memory for stack
|
||||
uint32_t stack_size, ///< size of stack
|
||||
|
||||
osPriority_t priority ///< initial thread priority (default: osPriorityNormal)
|
||||
);
|
||||
|
||||
void InitQueueAtr(
|
||||
osMessageQueueAttr_t *attr,
|
||||
const char *name, ///< name of the thread
|
||||
|
||||
void *cb_mem, ///< memory for control block
|
||||
uint32_t cb_size, ///< size of provided memory for control block
|
||||
|
||||
void *mem, ///< memory for data
|
||||
uint32_t mem_size ///< size of mem
|
||||
);
|
||||
|
||||
#define InitThreadAtrStatic(ATTR, NAME, CB, STACK, PRIOR) InitThreadAtr(ATTR,NAME,&CB,sizeof(CB),STACK,sizeof(STACK),PRIOR)
|
||||
#define InitQueueAtrStatic(ATTR, NAME, CB, MEM) InitQueueAtr(ATTR,NAME,&CB,sizeof(CB),MEM,sizeof(MEM))
|
||||
|
||||
#define InitThreadBlock(BLOCK, NAME, PRIOR) (BLOCK).id = 0; InitThreadAtr(&(BLOCK).attr,NAME,&(BLOCK).controlBlock,sizeof((BLOCK).controlBlock),(BLOCK).stack,sizeof((BLOCK).stack),PRIOR)
|
||||
#define InitThreadDynBlock(BLOCK, NAME, STACK, PRIOR) (BLOCK).id = 0; InitThreadAtr(&(BLOCK).attr,NAME,NULL,0,NULL,STACK,PRIOR)
|
||||
|
||||
|
||||
void utils_thread_block_start(void *env, osThreadId_t *id, osThreadAttr_t *attr, osThreadFunc_t func);
|
||||
|
||||
void utils_thread_block_pause(osThreadId_t id);
|
||||
|
||||
void utils_thread_block_stop(osThreadId_t *id);
|
||||
|
||||
#define ThreadBlock_Start(THREAD, ENV, FUNC) utils_thread_block_start(ENV,&(THREAD).id,&(THREAD).attr, (osThreadFunc_t)(FUNC))
|
||||
#define ThreadBlock_Pause(THREAD) utils_thread_block_pause((THREAD).id)
|
||||
#define ThreadBlock_Stop(THREAD) utils_thread_block_stop(&(THREAD).id)
|
||||
|
||||
|
||||
#define PinThreadToCore(BLOCK, CORE) (BLOCK).attr.pinToCore = 1; (BLOCK).attr.core = CORE
|
||||
#endif //CMSISRTOSTHREADSUTILS_CMSISRTOSTHREADSUTILS_H
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
{
|
||||
"dep": [
|
||||
{
|
||||
"type": "local",
|
||||
|
||||
"dir": "./MODULES/CmsisRtosInterface"
|
||||
}
|
||||
],
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"./"
|
||||
],
|
||||
"srcs": [
|
||||
"./*.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
#ifndef _DEVICE_CM7_ARM_CORTEXM7_ASM_H_
|
||||
#define _DEVICE_CM7_ARM_CORTEXM7_ASM_H_
|
||||
|
||||
|
||||
/** \brief Reverse byte order in a word.
|
||||
*/
|
||||
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION)
|
||||
#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a))
|
||||
#else
|
||||
#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \
|
||||
| ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U))
|
||||
#endif
|
||||
|
||||
/** \brief Enter low-power standby state
|
||||
* WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts.
|
||||
*/
|
||||
#if defined (__GNUC__)
|
||||
#define STANDBY() __asm volatile ("wfi")
|
||||
#else
|
||||
#define STANDBY() __asm("wfi")
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,865 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,271 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include "cmsis_iccarm.h"
|
||||
|
||||
/*
|
||||
* GHS Compiler
|
||||
*/
|
||||
#elif defined ( __ghs__ )
|
||||
#include "cmsis_ghs.h"
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,104 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_ghs.h
|
||||
* @brief CMSIS compiler GHS header file
|
||||
* @version V5.0.4
|
||||
* @date 09. April 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_GHS_H
|
||||
#define __CMSIS_GHS_H
|
||||
/* GHS MULTI intrinsic functions (e.g. __enable_interrupt()) */
|
||||
#include <arm_ghs.h>
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT restrict
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#endif
|
||||
#ifndef __DMB
|
||||
#define __DMB() __ASM("dmb")
|
||||
#endif
|
||||
#ifndef __DSB
|
||||
#define __DSB() __ASM("dsb")
|
||||
#endif
|
||||
#ifndef __ISB
|
||||
#define __ISB() __ASM("isb")
|
||||
#endif
|
||||
#ifndef __WFI
|
||||
#define __WFI() __ASM("wfi")
|
||||
#endif
|
||||
#ifndef __WFE
|
||||
#define __WFE() __ASM("wfe")
|
||||
#endif
|
||||
#ifndef __enable_irq
|
||||
#define __enable_irq() __ASM("cpsie i")
|
||||
#endif
|
||||
#ifndef __disable_irq
|
||||
#define __disable_irq() __ASM("cpsid i")
|
||||
#endif
|
||||
#ifndef __get_FPSCR
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
return __VMRS(__VFP_FPSCR);;
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_GHS_H */
|
||||
|
|
@ -0,0 +1,935 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_iccarm.h
|
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||
* @version V5.0.7
|
||||
* @date 19. June 2018
|
||||
******************************************************************************/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2018 IAR Systems
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#ifndef __CMSIS_ICCARM_H__
|
||||
#define __CMSIS_ICCARM_H__
|
||||
|
||||
#ifndef __ICCARM__
|
||||
#error This file should only be compiled by ICCARM
|
||||
#endif
|
||||
|
||||
#pragma system_include
|
||||
|
||||
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||
|
||||
#if (__VER__ >= 8000000)
|
||||
#define __ICCARM_V8 1
|
||||
#else
|
||||
#define __ICCARM_V8 0
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGNED
|
||||
#if __ICCARM_V8
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#elif (__VER__ >= 7080000)
|
||||
/* Needs IAR language extensions */
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#else
|
||||
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/
|
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||
/* Macros already defined */
|
||||
#else
|
||||
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||
#if __ARM_ARCH == 6
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif __ARM_ARCH == 7
|
||||
#if __ARM_FEATURE_DSP
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#else
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#endif /* __ARM_ARCH */
|
||||
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||
#endif
|
||||
|
||||
/* Alternativ core deduction for older ICCARM's */
|
||||
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#else
|
||||
#error "Unknown target."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#else
|
||||
#define __IAR_M0_FAMILY 0
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#if __ICCARM_V8
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#else
|
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_STRUCT
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_UNION
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#ifndef __FORCEINLINE
|
||||
#define __FORCEINLINE _Pragma("inline=forced")
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint16_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||
{
|
||||
*(__packed uint16_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint32_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||
{
|
||||
*(__packed uint32_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__packed struct __iar_u32 { uint32_t v; };
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||
#endif
|
||||
|
||||
#ifndef __USED
|
||||
#if __ICCARM_V8
|
||||
#define __USED __attribute__((used))
|
||||
#else
|
||||
#define __USED _Pragma("__root")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#if __ICCARM_V8
|
||||
#define __WEAK __attribute__((weak))
|
||||
#else
|
||||
#define __WEAK _Pragma("__weak")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||
#endif
|
||||
|
||||
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||
|
||||
#if defined(__CLZ)
|
||||
#undef __CLZ
|
||||
#endif
|
||||
#if defined(__REVSH)
|
||||
#undef __REVSH
|
||||
#endif
|
||||
#if defined(__RBIT)
|
||||
#undef __RBIT
|
||||
#endif
|
||||
#if defined(__SSAT)
|
||||
#undef __SSAT
|
||||
#endif
|
||||
#if defined(__USAT)
|
||||
#undef __USAT
|
||||
#endif
|
||||
|
||||
#include "iccarm_builtin.h"
|
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||
#define __disable_irq __iar_builtin_disable_interrupt
|
||||
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||
#define __enable_irq __iar_builtin_enable_interrupt
|
||||
#define __arm_rsr __iar_builtin_rsr
|
||||
#define __arm_wsr __iar_builtin_wsr
|
||||
|
||||
|
||||
#define __get_APSR() (__arm_rsr("APSR"))
|
||||
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||
#else
|
||||
#define __get_FPSCR() ( 0 )
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||
#define __get_MSP() (__arm_rsr("MSP"))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __get_MSPLIM() (0U)
|
||||
#else
|
||||
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||
#endif
|
||||
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||
#define __get_PSP() (__arm_rsr("PSP"))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __get_PSPLIM() (0U)
|
||||
#else
|
||||
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||
#endif
|
||||
|
||||
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||
|
||||
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||
#endif
|
||||
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __TZ_get_PSPLIM_NS() (0U)
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||
|
||||
#define __NOP __iar_builtin_no_operation
|
||||
|
||||
#define __CLZ __iar_builtin_CLZ
|
||||
#define __CLREX __iar_builtin_CLREX
|
||||
|
||||
#define __DMB __iar_builtin_DMB
|
||||
#define __DSB __iar_builtin_DSB
|
||||
#define __ISB __iar_builtin_ISB
|
||||
|
||||
#define __LDREXB __iar_builtin_LDREXB
|
||||
#define __LDREXH __iar_builtin_LDREXH
|
||||
#define __LDREXW __iar_builtin_LDREX
|
||||
|
||||
#define __RBIT __iar_builtin_RBIT
|
||||
#define __REV __iar_builtin_REV
|
||||
#define __REV16 __iar_builtin_REV16
|
||||
|
||||
__IAR_FT int16_t __REVSH(int16_t val)
|
||||
{
|
||||
return (int16_t) __iar_builtin_REVSH(val);
|
||||
}
|
||||
|
||||
#define __ROR __iar_builtin_ROR
|
||||
#define __RRX __iar_builtin_RRX
|
||||
|
||||
#define __SEV __iar_builtin_SEV
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __SSAT __iar_builtin_SSAT
|
||||
#endif
|
||||
|
||||
#define __STREXB __iar_builtin_STREXB
|
||||
#define __STREXH __iar_builtin_STREXH
|
||||
#define __STREXW __iar_builtin_STREX
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __USAT __iar_builtin_USAT
|
||||
#endif
|
||||
|
||||
#define __WFE __iar_builtin_WFE
|
||||
#define __WFI __iar_builtin_WFI
|
||||
|
||||
#if __ARM_MEDIA__
|
||||
#define __SADD8 __iar_builtin_SADD8
|
||||
#define __QADD8 __iar_builtin_QADD8
|
||||
#define __SHADD8 __iar_builtin_SHADD8
|
||||
#define __UADD8 __iar_builtin_UADD8
|
||||
#define __UQADD8 __iar_builtin_UQADD8
|
||||
#define __UHADD8 __iar_builtin_UHADD8
|
||||
#define __SSUB8 __iar_builtin_SSUB8
|
||||
#define __QSUB8 __iar_builtin_QSUB8
|
||||
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||
#define __USUB8 __iar_builtin_USUB8
|
||||
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||
#define __SADD16 __iar_builtin_SADD16
|
||||
#define __QADD16 __iar_builtin_QADD16
|
||||
#define __SHADD16 __iar_builtin_SHADD16
|
||||
#define __UADD16 __iar_builtin_UADD16
|
||||
#define __UQADD16 __iar_builtin_UQADD16
|
||||
#define __UHADD16 __iar_builtin_UHADD16
|
||||
#define __SSUB16 __iar_builtin_SSUB16
|
||||
#define __QSUB16 __iar_builtin_QSUB16
|
||||
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||
#define __USUB16 __iar_builtin_USUB16
|
||||
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||
#define __SASX __iar_builtin_SASX
|
||||
#define __QASX __iar_builtin_QASX
|
||||
#define __SHASX __iar_builtin_SHASX
|
||||
#define __UASX __iar_builtin_UASX
|
||||
#define __UQASX __iar_builtin_UQASX
|
||||
#define __UHASX __iar_builtin_UHASX
|
||||
#define __SSAX __iar_builtin_SSAX
|
||||
#define __QSAX __iar_builtin_QSAX
|
||||
#define __SHSAX __iar_builtin_SHSAX
|
||||
#define __USAX __iar_builtin_USAX
|
||||
#define __UQSAX __iar_builtin_UQSAX
|
||||
#define __UHSAX __iar_builtin_UHSAX
|
||||
#define __USAD8 __iar_builtin_USAD8
|
||||
#define __USADA8 __iar_builtin_USADA8
|
||||
#define __SSAT16 __iar_builtin_SSAT16
|
||||
#define __USAT16 __iar_builtin_USAT16
|
||||
#define __UXTB16 __iar_builtin_UXTB16
|
||||
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||
#define __SXTB16 __iar_builtin_SXTB16
|
||||
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||
#define __SMUAD __iar_builtin_SMUAD
|
||||
#define __SMUADX __iar_builtin_SMUADX
|
||||
#define __SMMLA __iar_builtin_SMMLA
|
||||
#define __SMLAD __iar_builtin_SMLAD
|
||||
#define __SMLADX __iar_builtin_SMLADX
|
||||
#define __SMLALD __iar_builtin_SMLALD
|
||||
#define __SMLALDX __iar_builtin_SMLALDX
|
||||
#define __SMUSD __iar_builtin_SMUSD
|
||||
#define __SMUSDX __iar_builtin_SMUSDX
|
||||
#define __SMLSD __iar_builtin_SMLSD
|
||||
#define __SMLSDX __iar_builtin_SMLSDX
|
||||
#define __SMLSLD __iar_builtin_SMLSLD
|
||||
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||
#define __SEL __iar_builtin_SEL
|
||||
#define __QADD __iar_builtin_QADD
|
||||
#define __QSUB __iar_builtin_QSUB
|
||||
#define __PKHBT __iar_builtin_PKHBT
|
||||
#define __PKHTB __iar_builtin_PKHTB
|
||||
#endif
|
||||
|
||||
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#define __CLZ __cmsis_iar_clz_not_active
|
||||
#define __SSAT __cmsis_iar_ssat_not_active
|
||||
#define __USAT __cmsis_iar_usat_not_active
|
||||
#define __RBIT __cmsis_iar_rbit_not_active
|
||||
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||
#endif
|
||||
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||
#endif
|
||||
|
||||
#ifdef __INTRINSICS_INCLUDED
|
||||
#error intrinsics.h is already included previously!
|
||||
#endif
|
||||
|
||||
#include <intrinsics.h>
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#undef __CLZ
|
||||
#undef __SSAT
|
||||
#undef __USAT
|
||||
#undef __RBIT
|
||||
#undef __get_APSR
|
||||
|
||||
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0U) { return 32U; }
|
||||
|
||||
uint32_t count = 0U;
|
||||
uint32_t mask = 0x80000000U;
|
||||
|
||||
while ((data & mask) == 0U)
|
||||
{
|
||||
count += 1U;
|
||||
mask = mask >> 1U;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||
{
|
||||
uint8_t sc = 31U;
|
||||
uint32_t r = v;
|
||||
for (v >>= 1U; v; v >>= 1U)
|
||||
{
|
||||
r <<= 1U;
|
||||
r |= v & 1U;
|
||||
sc--;
|
||||
}
|
||||
return (r << sc);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm("MRS %0,APSR" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#undef __get_FPSCR
|
||||
#undef __set_FPSCR
|
||||
#define __get_FPSCR() (0)
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
#pragma diag_suppress=Pe177
|
||||
|
||||
#define __enable_irq __enable_interrupt
|
||||
#define __disable_irq __disable_interrupt
|
||||
#define __NOP __no_operation
|
||||
|
||||
#define __get_xPSR __get_PSR
|
||||
|
||||
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||
{
|
||||
return __LDREX((unsigned long *)ptr);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||
{
|
||||
return __STREX(value, (unsigned long *)ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||
return(result);
|
||||
}
|
||||
|
||||
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||
}
|
||||
|
||||
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||
}
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
|
||||
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
|
||||
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#undef __IAR_FT
|
||||
#undef __IAR_M0_FAMILY
|
||||
#undef __ICCARM_V8
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
#pragma diag_default=Pe177
|
||||
|
||||
#endif /* __CMSIS_ICCARM_H__ */
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,275 @@
|
|||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.2
|
||||
* @date 25. May 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/**
|
||||
* @file compiler.h
|
||||
* @author Flagchip
|
||||
* @brief compiler define
|
||||
* @version 0.1.1
|
||||
* @date 2024-01-12
|
||||
*
|
||||
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
|
||||
*
|
||||
*/
|
||||
#ifndef DEVICE_COMPILER_H_
|
||||
#define DEVICE_COMPILER_H_
|
||||
|
||||
|
||||
#ifndef __IO
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (__GNUC__)
|
||||
#define INLINE __attribute__((always_inline)) inline
|
||||
#define LOCAL_INLINE __attribute__((always_inline)) static inline
|
||||
|
||||
#else
|
||||
#define INLINE inline
|
||||
#define LOCAL_INLINE static inline
|
||||
|
||||
#endif
|
||||
|
||||
#if (defined(__ICCARM__))
|
||||
#define STRINGIZE(x) #x
|
||||
#define ALIGN(n) _Pragma(STRINGIZE(data_alignment=(n)))
|
||||
#define PACKED __packed
|
||||
#endif
|
||||
|
||||
#if (defined(__GNUC__))
|
||||
#define ALIGN(n) __attribute__ ((aligned (n)))
|
||||
#define PACKED __packed
|
||||
#endif
|
||||
|
||||
#if (defined(__ghs__))
|
||||
#define INLINE inline
|
||||
#define LOCAL_INLINE static inline
|
||||
#define ALIGN(n) __attribute__((aligned(n)))
|
||||
#define PCAKED __attribute__((packed))
|
||||
#endif
|
||||
|
||||
#endif /* DEVICE_COMPILER_H_ */
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/**
|
||||
* @file device_header.h
|
||||
* @author Flagchip
|
||||
* @brief include all peripheral register files
|
||||
* @version 0.1.0
|
||||
* @date 2024-01-12
|
||||
*
|
||||
* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
|
||||
*
|
||||
*/
|
||||
#ifndef DEVICE_HEADER_H
|
||||
#define DEVICE_HEADER_H
|
||||
|
||||
#define __FPU_PRESENT 1
|
||||
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
|
||||
#define __ICACHE_PRESENT 1U
|
||||
#define __DCACHE_PRESENT 1U
|
||||
|
||||
#include <stdarg.h>
|
||||
|
||||
#include "typedef.h"
|
||||
#include "v_def.h"
|
||||
|
||||
#include "fcmath.h"
|
||||
#include "fcfunc.h"
|
||||
#include "cmsis_compiler.h"
|
||||
#include "core_cm7_regs.h"
|
||||
#include "arm_cortex_m7_asm.h"
|
||||
#include "mpu_armv7.h"
|
||||
|
||||
#include "fc7240_acc_regs.h"
|
||||
#include "fc7240_adc_regs.h"
|
||||
#include "fc7240_aontimer_regs.h"
|
||||
#include "fc7240_cmp_regs.h"
|
||||
#include "fc7240_cmu_regs.h"
|
||||
#include "fc7240_cordic_regs.h"
|
||||
#include "fc7240_cpm_regs.h"
|
||||
#include "fc7240_crc_regs.h"
|
||||
#include "fc7240_csc0_regs.h"
|
||||
#include "fc7240_dmamux_regs.h"
|
||||
#include "fc7240_dma_regs.h"
|
||||
#include "fc7240_eim_regs.h"
|
||||
#include "fc7240_erm_regs.h"
|
||||
#include "fc7240_fciic_regs.h"
|
||||
#include "fc7240_fcpit_regs.h"
|
||||
#include "fc7240_fcsmu_regs.h"
|
||||
#include "fc7240_fcspi_regs.h"
|
||||
#include "fc7240_fcuart_regs.h"
|
||||
#include "fc7240_flexcan_regs.h"
|
||||
#include "fc7240_fmc_regs.h"
|
||||
#include "fc7240_freqm_regs.h"
|
||||
#include "fc7240_ftu_regs.h"
|
||||
#include "fc7240_gpio_regs.h"
|
||||
#include "fc7240_intm_regs.h"
|
||||
#include "fc7240_ism_regs.h"
|
||||
#include "fc7240_lu_regs.h"
|
||||
#include "fc7240_mam_regs.h"
|
||||
#include "fc7240_mb_regs.h"
|
||||
#include "fc7240_msc_regs.h"
|
||||
#include "fc7240_ahb_overlay_regs.h"
|
||||
#include "fc7240_pcc_regs.h"
|
||||
#include "fc7240_pmc_regs.h"
|
||||
#include "fc7240_port_regs.h"
|
||||
#include "fc7240_ptimer_regs.h"
|
||||
#include "fc7240_rgm_regs.h"
|
||||
#include "fc7240_rtc_regs.h"
|
||||
#include "fc7240_scg_regs.h"
|
||||
#include "fc7240_scm_regs.h"
|
||||
#include "fc7240_stcu_regs.h"
|
||||
#include "fc7240_sec_regs.h"
|
||||
#include "fc7240_sent_regs.h"
|
||||
#include "fc7240_smc_regs.h"
|
||||
#include "fc7240_stcu_regs.h"
|
||||
#include "fc7240_tmu_regs.h"
|
||||
#include "fc7240_tpu_e_regs.h"
|
||||
#include "fc7240_tpu_h_regs.h"
|
||||
#include "fc7240_trgsel_regs.h"
|
||||
#include "fc7240_tstmp_regs.h"
|
||||
#include "fc7240_wdog_regs.h"
|
||||
#include "fc7240_wku_regs.h"
|
||||
|
||||
|
||||
#define PFLASH_START 0x01000000U
|
||||
#define PFLASH_END 0x011FFFFFU
|
||||
|
||||
#define SRAM_START 0x21000000U
|
||||
#define SRAM_END 0x21017FFFU
|
||||
|
||||
|
||||
#define INLINE_FLASHDRIVER_RAM STD_OFF
|
||||
|
||||
#define WDOG0_RECONF_LOCK_DELAY_US 100U /* 100us */
|
||||
|
||||
|
||||
|
||||
#if (defined(__ICCARM__))
|
||||
|
||||
#define PROCESS_UNUSED_VAR(var) (var) = (var);
|
||||
|
||||
#elif defined __GNUC__
|
||||
#define PROCESS_UNUSED_VAR(var) (void)(var);
|
||||
|
||||
#elif defined __ghs__
|
||||
|
||||
#define PROCESS_UNUSED_VAR(var) (void)(var);
|
||||
#endif
|
||||
|
||||
|
||||
#define FC4150F512 0x01U
|
||||
#define FC4150F2M 0x02U
|
||||
#define FC7300HSM 0x03U
|
||||
#define FC7300CM7 0x04U
|
||||
#define FC7240HOST 0x05U
|
||||
#define FC7240FLEXCORE 0x06U
|
||||
#define DEVICE_TYPE FC7240HOST
|
||||
|
||||
#endif /* DEVICE_HEADER_H */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
import os
|
||||
import re
|
||||
import time
|
||||
|
||||
def Add_Include(filePath,name):
|
||||
fp = open(filePath)
|
||||
lines = []
|
||||
for line in fp:
|
||||
lines.append(line)
|
||||
fp.close()
|
||||
fp.close()
|
||||
|
||||
del lines[:2] #delete previous define DRIVER_xxx_H
|
||||
lines.insert(0, r'#ifndef _'+name.upper()+'_H_') #add in LINE+1
|
||||
lines.insert(1, r'#define _'+name.upper()+'_H_') #add in LINE+1
|
||||
lines.insert(2, r'#ifdef __cplusplus') #add in LINE+1
|
||||
lines.insert(3, r' extern "C" {') #add in LINE+1
|
||||
lines.insert(4, r'#endif') #add in LINE+1
|
||||
|
||||
lines.insert(len(lines)-1, r'#ifdef __cplusplus') #add in LINE+1
|
||||
lines.insert(len(lines)-1, r'}') #add in LINE+1
|
||||
lines.insert(len(lines)-1, r'#endif') #add in LINE+1
|
||||
|
||||
s = '\n'.join(lines)
|
||||
fp = open(filePath, 'w')
|
||||
fp.write(s)
|
||||
fp.close()
|
||||
|
||||
|
||||
if __name__=='__main__':
|
||||
path = os.getcwd()
|
||||
for filename in os.listdir(path):
|
||||
result1 = os.path.splitext(filename)
|
||||
#print(filename+', '+result1[0]+'\n')
|
||||
|
||||
if result1[1] == '.h' :
|
||||
oldname=filename
|
||||
print(filename[7:-9])
|
||||
#time.sleep()
|
||||
newname='fc7240_'+filename[7:-9].lower()+'_regs.h'
|
||||
os.rename(oldname,newname);
|
||||
result1 = os.path.splitext(newname)
|
||||
Add_Include(newname,result1[0])
|
||||
#print(newname+'\n')
|
||||
|
|
@ -0,0 +1,719 @@
|
|||
#ifndef _FC7240_ACC_NU_Tztufn3_REGS_H_
|
||||
#define _FC7240_ACC_NU_Tztufn3_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- ACC Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup ACC_Peripheral_Access_Layer ACC Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** ACC - Size of Registers Arrays */
|
||||
|
||||
|
||||
|
||||
/** ACC - Register Layout Typedef */
|
||||
|
||||
#define ACC_IEBR_COUNT 2
|
||||
|
||||
#define ACC_DEBR_COUNT 2
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
uint8_t RESERVED_0[20];
|
||||
|
||||
__IO uint32_t CCR ; /* Configuration and Control Register, offset: 0x14 */
|
||||
|
||||
uint8_t RESERVED_1[96];
|
||||
|
||||
__I uint32_t CLIDR ; /* Cache Level ID Register, offset: 0x78 */
|
||||
|
||||
__I uint32_t CTR ; /* Cache Type Register, offset: 0x7C */
|
||||
|
||||
__I uint32_t CCSIDR ; /* Cache Size ID Register, offset: 0x80 */
|
||||
|
||||
__IO uint32_t CSSELR ; /* Cache Size Selection Register, offset: 0x84 */
|
||||
|
||||
uint8_t RESERVED_2[456];
|
||||
|
||||
__O uint32_t ICIALLU ; /* I-cache Invalidate All to PoU Register, offset: 0x250 */
|
||||
|
||||
uint8_t RESERVED_3[4];
|
||||
|
||||
__O uint32_t ICIMVAU ; /* I-cache Invalidate by MVA to PoU Register, offset: 0x258 */
|
||||
|
||||
__O uint32_t DCIMVAC ; /* D-cache Invalidate by MVA to PoC Register, offset: 0x25C */
|
||||
|
||||
__O uint32_t DCISW ; /* D-cache Invalidate by Set-way Register, offset: 0x260 */
|
||||
|
||||
__O uint32_t DCCMVAU ; /* D-cache Clean by MVA to PoU Register, offset: 0x264 */
|
||||
|
||||
__O uint32_t DCCMVAC ; /* D-cache Clean by MVA to PoC Register, offset: 0x268 */
|
||||
|
||||
__O uint32_t DCCSW ; /* D-cache Clean by Set-way Register, offset: 0x26C */
|
||||
|
||||
__O uint32_t DCCIMVAC ; /* D-cache Clean and Invalidate by MVA to PoC Register, offset: 0x270 */
|
||||
|
||||
__O uint32_t DCCISW ; /* D-cache Clean and Invalidate by Set-way Register, offset: 0x274 */
|
||||
|
||||
uint8_t RESERVED_4[36];
|
||||
|
||||
__IO uint32_t CACR ; /* L1 Cache Control Register, offset: 0x29C */
|
||||
|
||||
uint8_t RESERVED_5[16];
|
||||
|
||||
__IO uint32_t IEBR[ACC_IEBR_COUNT] ; /* Instruction Error Bank Register, offset: 0x2b0 */
|
||||
|
||||
__IO uint32_t DEBR[ACC_DEBR_COUNT] ; /* Data Error Bank Register, offset: 0x2b8 */
|
||||
|
||||
|
||||
|
||||
} ACC_Type, *ACC_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the ACC module. */
|
||||
|
||||
#define ACC_INSTANCE_COUNT (1u)
|
||||
|
||||
|
||||
|
||||
/* ACC - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral ACC base address */
|
||||
|
||||
#define ACC_BASE (0xE000ED00u)
|
||||
|
||||
/** Peripheral ACC base pointer */
|
||||
|
||||
#define ACC ((ACC_Type *)ACC_BASE)
|
||||
|
||||
/** Array initializer of ACC peripheral base addresses */
|
||||
|
||||
#define ACC_BASE_ADDRS {ACC_BASE}
|
||||
|
||||
/** Array initializer of ACC peripheral base pointers */
|
||||
|
||||
#define ACC_BASE_PTRS {ACC}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the ACC module. */
|
||||
|
||||
//#define ACC_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the ACC module. */
|
||||
|
||||
//#define ACC_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the ACC peripheral type */
|
||||
|
||||
//#define ACC_IRQS {ACC_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- ACC Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup ACC_Register_Masks ACC Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* CCR Bit Fields */
|
||||
|
||||
#define ACC_CCR_BP_MASK 0x40000u
|
||||
|
||||
#define ACC_CCR_BP_SHIFT 18u
|
||||
|
||||
#define ACC_CCR_BP_WIDTH 1u
|
||||
|
||||
#define ACC_CCR_BP(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_BP_SHIFT))&ACC_CCR_BP_MASK)
|
||||
|
||||
#define ACC_CCR_IC_MASK 0x20000u
|
||||
|
||||
#define ACC_CCR_IC_SHIFT 17u
|
||||
|
||||
#define ACC_CCR_IC_WIDTH 1u
|
||||
|
||||
#define ACC_CCR_IC(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_IC_SHIFT))&ACC_CCR_IC_MASK)
|
||||
|
||||
#define ACC_CCR_DC_MASK 0x10000u
|
||||
|
||||
#define ACC_CCR_DC_SHIFT 16u
|
||||
|
||||
#define ACC_CCR_DC_WIDTH 1u
|
||||
|
||||
#define ACC_CCR_DC(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_DC_SHIFT))&ACC_CCR_DC_MASK)
|
||||
|
||||
#define ACC_CCR_STKALIGN_MASK 0x200u
|
||||
|
||||
#define ACC_CCR_STKALIGN_SHIFT 9u
|
||||
|
||||
#define ACC_CCR_STKALIGN_WIDTH 1u
|
||||
|
||||
#define ACC_CCR_STKALIGN(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_STKALIGN_SHIFT))&ACC_CCR_STKALIGN_MASK)
|
||||
|
||||
#define ACC_CCR_BFHFNMIGN_MASK 0x100u
|
||||
|
||||
#define ACC_CCR_BFHFNMIGN_SHIFT 8u
|
||||
|
||||
#define ACC_CCR_BFHFNMIGN_WIDTH 1u
|
||||
|
||||
#define ACC_CCR_BFHFNMIGN(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_BFHFNMIGN_SHIFT))&ACC_CCR_BFHFNMIGN_MASK)
|
||||
|
||||
#define ACC_CCR_DIV_0_TRP_MASK 0x10u
|
||||
|
||||
#define ACC_CCR_DIV_0_TRP_SHIFT 4u
|
||||
|
||||
#define ACC_CCR_DIV_0_TRP_WIDTH 1u
|
||||
|
||||
#define ACC_CCR_DIV_0_TRP(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_DIV_0_TRP_SHIFT))&ACC_CCR_DIV_0_TRP_MASK)
|
||||
|
||||
#define ACC_CCR_UNALIGN_TRP_MASK 0x8u
|
||||
|
||||
#define ACC_CCR_UNALIGN_TRP_SHIFT 3u
|
||||
|
||||
#define ACC_CCR_UNALIGN_TRP_WIDTH 1u
|
||||
|
||||
#define ACC_CCR_UNALIGN_TRP(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_UNALIGN_TRP_SHIFT))&ACC_CCR_UNALIGN_TRP_MASK)
|
||||
|
||||
#define ACC_CCR_USERSETMPEND_MASK 0x2u
|
||||
|
||||
#define ACC_CCR_USERSETMPEND_SHIFT 1u
|
||||
|
||||
#define ACC_CCR_USERSETMPEND_WIDTH 1u
|
||||
|
||||
#define ACC_CCR_USERSETMPEND(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_USERSETMPEND_SHIFT))&ACC_CCR_USERSETMPEND_MASK)
|
||||
|
||||
#define ACC_CCR_NONBASETHRDENA_MASK 0x1u
|
||||
|
||||
#define ACC_CCR_NONBASETHRDENA_SHIFT 0u
|
||||
|
||||
#define ACC_CCR_NONBASETHRDENA_WIDTH 1u
|
||||
|
||||
#define ACC_CCR_NONBASETHRDENA(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCR_NONBASETHRDENA_SHIFT))&ACC_CCR_NONBASETHRDENA_MASK)
|
||||
|
||||
/* CCR Reg Mask */
|
||||
|
||||
#define ACC_CCR_MASK 0x0007031Bu
|
||||
|
||||
|
||||
|
||||
/* CLIDR Bit Fields */
|
||||
|
||||
#define ACC_CLIDR_LOUU_MASK 0x38000000u
|
||||
|
||||
#define ACC_CLIDR_LOUU_SHIFT 27u
|
||||
|
||||
#define ACC_CLIDR_LOUU_WIDTH 3u
|
||||
|
||||
#define ACC_CLIDR_LOUU(x) (((uint32_t)(((uint32_t)(x))<<ACC_CLIDR_LOUU_SHIFT))&ACC_CLIDR_LOUU_MASK)
|
||||
|
||||
#define ACC_CLIDR_LOC_MASK 0x7000000u
|
||||
|
||||
#define ACC_CLIDR_LOC_SHIFT 24u
|
||||
|
||||
#define ACC_CLIDR_LOC_WIDTH 3u
|
||||
|
||||
#define ACC_CLIDR_LOC(x) (((uint32_t)(((uint32_t)(x))<<ACC_CLIDR_LOC_SHIFT))&ACC_CLIDR_LOC_MASK)
|
||||
|
||||
#define ACC_CLIDR_LOCT_MASK 0x7u
|
||||
|
||||
#define ACC_CLIDR_LOCT_SHIFT 0u
|
||||
|
||||
#define ACC_CLIDR_LOCT_WIDTH 3u
|
||||
|
||||
#define ACC_CLIDR_LOCT(x) (((uint32_t)(((uint32_t)(x))<<ACC_CLIDR_LOCT_SHIFT))&ACC_CLIDR_LOCT_MASK)
|
||||
|
||||
/* CLIDR Reg Mask */
|
||||
|
||||
#define ACC_CLIDR_MASK 0x3F000007u
|
||||
|
||||
|
||||
|
||||
/* CTR Bit Fields */
|
||||
|
||||
#define ACC_CTR_FMT_MASK 0xE0000000u
|
||||
|
||||
#define ACC_CTR_FMT_SHIFT 29u
|
||||
|
||||
#define ACC_CTR_FMT_WIDTH 3u
|
||||
|
||||
#define ACC_CTR_FMT(x) (((uint32_t)(((uint32_t)(x))<<ACC_CTR_FMT_SHIFT))&ACC_CTR_FMT_MASK)
|
||||
|
||||
#define ACC_CTR_CWG_MASK 0xF000000u
|
||||
|
||||
#define ACC_CTR_CWG_SHIFT 24u
|
||||
|
||||
#define ACC_CTR_CWG_WIDTH 4u
|
||||
|
||||
#define ACC_CTR_CWG(x) (((uint32_t)(((uint32_t)(x))<<ACC_CTR_CWG_SHIFT))&ACC_CTR_CWG_MASK)
|
||||
|
||||
#define ACC_CTR_ERG_MASK 0xF00000u
|
||||
|
||||
#define ACC_CTR_ERG_SHIFT 20u
|
||||
|
||||
#define ACC_CTR_ERG_WIDTH 4u
|
||||
|
||||
#define ACC_CTR_ERG(x) (((uint32_t)(((uint32_t)(x))<<ACC_CTR_ERG_SHIFT))&ACC_CTR_ERG_MASK)
|
||||
|
||||
#define ACC_CTR_DMINLINE_MASK 0xF0000u
|
||||
|
||||
#define ACC_CTR_DMINLINE_SHIFT 16u
|
||||
|
||||
#define ACC_CTR_DMINLINE_WIDTH 4u
|
||||
|
||||
#define ACC_CTR_DMINLINE(x) (((uint32_t)(((uint32_t)(x))<<ACC_CTR_DMINLINE_SHIFT))&ACC_CTR_DMINLINE_MASK)
|
||||
|
||||
#define ACC_CTR_IMINLINE_MASK 0xFu
|
||||
|
||||
#define ACC_CTR_IMINLINE_SHIFT 0u
|
||||
|
||||
#define ACC_CTR_IMINLINE_WIDTH 4u
|
||||
|
||||
#define ACC_CTR_IMINLINE(x) (((uint32_t)(((uint32_t)(x))<<ACC_CTR_IMINLINE_SHIFT))&ACC_CTR_IMINLINE_MASK)
|
||||
|
||||
/* CTR Reg Mask */
|
||||
|
||||
#define ACC_CTR_MASK 0xEFFF000Fu
|
||||
|
||||
|
||||
|
||||
/* CCSIDR Bit Fields */
|
||||
|
||||
#define ACC_CCSIDR_WT_MASK 0x80000000u
|
||||
|
||||
#define ACC_CCSIDR_WT_SHIFT 31u
|
||||
|
||||
#define ACC_CCSIDR_WT_WIDTH 1u
|
||||
|
||||
#define ACC_CCSIDR_WT(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_WT_SHIFT))&ACC_CCSIDR_WT_MASK)
|
||||
|
||||
#define ACC_CCSIDR_WB_MASK 0x40000000u
|
||||
|
||||
#define ACC_CCSIDR_WB_SHIFT 30u
|
||||
|
||||
#define ACC_CCSIDR_WB_WIDTH 1u
|
||||
|
||||
#define ACC_CCSIDR_WB(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_WB_SHIFT))&ACC_CCSIDR_WB_MASK)
|
||||
|
||||
#define ACC_CCSIDR_RA_MASK 0x20000000u
|
||||
|
||||
#define ACC_CCSIDR_RA_SHIFT 29u
|
||||
|
||||
#define ACC_CCSIDR_RA_WIDTH 1u
|
||||
|
||||
#define ACC_CCSIDR_RA(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_RA_SHIFT))&ACC_CCSIDR_RA_MASK)
|
||||
|
||||
#define ACC_CCSIDR_WA_MASK 0x10000000u
|
||||
|
||||
#define ACC_CCSIDR_WA_SHIFT 28u
|
||||
|
||||
#define ACC_CCSIDR_WA_WIDTH 1u
|
||||
|
||||
#define ACC_CCSIDR_WA(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_WA_SHIFT))&ACC_CCSIDR_WA_MASK)
|
||||
|
||||
#define ACC_CCSIDR_NUMSETS_MASK 0xFFFE000u
|
||||
|
||||
#define ACC_CCSIDR_NUMSETS_SHIFT 13u
|
||||
|
||||
#define ACC_CCSIDR_NUMSETS_WIDTH 15u
|
||||
|
||||
#define ACC_CCSIDR_NUMSETS(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_NUMSETS_SHIFT))&ACC_CCSIDR_NUMSETS_MASK)
|
||||
|
||||
#define ACC_CCSIDR_ASSOCIATIVITY_MASK 0x1FF8u
|
||||
|
||||
#define ACC_CCSIDR_ASSOCIATIVITY_SHIFT 3u
|
||||
|
||||
#define ACC_CCSIDR_ASSOCIATIVITY_WIDTH 10u
|
||||
|
||||
#define ACC_CCSIDR_ASSOCIATIVITY(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_ASSOCIATIVITY_SHIFT))&ACC_CCSIDR_ASSOCIATIVITY_MASK)
|
||||
|
||||
#define ACC_CCSIDR_LINESIZE_MASK 0x7u
|
||||
|
||||
#define ACC_CCSIDR_LINESIZE_SHIFT 0u
|
||||
|
||||
#define ACC_CCSIDR_LINESIZE_WIDTH 3u
|
||||
|
||||
#define ACC_CCSIDR_LINESIZE(x) (((uint32_t)(((uint32_t)(x))<<ACC_CCSIDR_LINESIZE_SHIFT))&ACC_CCSIDR_LINESIZE_MASK)
|
||||
|
||||
/* CCSIDR Reg Mask */
|
||||
|
||||
#define ACC_CCSIDR_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* CSSELR Bit Fields */
|
||||
|
||||
#define ACC_CSSELR_LEVEL_MASK 0xEu
|
||||
|
||||
#define ACC_CSSELR_LEVEL_SHIFT 1u
|
||||
|
||||
#define ACC_CSSELR_LEVEL_WIDTH 3u
|
||||
|
||||
#define ACC_CSSELR_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<ACC_CSSELR_LEVEL_SHIFT))&ACC_CSSELR_LEVEL_MASK)
|
||||
|
||||
#define ACC_CSSELR_IND_MASK 0x1u
|
||||
|
||||
#define ACC_CSSELR_IND_SHIFT 0u
|
||||
|
||||
#define ACC_CSSELR_IND_WIDTH 1u
|
||||
|
||||
#define ACC_CSSELR_IND(x) (((uint32_t)(((uint32_t)(x))<<ACC_CSSELR_IND_SHIFT))&ACC_CSSELR_IND_MASK)
|
||||
|
||||
/* CSSELR Reg Mask */
|
||||
|
||||
#define ACC_CSSELR_MASK 0x0000000Fu
|
||||
|
||||
|
||||
|
||||
/* ICIALLU Bit Fields */
|
||||
|
||||
#define ACC_ICIALLU_ICIALLU_MASK 0xFFFFFFFFu
|
||||
|
||||
#define ACC_ICIALLU_ICIALLU_SHIFT 0u
|
||||
|
||||
#define ACC_ICIALLU_ICIALLU_WIDTH 32u
|
||||
|
||||
#define ACC_ICIALLU_ICIALLU(x) (((uint32_t)(((uint32_t)(x))<<ACC_ICIALLU_ICIALLU_SHIFT))&ACC_ICIALLU_ICIALLU_MASK)
|
||||
|
||||
/* ICIALLU Reg Mask */
|
||||
|
||||
#define ACC_ICIALLU_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* ICIMVAU Bit Fields */
|
||||
|
||||
#define ACC_ICIMVAU_MVA_MASK 0xFFFFFFE0u
|
||||
|
||||
#define ACC_ICIMVAU_MVA_SHIFT 5u
|
||||
|
||||
#define ACC_ICIMVAU_MVA_WIDTH 27u
|
||||
|
||||
#define ACC_ICIMVAU_MVA(x) (((uint32_t)(((uint32_t)(x))<<ACC_ICIMVAU_MVA_SHIFT))&ACC_ICIMVAU_MVA_MASK)
|
||||
|
||||
/* ICIMVAU Reg Mask */
|
||||
|
||||
#define ACC_ICIMVAU_MASK 0xFFFFFFE0u
|
||||
|
||||
|
||||
|
||||
/* DCIMVAC Bit Fields */
|
||||
|
||||
#define ACC_DCIMVAC_MVA_MASK 0xFFFFFFE0u
|
||||
|
||||
#define ACC_DCIMVAC_MVA_SHIFT 5u
|
||||
|
||||
#define ACC_DCIMVAC_MVA_WIDTH 27u
|
||||
|
||||
#define ACC_DCIMVAC_MVA(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCIMVAC_MVA_SHIFT))&ACC_DCIMVAC_MVA_MASK)
|
||||
|
||||
/* DCIMVAC Reg Mask */
|
||||
|
||||
#define ACC_DCIMVAC_MASK 0xFFFFFFE0u
|
||||
|
||||
|
||||
|
||||
/* DCISW Bit Fields */
|
||||
|
||||
#define ACC_DCISW_WAY_MASK 0xC0000000u
|
||||
|
||||
#define ACC_DCISW_WAY_SHIFT 30u
|
||||
|
||||
#define ACC_DCISW_WAY_WIDTH 2u
|
||||
|
||||
#define ACC_DCISW_WAY(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCISW_WAY_SHIFT))&ACC_DCISW_WAY_MASK)
|
||||
|
||||
#define ACC_DCISW_SET_MASK 0x3FE0u
|
||||
|
||||
#define ACC_DCISW_SET_SHIFT 5u
|
||||
|
||||
#define ACC_DCISW_SET_WIDTH 9u
|
||||
|
||||
#define ACC_DCISW_SET(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCISW_SET_SHIFT))&ACC_DCISW_SET_MASK)
|
||||
|
||||
/* DCISW Reg Mask */
|
||||
|
||||
#define ACC_DCISW_MASK 0xC0003FE0u
|
||||
|
||||
|
||||
|
||||
/* DCCMVAU Bit Fields */
|
||||
|
||||
#define ACC_DCCMVAU_MVA_MASK 0xFFFFFFE0u
|
||||
|
||||
#define ACC_DCCMVAU_MVA_SHIFT 5u
|
||||
|
||||
#define ACC_DCCMVAU_MVA_WIDTH 27u
|
||||
|
||||
#define ACC_DCCMVAU_MVA(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCMVAU_MVA_SHIFT))&ACC_DCCMVAU_MVA_MASK)
|
||||
|
||||
/* DCCMVAU Reg Mask */
|
||||
|
||||
#define ACC_DCCMVAU_MASK 0xFFFFFFE0u
|
||||
|
||||
|
||||
|
||||
/* DCCMVAC Bit Fields */
|
||||
|
||||
#define ACC_DCCMVAC_MVA_MASK 0xFFFFFFE0u
|
||||
|
||||
#define ACC_DCCMVAC_MVA_SHIFT 5u
|
||||
|
||||
#define ACC_DCCMVAC_MVA_WIDTH 27u
|
||||
|
||||
#define ACC_DCCMVAC_MVA(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCMVAC_MVA_SHIFT))&ACC_DCCMVAC_MVA_MASK)
|
||||
|
||||
/* DCCMVAC Reg Mask */
|
||||
|
||||
#define ACC_DCCMVAC_MASK 0xFFFFFFE0u
|
||||
|
||||
|
||||
|
||||
/* DCCSW Bit Fields */
|
||||
|
||||
#define ACC_DCCSW_WAY_MASK 0xC0000000u
|
||||
|
||||
#define ACC_DCCSW_WAY_SHIFT 30u
|
||||
|
||||
#define ACC_DCCSW_WAY_WIDTH 2u
|
||||
|
||||
#define ACC_DCCSW_WAY(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCSW_WAY_SHIFT))&ACC_DCCSW_WAY_MASK)
|
||||
|
||||
#define ACC_DCCSW_SET_MASK 0x3FE0u
|
||||
|
||||
#define ACC_DCCSW_SET_SHIFT 5u
|
||||
|
||||
#define ACC_DCCSW_SET_WIDTH 9u
|
||||
|
||||
#define ACC_DCCSW_SET(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCSW_SET_SHIFT))&ACC_DCCSW_SET_MASK)
|
||||
|
||||
/* DCCSW Reg Mask */
|
||||
|
||||
#define ACC_DCCSW_MASK 0xC0003FE0u
|
||||
|
||||
|
||||
|
||||
/* DCCIMVAC Bit Fields */
|
||||
|
||||
#define ACC_DCCIMVAC_MVA_MASK 0xFFFFFFE0u
|
||||
|
||||
#define ACC_DCCIMVAC_MVA_SHIFT 5u
|
||||
|
||||
#define ACC_DCCIMVAC_MVA_WIDTH 27u
|
||||
|
||||
#define ACC_DCCIMVAC_MVA(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCIMVAC_MVA_SHIFT))&ACC_DCCIMVAC_MVA_MASK)
|
||||
|
||||
/* DCCIMVAC Reg Mask */
|
||||
|
||||
#define ACC_DCCIMVAC_MASK 0xFFFFFFE0u
|
||||
|
||||
|
||||
|
||||
/* DCCISW Bit Fields */
|
||||
|
||||
#define ACC_DCCISW_WAY_MASK 0xC0000000u
|
||||
|
||||
#define ACC_DCCISW_WAY_SHIFT 30u
|
||||
|
||||
#define ACC_DCCISW_WAY_WIDTH 2u
|
||||
|
||||
#define ACC_DCCISW_WAY(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCISW_WAY_SHIFT))&ACC_DCCISW_WAY_MASK)
|
||||
|
||||
#define ACC_DCCISW_SET_MASK 0x3FE0u
|
||||
|
||||
#define ACC_DCCISW_SET_SHIFT 5u
|
||||
|
||||
#define ACC_DCCISW_SET_WIDTH 9u
|
||||
|
||||
#define ACC_DCCISW_SET(x) (((uint32_t)(((uint32_t)(x))<<ACC_DCCISW_SET_SHIFT))&ACC_DCCISW_SET_MASK)
|
||||
|
||||
/* DCCISW Reg Mask */
|
||||
|
||||
#define ACC_DCCISW_MASK 0xC0003FE0u
|
||||
|
||||
|
||||
|
||||
/* CACR Bit Fields */
|
||||
|
||||
#define ACC_CACR_FORCEWT_MASK 0x4u
|
||||
|
||||
#define ACC_CACR_FORCEWT_SHIFT 2u
|
||||
|
||||
#define ACC_CACR_FORCEWT_WIDTH 1u
|
||||
|
||||
#define ACC_CACR_FORCEWT(x) (((uint32_t)(((uint32_t)(x))<<ACC_CACR_FORCEWT_SHIFT))&ACC_CACR_FORCEWT_MASK)
|
||||
|
||||
#define ACC_CACR_ECCDIS_MASK 0x2u
|
||||
|
||||
#define ACC_CACR_ECCDIS_SHIFT 1u
|
||||
|
||||
#define ACC_CACR_ECCDIS_WIDTH 1u
|
||||
|
||||
#define ACC_CACR_ECCDIS(x) (((uint32_t)(((uint32_t)(x))<<ACC_CACR_ECCDIS_SHIFT))&ACC_CACR_ECCDIS_MASK)
|
||||
|
||||
#define ACC_CACR_SIWT_MASK 0x1u
|
||||
|
||||
#define ACC_CACR_SIWT_SHIFT 0u
|
||||
|
||||
#define ACC_CACR_SIWT_WIDTH 1u
|
||||
|
||||
#define ACC_CACR_SIWT(x) (((uint32_t)(((uint32_t)(x))<<ACC_CACR_SIWT_SHIFT))&ACC_CACR_SIWT_MASK)
|
||||
|
||||
/* CACR Reg Mask */
|
||||
|
||||
#define ACC_CACR_MASK 0x00000007u
|
||||
|
||||
|
||||
|
||||
/* IEBR Bit Fields */
|
||||
|
||||
#define ACC_IEBR_TOE_MASK 0x20000u
|
||||
|
||||
#define ACC_IEBR_TOE_SHIFT 17u
|
||||
|
||||
#define ACC_IEBR_TOE_WIDTH 1u
|
||||
|
||||
#define ACC_IEBR_TOE(x) (((uint32_t)(((uint32_t)(x))<<ACC_IEBR_TOE_SHIFT))&ACC_IEBR_TOE_MASK)
|
||||
|
||||
#define ACC_IEBR_RB_MASK 0x10000u
|
||||
|
||||
#define ACC_IEBR_RB_SHIFT 16u
|
||||
|
||||
#define ACC_IEBR_RB_WIDTH 1u
|
||||
|
||||
#define ACC_IEBR_RB(x) (((uint32_t)(((uint32_t)(x))<<ACC_IEBR_RB_SHIFT))&ACC_IEBR_RB_MASK)
|
||||
|
||||
#define ACC_IEBR_RL_MASK 0xFFFCu
|
||||
|
||||
#define ACC_IEBR_RL_SHIFT 2u
|
||||
|
||||
#define ACC_IEBR_RL_WIDTH 14u
|
||||
|
||||
#define ACC_IEBR_RL(x) (((uint32_t)(((uint32_t)(x))<<ACC_IEBR_RL_SHIFT))&ACC_IEBR_RL_MASK)
|
||||
|
||||
#define ACC_IEBR_LOCKED_MASK 0x2u
|
||||
|
||||
#define ACC_IEBR_LOCKED_SHIFT 1u
|
||||
|
||||
#define ACC_IEBR_LOCKED_WIDTH 1u
|
||||
|
||||
#define ACC_IEBR_LOCKED(x) (((uint32_t)(((uint32_t)(x))<<ACC_IEBR_LOCKED_SHIFT))&ACC_IEBR_LOCKED_MASK)
|
||||
|
||||
#define ACC_IEBR_VALID_MASK 0x1u
|
||||
|
||||
#define ACC_IEBR_VALID_SHIFT 0u
|
||||
|
||||
#define ACC_IEBR_VALID_WIDTH 1u
|
||||
|
||||
#define ACC_IEBR_VALID(x) (((uint32_t)(((uint32_t)(x))<<ACC_IEBR_VALID_SHIFT))&ACC_IEBR_VALID_MASK)
|
||||
|
||||
/* IEBR0 Reg Mask */
|
||||
|
||||
#define ACC_IEBR_MASK 0x0003FFFFu
|
||||
|
||||
|
||||
|
||||
/* DEBR Bit Fields */
|
||||
|
||||
#define ACC_DEBR_TOE_MASK 0x20000u
|
||||
|
||||
#define ACC_DEBR_TOE_SHIFT 17u
|
||||
|
||||
#define ACC_DEBR_TOE_WIDTH 1u
|
||||
|
||||
#define ACC_DEBR_TOE(x) (((uint32_t)(((uint32_t)(x))<<ACC_DEBR_TOE_SHIFT))&ACC_DEBR_TOE_MASK)
|
||||
|
||||
#define ACC_DEBR_RB_MASK 0x10000u
|
||||
|
||||
#define ACC_DEBR_RB_SHIFT 16u
|
||||
|
||||
#define ACC_DEBR_RB_WIDTH 1u
|
||||
|
||||
#define ACC_DEBR_RB(x) (((uint32_t)(((uint32_t)(x))<<ACC_DEBR_RB_SHIFT))&ACC_DEBR_RB_MASK)
|
||||
|
||||
#define ACC_DEBR_RL_MASK 0xFFFCu
|
||||
|
||||
#define ACC_DEBR_RL_SHIFT 2u
|
||||
|
||||
#define ACC_DEBR_RL_WIDTH 14u
|
||||
|
||||
#define ACC_DEBR_RL(x) (((uint32_t)(((uint32_t)(x))<<ACC_DEBR_RL_SHIFT))&ACC_DEBR_RL_MASK)
|
||||
|
||||
#define ACC_DEBR_LOCKED_MASK 0x2u
|
||||
|
||||
#define ACC_DEBR_LOCKED_SHIFT 1u
|
||||
|
||||
#define ACC_DEBR_LOCKED_WIDTH 1u
|
||||
|
||||
#define ACC_DEBR_LOCKED(x) (((uint32_t)(((uint32_t)(x))<<ACC_DEBR_LOCKED_SHIFT))&ACC_DEBR_LOCKED_MASK)
|
||||
|
||||
#define ACC_DEBR_VALID_MASK 0x1u
|
||||
|
||||
#define ACC_DEBR_VALID_SHIFT 0u
|
||||
|
||||
#define ACC_DEBR_VALID_WIDTH 1u
|
||||
|
||||
#define ACC_DEBR_VALID(x) (((uint32_t)(((uint32_t)(x))<<ACC_DEBR_VALID_SHIFT))&ACC_DEBR_VALID_MASK)
|
||||
|
||||
/* DEBR0 Reg Mask */
|
||||
|
||||
#define ACC_DEBR_MASK 0x0003FFFFu
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group ACC_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group ACC_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,831 @@
|
|||
#ifndef _FC7240_ADC_NU_Tztufn20_REGS_H_
|
||||
#define _FC7240_ADC_NU_Tztufn20_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- ADC Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** ADC - Size of Registers Arrays */
|
||||
|
||||
|
||||
|
||||
/** ADC - Register Layout Typedef */
|
||||
|
||||
#define ADC_SGCSR_COUNT 4
|
||||
|
||||
#define ADC_SC_COUNT 32
|
||||
|
||||
#define ADC_RESULT_COUNT 32
|
||||
|
||||
#define ADC_SAMPLE_TIME_OPTION_CNT 4U
|
||||
|
||||
#define ADC_SEQUENCE_GROUP_CNT 4U
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
__IO uint32_t INT_STATUS ; /* Interrupt Status Register, offset: 0x0 */
|
||||
|
||||
__IO uint32_t INT_ENABLE ; /* Interrupt Enable Register, offset: 0x4 */
|
||||
|
||||
__IO uint32_t CONTROL ; /* Control Register, offset: 0x8 */
|
||||
|
||||
__IO uint32_t CFG1 ; /* Configuration1 Register, offset: 0xC */
|
||||
|
||||
__IO uint32_t CFG2 ; /* Configuration2 Register, offset: 0x10 */
|
||||
|
||||
__IO uint32_t SMPR ; /* Sampling Rate Register, offset: 0x14 */
|
||||
|
||||
__IO uint32_t CMP_CTRL ; /* Compare Control Register, offset: 0x18 */
|
||||
|
||||
__IO uint32_t CMP_TR ; /* Compare Threshold Register, offset: 0x1C */
|
||||
|
||||
uint8_t RESERVED_0[8];
|
||||
|
||||
__IO uint32_t SGCSR[ADC_SGCSR_COUNT] ; /* Sequence Group Control and Status Register, offset: 0x28 */
|
||||
|
||||
uint8_t RESERVED_1[12];
|
||||
|
||||
__IO uint32_t CAL ; /* Calibration Register, offset: 0x44 */
|
||||
|
||||
uint8_t RESERVED_2[4];
|
||||
|
||||
__IO uint32_t FIFO_DATA ; /* FIFO Data Register, offset: 0x4C */
|
||||
|
||||
__IO uint32_t SC[ADC_SC_COUNT] ; /* Sequence Configuration Register, offset: 0x50 */
|
||||
|
||||
__IO uint32_t RESULT[ADC_RESULT_COUNT] ; /* Result Register, offset: 0xd0 */
|
||||
|
||||
|
||||
|
||||
} ADC_Type, *ADC_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the ADC module. */
|
||||
|
||||
#define ADC_INSTANCE_COUNT (2u)
|
||||
|
||||
|
||||
|
||||
/* ADC - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral ADC0 base address */
|
||||
|
||||
#define ADC0_BASE (0x4003b000u)
|
||||
|
||||
/** Peripheral ADC0 base pointer */
|
||||
|
||||
#define ADC0 ((ADC_Type *)ADC0_BASE)
|
||||
|
||||
/** Peripheral ADC1 base address */
|
||||
|
||||
#define ADC1_BASE (0x4003c000u)
|
||||
|
||||
/** Peripheral ADC1 base pointer */
|
||||
|
||||
#define ADC1 ((ADC_Type *)ADC1_BASE)
|
||||
|
||||
/** Array initializer of ADC peripheral base addresses */
|
||||
|
||||
#define ADC_BASE_ADDRS {ADC0_BASE, ADC1_BASE}
|
||||
|
||||
/** Array initializer of ADC peripheral base pointers */
|
||||
|
||||
#define ADC_BASE_PTRS {ADC0, ADC1}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the ADC module. */
|
||||
|
||||
//#define ADC_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the ADC module. */
|
||||
|
||||
//#define ADC_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the ADC peripheral type */
|
||||
|
||||
//#define ADC_IRQS {ADC0_IRQn, ADC1_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- ADC Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup ADC_Register_Masks ADC Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* INT_STATUS Bit Fields */
|
||||
|
||||
#define ADC_INT_STATUS_TRGERR_MASK 0xF000000u
|
||||
|
||||
#define ADC_INT_STATUS_TRGERR_SHIFT 24u
|
||||
|
||||
#define ADC_INT_STATUS_TRGERR_WIDTH 4u
|
||||
|
||||
#define ADC_INT_STATUS_TRGERR(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_TRGERR_SHIFT))&ADC_INT_STATUS_TRGERR_MASK)
|
||||
|
||||
#define ADC_INT_STATUS_TRG_STATUS_MASK 0xF0000u
|
||||
|
||||
#define ADC_INT_STATUS_TRG_STATUS_SHIFT 16u
|
||||
|
||||
#define ADC_INT_STATUS_TRG_STATUS_WIDTH 4u
|
||||
|
||||
#define ADC_INT_STATUS_TRG_STATUS(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_TRG_STATUS_SHIFT))&ADC_INT_STATUS_TRG_STATUS_MASK)
|
||||
|
||||
#define ADC_INT_STATUS_TRG_PRO_NUM_MASK 0x6000u
|
||||
|
||||
#define ADC_INT_STATUS_TRG_PRO_NUM_SHIFT 13u
|
||||
|
||||
#define ADC_INT_STATUS_TRG_PRO_NUM_WIDTH 2u
|
||||
|
||||
#define ADC_INT_STATUS_TRG_PRO_NUM(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_TRG_PRO_NUM_SHIFT))&ADC_INT_STATUS_TRG_PRO_NUM_MASK)
|
||||
|
||||
#define ADC_INT_STATUS_FIFO_RDY_MASK 0x100u
|
||||
|
||||
#define ADC_INT_STATUS_FIFO_RDY_SHIFT 8u
|
||||
|
||||
#define ADC_INT_STATUS_FIFO_RDY_WIDTH 1u
|
||||
|
||||
#define ADC_INT_STATUS_FIFO_RDY(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_FIFO_RDY_SHIFT))&ADC_INT_STATUS_FIFO_RDY_MASK)
|
||||
|
||||
#define ADC_INT_STATUS_ACMP_MASK 0x80u
|
||||
|
||||
#define ADC_INT_STATUS_ACMP_SHIFT 7u
|
||||
|
||||
#define ADC_INT_STATUS_ACMP_WIDTH 1u
|
||||
|
||||
#define ADC_INT_STATUS_ACMP(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_ACMP_SHIFT))&ADC_INT_STATUS_ACMP_MASK)
|
||||
|
||||
#define ADC_INT_STATUS_EMPTY_MASK 0x40u
|
||||
|
||||
#define ADC_INT_STATUS_EMPTY_SHIFT 6u
|
||||
|
||||
#define ADC_INT_STATUS_EMPTY_WIDTH 1u
|
||||
|
||||
#define ADC_INT_STATUS_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_EMPTY_SHIFT))&ADC_INT_STATUS_EMPTY_MASK)
|
||||
|
||||
#define ADC_INT_STATUS_FULL_MASK 0x20u
|
||||
|
||||
#define ADC_INT_STATUS_FULL_SHIFT 5u
|
||||
|
||||
#define ADC_INT_STATUS_FULL_WIDTH 1u
|
||||
|
||||
#define ADC_INT_STATUS_FULL(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_FULL_SHIFT))&ADC_INT_STATUS_FULL_MASK)
|
||||
|
||||
#define ADC_INT_STATUS_OVR_MASK 0x10u
|
||||
|
||||
#define ADC_INT_STATUS_OVR_SHIFT 4u
|
||||
|
||||
#define ADC_INT_STATUS_OVR_WIDTH 1u
|
||||
|
||||
#define ADC_INT_STATUS_OVR(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_OVR_SHIFT))&ADC_INT_STATUS_OVR_MASK)
|
||||
|
||||
#define ADC_INT_STATUS_EOSEQ_MASK 0x8u
|
||||
|
||||
#define ADC_INT_STATUS_EOSEQ_SHIFT 3u
|
||||
|
||||
#define ADC_INT_STATUS_EOSEQ_WIDTH 1u
|
||||
|
||||
#define ADC_INT_STATUS_EOSEQ(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_EOSEQ_SHIFT))&ADC_INT_STATUS_EOSEQ_MASK)
|
||||
|
||||
#define ADC_INT_STATUS_EOC_MASK 0x4u
|
||||
|
||||
#define ADC_INT_STATUS_EOC_SHIFT 2u
|
||||
|
||||
#define ADC_INT_STATUS_EOC_WIDTH 1u
|
||||
|
||||
#define ADC_INT_STATUS_EOC(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_EOC_SHIFT))&ADC_INT_STATUS_EOC_MASK)
|
||||
|
||||
#define ADC_INT_STATUS_EOSMP_MASK 0x2u
|
||||
|
||||
#define ADC_INT_STATUS_EOSMP_SHIFT 1u
|
||||
|
||||
#define ADC_INT_STATUS_EOSMP_WIDTH 1u
|
||||
|
||||
#define ADC_INT_STATUS_EOSMP(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_EOSMP_SHIFT))&ADC_INT_STATUS_EOSMP_MASK)
|
||||
|
||||
#define ADC_INT_STATUS_ADRDY_MASK 0x1u
|
||||
|
||||
#define ADC_INT_STATUS_ADRDY_SHIFT 0u
|
||||
|
||||
#define ADC_INT_STATUS_ADRDY_WIDTH 1u
|
||||
|
||||
#define ADC_INT_STATUS_ADRDY(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_STATUS_ADRDY_SHIFT))&ADC_INT_STATUS_ADRDY_MASK)
|
||||
|
||||
/* INT_STATUS Reg Mask */
|
||||
|
||||
#define ADC_INT_STATUS_MASK 0x0F0F61FFu
|
||||
|
||||
|
||||
|
||||
/* INT_ENABLE Bit Fields */
|
||||
|
||||
#define ADC_INT_ENABLE_TRGERR_IE_MASK 0x400u
|
||||
|
||||
#define ADC_INT_ENABLE_TRGERR_IE_SHIFT 10u
|
||||
|
||||
#define ADC_INT_ENABLE_TRGERR_IE_WIDTH 1u
|
||||
|
||||
#define ADC_INT_ENABLE_TRGERR_IE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_TRGERR_IE_SHIFT))&ADC_INT_ENABLE_TRGERR_IE_MASK)
|
||||
|
||||
#define ADC_INT_ENABLE_FIFO_RDY_IE_MASK 0x100u
|
||||
|
||||
#define ADC_INT_ENABLE_FIFO_RDY_IE_SHIFT 8u
|
||||
|
||||
#define ADC_INT_ENABLE_FIFO_RDY_IE_WIDTH 1u
|
||||
|
||||
#define ADC_INT_ENABLE_FIFO_RDY_IE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_FIFO_RDY_IE_SHIFT))&ADC_INT_ENABLE_FIFO_RDY_IE_MASK)
|
||||
|
||||
#define ADC_INT_ENABLE_ACMP_IE_MASK 0x80u
|
||||
|
||||
#define ADC_INT_ENABLE_ACMP_IE_SHIFT 7u
|
||||
|
||||
#define ADC_INT_ENABLE_ACMP_IE_WIDTH 1u
|
||||
|
||||
#define ADC_INT_ENABLE_ACMP_IE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_ACMP_IE_SHIFT))&ADC_INT_ENABLE_ACMP_IE_MASK)
|
||||
|
||||
#define ADC_INT_ENABLE_OVRIE_MASK 0x10u
|
||||
|
||||
#define ADC_INT_ENABLE_OVRIE_SHIFT 4u
|
||||
|
||||
#define ADC_INT_ENABLE_OVRIE_WIDTH 1u
|
||||
|
||||
#define ADC_INT_ENABLE_OVRIE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_OVRIE_SHIFT))&ADC_INT_ENABLE_OVRIE_MASK)
|
||||
|
||||
#define ADC_INT_ENABLE_EOSEQIE_MASK 0x8u
|
||||
|
||||
#define ADC_INT_ENABLE_EOSEQIE_SHIFT 3u
|
||||
|
||||
#define ADC_INT_ENABLE_EOSEQIE_WIDTH 1u
|
||||
|
||||
#define ADC_INT_ENABLE_EOSEQIE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_EOSEQIE_SHIFT))&ADC_INT_ENABLE_EOSEQIE_MASK)
|
||||
|
||||
#define ADC_INT_ENABLE_EOCIE_MASK 0x4u
|
||||
|
||||
#define ADC_INT_ENABLE_EOCIE_SHIFT 2u
|
||||
|
||||
#define ADC_INT_ENABLE_EOCIE_WIDTH 1u
|
||||
|
||||
#define ADC_INT_ENABLE_EOCIE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_EOCIE_SHIFT))&ADC_INT_ENABLE_EOCIE_MASK)
|
||||
|
||||
#define ADC_INT_ENABLE_EOSMPIE_MASK 0x2u
|
||||
|
||||
#define ADC_INT_ENABLE_EOSMPIE_SHIFT 1u
|
||||
|
||||
#define ADC_INT_ENABLE_EOSMPIE_WIDTH 1u
|
||||
|
||||
#define ADC_INT_ENABLE_EOSMPIE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_EOSMPIE_SHIFT))&ADC_INT_ENABLE_EOSMPIE_MASK)
|
||||
|
||||
#define ADC_INT_ENABLE_ADRDYIE_MASK 0x1u
|
||||
|
||||
#define ADC_INT_ENABLE_ADRDYIE_SHIFT 0u
|
||||
|
||||
#define ADC_INT_ENABLE_ADRDYIE_WIDTH 1u
|
||||
|
||||
#define ADC_INT_ENABLE_ADRDYIE(x) (((uint32_t)(((uint32_t)(x))<<ADC_INT_ENABLE_ADRDYIE_SHIFT))&ADC_INT_ENABLE_ADRDYIE_MASK)
|
||||
|
||||
/* INT_ENABLE Reg Mask */
|
||||
|
||||
#define ADC_INT_ENABLE_MASK 0x0000059Fu
|
||||
|
||||
|
||||
|
||||
/* CONTROL Bit Fields */
|
||||
|
||||
#define ADC_CONTROL_ADRST_MASK 0x10u
|
||||
|
||||
#define ADC_CONTROL_ADRST_SHIFT 4u
|
||||
|
||||
#define ADC_CONTROL_ADRST_WIDTH 1u
|
||||
|
||||
#define ADC_CONTROL_ADRST(x) (((uint32_t)(((uint32_t)(x))<<ADC_CONTROL_ADRST_SHIFT))&ADC_CONTROL_ADRST_MASK)
|
||||
|
||||
#define ADC_CONTROL_ADSTP_MASK 0x8u
|
||||
|
||||
#define ADC_CONTROL_ADSTP_SHIFT 3u
|
||||
|
||||
#define ADC_CONTROL_ADSTP_WIDTH 1u
|
||||
|
||||
#define ADC_CONTROL_ADSTP(x) (((uint32_t)(((uint32_t)(x))<<ADC_CONTROL_ADSTP_SHIFT))&ADC_CONTROL_ADSTP_MASK)
|
||||
|
||||
#define ADC_CONTROL_ADSTART_MASK 0x4u
|
||||
|
||||
#define ADC_CONTROL_ADSTART_SHIFT 2u
|
||||
|
||||
#define ADC_CONTROL_ADSTART_WIDTH 1u
|
||||
|
||||
#define ADC_CONTROL_ADSTART(x) (((uint32_t)(((uint32_t)(x))<<ADC_CONTROL_ADSTART_SHIFT))&ADC_CONTROL_ADSTART_MASK)
|
||||
|
||||
#define ADC_CONTROL_ADDIS_MASK 0x2u
|
||||
|
||||
#define ADC_CONTROL_ADDIS_SHIFT 1u
|
||||
|
||||
#define ADC_CONTROL_ADDIS_WIDTH 1u
|
||||
|
||||
#define ADC_CONTROL_ADDIS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CONTROL_ADDIS_SHIFT))&ADC_CONTROL_ADDIS_MASK)
|
||||
|
||||
#define ADC_CONTROL_ADEN_MASK 0x1u
|
||||
|
||||
#define ADC_CONTROL_ADEN_SHIFT 0u
|
||||
|
||||
#define ADC_CONTROL_ADEN_WIDTH 1u
|
||||
|
||||
#define ADC_CONTROL_ADEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CONTROL_ADEN_SHIFT))&ADC_CONTROL_ADEN_MASK)
|
||||
|
||||
/* CONTROL Reg Mask */
|
||||
|
||||
#define ADC_CONTROL_MASK 0x0000001Fu
|
||||
|
||||
|
||||
|
||||
/* CFG1 Bit Fields */
|
||||
|
||||
#define ADC_CFG1_OVRMOD_MASK 0x40000000u
|
||||
|
||||
#define ADC_CFG1_OVRMOD_SHIFT 30u
|
||||
|
||||
#define ADC_CFG1_OVRMOD_WIDTH 1u
|
||||
|
||||
#define ADC_CFG1_OVRMOD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_OVRMOD_SHIFT))&ADC_CFG1_OVRMOD_MASK)
|
||||
|
||||
#define ADC_CFG1_SEQGP_EN_MASK 0x20000000u
|
||||
|
||||
#define ADC_CFG1_SEQGP_EN_SHIFT 29u
|
||||
|
||||
#define ADC_CFG1_SEQGP_EN_WIDTH 1u
|
||||
|
||||
#define ADC_CFG1_SEQGP_EN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_SEQGP_EN_SHIFT))&ADC_CFG1_SEQGP_EN_MASK)
|
||||
|
||||
#define ADC_CFG1_SEQ_LEN_MASK 0x1F000000u
|
||||
|
||||
#define ADC_CFG1_SEQ_LEN_SHIFT 24u
|
||||
|
||||
#define ADC_CFG1_SEQ_LEN_WIDTH 5u
|
||||
|
||||
#define ADC_CFG1_SEQ_LEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_SEQ_LEN_SHIFT))&ADC_CFG1_SEQ_LEN_MASK)
|
||||
|
||||
#define ADC_CFG1_SEQ_MOD_MASK 0xC00000u
|
||||
|
||||
#define ADC_CFG1_SEQ_MOD_SHIFT 22u
|
||||
|
||||
#define ADC_CFG1_SEQ_MOD_WIDTH 2u
|
||||
|
||||
#define ADC_CFG1_SEQ_MOD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_SEQ_MOD_SHIFT))&ADC_CFG1_SEQ_MOD_MASK)
|
||||
|
||||
#define ADC_CFG1_AUTO_DIS_MASK 0x200000u
|
||||
|
||||
#define ADC_CFG1_AUTO_DIS_SHIFT 21u
|
||||
|
||||
#define ADC_CFG1_AUTO_DIS_WIDTH 1u
|
||||
|
||||
#define ADC_CFG1_AUTO_DIS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_AUTO_DIS_SHIFT))&ADC_CFG1_AUTO_DIS_MASK)
|
||||
|
||||
#define ADC_CFG1_WAIT_MASK 0x100000u
|
||||
|
||||
#define ADC_CFG1_WAIT_SHIFT 20u
|
||||
|
||||
#define ADC_CFG1_WAIT_WIDTH 1u
|
||||
|
||||
#define ADC_CFG1_WAIT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_WAIT_SHIFT))&ADC_CFG1_WAIT_MASK)
|
||||
|
||||
#define ADC_CFG1_TRIGSRC_MASK 0x70000u
|
||||
|
||||
#define ADC_CFG1_TRIGSRC_SHIFT 16u
|
||||
|
||||
#define ADC_CFG1_TRIGSRC_WIDTH 3u
|
||||
|
||||
#define ADC_CFG1_TRIGSRC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_TRIGSRC_SHIFT))&ADC_CFG1_TRIGSRC_MASK)
|
||||
|
||||
#define ADC_CFG1_TRIGMODE_MASK 0x3800u
|
||||
|
||||
#define ADC_CFG1_TRIGMODE_SHIFT 11u
|
||||
|
||||
#define ADC_CFG1_TRIGMODE_WIDTH 3u
|
||||
|
||||
#define ADC_CFG1_TRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_TRIGMODE_SHIFT))&ADC_CFG1_TRIGMODE_MASK)
|
||||
|
||||
#define ADC_CFG1_ALIGN_MASK 0x400u
|
||||
|
||||
#define ADC_CFG1_ALIGN_SHIFT 10u
|
||||
|
||||
#define ADC_CFG1_ALIGN_WIDTH 1u
|
||||
|
||||
#define ADC_CFG1_ALIGN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ALIGN_SHIFT))&ADC_CFG1_ALIGN_MASK)
|
||||
|
||||
#define ADC_CFG1_RES_MASK 0x300u
|
||||
|
||||
#define ADC_CFG1_RES_SHIFT 8u
|
||||
|
||||
#define ADC_CFG1_RES_WIDTH 2u
|
||||
|
||||
#define ADC_CFG1_RES(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_RES_SHIFT))&ADC_CFG1_RES_MASK)
|
||||
|
||||
#define ADC_CFG1_DMAEN_MASK 0x1u
|
||||
|
||||
#define ADC_CFG1_DMAEN_SHIFT 0u
|
||||
|
||||
#define ADC_CFG1_DMAEN_WIDTH 1u
|
||||
|
||||
#define ADC_CFG1_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_DMAEN_SHIFT))&ADC_CFG1_DMAEN_MASK)
|
||||
|
||||
/* CFG1 Reg Mask */
|
||||
|
||||
#define ADC_CFG1_MASK 0x7FF73F01u
|
||||
|
||||
|
||||
|
||||
/* CFG2 Bit Fields */
|
||||
|
||||
#define ADC_CFG2_FWMARK_MASK 0x1F000000u
|
||||
|
||||
#define ADC_CFG2_FWMARK_SHIFT 24u
|
||||
|
||||
#define ADC_CFG2_FWMARK_WIDTH 5u
|
||||
|
||||
#define ADC_CFG2_FWMARK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_FWMARK_SHIFT))&ADC_CFG2_FWMARK_MASK)
|
||||
|
||||
#define ADC_CFG2_TRG_PRI_MASK 0x100000u
|
||||
|
||||
#define ADC_CFG2_TRG_PRI_SHIFT 20u
|
||||
|
||||
#define ADC_CFG2_TRG_PRI_WIDTH 1u
|
||||
|
||||
#define ADC_CFG2_TRG_PRI(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_TRG_PRI_SHIFT))&ADC_CFG2_TRG_PRI_MASK)
|
||||
|
||||
#define ADC_CFG2_TRG_CLR_MASK 0x80000u
|
||||
|
||||
#define ADC_CFG2_TRG_CLR_SHIFT 19u
|
||||
|
||||
#define ADC_CFG2_TRG_CLR_WIDTH 1u
|
||||
|
||||
#define ADC_CFG2_TRG_CLR(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_TRG_CLR_SHIFT))&ADC_CFG2_TRG_CLR_MASK)
|
||||
|
||||
#define ADC_CFG2_AVG_EN_MASK 0x40000u
|
||||
|
||||
#define ADC_CFG2_AVG_EN_SHIFT 18u
|
||||
|
||||
#define ADC_CFG2_AVG_EN_WIDTH 1u
|
||||
|
||||
#define ADC_CFG2_AVG_EN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_AVG_EN_SHIFT))&ADC_CFG2_AVG_EN_MASK)
|
||||
|
||||
#define ADC_CFG2_AVG_LEN_MASK 0x30000u
|
||||
|
||||
#define ADC_CFG2_AVG_LEN_SHIFT 16u
|
||||
|
||||
#define ADC_CFG2_AVG_LEN_WIDTH 2u
|
||||
|
||||
#define ADC_CFG2_AVG_LEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_AVG_LEN_SHIFT))&ADC_CFG2_AVG_LEN_MASK)
|
||||
|
||||
#define ADC_CFG2_CG_ACK_MASK 0x4000u
|
||||
|
||||
#define ADC_CFG2_CG_ACK_SHIFT 14u
|
||||
|
||||
#define ADC_CFG2_CG_ACK_WIDTH 1u
|
||||
|
||||
#define ADC_CFG2_CG_ACK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_CG_ACK_SHIFT))&ADC_CFG2_CG_ACK_MASK)
|
||||
|
||||
#define ADC_CFG2_CG_MASK 0x2000u
|
||||
|
||||
#define ADC_CFG2_CG_SHIFT 13u
|
||||
|
||||
#define ADC_CFG2_CG_WIDTH 1u
|
||||
|
||||
#define ADC_CFG2_CG(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_CG_SHIFT))&ADC_CFG2_CG_MASK)
|
||||
|
||||
#define ADC_CFG2_REF_EXT_MASK 0x1000u
|
||||
|
||||
#define ADC_CFG2_REF_EXT_SHIFT 12u
|
||||
|
||||
#define ADC_CFG2_REF_EXT_WIDTH 1u
|
||||
|
||||
#define ADC_CFG2_REF_EXT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_REF_EXT_SHIFT))&ADC_CFG2_REF_EXT_MASK)
|
||||
|
||||
#define ADC_CFG2_DIV_MASK 0x300u
|
||||
|
||||
#define ADC_CFG2_DIV_SHIFT 8u
|
||||
|
||||
#define ADC_CFG2_DIV_WIDTH 2u
|
||||
|
||||
#define ADC_CFG2_DIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_DIV_SHIFT))&ADC_CFG2_DIV_MASK)
|
||||
|
||||
#define ADC_CFG2_STCNT_MASK 0xFFu
|
||||
|
||||
#define ADC_CFG2_STCNT_SHIFT 0u
|
||||
|
||||
#define ADC_CFG2_STCNT_WIDTH 8u
|
||||
|
||||
#define ADC_CFG2_STCNT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_STCNT_SHIFT))&ADC_CFG2_STCNT_MASK)
|
||||
|
||||
/* CFG2 Reg Mask */
|
||||
|
||||
#define ADC_CFG2_MASK 0x1F1F73FFu
|
||||
|
||||
|
||||
|
||||
/* SMPR Bit Fields */
|
||||
|
||||
#define ADC_SMPR_SMP_OPT3_MASK 0xFF000000u
|
||||
|
||||
#define ADC_SMPR_SMP_OPT3_SHIFT 24u
|
||||
|
||||
#define ADC_SMPR_SMP_OPT3_WIDTH 8u
|
||||
|
||||
#define ADC_SMPR_SMP_OPT3(x) (((uint32_t)(((uint32_t)(x))<<ADC_SMPR_SMP_OPT3_SHIFT))&ADC_SMPR_SMP_OPT3_MASK)
|
||||
|
||||
#define ADC_SMPR_SMP_OPT2_MASK 0xFF0000u
|
||||
|
||||
#define ADC_SMPR_SMP_OPT2_SHIFT 16u
|
||||
|
||||
#define ADC_SMPR_SMP_OPT2_WIDTH 8u
|
||||
|
||||
#define ADC_SMPR_SMP_OPT2(x) (((uint32_t)(((uint32_t)(x))<<ADC_SMPR_SMP_OPT2_SHIFT))&ADC_SMPR_SMP_OPT2_MASK)
|
||||
|
||||
#define ADC_SMPR_SMP_OPT1_MASK 0xFF00u
|
||||
|
||||
#define ADC_SMPR_SMP_OPT1_SHIFT 8u
|
||||
|
||||
#define ADC_SMPR_SMP_OPT1_WIDTH 8u
|
||||
|
||||
#define ADC_SMPR_SMP_OPT1(x) (((uint32_t)(((uint32_t)(x))<<ADC_SMPR_SMP_OPT1_SHIFT))&ADC_SMPR_SMP_OPT1_MASK)
|
||||
|
||||
#define ADC_SMPR_SMP_OPT0_MASK 0xFFu
|
||||
|
||||
#define ADC_SMPR_SMP_OPT0_SHIFT 0u
|
||||
|
||||
#define ADC_SMPR_SMP_OPT0_WIDTH 8u
|
||||
|
||||
#define ADC_SMPR_SMP_OPT0(x) (((uint32_t)(((uint32_t)(x))<<ADC_SMPR_SMP_OPT0_SHIFT))&ADC_SMPR_SMP_OPT0_MASK)
|
||||
|
||||
/* SMPR Reg Mask */
|
||||
|
||||
#define ADC_SMPR_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* CMP_CTRL Bit Fields */
|
||||
|
||||
#define ADC_CMP_CTRL_ACMPEN_MASK 0x80u
|
||||
|
||||
#define ADC_CMP_CTRL_ACMPEN_SHIFT 7u
|
||||
|
||||
#define ADC_CMP_CTRL_ACMPEN_WIDTH 1u
|
||||
|
||||
#define ADC_CMP_CTRL_ACMPEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CMP_CTRL_ACMPEN_SHIFT))&ADC_CMP_CTRL_ACMPEN_MASK)
|
||||
|
||||
#define ADC_CMP_CTRL_ACMPSGL_MASK 0x40u
|
||||
|
||||
#define ADC_CMP_CTRL_ACMPSGL_SHIFT 6u
|
||||
|
||||
#define ADC_CMP_CTRL_ACMPSGL_WIDTH 1u
|
||||
|
||||
#define ADC_CMP_CTRL_ACMPSGL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CMP_CTRL_ACMPSGL_SHIFT))&ADC_CMP_CTRL_ACMPSGL_MASK)
|
||||
|
||||
#define ADC_CMP_CTRL_ACMPCH_MASK 0x3Fu
|
||||
|
||||
#define ADC_CMP_CTRL_ACMPCH_SHIFT 0u
|
||||
|
||||
#define ADC_CMP_CTRL_ACMPCH_WIDTH 6u
|
||||
|
||||
#define ADC_CMP_CTRL_ACMPCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_CMP_CTRL_ACMPCH_SHIFT))&ADC_CMP_CTRL_ACMPCH_MASK)
|
||||
|
||||
/* CMP_CTRL Reg Mask */
|
||||
|
||||
#define ADC_CMP_CTRL_MASK 0x000000FFu
|
||||
|
||||
|
||||
|
||||
/* CMP_TR Bit Fields */
|
||||
|
||||
#define ADC_CMP_TR_HT_MASK 0xFFF0000u
|
||||
|
||||
#define ADC_CMP_TR_HT_SHIFT 16u
|
||||
|
||||
#define ADC_CMP_TR_HT_WIDTH 12u
|
||||
|
||||
#define ADC_CMP_TR_HT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CMP_TR_HT_SHIFT))&ADC_CMP_TR_HT_MASK)
|
||||
|
||||
#define ADC_CMP_TR_LT_MASK 0xFFFu
|
||||
|
||||
#define ADC_CMP_TR_LT_SHIFT 0u
|
||||
|
||||
#define ADC_CMP_TR_LT_WIDTH 12u
|
||||
|
||||
#define ADC_CMP_TR_LT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CMP_TR_LT_SHIFT))&ADC_CMP_TR_LT_MASK)
|
||||
|
||||
/* CMP_TR Reg Mask */
|
||||
|
||||
#define ADC_CMP_TR_MASK 0x0FFF0FFFu
|
||||
|
||||
|
||||
|
||||
/* SGCSR Bit Fields */
|
||||
|
||||
#define ADC_SGCSR_EOSG_MASK 0x1000000u
|
||||
|
||||
#define ADC_SGCSR_EOSG_SHIFT 24u
|
||||
|
||||
#define ADC_SGCSR_EOSG_WIDTH 1u
|
||||
|
||||
#define ADC_SGCSR_EOSG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SGCSR_EOSG_SHIFT))&ADC_SGCSR_EOSG_MASK)
|
||||
|
||||
#define ADC_SGCSR_EOSGIE_MASK 0x10000u
|
||||
|
||||
#define ADC_SGCSR_EOSGIE_SHIFT 16u
|
||||
|
||||
#define ADC_SGCSR_EOSGIE_WIDTH 1u
|
||||
|
||||
#define ADC_SGCSR_EOSGIE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SGCSR_EOSGIE_SHIFT))&ADC_SGCSR_EOSGIE_MASK)
|
||||
|
||||
#define ADC_SGCSR_SG_END_MASK 0x1F00u
|
||||
|
||||
#define ADC_SGCSR_SG_END_SHIFT 8u
|
||||
|
||||
#define ADC_SGCSR_SG_END_WIDTH 5u
|
||||
|
||||
#define ADC_SGCSR_SG_END(x) (((uint32_t)(((uint32_t)(x))<<ADC_SGCSR_SG_END_SHIFT))&ADC_SGCSR_SG_END_MASK)
|
||||
|
||||
#define ADC_SGCSR_SG_START_MASK 0x1Fu
|
||||
|
||||
#define ADC_SGCSR_SG_START_SHIFT 0u
|
||||
|
||||
#define ADC_SGCSR_SG_START_WIDTH 5u
|
||||
|
||||
#define ADC_SGCSR_SG_START(x) (((uint32_t)(((uint32_t)(x))<<ADC_SGCSR_SG_START_SHIFT))&ADC_SGCSR_SG_START_MASK)
|
||||
|
||||
/* SGCSR0 Reg Mask */
|
||||
|
||||
#define ADC_SGCSR_MASK 0x01011F1Fu
|
||||
|
||||
|
||||
|
||||
/* CAL Bit Fields */
|
||||
|
||||
#define ADC_CAL_CAL_EN_MASK 0x80000000u
|
||||
|
||||
#define ADC_CAL_CAL_EN_SHIFT 31u
|
||||
|
||||
#define ADC_CAL_CAL_EN_WIDTH 1u
|
||||
|
||||
#define ADC_CAL_CAL_EN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CAL_CAL_EN_SHIFT))&ADC_CAL_CAL_EN_MASK)
|
||||
|
||||
#define ADC_CAL_OFFSET_MASK 0xFFF0000u
|
||||
|
||||
#define ADC_CAL_OFFSET_SHIFT 16u
|
||||
|
||||
#define ADC_CAL_OFFSET_WIDTH 12u
|
||||
|
||||
#define ADC_CAL_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ADC_CAL_OFFSET_SHIFT))&ADC_CAL_OFFSET_MASK)
|
||||
|
||||
#define ADC_CAL_GAIN_MASK 0x1FFFu
|
||||
|
||||
#define ADC_CAL_GAIN_SHIFT 0u
|
||||
|
||||
#define ADC_CAL_GAIN_WIDTH 13u
|
||||
|
||||
#define ADC_CAL_GAIN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CAL_GAIN_SHIFT))&ADC_CAL_GAIN_MASK)
|
||||
|
||||
/* CAL Reg Mask */
|
||||
|
||||
#define ADC_CAL_MASK 0x8FFF1FFFu
|
||||
|
||||
|
||||
|
||||
/* FIFO_DATA Bit Fields */
|
||||
|
||||
#define ADC_FIFO_DATA_FIFO_DATA_MASK 0xFFFFu
|
||||
|
||||
#define ADC_FIFO_DATA_FIFO_DATA_SHIFT 0u
|
||||
|
||||
#define ADC_FIFO_DATA_FIFO_DATA_WIDTH 16u
|
||||
|
||||
#define ADC_FIFO_DATA_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x))<<ADC_FIFO_DATA_FIFO_DATA_SHIFT))&ADC_FIFO_DATA_FIFO_DATA_MASK)
|
||||
|
||||
/* FIFO_DATA Reg Mask */
|
||||
|
||||
#define ADC_FIFO_DATA_MASK 0x0000FFFFu
|
||||
|
||||
|
||||
|
||||
/* SC Bit Fields */
|
||||
|
||||
#define ADC_SC_DIFF_MASK 0x400u
|
||||
|
||||
#define ADC_SC_DIFF_SHIFT 10u
|
||||
|
||||
#define ADC_SC_DIFF_WIDTH 1u
|
||||
|
||||
#define ADC_SC_DIFF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC_DIFF_SHIFT))&ADC_SC_DIFF_MASK)
|
||||
|
||||
#define ADC_SC_SMPSEL_MASK 0x300u
|
||||
|
||||
#define ADC_SC_SMPSEL_SHIFT 8u
|
||||
|
||||
#define ADC_SC_SMPSEL_WIDTH 2u
|
||||
|
||||
#define ADC_SC_SMPSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC_SMPSEL_SHIFT))&ADC_SC_SMPSEL_MASK)
|
||||
|
||||
#define ADC_SC_COCO_MASK 0x80u
|
||||
|
||||
#define ADC_SC_COCO_SHIFT 7u
|
||||
|
||||
#define ADC_SC_COCO_WIDTH 1u
|
||||
|
||||
#define ADC_SC_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC_COCO_SHIFT))&ADC_SC_COCO_MASK)
|
||||
|
||||
#define ADC_SC_AIEN_MASK 0x40u
|
||||
|
||||
#define ADC_SC_AIEN_SHIFT 6u
|
||||
|
||||
#define ADC_SC_AIEN_WIDTH 1u
|
||||
|
||||
#define ADC_SC_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC_AIEN_SHIFT))&ADC_SC_AIEN_MASK)
|
||||
|
||||
#define ADC_SC_CHS_MASK 0x3Fu
|
||||
|
||||
#define ADC_SC_CHS_SHIFT 0u
|
||||
|
||||
#define ADC_SC_CHS_WIDTH 6u
|
||||
|
||||
#define ADC_SC_CHS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC_CHS_SHIFT))&ADC_SC_CHS_MASK)
|
||||
|
||||
/* SC0 Reg Mask */
|
||||
|
||||
#define ADC_SC_MASK 0x000007FFu
|
||||
|
||||
|
||||
|
||||
/* RESULT Bit Fields */
|
||||
|
||||
#define ADC_RESULT_RESULT_MASK 0xFFFFu
|
||||
|
||||
#define ADC_RESULT_RESULT_SHIFT 0u
|
||||
|
||||
#define ADC_RESULT_RESULT_WIDTH 16u
|
||||
|
||||
#define ADC_RESULT_RESULT(x) (((uint32_t)(((uint32_t)(x))<<ADC_RESULT_RESULT_SHIFT))&ADC_RESULT_RESULT_MASK)
|
||||
|
||||
/* RESULT0 Reg Mask */
|
||||
|
||||
#define ADC_RESULT_MASK 0x0000FFFFu
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group ADC_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group ADC_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,805 @@
|
|||
#ifndef _FC7240_AHB_OVERLAY_NU_Tztufn37_REGS_H_
|
||||
#define _FC7240_AHB_OVERLAY_NU_Tztufn37_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- AHB_OVERLAY Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup AHB_OVERLAY_Peripheral_Access_Layer AHB_OVERLAY Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** AHB_OVERLAY - Size of Registers Arrays */
|
||||
|
||||
|
||||
|
||||
/** AHB_OVERLAY - Register Layout Typedef */
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
__IO uint32_t REGION_0_SRC ; /* Region 0 Source Address Register, offset: 0x00 */
|
||||
|
||||
__IO uint32_t REGION_0_DST ; /* Region 0 Destination Address Register, offset: 0x04 */
|
||||
|
||||
__IO uint32_t REGION_0_SIZE ; /* Region 0 Size Register, offset: 0x08 */
|
||||
|
||||
__IO uint32_t REGION_0_EN ; /* Region 0 Enable Register, offset: 0x0C */
|
||||
|
||||
__IO uint32_t REGION_1_SRC ; /* Region 1 Source Address Register, offset: 0x10 */
|
||||
|
||||
__IO uint32_t REGION_1_DST ; /* Region 1 Destination Address Register, offset: 0x14 */
|
||||
|
||||
__IO uint32_t REGION_1_SIZE ; /* Region 1 Size Register, offset: 0x18 */
|
||||
|
||||
__IO uint32_t REGION_1_EN ; /* Region 1 Enable Register, offset: 0x1C */
|
||||
|
||||
__IO uint32_t REGION_2_SRC ; /* region 2 source address Register, offset: 0x20 */
|
||||
|
||||
__IO uint32_t REGION_2_DST ; /* Region 2 Destination Address Register, offset: 0x24 */
|
||||
|
||||
__IO uint32_t REGION_2_SIZE ; /* Region 2 Size Register, offset: 0x28 */
|
||||
|
||||
__IO uint32_t REGION_2_EN ; /* Region 2 Enable Register, offset: 0x2C */
|
||||
|
||||
uint8_t RESERVED_0[80];
|
||||
|
||||
__IO uint32_t GLOBAL_EN ; /* Enable of FAR and Overlay Register, offset: 0x80 */
|
||||
|
||||
__I uint32_t INTR_FLAG ; /* Flag of All Interrupt Register, offset: 0x84 */
|
||||
|
||||
__O uint32_t INTR_CLR ; /* Clear Bit of Interupt Register, offset: 0x88 */
|
||||
|
||||
__IO uint32_t INTR_EN ; /* Enable of Interrupt Register, offset: 0x8C */
|
||||
|
||||
__I uint32_t FAR_SRC ; /* Source of FAR Register, offset: 0x90 */
|
||||
|
||||
__IO uint32_t FAR_DST ; /* Sestination of FAR Register, offset: 0x94 */
|
||||
|
||||
__IO uint32_t FAR_SIZE ; /* Size of FAR Register, offset: 0x98 */
|
||||
|
||||
uint8_t RESERVED_1[4];
|
||||
|
||||
__I uint32_t REGION0_MASK ; /* Region 0 Mask Register, offset: 0xA0 */
|
||||
|
||||
__I uint32_t REGION1_MASK ; /* Region 1 Mask Register, offset: 0xA4 */
|
||||
|
||||
__I uint32_t REGION2_MASK ; /* Region 2 Mask Register, offset: 0xA8 */
|
||||
|
||||
|
||||
|
||||
} AHB_OVERLAY_Type, *AHB_OVERLAY_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the AHB_OVERLAY module. */
|
||||
|
||||
#define AHB_OVERLAY_INSTANCE_COUNT (1u)
|
||||
|
||||
|
||||
|
||||
/* AHB_OVERLAY - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral AHB_OVERLAY base address */
|
||||
|
||||
#define AHB_OVERLAY_BASE (0xE0081000u)
|
||||
|
||||
/** Peripheral AHB_OVERLAY base pointer */
|
||||
|
||||
#define AHB_OVERLAY ((AHB_OVERLAY_Type *)AHB_OVERLAY_BASE)
|
||||
|
||||
/** Array initializer of AHB_OVERLAY peripheral base addresses */
|
||||
|
||||
#define AHB_OVERLAY_BASE_ADDRS {AHB_OVERLAY_BASE}
|
||||
|
||||
/** Array initializer of AHB_OVERLAY peripheral base pointers */
|
||||
|
||||
#define AHB_OVERLAY_BASE_PTRS {AHB_OVERLAY}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the AHB_OVERLAY module. */
|
||||
|
||||
//#define AHB_OVERLAY_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the AHB_OVERLAY module. */
|
||||
|
||||
//#define AHB_OVERLAY_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the AHB_OVERLAY peripheral type */
|
||||
|
||||
//#define AHB_OVERLAY_IRQS {AHB_OVERLAY_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- AHB_OVERLAY Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup AHB_OVERLAY_Register_Masks AHB_OVERLAY Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* REGION_0_SRC Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_SRC_REGION0_SRC_MASK 0x1FFC00u
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_SRC_REGION0_SRC_SHIFT 10u
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_SRC_REGION0_SRC_WIDTH 11u
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_SRC_REGION0_SRC(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_0_SRC_REGION0_SRC_MASK)
|
||||
|
||||
/* REGION_0_SRC Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_SRC_MASK 0x001FFC00u
|
||||
|
||||
|
||||
|
||||
/* REGION_0_DST Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_DST_REGION0_DST_MASK 0xFFFFFC00u
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_DST_REGION0_DST_SHIFT 10u
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_DST_REGION0_DST_WIDTH 22u
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_DST_REGION0_DST(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_0_DST_REGION0_DST_MASK)
|
||||
|
||||
/* REGION_0_DST Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_DST_MASK 0xFFFFFC00u
|
||||
|
||||
|
||||
|
||||
/* REGION_0_SIZE Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_MASK 0x7Fu
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_WIDTH 7u
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_SHIFT))&AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE_MASK)
|
||||
|
||||
/* REGION_0_SIZE Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_SIZE_MASK 0x0000007Fu
|
||||
|
||||
|
||||
|
||||
/* REGION_0_EN Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK 0x1u
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_EN_REGION0_EN_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_EN_REGION0_EN_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_EN_REGION0_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_0_EN_REGION0_EN_SHIFT))&AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK)
|
||||
|
||||
/* REGION_0_EN Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION_0_EN_MASK 0x00000001u
|
||||
|
||||
|
||||
|
||||
/* REGION_1_SRC Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_SRC_REGION1_SRC_MASK 0x1FFC00u
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_SRC_REGION1_SRC_SHIFT 10u
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_SRC_REGION1_SRC_WIDTH 11u
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_SRC_REGION1_SRC(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_1_SRC_REGION1_SRC_MASK)
|
||||
|
||||
/* REGION_1_SRC Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_SRC_MASK 0x001FFC00u
|
||||
|
||||
|
||||
|
||||
/* REGION_1_DST Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_DST_REGION1_DST_MASK 0xFFFFFC00u
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_DST_REGION1_DST_SHIFT 10u
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_DST_REGION1_DST_WIDTH 22u
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_DST_REGION1_DST(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_1_DST_REGION1_DST_MASK)
|
||||
|
||||
/* REGION_1_DST Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_DST_MASK 0xFFFFFC00u
|
||||
|
||||
|
||||
|
||||
/* REGION_1_SIZE Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_MASK 0x7Fu
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_WIDTH 7u
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_SHIFT))&AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE_MASK)
|
||||
|
||||
/* REGION_1_SIZE Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_SIZE_MASK 0x0000007Fu
|
||||
|
||||
|
||||
|
||||
/* REGION_1_EN Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK 0x1u
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_EN_REGION1_EN_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_EN_REGION1_EN_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_EN_REGION1_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_1_EN_REGION1_EN_SHIFT))&AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK)
|
||||
|
||||
/* REGION_1_EN Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION_1_EN_MASK 0x00000001u
|
||||
|
||||
|
||||
|
||||
/* REGION_2_SRC Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_SRC_REGION2_SRC_MASK 0x1FFC00u
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_SRC_REGION2_SRC_SHIFT 10u
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_SRC_REGION2_SRC_WIDTH 11u
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_SRC_REGION2_SRC(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_2_SRC_REGION2_SRC_MASK)
|
||||
|
||||
/* REGION_2_SRC Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_SRC_MASK 0x001FFC00u
|
||||
|
||||
|
||||
|
||||
/* REGION_2_DST Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_DST_REGION2_DST_MASK 0xFFFFFC00u
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_DST_REGION2_DST_SHIFT 10u
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_DST_REGION2_DST_WIDTH 22u
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_DST_REGION2_DST(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_REGION_2_DST_REGION2_DST_MASK)
|
||||
|
||||
/* REGION_2_DST Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_DST_MASK 0xFFFFFC00u
|
||||
|
||||
|
||||
|
||||
/* REGION_2_SIZE Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_MASK 0x7Fu
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_WIDTH 7u
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_SHIFT))&AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE_MASK)
|
||||
|
||||
/* REGION_2_SIZE Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_SIZE_MASK 0x0000007Fu
|
||||
|
||||
|
||||
|
||||
/* REGION_2_EN Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK 0x1u
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_EN_REGION2_EN_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_EN_REGION2_EN_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_EN_REGION2_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION_2_EN_REGION2_EN_SHIFT))&AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK)
|
||||
|
||||
/* REGION_2_EN Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION_2_EN_MASK 0x00000001u
|
||||
|
||||
|
||||
|
||||
/* GLOBAL_EN Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK 0x2u
|
||||
|
||||
#define AHB_OVERLAY_GLOBAL_EN_FAR_EN_SHIFT 1u
|
||||
|
||||
#define AHB_OVERLAY_GLOBAL_EN_FAR_EN_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_GLOBAL_EN_FAR_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_GLOBAL_EN_FAR_EN_SHIFT))&AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK)
|
||||
|
||||
#define AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK 0x1u
|
||||
|
||||
#define AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_SHIFT))&AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK)
|
||||
|
||||
/* GLOBAL_EN Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_GLOBAL_EN_MASK 0x00000003u
|
||||
|
||||
|
||||
|
||||
/* INTR_FLAG Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_MASK 0x20000u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_SHIFT 17u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_MASK 0x10000u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_SHIFT 16u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_MASK 0x8000u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_SHIFT 15u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_MASK 0x4000u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_SHIFT 14u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_MASK 0x2000u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_SHIFT 13u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_MASK 0x1000u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_SHIFT 12u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_MASK 0x800u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_SHIFT 11u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_MASK 0x400u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_SHIFT 10u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_MASK 0x200u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_SHIFT 9u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_MASK 0x100u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_SHIFT 8u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_MASK 0x80u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_SHIFT 7u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_MASK 0x40u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_SHIFT 6u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_MASK 0x20u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_SHIFT 5u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_MASK 0x10u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_SHIFT 4u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_MASK 0x8u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_SHIFT 3u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_MASK 0x4u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_SHIFT 2u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_MASK 0x2u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_SHIFT 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_MASK 0x1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_SHIFT))&AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_MASK)
|
||||
|
||||
/* INTR_FLAG Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_INTR_FLAG_MASK 0x0003FFFFu
|
||||
|
||||
|
||||
|
||||
/* INTR_CLR Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_MASK 0x20000u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_SHIFT 17u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_FAR_SIZE_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_MASK 0x10000u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_SHIFT 16u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_FAR_DST_OVERFLOW_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_MASK 0x8000u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_SHIFT 15u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_FAR_DST_ON_FLASH_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_MASK 0x4000u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_SHIFT 14u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_D_CROS_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_MASK 0x2000u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_SHIFT 13u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_S_CROS_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_MASK 0x1000u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_SHIFT 12u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_SIZE_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_MASK 0x800u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_SHIFT 11u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_DST_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_MASK 0x400u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_SHIFT 10u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION2_SRC_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_MASK 0x200u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_SHIFT 9u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_D_CROS_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_MASK 0x100u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_SHIFT 8u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_S_CROS_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_MASK 0x80u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_SHIFT 7u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_SIZE_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_MASK 0x40u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_SHIFT 6u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_DST_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_MASK 0x20u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_SHIFT 5u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION1_SRC_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_MASK 0x10u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_SHIFT 4u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_D_CROS_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_MASK 0x8u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_SHIFT 3u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_S_CROS_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_MASK 0x4u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_SHIFT 2u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_SIZE_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_MASK 0x2u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_SHIFT 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_DST_INTR_CLR_MASK)
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_MASK 0x1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_SHIFT))&AHB_OVERLAY_INTR_CLR_REGION0_SRC_INTR_CLR_MASK)
|
||||
|
||||
/* INTR_CLR Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_INTR_CLR_MASK 0x0003FFFFu
|
||||
|
||||
|
||||
|
||||
/* INTR_EN Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK 0x1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_EN_INTR_ENABLE_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_INTR_EN_INTR_ENABLE_WIDTH 1u
|
||||
|
||||
#define AHB_OVERLAY_INTR_EN_INTR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_INTR_EN_INTR_ENABLE_SHIFT))&AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK)
|
||||
|
||||
/* INTR_EN Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_INTR_EN_MASK 0x00000001u
|
||||
|
||||
|
||||
|
||||
/* FAR_SRC Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR_MASK 0xFFFFFFFFu
|
||||
|
||||
#define AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR_WIDTH 32u
|
||||
|
||||
#define AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_FAR_SRC_FAR_SRC_ADDR_MASK)
|
||||
|
||||
/* FAR_SRC Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_FAR_SRC_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* FAR_DST Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_FAR_DST_FAR_DST_ADDR_MASK 0xFFFF0000u
|
||||
|
||||
#define AHB_OVERLAY_FAR_DST_FAR_DST_ADDR_SHIFT 16u
|
||||
|
||||
#define AHB_OVERLAY_FAR_DST_FAR_DST_ADDR_WIDTH 16u
|
||||
|
||||
#define AHB_OVERLAY_FAR_DST_FAR_DST_ADDR(x) (((uint32_t)(((uint32_t)(x))))&AHB_OVERLAY_FAR_DST_FAR_DST_ADDR_MASK)
|
||||
|
||||
/* FAR_DST Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_FAR_DST_MASK 0xFFFF0000u
|
||||
|
||||
|
||||
|
||||
/* FAR_SIZE Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_MASK 0x1FFu
|
||||
|
||||
#define AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_WIDTH 9u
|
||||
|
||||
#define AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_SHIFT))&AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL_MASK)
|
||||
|
||||
/* FAR_SIZE Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_FAR_SIZE_MASK 0x000001FFu
|
||||
|
||||
|
||||
|
||||
/* REGION0_MASK Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION0_MASK_REGION0_MASK_MASK 0xFFFFFFFFu
|
||||
|
||||
#define AHB_OVERLAY_REGION0_MASK_REGION0_MASK_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_REGION0_MASK_REGION0_MASK_WIDTH 32u
|
||||
|
||||
#define AHB_OVERLAY_REGION0_MASK_REGION0_MASK(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION0_MASK_REGION0_MASK_SHIFT))&AHB_OVERLAY_REGION0_MASK_REGION0_MASK_MASK)
|
||||
|
||||
/* REGION0_MASK Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION0_MASK_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* REGION1_MASK Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION1_MASK_REGION1_MASK_MASK 0xFFFFFFFFu
|
||||
|
||||
#define AHB_OVERLAY_REGION1_MASK_REGION1_MASK_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_REGION1_MASK_REGION1_MASK_WIDTH 32u
|
||||
|
||||
#define AHB_OVERLAY_REGION1_MASK_REGION1_MASK(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION1_MASK_REGION1_MASK_SHIFT))&AHB_OVERLAY_REGION1_MASK_REGION1_MASK_MASK)
|
||||
|
||||
/* REGION1_MASK Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION1_MASK_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* REGION2_MASK Bit Fields */
|
||||
|
||||
#define AHB_OVERLAY_REGION2_MASK_REGION2_MASK_MASK 0xFFFFFFFFu
|
||||
|
||||
#define AHB_OVERLAY_REGION2_MASK_REGION2_MASK_SHIFT 0u
|
||||
|
||||
#define AHB_OVERLAY_REGION2_MASK_REGION2_MASK_WIDTH 32u
|
||||
|
||||
#define AHB_OVERLAY_REGION2_MASK_REGION2_MASK(x) (((uint32_t)(((uint32_t)(x))<<AHB_OVERLAY_REGION2_MASK_REGION2_MASK_SHIFT))&AHB_OVERLAY_REGION2_MASK_REGION2_MASK_MASK)
|
||||
|
||||
/* REGION2_MASK Reg Mask */
|
||||
|
||||
#define AHB_OVERLAY_REGION2_MASK_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group AHB_OVERLAY_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group AHB_OVERLAY_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,277 @@
|
|||
#ifndef _FC7240_AONTIMER_NU_Tztufn16_REGS_H_
|
||||
#define _FC7240_AONTIMER_NU_Tztufn16_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- AONTIMER Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup AONTIMER_Peripheral_Access_Layer AONTIMER Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** AONTIMER - Size of Registers Arrays */
|
||||
|
||||
|
||||
|
||||
/** AONTIMER - Register Layout Typedef */
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
__IO uint32_t CSR ; /* Control Status Register, offset: 0x0 */
|
||||
|
||||
__IO uint32_t PSR ; /* Prescale Register, offset: 0x4 */
|
||||
|
||||
__IO uint32_t CMR ; /* Compare Register, offset: 0x8 */
|
||||
|
||||
__IO uint32_t CNR ; /* Counter Register, offset: 0xC */
|
||||
|
||||
|
||||
|
||||
} AONTIMER_Type, *AONTIMER_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the AONTIMER module. */
|
||||
|
||||
#define AONTIMER_INSTANCE_COUNT (1u)
|
||||
|
||||
|
||||
|
||||
/* AONTIMER - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral AONTIMER base address */
|
||||
|
||||
#define AONTIMER_BASE (0x4002f000u)
|
||||
|
||||
/** Peripheral AONTIMER base pointer */
|
||||
|
||||
#define AONTIMER ((AONTIMER_Type *)AONTIMER_BASE)
|
||||
|
||||
/** Array initializer of AONTIMER peripheral base addresses */
|
||||
|
||||
#define AONTIMER_BASE_ADDRS {AONTIMER_BASE}
|
||||
|
||||
/** Array initializer of AONTIMER peripheral base pointers */
|
||||
|
||||
#define AONTIMER_BASE_PTRS {AONTIMER}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the AONTIMER module. */
|
||||
|
||||
//#define AONTIMER_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the AONTIMER module. */
|
||||
|
||||
//#define AONTIMER_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the AONTIMER peripheral type */
|
||||
|
||||
//#define AONTIMER_IRQS {AONTIMER_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- AONTIMER Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup AONTIMER_Register_Masks AONTIMER Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* CSR Bit Fields */
|
||||
|
||||
#define AONTIMER_CSR_DBGEN_MASK 0x200u
|
||||
|
||||
#define AONTIMER_CSR_DBGEN_SHIFT 9u
|
||||
|
||||
#define AONTIMER_CSR_DBGEN_WIDTH 1u
|
||||
|
||||
#define AONTIMER_CSR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_DBGEN_SHIFT))&AONTIMER_CSR_DBGEN_MASK)
|
||||
|
||||
#define AONTIMER_CSR_TDRE_MASK 0x100u
|
||||
|
||||
#define AONTIMER_CSR_TDRE_SHIFT 8u
|
||||
|
||||
#define AONTIMER_CSR_TDRE_WIDTH 1u
|
||||
|
||||
#define AONTIMER_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TDRE_SHIFT))&AONTIMER_CSR_TDRE_MASK)
|
||||
|
||||
#define AONTIMER_CSR_TCF_MASK 0x80u
|
||||
|
||||
#define AONTIMER_CSR_TCF_SHIFT 7u
|
||||
|
||||
#define AONTIMER_CSR_TCF_WIDTH 1u
|
||||
|
||||
#define AONTIMER_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TCF_SHIFT))&AONTIMER_CSR_TCF_MASK)
|
||||
|
||||
#define AONTIMER_CSR_TIE_MASK 0x40u
|
||||
|
||||
#define AONTIMER_CSR_TIE_SHIFT 6u
|
||||
|
||||
#define AONTIMER_CSR_TIE_WIDTH 1u
|
||||
|
||||
#define AONTIMER_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TIE_SHIFT))&AONTIMER_CSR_TIE_MASK)
|
||||
|
||||
#define AONTIMER_CSR_TPS_MASK 0x30u
|
||||
|
||||
#define AONTIMER_CSR_TPS_SHIFT 4u
|
||||
|
||||
#define AONTIMER_CSR_TPS_WIDTH 2u
|
||||
|
||||
#define AONTIMER_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TPS_SHIFT))&AONTIMER_CSR_TPS_MASK)
|
||||
|
||||
#define AONTIMER_CSR_TPP_MASK 0x8u
|
||||
|
||||
#define AONTIMER_CSR_TPP_SHIFT 3u
|
||||
|
||||
#define AONTIMER_CSR_TPP_WIDTH 1u
|
||||
|
||||
#define AONTIMER_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TPP_SHIFT))&AONTIMER_CSR_TPP_MASK)
|
||||
|
||||
#define AONTIMER_CSR_TFC_MASK 0x4u
|
||||
|
||||
#define AONTIMER_CSR_TFC_SHIFT 2u
|
||||
|
||||
#define AONTIMER_CSR_TFC_WIDTH 1u
|
||||
|
||||
#define AONTIMER_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TFC_SHIFT))&AONTIMER_CSR_TFC_MASK)
|
||||
|
||||
#define AONTIMER_CSR_TMS_MASK 0x2u
|
||||
|
||||
#define AONTIMER_CSR_TMS_SHIFT 1u
|
||||
|
||||
#define AONTIMER_CSR_TMS_WIDTH 1u
|
||||
|
||||
#define AONTIMER_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TMS_SHIFT))&AONTIMER_CSR_TMS_MASK)
|
||||
|
||||
#define AONTIMER_CSR_TEN_MASK 0x1u
|
||||
|
||||
#define AONTIMER_CSR_TEN_SHIFT 0u
|
||||
|
||||
#define AONTIMER_CSR_TEN_WIDTH 1u
|
||||
|
||||
#define AONTIMER_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CSR_TEN_SHIFT))&AONTIMER_CSR_TEN_MASK)
|
||||
|
||||
/* CSR Reg Mask */
|
||||
|
||||
#define AONTIMER_CSR_MASK 0x000003FFu
|
||||
|
||||
|
||||
|
||||
/* PSR Bit Fields */
|
||||
|
||||
#define AONTIMER_PSR_PRESCALE_MASK 0x78u
|
||||
|
||||
#define AONTIMER_PSR_PRESCALE_SHIFT 3u
|
||||
|
||||
#define AONTIMER_PSR_PRESCALE_WIDTH 4u
|
||||
|
||||
#define AONTIMER_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_PSR_PRESCALE_SHIFT))&AONTIMER_PSR_PRESCALE_MASK)
|
||||
|
||||
#define AONTIMER_PSR_PBYP_MASK 0x4u
|
||||
|
||||
#define AONTIMER_PSR_PBYP_SHIFT 2u
|
||||
|
||||
#define AONTIMER_PSR_PBYP_WIDTH 1u
|
||||
|
||||
#define AONTIMER_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_PSR_PBYP_SHIFT))&AONTIMER_PSR_PBYP_MASK)
|
||||
|
||||
#define AONTIMER_PSR_PCS_MASK 0x3u
|
||||
|
||||
#define AONTIMER_PSR_PCS_SHIFT 0u
|
||||
|
||||
#define AONTIMER_PSR_PCS_WIDTH 2u
|
||||
|
||||
#define AONTIMER_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_PSR_PCS_SHIFT))&AONTIMER_PSR_PCS_MASK)
|
||||
|
||||
/* PSR Reg Mask */
|
||||
|
||||
#define AONTIMER_PSR_MASK 0x0000007Fu
|
||||
|
||||
|
||||
|
||||
/* CMR Bit Fields */
|
||||
|
||||
#define AONTIMER_CMR_COMPARE_MASK 0xFFFFu
|
||||
|
||||
#define AONTIMER_CMR_COMPARE_SHIFT 0u
|
||||
|
||||
#define AONTIMER_CMR_COMPARE_WIDTH 16u
|
||||
|
||||
#define AONTIMER_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CMR_COMPARE_SHIFT))&AONTIMER_CMR_COMPARE_MASK)
|
||||
|
||||
/* CMR Reg Mask */
|
||||
|
||||
#define AONTIMER_CMR_MASK 0x0000FFFFu
|
||||
|
||||
|
||||
|
||||
/* CNR Bit Fields */
|
||||
|
||||
#define AONTIMER_CNR_COUNTER_MASK 0xFFFFu
|
||||
|
||||
#define AONTIMER_CNR_COUNTER_SHIFT 0u
|
||||
|
||||
#define AONTIMER_CNR_COUNTER_WIDTH 16u
|
||||
|
||||
#define AONTIMER_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<AONTIMER_CNR_COUNTER_SHIFT))&AONTIMER_CNR_COUNTER_MASK)
|
||||
|
||||
/* CNR Reg Mask */
|
||||
|
||||
#define AONTIMER_CNR_MASK 0x0000FFFFu
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group AONTIMER_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group AONTIMER_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,773 @@
|
|||
#ifndef _FC7240_CMP_NU_Tztufn27_REGS_H_
|
||||
#define _FC7240_CMP_NU_Tztufn27_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- CMP Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** CMP - Size of Registers Arrays */
|
||||
|
||||
|
||||
|
||||
/** CMP - Register Layout Typedef */
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
uint8_t RESERVED_0[8];
|
||||
|
||||
__IO uint32_t CCR0 ; /* Comparator Control Register 0, offset: 0x8 */
|
||||
|
||||
__IO uint32_t CCR1 ; /* Comparator Control Register 1, offset: 0xC */
|
||||
|
||||
__IO uint32_t CCR2 ; /* Comparator Control Register 2, offset: 0x10 */
|
||||
|
||||
__IO uint32_t CCR3 ; /* Comparator Control Register 3, offset: 0x14 */
|
||||
|
||||
__IO uint32_t DCR ; /* Comparator DAC Control Register, offset: 0x18 */
|
||||
|
||||
__IO uint32_t IER ; /* Comparator Interrupt Enable Register, offset: 0x1C */
|
||||
|
||||
__IO uint32_t CSR ; /* Comparator Status Register, offset: 0x20 */
|
||||
|
||||
__IO uint32_t CSCR0 ; /* Channel Scan Control Register 0, offset: 0x24 */
|
||||
|
||||
__IO uint32_t CSCR1 ; /* Channel Scan Control Register 1, offset: 0x28 */
|
||||
|
||||
__IO uint32_t CSCSR ; /* Channel Scan Control and Status Register, offset: 0x2C */
|
||||
|
||||
__IO uint32_t CSSR ; /* Channel Scan Status Register, offset: 0x30 */
|
||||
|
||||
|
||||
|
||||
} CMP_Type, *CMP_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the CMP module. */
|
||||
|
||||
#define CMP_INSTANCE_COUNT (2u)
|
||||
|
||||
|
||||
|
||||
/* CMP - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral CMP0 base address */
|
||||
|
||||
#define CMP0_BASE (0x40040000u)
|
||||
|
||||
/** Peripheral CMP0 base pointer */
|
||||
|
||||
#define CMP0 ((CMP_Type *)CMP0_BASE)
|
||||
|
||||
/** Peripheral CMP1 base address */
|
||||
|
||||
#define CMP1_BASE (0x40041000u)
|
||||
|
||||
/** Peripheral CMP1 base pointer */
|
||||
|
||||
#define CMP1 ((CMP_Type *)CMP1_BASE)
|
||||
|
||||
/** Array initializer of CMP peripheral base addresses */
|
||||
|
||||
#define CMP_BASE_ADDRS {CMP0_BASE, CMP1_BASE}
|
||||
|
||||
/** Array initializer of CMP peripheral base pointers */
|
||||
|
||||
#define CMP_BASE_PTRS {CMP0, CMP1}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the CMP module. */
|
||||
|
||||
//#define CMP_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the CMP module. */
|
||||
|
||||
//#define CMP_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the CMP peripheral type */
|
||||
|
||||
//#define CMP_IRQS {CMP0_IRQn, CMP1_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- CMP Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup CMP_Register_Masks CMP Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* CCR0 Bit Fields */
|
||||
|
||||
#define CMP_CCR0_DACEN_SEL_MASK 0x4u
|
||||
|
||||
#define CMP_CCR0_DACEN_SEL_SHIFT 2u
|
||||
|
||||
#define CMP_CCR0_DACEN_SEL_WIDTH 1u
|
||||
|
||||
#define CMP_CCR0_DACEN_SEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR0_DACEN_SEL_SHIFT))&CMP_CCR0_DACEN_SEL_MASK)
|
||||
|
||||
#define CMP_CCR0_STOP_EN_MASK 0x2u
|
||||
|
||||
#define CMP_CCR0_STOP_EN_SHIFT 1u
|
||||
|
||||
#define CMP_CCR0_STOP_EN_WIDTH 1u
|
||||
|
||||
#define CMP_CCR0_STOP_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR0_STOP_EN_SHIFT))&CMP_CCR0_STOP_EN_MASK)
|
||||
|
||||
#define CMP_CCR0_EN_MASK 0x1u
|
||||
|
||||
#define CMP_CCR0_EN_SHIFT 0u
|
||||
|
||||
#define CMP_CCR0_EN_WIDTH 1u
|
||||
|
||||
#define CMP_CCR0_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR0_EN_SHIFT))&CMP_CCR0_EN_MASK)
|
||||
|
||||
/* CCR0 Reg Mask */
|
||||
|
||||
#define CMP_CCR0_MASK 0x00000007u
|
||||
|
||||
|
||||
|
||||
/* CCR1 Bit Fields */
|
||||
|
||||
#define CMP_CCR1_FILT_PER_MASK 0xFF000000u
|
||||
|
||||
#define CMP_CCR1_FILT_PER_SHIFT 24u
|
||||
|
||||
#define CMP_CCR1_FILT_PER_WIDTH 8u
|
||||
|
||||
#define CMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_FILT_PER_SHIFT))&CMP_CCR1_FILT_PER_MASK)
|
||||
|
||||
#define CMP_CCR1_FILT_CNT_MASK 0x70000u
|
||||
|
||||
#define CMP_CCR1_FILT_CNT_SHIFT 16u
|
||||
|
||||
#define CMP_CCR1_FILT_CNT_WIDTH 3u
|
||||
|
||||
#define CMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_FILT_CNT_SHIFT))&CMP_CCR1_FILT_CNT_MASK)
|
||||
|
||||
#define CMP_CCR1_EVT_SEL_MASK 0xC00u
|
||||
|
||||
#define CMP_CCR1_EVT_SEL_SHIFT 10u
|
||||
|
||||
#define CMP_CCR1_EVT_SEL_WIDTH 2u
|
||||
|
||||
#define CMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_EVT_SEL_SHIFT))&CMP_CCR1_EVT_SEL_MASK)
|
||||
|
||||
#define CMP_CCR1_WIN_CLS_MASK 0x200u
|
||||
|
||||
#define CMP_CCR1_WIN_CLS_SHIFT 9u
|
||||
|
||||
#define CMP_CCR1_WIN_CLS_WIDTH 1u
|
||||
|
||||
#define CMP_CCR1_WIN_CLS(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_WIN_CLS_SHIFT))&CMP_CCR1_WIN_CLS_MASK)
|
||||
|
||||
#define CMP_CCR1_WIN_INV_MASK 0x100u
|
||||
|
||||
#define CMP_CCR1_WIN_INV_SHIFT 8u
|
||||
|
||||
#define CMP_CCR1_WIN_INV_WIDTH 1u
|
||||
|
||||
#define CMP_CCR1_WIN_INV(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_WIN_INV_SHIFT))&CMP_CCR1_WIN_INV_MASK)
|
||||
|
||||
#define CMP_CCR1_CMPOUT_WIN_OW_MASK 0x80u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_WIN_OW_SHIFT 7u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_WIN_OW_WIDTH 1u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_WIN_OW(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_CMPOUT_WIN_OW_SHIFT))&CMP_CCR1_CMPOUT_WIN_OW_MASK)
|
||||
|
||||
#define CMP_CCR1_CMPOUT_WIN_OWEN_MASK 0x40u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_WIN_OWEN_SHIFT 6u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_WIN_OWEN_WIDTH 1u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_WIN_OWEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_CMPOUT_WIN_OWEN_SHIFT))&CMP_CCR1_CMPOUT_WIN_OWEN_MASK)
|
||||
|
||||
#define CMP_CCR1_CMPOUT_PEN_MASK 0x20u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_PEN_SHIFT 5u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_PEN_WIDTH 1u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_PEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_CMPOUT_PEN_SHIFT))&CMP_CCR1_CMPOUT_PEN_MASK)
|
||||
|
||||
#define CMP_CCR1_CMPOUT_SEL_MASK 0x10u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_SEL_SHIFT 4u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_SEL_WIDTH 1u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_SEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_CMPOUT_SEL_SHIFT))&CMP_CCR1_CMPOUT_SEL_MASK)
|
||||
|
||||
#define CMP_CCR1_CMPOUT_INV_MASK 0x8u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_INV_SHIFT 3u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_INV_WIDTH 1u
|
||||
|
||||
#define CMP_CCR1_CMPOUT_INV(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_CMPOUT_INV_SHIFT))&CMP_CCR1_CMPOUT_INV_MASK)
|
||||
|
||||
#define CMP_CCR1_DMA_EN_MASK 0x4u
|
||||
|
||||
#define CMP_CCR1_DMA_EN_SHIFT 2u
|
||||
|
||||
#define CMP_CCR1_DMA_EN_WIDTH 1u
|
||||
|
||||
#define CMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_DMA_EN_SHIFT))&CMP_CCR1_DMA_EN_MASK)
|
||||
|
||||
#define CMP_CCR1_SAMPLE_EN_MASK 0x2u
|
||||
|
||||
#define CMP_CCR1_SAMPLE_EN_SHIFT 1u
|
||||
|
||||
#define CMP_CCR1_SAMPLE_EN_WIDTH 1u
|
||||
|
||||
#define CMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_SAMPLE_EN_SHIFT))&CMP_CCR1_SAMPLE_EN_MASK)
|
||||
|
||||
#define CMP_CCR1_WIN_EN_MASK 0x1u
|
||||
|
||||
#define CMP_CCR1_WIN_EN_SHIFT 0u
|
||||
|
||||
#define CMP_CCR1_WIN_EN_WIDTH 1u
|
||||
|
||||
#define CMP_CCR1_WIN_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR1_WIN_EN_SHIFT))&CMP_CCR1_WIN_EN_MASK)
|
||||
|
||||
/* CCR1 Reg Mask */
|
||||
|
||||
#define CMP_CCR1_MASK 0xFF070FFFu
|
||||
|
||||
|
||||
|
||||
/* CCR2 Bit Fields */
|
||||
|
||||
#define CMP_CCR2_INMSEL_MASK 0x30000000u
|
||||
|
||||
#define CMP_CCR2_INMSEL_SHIFT 28u
|
||||
|
||||
#define CMP_CCR2_INMSEL_WIDTH 2u
|
||||
|
||||
#define CMP_CCR2_INMSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR2_INMSEL_SHIFT))&CMP_CCR2_INMSEL_MASK)
|
||||
|
||||
#define CMP_CCR2_INPSEL_MASK 0x3000000u
|
||||
|
||||
#define CMP_CCR2_INPSEL_SHIFT 24u
|
||||
|
||||
#define CMP_CCR2_INPSEL_WIDTH 2u
|
||||
|
||||
#define CMP_CCR2_INPSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR2_INPSEL_SHIFT))&CMP_CCR2_INPSEL_MASK)
|
||||
|
||||
#define CMP_CCR2_MSEL_MASK 0x700000u
|
||||
|
||||
#define CMP_CCR2_MSEL_SHIFT 20u
|
||||
|
||||
#define CMP_CCR2_MSEL_WIDTH 3u
|
||||
|
||||
#define CMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR2_MSEL_SHIFT))&CMP_CCR2_MSEL_MASK)
|
||||
|
||||
#define CMP_CCR2_PSEL_MASK 0x70000u
|
||||
|
||||
#define CMP_CCR2_PSEL_SHIFT 16u
|
||||
|
||||
#define CMP_CCR2_PSEL_WIDTH 3u
|
||||
|
||||
#define CMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR2_PSEL_SHIFT))&CMP_CCR2_PSEL_MASK)
|
||||
|
||||
#define CMP_CCR2_HYSTCTR_MASK 0x30u
|
||||
|
||||
#define CMP_CCR2_HYSTCTR_SHIFT 4u
|
||||
|
||||
#define CMP_CCR2_HYSTCTR_WIDTH 2u
|
||||
|
||||
#define CMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR2_HYSTCTR_SHIFT))&CMP_CCR2_HYSTCTR_MASK)
|
||||
|
||||
#define CMP_CCR2_HPMD_MASK 0x1u
|
||||
|
||||
#define CMP_CCR2_HPMD_SHIFT 0u
|
||||
|
||||
#define CMP_CCR2_HPMD_WIDTH 1u
|
||||
|
||||
#define CMP_CCR2_HPMD(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR2_HPMD_SHIFT))&CMP_CCR2_HPMD_MASK)
|
||||
|
||||
/* CCR2 Reg Mask */
|
||||
|
||||
#define CMP_CCR2_MASK 0x33770031u
|
||||
|
||||
|
||||
|
||||
/* CCR3 Bit Fields */
|
||||
|
||||
#define CMP_CCR3_DAC_RDY_CNT_MASK 0xFFC0u
|
||||
|
||||
#define CMP_CCR3_DAC_RDY_CNT_SHIFT 6u
|
||||
|
||||
#define CMP_CCR3_DAC_RDY_CNT_WIDTH 10u
|
||||
|
||||
#define CMP_CCR3_DAC_RDY_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR3_DAC_RDY_CNT_SHIFT))&CMP_CCR3_DAC_RDY_CNT_MASK)
|
||||
|
||||
#define CMP_CCR3_DAC_TRANS_BYP_MASK 0x1u
|
||||
|
||||
#define CMP_CCR3_DAC_TRANS_BYP_SHIFT 0u
|
||||
|
||||
#define CMP_CCR3_DAC_TRANS_BYP_WIDTH 1u
|
||||
|
||||
#define CMP_CCR3_DAC_TRANS_BYP(x) (((uint32_t)(((uint32_t)(x))<<CMP_CCR3_DAC_TRANS_BYP_SHIFT))&CMP_CCR3_DAC_TRANS_BYP_MASK)
|
||||
|
||||
/* CCR3 Reg Mask */
|
||||
|
||||
#define CMP_CCR3_MASK 0x0000FFC1u
|
||||
|
||||
|
||||
|
||||
/* DCR Bit Fields */
|
||||
|
||||
#define CMP_DCR_DAC_DATA_MASK 0xFF0000u
|
||||
|
||||
#define CMP_DCR_DAC_DATA_SHIFT 16u
|
||||
|
||||
#define CMP_DCR_DAC_DATA_WIDTH 8u
|
||||
|
||||
#define CMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x))<<CMP_DCR_DAC_DATA_SHIFT))&CMP_DCR_DAC_DATA_MASK)
|
||||
|
||||
#define CMP_DCR_VRSEL_MASK 0x100u
|
||||
|
||||
#define CMP_DCR_VRSEL_SHIFT 8u
|
||||
|
||||
#define CMP_DCR_VRSEL_WIDTH 1u
|
||||
|
||||
#define CMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_DCR_VRSEL_SHIFT))&CMP_DCR_VRSEL_MASK)
|
||||
|
||||
#define CMP_DCR_DAC_EN_MASK 0x1u
|
||||
|
||||
#define CMP_DCR_DAC_EN_SHIFT 0u
|
||||
|
||||
#define CMP_DCR_DAC_EN_WIDTH 1u
|
||||
|
||||
#define CMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_DCR_DAC_EN_SHIFT))&CMP_DCR_DAC_EN_MASK)
|
||||
|
||||
/* DCR Reg Mask */
|
||||
|
||||
#define CMP_DCR_MASK 0x00FF0101u
|
||||
|
||||
|
||||
|
||||
/* IER Bit Fields */
|
||||
|
||||
#define CMP_IER_CSF_IE_MASK 0x4u
|
||||
|
||||
#define CMP_IER_CSF_IE_SHIFT 2u
|
||||
|
||||
#define CMP_IER_CSF_IE_WIDTH 1u
|
||||
|
||||
#define CMP_IER_CSF_IE(x) (((uint32_t)(((uint32_t)(x))<<CMP_IER_CSF_IE_SHIFT))&CMP_IER_CSF_IE_MASK)
|
||||
|
||||
#define CMP_IER_CFF_IE_MASK 0x2u
|
||||
|
||||
#define CMP_IER_CFF_IE_SHIFT 1u
|
||||
|
||||
#define CMP_IER_CFF_IE_WIDTH 1u
|
||||
|
||||
#define CMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x))<<CMP_IER_CFF_IE_SHIFT))&CMP_IER_CFF_IE_MASK)
|
||||
|
||||
#define CMP_IER_CFR_IE_MASK 0x1u
|
||||
|
||||
#define CMP_IER_CFR_IE_SHIFT 0u
|
||||
|
||||
#define CMP_IER_CFR_IE_WIDTH 1u
|
||||
|
||||
#define CMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x))<<CMP_IER_CFR_IE_SHIFT))&CMP_IER_CFR_IE_MASK)
|
||||
|
||||
/* IER Reg Mask */
|
||||
|
||||
#define CMP_IER_MASK 0x00000007u
|
||||
|
||||
|
||||
|
||||
/* CSR Bit Fields */
|
||||
|
||||
#define CMP_CSR_CMPOUT_FILTER_MASK 0x100u
|
||||
|
||||
#define CMP_CSR_CMPOUT_FILTER_SHIFT 8u
|
||||
|
||||
#define CMP_CSR_CMPOUT_FILTER_WIDTH 1u
|
||||
|
||||
#define CMP_CSR_CMPOUT_FILTER(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSR_CMPOUT_FILTER_SHIFT))&CMP_CSR_CMPOUT_FILTER_MASK)
|
||||
|
||||
#define CMP_CSR_CSF_MASK 0x4u
|
||||
|
||||
#define CMP_CSR_CSF_SHIFT 2u
|
||||
|
||||
#define CMP_CSR_CSF_WIDTH 1u
|
||||
|
||||
#define CMP_CSR_CSF(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSR_CSF_SHIFT))&CMP_CSR_CSF_MASK)
|
||||
|
||||
#define CMP_CSR_CFF_MASK 0x2u
|
||||
|
||||
#define CMP_CSR_CFF_SHIFT 1u
|
||||
|
||||
#define CMP_CSR_CFF_WIDTH 1u
|
||||
|
||||
#define CMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSR_CFF_SHIFT))&CMP_CSR_CFF_MASK)
|
||||
|
||||
#define CMP_CSR_CFR_MASK 0x1u
|
||||
|
||||
#define CMP_CSR_CFR_SHIFT 0u
|
||||
|
||||
#define CMP_CSR_CFR_WIDTH 1u
|
||||
|
||||
#define CMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSR_CFR_SHIFT))&CMP_CSR_CFR_MASK)
|
||||
|
||||
/* CSR Reg Mask */
|
||||
|
||||
#define CMP_CSR_MASK 0x00000107u
|
||||
|
||||
|
||||
|
||||
/* CSCR0 Bit Fields */
|
||||
|
||||
#define CMP_CSCR0_CS_INITMOD_MASK 0x3F0000u
|
||||
|
||||
#define CMP_CSCR0_CS_INITMOD_SHIFT 16u
|
||||
|
||||
#define CMP_CSCR0_CS_INITMOD_WIDTH 6u
|
||||
|
||||
#define CMP_CSCR0_CS_INITMOD(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR0_CS_INITMOD_SHIFT))&CMP_CSCR0_CS_INITMOD_MASK)
|
||||
|
||||
#define CMP_CSCR0_CS_NSAM_MASK 0x300u
|
||||
|
||||
#define CMP_CSCR0_CS_NSAM_SHIFT 8u
|
||||
|
||||
#define CMP_CSCR0_CS_NSAM_WIDTH 2u
|
||||
|
||||
#define CMP_CSCR0_CS_NSAM(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR0_CS_NSAM_SHIFT))&CMP_CSCR0_CS_NSAM_MASK)
|
||||
|
||||
#define CMP_CSCR0_CS_EN_MASK 0x1u
|
||||
|
||||
#define CMP_CSCR0_CS_EN_SHIFT 0u
|
||||
|
||||
#define CMP_CSCR0_CS_EN_WIDTH 1u
|
||||
|
||||
#define CMP_CSCR0_CS_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR0_CS_EN_SHIFT))&CMP_CSCR0_CS_EN_MASK)
|
||||
|
||||
/* CSCR0 Reg Mask */
|
||||
|
||||
#define CMP_CSCR0_MASK 0x003F0301u
|
||||
|
||||
|
||||
|
||||
/* CSCR1 Bit Fields */
|
||||
|
||||
#define CMP_CSCR1_FIXCH_MASK 0x700000u
|
||||
|
||||
#define CMP_CSCR1_FIXCH_SHIFT 20u
|
||||
|
||||
#define CMP_CSCR1_FIXCH_WIDTH 3u
|
||||
|
||||
#define CMP_CSCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_FIXCH_SHIFT))&CMP_CSCR1_FIXCH_MASK)
|
||||
|
||||
#define CMP_CSCR1_FIXP_MASK 0x10000u
|
||||
|
||||
#define CMP_CSCR1_FIXP_SHIFT 16u
|
||||
|
||||
#define CMP_CSCR1_FIXP_WIDTH 1u
|
||||
|
||||
#define CMP_CSCR1_FIXP(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_FIXP_SHIFT))&CMP_CSCR1_FIXP_MASK)
|
||||
|
||||
#define CMP_CSCR1_CS_CH7EN_MASK 0x80u
|
||||
|
||||
#define CMP_CSCR1_CS_CH7EN_SHIFT 7u
|
||||
|
||||
#define CMP_CSCR1_CS_CH7EN_WIDTH 1u
|
||||
|
||||
#define CMP_CSCR1_CS_CH7EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH7EN_SHIFT))&CMP_CSCR1_CS_CH7EN_MASK)
|
||||
|
||||
#define CMP_CSCR1_CS_CH6EN_MASK 0x40u
|
||||
|
||||
#define CMP_CSCR1_CS_CH6EN_SHIFT 6u
|
||||
|
||||
#define CMP_CSCR1_CS_CH6EN_WIDTH 1u
|
||||
|
||||
#define CMP_CSCR1_CS_CH6EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH6EN_SHIFT))&CMP_CSCR1_CS_CH6EN_MASK)
|
||||
|
||||
#define CMP_CSCR1_CS_CH5EN_MASK 0x20u
|
||||
|
||||
#define CMP_CSCR1_CS_CH5EN_SHIFT 5u
|
||||
|
||||
#define CMP_CSCR1_CS_CH5EN_WIDTH 1u
|
||||
|
||||
#define CMP_CSCR1_CS_CH5EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH5EN_SHIFT))&CMP_CSCR1_CS_CH5EN_MASK)
|
||||
|
||||
#define CMP_CSCR1_CS_CH4EN_MASK 0x10u
|
||||
|
||||
#define CMP_CSCR1_CS_CH4EN_SHIFT 4u
|
||||
|
||||
#define CMP_CSCR1_CS_CH4EN_WIDTH 1u
|
||||
|
||||
#define CMP_CSCR1_CS_CH4EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH4EN_SHIFT))&CMP_CSCR1_CS_CH4EN_MASK)
|
||||
|
||||
#define CMP_CSCR1_CS_CH3EN_MASK 0x8u
|
||||
|
||||
#define CMP_CSCR1_CS_CH3EN_SHIFT 3u
|
||||
|
||||
#define CMP_CSCR1_CS_CH3EN_WIDTH 1u
|
||||
|
||||
#define CMP_CSCR1_CS_CH3EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH3EN_SHIFT))&CMP_CSCR1_CS_CH3EN_MASK)
|
||||
|
||||
#define CMP_CSCR1_CS_CH2EN_MASK 0x4u
|
||||
|
||||
#define CMP_CSCR1_CS_CH2EN_SHIFT 2u
|
||||
|
||||
#define CMP_CSCR1_CS_CH2EN_WIDTH 1u
|
||||
|
||||
#define CMP_CSCR1_CS_CH2EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH2EN_SHIFT))&CMP_CSCR1_CS_CH2EN_MASK)
|
||||
|
||||
#define CMP_CSCR1_CS_CH1EN_MASK 0x2u
|
||||
|
||||
#define CMP_CSCR1_CS_CH1EN_SHIFT 1u
|
||||
|
||||
#define CMP_CSCR1_CS_CH1EN_WIDTH 1u
|
||||
|
||||
#define CMP_CSCR1_CS_CH1EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH1EN_SHIFT))&CMP_CSCR1_CS_CH1EN_MASK)
|
||||
|
||||
#define CMP_CSCR1_CS_CH0EN_MASK 0x1u
|
||||
|
||||
#define CMP_CSCR1_CS_CH0EN_SHIFT 0u
|
||||
|
||||
#define CMP_CSCR1_CS_CH0EN_WIDTH 1u
|
||||
|
||||
#define CMP_CSCR1_CS_CH0EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCR1_CS_CH0EN_SHIFT))&CMP_CSCR1_CS_CH0EN_MASK)
|
||||
|
||||
/* CSCR1 Reg Mask */
|
||||
|
||||
#define CMP_CSCR1_MASK 0x007100FFu
|
||||
|
||||
|
||||
|
||||
/* CSCSR Bit Fields */
|
||||
|
||||
#define CMP_CSCSR_CS_SWCLR_MASK 0x20000u
|
||||
|
||||
#define CMP_CSCSR_CS_SWCLR_SHIFT 17u
|
||||
|
||||
#define CMP_CSCSR_CS_SWCLR_WIDTH 1u
|
||||
|
||||
#define CMP_CSCSR_CS_SWCLR(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_SWCLR_SHIFT))&CMP_CSCSR_CS_SWCLR_MASK)
|
||||
|
||||
#define CMP_CSCSR_CS_ACLR_MASK 0x10000u
|
||||
|
||||
#define CMP_CSCSR_CS_ACLR_SHIFT 16u
|
||||
|
||||
#define CMP_CSCSR_CS_ACLR_WIDTH 1u
|
||||
|
||||
#define CMP_CSCSR_CS_ACLR(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_ACLR_SHIFT))&CMP_CSCSR_CS_ACLR_MASK)
|
||||
|
||||
#define CMP_CSCSR_CS_CH7OUT_MASK 0x80u
|
||||
|
||||
#define CMP_CSCSR_CS_CH7OUT_SHIFT 7u
|
||||
|
||||
#define CMP_CSCSR_CS_CH7OUT_WIDTH 1u
|
||||
|
||||
#define CMP_CSCSR_CS_CH7OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH7OUT_SHIFT))&CMP_CSCSR_CS_CH7OUT_MASK)
|
||||
|
||||
#define CMP_CSCSR_CS_CH6OUT_MASK 0x40u
|
||||
|
||||
#define CMP_CSCSR_CS_CH6OUT_SHIFT 6u
|
||||
|
||||
#define CMP_CSCSR_CS_CH6OUT_WIDTH 1u
|
||||
|
||||
#define CMP_CSCSR_CS_CH6OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH6OUT_SHIFT))&CMP_CSCSR_CS_CH6OUT_MASK)
|
||||
|
||||
#define CMP_CSCSR_CS_CH5OUT_MASK 0x20u
|
||||
|
||||
#define CMP_CSCSR_CS_CH5OUT_SHIFT 5u
|
||||
|
||||
#define CMP_CSCSR_CS_CH5OUT_WIDTH 1u
|
||||
|
||||
#define CMP_CSCSR_CS_CH5OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH5OUT_SHIFT))&CMP_CSCSR_CS_CH5OUT_MASK)
|
||||
|
||||
#define CMP_CSCSR_CS_CH4OUT_MASK 0x10u
|
||||
|
||||
#define CMP_CSCSR_CS_CH4OUT_SHIFT 4u
|
||||
|
||||
#define CMP_CSCSR_CS_CH4OUT_WIDTH 1u
|
||||
|
||||
#define CMP_CSCSR_CS_CH4OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH4OUT_SHIFT))&CMP_CSCSR_CS_CH4OUT_MASK)
|
||||
|
||||
#define CMP_CSCSR_CS_CH3OUT_MASK 0x8u
|
||||
|
||||
#define CMP_CSCSR_CS_CH3OUT_SHIFT 3u
|
||||
|
||||
#define CMP_CSCSR_CS_CH3OUT_WIDTH 1u
|
||||
|
||||
#define CMP_CSCSR_CS_CH3OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH3OUT_SHIFT))&CMP_CSCSR_CS_CH3OUT_MASK)
|
||||
|
||||
#define CMP_CSCSR_CS_CH2OUT_MASK 0x4u
|
||||
|
||||
#define CMP_CSCSR_CS_CH2OUT_SHIFT 2u
|
||||
|
||||
#define CMP_CSCSR_CS_CH2OUT_WIDTH 1u
|
||||
|
||||
#define CMP_CSCSR_CS_CH2OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH2OUT_SHIFT))&CMP_CSCSR_CS_CH2OUT_MASK)
|
||||
|
||||
#define CMP_CSCSR_CS_CH1OUT_MASK 0x2u
|
||||
|
||||
#define CMP_CSCSR_CS_CH1OUT_SHIFT 1u
|
||||
|
||||
#define CMP_CSCSR_CS_CH1OUT_WIDTH 1u
|
||||
|
||||
#define CMP_CSCSR_CS_CH1OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH1OUT_SHIFT))&CMP_CSCSR_CS_CH1OUT_MASK)
|
||||
|
||||
#define CMP_CSCSR_CS_CH0OUT_MASK 0x1u
|
||||
|
||||
#define CMP_CSCSR_CS_CH0OUT_SHIFT 0u
|
||||
|
||||
#define CMP_CSCSR_CS_CH0OUT_WIDTH 1u
|
||||
|
||||
#define CMP_CSCSR_CS_CH0OUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSCSR_CS_CH0OUT_SHIFT))&CMP_CSCSR_CS_CH0OUT_MASK)
|
||||
|
||||
/* CSCSR Reg Mask */
|
||||
|
||||
#define CMP_CSCSR_MASK 0x000300FFu
|
||||
|
||||
|
||||
|
||||
/* CSSR Bit Fields */
|
||||
|
||||
#define CMP_CSSR_CS_ACTIVE_MASK 0x10000u
|
||||
|
||||
#define CMP_CSSR_CS_ACTIVE_SHIFT 16u
|
||||
|
||||
#define CMP_CSSR_CS_ACTIVE_WIDTH 1u
|
||||
|
||||
#define CMP_CSSR_CS_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_ACTIVE_SHIFT))&CMP_CSSR_CS_ACTIVE_MASK)
|
||||
|
||||
#define CMP_CSSR_CS_CH7F_MASK 0x80u
|
||||
|
||||
#define CMP_CSSR_CS_CH7F_SHIFT 7u
|
||||
|
||||
#define CMP_CSSR_CS_CH7F_WIDTH 1u
|
||||
|
||||
#define CMP_CSSR_CS_CH7F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH7F_SHIFT))&CMP_CSSR_CS_CH7F_MASK)
|
||||
|
||||
#define CMP_CSSR_CS_CH6F_MASK 0x40u
|
||||
|
||||
#define CMP_CSSR_CS_CH6F_SHIFT 6u
|
||||
|
||||
#define CMP_CSSR_CS_CH6F_WIDTH 1u
|
||||
|
||||
#define CMP_CSSR_CS_CH6F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH6F_SHIFT))&CMP_CSSR_CS_CH6F_MASK)
|
||||
|
||||
#define CMP_CSSR_CS_CH5F_MASK 0x20u
|
||||
|
||||
#define CMP_CSSR_CS_CH5F_SHIFT 5u
|
||||
|
||||
#define CMP_CSSR_CS_CH5F_WIDTH 1u
|
||||
|
||||
#define CMP_CSSR_CS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH5F_SHIFT))&CMP_CSSR_CS_CH5F_MASK)
|
||||
|
||||
#define CMP_CSSR_CS_CH4F_MASK 0x10u
|
||||
|
||||
#define CMP_CSSR_CS_CH4F_SHIFT 4u
|
||||
|
||||
#define CMP_CSSR_CS_CH4F_WIDTH 1u
|
||||
|
||||
#define CMP_CSSR_CS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH4F_SHIFT))&CMP_CSSR_CS_CH4F_MASK)
|
||||
|
||||
#define CMP_CSSR_CS_CH3F_MASK 0x8u
|
||||
|
||||
#define CMP_CSSR_CS_CH3F_SHIFT 3u
|
||||
|
||||
#define CMP_CSSR_CS_CH3F_WIDTH 1u
|
||||
|
||||
#define CMP_CSSR_CS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH3F_SHIFT))&CMP_CSSR_CS_CH3F_MASK)
|
||||
|
||||
#define CMP_CSSR_CS_CH2F_MASK 0x4u
|
||||
|
||||
#define CMP_CSSR_CS_CH2F_SHIFT 2u
|
||||
|
||||
#define CMP_CSSR_CS_CH2F_WIDTH 1u
|
||||
|
||||
#define CMP_CSSR_CS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH2F_SHIFT))&CMP_CSSR_CS_CH2F_MASK)
|
||||
|
||||
#define CMP_CSSR_CS_CH1F_MASK 0x2u
|
||||
|
||||
#define CMP_CSSR_CS_CH1F_SHIFT 1u
|
||||
|
||||
#define CMP_CSSR_CS_CH1F_WIDTH 1u
|
||||
|
||||
#define CMP_CSSR_CS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH1F_SHIFT))&CMP_CSSR_CS_CH1F_MASK)
|
||||
|
||||
#define CMP_CSSR_CS_CH0F_MASK 0x1u
|
||||
|
||||
#define CMP_CSSR_CS_CH0F_SHIFT 0u
|
||||
|
||||
#define CMP_CSSR_CS_CH0F_WIDTH 1u
|
||||
|
||||
#define CMP_CSSR_CS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<CMP_CSSR_CS_CH0F_SHIFT))&CMP_CSSR_CS_CH0F_MASK)
|
||||
|
||||
/* CSSR Reg Mask */
|
||||
|
||||
#define CMP_CSSR_MASK 0x000100FFu
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group CMP_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group CMP_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,351 @@
|
|||
#ifndef _FC7240_CMU_NU_Tztufn2_REGS_H_
|
||||
#define _FC7240_CMU_NU_Tztufn2_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- CMU Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup CMU_Peripheral_Access_Layer CMU Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** CMU - Size of Registers Arrays */
|
||||
|
||||
|
||||
|
||||
/** CMU - Register Layout Typedef */
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
uint8_t RESERVED_0[8];
|
||||
|
||||
__IO uint32_t CTRL ; /* Control Register, offset: 0x8 */
|
||||
|
||||
uint8_t RESERVED_1[4];
|
||||
|
||||
__IO uint32_t MIN ; /* Minimum Threshold Register, offset: 0x10 */
|
||||
|
||||
__IO uint32_t MAX ; /* Maximum Threshold Register, offset: 0x14 */
|
||||
|
||||
__IO uint32_t REF_WINDOW ; /* Reference Window Register, offset: 0x18 */
|
||||
|
||||
__I uint32_t MON_CNT ; /* Monitor Counter Register, offset: 0x1C */
|
||||
|
||||
__IO uint32_t ST ; /* Status Register, offset: 0x20 */
|
||||
|
||||
__IO uint32_t PERIOD ; /* Period Monitor Mode Configuration Register, offset: 0x24 */
|
||||
|
||||
|
||||
|
||||
} CMU_Type, *CMU_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the CMU module. */
|
||||
|
||||
#define CMU_INSTANCE_COUNT (5u)
|
||||
|
||||
|
||||
|
||||
/* CMU - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral CMU0 base address */
|
||||
|
||||
#define CMU0_BASE (0x40031000u)
|
||||
|
||||
/** Peripheral CMU0 base pointer */
|
||||
|
||||
#define CMU0 ((CMU_Type *)CMU0_BASE)
|
||||
|
||||
/** Peripheral CMU1 base address */
|
||||
|
||||
#define CMU1_BASE (0x40032000u)
|
||||
|
||||
/** Peripheral CMU1 base pointer */
|
||||
|
||||
#define CMU1 ((CMU_Type *)CMU1_BASE)
|
||||
|
||||
/** Peripheral CMU2 base address */
|
||||
|
||||
#define CMU2_BASE (0x40033000u)
|
||||
|
||||
/** Peripheral CMU2 base pointer */
|
||||
|
||||
#define CMU2 ((CMU_Type *)CMU2_BASE)
|
||||
|
||||
/** Peripheral CMU3 base address */
|
||||
|
||||
#define CMU3_BASE (0x40034000u)
|
||||
|
||||
/** Peripheral CMU3 base pointer */
|
||||
|
||||
#define CMU3 ((CMU_Type *)CMU3_BASE)
|
||||
|
||||
/** Peripheral CMU4 base address */
|
||||
|
||||
#define CMU4_BASE (0x40035000u)
|
||||
|
||||
/** Peripheral CMU4 base pointer */
|
||||
|
||||
#define CMU4 ((CMU_Type *)CMU4_BASE)
|
||||
|
||||
/** Array initializer of CMU peripheral base addresses */
|
||||
|
||||
#define CMU_BASE_ADDRS {CMU0_BASE, CMU1_BASE, CMU2_BASE, CMU3_BASE, CMU4_BASE}
|
||||
|
||||
/** Array initializer of CMU peripheral base pointers */
|
||||
|
||||
#define CMU_BASE_PTRS {CMU0, CMU1, CMU2, CMU3, CMU4}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the CMU module. */
|
||||
|
||||
//#define CMU_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the CMU module. */
|
||||
|
||||
//#define CMU_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the CMU peripheral type */
|
||||
|
||||
//#define CMU_IRQS {CMU0_IRQn, CMU1_IRQn, CMU2_IRQn, CMU3_IRQn, CMU4_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- CMU Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup CMU_Register_Masks CMU Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* CTRL Bit Fields */
|
||||
|
||||
#define CMU_CTRL_REF_DIV_MASK 0x70000u
|
||||
|
||||
#define CMU_CTRL_REF_DIV_SHIFT 16u
|
||||
|
||||
#define CMU_CTRL_REF_DIV_WIDTH 3u
|
||||
|
||||
#define CMU_CTRL_REF_DIV(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_REF_DIV_SHIFT))&CMU_CTRL_REF_DIV_MASK)
|
||||
|
||||
#define CMU_CTRL_IRQ_EN_MASK 0x40u
|
||||
|
||||
#define CMU_CTRL_IRQ_EN_SHIFT 6u
|
||||
|
||||
#define CMU_CTRL_IRQ_EN_WIDTH 1u
|
||||
|
||||
#define CMU_CTRL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_IRQ_EN_SHIFT))&CMU_CTRL_IRQ_EN_MASK)
|
||||
|
||||
#define CMU_CTRL_RESTART_EN_MASK 0x20u
|
||||
|
||||
#define CMU_CTRL_RESTART_EN_SHIFT 5u
|
||||
|
||||
#define CMU_CTRL_RESTART_EN_WIDTH 1u
|
||||
|
||||
#define CMU_CTRL_RESTART_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_RESTART_EN_SHIFT))&CMU_CTRL_RESTART_EN_MASK)
|
||||
|
||||
#define CMU_CTRL_LP_EN_MASK 0x10u
|
||||
|
||||
#define CMU_CTRL_LP_EN_SHIFT 4u
|
||||
|
||||
#define CMU_CTRL_LP_EN_WIDTH 1u
|
||||
|
||||
#define CMU_CTRL_LP_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_LP_EN_SHIFT))&CMU_CTRL_LP_EN_MASK)
|
||||
|
||||
#define CMU_CTRL_STOP_EN_MASK 0x8u
|
||||
|
||||
#define CMU_CTRL_STOP_EN_SHIFT 3u
|
||||
|
||||
#define CMU_CTRL_STOP_EN_WIDTH 1u
|
||||
|
||||
#define CMU_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_STOP_EN_SHIFT))&CMU_CTRL_STOP_EN_MASK)
|
||||
|
||||
#define CMU_CTRL_SW_RST_MASK 0x2u
|
||||
|
||||
#define CMU_CTRL_SW_RST_SHIFT 1u
|
||||
|
||||
#define CMU_CTRL_SW_RST_WIDTH 1u
|
||||
|
||||
#define CMU_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_SW_RST_SHIFT))&CMU_CTRL_SW_RST_MASK)
|
||||
|
||||
#define CMU_CTRL_ENABLE_MASK 0x1u
|
||||
|
||||
#define CMU_CTRL_ENABLE_SHIFT 0u
|
||||
|
||||
#define CMU_CTRL_ENABLE_WIDTH 1u
|
||||
|
||||
#define CMU_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<CMU_CTRL_ENABLE_SHIFT))&CMU_CTRL_ENABLE_MASK)
|
||||
|
||||
/* CTRL Reg Mask */
|
||||
|
||||
#define CMU_CTRL_MASK 0x0007007Bu
|
||||
|
||||
|
||||
|
||||
/* MIN Bit Fields */
|
||||
|
||||
#define CMU_MIN_MIN_MASK 0xFFFFFFu
|
||||
|
||||
#define CMU_MIN_MIN_SHIFT 0u
|
||||
|
||||
#define CMU_MIN_MIN_WIDTH 24u
|
||||
|
||||
#define CMU_MIN_MIN(x) (((uint32_t)(((uint32_t)(x))<<CMU_MIN_MIN_SHIFT))&CMU_MIN_MIN_MASK)
|
||||
|
||||
/* MIN Reg Mask */
|
||||
|
||||
#define CMU_MIN_MASK 0x00FFFFFFu
|
||||
|
||||
|
||||
|
||||
/* MAX Bit Fields */
|
||||
|
||||
#define CMU_MAX_MAX_MASK 0xFFFFFFu
|
||||
|
||||
#define CMU_MAX_MAX_SHIFT 0u
|
||||
|
||||
#define CMU_MAX_MAX_WIDTH 24u
|
||||
|
||||
#define CMU_MAX_MAX(x) (((uint32_t)(((uint32_t)(x))<<CMU_MAX_MAX_SHIFT))&CMU_MAX_MAX_MASK)
|
||||
|
||||
/* MAX Reg Mask */
|
||||
|
||||
#define CMU_MAX_MASK 0x00FFFFFFu
|
||||
|
||||
|
||||
|
||||
/* REF_WINDOW Bit Fields */
|
||||
|
||||
#define CMU_REF_WINDOW_REF_WINDOW_MASK 0xFFFFFFu
|
||||
|
||||
#define CMU_REF_WINDOW_REF_WINDOW_SHIFT 0u
|
||||
|
||||
#define CMU_REF_WINDOW_REF_WINDOW_WIDTH 24u
|
||||
|
||||
#define CMU_REF_WINDOW_REF_WINDOW(x) (((uint32_t)(((uint32_t)(x))<<CMU_REF_WINDOW_REF_WINDOW_SHIFT))&CMU_REF_WINDOW_REF_WINDOW_MASK)
|
||||
|
||||
/* REF_WINDOW Reg Mask */
|
||||
|
||||
#define CMU_REF_WINDOW_MASK 0x00FFFFFFu
|
||||
|
||||
|
||||
|
||||
/* MON_CNT Bit Fields */
|
||||
|
||||
#define CMU_MON_CNT_MON_CNT_MASK 0xFFFFFFu
|
||||
|
||||
#define CMU_MON_CNT_MON_CNT_SHIFT 0u
|
||||
|
||||
#define CMU_MON_CNT_MON_CNT_WIDTH 24u
|
||||
|
||||
#define CMU_MON_CNT_MON_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMU_MON_CNT_MON_CNT_SHIFT))&CMU_MON_CNT_MON_CNT_MASK)
|
||||
|
||||
/* MON_CNT Reg Mask */
|
||||
|
||||
#define CMU_MON_CNT_MASK 0x00FFFFFFu
|
||||
|
||||
|
||||
|
||||
/* ST Bit Fields */
|
||||
|
||||
#define CMU_ST_LOC_MASK 0x8000u
|
||||
|
||||
#define CMU_ST_LOC_SHIFT 15u
|
||||
|
||||
#define CMU_ST_LOC_WIDTH 1u
|
||||
|
||||
#define CMU_ST_LOC(x) (((uint32_t)(((uint32_t)(x))<<CMU_ST_LOC_SHIFT))&CMU_ST_LOC_MASK)
|
||||
|
||||
#define CMU_ST_MIS_MASK 0x100u
|
||||
|
||||
#define CMU_ST_MIS_SHIFT 8u
|
||||
|
||||
#define CMU_ST_MIS_WIDTH 1u
|
||||
|
||||
#define CMU_ST_MIS(x) (((uint32_t)(((uint32_t)(x))<<CMU_ST_MIS_SHIFT))&CMU_ST_MIS_MASK)
|
||||
|
||||
/* ST Reg Mask */
|
||||
|
||||
#define CMU_ST_MASK 0x00008100u
|
||||
|
||||
|
||||
|
||||
/* PERIOD Bit Fields */
|
||||
|
||||
#define CMU_PERIOD_WINDOW_MASK 0xF0000u
|
||||
|
||||
#define CMU_PERIOD_WINDOW_SHIFT 16u
|
||||
|
||||
#define CMU_PERIOD_WINDOW_WIDTH 4u
|
||||
|
||||
#define CMU_PERIOD_WINDOW(x) (((uint32_t)(((uint32_t)(x))<<CMU_PERIOD_WINDOW_SHIFT))&CMU_PERIOD_WINDOW_MASK)
|
||||
|
||||
#define CMU_PERIOD_EN_MASK 0x1u
|
||||
|
||||
#define CMU_PERIOD_EN_SHIFT 0u
|
||||
|
||||
#define CMU_PERIOD_EN_WIDTH 1u
|
||||
|
||||
#define CMU_PERIOD_EN(x) (((uint32_t)(((uint32_t)(x))<<CMU_PERIOD_EN_SHIFT))&CMU_PERIOD_EN_MASK)
|
||||
|
||||
/* PERIOD Reg Mask */
|
||||
|
||||
#define CMU_PERIOD_MASK 0x000F0001u
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group CMU_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group CMU_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,305 @@
|
|||
#ifndef _FC7240_CORDIC_NU_Tztufn44_REGS_H_
|
||||
#define _FC7240_CORDIC_NU_Tztufn44_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- CORDIC Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup CORDIC_Peripheral_Access_Layer CORDIC Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** CORDIC - Size of Registers Arrays */
|
||||
|
||||
|
||||
|
||||
/** CORDIC - Register Layout Typedef */
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
__IO uint32_t CTRL ; /* Control Register, offset: 0x0 */
|
||||
|
||||
uint8_t RESERVED_0[12];
|
||||
|
||||
__IO uint32_t X_INPUT ; /* X-axis Input Data Register, offset: 0x10 */
|
||||
|
||||
__IO uint32_t Y_INPUT ; /* Y-axis Input Data Register, offset: 0x14 */
|
||||
|
||||
__IO uint32_t Z_INPUT ; /* Z-axis Input Data Register, offset: 0x18 */
|
||||
|
||||
uint8_t RESERVED_1[4];
|
||||
|
||||
__IO uint32_t STAT ; /* State Register, offset: 0x20 */
|
||||
|
||||
__I uint32_t X_OUTPUT ; /* X-axis Output Data Register, offset: 0x24 */
|
||||
|
||||
__I uint32_t Y_OUTPUT ; /* Y-axis Output Data Register, offset: 0x28 */
|
||||
|
||||
__I uint32_t Z_OUTPUT ; /* Z-axis Output Data Register, offset: 0x2C */
|
||||
|
||||
|
||||
|
||||
} CORDIC_Type, *CORDIC_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the CORDIC module. */
|
||||
|
||||
#define CORDIC_INSTANCE_COUNT (1u)
|
||||
|
||||
|
||||
|
||||
/* CORDIC - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral CORDIC base address */
|
||||
|
||||
#define CORDIC_BASE (0x4002b000u)
|
||||
|
||||
/** Peripheral CORDIC base pointer */
|
||||
|
||||
#define CORDIC ((CORDIC_Type *)CORDIC_BASE)
|
||||
|
||||
/** Array initializer of CORDIC peripheral base addresses */
|
||||
|
||||
#define CORDIC_BASE_ADDRS {CORDIC_BASE}
|
||||
|
||||
/** Array initializer of CORDIC peripheral base pointers */
|
||||
|
||||
#define CORDIC_BASE_PTRS {CORDIC}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the CORDIC module. */
|
||||
|
||||
//#define CORDIC_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the CORDIC module. */
|
||||
|
||||
//#define CORDIC_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the CORDIC peripheral type */
|
||||
|
||||
//#define CORDIC_IRQS {CORDIC_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- CORDIC Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup CORDIC_Register_Masks CORDIC Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* CTRL Bit Fields */
|
||||
|
||||
#define CORDIC_CTRL_IE_MASK 0x80000000u
|
||||
|
||||
#define CORDIC_CTRL_IE_SHIFT 31u
|
||||
|
||||
#define CORDIC_CTRL_IE_WIDTH 1u
|
||||
|
||||
#define CORDIC_CTRL_IE(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_CTRL_IE_SHIFT))&CORDIC_CTRL_IE_MASK)
|
||||
|
||||
#define CORDIC_CTRL_SCALE_MASK 0x380u
|
||||
|
||||
#define CORDIC_CTRL_SCALE_SHIFT 7u
|
||||
|
||||
#define CORDIC_CTRL_SCALE_WIDTH 3u
|
||||
|
||||
#define CORDIC_CTRL_SCALE(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_CTRL_SCALE_SHIFT))&CORDIC_CTRL_SCALE_MASK)
|
||||
|
||||
#define CORDIC_CTRL_ITER_MASK 0x30u
|
||||
|
||||
#define CORDIC_CTRL_ITER_SHIFT 4u
|
||||
|
||||
#define CORDIC_CTRL_ITER_WIDTH 2u
|
||||
|
||||
#define CORDIC_CTRL_ITER(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_CTRL_ITER_SHIFT))&CORDIC_CTRL_ITER_MASK)
|
||||
|
||||
#define CORDIC_CTRL_OS_MASK 0xEu
|
||||
|
||||
#define CORDIC_CTRL_OS_SHIFT 1u
|
||||
|
||||
#define CORDIC_CTRL_OS_WIDTH 3u
|
||||
|
||||
#define CORDIC_CTRL_OS(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_CTRL_OS_SHIFT))&CORDIC_CTRL_OS_MASK)
|
||||
|
||||
#define CORDIC_CTRL_MODE_MASK 0x1u
|
||||
|
||||
#define CORDIC_CTRL_MODE_SHIFT 0u
|
||||
|
||||
#define CORDIC_CTRL_MODE_WIDTH 1u
|
||||
|
||||
#define CORDIC_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_CTRL_MODE_SHIFT))&CORDIC_CTRL_MODE_MASK)
|
||||
|
||||
/* CTRL Reg Mask */
|
||||
|
||||
#define CORDIC_CTRL_MASK 0x800003BFu
|
||||
|
||||
|
||||
|
||||
/* X_INPUT Bit Fields */
|
||||
|
||||
#define CORDIC_X_INPUT_DATA_MASK 0xFFFFFFFFu
|
||||
|
||||
#define CORDIC_X_INPUT_DATA_SHIFT 0u
|
||||
|
||||
#define CORDIC_X_INPUT_DATA_WIDTH 32u
|
||||
|
||||
#define CORDIC_X_INPUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_X_INPUT_DATA_SHIFT))&CORDIC_X_INPUT_DATA_MASK)
|
||||
|
||||
/* X_INPUT Reg Mask */
|
||||
|
||||
#define CORDIC_X_INPUT_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* Y_INPUT Bit Fields */
|
||||
|
||||
#define CORDIC_Y_INPUT_DATA_MASK 0xFFFFFFFFu
|
||||
|
||||
#define CORDIC_Y_INPUT_DATA_SHIFT 0u
|
||||
|
||||
#define CORDIC_Y_INPUT_DATA_WIDTH 32u
|
||||
|
||||
#define CORDIC_Y_INPUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_Y_INPUT_DATA_SHIFT))&CORDIC_Y_INPUT_DATA_MASK)
|
||||
|
||||
/* Y_INPUT Reg Mask */
|
||||
|
||||
#define CORDIC_Y_INPUT_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* Z_INPUT Bit Fields */
|
||||
|
||||
#define CORDIC_Z_INPUT_DATA_MASK 0xFFFFFFFFu
|
||||
|
||||
#define CORDIC_Z_INPUT_DATA_SHIFT 0u
|
||||
|
||||
#define CORDIC_Z_INPUT_DATA_WIDTH 32u
|
||||
|
||||
#define CORDIC_Z_INPUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_Z_INPUT_DATA_SHIFT))&CORDIC_Z_INPUT_DATA_MASK)
|
||||
|
||||
/* Z_INPUT Reg Mask */
|
||||
|
||||
#define CORDIC_Z_INPUT_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* STAT Bit Fields */
|
||||
|
||||
#define CORDIC_STAT_DONE_MASK 0x1u
|
||||
|
||||
#define CORDIC_STAT_DONE_SHIFT 0u
|
||||
|
||||
#define CORDIC_STAT_DONE_WIDTH 1u
|
||||
|
||||
#define CORDIC_STAT_DONE(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_STAT_DONE_SHIFT))&CORDIC_STAT_DONE_MASK)
|
||||
|
||||
/* STAT Reg Mask */
|
||||
|
||||
#define CORDIC_STAT_MASK 0x00000001u
|
||||
|
||||
|
||||
|
||||
/* X_OUTPUT Bit Fields */
|
||||
|
||||
#define CORDIC_X_OUTPUT_DATA_MASK 0xFFFFFFFFu
|
||||
|
||||
#define CORDIC_X_OUTPUT_DATA_SHIFT 0u
|
||||
|
||||
#define CORDIC_X_OUTPUT_DATA_WIDTH 32u
|
||||
|
||||
#define CORDIC_X_OUTPUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_X_OUTPUT_DATA_SHIFT))&CORDIC_X_OUTPUT_DATA_MASK)
|
||||
|
||||
/* X_OUTPUT Reg Mask */
|
||||
|
||||
#define CORDIC_X_OUTPUT_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* Y_OUTPUT Bit Fields */
|
||||
|
||||
#define CORDIC_Y_OUTPUT_DATA_MASK 0xFFFFFFFFu
|
||||
|
||||
#define CORDIC_Y_OUTPUT_DATA_SHIFT 0u
|
||||
|
||||
#define CORDIC_Y_OUTPUT_DATA_WIDTH 32u
|
||||
|
||||
#define CORDIC_Y_OUTPUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_Y_OUTPUT_DATA_SHIFT))&CORDIC_Y_OUTPUT_DATA_MASK)
|
||||
|
||||
/* Y_OUTPUT Reg Mask */
|
||||
|
||||
#define CORDIC_Y_OUTPUT_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* Z_OUTPUT Bit Fields */
|
||||
|
||||
#define CORDIC_Z_OUTPUT_DATA_MASK 0xFFFFFFFFu
|
||||
|
||||
#define CORDIC_Z_OUTPUT_DATA_SHIFT 0u
|
||||
|
||||
#define CORDIC_Z_OUTPUT_DATA_WIDTH 32u
|
||||
|
||||
#define CORDIC_Z_OUTPUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<CORDIC_Z_OUTPUT_DATA_SHIFT))&CORDIC_Z_OUTPUT_DATA_MASK)
|
||||
|
||||
/* Z_OUTPUT Reg Mask */
|
||||
|
||||
#define CORDIC_Z_OUTPUT_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group CORDIC_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group CORDIC_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,354 @@
|
|||
#ifndef _FC7240_CPM_NU_Tztufn6_REGS_H_
|
||||
#define _FC7240_CPM_NU_Tztufn6_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- CPM Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup CPM_Peripheral_Access_Layer CPM Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** CPM - Size of Registers Arrays */
|
||||
|
||||
|
||||
|
||||
/** CPM - Register Layout Typedef */
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
__IO uint32_t FISCR ; /* FPU Interrupt Status and Control Register, offset: 0x0 */
|
||||
|
||||
__IO uint32_t MISCR ; /* Miscellaneous Control Register, offset: 0x4 */
|
||||
|
||||
uint8_t RESERVED_0[24];
|
||||
|
||||
__IO uint32_t TCMRCR ; /* TCM Retry Control Register, offset: 0x20 */
|
||||
|
||||
|
||||
|
||||
} CPM_Type, *CPM_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the CPM module. */
|
||||
|
||||
#define CPM_INSTANCE_COUNT (1u)
|
||||
|
||||
|
||||
|
||||
/* CPM - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral CPM base address */
|
||||
|
||||
#define CPM_BASE (0xE0080000u)
|
||||
|
||||
/** Peripheral CPM base pointer */
|
||||
|
||||
#define CPM ((CPM_Type *)CPM_BASE)
|
||||
|
||||
/** Array initializer of CPM peripheral base addresses */
|
||||
|
||||
#define CPM_BASE_ADDRS {CPM_BASE}
|
||||
|
||||
/** Array initializer of CPM peripheral base pointers */
|
||||
|
||||
#define CPM_BASE_PTRS {CPM}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the CPM module. */
|
||||
|
||||
//#define CPM_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the CPM module. */
|
||||
|
||||
//#define CPM_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the CPM peripheral type */
|
||||
|
||||
//#define CPM_IRQS {CPM_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- CPM Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup CPM_Register_Masks CPM Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* FISCR Bit Fields */
|
||||
|
||||
#define CPM_FISCR_FIXCE_MASK 0x200000u
|
||||
|
||||
#define CPM_FISCR_FIXCE_SHIFT 21u
|
||||
|
||||
#define CPM_FISCR_FIXCE_WIDTH 1u
|
||||
|
||||
#define CPM_FISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIXCE_SHIFT))&CPM_FISCR_FIXCE_MASK)
|
||||
|
||||
#define CPM_FISCR_FIDCE_MASK 0x100000u
|
||||
|
||||
#define CPM_FISCR_FIDCE_SHIFT 20u
|
||||
|
||||
#define CPM_FISCR_FIDCE_WIDTH 1u
|
||||
|
||||
#define CPM_FISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIDCE_SHIFT))&CPM_FISCR_FIDCE_MASK)
|
||||
|
||||
#define CPM_FISCR_FOFCE_MASK 0x80000u
|
||||
|
||||
#define CPM_FISCR_FOFCE_SHIFT 19u
|
||||
|
||||
#define CPM_FISCR_FOFCE_WIDTH 1u
|
||||
|
||||
#define CPM_FISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FOFCE_SHIFT))&CPM_FISCR_FOFCE_MASK)
|
||||
|
||||
#define CPM_FISCR_FUFCE_MASK 0x40000u
|
||||
|
||||
#define CPM_FISCR_FUFCE_SHIFT 18u
|
||||
|
||||
#define CPM_FISCR_FUFCE_WIDTH 1u
|
||||
|
||||
#define CPM_FISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FUFCE_SHIFT))&CPM_FISCR_FUFCE_MASK)
|
||||
|
||||
#define CPM_FISCR_FDZCE_MASK 0x20000u
|
||||
|
||||
#define CPM_FISCR_FDZCE_SHIFT 17u
|
||||
|
||||
#define CPM_FISCR_FDZCE_WIDTH 1u
|
||||
|
||||
#define CPM_FISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FDZCE_SHIFT))&CPM_FISCR_FDZCE_MASK)
|
||||
|
||||
#define CPM_FISCR_FIOCE_MASK 0x10000u
|
||||
|
||||
#define CPM_FISCR_FIOCE_SHIFT 16u
|
||||
|
||||
#define CPM_FISCR_FIOCE_WIDTH 1u
|
||||
|
||||
#define CPM_FISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIOCE_SHIFT))&CPM_FISCR_FIOCE_MASK)
|
||||
|
||||
#define CPM_FISCR_FIXC_MASK 0x20u
|
||||
|
||||
#define CPM_FISCR_FIXC_SHIFT 5u
|
||||
|
||||
#define CPM_FISCR_FIXC_WIDTH 1u
|
||||
|
||||
#define CPM_FISCR_FIXC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIXC_SHIFT))&CPM_FISCR_FIXC_MASK)
|
||||
|
||||
#define CPM_FISCR_FIDC_MASK 0x10u
|
||||
|
||||
#define CPM_FISCR_FIDC_SHIFT 4u
|
||||
|
||||
#define CPM_FISCR_FIDC_WIDTH 1u
|
||||
|
||||
#define CPM_FISCR_FIDC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIDC_SHIFT))&CPM_FISCR_FIDC_MASK)
|
||||
|
||||
#define CPM_FISCR_FOFC_MASK 0x8u
|
||||
|
||||
#define CPM_FISCR_FOFC_SHIFT 3u
|
||||
|
||||
#define CPM_FISCR_FOFC_WIDTH 1u
|
||||
|
||||
#define CPM_FISCR_FOFC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FOFC_SHIFT))&CPM_FISCR_FOFC_MASK)
|
||||
|
||||
#define CPM_FISCR_FUFC_MASK 0x4u
|
||||
|
||||
#define CPM_FISCR_FUFC_SHIFT 2u
|
||||
|
||||
#define CPM_FISCR_FUFC_WIDTH 1u
|
||||
|
||||
#define CPM_FISCR_FUFC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FUFC_SHIFT))&CPM_FISCR_FUFC_MASK)
|
||||
|
||||
#define CPM_FISCR_FDZC_MASK 0x2u
|
||||
|
||||
#define CPM_FISCR_FDZC_SHIFT 1u
|
||||
|
||||
#define CPM_FISCR_FDZC_WIDTH 1u
|
||||
|
||||
#define CPM_FISCR_FDZC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FDZC_SHIFT))&CPM_FISCR_FDZC_MASK)
|
||||
|
||||
#define CPM_FISCR_FIOC_MASK 0x1u
|
||||
|
||||
#define CPM_FISCR_FIOC_SHIFT 0u
|
||||
|
||||
#define CPM_FISCR_FIOC_WIDTH 1u
|
||||
|
||||
#define CPM_FISCR_FIOC(x) (((uint32_t)(((uint32_t)(x))<<CPM_FISCR_FIOC_SHIFT))&CPM_FISCR_FIOC_MASK)
|
||||
|
||||
/* FISCR Reg Mask */
|
||||
|
||||
#define CPM_FISCR_MASK 0x003F003Fu
|
||||
|
||||
|
||||
|
||||
/* MISCR Bit Fields */
|
||||
|
||||
#define CPM_MISCR_AHBS_PRIORITY_MASK 0x1u
|
||||
|
||||
#define CPM_MISCR_AHBS_PRIORITY_SHIFT 0u
|
||||
|
||||
#define CPM_MISCR_AHBS_PRIORITY_WIDTH 1u
|
||||
|
||||
#define CPM_MISCR_AHBS_PRIORITY(x) (((uint32_t)(((uint32_t)(x))<<CPM_MISCR_AHBS_PRIORITY_SHIFT))&CPM_MISCR_AHBS_PRIORITY_MASK)
|
||||
|
||||
/* MISCR Reg Mask */
|
||||
|
||||
#define CPM_MISCR_MASK 0x00000001u
|
||||
|
||||
|
||||
|
||||
/* TCMRCR Bit Fields */
|
||||
|
||||
#define CPM_TCMRCR_D1RBCLR_MASK 0x4000u
|
||||
|
||||
#define CPM_TCMRCR_D1RBCLR_SHIFT 14u
|
||||
|
||||
#define CPM_TCMRCR_D1RBCLR_WIDTH 1u
|
||||
|
||||
#define CPM_TCMRCR_D1RBCLR(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D1RBCLR_SHIFT))&CPM_TCMRCR_D1RBCLR_MASK)
|
||||
|
||||
#define CPM_TCMRCR_D0RBCLR_MASK 0x2000u
|
||||
|
||||
#define CPM_TCMRCR_D0RBCLR_SHIFT 13u
|
||||
|
||||
#define CPM_TCMRCR_D0RBCLR_WIDTH 1u
|
||||
|
||||
#define CPM_TCMRCR_D0RBCLR(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D0RBCLR_SHIFT))&CPM_TCMRCR_D0RBCLR_MASK)
|
||||
|
||||
#define CPM_TCMRCR_IRBCLR_MASK 0x1000u
|
||||
|
||||
#define CPM_TCMRCR_IRBCLR_SHIFT 12u
|
||||
|
||||
#define CPM_TCMRCR_IRBCLR_WIDTH 1u
|
||||
|
||||
#define CPM_TCMRCR_IRBCLR(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_IRBCLR_SHIFT))&CPM_TCMRCR_IRBCLR_MASK)
|
||||
|
||||
#define CPM_TCMRCR_D1RBVLD_MASK 0x400u
|
||||
|
||||
#define CPM_TCMRCR_D1RBVLD_SHIFT 10u
|
||||
|
||||
#define CPM_TCMRCR_D1RBVLD_WIDTH 1u
|
||||
|
||||
#define CPM_TCMRCR_D1RBVLD(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D1RBVLD_SHIFT))&CPM_TCMRCR_D1RBVLD_MASK)
|
||||
|
||||
#define CPM_TCMRCR_D0RBVLD_MASK 0x200u
|
||||
|
||||
#define CPM_TCMRCR_D0RBVLD_SHIFT 9u
|
||||
|
||||
#define CPM_TCMRCR_D0RBVLD_WIDTH 1u
|
||||
|
||||
#define CPM_TCMRCR_D0RBVLD(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D0RBVLD_SHIFT))&CPM_TCMRCR_D0RBVLD_MASK)
|
||||
|
||||
#define CPM_TCMRCR_IRBVLD_MASK 0x100u
|
||||
|
||||
#define CPM_TCMRCR_IRBVLD_SHIFT 8u
|
||||
|
||||
#define CPM_TCMRCR_IRBVLD_WIDTH 1u
|
||||
|
||||
#define CPM_TCMRCR_IRBVLD(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_IRBVLD_SHIFT))&CPM_TCMRCR_IRBVLD_MASK)
|
||||
|
||||
#define CPM_TCMRCR_D1RBIE_MASK 0x40u
|
||||
|
||||
#define CPM_TCMRCR_D1RBIE_SHIFT 6u
|
||||
|
||||
#define CPM_TCMRCR_D1RBIE_WIDTH 1u
|
||||
|
||||
#define CPM_TCMRCR_D1RBIE(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D1RBIE_SHIFT))&CPM_TCMRCR_D1RBIE_MASK)
|
||||
|
||||
#define CPM_TCMRCR_D0RBIE_MASK 0x20u
|
||||
|
||||
#define CPM_TCMRCR_D0RBIE_SHIFT 5u
|
||||
|
||||
#define CPM_TCMRCR_D0RBIE_WIDTH 1u
|
||||
|
||||
#define CPM_TCMRCR_D0RBIE(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D0RBIE_SHIFT))&CPM_TCMRCR_D0RBIE_MASK)
|
||||
|
||||
#define CPM_TCMRCR_IRBIE_MASK 0x10u
|
||||
|
||||
#define CPM_TCMRCR_IRBIE_SHIFT 4u
|
||||
|
||||
#define CPM_TCMRCR_IRBIE_WIDTH 1u
|
||||
|
||||
#define CPM_TCMRCR_IRBIE(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_IRBIE_SHIFT))&CPM_TCMRCR_IRBIE_MASK)
|
||||
|
||||
#define CPM_TCMRCR_D1RBAC_MASK 0x4u
|
||||
|
||||
#define CPM_TCMRCR_D1RBAC_SHIFT 2u
|
||||
|
||||
#define CPM_TCMRCR_D1RBAC_WIDTH 1u
|
||||
|
||||
#define CPM_TCMRCR_D1RBAC(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D1RBAC_SHIFT))&CPM_TCMRCR_D1RBAC_MASK)
|
||||
|
||||
#define CPM_TCMRCR_D0RBAC_MASK 0x2u
|
||||
|
||||
#define CPM_TCMRCR_D0RBAC_SHIFT 1u
|
||||
|
||||
#define CPM_TCMRCR_D0RBAC_WIDTH 1u
|
||||
|
||||
#define CPM_TCMRCR_D0RBAC(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_D0RBAC_SHIFT))&CPM_TCMRCR_D0RBAC_MASK)
|
||||
|
||||
#define CPM_TCMRCR_IRBAC_MASK 0x1u
|
||||
|
||||
#define CPM_TCMRCR_IRBAC_SHIFT 0u
|
||||
|
||||
#define CPM_TCMRCR_IRBAC_WIDTH 1u
|
||||
|
||||
#define CPM_TCMRCR_IRBAC(x) (((uint32_t)(((uint32_t)(x))<<CPM_TCMRCR_IRBAC_SHIFT))&CPM_TCMRCR_IRBAC_MASK)
|
||||
|
||||
/* TCMRCR Reg Mask */
|
||||
|
||||
#define CPM_TCMRCR_MASK 0x00007777u
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group CPM_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group CPM_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
#ifndef DRIVER_CRC_H
|
||||
#define DRIVER_CRC_H
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- CRC Peripheral Access Layer
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
/*!
|
||||
* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** CRC - Size of Registers Arrays */
|
||||
|
||||
/** CRC - Register Layout Typedef */
|
||||
|
||||
typedef struct {
|
||||
union {
|
||||
__IO uint32_t uDATA; /** CRC Data union */
|
||||
struct {
|
||||
__IO uint16_t L; /** CRC_DATAL register., offset: 0x0 */
|
||||
__IO uint16_t H; /** CRC_DATAH register., offset: 0x2 */
|
||||
} tDATA_16;
|
||||
struct {
|
||||
__IO uint8_t LL; /** CRC_DATALL register., offset: 0x0 */
|
||||
__IO uint8_t LU; /** CRC_DATALU register., offset: 0x1 */
|
||||
__IO uint8_t HL; /** CRC_DATAHL register., offset: 0x2 */
|
||||
__IO uint8_t HU; /** CRC_DATAHU register., offset: 0x3 */
|
||||
} tDATA_8;
|
||||
} DATA;
|
||||
__IO uint32_t POLY ; /* CRC Polynomial Register, offset: 0x4 */
|
||||
__IO uint32_t CR ; /* CRC Control Register, offset: 0x8 */
|
||||
__IO uint32_t SDAT ; /* CRC Data Bit Swap Register, offset: 0xC */
|
||||
} CRC_Type, *CRC_MemMapPtr;
|
||||
|
||||
/** Number of instances of the CRC module. */
|
||||
#define CRC_INSTANCE_COUNT (1u)
|
||||
|
||||
/* CRC - Peripheral instance base addresses */
|
||||
/** Peripheral CRC base address */
|
||||
#define CRC_BASE (0x4002a000u)
|
||||
/** Peripheral CRC base pointer */
|
||||
#define CRC ((CRC_Type *)CRC_BASE)
|
||||
/** Array initializer of CRC peripheral base addresses */
|
||||
#define CRC_BASE_ADDRS {CRC_BASE}
|
||||
/** Array initializer of CRC peripheral base pointers */
|
||||
#define CRC_BASE_PTRS {CRC}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- CRC Register Masks
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
/*!
|
||||
* @addtogroup CRC_Register_Masks CRC Register Masks
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DATA Bit Fields */
|
||||
#define CRC_DATA_HU_MASK 0xFF000000u
|
||||
#define CRC_DATA_HU_SHIFT 24u
|
||||
#define CRC_DATA_HU_WIDTH 8u
|
||||
#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
|
||||
#define CRC_DATA_HL_MASK 0xFF0000u
|
||||
#define CRC_DATA_HL_SHIFT 16u
|
||||
#define CRC_DATA_HL_WIDTH 8u
|
||||
#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
|
||||
#define CRC_DATA_LU_MASK 0xFF00u
|
||||
#define CRC_DATA_LU_SHIFT 8u
|
||||
#define CRC_DATA_LU_WIDTH 8u
|
||||
#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
|
||||
#define CRC_DATA_LL_MASK 0xFFu
|
||||
#define CRC_DATA_LL_SHIFT 0u
|
||||
#define CRC_DATA_LL_WIDTH 8u
|
||||
#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
|
||||
/* DATA Reg Mask */
|
||||
#define CRC_DATA_MASK 0xFFFFFFFFu
|
||||
|
||||
/* POLY Bit Fields */
|
||||
#define CRC_POLY_HIGH_MASK 0xFFFF0000u
|
||||
#define CRC_POLY_HIGH_SHIFT 16u
|
||||
#define CRC_POLY_HIGH_WIDTH 16u
|
||||
#define CRC_POLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_POLY_HIGH_SHIFT))&CRC_POLY_HIGH_MASK)
|
||||
#define CRC_POLY_LOW_MASK 0xFFFFu
|
||||
#define CRC_POLY_LOW_SHIFT 0u
|
||||
#define CRC_POLY_LOW_WIDTH 16u
|
||||
#define CRC_POLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_POLY_LOW_SHIFT))&CRC_POLY_LOW_MASK)
|
||||
/* POLY Reg Mask */
|
||||
#define CRC_POLY_MASK 0xFFFFFFFFu
|
||||
|
||||
/* CR Bit Fields */
|
||||
#define CRC_CR_DSW_MASK 0xC0000000u
|
||||
#define CRC_CR_DSW_SHIFT 30u
|
||||
#define CRC_CR_DSW_WIDTH 2u
|
||||
#define CRC_CR_DSW(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_DSW_SHIFT))&CRC_CR_DSW_MASK)
|
||||
#define CRC_CR_DSR_MASK 0x30000000u
|
||||
#define CRC_CR_DSR_SHIFT 28u
|
||||
#define CRC_CR_DSR_WIDTH 2u
|
||||
#define CRC_CR_DSR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_DSR_SHIFT))&CRC_CR_DSR_MASK)
|
||||
#define CRC_CR_TCRC8_MASK 0x8000000u
|
||||
#define CRC_CR_TCRC8_SHIFT 27u
|
||||
#define CRC_CR_TCRC8_WIDTH 1u
|
||||
#define CRC_CR_TCRC8(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_TCRC8_SHIFT))&CRC_CR_TCRC8_MASK)
|
||||
#define CRC_CR_FXOR_MASK 0x4000000u
|
||||
#define CRC_CR_FXOR_SHIFT 26u
|
||||
#define CRC_CR_FXOR_WIDTH 1u
|
||||
#define CRC_CR_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_FXOR_SHIFT))&CRC_CR_FXOR_MASK)
|
||||
#define CRC_CR_WAS_MASK 0x2000000u
|
||||
#define CRC_CR_WAS_SHIFT 25u
|
||||
#define CRC_CR_WAS_WIDTH 1u
|
||||
#define CRC_CR_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_WAS_SHIFT))&CRC_CR_WAS_MASK)
|
||||
#define CRC_CR_TCRC_MASK 0x1000000u
|
||||
#define CRC_CR_TCRC_SHIFT 24u
|
||||
#define CRC_CR_TCRC_WIDTH 1u
|
||||
#define CRC_CR_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CR_TCRC_SHIFT))&CRC_CR_TCRC_MASK)
|
||||
/* CR Reg Mask */
|
||||
#define CRC_CR_MASK 0xFF000000u
|
||||
|
||||
/* SDAT Bit Fields */
|
||||
#define CRC_SDAT_HIGH_MASK 0xFFFF0000u
|
||||
#define CRC_SDAT_HIGH_SHIFT 16u
|
||||
#define CRC_SDAT_HIGH_WIDTH 16u
|
||||
#define CRC_SDAT_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_SDAT_HIGH_SHIFT))&CRC_SDAT_HIGH_MASK)
|
||||
#define CRC_SDAT_LOW_MASK 0xFFFFu
|
||||
#define CRC_SDAT_LOW_SHIFT 0u
|
||||
#define CRC_SDAT_LOW_WIDTH 16u
|
||||
#define CRC_SDAT_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_SDAT_LOW_SHIFT))&CRC_SDAT_LOW_MASK)
|
||||
/* SDAT Reg Mask */
|
||||
#define CRC_SDAT_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/ /* end of group CRC_Register_Masks */
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/ /* end of group CRC_Peripheral_Access_Layer */
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,174 @@
|
|||
#ifndef _FC7240_DMAMUX_NU_Tztufn36_REGS_H_
|
||||
#define _FC7240_DMAMUX_NU_Tztufn36_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- DMAMUX Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** DMAMUX - Size of Registers Arrays */
|
||||
|
||||
|
||||
|
||||
/** DMAMUX - Register Layout Typedef */
|
||||
|
||||
#define DMAMUX_CHCFG_COUNT 16
|
||||
#define DMAMUX_CHTRG_TRG_COUNT 4
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
__IO uint8_t CHCFG[DMAMUX_CHCFG_COUNT] ; /* Channel N Configuration Register, offset: 0x0 */
|
||||
|
||||
uint8_t RESERVED_0[16];
|
||||
|
||||
__IO uint8_t CHTRG ; /* Channel N Trigger Register, offset: 0x20 */
|
||||
|
||||
|
||||
|
||||
} DMAMUX_Type, *DMAMUX_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the DMAMUX module. */
|
||||
|
||||
#define DMAMUX_INSTANCE_COUNT (1u)
|
||||
|
||||
|
||||
|
||||
/* DMAMUX - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral DMAMUX base address */
|
||||
|
||||
#define DMAMUX_BASE (0x4000a000u)
|
||||
|
||||
/** Peripheral DMAMUX base pointer */
|
||||
|
||||
#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
|
||||
|
||||
/** Array initializer of DMAMUX peripheral base addresses */
|
||||
|
||||
#define DMAMUX_BASE_ADDRS {DMAMUX_BASE}
|
||||
|
||||
/** Array initializer of DMAMUX peripheral base pointers */
|
||||
|
||||
#define DMAMUX_BASE_PTRS {DMAMUX}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the DMAMUX module. */
|
||||
|
||||
//#define DMAMUX_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the DMAMUX module. */
|
||||
|
||||
//#define DMAMUX_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the DMAMUX peripheral type */
|
||||
|
||||
//#define DMAMUX_IRQS {DMAMUX_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- DMAMUX Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* CHCFG Bit Fields */
|
||||
|
||||
#define DMAMUX_CHCFG_ENBL_MASK 0x80u
|
||||
|
||||
#define DMAMUX_CHCFG_ENBL_SHIFT 7u
|
||||
|
||||
#define DMAMUX_CHCFG_ENBL_WIDTH 1u
|
||||
|
||||
#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
|
||||
|
||||
#define DMAMUX_CHCFG_SOURCE_MASK 0x7Fu
|
||||
|
||||
#define DMAMUX_CHCFG_SOURCE_SHIFT 0u
|
||||
|
||||
#define DMAMUX_CHCFG_SOURCE_WIDTH 7u
|
||||
|
||||
#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
|
||||
|
||||
/* CHCFG Reg Mask */
|
||||
|
||||
#define DMAMUX_CHCFG_MASK 0xFFu
|
||||
|
||||
|
||||
|
||||
/* CHTRG Bit Fields */
|
||||
|
||||
#define DMAMUX_CHTRG_TRIG_MASK 0x1u
|
||||
|
||||
#define DMAMUX_CHTRG_TRIG_SHIFT 0u
|
||||
|
||||
#define DMAMUX_CHTRG_TRIG_WIDTH 1u
|
||||
|
||||
#define DMAMUX_CHTRG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHTRG_TRIG_SHIFT))&DMAMUX_CHTRG_TRIG_MASK)
|
||||
|
||||
/* CHTRG Reg Mask */
|
||||
|
||||
#define DMAMUX_CHTRG_MASK 0x0Fu
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group DMAMUX_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,379 @@
|
|||
#ifndef _FC7240_EIM_NU_Tztufn26_REGS_H_
|
||||
#define _FC7240_EIM_NU_Tztufn26_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- EIM Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** EIM - Size of Registers Arrays */
|
||||
|
||||
|
||||
|
||||
/** EIM - Register Layout Typedef */
|
||||
|
||||
#define EIM_CTRL_REG_COUNT 83
|
||||
|
||||
#define EIM_BUS_REG_COUNT 4
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
__IO uint32_t CR ; /* Configuration Register, offset: 0x0 */
|
||||
|
||||
uint8_t RESERVED_0[12];
|
||||
|
||||
__IO uint32_t CTRL_REG[EIM_CTRL_REG_COUNT] ; /* Channel N Control Register, offset: 0x10 */
|
||||
|
||||
uint8_t RESERVED_1[676];
|
||||
|
||||
__IO uint32_t CPU0_LOCKSTEP ; /* CPU0 LOCKSTEP Error Injection Register, offset: 0x400 */
|
||||
|
||||
uint8_t RESERVED_2[4];
|
||||
|
||||
__IO uint32_t DMA0_LOCKSTEP ; /* DMA0 LOCKSTEP Error Injection Register, offset: 0x408 */
|
||||
|
||||
uint8_t RESERVED_3[1012];
|
||||
|
||||
__IO uint32_t BUS_REG[EIM_BUS_REG_COUNT] ; /* Bus Register, offset: 0x800 */
|
||||
|
||||
|
||||
|
||||
} EIM_Type, *EIM_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the EIM module. */
|
||||
|
||||
#define EIM_INSTANCE_COUNT (1u)
|
||||
|
||||
|
||||
|
||||
/* EIM - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral EIM base address */
|
||||
|
||||
#define EIM_BASE (0x40019000u)
|
||||
|
||||
/** Peripheral EIM base pointer */
|
||||
|
||||
#define EIM ((EIM_Type *)EIM_BASE)
|
||||
|
||||
/** Array initializer of EIM peripheral base addresses */
|
||||
|
||||
#define EIM_BASE_ADDRS {EIM_BASE}
|
||||
|
||||
/** Array initializer of EIM peripheral base pointers */
|
||||
|
||||
#define EIM_BASE_PTRS {EIM}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the EIM module. */
|
||||
|
||||
//#define EIM_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the EIM module. */
|
||||
|
||||
//#define EIM_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the EIM peripheral type */
|
||||
|
||||
//#define EIM_IRQS {EIM_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- EIM Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup EIM_Register_Masks EIM Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* CR Bit Fields */
|
||||
|
||||
#define EIM_CR_GEIEN_MASK 0x1u
|
||||
|
||||
#define EIM_CR_GEIEN_SHIFT 0u
|
||||
|
||||
#define EIM_CR_GEIEN_WIDTH 1u
|
||||
|
||||
#define EIM_CR_GEIEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CR_GEIEN_SHIFT))&EIM_CR_GEIEN_MASK)
|
||||
|
||||
/* CR Reg Mask */
|
||||
|
||||
#define EIM_CR_MASK 0x00000001u
|
||||
|
||||
|
||||
|
||||
/* CTRL_REG Bit Fields */
|
||||
|
||||
#define EIM_CTRL_REG_DWP_LOCK_MASK 0x80000000u
|
||||
|
||||
#define EIM_CTRL_REG_DWP_LOCK_SHIFT 31u
|
||||
|
||||
#define EIM_CTRL_REG_DWP_LOCK_WIDTH 1u
|
||||
|
||||
#define EIM_CTRL_REG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_DWP_LOCK_SHIFT))&EIM_CTRL_REG_DWP_LOCK_MASK)
|
||||
|
||||
#define EIM_CTRL_REG_DWP_MASK 0x70000000u
|
||||
|
||||
#define EIM_CTRL_REG_DWP_SHIFT 28u
|
||||
|
||||
#define EIM_CTRL_REG_DWP_WIDTH 3u
|
||||
|
||||
#define EIM_CTRL_REG_DWP(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_DWP_SHIFT))&EIM_CTRL_REG_DWP_MASK)
|
||||
|
||||
#define EIM_CTRL_REG_BUS_SEL_MASK 0x30u
|
||||
|
||||
#define EIM_CTRL_REG_BUS_SEL_SHIFT 4u
|
||||
|
||||
#define EIM_CTRL_REG_BUS_SEL_WIDTH 2u
|
||||
|
||||
#define EIM_CTRL_REG_BUS_SEL(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_BUS_SEL_SHIFT))&EIM_CTRL_REG_BUS_SEL_MASK)
|
||||
|
||||
#define EIM_CTRL_REG_ATTREIE_MASK 0x8u
|
||||
|
||||
#define EIM_CTRL_REG_ATTREIE_SHIFT 3u
|
||||
|
||||
#define EIM_CTRL_REG_ATTREIE_WIDTH 1u
|
||||
|
||||
#define EIM_CTRL_REG_ATTREIE(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_ATTREIE_SHIFT))&EIM_CTRL_REG_ATTREIE_MASK)
|
||||
|
||||
#define EIM_CTRL_REG_ADDREIE_MASK 0x4u
|
||||
|
||||
#define EIM_CTRL_REG_ADDREIE_SHIFT 2u
|
||||
|
||||
#define EIM_CTRL_REG_ADDREIE_WIDTH 1u
|
||||
|
||||
#define EIM_CTRL_REG_ADDREIE(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_ADDREIE_SHIFT))&EIM_CTRL_REG_ADDREIE_MASK)
|
||||
|
||||
#define EIM_CTRL_REG_DATA1EIE_MASK 0x2u
|
||||
|
||||
#define EIM_CTRL_REG_DATA1EIE_SHIFT 1u
|
||||
|
||||
#define EIM_CTRL_REG_DATA1EIE_WIDTH 1u
|
||||
|
||||
#define EIM_CTRL_REG_DATA1EIE(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_DATA1EIE_SHIFT))&EIM_CTRL_REG_DATA1EIE_MASK)
|
||||
|
||||
#define EIM_CTRL_REG_DATA0EIE_MASK 0x1u
|
||||
|
||||
#define EIM_CTRL_REG_DATA0EIE_SHIFT 0u
|
||||
|
||||
#define EIM_CTRL_REG_DATA0EIE_WIDTH 1u
|
||||
|
||||
#define EIM_CTRL_REG_DATA0EIE(x) (((uint32_t)(((uint32_t)(x))<<EIM_CTRL_REG_DATA0EIE_SHIFT))&EIM_CTRL_REG_DATA0EIE_MASK)
|
||||
|
||||
/* CTRL_REG0 Reg Mask */
|
||||
|
||||
#define EIM_CTRL_REG_MASK 0xF000003Fu
|
||||
|
||||
|
||||
|
||||
/* CPU0_LOCKSTEP Bit Fields */
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_DWP_LOCK_MASK 0x80000000u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_DWP_LOCK_SHIFT 31u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_DWP_LOCK_WIDTH 1u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_DWP_LOCK_SHIFT))&EIM_CPU0_LOCKSTEP_DWP_LOCK_MASK)
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_DWP_MASK 0x70000000u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_DWP_SHIFT 28u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_DWP_WIDTH 3u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_DWP(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_DWP_SHIFT))&EIM_CPU0_LOCKSTEP_DWP_MASK)
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_MASK 0x8u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_SHIFT 3u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_WIDTH 1u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_SHIFT))&EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET_MASK)
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_MASK 0x4u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_SHIFT 2u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_WIDTH 1u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_SHIFT))&EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET_MASK)
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_MASK 0x2u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_SHIFT 1u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_WIDTH 1u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_SHIFT))&EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR_MASK)
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_MASK 0x1u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_SHIFT 0u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_WIDTH 1u
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR(x) (((uint32_t)(((uint32_t)(x))<<EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_SHIFT))&EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR_MASK)
|
||||
|
||||
/* CPU0_LOCKSTEP Reg Mask */
|
||||
|
||||
#define EIM_CPU0_LOCKSTEP_MASK 0xF000000Fu
|
||||
|
||||
|
||||
|
||||
/* DMA0_LOCKSTEP Bit Fields */
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_DWP_LOCK_MASK 0x80000000u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_DWP_LOCK_SHIFT 31u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_DWP_LOCK_WIDTH 1u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_DWP_LOCK_SHIFT))&EIM_DMA0_LOCKSTEP_DWP_LOCK_MASK)
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_DWP_MASK 0x70000000u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_DWP_SHIFT 28u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_DWP_WIDTH 3u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_DWP(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_DWP_SHIFT))&EIM_DMA0_LOCKSTEP_DWP_MASK)
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_MASK 0x8u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_SHIFT 3u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_WIDTH 1u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_SHIFT))&EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_SET_MASK)
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_MASK 0x4u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_SHIFT 2u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_WIDTH 1u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_SHIFT))&EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_SET_MASK)
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_MASK 0x2u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_SHIFT 1u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_WIDTH 1u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_SHIFT))&EIM_DMA0_LOCKSTEP_LOCKSTEP_MON0_CLR_MASK)
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_MASK 0x1u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_SHIFT 0u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_WIDTH 1u
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR(x) (((uint32_t)(((uint32_t)(x))<<EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_SHIFT))&EIM_DMA0_LOCKSTEP_LOCKSTEP_MON1_CLR_MASK)
|
||||
|
||||
/* DMA0_LOCKSTEP Reg Mask */
|
||||
|
||||
#define EIM_DMA0_LOCKSTEP_MASK 0xF000000Fu
|
||||
|
||||
|
||||
|
||||
/* BUS_REG Bit Fields */
|
||||
|
||||
#define EIM_BUS_REG_ATTR_MASK 0x1F000000u
|
||||
|
||||
#define EIM_BUS_REG_ATTR_SHIFT 24u
|
||||
|
||||
#define EIM_BUS_REG_ATTR_WIDTH 5u
|
||||
|
||||
#define EIM_BUS_REG_ATTR(x) (((uint32_t)(((uint32_t)(x))<<EIM_BUS_REG_ATTR_SHIFT))&EIM_BUS_REG_ATTR_MASK)
|
||||
|
||||
#define EIM_BUS_REG_ADDR_MASK 0x1F0000u
|
||||
|
||||
#define EIM_BUS_REG_ADDR_SHIFT 16u
|
||||
|
||||
#define EIM_BUS_REG_ADDR_WIDTH 5u
|
||||
|
||||
#define EIM_BUS_REG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<EIM_BUS_REG_ADDR_SHIFT))&EIM_BUS_REG_ADDR_MASK)
|
||||
|
||||
#define EIM_BUS_REG_DATA1_MASK 0x7F00u
|
||||
|
||||
#define EIM_BUS_REG_DATA1_SHIFT 8u
|
||||
|
||||
#define EIM_BUS_REG_DATA1_WIDTH 7u
|
||||
|
||||
#define EIM_BUS_REG_DATA1(x) (((uint32_t)(((uint32_t)(x))<<EIM_BUS_REG_DATA1_SHIFT))&EIM_BUS_REG_DATA1_MASK)
|
||||
|
||||
#define EIM_BUS_REG_DATA0_MASK 0x7Fu
|
||||
|
||||
#define EIM_BUS_REG_DATA0_SHIFT 0u
|
||||
|
||||
#define EIM_BUS_REG_DATA0_WIDTH 7u
|
||||
|
||||
#define EIM_BUS_REG_DATA0(x) (((uint32_t)(((uint32_t)(x))<<EIM_BUS_REG_DATA0_SHIFT))&EIM_BUS_REG_DATA0_MASK)
|
||||
|
||||
/* BUS_REG0 Reg Mask */
|
||||
|
||||
#define EIM_BUS_REG_MASK 0x1F1F7F7Fu
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group EIM_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group EIM_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,456 @@
|
|||
#ifndef _FC7240_FCPIT_NU_Tztufn30_REGS_H_
|
||||
#define _FC7240_FCPIT_NU_Tztufn30_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- FCPIT Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup FCPIT_Peripheral_Access_Layer FCPIT Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** FCPIT - Size of Registers Arrays */
|
||||
#define FCPIT_CHANNEL_NUM 4u
|
||||
|
||||
|
||||
/** FCPIT - Register Layout Typedef */
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
uint8_t RESERVED_0[8];
|
||||
|
||||
__IO uint32_t MCR ; /* Module Control Register, offset: 0x8 */
|
||||
|
||||
__IO uint32_t MSR ; /* Module Status Register, offset: 0xC */
|
||||
|
||||
__IO uint32_t MIER ; /* Module Interrupt Enable Register, offset: 0x10 */
|
||||
|
||||
__IO uint32_t SETTEN ; /* Set Timer Enable Register, offset: 0x14 */
|
||||
|
||||
__IO uint32_t CLRTEN ; /* Clear Timer Enable Register, offset: 0x18 */
|
||||
|
||||
uint8_t RESERVED_1[4];
|
||||
|
||||
struct
|
||||
{
|
||||
|
||||
__IO uint32_t TVAL ; /* Timer Value Register, offset: 0x20 */
|
||||
|
||||
__I uint32_t CVAL ; /* Current Timer Value Register, offset: 0x24 */
|
||||
|
||||
__IO uint32_t TCTRL ; /* Timer Control Register, offset: 0x28 */
|
||||
|
||||
uint8_t RESERVED_2[4];
|
||||
}CONTROLS[FCPIT_CHANNEL_NUM];
|
||||
|
||||
|
||||
|
||||
} FCPIT_Type, *FCPIT_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the FCPIT module. */
|
||||
|
||||
#define FCPIT_INSTANCE_COUNT (1u)
|
||||
|
||||
|
||||
#define MAX_FCPIT_CHANNEL_NUM (4u)
|
||||
|
||||
/* FCPIT - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral FCPIT base address */
|
||||
|
||||
#define FCPIT_BASE (0x4002e000u)
|
||||
|
||||
/** Peripheral FCPIT base pointer */
|
||||
|
||||
#define FCPIT ((FCPIT_Type *)FCPIT_BASE)
|
||||
|
||||
/** Array initializer of FCPIT peripheral base addresses */
|
||||
|
||||
#define FCPIT_BASE_ADDRS {FCPIT_BASE}
|
||||
|
||||
/** Array initializer of FCPIT peripheral base pointers */
|
||||
|
||||
#define FCPIT_BASE_PTRS {FCPIT}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the FCPIT module. */
|
||||
|
||||
//#define FCPIT_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the FCPIT module. */
|
||||
|
||||
//#define FCPIT_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the FCPIT peripheral type */
|
||||
|
||||
//#define FCPIT_IRQS {FCPIT_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- FCPIT Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup FCPIT_Register_Masks FCPIT Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* MCR Bit Fields */
|
||||
|
||||
#define FCPIT_MCR_DBG_EN_MASK 0x8u
|
||||
|
||||
#define FCPIT_MCR_DBG_EN_SHIFT 3u
|
||||
|
||||
#define FCPIT_MCR_DBG_EN_WIDTH 1u
|
||||
|
||||
#define FCPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MCR_DBG_EN_SHIFT))&FCPIT_MCR_DBG_EN_MASK)
|
||||
|
||||
#define FCPIT_MCR_LPM_EN_MASK 0x4u
|
||||
|
||||
#define FCPIT_MCR_LPM_EN_SHIFT 2u
|
||||
|
||||
#define FCPIT_MCR_LPM_EN_WIDTH 1u
|
||||
|
||||
#define FCPIT_MCR_LPM_EN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MCR_LPM_EN_SHIFT))&FCPIT_MCR_LPM_EN_MASK)
|
||||
|
||||
#define FCPIT_MCR_SW_RST_MASK 0x2u
|
||||
|
||||
#define FCPIT_MCR_SW_RST_SHIFT 1u
|
||||
|
||||
#define FCPIT_MCR_SW_RST_WIDTH 1u
|
||||
|
||||
#define FCPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MCR_SW_RST_SHIFT))&FCPIT_MCR_SW_RST_MASK)
|
||||
|
||||
#define FCPIT_MCR_M_CEN_MASK 0x1u
|
||||
|
||||
#define FCPIT_MCR_M_CEN_SHIFT 0u
|
||||
|
||||
#define FCPIT_MCR_M_CEN_WIDTH 1u
|
||||
|
||||
#define FCPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MCR_M_CEN_SHIFT))&FCPIT_MCR_M_CEN_MASK)
|
||||
|
||||
/* MCR Reg Mask */
|
||||
|
||||
#define FCPIT_MCR_MASK 0x0000000Fu
|
||||
|
||||
|
||||
|
||||
/* MSR Bit Fields */
|
||||
|
||||
#define FCPIT_MSR_TIF3_MASK 0x8u
|
||||
|
||||
#define FCPIT_MSR_TIF3_SHIFT 3u
|
||||
|
||||
#define FCPIT_MSR_TIF3_WIDTH 1u
|
||||
|
||||
#define FCPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MSR_TIF3_SHIFT))&FCPIT_MSR_TIF3_MASK)
|
||||
|
||||
#define FCPIT_MSR_TIF2_MASK 0x4u
|
||||
|
||||
#define FCPIT_MSR_TIF2_SHIFT 2u
|
||||
|
||||
#define FCPIT_MSR_TIF2_WIDTH 1u
|
||||
|
||||
#define FCPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MSR_TIF2_SHIFT))&FCPIT_MSR_TIF2_MASK)
|
||||
|
||||
#define FCPIT_MSR_TIF1_MASK 0x2u
|
||||
|
||||
#define FCPIT_MSR_TIF1_SHIFT 1u
|
||||
|
||||
#define FCPIT_MSR_TIF1_WIDTH 1u
|
||||
|
||||
#define FCPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MSR_TIF1_SHIFT))&FCPIT_MSR_TIF1_MASK)
|
||||
|
||||
#define FCPIT_MSR_TIF0_MASK 0x1u
|
||||
|
||||
#define FCPIT_MSR_TIF0_SHIFT 0u
|
||||
|
||||
#define FCPIT_MSR_TIF0_WIDTH 1u
|
||||
|
||||
#define FCPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MSR_TIF0_SHIFT))&FCPIT_MSR_TIF0_MASK)
|
||||
|
||||
/* MSR Reg Mask */
|
||||
|
||||
#define FCPIT_MSR_MASK 0x0000000Fu
|
||||
|
||||
|
||||
|
||||
/* MIER Bit Fields */
|
||||
|
||||
#define FCPIT_MIER_TIE3_MASK 0x8u
|
||||
|
||||
#define FCPIT_MIER_TIE3_SHIFT 3u
|
||||
|
||||
#define FCPIT_MIER_TIE3_WIDTH 1u
|
||||
|
||||
#define FCPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MIER_TIE3_SHIFT))&FCPIT_MIER_TIE3_MASK)
|
||||
|
||||
#define FCPIT_MIER_TIE2_MASK 0x4u
|
||||
|
||||
#define FCPIT_MIER_TIE2_SHIFT 2u
|
||||
|
||||
#define FCPIT_MIER_TIE2_WIDTH 1u
|
||||
|
||||
#define FCPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MIER_TIE2_SHIFT))&FCPIT_MIER_TIE2_MASK)
|
||||
|
||||
#define FCPIT_MIER_TIE1_MASK 0x2u
|
||||
|
||||
#define FCPIT_MIER_TIE1_SHIFT 1u
|
||||
|
||||
#define FCPIT_MIER_TIE1_WIDTH 1u
|
||||
|
||||
#define FCPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MIER_TIE1_SHIFT))&FCPIT_MIER_TIE1_MASK)
|
||||
|
||||
#define FCPIT_MIER_TIE0_MASK 0x1u
|
||||
|
||||
#define FCPIT_MIER_TIE0_SHIFT 0u
|
||||
|
||||
#define FCPIT_MIER_TIE0_WIDTH 1u
|
||||
|
||||
#define FCPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_MIER_TIE0_SHIFT))&FCPIT_MIER_TIE0_MASK)
|
||||
|
||||
/* MIER Reg Mask */
|
||||
|
||||
#define FCPIT_MIER_MASK 0x0000000Fu
|
||||
|
||||
|
||||
|
||||
/* SETTEN Bit Fields */
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_3_MASK 0x8u
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_3_SHIFT 3u
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_3_WIDTH 1u
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_SETTEN_SET_T_EN_3_SHIFT))&FCPIT_SETTEN_SET_T_EN_3_MASK)
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_2_MASK 0x4u
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_2_SHIFT 2u
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_2_WIDTH 1u
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_SETTEN_SET_T_EN_2_SHIFT))&FCPIT_SETTEN_SET_T_EN_2_MASK)
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_1_MASK 0x2u
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_1_SHIFT 1u
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_1_WIDTH 1u
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_SETTEN_SET_T_EN_1_SHIFT))&FCPIT_SETTEN_SET_T_EN_1_MASK)
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_0_MASK 0x1u
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_0_SHIFT 0u
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_0_WIDTH 1u
|
||||
|
||||
#define FCPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_SETTEN_SET_T_EN_0_SHIFT))&FCPIT_SETTEN_SET_T_EN_0_MASK)
|
||||
|
||||
/* SETTEN Reg Mask */
|
||||
|
||||
#define FCPIT_SETTEN_MASK 0x0000000Fu
|
||||
|
||||
|
||||
|
||||
/* CLRTEN Bit Fields */
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_3_MASK 0x8u
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_3_SHIFT 3u
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_3_WIDTH 1u
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CLRTEN_CLR_T_EN_3_SHIFT))&FCPIT_CLRTEN_CLR_T_EN_3_MASK)
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_2_MASK 0x4u
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_2_SHIFT 2u
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_2_WIDTH 1u
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CLRTEN_CLR_T_EN_2_SHIFT))&FCPIT_CLRTEN_CLR_T_EN_2_MASK)
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_1_MASK 0x2u
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_1_SHIFT 1u
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_1_WIDTH 1u
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CLRTEN_CLR_T_EN_1_SHIFT))&FCPIT_CLRTEN_CLR_T_EN_1_MASK)
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_0_MASK 0x1u
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_0_SHIFT 0u
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_0_WIDTH 1u
|
||||
|
||||
#define FCPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CLRTEN_CLR_T_EN_0_SHIFT))&FCPIT_CLRTEN_CLR_T_EN_0_MASK)
|
||||
|
||||
/* CLRTEN Reg Mask */
|
||||
|
||||
#define FCPIT_CLRTEN_MASK 0x0000000Fu
|
||||
|
||||
|
||||
|
||||
/* TVAL Bit Fields */
|
||||
|
||||
#define FCPIT_TVAL_TMR_VAL_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCPIT_TVAL_TMR_VAL_SHIFT 0u
|
||||
|
||||
#define FCPIT_TVAL_TMR_VAL_WIDTH 32u
|
||||
|
||||
#define FCPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TVAL_TMR_VAL_SHIFT))&FCPIT_TVAL_TMR_VAL_MASK)
|
||||
|
||||
/* TVAL0 Reg Mask */
|
||||
|
||||
#define FCPIT_TVAL_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* CVAL Bit Fields */
|
||||
|
||||
#define FCPIT_CVAL_TMR_CUR_VAL_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCPIT_CVAL_TMR_CUR_VAL_SHIFT 0u
|
||||
|
||||
#define FCPIT_CVAL_TMR_CUR_VAL_WIDTH 32u
|
||||
|
||||
#define FCPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_CVAL_TMR_CUR_VAL_SHIFT))&FCPIT_CVAL_TMR_CUR_VAL_MASK)
|
||||
|
||||
/* CVAL0 Reg Mask */
|
||||
|
||||
#define FCPIT_CVAL_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* TCTRL Bit Fields */
|
||||
|
||||
#define FCPIT_TCTRL_TRG_SEL_MASK 0xF000000u
|
||||
|
||||
#define FCPIT_TCTRL_TRG_SEL_SHIFT 24u
|
||||
|
||||
#define FCPIT_TCTRL_TRG_SEL_WIDTH 4u
|
||||
|
||||
#define FCPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TRG_SEL_SHIFT))&FCPIT_TCTRL_TRG_SEL_MASK)
|
||||
|
||||
#define FCPIT_TCTRL_TRG_SRC_MASK 0x800000u
|
||||
|
||||
#define FCPIT_TCTRL_TRG_SRC_SHIFT 23u
|
||||
|
||||
#define FCPIT_TCTRL_TRG_SRC_WIDTH 1u
|
||||
|
||||
#define FCPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TRG_SRC_SHIFT))&FCPIT_TCTRL_TRG_SRC_MASK)
|
||||
|
||||
#define FCPIT_TCTRL_TROT_MASK 0x40000u
|
||||
|
||||
#define FCPIT_TCTRL_TROT_SHIFT 18u
|
||||
|
||||
#define FCPIT_TCTRL_TROT_WIDTH 1u
|
||||
|
||||
#define FCPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TROT_SHIFT))&FCPIT_TCTRL_TROT_MASK)
|
||||
|
||||
#define FCPIT_TCTRL_TSOI_MASK 0x20000u
|
||||
|
||||
#define FCPIT_TCTRL_TSOI_SHIFT 17u
|
||||
|
||||
#define FCPIT_TCTRL_TSOI_WIDTH 1u
|
||||
|
||||
#define FCPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TSOI_SHIFT))&FCPIT_TCTRL_TSOI_MASK)
|
||||
|
||||
#define FCPIT_TCTRL_TSOT_MASK 0x10000u
|
||||
|
||||
#define FCPIT_TCTRL_TSOT_SHIFT 16u
|
||||
|
||||
#define FCPIT_TCTRL_TSOT_WIDTH 1u
|
||||
|
||||
#define FCPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_TSOT_SHIFT))&FCPIT_TCTRL_TSOT_MASK)
|
||||
|
||||
#define FCPIT_TCTRL_MODE_MASK 0xCu
|
||||
|
||||
#define FCPIT_TCTRL_MODE_SHIFT 2u
|
||||
|
||||
#define FCPIT_TCTRL_MODE_WIDTH 2u
|
||||
|
||||
#define FCPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_MODE_SHIFT))&FCPIT_TCTRL_MODE_MASK)
|
||||
|
||||
#define FCPIT_TCTRL_CHAIN_MASK 0x2u
|
||||
|
||||
#define FCPIT_TCTRL_CHAIN_SHIFT 1u
|
||||
|
||||
#define FCPIT_TCTRL_CHAIN_WIDTH 1u
|
||||
|
||||
#define FCPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_CHAIN_SHIFT))&FCPIT_TCTRL_CHAIN_MASK)
|
||||
|
||||
#define FCPIT_TCTRL_T_EN_MASK 0x1u
|
||||
|
||||
#define FCPIT_TCTRL_T_EN_SHIFT 0u
|
||||
|
||||
#define FCPIT_TCTRL_T_EN_WIDTH 1u
|
||||
|
||||
#define FCPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x))<<FCPIT_TCTRL_T_EN_SHIFT))&FCPIT_TCTRL_T_EN_MASK)
|
||||
|
||||
/* TCTRL0 Reg Mask */
|
||||
|
||||
#define FCPIT_TCTRL_MASK 0x0F87000Fu
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group FCPIT_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group FCPIT_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,929 @@
|
|||
#ifndef _FC7240_FCSMU_NU_Tztufn38_REGS_H_
|
||||
#define _FC7240_FCSMU_NU_Tztufn38_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- FCSMU Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup FCSMU_Peripheral_Access_Layer FCSMU Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** FCSMU - Size of Registers Arrays */
|
||||
|
||||
|
||||
|
||||
/** FCSMU - Register Layout Typedef */
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
__IO uint32_t CTRL ; /* Control Register, offset: 0x0 */
|
||||
|
||||
__O uint32_t OPRK ; /* Operation Key Register, offset: 0x4 */
|
||||
|
||||
__IO uint32_t SOCTRL ; /* Status Output Control Register, offset: 0x8 */
|
||||
|
||||
__IO uint32_t FCCR0 ; /* Fault Clear Control Register 0, offset: 0xC */
|
||||
|
||||
uint8_t RESERVED_0[12];
|
||||
|
||||
__IO uint32_t FRST0 ; /* Fault Reset Control Register 0, offset: 0x1C */
|
||||
|
||||
uint8_t RESERVED_1[12];
|
||||
|
||||
__IO uint32_t FST0 ; /* Fault Status Register, offset: 0x2C */
|
||||
|
||||
uint8_t RESERVED_2[12];
|
||||
|
||||
__O uint32_t FST_UNLK ; /* Fault Status Register Unlock Register, offset: 0x3C */
|
||||
|
||||
__IO uint32_t FE0 ; /* Fault Enable Register, offset: 0x40 */
|
||||
|
||||
uint8_t RESERVED_3[12];
|
||||
|
||||
__IO uint32_t WARNING_EN0 ; /* Warning State Enable Register 0, offset: 0x50 */
|
||||
|
||||
uint8_t RESERVED_4[12];
|
||||
|
||||
__IO uint32_t WARNING_TO ; /* Warning Timeout Interval Register, offset: 0x60 */
|
||||
|
||||
__IO uint32_t CFG_TO ; /* Configuration State Timeout Interval Register, offset: 0x64 */
|
||||
|
||||
__IO uint32_t SOUT_DIAG ; /* SOUT Diagnostic Register, offset: 0x68 */
|
||||
|
||||
__I uint32_t STATUS ; /* Status Register, offset: 0x6C */
|
||||
|
||||
__I uint32_t NTW ; /* Normal to Warning Register, offset: 0x70 */
|
||||
|
||||
__I uint32_t WTF ; /* Warning to Fault Register, offset: 0x74 */
|
||||
|
||||
__I uint32_t NTF ; /* Normal to Fault Register, offset: 0x78 */
|
||||
|
||||
__I uint32_t FTW ; /* Fault to Warning Register, offset: 0x7C */
|
||||
|
||||
uint8_t RESERVED_5[4];
|
||||
|
||||
__O uint32_t INJECT ; /* Fault Injection Register, offset: 0x84 */
|
||||
|
||||
__IO uint32_t IRQ_STAT ; /* IRQ Status Register, offset: 0x88 */
|
||||
|
||||
__IO uint32_t IRQ_EN ; /* IRQ Enable Register, offset: 0x8C */
|
||||
|
||||
uint8_t RESERVED_6[4];
|
||||
|
||||
__O uint32_t TEMP_UNLK ; /* Temporary Configuration State Unlock Register, offset: 0x94 */
|
||||
|
||||
__O uint32_t PERMNT_LOCK ; /* Permanent Configuration State Lock Register, offset: 0x98 */
|
||||
|
||||
__IO uint32_t STMR ; /* SOUT Timer Interval Register, offset: 0x9C */
|
||||
|
||||
__IO uint32_t WARNING_IEN0 ; /* Warning State Interrupt Enable Register, offset: 0xA0 */
|
||||
|
||||
uint8_t RESERVED_7[12];
|
||||
|
||||
__IO uint32_t FAULT_IEN0 ; /* Fault State Interrupt Enable Register, offset: 0xB0 */
|
||||
|
||||
uint8_t RESERVED_8[12];
|
||||
|
||||
__IO uint32_t SOUT_EN0 ; /* SOUT Enable Register, offset: 0xC0 */
|
||||
|
||||
uint8_t RESERVED_9[12];
|
||||
|
||||
__I uint32_t WARNING_TMR ; /* Warning State Timer Register, offset: 0xD0 */
|
||||
|
||||
__I uint32_t SM_TMR ; /* Safe Mode State Timer Register, offset: 0xD4 */
|
||||
|
||||
__I uint32_t CFG_TMR ; /* Configuration State Timer Register, offset: 0xD8 */
|
||||
|
||||
__I uint32_t SOUT_TMR ; /* SOUT Timer Register, offset: 0xDC */
|
||||
|
||||
__IO uint32_t CRC_CTRL ; /* CRC Control Register, offset: 0xE0 */
|
||||
|
||||
__I uint32_t CRC_RES ; /* CRC Result Register, offset: 0xE4 */
|
||||
|
||||
|
||||
|
||||
} FCSMU_Type, *FCSMU_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the FCSMU module. */
|
||||
|
||||
#define FCSMU_INSTANCE_COUNT (1u)
|
||||
|
||||
|
||||
|
||||
/* FCSMU - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral FCSMU base address */
|
||||
|
||||
#define FCSMU_BASE (0x4000f000u)
|
||||
|
||||
/** Peripheral FCSMU base pointer */
|
||||
|
||||
#define FCSMU ((FCSMU_Type *)FCSMU_BASE)
|
||||
|
||||
/** Array initializer of FCSMU peripheral base addresses */
|
||||
|
||||
#define FCSMU_BASE_ADDRS {FCSMU_BASE}
|
||||
|
||||
/** Array initializer of FCSMU peripheral base pointers */
|
||||
|
||||
#define FCSMU_BASE_PTRS {FCSMU}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the FCSMU module. */
|
||||
|
||||
//#define FCSMU_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the FCSMU module. */
|
||||
|
||||
//#define FCSMU_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the FCSMU peripheral type */
|
||||
|
||||
//#define FCSMU_IRQS {FCSMU_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- FCSMU Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup FCSMU_Register_Masks FCSMU Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* CTRL Bit Fields */
|
||||
|
||||
#define FCSMU_CTRL_DBGEN_MASK 0x200u
|
||||
|
||||
#define FCSMU_CTRL_DBGEN_SHIFT 9u
|
||||
|
||||
#define FCSMU_CTRL_DBGEN_WIDTH 1u
|
||||
|
||||
#define FCSMU_CTRL_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CTRL_DBGEN_SHIFT))&FCSMU_CTRL_DBGEN_MASK)
|
||||
|
||||
#define FCSMU_CTRL_OPS_MASK 0xC0u
|
||||
|
||||
#define FCSMU_CTRL_OPS_SHIFT 6u
|
||||
|
||||
#define FCSMU_CTRL_OPS_WIDTH 2u
|
||||
|
||||
#define FCSMU_CTRL_OPS(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CTRL_OPS_SHIFT))&FCSMU_CTRL_OPS_MASK)
|
||||
|
||||
#define FCSMU_CTRL_OPC_MASK 0x1Fu
|
||||
|
||||
#define FCSMU_CTRL_OPC_SHIFT 0u
|
||||
|
||||
#define FCSMU_CTRL_OPC_WIDTH 5u
|
||||
|
||||
#define FCSMU_CTRL_OPC(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CTRL_OPC_SHIFT))&FCSMU_CTRL_OPC_MASK)
|
||||
|
||||
/* CTRL Reg Mask */
|
||||
|
||||
#define FCSMU_CTRL_MASK 0x000002DFu
|
||||
|
||||
|
||||
|
||||
/* OPRK Bit Fields */
|
||||
|
||||
#define FCSMU_OPRK_OPKEY_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_OPRK_OPKEY_SHIFT 0u
|
||||
|
||||
#define FCSMU_OPRK_OPKEY_WIDTH 32u
|
||||
|
||||
#define FCSMU_OPRK_OPKEY(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_OPRK_OPKEY_SHIFT))&FCSMU_OPRK_OPKEY_MASK)
|
||||
|
||||
/* OPRK Reg Mask */
|
||||
|
||||
#define FCSMU_OPRK_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* SOCTRL Bit Fields */
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_PEN_MASK 0x2000000u
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_PEN_SHIFT 25u
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_PEN_WIDTH 1u
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_PEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_SOUT_PEN_SHIFT))&FCSMU_SOCTRL_SOUT_PEN_MASK)
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_CTRL_MASK 0x1800000u
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_CTRL_SHIFT 23u
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_CTRL_WIDTH 2u
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_CTRL(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_SOUT_CTRL_SHIFT))&FCSMU_SOCTRL_SOUT_CTRL_MASK)
|
||||
|
||||
#define FCSMU_SOCTRL_DIVEX_MASK 0x200000u
|
||||
|
||||
#define FCSMU_SOCTRL_DIVEX_SHIFT 21u
|
||||
|
||||
#define FCSMU_SOCTRL_DIVEX_WIDTH 1u
|
||||
|
||||
#define FCSMU_SOCTRL_DIVEX(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_DIVEX_SHIFT))&FCSMU_SOCTRL_DIVEX_MASK)
|
||||
|
||||
#define FCSMU_SOCTRL_SMRDT_MASK 0x1E0000u
|
||||
|
||||
#define FCSMU_SOCTRL_SMRDT_SHIFT 17u
|
||||
|
||||
#define FCSMU_SOCTRL_SMRDT_WIDTH 4u
|
||||
|
||||
#define FCSMU_SOCTRL_SMRDT(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_SMRDT_SHIFT))&FCSMU_SOCTRL_SMRDT_MASK)
|
||||
|
||||
#define FCSMU_SOCTRL_FASTEN_MASK 0x4000u
|
||||
|
||||
#define FCSMU_SOCTRL_FASTEN_SHIFT 14u
|
||||
|
||||
#define FCSMU_SOCTRL_FASTEN_WIDTH 1u
|
||||
|
||||
#define FCSMU_SOCTRL_FASTEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_FASTEN_SHIFT))&FCSMU_SOCTRL_FASTEN_MASK)
|
||||
|
||||
#define FCSMU_SOCTRL_POLSW_MASK 0x2000u
|
||||
|
||||
#define FCSMU_SOCTRL_POLSW_SHIFT 13u
|
||||
|
||||
#define FCSMU_SOCTRL_POLSW_WIDTH 1u
|
||||
|
||||
#define FCSMU_SOCTRL_POLSW(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_POLSW_SHIFT))&FCSMU_SOCTRL_POLSW_MASK)
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_PTC_MASK 0x1C00u
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_PTC_SHIFT 10u
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_PTC_WIDTH 3u
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_PTC(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_SOUT_PTC_SHIFT))&FCSMU_SOCTRL_SOUT_PTC_MASK)
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_DIV_MASK 0x3FFu
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_DIV_SHIFT 0u
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_DIV_WIDTH 10u
|
||||
|
||||
#define FCSMU_SOCTRL_SOUT_DIV(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOCTRL_SOUT_DIV_SHIFT))&FCSMU_SOCTRL_SOUT_DIV_MASK)
|
||||
|
||||
/* SOCTRL Reg Mask */
|
||||
|
||||
#define FCSMU_SOCTRL_MASK 0x03BE7FFFu
|
||||
|
||||
|
||||
|
||||
/* FCCR0 Bit Fields */
|
||||
|
||||
#define FCSMU_FCCR0_FCC_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_FCCR0_FCC_SHIFT 0u
|
||||
|
||||
#define FCSMU_FCCR0_FCC_WIDTH 32u
|
||||
|
||||
#define FCSMU_FCCR0_FCC(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FCCR0_FCC_SHIFT))&FCSMU_FCCR0_FCC_MASK)
|
||||
|
||||
/* FCCR0 Reg Mask */
|
||||
|
||||
#define FCSMU_FCCR0_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* FRST0 Bit Fields */
|
||||
|
||||
#define FCSMU_FRST0_FRST_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_FRST0_FRST_SHIFT 0u
|
||||
|
||||
#define FCSMU_FRST0_FRST_WIDTH 32u
|
||||
|
||||
#define FCSMU_FRST0_FRST(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FRST0_FRST_SHIFT))&FCSMU_FRST0_FRST_MASK)
|
||||
|
||||
/* FRST0 Reg Mask */
|
||||
|
||||
#define FCSMU_FRST0_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* FST0 Bit Fields */
|
||||
|
||||
#define FCSMU_FST0_ST_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_FST0_ST_SHIFT 0u
|
||||
|
||||
#define FCSMU_FST0_ST_WIDTH 32u
|
||||
|
||||
#define FCSMU_FST0_ST(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FST0_ST_SHIFT))&FCSMU_FST0_ST_MASK)
|
||||
|
||||
/* FST0 Reg Mask */
|
||||
|
||||
#define FCSMU_FST0_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* FST_UNLK Bit Fields */
|
||||
|
||||
#define FCSMU_FST_UNLK_KEY_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_FST_UNLK_KEY_SHIFT 0u
|
||||
|
||||
#define FCSMU_FST_UNLK_KEY_WIDTH 32u
|
||||
|
||||
#define FCSMU_FST_UNLK_KEY(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FST_UNLK_KEY_SHIFT))&FCSMU_FST_UNLK_KEY_MASK)
|
||||
|
||||
/* FST_UNLK Reg Mask */
|
||||
|
||||
#define FCSMU_FST_UNLK_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* FE0 Bit Fields */
|
||||
|
||||
#define FCSMU_FE0_EN_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_FE0_EN_SHIFT 0u
|
||||
|
||||
#define FCSMU_FE0_EN_WIDTH 32u
|
||||
|
||||
#define FCSMU_FE0_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FE0_EN_SHIFT))&FCSMU_FE0_EN_MASK)
|
||||
|
||||
/* FE0 Reg Mask */
|
||||
|
||||
#define FCSMU_FE0_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* WARNING_EN0 Bit Fields */
|
||||
|
||||
#define FCSMU_WARNING_EN0_EN_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_WARNING_EN0_EN_SHIFT 0u
|
||||
|
||||
#define FCSMU_WARNING_EN0_EN_WIDTH 32u
|
||||
|
||||
#define FCSMU_WARNING_EN0_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_WARNING_EN0_EN_SHIFT))&FCSMU_WARNING_EN0_EN_MASK)
|
||||
|
||||
/* WARNING_EN0 Reg Mask */
|
||||
|
||||
#define FCSMU_WARNING_EN0_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* WARNING_TO Bit Fields */
|
||||
|
||||
#define FCSMU_WARNING_TO_TIME_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_WARNING_TO_TIME_SHIFT 0u
|
||||
|
||||
#define FCSMU_WARNING_TO_TIME_WIDTH 32u
|
||||
|
||||
#define FCSMU_WARNING_TO_TIME(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_WARNING_TO_TIME_SHIFT))&FCSMU_WARNING_TO_TIME_MASK)
|
||||
|
||||
/* WARNING_TO Reg Mask */
|
||||
|
||||
#define FCSMU_WARNING_TO_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* CFG_TO Bit Fields */
|
||||
|
||||
#define FCSMU_CFG_TO_TIME_MASK 0x7u
|
||||
|
||||
#define FCSMU_CFG_TO_TIME_SHIFT 0u
|
||||
|
||||
#define FCSMU_CFG_TO_TIME_WIDTH 3u
|
||||
|
||||
#define FCSMU_CFG_TO_TIME(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CFG_TO_TIME_SHIFT))&FCSMU_CFG_TO_TIME_MASK)
|
||||
|
||||
/* CFG_TO Reg Mask */
|
||||
|
||||
#define FCSMU_CFG_TO_MASK 0x00000007u
|
||||
|
||||
|
||||
|
||||
/* SOUT_DIAG Bit Fields */
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SIN1_MASK 0x20u
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SIN1_SHIFT 5u
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SIN1_WIDTH 1u
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SIN1(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOUT_DIAG_SIN1_SHIFT))&FCSMU_SOUT_DIAG_SIN1_MASK)
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SIN0_MASK 0x10u
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SIN0_SHIFT 4u
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SIN0_WIDTH 1u
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SIN0(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOUT_DIAG_SIN0_SHIFT))&FCSMU_SOUT_DIAG_SIN0_MASK)
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SOUT1_MASK 0x2u
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SOUT1_SHIFT 1u
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SOUT1_WIDTH 1u
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SOUT1(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOUT_DIAG_SOUT1_SHIFT))&FCSMU_SOUT_DIAG_SOUT1_MASK)
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SOUT0_MASK 0x1u
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SOUT0_SHIFT 0u
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SOUT0_WIDTH 1u
|
||||
|
||||
#define FCSMU_SOUT_DIAG_SOUT0(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOUT_DIAG_SOUT0_SHIFT))&FCSMU_SOUT_DIAG_SOUT0_MASK)
|
||||
|
||||
/* SOUT_DIAG Reg Mask */
|
||||
|
||||
#define FCSMU_SOUT_DIAG_MASK 0x00000033u
|
||||
|
||||
|
||||
|
||||
/* STATUS Bit Fields */
|
||||
|
||||
#define FCSMU_STATUS_SOUTPIN_MASK 0x30u
|
||||
|
||||
#define FCSMU_STATUS_SOUTPIN_SHIFT 4u
|
||||
|
||||
#define FCSMU_STATUS_SOUTPIN_WIDTH 2u
|
||||
|
||||
#define FCSMU_STATUS_SOUTPIN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_STATUS_SOUTPIN_SHIFT))&FCSMU_STATUS_SOUTPIN_MASK)
|
||||
|
||||
#define FCSMU_STATUS_FIF_MASK 0x8u
|
||||
|
||||
#define FCSMU_STATUS_FIF_SHIFT 3u
|
||||
|
||||
#define FCSMU_STATUS_FIF_WIDTH 1u
|
||||
|
||||
#define FCSMU_STATUS_FIF(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_STATUS_FIF_SHIFT))&FCSMU_STATUS_FIF_MASK)
|
||||
|
||||
#define FCSMU_STATUS_STAT_MASK 0x7u
|
||||
|
||||
#define FCSMU_STATUS_STAT_SHIFT 0u
|
||||
|
||||
#define FCSMU_STATUS_STAT_WIDTH 3u
|
||||
|
||||
#define FCSMU_STATUS_STAT(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_STATUS_STAT_SHIFT))&FCSMU_STATUS_STAT_MASK)
|
||||
|
||||
/* STATUS Reg Mask */
|
||||
|
||||
#define FCSMU_STATUS_MASK 0x0000003Fu
|
||||
|
||||
|
||||
|
||||
/* NTW Bit Fields */
|
||||
|
||||
#define FCSMU_NTW_INDEX_MASK 0xFFu
|
||||
|
||||
#define FCSMU_NTW_INDEX_SHIFT 0u
|
||||
|
||||
#define FCSMU_NTW_INDEX_WIDTH 8u
|
||||
|
||||
#define FCSMU_NTW_INDEX(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_NTW_INDEX_SHIFT))&FCSMU_NTW_INDEX_MASK)
|
||||
|
||||
/* NTW Reg Mask */
|
||||
|
||||
#define FCSMU_NTW_MASK 0x000000FFu
|
||||
|
||||
|
||||
|
||||
/* WTF Bit Fields */
|
||||
|
||||
#define FCSMU_WTF_FLAG_MASK 0x200u
|
||||
|
||||
#define FCSMU_WTF_FLAG_SHIFT 9u
|
||||
|
||||
#define FCSMU_WTF_FLAG_WIDTH 1u
|
||||
|
||||
#define FCSMU_WTF_FLAG(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_WTF_FLAG_SHIFT))&FCSMU_WTF_FLAG_MASK)
|
||||
|
||||
#define FCSMU_WTF_INDEX_MASK 0xFFu
|
||||
|
||||
#define FCSMU_WTF_INDEX_SHIFT 0u
|
||||
|
||||
#define FCSMU_WTF_INDEX_WIDTH 8u
|
||||
|
||||
#define FCSMU_WTF_INDEX(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_WTF_INDEX_SHIFT))&FCSMU_WTF_INDEX_MASK)
|
||||
|
||||
/* WTF Reg Mask */
|
||||
|
||||
#define FCSMU_WTF_MASK 0x000002FFu
|
||||
|
||||
|
||||
|
||||
/* NTF Bit Fields */
|
||||
|
||||
#define FCSMU_NTF_FLAG_MASK 0x200u
|
||||
|
||||
#define FCSMU_NTF_FLAG_SHIFT 9u
|
||||
|
||||
#define FCSMU_NTF_FLAG_WIDTH 1u
|
||||
|
||||
#define FCSMU_NTF_FLAG(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_NTF_FLAG_SHIFT))&FCSMU_NTF_FLAG_MASK)
|
||||
|
||||
#define FCSMU_NTF_INDEX_MASK 0xFFu
|
||||
|
||||
#define FCSMU_NTF_INDEX_SHIFT 0u
|
||||
|
||||
#define FCSMU_NTF_INDEX_WIDTH 8u
|
||||
|
||||
#define FCSMU_NTF_INDEX(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_NTF_INDEX_SHIFT))&FCSMU_NTF_INDEX_MASK)
|
||||
|
||||
/* NTF Reg Mask */
|
||||
|
||||
#define FCSMU_NTF_MASK 0x000002FFu
|
||||
|
||||
|
||||
|
||||
/* FTW Bit Fields */
|
||||
|
||||
#define FCSMU_FTW_INDEX_MASK 0xFFu
|
||||
|
||||
#define FCSMU_FTW_INDEX_SHIFT 0u
|
||||
|
||||
#define FCSMU_FTW_INDEX_WIDTH 8u
|
||||
|
||||
#define FCSMU_FTW_INDEX(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FTW_INDEX_SHIFT))&FCSMU_FTW_INDEX_MASK)
|
||||
|
||||
/* FTW Reg Mask */
|
||||
|
||||
#define FCSMU_FTW_MASK 0x000000FFu
|
||||
|
||||
|
||||
|
||||
/* INJECT Bit Fields */
|
||||
|
||||
#define FCSMU_INJECT_INDEX_MASK 0x7Fu
|
||||
|
||||
#define FCSMU_INJECT_INDEX_SHIFT 0u
|
||||
|
||||
#define FCSMU_INJECT_INDEX_WIDTH 7u
|
||||
|
||||
#define FCSMU_INJECT_INDEX(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_INJECT_INDEX_SHIFT))&FCSMU_INJECT_INDEX_MASK)
|
||||
|
||||
/* INJECT Reg Mask */
|
||||
|
||||
#define FCSMU_INJECT_MASK 0x0000007Fu
|
||||
|
||||
|
||||
|
||||
/* IRQ_STAT Bit Fields */
|
||||
|
||||
#define FCSMU_IRQ_STAT_FAULT_IRQ_MASK 0x4u
|
||||
|
||||
#define FCSMU_IRQ_STAT_FAULT_IRQ_SHIFT 2u
|
||||
|
||||
#define FCSMU_IRQ_STAT_FAULT_IRQ_WIDTH 1u
|
||||
|
||||
#define FCSMU_IRQ_STAT_FAULT_IRQ(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_IRQ_STAT_FAULT_IRQ_SHIFT))&FCSMU_IRQ_STAT_FAULT_IRQ_MASK)
|
||||
|
||||
#define FCSMU_IRQ_STAT_WARNING_IRQ_MASK 0x2u
|
||||
|
||||
#define FCSMU_IRQ_STAT_WARNING_IRQ_SHIFT 1u
|
||||
|
||||
#define FCSMU_IRQ_STAT_WARNING_IRQ_WIDTH 1u
|
||||
|
||||
#define FCSMU_IRQ_STAT_WARNING_IRQ(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_IRQ_STAT_WARNING_IRQ_SHIFT))&FCSMU_IRQ_STAT_WARNING_IRQ_MASK)
|
||||
|
||||
#define FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK 0x1u
|
||||
|
||||
#define FCSMU_IRQ_STAT_CFG_TO_IRQ_SHIFT 0u
|
||||
|
||||
#define FCSMU_IRQ_STAT_CFG_TO_IRQ_WIDTH 1u
|
||||
|
||||
#define FCSMU_IRQ_STAT_CFG_TO_IRQ(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_IRQ_STAT_CFG_TO_IRQ_SHIFT))&FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK)
|
||||
|
||||
/* IRQ_STAT Reg Mask */
|
||||
|
||||
#define FCSMU_IRQ_STAT_MASK 0x00000007u
|
||||
|
||||
|
||||
|
||||
/* IRQ_EN Bit Fields */
|
||||
|
||||
#define FCSMU_IRQ_EN_CFG_TO_IEN_MASK 0x1u
|
||||
|
||||
#define FCSMU_IRQ_EN_CFG_TO_IEN_SHIFT 0u
|
||||
|
||||
#define FCSMU_IRQ_EN_CFG_TO_IEN_WIDTH 1u
|
||||
|
||||
#define FCSMU_IRQ_EN_CFG_TO_IEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_IRQ_EN_CFG_TO_IEN_SHIFT))&FCSMU_IRQ_EN_CFG_TO_IEN_MASK)
|
||||
|
||||
/* IRQ_EN Reg Mask */
|
||||
|
||||
#define FCSMU_IRQ_EN_MASK 0x00000001u
|
||||
|
||||
|
||||
|
||||
/* TEMP_UNLK Bit Fields */
|
||||
|
||||
#define FCSMU_TEMP_UNLK_KEY_MASK 0x1FFu
|
||||
|
||||
#define FCSMU_TEMP_UNLK_KEY_SHIFT 0u
|
||||
|
||||
#define FCSMU_TEMP_UNLK_KEY_WIDTH 9u
|
||||
|
||||
#define FCSMU_TEMP_UNLK_KEY(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_TEMP_UNLK_KEY_SHIFT))&FCSMU_TEMP_UNLK_KEY_MASK)
|
||||
|
||||
/* TEMP_UNLK Reg Mask */
|
||||
|
||||
#define FCSMU_TEMP_UNLK_MASK 0x000001FFu
|
||||
|
||||
|
||||
|
||||
/* PERMNT_LOCK Bit Fields */
|
||||
|
||||
#define FCSMU_PERMNT_LOCK_KEY_MASK 0x1FFu
|
||||
|
||||
#define FCSMU_PERMNT_LOCK_KEY_SHIFT 0u
|
||||
|
||||
#define FCSMU_PERMNT_LOCK_KEY_WIDTH 9u
|
||||
|
||||
#define FCSMU_PERMNT_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_PERMNT_LOCK_KEY_SHIFT))&FCSMU_PERMNT_LOCK_KEY_MASK)
|
||||
|
||||
/* PERMNT_LOCK Reg Mask */
|
||||
|
||||
#define FCSMU_PERMNT_LOCK_MASK 0x000001FFu
|
||||
|
||||
|
||||
|
||||
/* STMR Bit Fields */
|
||||
|
||||
#define FCSMU_STMR_FTTI_MASK 0xC0000000u
|
||||
|
||||
#define FCSMU_STMR_FTTI_SHIFT 30u
|
||||
|
||||
#define FCSMU_STMR_FTTI_WIDTH 2u
|
||||
|
||||
#define FCSMU_STMR_FTTI(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_STMR_FTTI_SHIFT))&FCSMU_STMR_FTTI_MASK)
|
||||
|
||||
#define FCSMU_STMR_MTE_MASK 0x4000u
|
||||
|
||||
#define FCSMU_STMR_MTE_SHIFT 14u
|
||||
|
||||
#define FCSMU_STMR_MTE_WIDTH 1u
|
||||
|
||||
#define FCSMU_STMR_MTE(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_STMR_MTE_SHIFT))&FCSMU_STMR_MTE_MASK)
|
||||
|
||||
#define FCSMU_STMR_MINI_TIME_MASK 0x3FFFu
|
||||
|
||||
#define FCSMU_STMR_MINI_TIME_SHIFT 0u
|
||||
|
||||
#define FCSMU_STMR_MINI_TIME_WIDTH 14u
|
||||
|
||||
#define FCSMU_STMR_MINI_TIME(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_STMR_MINI_TIME_SHIFT))&FCSMU_STMR_MINI_TIME_MASK)
|
||||
|
||||
/* STMR Reg Mask */
|
||||
|
||||
#define FCSMU_STMR_MASK 0xC0007FFFu
|
||||
|
||||
|
||||
|
||||
/* WARNING_IEN0 Bit Fields */
|
||||
|
||||
#define FCSMU_WARNING_IEN0_EN_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_WARNING_IEN0_EN_SHIFT 0u
|
||||
|
||||
#define FCSMU_WARNING_IEN0_EN_WIDTH 32u
|
||||
|
||||
#define FCSMU_WARNING_IEN0_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_WARNING_IEN0_EN_SHIFT))&FCSMU_WARNING_IEN0_EN_MASK)
|
||||
|
||||
/* WARNING_IEN0 Reg Mask */
|
||||
|
||||
#define FCSMU_WARNING_IEN0_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* FAULT_IEN0 Bit Fields */
|
||||
|
||||
#define FCSMU_FAULT_IEN0_EN_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_FAULT_IEN0_EN_SHIFT 0u
|
||||
|
||||
#define FCSMU_FAULT_IEN0_EN_WIDTH 32u
|
||||
|
||||
#define FCSMU_FAULT_IEN0_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_FAULT_IEN0_EN_SHIFT))&FCSMU_FAULT_IEN0_EN_MASK)
|
||||
|
||||
/* FAULT_IEN0 Reg Mask */
|
||||
|
||||
#define FCSMU_FAULT_IEN0_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* SOUT_EN0 Bit Fields */
|
||||
|
||||
#define FCSMU_SOUT_EN0_EN_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_SOUT_EN0_EN_SHIFT 0u
|
||||
|
||||
#define FCSMU_SOUT_EN0_EN_WIDTH 32u
|
||||
|
||||
#define FCSMU_SOUT_EN0_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOUT_EN0_EN_SHIFT))&FCSMU_SOUT_EN0_EN_MASK)
|
||||
|
||||
/* SOUT_EN0 Reg Mask */
|
||||
|
||||
#define FCSMU_SOUT_EN0_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* WARNING_TMR Bit Fields */
|
||||
|
||||
#define FCSMU_WARNING_TMR_VAL_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_WARNING_TMR_VAL_SHIFT 0u
|
||||
|
||||
#define FCSMU_WARNING_TMR_VAL_WIDTH 32u
|
||||
|
||||
#define FCSMU_WARNING_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_WARNING_TMR_VAL_SHIFT))&FCSMU_WARNING_TMR_VAL_MASK)
|
||||
|
||||
/* WARNING_TMR Reg Mask */
|
||||
|
||||
#define FCSMU_WARNING_TMR_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* SM_TMR Bit Fields */
|
||||
|
||||
#define FCSMU_SM_TMR_VAL_MASK 0xFFFFu
|
||||
|
||||
#define FCSMU_SM_TMR_VAL_SHIFT 0u
|
||||
|
||||
#define FCSMU_SM_TMR_VAL_WIDTH 16u
|
||||
|
||||
#define FCSMU_SM_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SM_TMR_VAL_SHIFT))&FCSMU_SM_TMR_VAL_MASK)
|
||||
|
||||
/* SM_TMR Reg Mask */
|
||||
|
||||
#define FCSMU_SM_TMR_MASK 0x0000FFFFu
|
||||
|
||||
|
||||
|
||||
/* CFG_TMR Bit Fields */
|
||||
|
||||
#define FCSMU_CFG_TMR_VAL_MASK 0x1FFFFFu
|
||||
|
||||
#define FCSMU_CFG_TMR_VAL_SHIFT 0u
|
||||
|
||||
#define FCSMU_CFG_TMR_VAL_WIDTH 21u
|
||||
|
||||
#define FCSMU_CFG_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CFG_TMR_VAL_SHIFT))&FCSMU_CFG_TMR_VAL_MASK)
|
||||
|
||||
/* CFG_TMR Reg Mask */
|
||||
|
||||
#define FCSMU_CFG_TMR_MASK 0x001FFFFFu
|
||||
|
||||
|
||||
|
||||
/* SOUT_TMR Bit Fields */
|
||||
|
||||
#define FCSMU_SOUT_TMR_VAL_MASK 0x7FFFFFu
|
||||
|
||||
#define FCSMU_SOUT_TMR_VAL_SHIFT 0u
|
||||
|
||||
#define FCSMU_SOUT_TMR_VAL_WIDTH 23u
|
||||
|
||||
#define FCSMU_SOUT_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_SOUT_TMR_VAL_SHIFT))&FCSMU_SOUT_TMR_VAL_MASK)
|
||||
|
||||
/* SOUT_TMR Reg Mask */
|
||||
|
||||
#define FCSMU_SOUT_TMR_MASK 0x007FFFFFu
|
||||
|
||||
|
||||
|
||||
/* CRC_CTRL Bit Fields */
|
||||
|
||||
#define FCSMU_CRC_CTRL_DONE_MASK 0x40u
|
||||
|
||||
#define FCSMU_CRC_CTRL_DONE_SHIFT 6u
|
||||
|
||||
#define FCSMU_CRC_CTRL_DONE_WIDTH 1u
|
||||
|
||||
#define FCSMU_CRC_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_DONE_SHIFT))&FCSMU_CRC_CTRL_DONE_MASK)
|
||||
|
||||
#define FCSMU_CRC_CTRL_EF_MASK 0x20u
|
||||
|
||||
#define FCSMU_CRC_CTRL_EF_SHIFT 5u
|
||||
|
||||
#define FCSMU_CRC_CTRL_EF_WIDTH 1u
|
||||
|
||||
#define FCSMU_CRC_CTRL_EF(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_EF_SHIFT))&FCSMU_CRC_CTRL_EF_MASK)
|
||||
|
||||
#define FCSMU_CRC_CTRL_BUSY_MASK 0x10u
|
||||
|
||||
#define FCSMU_CRC_CTRL_BUSY_SHIFT 4u
|
||||
|
||||
#define FCSMU_CRC_CTRL_BUSY_WIDTH 1u
|
||||
|
||||
#define FCSMU_CRC_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_BUSY_SHIFT))&FCSMU_CRC_CTRL_BUSY_MASK)
|
||||
|
||||
#define FCSMU_CRC_CTRL_EOEN_MASK 0x8u
|
||||
|
||||
#define FCSMU_CRC_CTRL_EOEN_SHIFT 3u
|
||||
|
||||
#define FCSMU_CRC_CTRL_EOEN_WIDTH 1u
|
||||
|
||||
#define FCSMU_CRC_CTRL_EOEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_EOEN_SHIFT))&FCSMU_CRC_CTRL_EOEN_MASK)
|
||||
|
||||
#define FCSMU_CRC_CTRL_CHKEN_MASK 0x4u
|
||||
|
||||
#define FCSMU_CRC_CTRL_CHKEN_SHIFT 2u
|
||||
|
||||
#define FCSMU_CRC_CTRL_CHKEN_WIDTH 1u
|
||||
|
||||
#define FCSMU_CRC_CTRL_CHKEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_CHKEN_SHIFT))&FCSMU_CRC_CTRL_CHKEN_MASK)
|
||||
|
||||
#define FCSMU_CRC_CTRL_TRGEN_MASK 0x2u
|
||||
|
||||
#define FCSMU_CRC_CTRL_TRGEN_SHIFT 1u
|
||||
|
||||
#define FCSMU_CRC_CTRL_TRGEN_WIDTH 1u
|
||||
|
||||
#define FCSMU_CRC_CTRL_TRGEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_TRGEN_SHIFT))&FCSMU_CRC_CTRL_TRGEN_MASK)
|
||||
|
||||
#define FCSMU_CRC_CTRL_GEN_MASK 0x1u
|
||||
|
||||
#define FCSMU_CRC_CTRL_GEN_SHIFT 0u
|
||||
|
||||
#define FCSMU_CRC_CTRL_GEN_WIDTH 1u
|
||||
|
||||
#define FCSMU_CRC_CTRL_GEN(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_CTRL_GEN_SHIFT))&FCSMU_CRC_CTRL_GEN_MASK)
|
||||
|
||||
/* CRC_CTRL Reg Mask */
|
||||
|
||||
#define FCSMU_CRC_CTRL_MASK 0x0000007Fu
|
||||
|
||||
|
||||
|
||||
/* CRC_RES Bit Fields */
|
||||
|
||||
#define FCSMU_CRC_RES_RESULT_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSMU_CRC_RES_RESULT_SHIFT 0u
|
||||
|
||||
#define FCSMU_CRC_RES_RESULT_WIDTH 32u
|
||||
|
||||
#define FCSMU_CRC_RES_RESULT(x) (((uint32_t)(((uint32_t)(x))<<FCSMU_CRC_RES_RESULT_SHIFT))&FCSMU_CRC_RES_RESULT_MASK)
|
||||
|
||||
/* CRC_RES Reg Mask */
|
||||
|
||||
#define FCSMU_CRC_RES_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group FCSMU_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group FCSMU_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,821 @@
|
|||
#ifndef _FC7240_FCSPI_NU_Tztufn50_REGS_H_
|
||||
#define _FC7240_FCSPI_NU_Tztufn50_REGS_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- FCSPI Peripheral Access Layer
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup FCSPI_Peripheral_Access_Layer FCSPI Peripheral Access Layer
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** FCSPI - Size of Registers Arrays */
|
||||
|
||||
|
||||
|
||||
/** FCSPI - Register Layout Typedef */
|
||||
|
||||
|
||||
|
||||
typedef struct {
|
||||
|
||||
|
||||
|
||||
uint8_t RESERVED_0[16];
|
||||
|
||||
__IO uint32_t CTRL ; /* Control Register, offset: 0x10 */
|
||||
|
||||
__IO uint32_t STATUS ; /* Status Register, offset: 0x14 */
|
||||
|
||||
__IO uint32_t INT_EN ; /* Interrupt Enable Register, offset: 0x18 */
|
||||
|
||||
__IO uint32_t DMA_EN ; /* DMA Enable Register, offset: 0x1C */
|
||||
|
||||
__IO uint32_t CFG0 ; /* Configuration Register 0, offset: 0x20 */
|
||||
|
||||
__IO uint32_t CFG1 ; /* Configuration Register 1, offset: 0x24 */
|
||||
|
||||
uint8_t RESERVED_1[8];
|
||||
|
||||
__IO uint32_t DATA_MATCH0 ; /* Data Match Register 0, offset: 0x30 */
|
||||
|
||||
__IO uint32_t DATA_MATCH1 ; /* Data Match Register 1, offset: 0x34 */
|
||||
|
||||
uint8_t RESERVED_2[8];
|
||||
|
||||
__IO uint32_t CLK_CFG ; /* Clock Configuration Register, offset: 0x40 */
|
||||
|
||||
uint8_t RESERVED_3[20];
|
||||
|
||||
__IO uint32_t FIFO_WTM ; /* FIFO Water Mark Register, offset: 0x58 */
|
||||
|
||||
__I uint32_t FIFO_STATUS ; /* FIFO Status Register, offset: 0x5C */
|
||||
|
||||
__IO uint32_t TR_CTRL ; /* Transmit and Receive Control Register, offset: 0x60 */
|
||||
|
||||
__O uint32_t TX_DATA ; /* Transmit Data Register, offset: 0x64 */
|
||||
|
||||
uint8_t RESERVED_4[8];
|
||||
|
||||
__I uint32_t RX_STATUS ; /* Receive Status Register, offset: 0x70 */
|
||||
|
||||
__I uint32_t RX_DATA ; /* Receive Data Register, offset: 0x74 */
|
||||
|
||||
|
||||
|
||||
} FCSPI_Type, *FCSPI_MemMapPtr;
|
||||
|
||||
|
||||
|
||||
/** Number of instances of the FCSPI module. */
|
||||
|
||||
#define FCSPI_INSTANCE_COUNT (6u)
|
||||
|
||||
|
||||
|
||||
/* FCSPI - Peripheral instance base addresses */
|
||||
|
||||
/** Peripheral FCSPI0 base address */
|
||||
|
||||
#define FCSPI0_BASE (0x40062000u)
|
||||
|
||||
/** Peripheral FCSPI0 base pointer */
|
||||
|
||||
#define FCSPI0 ((FCSPI_Type *)FCSPI0_BASE)
|
||||
|
||||
/** Peripheral FCSPI1 base address */
|
||||
|
||||
#define FCSPI1_BASE (0x40063000u)
|
||||
|
||||
/** Peripheral FCSPI1 base pointer */
|
||||
|
||||
#define FCSPI1 ((FCSPI_Type *)FCSPI1_BASE)
|
||||
|
||||
/** Peripheral FCSPI2 base address */
|
||||
|
||||
#define FCSPI2_BASE (0x40064000u)
|
||||
|
||||
/** Peripheral FCSPI2 base pointer */
|
||||
|
||||
#define FCSPI2 ((FCSPI_Type *)FCSPI2_BASE)
|
||||
|
||||
/** Peripheral FCSPI3 base address */
|
||||
|
||||
#define FCSPI3_BASE (0x4043f000u)
|
||||
|
||||
/** Peripheral FCSPI3 base pointer */
|
||||
|
||||
#define FCSPI3 ((FCSPI_Type *)FCSPI3_BASE)
|
||||
|
||||
/** Peripheral FCSPI4 base address */
|
||||
|
||||
#define FCSPI4_BASE (0x40440000u)
|
||||
|
||||
/** Peripheral FCSPI4 base pointer */
|
||||
|
||||
#define FCSPI4 ((FCSPI_Type *)FCSPI4_BASE)
|
||||
|
||||
/** Peripheral FCSPI5 base address */
|
||||
|
||||
#define FCSPI5_BASE (0x40441000u)
|
||||
|
||||
/** Peripheral FCSPI5 base pointer */
|
||||
|
||||
#define FCSPI5 ((FCSPI_Type *)FCSPI5_BASE)
|
||||
|
||||
/** Array initializer of FCSPI peripheral base addresses */
|
||||
|
||||
#define FCSPI_BASE_ADDRS {FCSPI0_BASE, FCSPI1_BASE, FCSPI2_BASE, FCSPI3_BASE, FCSPI4_BASE, FCSPI5_BASE}
|
||||
|
||||
/** Array initializer of FCSPI peripheral base pointers */
|
||||
|
||||
#define FCSPI_BASE_PTRS {FCSPI0, FCSPI1, FCSPI2, FCSPI3, FCSPI4, FCSPI5}
|
||||
|
||||
// need fill by yourself
|
||||
|
||||
///** Number of interrupt vector arrays for the FCSPI module. */
|
||||
|
||||
//#define FCSPI_IRQS_ARR_COUNT (1u)
|
||||
|
||||
///** Number of interrupt channels for the FCSPI module. */
|
||||
|
||||
//#define FCSPI_IRQS_CH_COUNT (1u)
|
||||
|
||||
///** Interrupt vectors for the FCSPI peripheral type */
|
||||
|
||||
//#define FCSPI_IRQS {FCSPI0_IRQn, FCSPI1_IRQn, FCSPI2_IRQn, FCSPI3_IRQn, FCSPI4_IRQn, FCSPI5_IRQn}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
|
||||
-- FCSPI Register Masks
|
||||
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @addtogroup FCSPI_Register_Masks FCSPI Register Masks
|
||||
|
||||
* @{
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* CTRL Bit Fields */
|
||||
|
||||
#define FCSPI_CTRL_RST_RF_MASK 0x200u
|
||||
|
||||
#define FCSPI_CTRL_RST_RF_SHIFT 9u
|
||||
|
||||
#define FCSPI_CTRL_RST_RF_WIDTH 1u
|
||||
|
||||
#define FCSPI_CTRL_RST_RF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CTRL_RST_RF_SHIFT))&FCSPI_CTRL_RST_RF_MASK)
|
||||
|
||||
#define FCSPI_CTRL_RST_TF_MASK 0x100u
|
||||
|
||||
#define FCSPI_CTRL_RST_TF_SHIFT 8u
|
||||
|
||||
#define FCSPI_CTRL_RST_TF_WIDTH 1u
|
||||
|
||||
#define FCSPI_CTRL_RST_TF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CTRL_RST_TF_SHIFT))&FCSPI_CTRL_RST_TF_MASK)
|
||||
|
||||
#define FCSPI_CTRL_DBG_EN_MASK 0x8u
|
||||
|
||||
#define FCSPI_CTRL_DBG_EN_SHIFT 3u
|
||||
|
||||
#define FCSPI_CTRL_DBG_EN_WIDTH 1u
|
||||
|
||||
#define FCSPI_CTRL_DBG_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CTRL_DBG_EN_SHIFT))&FCSPI_CTRL_DBG_EN_MASK)
|
||||
|
||||
#define FCSPI_CTRL_WAIT_DIS_MASK 0x4u
|
||||
|
||||
#define FCSPI_CTRL_WAIT_DIS_SHIFT 2u
|
||||
|
||||
#define FCSPI_CTRL_WAIT_DIS_WIDTH 1u
|
||||
|
||||
#define FCSPI_CTRL_WAIT_DIS(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CTRL_WAIT_DIS_SHIFT))&FCSPI_CTRL_WAIT_DIS_MASK)
|
||||
|
||||
#define FCSPI_CTRL_SW_RST_MASK 0x2u
|
||||
|
||||
#define FCSPI_CTRL_SW_RST_SHIFT 1u
|
||||
|
||||
#define FCSPI_CTRL_SW_RST_WIDTH 1u
|
||||
|
||||
#define FCSPI_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CTRL_SW_RST_SHIFT))&FCSPI_CTRL_SW_RST_MASK)
|
||||
|
||||
#define FCSPI_CTRL_M_EN_MASK 0x1u
|
||||
|
||||
#define FCSPI_CTRL_M_EN_SHIFT 0u
|
||||
|
||||
#define FCSPI_CTRL_M_EN_WIDTH 1u
|
||||
|
||||
#define FCSPI_CTRL_M_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CTRL_M_EN_SHIFT))&FCSPI_CTRL_M_EN_MASK)
|
||||
|
||||
/* CTRL Reg Mask */
|
||||
|
||||
#define FCSPI_CTRL_MASK 0x0000030Fu
|
||||
|
||||
|
||||
|
||||
/* STATUS Bit Fields */
|
||||
|
||||
#define FCSPI_STATUS_BF_MASK 0x1000000u
|
||||
|
||||
#define FCSPI_STATUS_BF_SHIFT 24u
|
||||
|
||||
#define FCSPI_STATUS_BF_WIDTH 1u
|
||||
|
||||
#define FCSPI_STATUS_BF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_BF_SHIFT))&FCSPI_STATUS_BF_MASK)
|
||||
|
||||
#define FCSPI_STATUS_DMF_MASK 0x2000u
|
||||
|
||||
#define FCSPI_STATUS_DMF_SHIFT 13u
|
||||
|
||||
#define FCSPI_STATUS_DMF_WIDTH 1u
|
||||
|
||||
#define FCSPI_STATUS_DMF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_DMF_SHIFT))&FCSPI_STATUS_DMF_MASK)
|
||||
|
||||
#define FCSPI_STATUS_RX_FO_MASK 0x1000u
|
||||
|
||||
#define FCSPI_STATUS_RX_FO_SHIFT 12u
|
||||
|
||||
#define FCSPI_STATUS_RX_FO_WIDTH 1u
|
||||
|
||||
#define FCSPI_STATUS_RX_FO(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_RX_FO_SHIFT))&FCSPI_STATUS_RX_FO_MASK)
|
||||
|
||||
#define FCSPI_STATUS_TX_FU_MASK 0x800u
|
||||
|
||||
#define FCSPI_STATUS_TX_FU_SHIFT 11u
|
||||
|
||||
#define FCSPI_STATUS_TX_FU_WIDTH 1u
|
||||
|
||||
#define FCSPI_STATUS_TX_FU(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_TX_FU_SHIFT))&FCSPI_STATUS_TX_FU_MASK)
|
||||
|
||||
#define FCSPI_STATUS_TCF_MASK 0x400u
|
||||
|
||||
#define FCSPI_STATUS_TCF_SHIFT 10u
|
||||
|
||||
#define FCSPI_STATUS_TCF_WIDTH 1u
|
||||
|
||||
#define FCSPI_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_TCF_SHIFT))&FCSPI_STATUS_TCF_MASK)
|
||||
|
||||
#define FCSPI_STATUS_FEF_MASK 0x200u
|
||||
|
||||
#define FCSPI_STATUS_FEF_SHIFT 9u
|
||||
|
||||
#define FCSPI_STATUS_FEF_WIDTH 1u
|
||||
|
||||
#define FCSPI_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_FEF_SHIFT))&FCSPI_STATUS_FEF_MASK)
|
||||
|
||||
#define FCSPI_STATUS_RX_WF_MASK 0x100u
|
||||
|
||||
#define FCSPI_STATUS_RX_WF_SHIFT 8u
|
||||
|
||||
#define FCSPI_STATUS_RX_WF_WIDTH 1u
|
||||
|
||||
#define FCSPI_STATUS_RX_WF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_RX_WF_SHIFT))&FCSPI_STATUS_RX_WF_MASK)
|
||||
|
||||
#define FCSPI_STATUS_RX_FF_MASK 0x2u
|
||||
|
||||
#define FCSPI_STATUS_RX_FF_SHIFT 1u
|
||||
|
||||
#define FCSPI_STATUS_RX_FF_WIDTH 1u
|
||||
|
||||
#define FCSPI_STATUS_RX_FF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_RX_FF_SHIFT))&FCSPI_STATUS_RX_FF_MASK)
|
||||
|
||||
#define FCSPI_STATUS_TX_FF_MASK 0x1u
|
||||
|
||||
#define FCSPI_STATUS_TX_FF_SHIFT 0u
|
||||
|
||||
#define FCSPI_STATUS_TX_FF_WIDTH 1u
|
||||
|
||||
#define FCSPI_STATUS_TX_FF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_STATUS_TX_FF_SHIFT))&FCSPI_STATUS_TX_FF_MASK)
|
||||
|
||||
/* STATUS Reg Mask */
|
||||
|
||||
#define FCSPI_STATUS_MASK 0x01003F03u
|
||||
|
||||
|
||||
|
||||
/* INT_EN Bit Fields */
|
||||
|
||||
#define FCSPI_INT_EN_DMIE_MASK 0x2000u
|
||||
|
||||
#define FCSPI_INT_EN_DMIE_SHIFT 13u
|
||||
|
||||
#define FCSPI_INT_EN_DMIE_WIDTH 1u
|
||||
|
||||
#define FCSPI_INT_EN_DMIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_DMIE_SHIFT))&FCSPI_INT_EN_DMIE_MASK)
|
||||
|
||||
#define FCSPI_INT_EN_RFOIE_MASK 0x1000u
|
||||
|
||||
#define FCSPI_INT_EN_RFOIE_SHIFT 12u
|
||||
|
||||
#define FCSPI_INT_EN_RFOIE_WIDTH 1u
|
||||
|
||||
#define FCSPI_INT_EN_RFOIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_RFOIE_SHIFT))&FCSPI_INT_EN_RFOIE_MASK)
|
||||
|
||||
#define FCSPI_INT_EN_TFUIE_MASK 0x800u
|
||||
|
||||
#define FCSPI_INT_EN_TFUIE_SHIFT 11u
|
||||
|
||||
#define FCSPI_INT_EN_TFUIE_WIDTH 1u
|
||||
|
||||
#define FCSPI_INT_EN_TFUIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_TFUIE_SHIFT))&FCSPI_INT_EN_TFUIE_MASK)
|
||||
|
||||
#define FCSPI_INT_EN_TCIE_MASK 0x400u
|
||||
|
||||
#define FCSPI_INT_EN_TCIE_SHIFT 10u
|
||||
|
||||
#define FCSPI_INT_EN_TCIE_WIDTH 1u
|
||||
|
||||
#define FCSPI_INT_EN_TCIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_TCIE_SHIFT))&FCSPI_INT_EN_TCIE_MASK)
|
||||
|
||||
#define FCSPI_INT_EN_FEIE_MASK 0x200u
|
||||
|
||||
#define FCSPI_INT_EN_FEIE_SHIFT 9u
|
||||
|
||||
#define FCSPI_INT_EN_FEIE_WIDTH 1u
|
||||
|
||||
#define FCSPI_INT_EN_FEIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_FEIE_SHIFT))&FCSPI_INT_EN_FEIE_MASK)
|
||||
|
||||
#define FCSPI_INT_EN_RWIE_MASK 0x100u
|
||||
|
||||
#define FCSPI_INT_EN_RWIE_SHIFT 8u
|
||||
|
||||
#define FCSPI_INT_EN_RWIE_WIDTH 1u
|
||||
|
||||
#define FCSPI_INT_EN_RWIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_RWIE_SHIFT))&FCSPI_INT_EN_RWIE_MASK)
|
||||
|
||||
#define FCSPI_INT_EN_RFIE_MASK 0x2u
|
||||
|
||||
#define FCSPI_INT_EN_RFIE_SHIFT 1u
|
||||
|
||||
#define FCSPI_INT_EN_RFIE_WIDTH 1u
|
||||
|
||||
#define FCSPI_INT_EN_RFIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_RFIE_SHIFT))&FCSPI_INT_EN_RFIE_MASK)
|
||||
|
||||
#define FCSPI_INT_EN_TFIE_MASK 0x1u
|
||||
|
||||
#define FCSPI_INT_EN_TFIE_SHIFT 0u
|
||||
|
||||
#define FCSPI_INT_EN_TFIE_WIDTH 1u
|
||||
|
||||
#define FCSPI_INT_EN_TFIE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_INT_EN_TFIE_SHIFT))&FCSPI_INT_EN_TFIE_MASK)
|
||||
|
||||
/* INT_EN Reg Mask */
|
||||
|
||||
#define FCSPI_INT_EN_MASK 0x00003F03u
|
||||
|
||||
|
||||
|
||||
/* DMA_EN Bit Fields */
|
||||
|
||||
#define FCSPI_DMA_EN_RFDE_MASK 0x2u
|
||||
|
||||
#define FCSPI_DMA_EN_RFDE_SHIFT 1u
|
||||
|
||||
#define FCSPI_DMA_EN_RFDE_WIDTH 1u
|
||||
|
||||
#define FCSPI_DMA_EN_RFDE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_DMA_EN_RFDE_SHIFT))&FCSPI_DMA_EN_RFDE_MASK)
|
||||
|
||||
#define FCSPI_DMA_EN_TFDE_MASK 0x1u
|
||||
|
||||
#define FCSPI_DMA_EN_TFDE_SHIFT 0u
|
||||
|
||||
#define FCSPI_DMA_EN_TFDE_WIDTH 1u
|
||||
|
||||
#define FCSPI_DMA_EN_TFDE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_DMA_EN_TFDE_SHIFT))&FCSPI_DMA_EN_TFDE_MASK)
|
||||
|
||||
/* DMA_EN Reg Mask */
|
||||
|
||||
#define FCSPI_DMA_EN_MASK 0x00000003u
|
||||
|
||||
|
||||
|
||||
/* CFG0 Bit Fields */
|
||||
|
||||
#define FCSPI_CFG0_AKDS_MASK 0x400u
|
||||
|
||||
#define FCSPI_CFG0_AKDS_SHIFT 10u
|
||||
|
||||
#define FCSPI_CFG0_AKDS_WIDTH 1u
|
||||
|
||||
#define FCSPI_CFG0_AKDS(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG0_AKDS_SHIFT))&FCSPI_CFG0_AKDS_MASK)
|
||||
|
||||
#define FCSPI_CFG0_RDMO_MASK 0x200u
|
||||
|
||||
#define FCSPI_CFG0_RDMO_SHIFT 9u
|
||||
|
||||
#define FCSPI_CFG0_RDMO_WIDTH 1u
|
||||
|
||||
#define FCSPI_CFG0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG0_RDMO_SHIFT))&FCSPI_CFG0_RDMO_MASK)
|
||||
|
||||
#define FCSPI_CFG0_TRGEN_MASK 0x1u
|
||||
|
||||
#define FCSPI_CFG0_TRGEN_SHIFT 0u
|
||||
|
||||
#define FCSPI_CFG0_TRGEN_WIDTH 1u
|
||||
|
||||
#define FCSPI_CFG0_TRGEN(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG0_TRGEN_SHIFT))&FCSPI_CFG0_TRGEN_MASK)
|
||||
|
||||
/* CFG0 Reg Mask */
|
||||
|
||||
#define FCSPI_CFG0_MASK 0x00000601u
|
||||
|
||||
|
||||
|
||||
/* CFG1 Bit Fields */
|
||||
|
||||
#define FCSPI_CFG1_PCS_CFG_MASK 0x8000000u
|
||||
|
||||
#define FCSPI_CFG1_PCS_CFG_SHIFT 27u
|
||||
|
||||
#define FCSPI_CFG1_PCS_CFG_WIDTH 1u
|
||||
|
||||
#define FCSPI_CFG1_PCS_CFG(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_PCS_CFG_SHIFT))&FCSPI_CFG1_PCS_CFG_MASK)
|
||||
|
||||
#define FCSPI_CFG1_OUT_CFG_MASK 0x4000000u
|
||||
|
||||
#define FCSPI_CFG1_OUT_CFG_SHIFT 26u
|
||||
|
||||
#define FCSPI_CFG1_OUT_CFG_WIDTH 1u
|
||||
|
||||
#define FCSPI_CFG1_OUT_CFG(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_OUT_CFG_SHIFT))&FCSPI_CFG1_OUT_CFG_MASK)
|
||||
|
||||
#define FCSPI_CFG1_PIN_CFG_MASK 0x3000000u
|
||||
|
||||
#define FCSPI_CFG1_PIN_CFG_SHIFT 24u
|
||||
|
||||
#define FCSPI_CFG1_PIN_CFG_WIDTH 2u
|
||||
|
||||
#define FCSPI_CFG1_PIN_CFG(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_PIN_CFG_SHIFT))&FCSPI_CFG1_PIN_CFG_MASK)
|
||||
|
||||
#define FCSPI_CFG1_MAT_CFG_MASK 0x70000u
|
||||
|
||||
#define FCSPI_CFG1_MAT_CFG_SHIFT 16u
|
||||
|
||||
#define FCSPI_CFG1_MAT_CFG_WIDTH 3u
|
||||
|
||||
#define FCSPI_CFG1_MAT_CFG(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_MAT_CFG_SHIFT))&FCSPI_CFG1_MAT_CFG_MASK)
|
||||
|
||||
#define FCSPI_CFG1_PCS_POL_MASK 0xF00u
|
||||
|
||||
#define FCSPI_CFG1_PCS_POL_SHIFT 8u
|
||||
|
||||
#define FCSPI_CFG1_PCS_POL_WIDTH 4u
|
||||
|
||||
#define FCSPI_CFG1_PCS_POL(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_PCS_POL_SHIFT))&FCSPI_CFG1_PCS_POL_MASK)
|
||||
|
||||
#define FCSPI_CFG1_INT_PCS_MASK 0x4u
|
||||
|
||||
#define FCSPI_CFG1_INT_PCS_SHIFT 2u
|
||||
|
||||
#define FCSPI_CFG1_INT_PCS_WIDTH 1u
|
||||
|
||||
#define FCSPI_CFG1_INT_PCS(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_INT_PCS_SHIFT))&FCSPI_CFG1_INT_PCS_MASK)
|
||||
|
||||
#define FCSPI_CFG1_SCK_LB_MASK 0x2u
|
||||
|
||||
#define FCSPI_CFG1_SCK_LB_SHIFT 1u
|
||||
|
||||
#define FCSPI_CFG1_SCK_LB_WIDTH 1u
|
||||
|
||||
#define FCSPI_CFG1_SCK_LB(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_SCK_LB_SHIFT))&FCSPI_CFG1_SCK_LB_MASK)
|
||||
|
||||
#define FCSPI_CFG1_MASTER_MASK 0x1u
|
||||
|
||||
#define FCSPI_CFG1_MASTER_SHIFT 0u
|
||||
|
||||
#define FCSPI_CFG1_MASTER_WIDTH 1u
|
||||
|
||||
#define FCSPI_CFG1_MASTER(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CFG1_MASTER_SHIFT))&FCSPI_CFG1_MASTER_MASK)
|
||||
|
||||
/* CFG1 Reg Mask */
|
||||
|
||||
#define FCSPI_CFG1_MASK 0x0F070F07u
|
||||
|
||||
|
||||
|
||||
/* DATA_MATCH0 Bit Fields */
|
||||
|
||||
#define FCSPI_DATA_MATCH0_DATA0_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSPI_DATA_MATCH0_DATA0_SHIFT 0u
|
||||
|
||||
#define FCSPI_DATA_MATCH0_DATA0_WIDTH 32u
|
||||
|
||||
#define FCSPI_DATA_MATCH0_DATA0(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_DATA_MATCH0_DATA0_SHIFT))&FCSPI_DATA_MATCH0_DATA0_MASK)
|
||||
|
||||
/* DATA_MATCH0 Reg Mask */
|
||||
|
||||
#define FCSPI_DATA_MATCH0_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* DATA_MATCH1 Bit Fields */
|
||||
|
||||
#define FCSPI_DATA_MATCH1_DATA1_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSPI_DATA_MATCH1_DATA1_SHIFT 0u
|
||||
|
||||
#define FCSPI_DATA_MATCH1_DATA1_WIDTH 32u
|
||||
|
||||
#define FCSPI_DATA_MATCH1_DATA1(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_DATA_MATCH1_DATA1_SHIFT))&FCSPI_DATA_MATCH1_DATA1_MASK)
|
||||
|
||||
/* DATA_MATCH1 Reg Mask */
|
||||
|
||||
#define FCSPI_DATA_MATCH1_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* CLK_CFG Bit Fields */
|
||||
|
||||
#define FCSPI_CLK_CFG_SCKPCS_MASK 0xFF000000u
|
||||
|
||||
#define FCSPI_CLK_CFG_SCKPCS_SHIFT 24u
|
||||
|
||||
#define FCSPI_CLK_CFG_SCKPCS_WIDTH 8u
|
||||
|
||||
#define FCSPI_CLK_CFG_SCKPCS(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CLK_CFG_SCKPCS_SHIFT))&FCSPI_CLK_CFG_SCKPCS_MASK)
|
||||
|
||||
#define FCSPI_CLK_CFG_PCSSCK_MASK 0xFF0000u
|
||||
|
||||
#define FCSPI_CLK_CFG_PCSSCK_SHIFT 16u
|
||||
|
||||
#define FCSPI_CLK_CFG_PCSSCK_WIDTH 8u
|
||||
|
||||
#define FCSPI_CLK_CFG_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CLK_CFG_PCSSCK_SHIFT))&FCSPI_CLK_CFG_PCSSCK_MASK)
|
||||
|
||||
#define FCSPI_CLK_CFG_PCSPCS_MASK 0xFF00u
|
||||
|
||||
#define FCSPI_CLK_CFG_PCSPCS_SHIFT 8u
|
||||
|
||||
#define FCSPI_CLK_CFG_PCSPCS_WIDTH 8u
|
||||
|
||||
#define FCSPI_CLK_CFG_PCSPCS(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CLK_CFG_PCSPCS_SHIFT))&FCSPI_CLK_CFG_PCSPCS_MASK)
|
||||
|
||||
#define FCSPI_CLK_CFG_SCKDIV_MASK 0xFFu
|
||||
|
||||
#define FCSPI_CLK_CFG_SCKDIV_SHIFT 0u
|
||||
|
||||
#define FCSPI_CLK_CFG_SCKDIV_WIDTH 8u
|
||||
|
||||
#define FCSPI_CLK_CFG_SCKDIV(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_CLK_CFG_SCKDIV_SHIFT))&FCSPI_CLK_CFG_SCKDIV_MASK)
|
||||
|
||||
/* CLK_CFG Reg Mask */
|
||||
|
||||
#define FCSPI_CLK_CFG_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* FIFO_WTM Bit Fields */
|
||||
|
||||
#define FCSPI_FIFO_WTM_RXWATER_MASK 0x70000u
|
||||
|
||||
#define FCSPI_FIFO_WTM_RXWATER_SHIFT 16u
|
||||
|
||||
#define FCSPI_FIFO_WTM_RXWATER_WIDTH 3u
|
||||
|
||||
#define FCSPI_FIFO_WTM_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_FIFO_WTM_RXWATER_SHIFT))&FCSPI_FIFO_WTM_RXWATER_MASK)
|
||||
|
||||
#define FCSPI_FIFO_WTM_TXWATER_MASK 0x7u
|
||||
|
||||
#define FCSPI_FIFO_WTM_TXWATER_SHIFT 0u
|
||||
|
||||
#define FCSPI_FIFO_WTM_TXWATER_WIDTH 3u
|
||||
|
||||
#define FCSPI_FIFO_WTM_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_FIFO_WTM_TXWATER_SHIFT))&FCSPI_FIFO_WTM_TXWATER_MASK)
|
||||
|
||||
/* FIFO_WTM Reg Mask */
|
||||
|
||||
#define FCSPI_FIFO_WTM_MASK 0x00070007u
|
||||
|
||||
|
||||
|
||||
/* FIFO_STATUS Bit Fields */
|
||||
|
||||
#define FCSPI_FIFO_STATUS_RXCNT_MASK 0xF0000u
|
||||
|
||||
#define FCSPI_FIFO_STATUS_RXCNT_SHIFT 16u
|
||||
|
||||
#define FCSPI_FIFO_STATUS_RXCNT_WIDTH 4u
|
||||
|
||||
#define FCSPI_FIFO_STATUS_RXCNT(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_FIFO_STATUS_RXCNT_SHIFT))&FCSPI_FIFO_STATUS_RXCNT_MASK)
|
||||
|
||||
#define FCSPI_FIFO_STATUS_TXCNT_MASK 0xFu
|
||||
|
||||
#define FCSPI_FIFO_STATUS_TXCNT_SHIFT 0u
|
||||
|
||||
#define FCSPI_FIFO_STATUS_TXCNT_WIDTH 4u
|
||||
|
||||
#define FCSPI_FIFO_STATUS_TXCNT(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_FIFO_STATUS_TXCNT_SHIFT))&FCSPI_FIFO_STATUS_TXCNT_MASK)
|
||||
|
||||
/* FIFO_STATUS Reg Mask */
|
||||
|
||||
#define FCSPI_FIFO_STATUS_MASK 0x000F000Fu
|
||||
|
||||
|
||||
|
||||
/* TR_CTRL Bit Fields */
|
||||
|
||||
#define FCSPI_TR_CTRL_SCK_POL_MASK 0x80000000u
|
||||
|
||||
#define FCSPI_TR_CTRL_SCK_POL_SHIFT 31u
|
||||
|
||||
#define FCSPI_TR_CTRL_SCK_POL_WIDTH 1u
|
||||
|
||||
#define FCSPI_TR_CTRL_SCK_POL(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_SCK_POL_SHIFT))&FCSPI_TR_CTRL_SCK_POL_MASK)
|
||||
|
||||
#define FCSPI_TR_CTRL_SCK_PHA_MASK 0x40000000u
|
||||
|
||||
#define FCSPI_TR_CTRL_SCK_PHA_SHIFT 30u
|
||||
|
||||
#define FCSPI_TR_CTRL_SCK_PHA_WIDTH 1u
|
||||
|
||||
#define FCSPI_TR_CTRL_SCK_PHA(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_SCK_PHA_SHIFT))&FCSPI_TR_CTRL_SCK_PHA_MASK)
|
||||
|
||||
#define FCSPI_TR_CTRL_PRESCALE_MASK 0x38000000u
|
||||
|
||||
#define FCSPI_TR_CTRL_PRESCALE_SHIFT 27u
|
||||
|
||||
#define FCSPI_TR_CTRL_PRESCALE_WIDTH 3u
|
||||
|
||||
#define FCSPI_TR_CTRL_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_PRESCALE_SHIFT))&FCSPI_TR_CTRL_PRESCALE_MASK)
|
||||
|
||||
#define FCSPI_TR_CTRL_PCS_MASK 0x3000000u
|
||||
|
||||
#define FCSPI_TR_CTRL_PCS_SHIFT 24u
|
||||
|
||||
#define FCSPI_TR_CTRL_PCS_WIDTH 2u
|
||||
|
||||
#define FCSPI_TR_CTRL_PCS(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_PCS_SHIFT))&FCSPI_TR_CTRL_PCS_MASK)
|
||||
|
||||
#define FCSPI_TR_CTRL_LSBF_MASK 0x800000u
|
||||
|
||||
#define FCSPI_TR_CTRL_LSBF_SHIFT 23u
|
||||
|
||||
#define FCSPI_TR_CTRL_LSBF_WIDTH 1u
|
||||
|
||||
#define FCSPI_TR_CTRL_LSBF(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_LSBF_SHIFT))&FCSPI_TR_CTRL_LSBF_MASK)
|
||||
|
||||
#define FCSPI_TR_CTRL_BYSW_MASK 0x400000u
|
||||
|
||||
#define FCSPI_TR_CTRL_BYSW_SHIFT 22u
|
||||
|
||||
#define FCSPI_TR_CTRL_BYSW_WIDTH 1u
|
||||
|
||||
#define FCSPI_TR_CTRL_BYSW(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_BYSW_SHIFT))&FCSPI_TR_CTRL_BYSW_MASK)
|
||||
|
||||
#define FCSPI_TR_CTRL_CT_EN_MASK 0x200000u
|
||||
|
||||
#define FCSPI_TR_CTRL_CT_EN_SHIFT 21u
|
||||
|
||||
#define FCSPI_TR_CTRL_CT_EN_WIDTH 1u
|
||||
|
||||
#define FCSPI_TR_CTRL_CT_EN(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_CT_EN_SHIFT))&FCSPI_TR_CTRL_CT_EN_MASK)
|
||||
|
||||
#define FCSPI_TR_CTRL_CT_GO_MASK 0x100000u
|
||||
|
||||
#define FCSPI_TR_CTRL_CT_GO_SHIFT 20u
|
||||
|
||||
#define FCSPI_TR_CTRL_CT_GO_WIDTH 1u
|
||||
|
||||
#define FCSPI_TR_CTRL_CT_GO(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_CT_GO_SHIFT))&FCSPI_TR_CTRL_CT_GO_MASK)
|
||||
|
||||
#define FCSPI_TR_CTRL_RX_MSK_MASK 0x80000u
|
||||
|
||||
#define FCSPI_TR_CTRL_RX_MSK_SHIFT 19u
|
||||
|
||||
#define FCSPI_TR_CTRL_RX_MSK_WIDTH 1u
|
||||
|
||||
#define FCSPI_TR_CTRL_RX_MSK(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_RX_MSK_SHIFT))&FCSPI_TR_CTRL_RX_MSK_MASK)
|
||||
|
||||
#define FCSPI_TR_CTRL_TX_MSK_MASK 0x40000u
|
||||
|
||||
#define FCSPI_TR_CTRL_TX_MSK_SHIFT 18u
|
||||
|
||||
#define FCSPI_TR_CTRL_TX_MSK_WIDTH 1u
|
||||
|
||||
#define FCSPI_TR_CTRL_TX_MSK(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_TX_MSK_SHIFT))&FCSPI_TR_CTRL_TX_MSK_MASK)
|
||||
|
||||
#define FCSPI_TR_CTRL_WIDTH_MASK 0x30000u
|
||||
|
||||
#define FCSPI_TR_CTRL_WIDTH_SHIFT 16u
|
||||
|
||||
#define FCSPI_TR_CTRL_WIDTH_WIDTH 2u
|
||||
|
||||
#define FCSPI_TR_CTRL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_WIDTH_SHIFT))&FCSPI_TR_CTRL_WIDTH_MASK)
|
||||
|
||||
#define FCSPI_TR_CTRL_FRM_SZ_MASK 0xFFFu
|
||||
|
||||
#define FCSPI_TR_CTRL_FRM_SZ_SHIFT 0u
|
||||
|
||||
#define FCSPI_TR_CTRL_FRM_SZ_WIDTH 12u
|
||||
|
||||
#define FCSPI_TR_CTRL_FRM_SZ(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TR_CTRL_FRM_SZ_SHIFT))&FCSPI_TR_CTRL_FRM_SZ_MASK)
|
||||
|
||||
/* TR_CTRL Reg Mask */
|
||||
|
||||
#define FCSPI_TR_CTRL_MASK 0xFBFF0FFFu
|
||||
|
||||
|
||||
|
||||
/* TX_DATA Bit Fields */
|
||||
|
||||
#define FCSPI_TX_DATA_DATA_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSPI_TX_DATA_DATA_SHIFT 0u
|
||||
|
||||
#define FCSPI_TX_DATA_DATA_WIDTH 32u
|
||||
|
||||
#define FCSPI_TX_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_TX_DATA_DATA_SHIFT))&FCSPI_TX_DATA_DATA_MASK)
|
||||
|
||||
/* TX_DATA Reg Mask */
|
||||
|
||||
#define FCSPI_TX_DATA_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
/* RX_STATUS Bit Fields */
|
||||
|
||||
#define FCSPI_RX_STATUS_RX_EMPTY_MASK 0x2u
|
||||
|
||||
#define FCSPI_RX_STATUS_RX_EMPTY_SHIFT 1u
|
||||
|
||||
#define FCSPI_RX_STATUS_RX_EMPTY_WIDTH 1u
|
||||
|
||||
#define FCSPI_RX_STATUS_RX_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_RX_STATUS_RX_EMPTY_SHIFT))&FCSPI_RX_STATUS_RX_EMPTY_MASK)
|
||||
|
||||
#define FCSPI_RX_STATUS_FD_MASK 0x1u
|
||||
|
||||
#define FCSPI_RX_STATUS_FD_SHIFT 0u
|
||||
|
||||
#define FCSPI_RX_STATUS_FD_WIDTH 1u
|
||||
|
||||
#define FCSPI_RX_STATUS_FD(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_RX_STATUS_FD_SHIFT))&FCSPI_RX_STATUS_FD_MASK)
|
||||
|
||||
/* RX_STATUS Reg Mask */
|
||||
|
||||
#define FCSPI_RX_STATUS_MASK 0x00000003u
|
||||
|
||||
|
||||
|
||||
/* RX_DATA Bit Fields */
|
||||
|
||||
#define FCSPI_RX_DATA_RX_DATA_MASK 0xFFFFFFFFu
|
||||
|
||||
#define FCSPI_RX_DATA_RX_DATA_SHIFT 0u
|
||||
|
||||
#define FCSPI_RX_DATA_RX_DATA_WIDTH 32u
|
||||
|
||||
#define FCSPI_RX_DATA_RX_DATA(x) (((uint32_t)(((uint32_t)(x))<<FCSPI_RX_DATA_RX_DATA_SHIFT))&FCSPI_RX_DATA_RX_DATA_MASK)
|
||||
|
||||
/* RX_DATA Reg Mask */
|
||||
|
||||
#define FCSPI_RX_DATA_MASK 0xFFFFFFFFu
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group FCSPI_Register_Masks */
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
|
||||
* @}
|
||||
|
||||
*/ /* end of group FCSPI_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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Reference in New Issue