Init

2025-04-24 14:53:54 +03:00 · 2025-04-24 14:53:54 +03:00 · 0ec4cc68be
commit 0ec4cc68be
928 changed files with 46423 additions and 0 deletions
--- a/artery_f435.cfg
+++ b/artery_f435.cfg
@ -0,0 +1,27 @@
+#
+# This is an STM32F429 discovery board with a single STM32F429ZI chip.
+# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090
+#
+
+source [find interface/atlink.cfg]
+
+#transport select hla_swd
+
+source [find target/at32f435xG.cfg]
+
+#reset_config trst_only
+#reset_config srst_only
+#reset_config trst_and_srst
+#reset_config srst_pulls_trst
+#reset_config combined
+#reset_config srst_gates_jtag
+#reset_config trst_push_pull
+#reset_config trst_push_pull
+
+reset_config none
+
+#reset_config [none|trst_only|srst_only|trst_and_srst]
+#[srst_pulls_trst|trst_pulls_srst|combined|separate]
+#[srst_gates_jtag|srst_nogate] [trst_push_pull|trst_open_drain]
+#[srst_push_pull|srst_open_drain]
+#[connect_deassert_srst|connect_assert_srst]
--- a/firmware/boot.xfsb
+++ b/firmware/boot.xfsb
--- a/firmware/module1.xfsb
+++ b/firmware/module1.xfsb
--- a/firmware/module2.xfsb
+++ b/firmware/module2.xfsb
--- a/libdl-1.dll
+++ b/libdl-1.dll
--- a/libevil-1.dll
+++ b/libevil-1.dll
--- a/libftdi1.dll
+++ b/libftdi1.dll
--- a/libgcc_s_sjlj-1.dll
+++ b/libgcc_s_sjlj-1.dll
--- a/libusb0.dll
+++ b/libusb0.dll
--- a/libwinpthread-1.dll
+++ b/libwinpthread-1.dll
--- a/openocd.exe
+++ b/openocd.exe
--- a/scripts/bitsbytes.tcl
+++ b/scripts/bitsbytes.tcl
@ -0,0 +1,59 @@
+#----------------------------------------
+# Purpose - Create some $BIT variables
+#           Create $K and $M variables
+#          and some bit field extraction variables.
+# Create helper variables ...
+#    BIT0.. BIT31
+
+for { set x 0  } { $x < 32 } { set x [expr {$x + 1}]} {
+    set vn [format "BIT%d" $x]
+    global $vn
+    set $vn   [expr {1 << $x}]
+}
+
+# Create K bytes values
+#    __1K ... to __2048K
+for { set x 1  } { $x < 2048 } { set x [expr {$x * 2}]} {
+    set vn [format "__%dK" $x]
+    global $vn
+    set $vn   [expr {1024 * $x}]
+}
+
+# Create M bytes values
+#    __1M ... to __2048K
+for { set x 1  } { $x < 2048 } { set x [expr {$x * 2}]} {
+    set vn [format "__%dM" $x]
+    global $vn
+    set $vn [expr {1024 * 1024 * $x}]
+}
+
+proc create_mask { MSB LSB } {
+    return [expr {((1 << ($MSB - $LSB + 1))-1) << $LSB}]
+}
+
+# Cut Bits $MSB to $LSB out of this value.
+# Example: % format "0x%08x" [extract_bitfield 0x12345678 27 16]
+# Result:  0x02340000
+
+proc extract_bitfield { VALUE MSB LSB } {
+    return [expr {[create_mask $MSB $LSB] & $VALUE}]
+}
+
+
+# Cut bits $MSB to $LSB out of this value
+# and shift (normalize) them down to bit 0.
+#
+# Example: % format "0x%08x" [normalize_bitfield 0x12345678 27 16]
+# Result:  0x00000234
+#
+proc normalize_bitfield { VALUE MSB LSB } {
+    return [expr {[extract_bitfield $VALUE $MSB $LSB ] >> $LSB}]
+}
+
+proc show_normalize_bitfield { VALUE MSB LSB } {
+    set m [create_mask $MSB $LSB]
+    set mr [expr {$VALUE & $m}]
+    set sr [expr {$mr >> $LSB}]
+    echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr]
+   return $sr
+}
--- a/scripts/board/8devices-lima.cfg
+++ b/scripts/board/8devices-lima.cfg
@ -0,0 +1,30 @@
+# Product page:
+# https://www.8devices.com/products/lima
+#
+# Location of JTAG pins:
+# J2 GPIO0	JTAG TCK
+# J2 GPIO1	JTAG TDI
+# J2 GPIO2	JTAG TDO
+# J2 GPIO3	JTAG TMS
+# J2 RST	directly connected to RESET_L of the SoC and can be used as
+#               JTAG SRST. Note: this pin will also reset the debug engine.
+# J1 +3,3V	Can be use as JTAG Vref
+# J1 or J2 GND	Can be used for JTAG GND
+#
+# This board is powered from mini USB connecter which is also used
+# as USB to UART converted based on FTDI FT230XQ chip
+
+source [find target/qualcomm_qca4531.cfg]
+
+proc board_init { } {
+	qca4531_ddr2_550_550_init
+}
+
+$_TARGETNAME configure -event reset-init {
+	board_init
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
--- a/scripts/board/actux3.cfg
+++ b/scripts/board/actux3.cfg
@ -0,0 +1,69 @@
+# board config file for AcTux3/XBA IXP42x board
+# Date:   2010-12-16
+# Author: Michael Schwingen <michael@schwingen.org>
+
+reset_config trst_and_srst separate
+
+adapter srst delay 100
+jtag_ntrst_delay 100
+
+source [find target/ixp42x.cfg]
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init { init_actux3 }
+
+proc init_actux3 { } {
+    ##########################################################################
+    # setup expansion bus CS
+    ##########################################################################
+    mww 0xc4000000  0xbd113842  ;#CS0  : Flash, write enabled @0x50000000
+    mww 0xc4000004  0x94d10013  ;#CS1
+    mww 0xc4000008  0x95960003  ;#CS2
+    mww 0xc400000c  0x00000000  ;#CS3
+    mww 0xc4000010  0x80900003  ;#CS4
+    mww 0xc4000014  0x9d520003  ;#CS5
+    mww 0xc4000018  0x81860001  ;#CS6
+    mww 0xc400001c  0x80900003  ;#CS7
+
+    ixp42x_init_sdram $::IXP42x_SDRAM_16MB_4Mx16_1BANK 2100 3
+
+    #mww 0xc4000020  0xffffee ;# CFG0: remove expansion bus boot flash mirror at 0x00000000
+
+    ixp42x_set_bigendian
+
+    flash probe 0
+}
+
+proc flash_boot { {FILE "/tftpboot/actux3/u-boot.bin"} } {
+    echo "writing bootloader: $FILE"
+    flash write_image erase $FILE 0x50000000 bin
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
+
+init
+reset init
+
+# setup to debug u-boot in flash
+proc uboot_debug {} {
+    gdb_breakpoint_override hard
+    xscale vector_catch 0xFF
+
+    xscale vector_table low  1 0xe59ff018
+    xscale vector_table low  2 0xe59ff018
+    xscale vector_table low  3 0xe59ff018
+    xscale vector_table low  4 0xe59ff018
+    xscale vector_table low  5 0xe59ff018
+    xscale vector_table low  6 0xe59ff018
+    xscale vector_table low  7 0xe59ff018
+
+    xscale vector_table high 1 0xe59ff018
+    xscale vector_table high 2 0xe59ff018
+    xscale vector_table high 3 0xe59ff018
+    xscale vector_table high 4 0xe59ff018
+    xscale vector_table high 5 0xe59ff018
+    xscale vector_table high 6 0xe59ff018
+    xscale vector_table high 7 0xe59ff018
+}
--- a/scripts/board/adapteva_parallella1.cfg
+++ b/scripts/board/adapteva_parallella1.cfg
@ -0,0 +1,7 @@
+#
+# Adapteva Parallella-I board (via Porcupine-1 adapter board)
+#
+
+reset_config srst_only
+
+source [find target/zynq_7000.cfg]
--- a/scripts/board/adsp-sc584-ezbrd.cfg
+++ b/scripts/board/adsp-sc584-ezbrd.cfg
@ -0,0 +1,30 @@
+#
+# Analog Devices ADSP-SC584-EZBRD evaluation board
+#
+# Evaluation boards by Analog Devices (and designs derived from them) use a
+# non-standard 10-pin 0.05" ARM Cortex Debug Connector.  In this bastardized
+# implementation, pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST.
+#
+# As a result, a standards-compliant debug pod will force /TRST active,
+# putting the processor's debug interface into reset and preventing usage.
+#
+# A connector adapter must be employed on these boards to isolate or remap
+# /TRST so that it is only asserted when intended.
+
+# Analog expects users to use their proprietary ICE-1000 / ICE-2000 with all
+# ADSP-SC58x designs, but this is an ARM target (and subject to the
+# qualifications above) many ARM debug pods should be compatible.
+
+#source [find interface/cmsis-dap.cfg]
+source [find interface/jlink.cfg]
+
+# Analog's silicon supports SWD and JTAG, but their proprietary ICE is limited
+# to JTAG.  (This is presumably why their connector pinout was modified.)
+# SWD is chosen here, as it is more efficient and doesn't require /TRST.
+
+transport select swd
+
+# chosen speed is 'safe' choice, but your adapter may be capable of more
+adapter speed 400
+
+source [find target/adsp-sc58x.cfg]
--- a/scripts/board/alphascale_asm9260_ek.cfg
+++ b/scripts/board/alphascale_asm9260_ek.cfg
@ -0,0 +1,69 @@
+source [find target/alphascale_asm9260t.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event reset-init {
+	echo "Configure clock"
+	# Enable SRAM clk
+	mww 0x80040024 0x4
+	# Enable IRQ clk
+	mww 0x80040034 0x100
+	# Enable DMA0,1 clk
+	mww 0x80040024 0x600
+	# Make sysre syspll is enabled
+	mww 0x80040238 0x750
+	#CPU = PLLCLK/2
+	mww 0x8004017C 0x2
+	#SYSAHBCLK = CPUCLK/2
+	mww 0x80040180 0x2
+	# Set PLL freq to 480MHz
+	mww 0x80040100 480
+	# normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0)
+	sleep 100
+
+	# select PLL as main source
+	mww 0x80040120 0x1
+	# disable and enable main clk to update changes?
+	mww 0x80040124 0x0
+	mww 0x80040124 0x1
+
+	echo "Configure memory"
+	#enable EMI CLK
+	mww 0x80040024 0x40
+
+	# configure memory controller for internal SRAM
+	mww 0x80700000 0x1188
+	# change default emi clk delay
+	mww 0x8004034C 0xA0503
+	# make sure chip_select_register2_low has correct value (why?)
+	mww 0x8070001c 0x20000000
+	# set type to sdram and size to 32MB
+	mww 0x8070005c 0xa
+	# configure internal SDRAM timing
+	mww 0x80700004 0x024996d9
+	# configure Static Memory timing
+	mww 0x80700094 0x00542b4f
+
+	echo "Configure uart4"
+	# enable pinctrl clk
+	mww 0x80040024 0x2000000
+	# mux GPIO3_0 and GPIO3_1 to UART4
+	mww 0x80044060 0x2
+	mww 0x80044064 0x2
+	# configure UART4CLKDIV
+	mww 0x800401a8 0x1
+	# enable uart4 clk
+	mww 0x80040024 0x8000
+	# clear softrst and clkgate on uart4
+	mww 0x80010008 0xC0000000
+	# set bandrate 115200 12M
+	mww 0x80010030 0x00062070
+	# enable Rx&Tx
+	mww 0x80010024 0x301
+	# clear hw control
+	mww 0x80010028 0xc000
+}
+
+$_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000
+$_TARGETNAME arm7_9 fast_memory_access enable
+$_TARGETNAME arm7_9 dcc_downloads enable
--- a/scripts/board/altera_sockit.cfg
+++ b/scripts/board/altera_sockit.cfg
@ -0,0 +1,18 @@
+#
+# Cyclone V SocKit board
+# http://www.altera.com/b/arrow-sockit.html
+#
+# Software support page:
+# http://www.rocketboards.org/
+
+# openocd does not currently support the on-board USB Blaster II.
+# Install the JTAG header and use a USB Blaster instead.
+adapter driver usb_blaster
+
+source [find target/altera_fpgasoc.cfg]
+
+# If the USB Blaster II were supported, these settings would be needed
+#usb_blaster vid_pid 0x09fb 0x6810
+#usb_blaster device_desc "USB-Blaster II"
+
+adapter speed 100
--- a/scripts/board/am3517evm.cfg
+++ b/scripts/board/am3517evm.cfg
@ -0,0 +1,20 @@
+# DANGER!!!! early work in progress for this PCB/target.
+#
+# The most basic operations work well enough that it is
+# useful to have this in the repository for cooperation
+# alpha testing purposes.
+#
+# TI AM3517
+#
+# http://focus.ti.com/docs/prod/folders/print/am3517.html
+# http://processors.wiki.ti.com/index.php/Debug_Access_Port_(DAP)
+# http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x
+
+set CHIPTYPE "am35x"
+source [find target/amdm37x.cfg]
+
+# The TI-14 JTAG connector does not have srst.  CPU reset is handled in
+# hardware.
+reset_config trst_only
+
+# "amdm37x_dbginit am35x.cpu" needs to be run after init.
--- a/scripts/board/ampere_emag8180.cfg
+++ b/scripts/board/ampere_emag8180.cfg
@ -0,0 +1,38 @@
+#
+# OpenOCD Board Configuration for eMAG Development Platform
+#
+# Copyright (c) 2019-2021, Ampere Computing LLC
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program;
+#
+#
+
+#
+# Configure JTAG speed
+#
+
+adapter speed 2000
+
+#
+# Configure Resets
+#
+
+jtag_ntrst_delay 100
+reset_config trst_only
+
+#
+# Configure Targets
+#
+
+source [find target/ampere_emag.cfg]
--- a/scripts/board/arm_evaluator7t.cfg
+++ b/scripts/board/arm_evaluator7t.cfg
@ -0,0 +1,9 @@
+# This board is from ARM and has an samsung s3c45101x01 chip
+
+source [find target/samsung_s3c4510.cfg]
+
+#
+# FIXME:
+#  Add (A) sdram configuration
+#  Add (B) flash cfi programming configuration
+#
--- a/scripts/board/arm_musca_a.cfg
+++ b/scripts/board/arm_musca_a.cfg
@ -0,0 +1,44 @@
+#
+# Configuration script for ARM Musca-A development board
+#
+# For now we do not support Musca A flash programming using OpenOCD. However, a
+# work area is configured for flash programming speed up.
+#
+# GDB considers all memory as RAM unless target supplies a memory map.
+# OpenOCD will only send memory map if flash banks are configured. Otherwise,
+# configure GDB after connection by issuing following commands:
+# (gdb) mem 0x10200000 0x109FFFFF ro
+# (gdb) mem 0x00200000 0x009FFFFF ro
+# (gdb) set mem inaccessible-by-default off
+
+# ARM Musca A board supports both JTAG and SWD transports.
+source [find target/swj-dp.tcl]
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+global _CHIPNAME
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME MUSCA_A
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x6ba00477
+}
+
+# Enable CPU1 debugging as a separate GDB target
+set _ENABLE_CPU1 1
+
+# Musca A1 has 32KB SRAM banks. Override default work-area-size to 8KB per CPU
+set WORKAREASIZE_CPU0 0x2000
+set WORKAREASIZE_CPU1 0x2000
+
+# Set SRAM bank 1 to be used for work area. Override here if needed.
+set WORKAREAADDR_CPU0 0x30008000
+set WORKAREAADDR_CPU1 0x3000A000
+
+source [find target/arm_corelink_sse200.cfg]
--- a/scripts/board/arty_s7.cfg
+++ b/scripts/board/arty_s7.cfg
@ -0,0 +1,35 @@
+#
+# Arty S7: Spartan7 25/50 FPGA Board for Makers and Hobbyists
+#
+# https://www.xilinx.com/products/boards-and-kits/1-pnziih.html
+# https://store.digilentinc.com/arty-s7-spartan-7-fpga-board-for-makers-and-hobbyists/
+
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# Xilinx Spartan7-25/50 FPGA (XC7S{25,50}-CSGA324)
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+
+adapter speed 25000
+
+# Usage:
+#
+# Load Bitstream into FPGA:
+#    openocd -f board/arty_s7.cfg -c "init;\
+#    pld load 0 bitstream.bit;\
+#    shutdown"
+#
+# Write Bitstream to Flash:
+#    openocd -f board/arty_s7.cfg -c "init;\
+#    jtagspi_init 0 bscan_spi_xc7s??.bit;\
+#    jtagspi_program bitstream.bin 0;\
+#    xc7_program xc7.tap;\
+#    shutdown"
+#
+# jtagspi flash proxies can be found at:
+# https://github.com/quartiq/bscan_spi_bitstreams
+#
+# For the Spartan 50 variant, use
+#  - https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s50.bit
+# For the Spartan 25 variant, use
+#  - https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s25.bit
--- a/scripts/board/asus-rt-n16.cfg
+++ b/scripts/board/asus-rt-n16.cfg
@ -0,0 +1,15 @@
+#
+# http://wikidevi.com/wiki/ASUS_RT-N16
+#
+
+set partition_list {
+    CFE		{ Bootloader			0xbc000000 0x00040000 }
+    firmware	{ "Kernel+rootfs"		0xbc040000 0x01fa0000 }
+    nvram	{ "Config space"		0xbdfe0000 0x00020000 }
+}
+
+source [find target/bcm4718.cfg]
+
+# External 32MB NOR Flash (Macronix MX29GL256EHTI2I-90Q)
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 1 1 $_TARGETNAME x16_as_x8
--- a/scripts/board/asus-rt-n66u.cfg
+++ b/scripts/board/asus-rt-n66u.cfg
@ -0,0 +1,19 @@
+#
+# http://wikidevi.com/wiki/Asus_RT-N66U
+#
+
+echo "ATTENTION: you need to solder a 4.7-10k pullup resistor to pin 21 of flash IC"
+echo "to enable JTAG, see http://wl500g.info/album.php?albumid=28&attachmentid=8991 ,"
+echo "there is an unpopulated footprint near U8.\n"
+
+set partition_list {
+    CFE		{ Bootloader			0xbc000000 0x00040000 }
+    firmware	{ "Kernel+rootfs"		0xbc040000 0x01fa0000 }
+    nvram	{ "Config space"		0xbdfe0000 0x00020000 }
+}
+
+source [find target/bcm4706.cfg]
+
+# External 32MB NOR Flash (Spansion S29GL256P10TF101
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 2 2 $_TARGETNAME
--- a/scripts/board/at91cap7a-stk-sdram.cfg
+++ b/scripts/board/at91cap7a-stk-sdram.cfg
@ -0,0 +1,163 @@
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394
+#
+# use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME cap7
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x40700f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-start {
+	# start off real slow when we're running off internal RC oscillator
+	adapter speed 32
+}
+
+proc peek32 {address} {
+	return [read_memory $address 32 1]
+}
+
+# Wait for an expression to be true with a timeout
+proc wait_state {expression} {
+	for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} {
+		if {[uplevel 1 $expression] == 0} {
+			return
+		}
+	}
+	return -code 1 "Timed out"
+}
+
+# Use a global variable here to be able to tinker interactively with
+# post reset jtag frequency.
+global post_reset_khz
+# Danger!!!! Even 16MHz kinda works with this target, but
+# it needs to be as low as 2000kHz to be stable.
+set post_reset_khz 2000
+
+$_TARGETNAME configure -event reset-init {
+	echo "Configuring master clock"
+	# disable watchdog
+	mww 0xfffffd44 0xff008000
+	# enable user reset
+	mww 0xfffffd08 0xa5000001
+	# Enable main oscillator
+	mww 0xFFFFFc20  0x00000f01
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
+
+	# Set PLLA to 96MHz
+	mww 0xFFFFFc28 0x20072801
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
+
+	# Select prescaler
+	mww 0xFFFFFC30 0x00000004
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
+
+	# Select master clock to 48MHz
+	mww 0xFFFFFC30 0x00000006
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
+
+	echo "Master clock ok."
+
+	# Now that we're up and running, crank up speed!
+	global post_reset_khz ;	adapter speed $post_reset_khz
+
+	echo "Configuring the SDRAM controller..."
+
+	# Configure EBI Chip select for SDRAM
+	mww 0xFFFFEF30 0x00000102
+
+	# Enable clock on EBI PIOs
+	mww 0xFFFFFC10 0x00000004
+
+	# Configure PIO for SDRAM
+	mww 0xFFFFF470 0xFFFF0000
+	mww 0xFFFFF474 0x00000000
+	mww 0xFFFFF404 0xFFFF0000
+
+	# Configure SDRAMC CR
+	mww 0xFFFFEA08 0xA63392F9
+
+	# NOP command
+	mww 0xFFFFEA00 0x1
+	mww 0x20000000 0
+
+	# Precharge All Banks command
+	mww 0xFFFFEA00 0x2
+	mww 0x20000000 0
+
+	# Set 1st CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000010 0x00000001
+
+	# Set 2nd CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000020 0x00000002
+
+	# Set 3rd CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000030 0x00000003
+
+	# Set 4th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000040 0x00000004
+
+	# Set 5th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000050 0x00000005
+
+	# Set 6th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000060 0x00000006
+
+	# Set 7th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000070 0x00000007
+
+	# Set 8th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000080 0x00000008
+
+	# Set LMR operation
+	mww 0xFFFFEA00 0x00000003
+
+	# Perform LMR burst=1, lat=2
+	mww 0x20000020 0xCAFEDEDE
+
+	# Set Refresh Timer
+	mww 0xFFFFEA04 0x00000203
+
+	# Set Normal mode
+	mww 0xFFFFEA00 0x00000000
+	mww 0x20000000 0x00000000
+
+	#remap internal memory at address 0x0
+	mww 0xffffef00 0x3
+
+	echo "SDRAM configuration ok."
+}
+
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+#set _FLASHNAME $_CHIPNAME.flash
+#flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
--- a/scripts/board/at91eb40a.cfg
+++ b/scripts/board/at91eb40a.cfg
@ -0,0 +1,67 @@
+#Script for AT91EB40a
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME at91eb40a
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1f0f0f0f
+}
+
+
+#Atmel ties SRST & TRST together, at which point it makes
+#no sense to use TRST, but use TMS instead.
+#
+#The annoying thing with tying SRST & TRST together is that
+#there is no way to halt the CPU *before and during* the
+#SRST reset, which means that the CPU will run a number
+#of cycles before it can be halted(as much as milliseconds).
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#target configuration
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# speed up memory downloads
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+#flash driver
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x01000000 0x200000 2 2 $_TARGETNAME
+
+# required for usable performance. Used for lots of
+# other things than flash programming.
+$_TARGETNAME configure -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init {
+	echo "Running reset init script for AT91EB40A"
+	# Reset script for AT91EB40a
+	reg cpsr 0x000000D3
+	mww 0xFFE00020 0x1
+	mww 0xFFE00024 0x00000000
+	mww 0xFFE00000 0x01002539
+	mww 0xFFFFF124 0xFFFFFFFF
+	mww 0xffff0010 0x100
+	mww 0xffff0034 0x100
+}
+
+# This target is pretty snappy...
+adapter speed 16000
--- a/scripts/board/at91rm9200-dk.cfg
+++ b/scripts/board/at91rm9200-dk.cfg
@ -0,0 +1,82 @@
+#
+# This is for the "at91rm9200-DK" (not the EK) eval board.
+#
+# The two are probably very simular.... I have DK...
+#
+# It has atmel at91rm9200 chip.
+source [find target/at91rm9200.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
+
+#flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00200000 2 2 $_TARGETNAME
+
+
+proc at91rm9200_dk_init { } {
+    # Try to run at 1khz... Yea, that slow!
+    # Chip is really running @ 32khz
+    adapter speed 8
+
+    mww 0xfffffc64 0xffffffff
+    ##  disable all clocks but system clock
+    mww 0xfffffc04 0xfffffffe
+    ##  disable all clocks to pioa and piob
+    mww 0xfffffc14 0xffffffc3
+    ##  master clock = slow cpu = slow
+    ##  (means the CPU is running at 32khz!)
+    mww 0xfffffc30 0
+    ##  main osc enable
+    mww 0xfffffc20 0x0000ff01
+    ##  program pllA
+    mww 0xfffffc28 0x20263e04
+    ##  program pllB
+    mww 0xfffffc2c 0x10483e0e
+    ##  let pll settle... sleep 100msec
+    sleep 100
+    ##  switch to fast clock
+    mww 0xfffffc30 0x202
+    ## Sleep some - (go read)
+    sleep 100
+
+    #========================================
+    # CPU now runs at 180mhz
+    # SYS runs at 60mhz.
+    adapter speed 40000
+    #========================================
+
+
+    ##  set memc for all memories
+    mww 0xffffff60 0x02
+    ##  program smc controller
+    mww 0xffffff70 0x3284
+    ##  init sdram
+    mww 0xffffff98 0x7fffffd0
+    ##  all banks precharge
+    mww 0xffffff80 0x02
+    ##  touch sdram chip to make it work
+    mww 0x20000000 0
+    ##  sdram controller mode register
+    mww 0xffffff90 0x04
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    ##  sdram controller mode register
+    ##  Refresh, etc....
+    mww 0xffffff90 0x03
+    mww 0x20000080 0
+    mww 0xffffff94 0x1f4
+    mww 0x20000080 0
+    mww 0xffffff90 0x10
+    mww 0x20000000 0
+    mww 0xffffff00 0x01
+
+}
--- a/scripts/board/at91rm9200-ek.cfg
+++ b/scripts/board/at91rm9200-ek.cfg
@ -0,0 +1,114 @@
+#
+# Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+#
+# under GPLv2 Only
+#
+# This is for the "at91rm9200-ek" eval board.
+#
+#
+# It has atmel at91rm9200 chip.
+source [find target/at91rm9200.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91rm9200_ek_init }
+
+## flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+
+# The chip may run @ 32khz, so set a really low JTAG speed
+adapter speed 8
+
+proc at91rm9200_ek_init { } {
+	# Try to run at 1khz... Yea, that slow!
+	# Chip is really running @ 32khz
+	adapter speed 8
+
+	mww 0xfffffc64 0xffffffff
+	## disable all clocks but system clock
+	mww 0xfffffc04 0xfffffffe
+	## disable all clocks to pioa and piob
+	mww 0xfffffc14 0xffffffc3
+	## master clock = slow cpu = slow
+	## (means the CPU is running at 32khz!)
+	mww 0xfffffc30 0
+	## main osc enable
+	mww 0xfffffc20 0x0000ff01
+	## MC_PUP
+	mww 0xFFFFFF50 0x00000000
+	## MC_PUER: Memory controller protection unit disable
+	mww 0xFFFFFF54 0x00000000
+	## EBI_CFGR
+	mww 0xFFFFFF64 0x00000000
+	## SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
+	mww 0xFFFFFF70 0x00003284
+
+	## Init Clocks
+	## CKGR_PLLAR
+	mww 0xFFFFFC28 0x2000BF05
+	## PLLAR: 179,712000 MHz for PCK
+	mww 0xFFFFFC28 0x20263E04
+	sleep 100
+	## PMC_MCKR
+	mww 0xFFFFFC30 0x00000100
+	sleep 100
+	## ;MCKR : PCK/3 = MCK Master Clock = 59,904000MHz from PLLA
+	mww 0xFFFFFC30 0x00000202
+	sleep 100
+
+	#========================================
+	# CPU now runs at 180mhz
+	# SYS runs at 60mhz.
+	adapter speed 40000
+	#========================================
+
+	## Init SDRAM
+	## PIOC_ASR: Configure PIOC as peripheral (D16/D31)
+	mww 0xFFFFF870 0xFFFF0000
+	## PIOC_BSR:
+	mww 0xFFFFF874 0x00000000
+	## PIOC_PDR:
+	mww 0xFFFFF804 0xFFFF0000
+	## EBI_CSA : CS1=SDRAM
+	mww 0xFFFFFF60 0x00000002
+	## EBI_CFGR:
+	mww 0xFFFFFF64 0x00000000
+	## SDRC_CR :
+	mww 0xFFFFFF98 0x2188c155
+	## SDRC_MR : Precharge All
+	mww 0xFFFFFF90 0x00000002
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Refresh
+	mww 0xFFFFFF90 0x00000004
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Load Mode Register
+	mww 0xFFFFFF90 0x00000003
+	## access SDRAM
+	mww 0x20000080 0x00000000
+	## SDRC_TR : Write refresh rate
+	mww 0xFFFFFF94 0x000002E0
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Normal Mode
+	mww 0xFFFFFF90 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+}
--- a/scripts/board/at91sam9261-ek.cfg
+++ b/scripts/board/at91sam9261-ek.cfg
@ -0,0 +1,63 @@
+################################################################################
+# Atmel AT91SAM9261-EK eval board
+################################################################################
+
+source [find mem_helper.tcl]
+source [find target/at91sam9261.cfg]
+uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9261.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9261_matrix.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9261.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+scan_chain
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91sam9261ek_reset_init }
+$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
+
+proc at91sam9261ek_reset_init { } {
+
+	;# for ppla at 199 Mhz
+	set config(master_pll_div)	15
+	set config(master_pll_mul)	162
+
+	;# for ppla at 239 Mhz
+	;# set master_pll_div	1
+	;# set master_pll_mul	13
+
+	set val	$::AT91_WDT_WDV							;# Counter Value
+	set val	[expr {$val | $::AT91_WDT_WDDIS}]		;# Watchdog Disable
+	set val	[expr {$val | $::AT91_WDT_WDD}]			;# Delta Value
+	set val	[expr {$val | $::AT91_WDT_WDDBGHLT}]	;# Debug Halt
+	set val	[expr {$val | $::AT91_WDT_WDIDLEHLT}]	;# Idle Halt
+
+	set config(wdt_mr_val) $val
+
+	;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
+	set config(matrix_ebicsa_addr)	$::AT91_MATRIX_EBICSA
+	set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]
+
+	;# SDRAMC_CR - Configuration register
+	set val $::AT91_SDRAMC_NC_9
+	set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+	set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+	set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+	set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+	set val [expr {$val | (2 <<  8)}]		;# Write Recovery Delay
+	set val [expr {$val | (7 << 12)}]		;# Row Cycle Delay
+	set val [expr {$val | (3 << 16)}]		;# Row Precharge Delay
+	set val [expr {$val | (2 << 20)}]		;# Row to Column Delay
+	set val [expr {$val | (5 << 24)}]		;# Active to Precharge Delay
+	set val [expr {$val | (8 << 28)}]		;# Exit Self Refresh to Active Delay
+
+	set config(sdram_cr_val) $val
+
+	set config(sdram_tr_val) 0x13c
+
+	set config(sdram_base) $::AT91_CHIPSELECT_1
+	at91sam9_reset_init $config
+}
--- a/scripts/board/at91sam9263-ek.cfg
+++ b/scripts/board/at91sam9263-ek.cfg
@ -0,0 +1,63 @@
+################################################################################
+# Atmel AT91SAM9263-EK eval board
+################################################################################
+
+source [find mem_helper.tcl]
+source [find target/at91sam9263.cfg]
+uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9263.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9263_matrix.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9263.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+scan_chain
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91sam9263ek_reset_init }
+$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
+
+proc at91sam9263ek_reset_init { } {
+
+	set config(master_pll_div)	14
+	set config(master_pll_mul)	171
+
+	set val	$::AT91_WDT_WDV							;# Counter Value
+	set val	[expr {$val | $::AT91_WDT_WDDIS}]		;# Watchdog Disable
+	set val	[expr {$val | $::AT91_WDT_WDD}]			;# Delta Value
+	set val	[expr {$val | $::AT91_WDT_WDDBGHLT}]	;# Debug Halt
+	set val	[expr {$val | $::AT91_WDT_WDIDLEHLT}]	;# Idle Halt
+
+	set config(wdt_mr_val) $val
+
+	set config(sdram_piod) 1
+	;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
+	set config(matrix_ebicsa_addr)	$::AT91_MATRIX_EBI0CSA
+
+	set val	$::AT91_MATRIX_EBI0_DBPUC
+	set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}]
+	set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}]
+	set config(matrix_ebicsa_val) $val
+
+	;# SDRAMC_CR - Configuration register
+	set val $::AT91_SDRAMC_NC_9
+	set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+	set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+	set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+	set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+	set val [expr {$val | (1 <<  8)}]		;# Write Recovery Delay
+	set val [expr {$val | (7 << 12)}]		;# Row Cycle Delay
+	set val [expr {$val | (2 << 16)}]		;# Row Precharge Delay
+	set val [expr {$val | (2 << 20)}]		;# Row to Column Delay
+	set val [expr {$val | (5 << 24)}]		;# Active to Precharge Delay
+	set val [expr {$val | (1 << 28)}]		;# Exit Self Refresh to Active Delay
+
+	set config(sdram_cr_val) $val
+
+	set config(sdram_tr_val) 0x13c
+
+	set config(sdram_base) $::AT91_CHIPSELECT_1
+	at91sam9_reset_init $config
+}
--- a/scripts/board/at91sam9g20-ek.cfg
+++ b/scripts/board/at91sam9g20-ek.cfg
@ -0,0 +1,216 @@
+#################################################################################################
+#												#
+# Author: Gary Carlson (gcarlson@carlson-minot.com)						#
+# Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8.	#
+#												#
+#################################################################################################
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+source [find target/at91sam9g20.cfg]
+
+set _FLASHTYPE nandflash_cs3
+
+# Set reset type.  Note that the AT91SAM9G20-EK board has the trst signal disconnected.  Therefore
+# the reset needs to be configured for "srst_only".  If for some reason, a zero-ohm jumper is
+# added to the board to connect the trst signal, then this parameter may need to be changed.
+
+reset_config srst_only
+
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
+# AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has
+# some powerful features, we want to have a special function that handles "reset init".  To do this we declare
+# an event handler where these special activities can take place.
+
+scan_chain
+$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
+$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
+
+# NandFlash configuration and definition
+
+nand device nandflash_cs3 at91sam9 $_TARGETNAME 0x40000000 0xfffffe800
+at91sam9 cle 0 22
+at91sam9 ale 0 21
+at91sam9 rdy_busy 0 0xfffff800 13
+at91sam9 ce 0 0xfffff800 14
+
+proc read_register {register} {
+	return [read_memory $register 32 1]
+}
+
+proc at91sam9g20_reset_start { } {
+
+	# Make sure that the the jtag is running slow, since there are a number of different ways the board
+	# can be configured coming into this state that can cause communication problems with the jtag
+	# adapter.  Also since this call can be made following a "reset init" where fast memory accesses
+	# are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
+	# jtag speed without causing GDB keep alive problem.
+
+	arm7_9 fast_memory_access disable
+	adapter speed 2                 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+	halt                            ;# Make sure processor is halted, or error will result in following steps.
+	wait_halt 10000
+	mww 0xfffffd08 0xa5000501       ;# RSTC_MR : enable user reset.
+}
+
+proc at91sam9g20_reset_init { } {
+
+	# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
+	# a number of steps that must be carefully performed.  The process outline below follows the
+	# recommended procedure outlined in the AT91SAM9G20 technical manual.
+	#
+	# Several key and very important things to keep in mind:
+	# The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts.  This
+	# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
+	# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
+
+	mww 0xfffffd44 0x00008000	;# WDT_MR : disable watchdog.
+
+	# Enable the main 18.432 MHz oscillator in CKGR_MOR register.
+	# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
+
+	mww 0xfffffc20 0x00004001
+	while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
+
+	# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
+	# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
+
+	mww 0xfffffc28 0x202a3f01
+	while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
+
+	# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
+	# Wait for MCKRDY signal from PMC_SR to assert.
+
+	mww 0xfffffc30 0x00000101
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
+
+	# Now change PMC_MCKR register to select PLLA.
+	# Wait for MCKRDY signal from PMC_SR to assert.
+
+	mww 0xfffffc30 0x00001302
+	while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
+
+	# Processor and master clocks are now operating and stable at maximum frequency possible:
+	#	-> MCLK = 132.096 MHz
+	#	-> PCLK = 396.288 MHz
+
+	# Switch over to adaptive clocking.
+
+	adapter speed 0
+
+	# Enable faster DCC downloads and memory accesses.
+
+	arm7_9 dcc_downloads enable
+	arm7_9 fast_memory_access enable
+
+	# To be able to use external SDRAM, several peripheral configuration registers must
+	# be modified.  The first change is made to PIO_ASR to select peripheral functions
+	# for D15 through D31.  The second change is made to the PIO_PDR register to disable
+	# this for D15 through D31.
+
+	mww 0xfffff870 0xffff0000
+	mww 0xfffff804 0xffff0000
+
+	# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
+	# using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on
+	# the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
+
+	mww 0xffffef1c 0x000100a
+
+	# The AT91SAM9G20-EK evaluation board has built-in NandFlash.  The exact physical timing characteristics
+	# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
+	# a number of registers.  The first step involves setting up the general I/O pins on the processor
+	# to be able to interface and support the external memory.
+
+	mww 0xfffffc10 0x00000010	;# PMC_PCER : enable PIOC clock
+	mww 0xfffff800 0x00006000	;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
+	mww 0xfffff810 0x00004000	;# PIOC_OER : enable output on 14
+	mww 0xfffff814 0x00002000	;# PIOC_ODR : disable output on 13
+    	mww 0xfffff830 0x00004000	;# PIOC_SODR : set 14 to disable NAND
+
+	# The exact physical timing characteristics for the memory type used on the current board
+	# (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,
+	# SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.  Computing the exact values of these registers
+	# is a little tedious to do here.  If you have questions about how to do this, Atmel has
+	# a decent application note #6255B that covers this process.
+
+	mww 0xffffec30 0x00020002	;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
+	mww 0xffffec34 0x04040404	;# SMC_PULSE3 : 4 clock cycle pulse for all signals
+	mww 0xffffec38 0x00070006	;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
+	mww 0xffffec3C 0x00020003	;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+
+	mww 0xffffe800 0x00000001	;# ECC_CR : reset the ECC parity registers
+	mww 0xffffe804 0x00000002	;# ECC_MR : page size is 2112 words (word is 8 bits)
+
+	# Identify NandFlash bank 0.
+
+	nand probe nandflash_cs3
+
+	# The AT91SAM9G20-EK evaluation board has built-in serial data flash also.
+
+	# Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
+	# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference
+	# for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
+	# into the SDRAM_CR register.  Using the memory datasheet for the -75 grade part and assuming a master clock
+	# of 132.096 MHz then the SDCLK period is equal to 7.6 ns.  This means the device requires:
+	#
+	#	CAS latency = 3 cycles
+	#	TXSR = 10 cycles
+	#	TRAS = 6 cycles
+	#	TRCD = 3 cycles
+	#	TRP = 3 cycles
+	#	TRC = 9 cycles
+	#	TWR = 2 cycles
+	#	9 column, 13 row, 4 banks
+	#	refresh equal to or less then 7.8 us for commercial/industrial rated devices
+	#
+	#	Thus SDRAM_CR = 0xa6339279
+
+	mww 0xffffea08 0xa6339279
+
+	# Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
+	# the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x00000001
+	mww 0x20000000 0
+
+	# Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
+	# value into the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x00000002
+	mww 0x20000000 0
+
+	# Now issue an 'Auto-Refresh' command through the SDRAMC_MR register.  Follow this operation by writing
+	# zero values eight times into the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+
+	# Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
+	# the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x3
+	mww 0x20000000 0
+
+	# Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting
+	# memory location for the SDRAM.
+
+	mww 0xffffea00 0x0
+	mww 0x20000000 0
+
+	# Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
+
+	mww 0xffffea04 0x0000039c
+}
--- a/scripts/board/atmel_at91sam7s-ek.cfg
+++ b/scripts/board/atmel_at91sam7s-ek.cfg
@ -0,0 +1,6 @@
+# Atmel AT91SAM7S-EK
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784
+
+set CHIPNAME at91sam7s256
+
+source [find target/at91sam7sx.cfg]
--- a/scripts/board/atmel_at91sam9260-ek.cfg
+++ b/scripts/board/atmel_at91sam9260-ek.cfg
@ -0,0 +1,81 @@
+################################################################################
+# Atmel AT91SAM9260-EK eval board
+#
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
+#
+# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
+#                     OSCSEL configured for external 32.768 kHz crystal
+#
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
+#
+################################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9260.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 32.768 kHz.
+        # JTAG Frequency must be 6 times slower if RCLK is not supported.
+        jtag_rclk 5
+        halt
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        mww phys 0xfffffd08 0xa5000501
+}
+
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
+        sleep 10                          ;# wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+	mww 0xfffff870 0xffff0000         ;# PIO_ASR  : Select peripheral function for D15..D31
+        mww 0xfffff804 0xffff0000         ;# PIO_PDR  : Disable PIO function for D15..D31
+
+        mww 0xffffef1c 0x00010002         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2b6              ;# SDRAMC_TR : Set refresh timer count to 7us
+}
--- a/scripts/board/atmel_at91sam9rl-ek.cfg
+++ b/scripts/board/atmel_at91sam9rl-ek.cfg
@ -0,0 +1,75 @@
+################################################################################
+#
+# Generated for Atmel AT91SAM9RL-EK evaluation board using Atmel SAM-ICE (J-Link) V6
+#
+# Atmel AT91SAM9RL : PLL = 200 MHz, MCK = 100 MHz
+#                     OSCSEL configured for external 32.768 kHz crystal
+#
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
+#
+################################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9rl.cfg]
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 32.768 kHz.
+        # JTAG Frequency must be 6 times slower if RCLK is not supported.
+        jtag_rclk 5
+        halt
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        mww phys 0xfffffd08 0xa5000501
+}
+
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc28 0x2031bf03         ;# CKGR_PLLR: Set PLL Register for 200 MHz
+        sleep 20                          ;# wait 20 ms
+        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          ;# wait 10 ms
+        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLL is selected (100 MHz)
+        sleep 10                          ;# wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
+
+	mww 0xfffff670 0xffff0000         ;# PIO_ASR  : Select peripheral function for D16..D31 (PIOB)
+        mww 0xfffff604 0xffff0000         ;# PIO_PDR  : Disable PIO function for D16..D31 (PIOB)
+
+        mww 0xffffef20 0x00010002         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+	mww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2b6              ;# SDRAMC_TR : Set refresh timer count to 7us
+}
--- a/scripts/board/atmel_sam3n_ek.cfg
+++ b/scripts/board/atmel_sam3n_ek.cfg
@ -0,0 +1,12 @@
+
+#
+# Board configuration for Atmel's SAM3N-EK
+#
+
+reset_config srst_only
+
+set CHIPNAME at91sam3n4c
+
+adapter speed 32
+
+source [find target/at91sam3nXX.cfg]
--- a/scripts/board/atmel_sam3s_ek.cfg
+++ b/scripts/board/atmel_sam3s_ek.cfg
@ -0,0 +1 @@
+source [find target/at91sam3sXX.cfg]
--- a/scripts/board/atmel_sam3u_ek.cfg
+++ b/scripts/board/atmel_sam3u_ek.cfg
@ -0,0 +1,3 @@
+source [find target/at91sam3u4e.cfg]
+
+reset_config srst_only
--- a/scripts/board/atmel_sam3x_ek.cfg
+++ b/scripts/board/atmel_sam3x_ek.cfg
@ -0,0 +1,3 @@
+source [find target/at91sam3ax_8x.cfg]
+
+reset_config srst_only
--- a/scripts/board/atmel_sam4e_ek.cfg
+++ b/scripts/board/atmel_sam4e_ek.cfg
@ -0,0 +1,7 @@
+# This is an SAM4E-EK board with a single SAM4E16 chip.
+# http://www.atmel.com/tools/sam4e-ek.aspx
+
+# chip name
+set CHIPNAME SAM4E16E
+
+source [find target/at91sam4sXX.cfg]
--- a/scripts/board/atmel_sam4l8_xplained_pro.cfg
+++ b/scripts/board/atmel_sam4l8_xplained_pro.cfg
@ -0,0 +1,11 @@
+#
+# Atmel SAM4L8 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAM4L8-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME ATSAM4LC8CA
+
+source [find target/at91sam4lXX.cfg]
--- a/scripts/board/atmel_sam4s_ek.cfg
+++ b/scripts/board/atmel_sam4s_ek.cfg
@ -0,0 +1 @@
+source [find target/at91sam4sXX.cfg]
--- a/scripts/board/atmel_sam4s_xplained_pro.cfg
+++ b/scripts/board/atmel_sam4s_xplained_pro.cfg
@ -0,0 +1,11 @@
+#
+# Atmel SAM4S Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAM4S-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME ATSAM4SD32C
+
+source [find target/at91sam4sd32x.cfg]
--- a/scripts/board/atmel_samc20_xplained_pro.cfg
+++ b/scripts/board/atmel_samc20_xplained_pro.cfg
@ -0,0 +1,10 @@
+#
+# Atmel SAMC20 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samc20j18
+
+source [find target/at91samdXX.cfg]
--- a/scripts/board/atmel_samc21_xplained_pro.cfg
+++ b/scripts/board/atmel_samc21_xplained_pro.cfg
@ -0,0 +1,11 @@
+#
+# Atmel SAMC21 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAMC21-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samc21j18
+
+source [find target/at91samdXX.cfg]
--- a/scripts/board/atmel_samd10_xplained_mini.cfg
+++ b/scripts/board/atmel_samd10_xplained_mini.cfg
@ -0,0 +1,10 @@
+#
+# Atmel SAMD10 Xplained mini evaluation kit.
+# http://www.atmel.com/tools/atsamd10-xmini.aspx
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd10d14
+
+source [find target/at91samdXX.cfg]
--- a/scripts/board/atmel_samd11_xplained_pro.cfg
+++ b/scripts/board/atmel_samd11_xplained_pro.cfg
@ -0,0 +1,10 @@
+#
+# Atmel SAMD11 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd11d14
+
+source [find target/at91samdXX.cfg]
--- a/scripts/board/atmel_samd20_xplained_pro.cfg
+++ b/scripts/board/atmel_samd20_xplained_pro.cfg
@ -0,0 +1,11 @@
+#
+# Atmel SAMD20 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAMD20-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd20j18
+
+source [find target/at91samdXX.cfg]
--- a/scripts/board/atmel_samd21_xplained_pro.cfg
+++ b/scripts/board/atmel_samd21_xplained_pro.cfg
@ -0,0 +1,10 @@
+#
+# Atmel SAMD21 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd21j18
+
+source [find target/at91samdXX.cfg]
--- a/scripts/board/atmel_same70_xplained.cfg
+++ b/scripts/board/atmel_same70_xplained.cfg
@ -0,0 +1,12 @@
+#
+# Atmel SAME70 Xplained evaluation kit.
+# http://www.atmel.com/tools/ATSAME70-XPLD.aspx
+#
+# Connect using the EDBG chip on the dev kit over USB
+source [find interface/cmsis-dap.cfg]
+
+set CHIPNAME atsame70q21
+
+source [find target/atsamv.cfg]
+
+reset_config srst_only
--- a/scripts/board/atmel_samg53_xplained_pro.cfg
+++ b/scripts/board/atmel_samg53_xplained_pro.cfg
@ -0,0 +1,11 @@
+#
+# Atmel SAMG53 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAMG53-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME ATSAMG53N19
+
+source [find target/at91samg5x.cfg]
--- a/scripts/board/atmel_samg55_xplained_pro.cfg
+++ b/scripts/board/atmel_samg55_xplained_pro.cfg
@ -0,0 +1,11 @@
+#
+# Atmel SAMG55 Xplained Pro evaluation kit.
+# http://www.atmel.com/tools/ATSAMG55-XPRO.aspx
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME ATSAMG55J19
+
+source [find target/at91samg5x.cfg]
--- a/scripts/board/atmel_saml21_xplained_pro.cfg
+++ b/scripts/board/atmel_saml21_xplained_pro.cfg
@ -0,0 +1,10 @@
+#
+# Atmel SAML21 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91saml21j18
+
+source [find target/at91samdXX.cfg]
--- a/scripts/board/atmel_samr21_xplained_pro.cfg
+++ b/scripts/board/atmel_samr21_xplained_pro.cfg
@ -0,0 +1,10 @@
+#
+# Atmel SAMR21 Xplained Pro evaluation kit.
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samr21g18
+
+source [find target/at91samdXX.cfg]
--- a/scripts/board/atmel_samv71_xplained_ultra.cfg
+++ b/scripts/board/atmel_samv71_xplained_ultra.cfg
@ -0,0 +1,12 @@
+#
+# Atmel SAMV71 Xplained Ultra evaluation kit.
+# http://www.atmel.com/tools/ATSAMV71-XULT.aspx
+#
+# To connect using the EDBG chip on the dev kit over USB, you will
+# first need to source [find interface/cmsis-dap.cfg]
+# however, since this board also has a SWD+ETM connector, we don't
+# automatically source that file here.
+
+set CHIPNAME samv71
+
+source [find target/atsamv.cfg]
--- a/scripts/board/avnet_ultrazed-eg.cfg
+++ b/scripts/board/avnet_ultrazed-eg.cfg
@ -0,0 +1,16 @@
+#
+# AVNET UltraZED EG StarterKit
+# ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2
+#
+source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
+# jtag transport only
+transport select jtag
+# reset lines are not wired
+reset_config none
+
+# slow default clock
+adapter speed 1000
+
+set CHIPNAME uscale
+
+source [find target/xilinx_zynqmp.cfg]
--- a/scripts/board/balloon3-cpu.cfg
+++ b/scripts/board/balloon3-cpu.cfg
@ -0,0 +1,14 @@
+# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/
+# The board has separate JTAG ports for cpu and CPLD/FPGA devices
+# Chaining is done on IO interfaces if desired.
+
+source [find target/pxa270.cfg]
+
+# The board supports separate reset lines
+# Override this in the interface config for parallel dongles
+reset_config trst_and_srst separate
+
+# flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
+# 29LV650 64Mbit Flash
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 $_TARGETNAME
--- a/scripts/board/bcm28155_ap.cfg
+++ b/scripts/board/bcm28155_ap.cfg
@ -0,0 +1,8 @@
+# BCM28155_AP
+
+adapter speed 20000
+
+set CHIPNAME bcm28155
+source [find target/bcm281xx.cfg]
+
+reset_config trst_and_srst
--- a/scripts/board/bluefield.cfg
+++ b/scripts/board/bluefield.cfg
@ -0,0 +1,6 @@
+#
+# Board configuration for BlueField SoC.
+#
+
+source [find interface/rshim.cfg]
+source [find target/bluefield.cfg]
--- a/scripts/board/bt-homehubv1.cfg
+++ b/scripts/board/bt-homehubv1.cfg
@ -0,0 +1,15 @@
+#
+# BT HomeHub v1
+#
+
+set partition_list {
+    CFE       { Bootloader              0xbe400000 0x00020000 }
+    firmware  { "Kernel+rootfs"         0xbe420000 0x007d0000 }
+    fisdir    { "FIS Directory"         0xbebf0000 0x0000f000 }
+    nvram     { "Config space"          0xbebff000 0x00001000 }
+}
+
+source [find target/bcm6348.cfg]
+
+set _FLASHNAME $_CHIPNAME.norflash
+flash bank $_FLASHNAME cfi 0xbe400000 0x00800000 2 2 $_TARGETNAME
--- a/scripts/board/colibri.cfg
+++ b/scripts/board/colibri.cfg
@ -0,0 +1,9 @@
+# Toradex Colibri PXA270
+source [find target/pxa270.cfg]
+reset_config trst_and_srst srst_push_pull
+adapter srst pulse_width 40
+
+# CS0 -- one bank of CFI flash, 32 MBytes
+# the bank is 32-bits wide, two 16-bit chips in parallel
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
--- a/scripts/board/crossbow_tech_imote2.cfg
+++ b/scripts/board/crossbow_tech_imote2.cfg
@ -0,0 +1,13 @@
+# Crossbow Technology iMote2
+
+set  CHIPNAME imote2
+source [find target/pxa270.cfg]
+
+# longer-than-normal reset delay
+adapter srst delay 800
+
+reset_config trst_and_srst separate
+
+# works for P30 flash
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
--- a/scripts/board/csb337.cfg
+++ b/scripts/board/csb337.cfg
@ -0,0 +1,117 @@
+# Cogent CSB337
+#   http://cogcomp.com/csb_csb337.htm
+
+source [find target/at91rm9200.cfg]
+
+# boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+
+# ETM9 trace port connector present on this board, 16 data pins.
+if { [info exists ETM_DRIVER] } {
+	etm config $_TARGETNAME 16 normal half $ETM_DRIVER
+	# OpenOCD may someday support a real trace port driver...
+	# system config file would need to configure it.
+} else {
+	etm config $_TARGETNAME 16 normal half dummy
+	etm_dummy config $_TARGETNAME
+}
+
+proc csb337_clk_init { } {
+	# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
+	adapter speed 8
+
+	# CKGR_MOR:  start main oscillator (3.6864 MHz)
+	mww 0xfffffc20 0xff01
+	sleep 10
+
+	# CKGR_PLLAR:  start PLL A for CPU and peripherals (184.32 MHz)
+	mww 0xfffffc28 0x20313e01
+	# CKGR_PLLBR:  start PLL B for USB timing (96 MHz, with div2)
+	mww 0xfffffc2c 0x12703e18
+	# let PLLs lock
+	sleep 10
+
+	# PMC_MCKR:  switch to CPU clock = PLLA, master clock = CPU/4
+	mww 0xfffffc30 0x0302
+	sleep 20
+
+	# CPU is in Normal Mode ... allows faster JTAG clock speed
+	adapter speed 40000
+}
+
+proc csb337_nor_init { } {
+	# SMC_CSR0:  adjust timings (10 wait states)
+	mww 0xffffff70 0x1100318a
+
+	flash probe 0
+}
+
+proc csb337_sdram_init { } {
+	# enable PIOC clock
+	mww 0xfffffc10 0x0010
+	# PC31..PC16 are D31..D16, with internal pullups like D15..D0
+	mww 0xfffff870 0xffff0000
+	mww 0xfffff874 0x0
+	mww 0xfffff804 0xffff0000
+
+	# SDRC_CR: set timings
+	mww 0xffffff98 0x2188b0d5
+
+	# SDRC_MR: issue all banks precharge to SDRAM
+	mww 0xffffff90 2
+	mww 0x20000000 0
+
+	# SDRC_MR: 8 autorefresh cycles
+	mww 0xffffff90 4
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+
+	# SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
+	mww 0xffffff90 3
+	mww 0x20000080 0
+
+	# SDRC_TR: set refresh rate
+	mww 0xffffff94 0x200
+	mww 0x20000000 0
+
+	# SDRC_MR: normal mode, 32 bit bus
+	mww 0xffffff90 0
+	mww 0x20000000 0
+}
+
+# The rm9200 chip has just been reset.  Bring it up far enough
+# that we can write flash or run code from SDRAM.
+proc csb337_reset_init { } {
+	csb337_clk_init
+
+	# EBI_CSA:  CS0 = NOR, CS1 = SDRAM
+	mww 0xffffff60 0x02
+
+	csb337_nor_init
+	csb337_sdram_init
+
+	# Update CP15 control register ... we don't seem to be able to
+	# read/modify/write its value through a TCL variable, so just
+	# write it.  Fields are zero unless listed here ... and note
+	# that OpenOCD numbers this register "2", not "1" (!).
+	#
+	#  - Core to use Async Clocking mode (so it uses 184 MHz most
+	#    of the time instead of limiting to the master clock rate):
+	#	iA(31) = 1, nF(30) = 1
+	#  - Icache on (it's disabled now, slowing i-fetches)
+	#	I(12) = 1
+	#  - Reserved/ones
+	#	6:3 = 1
+	arm920t cp15 2 0xc0001078
+}
+
+$_TARGETNAME configure -event reset-init {csb337_reset_init}
+
+arm7_9 fast_memory_access enable
--- a/scripts/board/csb732.cfg
+++ b/scripts/board/csb732.cfg
@ -0,0 +1,71 @@
+# The Cogent CSB732 board has a single i.MX35 chip
+source [find target/imx35.cfg]
+
+# Determined by trial and error
+reset_config trst_and_srst combined
+adapter srst delay 200
+jtag_ntrst_delay 200
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { csb732_init }
+
+# Bare-bones initialization of core clocks and SDRAM
+proc csb732_init { } {
+
+	# Disable fast writing only for init
+	memwrite burst disable
+
+	# All delay loops are omitted.
+	# We assume the interpreter latency is enough.
+
+	# Allow access to all coprocessors
+	arm mcr 15 0 15 1 0 0x2001
+
+	# Disable MMU, caches, write buffer
+	arm mcr 15 0 1 0 0 0x78
+
+	# Grant manager access to all domains
+	arm mcr 15 0 3 0 0 0xFFFFFFFF
+
+	# Set ARM clock to 532 MHz, AHB to 133 MHz
+	mww 0x53F80004 0x1000
+
+	# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
+	mww 0x53F8001C 0xB2C01
+
+	set ESDMISC 0xB8001010
+	set ESDCFG0 0xB8001004
+	set ESDCTL0 0xB8001000
+
+	# Enable DDR
+	mww $ESDMISC 0x4
+
+	# Timing
+	mww $ESDCFG0 0x007fff3f
+
+	# CS0
+	mww $ESDCTL0 0x92120080
+
+	# Precharge all dummy write
+	mww 0x80000400 0
+
+	# Enable CS) auto-refresh
+	mww $ESDCTL0 0xA2120080
+
+	# Refresh twice (dummy writes)
+	mww 0x80000000 0
+	mww 0x80000000 0
+
+	# Enable CS0 load mode register
+	mww $ESDCTL0 0xB2120080
+
+	# Dummy writes
+	mwb 0x80000033 0x01
+	mwb 0x81000000 0x01
+
+	mww $ESDCTL0 0x82226080
+	mww 0x80000000 0
+
+	# Re-enable fast writing
+	memwrite burst enable
+}
--- a/scripts/board/da850evm.cfg
+++ b/scripts/board/da850evm.cfg
@ -0,0 +1,10 @@
+#DA850 EVM board
+# http://focus.ti.com/dsp/docs/thirdparty/catalog/devtoolsproductfolder.tsp?actionPerformed=productFolder&productId=5939
+# http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit
+
+source [find target/omapl138.cfg]
+
+reset_config trst_and_srst separate
+
+#currently any pinmux/timing must be setup by UBL before openocd can do debug
+#TODO: implement pinmux/timing on reset like in board/dm365evm.cfg
--- a/scripts/board/digi_connectcore_wi-9c.cfg
+++ b/scripts/board/digi_connectcore_wi-9c.cfg
@ -0,0 +1,130 @@
+######################################
+# Target: DIGI ConnectCore Wi-9C
+######################################
+
+reset_config trst_and_srst
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME ns9360
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+  # This config file was defaulting to big endian..
+   set  _ENDIAN big
+}
+
+
+# What's a good fallback frequency for this board if RCLK is
+# not available??
+jtag_rclk 1000
+
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926031
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+adapter srst delay 200
+jtag_ntrst_delay 0
+
+
+######################
+# Target configuration
+######################
+
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-init {
+	mww 0x90600104 0x33313333
+	mww 0xA0700000 0x00000001  ;# Enable the memory controller.
+	mww 0xA0700024 0x00000006  ;# Set the refresh counter 6
+	mww 0xA0700028 0x00000001  ;#
+	mww 0xA0700030 0x00000001  ;# Set the precharge period
+	mww 0xA0700034 0x00000004  ;# Active to precharge command period is 16 clock cycles
+	mww 0xA070003C 0x00000001  ;# tAPR
+	mww 0xA0700040 0x00000005  ;# tDAL
+	mww 0xA0700044 0x00000001  ;# tWR
+	mww 0xA0700048 0x00000006  ;# tRC 32 clock cycles
+	mww 0xA070004C 0x00000006  ;# tRFC 32 clock cycles
+	mww 0xA0700054 0x00000001  ;# tRRD
+	mww 0xA0700058 0x00000001  ;# tMRD
+	mww 0xA0700100 0x00004280  ;# Dynamic Config 0 (cs4)
+	mww 0xA0700120 0x00004280  ;# Dynamic Config 1 (cs5)
+	mww 0xA0700140 0x00004280  ;# Dynamic Config 2 (cs6)
+	mww 0xA0700160 0x00004280  ;# Dynamic Config 3 (cs7)
+	#
+	mww 0xA0700104 0x00000203  ;# CAS latency is 2 at 100 MHz
+	mww 0xA0700124 0x00000203  ;# CAS latency is 2 at 100 MHz
+	mww 0xA0700144 0x00000203  ;# CAS latency is 2 at 100 MHz
+	mww 0xA0700164 0x00000203  ;# CAS latency is 2 at 100 MHz
+	#
+	mww 0xA0700020 0x00000103  ;# issue SDRAM PALL command
+	#
+	mww 0xA0700024 0x00000001  ;# Set the refresh counter to be as small as possible
+	#
+	# Add some dummy writes to give the SDRAM time to settle, it needs two
+	# AHB clock cycles, here we poke in the debugger flag, this lets
+	# the software know that we are in the debugger
+	mww 0xA0900000 0x00000002
+	mww 0xA0900000 0x00000002
+	mww 0xA0900000 0x00000002
+	mww 0xA0900000 0x00000002
+	mww 0xA0900000 0x00000002
+	#
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	#
+	mww 0xA0700024 0x00000030 ;# Set the refresh counter to 30
+	mww 0xA0700020 0x00000083 ;# Issue SDRAM MODE command
+	#
+	# Next we perform a read of RAM.
+	# mw = move word.
+	mdw 0x00022000
+	# mw 0x00022000:P, r3  # 22000 for cas2 latency, 32000 for cas 3
+	#
+	mww 0xA0700020 0x00000003   ;# issue SDRAM NORMAL command
+	mww 0xA0700100 0x00084280   ;# Enable buffer access
+	mww 0xA0700120 0x00084280   ;# Enable buffer access
+	mww 0xA0700140 0x00084280   ;# Enable buffer access
+	mww 0xA0700160 0x00084280   ;# Enable buffer access
+
+	#Set byte lane state (static mem 1)"
+	mww 0xA0700220 0x00000082
+	#Flash Start
+	mww 0xA09001F8 0x50000000
+	#Flash Mask Reg
+	mww 0xA09001FC 0xFF000001
+	mww 0xA0700028 0x00000001
+
+	#  RAMAddr = 0x00020000
+	#  RAMSize = 0x00004000
+
+	# Set the processor mode
+	reg cpsr 0xd3
+}
+
+$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
+
+#####################
+# Flash configuration
+#####################
+
+#M29DW323DB - not working
+#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 $_TARGETNAME
--- a/scripts/board/digilent_analog_discovery.cfg
+++ b/scripts/board/digilent_analog_discovery.cfg
@ -0,0 +1,18 @@
+#
+# Digilent Analog Discovery
+#
+# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,842,1018&Prod=ANALOG-DISCOVERY
+#
+# Config is based on data from
+# https://github.com/bvanheu/urjtag-ad/commit/8bd883ee01d134f94b79cbbd00df42cd03bafd71
+#
+
+adapter driver ftdi
+ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6014
+
+ftdi layout_init 0x8008 0x800b
+
+adapter speed 25000
+
+source [find cpld/xilinx-xc6s.cfg]
--- a/scripts/board/digilent_atlys.cfg
+++ b/scripts/board/digilent_atlys.cfg
@ -0,0 +1,17 @@
+# http://digilentinc.com/atlys/
+#
+# The Digilent Atlys normally requires proprietary tools to program and will
+# enumerate as:
+#   ID 1443:0007 Digilent Development board JTAG
+#
+# However, the ixo-usb-jtag project provides an alternative open firmware for
+# the on board programmer. When using this firmware the board will then
+# enumerate as:
+#   ID 16c0:06ad Van Ooijen Technische Informatica
+# (With SerialNumber == hw_nexys)
+#
+# See the interface/usb-jtag.cfg for more information.
+
+source [find interface/usb-jtag.cfg]
+source [find cpld/xilinx-xc6s.cfg]
+source [find cpld/jtagspi.cfg]
--- a/scripts/board/digilent_nexys_video.cfg
+++ b/scripts/board/digilent_nexys_video.cfg
@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Digilent Nexys Video with Xilinx Artix-7 FPGA
+# https://reference.digilentinc.com/programmable-logic/nexys-video/start
+
+adapter driver ftdi
+adapter speed 30000
+
+ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6010
+
+# channel 0 is dedicated for Digilent's DPTI Interface
+# channel 1 is used for JTAG
+ftdi channel 1
+
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0088 0x008b
+reset_config none
+
+# Enable sampling on falling edge for high JTAG speeds.
+ftdi tdo_sample_edge falling
+
+transport select jtag
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
--- a/scripts/board/digilent_zedboard.cfg
+++ b/scripts/board/digilent_zedboard.cfg
@ -0,0 +1,11 @@
+#
+# Digilent Zedboard Rev.C, Rev.D with Xilinx Zynq chip
+#
+# http://zedboard.com/product/zedboard
+#
+
+source [find interface/ftdi/digilent_jtag_smt2.cfg]
+
+reset_config srst_only srst_push_pull
+
+source [find target/zynq_7000.cfg]
--- a/scripts/board/diolan_lpc4350-db1.cfg
+++ b/scripts/board/diolan_lpc4350-db1.cfg
@ -0,0 +1,9 @@
+#
+# Diolan LPC-4350-DB1 development board
+#
+
+set CHIPNAME lpc4350
+
+source [find target/lpc4350.cfg]
+
+flash bank $_CHIPNAME.nor cfi 0x1C000000 0x00200000 2 2 $_CHIPNAME.m4
--- a/scripts/board/diolan_lpc4357-db1.cfg
+++ b/scripts/board/diolan_lpc4357-db1.cfg
@ -0,0 +1,9 @@
+#
+# Diolan LPC-4357-DB1 development board
+#
+
+set CHIPNAME lpc4357
+
+source [find target/lpc4357.cfg]
+
+flash bank $_CHIPNAME.nor cfi 0x1C000000 0x00200000 2 2 $_CHIPNAME.m4
--- a/scripts/board/dk-tm4c129.cfg
+++ b/scripts/board/dk-tm4c129.cfg
@ -0,0 +1,3 @@
+echo "WARNING: board/dk-tm4c129.cfg is deprecated, please switch to board/ti_dk-tm4c129.cfg"
+
+source [find board/ti_dk-tm4c129.cfg]
--- a/scripts/board/dm355evm.cfg
+++ b/scripts/board/dm355evm.cfg
@ -0,0 +1,201 @@
+# DM355 EVM board
+#   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
+#   http://c6000.spectrumdigital.com/evmdm355/
+
+source [find target/ti_dm355.cfg]
+
+reset_config trst_and_srst separate
+
+# NOTE:  disable or replace this call to dm355evm_init if you're
+# debugging new UBL code from SRAM.
+$_TARGETNAME configure -event reset-init { dm355evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc.  It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm355evm_init {} {
+	global dm355
+
+	echo "Initialize DM355 EVM board"
+
+	# CLKIN	= 24 MHz ... can't talk quickly to ARM yet
+	jtag_rclk 1500
+
+	########################
+	# PLL1		= 432 MHz (/8, x144)
+	# ...SYSCLK1	= 216 MHz (/2)  ... ARM, MJCP
+	# ...SYSCLK2	= 108 MHz (/4)  ... Peripherals
+	# ...SYSCLK3	= 27  MHz (/16) ... VPBE, DAC
+	# ...SYSCLK4	= 108 MHz (/4)  ... VPSS
+	#	pll1.{prediv,div1,div2} are fixed
+	#	pll1.postdiv set in MISC (for *this* speed grade)
+
+	set addr [dict get $dm355 pllc1]
+	set pll_divs [dict create]
+	dict set pll_divs div3 16
+	dict set pll_divs div4 4
+	pll_v02_setup $addr 144 $pll_divs
+
+	# ARM is now running at 216 MHz, so JTAG can go faster
+	jtag_rclk 20000
+
+	########################
+	# PLL2		= 342 MHz (/8, x114)
+	# ....SYSCLK1	= 342 MHz (/1)  ... DDR PHY at 171 MHz, 2x clock
+	#	pll2.{postdiv,div1} are fixed
+
+	set addr [dict get $dm355 pllc2]
+	set pll_divs [dict create]
+	dict set pll_divs div1 1
+	dict set pll_divs prediv 8
+	pll_v02_setup $addr 114 $pll_divs
+
+	########################
+	# PINMUX
+
+	# All Video Inputs
+	davinci_pinmux $dm355 0 0x00007f55
+	# All Video Outputs
+	davinci_pinmux $dm355 1 0x00145555
+	# EMIFA (NOTE: more could be set up for use as GPIOs)
+	davinci_pinmux $dm355 2 0x00000c08
+	# SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
+	davinci_pinmux $dm355 3 0x1bff55ff
+	# MMC/SD0 instead of MS; SPI0
+	davinci_pinmux $dm355 4 0x00000000
+
+	########################
+	# PSC setup (minimal)
+
+	# DDR EMIF/13, AEMIF/14, UART0/19
+	psc_enable 13
+	psc_enable 14
+	psc_enable 19
+	psc_go
+
+	########################
+	# DDR2 EMIF
+
+	# VTPIOCR impedance calibration
+	set addr [dict get $dm355 sysbase]
+	set addr [expr {$addr + 0x70}]
+
+	# clear CLR, LOCK, PWRDN; wait a clock; set CLR
+	mmw $addr 0 0x20c0
+	mmw $addr 0x2000 0
+
+	# wait for READY
+        while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 }
+
+	# set IO_READY; then LOCK and PWRSAVE; then PWRDN
+	mmw $addr 0x4000 0
+	mmw $addr 0x0180 0
+	mmw $addr 0x0040 0
+
+	# NOTE:  this DDR2 initialization sequence borrows from
+	# both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.
+
+	# reset (then re-enable) DDR controller
+	psc_reset 13
+	psc_go
+	psc_enable 13
+	psc_go
+
+	# now set it up for Micron MT47H64M16HR-37E @ 171 MHz
+
+	set addr [dict get $dm355 ddr_emif]
+
+	# DDRPHYCR1
+	mww [expr {$addr + 0xe4}] 0x50006404
+
+	# PBBPR -- burst priority
+	mww [expr {$addr + 0x20}] 0xfe
+
+	# SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
+	mmw [expr {$addr + 0x08}] 0x00800000 0
+	mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff
+
+	# SDTIMR0, SDTIMR1
+	mww [expr {$addr + 0x10}] 0x2a923249
+	mww [expr {$addr + 0x14}] 0x4c17c763
+
+	# SDCR -- relock SDTIM*
+	mmw [expr {$addr + 0x08}] 0 0x00008000
+
+	# SDRCR -- refresh rate (171 MHz * 7.8usec)
+	mww [expr {$addr + 0x0c}] 1336
+
+	########################
+	# ASYNC EMIF
+
+	set addr [dict get $dm355 a_emif]
+
+	# slow/pessimistic timings
+	set nand_timings 0x40400204
+	# fast (25% faster page reads)
+	#set nand_timings 0x0400008c
+
+	# AWCCR
+	mww [expr {$addr + 0x04}] 0xff
+	# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
+	mww [expr {$addr + 0x10}] $nand_timings
+	# CS1 == dm9000 Ethernet
+	mww [expr {$addr + 0x14}] 0x00a00505
+	# NANDFCR -- only CS0 has NAND
+	mww [expr {$addr + 0x60}] 0x01
+
+	# default: both chipselects to the NAND socket are used
+	nand probe 0
+	nand probe 1
+
+	########################
+	# UART0
+
+	set addr [dict get $dm355 uart0]
+
+	# PWREMU_MGNT -- rx + tx in reset
+	mww [expr {$addr + 0x30}] 0
+
+	# DLL, DLH -- 115200 baud
+	mwb [expr {$addr + 0x20}] 0x0d
+	mwb [expr {$addr + 0x24}] 0x00
+
+	# FCR - clear and disable FIFOs
+	mwb [expr {$addr + 0x08}] 0x07
+	mwb [expr {$addr + 0x08}] 0x00
+
+	# IER - disable IRQs
+	mwb [expr {$addr + 0x04}] 0x00
+
+	# LCR - 8-N-1
+	mwb [expr {$addr + 0x0c}] 0x03
+
+	# MCR - no flow control or loopback
+	mwb [expr {$addr + 0x10}] 0x00
+
+	# PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
+	mww [expr {$addr + 0x30}] 0xe001
+
+
+	########################
+
+	# turn on icache - set I bit in cp15 register c1
+	arm mcr 15 0 0 1 0 0x00051078
+}
+
+# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
+#
+# NOTE:  "hwecc4" here presumes that if you're using the standard 2GB NAND
+# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
+# use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
+# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
+set _FLASHNAME $_CHIPNAME.boot
+nand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
+set _FLASHNAME $_CHIPNAME.flash
+nand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
+
+# FIXME
+#  - support writing UBL with its header (new layout only with new ROMs)
+#  - support writing ABL/U-Boot with its header (new layout)
--- a/scripts/board/dm365evm.cfg
+++ b/scripts/board/dm365evm.cfg
@ -0,0 +1,145 @@
+# DM365 EVM board -- Beta
+#   http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html
+#   http://support.spectrumdigital.com/boards/evmdm365
+
+source [find target/ti_dm365.cfg]
+
+# NOTE:  in Rev C boards, the CPLD ignores SRST from the ARM-20 JTAG
+# connector, so it doesn't affect generation of the reset signal.
+# Accordingly, resets require something else.  ICEpick could do it;
+# but its docs aren't generally available.
+#
+# At this writing, newer boards aren't available ... so assume no SRST.
+# Also ICEpick docs aren't available ... so we must use watchdog reset,
+# and hope the CPU isn't wedged or in a WFI loop (either of which can
+# block access to CPU and thus watchdog registers).
+
+reset_config trst_only
+$_TARGETNAME configure -event reset-assert "davinci_wdog_reset"
+
+# SW5.1 routes CS0: NAND vs OneNAND.
+# SW4.6:4 controls AEMIF width (8 for NAND, 16 for OneNand)
+# for boot-from-flash, those must agree with SW4.3:1 settings.
+
+if { [info exists CS0MODE] } {
+	# NAND or OneNAND
+	set CS0 $CS0MODE
+} else {
+	set CS0 ""
+	echo "WARNING:  CS0 configuration not known"
+	proc cs0_setup {a_emif} {}
+	proc flashprobe {} {}
+}
+
+set a_emif [dict get $dm365 a_emif]
+
+# As shipped:  boot from NAND.
+if { $CS0 == "NAND" } {
+	echo "CS0 NAND"
+
+	# NAND socket has two chipselects.  Default MT29F16G08FAA chip
+	# has 1GByte on each one.
+	# NOTE:  "hwecc4" here presumes that you're not updating anything
+	# that needs infix layout (e.g. UBL, old U-Boot, etc)
+	nand device low davinci $_TARGETNAME 0x02000000 hwecc4 $a_emif
+	nand device high davinci $_TARGETNAME 0x02004000 hwecc4 $a_emif
+
+	proc cs0_setup {a_emif} {
+		global dm365
+
+		# 8 bit EMIF
+		davinci_pinmux $dm365 2 0x00000016
+
+		# slow/pessimistic timings
+		set nand_timings 0x40400204
+		# fast (25% faster page reads)
+		#set nand_timings 0x0400008c
+
+		# CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes)
+		mww [expr {$a_emif + 0x10}] $nand_timings
+
+		# NANDFCR -- CS0 has NAND
+		mww [expr {$a_emif + 0x60}] 0x01
+	}
+	proc flashprobe {} {
+		nand probe 0
+		nand probe 1
+	}
+
+} elseif { $CS0 == "OneNAND" } {
+	echo "CS0 OneNAND"
+
+	# No support for this OneNAND in OpenOCD (yet) or Linux ...
+	# REVISIT OneNAND timings not verified to work!
+	echo "WARNING -- OneNAND not yet tested!"
+
+	proc cs0_setup {a_emif} {
+		global dm365
+
+		# 16 bit EMIF
+		davinci_pinmux $dm365 2 0x00000055
+
+		# CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes)
+		mww [expr {$a_emif + 0x10}] 0x00000001
+
+		# ONENANDCTRL -- CS0 has OneNAND, enable sync reads
+		mww [expr {$a_emif + 0x5c}] 0x0441
+	}
+	proc flashprobe {} { }
+}
+
+# NOTE:  disable or replace this call to dm365evm_init if you're
+# debugging new UBL/NANDboot code from SRAM.
+$_TARGETNAME configure -event reset-init { dm365evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc.  It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm365evm_init {} {
+	global dm365
+
+	echo "Initialize DM365 EVM board"
+
+	# CLKIN	= 24 MHz ... can't talk quickly to ARM yet
+	adapter speed 1500
+
+	# FIXME -- PLL init
+
+	########################
+	# PINMUX setup
+
+	davinci_pinmux $dm365 0 0x00fd0000
+	davinci_pinmux $dm365 1 0x00145555
+	# mux2 controls AEMIF ... 8 bit for NAND, 16 for OneNand
+	davinci_pinmux $dm365 3 0x375affff
+	davinci_pinmux $dm365 4 0x55556555
+
+	########################
+	# PSC setup (minimal)
+
+	# DDR EMIF/13, AEMIF/14, UART0/19
+	psc_enable 13
+	psc_enable 14
+	psc_enable 19
+	psc_go
+
+	# FIXME setup DDR2 (needs PLL)
+
+	########################
+	# ASYNC EMIF
+
+	set a_emif [dict get $dm365 a_emif]
+
+	# AWCCR
+	mww [expr {$a_emif + 0x04}] 0xff
+	# CS0 == NAND or OneNAND
+	cs0_setup $a_emif
+	# CS1 == CPLD
+	mww [expr {$a_emif + 0x14}] 0x00a00505
+
+	# FIXME setup UART0
+
+	flashprobe
+}
--- a/scripts/board/dm6446evm.cfg
+++ b/scripts/board/dm6446evm.cfg
@ -0,0 +1,75 @@
+# DM6446 EVM board
+#   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm6446.html
+#   http://c6000.spectrumdigital.com/davincievm/
+# EVM is just the board; buy that at Spectrum.
+# The "kit" from TI also has: video camera, LCD video monitor, more.
+
+source [find target/ti_dm6446.cfg]
+
+# J4 controls what CS2 hooks up to, usually NOR or NAND flash.
+# S3.1/S3.2 controls boot mode, which may force J4 and S3.3 settings.
+# S3.3 controls AEMIF bus width.
+
+if { [info exists J4_OPTION] } {
+	# NOR, NAND, SRAM, ...
+	set CS2_MODE $J4_OPTION
+} else {
+	set CS2_MODE ""
+}
+
+# ARM boot:
+#  S3.1 = 0, S3.2 = 0	==> ROM/UBL boot via NAND (J4 == NAND)
+#  S3.1 = 1, S3.2 = 0	==> AEMIF boot (J4 == NOR or SRAM)
+#  S3.1 = 0, S3.2 = 1	==> ROM/UBL boot via HPI
+#  S3.1 = 1, S3.2 = 1	==> ROM/UBL boot via UART (J4 == don't care)
+# AEMIF bus width:
+#  S3.3 = 0		==> 8 bit bus width
+#  S3.3 = 1		==> 16 bit bus width
+# DSP boot:
+#  S3.4 = 0		==> controlled by ARM
+
+if { $CS2_MODE == "NOR" } {
+	# 16 Mbytes address space; 16 bit bus width
+	# (older boards used 32MB parts, with upper 16 MB unusable)
+	set _FLASHNAME $_CHIPNAME.flash
+	flash bank $_FLASHNAME cfi 0x02000000 0x01000000 2 2 $_TARGETNAME
+	proc flashprobe {} { flash probe 0 }
+} elseif { $CS2_MODE == "NAND" } {
+	# 64 Mbyte small page; 8 bit bus width
+	nand device davinci $_TARGETNAME 0x02000000 hwecc1 0x01e00000
+	proc flashprobe {} { nand probe 0 }
+} elseif { $CS2_MODE == "SRAM" } {
+	# 4 Mbyte address space; 16 bit bus width
+	# loaded via JTAG or HPI
+	proc flashprobe {} {}
+} else {
+	# maybe it's HPI boot?  can't tell...
+	echo "WARNING:  CS2/flash configuration not recognized"
+	proc flashprobe {} {}
+}
+
+# NOTE:  disable or replace this call to dm6446evm_init if you're
+# debugging new UBL code from SRAM (for NAND boot).
+$_TARGETNAME configure -event reset-init { dm6446evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc.  It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm6446evm_init {} {
+
+	echo "Initialize DM6446 EVM board"
+
+	# FIXME initialize everything:
+	#  - PLL1
+	#  - PLL2
+	#  - PINMUX
+	#  - PSC
+	#  - DDR
+	#  - AEMIF
+	#  - UART0
+	#  - icache
+
+	flashprobe
+}
--- a/scripts/board/dp_busblaster_v3.cfg
+++ b/scripts/board/dp_busblaster_v3.cfg
@ -0,0 +1,13 @@
+#
+# Dangerous Prototypes - Bus Blaster
+#
+# http://dangerousprototypes.com/docs/Bus_Blaster
+#
+# To reprogram the on-board CPLD do:
+# openocd -f board/dp_busblaster_v3.cfg -c "adapter speed 1000; init; svf <path_to_svf>; shutdown"
+#
+
+source [find interface/ftdi/dp_busblaster.cfg]
+ftdi channel 1
+
+jtag newtap xc2c32a tap -expected-id 0x06e1c093 -irlen 8
--- a/scripts/board/dp_busblaster_v4.cfg
+++ b/scripts/board/dp_busblaster_v4.cfg
@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Dangerous Prototypes - Bus Blaster
+#
+# http://dangerousprototypes.com/docs/Bus_Blaster
+#
+# The Bus Blaster has a configurable buffer between the FTDI FT2232H
+# and the JTAG header which allows it to emulate various debugger
+# types. This config works with KT-Link compatible implementation from
+# https://raw.githubusercontent.com/dergraaf/busblaster_v4/master/ktlink/ktlink.svf
+#
+# To reprogram the on-board CPLD do:
+# openocd -f board/dp_busblaster_v4.cfg -c "adapter speed 1000; init; svf <path_to_svf>; shutdown"
+#
+
+source [find interface/ftdi/dp_busblaster.cfg]
+ftdi channel 1
+
+jtag newtap xc2c64a tap -expected-id 0x06e5c093 -irlen 8
--- a/scripts/board/dptechnics_dpt-board-v1.cfg
+++ b/scripts/board/dptechnics_dpt-board-v1.cfg
@ -0,0 +1,32 @@
+# Product page:
+# https://www.dptechnics.com/en/products/dpt-board-v1.html
+#
+# JTAG is a 5 pin array located close to main module in following order:
+# 1. JTAG TCK
+# 2. JTAG TDO
+# 3. JTAG TDI
+# 4. JTAG TMS
+# 5. GND	The GND is located near letter G of word JTAG on board.
+#
+# Two RST pins are connected to:
+# 1. GND
+# 2. GPIO11	this pin is located near letter R of word RST.
+#
+# To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example
+# with 10K resistor connected to V3.3 pin.
+#
+# This board is powered from micro USB connector. No real reset pin or button, for
+# example RESET_L is available.
+
+source [find target/atheros_ar9331.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	ar9331_25mhz_pll_init
+	sleep 1
+	ar9331_ddr2_init
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
--- a/scripts/board/efikamx.cfg
+++ b/scripts/board/efikamx.cfg
@ -0,0 +1,10 @@
+# Genesi USA EfikaMX
+#  http://www.genesi-usa.com/products/efika
+
+# Fall back to 6MHz if RTCK is not supported
+jtag_rclk 6000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 6000 }
+
+source [find target/imx51.cfg]
+
+reset_config trst_only
--- a/scripts/board/efm32.cfg
+++ b/scripts/board/efm32.cfg
@ -0,0 +1,11 @@
+# Configuration for EFM32 boards with on-board SEGGER J-Link
+#
+# Tested with Tiny, Giant and Zero Gecko Starter Kit.
+#
+
+source [find interface/jlink.cfg]
+transport select swd
+adapter speed 1000
+
+set CHIPNAME efm32
+source [find target/efm32.cfg]
--- a/scripts/board/eir.cfg
+++ b/scripts/board/eir.cfg
@ -0,0 +1,93 @@
+# Elector Internet Radio board
+# http://www.ethernut.de/en/hardware/eir/index.html
+
+source [find target/at91sam7se512.cfg]
+
+$_TARGETNAME configure -event reset-init {
+	# WDT_MR, disable watchdog
+	mww 0xFFFFFD44 0x00008000
+
+	# RSTC_MR, enable user reset
+	mww 0xfffffd08 0xa5000001
+
+	# CKGR_MOR
+	mww 0xFFFFFC20 0x00000601
+	sleep 10
+
+	# CKGR_PLLR
+	mww 0xFFFFFC2C 0x00481c0e
+	sleep 10
+
+	# PMC_MCKR
+	mww 0xFFFFFC30 0x00000007
+	sleep 10
+
+	# PMC_IER
+	mww 0xFFFFFF60 0x00480100
+
+	#
+	# Enable SDRAM interface.
+	#
+
+	# Enable SDRAM control at PIO A.
+	mww 0xfffff474 0x3f800000 ;# PIO_BSR_OFF
+	mww 0xfffff404 0x3f800000 ;# PIO_PDR_OFF
+
+	# Enable address bus (A0, A2-A11, A13-A17) at PIO B
+	mww 0xfffff674 0x0003effd ;# PIO_BSR_OFF
+	mww 0xfffff604 0x0003effd ;# PIO_PDR_OFF
+
+	# Enable 16 bit data bus at PIO C
+	mww 0xfffff870 0x0000ffff ;# PIO_ASR_OFF
+	mww 0xfffff804 0x0000ffff ;# PIO_PDR_OFF
+
+	# Enable SDRAM chip select
+	mww 0xffffff80 0x00000002 ;# EBI_CSA_OFF
+
+	# Set SDRAM characteristics in configuration register.
+	# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
+	mww 0xffffffb8 0x2192215a ;# SDRAMC_CR_OFF
+	sleep 10
+
+	# Issue 16 bit SDRAM command: NOP
+	mww 0xffffffb0 0x00000011 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+
+	# Issue 16 bit SDRAM command: Precharge all
+	mww 0xffffffb0 0x00000012 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+
+	# Issue 8 auto-refresh cycles
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+
+	# Issue 16 bit SDRAM command: Set mode register
+	mww 0xffffffb0 0x00000013 ;# SDRAMC_MR_OFF
+	mww 0x20000014 0xcafedede
+
+	# Set refresh rate count ???
+	mww 0xffffffb4 0x00000013 ;# SDRAMC_TR_OFF
+
+	# Issue 16 bit SDRAM command: Normal mode
+	mww 0xffffffb0 0x00000010 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000180
+
+	#
+	# Enable external reset key.
+	#
+	mww 0xfffffd08 0xa5000001
+}
--- a/scripts/board/ek-lm3s1968.cfg
+++ b/scripts/board/ek-lm3s1968.cfg
@ -0,0 +1,19 @@
+#
+# TI/Luminary Stellaris LM3S1968 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s1968
+#
+
+# NOTE:  to use J-Link instead of the on-board interface,
+# you may also need to reduce adapter speed to be about 1200.
+# source [find interface/jlink.cfg]
+
+# include the FT2232 interface config for on-board JTAG interface
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using in JTAG mode, as done here.
+source [find interface/ftdi/luminary.cfg]
+
+# include the target config
+set WORKAREASIZE 0x2000
+set CHIPNAME lm3s1968
+source [find target/stellaris.cfg]
--- a/scripts/board/ek-lm3s3748.cfg
+++ b/scripts/board/ek-lm3s3748.cfg
@ -0,0 +1,14 @@
+#
+# TI/Luminary Stellaris lm3s3748 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s3748
+#
+
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using it in JTAG mode, as done here.
+source [find interface/ftdi/luminary.cfg]
+
+# 20k working area
+set WORKAREASIZE 0x4000
+set CHIPNAME lm3s3748
+source [find target/stellaris.cfg]
--- a/scripts/board/ek-lm3s6965.cfg
+++ b/scripts/board/ek-lm3s6965.cfg
@ -0,0 +1,15 @@
+#
+# TI/Luminary Stellaris LM3S6965 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s6965
+#
+
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using it in JTAG mode, as done here.
+source [find interface/ftdi/luminary.cfg]
+
+# 20k working area
+set WORKAREASIZE 0x5000
+set CHIPNAME lm3s6965
+# include the target config
+source [find target/stellaris.cfg]
--- a/scripts/board/ek-lm3s811-revb.cfg
+++ b/scripts/board/ek-lm3s811-revb.cfg
@ -0,0 +1,14 @@
+#
+# TI/Luminary Stellaris LM3S811 Evaluation Kits (rev B and earlier)
+#
+# http://www.ti.com/tool/ek-lm3s811
+#
+
+# NOTE: newer 811-EK boards (rev C and above) shouldn't use this.
+# use board/ek-lm3s811.cfg
+source [find interface/ftdi/luminary-lm3s811.cfg]
+
+# include the target config
+set WORKAREASIZE 0x2000
+set CHIPNAME lm3s811
+source [find target/stellaris.cfg]
--- a/scripts/board/ek-lm3s811.cfg
+++ b/scripts/board/ek-lm3s811.cfg
@ -0,0 +1,15 @@
+#
+# TI/Luminary Stellaris LM3S811 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s811
+#
+
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using it in JTAG mode, as done here.
+# NOTE:  older '811-EK boards (before rev C) shouldn't use this.
+source [find interface/ftdi/luminary.cfg]
+
+# include the target config
+set WORKAREASIZE 0x2000
+set CHIPNAME lm3s811
+source [find target/stellaris.cfg]
--- a/scripts/board/ek-lm3s8962.cfg
+++ b/scripts/board/ek-lm3s8962.cfg
@ -0,0 +1,15 @@
+#
+# TI/Luminary Stellaris LM3S8962 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s8962
+#
+
+# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+# so is using it in JTAG mode, as done here.
+source [find interface/ftdi/luminary.cfg]
+
+# 64k working area
+set WORKAREASIZE 0x10000
+set CHIPNAME lm3s8962
+# include the target config
+source [find target/stellaris.cfg]
--- a/scripts/board/ek-lm3s9b9x.cfg
+++ b/scripts/board/ek-lm3s9b9x.cfg
@ -0,0 +1,14 @@
+#
+# TI/Luminary Stellaris LM3S9B9x Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s9b90
+# http://www.ti.com/tool/ek-lm3s9b92
+#
+
+# NOTE:  using the bundled FT2232 JTAG/SWD/SWO interface is optional!
+# so is using in JTAG mode, as done here.
+source [find interface/ftdi/luminary-icdi.cfg]
+
+set WORKAREASIZE 0x4000
+set CHIPNAME lm3s9b9x
+source [find target/stellaris.cfg]
--- a/scripts/board/ek-lm3s9d92.cfg
+++ b/scripts/board/ek-lm3s9d92.cfg
@ -0,0 +1,14 @@
+#
+# TI/Luminary Stellaris LM3S9D92 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm3s9d92
+#
+
+# NOTE:  using the bundled FT2232 JTAG/SWD/SWO interface is optional!
+# so is using in JTAG mode, as done here.
+source [find interface/ftdi/luminary-icdi.cfg]
+
+# 64k working area
+set WORKAREASIZE 0x10000
+set CHIPNAME lm3s9d92
+source [find target/stellaris.cfg]
--- a/scripts/board/ek-lm4f120xl.cfg
+++ b/scripts/board/ek-lm4f120xl.cfg
@ -0,0 +1,17 @@
+#
+# TI Stellaris Launchpad ek-lm4f120xl Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm4f120xl
+#
+
+#
+# NOTE: using the bundled ICDI interface is optional!
+# This interface is not ftdi based as previous boards were
+#
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME lm4f120h5qr
+source [find target/stellaris.cfg]
--- a/scripts/board/ek-lm4f232.cfg
+++ b/scripts/board/ek-lm4f232.cfg
@ -0,0 +1,17 @@
+#
+# TI Stellaris LM4F232 Evaluation Kits
+#
+# http://www.ti.com/tool/ek-lm4f232
+#
+
+#
+# NOTE: using the bundled ICDI interface is optional!
+# This interface is not ftdi based as previous boards were
+#
+source [find interface/ti-icdi.cfg]
+
+transport select hla_jtag
+
+set WORKAREASIZE 0x8000
+set CHIPNAME lm4f23x
+source [find target/stellaris.cfg]
--- a/scripts/board/ek-tm4c123gxl.cfg
+++ b/scripts/board/ek-tm4c123gxl.cfg
@ -0,0 +1,3 @@
+echo "WARNING: board/ek-tm4c123gxl.cfg is deprecated, please switch to board/ti_ek-tm4c123gxl.cfg"
+
+source [find board/ti_ek-tm4c123gxl.cfg]
--- a/scripts/board/ek-tm4c1294xl.cfg
+++ b/scripts/board/ek-tm4c1294xl.cfg
@ -0,0 +1,3 @@
+echo "WARNING: board/ek-tm4c1294xl.cfg is deprecated, please switch to board/ti_ek-tm4c1294xl.cfg"
+
+source [find board/ti_ek-tm4c1294xl.cfg]
--- a/scripts/board/embedded-artists_lpc2478-32.cfg
+++ b/scripts/board/embedded-artists_lpc2478-32.cfg
@ -0,0 +1,151 @@
+# Embedded Artists eval board for LPC2478
+# http://www.embeddedartists.com/
+
+# Target device: LPC2478
+set CCLK 72000
+source [find target/lpc2478.cfg]
+
+# Helper
+#
+proc read_register {register} {
+    return [read_memory $register 32 1]
+}
+
+proc init_board {} {
+    # Delays on reset lines
+    adapter srst delay 500
+    jtag_ntrst_delay 1
+
+    # Adaptive JTAG clocking through RTCK.
+    #
+    jtag_rclk 20
+
+    global _TARGETNAME
+    global _CHIPNAME
+
+    # A working area will help speeding the flash programming
+    $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0
+
+    # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
+    flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
+
+    # Event handlers
+    #
+    $_TARGETNAME configure -event reset-start {
+        # Back to the slow JTAG clock
+        jtag_rclk 20
+    }
+
+    $_TARGETNAME configure -event reset-init {
+        arm core_state arm
+        arm7_9 dcc_downloads enable     ;# Speed up downloads by using DCC transfer
+        arm7_9 fast_memory_access enable
+
+        # Peripheral clocks
+        mww 0xE01FC0C4 0x04280FFE       ;# PCONP: (reset value)
+
+        # Map the user flash to the vector table area (0x00...0x3F)
+        mww 0xE01FC040 0x00000001       ;# MEMMAP: User flash
+
+        # Memory accelerator module
+        mww 0xE01FC004 0x00000003       ;# MAMTIM: 3 clock cycles
+        mww 0xE01FC000 0x00000002       ;# MAMCR: fully enabled
+
+        # Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0)
+        mww 0xE002C014 0x55010115       ;# PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,
+                                         # P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,
+                                         # P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3
+        mww 0xE002C018 0x55555555       ;# PINSEL6: P3.0...P3.15=D0...D15
+        mww 0xE002C01C 0x55555555       ;# PINSEL7: P3.16...P3.31=D16...D31
+        mww 0xE002C020 0x55555555       ;# PINSEL8: P4.0...P4.15=A0...A15
+        mww 0xE002C024 0x50051555       ;# PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,
+                                         # P4.25=WE, P4.30=CS0, P4.31=CS1
+        mww 0xFFE08000 0x00000001       ;# EMCControl: Enable EMC
+
+        # Start PLL, then use faster JTAG clock
+        enable_pll
+        jtag_rclk 3000
+
+        # 16-bit flash @ CS0 (SST39VF3201-70)
+        mww 0xFFE08200 0x00080081       ;# EMCStaticConfig0: 16 bit, PB=1, buffers on
+        mww 0xFFE08204 0x00000000       ;# EMCStaticWaitWen0
+        mww 0xFFE08208 0x00000000       ;# EMCStaticWaitOen0
+        mww 0xFFE0820C 0x00000005       ;# EMCStaticWaitRd0
+        mww 0xFFE08210 0x00000005       ;# EMCStaticWaitPage0
+        mww 0xFFE08214 0x00000003       ;# EMCStaticWaitWr0
+        mww 0xFFE08218 0x00000001       ;# EMCStaticWaitTurn0
+
+        # 8-bit NAND @ CS1
+        # TODO
+
+        # 32-bit SDRAM @ DYCS0 (K4M563233G-HN75)
+        mww 0xFFE08028 0x00000001       ;# EMCDynamicReadConfig
+        mww 0xFFE08030 0x00000001       ;# EMCDynamicRP
+        mww 0xFFE08034 0x00000003       ;# EMCDynamicRAS
+        mww 0xFFE08038 0x00000005       ;# EMCDynamicSREX
+        mww 0xFFE0803C 0x00000001       ;# EMCDynamicAPR
+        mww 0xFFE08040 0x00000005       ;# EMCDynamicDAL
+        mww 0xFFE08044 0x00000001       ;# EMCDynamicWR
+        mww 0xFFE08048 0x00000005       ;# EMCDynamicRC
+        mww 0xFFE0804C 0x00000005       ;# EMCDynamicRFC
+        mww 0xFFE08050 0x00000005       ;# EMCDynamicXSR
+        mww 0xFFE08054 0x00000001       ;# EMCDynamicRRD
+        mww 0xFFE08058 0x00000001       ;# EMCDynamicMRD
+        #
+        mww 0xFFE08104 0x00000202       ;# EMCDynamicRasCas0
+        mww 0xFFE08100 0x00005488       ;# EMCDynamicConfig0
+        sleep 100
+        mww 0xFFE08020 0x00000183       ;# EMCDynamicControl: Clock on continuously, NOP
+        sleep 10
+        mww 0xFFE08020 0x00000103       ;# EMCDynamicControl: PRECHARGE-ALL
+        mww 0xFFE08024 0x00000046       ;# EMCDynamicRefresh
+        sleep 100
+        mww 0xFFE08020 0x00000083       ;# EMCDynamicControl: MODE
+        mdw 0xA0011000 1                ;# Set SDRAM mode register
+        mww 0xFFE08020 0x00000000       ;# EMCDynamicControl: NORMAL
+        mww 0xFFE08100 0x00085488       ;# EMCDynamicConfig0: Enable buffers
+    }
+
+    $_TARGETNAME configure -event gdb-attach {
+        # Without this gdb-attach will first time as probe will fail
+        reset init
+    }
+}
+
+# Enable the PLL.
+# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
+# Note: The PLL output runs at a frequency N times the desired CPU clock.
+#       It in unavoidable that the CPU clock drops down to (4 MHz/N) during
+#       the initialization!
+#       Here: N=4
+#       Note that if the PLL is already active at the time this script is
+#       called, the effective value of N is the value of CCLKCFG at that time!
+#
+proc enable_pll {} {
+    # Disconnect PLL in case it is already connected
+    if {[expr {[read_register 0xE01FC080] & 0x03}] == 3} {
+        # Disconnect it, but leave it enabled
+        # (This MUST be done in two steps)
+        mww 0xE01FC080 0x00000001       ;# PLLCON: disconnect PLL
+        mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+        mww 0xE01FC08C 0x00000055       ;# PLLFEED
+    }
+    # Disable PLL (as it might already be enabled at this time!)
+    mww 0xE01FC080 0x00000000       ;# PLLCON: disable PLL
+    mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+    mww 0xE01FC08C 0x00000055       ;# PLLFEED
+
+    # Setup PLL to generate 288 MHz from internal RC oscillator
+    mww 0xE01FC10C 0x00000000       ;# CLKSRCSEL: IRC
+    mww 0xE01FC084 0x00000023       ;# PLLCFG: N=1, M=36
+    mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+    mww 0xE01FC08C 0x00000055       ;# PLLFEED
+    mww 0xE01FC080 0x00000001       ;# PLLCON: enable PLL
+    mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+    mww 0xE01FC08C 0x00000055       ;# PLLFEED
+    sleep 100
+    mww 0xE01FC104 0x00000003       ;# CCLKCFG: divide by 4 (72 MHz)
+    mww 0xE01FC080 0x00000003       ;# PLLCON: connect PLL
+    mww 0xE01FC08C 0x000000AA       ;# PLLFEED
+    mww 0xE01FC08C 0x00000055       ;# PLLFEED
+}
--- a/scripts/board/emcraft_imx8m-som-bsb.cfg
+++ b/scripts/board/emcraft_imx8m-som-bsb.cfg
@ -0,0 +1,22 @@
+#
+# configuration file for Emcraft IMX8M-SOM-BSB
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# SRST and TRST are wired up
+reset_config trst_and_srst
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+# board has an i.MX8MQ with 4 Cortex-A53 cores
+set CHIPNAME imx8mq
+set CHIPCORES 4
+
+# source SoC configuration
+source [find target/imx8m.cfg]
--- a/scripts/board/emcraft_twr-vf6-som-bsb.cfg
+++ b/scripts/board/emcraft_twr-vf6-som-bsb.cfg
@ -0,0 +1,9 @@
+#
+# EmCraft Systems TWR-VF6-SOM-BSB
+#
+# http://www.emcraft.com/products/259#twr-kit
+#
+
+source [find board/emcraft_vf6-som.cfg]
+
+reset_config srst_only srst_nogate
--- a/scripts/board/emcraft_vf6-som.cfg
+++ b/scripts/board/emcraft_vf6-som.cfg
@ -0,0 +1,8 @@
+#
+# EmCraft Systems Vybrid VF6 SOM
+#
+# http://www.emcraft.com/products/259#som
+#
+
+set CHIPNAME vf610
+source [find target/vybrid_vf6xx.cfg]
--- a/scripts/board/ethernut3.cfg
+++ b/scripts/board/ethernut3.cfg
@ -0,0 +1,86 @@
+#
+# Ethernut 3 board configuration file
+#
+# http://www.ethernut.de/en/hardware/enut3/
+
+
+# AT91R40008-66AU ARM7TDMI Microcontroller
+# 256kB internal RAM
+source [find target/at91r40008.cfg]
+
+
+# AT49BV322A-70TU NOR Flash
+# 2M x 16 mode at address 0x10000000
+# Common flash interface supported
+#
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME
+
+
+# Micrel MIC2775-29YM5 Supervisor
+# Reset output will remain active for 280ms (maximum)
+#
+adapter srst delay 300
+jtag_ntrst_delay 300
+
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+adapter speed 16000
+
+
+# Target events
+#
+$_TARGETNAME configure -event reset-init { board_init }
+
+# Initialize board hardware
+#
+proc board_init { } {
+	board_remap
+	flash probe 0
+}
+
+# Memory remap
+#
+proc board_remap {{VERBOSE 0}} {
+	# CS0: NOR flash
+	#      16MB @ 0x10000000
+	#      16-bit data bus
+	#      4 wait states
+	#
+	mww 0xffe00000 0x1000212d
+
+	# CS1: Ethernet controller
+	#      1MB @ 0x20000000
+	#      16-bit data bus
+	#      2 wait states
+	#      Byte select access
+	#
+	mww 0xffe00004 0x20003025
+
+	# CS2: CPLD registers
+	#      1MB @ 0x21000000
+	#      8-bit data bus
+	#      2 wait states
+	#
+	mww 0xffe00008 0x21002026
+
+	# CS3: Expansion bus
+	#      1MB @ 0x22000000
+	#      8-bit data bus
+	#      8 wait states
+	#
+	mww 0xffe00010 0x22002e3e
+
+	# Remap command
+	#
+	mww 0xffe00020 0x00000001
+
+	if {$VERBOSE != 0} {
+		echo "0x00000000 RAM"
+		echo "0x10000000 Flash"
+		echo "0x20000000 Ethernet"
+		echo "0x21000000 CPLD"
+		echo "0x22000000 Expansion"
+	}
+}
--- a/scripts/board/evb-lan9255.cfg
+++ b/scripts/board/evb-lan9255.cfg
@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Microchip LAN9255 evaluation board
+# https://www.microchip.com/en-us/development-tool/EV25Y25A
+#
+
+set CHIPNAME same53
+
+source [find target/atsame5x.cfg]
+
+reset_config srst_only
--- a/Show More
+++ b/Show More