# script for AT32f4xx family

#
# AT32 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

# increase working area
set WORKAREASIZE 0x1000
if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME at32f4xx
}

if { [info exists ENDIAN] } {
   set _ENDIAN $ENDIAN
} else {
   set _ENDIAN little
}

# Work-area is a space in RAM used for flash programming
# By default use 64kB
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x1000
}

#jtag scan chain
if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   if { [using_jtag] } {
      set _CPUTAPID 0x4ba00477
   } else {
      set _CPUTAPID 0x2ba01477
   }
}

# Allow overriding the Flash bank size
if { [info exists FLASH_SIZE] } {
    set _FLASH_SIZE $FLASH_SIZE
} else {
    # autodetect size
    set _FLASH_SIZE 0
}


swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0


# flash size will be probed
set _FLASHNAME $_CHIPNAME.bank1
flash bank $_FLASHNAME at32f4xx 0x08000000 0 0 0 $_TARGETNAME 0x40023C00 0x1FFFF800


# enable at32 qspi1
set QSPI1 1

if { [info exists QSPI1] && $QSPI1 } {
    set a [llength [flash list]]
	set _QSPINAME $_CHIPNAME.qspi1
	flash bank $_QSPINAME at32qspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
}




# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
adapter speed 5000

adapter srst delay 100

reset_config srst_nogate

if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
     cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event examine-end {
	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
	mmw 0xE0042004 0x00000307 0
}

$_TARGETNAME configure -event trace-config {
	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
	# change this value accordingly to configure trace pins
	# assignment
	mmw 0xE0042004 0x00000020 0
}

$_TARGETNAME configure -event reset-init {
	mww 0x400238A0 0x000F5000
	mww 0x40023C00 0x000001F1
	sleep 1
	qspi1_init
}

$_TARGETNAME configure -event halted { qspi1_init }

# QSPI1 initialization GPIOA 0x40020000, GPIOB 0x40020400, GPIOC 0x40020800 GPIOD 0x40020C00, GPIOE 0x40021000, GPIOF 0x40021400, GPIOG 0x40021800 GPIOH 0x40021C00
proc qspi1_init { } {
	global a
	mww 0x400238A0 0x000F5000
	mww 0x40023C00 0x000001F1
	
	#Enable GPIO AHB Clock 
	mmw 0x40023830 0x0000003F 0 ;# CRM->AHBEN1 |= GPIOA-GPIOH (enable clocks)
	mmw 0x40023838 0x00000002 0 ;# Enable QSPI1 and QSPI2 Clock
	
###################Select QSPI1 GPIO IO0, IO1, IO2, IO3, SCK, CS##############################
	# set QSPI1_IO0_PA6 1 ;#PA6
	# set QSPI1_IO0_PB0 1 ;#PB0
	# set QSPI1_IO0_PB11 1 ;#PB11
	 set QSPI1_IO0_PC9 1  ;#PC9
	# set QSPI1_IO0_PB5 1 ;#PB5
	# set QSPI1_IO0_PF6 1    ;#PF6
	
	# set QSPI1_IO1_PA7 1 ;#PA7
	# set QSPI1_IO1_PB10 1 ;#PB10
	# set QSPI1_IO1_PC10 1 ;#PC10
	 set QSPI1_IO1_PB7 1 ;#PB7
	
	# set QSPI1_IO2_PA15 1 ;#PA15
	# set QSPI1_IO2_PC4  1 ;#PC4
	 set QSPI1_IO2_PC8 1 ;#PC8
	# set QSPI1_IO2_PA6 1 ;#PA6
	
	# set QSPI1_IO3_PA1 1 ;#PA1
	# set QSPI1_IO3_PB3  1 ;#PB3
	 set QSPI1_IO3_PC5 1 ;#PC5
	
	# set QSPI1_SCK_PB1 1 ;#PB1
	 set QSPI1_SCK_PB2  1 ;#PB2
	# set QSPI1_SCK_PB4 1 ;#PB4
	  
	# set QSPI1_CS_PB6 1 ;#PB6
	# set QSPI1_CS_PB9  1 ;#PB9
	# set QSPI1_CS_PB10 1 ;#PB10
	 set QSPI1_CS_PC11 1 ;#PC11
	# set QSPI1_CS_PA2 1 ;#PA2
	
	
##############################QSPI1_IO0###############################	
	# QSPI_IO0: PA6, PB0, PB11, PC9, PB5, PF6
	if { [info exists QSPI1_IO0_PA6] && $QSPI1_IO0_PA6 } {	
		mmw 0x40020000 0x00002000 0
		mmw 0x40020008 0x00001000 0
		mmw 0x40020020 0x0B000000 0
	}
	
	if { [info exists QSPI1_IO0_PB0] && $QSPI1_IO0_PB0 } {	
		mmw 0x40020400 0x00000002 0
		mmw 0x40020408 0x00000001 0
		mmw 0x40020420 0x0000000B 0
	}
	
	if { [info exists QSPI1_IO0_PB11] && $QSPI1_IO0_PB11 } {	
		mmw 0x40020400 0x00800000 0
		mmw 0x40020408 0x00400000 0
		mmw 0x40020424 0x0000B000 0
	}
	
	if { [info exists QSPI1_IO0_PC9] && $QSPI1_IO0_PC9 } {	
		mmw 0x40020800 0x00080000 0
		mmw 0x40020808 0x00040000 0
		mmw 0x40020824 0x000000B0 0
	}
	
	if { [info exists QSPI1_IO0_PB5] && $QSPI1_IO0_PB5 } {	
		mmw 0x40020400 0x00000800 0
		mmw 0x40020408 0x00000400 0
		mmw 0x40020420 0x00B00000 0
	}
	
	if { [info exists QSPI1_IO0_PF6] && $QSPI1_IO0_PF6 } {	
		mmw 0x40021400 0x00002000 0
		mmw 0x40021408 0x00001000 0
		mmw 0x40021420 0x0B000000 0
	}
	
	
##############################QSPI1_IO1###############################	
	#QSPI_IO1: PA7, PB7, PB10, PC10
	
	if { [info exists QSPI1_IO1_PA7] && $QSPI1_IO1_PA7 } {	
		mmw 0x40020000 0x00008000 0
		mmw 0x40020008 0x00004000 0
		mmw 0x40020020 0xB0000000 0
	}
	
	if { [info exists QSPI1_IO1_PB7] && $QSPI1_IO1_PB7 } {	
		mmw 0x40020400 0x00008000 0
		mmw 0x40020408 0x00004000 0
		mmw 0x40020420 0xB0000000 0
	}
	
	if { [info exists QSPI1_IO1_PB10] && $QSPI1_IO1_PB10 } {	
		mmw 0x40020400 0x00200000 0
		mmw 0x40020408 0x00100000 0
		mmw 0x40020424 0x00000B00 0
	}
	
	if { [info exists QSPI1_IO1_PC10] && $QSPI1_IO1_PC10 } {	
		mmw 0x40020800 0x00200000 0
		mmw 0x40020808 0x00100000 0
		mmw 0x40020824 0x00000B00 0
	}
	
##############################QSPI1_IO2###############################		
	#QSPI_IO2: PA6, PA15, PC4, PC8
	
	if { [info exists QSPI1_IO2_PA6] && $QSPI1_IO2_PA6 } {	
	
		mmw 0x40020000 0x00002000 0
		mmw 0x40020008 0x00001000 0
		mmw 0x40020020 0x0D000000 0
	}
	
	if { [info exists QSPI1_IO2_PA15] && $QSPI1_IO2_PA15 } {	
	
		mmw 0x40020000 0x80000000 0
		mmw 0x40020008 0x40000000 0
		mmw 0x40020024 0xB0000000 0
	}
	
	if { [info exists QSPI1_IO2_PC4] && $QSPI1_IO2_PC4 } {	
	
		mmw 0x40020800 0x00000200 0
		mmw 0x40020808 0x00000100 0
		mmw 0x40020820 0x000B0000 0
	}
	
	if { [info exists QSPI1_IO2_PC8] && $QSPI1_IO2_PC8 } {	
	
		mmw 0x40020800 0x00020000 0
		mmw 0x40020808 0x00010000 0
		mmw 0x40020824 0x0000000B 0
	}
	
	
##############################QSPI1_IO3###############################		
	#QSPI_IO3: PA1, PB3, PC5
	
	if { [info exists QSPI1_IO3_PA1] && $QSPI1_IO3_PA1 } {	
		mmw 0x40020000 0x00000008 0
		mmw 0x40020008 0x00000004 0
		mmw 0x40020020 0x000000B0 0
	}
	
	if { [info exists QSPI1_IO3_PB3] && $QSPI1_IO3_PB3 } {	
		mmw 0x40020400 0x00000080 0
		mmw 0x40020408 0x00000040 0
		mmw 0x40020420 0x0000B000 0
	}
	
	if { [info exists QSPI1_IO3_PC5] && $QSPI1_IO3_PC5 } {	
	
		mmw 0x40020800 0x00000800 0
		mmw 0x40020808 0x00000400 0
		mmw 0x40020820 0x00B00000 0
	}
	
##############################QSPI1_SCK###############################		
	#QSPI_SCK: PB1, PB2, PB4
	
	if { [info exists QSPI1_SCK_PB1] && $QSPI1_SCK_PB1 } {	
		mmw 0x40020400 0x00000008 0
		mmw 0x40020408 0x00000004 0
		mmw 0x40020420 0x000000B0 0
	}
	
	if { [info exists QSPI1_SCK_PB2] && $QSPI1_SCK_PB2 } {	
		mmw 0x40020400 0x00000020 0
		mmw 0x40020408 0x00000010 0
		mmw 0x40020420 0x00000B00 0
	}
	
	if { [info exists QSPI1_SCK_PB4] && $QSPI1_SCK_PB4 } {	
		mmw 0x40020400 0x00000200 0
		mmw 0x40020408 0x00000100 0
		mmw 0x40020420 0x000B0000 0
	}
	
	
##############################QSPI1_CS###############################		
	#QSPI_CS: PA2, PB6, PB9, PB10, PC11
	
	if { [info exists QSPI1_CS_PA2] && $QSPI1_CS_PA2 } {	
		mmw 0x40020000 0x00000020 0
		mmw 0x40020008 0x00000010 0
		mmw 0x40020020 0x00000B00 0
	}
	
	if { [info exists QSPI1_CS_PB6] && $QSPI1_CS_PB6 } {	
		mmw 0x40020400 0x00002000 0
		mmw 0x40020408 0x00001000 0
		mmw 0x40020420 0x0B000000 0
	}
	
	if { [info exists QSPI1_CS_PB9] && $QSPI1_CS_PB9 } {	
		mmw 0x40020400 0x00080000 0
		mmw 0x40020408 0x00040000 0
		mmw 0x40020424 0x000000B0 0
	}
	
	if { [info exists QSPI1_CS_PB10] && $QSPI1_CS_PB10 } {	
		mmw 0x40020400 0x00200000 0
		mmw 0x40020408 0x00100000 0
		mmw 0x40020424 0x00000D00 0
	}
	
	if { [info exists QSPI1_CS_PC11] && $QSPI1_CS_PC11 } {	
		mmw 0x40020800 0x00800000 0
		mmw 0x40020808 0x00400000 0
		mmw 0x40020824 0x0000B000 0
	}
}	
