//
// Created by ilya on 09.01.24.
//

#ifndef NAU88U10YG_ENUMS_H
#define NAU88U10YG_ENUMS_H

////  POWER MANAGEMENT REGISTERS
// IMPEDANCE SELECTION
typedef enum {
    NAU88U10YG_PowerManagement1_REFIMP_Disable = 0b00,
    NAU88U10YG_PowerManagement1_REFIMP_80KOm = 0b01,
    NAU88U10YG_PowerManagement1_REFIMP_300KOm = 0b10,
    NAU88U10YG_PowerManagement1_REFIMP_3KOm = 0b11,
}eNAU88U10YG_PowerManagement1_REFIMP;

//// AUDIO CONTROL REGISTERS (REG_AUDIO_INTERFACE)
// Word Length Selection
typedef enum {
    NAU88U10YG_AudioInterface_WLEN_16Bits = 0b00,
    NAU88U10YG_AudioInterface_WLEN_20Bits = 0b01,
    NAU88U10YG_AudioInterface_WLEN_24Bits = 0b10,
    NAU88U10YG_AudioInterface_WLEN_32Bits = 0b11,
}eNAU88U10YG_AudioInterface_WLEN;

// Audio Data Format Select
typedef enum {
    NAU88U10YG_AudioInterface_AIFMT_RightJustified = 0b00,
    NAU88U10YG_AudioInterface_AIFMT_LeftJustified = 0b01,
    NAU88U10YG_AudioInterface_AIFMT_I2S = 0b10,
    NAU88U10YG_AudioInterface_AIFMT_PCM_A = 0b11,
}eNAU88U10YG_AudioInterface_AIFMT;

// Companding Mode 8-bit word enable
typedef enum {
    NAU88U10YG_CompandingCMB8_NormalOperation = 0b0,
    NAU88U10YG_CompandingCMB8_8bit_Operation = 0b1,
}eNAU88U10YG_CompandingCMB8;

// DAC Companding Selection
typedef enum {
    NAU88U10YG_CompandingDACCM_Disabled = 0b00,
    NAU88U10YG_CompandingDACCM_uLaw = 0b10,
    NAU88U10YG_CompandingDACCM_ALaw = 0b11,
}eNAU88U10YG_CompandingDACCM;

// ADC Companding Selection
typedef enum {
    NAU88U10YG_CompandingADCCM_Disabled = 0b00,
    NAU88U10YG_CompandingADCCM_uLaw = 0b10,
    NAU88U10YG_CompandingADCCM_ALaw = 0b11,
}eNAU88U10YG_CompandingADCCM;

//// Clock Control Register
// Master Clock Selection
typedef enum {
    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div1 = 0b000,
    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div1_5 = 0b001,
    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div2 = 0b010,
    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div3 = 0b011,
    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div4 = 0b100,
    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div6 = 0b101,
    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div8 = 0b110,
    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div12 = 0b111,
}eNAU88U10YG_ClockControl1_MCLKSEL;

// Bit Clock Select
typedef enum {
    NAU88U10YG_ClockControl1_BCLKSEL_Mode_div1 = 0b000, //BCLK=MCLK
    NAU88U10YG_ClockControl1_BCLKSEL_Mode_div2 = 0b001, //BCLK=MCLK/2
    NAU88U10YG_ClockControl1_BCLKSEL_Mode_div4 = 0b010,
    NAU88U10YG_ClockControl1_BCLKSEL_Mode_div8 = 0b011,
    NAU88U10YG_ClockControl1_BCLKSEL_Mode_div16 = 0b100,
    NAU88U10YG_ClockControl1_BCLKSEL_Mode_div32 = 0b101,
}eNAU88U10YG_ClockControl1_BCLKSEL;

// Source of Internal Clock
typedef enum {
    NAU88U10YG_ClockControl1_CLKM_PLL_Bypassed = 0b0,
    NAU88U10YG_ClockControl1_CLKM_PLL_Output = 0b1
}eNAU88U10YG_ClockControl1_CLKM;

// FRAME and BCLK
typedef enum {
    NAU88U10YG_ClockControl1_CLKIOEN_Mode_Slave = 0b0,
    NAU88U10YG_ClockControl1_CLKIOEN_Mode_Master = 0b1
}eNAU88U10YG_ClockControl1_CLKIOEN;


/// Audio Sample Rate Control Register (Clock Control 2)
// Sample Rate Selection
typedef enum {
    NAU88U10YG_ClockControl2_SMPLR_Mode_48KHz = 0b000,
    NAU88U10YG_ClockControl2_SMPLR_Mode_32KHz = 0b001,
    NAU88U10YG_ClockControl2_SMPLR_Mode_24KHz = 0b010,
    NAU88U10YG_ClockControl2_SMPLR_Mode_16KHz = 0b011,
    NAU88U10YG_ClockControl2_SMPLR_Mode_12KHz = 0b100,
    NAU88U10YG_ClockControl2_SMPLR_Mode_8KHz = 0b101,
}eNAU88U10YG_ClockControl2_SMPLR;

// Slow Clock Enable
typedef enum {
    NAU88U10YG_ClockControl2_MCLK_SCLKEN_MCLK = 0b0,
    NAU88U10YG_ClockControl2_MCLK_SCLKEN_PLL_Output = 0b1, // Period 2^21 * MCLK
}eNAU88U10YG_ClockControl2_MCLK_SCLKEN;


//// DAC Control Register (REG_DAC_CTRL)
// Over Sample Rate
typedef enum {
    NAU88U10YG_DAC_CTRL_DACOS_64x = 0b0,
    NAU88U10YG_DAC_CTRL_DACOS_128x = 0b1,
}eNAU88U10YG_DAC_CTRL_DACOS;

// Polarity Invert
typedef enum {
    NAU88U10YG_DAC_CTRL_DACPL_Normal = 0b0,
    eNAU88U10YG_DAC_CTRL_DACPL_DAC_Output_invert = 0b1
}eNAU88U10YG_DAC_CTRL_DACPL;

// De-emphasis
typedef enum {
    NAU88U10YG_DAC_CTRL_DEEMP_No_deEmphasis = 0b00,
    NAU88U10YG_DAC_CTRL_DEEMP_SMPLR_33KHz = 0b01,
    NAU88U10YG_DAC_CTRL_DEEMP_SMPLR_44_1KHz = 0b10,
    NAU88U10YG_DAC_CTRL_DEEMP_SMPLR_48KHz = 0b11,
}eNAU88U10YG_DAC_CTRL_DEEMP;

////  DAC Gain Control Register (REG_DAC_VOLUME)
// DAC Gain (DACGAIN)
// DAC Gain Range -127dB to 0dB @ 0.5 increments
// 0x0 - Digital Mute

//// ADC Control Register (REG_ADC_CTRL)
// Audio or Application Mode
typedef enum {
    NAU88U10YG_ADC_CTRL_HPFAM_Audio = 0b0, // 1st order, fc ~ 3.7 Hz
    NAU88U10YG_ADC_CTRL_HPFAM_Application = 0b1 //2 nd order, fc = HPF
}eNAU88U10YG_ADC_CTRL_HPFAM;

// Over Sample Rate
typedef enum {
    NAU88U10YG_ADC_CTRL_ADCOS_64x = 0b0, // Lowest power
    NAU88U10YG_ADC_CTRL_ADCOS_128x = 0b1 // best SNR
}eNAU88U10YG_ADC_CTRL_ADCOS;

// High Pass Filter
//HPF 12.3.7 ADC Control Register page 67

// ADC Gain Control Register
//0x0 - unused
// ADC Gain Range -127dB to 0dB @ 0.5 increments

/// INPUT, OUTPUT & MIXER CONTROL
/// Output Register
// MONO Output Boost Stage
typedef enum {
    NAU88U10YG_OUTPUT_CTRL_MOUTBST_x1_0VREF_GainBoost = 0b00, //(1.0 x VREF) Gain Boost
    NAU88U10YG_OUTPUT_CTRL_MOUTBST_x1_5VREF_GainBoost = 0b01, //(1.5 x VREF) Gain Boost
}eNAU88U10YG_OUTPUT_CTRL_MOUTBST;

// Speaker Output Boost Stage
typedef enum {
    NAU88U10YG_OUTPUT_CTRL_SPKBST_x1_0VREF_GainBoost = 0b00, //(1.0 x VREF) Gain Boost
    NAU88U10YG_OUTPUT_CTRL_SPKBST_x1_5VREF_GainBoost = 0b01, //(1.5 x VREF) Gain Boost
}eNAU88U10YG_OUTPUT_CTRL_SPKBST;

typedef enum {
    NAU88U10YG_OUTPUT_CTRL_AOUTIMP_1kOm = 0b00, //~1kΩ
    NAU88U10YG_OUTPUT_CTRL_AOUTIMP_30kOm = 0b01, //~30 kΩ
}eNAU88U10YG_OUTPUT_CTRL_AOUTIMP;
#endif //NAU88U10YG_ENUMS_H