Init

Inc/nau88u10yg.h

@@ -0,0 +1,298 @@
+//
+// Created by ilya on 10.01.24.
+//
+
+#ifndef NAU88U10YG_H
+#define NAU88U10YG_H
+
+#include "nau88u10yg_enums.h"
+#include "nau88u10yg_regs.h"
+#include "stdbool.h"
+#include "stdint.h"
+#include "I2cIO.h"
+
+// Desired Output 11.28960
+#define PLL_K_1_MCLK_26MHz_mode1 0x3C
+#define PLL_K_2_MCLK_26MHz_mode1 0x145
+#define PLL_K_3_MCLK_26MHz_mode1 0x1D4
+
+// Desired Output 12.28800
+#define PLL_K_1_MCLK_26MHz_mode2 0x23
+#define PLL_K_2_MCLK_26MHz_mode2 0x1EA
+#define PLL_K_3_MCLK_26MHz_mode2 0x126
+
+//todo инвертировать данные во всех структурах, аналогично power manager, проверить, нужно ли это на самом деле
+
+typedef union {
+    uint16_t raw;
+    struct  {
+//        uint8_t addr: 7;
+        uint16_t data: 9;
+        uint8_t addr: 7;
+    };
+} NAU88U10YG_RegAddrPacket;
+
+typedef union {
+    uint8_t raw: 8;
+    struct  {
+        uint8_t data: 1;
+        uint8_t regAddr: 7;
+    };
+} NAU88U10YG_StartReadingConditionPacket;
+
+///-------------------------------------------- POWER MANAGEMENT -------------------------------------------------------
+typedef union {
+    uint16_t raw: 9;
+    struct {
+        eNAU88U10YG_PowerManagement1_REFIMP ReferenceImpedance_Select: 2;
+        bool IOBuffer_Enable: 1;
+        bool AnalogueAmplifierBiasControl_Enable: 1;
+        bool MicrophoneBias_Enable: 1;
+        bool PLL_Enable: 1;
+        uint8_t : 2;
+        bool DCBUF_Enable: 1;
+        //
+//        bool DCBUF_Enable: 1;
+//        uint8_t : 2;
+//        bool PLL_Enable: 1;
+//        bool MicrophoneBias_Enable: 1;
+//        bool AnalogueAmplifierBiasControl_Enable: 1;
+//        bool IOBuffer_Enable: 1;
+//        eNAU88U10YG_PowerManagement1_REFIMP ReferenceImpedance_Select: 2;
+    };
+} NAU88U10YG_PowerManagement1;
+
+typedef union {
+    uint16_t raw: 9;
+    struct {
+        bool ADC_Enable: 1;
+        uint8_t : 1;
+        bool PGA_Enable: 1;
+        uint8_t : 1;
+        bool InputBoost_Enable: 1;
+        uint8_t : 4;
+        //
+//        uint8_t : 4;
+//        bool InputBoost_Enable: 1;
+//        uint8_t : 1;
+//        bool PGA_Enable: 1;
+//        uint8_t : 1;
+//        bool ADC_Enable: 1;
+    };
+} NAU88U10YG_PowerManagement2;
+
+typedef union {
+    uint16_t raw: 9;
+    struct {
+        bool DAC_Enable:1;
+        uint8_t : 1;
+        bool SpeakerMixer_Enable:1;
+        bool MONOMixer_Enable:1;
+        uint8_t : 1;
+        bool SPKOUT_P_Enable: 1;
+        bool SPKOUT_N_Enable: 1;
+        bool MOUT_Enable: 1;
+        uint8_t : 1;
+        //
+//        uint8_t : 1;
+//        bool MOUT_Enable: 1;
+//        bool SPKOUT_N_Enable: 1;
+//        bool SPKOUT_P_Enable: 1;
+//        uint8_t : 1;
+//        bool MONOMixer_Enable:1;
+//        bool SpeakerMixer_Enable:1;
+//        uint8_t : 1;
+//        bool DAC_Enable:1;
+    };
+} NAU88U10YG_PowerManagement3;
+
+typedef struct {
+    NAU88U10YG_PowerManagement1 powerManagement1;
+    NAU88U10YG_PowerManagement2 powerManagement2;
+    NAU88U10YG_PowerManagement3 powerManagement3;
+}NAU88U10YG_PowerManagement_State;
+
+
+///----------------------------------------------- AUDIO CONTROL -------------------------------------------------------
+typedef union {
+    uint16_t raw: 9;
+    struct {
+        bool BCLK_Polarity:1;
+        bool FrameClock_Polarity:1;
+        eNAU88U10YG_AudioInterface_WLEN WordLength_Selection:2;
+        eNAU88U10YG_AudioInterface_AIFMT AudioDataFormat_Select:2;
+        bool DACDatePhasesOfFrameClock:1; //0-left 1-right
+        bool ADCDatePhasesOfFrameClock:1; //0-left 1-right
+        uint8_t : 1;
+    };
+} NAU88U10YG_AudioInterface;
+
+typedef union {
+    uint16_t raw: 9;
+    struct {
+        uint8_t : 3;
+        bool CompandingMode_8bit_Enable:1;
+        eNAU88U10YG_CompandingDACCM DACCompanding_Select:2;
+        eNAU88U10YG_CompandingADCCM ADCCompanding_Select:2;
+        bool ADDAP:1; //  Setting ADDAP[0] bit to HIGH enables the loopback so that the ADC data can be fed directly into the DAC input.
+    };
+} NAU88U10YG_AudioInterfaceCompanding;
+
+typedef union {
+    uint16_t raw: 9;
+    struct {
+        eNAU88U10YG_ClockControl1_CLKM InternalClock_Sourse:1;
+        eNAU88U10YG_ClockControl1_MCLKSEL MasterClock_Selection:3;
+        eNAU88U10YG_ClockControl1_BCLKSEL BitClockSelect:3;
+        uint8_t : 1;
+        eNAU88U10YG_ClockControl1_CLKIOEN FRAMEandBCLk_Mode:1;
+    };
+} NAU88U10YG_ClockControl;
+
+typedef union {
+    uint16_t raw: 9;
+    struct {
+        uint8_t : 5;
+        eNAU88U10YG_ClockControl2_SMPLR SampleRate_Selection:3;
+        bool SlowClock_Enable:1;
+    };
+} NAU88U10YG_AudioSampleRateControl;
+
+typedef union {
+    uint16_t raw: 9;
+    struct {
+        uint8_t : 2;
+        bool SoftMute_Enable:1;
+        eNAU88U10YG_DAC_CTRL_DEEMP De_emphasis_Select:2;
+        eNAU88U10YG_DAC_CTRL_DACOS OverSampleRate:1;
+        bool AutoMute_Enable:1;
+        uint8_t : 1;
+        eNAU88U10YG_DAC_CTRL_DACPL PolarityInvert:1;
+    };
+} NAU88U10YG_DACControl;
+
+typedef union {
+    uint16_t raw: 9;
+    struct {
+        uint8_t : 1;
+        uint8_t DACGain :8;
+    };
+} NAU88U10YG_DACGainControl;
+
+typedef union {
+    uint16_t raw: 9;
+     struct {
+        bool HighPassFilter_Enable:1;
+        eNAU88U10YG_ADC_CTRL_HPFAM AudioOrAplication_Mode:1;
+        uint8_t HigtPassFilter:3;
+        eNAU88U10YG_ADC_CTRL_ADCOS OverSampleRate:1;
+        bool ADCPolarity:1;
+    };
+} NAU88U10YG_ADCControl;
+
+typedef union {
+    uint16_t raw: 9;
+    struct {
+        uint8_t : 1;
+        uint8_t ADCGain :8;
+    };
+} NAU88U10YG_ADCGainControl;
+
+typedef struct {
+    NAU88U10YG_AudioInterface AudioInterface;
+    NAU88U10YG_AudioInterfaceCompanding AudioInterfaceCopanding;
+    NAU88U10YG_ClockControl ClockControl;
+    NAU88U10YG_AudioSampleRateControl AudioSampleRateControl;
+    NAU88U10YG_DACControl DACControl;
+    NAU88U10YG_DACGainControl DACGainControl;
+    NAU88U10YG_ADCControl ADCControl;
+    NAU88U10YG_ADCGainControl ADCGainControl;
+}NAU88U10YG_AudioControl;
+
+
+///------------------------------------------------- PLL CONTROL -----------------------------------------------------//
+typedef struct {
+    uint16_t raw: 9;
+    struct {
+        uint8_t : 4;
+        uint8_t PLLClock :1;
+        uint8_t PLLInteger :4;
+    };
+}NAU88U10YG_PLLControl;
+
+typedef struct {
+    uint16_t raw: 9;
+    struct {
+        uint8_t : 3;
+        uint8_t PLLK :6;
+    };
+}NAU88U10YG_PLLK1;
+
+typedef struct {
+    uint16_t raw: 9;
+    struct {
+        uint16_t PLLK :9;
+    };
+}NAU88U10YG_PLLK2;
+
+typedef struct {
+    uint16_t raw: 9;
+    struct {
+        uint16_t PLLK :9;
+    };
+}NAU88U10YG_PLLK3;
+
+typedef struct {
+    NAU88U10YG_PLLControl PLL_Control;
+    NAU88U10YG_PLLK1 PLLK1;
+    NAU88U10YG_PLLK2 PLLK2;
+    NAU88U10YG_PLLK3 PLLK3;
+}NAU88U10YG_PLL;
+
+////-------------------------------------INPUT, OUTPUT & MIXER CONTROL--------------------------------------------------
+
+typedef struct {
+    uint16_t raw: 9;
+    struct {
+        uint8_t : 1;
+        bool MOUTAttenuation :1;
+        bool SPKAttenuation :1;
+        uint8_t : 6;
+    };
+}NAU88U10YG_AttenuationControl;
+
+typedef struct {
+    uint16_t raw: 9;
+    struct {
+        eNAU88U10YG_OUTPUT_CTRL_AOUTIMP AnalogOutputResistance :1;
+        bool ThermalShutdown_Enable :1;
+        eNAU88U10YG_OUTPUT_CTRL_SPKBST SpeakerOutputBoostStage  :1;
+        eNAU88U10YG_OUTPUT_CTRL_MOUTBST MONOOutputBoostStage :1;
+        uint8_t : 5;
+        //
+//        uint8_t : 3;
+//        uint8_t MONOOutputBoostStage :1;
+//        uint8_t SpeakerOutputBoostStage  :1;
+//        bool ThermalShutdown_Enable :1;
+//        uint8_t AnalogOutputResistance :1;
+    };
+}NAU88U10YG_OutputCtrl;
+
+typedef struct {
+    uint16_t raw: 9;
+    struct {
+        uint8_t SPKGain : 6;
+        bool SPKMuteEnable :1;
+        bool SPKZC :1;
+        uint8_t : 1;
+    };
+}NAU88U10YG_SpeakerGainControll;
+
+////--------------------------------------------------------------------------------------------------------------------
+
+bool xAudioCodecReadRegister(tI2cIO *i2c, uint16_t AdrRegQwery, uint16_t *DataRegResult);
+
+bool xAudioCodecWrite_Register8b_Data8b(tI2cIO *i2c, uint8_t reg, uint8_t data);
+
+
+#endif //NAU88U10YG_H

Inc/nau88u10yg_enums.h

@@ -0,0 +1,172 @@
+//
+// Created by ilya on 09.01.24.
+//
+
+#ifndef NAU88U10YG_ENUMS_H
+#define NAU88U10YG_ENUMS_H
+
+////  POWER MANAGEMENT REGISTERS
+// IMPEDANCE SELECTION
+typedef enum {
+    NAU88U10YG_PowerManagement1_REFIMP_Disable = 0b00,
+    NAU88U10YG_PowerManagement1_REFIMP_80KOm = 0b01,
+    NAU88U10YG_PowerManagement1_REFIMP_300KOm = 0b10,
+    NAU88U10YG_PowerManagement1_REFIMP_3KOm = 0b11,
+}eNAU88U10YG_PowerManagement1_REFIMP;
+
+//// AUDIO CONTROL REGISTERS (REG_AUDIO_INTERFACE)
+// Word Length Selection
+typedef enum {
+    NAU88U10YG_AudioInterface_WLEN_16Bits = 0b00,
+    NAU88U10YG_AudioInterface_WLEN_20Bits = 0b01,
+    NAU88U10YG_AudioInterface_WLEN_24Bits = 0b10,
+    NAU88U10YG_AudioInterface_WLEN_32Bits = 0b11,
+}eNAU88U10YG_AudioInterface_WLEN;
+
+// Audio Data Format Select
+typedef enum {
+    NAU88U10YG_AudioInterface_AIFMT_RightJustified = 0b00,
+    NAU88U10YG_AudioInterface_AIFMT_LeftJustified = 0b01,
+    NAU88U10YG_AudioInterface_AIFMT_I2S = 0b10,
+    NAU88U10YG_AudioInterface_AIFMT_PCM_A = 0b11,
+}eNAU88U10YG_AudioInterface_AIFMT;
+
+// Companding Mode 8-bit word enable
+typedef enum {
+    NAU88U10YG_CompandingCMB8_NormalOperation = 0b0,
+    NAU88U10YG_CompandingCMB8_8bit_Operation = 0b1,
+}eNAU88U10YG_CompandingCMB8;
+
+// DAC Companding Selection
+typedef enum {
+    NAU88U10YG_CompandingDACCM_Disabled = 0b00,
+    NAU88U10YG_CompandingDACCM_uLaw = 0b10,
+    NAU88U10YG_CompandingDACCM_ALaw = 0b11,
+}eNAU88U10YG_CompandingDACCM;
+
+// ADC Companding Selection
+typedef enum {
+    NAU88U10YG_CompandingADCCM_Disabled = 0b00,
+    NAU88U10YG_CompandingADCCM_uLaw = 0b10,
+    NAU88U10YG_CompandingADCCM_ALaw = 0b11,
+}eNAU88U10YG_CompandingADCCM;
+
+//// Clock Control Register
+// Master Clock Selection
+typedef enum {
+    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div1 = 0b000,
+    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div1_5 = 0b001,
+    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div2 = 0b010,
+    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div3 = 0b011,
+    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div4 = 0b100,
+    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div6 = 0b101,
+    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div8 = 0b110,
+    NAU88U10YG_ClockControl1_MCLKSEL_Mode_div12 = 0b111,
+}eNAU88U10YG_ClockControl1_MCLKSEL;
+
+// Bit Clock Select
+typedef enum {
+    NAU88U10YG_ClockControl1_BCLKSEL_Mode_div1 = 0b000, //BCLK=MCLK
+    NAU88U10YG_ClockControl1_BCLKSEL_Mode_div2 = 0b001, //BCLK=MCLK/2
+    NAU88U10YG_ClockControl1_BCLKSEL_Mode_div4 = 0b010,
+    NAU88U10YG_ClockControl1_BCLKSEL_Mode_div8 = 0b011,
+    NAU88U10YG_ClockControl1_BCLKSEL_Mode_div16 = 0b100,
+    NAU88U10YG_ClockControl1_BCLKSEL_Mode_div32 = 0b101,
+}eNAU88U10YG_ClockControl1_BCLKSEL;
+
+// Source of Internal Clock
+typedef enum {
+    NAU88U10YG_ClockControl1_CLKM_PLL_Bypassed = 0b0,
+    NAU88U10YG_ClockControl1_CLKM_PLL_Output = 0b1
+}eNAU88U10YG_ClockControl1_CLKM;
+
+// FRAME and BCLK
+typedef enum {
+    NAU88U10YG_ClockControl1_CLKIOEN_Mode_Slave = 0b0,
+    NAU88U10YG_ClockControl1_CLKIOEN_Mode_Master = 0b1
+}eNAU88U10YG_ClockControl1_CLKIOEN;
+
+
+/// Audio Sample Rate Control Register (Clock Control 2)
+// Sample Rate Selection
+typedef enum {
+    NAU88U10YG_ClockControl2_SMPLR_Mode_48KHz = 0b000,
+    NAU88U10YG_ClockControl2_SMPLR_Mode_32KHz = 0b001,
+    NAU88U10YG_ClockControl2_SMPLR_Mode_24KHz = 0b010,
+    NAU88U10YG_ClockControl2_SMPLR_Mode_16KHz = 0b011,
+    NAU88U10YG_ClockControl2_SMPLR_Mode_12KHz = 0b100,
+    NAU88U10YG_ClockControl2_SMPLR_Mode_8KHz = 0b101,
+}eNAU88U10YG_ClockControl2_SMPLR;
+
+// Slow Clock Enable
+typedef enum {
+    NAU88U10YG_ClockControl2_MCLK_SCLKEN_MCLK = 0b0,
+    NAU88U10YG_ClockControl2_MCLK_SCLKEN_PLL_Output = 0b1, // Period 2^21 * MCLK
+}eNAU88U10YG_ClockControl2_MCLK_SCLKEN;
+
+
+//// DAC Control Register (REG_DAC_CTRL)
+// Over Sample Rate
+typedef enum {
+    NAU88U10YG_DAC_CTRL_DACOS_64x = 0b0,
+    NAU88U10YG_DAC_CTRL_DACOS_128x = 0b1,
+}eNAU88U10YG_DAC_CTRL_DACOS;
+
+// Polarity Invert
+typedef enum {
+    NAU88U10YG_DAC_CTRL_DACPL_Normal = 0b0,
+    eNAU88U10YG_DAC_CTRL_DACPL_DAC_Output_invert = 0b1
+}eNAU88U10YG_DAC_CTRL_DACPL;
+
+// De-emphasis
+typedef enum {
+    NAU88U10YG_DAC_CTRL_DEEMP_No_deEmphasis = 0b00,
+    NAU88U10YG_DAC_CTRL_DEEMP_SMPLR_33KHz = 0b01,
+    NAU88U10YG_DAC_CTRL_DEEMP_SMPLR_44_1KHz = 0b10,
+    NAU88U10YG_DAC_CTRL_DEEMP_SMPLR_48KHz = 0b11,
+}eNAU88U10YG_DAC_CTRL_DEEMP;
+
+////  DAC Gain Control Register (REG_DAC_VOLUME)
+// DAC Gain (DACGAIN)
+// DAC Gain Range -127dB to 0dB @ 0.5 increments
+// 0x0 - Digital Mute
+
+//// ADC Control Register (REG_ADC_CTRL)
+// Audio or Application Mode
+typedef enum {
+    NAU88U10YG_ADC_CTRL_HPFAM_Audio = 0b0, // 1st order, fc ~ 3.7 Hz
+    NAU88U10YG_ADC_CTRL_HPFAM_Application = 0b1 //2 nd order, fc = HPF
+}eNAU88U10YG_ADC_CTRL_HPFAM;
+
+// Over Sample Rate
+typedef enum {
+    NAU88U10YG_ADC_CTRL_ADCOS_64x = 0b0, // Lowest power
+    NAU88U10YG_ADC_CTRL_ADCOS_128x = 0b1 // best SNR
+}eNAU88U10YG_ADC_CTRL_ADCOS;
+
+// High Pass Filter
+//HPF 12.3.7 ADC Control Register page 67
+
+// ADC Gain Control Register
+//0x0 - unused
+// ADC Gain Range -127dB to 0dB @ 0.5 increments
+
+/// INPUT, OUTPUT & MIXER CONTROL
+/// Output Register
+// MONO Output Boost Stage
+typedef enum {
+    NAU88U10YG_OUTPUT_CTRL_MOUTBST_x1_0VREF_GainBoost = 0b00, //(1.0 x VREF) Gain Boost
+    NAU88U10YG_OUTPUT_CTRL_MOUTBST_x1_5VREF_GainBoost = 0b01, //(1.5 x VREF) Gain Boost
+}eNAU88U10YG_OUTPUT_CTRL_MOUTBST;
+
+// Speaker Output Boost Stage
+typedef enum {
+    NAU88U10YG_OUTPUT_CTRL_SPKBST_x1_0VREF_GainBoost = 0b00, //(1.0 x VREF) Gain Boost
+    NAU88U10YG_OUTPUT_CTRL_SPKBST_x1_5VREF_GainBoost = 0b01, //(1.5 x VREF) Gain Boost
+}eNAU88U10YG_OUTPUT_CTRL_SPKBST;
+
+typedef enum {
+    NAU88U10YG_OUTPUT_CTRL_AOUTIMP_1kOm = 0b00, //~1kΩ
+    NAU88U10YG_OUTPUT_CTRL_AOUTIMP_30kOm = 0b01, //~30 kΩ
+}eNAU88U10YG_OUTPUT_CTRL_AOUTIMP;
+#endif //NAU88U10YG_ENUMS_H

Inc/nau88u10yg_regs.h

@@ -0,0 +1,86 @@
+//
+// Created by ilya on 09.01.24.
+//
+
+#ifndef NAU88U10YG_REGS_H
+#define NAU88U10YG_REGS_H
+
+//0b00110100
+
+#define NAU88U10YG_ADDRESS_READ 0x35
+#define NAU88U10YG_ADDRESS_WRITE 0x34
+#define NAU88U10YG_IO_TIMEOUT 0xFFFF
+
+//// Register Bits ////
+
+#define NAU88U10YG_REG_SOFTWARE_RESET 0x00
+// POWER MANAGEMENT //
+#define NAU88U10YG_REG_POWER_MANAGEMENT_1 0x01
+#define NAU88U10YG_REG_POWER_MANAGEMENT_2 0x02
+#define NAU88U10YG_REG_POWER_MANAGEMENT_3 0x03
+// AUDIO CONTROL //
+#define NAU88U10YG_REG_AUDIO_INTERFACE 0x04
+#define NAU88U10YG_REG_COMPANDING 0x05
+#define NAU88U10YG_REG_CLOCK_CONTROL_1 0x06
+#define NAU88U10YG_REG_CLOCK_CONTROL_2 0x07
+#define NAU88U10YG_REG_DAC_CTRL 0x0A
+#define NAU88U10YG_REG_DAC_VOLUME 0x0B
+#define NAU88U10YG_REG_ADC_CTRL 0x0E
+#define NAU88U10YG_REG_ADC_VOLUME 0x0F
+// EQUALISER //
+#define NAU88U10YG_REG_EQ1_LOW_CUTOFF 0x12
+#define NAU88U10YG_REG_EQ2_PEAK1 0x13
+#define NAU88U10YG_REG_EQ3_PEAK2 0x14
+#define NAU88U10YG_REG_EQ4_PEAK3 0x15
+#define NAU88U10YG_REG_EQ5_HIGH_CUTOFF 0x16
+// DIGITAL TO ANALOG (DAC) LIMITER //
+#define NAU88U10YG_REG_DAC_LIMITER1 0x17
+#define NAU88U10YG_REG_DAC_LIMITER2 0x18
+// NOTCH FILTER //
+#define NAU88U10YG_REG_NOTCH_FILTER_HIGH_1 0x1B
+#define NAU88U10YG_REG_NOTCH_FILTER_LOW_1 0x1C
+#define NAU88U10YG_REG_NOTCH_FILTER_HIGH_2 0x1D
+#define NAU88U10YG_REG_NOTCH_FILTER_LOW_2 0x1E
+// ALC CONTROL //
+#define NAU88U10YG_REG_ALC_CTRL_1 0x20
+#define NAU88U10YG_REG_ALC_CTRL_2 0x21
+#define NAU88U10YG_REG_ALC_CTRL_3 0x22
+#define NAU88U10YG_REG_NOISE_GATE 0x23
+// PLL CONTROL //
+#define NAU88U10YG_REG_PLL_N_CTRL 0x24
+#define NAU88U10YG_REG_PLL_K_1 0x25
+#define NAU88U10YG_REG_PLL_K_2 0x26
+#define NAU88U10YG_REG_PLL_K_3 0x27
+// INPUT, OUTPUT & MIXER CONTROL //
+#define NAU88U10YG_REG_ATTENUATION_CTRL 0x28
+#define NAU88U10YG_REG_INPUT_CTRL 0x2C
+#define NAU88U10YG_REG_PGA_GAIN 0x2D
+#define NAU88U10YG_REG_ADC_BOOST 0x2F
+#define NAU88U10YG_REG_OUTPUT_CTRL 0x31
+#define NAU88U10YG_REG_MIXER_CTRL 0x32
+#define NAU88U10YG_REG_SPKOUT_VOLUME 0x36
+#define NAU88U10YG_REG_MONO_MIXER_CONTROL 0x38
+// LOW POWER CONTROL //
+#define NAU88U10YG_REG_POWER_MANAGEMENT_4 0x3A
+// PCM TIME SLOT & ADCOUT IMPEDANCE OPTION CONTROL //
+#define NAU88U10YG_REG_POWER_TIME_SLOT 0x3B
+#define NAU88U10YG_REG_POWER_ADCOUT_DRIVE 0x3C
+// REGISTER ID //
+#define NAU88U10YG_REG_POWER_SILCON_REVISION 0x3E
+#define NAU88U10YG_REG_POWER_2WIRE_ID 0x3F
+#define NAU88U10YG_REG_POWER_ADDITIONAL_ID 0x40
+#define NAU88U10YG_REG_POWER_RESERVED 0x41
+#define NAU88U10YG_REG_POWER_HIGH_VOLTAGE_CTRL 0x45
+#define NAU88U10YG_REG_POWER_ALC_ENHANCEMENT_1 0x46
+#define NAU88U10YG_REG_POWER_ALC_ENHANCEMENT_2 0x47
+#define NAU88U10YG_REG_POWER_ADDITIONAL_IF_CTRL 0x49
+#define NAU88U10YG_REG_POWER_POWERTIEOFF_CTRL 0x4B
+#define NAU88U10YG_REG_AGC_P2P_DETECTOR 0x4C
+#define NAU88U10YG_REG_AGC_PEAK_DETECTOR 0x4D
+#define NAU88U10YG_REG_CONTROL_AND_STATUS 0x4E
+#define NAU88U10YG_REG_OUTPUT_TIEOFF_CTRL 0x4F
+
+
+
+
+#endif //NAU88U10YG_REGS_H

Src/nau88u10yg_audio_codec.c

@@ -0,0 +1,30 @@
+#include "nau88u10yg.h"
+
+
+bool xAudioCodecReadRegister(tI2cIO *i2c, uint16_t AdrRegQwery, uint16_t *DataRegResult) {
+    uint8_t pack = AdrRegQwery << 1 | 0b0 << 0;
+    uint8_t i2cPack[2]={0};
+    uint16_t data = 0;
+    I2cWrite(i2c, NAU88U10YG_ADDRESS_WRITE, &pack, 1, NAU88U10YG_IO_TIMEOUT);
+    uint16_t result = I2cRead(i2c, NAU88U10YG_ADDRESS_READ, (uint8_t *) &data, 2, NAU88U10YG_IO_TIMEOUT);
+    i2cPack[0] = data>>8;
+    i2cPack[1] = data;
+    *DataRegResult = (uint16_t)*i2cPack;
+    return result;
+}
+
+
+
+bool xAudioCodecWriteRegister(tI2cIO *i2c, NAU88U10YG_RegAddrPacket packet){
+    uint8_t i2cPack[2]={0};
+    i2cPack[0] = packet.raw>>8;
+    i2cPack[1] = packet.raw;
+    return I2cWrite(i2c,NAU88U10YG_ADDRESS_WRITE,i2cPack,2,NAU88U10YG_IO_TIMEOUT);
+}
+
+bool xAudioCodecWrite_Register8b_Data8b(tI2cIO *i2c, uint8_t reg, uint8_t data){
+    uint8_t i2cPack[2]={0};
+    i2cPack[0] = reg;
+    i2cPack[1] = data;
+    return I2cWrite(i2c,NAU88U10YG_ADDRESS_WRITE,i2cPack,2,NAU88U10YG_IO_TIMEOUT)==2;
+}

modular.json

@@ -0,0 +1,10 @@
+{
+  "cmake": {
+    "inc_dirs": [
+      "./Inc"
+    ],
+    "srcs": [
+      "./Src/**.c"
+    ]
+  }
+}