Добавлены интерфейсы и драйверы
This commit is contained in:
cfif
commit
30534e7bf7
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//
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// Created by cfif on 16.09.22.
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//
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#ifndef SERIALPORT_SERIALPORT_FLAHCHIP_H
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#define SERIALPORT_SERIALPORT_FLAHCHIP_H
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#include "SerialPort.h"
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#include "cmsis_os2.h"
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#include "stdbool.h"
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#include "interrupt_manager.h"
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#include "fc7xxx_driver_fcuart.h"
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#include "fc7xxx_driver_pcc.h"
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#include "fc7xxx_driver_port.h"
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#include "fc7xxx_driver_scg.h"
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#include "fc7xxx_driver_gpio.h"
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#include "fc7xxx_driver_dma.h"
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typedef struct {
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uint8_t UART_INDEX;
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DMA_ChannelType RX_DMA_CHANNEL;
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FCUART_Type *UART;
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uint32_t DMA_BUF_LEN;
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uint32_t UART_DMA_RECEIVED_LEN_BUF;
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uint8 s_SampleTmp[4];
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FCUART_DataType s_tFCUART_TxMsg;
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FCUART_InitType tInitCfg;
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FCUART_InterruptType tInterruptCfg;
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DMA_InitType dmaInitCfg;
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DMA_ChannelCfgType chnCfg;
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DMA_InterruptCfgType interruptCfg;
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osMessageQueueId_t txAccessQueue;
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osMessageQueueId_t rxDataQueue;
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osMessageQueueId_t rxDataSnifferQueue;
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osMessageQueueId_t rxDataSnifferSecondQueue;
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} tSerialPortFlagchip;
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void vSerialPortInitDMA(
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tSerialPortFlagchip *env,
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FCUART_Type *uart,
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PCC_ClkSrcType uartClock,
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uint32_t BoundRate,
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uint8 UART_INDEX, // UART0 = 0 ... UART7 = 7
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IRQn_Type IRQ_UART, // FCUART0_IRQn ... FCUART7_IRQn
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uint8 UART_PRIORITY,
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DMA_ChannelType RX_DMA_CHANNEL,
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DMA_RequestSourceType RX_DMA_CHANNEL_REQ,
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uint8_t *DMA_BUF,
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uint16_t DMA_BUF_LEN,
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IRQn_Type IRQ_DMA,
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uint8_t IRQ_DMA_PRIORITY,
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uint8_t IRQ_DMA_CHANNEL_PRIORITY,
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uint32_t rxBufferLength,
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uint32_t rxSnifferLength,
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DMA_TransferCompleteCallbackType pTransferCompleteNotify,
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DMA_TransferErrorCallbackType pTransferErrorNotify,
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FCUART_IdleInterrupt_CallBackType FCUART_IldeInterrupt_CallBack,
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FCUART_ErrorInterrupt_CallBackType FCUART_ErrorInterrupt_CallBack,
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FCUART_TxRxInterrupt_CallBackType FCUART_TxEmptyInterrupt_CallBack,
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FCUART_TxRxInterrupt_CallBackType FCUART_TxCompleteInterrupt_CallBack
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);
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tSerialPortIO vSerialPortGetIo(tSerialPortFlagchip *env);
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void SerialPort_RxDmaBufToQueue(tSerialPortFlagchip *env, const void *pSrcBuffer);
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/*
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#define vSerialPortInitDMAName(ENV, NAME, DMA, RX_DMA_CHANNEL, RX_DMA_CHANNEL_MUX, RX_DMAMUX_DMAREQ_ID, RX_DMA_Channel_IRQ, RX_DMA_FDT_FLAG, DMA_BUF, DMA_BUF_LEN, TX_DMA_CHANNEL, TX_DMA_CHANNEL_MUX, TX_DMAMUX_DMAREQ_ID, TX_DMA_Channel_IRQ, TX_DMA_FDT_FLAG, SWAP, BOUND_RATE, PRIORITY, LEN) \
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vSerialPortInitDMA(ENV, NAME, DMA, RX_DMA_CHANNEL, RX_DMA_CHANNEL_MUX, RX_DMAMUX_DMAREQ_ID, RX_DMA_Channel_IRQ, RX_DMA_FDT_FLAG, DMA_BUF, DMA_BUF_LEN, TX_DMA_CHANNEL, TX_DMA_CHANNEL_MUX, TX_DMAMUX_DMAREQ_ID, TX_DMA_Channel_IRQ, TX_DMA_FDT_FLAG, SWAP, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, PRIORITY, LEN, 0)
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#define vSerialPortInitDMANameWithSniffer(ENV, NAME, DMA, RX_DMA_CHANNEL, RX_DMA_CHANNEL_MUX, RX_DMAMUX_DMAREQ_ID, RX_DMA_Channel_IRQ, RX_DMA_FDT_FLAG, DMA_BUF, DMA_BUF_LEN, TX_DMA_CHANNEL, TX_DMA_CHANNEL_MUX, TX_DMAMUX_DMAREQ_ID, TX_DMA_Channel_IRQ, TX_DMA_FDT_FLAG, SWAP, BOUND_RATE, PRIORITY, LEN, SNIFFER_LEN) \
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vSerialPortInitDMA(ENV, NAME, DMA, RX_DMA_CHANNEL, RX_DMA_CHANNEL_MUX, RX_DMAMUX_DMAREQ_ID, RX_DMA_Channel_IRQ, RX_DMA_FDT_FLAG, DMA_BUF, DMA_BUF_LEN, TX_DMA_CHANNEL, TX_DMA_CHANNEL_MUX, TX_DMAMUX_DMAREQ_ID, TX_DMA_Channel_IRQ, TX_DMA_FDT_FLAG, SWAP, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, PRIORITY, LEN, SNIFFER_LEN)
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#define DMANONE_CHANNELNONE NULL
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#define DMANONE NULL
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#define DMANONEMUX_CHANNELNONE NULL
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#define DMANONE_FDTNONE_FLAG (uint32_t)0
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#define DMANONE_ChannelNONE_IRQn (IRQn_Type)0
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#define vSerialPortInitDmaWithNameAndSniffer(\
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ENV, NAME, BOUND_RATE, \
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RX_DMA, RX_CH, \
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TX_DMA, TX_CH, \
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SWAP, PRIORITY, \
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RX_DMA_BUF, RX_DMA_BUF_LEN, \
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QUEUE_LEN, SNIFFER_LEN \
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) \
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vSerialPortInitDMA(\
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ENV, NAME, DMA##RX_DMA, DMA##TX_DMA, \
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DMA##RX_DMA##_CHANNEL##RX_CH, DMA##RX_DMA##MUX_CHANNEL##RX_CH, DMAMUX_DMAREQ_ID_##NAME##_RX, DMA##RX_DMA##_Channel##RX_CH##_IRQn, DMA##RX_DMA##_FDT##RX_CH##_FLAG,\
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RX_DMA_BUF, RX_DMA_BUF_LEN, \
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DMA##TX_DMA##_CHANNEL##TX_CH, DMA##TX_DMA##MUX_CHANNEL##TX_CH, DMAMUX_DMAREQ_ID_##NAME##_TX, DMA##TX_DMA##_Channel##TX_CH##_IRQn, DMA##TX_DMA##_FDT##TX_CH##_FLAG,\
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SWAP, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, \
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PRIORITY, QUEUE_LEN, SNIFFER_LEN\
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)
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#define vSerialPortInitDmaExtWithNameAndSniffer(\
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ENV, NAME, BOUND_RATE, \
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RX_DMA, RX_CH, \
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TX_DMA, TX_CH, \
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SWAP, FLOW, PRIORITY, \
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RX_DMA_BUF, RX_DMA_BUF_LEN, \
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QUEUE_LEN, SNIFFER_LEN \
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) \
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vSerialPortInitDMAExt(\
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ENV, NAME, DMA##RX_DMA, DMA##TX_DMA, \
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DMA##RX_DMA##_CHANNEL##RX_CH, DMA##RX_DMA##MUX_CHANNEL##RX_CH, DMAMUX_DMAREQ_ID_##NAME##_RX, DMA##RX_DMA##_Channel##RX_CH##_IRQn, DMA##RX_DMA##_FDT##RX_CH##_FLAG,\
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RX_DMA_BUF, RX_DMA_BUF_LEN, \
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DMA##TX_DMA##_CHANNEL##TX_CH, DMA##TX_DMA##MUX_CHANNEL##TX_CH, DMAMUX_DMAREQ_ID_##NAME##_TX, DMA##TX_DMA##_Channel##TX_CH##_IRQn, DMA##TX_DMA##_FDT##TX_CH##_FLAG,\
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SWAP, FLOW, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, \
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PRIORITY, QUEUE_LEN, SNIFFER_LEN\
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)
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#define vSerialPortInitName(ENV, NAME, SWAP, BOUND_RATE, PRIORITY, LEN) \
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vSerialPortInit(ENV, NAME, SWAP, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, PRIORITY, LEN, 0)
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#define vSerialPortExtInitName(ENV, NAME, SWAP, FLOW, BOUND_RATE, PRIORITY, LEN) \
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vSerialPortInit(ENV, NAME, SWAP, FLOW, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, PRIORITY, LEN, 0)
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#define vSerialPortInitNameWithSniffer(ENV, NAME, SWAP, BOUND_RATE, PRIORITY, LEN, SNIFFER_LEN) \
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vSerialPortInit(ENV, NAME, SWAP, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, PRIORITY, LEN, SNIFFER_LEN)
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#define vSerialPortExtInitNameWithSniffer(ENV, NAME, SWAP, FLOW, BOUND_RATE, PRIORITY, LEN, SNIFFER_LEN) \
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vSerialPortInit(ENV, NAME, SWAP, FLOW, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, PRIORITY, LEN, SNIFFER_LEN)
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void vSerialPortIrqProcessing(tSerialPortArtery *env);
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void vSerialPortIrqProcessingDMA(tSerialPortArtery *env);
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//void vSerialPortIrqProcessingDMAloop(tSerialPortArtery *env, uint32_t len);
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void SerialPort_IrqProcessing_UartIdle(tSerialPortArtery *env);
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void SerialPort_IrqProcessing_DmaRxLoop(tSerialPortArtery *env);
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void SerialPort_IrqProcessingFilter_UartIdle(tSerialPortArtery *env, tSerialPortIO *virtualPort, uint16_t *counterBufFilterStr, uint8_t *bufStrFilter, uint16_t maxBufStrFilter, const char *FilterStr[], uint8_t countFiler);
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void SerialPort_IrqProcessingFilter_DmaRxLoop(tSerialPortArtery *env, tSerialPortIO *virtualPort, uint16_t *counterBufFilterStr, uint8_t *bufStrFilter, uint16_t maxBufStrFilter, const char *FilterStr[], uint8_t countFiler);
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void SerialPort_IrqProcessing_DmaTx(tSerialPortArtery *env);
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tSerialPortIO vSerialPortGetIo(tSerialPortArtery *env);
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tSerialPortIO vSerialPortGetSnifferIo(tSerialPortArtery *env);
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tSerialPortIO SerialPort_GetSnifferSecondIo(tSerialPortArtery *env);
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uint16_t vSerialPortTransmit(tSerialPortArtery *env, uint8_t *data, uint16_t size, uint32_t timeout);
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uint16_t vSerialPortBlindTransmit(tSerialPortArtery *env, uint8_t *data, uint16_t size, uint32_t timeout);
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void SerialPort_IrqProcessing_DmaTxBlind(tSerialPortArtery *env);
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*/
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#endif //SERIALPORT_SERIALPORT_FLAHCHIP_H
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@ -0,0 +1,286 @@
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//
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// Created by cfif on 16.09.22.
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//
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#include <SystemDelayInterface.h>
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#include "SerialPortFlagchip.h"
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#include "string.h"
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void vSerialPortInitDMA(
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tSerialPortFlagchip *env,
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FCUART_Type *uart,
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PCC_ClkSrcType uartClock,
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uint32_t BoundRate,
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uint8 UART_INDEX, // UART0 = 0 ... UART7 = 7
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IRQn_Type IRQ_UART, // FCUART0_IRQn ... FCUART7_IRQn
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uint8 UART_PRIORITY,
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DMA_ChannelType RX_DMA_CHANNEL,
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DMA_RequestSourceType RX_DMA_CHANNEL_REQ,
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uint8_t *DMA_BUF,
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uint16_t DMA_BUF_LEN,
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IRQn_Type IRQ_DMA,
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uint8_t IRQ_DMA_PRIORITY,
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uint8_t IRQ_DMA_CHANNEL_PRIORITY,
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uint32_t rxBufferLength,
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uint32_t rxSnifferLength,
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DMA_TransferCompleteCallbackType pTransferCompleteNotify,
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DMA_TransferErrorCallbackType pTransferErrorNotify,
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FCUART_IdleInterrupt_CallBackType FCUART_IldeInterrupt_CallBack,
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FCUART_ErrorInterrupt_CallBackType FCUART_ErrorInterrupt_CallBack,
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FCUART_TxRxInterrupt_CallBackType FCUART_TxEmptyInterrupt_CallBack,
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FCUART_TxRxInterrupt_CallBackType FCUART_TxCompleteInterrupt_CallBack
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) {
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env->UART_INDEX = UART_INDEX;
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env->RX_DMA_CHANNEL = RX_DMA_CHANNEL;
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env->UART = uart;
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env->DMA_BUF_LEN = DMA_BUF_LEN;
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env->UART_DMA_RECEIVED_LEN_BUF = 0;
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env->txAccessQueue = osMessageQueueNew(1, 1, NULL);
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env->rxDataQueue = osMessageQueueNew(rxBufferLength, 1, NULL);
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if (rxSnifferLength) {
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env->rxDataSnifferQueue = osMessageQueueNew(rxSnifferLength, 1, NULL);
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} else {
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env->rxDataSnifferQueue = 0;
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}
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FCUART_InitMemory(UART_INDEX);
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PCC_CtrlType bSP_PCC_Config;
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bSP_PCC_Config.eClockName = uartClock;
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bSP_PCC_Config.bEn = true;
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bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV;
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bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED;
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PCC_SetPcc(&bSP_PCC_Config);
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env->dmaInitCfg.eArbitrationAlgorithm = DMA_ARBITRATION_ALGORITHM_FIXED_PRIORITY;
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env->dmaInitCfg.bHaltOnError = false;
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DMA_Init(DMA_INSTANCE_0, &env->dmaInitCfg);
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env->chnCfg.pSrcBuffer = &(uart->DATA);
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env->chnCfg.pDestBuffer = DMA_BUF;
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env->chnCfg.u32BlockSize = 1U;
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env->chnCfg.u16BlockCount = 1U;
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env->chnCfg.u8ChannelPriority = IRQ_DMA_CHANNEL_PRIORITY;
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env->chnCfg.eSrcDataSize = DMA_TRANSFER_SIZE_1B;
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env->chnCfg.eDestDataSize = DMA_TRANSFER_SIZE_1B;
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env->chnCfg.eSrcIncMode = DMA_INCREMENT_DISABLE;
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env->chnCfg.eDestIncMode = DMA_INCREMENT_DATA_SIZE;
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env->chnCfg.bSrcBlockOffsetEn = false;
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env->chnCfg.bDestBlockOffsetEn = false;
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env->chnCfg.s32BlockOffset = 0;
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env->chnCfg.bSrcAddrLoopbackEn = false;
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env->chnCfg.bDestAddrLoopbackEn = false;
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env->chnCfg.bAutoStop = false;
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env->chnCfg.bSrcCircularBufferEn = false;
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env->chnCfg.u32SrcCircBufferSize = 0U;
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env->chnCfg.bDestCircularBufferEn = false;
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env->chnCfg.u32DestCircBufferSize = 0U;
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env->chnCfg.eTriggerSrc = RX_DMA_CHANNEL_REQ;
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DMA_InitChannel(DMA_INSTANCE_0, RX_DMA_CHANNEL, &env->chnCfg);
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env->interruptCfg.bTransferCompleteIntEn = true;
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env->interruptCfg.pTransferCompleteNotify = pTransferCompleteNotify;
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env->interruptCfg.bTransferErrorIntEn = true;
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env->interruptCfg.pTransferErrorNotify = pTransferErrorNotify;
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DMA_InitChannelInterrupt(DMA_INSTANCE_0, RX_DMA_CHANNEL, &env->interruptCfg);
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DMA_StartChannel(DMA_INSTANCE_0, RX_DMA_CHANNEL);
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NVIC_SetPriority(IRQ_DMA, IRQ_DMA_PRIORITY);
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NVIC_EnableIRQ(IRQ_DMA);
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FCUART_ErrorType tRetVal;
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uint32_t u32PccFuncClk;
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u32PccFuncClk = PCC_GetPccFunctionClock(uartClock);
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if (u32PccFuncClk != 0U) {
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env->tInitCfg.bEnRxFullDma = true; // UART receiver full DMA disable
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env->tInitCfg.bEnRxFifo = false; // UART fifo disable
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env->tInitCfg.bEnTxFifo = true; // UART tx fifo enable
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env->tInitCfg.u8TxFifoWaterMark = 0U; // UART tx fifo 16 bytes trigger
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env->tInitCfg.eIdleCharNum = FCUART_IDLE_CHARCTER_64; // UART idle character number 64
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env->tInitCfg.eIdleStart = FCUART_START_AFTER_STOPBIT; // UART idle character type
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env->tInitCfg.u32Baudrate = BoundRate; // UART baud-rate
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env->tInitCfg.eBitMode = UART_BITMODE_8; // UART bit mode
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env->tInitCfg.bParityEnable = false; // UART parity check enable
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env->tInitCfg.eStopBit = UART_STOPBIT_NUM_1; // UART stop bit number
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env->tInitCfg.u32ClkSrcHz = u32PccFuncClk; // UART function clock
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env->tInitCfg.u32TransmitTimeout = 0xFFFFFFFFU; // Transmit timeout tick
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// start initial UART
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tRetVal = FCUART_Init(UART_INDEX, &env->tInitCfg);
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if (tRetVal == FCUART_ERROR_OK) {
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env->s_tFCUART_TxMsg.pDatas = (uint8_t *) env->s_SampleTmp; // data buffer must set an array address
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env->s_tFCUART_TxMsg.u32DataLen = 0;
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env->tInterruptCfg.pTxBuf = &env->s_tFCUART_TxMsg;
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env->tInterruptCfg.bEnIdleInterrupt = true;
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env->tInterruptCfg.pIdleNotify = FCUART_IldeInterrupt_CallBack;
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env->tInterruptCfg.bEnErrorInterrupt = true;
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env->tInterruptCfg.pErrorNotify = FCUART_ErrorInterrupt_CallBack;
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env->tInterruptCfg.bEnRxInterrupt = false;
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env->tInterruptCfg.pRxNotify = NULL;
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env->tInterruptCfg.bEnTxInterrupt = true;
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env->tInterruptCfg.pTxEmptyNotify = FCUART_TxEmptyInterrupt_CallBack;
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env->tInterruptCfg.pTxCompleteNotify = FCUART_TxCompleteInterrupt_CallBack;
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tRetVal = FCUART_SetInterrupt(UART_INDEX, &env->tInterruptCfg);
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NVIC_SetPriority(IRQ_UART, UART_PRIORITY);
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NVIC_EnableIRQ(IRQ_UART);
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tRetVal = FCUART_StartReceive(UART_INDEX);
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}
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}
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}
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static uint16_t vSerialPortReceiveQueue(tSerialPortFlagchip *env, uint8_t *data, uint16_t size, uint32_t timeout,
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osMessageQueueId_t queueId) {
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PROCESS_UNUSED_VAR(env)
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uint16_t received = 0;
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if (timeout) {
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uint32_t endMs = SystemGetMs() + timeout;
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uint32_t leftMs;
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while (size && ((timeout == SystemWaitForever) || (endMs > SystemGetMs()))) {
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leftMs = endMs - SystemGetMs();
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if (osMessageQueueGet(queueId, data, NULL, leftMs) == osOK) {
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--size;
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++received;
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++data;
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}
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}
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} else {
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while (size) {
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if (osMessageQueueGet(queueId, data, NULL, 0) == osOK) {
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--size;
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++received;
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++data;
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} else {
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return received;
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}
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}
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}
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return received;
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}
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static uint16_t vSerialPortReceive(tSerialPortFlagchip *env, uint8_t *data, uint16_t size, uint32_t timeout) {
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return vSerialPortReceiveQueue(env, data, size, timeout, env->rxDataQueue);
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}
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static uint16_t vSerialPortReceiveSniffer(tSerialPortFlagchip *env, uint8_t *data, uint16_t size, uint32_t timeout) {
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return env->rxDataSnifferQueue
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? vSerialPortReceiveQueue(env, data, size, timeout, env->rxDataSnifferQueue)
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: 0;
|
||||
}
|
||||
|
||||
static uint16_t
|
||||
vSerialPortReceiveSnifferSecond(tSerialPortFlagchip *env, uint8_t *data, uint16_t size, uint32_t timeout) {
|
||||
|
||||
return env->rxDataSnifferSecondQueue
|
||||
? vSerialPortReceiveQueue(env, data, size, timeout, env->rxDataSnifferSecondQueue)
|
||||
: 0;
|
||||
}
|
||||
|
||||
|
||||
static uint16_t
|
||||
vSerialPortTransmitOverCore(tSerialPortFlagchip *env, uint8_t *data, uint16_t size, uint32_t timeout) {
|
||||
|
||||
uint16_t sent = 0;
|
||||
|
||||
FCUART_ErrorType tRetVal;
|
||||
|
||||
tRetVal = FCUART_AssignTxInterruptData(env->UART_INDEX, (uint8 *) data, size);
|
||||
|
||||
tRetVal = FCUART_StartTransmit(env->UART_INDEX);
|
||||
|
||||
PROCESS_UNUSED_VAR(tRetVal)
|
||||
|
||||
uint8_t res;
|
||||
|
||||
sent = (osMessageQueueGet(env->txAccessQueue, &res, 0, timeout) == osOK) ? size : 0;
|
||||
|
||||
return sent;
|
||||
}
|
||||
|
||||
void SerialPort_RxDmaBufToQueue(tSerialPortFlagchip *env, const void *pSrcBuffer) {
|
||||
|
||||
for (uint32_t i = 0; i < env->UART_DMA_RECEIVED_LEN_BUF; ++i) {
|
||||
osMessageQueuePut(env->rxDataQueue, &((uint8 *)pSrcBuffer)[i], 0x0, 0U);
|
||||
if (env->rxDataSnifferQueue) {
|
||||
osMessageQueuePut(env->rxDataSnifferQueue, &((uint8 *)pSrcBuffer)[i], 0x0, 0U);
|
||||
}
|
||||
}
|
||||
|
||||
env->UART_DMA_RECEIVED_LEN_BUF = 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
static SerialPortIOTransaction vSerialPortTransmitterGet(tSerialPortFlagchip *env) {
|
||||
|
||||
PROCESS_UNUSED_VAR(env)
|
||||
|
||||
return (SerialPortIOTransaction) vSerialPortTransmitOverCore;
|
||||
|
||||
}
|
||||
|
||||
tSerialPortIO vSerialPortGetIo(tSerialPortFlagchip *env) {
|
||||
tSerialPortIO io = {
|
||||
.env = env,
|
||||
.receive = (SerialPortIOTransaction) vSerialPortReceive,
|
||||
.transmit = vSerialPortTransmitterGet(env)
|
||||
};
|
||||
return io;
|
||||
}
|
||||
|
||||
tSerialPortIO vSerialPortGetSnifferIo(tSerialPortFlagchip *env) {
|
||||
tSerialPortIO io = {
|
||||
.env = env,
|
||||
.receive = (SerialPortIOTransaction) vSerialPortReceiveSniffer,
|
||||
.transmit = vSerialPortTransmitterGet(env)
|
||||
};
|
||||
return io;
|
||||
}
|
||||
|
||||
tSerialPortIO SerialPort_GetSnifferSecondIo(tSerialPortFlagchip *env) {
|
||||
tSerialPortIO io = {
|
||||
.env = env,
|
||||
.receive = (SerialPortIOTransaction) vSerialPortReceiveSnifferSecond,
|
||||
.transmit = vSerialPortTransmitterGet(env)
|
||||
};
|
||||
return io;
|
||||
}
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
{
|
||||
"dep": [
|
||||
{
|
||||
"type": "git",
|
||||
"provider": "HVAC_M7",
|
||||
"repo": "SerialPort"
|
||||
},
|
||||
{
|
||||
"type": "git",
|
||||
"provider": "HVAC_M7",
|
||||
"repo": "SystemDelayInterface"
|
||||
}
|
||||
],
|
||||
"cmake": {
|
||||
"inc_dirs": [
|
||||
"Inc"
|
||||
],
|
||||
"srcs": [
|
||||
"Src/**.c"
|
||||
]
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue