From 9f2871bdb1327b89c606b044a481c496ba91dbbf Mon Sep 17 00:00:00 2001 From: cfif Date: Mon, 13 Oct 2025 10:12:50 +0300 Subject: [PATCH] =?UTF-8?q?=D0=9E=D0=B1=D0=BD=D0=BE=D0=B2=D0=BB=D0=B5?= =?UTF-8?q?=D0=BD=D0=B8=D0=B5?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Inc/PwmFlagchip.h | 25 +++++++++++++++ Src/PwmFlagchip.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++ modular.json | 10 ++++++ 3 files changed, 117 insertions(+) create mode 100644 Inc/PwmFlagchip.h create mode 100644 Src/PwmFlagchip.c create mode 100644 modular.json diff --git a/Inc/PwmFlagchip.h b/Inc/PwmFlagchip.h new file mode 100644 index 0000000..86bc570 --- /dev/null +++ b/Inc/PwmFlagchip.h @@ -0,0 +1,25 @@ +// +// Created by cfif on 17.11.22. +// + +#ifndef PWM_FLAGCHIP_H +#define PWM_FLAGCHIP_H + +#include "PwmIO.h" +#include "cmsis_os2.h" +#include "fc7xxx_driver_tpu.h" +#include "interrupt_manager.h" + +typedef struct { + + TPU_InterruptCfgType etpu_Int_config_tbl; + TPU_PwmCfgType etpu_pwmconfig_tbl; + + uint8_t TPU_PWM_CHANNEL; + +} tPwmFlagchip; + + +tPwmIO vPwmGetIo(tPwmFlagchip *env); + +#endif //PWM_FLAGCHIP_H diff --git a/Src/PwmFlagchip.c b/Src/PwmFlagchip.c new file mode 100644 index 0000000..7a93f13 --- /dev/null +++ b/Src/PwmFlagchip.c @@ -0,0 +1,82 @@ +// +// Created by cfif on 07.09.22. +// +#include +#include "PwmFlagchip.h" + +void Set_Tpu_PwmCallback(tPwmFlagchip *env) { + TPU_PwmServiceReq(env->TPU_PWM_CHANNEL, env->etpu_pwmconfig_tbl.u32ActiveTime, + env->etpu_pwmconfig_tbl.u32PeriodTime); +} + +tPwmFlagchip PWM_Initial( + uint32_t PeriodTime, + uint32_t ActiveTime, + uint8_t TPU_PWM_CHANNEL, + uint8 TPU0_CH_PRIORITY, + TPU_EventCallbackType Bsp_Tpu_PwmCallback, + TPU_TCR1OverflowCallbackType Bsp_Tpu_OverflowCallBack) { + + + tPwmFlagchip pwm = { + + .etpu_pwmconfig_tbl = { + .eTBS1 = TPUE_EQUAL_ONLY_CAPBASE_TCR1_MATCHBASE_TCR1, + .eTBS2 = TPUE_EQUAL_ONLY_CAPBASE_TCR1_MATCHBASE_TCR1, + .bPwmUseTCR1 = (bool) true, + .bPwmUseTCR2 = (bool) false, + .u32ActiveTime = ActiveTime, + .u32PeriodTime = PeriodTime, + .bActiveHigh = (bool) true + }, + + .etpu_Int_config_tbl = { + .bEventIntEn = (bool) true, + .bTCR1OverFlowEventIntEn = (bool) true, + .bTCR2OverFlowEventIntEn = (bool) false, + .pEventNotify = Bsp_Tpu_PwmCallback, + .pHSANotify = NULL, + .pTCR1OverflowNotify = Bsp_Tpu_OverflowCallBack, + .pTCR2OverflowNotify = NULL, + .eChTrigType = TPUH_ANY_EVENT_GATED_BY_MSRTSR + }, + + .TPU_PWM_CHANNEL = TPU_PWM_CHANNEL + + + }; + + TPU_DeInit(); + TPU_Init(); + TPU_PwmModeInit(TPU_PWM_CHANNEL, &pwm.etpu_pwmconfig_tbl); + TPU_InitChannelInterrupt(TPU_PWM_CHANNEL, &pwm.etpu_Int_config_tbl); + + NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUP_4); + + if (TPU_PWM_CHANNEL <= 7) { + NVIC_EnableIRQ(TPU0_CH0_7_IRQn); + NVIC_SetPriority(TPU0_CH0_7_IRQn, TPU0_CH_PRIORITY); + } else if (TPU_PWM_CHANNEL <= 15) { + NVIC_EnableIRQ(TPU0_CH8_15_IRQn); + NVIC_SetPriority(TPU0_CH8_15_IRQn, TPU0_CH_PRIORITY); + } else if (TPU_PWM_CHANNEL <= 23) { + NVIC_EnableIRQ(TPU0_CH16_23_IRQn); + NVIC_SetPriority(TPU0_CH16_23_IRQn, TPU0_CH_PRIORITY); + } else if (TPU_PWM_CHANNEL <= 31) { + NVIC_EnableIRQ(TPU0_CH24_31_IRQn); + NVIC_SetPriority(TPU0_CH24_31_IRQn, TPU0_CH_PRIORITY); + } + return pwm; +} + +static void vPwmRun(tPwmFlagchip *env) { + TPU_StartChannel(); +} + +tPwmIO vPwmGetIo(tPwmFlagchip *env) { + tPwmIO io = { + .env = env, + .run = (PwmIOTransaction) vPwmRun, + }; + return io; +} \ No newline at end of file diff --git a/modular.json b/modular.json new file mode 100644 index 0000000..71971cd --- /dev/null +++ b/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file