453 lines
16 KiB
C
453 lines
16 KiB
C
/**
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* @file module_driver_smc.h
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* @author Flagchip
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* @brief SMC driver type definition and API
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* @version 2.0.0
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* @date 2024-08-20
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*
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* SDK Version: 2.6.0
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*
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* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
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*
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* @details
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2023-12-15 Flagchip085 N/A First version for FC7300
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* 2.0.0 2024-10-12 Flagchip085 N/A Change version and release
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******************************************************************************** */
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#ifndef _DRIVER_MODULE_DRIVER_SMC_H_
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#define _DRIVER_MODULE_DRIVER_SMC_H_
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#include "HwA_smc.h"
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#if SMC_INSTANCE_COUNT > 0U
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#include "HwA_pmc.h"
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#include "HwA_cm7.h"
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/**
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* @addtogroup module_driver_smc
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* @{
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*/
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/********* Dev Error Report ************/
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#ifndef SMC_DEV_ERROR_REPORT
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#define SMC_DEV_ERROR_REPORT STD_OFF
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#endif
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#if SMC_DEV_ERROR_REPORT == STD_ON
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#define SMC_ReportDevError(func, error) ReportDevError(SMC_MODULE_ID, func, error)
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#endif
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/**
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* @name SMC API Service IDs
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* @{
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*/
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#define SMC_SET_CLOCK_OUT_ID 0x00U
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#define SMC_SET_AONCLKSRC_ID 0x01U
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#define SMC_GET_CLOCK_FREQ_ID 0x02U
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/** @}*/
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/**
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* @name SMC Dev Error Code
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* @brief Error Code of calling SMC apis
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* @{
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*/
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#define SMC_E_PARAM_POINTER 0x01U
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#define SMC_E_PARAM_OUT_RANGE 0x02U
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/** @}*/
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/********* Local defines ************/
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#define SMC_AONCLK_128K 128000U
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#define SMC_AONCLK_32K 32000U
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#define SMC_AONCLK_SOSC_32K 32768U
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#define SMC_AONCLK_1K 1000U
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#define LP_WAKEUP_PAD_NUM 5U
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#define SMC_TSTMP0_DUMMY_CYCLES_1M 4800U /* 4 * 4 Source Clock Cycle = 4 * 4 * 300M/1M */
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#define SMC_TSTMP0_DUMMY_CYCLES_32K 150000U /* 4 * 4 Source Clock Cycle = 4 * 4 * 300M/32K */
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#define SMC_TSTMP0_DUMMY_CYCLES_250K 19200U /* 4 * 4 Source Clock Cycle = 4 * 4 * 300M/250K */
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/** @brief Smc return type. */
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typedef enum
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{
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SMC_STATUS_SUCCESS = 0U,
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SMC_STATUS_PARAM_INVALID = 1U
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} SMC_StatusType;
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/** @brief Smc mode */
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typedef enum
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{
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SMC_MODE_RUN = 0U, /**< The MCU can run at full speed and the internal supply is fully regulated, that is, in run regulation */
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SMC_MODE_STOP, /**< Core enters sleep mode and no other clock is gated. Only the core clock is gated. */
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SMC_MODE_WAIT, /**< Both core and bus clocks are gated off. */
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SMC_MODE_STANBY_0, /**< All clocks except some low-power clocks can keep on are gated off and the PD1 domain is powered off. please refer to reference manual for detail about standby mode 0. */
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SMC_MODE_STANBY_1, /**< All clocks except some low-power clocks can keep on are gated off and the PD1 domain is powered off. please refer to reference manual for detail about standby mode 1. */
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SMC_MODE_STANBY_2, /**< All clocks except some low-power clocks can keep on are gated off and the PD1 domain is powered off. please refer to reference manual for detail about standby mode 2. */
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SMC_MODE_STANBY_3 /**< All clocks except some low-power clocks can keep on are gated off and the PD1 domain is powered off. please refer to reference manual for detail about standby mode 3. */
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} SMC_ModeType;
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#if SMC_CLOCKCONFIG_SUPPORT
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/**
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* @brief SMC clock source type for clock infomation querry
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*
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*/
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typedef enum
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{
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SMC_AON32K_CLK = 0U, /*!< AON32K_CLK */
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SMC_RTC_CLK = 1U, /*!< RTC_CLK */
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SMC_AON_CLK = 2U, /*!< AON_CLK */
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SMC_CLKOUT_CLK = 3U, /*!< CLKOUT_CLK */
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SMC_END_OF_CLOCKS = 4U /*!< End of SMC clocks */
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} SMC_ClkSrcType;
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/**
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* @brief Data type for register SMC_CLKOUT_CTRL,mainly focus on CLKOUT setting
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*
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*/
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typedef struct
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{
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bool bEnable; /*!< SMC ClockOut enable */
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SMC_ClockOutSrcType eClkOutSrc; /*!< SMC ClockOut source select */
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SMC_ClockOutDivType eDivider; /*!< SMC ClockOut divide ratio */
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} SMC_ClkoutType;
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/**
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* @brief SMC_AONCLKSR clock source info
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*
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*/
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typedef struct
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{
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SMC_AON32KClkSrcType eAon32KSel; /*!< SMC 32 KHz Always-on Clock Source Select */
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SMC_RTCClkSrcType eRtcSel; /*!< SMC RTC Clock Source Select */
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SMC_AONClkSrcType eAonSel; /*!< SMC AON Clock Source Select */
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} SMC_AONCLKSRType;
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/**
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* @brief LP WakeUp Pad source
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*/
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typedef enum
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{
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SMC_LPWAKEUP_PAD_DISABLE = 0U, /*!< Disable */
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SMC_LPWAKEUP_PAD_AONTIMER_TRIGGER = 1U, /*!< AONTIMER Trigger */
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SMC_LPWAKEUP_PAD_RTC_ALARM = 2U, /*!< RTC Alarm(Interrupt) */
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#if SMC_CMP0_LPWAKEUP_SUPPORT
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SMC_LPWAKEUP_PAD_CMP0_OUTPUT = 3U, /*!< CMP0 Output */
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#endif /* SMC_CMP0_LPWAKEUP_SUPPORT */
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#if SMC_ADC2_LPWAKEUP_SUPPORT
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SMC_LPWAKEUP_PAD_ADC1_CMP = 4U, /*!< ADC1 CMP */
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SMC_LPWAKEUP_PAD_ADC2_CMP = 5U, /*!< ADC2 CMP */
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#else
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SMC_LPWAKEUP_PAD_ADC0_CMP = 4U, /*!< ADC0 CMP */
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SMC_LPWAKEUP_PAD_ADC1_CMP = 5U, /*!< ADC1 CMP */
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#endif /* SMC_ADC2_LPWAKEUP_SUPPORT */
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SMC_LPWAKEUP_PAD_PMC_RPM_ENTRY = 6U, /*!< PMC RPM Entry */
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SMC_LPWAKEUP_PAD_WKU_INTERRUPT = 7U, /*!< WKU Interrupt */
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SMC_LPWAKEUP_PAD_TSTMP0_PWM_TRIGGER0 = 8U, /*!< TSTMP0 PWM TRIGGER0, use modulate 0 as posedge, modulate 1 as negedge */
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SMC_LPWAKEUP_PAD_TSTMP0_PWM_TRIGGER1 = 9U, /*!< TSTMP0 PWM TRIGGER1, use modulate 2 as posedge, modulate 3 as negedge */
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SMC_LPWAKEUP_PAD_TSTMP0_CH0_TRIGGER = 10U, /*!< TSTMP0 CH0 TRIGGER */
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SMC_LPWAKEUP_PAD_TSTMP0_CH1_TRIGGER = 11U, /*!< TSTMP0 CH1 TRIGGER */
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SMC_LPWAKEUP_PAD_PMC_V11_EN = 12U /*!< PMC V11 EN */
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} SMC_LPWakeUpPadSrcType;
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/**
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* @brief LP WakeUp Pad polarity select
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*/
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typedef enum
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{
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SMC_LPWAKEUP_PADPOL_KEEP = 0U, /*!< Keep the LP_WAKEUP CFGx */
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SMC_LPWAKEUP_PADPOL_INVERT /*!< Invert the LP_WAKEUP CFGx */
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} SMC_LPWakeUpPadPolType;
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/**
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* @brief data type for register SMC_AONCLKSEL
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*/
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typedef struct
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{
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uint8_t u8LPWakeUpPadNum; /*!< SMC LP WakeUp Pad number */
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SMC_LPWakeUpPadSrcType eLpWakeUpPadSel; /*!< SMC LP WakeUp Pad source select */
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SMC_LPWakeUpPadPolType eLpWakeUpPadPolSel; /*!< SMC LP WakeUp Pad polarity select */
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} SMC_LPWakeUpPadType;
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#if SMC_SRAM2_RENTENTION_MODE_SUPPORT
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/**
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* @brief SRAM2 block retention control
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*/
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typedef enum
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{
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SMC_SRAM2_RETENTION_DISABLE = 0, /*!< SRAM2 Block Retention 32KB */
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SMC_SRAM2_RETENTION_32KB = 0x1U, /*!< SRAM2 Block Retention 32KB */
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SMC_SRAM2_RETENTION_64KB = 0x3U, /*!< SRAM2 Block Retention 64KB */
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SMC_SRAM2_RETENTION_96KB = 0x7U, /*!< SRAM2 Block Retention 96KB */
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SMC_SRAM2_RETENTION_128KB = 0xFU, /*!< SRAM2 Block Retention 128KB */
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SMC_SRAM2_RETENTION_160KB = 0x1FU, /*!< SRAM2 Block Retention 160KB */
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SMC_SRAM2_RETENTION_192KB = 0x3FU, /*!< SRAM2 Block Retention 192KB */
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SMC_SRAM2_RETENTION_224KB = 0x7FU, /*!< SRAM2 Block Retention 224KB */
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SMC_SRAM2_RETENTION_256KB = 0xFFU, /*!< SRAM2 Block Retention 256KB */
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SMC_SRAM2_RETENTION_288KB = 0x1FFU, /*!< SRAM2 Block Retention 288KB */
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SMC_SRAM2_RETENTION_320KB = 0x3FFU, /*!< SRAM2 Block Retention 320KB */
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SMC_SRAM2_RETENTION_352KB = 0x7FFU, /*!< SRAM2 Block Retention 352KB */
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SMC_SRAM2_RETENTION_384KB = 0xFFFU /*!< SRAM2 Block Retention 384KB */
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} SMC_Sram2RentenCtrlType;
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#endif /* SMC_SRAM2_RENTENTION_MODE_SUPPORT */
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#if SMC_LP_GOOD_SUPPORT
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/**
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* @brief Power good lock selection
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*/
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typedef enum
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{
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SMC_PG_LOCK_PTE1 = 0U, /* PTE1 is locked for LP_GOOD function when PG_IOLOCK_EN is 1 */
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SMC_PG_LOCK_PTE22 = 1U, /* PTE22 is locked for LP_GOOD function when PG_IOLOCK_EN is 1 */
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SMC_PG_LOCK_PTE20 = 2U, /* PTE20 is locked for LP_GOOD function when PG_IOLOCK_EN is 1 */
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SMC_PG_LOCK_PTI20 = 3U /* PTI20 is locked for LP_GOOD function when PG_IOLOCK_EN is 1 */
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} SMC_PGLockSelType;
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/**
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* @brief Power good polarity
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*/
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typedef enum
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{
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SMC_PG_ACTIVE_POL_HIGH = 0U, /* Level 1 is active of LP_GOOD pad */
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SMC_PG_ACTIVE_POL_LOW = 1U /* Level 0 is active of LP_GOOD pad */
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} SMC_PGActivePolType;
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#endif
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/**
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* @brief Power good control
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*/
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typedef struct
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{
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#if SMC_LP_GOOD_SUPPORT
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bool bEnable; /*!< SMC PG IO enable */
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SMC_PGLockSelType ePGLockSel; /*!< SMC PG IOLOCK selection */
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SMC_PGActivePolType ePGActivePol; /*!< SMC PG Active Polarity selection */
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#endif
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uint16_t u16RpmExitCnt; /*!< SMC RPM exit count */
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} SMC_PGCtrlType;
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/**
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* @brief SMC mixed type
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*/
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typedef struct
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{
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#if SMC_SRAM2_RENTENTION_MODE_SUPPORT
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SMC_Sram2RentenCtrlType eRamRetenSel; /*!< SMC SRAM2 block selection */
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#endif /* SMC_SRAM2_RENTENTION_MODE_SUPPORT */
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SMC_PGCtrlType tPGCtrlConifg; /*!< SMC PG control configuration */
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} SMC_MixedUsedType;
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#if SMC_SCG_WAKEUP_CONFIG_SUPPORT
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/**
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* @brief SMC SCG wakeup source selection
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*/
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typedef enum
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{
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SMC_SCG_WAKUP_SOURCE_DISABLED = 0U, /*!< SMC SCG wakeup source selection0 */
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SMC_SCG_WAKUP_SOURCE_AONTIMER = 1U, /*!< SMC SCG wakeup source selection1 */
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#if SMC_SCG_WAKEUP_SRC_TSTMP_EXT_TRG_SUPPORT
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SMC_SCG_WAKUP_SOURCE_TSTMP_EXT_TRG0 = 2U, /*!< SMC SCG wakeup source selection2 */
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SMC_SCG_WAKUP_SOURCE_TSTMP_EXT_TRG1 = 3U, /*!< SMC SCG wakeup source selection3 */
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#endif
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#if SMC_SCG_WAKEUP_SRC_TSTMP_EDGE_TRG_SUPPORT
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SMC_SCG_WAKUP_SOURCE_TSTMP_EDGE_TRG2 = 2U, /*!< SMC SCG wakeup source selection2 */
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SMC_SCG_WAKUP_SOURCE_TSTMP_EDGE_TRG3 = 3U, /*!< SMC SCG wakeup source selection3 */
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#endif
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SMC_SCG_WAKUP_SOURCE_RTC = 4U, /*!< SMC SCG wakeup source selection4 */
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SMC_SCG_WAKUP_SOURCE_AONDIV_CLOCK1 = 5U, /*!< SMC SCG wakeup source selection5 */
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SMC_SCG_WAKUP_SOURCE_RGPIOC_GPIO_INT0 = 6U, /*!< SMC SCG wakeup source selection6 */
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SMC_SCG_WAKUP_SOURCE_RGPIOC_GPIO_INT2 = 7U, /*!< SMC SCG wakeup source selection7 */
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SMC_SCG_WAKUP_SOURCE_RGPIOC_GPIO_INT4 = 8U /*!< SMC SCG wakeup source selection8 */
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} SMC_SCGWakeUpSourceSelection;
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/**
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* @brief SMC SCG wakeup polarity selection
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*/
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typedef enum
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{
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SMC_SCG_WAKUP_POLARITY_NORMAL = 0U, /*!< SMC SCG wakeup polarity selection0 */
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SMC_SCG_WAKUP_POLARITY_REVERSED = 1U, /*!< SMC SCG wakeup polarity selection1 */
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} SMC_SCGWakeUpPolaritySelection;
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/**
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* @brief SMC SCG SIRC Trigger to ADC config
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*/
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typedef enum
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{
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SMC_SCG_SIRC_TRIGGER_TO_ADCS_DISABLE = 0U, /*!< SMC SCG SIRC Trigger to ADC Disable */
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#if SMC_SCG_WARKEUP_ADC1_AND_ADC2
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SMC_SCG_SIRC_TRIGGER_TO_ADC1 = 1U, /*!< SMC SCG SIRC Trigger to ADC1 */
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SMC_SCG_SIRC_TRIGGER_TO_ADC2 = 2U, /*!< SMC SCG SIRC Trigger to ADC2 */
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SMC_SCG_SIRC_TRIGGER_TO_ADC1_AND_ADC2 = 3U /*!< SMC SCG SIRC Trigger to ADC1 and ADC2 */
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#endif
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#if SMC_SCG_WARKEUP_ADC0_AND_ADC1
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SMC_SCG_SIRC_TRIGGER_TO_ADC0 = 1U, /*!< SMC SCG SIRC Trigger to ADC0 */
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SMC_SCG_SIRC_TRIGGER_TO_ADC1 = 2U, /*!< SMC SCG SIRC Trigger to ADC1 */
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SMC_SCG_SIRC_TRIGGER_TO_ADC0_AND_ADC1 = 3U /*!< SMC SCG SIRC Trigger to ADC0 and ADC1 */
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#endif
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} SMC_SCGSIRCTriggerToADCSelection;
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/**
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* @brief SMC SCG WAKEUP Register Lock Selection
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*/
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typedef enum
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{
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SMC_SCG_WAKEUP_REG_UNLOCK = 0U, /*!< SMC SCG WAKEUP Register Unlock */
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SMC_SCG_WAKEUP_REG_LOCK = 1U /*!< SMC SCG WAKEUP Register Lock */
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} SMC_SCGWakeUpRegLockSelection;
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typedef struct
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{
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SMC_SCGWakeUpSourceSelection eWakeUpSource; /*!< SMC SCG Wakeup Source Selection */
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SMC_SCGWakeUpPolaritySelection eWakeUpPolarity; /*!< SMC SCG Wakeup Polarity Selection */
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SMC_SCGSIRCTriggerToADCSelection eSircTriggerToAdc; /*!< SMC SCG SIRC Trigger to ADC Selection */
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SMC_SCGWakeUpRegLockSelection eRegLockSel; /*!< SMC SCG WAKEUP Register Lock Selection */
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} SMC_SCGWakeUpConfigType;
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#endif
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#if SMC_TSTMP0CLOCK_CONFIG_SUPPORT
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/**
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* @brief SMC Tstmp0 clock divider
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*/
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typedef enum
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{
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SMC_TSTMP0_CLOCK_DIV_BY1 = 0U, /*!< SMC TSTMP0 Clock Divider By 1 */
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SMC_TSTMP0_CLOCK_DIV_BY2 = 1U, /*!< SMC TSTMP0 Clock Divider By 2 */
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SMC_TSTMP0_CLOCK_DIV_BY3 = 2U, /*!< SMC TSTMP0 Clock Divider By 3 */
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SMC_TSTMP0_CLOCK_DIV_BY4 = 3U, /*!< SMC TSTMP0 Clock Divider By 4 */
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SMC_TSTMP0_CLOCK_DIV_BY5 = 4U, /*!< SMC TSTMP0 Clock Divider By 5 */
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SMC_TSTMP0_CLOCK_DIV_BY6 = 5U, /*!< SMC TSTMP0 Clock Divider By 6 */
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SMC_TSTMP0_CLOCK_DIV_BY7 = 6U, /*!< SMC TSTMP0 Clock Divider By 7 */
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SMC_TSTMP0_CLOCK_DIV_BY8 = 7U /*!< SMC TSTMP0 Clock Divider By 8 */
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} SMC_Tstmp0ClkDivType;
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/**
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* @brief SMC Tstmp0 clock source
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*/
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typedef enum
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{
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SMC_TSTMP0_CLK_SRC_SIRCDIV_1M = 0U, /*!< SMC TSTMP0 Clock Source SIRCDIV1M */
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SMC_TSTMP0_CLK_SRC_SIRC_32K = 1U, /*!< SMC TSTMP0 Clock Source SIRC_32K */
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SMC_TSTMP0_CLK_SRC_SOSC_32K = 2U, /*!< SMC TSTMP0 Clock Source SOSC_32K */
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SMC_TSTMP0_CLK_SRC_FOSC_DIVL = 3U /*!< SMC TSTMP0 Clock Source FOSC_DIVL */
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} SMC_Tstmp0ClkSrcType;
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/**
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* @brief SMC Tstmp0 clock configuration
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*/
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typedef struct
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{
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SMC_Tstmp0ClkDivType eClkDiv; /*!< SMC Tstmp0 clock divider */
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SMC_Tstmp0ClkSrcType eClkSrc; /*!< SMC Tstmp0 clock source */
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} SMC_Tmtmp0ClkConfigType;
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#endif /* #if SMC_TSTMP0CLOCK_CONFIG_SUPPORT */
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#endif /* #if SMC_CLOCKCONFIG_SUPPORT */
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#if SCG_PLLX_CLK1_SUPPORT
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/**
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* @brief SMC PLLx stop mode operation status
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*/
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typedef struct
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{
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bool bPll0Clk1GateOff; /*!< PLL0 Clk1 gate off status */
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#if SCG_PLL0_CLK2_SUPPORT
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bool bPll0Clk2GateOff; /*!< PLL0 Clk2 gate off status */
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#endif /* SCG_PLL0_CLK2_SUPPORT */
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#if SCG_PLL1_SUPPORT
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bool bPll1Clk1GateOff; /*!< PLL1 Clk1 gate off status */
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#endif /* SCG_PLL1_SUPPORT */
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} SMC_PllStatusType;
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#endif /* #if SCG_PLLX_CLK1_SUPPORT */
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/* global functions */
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/**
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* @brief Set system mode
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*
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* @param eMode MCU low power mode
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*
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*/
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void SMC_SetSystemMode(const SMC_ModeType eMode);
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#if SMC_CLOCKCONFIG_SUPPORT
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/**
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* @brief set always on clock source configuration include AON32K, RTC, AONCLK clock.
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*
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* @param pAonclkSrcType pointer to AONCLKSR instance for AON clock source configuration
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* @param bLockStatus to lock current register
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*
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* @return Set clock out operation success/failed
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*/
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SMC_StatusType SMC_SetAonClkSrc(const SMC_AONCLKSRType *const pAonclkSrcType, bool bLockStatus);
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/**
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* @brief Report the clock source status and frequency configured in MCU run time.
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* The clock frequency and status would change by clock set function.
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*
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* @param eClkkName: the SMC clock source to query
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* @param pFreq: frequency variable point to get the frequency value
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* @return true or false. This indicate the clock source status invalid or request clock source out of
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* range.
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*/
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SMC_StatusType SMC_GetSMCClockFreq(const SMC_ClkSrcType eClkkName, uint32_t *const pFreq);
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/**
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* @brief Configure the low power wakeup PAD output in SMC_LP_WAKEUP register
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*
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* @param SMC_LPWakeUpPadType the low power wakeup PAD source and polarity configuration
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*/
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void SMC_SetLPWakeUpPad(const SMC_LPWakeUpPadType* pLPWakeUpPad);
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/**
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* @brief Configure SMC mixed used control
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*
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* @param SMC_MixedUsedType SMC mixed used control
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*/
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void SMC_SetMixedUsedConfiguration(const SMC_MixedUsedType* pMixedUsedConfig);
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|
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/**
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* @brief Set clock out
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*
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* @param pSmcClkOut Clock out setting
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* @param bLockStatus Lock status
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* @return Smc return type
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|
*/
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SMC_StatusType SMC_SetClockOut(const SMC_ClkoutType *const pSmcClkOut, bool bLockStatus);
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#endif /* #if SMC_CLOCKCONFIG_SUPPORT */
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#if SMC_SCG_WAKEUP_CONFIG_SUPPORT
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/**
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* @brief Set scg wakup configuration.
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|
*
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* @param SMC_SCGWakeUpConfigType SCG wakeup configuration
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|
*
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|
*/
|
|
void SMC_SetSCGWakeUpConfiguration(const SMC_SCGWakeUpConfigType *const pSCGWakeupConfig);
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#endif
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|
#if SMC_TSTMP0CLOCK_CONFIG_SUPPORT
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/**
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|
* @brief Set tstmp0 clock configuration.
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|
*
|
|
* @param SMC_Tmtmp0ClkConfigType Tstmp0 clock configuration
|
|
*
|
|
* @note configuration sequence:
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|
* 1. Disable EN and wait for 4 clock cycles
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|
* 2. Set div and sel
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|
* 3. Enable EN and wait for 4 clock cycles
|
|
* if set lock bit, this register can be restored by POR
|
|
*/
|
|
void SMC_SetTstmp0ClockConfiguration(const SMC_Tmtmp0ClkConfigType *const pTstmp0ClkConfig);
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|
#endif /* #if SMC_TSTMP0CLOCK_CONFIG_SUPPORT */
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|
|
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/** @}*/ /* module_driver_smc */
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|
|
|
#endif /* #if SMC_INSTANCE_COUNT > 0U */
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|
|
|
#endif
|