487 lines
18 KiB
C
487 lines
18 KiB
C
/**
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* @file module_driver_rgm.h
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* @author Flagchip
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* @brief RGM driver type definition and API
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* @version 2.0.0
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* @date 2024-08-20
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*
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* SDK Version: 2.6.0
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*
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* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
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*
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* @details
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2023-12-15 Flagchip074 N/A First version for FC7300
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* 2.0.0 2024-10-12 Flagchip074 N/A Change version and release
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******************************************************************************** */
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#ifndef _DRIVER_MODULE_DRIVER_RGM_H_
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#define _DRIVER_MODULE_DRIVER_RGM_H_
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#include "HwA_rgm.h"
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#if RGM_INSTANCE_COUNT > 0U
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/**
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* @addtogroup module_driver_rgm
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* @{
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*/
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/**
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* @name RGM API Service IDs
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*
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* @{
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*/
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#define RGM_INIT_ID 0x00U
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/** @}*/
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/**
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* @name RGM Dev Error Code
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* @brief Error Code of calling RGM apis
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*
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* @{
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*/
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#define RGM_E_PARAM_DELAY_TIME 0x01U
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#define RGM_E_PARAM_POINTER 0x02U
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/** @}*/
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/** @brief Rgm return type. */
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typedef enum
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{
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RGM_STATUS_SUCCESS = 0U, /**< Return status success */
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RGM_STATUS_PARAM_INVALID = 1U, /**< Return status parameter invalid */
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RGM_STATUS_COREID_INVALID = 2U, /**< Return status core id invalid */
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RGM_STATUS_CLOCK_INVALID /**< Return status clock invalid */
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} RGM_StatusType;
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/** @brief Rgm reset pin filter clock type. */
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typedef enum
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{
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RGM_RESET_FILTER_DISABLE = 0U, /**< Reset Pin Filter Disable */
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RGM_RESET_FILTER_BUS_CLOCK = 1U /**< Reset Pin Filter Bus Clock */
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} RGM_FilterClkSrc;
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/**
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* @brief The structure of the SCG processing handle
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*
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*/
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typedef struct _RGM_HandleType
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{
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void (*pRgmCpu0ResetInterruptNotify)(struct _RGM_HandleType *pHandle, uint32_t u32ResetReson); /**< Cpu0 reset interrupt callback */
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#if RGM_C1_SUPPORT
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void (*pRgmCpu1ResetInterruptNotify)(struct _RGM_HandleType *pHandle, uint32_t u32ResetReson); /**< Cpu1 reset interrupt callback */
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void (*pRgmCpu0IntFromOtherCpuNotify)(struct _RGM_HandleType *pHandle, uint8_t u8CoreId); /**< Cpu0 interrupt from other cpu callback */
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#endif
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#if RGM_C2_SUPPORT
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void (*pRgmCpu2ResetInterruptNotify)(struct _RGM_HandleType *pHandle, uint32_t u32ResetReson); /**< Cpu2 reset interrupt callback */
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void (*pRgmCpu1IntFromOtherCpuNotify)(struct _RGM_HandleType *pHandle, uint8_t u8CoreId); /**< Cpu1 interrupt from other cpu callback */
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void (*pRgmCpu2IntFromOtherCpuNotify)(struct _RGM_HandleType *pHandle, uint8_t u8CoreId); /**< Cpu2 interrupt from other cpu callback */
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#endif
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#if RGM_C3_SUPPORT
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void (*pRgmCpu3ResetInterruptNotify)(struct _RGM_HandleType *pHandle, uint32_t u32ResetReson); /**< Cpu3 reset interrupt callback */
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void (*pRgmCpu3IntFromOtherCpuNotify)(struct _RGM_HandleType *pHandle, uint8_t u8CoreId); /**< Cpu3 interrupt from other cpu callback */
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#endif
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} RGM_HandleType;
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/** @brief Rgm configure type */
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typedef struct
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{
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bool bResetfiltAonLp; /**< Reset Pin Filter using AON32K Clock in Low Power Mode */
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#if RGM_C1_SUPPORT
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bool bCpu1RstIntSendCpu0En; /**< Cpu1 reset interrupt to Cpu0 enable/disable */
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bool bCpu1RstTrigSysRstEn; /**< Cpu1 reset generate system reset enable/disable */
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RGM_CoreRstTrigSysRstMangerType eCpu1Rst; /**< Core reset trigger system reset event flag */
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#endif
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#if RGM_C2_SUPPORT
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bool bCpu1RstIntSendCpu2En; /**< Cpu1 reset interrupt to Cpu2 enable/disable */
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bool bCpu2RstIntSendCpu0En; /**< Cpu2 reset interrupt to Cpu0 enable/disable */
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bool bCpu2RstIntSendCpu1En; /**< Cpu2 reset interrupt to Cpu1 enable/disable */
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bool bCpu2RstTrigSysRstEn; /**< Cpu2 reset generate system reset enable/disable */
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RGM_CoreRstTrigSysRstMangerType eCpu2Rst; /**< Core reset trigger system reset event flag */
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#endif
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#if RGM_C3_SUPPORT
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bool bCpu1RstIntSendCpu3En; /**< Cpu1 reset interrupt to Cpu3 enable/disable */
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bool bCpu2RstIntSendCpu3En; /**< Cpu2 reset interrupt to Cpu3 enable/disable */
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bool bCpu3RstIntSendCpu0En; /**< Cpu3 reset interrupt to Cpu0 enable/disable */
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bool bCpu3RstIntSendCpu12En; /**< Cpu3 reset interrupt to Cpu12 enable/disable */
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bool bCpu3RstTrigSysRstEn; /**< Cpu3 reset generate system reset enable/disable */
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RGM_CoreRstTrigSysRstMangerType eCpu3Rst; /**< Core reset trigger system reset event flag */
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#endif
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uint8_t u8BusClockFilterWidth; /**< Reset Pin Filter Bus Clock Width Configuration */
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RGM_FilterClkSrc eFliterClkSrc; /**< Reset Pin Filter Clock source */
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RGM_ResetDelayType eDelay; /**< Reset delay after interrupt assert */
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uint32_t u32SystemInterruptMask; /**< System interrupt enable mask */
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uint32_t u32Cpu0InterruptMask; /**< Core interrupt enable mask */
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#if RGM_C1_SUPPORT
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uint32_t u32Cpu1InterruptMask; /**< Core interrupt enable mask */
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void (*pRgmCpu1ResetInterruptNotify)(RGM_HandleType *pHandle, uint32_t u32ResetReson); /**< Cpu1 reset interrupt callback */
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void (*pRgmCpu0IntFromOtherCpuNotify)(RGM_HandleType *pHandle, uint8_t u8CoreId); /**< Cpu0 interrupt from other cpu callback */
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#endif
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#if RGM_C2_SUPPORT
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uint32_t u32Cpu2InterruptMask; /**< Core interrupt enable mask */
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void (*pRgmCpu2ResetInterruptNotify)(RGM_HandleType *pHandle, uint32_t u32ResetReson); /**< Cpu2 reset interrupt callback */
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void (*pRgmCpu1IntFromOtherCpuNotify)(RGM_HandleType *pHandle, uint8_t u8CoreId); /**< Cpu1 interrupt from other cpu callback */
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void (*pRgmCpu2IntFromOtherCpuNotify)(RGM_HandleType *pHandle, uint8_t u8CoreId); /**< Cpu2 interrupt from other cpu callback */
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#endif
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#if RGM_C3_SUPPORT
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uint32_t u32Cpu3InterruptMask; /**< Core interrupt enable mask */
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void (*pRgmCpu3ResetInterruptNotify)(RGM_HandleType *pHandle, uint32_t u32ResetReson); /**< Cpu3 reset interrupt callback */
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void (*pRgmCpu3IntFromOtherCpuNotify)(RGM_HandleType *pHandle, uint8_t u8CoreId); /**< Cpu3 interrupt from other cpu callback */
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#endif
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void (*pRgmCpu0ResetInterruptNotify)(RGM_HandleType *pHandle, uint32_t u32ResetReson); /**< Cpu0 reset interrupt callback */
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} RGM_ConfigType;
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/**
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* @brief This api can get RGM_SRS register that indicate the source of the most recent reset.
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*
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* @return RGM->RGM_SRS register, bit 0-15,29-31 corresponding to RGM_ResetEventType, refer to reference manual for details.
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* @note Multiple flags can be set if multiple reset events occur at the same time
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*/
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uint32_t RGM_GetSystemLastResetFLag(void);
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/**
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* @brief This api can get RGM_SSRS register that indicate all reset sources since the last POR or LVD that have not been cleared by software.
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*
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* @return RGM->RGM_SSRS register, bit 0-15,29-31 corresponding to RGM_ResetEventType, refer to reference manual for details.
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*/
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uint32_t RGM_GetSystemAllResetFlag(void);
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/**
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* @brief This api can clear all reset flag of RGM_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
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*
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*/
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void RGM_ClearSystemAllResetFlagAfterPOR(void);
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/**
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* @brief Enable reset pin filter
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*
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* @param eClk Reset pin filter clock source
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* @param u8BusClockFilterWidth Bus clock filter width
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* @param bLpClkEn select whether enable reset pin filter using AON32clock in low power mode
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* @return RGM return type
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* @note If use AON32K clock, A reset signal whose length is less than 2 AON32K clock periods will be filtered
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*/
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RGM_StatusType RGM_EnableResetFilter(RGM_FilterClkSrc eClk, uint8_t u8BusClockFilterWidth, bool bLpClkEn);
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/**
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* @brief Disable reset pin filter
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*
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* @param eClk Reset pin filter clock source
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* @param bLpClkEn select whether disable reset pin filter using AON32clock in low power mode
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* @return RGM return type
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*/
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RGM_StatusType RGM_DisableResetFilter(RGM_FilterClkSrc eClk, bool bLpClkEn);
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/**
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* @brief This api can enable interrupt before an system reset appear.
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*
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* @param eDelay Enumeration of delay cycles
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* @param eResetInterrupt Reset event flag, like: RGM_INT_CLKERR0 | RGM_INT_FCSMU
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* @return RGM return type
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*
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* @note Here is the interrupted master switch control
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*/
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RGM_StatusType RGM_EnableSystemResetInt(RGM_ResetDelayType eDelay, RGM_SysResetIntMangerType eResetInterrupt);
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/**
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* @brief This api can disable interrupt before an system reset appear.
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*
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* @param eResetInterrupt Reset event flag, like: RGM_INT_CLKERR0 | RGM_INT_FCSMU
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* @return RGM return type
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*/
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void RGM_DisableSystemResetInt(RGM_SysResetIntMangerType eResetInterrupt);
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/**
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* @brief Generate software reset through cotex-m register
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*
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*/
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void RGM_GenerateSystemCoreReset(void);
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/**
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* @brief Generate software reset through RGM C0_RST register
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*
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*/
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void RGM_GenerateCpu0SwReset(void);
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/**
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* @brief This api can disable interrupt before an CPU0 core related reset appear.
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*
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* @param eCPU0Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST
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* @return RGM return type
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*/
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RGM_StatusType RGM_DisableCPU0CoreResetInt(RGM_CoreResetIntMangerType eCPU0Interrupt);
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/**
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* @brief Get the CPU0 exit reset flag
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*
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* @return RGM_CPU_OUT_RST_UNDER CPU0 is under reset
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* @return RGM_CPU_OUT_RST_OUT CPU0 is out of reset
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*/
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RGM_CoreResetStatusType RGM_GetCPU0OutResetFlag(void);
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/**
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* @brief This api can get RGM_C0_SRS register that indicate the source of the most recent CPU0 reset.
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*
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* @return RGM->RGM_C0_SRS register, bit 0-20 corresponding to RGM_ResetEventType, refer to reference manual for details.
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* @note Multiple flags can be set if multiple reset events occur at the same time
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*/
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uint32_t RGM_GetCPU0LastResetFLag(void);
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/**
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* @brief This api can get RGM_C0_SSRS register that indicate all CPU0 reset sources since the last POR or LVD that have not been cleared by software.
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*
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* @returnRGM->RGM_C0_SSRS register, bit 0-20,29-31 corresponding to RGM_CPUResetEventType, refer to reference manual for details.
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*/
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uint32_t RGM_GetCPU0AllResetFlag(void);
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/**
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* @brief This api can clear all reset flag of RGM_C0_SSRS register which indicate CPU0 all reset sources since the last POR or LVD that have not been cleared by software.
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*
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*/
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void RGM_ClearCPU0AllResetFlagAfterPOR(void);
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#if RGM_C1_SUPPORT
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/**
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* @brief This api can configure the selected CPU1 core related reset as a system reset.
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*
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* @param eCPU1SystemReset Select the CPU1 core related reset need to be configured as system reset
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* @return RGM return type
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*/
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RGM_StatusType RGM_EnableCPU1CoreSystemReset(RGM_CoreRstTrigSysRstMangerType eCPU1SystemReset);
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/**
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* @brief This api can configure the selected CPU1 core related reset as non system reset.
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*
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* @param eCPU1SystemReset Select the CPU1 core related reset need to be configured as non system reset
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* @return RGM return type
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*/
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RGM_StatusType RGM_DisableCPU1CoreSystemReset(RGM_CoreRstTrigSysRstMangerType eCPU1SystemReset);
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/**
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* @brief This api can disable interrupt before an CPU1 core related reset appear.
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*
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* @param eCPU1Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST
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* @return RGM return type
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*/
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RGM_StatusType RGM_DisableCPU1CoreResetInt(RGM_CoreResetIntMangerType eCPU1Interrupt);
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/**
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* @brief Get the CPU1 exit reset flag
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*
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* @return RGM_CPU_OUT_RST_UNDER CPU1 is under reset
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* @return RGM_CPU_OUT_RST_OUT CPU1 is out of reset
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*/
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RGM_CoreResetStatusType RGM_GetCPU1OutResetFlag(void);
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/**
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* @brief Generate software reset through RGM C1_RST register
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*
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*/
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void RGM_GenerateCpu1SwReset(void);
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/**
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* @brief This api can get RGM_C1_SRS register that indicate the source of the most recent CPU1 reset.
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*
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* @return RGM->RGM_C1_SRS register, bit 0-20 corresponding to RGM_ResetEventType, refer to reference manual for details.
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* @note Multiple flags can be set if multiple reset events occur at the same time
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*/
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uint32_t RGM_GetCPU1LastResetFLag(void);
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/**
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* @brief This api can release CPU1.
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*
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* @note After writing, this bit will be locked.
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*/
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void RGM_ReleaseCPU1(void);
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/**
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* @brief This api can get RGM_C1_SSRS register that indicate all CPU1 reset sources since the last POR or LVD that have not been cleared by software.
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*
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* @returnRGM->RGM_C1_SSRS register, bit 0-20,29-31 corresponding to RGM_CPUResetEventType, refer to reference manual for details.
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*/
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uint32_t RGM_GetCPU1AllResetFlag(void);
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/**
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* @brief This api can clear all reset flag of RGM_C1_SSRS register which indicate CPU1 all reset sources since the last POR or LVD that have not been cleared by software.
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*
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*/
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void RGM_ClearCPU1AllResetFlagAfterPOR(void);
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#endif
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#if RGM_C2_SUPPORT
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/**
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* @brief This api can configure the selected CPU2 core related reset as a system reset.
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*
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* @param eCPU2SystemReset Select the CPU2 core related reset need to be configured as system reset
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* @return RGM return type
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*/
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RGM_StatusType RGM_EnableCPU2CoreSystemReset(RGM_CoreRstTrigSysRstMangerType eCPU2SystemReset);
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/**
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* @brief This api can configure the selected CPU2 core related reset as non system reset.
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*
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* @param eCPU2SystemReset Select the CPU2 core related reset need to be configured as non system reset
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* @return RGM return type
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*/
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RGM_StatusType RGM_DisableCPU2CoreSystemReset(RGM_CoreRstTrigSysRstMangerType eCPU2SystemReset);
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/**
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* @brief This api can disable interrupt before an CPU2 core related reset appear.
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*
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* @param eCPU2Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST
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* @return RGM return type
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*/
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RGM_StatusType RGM_DisableCPU2CoreResetInt(RGM_CoreResetIntMangerType eCPU2Interrupt);
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/**
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* @brief Get the CPU2 exit reset flag
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*
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* @return RGM_CPU_OUT_RST_UNDER CPU2 is under reset
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* @return RGM_CPU_OUT_RST_OUT CPU2 is out of reset
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*/
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RGM_CoreResetStatusType RGM_GetCPU2OutResetFlag(void);
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/**
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* @brief Generate software reset through RGM C2_RST register
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*
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*/
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void RGM_GenerateCpu2SwReset(void);
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/**
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* @brief This api can get RGM_C2_SRS register that indicate the source of the most recent CPU2 reset.
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*
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* @return RGM->RGM_C2_SRS register, bit 0-20 corresponding to RGM_ResetEventType, refer to reference manual for details.
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* @note Multiple flags can be set if multiple reset events occur at the same time
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*/
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uint32_t RGM_GetCPU2LastResetFLag(void);
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/**
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* @brief This api can release CPU2.
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*
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* @note After writing, this bit will be locked.
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*/
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void RGM_ReleaseCPU2(void);
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/**
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* @brief This api can get RGM_C2_SSRS register that indicate all CPU2 reset sources since the last POR or LVD that have not been cleared by software.
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*
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* @return RGM->RGM_C2_SSRS register, bit 0-20,29-31 corresponding to RGM_CPUResetEventType, refer to reference manual for details.
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*/
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uint32_t RGM_GetCPU2AllResetFlag(void);
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/**
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* @brief This api can clear all reset flag of RGM_C2_SSRS register which indicate CPU2 all reset sources since the last POR or LVD that have not been cleared by software.
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*
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*/
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void RGM_ClearCPU2AllResetFlagAfterPOR(void);
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#endif
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#if RGM_C3_SUPPORT
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/**
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* @brief This api can configure the selected CPU3 core related reset as a system reset.
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*
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* @param eCPU3SystemReset Select the CPU3 core related reset need to be configured as system reset
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* @return RGM return type
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*/
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RGM_StatusType RGM_EnableCPU3CoreSystemReset(RGM_CoreRstTrigSysRstMangerType eCPU3SystemReset);
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/**
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* @brief This api can configure the selected CPU3 core related reset as non system reset.
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*
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* @param eCPU3SystemReset Select the CPU3 core related reset need to be configured as non system reset
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* @return RGM return type
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*/
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RGM_StatusType RGM_DisableCPU3CoreSystemReset(RGM_CoreRstTrigSysRstMangerType eCPU3SystemReset);
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/**
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* @brief This api can disable interrupt before an CPU3 core related reset appear.
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*
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* @param eCPU3Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST
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* @return RGM return type
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*/
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RGM_StatusType RGM_DisableCPU3CoreResetInt(RGM_CoreResetIntMangerType eCPU3Interrupt);
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/**
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* @brief Get the CPU3 exit reset flag
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*
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* @return RGM_CPU_OUT_RST_UNDER CPU3 is under reset
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* @return RGM_CPU_OUT_RST_OUT CPU3 is out of reset
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*/
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RGM_CoreResetStatusType RGM_GetCPU3OutResetFlag(void);
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/**
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* @brief Generate software reset through RGM C3_RST register
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*
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*/
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void RGM_GenerateCPU3SwReset(void);
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/**
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* @brief This api can get RGM_C3_SRS register that indicate the source of the most recent CPU3 reset.
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*
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* @return RGM->RGM_C3_SRS register, bit 0-20 corresponding to RGM_ResetEventType, refer to reference manual for details.
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* @note Multiple flags can be set if multiple reset events occur at the same time
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*/
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uint32_t RGM_GetCPU3LastResetFLag(void);
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/**
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* @brief This api can release CPU3.
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*
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* @note After writing, this bit will be locked.
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*/
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void RGM_ReleaseCPU3(void);
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/**
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* @brief This api can get RGM_C3_SSRS register that indicate all CPU3 reset sources since the last POR or LVD that have not been cleared by software.
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*
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* @return RGM->RGM_C3_SSRS register, bit 0-20,29-31 corresponding to RGM_CPUResetEventType, refer to reference manual for details.
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*/
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uint32_t RGM_GetCPU3AllResetFlag(void);
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/**
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* @brief This api can clear all reset flag of RGM_C3_SSRS register which indicate CPU3 all reset sources since the last POR or LVD that have not been cleared by software.
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*
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*/
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void RGM_ClearCPU3AllResetFlagAfterPOR(void);
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#endif
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/**
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* @brief RGM Pre-interrupt entry
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*
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*/
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void RGM_Pre_UserIRQHandler(RGM_HandleType* pRgmHandle);
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#if (RGM_C1_SUPPORT || RGM_C2_SUPPORT || RGM_C3_SUPPORT)
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/**
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* @brief RGM Other core interrupt entry
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*
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*/
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void RGM_Other_UserIRQHandler(RGM_HandleType* pRgmHandle);
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#endif
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/**
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* @brief RGM initialize function
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*
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* @param pRgmHandle RGM handle
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* @param pInitCfg Init pointer
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*
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* @note
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* 1. RGM system related register configured by core 0
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* 2. If core1/core2 use RGM, both core0 and core1/core2 need call RGM_Init
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* and different pRgmHandle need be given
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*/
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void RGM_Init(RGM_HandleType* pRgmHandle, RGM_ConfigType *pInitCfg);
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/** @}*/ /* module_driver_rgm */
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#endif /* #if RGM_INSTANCE_COUNT > 0U */
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#endif /* end of _DRIVER_MODULE_DRIVER_RGM_H_ */
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