352 lines
11 KiB
C
352 lines
11 KiB
C
/**
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* @file module_driver_ospi.h
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* @author Flagchip
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* @brief OSPI driver type definition and API
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* @version 2.0.0
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* @date 2024-08-20
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*
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* SDK Version: 2.6.0
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*
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* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
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*
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* @details
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2023-12-15 Flagchip100 N/A First version for FC7300
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* 2.0.0 2024-10-12 Flagchip122 N/A Change version and release
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******************************************************************************** */
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#ifndef _DRIVER_MODULE_DRIVER_OSPI_H_
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#define _DRIVER_MODULE_DRIVER_OSPI_H_
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#include "HwA_ospi.h"
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#if OSPI_INSTANCE_COUNT > 0U
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/**
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* @addtogroup module_driver_ospi
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* @{
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*/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/**
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* @name Ospi API Service IDs
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* @brief These macros define the command IDs used for communication with the on-chip OSPI interface.
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* Each ID corresponds to a specific operation that can be performed via the OSPI interface.
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*
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* @{
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*/
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#define OSPI_INIT_ID ((uint8) 0x00u)
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#define OSPI_SET_FLASHCFG_ID ((uint8) 0x01u)
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#define OSPI_UPDATE_LUT_ID ((uint8) 0x02u)
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#define OSPI_WRITE_FIFO_ID ((uint8) 0x03u)
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#define OSPI_READ_FIFO_ID ((uint8) 0x04u)
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#define OSPI_TRANSFER_BLOCKING_ID ((uint8) 0x05u)
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#define OSPI_TRANSFER_NONBLOCKING_ID ((uint8) 0x06u)
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/** @}*/
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/**
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* @name Ospi Dev Error Code
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* @brief Error Code of calling OSPI apis
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* @{
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*/
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#define OSPI_E_PARAM_POINTER ((uint8)0x01u)
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#define OSPI_E_PARAM_INVALID ((uint8)0x02u)
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/** @}*/
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/**
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* @name IO configurations IO configurations for the OSPI interface
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* @brief IO configurations for the OSPI interface
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* @{
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*/
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#define SINGLE_IO 0x00 /**< Single I/O */
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#define DUAL_IO 0x01 /**< Dual I/O */
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#define QUAD_IO 0x02 /**< Quad I/O */
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#define OCTAL_IO 0x03 /**< Octal I/O */
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/** @}*/
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/**
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* @name OSPI command_set OSPI command set definitions
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* @brief OSPI command set definitions
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* @{
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*/
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#define OSPI_CMD_STOP 0x0 /**< Stop command */
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#define OSPI_CFG_DRV 0x1 /**< Configure drive strength */
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#define OSPI_CFG_ADDR 0x2 /**< Configure address */
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#define OSPI_CMD_DUMMY 0x3 /**< Configure dummy cycles */
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#define OSPI_CFG_MODE8 0x4 /**< Configure mode 8 */
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#define OSPI_CFG_MODE2 0x5 /**< Configure mode 2 */
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#define OSPI_CFG_MODE4 0x6 /**< Configure mode 4 */
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#define OSPI_READ_DRV 0x7 /**< Configure read drive strength */
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#define OSPI_WRITE_DRV 0x8 /**< Configure write drive strength */
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#define OSPI_CMD_END 0x9 /**< End command */
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#define OSPI_CFG_ADDR_DDR 0xA /**< Configure address DDR */
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#define OSPI_CFG_MODE8_DDR 0xB /**< Configure mode 8 DDR */
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#define OSPI_CFG_MODE2_DDR 0xC /**< Configure mode 2 DDR */
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#define OSPI_CFG_MODE4_DDR 0xD /**< Configure mode 4 DDR */
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#define OSPI_READ_DRV_DDR 0xE /**< Configure read drive strength DDR */
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#define OSPI_WRITE_DRV_DDR 0xF /**< Configure write drive strength DDR */
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#define OSPI_CFG_DRV_DDR 0x11 /**< Configure drive strength DDR */
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#define OSPI_CFG_CADDR 0x12 /**< Configure CADDR */
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#define OSPI_CFG_CADDR_DDR 0x13 /**< Configure CADDR DDR */
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/** @}*/
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#define OSPI_FIFO_DEPTH_MAX 16 /**< OSPI FIFO depth */
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#define OSPI_ONE_TRANSFER_SIZE_MAX 64 /**< OSPI one transfer size */
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/**
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* @brief Status returned by OSPI APIs
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*
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*/
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typedef enum {
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OSPI_STATUS_SUCCESS = 0, /*!< API execute successfully */
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OSPI_STATUS_PARAM_ERR, /*!< parameter error */
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OSPI_STATUS_TIMEOUT
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} OSPI_StatusType;
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typedef enum
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{
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OSPI_OPERATION_COMMAND, /*!< OSPI operation: Only command, both TX and Rx buffer are ignored. */
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OSPI_OPERATION_CONFIG, /*!< OSPI operation: Configure device mode, the TX fifo size is fixed in LUT. */
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OSPI_OPERATION_READ, /*!< OSPI operation: Read, only Rx Buffer is effective. */
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OSPI_OPERATION_WRITE, /*!< OSPI operation: Read, only Tx Buffer is effective. */
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} OSPI_OperationType;
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/**
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* @brief The basic configuration option for the OSPI peripheral
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*
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*/
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typedef struct
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{
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bool bDdrEn;
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OSPI_DqsSrcSelType eDqsSrcSel;
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OSPI_ClockDivideType eClkDivider;
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OSPI_ClockMuxType eClkMux;
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OSPI_EndianType eEndian;
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} OSPI_ConfigType;
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/**
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* @brief Define the structure for OSPI device configuration.
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*
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* This structure is used to configure the parameters of the OSPI (OctoSPI) interface.
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*/
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typedef struct
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{
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uint32_t u32FlashAddress;
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uint32_t u32FlashTopAddress;
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uint8_t u8FlashColAddressSpace;
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uint8_t u8WordAddressable;
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uint8_t u8CsHoldTime;
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uint8_t u8CsSetupTime;
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uint8_t u8DelayLine;
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} OSPI_DeviceConfigType;
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/**
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* @brief FlexSPI Transfer structure definition.
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*
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* This structure defines the parameters required for a FlexSPI transfer operation.
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*
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*
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*/
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typedef struct _flexspi_transfer
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{
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uint32_t deviceAddress; /*!< Operation device address. */
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OSPI_OperationType cmdType; /*!< Execution command type. */
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uint8_t seqIndex; /*!< Sequence ID for command. */
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uint32_t * data; /*!< Data buffer. */
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uint16_t dataSize; /*!< Data size in bytes. */
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} OSPI_TransferType;
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#define OSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
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(OSPI_LUT_INSTR0_CMD_NAME(cmd0) | OSPI_LUT_INSTR0_PAD_NUM(pad0) | OSPI_LUT_INSTR0_DRV_CMD(op0) | \
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OSPI_LUT_INSTR1_CMD_NAME(cmd1) | OSPI_LUT_INSTR1_PAD_NUM(pad1) | OSPI_LUT_INSTR1_DRV_CMD(op1))
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/********* Global Functions ************/
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/**
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* @brief Initialize OSPI configuration
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*
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* @param base OSPI peripheral base address
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* @param pConfig the basic configurations of the OSPI
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*/
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void OSPI_Init(OSPI_Type *base, const OSPI_ConfigType *const pConfig);
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/**
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* @brief Get OSPI configuration
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*
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* @param config the basic configurations of the OSPI
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*/
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void OSPI_GetDefaultConfig(OSPI_ConfigType *config);
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/**
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* @brief De-initialize the OSPI
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*
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* @param base OSPI peripheral base address
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*/
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void OSPI_DeInit(OSPI_Type *base);
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/**
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* @brief OSPI Config Flash Parameter
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*
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* @param base OSPI peripheral base address
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* @param pConfig the basic configurations of the OSPI
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*/
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void OSPI_FlashConfig(OSPI_Type *base, OSPI_DeviceConfigType *pConfig);
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/**
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* @brief OSPI Config LUT
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*
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* @param base OSPI peripheral base address
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* @param index index to be written
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* @param cmd Command sequence array
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* @param count Number of sequences
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*
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*/
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void OSPI_UpdateLUT(OSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count);
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/**
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* @brief OSPI Wait bus command transaction done
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*
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* @param base OSPI peripheral base address
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* @return OSPI_StatusType whether the operation is successfully
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*/
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OSPI_StatusType OSPI_Wait_Cmd_Done(OSPI_Type *base);
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/**
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* @brief OSPI Wait bus command transaction done
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*
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* @param base OSPI peripheral base address
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* @return OSPI_StatusType whether the operation is successfully
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*/
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OSPI_StatusType OSPI_Wait_Bus_Idle(OSPI_Type *base);
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/**
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* @brief OSPI write fifo，fifo size is 16words.
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*
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* @param base OSPI peripheral base address
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* @param u8SeqId the cmd id location in lut.
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* @param pBuf the write buffer start address.
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* @param u8Size fifo size to be written.
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* @return OSPI_StatusType whether the operation is successfully
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*/
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OSPI_StatusType OSPI_Write_Fifo(OSPI_Type *base, uint8_t u8SeqId, uint32_t *pBuf, uint16_t u16Size);
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/**
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* @brief OSPI read fifo，fifo size is 16words.
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*
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* @param base OSPI peripheral base address
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* @param u8SeqId the cmd id location in lut.
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* @param pBuf the read buffer start address.
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* @param u8Size fifo size to be read.
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* @return OSPI_StatusType whether the operation is successfully
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*/
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OSPI_StatusType OSPI_Read_Fifo(OSPI_Type *base, uint8_t u8SeqId, uint32_t *pBuf, uint16_t u16Size);
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/**
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* @brief OSPI blocking transfer data.
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*
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* @param base OSPI peripheral base address
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* @param xfer pointer to the transfer structure
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* @return OSPI_StatusType whether the operation is successfully
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*/
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OSPI_StatusType OSPI_TransferBlocking(OSPI_Type *base, OSPI_TransferType *xfer);
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/**
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* @brief OSPI non-blocking transfer data.
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*
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* @param base OSPI peripheral base address
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* @param xfer pointer to the transfer structure
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* @return OSPI_StatusType whether the operation is successfully
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*/
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OSPI_StatusType OSPI_TransferNonBlocking(OSPI_Type *base, OSPI_TransferType *xfer);
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/*!
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* @brief Gets OSPI IP rx fifo address for DMA transfer.
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*
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* @param base OSPI peripheral base address.
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* @return The rx fifo address.
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*/
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static inline uint32_t OSPI_GetRxFifoAddress(OSPI_Type *base)
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{
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return OSPI_HWA_GetRFDRAddr(base);
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}
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/*!
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* @brief Enables or disables OSPI IP Rx FIFO DMA requests.
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*
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* @param base OSPI peripheral base address.
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* @param u8Enable Enable flag for receive DMA request. Pass true for enable, false for disable.
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*/
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static inline void OSPI_EnableRxDMA(OSPI_Type *base, uint8_t u8Enable)
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{
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OSPI_HWA_SetRxDMA(base, u8Enable);
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}
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/*!
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* @brief Set OSPI Rx watermark value.
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*
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* @param base OSPI peripheral base address.
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* @param u8Value Rx watermark value.
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*/
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static inline void OSPI_SetRxWatermark(OSPI_Type *base, uint8_t u8Value)
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{
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OSPI_HWA_SetRxFifoWaterMark(base, u8Value);
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}
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/*!
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* @brief Gets OSPI IP tx fifo address for DMA transfer.
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*
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* @param base OSPI peripheral base address.
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* @return The tx fifo address.
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*/
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static inline uint32_t OSPI_GetTxFifoAddress(OSPI_Type *base)
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{
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return OSPI_HWA_GetTFDRAddr(base);
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}
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/*!
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* @brief Enables or disables OSPI IP Tx FIFO DMA requests.
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*
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* @param base OSPI peripheral base address.
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* @param u8Enable Enable flag for transmit DMA request. Pass true for enable, false for disable.
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*/
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static inline void OSPI_EnableTxDMA(OSPI_Type *base, uint8_t u8Enable)
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{
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OSPI_HWA_SetTxDMA(base, u8Enable);
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}
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/*!
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* @brief Set OSPI Tx watermark value.
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*
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* @param base OSPI peripheral base address.
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* @param u8Value Tx watermark value.
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*/
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static inline void OSPI_SetTxWatermark(OSPI_Type *base, uint8_t u8Value)
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{
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OSPI_HWA_SetTxFifoWaterMark(base, u8Value);
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}
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/**
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* @brief OSPI interrupt driver handler
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*
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* @param base OSPI peripheral base address
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*/
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void OSPI_DriverIRQHandler(OSPI_Type *base);
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#if defined(__cplusplus)
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}
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#endif
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/** @} */
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#endif /* #if OSPI_INSTANCE_COUNT > 0U */
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#endif /* _DRIVER_MODULE_DRIVER_OSPI_H_ */
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