465 lines
16 KiB
C
465 lines
16 KiB
C
/**
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* @file module_driver_msc.h
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* @author flagchip
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* @brief MSC driver type definition and API
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* @version 2.0.0
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* @date 2024-08-20
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*
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* SDK Version: 2.6.0
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*
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* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2023-12-15 Flagchip084 N/A First version for FC7300
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* 2.0.0 2024-10-12 Flagchip084 N/A Change version and release
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******************************************************************************** */
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#ifndef _DRIVER_MODULE_DRIVER_MSC_H_
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#define _DRIVER_MODULE_DRIVER_MSC_H_
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#include "HwA_msc.h"
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#if MSC_INSTANCE_COUNT > 0U
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/**
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* @addtogroup module_driver_msc
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* @{
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*/
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#ifndef MSC_DEV_ERROR_REPORT
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#define MSC_DEV_ERROR_REPORT STD_OFF
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#endif
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#if MSC_DEV_ERROR_REPORT == STD_ON
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#define MSC_ReportDevError(func, error) ReportDevError(MSC_MODULE_ID, func, error)
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#endif
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/**
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* @name MSC API Service IDs
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*
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* @{
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*/
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#define MSC_INIT_ID 0x00U
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#define MSC_DEINIT_ID 0x01U
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#define MSC_INIT_STRUCTURE_ID 0x02U
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#define MSC_INIT_INTERRUPT_ID 0x03U
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#define MSC_SEL_TRANSMITTING_SOURCE_ID 0x04U
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#define MSC_SET_EMERGENCY_LOAD_ID 0x05U
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#define MSC_SET_IO_CONTROL_ID 0x06U
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#define MSC_ENABLE_ID 0x07U
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#define MSC_DISABLE_ID 0x08U
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#define MSC_SET_DATA_FRAME_ID 0x09U
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#define MSC_SEND_DATA_FRAME_ID 0x0AU
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#define MSC_SEND_COMMAND_FRAME_ID 0x0BU
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#define MSC_GET_RECEIVED_FRAME_ADDR_ID 0x0CU
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#define MSC_GET_RECEIVED_FRAME_ID 0x0DU
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#define MSC_GET_INTERRUPT_STATUS_ID 0x0EU
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#define MSC_ENABLE_TRANSMIT_ID 0x0FU
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#define MSC_CLEAR_DATA_FRAME_INTERRUPT_FLAG_ID 0x10U
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#define MSC_CLEAR_COMMAND_FRAME_INTERRUPT_FLAG_ID 0x11U
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#define MSC_CLEAR_TIME_FRAME_INTERRUPT_FLAG_ID 0x12U
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#define MSC_CLEAR_RECEIVE_INTERRUPT_FLAG_ID 0x13U
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#define MSC_CLEAR_TIMEOUT_INTERRUPT_FLAG_ID 0x14U
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/** @} */
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/**
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* @name FTU Dev Error Code
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* @brief Error Code of calling FTU apis
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*
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* @{
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*/
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#define MSC_E_PARAM_INSTANCE 0x01U
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#define MSC_E_PARAM_RXINDEX 0x02U
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#define MSC_E_PARAM_POINTER 0x03U
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#define MSC_E_PARAM_BITLENGTH 0x04U
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/** @}*/
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#define MSC_INSTANCE_0 0U /*!< MSC instance 0 is selected. */
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#define MSC_INSTANCE_1 1U /*!< MSC instance 1 is selected. */
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typedef uint8_t MSC_InstanceType;
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typedef enum
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{
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MSC_RETURN_OK = 0x00U, /*!< The SENT operation is succeeded */
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MSC_RETURN_E_NOT_OK = 0x01U, /*!< The SENT operation is failed */
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MSC_RETURN_E_PARAM = 0x04U, /*!< The SENT parameter is incorrect or out of range. */
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} MSC_ReturnType;
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typedef enum
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{
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MSC_RDR0 = 0x0U,
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MSC_RDR1 = 0x1U,
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MSC_RDR2 = 0x2U,
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MSC_RDR3 = 0x3U,
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MSC_RDRx_COUNT = 0x4U
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} MSC_RDRxIndexType;
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typedef enum
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{
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MSC_RFIE_DISABLE = 0x0U, /*!< Interrupt generation disabled. */
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MSC_RFIE_MODE1 = 0x1U, /*!< The interrupt is generated when data is received and written into the RDRx. */
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MSC_RFIE_MODE2 = 0x2U, /*!< The interrupt is generated when received data is not equal to 0. */
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MSC_RFIE_MODE3 = 0x3U /*!< The interrupt is generated when data is received and written into register RDR3. */
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} MSC_RFIEModeType;
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typedef enum
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{
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MSC_DFIE_DISABLE = 0x0U, /*!< Disable. */
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MSC_DFIE_MODE1 = 0x1U, /*!< Interrupt is generated when the last data bit has been shifted. */
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MSC_DFIE_MODE2 = 0x2U /*!< Interrupt is generated when the first data bit has been shifted. */
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} MSC_DFIEModeType;
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typedef struct _MSC_HandleType
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{
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MSC_InstanceType eInstance;
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uint8_t reserve0[3];
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struct
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{
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void (*pISRCallback)(const struct _MSC_HandleType *pMscHandle, const uint32_t u32Status);
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void (*pTOISRCallback)(const struct _MSC_HandleType *pMscHandle);
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bool bToEnableFlag;
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} tSettings;
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} MSC_HandleType;
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/** @brief MSC interrupt configure structure. */
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typedef struct
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{
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bool bCFIntEnable; /*!< MSC_INCR[CFIE] bit, interrupt enable, if this bit asserted, command frame can lead the interrupt. */
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bool bTFIntEnable; /*!< MSC_INCR[TFIE] bit, interrupt enable, if this bit asserted, time frame can lead the interrupt. */
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MSC_RFIEModeType eRFIEMode; /*!< Interrupt mode of RFIE. */
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MSC_DFIEModeType eDFIEMode; /*!< Interrupt mode of DFIE. */
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bool bTOIntEnable; /*!< Enable the interrupt of timeout. */
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uint16_t u16TimeoutValue; /*!< Timeout value of timeout interrupt. */
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void (*pISRCallback)(const MSC_HandleType *pMscHandle, const uint32_t u32Status);
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void (*pTOISRCallback)(const MSC_HandleType *pMscHandle);
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} MSC_InterruptCfgType;
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/**
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* @brief MSC Channel ISR callback function prototype
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*
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*/
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typedef void (*MSC_ISRCallbackType)(const MSC_HandleType *pMscHandle, const uint32_t u32Status);
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typedef enum
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{
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MSC_SDI_SEL_SDI0 = 0x0U, /*!< SDI0 input is selected for SDI. */
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MSC_SDI_SEL_SDI1 = 0x1U, /*!< SDI1 input is selected for SDI. */
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MSC_SDI_SEL_SDI2 = 0x2U, /*!< SDI2 input is selected for SDI. */
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MSC_SDI_SEL_SDI3 = 0x3U, /*!< SDI3 input is selected for SDI. */
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MSC_SDI_SEL_SDI4 = 0x4U, /*!< SDI4 input is selected for SDI. */
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MSC_SDI_SEL_SDI5 = 0x5U, /*!< SDI5 input is selected for SDI. */
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MSC_SDI_SEL_SDI6 = 0x6U, /*!< SDI6 input is selected for SDI. */
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MSC_SDI_SEL_SDI7 = 0x7U /*!< SDI7 input is selected for SDI. */
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} MSC_SDISelectionType;
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typedef enum
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{
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MSC_ENC_SEL_EN0 = 0x0U, /*!< EN0 is selected for ENC. */
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MSC_ENC_SEL_EN1 = 0x1U, /*!< EN1 is selected for ENC. */
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MSC_ENC_SEL_EN2 = 0x2U, /*!< EN2 is selected for ENC. */
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MSC_ENC_SEL_EN3 = 0x3U /*!< EN3 is selected for ENC. */
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} MSC_ENCSelectionType;
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typedef enum
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{
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MSC_ENH_SEL_EN0 = 0x0U, /*!< EN0 is selected for ENH. */
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MSC_ENH_SEL_EN1 = 0x1U, /*!< EN1 is selected for ENH. */
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MSC_ENH_SEL_EN2 = 0x2U, /*!< EN2 is selected for ENH. */
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MSC_ENH_SEL_EN3 = 0x3U /*!< EN3 is selected for ENH. */
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} MSC_ENHSelectionType;
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typedef enum
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{
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MSC_ENL_SEL_EN0 = 0x0U, /*!< EN0 is selected for ENL. */
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MSC_ENL_SEL_EN1 = 0x1U, /*!< EN1 is selected for ENL. */
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MSC_ENL_SEL_EN2 = 0x2U, /*!< EN2 is selected for ENL. */
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MSC_ENL_SEL_EN3 = 0x3U /*!< EN3 is selected for ENL. */
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} MSC_ENLSelectionType;
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typedef enum
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{
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MSC_FLC_ACTIVE_ON_FRAMES = 0x0U, /*!< FCL is actived only during the active phases of frames. */
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MSC_FLC_ALWAYS_ACTIVE = 0x1U /*!< FCL is always active whether or not a downstream frame is transmitted currently.. */
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} MSC_FCLControlType;
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typedef enum
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{
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MSC_INPUT_IDENTICAL = 0x0U, /*!< SDI and SI signal polarities are identical. */
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MSC_INPUT_INVERTED = 0x1U /*!< SDI and SI signal polarities are inverted. */
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} MSC_InputPolarityType;
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typedef enum
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{
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MSC_ENX_IDENTICAL = 0x0U, /*!< Enx and ENL, ENH, ENC signal polarities are identical (high active). */
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MSC_ENX_INVERTED = 0x1U /*!< ENx and ENL, ENH, ENC signal polarities are inverted (low active). */
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} MSC_ENxPolarityType;
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typedef enum
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{
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MSC_SO_IDENTICAL = 0x0U, /*!< SOP and SO signal polarity is identical. */
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MSC_SO_INVERTED = 0x1U /*!< SOP and SO signal polarity is inverted. */
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} MSC_SOPolarityType;
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typedef enum
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{
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MSC_FLC_IDENTICAL = 0x0U, /*!< FCLP and FCL polarity is identical. */
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MSC_FLC_INVERTED = 0x1U /*!< FCLP and FCL polarity is inverted. */
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} MSC_FCLpolarityType;
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typedef struct
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{
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MSC_SDISelectionType eSDIsel; /*!< SDI seletion. */
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MSC_ENCSelectionType eENCSel; /*!< ENC seletion. */
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MSC_ENHSelectionType eENHSel; /*!< ENH seletion. */
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MSC_ENLSelectionType eENLSel; /*!< ENL seletion. */
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MSC_FCLControlType eFclCtrl; /*!< FCL Control. */
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MSC_InputPolarityType eSDIPol; /*!< SDI Polarity. */
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MSC_ENxPolarityType eENXPol; /*!< ENX Polarity. */
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MSC_SOPolarityType eSOPPol; /*!< SO Polarity. */
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MSC_FCLpolarityType eFCLPPol; /*!< FCL Polarity. */
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} MSC_IOControlInitType;
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typedef enum
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{
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MSC_TRANS_SOURCE_DATA_REG = 0x0U, /*!< SSL[x] is taken from TCDAR.DL[x]. */
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MSC_TRANS_SOURCE_ALTIN = 0x2U, /*!< SSL[x] is taken from the ALTINL input line x. */
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MSC_TRANS_SOURCE_ALTIN_INV = 0x3U, /*!< SSL[x] is taken from the ALTINL input line x in inverted state. */
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} MSC_TransSourceType;
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typedef enum
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{
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MSC_TRIGGER_MODE = 0x00U, /*!< Trigger work mode. */
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MSC_REPETITION_MODE = 0x01U /*!< Repetition work mode. */
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} MSC_WorkModeType;
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typedef enum
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{
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MSC_EVEN_PARITY = 0x00U, /*!< Reception even parity. */
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MSC_ODD_PARITY = 0x01U /*!< Reception odd parity. */
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} MSC_ParityType;
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typedef enum
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{
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MSC_RECEIVE_DISABLED = 0x00U, /*!< Receiving channel is disabled. */
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MSC_BAUDRATE_FMSC_DIV4 = 0x01U, /*!< Baud rate=fmsc/4. */
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MSC_BAUDRATE_FMSC_DIV8 = 0x02U, /*!< Baud rate=fmsc/8. */
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MSC_BAUDRATE_FMSC_DIV16 = 0x03U, /*!< Baud rate=fmsc/16. */
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MSC_BAUDRATE_FMSC_DIV32 = 0x04U, /*!< Baud rate=fmsc/32. */
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MSC_BAUDRATE_FMSC_DIV64 = 0x05U, /*!< Baud rate=fmsc/64. */
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MSC_BAUDRATE_FMSC_DIV128 = 0x06U, /*!< Baud rate=fmsc/128. */
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MSC_BAUDRATE_FMSC_DIV256 = 0x07U /*!< Baud rate=fmsc/256. */
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} MSC_ReceiveBaudRateType;
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typedef enum
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{
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MSC_FRAME_12_BIT = 0x00U, /*!< 12-bit frame selected. */
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MSC_FRAME_16_BIT = 0x01U /*!< 16-bit frame selected. */
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} MSC_ReceiveFrameType;
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typedef struct
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{
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uint8_t u8PassiveLength; /*!< Frame Passive length. */
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uint8_t u8PTFNumber; /*!< The number of passive time frames that are inserted in repetition mode between two data frames. */
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MSC_WorkModeType eWorkMode; /*!< MSC work mode. */
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uint8_t u8CommandBitLength; /*!< Bit length of command frame. */
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bool bSelSRH; /*!< Select SRH. */
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uint8_t u8SRHDataBitLength; /*!< Bit length of SRH. */
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bool bSelSRL; /*!< Select SRL. */
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uint8_t u8SRLDataBitLength; /*!< Bit length of SRL. */
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bool bDelayControl; /*!< Hardware Receive Interrupt Delay Control. */
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MSC_ParityType eParity; /*!< Parity mode. */
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MSC_ReceiveBaudRateType eBaudRate; /*!< Baudrate. */
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MSC_ReceiveFrameType eRsvFrameType; /*!< Frame type. */
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} MSC_InitCfgType;
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/**
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* @brief Initialize the MSC structure with the provided configuration.
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*
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* @param pInitConfig Pointer to the MSC initialization configuration structure.
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* @return MSC_ReturnType Returns MSC_RETURN_OK if the initialization is successful,
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* otherwise returns an error code indicating the failure.
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*/
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MSC_ReturnType MSC_InitStructure(MSC_InitCfgType *pInitConfig);
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/**
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* @brief Init the MSC.
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*
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* @param pMscHandle InstanceHandle
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* @param pInitConfig MSCInstance initial configuration.
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*/
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MSC_ReturnType MSC_Init(MSC_HandleType *pMscHandle, const MSC_InitCfgType *pInitConfig);
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/**
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* @brief De-initialize the MSC.
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*
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* This function de-initializes the MSC module, resetting it to its default state.
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*
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* @param pMscHandle Pointer to the MSC handle structure.
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* @return MSC_ReturnType Returns MSC_RETURN_OK if de-initialization is successful,
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* otherwise returns an error code indicating the failure.
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*/
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MSC_ReturnType MSC_DeInit(MSC_HandleType *pMscHandle);
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/**
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* @brief Init the MSC interrupt.
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*
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* @param pMscHandle InstanceHandle
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* @param pInteruptConfig MSCInstance interrupt configuration.
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*/
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void MSC_initInterrupt(MSC_HandleType *pMscHandle, const MSC_InterruptCfgType *pInteruptConfig);
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/**
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* @brief Select the transmitting sources.
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*
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* @param pMscHandle InstanceHandle
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* @param u32SourceMask Transmitting sources.
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* @param eSourceType Transmitting sources type.
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*/
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void MSC_SelTranmittingSource(const MSC_HandleType *pMscHandle, uint32_t u32SourceMask, MSC_TransSourceType eSourceType);
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/**
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* @brief Set Emergency load value.
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*
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* @param pMscHandle InstanceHandle
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* @param u32Value Emergency load value.
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*/
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void MSC_SetEmergencyLoad(const MSC_HandleType *pMscHandle, uint32_t u32Value);
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/**
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* @brief Configure the MSC IO control.
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*
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* @param pMscHandle InstanceHandle
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* @param pIOConfig MSC IO control configuration.
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*/
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void MSC_SetIOControl(const MSC_HandleType *pMscHandle, const MSC_IOControlInitType *pIOConfig);
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/**
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* @brief Enable MSC.
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*
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* @param pMscHandle InstanceHandle
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*/
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void MSC_Enable(const MSC_HandleType *pMscHandle);
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/**
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* @brief Disable MSC.
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*
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* @param pMscHandle InstanceHandle
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*/
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void MSC_Disable(const MSC_HandleType *pMscHandle);
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/**
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* @brief MSC set data frame.
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*
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* @param pMscHandle InstanceHandle
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* @param u32Data Data to be sent.
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*/
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void MSC_SetDataFrame(const MSC_HandleType *pMscHandle, uint32_t u32Data);
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/**
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* @brief MSC send data frame.
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*
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* @param pMscHandle InstanceHandle
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*/
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void MSC_SendDataFrame(const MSC_HandleType *pMscHandle);
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/**
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* @brief MSC send command frame.
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*
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* @param pMscHandle InstanceHandle
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* @param u32Command command to be sent.
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*/
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void MSC_SendCommandFrame(const MSC_HandleType *pMscHandle, uint32_t u32Command);
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/**
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* @brief Get the msc received data address.
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*
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* @param pMscHandle InstanceHandle
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* @param eIndex Receive data register index.
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* @return uint8_t Receiverd data address.
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*/
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uint8_t MSC_GetReceivedFrameAddr(const MSC_HandleType *pMscHandle, MSC_RDRxIndexType eIndex);
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/**
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* @brief Get the msc received data.
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*
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* @param pMscHandle InstanceHandle
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* @param eIndex Receive data register index.
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* @param pData Received data value.
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* @return MSC_ReceiveStatusType Status of getting received data.
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*/
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MSC_ReceiveStatusType MSC_GetReceivedFrame(const MSC_HandleType *pMscHandle, MSC_RDRxIndexType eIndex, uint8_t *pData);
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/**
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* @brief Get the msc interrupt status.
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*
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* @param pMscHandle InstanceHandle
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* @return uint32_t Interrupt status.
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*/
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uint32_t MSC_GetInterruptStatus(const MSC_HandleType *pMscHandle);
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/**
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* @brief Get the msc interrupt status.
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*
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* @param pMscHandle InstanceHandle
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* @return uint32_t Interrupt status.
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*/
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uint32_t MSC_GetToInterruptStatus(const MSC_HandleType *pMscHandle);
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/**
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* @brief Get the msc interrupt status.
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*
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* @param pMscHandle InstanceHandle
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* @param bEnable Enable transmit channel.
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*/
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void MSC_EnableTrasmit(const MSC_HandleType *pMscHandle, bool bEnable);
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/**
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* @brief Clear the msc data frame interrupt flag.
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*
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* @param pMscHandle InstanceHandle
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*/
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void MSC_ClearDataFrameInterruptFlag(const MSC_HandleType *pMscHandle);
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/**
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* @brief Clear the msc command frame interrupt flag.
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*
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* @param pMscHandle InstanceHandle
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*/
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void MSC_ClearCommandFrameInterruptFlag(const MSC_HandleType *pMscHandle);
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/**
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* @brief Clear the msc time frame interrupt flag.
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*
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* @param pMscHandle InstanceHandle
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*/
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void MSC_ClearTimeFrameInterruptFlag(const MSC_HandleType *pMscHandle);
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/**
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* @brief Clear the msc receive interrupt flag.
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*
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* @param pMscHandle InstanceHandle
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*/
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void MSC_ClearReceiveInterruptFlag(const MSC_HandleType *pMscHandle);
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/**
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* @brief Clear the msc timeout interrupt flag.
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*
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* @param pMscHandle InstanceHandle
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*/
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void MSC_ClearTimeoutInterruptFlag(const MSC_HandleType *pMscHandle);
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void MSCn_IRQHandler(const MSC_HandleType *pMscHandle);
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/** @}*/ /* module_driver_msc. */
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#endif /* #if MSC_INSTANCE_COUNT > 0U */
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#endif
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