410 lines
13 KiB
C
410 lines
13 KiB
C
/**
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* @file module_driver_ldi.h
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* @author Flagchip
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* @brief LDI driver type definition and API
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* @version 2.0.0
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* @date 2025-06-18
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*
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* SDK Version: 2.6.0
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*
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* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
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*
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* @details
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2025-06-18 Flagchip0121 N/A Init version
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******************************************************************************** */
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#ifndef _DRIVER_MODULE_DRIVER_LDI_H_
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#define _DRIVER_MODULE_DRIVER_LDI_H_
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#include "HwA_ldi.h"
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#if LDI_INSTANCE_COUNT > 0U
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#include <stddef.h>
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/**
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* @addtogroup module_driver_ldi
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* @{
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*/
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/********* global define ************/
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/**
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* @name LDI API Service IDs
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*
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* @{
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*/
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#define LDI_Init_ID 0U
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#define LDI_Deinit_ID 1U
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#define LDI_Transmit_ID 2U
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#define LDI_Transmit_IT_ID 3U
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#define LDI_Transmit_DMA_ID 4U
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#define LDI_IRQHandler_ID 5U
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#define LDI_DmaDoneCallback_Tx_ID 6U
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/** @}*/
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/**
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* @name LDI Dev Error Code
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* @brief Error Code of calling GPIO apis
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*
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* @{
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*/
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#define LDI_E_PARAM_INSTANCE 0x01U
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#define LDI_E_PARAM_INPUT 0x02U
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#define LDI_E_PARAM_STATUS 0x03U
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/** @}*/
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/** @brief Ldi rcfg max */
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#define LDI_RCFG_MAX 255U
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/** @brief Ldi gclk start max */
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#define LDI_GCLK_START_MAX 255U
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/** @brief Ldi gclk end max */
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#define LDI_GCLK_START_END 255U
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/** @brief Ldi gclk period max */
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#define LDI_GCLK_PERIOD_MAX 32767U
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/** @brief Ldi signal window start max */
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#define LDI_SIGNAL_WINDOW_START_MAX 255U
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/** @brief Ldi signal window end max */
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#define LDI_SIGNAL_WINDOW_END_MAX 255U
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/********* global typedef ************/
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/** @brief Ldi pull status */
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typedef enum
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{
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LDI_PULL_DOWN = 0U,
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LDI_PULL_UP
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} LDI_PullStatusType;
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/** @brief Gpio direction */
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typedef enum
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{
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LDI_GPIO_OUT = 0U,
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LDI_GPIO_IN,
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LDI_GPIO_ZERO
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} LDI_GpioDirType;
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/** @brief Gpio initialization level */
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typedef enum
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{
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LDI_GPIO_LOW = 0U,
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LDI_GPIO_HIGH
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} LDI_GpioLevelType;
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/** @brief Ldi Dclk source */
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typedef enum
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{
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LDI_DCLK_SDR_MODE = 0U,
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LDI_DCLK_DDR_MODE
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} LDI_DclkSrcType;
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/** @brief Ldi Gclk source */
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typedef enum
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{
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LDI_GCLK_SDR_CLK = 0U,
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LDI_GCLK_DDR_CLK,
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LDI_GCLK_GCLKDIV_CLK
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} LDI_GclkSrcType;
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/** @brief Ldi Gclk prediv source */
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typedef enum
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{
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LDI_GCLKPREDIV_BY1 = 0U, /**< Divided by 1. */
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LDI_GCLKPREDIV_BY2 = 1U, /**< Divided by 2. */
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LDI_GCLKPREDIV_BY3 = 2U, /**< Divided by 3. */
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LDI_GCLKPREDIV_BY4 = 3U, /**< Divided by 4. */
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LDI_GCLKPREDIV_BY5 = 4U, /**< Divided by 5. */
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LDI_GCLKPREDIV_BY6 = 5U, /**< Divided by 6. */
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LDI_GCLKPREDIV_BY7 = 6U, /**< Divided by 7. */
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LDI_GCLKPREDIV_BY8 = 7U, /**< Divided by 8. */
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LDI_GCLKPREDIV_BY9 = 8U, /**< Divided by 9. */
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LDI_GCLKPREDIV_BY10 = 9U, /**< Divided by 10. */
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LDI_GCLKPREDIV_BY11 = 10U, /**< Divided by 11. */
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LDI_GCLKPREDIV_BY12 = 11U, /**< Divided by 12. */
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LDI_GCLKPREDIV_BY13 = 12U, /**< Divided by 13. */
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LDI_GCLKPREDIV_BY14 = 13U, /**< Divided by 14. */
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LDI_GCLKPREDIV_BY15 = 14U, /**< Divided by 15. */
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LDI_GCLKPREDIV_BY16 = 15U /**< Divided by 16. */
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} LDI_GCLkPredivType;
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/** @brief Ldi DDR/SDR prediv source */
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typedef enum
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{
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LDI_DDRSDRPREDIV_BY1 = 0U, /**< Divided by 1. */
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LDI_DDRSDRPREDIV_BY2 = 1U, /**< Divided by 2. */
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LDI_DDRSDRPREDIV_BY4 = 2U, /**< Divided by 4. */
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LDI_DDRSDRPREDIV_BY8 = 3U, /**< Divided by 8. */
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LDI_DDRSDRPREDIV_BY12 = 4U, /**< Divided by 12. */
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LDI_DDRSDRPREDIV_BY16 = 5U /**< Divided by 16. */
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} LDI_DdrSdrPredivType;
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/** @brief Ldi Spread Direction */
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typedef enum
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{
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LDI_SPREAD_DECREASE = 0U, /**< Spread decrease. */
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LDI_SPREAD_INCREASE = 1U /**< Spread increase. */
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} LDI_SpreadDirectType;
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/** @brief Ldi Spread Mode prediv source */
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typedef enum
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{
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LDI_DISABLE_SPREAD_SPECTRUM = 0U, /**< Disable Spread Spectrum Mode. */
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LDI_2BIT_RADND_DATA = 1U, /**< Divider will update with 2-bit random data. */
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} LDI_SpreadModeType;
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/** @brief LDI instance number */
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typedef enum
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{
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LDI0 = 0U,
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} LDI_InstanceType;
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/**
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* @brief LDI states
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*
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*/
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typedef enum {
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LDI_STATE_UNINIT = 0x00U, /*!< Peripheral not Initialized */
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LDI_STATE_IDLE = 0x01U, /*!< Peripheral Initialized and idle for use */
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LDI_STATE_BUSY = 0x02U /*!< an internal process is ongoing */
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} LDI_StateType;
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/**
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* @brief LDI states
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*
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*/
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typedef enum {
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LDI_STATUS_SUCCESS = 0x0U, /*!< The LDI operation is succeed */
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LDI_STATUS_ERROR = 0x1U, /*!< The LDI operation is failed */
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LDI_STATUS_TIMEOUT = 0x2U /*!< The LDI operation is failed because of time out */
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} LDI_StatesType;
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/**
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* @brief LDI display states
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*
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*/
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typedef enum {
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LDI_DISPLAY_STOP = 0x00U, /*!< LDI START display */
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LDI_DISPLAY_START = 0x01U, /*!< LDI STOP display */
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} LDI_DisplayStateType;
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/**
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* @brief LDI data bit order
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*
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*/
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typedef enum
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{
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LDI_MSB_FIRST = 0, /**< most significant bit first handle, from msb to lsb */
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LDI_LSB_FIRST = 1 /**< least significant bit first handle, from lsb to msb */
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} LDI_DataFirstBitType;
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/** @brief Ldi dclk configuration structure */
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typedef struct
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{
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LDI_DclkSrcType eLdiDclkMode; /**< Ldi clock mode */
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uint8_t RESERVED_0[3];
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} LDI_DclkCfg;
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/** @brief Ldi gclk configuration structure */
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typedef struct
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{
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LDI_GclkSrcType eLdiGclkSrc; /**< Ldi Gclk source */
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LDI_GCLkPredivType eLdiGclkDivider; /**< Ldi Gclk Prediv mode */
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uint8_t RESERVED_0[2];
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} LDI_GclkCfg;
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/** @brief Ldi clock configuration structure */
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typedef struct
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{
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LDI_GclkCfg tGclkcfg; /**< Ldi Gclk config */
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LDI_DclkCfg tDclkcfg; /**< Ldi Dclk config */
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LDI_DdrSdrPredivType eDdrSdrDivider; /**< Ldi Ddr and Sdr Prediv config */
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boolean bDdrSdrDelayEn; /**< Ldi Ddr and Sdr delay enable */
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LDI_SpreadModeType eSpreadMode; /**< Ldi Spread Mode Prediv mode */
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LDI_SpreadDirectType eSpreadDirect; /**< Ldi Spread Direction mode */
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} LDI_ClkCfg;
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/** @brief Ldi clock configuration structure */
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typedef struct
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{
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uint32_t u32Rows; /**< Ldi Gclk config */
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uint32_t u32Channels; /**< Ldi Dclk config */
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uint32_t u32Cascds; /**< Ldi Ddr and Sdr Prediv config */
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uint32_t u32Dnums; /**< Data nums per pixel(Size in Bytes) */
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} LDI_ScreenCfg;
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/** @brief Ldi display row configuration */
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typedef uint8_t LDI_PxdRcfgType;
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/** @brief Ldi dispaly gclk configuration structure */
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typedef struct
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{
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uint8_t u8GclkStart; /**< Cycles of SDR Clock before GCLK Active Window, Max 255*/
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uint8_t u8GclkEnd; /**< Cycles of SDR Clock after GCLK Active Window, Max 255*/
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boolean bGclkRmodeEn; /**< CLK is working in Row mode; other config will not be active when this config is enable. */
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uint8_t RESERVED_0[3];
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uint32_t u32GclkPeriod; /**< Period of GCLK Enable during Line Display, Max 32767 */
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} LDI_PxdGcfgType;
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/** @brief Pixel Display SOE Configuration structure */
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typedef struct
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{
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uint8_t u8ScfgSignalwinStart; /**< Signal Window Start, Max 255*/
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uint8_t u8ScfgSignalwinEnd; /**< Signal Window End, Max 255*/
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boolean bScfgClockModeEn; /**< Enable clock Mode */
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boolean bScfgRepeatModeEn; /**< Enable repeat Mode */
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uint8_t RESERVED_0[2];
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} LDI_PxdScfgType;
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/** @brief Pixel Display DOE Configuration structure */
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typedef struct
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{
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uint8_t u8DcfgSignalwinStart; /**< Signal Window Start, Max 255*/
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uint8_t u8DcfgSignalwinEnd; /**< Signal Window End, Max 255*/
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boolean bDcfgClockModeEn; /**< Enable clock Mode */
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boolean bDcfgRepeatModeEn; /**< Enable repeat Mode */
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uint8_t RESERVED_0[2];
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} LDI_PxdDcfgType;
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/** @brief Pixel Display SDI Configuration structure */
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typedef struct
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{
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uint8_t u8IcfgSignalwinStart; /**< Signal Window Start, Max 255*/
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uint8_t u8IcfgSignalwinEnd; /**< Signal Window End, Max 255*/
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boolean bIcfgClockModeEn; /**< Enable clock Mode */
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boolean bIcfgRepeatModeEn; /**< Enable repeat Mode */
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uint8_t RESERVED_0[2];
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} LDI_PxdIcfgType;
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/** @brief Ldi display configuration structure */
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typedef struct
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{
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LDI_PxdRcfgType u8PxdRcfg; /**< Pixel Display Row Configuration */
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uint8_t RESERVED_0[3];
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LDI_PxdGcfgType tPxdGcfg; /**< Pixel Display GCLK Configuration */
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LDI_PxdScfgType tPxdScfg; /**< Pixel Display SOE Configuration */
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LDI_PxdDcfgType tPxdDcfg; /**< Pixel Display DOE Configuration */
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LDI_PxdIcfgType tPxdIcfg; /**< Pixel Display SDI Configuration */
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} LDI_DisplayCfg;
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/** @brief Ldi update channel configuration structure */
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typedef struct
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{
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boolean bChannel0En; /**< Enable channel 0, channel 0 must config */
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boolean bChannel1En; /**< Enable channel 1 */
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boolean bChannel2En; /**< Enable channel 2 */
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boolean bChannel3En; /**< Enable channel 3 */
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} LDI_EnChannelType;
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/** @brief Ldi initialization structure */
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typedef struct
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{
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const uint16_t *pLdiData0; /**< Ldi channel 0 data */
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const uint16_t *pLdiData1; /**< Ldi channel 1 data */
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const uint16_t *pLdiData2; /**< Ldi channel 2 data */
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const uint16_t *pLdiData3; /**< Ldi channel 3 data */
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uint32_t u32LdiDatalen; /**< The LDI updates the data length, and the data length is the same for all channels */
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} LDI_UpdateType;
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/**
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* @brief The structure of the LDI processing handle
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*
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*/
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typedef struct _LDI_HandleType
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{
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LDI_InstanceType eInstance; /*!< LDI instance*/
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uint8_t RESERVED_0[3];
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struct
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{
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LDI_StateType eLdiState; /*!< LDI state*/
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LDI_DisplayStateType eLdiDisplayState; /*!< LDI display state*/
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uint8_t RESERVED_0[2];
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LDI_EnChannelType tChannelState; /*!< LDI channel state*/
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void (*pUpdateCallback)(void);
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} tStatus;
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} LDI_HandleType;
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/** @brief Ldi initialization structure */
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typedef struct
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{
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LDI_ClkCfg tClkcfg; /**< Ldi Clk config */
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LDI_ScreenCfg tScreencfg; /**< Ldi screen config */
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LDI_DisplayCfg tDisplayfg; /**< Ldi display config */
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LDI_EnChannelType tEnChannelfg; /**< Ldi enable channel config */
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LDI_DataFirstBitType eBitOrder; /**< MSB or LSB */
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uint8_t RESERVED_0[3];
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void (*pUpdateCallback)(void);
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} LDI_InitType;
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/********* global API ************/
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/**
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* @brief Initialize ldi
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*
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* @param pLdiHandle pLdiHandle LDI handle for LDI functionality
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* @param pInitStruct Initialization structure of ldi
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*/
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void LDI_Init(LDI_HandleType *pLdiHandle, const LDI_InitType *const pInitStruct);
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/**
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* @brief De-initialize the Ldi instance
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*
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* @param pLdiHandle pLdiHandle LDI handle for LDI functionality
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*/
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void LDI_Deinit(LDI_HandleType *pLdiHandle);
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/**
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* @brief Update data in poll mode (block)
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*
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* @param pLdiHandle pLdiHandle LDI handle for LDI functionality
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* @param pUpdateStruct Ldi update data struct
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*
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* @return LDI_StatesType
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*/
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LDI_StatesType LDI_Update(LDI_HandleType *pLdiHandle, const LDI_UpdateType *const pUpdateStruct);
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/**
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* @brief Update data in DMA mode (Non-block)
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*
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* @param pLdiHandle pLdiHandle LDI handle for LDI functionality
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* @param pUpdateStruct Ldi update data struct
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*
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* @return LDI_StatesType
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*/
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LDI_StatesType LDI_Update_DMA(LDI_HandleType *pLdiHandle, const LDI_UpdateType *const pUpdateStruct);
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/**
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* @brief Ldi start display
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*
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* @param pLdiHandle pLdiHandle LDI handle for LDI functionality
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*/
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void LDI_Dispaly_Start(LDI_HandleType *pLdiHandle);
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/**
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* @brief Ldi stop display
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*
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* @param pLdiHandle pLdiHandle LDI handle for LDI functionality
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*/
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void LDI_Dispaly_Stop(LDI_HandleType *pLdiHandle);
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/**
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* @brief LDIn Interrupt Handler.
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*
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* @param pLdiHandle pLdiHandle LDI handle for LDI functionality
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*/
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void LDIn_IRQHandler(LDI_HandleType *pLdiHandle);
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/** @}*/ /* module_driver_ldi */
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#endif
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#endif
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