467 lines
13 KiB
C
467 lines
13 KiB
C
/**
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* @file module_driver_ospi.c
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* @author Flagchip
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* @brief OSPI driver type definition and API
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* @version 2.0.0
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* @date 2023-08-02
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*
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* SDK Version: 2.6.0
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*
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* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
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*
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* @details
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2023-01-30 Flagchip087 N/A First version for FC7300
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* 0.2.0 2023-08-02 Flagchip100 N/A Adjust the OSPI driver framework.
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* 0.3.0 2024-08-27 Flagchip122 N/A FC7xxx sdk 2.0
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******************************************************************************** */
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#include "module_driver_ospi.h"
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#if OSPI_INSTANCE_COUNT > 0U
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/********* Local variable ************/
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#define OSPI_LUT_KEY_VAL (0xFC03FC03UL)
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#ifndef OSPI_DEV_ERROR_REPORT
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#define OSPI_DEV_ERROR_REPORT STD_OFF
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#endif
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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#define OSPI_ReportDevError(func, error) ReportDevError(OSPI_MODULE_ID, func, error)
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#endif
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/********* Global Functions ************/
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/**
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* @brief Initialize OSPI configuration
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*
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* @param base OSPI peripheral base address
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* @param config the basic configurations of the OSPI
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*/
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void OSPI_Init(OSPI_Type *base, const OSPI_ConfigType *const pConfig)
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{
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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if(pConfig == NULL_PTR )
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{
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OSPI_ReportDevError(OSPI_INIT_ID, OSPI_E_PARAM_POINTER);
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}
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else if((pConfig->bDdrEn == true) && (pConfig->eDqsSrcSel != DQS_EXTERNAL_PADINPUT))
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{
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OSPI_ReportDevError(OSPI_INIT_ID, OSPI_E_PARAM_INVALID);
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}
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else
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{
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#endif
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OSPI_HWA_SetCtrlValue(base,CTRL_RST_VALUE);
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OSPI_HWA_SetSocCfgValue(base, 0U);
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OSPI_HWA_ModuleDisable(base);
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OSPI_HWA_InternalRefclkDiv(base, pConfig->eClkDivider);
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OSPI_HWA_InternalRefclkSource(base, pConfig->eClkMux);
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OSPI_HWA_EndianSelect(base, pConfig->eEndian);
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OSPI_HWA_PadIbeEnable(base);
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OSPI_HWA_InternalRefclkEnable(base);
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OSPI_HWA_DqsInvertedEnable(base);
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OSPI_HWA_DqsSource(base, pConfig->eDqsSrcSel);
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OSPI_HWA_DqsModeEnable(base);
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if (pConfig->eDqsSrcSel == DQS_EXTERNAL_PADINPUT)
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{
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if (pConfig->bDdrEn)
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{
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OSPI_HWA_DdrClkEnable(base);
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OSPI_HWA_DdrModeEnable(base);
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}
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OSPI_HWA_ObeTimRelaxEnable(base);
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OSPI_HWA_DqsOutEnable(base);
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OSPI_HWA_DqsLatEnable(base);
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OSPI_HWA_Dio3DefLow(base);
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OSPI_HWA_Dio2DefLow(base);
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OSPI_HWA_SetDataHoldTime(base, 1);
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}
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else if (pConfig->eDqsSrcSel == DQS_PAD_LOOPBACK)
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{
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OSPI_HWA_SetSampleDlyClkCycle(base, 0);
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OSPI_HWA_SelectRefClkEdge(base, 1);
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}
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else
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{
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}
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OSPI_HWA_ModuleEnable(base);
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OSPI_HWA_ClearTxFifo(base);
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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}
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#endif
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}
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/**
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* @brief Get OSPI configuration
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*
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* @param config the basic configurations of the OSPI
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*/
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void OSPI_GetDefaultConfig(OSPI_ConfigType *config)
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{
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config->bDdrEn = true;
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config->eDqsSrcSel = DQS_EXTERNAL_PADINPUT;
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config->eClkDivider = OSPI_CLOCK_DIV_4;
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config->eClkMux = OSPI_MUX_PLL1;
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config->eEndian = OSPI_LITTLE_ENDIAN;
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}
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/**
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* @brief De-initialize the OSPI
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*
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* @param base OSPI peripheral base address
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*/
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void OSPI_DeInit(OSPI_Type *base)
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{
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/* Set register to reset value */
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OSPI_HWA_SetCtrlValue(base, CTRL_RST_VALUE);
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OSPI_HWA_SetSocCfgValue(base, 0);
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OSPI_HWA_ModuleDisable(base);
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}
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/**
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* @brief OSPI Config Flash Parameter
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*
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* @param base OSPI peripheral base address
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* @param pConfig the basic configurations of the OSPI
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*/
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void OSPI_FlashConfig(OSPI_Type *base, OSPI_DeviceConfigType *pConfig)
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{
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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if(pConfig == NULL_PTR)
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{
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OSPI_ReportDevError(OSPI_SET_FLASHCFG_ID, OSPI_E_PARAM_POINTER);
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}
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else if( (pConfig->u8CsHoldTime > (uint8_t)16) ||
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(pConfig->u8CsSetupTime > (uint8_t)16) ||
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(pConfig->u8FlashColAddressSpace > (uint8_t)16) )
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{
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OSPI_ReportDevError(OSPI_SET_FLASHCFG_ID, OSPI_E_PARAM_INVALID);
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}
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else
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{
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#endif
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OSPI_HWA_SetCsHoldTime(base, pConfig->u8CsHoldTime);
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OSPI_HWA_SetCsSetupTime(base, pConfig->u8CsSetupTime);
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OSPI_HWA_CfgDelayLine(base, pConfig->u8DelayLine);
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OSPI_HWA_SetFlashAddr(base, pConfig->u32FlashAddress);
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OSPI_HWA_SetFlashTopAddr(base, pConfig->u32FlashTopAddress);
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OSPI_HWA_SetFlashAddrMode(base, pConfig->u8WordAddressable);
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OSPI_HWA_SetColAddrSpace(base, pConfig->u8FlashColAddressSpace);
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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}
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#endif
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}
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/**
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* @brief OSPI Config LUT
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*
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* @param base OSPI peripheral base address
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* @param index index to be written
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* @param cmd Command sequence array
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* @param count Number of sequences
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*
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*/
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void OSPI_UpdateLUT(OSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
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{
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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if(cmd == NULL_PTR)
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{
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OSPI_ReportDevError(OSPI_UPDATE_LUT_ID, OSPI_E_PARAM_POINTER);
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}
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else if((count > 16U) || (index >3U))
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{
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OSPI_ReportDevError(OSPI_UPDATE_LUT_ID, OSPI_E_PARAM_INVALID);
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}
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else
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{
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#endif
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uint8_t i = 0;
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volatile uint32_t *lutBase;
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/* Wait for bus idle before change flash configuration. */
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if (OSPI_Wait_Bus_Idle(base) != OSPI_STATUS_SUCCESS)
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{
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return;
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}
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/* Unlock LUT for update. */
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base->LUT_KEY = OSPI_LUT_KEY_VAL;
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base->LUT_CFG = 0x02;
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lutBase = &base->LUT[index*4];
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for (i = 0; i < count; i++)
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{
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*lutBase = *cmd;
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lutBase++;
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cmd++;
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}
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/* Lock LUT. */
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base->LUT_KEY = OSPI_LUT_KEY_VAL;
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base->LUT_CFG = 0x01;
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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}
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#endif
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}
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/**
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* @brief OSPI Wait bus command transaction done
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*
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* @param base OSPI peripheral base address
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* @return OSPI_StatusType whether the operation is successfully
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*/
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OSPI_StatusType OSPI_Wait_Cmd_Done(OSPI_Type *base)
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{
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OSPI_StatusType eRet = OSPI_STATUS_TIMEOUT;
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uint32_t timeout = 0xfffff;
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do
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{
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if ((OSPI_HWA_GetFlag(base) & OSPI_FLAG_BUSDF_MASK ) != (uint32_t)0)
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{
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OSPI_HWA_ClearFlag(base, OSPI_FLAG_BUSDF_MASK);
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eRet = OSPI_STATUS_SUCCESS;
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break;
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}
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timeout--;
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}
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while(timeout);
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return eRet;
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}
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/**
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* @brief OSPI Wait bus command transaction done
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*
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* @param base OSPI peripheral base address
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* @return OSPI_StatusType whether the operation is successfully
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*/
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OSPI_StatusType OSPI_Wait_Bus_Idle(OSPI_Type *base)
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{
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OSPI_StatusType eRet = OSPI_STATUS_TIMEOUT;
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uint32_t timeout = 0xfffff;
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do
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{
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if ((OSPI_HWA_GetStatus(base) & OSPI_STATUS_BUSY_MASK) == (uint32_t)0)
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{
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eRet = OSPI_STATUS_SUCCESS;
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break;
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}
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timeout--;
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}
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while(timeout);
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return eRet;
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}
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/**
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* @brief OSPI write fifo，fifo size is 16words.
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*
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* @param base OSPI peripheral base address
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* @param u8SeqId the cmd id location in lut.
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* @param pBuf the write buffer start address.
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* @param u16Size fifo size to be written.
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* @return OSPI_StatusType whether the operation is successfully
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*/
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OSPI_StatusType OSPI_Write_Fifo(OSPI_Type *base, uint8_t u8SeqId, uint32_t *pBuf, uint16_t u16Size)
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{
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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if(pBuf == NULL_PTR)
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{
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OSPI_ReportDevError(OSPI_WRITE_FIFO_ID, OSPI_E_PARAM_POINTER);
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}
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else if(u8SeqId > 3U)
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{
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OSPI_ReportDevError(OSPI_WRITE_FIFO_ID, OSPI_E_PARAM_INVALID);
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}
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else
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{
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#endif
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OSPI_StatusType eRet = OSPI_STATUS_SUCCESS;
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uint8_t u8LoopI, u8LoopMax;
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/* Data Register is 32-bit, so loop should div 4 */
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u8LoopMax = (uint8_t)u16Size >> 2;
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for (u8LoopI = 0; u8LoopI < u8LoopMax; u8LoopI++)
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{
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OSPI_HWA_WriteTxData(base, pBuf[u8LoopI]);
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}
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OSPI_HWA_SetCmdIdSize(base, u8SeqId, u16Size);
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eRet = OSPI_Wait_Cmd_Done(base);
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if (eRet == OSPI_STATUS_SUCCESS)
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{
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eRet = OSPI_Wait_Bus_Idle(base);
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}
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return eRet;
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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}
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#endif
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}
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/**
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* @brief OSPI read fifo，fifo size is 16words.
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*
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* @param base OSPI peripheral base address
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* @param u8SeqId the cmd id location in lut.
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* @param pBuf the read buffer start address.
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* @param u32Size fifo size to be read.
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* @return OSPI_StatusType whether the operation is successfully
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*/
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OSPI_StatusType OSPI_Read_Fifo(OSPI_Type *base, uint8_t u8SeqId, uint32_t *pBuf, uint16_t u16Size)
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{
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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if(pBuf == NULL_PTR)
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{
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OSPI_ReportDevError(OSPI_READ_FIFO_ID, OSPI_E_PARAM_POINTER);
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}
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else if(u8SeqId > 3U)
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{
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OSPI_ReportDevError(OSPI_READ_FIFO_ID, OSPI_E_PARAM_INVALID);
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}
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else
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{
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#endif
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OSPI_StatusType eRet = OSPI_STATUS_SUCCESS;
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uint8_t u8LoopI, u8LoopMax;
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OSPI_HWA_SetCmdIdSize(base, u8SeqId, u16Size);
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eRet = OSPI_Wait_Cmd_Done(base);
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if (eRet == OSPI_STATUS_SUCCESS)
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{
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u8LoopMax = OSPI_HWA_GetRxFifoFillLevel(base);
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for (u8LoopI = 0; u8LoopI < u8LoopMax; u8LoopI++)
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{
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pBuf[u8LoopI] = OSPI_HWA_ReadSecondaryRcvFifoReg(base);
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}
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}
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return eRet;
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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}
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#endif
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}
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/**
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* @brief OSPI write sequence data.
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*
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* @param base OSPI peripheral base address
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* @param xfer pointer to the transfer structure
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* @return OSPI_StatusType whether the operation is successfully
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*/
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OSPI_StatusType OSPI_TransferBlocking(OSPI_Type *base, OSPI_TransferType *xfer)
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{
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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if(xfer == NULL_PTR)
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{
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OSPI_ReportDevError(OSPI_TRANSFER_BLOCKING_ID, OSPI_E_PARAM_POINTER);
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}
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else
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{
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#endif
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OSPI_StatusType eRet = OSPI_STATUS_SUCCESS;
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uint32_t u32TotalSize = xfer->dataSize;
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uint32_t u32BaseAddr = xfer->deviceAddress;
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uint32_t u32LoopCounter = 0;
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uint32_t u32CurrentSize = 0;
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if (xfer->cmdType == OSPI_OPERATION_WRITE)
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{
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while (u32TotalSize > 0)
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{
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OSPI_HWA_SetFlashAddr(base, u32BaseAddr + u32LoopCounter * OSPI_ONE_TRANSFER_SIZE_MAX);
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u32CurrentSize = u32TotalSize > OSPI_ONE_TRANSFER_SIZE_MAX ? OSPI_ONE_TRANSFER_SIZE_MAX : u32TotalSize;
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eRet = OSPI_Write_Fifo(base, xfer->seqIndex, xfer->data + u32LoopCounter * OSPI_FIFO_DEPTH_MAX, (uint16_t)u32CurrentSize);
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if (eRet == OSPI_STATUS_SUCCESS)
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{
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u32TotalSize -= u32CurrentSize;
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u32LoopCounter++;
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}
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else
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{
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break;
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}
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}
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}
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else if (xfer->cmdType == OSPI_OPERATION_READ)
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{
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while (u32TotalSize > 0)
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{
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OSPI_HWA_SetFlashAddr(base, u32BaseAddr + u32LoopCounter * OSPI_ONE_TRANSFER_SIZE_MAX);
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u32CurrentSize = u32TotalSize > OSPI_ONE_TRANSFER_SIZE_MAX ? OSPI_ONE_TRANSFER_SIZE_MAX : u32TotalSize;
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eRet = OSPI_Read_Fifo(base, xfer->seqIndex, xfer->data + u32LoopCounter * OSPI_FIFO_DEPTH_MAX, (uint16_t)u32CurrentSize);
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if (eRet == OSPI_STATUS_SUCCESS)
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{
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u32TotalSize -= u32CurrentSize;
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u32LoopCounter++;
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}
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else
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{
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break;
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}
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}
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}
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else
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{
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}
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return eRet;
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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}
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#endif
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}
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OSPI_StatusType OSPI_TransferNonBlocking(OSPI_Type *base, OSPI_TransferType *xfer)
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{
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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if(xfer == NULL_PTR)
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{
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OSPI_ReportDevError(OSPI_TRANSFER_NONBLOCKING_ID, OSPI_E_PARAM_POINTER);
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}
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else
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{
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#endif
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OSPI_StatusType eRet = OSPI_STATUS_SUCCESS;
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if ((xfer->cmdType == OSPI_OPERATION_WRITE) || (xfer->cmdType == OSPI_OPERATION_READ))
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{
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OSPI_HWA_SetFlashAddr(base, xfer->deviceAddress);
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OSPI_HWA_SetCmdIdSize(base, xfer->seqIndex, xfer->dataSize);
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}
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else
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{
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}
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return eRet;
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#if OSPI_DEV_ERROR_REPORT == STD_ON
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}
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#endif
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}
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void OSPI_DriverIRQHandler(OSPI_Type *base)
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{
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(void)base;
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}
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#endif /* #if OSPI_INSTANCE_COUNT > 0U */
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