248 lines
6.9 KiB
C
248 lines
6.9 KiB
C
/* @file module_driver_cpm.c
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* @author Flagchip
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* @brief CPM driver type definition and API
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* @version 2.0.0
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* @date 2024-08-20
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*
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* SDK Version: 2.6.0
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*
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* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 2.0.0 2024-8-26 Flagchip120 N/A Release version for FC7300
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******************************************************************************** */
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#include "module_driver_cpm.h"
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#include "module_driver_fcuart.h"
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#if CPM_INSTANCE_COUNT > 0U
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static CPM_Type * const s_pCpmBasePtrs[CPM_INSTANCE_COUNT] = CPM_BASE_PTRS;
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/* ################################################################################## */
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/* ########################### Local Prototype Functions ############################ */
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/* ################################################################################## */
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/* ################################ Global Functions ################################ */
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/**
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*
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* @brief Configures the CPM module interrupts.
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*
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* This function configures the CPM module interrupts to enable/disable various interrupt sources.
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*
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* @param pCpmHandle CPM handle
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* @param eIntSrc CPM FPU interrupt type. refer CPM FISCR register
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* @param bEnable 1: interrupt enable, 0:interrupt disable.
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*/
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void CPM_FpuIntMode(CPM_HandleType* pCpmHandle, FPU_IntType eIntSrc, bool bEnable)
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{
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CPM_Type * const pCpm = s_pCpmBasePtrs[pCpmHandle->eInstance];
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switch (eIntSrc)
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{
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case CPM_FPU_FIO:
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CPM_HWA_SetFioceInt(pCpm, bEnable);
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break;
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case CPM_FPU_FDZ:
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CPM_HWA_SetFdzceInt(pCpm, bEnable);
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break;
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case CPM_FPU_FOF:
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CPM_HWA_SetFofceInt(pCpm, bEnable);
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break;
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case CPM_FPU_FUF:
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CPM_HWA_SetFufceInt(pCpm, bEnable);
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break;
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case CPM_FPU_FIX:
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CPM_HWA_SetFixceInt(pCpm, bEnable);
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break;
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case CPM_FPU_FID:
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CPM_HWA_SetFidceInt(pCpm, bEnable);
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break;
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default :
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/* Invalid parameter: return */
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break;
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}
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}
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/**
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* @brief Get CPM Interrupt occurred flag
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*
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* This function returns the interrupt flag.
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*
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* @param pCpmHandle CPM handle
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* @param eIntSrc CPM FPU interrupt type. refer CPM FISCR register
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* @return true interrupt occurred
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* @return false No interrupt
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*/
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bool CPM_GetFpuIntStatus(CPM_HandleType* pCpmHandle, FPU_IntType eIntSrc)
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{
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CPM_Type * const pCpm = s_pCpmBasePtrs[pCpmHandle->eInstance];
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bool bRetVal = false;
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switch(eIntSrc){
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case CPM_FPU_FIO:
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bRetVal = CPM_HWA_GetFpuFiocFlag(pCpm);
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break;
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case CPM_FPU_FDZ:
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bRetVal = CPM_HWA_GetFpuFdzcFlag(pCpm);
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break;
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case CPM_FPU_FOF:
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bRetVal = CPM_HWA_GetFpuFofcFlag(pCpm);
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break;
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case CPM_FPU_FUF:
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bRetVal = CPM_HWA_GetFpuFufcFlag(pCpm);
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break;
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case CPM_FPU_FIX:
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bRetVal = CPM_HWA_GetFpuFixcFlag(pCpm);
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break;
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case CPM_FPU_FID:
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bRetVal = CPM_HWA_GetFpuFidcFlag(pCpm);
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break;
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default:
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break;
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}
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return bRetVal;
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}
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#ifdef FPU_USED_ENABLE
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/**
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* @brief CPM_Read_FPSCR
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* Return the current value of FPSCR
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* @return u32RetVal
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*/
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uint32_t CPM_Read_FPSCR(void)
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{
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uint32_t u32RetVal = 0U;
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__asm(
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"vmrs %0, fpscr" : "=r" (u32RetVal)
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);
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return u32RetVal;
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}
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/**
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* @brief CPM_Write_FPSCR
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*
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* @param u32SetVal set the value for FPSCR
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*/
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void CPM_Write_FPSCR(uint32_t u32SetVal)
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{
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__asm(
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"vmsr fpscr, %0" : : "r" (u32SetVal)
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);
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}
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/**
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* @brief Deinit Cpm set interrupt
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*
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* Restore the Cpm FISCR to its reset state
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*
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* @param pCpmHandle CPM handle
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*/
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void CPM_DeInitInterrupt(CPM_HandleType* pCpmHandle)
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{
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CPM_Type * const pCpm = s_pCpmBasePtrs[pCpmHandle->eInstance];
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uint32_t u32RetVal;
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CPM_HWA_SetFiscr(pCpm, 0x0U);
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u32RetVal = CPM_Read_FPSCR();
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/* Clear FPSCR IDC/IXC/UFC/OPF/DZC/IOC flag*/
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u32RetVal &=0xFFFFFF90u;
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CPM_Write_FPSCR(u32RetVal);
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}
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#endif
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/**
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* @brief Cpm set interrupt
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*
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* @param pCpmHandle CPM handle
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* @param pIntStruct interrupt structure pointer
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* @return Cpm return type
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*/
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CPM_RetType CPM_InitInterrupt(CPM_HandleType* pCpmHandle, const CPM_InterruptType *pIntStruct)
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{
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CPM_RetType eRet = CPM_STATUS_SUCCESS;
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if(NULL == pIntStruct)
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{
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eRet = CPM_STATUS_PARAM_INVALID;
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}
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else
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{
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if(pIntStruct->u8CpmEnable != 0U)
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{
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if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FIOC_MASK) == CPM_FPU_FIO)
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{
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CPM_FpuIntMode(pCpmHandle, CPM_FPU_FIO,true);
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}
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if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FDZC_MASK) == CPM_FPU_FDZ)
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{
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CPM_FpuIntMode(pCpmHandle, CPM_FPU_FDZ,true);
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}
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if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FUFC_MASK) == CPM_FPU_FUF)
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{
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CPM_FpuIntMode(pCpmHandle, CPM_FPU_FUF,true);
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}
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if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FOFC_MASK) == CPM_FPU_FOF)
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{
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CPM_FpuIntMode(pCpmHandle, CPM_FPU_FOF,true);
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}
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if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FIDC_MASK) == CPM_FPU_FID)
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{
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CPM_FpuIntMode(pCpmHandle, CPM_FPU_FID,true);
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}
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if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FIXC_MASK) == CPM_FPU_FIX)
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{
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CPM_FpuIntMode(pCpmHandle, CPM_FPU_FIX,true);
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}
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}
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pCpmHandle->tSettings.pCpmCallback = pIntStruct->pIsrNotify;
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}
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return eRet;
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}
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#if (CPM_CONTAIN_CPUID == STD_ON)
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uint32_t CPM_MiscrGetCoreMode(CPM_HandleType* pCpmHandle)
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{
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CPM_Type * const pCpm = s_pCpmBasePtrs[pCpmHandle->eInstance];
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return CPM_HWA_GetCoreIDValve(pCpm);
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}
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#endif
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/**
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* @brief Gets the value of the FIscr register.
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*
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* This function retrieves the value of the FIscr register using the provided CPM module handle.
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* The FIscr register contains status information about interrupts and exceptions within the CPM module.
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* Reading this register's value provides insight into the current state of interrupts and exceptions.
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*
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* @param pCpmHandle Pointer to the CPM module handle. This handle identifies the CPM instance to be accessed.
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* @return uint32_t The value of the FIscr register.
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*/
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uint32_t CPM_GetFiscr(CPM_HandleType* pCpmHandle)
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{
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CPM_Type * const pCpm = s_pCpmBasePtrs[pCpmHandle->eInstance];
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return CPM_HWA_GetFiscr(pCpm);
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}
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/**
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* @brief CPM interrupt function
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*
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* @param pCpmHandle CPM handle
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*/
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void CPM_CommonProcessInterrupt(CPM_HandleType* pCpmHandle)
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{
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if(pCpmHandle->tSettings.pCpmCallback != NULL)
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{
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pCpmHandle->tSettings.pCpmCallback(pCpmHandle);
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}
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}
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#endif
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