211 lines
6.6 KiB
C
211 lines
6.6 KiB
C
/**
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* @file module_driver_pcc.h
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* @author Flagchip
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* @brief PCC driver type definition and API
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* @version 2.0.0
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* @date 2024-08-20
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*
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* SDK Version: 2.6.0
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*
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* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2023-12-15 Flagchip055 N/A First version for FC7300
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* 2.0.0 2024-10-12 Flagchip055 N/A Change version and release
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******************************************************************************** */
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#ifndef _DRIVER_MODULE_DRIVER_PCC_H_
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#define _DRIVER_MODULE_DRIVER_PCC_H_
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#include "device_header.h"
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#if PCC_INSTANCE_COUNT > 0U
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/**
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* @addtogroup module_driver_pcc
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* @{
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*/
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/**
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* @name PCC API Service IDs
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*
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* @{
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*/
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#define PCC_SET_PCC_ID 0x00U
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#define PCC_GET_PCC_INTERFACE_CLOCK_ID 0x01U
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#define PCC_GET_PCC_FUNCTION_CLOCK_ID 0x02U
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/** @}*/
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/**
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* @name PCC Dev Error Code
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* @brief Error Code of calling PCC apis
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*
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* @{
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*/
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#define PCC_E_PARAM_POINTER 0x01U
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#define PCC_E_PARAM_OUT_RANGE 0x02U
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/** @}*/
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/** @brief Marco for PCCn Bit Field definition */
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#define PCC_DWPLK_MASK 0x80000000u
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#define PCC_DWPLK_SHIFT 31u
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#define PCC_DWPLK_WIDTH 1u
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#define PCC_DWP_MASK 0x70000000u
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#define PCC_DWP_SHIFT 28u
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#define PCC_DWP_WIDTH 3u
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#define PCC_DWP(x) (((uint32_t)(((uint32_t)(x))<<PCC_DWP_SHIFT))&PCC_DWP_MASK)
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#define PCC_CGC_MASK 0x800000U
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#define PCC_CGC_SHIFT 23U
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#define PCC_CGC_WIDTH 1U
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#define PCC_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_CGC_SHIFT))&PCC_CGC_MASK)
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#define PCC_SEL_MASK 0x700000U
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#define PCC_SEL_SHIFT 20U
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#define PCC_SEL_WIDTH 3U
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#define PCC_SEL(x) (((uint32_t)(((uint32_t)(x))<<PCC_SEL_SHIFT))&PCC_SEL_MASK)
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#define PCC_GetSEL(x) ((((uint32_t)(x))&PCC_SEL_MASK)>>PCC_SEL_SHIFT)
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#define PCC_DIV_MASK 0x7U
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#define PCC_DIV_SHIFT 0U
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#define PCC_DIV_WIDTH 3U
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#define PCC_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCC_DIV_SHIFT))&PCC_DIV_MASK)
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#define PCC_GetDIV(x) ((((uint32_t)(x))&PCC_DIV_MASK)>>PCC_DIV_SHIFT)
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#define PCC_SWR_MASK 0x10000u
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#define PCC_MUX_MAX_NUMBER 8U
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/**
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* @brief Pcc clock status
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*/
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typedef enum
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{
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PCC_STATUS_SUCCESS = 0U,
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PCC_STATUS_CLOCK_INVALID = 1U,
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PCC_STATUS_CONFIGURED_NOT_SUPPORT = 1U,
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} PCC_StatusType;
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/**
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* @brief defined the clock source for function clock,match with PCC_XXX[SEL] bit filed.
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*/
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typedef enum
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{
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PCC_CLKGATE_SRC_OFF = 0U,
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PCC_CLKGATE_SRC_FOSCDIV = 1U,
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PCC_CLKGATE_SRC_SIRCDIV = 2U,
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PCC_CLKGATE_SRC_FIRCDIV = 3U,
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#if PCC_PLLX_CLK1_SUPPORT
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#if PCC_PLLX_CLK2_SUPPORT
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PCC_CLKGATE_SRC_PLL0CLK2 = 4U,
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#else
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PCC_CLKGATE_SRC_PLL1CLK1 = 4U,
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#endif /* PCC_PLLX_CLK2_SUPPORT */
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#else
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PCC_CLKGATE_SRC_RESERVE0 = 4U,
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#endif /* PCC_PLLX_CLK1_SUPPORT */
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#if PCC_PLL1_CLK_SUPPORT
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PCC_CLKGATE_SRC_PLL1DIV = 5U,
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#else
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PCC_CLKGATE_SRC_RESERVE1 = 5U,
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#endif /* PCC_PLL1_CLK_SUPPORT */
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PCC_CLKGATE_SRC_PLL0DIV = 6U,
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#if PCC_PLLX_CLK1_SUPPORT
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PCC_CLKGATE_SRC_PLL0CLK1 = 7U
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#else
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PCC_CLKGATE_SRC_RESERVE2 = 7U
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#endif
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} PCC_ClkGateSrcType;
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/**
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* @brief define the clock divider,match with PCC_XXX[DIV] bit filed.
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*/
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typedef enum
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{
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PCC_CLK_DIV_BY1 = 0U, /*!< Divide by 1 (pass-through, no clock divide) */
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PCC_CLK_DIV_BY2 = 1U, /*!< Divide by 2 */
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PCC_CLK_DIV_BY3 = 2U, /*!< Divide by 3 */
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PCC_CLK_DIV_BY4 = 3U, /*!< Divide by 4 */
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PCC_CLK_DIV_BY5 = 4U, /*!< Divide by 5 */
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PCC_CLK_DIV_BY6 = 5U, /*!< Divide by 6 */
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PCC_CLK_DIV_BY7 = 6U, /*!< Divide by 7 */
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PCC_CLK_DIV_BY8 = 7U, /*!< Divide by 8 */
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PCC_CLK_UNINVOLVED = 8U /*!< Current peripheral dose not contain DIV configuration */
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} PCC_ClkDivType;
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/**
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* @brief Indicate which CPU can control PCC
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*/
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typedef enum
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{
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PCC_CTRL_BY_ALL = 0U, /*!< All CPUs are allowed to write this peripheral */
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PCC_CTRL_BY_CPU0 = 1U, /*!< Only CPU0 is allowed to control this peripheral */
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PCC_CTRL_BY_CPU1 = 2U, /*!< Only CPU1 is allowed to control this peripheral */
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PCC_CTRL_BY_CPU2 = 3U, /*!< Only CPU2 is allowed to control this peripheral */
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PCC_CTRL_BY_NONE = 7U, /*!<None CPU is allowed to control this peripheral */
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} PCC_CtrlOwnerType;
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/**
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* @brief define the PCC module initialization structure.
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*/
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typedef struct
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{
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PCC_ClkSrcType eClockName; /*!< Peripheral clock */
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bool bEn; /*!< Peripheral clock enable or disable */
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PCC_ClkGateSrcType eClkSrc; /*!< Peripheral function clock source select */
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PCC_ClkDivType eDivider; /*!< Peripheral clock divider value */
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#if PCC_DWP_SUPPORT
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PCC_CtrlOwnerType eCtrlOwner; /*!< Peripheral control by which CPI */
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#endif
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#if PCC_DWPLK_SUPPORT
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bool bLockCtrl; /*!< Peripheral control setting locked or not which configured by eCtrlOwner */
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#endif
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} PCC_CtrlType;
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/**
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* @brief get PCC function clock status and value.
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*
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* @param pcc_ClkSrcType eClockName: used for choose PCC clock source to query.
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* @return uint32_t Pcc function clock frequency, if PCC is not enable or do not have clock mux configuration,
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* the function will return 0
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*/
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uint32_t PCC_GetPccFunctionClock(const PCC_ClkSrcType eClockName);
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/**
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* @brief get PCC interface clock status and value.
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*
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* @param pcc_ClkSrcType eClockName: used for choose PCC clock source to query.
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*/
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uint32_t PCC_GetPccInterfaceClock(const PCC_ClkSrcType eClockName);
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/**
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* @brief set PCC one peripheral clock configuration.
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*
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* @param PCC_CtrlType* pConfig: the PCC initialize value point set by user.
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* @return PCC_StatusType pcc function status
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*/
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PCC_StatusType PCC_SetPcc(const PCC_CtrlType *const pConfig);
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/**
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* @brief Generate peripheral reset
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*
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*/
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void PCC_GenPeripheralReset(const PCC_ClkSrcType eClockName);
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/** @}*/ /* module_driver_pcc */
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#endif /* #if PCC_INSTANCE_COUNT > 0U */
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#endif
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