350 lines
14 KiB
C
350 lines
14 KiB
C
/**
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* @file module_driver_lu.h
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* @author Flagchip
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* @brief LU driver type definition and API
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* @version 2.0.0
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* @date 2024-08-20
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*
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* SDK Version: 2.6.0
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*
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* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
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*
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* @details
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*/
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#ifndef _DRIVER_MODULE_DRIVER_ELU_H_
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#define _DRIVER_MODULE_DRIVER_ELU_H_
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#include "HwA_elu.h"
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#if ELU_INSTANCE_COUNT > 0U
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/**
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* @addtogroup module_driver_lu
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* @{
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*/
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/**
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* @name CORDIC API Service IDs
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* @{
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*/
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#define LU_INIT_ID 0x00 /**< Service ID for LU initialization. */
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#define LU_DEINIT_ID 0x01 /**< Service ID for LU deinitialization. */
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/**
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* @}
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*/
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/**
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* @name LU Dev Error Code
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* @{
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*/
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#define LU_E_PARAM_INSTANCE 0x01U /**< Error code for invalid LU instance parameter. */
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#define LU_E_PARAM_NULLPTR 0x02U /**< Error code for null pointer parameter. */
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/**
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* @}
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*/
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#define LU_AOI_IN_N_CFG_N(AoiIn, AoiInN, InNCfgNType) ((((uint32_t)(InNType) & 0x3U) << (((uint32_t)3U - (uint32_t)(AoiInN)) << 3U)) << (((uint32_t)3U - (uint32_t)(AoiIn)) << 3U))
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#define LU_AOI_IN_N_CFG_N_MASK(AoiIn, AoiInN) (((uint32_t)0x3U << (((uint32_t)3U - (uint32_t)(AoiInN)) << 3U)) << (((uint32_t)3U - (uint32_t)(AoiIn)) << 3U))
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#define LU_AOI_IN_CFG(AoiInN, CfgNType) ((((uint32_t)(CfgNType) & 0x3U) << (((uint32_t)3U - (uint32_t)(AoiInN)) << 1U)))
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#define LU_AOI_IN_CFG_MASK(AoiInN) ((((uint32_t)0x3U) << (((uint32_t)3U - (uint32_t)(AoiInN)) << 1U)))
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#define LU_AOI_IN_N_CFG(AoiIn, InNType) ((((uint32_t)(InNType) & 0xFFU) << (((uint32_t)3U - (uint32_t)(AoiIn)) << 3U)))
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#define LU_AOI_IN_N_CFG_MASK(AoiIn) ((((uint32_t)0xFFU) << (((uint32_t)3U - (uint32_t)(AoiIn)) << 3U)))
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#define LU_SYNC_CONTROL_INPUT_N(InputN, value) ((uint32_t)(value) << (InputN))
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/** @brief LU instance */
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typedef enum
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{
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LU_INSTANCE_0 = 0U,
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LU_INSTANCE_1
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} LU_InstanceType;
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/** @brief LU return structure */
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typedef enum
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{
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LU_STATUS_SUCCESS = 0U,
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LU_STATUS_PARAM_INVALID = 1U
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} LU_StatusType;
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/** @brief LU output initialization value */
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typedef enum
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{
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LU_OUTPUT_INIT_ZERO = 0U,
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LU_OUTPUT_INIT_ONE,
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LU_OUTPUT_INIT_DISABLE
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} LU_LG_FFOutputInitValueType;
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/** @brief LU IN(n) configuration register type */
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typedef struct
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{
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LU_InputDType eInACfg; /**< LUT IN A configuration */
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LU_InputDType eInBCfg; /**< LUT IN B configuration */
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LU_InputDType eInCCfg; /**< LUT IN C configuration */
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LU_InputDType eInDCfg; /**< LUT IN D configuration */
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} LU_LG_InPutConfigType;
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/** @brief LU IN(n) configuration register type */
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typedef struct
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{
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LU_OutputDType eOut0ACfg; /**< LU OUT 0A configuration */
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LU_OutputDType eOut0BCfg; /**< LU OUT 0B configuration */
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LU_OutputDType eOut1ACfg; /**< LU OUT 1A configuration */
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LU_OutputDType eOut1BCfg; /**< LU OUT 1B configuration */
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LU_OutputDType eOut2ACfg; /**< LU OUT 2A configuration */
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LU_OutputDType eOut2BCfg; /**< LU OUT 2B configuration */
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LU_OutputDType eOut3ACfg; /**< LU OUT 3A configuration */
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LU_OutputDType eOut3BCfg; /**< LU OUT 3B configuration */
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} LU_OutputConfigType;
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/** @brief LU LG inputs synchronous control */
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typedef struct
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{
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bool bInputASync; /**< LU IN A sync control */
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bool bInputBSync; /**< LU IN B sync control */
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bool bInputCSync; /**< LU IN C sync control */
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bool bInputDSync; /**< LU IN D sync control */
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} LU_LG_InputSyncCtrlType;
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/** @brief LU_Handle type */
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typedef struct _LU_HandleType
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{
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LU_InstanceType eInstance;
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struct
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{
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uint32_t u32DATA0; /** direct access to DU_DATA0 Register */
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uint32_t u32DATA1; /** direct access to DU_DATA1 Register */
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uint32_t u32DATA2; /** direct access to DU_DATA2 Register */
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uint32_t u32DATA3; /** direct access to DU_DATA3 Register */
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uint32_t u32DATA4; /** direct access to DU_DATA4 Register */
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uint32_t u32DATA5; /** direct access to DU_DATA5 Register */
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uint32_t u32DATA6; /** direct access to DU_DATA6 Register */
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uint32_t u32DATA7; /** direct access to DU_DATA7 Register */
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void(*pDuInterruptCallback)(struct _LU_HandleType *pHandle);
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void(*(pLgInterruptCallback[4]))(struct _LU_HandleType *pHandle);
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}Lu_Status;
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}LU_HandleType;
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/** @brief Lg configuration type */
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typedef struct
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{
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bool bEnableInterrupt; /**< Enable lg interrupt or not, only lg_outa support */
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bool bGenerateDMARequest; /**< Generation of DMA request, only lg_outb support */
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uint8_t u8Lut0FiltCnt; /**< Lut0 input filter sample count */
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uint8_t u8Lut0Period; /**< Lut0 input filter sample period */
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uint8_t u8Lut1FiltCnt; /**< Lut1 input filter sample count */
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uint8_t u8Lut1Period; /**< Lut1 input filter sample period */
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uint16_t u16LUT0Position; /**< Specifies the LUT0 positions */
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uint16_t u16LUT1Position; /**< Specifies the LUT1 positions */
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LU_LG_InPutConfigType tLgInputConfig; /**< LG configuration */
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LU_LG_InputSyncCtrlType tSyncCtrl; /**< inputs sync control, when set, would sync input product with bus clock */
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LU_LG_BypassModeType eLutMode; /**< Lut mode */
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LU_LG_ConfigModeType eFFMode; /**< flip-flop mode */
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LU_LG_FFOutputInitValueType eFFInitValue; /**< flip-flop initial value */
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LU_LG_InputNType eFbMode; /**< feedback override control in JKFF mode */
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void(*pLgInterruptCallback)(struct _LU_HandleType *pHandle);
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} LU_LG_ConfigType;
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/** @brief DU_INCR configuration type */
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typedef struct
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{
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uint32_t u32InitialVal; /** increments data by 1 from an initial value (DU_DATA0) until reaches a final value (DU_DATA1) */
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uint32_t u32FinalVal;
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LU_DU_CaptureModeType eCaptureEdge;
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}LU_DU_INCR_ConfigType;
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/** @brief DU_DECR configuration type */
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typedef struct
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{
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uint32_t u32InitialVal; /** decrements data from an initial value (DU_DATA0) until it reaches "0" */
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LU_DU_CaptureModeType eCaptureEdge;
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}LU_DU_DECR_ConfigType;
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/** @brief DU_INCR_WRAP configuration type */
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typedef struct
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{
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uint32_t u32InitialVal; /** increments data by 1 from an initial value (DU_DATA0) until reaches a final value (DU_DATA1) */
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uint32_t u32FinalVal; /** INCR_Wrap wraps around to DU_DATA0 */
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LU_DU_CaptureModeType eCaptureEdge;
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}LU_DU_INCR_WRAP_ConfigType;
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/** @brief DU_DECR_WRAP configuration type */
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typedef struct
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{
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uint32_t u32InitialVal; /** decrements data from an initial value (DU_DATA0) until it reaches "0" */
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LU_DU_CaptureModeType eCaptureEdge;
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}LU_DU_DECR_WRAP_ConfigType; /** DECR_Wrap wraps around to DU_DATA1 */
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/** @brief DU_INCR_DECR configuration type */
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typedef struct
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{
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uint32_t u32InitialVal; /** INCR_DECR is a combination of INCR and DECR */
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uint32_t u32FinalVal;
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}LU_DU_INCR_DECR_ConfigType;
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/** @brief DU_INCR_DECR_WRAP configuration type */
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typedef struct
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{
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uint32_t u32InitialVal; /** INCR_DECR_Wrap has the same functionality as INCR_DECR with wrap around to DU_DATA0 on reaching the limits(DU_DATA1 or "0"). */
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uint32_t u32FinalVal;
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}LU_DU_INCR_DECR_WRAP_ConfigType;
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/** @brief DU_INCR_WRAP_MODE1 configuration type */
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typedef struct
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{
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uint32_t u32InitialVal; /** INCR_DECR_Wrap has the same functionality as INCR_DECR with wrap around to DU_DATA0 on reaching the limits(DU_DATA1 or "0"). */
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uint32_t u32MediumVal;
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uint32_t u32FinalVal;
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LU_DU_CaptureModeType eCaptureEdge;
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}LU_DU_INCR_WRAP_MODE1_ConfigType;
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/** @brief DU_INCR_DECR_WRAP_MODE1 configuration type */
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typedef struct
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{
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uint32_t u32InitialVal; /** INCR_DECR_Wrap_Mode1 is a combination of INCR and DECR */
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uint32_t u32MediumVal;
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uint32_t u32FinalVal;
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LU_DU_CaptureModeType eCaptureEdge;
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}LU_DU_INCR_DECR_WRAP_MODE1_ConfigType;
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/** @brief DU_SHIFT_IN_LEFT configuration type */
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typedef struct
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{
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bool bShiftInitCfg; /** The first trigger signal is sent or not*/
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bool bContinuousEnable; /** Enable continuous mode */
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uint32_t u32ShiftInBitCnt; /** Up to 96bit can be collected at a time and stored in DU_DATA4, DU_DATA6, DU_DATA5 in sequence */
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}LU_DU_SHIFT_IN_LEFT_ConfigType;
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/** @brief DU_SHIFT_IN_RIGHT configuration type */
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typedef struct
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{
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bool bShiftInitCfg; /** The first trigger signal is sent or not*/
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bool bContinuousEnable; /** Enable continuous mode */
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uint32_t u32ShiftInBitCnt; /** Up to 96bit */
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}LU_DU_SHIFT_IN_RIGHT_ConfigType;
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/** @brief DU_SHIFT_OUT_LEFT configuration type */
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typedef struct
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{
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bool bShiftInitCfg; /** The first trigger signal is sent or not*/
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bool bContinuousEnable; /** Enable continuous mode */
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uint32_t u32ShiftInBitCnt; /** Up to 96bit can be collected at a time and stored in DU_DATA4, DU_DATA6, DU_DATA5 in sequence */
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uint32_t u32ShiftData1; /** and DU_DATA1, DU_DATA0, and DU_DATA2 can be sent in sequence*/
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uint32_t u32ShiftData0;
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uint32_t u32ShiftData2;
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}LU_DU_SHIFT_OUT_LEFT_ConfigType;
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/** @brief DU_SHIFT_OUT_RIGHT configuration type */
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typedef struct
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{
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bool bShiftInitCfg; /** The first trigger signal is sent or not*/
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bool bContinuousEnable; /** Enable continuous mode */
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uint32_t u32ShiftInBitCnt; /** Up to 96bit can be collected at a time and stored in DU_DATA4, DU_DATA6, DU_DATA5 in sequence */
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uint32_t u32ShiftData1; /** and DU_DATA1, DU_DATA0, and DU_DATA2 can be sent in sequence*/
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uint32_t u32ShiftData0;
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uint32_t u32ShiftData2;
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}LU_DU_SHIFT_OUT_RIGHT_ConfigType;
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/** @brief DU_FLEX_MODE configuration type */
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typedef struct
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{
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uint32_t u32CTRL; /** direct access to DU_CTRL Register */
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uint32_t u32CFG; /** direct access to DU_CFG Register */
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uint32_t u32DATA0; /** direct access to DU_DATA0 Register */
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uint32_t u32DATA1; /** direct access to DU_DATA1 Register */
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uint32_t u32DATA2; /** direct access to DU_DATA2 Register */
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uint32_t u32DATA3; /** direct access to DU_DATA3 Register */
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uint32_t u32DATA4; /** direct access to DU_DATA4 Register */
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uint32_t u32DATA5; /** direct access to DU_DATA5 Register */
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uint32_t u32DATA6; /** direct access to DU_DATA6 Register */
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uint32_t u32DATA7; /** direct access to DU_DATA7 Register */
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}LU_DU_FLEX_MODE_ConfigType;
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/** @brief DU input configuration type */
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typedef struct
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{
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LU_DU_InputMuxType eDuInputASelect;
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LU_DU_InputMuxType eDuInputBSelect;
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LU_DU_InputMuxType eDuInputCSelect;
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}LU_DU_Input_ConfigType;
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typedef struct
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{
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uint32_t u32MatchData;
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uint32_t u32MatchMask;
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}LU_DU_MATCH_MODE_ConfigType;
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/** @brief DU configuration type */
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typedef struct
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{
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bool bEnableMatchInterrupt; /**< Enable du interrupt or not */
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bool bEnableUnderflowInterrupt; /**< Enable du interrupt or not */
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bool bEnableOverflowInterrupt; /**< Enable du interrupt or not */
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bool bGenerateMatchDMARequest; /**< Generation of DMA request*/
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bool bGenerateUnderflowDMARequest; /**< Generation of DMA request*/
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bool bGenerateOverflowDMARequest; /**< Generation of DMA request*/
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LU_DU_OpcType eDuOperationCode;
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LU_DU_Input_ConfigType tDuInputSelect;
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void(*pDuInterruptCallback)(struct _LU_HandleType *pHandle);
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union
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{
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LU_DU_INCR_ConfigType tINCR_Cfg;
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LU_DU_DECR_ConfigType tDECR_Cfg;
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LU_DU_INCR_WRAP_ConfigType tINCR_WRAP_Cfg;
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LU_DU_DECR_WRAP_ConfigType tDECR_WRAP_Cfg;
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LU_DU_INCR_DECR_ConfigType tINCR_DECR_Cfg;
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LU_DU_INCR_DECR_WRAP_ConfigType tINCR_DECR_WRAP_Cfg;
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LU_DU_INCR_WRAP_MODE1_ConfigType tINCR_WRAP_MODE1_Cfg;
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LU_DU_INCR_DECR_WRAP_MODE1_ConfigType tINCR_DECR_WRAP_MODE1_Cfg;
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LU_DU_SHIFT_IN_LEFT_ConfigType tSHIFT_IN_LEFT_Cfg;
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LU_DU_SHIFT_IN_RIGHT_ConfigType tSHIFT_IN_RIGHT_Cfg;
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LU_DU_SHIFT_OUT_LEFT_ConfigType tSHIFT_OUT_LEFT_Cfg;
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LU_DU_SHIFT_OUT_RIGHT_ConfigType tSHIFT_OUT_RIGHT_Cfg;
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LU_DU_FLEX_MODE_ConfigType tFlex_Mode_Cfg;
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LU_DU_MATCH_MODE_ConfigType tMatch_Mode_Cfg;
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}DU_OperationCfg;
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} LU_DU_ConfigType;
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/** @brief LU configuration type */
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typedef struct
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{
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LU_LG_ConfigType tLgCfg[LG_CNT];
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LU_DU_ConfigType tDuCfg;
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LU_OutputConfigType tLuOutCfg;
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LU_PrescalerType eLuClockPreScaler;
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} LU_ConfigType;
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/* global functions */
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/**
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* @brief Initialize LU instance
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*
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* @param eLu LU instance
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* @param pInitStruct LU initialization structure
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* @return LU return type
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*/
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LU_StatusType LU_Init(LU_HandleType *pLuHandler, const LU_ConfigType *const pInitStruct);
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/**
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* @brief De-initialize LU instance
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*
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* @param eLu LU instance
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*/
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void LU_Deinit(LU_HandleType *pLuHandler);
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/**
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* @brief Lu interrupt function.
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* @param pLuHandle Lu processing handle
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*/
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void LUn_IRQHandler(LU_HandleType *pLuHandle);
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/** @}*/ /* module_driver_lu */
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#endif /* #if LU_INSTANCE_COUNT > 0U */
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#endif
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