313 lines
9.1 KiB
C
313 lines
9.1 KiB
C
/**
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* @file fc7xxx_driver_rgm.c
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* @author Flagchip
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* @brief FC7xxx RGM driver source code
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* @version 0.1.0
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* @date 2024-01-12
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*
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* @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd.
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*
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* @details
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*/
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/********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240
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********************************************************************************/
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#include "fc7xxx_driver_rgm.h"
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#include "interrupt_manager.h"
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/** @brief Rgm user defined CPU0 core related system interrupt function */
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static RGM_InterruptCallBackType s_pRgmCPU0PreIntPtr = NULL;
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/** @brief Rgm pre-reset interrupt entry */
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void RGM_Pre_IRQHandler(void);
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/**
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* @brief This api can get RGM_SRS register that indicate the source of the most recent reset.
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*
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* @return RGM->RGM_SRS register, bit 0-15,29-31 corresponding to RGM_ResetEventType, refer to reference manual for details.
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* @note Multiple flags can be set if multiple reset events occur at the same time
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*/
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uint32_t RGM_GetLastResetFLag(void)
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{
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return RGM_HWA_ReadLastResetFlag();
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}
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/**
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* @brief This api can get RGM_SSRS register that indicate all reset sources since the last POR or LVD that have not been cleared by software.
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*
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* @return RGM->RGM_SSRS register, bit 0-15,29-31 corresponding to RGM_ResetEventType, refer to reference manual for details.
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*/
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uint32_t RGM_GetAllResetFlag(void)
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{
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return RGM_HWA_ReadAllResetFlagBeforePOR();
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}
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/**
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* @brief This api can clear reset flag of RGM_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
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*
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* @param eReset Enumeration of reset event flag
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*/
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void RGM_ClearResetFlagAfterPOR(const RGM_ResetEventType eReset)
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{
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RGM_HWA_ClearResetFlagAfterPOR(eReset);
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}
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/**
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* @brief This api can clear all reset flag of RGM_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software.
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*
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*/
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void RGM_ClearAllResetFlagAfterPOR(void)
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{
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RGM_HWA_ClearAllResetFlagAfterPOR();
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}
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/**
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* @brief Enable reset pin filter
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*
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* @param eClk Reset pin filter clock source
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* @param u8BusClockFilterWidth Bus clock filter width
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* @param bLpClkEn select whether enable reset pin filter using AON32clock in low power mode
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* @return RGM return type
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* @note If use AON32K clock, A reset signal whose length is less than 2 AON32K clock periods will be filtered
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*/
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RGM_StatusType RGM_EnableResetFilter(RGM_FilterClkSrc eClk, uint8_t u8BusClockFilterWidth, bool bLpClkEn)
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{
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RGM_StatusType eRet = RGM_STATUS_SUCCESS;
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if(eClk > RGM_RESET_FILTER_AON32K_CLOCK)
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{
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eRet = RGM_STATUS_PARAM_INVALID;
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}
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if (RGM_STATUS_SUCCESS == eRet)
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{
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if (RGM_RESET_FILTER_AON32K_CLOCK == eClk)
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{
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if ((RGM_HWA_ReadResetPinFilterEnable() & RGM_RSTFLT_RSTFLT_BUS_MASK) >> RGM_RSTFLT_RSTFLT_BUS_SHIFT == 1U)
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{
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RGM_HWA_DisableBusClockFilter();
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}
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RGM_HWA_EnableAon32kClockFilter();
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}
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if (RGM_RESET_FILTER_BUS_CLOCK == eClk)
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{
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if ((RGM_HWA_ReadResetPinFilterEnable() & RGM_RSTFLT_RSTFLT_AON_MASK) >> RGM_RSTFLT_RSTFLT_AON_SHIFT == 1U)
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{
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RGM_HWA_DisableAon32kClockFilter();
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}
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RGM_HWA_SetBusClockFilterWidth(u8BusClockFilterWidth);
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RGM_HWA_EnableBusClockFilter();
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}
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if (bLpClkEn)
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{
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RGM_HWA_EnableAon32kLPClockFilter();
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}
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}
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return eRet;
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}
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/**
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* @brief Disable reset pin filter
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*
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* @param eClk Reset pin filter clock source
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* @param bLpClkEn select whether disable reset pin filter using AON32clock in low power mode
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* @return RGM return type
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*/
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RGM_StatusType RGM_DisableResetFilter(RGM_FilterClkSrc eClk, bool bLpClkEn)
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{
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RGM_StatusType eRet = RGM_STATUS_SUCCESS;
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if (eClk > RGM_RESET_FILTER_AON32K_CLOCK)
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{
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eRet = RGM_STATUS_PARAM_INVALID;
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}
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if (RGM_STATUS_SUCCESS == eRet)
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{
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if (RGM_RESET_FILTER_AON32K_CLOCK == eClk)
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{
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RGM_HWA_DisableAon32kClockFilter();
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}
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if (bLpClkEn)
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{
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RGM_HWA_DisableAon32kLPClockFilter();
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}
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if (RGM_RESET_FILTER_BUS_CLOCK == eClk)
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{
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RGM_HWA_ClearBusClockFilterWidth();
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RGM_HWA_DisableBusClockFilter();
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}
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}
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return eRet;
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}
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/**
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* @brief This api can enable interrupt before an system reset appear.
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*
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* @param eDelay Enumeration of delay cycles
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* @param eResetInterrupt Reset event flag, like: RGM_INT_CLKERR0 | RGM_INT_FCSMU
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* @return RGM return type
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*
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* @note Here is the interrupted master switch control
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*/
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RGM_StatusType RGM_EnableSystemResetInt(RGM_ResetDelayType eDelay, RGM_ResetIntMangerType eResetInterrupt)
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{
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RGM_StatusType eRet = RGM_STATUS_SUCCESS;
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if (eDelay > RGM_512_CLOCK_CYCLES)
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{
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eRet = RGM_STATUS_PARAM_INVALID;
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}
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if (RGM_STATUS_SUCCESS == eRet)
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{
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RGM_HWA_EnableGlobalResetInterrupt();
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RGM_HWA_SetResetDelay(eDelay);
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RGM_HWA_EnableResetInterrupt(eResetInterrupt);
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}
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return eRet;
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}
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/**
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* @brief This api can disable interrupt before an system reset appear.
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*
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* @param eResetInterrupt Reset event flag, like: RGM_INT_CLKERR0 | RGM_INT_FCSMU
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* @param bClearDelay Whether to clear delay configuration
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* @return RGM return type
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*/
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RGM_StatusType RGM_DisableSystemResetInt(RGM_ResetIntMangerType eResetInterrupt, bool bClearDelay)
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{
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RGM_StatusType eRet = RGM_STATUS_SUCCESS;
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if (bClearDelay)
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{
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RGM_HWA_ClearResetDelay();
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}
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RGM_HWA_DisableResetInterrupt(eResetInterrupt);
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return eRet;
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}
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/**
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* @brief Generate software reset through cotex-m register
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*
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*/
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void RGM_GenerateSwReset(void)
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{
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CM7_HWA_SystemReset();
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}
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/**
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* @brief This api can enable interrupt before an CPU0 core related reset appear.
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*
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* @param eCPU0Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST
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* @param pIsrNotify Interrupt function
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* @return RGM return type
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*/
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RGM_StatusType RGM_EnableCPU0CoreResetInt(RGM_CPUIntMangerType eCPU0Interrupt,RGM_InterruptCallBackType pIsrNotify)
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{
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RGM_StatusType eRet = RGM_STATUS_SUCCESS;
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if((uint8_t)eCPU0Interrupt > 0x1FU)
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{
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eRet = RGM_STATUS_PARAM_INVALID;
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}
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if (RGM_STATUS_SUCCESS == eRet)
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{
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RGM_HWA_EnableCPU0InterruptFlag(eCPU0Interrupt);
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s_pRgmCPU0PreIntPtr = pIsrNotify;
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}
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return eRet;
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}
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/**
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* @brief This api can disable interrupt before an CPU0 core related reset appear.
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*
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* @param eCPU0Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST
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* @return RGM return type
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*/
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RGM_StatusType RGM_DisableCPU0CoreResetInt(RGM_CPUIntMangerType eCPU0Interrupt)
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{
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RGM_StatusType eRet = RGM_STATUS_SUCCESS;
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if((uint8_t)eCPU0Interrupt > 0x1FU)
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{
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eRet = RGM_STATUS_PARAM_INVALID;
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}
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if (RGM_STATUS_SUCCESS == eRet)
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{
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RGM_HWA_DisableCPU0InterruptFlag(eCPU0Interrupt);
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}
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return eRet;
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}
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/**
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* @brief Get the CPU0 exit reset flag
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*
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* @return RGM_CPU_OUT_RST_UNDER CPU0 is under reset
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* @return RGM_CPU_OUT_RST_OUT CPU0 is out of reset
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*/
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RGM_CPUOutResetType RGM_GetCPU0OutResetFlag(void)
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{
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return RGM_HWA_GetCPU0OutResetFlag();
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}
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/**
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* @brief Generate a CPU0 software reset.
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*
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*/
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void RGM_GenerateCPU0SwReset(void)
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{
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RGM_HWA_CPU0SWReset();
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}
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/**
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* @brief This api can get RGM_C0_SRS register that indicate the source of the most recent CPU0 reset.
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*
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* @return RGM->RGM_C0_SRS register, bit 0-20 corresponding to RGM_ResetEventType, refer to reference manual for details.
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* @note Multiple flags can be set if multiple reset events occur at the same time
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*/
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uint32_t RGM_GetCPU0LastResetFLag(void)
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{
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return RGM_HWA_ReadCPU0LastResetFlag();
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}
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/**
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* @brief This api can get RGM_C0_SSRS register that indicate all CPU0 reset sources since the last POR or LVD that have not been cleared by software.
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*
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* @returnRGM->RGM_C0_SSRS register, bit 0-20,29-31 corresponding to RGM_CPUResetEventType, refer to reference manual for details.
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*/
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uint32_t RGM_GetCPU0AllResetFlag(void)
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{
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return RGM_HWA_ReadCPU0AllResetFlagBeforePOR();
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}
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/**
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* @brief This api can clear reset flag of RGM_C0_SSRS register which indicate CPU0 all reset sources since the last POR or LVD that have not been cleared by software.
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*
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* @param eReset Enumeration of reset event flag
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*/
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void RGM_ClearCPU0ResetFlagAfterPOR(const RGM_CPUResetEventType eReset)
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{
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RGM_HWA_ClearC0ResetFlagAfterPOR(eReset);
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}
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/**
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* @brief This api can clear all reset flag of RGM_C0_SSRS register which indicate CPU0 all reset sources since the last POR or LVD that have not been cleared by software.
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*
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*/
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void RGM_ClearCPU0AllResetFlagAfterPOR(void)
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{
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RGM_HWA_ClearC0AllResetFlagAfterPOR();
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}
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/**
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* @brief RGM Pre-interrupt entry
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*
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*/
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void RGM_Pre_IRQHandler(void)
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{
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IntMgr_DisableGlobalInterrupt();
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if (NULL != s_pRgmCPU0PreIntPtr)
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{
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s_pRgmCPU0PreIntPtr(RGM_GetCPU0LastResetFLag());
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}
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IntMgr_EnableGlobalInterrupt();
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}
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