Обновление после командировки 29.06.2026
This commit is contained in:
cfif
parent
1e4fd372c8
commit
a0260d1c91
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@ -173,7 +173,7 @@ typedef struct
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{
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uint8_t u8TxHandler; /**< one message buffer used one handler, range 0 ~ txMbCnt-1 */
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uint8_t bWaitTxCompleted;/**< wait transmit complete and clear iflag */
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uint16_t u16WaitTxTimeout; /**< wait transmit complete timeout */
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uint32_t u16WaitTxTimeout; /**< wait transmit complete timeout */
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uint8_t bEnFd; /**< enable FLEXCAN fd */
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uint8_t bEnBrs; /**< enable canfd data bit switch */
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uint32_t u32CanId; /**< FLEXCAN id */
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@ -458,7 +458,6 @@ void FLEXCAN_IRQHandler(uint8_t u8CanIndex);
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/** @}*/
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bool IsTxBufferFree_ByCode(uint8_t canIndex, uint8_t handler);
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#endif
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@ -70,7 +70,7 @@ extern "C" {
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#define DFLASH_BANK_NUM 0x01U
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/** DFlash Bank 0 size */
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#define DFLASH_BANK0_SIZE 0x00020000U
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#define DFLASH_BANK0_SIZE_ 0x00020000U
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#define FLASH_256KB_SIZE 0x00040000U
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@ -467,6 +467,164 @@ LOCAL_INLINE FLEXCAN_ErrorType FLEXCAN_LL_CheckFdInstance(uint8_t u8CanIndex)
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*
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* @param u8CanIndex CanIndex, Must less than FLEXCAN_INSTANCE_COUNT
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*/
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/* Every CAN contains message buffer number */
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#define FLEXCAN_MB_NUM_PTRS {32U,32U,32U,32U}
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/* Number of instances of the FLEXCAN FD module. */
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#define FLEXCAN_FD_SUPPORT_PTRS {1U,1U,1U,1U}
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/* Support Gate */
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#define FLEXCAN_GATE_BUFNUM_PTRS {0U,0U,0U,0U}
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/* Support pretend network */
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#define FLEXCAN_PNET_SUPPORT_PTRS {1U,1U,1U,1U}
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/* IFlag1...IFlagn, IMask1...IMaskn */
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#define FLEXCAN_IFLAGMASK_NUM_PTRS {1U,1U,1U,1U}
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#define FLEXCAN_IFLAGMASK_NUM_MAX 1U
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/* MBDSR0..MBDSRn */
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#define FLEXCAN_FD_DATALEN_RANGE_NUM_PTRS {1U,1U,1U,1U}
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#define FLEXCAN_FD_DATALEN_RANGE_NUM_MAX 1U
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/* Enhanced Rx FIFO */
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#define FLEXCAN_ENHANCED_FIFO_ELEMENT_MAX_PTRS {32U,32U,32U,32U}
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#define FLEXCAN_ENHANCED_FIFO_DEPTH_PTRS {12U,12U,12U,12U}
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static const uint8_t s_aFlexCanFd_SupportTable[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_FD_SUPPORT_PTRS;
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static const uint8_t s_aFlexCanEnhancedElementNums[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_ENHANCED_FIFO_ELEMENT_MAX_PTRS;
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static const uint8_t s_aFlexCanMbNums[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_MB_NUM_PTRS;
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static const uint8_t s_aFlexCanDataLenNums[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_FD_DATALEN_RANGE_NUM_PTRS;
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static const uint8_t s_aFlexCanEnhancedDepthp[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_ENHANCED_FIFO_DEPTH_PTRS;
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static const uint8_t s_aFlexCanGateNumSizes[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_GATE_BUFNUM_PTRS;
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static const uint8_t s_aFlexCanIflagMaskSizes[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_IFLAGMASK_NUM_PTRS;
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static const uint8_t s_aFlexCanPnetSupportTable[FLEXCAN_INSTANCE_COUNT]=FLEXCAN_PNET_SUPPORT_PTRS;
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#define FLEXCAN_MB_RAM_OFFSET 0x80U /* length is MB_Num*4*4 */
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#define FLEXCAN_RXIMR_OFFSET 0x880U /* Length is MB_Num*4 */
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#define FLEXCAN_RXFIR_TEST_OFFSET 0xA80U
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#define FLEXCAN_RXFIR_TEST_LEN 0x18U /* Length is 0x18 */
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#define FLEXCAN_MASK_OFFSET 0xAA0U
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#define FLEXCAN_MASK_LEN 0x10U /* Length is 0x10, RX14MASK, RX15MASK,RXMGMAXK, and RSFGMASK */
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#define FLEXCAN_SMBTX_OFFSET 0xAB0U
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#define FLEXCAN_SMBTX_LEN 0x10U /* Length is 0x10 */
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#define FLEXCAN_SMBRX0_OFFSET 0xAC0U
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#define FLEXCAN_SMBRX0_LEN 0x10U /* Length is 0x10 */
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#define FLEXCAN_SMBRX1_OFFSET 0xAD0U
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#define FLEXCAN_SMBRX1_LEN 0x10U /* Length is 0x10 */
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#define FLEXCAN_FD_SMBTX_OFFSET 0xF28U
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#define FLEXCAN_FD_SMBTX_LEN 0x48U /* Length is 0x48 */
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#define FLEXCAN_FD_SMBRX0_OFFSET 0xF70U
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#define FLEXCAN_FD_SMBRX0_LEN 0x48U /* Length is 0x48 */
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#define FLEXCAN_FD_SMBRX1_OFFSET 0xFB8U
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#define FLEXCAN_FD_SMBRX1_LEN 0x48U /* Length is 0x48 */
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#define FLEXCAN_ERX_FIFO_OFFSET 0x2000U /* Length is Depth*20(fd) or Depth*6(non-fd) */
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#define FLEXCAN_ERX_FIFO_FD_WIDTH 20U
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#define FLEXCAN_ERX_FIFO_NONFD_WIDTH 6U
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#define FLEXCAN_ERFFEL_OFFSET 0x3000U /* Length is element_num*4 */
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#define FLEXCAN_GATEBUF_OFFSET 0x1A10U /* Length is gatebuf_num*2*4 */
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static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex)
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{
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volatile uint32_t u32Index ;
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volatile uint32_t ramAddr;
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FLEXCAN_Type *pCan;
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pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[(uint8_t)u8CanIndex];
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for (u32Index = 0U; u32Index < s_aFlexCanMbNums[u8CanIndex]*4U; u32Index++)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_MB_RAM_OFFSET, u32Index * 4U);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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for (u32Index = 0U; u32Index < s_aFlexCanMbNums[u8CanIndex]; u32Index++)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_RXIMR_OFFSET, u32Index * 4U);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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for (u32Index = 0U; u32Index < FLEXCAN_RXFIR_TEST_LEN; u32Index+=4U)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_RXFIR_TEST_OFFSET, u32Index);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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for (u32Index = 0U; u32Index < FLEXCAN_MASK_LEN; u32Index+=4U)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_MASK_OFFSET, u32Index);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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for (u32Index = 0U; u32Index < FLEXCAN_SMBTX_LEN; u32Index+=4U)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_SMBTX_OFFSET, u32Index);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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for (u32Index = 0U; u32Index < FLEXCAN_SMBRX0_LEN; u32Index+=4U)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_SMBRX0_OFFSET, u32Index);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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for (u32Index = 0U; u32Index < FLEXCAN_SMBRX1_LEN; u32Index+=4U)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_SMBRX1_OFFSET, u32Index);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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/* only can fd support these memory */
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if(s_aFlexCanFd_SupportTable[u8CanIndex])
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{
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for (u32Index = 0U; u32Index < FLEXCAN_FD_SMBTX_LEN; u32Index+=4U)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_FD_SMBTX_OFFSET, u32Index);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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for (u32Index = 0U; u32Index < FLEXCAN_FD_SMBRX0_LEN; u32Index+=4U)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_FD_SMBRX0_OFFSET, u32Index);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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for (u32Index = 0U; u32Index < FLEXCAN_FD_SMBRX1_LEN; u32Index+=4U)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_FD_SMBRX1_OFFSET, u32Index);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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}
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/* only enhanced rx fifo support these memory */
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if(s_aFlexCanEnhancedDepthp[u8CanIndex])
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{
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/** initial rx fifo with fd */
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for (u32Index = 0U; u32Index < s_aFlexCanEnhancedDepthp[u8CanIndex]*4U*FLEXCAN_ERX_FIFO_FD_WIDTH; u32Index+=4U)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_ERX_FIFO_OFFSET, u32Index );
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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/* enhanced fifo elements */
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for (u32Index = 0U; u32Index < s_aFlexCanEnhancedElementNums[u8CanIndex]; u32Index++)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_ERFFEL_OFFSET, u32Index * 4U);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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}
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/* gate buffer */
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if(s_aFlexCanGateNumSizes[u8CanIndex])
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{
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for (u32Index = 0U; u32Index < s_aFlexCanGateNumSizes[u8CanIndex]*2U; u32Index++)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_GATEBUF_OFFSET, u32Index * 4U);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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}
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}
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/*
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static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex)
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{
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volatile uint32_t u8Index ;
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@ -493,11 +651,13 @@ static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex)
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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for (u8Index = 0U; u8Index < MASK_WORD_NUM; u8Index++)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, MASK_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN);
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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for (u8Index = 0U; u8Index < SMBTX_WORD_NUM; u8Index++)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, SMBTX_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN);
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@ -516,7 +676,7 @@ static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex)
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FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
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}
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/* can fd only */
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// can fd only
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if (FLEXCAN_LL_CheckFdInstance(u8CanIndex) == FLEXCAN_ERROR_OK)
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{
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for (u8Index = 0U; u8Index < FD_SMBTX_WORD_NUM; u8Index++)
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@ -538,7 +698,7 @@ static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex)
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}
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/** initial rx fifo */
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// initial rx fifo
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for (u8Index = 0U; u8Index < ERX_FIFO_WORD_NUM; u8Index++)
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{
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ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, ERX_FIFO_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN);
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@ -554,7 +714,7 @@ static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex)
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}
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}
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*/
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/**
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@ -1435,7 +1595,7 @@ FLEXCAN_ErrorType FLEXCAN_Init(uint8_t u8CanIndex, const FLEXCAN_InitType *const
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FLEXCAN_HWA_SetCtrl1(pCan, u32TempCtrl1);
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/* initial RAM to avoid ECC error */
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/* initial RAM to avoid ECC error CFIFCFIF*/
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FLEXCAN_LL_EmbededRam_Init(u8CanIndex);
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u32TempMcr = FLEXCAN_MCR_MDIS(0) | /* enable pCan module */
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@ -2022,6 +2182,7 @@ FLEXCAN_ErrorType FLEXCAN_Stop(uint8_t u8CanIndex)
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return tRetVal;
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}
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/**
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* @brief Transmit data, if tx disable, must call FLEXCAN_TransmitProcess after transmiting
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*
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@ -2160,21 +2321,7 @@ FLEXCAN_ErrorType FLEXCAN_TransmitData(uint8_t u8CanIndex, const FLEXCAN_TxMsgTy
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/* CODE set 0x0C to transmit */
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FLEXCAN_MB_CODE_SET(u32TempAddr, 0x0CU);
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if (pTxMsg->bWaitTxCompleted)
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{
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}
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else
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{
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u32WordLen = FLEXCAN_HWA_GetFlag1NoFifoFlag(pCan, u8TxRealMbIndex);
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if (u32WordLen == 0U)
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{
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tRetVal = FLEXCAN_ERROR_TIMEOUT;
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}
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}
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// -------------------------------
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/*
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if (pTxMsg->bWaitTxCompleted)
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{
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u32TempAddr = 0U;
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@ -2182,10 +2329,8 @@ FLEXCAN_ErrorType FLEXCAN_TransmitData(uint8_t u8CanIndex, const FLEXCAN_TxMsgTy
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while ((u32WordLen == 0U) && (u32TempAddr++ < pTxMsg->u16WaitTxTimeout))
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{
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u32WordLen = FLEXCAN_HWA_GetFlag1NoFifoFlag(pCan, u8TxRealMbIndex);
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// osThreadYield();
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}
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if (u32WordLen == 0U)
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{
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tRetVal = FLEXCAN_ERROR_TIMEOUT;
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@ -2200,9 +2345,7 @@ FLEXCAN_ErrorType FLEXCAN_TransmitData(uint8_t u8CanIndex, const FLEXCAN_TxMsgTy
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tRetVal = FLEXCAN_ERROR_TIMEOUT;
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}
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}
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*/
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// --------------------------
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}
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}
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#if FLEXCAN_CHECK_PARAMETERS == STD_ON
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@ -2213,31 +2356,6 @@ FLEXCAN_ErrorType FLEXCAN_TransmitData(uint8_t u8CanIndex, const FLEXCAN_TxMsgTy
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}
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bool IsTxBufferFree_ByCode(uint8_t canIndex, uint8_t handler) {
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FLEXCAN_Type *pCan = s_aFlexCan_InstanceTable[canIndex];
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FLEXCAN_SettingType *pCurSetting = &s_aFlexCan_Setting_Table[canIndex];
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if (handler >= pCurSetting->u8TxMbCnt1) {
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return false; // Неверный handler
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}
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uint8_t realIndex = pCurSetting->u8TxMbStart1 + handler;
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// Читаем код из первого слова MB
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uint32_t addr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(
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&(pCan->RAM[0U]), realIndex, pCurSetting->eMbDataWidth, 0U);
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uint32_t code = FLEXCAN_MB_CODE_GET(addr);
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// Коды состояния буфера:
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// 0x0 = EMPTY (не использовался) - СВОБОДЕН
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// 0x8 = INACTIVE (неактивен) - СВОБОДЕН
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// 0xC = TRANSMITTING (передаёт) - ЗАНЯТ
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// 0x9 = ABORTING (прерывается) - ЗАНЯТ
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return (code == 0x0 || code == 0x8);
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}
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/**
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* @brief Process flag after transmit
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*
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@ -2850,3 +2968,27 @@ void FLEXCAN_IRQHandler(uint8_t u8CanIndex)
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#endif
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}
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bool IsTxBufferFree_ByCode(uint8_t canIndex, uint8_t handler) {
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FLEXCAN_Type *pCan = s_aFlexCan_InstanceTable[canIndex];
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FLEXCAN_SettingType *pCurSetting = &s_aFlexCan_Setting_Table[canIndex];
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if (handler >= pCurSetting->u8TxMbCnt1) {
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return false; // Неверный handler
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}
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uint8_t realIndex = pCurSetting->u8TxMbStart1 + handler;
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// Читаем код из первого слова MB
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uint32_t addr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(
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&(pCan->RAM[0U]), realIndex, pCurSetting->eMbDataWidth, 0U);
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uint32_t code = FLEXCAN_MB_CODE_GET(addr);
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// Коды состояния буфера:
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// 0x0 = EMPTY (не использовался) - СВОБОДЕН
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// 0x8 = INACTIVE (неактивен) - СВОБОДЕН
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// 0xC = TRANSMITTING (передаёт) - ЗАНЯТ
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// 0x9 = ABORTING (прерывается) - ЗАНЯТ
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return (code == 0x0 || code == 0x8);
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}
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@ -118,7 +118,7 @@ static FMC_Lock_StatusType FMCDRIVER_DFlashLockRegion(const FMC_InstanceType eIn
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u32Index = 2U;
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if ((u32Address >= DFLASH_ADDR_START) && (u32Address <= DFLASH_ADDR_END))
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{
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u32Temp = 1UL << ((u32Address - DFLASH_ADDR_START - DFLASH_BANK0_SIZE * (u32Index - 2U)) >> 13);
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u32Temp = 1UL << ((u32Address - DFLASH_ADDR_START - DFLASH_BANK0_SIZE_ * (u32Index - 2U)) >> 13);
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u32Temp = bLock ? (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) | u32Temp) : (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) & ~u32Temp);
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FMC_HWA_SetFBFPELCKValue(pFMC, u32Index, u32Temp);
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}
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@ -188,11 +188,11 @@ FMC_Lock_StatusType FMCDRIVER_FlashLock(FMC_DRIVER_Lock_ParamType *pFmcParam)
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void FMCDRIVER_SwapBlock(const FMC_InstanceType eInstance, FMC_API_ACTIVE_BLOCK_TYPE bActive)
|
||||
{
|
||||
FMC_Type *const pFMC = s_apFmcBase[eInstance];
|
||||
// if (0U == FMC_HWA_GetOTACtrlValue(pFMC, 0))
|
||||
// {
|
||||
if (0U == FMC_HWA_GetOTACtrlValue(pFMC, 0))
|
||||
{
|
||||
FMC_HWA_SetOTAActive(pFMC, 0, bActive);
|
||||
FMC_HWA_SetOTAEnable(pFMC, 0);
|
||||
// }
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in New Issue