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Обновление после командировки 29.06.2026

This commit is contained in:
cfif 2026-06-29 13:13:45 +03:00
parent 1e4fd372c8
commit a0260d1c91
4 changed files with 195 additions and 54 deletions
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3
Inc/fc7xxx_driver_flexcan.h
View File

@ -173,7 +173,7 @@ typedef struct
{ {
uint8_t u8TxHandler; /**< one message buffer used one handler, range 0 ~ txMbCnt-1 */ uint8_t u8TxHandler; /**< one message buffer used one handler, range 0 ~ txMbCnt-1 */
uint8_t bWaitTxCompleted;/**< wait transmit complete and clear iflag */ uint8_t bWaitTxCompleted;/**< wait transmit complete and clear iflag */
uint16_t u16WaitTxTimeout; /**< wait transmit complete timeout */ uint32_t u16WaitTxTimeout; /**< wait transmit complete timeout */
uint8_t bEnFd; /**< enable FLEXCAN fd */ uint8_t bEnFd; /**< enable FLEXCAN fd */
uint8_t bEnBrs; /**< enable canfd data bit switch */ uint8_t bEnBrs; /**< enable canfd data bit switch */
uint32_t u32CanId; /**< FLEXCAN id */ uint32_t u32CanId; /**< FLEXCAN id */
@ -458,7 +458,6 @@ void FLEXCAN_IRQHandler(uint8_t u8CanIndex);
/** @}*/ /** @}*/
bool IsTxBufferFree_ByCode(uint8_t canIndex, uint8_t handler); bool IsTxBufferFree_ByCode(uint8_t canIndex, uint8_t handler);
#endif #endif

2
Inc/fc7xxx_driver_fmc.h
View File

@ -70,7 +70,7 @@ extern "C" {
#define DFLASH_BANK_NUM 0x01U #define DFLASH_BANK_NUM 0x01U
/** DFlash Bank 0 size */ /** DFlash Bank 0 size */
#define DFLASH_BANK0_SIZE 0x00020000U #define DFLASH_BANK0_SIZE_ 0x00020000U
#define FLASH_256KB_SIZE 0x00040000U #define FLASH_256KB_SIZE 0x00040000U

236
Src/fc7xxx_driver_flexcan.c
View File

@ -467,6 +467,164 @@ LOCAL_INLINE FLEXCAN_ErrorType FLEXCAN_LL_CheckFdInstance(uint8_t u8CanIndex)
* *
* @param u8CanIndex CanIndex, Must less than FLEXCAN_INSTANCE_COUNT * @param u8CanIndex CanIndex, Must less than FLEXCAN_INSTANCE_COUNT
*/ */
/* Every CAN contains message buffer number */
#define FLEXCAN_MB_NUM_PTRS {32U,32U,32U,32U}
/* Number of instances of the FLEXCAN FD module. */
#define FLEXCAN_FD_SUPPORT_PTRS {1U,1U,1U,1U}
/* Support Gate */
#define FLEXCAN_GATE_BUFNUM_PTRS {0U,0U,0U,0U}
/* Support pretend network */
#define FLEXCAN_PNET_SUPPORT_PTRS {1U,1U,1U,1U}
/* IFlag1...IFlagn, IMask1...IMaskn */
#define FLEXCAN_IFLAGMASK_NUM_PTRS {1U,1U,1U,1U}
#define FLEXCAN_IFLAGMASK_NUM_MAX 1U
/* MBDSR0..MBDSRn */
#define FLEXCAN_FD_DATALEN_RANGE_NUM_PTRS {1U,1U,1U,1U}
#define FLEXCAN_FD_DATALEN_RANGE_NUM_MAX 1U
/* Enhanced Rx FIFO */
#define FLEXCAN_ENHANCED_FIFO_ELEMENT_MAX_PTRS {32U,32U,32U,32U}
#define FLEXCAN_ENHANCED_FIFO_DEPTH_PTRS {12U,12U,12U,12U}
static const uint8_t s_aFlexCanFd_SupportTable[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_FD_SUPPORT_PTRS;
static const uint8_t s_aFlexCanEnhancedElementNums[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_ENHANCED_FIFO_ELEMENT_MAX_PTRS;
static const uint8_t s_aFlexCanMbNums[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_MB_NUM_PTRS;
static const uint8_t s_aFlexCanDataLenNums[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_FD_DATALEN_RANGE_NUM_PTRS;
static const uint8_t s_aFlexCanEnhancedDepthp[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_ENHANCED_FIFO_DEPTH_PTRS;
static const uint8_t s_aFlexCanGateNumSizes[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_GATE_BUFNUM_PTRS;
static const uint8_t s_aFlexCanIflagMaskSizes[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_IFLAGMASK_NUM_PTRS;
static const uint8_t s_aFlexCanPnetSupportTable[FLEXCAN_INSTANCE_COUNT]=FLEXCAN_PNET_SUPPORT_PTRS;
#define FLEXCAN_MB_RAM_OFFSET 0x80U /* length is MB_Num*4*4 */
#define FLEXCAN_RXIMR_OFFSET 0x880U /* Length is MB_Num*4 */
#define FLEXCAN_RXFIR_TEST_OFFSET 0xA80U
#define FLEXCAN_RXFIR_TEST_LEN 0x18U /* Length is 0x18 */
#define FLEXCAN_MASK_OFFSET 0xAA0U
#define FLEXCAN_MASK_LEN 0x10U /* Length is 0x10, RX14MASK, RX15MASK,RXMGMAXK, and RSFGMASK */
#define FLEXCAN_SMBTX_OFFSET 0xAB0U
#define FLEXCAN_SMBTX_LEN 0x10U /* Length is 0x10 */
#define FLEXCAN_SMBRX0_OFFSET 0xAC0U
#define FLEXCAN_SMBRX0_LEN 0x10U /* Length is 0x10 */
#define FLEXCAN_SMBRX1_OFFSET 0xAD0U
#define FLEXCAN_SMBRX1_LEN 0x10U /* Length is 0x10 */
#define FLEXCAN_FD_SMBTX_OFFSET 0xF28U
#define FLEXCAN_FD_SMBTX_LEN 0x48U /* Length is 0x48 */
#define FLEXCAN_FD_SMBRX0_OFFSET 0xF70U
#define FLEXCAN_FD_SMBRX0_LEN 0x48U /* Length is 0x48 */
#define FLEXCAN_FD_SMBRX1_OFFSET 0xFB8U
#define FLEXCAN_FD_SMBRX1_LEN 0x48U /* Length is 0x48 */
#define FLEXCAN_ERX_FIFO_OFFSET 0x2000U /* Length is Depth*20(fd) or Depth*6(non-fd) */
#define FLEXCAN_ERX_FIFO_FD_WIDTH 20U
#define FLEXCAN_ERX_FIFO_NONFD_WIDTH 6U
#define FLEXCAN_ERFFEL_OFFSET 0x3000U /* Length is element_num*4 */
#define FLEXCAN_GATEBUF_OFFSET 0x1A10U /* Length is gatebuf_num*2*4 */
static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex)
{
volatile uint32_t u32Index ;
volatile uint32_t ramAddr;
FLEXCAN_Type *pCan;
pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[(uint8_t)u8CanIndex];
for (u32Index = 0U; u32Index < s_aFlexCanMbNums[u8CanIndex]*4U; u32Index++)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_MB_RAM_OFFSET, u32Index * 4U);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
for (u32Index = 0U; u32Index < s_aFlexCanMbNums[u8CanIndex]; u32Index++)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_RXIMR_OFFSET, u32Index * 4U);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
for (u32Index = 0U; u32Index < FLEXCAN_RXFIR_TEST_LEN; u32Index+=4U)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_RXFIR_TEST_OFFSET, u32Index);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
for (u32Index = 0U; u32Index < FLEXCAN_MASK_LEN; u32Index+=4U)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_MASK_OFFSET, u32Index);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
for (u32Index = 0U; u32Index < FLEXCAN_SMBTX_LEN; u32Index+=4U)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_SMBTX_OFFSET, u32Index);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
for (u32Index = 0U; u32Index < FLEXCAN_SMBRX0_LEN; u32Index+=4U)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_SMBRX0_OFFSET, u32Index);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
for (u32Index = 0U; u32Index < FLEXCAN_SMBRX1_LEN; u32Index+=4U)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_SMBRX1_OFFSET, u32Index);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
/* only can fd support these memory */
if(s_aFlexCanFd_SupportTable[u8CanIndex])
{
for (u32Index = 0U; u32Index < FLEXCAN_FD_SMBTX_LEN; u32Index+=4U)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_FD_SMBTX_OFFSET, u32Index);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
for (u32Index = 0U; u32Index < FLEXCAN_FD_SMBRX0_LEN; u32Index+=4U)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_FD_SMBRX0_OFFSET, u32Index);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
for (u32Index = 0U; u32Index < FLEXCAN_FD_SMBRX1_LEN; u32Index+=4U)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_FD_SMBRX1_OFFSET, u32Index);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
}
/* only enhanced rx fifo support these memory */
if(s_aFlexCanEnhancedDepthp[u8CanIndex])
{
/** initial rx fifo with fd */
for (u32Index = 0U; u32Index < s_aFlexCanEnhancedDepthp[u8CanIndex]*4U*FLEXCAN_ERX_FIFO_FD_WIDTH; u32Index+=4U)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_ERX_FIFO_OFFSET, u32Index );
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
/* enhanced fifo elements */
for (u32Index = 0U; u32Index < s_aFlexCanEnhancedElementNums[u8CanIndex]; u32Index++)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_ERFFEL_OFFSET, u32Index * 4U);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
}
/* gate buffer */
if(s_aFlexCanGateNumSizes[u8CanIndex])
{
for (u32Index = 0U; u32Index < s_aFlexCanGateNumSizes[u8CanIndex]*2U; u32Index++)
{
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_GATEBUF_OFFSET, u32Index * 4U);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
}
}
}
/*
static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex) static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex)
{ {
volatile uint32_t u8Index ; volatile uint32_t u8Index ;
@ -493,11 +651,13 @@ static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex)
FLEXCAN_REG32_CONTENT(ramAddr) = 0U; FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
} }
for (u8Index = 0U; u8Index < MASK_WORD_NUM; u8Index++) for (u8Index = 0U; u8Index < MASK_WORD_NUM; u8Index++)
{ {
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, MASK_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, MASK_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN);
FLEXCAN_REG32_CONTENT(ramAddr) = 0U; FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
} }
for (u8Index = 0U; u8Index < SMBTX_WORD_NUM; u8Index++) for (u8Index = 0U; u8Index < SMBTX_WORD_NUM; u8Index++)
{ {
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, SMBTX_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, SMBTX_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN);
@ -516,7 +676,7 @@ static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex)
FLEXCAN_REG32_CONTENT(ramAddr) = 0U; FLEXCAN_REG32_CONTENT(ramAddr) = 0U;
} }
/* can fd only */ // can fd only
if (FLEXCAN_LL_CheckFdInstance(u8CanIndex) == FLEXCAN_ERROR_OK) if (FLEXCAN_LL_CheckFdInstance(u8CanIndex) == FLEXCAN_ERROR_OK)
{ {
for (u8Index = 0U; u8Index < FD_SMBTX_WORD_NUM; u8Index++) for (u8Index = 0U; u8Index < FD_SMBTX_WORD_NUM; u8Index++)
@ -538,7 +698,7 @@ static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex)
} }
/** initial rx fifo */ // initial rx fifo
for (u8Index = 0U; u8Index < ERX_FIFO_WORD_NUM; u8Index++) for (u8Index = 0U; u8Index < ERX_FIFO_WORD_NUM; u8Index++)
{ {
ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, ERX_FIFO_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, ERX_FIFO_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN);
@ -554,7 +714,7 @@ static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex)
} }
} }
*/
/** /**
@ -1435,7 +1595,7 @@ FLEXCAN_ErrorType FLEXCAN_Init(uint8_t u8CanIndex, const FLEXCAN_InitType *const
FLEXCAN_HWA_SetCtrl1(pCan, u32TempCtrl1); FLEXCAN_HWA_SetCtrl1(pCan, u32TempCtrl1);
/* initial RAM to avoid ECC error */ /* initial RAM to avoid ECC error CFIFCFIF*/
FLEXCAN_LL_EmbededRam_Init(u8CanIndex); FLEXCAN_LL_EmbededRam_Init(u8CanIndex);
u32TempMcr = FLEXCAN_MCR_MDIS(0) | /* enable pCan module */ u32TempMcr = FLEXCAN_MCR_MDIS(0) | /* enable pCan module */
@ -2022,6 +2182,7 @@ FLEXCAN_ErrorType FLEXCAN_Stop(uint8_t u8CanIndex)
return tRetVal; return tRetVal;
} }
/** /**
* @brief Transmit data, if tx disable, must call FLEXCAN_TransmitProcess after transmiting * @brief Transmit data, if tx disable, must call FLEXCAN_TransmitProcess after transmiting
* *
@ -2160,21 +2321,7 @@ FLEXCAN_ErrorType FLEXCAN_TransmitData(uint8_t u8CanIndex, const FLEXCAN_TxMsgTy
/* CODE set 0x0C to transmit */ /* CODE set 0x0C to transmit */
FLEXCAN_MB_CODE_SET(u32TempAddr, 0x0CU); FLEXCAN_MB_CODE_SET(u32TempAddr, 0x0CU);
if (pTxMsg->bWaitTxCompleted)
{
}
else
{
u32WordLen = FLEXCAN_HWA_GetFlag1NoFifoFlag(pCan, u8TxRealMbIndex);
if (u32WordLen == 0U)
{
tRetVal = FLEXCAN_ERROR_TIMEOUT;
}
}
// -------------------------------
/*
if (pTxMsg->bWaitTxCompleted) if (pTxMsg->bWaitTxCompleted)
{ {
u32TempAddr = 0U; u32TempAddr = 0U;
@ -2182,10 +2329,8 @@ FLEXCAN_ErrorType FLEXCAN_TransmitData(uint8_t u8CanIndex, const FLEXCAN_TxMsgTy
while ((u32WordLen == 0U) && (u32TempAddr++ < pTxMsg->u16WaitTxTimeout)) while ((u32WordLen == 0U) && (u32TempAddr++ < pTxMsg->u16WaitTxTimeout))
{ {
u32WordLen = FLEXCAN_HWA_GetFlag1NoFifoFlag(pCan, u8TxRealMbIndex); u32WordLen = FLEXCAN_HWA_GetFlag1NoFifoFlag(pCan, u8TxRealMbIndex);
// osThreadYield();
} }
if (u32WordLen == 0U) if (u32WordLen == 0U)
{ {
tRetVal = FLEXCAN_ERROR_TIMEOUT; tRetVal = FLEXCAN_ERROR_TIMEOUT;
@ -2200,9 +2345,7 @@ FLEXCAN_ErrorType FLEXCAN_TransmitData(uint8_t u8CanIndex, const FLEXCAN_TxMsgTy
tRetVal = FLEXCAN_ERROR_TIMEOUT; tRetVal = FLEXCAN_ERROR_TIMEOUT;
} }
} }
*/
// --------------------------
} }
} }
#if FLEXCAN_CHECK_PARAMETERS == STD_ON #if FLEXCAN_CHECK_PARAMETERS == STD_ON
@ -2213,31 +2356,6 @@ FLEXCAN_ErrorType FLEXCAN_TransmitData(uint8_t u8CanIndex, const FLEXCAN_TxMsgTy
} }
bool IsTxBufferFree_ByCode(uint8_t canIndex, uint8_t handler) {
FLEXCAN_Type *pCan = s_aFlexCan_InstanceTable[canIndex];
FLEXCAN_SettingType *pCurSetting = &s_aFlexCan_Setting_Table[canIndex];
if (handler >= pCurSetting->u8TxMbCnt1) {
return false; // Неверный handler
}
uint8_t realIndex = pCurSetting->u8TxMbStart1 + handler;
// Читаем код из первого слова MB
uint32_t addr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(
&(pCan->RAM[0U]), realIndex, pCurSetting->eMbDataWidth, 0U);
uint32_t code = FLEXCAN_MB_CODE_GET(addr);
// Коды состояния буфера:
// 0x0 = EMPTY (не использовался) - СВОБОДЕН
// 0x8 = INACTIVE (неактивен) - СВОБОДЕН
// 0xC = TRANSMITTING (передаёт) - ЗАНЯТ
// 0x9 = ABORTING (прерывается) - ЗАНЯТ
return (code == 0x0 || code == 0x8);
}
/** /**
* @brief Process flag after transmit * @brief Process flag after transmit
* *
@ -2850,3 +2968,27 @@ void FLEXCAN_IRQHandler(uint8_t u8CanIndex)
#endif #endif
} }
bool IsTxBufferFree_ByCode(uint8_t canIndex, uint8_t handler) {
FLEXCAN_Type *pCan = s_aFlexCan_InstanceTable[canIndex];
FLEXCAN_SettingType *pCurSetting = &s_aFlexCan_Setting_Table[canIndex];
if (handler >= pCurSetting->u8TxMbCnt1) {
return false; // Неверный handler
}
uint8_t realIndex = pCurSetting->u8TxMbStart1 + handler;
// Читаем код из первого слова MB
uint32_t addr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(
&(pCan->RAM[0U]), realIndex, pCurSetting->eMbDataWidth, 0U);
uint32_t code = FLEXCAN_MB_CODE_GET(addr);
// Коды состояния буфера:
// 0x0 = EMPTY (не использовался) - СВОБОДЕН
// 0x8 = INACTIVE (неактивен) - СВОБОДЕН
// 0xC = TRANSMITTING (передаёт) - ЗАНЯТ
// 0x9 = ABORTING (прерывается) - ЗАНЯТ
return (code == 0x0 || code == 0x8);
}

8
Src/fc7xxx_driver_fmc.c
View File

@ -118,7 +118,7 @@ static FMC_Lock_StatusType FMCDRIVER_DFlashLockRegion(const FMC_InstanceType eIn
u32Index = 2U; u32Index = 2U;
if ((u32Address >= DFLASH_ADDR_START) && (u32Address <= DFLASH_ADDR_END)) if ((u32Address >= DFLASH_ADDR_START) && (u32Address <= DFLASH_ADDR_END))
{ {
u32Temp = 1UL << ((u32Address - DFLASH_ADDR_START - DFLASH_BANK0_SIZE * (u32Index - 2U)) >> 13); u32Temp = 1UL << ((u32Address - DFLASH_ADDR_START - DFLASH_BANK0_SIZE_ * (u32Index - 2U)) >> 13);
u32Temp = bLock ? (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) | u32Temp) : (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) & ~u32Temp); u32Temp = bLock ? (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) | u32Temp) : (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) & ~u32Temp);
FMC_HWA_SetFBFPELCKValue(pFMC, u32Index, u32Temp); FMC_HWA_SetFBFPELCKValue(pFMC, u32Index, u32Temp);
} }
@ -188,11 +188,11 @@ FMC_Lock_StatusType FMCDRIVER_FlashLock(FMC_DRIVER_Lock_ParamType *pFmcParam)
void FMCDRIVER_SwapBlock(const FMC_InstanceType eInstance, FMC_API_ACTIVE_BLOCK_TYPE bActive) void FMCDRIVER_SwapBlock(const FMC_InstanceType eInstance, FMC_API_ACTIVE_BLOCK_TYPE bActive)
{ {
FMC_Type *const pFMC = s_apFmcBase[eInstance]; FMC_Type *const pFMC = s_apFmcBase[eInstance];
// if (0U == FMC_HWA_GetOTACtrlValue(pFMC, 0)) if (0U == FMC_HWA_GetOTACtrlValue(pFMC, 0))
// { {
FMC_HWA_SetOTAActive(pFMC, 0, bActive); FMC_HWA_SetOTAActive(pFMC, 0, bActive);
FMC_HWA_SetOTAEnable(pFMC, 0); FMC_HWA_SetOTAEnable(pFMC, 0);
// } }
} }
/** /**