725 lines
18 KiB
C
725 lines
18 KiB
C
/**
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* @file HwA_scm.h
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* @author flagchip
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* @brief Hardware access layer for SCM
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* @version 2.0.0
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* @date 2024-08-20
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*
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* SDK Version: 2.6.0
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*
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* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2023-12-15 Flagchip055 N/A First version for FC7300
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* 2.0.0 2024-10-12 Flagchip055 N/A Change version and release
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******************************************************************************** */
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#ifndef _HWA_SCM_H_
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#define _HWA_SCM_H_
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#include "device_header.h"
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#if SCM_INSTANCE_COUNT > 0U
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/**
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* @brief SCM adc trigger selection
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*/
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typedef enum
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{
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SCM_ADC_INSTANCE_0 = 0U,
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SCM_ADC_INSTANCE_1 = 1U,
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SCM_ADC_INSTANCE_2 = 2U,
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SCM_ADC_INSTANCE_3 = 3U,
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SCM_ADC_INSTANCE_4 = 4U,
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SCM_ADC_INSTANCE_5 = 5U,
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} SCM_AdcInstance;
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/**
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* @brief SCM adc trigger selection
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*/
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typedef enum
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{
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SCM_ADC_TRIGGER_PTIMER = 0U,
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SCM_ADC_TRIGGER_TRGSEL = 1U,
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} SCM_AdcTriggerSel;
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/**
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* @brief SCM adc pre-trigger selection
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*/
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typedef enum
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{
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SCM_ADC_PRE_TRIGGER_PTIMER = 0U,
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SCM_ADC_PRE_TRIGGER_TRGSEL = 1U,
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SCM_ADC_PRE_TRIGGER_SCM_SOFTWARE_PRE_TRIGGER = 2U,
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} SCM_AdcPreTriggerSel;
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/**
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* @brief SCM software trigger source
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*/
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typedef enum
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{
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SCM_SOFTWARE_PRE_TRIGGER_0 = 0U, /*!< SCM software pre-trigger 0 */
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SCM_SOFTWARE_PRE_TRIGGER_1 = 1U, /*!< SCM software pre-trigger 1 */
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SCM_SOFTWARE_PRE_TRIGGER_2 = 2U, /*!< SCM software pre-trigger 2 */
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SCM_SOFTWARE_PRE_TRIGGER_3 = 3U, /*!< SCM software pre-trigger 3 */
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} SCM_SoftwarePreTrigger;
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/**
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* @defgroup HwA_scm HwA_scm
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* @ingroup module_driver_scm
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* @{
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*/
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/********* Local typedef ************/
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/********* Local inline function ************/
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/**
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* @brief Get UIDL data(Unique identification for the chip. Loaded from NVR)
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*
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* @return return value
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*/
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LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDL(void)
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{
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return SCM->UIDL;
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}
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/**
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* @brief Get UIDML data(Unique identification for the chip. Loaded from NVR)
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*
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* @return return value
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*/
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LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDML(void)
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{
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return SCM->UIDML;
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}
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/**
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* @brief Get UIDMH data(Unique identification for the chip. Loaded from NVR)
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*
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* @return return value
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*/
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LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDMH(void)
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{
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return SCM->UIDMH;
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}
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/**
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* @brief Get UIDH data(Unique identification for the chip. Loaded from NVR)
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*
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* @return return value
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*/
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LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDH(void)
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{
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return SCM->UIDH;
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}
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/**
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* @brief Get Family Identification
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*
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* @return return value
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*/
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LOCAL_INLINE uint8_t SCM_HWA_GetData_FamilyID(void)
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{
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return (uint8_t)((SCM->PARTID0 & (uint32_t)SCM_PARTID0_FAM_ID_MASK) >> (uint32_t)SCM_PARTID0_FAM_ID_SHIFT);
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}
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/**
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* @brief Get Revision Identification
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*
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* @return return value
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*/
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LOCAL_INLINE uint8_t SCM_HWA_GetData_RevID(void)
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{
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return (uint8_t)((SCM->PARTID0 & (uint32_t)SCM_PARTID0_REVID_MASK));
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}
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/**
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* @brief Set the ISM_ROUTING register value
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*
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* @param u32Val value to be set
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*/
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LOCAL_INLINE void SCM_HWA_Set_ISM_ROUTING(uint32_t u32Val)
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{
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SCM->ISM_ROUTING = u32Val;
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}
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/**
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* @brief Get CHIPCFG0 register status
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*
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* @return return value
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*/
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LOCAL_INLINE uint32_t SCM_HWA_Get_CHIPCFG0(void)
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{
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return SCM->CHIPCFG0;
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}
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/**
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* @brief Set the SOCMISC register value
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*
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* @param u32Val value to be set
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*/
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LOCAL_INLINE void SCM_HWA_Set_SOCMISC(uint32_t u32Val)
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{
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SCM->SOCMISC = u32Val;
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}
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/**
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* @brief Get the SOCMISC register status
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*
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* @return Lock status
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*/
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LOCAL_INLINE uint32_t SCM_HWA_Get_SOCMISC(void)
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{
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return SCM->SOCMISC;
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}
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#if SCM_GET_DEVICEID_SUPPORT
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/**
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* @brief Get device ID
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*
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* @return return value
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*/
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LOCAL_INLINE uint32_t SCM_HWA_GetData_DeviceID(void)
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{
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return ((SCM->CHIPCFG1 & (uint32_t)SCM_CHIPCFG1_DEVICE_ID_MASK) >> (uint32_t)SCM_CHIPCFG1_DEVICE_ID_SHIFT);
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}
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#endif
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/**
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* @brief Get SYSAP_CTRL register status
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*
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* @return Register status
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*/
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LOCAL_INLINE uint32_t SCM_HWA_Get_SYSAP_CTRL(void)
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{
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return SCM->SYSAP_CTRL;
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}
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#if SCM_CRC_SUPPORT
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/**
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* @brief Set the CRCCSR register value
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*
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* @param u32Val value to be set
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*/
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LOCAL_INLINE void SCM_HWA_Set_CRCCSR(uint32_t u32Val)
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{
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SCM->CRCCSR = u32Val;
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}
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/**
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* @brief Get CRCCSR register status
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*
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* @return Register status
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*/
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LOCAL_INLINE uint32_t SCM_HWA_Get_CRCCSR(void)
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{
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return SCM->CRCCSR;
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}
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/**
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* @brief Set CRC check enable/disable
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*
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* @param bEnable Enable/Disable
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*/
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LOCAL_INLINE void SCM_HWA_SetCrcCheckEnable(bool bEnable)
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{
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SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_CHKEN_MASK))) | SCM_CRCCSR_CHKEN(bEnable);
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}
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/**
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* @brief Set CRC trigger enable/disable
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*
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* @param bEnable Enable/Disable
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*/
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LOCAL_INLINE void SCM_HWA_SetCrcTriggerEnable(bool bEnable)
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{
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SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_TRGEN_MASK))) | SCM_CRCCSR_TRGEN(bEnable);
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}
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/**
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* @brief Set CRC error out enable/disable
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*
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* @param bEnable Enable/Disable
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*/
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LOCAL_INLINE void SCM_HWA_SetCrcErrorOutEnable(bool bEnable)
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{
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SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_EOEN_MASK))) | SCM_CRCCSR_EOEN(bEnable);
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}
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/**
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* @brief Clear CRC error flag
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*/
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LOCAL_INLINE void SCM_HWA_ClearCrcErrorFlag(void)
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{
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SCM->CRCCSR |= SCM_CRCCSR_ERR_MASK;
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}
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/**
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* @brief Get CRC Done Flag
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*
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* @return CRC Done Flag
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*/
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LOCAL_INLINE bool SCM_HWA_GetCrcDoneFlag(void)
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{
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return ((SCM->CRCCSR & SCM_CRCCSR_BUY_MASK) == SCM_CRCCSR_BUY_MASK) ? false : true;
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}
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/**
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* @brief Set CRC software generate enable/disable
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*
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* @param bEnable Enable/Disable
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*/
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LOCAL_INLINE void SCM_HWA_SetCrcGenerateEnable(bool bEnable)
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{
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SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_GEN_MASK))) | SCM_CRCCSR_GEN(bEnable);
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}
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/**
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* @brief Get CRC result
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*
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* @return CRC result
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*/
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LOCAL_INLINE uint32_t SCM_HWA_GetCrcResult(void)
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{
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return SCM->CRCRES;
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}
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#endif
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/**
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* @brief Set the FTU_GTBC register value
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*
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* @param u32Val value to be set
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*/
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LOCAL_INLINE void SCM_HWA_Set_FTU_GTBC(uint32_t u32Val)
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{
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#if defined (SCM_FTU_GTBC_FTU_GTBC_MASK)
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SCM->FTU_GTBC = u32Val;
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#elif defined (SCM_FTU_GTBC_FTU0_GTBC_MASK)
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SCM->FTU_GTBC = u32Val;
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#else
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#error "No valid SCM_FTU_GTB*_FTU*_GTBC_MASK definition"
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#endif
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}
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#if defined(SCM_GTBC_TPU_SELECT_SUPPORT) && (SCM_GTBC_TPU_SELECT_SUPPORT)
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/**
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* @brief Configure TPU global time base control selection
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*
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* @param bEn Enable or disable TPU Global Time Base
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*/
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LOCAL_INLINE void SCM_HWA_ConfigTpuGTBSelect(bool bEn)
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{
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#if defined(SCM_FTU_GTBC_ETPU_GTBC_MASK)
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SCM->FTU_GTBC &= ~(uint32_t)SCM_FTU_GTBC_ETPU_GTBC_MASK;
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SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_ETPU_GTBC(bEn);
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#elif defined(SCM_FTU_GTBC_TPU_GTBC_MASK)
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SCM->FTU_GTBC &= ~(uint32_t)SCM_FTU_GTBC_TPU_GTBC_MASK;
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SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_TPU_GTBC(bEn);
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#else
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#error "No valid SCM_FTU_GTBC_*TPU definition"
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#endif
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}
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#endif
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/**
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* @brief Set TPU clock enable/disable
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*
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* @param bEnable Enable/Disable
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*/
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LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_TPUClock(bool bEnable)
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{
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#if defined(SCM_SUBSYSPCC_SUPPORT) && defined(SCM_SUBSYSPCC_SUPPORT)
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SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_CLKEN_TPU_MASK)) |
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SCM_SUBSYS_PCC_CLKEN_TPU(bEnable));
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#elif (SCM_TPUPCC_SUPPORT && SCM_TPUPCC_SUPPORT)
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SCM->TPU_PCC = ((SCM->TPU_PCC & (~(uint32_t)SCM_TPU_PCC_CLKEN_TPU_MASK)) |
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SCM_TPU_PCC_CLKEN_TPU(bEnable));
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#else
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PROCESS_UNUSED_VAR(bEnable);
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#endif
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}
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/**
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* @brief Set SubSystem clock enable/disable
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*
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* @param bEnable Enable/Disable
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*/
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LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_SubSystemClock(bool bEnable)
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{
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#if (SCM_FLEXHSM_PCC_SUPPORT && SCM_FLEXHSM_PCC_SUPPORT)
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SCM->FLEXHSM_PCC = ((SCM->FLEXHSM_PCC & (~(uint32_t)SCM_FLEXHSM_PCC_CLKEN_FLEXHSM_MASK)) |
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SCM_FLEXHSM_PCC_CLKEN_FLEXHSM(bEnable));
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#elif (SCM_SUBSYSPCC_SUPPORT && SCM_SUBSYSPCC_SUPPORT)
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SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_CLKEN_SUBSYS_MASK)) |
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SCM_SUBSYS_PCC_CLKEN_SUBSYS(bEnable));
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#else
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PROCESS_UNUSED_VAR(bEnable);
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#endif
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}
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#if defined(SCM_GTBC_FTU_SELECT_SUPPORT) && (SCM_GTBC_FTU_SELECT_SUPPORT)
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/**
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* @brief Set FTU global time base control selection
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*
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* @param u32SelectedFtu The GTBC mask of Selected Ftu instance,it is the or value of SCM_FTUGTBCtrlType.
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* eg.u32SelectedFtu == 1 means FTU0 selected, u32SelectedFtu == 5 means FTU0 and FTU2 selected.
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*/
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LOCAL_INLINE void SCM_HWA_SetFtuGTBSelect(uint32_t u32SelectedFtu)
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{
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SCM->FTU_GTBC |= (u32SelectedFtu & 0xFFu) << SCM_FTU_GTBC_FTU0_GTBC_SHIFT;
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}
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/**
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* @brief Clear FTU global time base control selection
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*
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* @param u32SelectedFtu The GTBC mask of Selected Ftu instance,it is the or value of SCM_FTUGTBCtrlType.
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* eg.u32SelectedFtu == 1 means FTU0 selected, u32SelectedFtu == 5 means FTU0 and FTU2 selected.
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*/
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LOCAL_INLINE void SCM_HWA_ClearFtuGTBSelect(uint32_t u32SelectedFtu)
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{
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SCM->FTU_GTBC &= ~(uint32_t)((u32SelectedFtu & 0xFFu) << SCM_FTU_GTBC_FTU0_GTBC_SHIFT);
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}
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#endif
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#if defined(SCM_FTU_GTBC_TSTMP_TRIG_SUPPORT) && (SCM_FTU_GTBC_TSTMP_TRIG_SUPPORT)
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/**
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* @brief Configure FTU Global Time Base Control Mask Register
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*
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* @param u8FtuIndex The selected FTU instance (must be 0 ~ 7)
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* @param u32Value Value to be set (must be 0 ~ 15)
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*/
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LOCAL_INLINE void SCM_HWA_ConfigFtuGTBMask(uint8_t u8FtuIndex, uint32_t u32Value)
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{
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#if defined(SCM_FTU_GTBEM_FTU0_GTBEM_MASK)
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SCM->FTU_GTBEM = (SCM->FTU_GTBEM & (~((uint32_t)SCM_FTU_GTBEM_FTU0_GTBEM_MASK << (SCM_FTU_GTBEM_FTU0_GTBEM_WIDTH * u8FtuIndex))))
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| (((uint32_t)u32Value & SCM_FTU_GTBEM_FTU0_GTBEM_MASK) << (SCM_FTU_GTBEM_FTU0_GTBEM_WIDTH * u8FtuIndex));
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#elif defined(SCM_FTU_GTBCM_FTU0_GTBCM_MASK)
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SCM->FTU_GTBCM = (SCM->FTU_GTBCM & (~((uint32_t)SCM_FTU_GTBCM_FTU0_GTBCM_MASK << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex))))
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| (((uint32_t)u32Value & SCM_FTU_GTBCM_FTU0_GTBCM_MASK) << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex));
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#else
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#error "No valid SCM_FTU_GTB*M_FTU*_GTB*M definition"
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#endif
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}
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/**
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* @brief Clear FTU Global Time Base Control Mask Register
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*
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* @param u8FtuIndex The selected FTU instance (must be 0 ~ 7)
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*/
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LOCAL_INLINE void SCM_HWA_ClearFtuGTBMask(uint8_t u8FtuIndex)
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{
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#if defined(SCM_FTU_GTBEM_FTU0_GTBEM_MASK)
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SCM->FTU_GTBEM &= ~ ((uint32_t)SCM_FTU_GTBEM_FTU0_GTBEM_MASK << (SCM_FTU_GTBEM_FTU0_GTBEM_WIDTH * u8FtuIndex));
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#elif defined(SCM_FTU_GTBCM_FTU0_GTBCM_MASK)
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SCM->FTU_GTBCM &= ~ ((uint32_t)SCM_FTU_GTBCM_FTU0_GTBCM_MASK << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex));
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#else
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#error "No valid SCM_FTU_GTB*M_FTU*_GTB*M definition"
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#endif
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}
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#endif
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#if SCM_PTIMER_CHANNEL_SELECTION_SUPPORT
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/**
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* @brief Set the ADC_ROUTING2 register value
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*
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* @param u32Val value to be set
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*/
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LOCAL_INLINE void SCM_HWA_Set_ADC_ROUTING2(uint32_t u32Val)
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{
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SCM->ADC_ROUTING2 = u32Val;
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}
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/**
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* @brief Get the ADC_ROUTING2 register status
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*
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* @return Lock status
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*/
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LOCAL_INLINE uint32_t SCM_HWA_Get_ADC_ROUTING2(void)
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{
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return SCM->ADC_ROUTING2;
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}
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#endif
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#ifdef SCM_CPU1VTOR_CPU1_INIT_VECTOR_MASK
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/**
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* @brief Set the CPU1VTOR register value
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*
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* @param u32Val value to be set
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*/
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LOCAL_INLINE void SCM_HWA_Set_CPU1VTOR(uint32_t u32Val)
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{
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SCM->CPU1VTOR = u32Val;
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}
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/**
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* @brief Get the CPU1VTOR register status
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*
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* @return Lock status
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*/
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LOCAL_INLINE uint32_t SCM_HWA_Get_CPU1VTOR(void)
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{
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return SCM->CPU1VTOR;
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}
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/**
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* @brief Set CPU1 Vector Table Register vector initial vector
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*
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* @param u32Value value to be set
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*/
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LOCAL_INLINE void SCM_HWA_CPU1VTOR_SetVector(uint32_t u32Value)
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{
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uint32_t u32RegVal = SCM->CPU1VTOR;
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SCM->CPU1VTOR = ((u32RegVal & (~(uint32_t)SCM_CPU1VTOR_CPU1_INIT_VECTOR_MASK)) | SCM_CPU1VTOR_CPU1_INIT_VECTOR(u32Value));
|
|
}
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|
#endif
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|
|
|
#ifdef SCM_CPU2VTOR_CPU2_INIT_VECTOR_MASK
|
|
/**
|
|
* @brief Set the CPU2VTOR register value
|
|
*
|
|
* @param u32Val value to be set
|
|
*/
|
|
LOCAL_INLINE void SCM_HWA_Set_CPU2VTOR(uint32_t u32Val)
|
|
{
|
|
SCM->CPU2VTOR = u32Val;
|
|
}
|
|
|
|
/**
|
|
* @brief Get the CPU2VTOR register status
|
|
*
|
|
* @return Lock status
|
|
*/
|
|
LOCAL_INLINE uint32_t SCM_HWA_Get_CPU2VTOR(void)
|
|
{
|
|
return SCM->CPU2VTOR;
|
|
}
|
|
|
|
/**
|
|
* @brief Set Core Hold Register vector initial vector
|
|
*
|
|
* @param u32Value value to be set
|
|
*/
|
|
LOCAL_INLINE void SCM_HWA_CPU2VTOR_SetVector(uint32_t u32Value)
|
|
{
|
|
uint32_t u32RegVal = SCM->CPU2VTOR;
|
|
SCM->CPU2VTOR = ((u32RegVal & (~(uint32_t)SCM_CPU2VTOR_CPU2_INIT_VECTOR_MASK)) | SCM_CPU2VTOR_CPU2_INIT_VECTOR(u32Value));
|
|
}
|
|
#endif
|
|
|
|
#ifdef SCM_CPU3VTOR_CPU3_INIT_VECTOR_MASK
|
|
/**
|
|
* @brief Set the CPU3VTOR register value
|
|
*
|
|
* @param u32Val value to be set
|
|
*/
|
|
LOCAL_INLINE void SCM_HWA_Set_CPU3VTOR(uint32_t u32Val)
|
|
{
|
|
SCM->CPU3VTOR = u32Val;
|
|
}
|
|
|
|
/**
|
|
* @brief Get the CPU3VTOR register status
|
|
*
|
|
* @return Lock status
|
|
*/
|
|
LOCAL_INLINE uint32_t SCM_HWA_Get_CPU3VTOR(void)
|
|
{
|
|
return SCM->CPU3VTOR;
|
|
}
|
|
|
|
/**
|
|
* @brief Set Core Hold Register vector initial vector
|
|
*
|
|
* @param u32Value value to be set
|
|
*/
|
|
LOCAL_INLINE void SCM_HWA_CPU3VTOR_SetVector(uint32_t u32Value)
|
|
{
|
|
uint32_t u32RegVal = SCM->CPU3VTOR;
|
|
SCM->CPU3VTOR = ((u32RegVal & (~(uint32_t)SCM_CPU3VTOR_CPU3_INIT_VECTOR_MASK)) | SCM_CPU3VTOR_CPU3_INIT_VECTOR(u32Value));
|
|
}
|
|
#endif
|
|
|
|
#ifdef SCM_CORE_HOLD_CPU1_CORE_HOLD_MASK
|
|
/**
|
|
* @brief Set cpu1 hold enable status
|
|
*
|
|
* @param bEnable Enable/Disable status
|
|
*/
|
|
LOCAL_INLINE void SCM_HWA_SetCOREHOLD_Cpu1Hold(bool bEnable)
|
|
{
|
|
if (true == bEnable)
|
|
{
|
|
SCM->CORE_HOLD |= (uint32_t)SCM_CORE_HOLD_CPU1_CORE_HOLD_MASK;
|
|
}
|
|
else
|
|
{
|
|
SCM->CORE_HOLD &= ~(uint32_t)SCM_CORE_HOLD_CPU1_CORE_HOLD_MASK;
|
|
}
|
|
}
|
|
#endif
|
|
#ifdef SCM_CORE_HOLD_CPU2_CORE_HOLD_MASK
|
|
/**
|
|
* @brief Set cpu2 hold enable status
|
|
*
|
|
* @param bEnable Enable/Disable status
|
|
*/
|
|
LOCAL_INLINE void SCM_HWA_SetCOREHOLD_Cpu2Hold(bool bEnable)
|
|
{
|
|
if (true == bEnable)
|
|
{
|
|
SCM->CORE_HOLD |= (uint32_t)SCM_CORE_HOLD_CPU2_CORE_HOLD_MASK;
|
|
}
|
|
else
|
|
{
|
|
SCM->CORE_HOLD &= ~(uint32_t)SCM_CORE_HOLD_CPU2_CORE_HOLD_MASK;
|
|
}
|
|
}
|
|
#endif
|
|
#ifdef SCM_CORE_HOLD_CPU3_CORE_HOLD_MASK
|
|
/**
|
|
* @brief Set cpu3 hold enable status
|
|
*
|
|
* @param bEnable Enable/Disable status
|
|
*/
|
|
LOCAL_INLINE void SCM_HWA_SetCOREHOLD_Cpu3Hold(bool bEnable)
|
|
{
|
|
if (true == bEnable)
|
|
{
|
|
SCM->CORE_HOLD |= (uint32_t)SCM_CORE_HOLD_CPU3_CORE_HOLD_MASK;
|
|
}
|
|
else
|
|
{
|
|
SCM->CORE_HOLD &= ~(uint32_t)SCM_CORE_HOLD_CPU3_CORE_HOLD_MASK;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#if SCM_ADC_PRE_TRIGGER_SEL_SUPPORT
|
|
LOCAL_INLINE void SCM_HWA_SetAdcPretriggerSel(SCM_AdcInstance eInstance, SCM_AdcPreTriggerSel ePreTriggerSel)
|
|
{
|
|
#if ADC_INSTANCE_COUNT > 5U
|
|
if (eInstance == SCM_ADC_INSTANCE_5)
|
|
{
|
|
SCM->ADC_ROUTING1 = (SCM->ADC_ROUTING1 & ~SCM_ADC_ROUTING1_ADC5_PRETRGSEL_MASK) |
|
|
SCM_ADC_ROUTING1_ADC5_PRETRGSEL(ePreTriggerSel);
|
|
}
|
|
else
|
|
#endif
|
|
#if ADC_INSTANCE_COUNT > 4U
|
|
if (eInstance == SCM_ADC_INSTANCE_4)
|
|
{
|
|
SCM->ADC_ROUTING1 = (SCM->ADC_ROUTING1 & ~SCM_ADC_ROUTING1_ADC4_PRETRGSEL_MASK) |
|
|
SCM_ADC_ROUTING1_ADC4_PRETRGSEL(ePreTriggerSel);
|
|
}
|
|
else
|
|
#endif
|
|
#if ADC_INSTANCE_COUNT > 3U
|
|
if (eInstance == SCM_ADC_INSTANCE_3)
|
|
{
|
|
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC3_PRETRGSEL_MASK) |
|
|
SCM_ADC_ROUTING_ADC3_PRETRGSEL(ePreTriggerSel);
|
|
}
|
|
else
|
|
#endif
|
|
#if ADC_INSTANCE_COUNT > 2U
|
|
if (eInstance == SCM_ADC_INSTANCE_2)
|
|
{
|
|
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC2_PRETRGSEL_MASK) |
|
|
SCM_ADC_ROUTING_ADC2_PRETRGSEL(ePreTriggerSel);
|
|
}
|
|
else
|
|
#endif
|
|
#if ADC_INSTANCE_COUNT > 1U
|
|
if (eInstance == SCM_ADC_INSTANCE_1)
|
|
{
|
|
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC1_PRETRGSEL_MASK) |
|
|
SCM_ADC_ROUTING_ADC1_PRETRGSEL(ePreTriggerSel);
|
|
}
|
|
else
|
|
#endif
|
|
#if ADC_INSTANCE_COUNT > 0U
|
|
if (eInstance == SCM_ADC_INSTANCE_0)
|
|
{
|
|
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC0_PRETRGSEL_MASK) |
|
|
SCM_ADC_ROUTING_ADC0_PRETRGSEL(ePreTriggerSel);
|
|
}
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if SCM_ADC_TRIGGER_SEL_SUPPORT
|
|
LOCAL_INLINE void SCM_HWA_SetAdcTriggerSel(SCM_AdcInstance eInstance, SCM_AdcTriggerSel eTriggerSel)
|
|
{
|
|
#if ADC_INSTANCE_COUNT > 5U
|
|
if (eInstance == SCM_ADC_INSTANCE_5)
|
|
{
|
|
SCM->ADC_ROUTING1 = (SCM->ADC_ROUTING1 & ~SCM_ADC_ROUTING1_ADC5_TRGSEL_MASK) |
|
|
SCM_ADC_ROUTING1_ADC5_TRGSEL(eTriggerSel);
|
|
}
|
|
else
|
|
#endif
|
|
#if ADC_INSTANCE_COUNT > 4U
|
|
if (eInstance == SCM_ADC_INSTANCE_4)
|
|
{
|
|
SCM->ADC_ROUTING1 = (SCM->ADC_ROUTING1 & ~SCM_ADC_ROUTING1_ADC4_TRGSEL_MASK) |
|
|
SCM_ADC_ROUTING1_ADC4_TRGSEL(eTriggerSel);
|
|
}
|
|
else
|
|
#endif
|
|
#if ADC_INSTANCE_COUNT > 3U
|
|
if (eInstance == SCM_ADC_INSTANCE_3)
|
|
{
|
|
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC3_TRGSEL_MASK) |
|
|
SCM_ADC_ROUTING_ADC3_TRGSEL(eTriggerSel);
|
|
}
|
|
else
|
|
#endif
|
|
#if ADC_INSTANCE_COUNT > 2U
|
|
if (eInstance == SCM_ADC_INSTANCE_2)
|
|
{
|
|
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC2_TRGSEL_MASK) |
|
|
SCM_ADC_ROUTING_ADC2_TRGSEL(eTriggerSel);
|
|
}
|
|
else
|
|
#endif
|
|
#if ADC_INSTANCE_COUNT > 1U
|
|
if (eInstance == SCM_ADC_INSTANCE_1)
|
|
{
|
|
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC1_TRGSEL_MASK) |
|
|
SCM_ADC_ROUTING_ADC1_TRGSEL(eTriggerSel);
|
|
}
|
|
else
|
|
#endif
|
|
#if ADC_INSTANCE_COUNT > 0U
|
|
if (eInstance == SCM_ADC_INSTANCE_0)
|
|
{
|
|
SCM->ADC_ROUTING = (SCM->ADC_ROUTING & ~SCM_ADC_ROUTING_ADC0_TRGSEL_MASK) |
|
|
SCM_ADC_ROUTING_ADC0_TRGSEL(eTriggerSel);
|
|
}
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if SCM_HSADC_BIAS_FORCE_ENABLE_SUPPORT
|
|
|
|
LOCAL_INLINE void SCM_HWA_SetHsadcBiasForceEnable(void)
|
|
{
|
|
SCM->ADC_CFG = SCM->ADC_CFG | (1U << 31U);
|
|
}
|
|
|
|
#endif
|
|
|
|
/** @}*/
|
|
|
|
#endif /* #if SCM_INSTANCE_COUNT > 0U */
|
|
|
|
#endif /*#ifndef _HWA_SCM_H_ */
|