257 lines
8.0 KiB
C
257 lines
8.0 KiB
C
/**
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* @file HwA_hrpwm.h
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* @author Flagchip
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* @brief HRPWM hardware access layer
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* @version 2.0.0
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* @date 2024-11-06
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*
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* SDK Version: 2.6.0
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*
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* @copyright Copyright (c) 2020-2024 Flagchip Semiconductors Co., Ltd.
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*
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*/
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/* ********************************************************************************
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* Revision History:
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*
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* Version Date Initials CR# Descriptions
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* --------- ---------- ------------ ---------- ---------------
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* 0.1.0 2023-12-15 Flagchip070 N/A First version for FC7300
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* 2.0.0 2024-10-12 Flagchip070 N/A Change version and release
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******************************************************************************** */
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#ifndef _HWA_HRPWM_H_
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#define _HWA_HRPWM_H_
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#include "device_header.h"
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#if defined(HRPWM_INSTANCE_COUNT) && (HRPWM_INSTANCE_COUNT > 0U)
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/**
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* @defgroup HwA_hrpwm HwA_hrpwm
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* @ingroup module_driver_hrpwm
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* @{
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*/
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/* Define the unlock write code for the HRPWM module, used to unlock HRPWM registers for configuration */
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#define HRPWM_UNLOCK_WRITE_CODE 0x10248888U
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/* Define the lock write code for the HRPWM module, used to lock HRPWM registers to protect configuration */
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#define HRPWM_LOCK_WRITE_CODE 0x1024CAFEU
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/**
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* @brief Enable or disable an HRPWM channel
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param u8Channel The HRPWM channel number to control
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* @param bEnable True to enable the channel, False to disable the channel
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*/
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LOCAL_INLINE void HRPWM_HWA_SetChannelEnable(HRPWM_Type * const pHrpwm, uint8_t u8Channel, bool bEnable)
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{
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pHrpwm->EN_CTRL = (pHrpwm->EN_CTRL & (~(1U << u8Channel))) | ((uint32_t)bEnable << u8Channel);
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}
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/**
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* @brief Set bypass mode for an HRPWM channel
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param u8Channel The HRPWM channel number to control
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* @param bBypass True to enable bypass mode, False to disable bypass mode
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*/
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LOCAL_INLINE void HRPWM_HWA_SetChannelBypass(HRPWM_Type * const pHrpwm, uint8_t u8Channel, bool bBypass)
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{
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pHrpwm->BYPASS_CTRL = (pHrpwm->BYPASS_CTRL & (~(1U << u8Channel))) | ((uint32_t)bBypass << u8Channel);
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}
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/**
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* @brief Set Fault bypass enable for an HRPWM channel
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param u8Channel The HRPWM channel number to control
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* @param bBypass True to enable HRPWM fault, False to disable HRPWM fault
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*/
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LOCAL_INLINE void HRPWM_HWA_SetChannelFaultEnable(HRPWM_Type * const pHrpwm, uint8_t u8Channel, bool bBypass)
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{
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pHrpwm->FAULT_BYPASS_CTRL = (pHrpwm->FAULT_BYPASS_CTRL & (~(1U << u8Channel))) | ((uint32_t)bBypass << u8Channel);
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}
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/**
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* @brief Enable or disable the internal LDO
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param bEnable True to enable the internal LDO, False to disable the internal LDO
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*/
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LOCAL_INLINE void HRPWM_HWA_SetInternalLDOEnable(HRPWM_Type * const pHrpwm, bool bEnable)
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{
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pHrpwm->ANA_CTRL = (pHrpwm->ANA_CTRL & (~HRPWM_ANA_CTRL_PH_LDOEN_MASK)) | HRPWM_ANA_CTRL_PH_LDOEN(bEnable);
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}
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/**
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* @brief Set bypass mode for the internal LDO
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param bEnable True to enable LDO bypass mode, False to disable LDO bypass mode
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*/
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LOCAL_INLINE void HRPWM_HWA_SetInternalLDOBypass(HRPWM_Type * const pHrpwm, bool bEnable)
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{
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pHrpwm->ANA_CTRL = (pHrpwm->ANA_CTRL & (~HRPWM_ANA_CTRL_PH_LDOBYPASSEN_MASK)) | HRPWM_ANA_CTRL_PH_LDOBYPASSEN(bEnable);
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}
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/**
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* @brief Enable or disable phase generation
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param bEnable True to enable phase generation, False to disable phase generation
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*/
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LOCAL_INLINE void HRPWM_HWA_SetPhaseGeneration(HRPWM_Type * const pHrpwm, bool bEnable)
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{
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pHrpwm->ANA_CTRL = (pHrpwm->ANA_CTRL & (~HRPWM_ANA_CTRL_PH_EN_MASK)) | HRPWM_ANA_CTRL_PH_EN(bEnable);
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}
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/**
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* @brief Set the value of the ANA_CTRL register
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param u32Value The value to set for the ANA_CTRL register
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*/
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LOCAL_INLINE void HRPWM_HWA_SetANACtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value)
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{
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pHrpwm->ANA_CTRL = u32Value;
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}
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/**
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* @brief Get the value of the ANA_CTRL register
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @return uint32_t The value of the ANA_CTRL register
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*/
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LOCAL_INLINE uint32_t HRPWM_HWA_GetANACtrl(HRPWM_Type * const pHrpwm)
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{
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return pHrpwm->ANA_CTRL;
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}
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/**
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* @brief Check if the analog power is OK
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @return true If the analog power is OK, otherwise false
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*/
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LOCAL_INLINE bool HRPWM_HWA_GetAnolagPowerOK(HRPWM_Type * const pHrpwm)
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{
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return (bool)((pHrpwm->ANA_CTRL & HRPWM_ANA_CTRL_ANA_POWER_OK_MASK) >> HRPWM_ANA_CTRL_ANA_POWER_OK_SHIFT);
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}
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/**
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* @brief Check if phase generation is locked
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @return true If phase generation is locked, otherwise false
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*/
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LOCAL_INLINE bool HRPWM_HWA_GetPhaseGenLock(HRPWM_Type * const pHrpwm)
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{
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return (bool)pHrpwm->ANA_CTRL & HRPWM_ANA_CTRL_PH_LOCK_MASK;
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}
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/**
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* @brief Unlock HRPWM registers for write operations
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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*/
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LOCAL_INLINE void HRPWM_HWA_UnlockRegisterWrite(HRPWM_Type * const pHrpwm)
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{
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pHrpwm->LOCK_CTRL = HRPWM_UNLOCK_WRITE_CODE;
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}
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/**
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* @brief Lock HRPWM registers to prevent write operations
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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*/
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LOCAL_INLINE void HRPWM_HWA_LockRegisterWrite(HRPWM_Type * const pHrpwm)
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{
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pHrpwm->LOCK_CTRL = HRPWM_LOCK_WRITE_CODE;
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}
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/**
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* @brief Set fault software release mode
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param u8Channel The HRPWM channel number to configure
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* @param bSwRelease True: fault release by writing FAULT_STATUS, False: fault release without software
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*/
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LOCAL_INLINE void HRPWM_HWA_SetSWFaultRelease(HRPWM_Type * const pHrpwm, uint8_t u8Channel, bool bSwRelease)
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{
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pHrpwm->FAULT_SW_CTRL_EN = (pHrpwm->FAULT_SW_CTRL_EN & (~(1U << u8Channel))) | ((uint32_t)bSwRelease << u8Channel);
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}
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/**
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* @brief Get fault status
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @return uint8_t The current fault status
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*/
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LOCAL_INLINE uint8_t HRPWM_HWA_GetFaultStatus(HRPWM_Type * const pHrpwm)
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{
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return (uint8_t)(pHrpwm->FAULT_STATUS & HRPWM_FAULT_STATUS_MASK);
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}
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/**
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* @brief Clear fault status
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param u8Mask The fault status mask to clear
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*/
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LOCAL_INLINE void HRPWM_HWA_ClearFaultStatus(HRPWM_Type * const pHrpwm, uint8_t u8Mask)
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{
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pHrpwm->FAULT_STATUS = (uint32_t)u8Mask;
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}
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/**
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* @brief Set the value of the EN_CTRL register
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param u32Value The value to set for the EN_CTRL register
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*/
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LOCAL_INLINE void HRPWM_HWA_SetENCtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value)
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{
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pHrpwm->EN_CTRL = u32Value;
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}
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/**
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* @brief Set the value of the BYPASS_CTRL register
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param u32Value The value to set for the BYPASS_CTRL register
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*/
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LOCAL_INLINE void HRPWM_HWA_SetBypassCtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value)
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{
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pHrpwm->BYPASS_CTRL = u32Value;
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}
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/**
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* @brief Set the value of the FAULT_BYPASS_CTRL register
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param u32Value The value to set for the FAULT_BYPASS_CTRL register
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*/
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LOCAL_INLINE void HRPWM_HWA_SetFltBypassCtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value)
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{
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pHrpwm->FAULT_BYPASS_CTRL = u32Value;
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}
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/**
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* @brief Set the value of the FAULT_SW_CTRL_EN register
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*
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* @param pHrpwm Base address pointer of the HRPWM peripheral
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* @param u32Value The value to set for the FAULT_SW_CTRL_EN register
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*/
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LOCAL_INLINE void HRPWM_HWA_SetFltSWCtrl(HRPWM_Type * const pHrpwm, uint32_t u32Value)
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{
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pHrpwm->FAULT_SW_CTRL_EN = u32Value;
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}
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/** @}*/
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#endif /* defined(HRPWM_INSTANCE_COUNT) && (HRPWM_INSTANCE_COUNT > 0U) */
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#endif /* _HWA_HRPWM_H_ */
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