/** * @file HwA_port.h * @author Flagchip * @brief FC7xxx PORT hardware access layer * @version 0.1.0 * @date 2023-02-13 * * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. * * @details */ /* ******************************************************************************** * Revision History: * * Version Date Initials CR# Descriptions * --------- ---------- ------------ ---------- --------------- * 0.1.0 2022-11-18 Flagchip071 N/A First version for FC7xxx ******************************************************************************** */ #ifndef _HWA_PORT_H_ #define _HWA_PORT_H_ #include "device_header.h" /********* Local typedef ************/ /** @brief Port Mode Type */ typedef uint32_t Port_PinModeType; /** @brief PORTA 0 Mode enumeration */ typedef enum { PORTA_0_ADC1_SE30 = 0U, PORTA_0_GPIO = 1U, PORTA_0_FTU2_CH1 = 2U, PORTA_0_AONTIMER0_CLK1 = 3U, PORTA_0_SENT0_RXD3 = 4U, PORTA_0_TPU_CH1 = 5U, PORTA_0_FCUART0_CTS = 6U, PORTA_0_TRGSEL_OUT3 = 7U, } PORT_A0MuxType; /** @brief PORTA 1 Mode enumeration */ typedef enum { PORTA_1_ADC1_SE29 = 0U, PORTA_1_GPIO = 1U, PORTA_1_FTU1_CH1 = 2U, PORTA_1_AONTIMER0_CLK2 = 3U, PORTA_1_SENT0_RXD2 = 4U, PORTA_1_FTU1_QD_PHB = 5U, PORTA_1_FCUART0_RTS = 6U, PORTA_1_TRGSEL_OUT0 = 7U, } PORT_A1MuxType; /** @brief PORTA 10 Mode enumeration */ typedef enum { PORTA_10_GPIO = 1U, PORTA_10_FTU1_CH4 = 2U, PORTA_10_AONTIMER0_CLK0 = 3U, PORTA_10_TPU_CH30 = 4U, PORTA_10_FCIIC0_SCL = 5U, PORTA_10_JTAG_TDO = 7U, } PORT_A10MuxType; /** @brief PORTA 11 Mode enumeration */ typedef enum { PORTA_11_GPIO = 1U, PORTA_11_FTU1_CH5 = 2U, PORTA_11_LP_WAKEUP2 = 3U, PORTA_11_TPU_CH29 = 4U, PORTA_11_FCSPI0_PCS0 = 5U, PORTA_11_NMI_b = 7U, } PORT_A11MuxType; /** @brief PORTA 12 Mode enumeration */ typedef enum { PORTA_12_GPIO = 1U, PORTA_12_FTU1_CH6 = 2U, PORTA_12_FLEXCAN1_RX = 3U, PORTA_12_FCSPI0_SOUT = 5U, PORTA_12_FTU1_QD_PHB = 6U, PORTA_12_TPU_CH9 = 7U, } PORT_A12MuxType; /** @brief PORTA 13 Mode enumeration */ typedef enum { PORTA_13_ADC0_SE20 = 0U, PORTA_13_GPIO = 1U, PORTA_13_FTU1_CH7 = 2U, PORTA_13_FLEXCAN1_TX = 3U, PORTA_13_CMP1_OUT = 4U, PORTA_13_FCUART0_RX = 5U, PORTA_13_FTU1_QD_PHA = 6U, PORTA_13_TPU_CH8 = 7U, } PORT_A13MuxType; /** @brief PORTA 14 Mode enumeration */ typedef enum { PORTA_14_ADC0_SE21 = 0U, PORTA_14_GPIO = 1U, PORTA_14_FTU_FLT17 = 2U, PORTA_14_AONTIMER0_CLK1 = 3U, PORTA_14_FCUART0_TX = 5U, PORTA_14_TPU_CH7 = 6U, } PORT_A14MuxType; /** @brief PORTA 15 Mode enumeration */ typedef enum { PORTA_15_ADC0_SE26 = 0U, PORTA_15_GPIO = 1U, PORTA_15_FTU1_CH2 = 2U, PORTA_15_TRGSEL_OUT0 = 5U, PORTA_15_FLEXCAN3_RX = 6U, PORTA_15_TPU_CH5 = 7U, } PORT_A15MuxType; /** @brief PORTA 16 Mode enumeration */ typedef enum { PORTA_16_ADC0_SE28 = 0U, PORTA_16_GPIO = 1U, PORTA_16_FTU1_CH3 = 2U, PORTA_16_FCSPI1_PCS2 = 3U, PORTA_16_FTU1_QD_PHA = 4U, PORTA_16_SENT0_RXD1 = 5U, PORTA_16_FLEXCAN3_TX = 6U, PORTA_16_TPU_CH4 = 7U, } PORT_A16MuxType; /** @brief PORTA 17 Mode enumeration */ typedef enum { PORTA_17_GPIO = 1U, PORTA_17_FTU0_CH6 = 2U, PORTA_17_FTU7_CH0 = 3U, PORTA_17_FLEXCAN2_TX = 4U, PORTA_17_FCSPI5_PCS0 = 5U, PORTA_17_FTU_FLT15 = 6U, PORTA_17_FCUART3_RX = 7U, } PORT_A17MuxType; /** @brief PORTA 18 Mode enumeration */ typedef enum { PORTA_18_GPIO = 1U, PORTA_18_FTU4_CH0 = 2U, PORTA_18_FCUART1_TX = 3U, PORTA_18_TPU_CH0 = 4U, PORTA_18_TPU_TCRCLK = 5U, PORTA_18_FCSPI4_PCS1 = 6U, } PORT_A18MuxType; /** @brief PORTA 19 Mode enumeration */ typedef enum { PORTA_19_GPIO = 1U, PORTA_19_FTU4_CH1 = 2U, PORTA_19_FCUART1_RX = 3U, PORTA_19_TPU_CH1 = 4U, PORTA_19_FCSPI4_PCS2 = 6U, } PORT_A19MuxType; /** @brief PORTA 2 Mode enumeration */ typedef enum { PORTA_2_GPIO = 1U, PORTA_2_FTU3_CH0 = 2U, PORTA_2_FCIIC0_SDA = 3U, PORTA_2_TPU_CH1 = 4U, PORTA_2_FCSPI5_SOUT = 5U, PORTA_2_FCUART0_RX = 6U, } PORT_A2MuxType; /** @brief PORTA 20 Mode enumeration */ typedef enum { PORTA_20_GPIO = 1U, PORTA_20_FTU4_CH2 = 2U, PORTA_20_FCUART3_RTS = 3U, PORTA_20_TPU_CH2 = 4U, PORTA_20_FLEXCAN2_RX = 5U, PORTA_20_FCSPI4_PCS3 = 6U, } PORT_A20MuxType; /** @brief PORTA 21 Mode enumeration */ typedef enum { PORTA_21_GPIO = 1U, PORTA_21_FTU4_CH3 = 2U, PORTA_21_FCUART3_CTS = 3U, PORTA_21_TPU_CH3 = 4U, PORTA_21_FLEXCAN2_TX = 5U, } PORT_A21MuxType; /** @brief PORTA 23 Mode enumeration */ typedef enum { PORTA_23_GPIO = 1U, PORTA_23_FTU4_CH6 = 2U, PORTA_23_FCUART3_RX = 3U, PORTA_23_TPU_CH25 = 4U, PORTA_23_FCSPI4_SCK = 6U, } PORT_A23MuxType; /** @brief PORTA 24 Mode enumeration */ typedef enum { PORTA_24_GPIO = 1U, PORTA_24_FTU4_CH7 = 2U, PORTA_24_FCUART3_TX = 3U, PORTA_24_TPU_CH4 = 4U, PORTA_24_FCSPI4_SIN = 6U, } PORT_A24MuxType; /** @brief PORTA 25 Mode enumeration */ typedef enum { PORTA_25_ADC0_SE0 = 0U, PORTA_25_GPIO = 1U, PORTA_25_FTU5_CH0 = 2U, PORTA_25_FCSPI2_PCS2 = 3U, PORTA_25_FTU2_CH5 = 4U, PORTA_25_FCUART2_RX = 5U, PORTA_25_TPU_TCRCLK = 6U, PORTA_25_TPU_CH0 = 7U, } PORT_A25MuxType; /** @brief PORTA 26 Mode enumeration */ typedef enum { PORTA_26_ADC0_SE2 = 0U, PORTA_26_GPIO = 1U, PORTA_26_FTU5_CH1 = 2U, PORTA_26_FTU2_CH4 = 4U, PORTA_26_FCSPI1_PCS0 = 5U, PORTA_26_TPU_CH1 = 7U, } PORT_A26MuxType; /** @brief PORTA 27 Mode enumeration */ typedef enum { PORTA_27_ADC0_SE6 = 0U, PORTA_27_GPIO = 1U, PORTA_27_FTU5_CH2 = 2U, PORTA_27_FLEXCAN0_TX = 3U, PORTA_27_FCUART0_TX = 4U, PORTA_27_FCSPI1_SOUT = 5U, PORTA_27_TPU_CH2 = 7U, } PORT_A27MuxType; /** @brief PORTA 28 Mode enumeration */ typedef enum { PORTA_28_ADC0_SE7 = 0U, PORTA_28_GPIO = 1U, PORTA_28_FTU5_CH3 = 2U, PORTA_28_FLEXCAN0_RX = 3U, PORTA_28_FCUART0_RX = 4U, PORTA_28_FCSPI1_SCK = 5U, PORTA_28_TPU_CH4 = 7U, } PORT_A28MuxType; /** @brief PORTA 29 Mode enumeration */ typedef enum { PORTA_29_ADC0_SE9 = 0U, PORTA_29_GPIO = 1U, PORTA_29_FTU5_CH4 = 2U, PORTA_29_FCUART2_TX = 3U, PORTA_29_FCSPI1_SIN = 5U, PORTA_29_TPU_CH6 = 7U, } PORT_A29MuxType; /** @brief PORTA 3 Mode enumeration */ typedef enum { PORTA_3_GPIO = 1U, PORTA_3_FTU3_CH1 = 2U, PORTA_3_FCIIC0_SCL = 3U, PORTA_3_TPU_CH2 = 4U, PORTA_3_FCSPI5_SCK = 5U, PORTA_3_FCUART0_TX = 6U, } PORT_A3MuxType; /** @brief PORTA 30 Mode enumeration */ typedef enum { PORTA_30_GPIO = 1U, PORTA_30_FTU5_CH5 = 2U, PORTA_30_FCUART2_RX = 3U, PORTA_30_TPU_CH7 = 7U, } PORT_A30MuxType; /** @brief PORTA 31 Mode enumeration */ typedef enum { PORTA_31_ADC0_SE13_CMP0_IN3 = 0U, PORTA_31_GPIO = 1U, PORTA_31_FTU5_CH6 = 2U, PORTA_31_FLEXCAN3_TX = 3U, PORTA_31_TPU_CH8 = 6U, PORTA_31_FCSPI0_PCS1 = 7U, } PORT_A31MuxType; /** @brief PORTA 4 Mode enumeration */ typedef enum { PORTA_4_GPIO = 1U, PORTA_4_FTU1_CH0 = 2U, PORTA_4_TRGSEL_OUT7 = 3U, PORTA_4_CMP0_OUT = 4U, PORTA_4_LP_WAKEUP4 = 5U, PORTA_4_JTAG_TMS_SWD_DIO = 7U, } PORT_A4MuxType; /** @brief PORTA 6 Mode enumeration */ typedef enum { PORTA_6_ADC1_SE9 = 0U, PORTA_6_GPIO = 1U, PORTA_6_FTU_FLT13 = 2U, PORTA_6_FCSPI1_PCS1 = 3U, PORTA_6_FTU5_CH5 = 4U, PORTA_6_TRGSEL_OUT4 = 5U, PORTA_6_FCUART1_CTS = 6U, PORTA_6_FTU4_CH7 = 7U, } PORT_A6MuxType; /** @brief PORTA 7 Mode enumeration */ typedef enum { PORTA_7_GPIO = 1U, PORTA_7_FTU_FLT12 = 2U, PORTA_7_FTU3_CH1 = 3U, PORTA_7_FTU5_CH3 = 4U, PORTA_7_FCSPI1_SCK = 5U, PORTA_7_FCUART1_RTS = 6U, PORTA_7_MSC0_EN0 = 7U, } PORT_A7MuxType; /** @brief PORTA 8 Mode enumeration */ typedef enum { PORTA_8_ADC1_SE3 = 0U, PORTA_8_GPIO = 1U, PORTA_8_FCUART2_RX = 2U, PORTA_8_FTU1_CH0 = 3U, PORTA_8_CMP0_OUT = 4U, PORTA_8_FTU_FLT21 = 5U, PORTA_8_FCUART0_RX = 6U, PORTA_8_TPU_CH13 = 7U, } PORT_A8MuxType; /** @brief PORTA 9 Mode enumeration */ typedef enum { PORTA_9_ADC1_SE7 = 0U, PORTA_9_GPIO = 1U, PORTA_9_FCUART2_TX = 2U, PORTA_9_FTU4_CH4 = 3U, PORTA_9_FTU_FLT20 = 5U, PORTA_9_FCUART0_TX = 6U, PORTA_9_TPU_CH12 = 7U, } PORT_A9MuxType; /** @brief PORTB 0 Mode enumeration */ typedef enum { PORTB_0_ADC1_SE10 = 0U, PORTB_0_GPIO = 1U, PORTB_0_FCUART0_RX = 2U, PORTB_0_FCSPI0_PCS0 = 3U, PORTB_0_FTU1_CH5 = 4U, PORTB_0_FLEXCAN0_RX = 5U, PORTB_0_FTU4_CH6 = 6U, PORTB_0_MSC0_SDI1 = 7U, } PORT_B0MuxType; /** @brief PORTB 1 Mode enumeration */ typedef enum { PORTB_1_ADC1_SE11 = 0U, PORTB_1_GPIO = 1U, PORTB_1_FCUART0_TX = 2U, PORTB_1_FCSPI0_SOUT = 3U, PORTB_1_FTU_TCK0 = 4U, PORTB_1_FLEXCAN0_TX = 5U, PORTB_1_FTU4_CH5 = 6U, PORTB_1_MSC0_EN1 = 7U, } PORT_B1MuxType; /** @brief PORTB 10 Mode enumeration */ typedef enum { PORTB_10_GPIO = 1U, PORTB_10_FTU3_CH2 = 2U, PORTB_10_FLEXCAN0_TX = 3U, PORTB_10_SENT0_RXD0 = 4U, PORTB_10_TRGSEL_OUT2 = 5U, PORTB_10_TPU_CH0 = 6U, PORTB_10_TPU_TCRCLK = 7U, } PORT_B10MuxType; /** @brief PORTB 11 Mode enumeration */ typedef enum { PORTB_11_V15_BASE_DRIVER = 0U, PORTB_11_GPIO = 1U, PORTB_11_FTU6_CH0 = 2U, PORTB_11_FCUART2_TX = 3U, PORTB_11_FLEXCAN0_TX = 4U, } PORT_B11MuxType; /** @brief PORTB 12 Mode enumeration */ typedef enum { PORTB_12_GPIO = 1U, PORTB_12_FTU0_CH0 = 2U, PORTB_12_TPU_CH26 = 5U, PORTB_12_FCSMU_PIN0 = 7U, } PORT_B12MuxType; /** @brief PORTB 13 Mode enumeration */ typedef enum { PORTB_13_GPIO = 1U, PORTB_13_FTU0_CH1 = 2U, PORTB_13_FCUART6_CTS = 4U, PORTB_13_TPU_CH25 = 5U, PORTB_13_FCSMU_PIN1 = 7U, } PORT_B13MuxType; /** @brief PORTB 14 Mode enumeration */ typedef enum { PORTB_14_ADC1_SE18 = 0U, PORTB_14_GPIO = 1U, PORTB_14_FTU0_CH2 = 2U, PORTB_14_FCSPI1_SCK = 3U, PORTB_14_TPU_CH5 = 4U, PORTB_14_FTU5_CH4 = 6U, PORTB_14_FLEXCAN2_RX = 7U, } PORT_B14MuxType; /** @brief PORTB 15 Mode enumeration */ typedef enum { PORTB_15_ADC1_SE17 = 0U, PORTB_15_GPIO = 1U, PORTB_15_FTU0_CH3 = 2U, PORTB_15_FCSPI1_SIN = 3U, PORTB_15_TPU_CH6 = 4U, PORTB_15_FTU5_CH5 = 6U, PORTB_15_FLEXCAN2_TX = 7U, } PORT_B15MuxType; /** @brief PORTB 16 Mode enumeration */ typedef enum { PORTB_16_ADC1_SE16 = 0U, PORTB_16_GPIO = 1U, PORTB_16_FTU0_CH4 = 2U, PORTB_16_FCSPI1_SOUT = 3U, PORTB_16_TPU_CH7 = 4U, PORTB_16_FTU5_CH6 = 6U, } PORT_B16MuxType; /** @brief PORTB 17 Mode enumeration */ typedef enum { PORTB_17_GPIO = 1U, PORTB_17_FTU0_CH5 = 2U, PORTB_17_FCSPI1_PCS3 = 3U, PORTB_17_FLEXCAN2_RX = 4U, PORTB_17_TRGSEL_OUT3 = 5U, PORTB_17_FTU5_CH7 = 6U, PORTB_17_FCUART3_TX = 7U, } PORT_B17MuxType; /** @brief PORTB 18 Mode enumeration */ typedef enum { PORTB_18_GPIO = 1U, PORTB_18_FTU5_CH7 = 2U, PORTB_18_FLEXCAN3_RX = 3U, PORTB_18_FCSPI4_PCS2 = 4U, PORTB_18_FCSPI1_PCS1 = 5U, PORTB_18_TPU_CH9 = 6U, } PORT_B18MuxType; /** @brief PORTB 19 Mode enumeration */ typedef enum { PORTB_19_CMP0_IN4 = 0U, PORTB_19_GPIO = 1U, PORTB_19_FTU6_CH2 = 2U, PORTB_19_FCUART4_RX = 3U, PORTB_19_FLEXCAN3_TX = 4U, PORTB_19_TPU_CH5 = 6U, } PORT_B19MuxType; /** @brief PORTB 20 Mode enumeration */ typedef enum { PORTB_20_ADC0_SE14 = 0U, PORTB_20_GPIO = 1U, PORTB_20_FTU2_CH5 = 2U, PORTB_20_FCUART1_TX = 3U, PORTB_20_FTU6_CH2 = 4U, PORTB_20_TPU_CH10 = 6U, PORTB_20_SCG_CLKOUT = 7U, } PORT_B20MuxType; /** @brief PORTB 21 Mode enumeration */ typedef enum { PORTB_21_ADC0_SE15 = 0U, PORTB_21_GPIO = 1U, PORTB_21_FTU2_CH4 = 2U, PORTB_21_FCUART1_RX = 3U, PORTB_21_FTU6_CH3 = 4U, PORTB_21_TPU_CH11 = 6U, } PORT_B21MuxType; /** @brief PORTB 22 Mode enumeration */ typedef enum { PORTB_22_GPIO = 1U, PORTB_22_FTU_FLT8 = 2U, PORTB_22_FLEXCAN2_TX = 3U, PORTB_22_TPU_CH12 = 4U, PORTB_22_FTU6_CH6 = 5U, PORTB_22_MSC0_EN0 = 6U, PORTB_22_FCSPI3_PCS1 = 7U, } PORT_B22MuxType; /** @brief PORTB 23 Mode enumeration */ typedef enum { PORTB_23_CMP1_IN6 = 0U, PORTB_23_GPIO = 1U, PORTB_23_FTU_FLT9 = 2U, PORTB_23_FCUART1_RX = 3U, PORTB_23_FTU4_CH7 = 4U, PORTB_23_FTU7_CH7 = 5U, PORTB_23_TPU_CH13 = 6U, PORTB_23_MSC0_FCLP = 7U, } PORT_B23MuxType; /** @brief PORTB 24 Mode enumeration */ typedef enum { PORTB_24_CMP0_IN5 = 0U, PORTB_24_GPIO = 1U, PORTB_24_FTU6_CH3 = 2U, PORTB_24_FCUART4_TX = 3U, PORTB_24_FLEXCAN3_RX = 4U, PORTB_24_TPU_CH6 = 6U, } PORT_B24MuxType; /** @brief PORTB 25 Mode enumeration */ typedef enum { PORTB_25_GPIO = 1U, PORTB_25_FTU1_CH2 = 2U, PORTB_25_FTU1_QD_PHB = 3U, PORTB_25_FCSPI2_PCS0 = 4U, PORTB_25_FTU6_CH7 = 5U, PORTB_25_FCUART3_TX = 6U, } PORT_B25MuxType; /** @brief PORTB 26 Mode enumeration */ typedef enum { PORTB_26_CMP0_IN6 = 0U, PORTB_26_GPIO = 1U, PORTB_26_FTU6_CH4 = 2U, PORTB_26_FCSPI3_SCK = 3U, PORTB_26_FCUART3_TX = 4U, PORTB_26_TPU_CH7 = 6U, } PORT_B26MuxType; /** @brief PORTB 27 Mode enumeration */ typedef enum { PORTB_27_GPIO = 1U, PORTB_27_FTU7_CH5 = 2U, PORTB_27_FTU2_CH2 = 3U, PORTB_27_FCSPI2_SOUT = 4U, PORTB_27_FCUART5_RTS = 5U, PORTB_27_TPU_CH14 = 6U, } PORT_B27MuxType; /** @brief PORTB 28 Mode enumeration */ typedef enum { PORTB_28_GPIO = 1U, PORTB_28_FTU7_CH4 = 2U, PORTB_28_FTU2_CH1 = 3U, PORTB_28_FCSPI2_SIN = 4U, PORTB_28_FCUART5_CTS = 5U, PORTB_28_TPU_CH15 = 6U, } PORT_B28MuxType; /** @brief PORTB 29 Mode enumeration */ typedef enum { PORTB_29_GPIO = 1U, PORTB_29_FTU1_CH0 = 2U, PORTB_29_FCUART5_TX = 3U, PORTB_29_FCSPI2_SCK = 4U, PORTB_29_FTU1_QD_PHB = 5U, PORTB_29_FCUART7_RTS = 6U, PORTB_29_TPU_CH16 = 7U, } PORT_B29MuxType; /** @brief PORTB 3 Mode enumeration */ typedef enum { PORTB_3_GPIO = 1U, PORTB_3_FTU1_CH1 = 2U, PORTB_3_FCSPI0_SIN = 3U, PORTB_3_FTU1_QD_PHA = 4U, PORTB_3_FTU7_CH3 = 5U, PORTB_3_TPU_CH10 = 6U, PORTB_3_FCUART5_RX = 7U, } PORT_B3MuxType; /** @brief PORTB 30 Mode enumeration */ typedef enum { PORTB_30_CMP0_IN7 = 0U, PORTB_30_GPIO = 1U, PORTB_30_FTU6_CH5 = 2U, PORTB_30_FCSPI3_SIN = 3U, PORTB_30_FCUART3_RX = 4U, PORTB_30_TPU_CH8 = 6U, } PORT_B30MuxType; /** @brief PORTB 31 Mode enumeration */ typedef enum { PORTB_31_CMP1_IN0 = 0U, PORTB_31_GPIO = 1U, PORTB_31_FTU7_CH7 = 2U, PORTB_31_FCSPI3_SOUT = 3U, PORTB_31_FCUART5_TX = 4U, PORTB_31_TPU_CH9 = 5U, } PORT_B31MuxType; /** @brief PORTB 4 Mode enumeration */ typedef enum { PORTB_4_GPIO = 1U, PORTB_4_FTU0_CH4 = 2U, PORTB_4_FCIIC1_SDA = 3U, PORTB_4_FCSPI4_SOUT = 4U, PORTB_4_FTU7_CH6 = 5U, PORTB_4_ETM_TRACE_D6 = 6U, PORTB_4_TRGSEL_OUT4 = 7U, } PORT_B4MuxType; /** @brief PORTB 5 Mode enumeration */ typedef enum { PORTB_5_GPIO = 1U, PORTB_5_FTU0_CH5 = 2U, PORTB_5_FCIIC1_SCL = 3U, PORTB_5_FCSPI4_PCS0 = 4U, PORTB_5_SCG_CLKOUT = 5U, PORTB_5_ETM_TRACE_D5 = 6U, PORTB_5_TRGSEL_OUT5 = 7U, } PORT_B5MuxType; /** @brief PORTB 6 Mode enumeration */ typedef enum { PORTB_6_XTAL = 0U, PORTB_6_GPIO = 1U, PORTB_6_FCIIC0_SDA = 2U, } PORT_B6MuxType; /** @brief PORTB 7 Mode enumeration */ typedef enum { PORTB_7_EXTAL = 0U, PORTB_7_GPIO = 1U, PORTB_7_FCIIC0_SCL = 2U, } PORT_B7MuxType; /** @brief PORTB 8 Mode enumeration */ typedef enum { PORTB_8_ADC1_SE28 = 0U, PORTB_8_GPIO = 1U, PORTB_8_FTU3_CH0 = 2U, PORTB_8_FLEXCAN0_RX = 3U, PORTB_8_SENT0_RXD1 = 4U, PORTB_8_TPU_CH0 = 5U, PORTB_8_FCUART1_CTS = 6U, } PORT_B8MuxType; /** @brief PORTB 9 Mode enumeration */ typedef enum { PORTB_9_ADC1_SE25 = 0U, PORTB_9_GPIO = 1U, PORTB_9_FTU3_CH1 = 2U, PORTB_9_FTU1_CH6 = 3U, PORTB_9_TRGSEL_OUT1 = 5U, PORTB_9_TPU_CH29 = 6U, PORTB_9_FCSPI5_PCS0 = 7U, } PORT_B9MuxType; /** @brief PORTC 0 Mode enumeration */ typedef enum { PORTC_0_GPIO = 1U, PORTC_0_FTU0_CH0 = 2U, PORTC_0_FLEXCAN2_RX = 3U, PORTC_0_TPU_CH15 = 4U, PORTC_0_FlexCore_TCLK = 5U, PORTC_0_FTU1_CH6 = 6U, PORTC_0_FCSPI3_PCS2 = 7U, } PORT_C0MuxType; /** @brief PORTC 1 Mode enumeration */ typedef enum { PORTC_1_GPIO = 1U, PORTC_1_FTU0_CH1 = 2U, PORTC_1_TPU_CH16 = 3U, PORTC_1_FCSPI2_SOUT = 4U, PORTC_1_FlexCore_TDI = 5U, PORTC_1_FTU1_CH7 = 6U, PORTC_1_FCUART3_TX = 7U, } PORT_C1MuxType; /** @brief PORTC 10 Mode enumeration */ typedef enum { PORTC_10_ADC1_SE12 = 0U, PORTC_10_GPIO = 1U, PORTC_10_FTU3_CH4 = 2U, PORTC_10_FTU0_CH5 = 3U, PORTC_10_FCUART6_RX = 4U, PORTC_10_FTU7_CH1 = 6U, PORTC_10_TPU_CH8 = 7U, } PORT_C10MuxType; /** @brief PORTC 11 Mode enumeration */ typedef enum { PORTC_11_ADC1_SE13 = 0U, PORTC_11_GPIO = 1U, PORTC_11_FTU3_CH5 = 2U, PORTC_11_FTU4_CH2 = 3U, PORTC_11_FCUART6_TX = 4U, PORTC_11_FCSPI1_PCS0 = 5U, PORTC_11_FTU7_CH2 = 6U, PORTC_11_TPU_CH9 = 7U, } PORT_C11MuxType; /** @brief PORTC 12 Mode enumeration */ typedef enum { PORTC_12_ADC1_SE14 = 0U, PORTC_12_GPIO = 1U, PORTC_12_FTU3_CH6 = 2U, PORTC_12_FTU2_CH6 = 3U, PORTC_12_FCUART2_CTS = 4U, PORTC_12_TRGSEL_OUT5 = 5U, PORTC_12_FCUART7_RX = 6U, PORTC_12_MSC0_SOP = 7U, } PORT_C12MuxType; /** @brief PORTC 13 Mode enumeration */ typedef enum { PORTC_13_ADC1_SE15 = 0U, PORTC_13_GPIO = 1U, PORTC_13_FTU3_CH7 = 2U, PORTC_13_FTU2_CH7 = 3U, PORTC_13_FCUART2_RTS = 4U, PORTC_13_TRGSEL_OUT6 = 5U, PORTC_13_FCUART7_TX = 6U, PORTC_13_MSC0_FCLP = 7U, } PORT_C13MuxType; /** @brief PORTC 14 Mode enumeration */ typedef enum { PORTC_14_CMP1_IN7 = 0U, PORTC_14_GPIO = 1U, PORTC_14_FTU1_CH2 = 2U, PORTC_14_TPU_CH11 = 3U, PORTC_14_FCSPI2_PCS0 = 4U, PORTC_14_FTU1_QD_PHA = 5U, PORTC_14_TRGSEL_OUT6 = 6U, } PORT_C14MuxType; /** @brief PORTC 15 Mode enumeration */ typedef enum { PORTC_15_CMP1_IN5 = 0U, PORTC_15_GPIO = 1U, PORTC_15_FTU1_CH3 = 2U, PORTC_15_TPU_CH12 = 3U, PORTC_15_FCSPI2_SCK = 4U, PORTC_15_FTU6_CH1 = 5U, PORTC_15_TRGSEL_OUT7 = 6U, PORTC_15_FCUART5_TX = 7U, } PORT_C15MuxType; /** @brief PORTC 16 Mode enumeration */ typedef enum { PORTC_16_CMP1_IN4 = 0U, PORTC_16_GPIO = 1U, PORTC_16_FTU_FLT7 = 2U, PORTC_16_FTU4_CH0 = 3U, PORTC_16_FCSPI2_SIN = 4U, PORTC_16_FTU7_CH4 = 5U, PORTC_16_TPU_CH13 = 6U, PORTC_16_FCUART5_RX = 7U, } PORT_C16MuxType; /** @brief PORTC 17 Mode enumeration */ typedef enum { PORTC_17_DEBUGMUX_P1 = 0U, PORTC_17_GPIO = 1U, PORTC_17_FTU_FLT6 = 2U, PORTC_17_FTU4_CH1 = 3U, PORTC_17_FCSPI2_PCS3 = 4U, PORTC_17_FTU6_CH2 = 5U, PORTC_17_TPU_CH14 = 6U, PORTC_17_FCUART4_TX = 7U, } PORT_C17MuxType; /** @brief PORTC 18 Mode enumeration */ typedef enum { PORTC_18_CMP1_IN1 = 0U, PORTC_18_GPIO = 1U, PORTC_18_FTU7_CH6 = 2U, PORTC_18_FCSPI3_PCS0 = 3U, PORTC_18_FCUART5_RX = 4U, PORTC_18_TPU_CH10 = 5U, } PORT_C18MuxType; /** @brief PORTC 19 Mode enumeration */ typedef enum { PORTC_19_GPIO = 1U, PORTC_19_FTU7_CH3 = 2U, PORTC_19_FCSPI2_PCS1 = 4U, PORTC_19_TPU_CH17 = 5U, PORTC_19_FCUART3_RX = 6U, } PORT_C19MuxType; /** @brief PORTC 2 Mode enumeration */ typedef enum { PORTC_2_DEBUGMUX_P2 = 0U, PORTC_2_GPIO = 1U, PORTC_2_FTU0_CH2 = 2U, PORTC_2_FLEXCAN0_RX = 3U, PORTC_2_FCUART0_RX = 4U, PORTC_2_FTU5_CH4 = 5U, PORTC_2_ETM_TRACE_CLKOUT = 6U, PORTC_2_FCSPI0_PCS2 = 7U, } PORT_C2MuxType; /** @brief PORTC 20 Mode enumeration */ typedef enum { PORTC_20_GPIO = 1U, PORTC_20_FTU7_CH2 = 2U, PORTC_20_FCSPI2_SCK = 4U, PORTC_20_FCUART3_RTS = 5U, PORTC_20_TPU_CH12 = 6U, PORTC_20_MSC0_FCLP = 7U, } PORT_C20MuxType; /** @brief PORTC 21 Mode enumeration */ typedef enum { PORTC_21_GPIO = 1U, PORTC_21_FTU7_CH1 = 2U, PORTC_21_FCSPI2_SIN = 4U, PORTC_21_FCUART3_CTS = 5U, PORTC_21_TPU_CH13 = 6U, PORTC_21_MSC0_SOP = 7U, } PORT_C21MuxType; /** @brief PORTC 22 Mode enumeration */ typedef enum { PORTC_22_GPIO = 1U, PORTC_22_FTU6_CH4 = 2U, PORTC_22_FCSPI0_SCK = 3U, PORTC_22_FCUART5_RX = 4U, PORTC_22_FTU7_CH6 = 5U, PORTC_22_TPU_CH18 = 6U, PORTC_22_MSC0_EN2 = 7U, } PORT_C22MuxType; /** @brief PORTC 23 Mode enumeration */ typedef enum { PORTC_23_GPIO = 1U, PORTC_23_FTU7_CH0 = 2U, PORTC_23_FCUART6_TX = 3U, PORTC_23_FCSPI2_SOUT = 4U, PORTC_23_TPU_CH14 = 6U, PORTC_23_MSC0_EN3 = 7U, } PORT_C23MuxType; /** @brief PORTC 24 Mode enumeration */ typedef enum { PORTC_24_GPIO = 1U, PORTC_24_FTU4_CH3 = 2U, PORTC_24_FCUART6_RX = 3U, PORTC_24_FCSPI2_PCS0 = 4U, PORTC_24_TPU_CH15 = 6U, PORTC_24_MSC0_SDI2 = 7U, } PORT_C24MuxType; /** @brief PORTC 25 Mode enumeration */ typedef enum { PORTC_25_ADC1_SE20 = 0U, PORTC_25_GPIO = 1U, PORTC_25_FTU4_CH1 = 2U, PORTC_25_FCUART5_RTS = 3U, PORTC_25_FCUART6_TX = 4U, PORTC_25_FTU0_CH6 = 5U, PORTC_25_SENT0_RXD0 = 6U, PORTC_25_FCSPI4_SCK = 7U, } PORT_C25MuxType; /** @brief PORTC 26 Mode enumeration */ typedef enum { PORTC_26_ADC1_SE21 = 0U, PORTC_26_GPIO = 1U, PORTC_26_FTU4_CH0 = 2U, PORTC_26_FCUART5_CTS = 3U, PORTC_26_FCUART6_RX = 4U, PORTC_26_FTU1_CH4 = 5U, PORTC_26_SENT0_RXD1 = 6U, PORTC_26_FCSPI4_PCS0 = 7U, } PORT_C26MuxType; /** @brief PORTC 27 Mode enumeration */ typedef enum { PORTC_27_GPIO = 1U, PORTC_27_FTU4_CH4 = 2U, PORTC_27_FTU3_CH3 = 3U, PORTC_27_FCSPI4_SOUT = 4U, PORTC_27_TPU_CH19 = 6U, PORTC_27_MSC0_EN0 = 7U, } PORT_C27MuxType; /** @brief PORTC 28 Mode enumeration */ typedef enum { PORTC_28_GPIO = 1U, PORTC_28_FTU4_CH7 = 2U, PORTC_28_FLEXCAN3_TX = 3U, PORTC_28_FTU3_CH2 = 4U, PORTC_28_TPU_CH20 = 6U, PORTC_28_MSC0_SDI0 = 7U, } PORT_C28MuxType; /** @brief PORTC 29 Mode enumeration */ typedef enum { PORTC_29_GPIO = 1U, PORTC_29_FTU5_CH2 = 2U, PORTC_29_FLEXCAN3_RX = 3U, PORTC_29_FCSPI4_SIN = 4U, PORTC_29_TPU_CH21 = 6U, } PORT_C29MuxType; /** @brief PORTC 3 Mode enumeration */ typedef enum { PORTC_3_GPIO = 1U, PORTC_3_FTU0_CH3 = 2U, PORTC_3_FLEXCAN0_TX = 3U, PORTC_3_FCUART0_TX = 4U, PORTC_3_FTU5_CH2 = 5U, PORTC_3_ETM_TRACE_D7 = 6U, PORTC_3_FCSPI0_SOUT = 7U, } PORT_C3MuxType; /** @brief PORTC 30 Mode enumeration */ typedef enum { PORTC_30_GPIO = 1U, PORTC_30_FTU5_CH4 = 2U, PORTC_30_FTU3_CH0 = 3U, PORTC_30_FCSPI4_PCS0 = 4U, PORTC_30_TPU_CH22 = 6U, } PORT_C30MuxType; /** @brief PORTC 31 Mode enumeration */ typedef enum { PORTC_31_GPIO = 1U, PORTC_31_FTU5_CH6 = 2U, PORTC_31_FTU3_CH4 = 3U, PORTC_31_FCIIC1_SDA = 4U, PORTC_31_FLEXCAN1_RX = 5U, PORTC_31_TPU_CH23 = 6U, } PORT_C31MuxType; /** @brief PORTC 4 Mode enumeration */ typedef enum { PORTC_4_GPIO = 1U, PORTC_4_JTAG_TCLK_SWD_CLK = 7U, } PORT_C4MuxType; /** @brief PORTC 5 Mode enumeration */ typedef enum { PORTC_5_GPIO = 1U, PORTC_5_FTU2_CH0 = 2U, PORTC_5_RTC_CLKOUT = 3U, PORTC_5_CMP1_OUT = 4U, PORTC_5_FCIIC0_SDA = 5U, PORTC_5_FTU2_QD_PHB = 6U, PORTC_5_JTAG_TDI = 7U, } PORT_C5MuxType; /** @brief PORTC 6 Mode enumeration */ typedef enum { PORTC_6_ADC0_SE29 = 0U, PORTC_6_GPIO = 1U, PORTC_6_FCUART1_RX = 2U, PORTC_6_FLEXCAN1_RX = 3U, PORTC_6_FTU3_CH2 = 4U, PORTC_6_SENT0_RXD0 = 5U, PORTC_6_TPU_CH3 = 6U, } PORT_C6MuxType; /** @brief PORTC 7 Mode enumeration */ typedef enum { PORTC_7_ADC0_SE30 = 0U, PORTC_7_GPIO = 1U, PORTC_7_FCUART1_TX = 2U, PORTC_7_FLEXCAN1_TX = 3U, PORTC_7_FTU3_CH3 = 4U, PORTC_7_TPU_CH2 = 6U, } PORT_C7MuxType; /** @brief PORTC 8 Mode enumeration */ typedef enum { PORTC_8_GPIO = 1U, PORTC_8_FCUART1_RX = 2U, PORTC_8_FTU_FLT11 = 3U, PORTC_8_FTU5_CH1 = 4U, PORTC_8_FCSPI1_SIN = 5U, PORTC_8_FCUART0_CTS = 6U, PORTC_8_MSC0_EN1 = 7U, } PORT_C8MuxType; /** @brief PORTC 9 Mode enumeration */ typedef enum { PORTC_9_GPIO = 1U, PORTC_9_FCUART1_TX = 2U, PORTC_9_FTU_FLT10 = 3U, PORTC_9_FTU5_CH0 = 4U, PORTC_9_FCSPI1_SOUT = 5U, PORTC_9_FCUART0_RTS = 6U, PORTC_9_FCUART5_TX = 7U, } PORT_C9MuxType; /** @brief PORTD 0 Mode enumeration */ typedef enum { PORTD_0_ADC1_SE1 = 0U, PORTD_0_GPIO = 1U, PORTD_0_FTU0_CH2 = 2U, PORTD_0_FTU2_CH0 = 3U, PORTD_0_FCSPI1_SCK = 4U, PORTD_0_TPU_CH28 = 5U, PORTD_0_ETM_TRACE_D0 = 6U, PORTD_0_TRGSEL_OUT1 = 7U, } PORT_D0MuxType; /** @brief PORTD 1 Mode enumeration */ typedef enum { PORTD_1_ADC1_SE5 = 0U, PORTD_1_GPIO = 1U, PORTD_1_FTU0_CH3 = 2U, PORTD_1_FTU2_CH1 = 3U, PORTD_1_FCSPI1_SIN = 4U, PORTD_1_TPU_CH29 = 5U, PORTD_1_TRGSEL_OUT2 = 7U, } PORT_D1MuxType; /** @brief PORTD 10 Mode enumeration */ typedef enum { PORTD_10_GPIO = 1U, PORTD_10_FTU2_CH0 = 2U, PORTD_10_FTU2_QD_PHB = 3U, PORTD_10_SCG_CLKOUT = 4U, PORTD_10_FlexCore_TMS = 5U, PORTD_10_ETM_TRACE_D3 = 6U, PORTD_10_FCSPI3_PCS3 = 7U, } PORT_D10MuxType; /** @brief PORTD 11 Mode enumeration */ typedef enum { PORTD_11_GPIO = 1U, PORTD_11_FTU2_CH1 = 2U, PORTD_11_FTU2_QD_PHA = 3U, PORTD_11_FCSPI4_PCS1 = 4U, PORTD_11_FCUART2_CTS = 5U, PORTD_11_ETM_TRACE_D2 = 6U, PORTD_11_FCSPI3_PCS0 = 7U, } PORT_D11MuxType; /** @brief PORTD 12 Mode enumeration */ typedef enum { PORTD_12_GPIO = 1U, PORTD_12_FTU2_CH2 = 2U, PORTD_12_FCUART4_RX = 3U, PORTD_12_FTU6_CH7 = 4U, PORTD_12_FCUART2_RTS = 5U, PORTD_12_ETM_TRACE_D1 = 6U, PORTD_12_FCSPI3_SOUT = 7U, } PORT_D12MuxType; /** @brief PORTD 13 Mode enumeration */ typedef enum { PORTD_13_GPIO = 1U, PORTD_13_FTU6_CH3 = 2U, PORTD_13_FCUART1_TX = 3U, PORTD_13_TPU_CH11 = 4U, PORTD_13_FCUART7_CTS = 6U, PORTD_13_MSC0_SOP = 7U, } PORT_D13MuxType; /** @brief PORTD 15 Mode enumeration */ typedef enum { PORTD_15_ADC0_SE11_CMP0_IN1 = 0U, PORTD_15_GPIO = 1U, PORTD_15_FTU0_CH0 = 2U, PORTD_15_FCUART2_RTS = 3U, PORTD_15_TPU_CH18 = 4U, PORTD_15_ETM_TRACE_D3 = 6U, PORTD_15_FCSPI0_SCK = 7U, } PORT_D15MuxType; /** @brief PORTD 16 Mode enumeration */ typedef enum { PORTD_16_ADC0_SE10_CMP0_IN0 = 0U, PORTD_16_GPIO = 1U, PORTD_16_FTU0_CH1 = 2U, PORTD_16_TPU_CH19 = 4U, PORTD_16_ETM_TRACE_D2 = 6U, PORTD_16_FCSPI0_SIN = 7U, } PORT_D16MuxType; /** @brief PORTD 17 Mode enumeration */ typedef enum { PORTD_17_ADC0_SE8 = 0U, PORTD_17_GPIO = 1U, PORTD_17_FTU6_CH1 = 2U, PORTD_17_FCUART7_RX = 3U, PORTD_17_FTU_FLT3 = 4U, PORTD_17_FCSPI4_PCS0 = 6U, PORTD_17_TPU_CH5 = 7U, } PORT_D17MuxType; /** @brief PORTD 18 Mode enumeration */ typedef enum { PORTD_18_GPIO = 1U, PORTD_18_FTU5_CH7 = 2U, PORTD_18_FTU3_CH5 = 3U, PORTD_18_FCSPI4_SCK = 4U, PORTD_18_TPU_CH24 = 6U, } PORT_D18MuxType; /** @brief PORTD 19 Mode enumeration */ typedef enum { PORTD_19_GPIO = 1U, PORTD_19_FTU6_CH0 = 2U, PORTD_19_FCSPI1_PCS2 = 3U, PORTD_19_FCIIC1_SCL = 4U, PORTD_19_FLEXCAN1_TX = 5U, PORTD_19_SENT0_RXD2 = 6U, } PORT_D19MuxType; /** @brief PORTD 2 Mode enumeration */ typedef enum { PORTD_2_GPIO = 1U, PORTD_2_FTU3_CH4 = 2U, PORTD_2_FTU6_CH5 = 3U, PORTD_2_FCUART6_RX = 4U, PORTD_2_FCSPI5_PCS2 = 5U, PORTD_2_FTU1_CH1 = 6U, PORTD_2_ISP_EN_B = 7U, } PORT_D2MuxType; /** @brief PORTD 20 Mode enumeration */ typedef enum { PORTD_20_GPIO = 1U, PORTD_20_FTU6_CH2 = 2U, PORTD_20_FCUART5_RX = 3U, PORTD_20_TPU_CH16 = 4U, PORTD_20_SENT0_RXD2 = 6U, PORTD_20_FCSPI4_SIN = 7U, } PORT_D20MuxType; /** @brief PORTD 21 Mode enumeration */ typedef enum { PORTD_21_ADC1_SE22 = 0U, PORTD_21_GPIO = 1U, PORTD_21_FTU6_CH3 = 2U, PORTD_21_FCUART5_TX = 3U, PORTD_21_TPU_CH17 = 4U, PORTD_21_SENT0_RXD3 = 6U, PORTD_21_FCSPI4_SOUT = 7U, } PORT_D21MuxType; /** @brief PORTD 22 Mode enumeration */ typedef enum { PORTD_22_ADC1_SE19 = 0U, PORTD_22_GPIO = 1U, PORTD_22_FTU6_CH1 = 2U, PORTD_22_FTU0_CH1 = 3U, PORTD_22_TPU_TCRCLK = 4U, PORTD_22_FCSPI5_PCS3 = 5U, PORTD_22_FLEXCAN1_RX = 6U, } PORT_D22MuxType; /** @brief PORTD 23 Mode enumeration */ typedef enum { PORTD_23_GPIO = 1U, PORTD_23_FTU6_CH5 = 2U, PORTD_23_FLEXCAN3_TX = 4U, PORTD_23_TPU_CH27 = 5U, PORTD_23_FTU1_CH0 = 6U, } PORT_D23MuxType; /** @brief PORTD 24 Mode enumeration */ typedef enum { PORTD_24_GPIO = 1U, PORTD_24_FTU3_CH3 = 2U, PORTD_24_TPU_CH28 = 3U, PORTD_24_FCUART6_RTS = 4U, PORTD_24_FCSPI5_PCS1 = 5U, PORTD_24_FLEXCAN1_TX = 6U, } PORT_D24MuxType; /** @brief PORTD 25 Mode enumeration */ typedef enum { PORTD_25_ADC1_SE24 = 0U, PORTD_25_GPIO = 1U, PORTD_25_FTU6_CH6 = 2U, PORTD_25_FTU0_CH0 = 3U, PORTD_25_FCUART4_RTS = 4U, PORTD_25_TPU_CH18 = 6U, PORTD_25_FCSPI5_SCK = 7U, } PORT_D25MuxType; /** @brief PORTD 26 Mode enumeration */ typedef enum { PORTD_26_ADC1_SE26 = 0U, PORTD_26_GPIO = 1U, PORTD_26_FTU6_CH7 = 2U, PORTD_26_FTU3_CH7 = 3U, PORTD_26_FCUART4_CTS = 4U, PORTD_26_SENT0_RXD3 = 5U, PORTD_26_TPU_CH19 = 6U, PORTD_26_FCSPI5_SIN = 7U, } PORT_D26MuxType; /** @brief PORTD 27 Mode enumeration */ typedef enum { PORTD_27_ADC1_SE27 = 0U, PORTD_27_GPIO = 1U, PORTD_27_FTU7_CH0 = 2U, PORTD_27_FCUART6_TX = 3U, PORTD_27_FLEXCAN3_RX = 4U, PORTD_27_TPU_CH30 = 6U, } PORT_D27MuxType; /** @brief PORTD 28 Mode enumeration */ typedef enum { PORTD_28_GPIO = 1U, PORTD_28_FTU7_CH1 = 2U, PORTD_28_FCUART6_RX = 3U, PORTD_28_TPU_CH31 = 6U, PORTD_28_FCSPI5_PCS1 = 7U, } PORT_D28MuxType; /** @brief PORTD 29 Mode enumeration */ typedef enum { PORTD_29_GPIO = 1U, PORTD_29_FTU7_CH2 = 2U, PORTD_29_FCUART7_RX = 3U, PORTD_29_TPU_CH14 = 6U, } PORT_D29MuxType; /** @brief PORTD 3 Mode enumeration */ typedef enum { PORTD_3_GPIO = 1U, PORTD_3_FTU3_CH5 = 2U, PORTD_3_FCSPI1_PCS0 = 3U, PORTD_3_FCSPI5_PCS0 = 5U, PORTD_3_FTU1_CH2 = 6U, PORTD_3_TPU_CH3 = 7U, } PORT_D3MuxType; /** @brief PORTD 30 Mode enumeration */ typedef enum { PORTD_30_ADC1_SE31 = 0U, PORTD_30_GPIO = 1U, PORTD_30_FTU7_CH3 = 2U, PORTD_30_FCUART7_TX = 3U, PORTD_30_TPU_CH15 = 6U, } PORT_D30MuxType; /** @brief PORTD 31 Mode enumeration */ typedef enum { PORTD_31_ADC0_SE31 = 0U, PORTD_31_GPIO = 1U, PORTD_31_FTU7_CH4 = 2U, PORTD_31_AONTIMER0_CLK0 = 3U, PORTD_31_SENT0_RXD2 = 4U, PORTD_31_FCUART7_RX = 5U, PORTD_31_TPU_CH20 = 6U, PORTD_31_FCSPI5_PCS2 = 7U, } PORT_D31MuxType; /** @brief PORTD 4 Mode enumeration */ typedef enum { PORTD_4_ADC1_SE23 = 0U, PORTD_4_GPIO = 1U, PORTD_4_FTU_FLT16 = 2U, PORTD_4_FTU6_CH4 = 3U, PORTD_4_FCUART6_TX = 4U, PORTD_4_FCSPI5_SIN = 5U, PORTD_4_FTU1_CH3 = 6U, PORTD_4_TPU_CH4 = 7U, } PORT_D4MuxType; /** @brief PORTD 5 Mode enumeration */ typedef enum { PORTD_5_GPIO = 1U, PORTD_5_FTU2_CH3 = 2U, PORTD_5_FCUART4_TX = 3U, PORTD_5_FTU_FLT5 = 4U, PORTD_5_FTU7_CH5 = 5U, PORTD_5_TPU_CH20 = 6U, PORTD_5_FCSPI3_SIN = 7U, } PORT_D5MuxType; /** @brief PORTD 6 Mode enumeration */ typedef enum { PORTD_6_GPIO = 1U, PORTD_6_FCUART2_RX = 2U, PORTD_6_FLEXCAN3_RX = 3U, PORTD_6_FTU_FLT4 = 4U, PORTD_6_FTU2_CH4 = 5U, PORTD_6_TPU_CH21 = 6U, PORTD_6_FCSPI3_SCK = 7U, } PORT_D6MuxType; /** @brief PORTD 7 Mode enumeration */ typedef enum { PORTD_7_GPIO = 1U, PORTD_7_FCUART2_TX = 2U, PORTD_7_FLEXCAN3_TX = 3U, PORTD_7_FCSPI4_SIN = 4U, PORTD_7_FTU2_CH5 = 5U, PORTD_7_ETM_TRACE_D0 = 6U, } PORT_D7MuxType; /** @brief PORTD 8 Mode enumeration */ typedef enum { PORTD_8_CMP1_IN3 = 0U, PORTD_8_GPIO = 1U, PORTD_8_FCIIC1_SDA = 2U, PORTD_8_FTU4_CH2 = 3U, PORTD_8_FCSPI2_PCS2 = 4U, PORTD_8_FlexCore_TRST = 5U, PORTD_8_FTU1_CH4 = 6U, PORTD_8_FCUART4_RX = 7U, } PORT_D8MuxType; /** @brief PORTD 9 Mode enumeration */ typedef enum { PORTD_9_CMP1_IN2 = 0U, PORTD_9_GPIO = 1U, PORTD_9_FCIIC1_SCL = 2U, PORTD_9_FTU4_CH3 = 3U, PORTD_9_FCSPI2_PCS1 = 4U, PORTD_9_FlexCore_TDO = 5U, PORTD_9_FTU1_CH5 = 6U, PORTD_9_FCUART3_RX = 7U, } PORT_D9MuxType; /** @brief PORTE 0 Mode enumeration */ typedef enum { PORTE_0_ADC0_SE16 = 0U, PORTE_0_GPIO = 1U, PORTE_0_FCUART0_CTS = 2U, PORTE_0_FTU_TCK1 = 3U, PORTE_0_FCIIC1_SDA = 4U, PORTE_0_FCSPI0_SCK = 5U, PORTE_0_FTU_FLT19 = 6U, PORTE_0_TPU_CH11 = 7U, } PORT_E0MuxType; /** @brief PORTE 1 Mode enumeration */ typedef enum { PORTE_1_ADC0_SE17 = 0U, PORTE_1_GPIO = 1U, PORTE_1_FCUART0_RTS = 2U, PORTE_1_FCIIC1_SCL = 4U, PORTE_1_FCSPI0_SIN = 5U, PORTE_1_FTU_FLT18 = 6U, PORTE_1_TPU_CH10 = 7U, } PORT_E1MuxType; /** @brief PORTE 10 Mode enumeration */ typedef enum { PORTE_10_ADC1_SE0 = 0U, PORTE_10_GPIO = 1U, PORTE_10_FTU2_CH4 = 2U, PORTE_10_FCSPI2_PCS1 = 3U, PORTE_10_TPU_CH26 = 4U, PORTE_10_FCUART2_TX = 5U, PORTE_10_SCG_CLKOUT = 6U, PORTE_10_TRGSEL_OUT4 = 7U, } PORT_E10MuxType; /** @brief PORTE 11 Mode enumeration */ typedef enum { PORTE_11_ADC1_SE4 = 0U, PORTE_11_GPIO = 1U, PORTE_11_FTU2_CH5 = 2U, PORTE_11_FCSPI2_PCS0 = 3U, PORTE_11_TPU_CH27 = 5U, PORTE_11_TRGSEL_OUT5 = 7U, } PORT_E11MuxType; /** @brief PORTE 12 Mode enumeration */ typedef enum { PORTE_12_ADC0_SE3 = 0U, PORTE_12_GPIO = 1U, PORTE_12_FTU6_CH0 = 2U, PORTE_12_FCUART7_TX = 3U, PORTE_12_FTU_FLT2 = 4U, PORTE_12_FCSPI4_SOUT = 6U, PORTE_12_TPU_CH3 = 7U, } PORT_E12MuxType; /** @brief PORTE 13 Mode enumeration */ typedef enum { PORTE_13_ADC0_SE5 = 0U, PORTE_13_GPIO = 1U, PORTE_13_FTU4_CH5 = 2U, PORTE_13_FCSPI2_SOUT = 3U, PORTE_13_TPU_CH24 = 4U, PORTE_13_FTU3_CH3 = 5U, } PORT_E13MuxType; /** @brief PORTE 14 Mode enumeration */ typedef enum { PORTE_14_OSC32K_XTAL = 0U, PORTE_14_GPIO = 1U, PORTE_14_FTU2_CH7 = 2U, PORTE_14_FTU2_QD_PHA = 3U, PORTE_14_FTU_FLT0 = 4U, PORTE_14_FLEXCAN0_RX = 5U, PORTE_14_TPU_TCRCLK = 6U, } PORT_E14MuxType; /** @brief PORTE 15 Mode enumeration */ typedef enum { PORTE_15_ADC1_SE2 = 0U, PORTE_15_GPIO = 1U, PORTE_15_FTU2_CH6 = 2U, PORTE_15_FCSPI2_SCK = 3U, PORTE_15_TPU_CH30 = 4U, PORTE_15_FCUART1_CTS = 6U, PORTE_15_TRGSEL_OUT6 = 7U, } PORT_E15MuxType; /** @brief PORTE 16 Mode enumeration */ typedef enum { PORTE_16_ADC1_SE6 = 0U, PORTE_16_GPIO = 1U, PORTE_16_FTU2_CH7 = 2U, PORTE_16_FCSPI2_SIN = 3U, PORTE_16_TPU_CH31 = 4U, PORTE_16_FCUART1_RTS = 6U, PORTE_16_TRGSEL_OUT7 = 7U, } PORT_E16MuxType; /** @brief PORTE 17 Mode enumeration */ typedef enum { PORTE_17_GPIO = 1U, PORTE_17_FTU7_CH5 = 2U, PORTE_17_SENT0_RXD0 = 4U, PORTE_17_TPU_CH21 = 6U, PORTE_17_FCSPI5_SOUT = 7U, } PORT_E17MuxType; /** @brief PORTE 18 Mode enumeration */ typedef enum { PORTE_18_ADC0_SE27 = 0U, PORTE_18_GPIO = 1U, PORTE_18_FTU7_CH6 = 2U, PORTE_18_FTU6_CH7 = 3U, PORTE_18_SENT0_RXD1 = 4U, PORTE_18_FCUART7_TX = 5U, PORTE_18_TPU_CH22 = 6U, PORTE_18_FCSPI5_PCS3 = 7U, } PORT_E18MuxType; /** @brief PORTE 19 Mode enumeration */ typedef enum { PORTE_19_ADC0_SE23 = 0U, PORTE_19_GPIO = 1U, PORTE_19_SCG_CLKOUT = 2U, PORTE_19_FCIIC0_SCL = 3U, PORTE_19_RTC_CLKOUT = 4U, PORTE_19_FLEXCAN2_RX = 5U, PORTE_19_TPU_CH31 = 6U, } PORT_E19MuxType; /** @brief PORTE 2 Mode enumeration */ typedef enum { PORTE_2_ADC0_SE24 = 0U, PORTE_2_GPIO = 1U, PORTE_2_FTU6_CH6 = 2U, PORTE_2_AONTIMER0_CLK2 = 3U, PORTE_2_FTU3_CH6 = 4U, PORTE_2_SENT0_RXD3 = 5U, PORTE_2_FCUART1_CTS = 6U, PORTE_2_FTU1_CH7 = 7U, } PORT_E2MuxType; /** @brief PORTE 20 Mode enumeration */ typedef enum { PORTE_20_ADC0_SE22 = 0U, PORTE_20_GPIO = 1U, PORTE_20_FTU4_CH0 = 2U, PORTE_20_FCIIC0_SDA = 3U, PORTE_20_FTU1_CH3 = 4U, PORTE_20_FCSPI0_PCS0 = 5U, } PORT_E20MuxType; /** @brief PORTE 21 Mode enumeration */ typedef enum { PORTE_21_GPIO = 1U, PORTE_21_FTU4_CH1 = 2U, PORTE_21_AONTIMER0_CLK2 = 3U, PORTE_21_FLEXCAN0_TX = 4U, PORTE_21_FCUART0_RTS = 5U, } PORT_E21MuxType; /** @brief PORTE 22 Mode enumeration */ typedef enum { PORTE_22_GPIO = 1U, PORTE_22_FTU4_CH2 = 2U, PORTE_22_LP_WAKEUP0 = 3U, PORTE_22_FLEXCAN0_RX = 4U, PORTE_22_FCUART0_CTS = 5U, } PORT_E22MuxType; /** @brief PORTE 23 Mode enumeration */ typedef enum { PORTE_23_ADC0_SE19 = 0U, PORTE_23_GPIO = 1U, PORTE_23_FTU4_CH3 = 2U, PORTE_23_FCUART0_TX = 3U, PORTE_23_TPU_CH26 = 4U, PORTE_23_FCSPI0_PCS3 = 5U, PORTE_23_LP_WAKEUP1 = 6U, } PORT_E23MuxType; /** @brief PORTE 24 Mode enumeration */ typedef enum { PORTE_24_ADC0_SE18 = 0U, PORTE_24_GPIO = 1U, PORTE_24_FTU4_CH4 = 2U, PORTE_24_FLEXCAN2_TX = 3U, PORTE_24_TPU_CH27 = 4U, PORTE_24_FCSPI0_PCS2 = 5U, } PORT_E24MuxType; /** @brief PORTE 25 Mode enumeration */ typedef enum { PORTE_25_DEBUGMUX_P0 = 0U, PORTE_25_GPIO = 1U, PORTE_25_FTU4_CH5 = 2U, PORTE_25_FCUART0_RX = 3U, PORTE_25_TPU_CH28 = 4U, PORTE_25_FCSPI0_PCS1 = 5U, } PORT_E25MuxType; /** @brief PORTE 26 Mode enumeration */ typedef enum { PORTE_26_GPIO = 1U, PORTE_26_FTU4_CH6 = 2U, PORTE_26_LP_WAKEUP3 = 3U, PORTE_26_FTU1_CH2 = 4U, PORTE_26_FCUART1_TX = 5U, PORTE_26_TPU_CH23 = 6U, } PORT_E26MuxType; /** @brief PORTE 27 Mode enumeration */ typedef enum { PORTE_27_GPIO = 1U, PORTE_27_FTU4_CH7 = 2U, PORTE_27_FLEXCAN2_RX = 3U, PORTE_27_FTU1_CH0 = 4U, PORTE_27_FCUART1_RX = 5U, PORTE_27_TPU_CH24 = 6U, } PORT_E27MuxType; /** @brief PORTE 29 Mode enumeration */ typedef enum { PORTE_29_GPIO = 1U, PORTE_29_FTU2_CH0 = 2U, PORTE_29_RTC_CLKOUT = 3U, PORTE_29_FTU1_CH1 = 4U, PORTE_29_FLEXCAN2_TX = 5U, PORTE_29_FTU2_QD_PHA = 6U, PORTE_29_TPU_CH25 = 7U, } PORT_E29MuxType; /** @brief PORTE 3 Mode enumeration */ typedef enum { PORTE_3_OSC32K_EXTAL = 0U, PORTE_3_GPIO = 1U, PORTE_3_FTU2_CH6 = 2U, PORTE_3_FCUART2_RX = 3U, PORTE_3_FTU_FLT1 = 4U, PORTE_3_FTU2_QD_PHB = 5U, PORTE_3_FTU_TCK0 = 6U, } PORT_E3MuxType; /** @brief PORTE 4 Mode enumeration */ typedef enum { PORTE_4_ADC0_SE4 = 0U, PORTE_4_GPIO = 1U, PORTE_4_FTU6_CH0 = 2U, PORTE_4_FTU2_QD_PHB = 3U, PORTE_4_FCSPI1_PCS0 = 4U, PORTE_4_FTU2_CH2 = 5U, PORTE_4_ETM_TRACE_D1 = 6U, PORTE_4_TPU_CH22 = 7U, } PORT_E4MuxType; /** @brief PORTE 5 Mode enumeration */ typedef enum { PORTE_5_ADC0_SE1 = 0U, PORTE_5_GPIO = 1U, PORTE_5_FTU_TCK2 = 2U, PORTE_5_FTU2_QD_PHA = 3U, PORTE_5_FCSPI1_SOUT = 4U, PORTE_5_FTU2_CH3 = 5U, PORTE_5_TPU_CH23 = 6U, } PORT_E5MuxType; /** @brief PORTE 6 Mode enumeration */ typedef enum { PORTE_6_ADC0_SE25 = 0U, PORTE_6_GPIO = 1U, PORTE_6_FTU7_CH7 = 2U, PORTE_6_FTU6_CH3 = 3U, PORTE_6_FTU3_CH7 = 4U, PORTE_6_SENT0_RXD2 = 5U, PORTE_6_FCUART1_RTS = 6U, PORTE_6_TPU_CH6 = 7U, } PORT_E6MuxType; /** @brief PORTE 7 Mode enumeration */ typedef enum { PORTE_7_ADC1_SE8 = 0U, PORTE_7_GPIO = 1U, PORTE_7_FTU0_CH7 = 2U, PORTE_7_FTU_FLT14 = 3U, PORTE_7_FTU5_CH6 = 4U, PORTE_7_TRGSEL_OUT3 = 5U, PORTE_7_SENT0_RXD3 = 6U, PORTE_7_MSC0_SDI3 = 7U, } PORT_E7MuxType; /** @brief PORTE 8 Mode enumeration */ typedef enum { PORTE_8_GPIO = 1U, PORTE_8_FTU0_CH6 = 2U, PORTE_8_FCSPI4_SCK = 4U, PORTE_8_FTU7_CH7 = 5U, PORTE_8_ETM_TRACE_D4 = 6U, PORTE_8_FCSPI0_PCS3 = 7U, } PORT_E8MuxType; /** @brief PORTE 9 Mode enumeration */ typedef enum { PORTE_9_ADC0_SE12_CMP0_IN2 = 0U, PORTE_9_GPIO = 1U, PORTE_9_FTU0_CH7 = 2U, PORTE_9_FCUART2_CTS = 3U, PORTE_9_TPU_CH17 = 4U, PORTE_9_ETM_TRACE_CLKOUT = 6U, PORTE_9_FCSPI0_PCS0 = 7U, } PORT_E9MuxType; /** @brief Port Pin Mux structure */ typedef union { PORT_A0MuxType ePortA0Mode; PORT_A1MuxType ePortA1Mode; PORT_A2MuxType ePortA2Mode; PORT_A3MuxType ePortA3Mode; PORT_A4MuxType ePortA4Mode; PORT_A6MuxType ePortA6Mode; PORT_A7MuxType ePortA7Mode; PORT_A8MuxType ePortA8Mode; PORT_A9MuxType ePortA9Mode; PORT_A10MuxType ePortA10Mode; PORT_A11MuxType ePortA11Mode; PORT_A12MuxType ePortA12Mode; PORT_A13MuxType ePortA13Mode; PORT_A14MuxType ePortA14Mode; PORT_A15MuxType ePortA15Mode; PORT_A16MuxType ePortA16Mode; PORT_A17MuxType ePortA17Mode; PORT_A18MuxType ePortA18Mode; PORT_A19MuxType ePortA19Mode; PORT_A20MuxType ePortA20Mode; PORT_A21MuxType ePortA21Mode; PORT_A23MuxType ePortA23Mode; PORT_A24MuxType ePortA24Mode; PORT_A25MuxType ePortA25Mode; PORT_A26MuxType ePortA26Mode; PORT_A27MuxType ePortA27Mode; PORT_A28MuxType ePortA28Mode; PORT_A29MuxType ePortA29Mode; PORT_A30MuxType ePortA30Mode; PORT_A31MuxType ePortA31Mode; PORT_B0MuxType ePortB0Mode; PORT_B1MuxType ePortB1Mode; PORT_B3MuxType ePortB3Mode; PORT_B4MuxType ePortB4Mode; PORT_B5MuxType ePortB5Mode; PORT_B6MuxType ePortB6Mode; PORT_B7MuxType ePortB7Mode; PORT_B8MuxType ePortB8Mode; PORT_B9MuxType ePortB9Mode; PORT_B10MuxType ePortB10Mode; PORT_B11MuxType ePortB11Mode; PORT_B12MuxType ePortB12Mode; PORT_B13MuxType ePortB13Mode; PORT_B14MuxType ePortB14Mode; PORT_B15MuxType ePortB15Mode; PORT_B16MuxType ePortB16Mode; PORT_B17MuxType ePortB17Mode; PORT_B18MuxType ePortB18Mode; PORT_B19MuxType ePortB19Mode; PORT_B20MuxType ePortB20Mode; PORT_B21MuxType ePortB21Mode; PORT_B22MuxType ePortB22Mode; PORT_B23MuxType ePortB23Mode; PORT_B24MuxType ePortB24Mode; PORT_B25MuxType ePortB25Mode; PORT_B26MuxType ePortB26Mode; PORT_B27MuxType ePortB27Mode; PORT_B28MuxType ePortB28Mode; PORT_B29MuxType ePortB29Mode; PORT_B30MuxType ePortB30Mode; PORT_B31MuxType ePortB31Mode; PORT_C0MuxType ePortC0Mode; PORT_C1MuxType ePortC1Mode; PORT_C2MuxType ePortC2Mode; PORT_C3MuxType ePortC3Mode; PORT_C4MuxType ePortC4Mode; PORT_C5MuxType ePortC5Mode; PORT_C6MuxType ePortC6Mode; PORT_C7MuxType ePortC7Mode; PORT_C8MuxType ePortC8Mode; PORT_C9MuxType ePortC9Mode; PORT_C10MuxType ePortC10Mode; PORT_C11MuxType ePortC11Mode; PORT_C12MuxType ePortC12Mode; PORT_C13MuxType ePortC13Mode; PORT_C14MuxType ePortC14Mode; PORT_C15MuxType ePortC15Mode; PORT_C16MuxType ePortC16Mode; PORT_C17MuxType ePortC17Mode; PORT_C18MuxType ePortC18Mode; PORT_C19MuxType ePortC19Mode; PORT_C20MuxType ePortC20Mode; PORT_C21MuxType ePortC21Mode; PORT_C22MuxType ePortC22Mode; PORT_C23MuxType ePortC23Mode; PORT_C24MuxType ePortC24Mode; PORT_C25MuxType ePortC25Mode; PORT_C26MuxType ePortC26Mode; PORT_C27MuxType ePortC27Mode; PORT_C28MuxType ePortC28Mode; PORT_C29MuxType ePortC29Mode; PORT_C30MuxType ePortC30Mode; PORT_C31MuxType ePortC31Mode; PORT_D0MuxType ePortD0Mode; PORT_D1MuxType ePortD1Mode; PORT_D2MuxType ePortD2Mode; PORT_D3MuxType ePortD3Mode; PORT_D4MuxType ePortD4Mode; PORT_D5MuxType ePortD5Mode; PORT_D6MuxType ePortD6Mode; PORT_D7MuxType ePortD7Mode; PORT_D8MuxType ePortD8Mode; PORT_D9MuxType ePortD9Mode; PORT_D10MuxType ePortD10Mode; PORT_D11MuxType ePortD11Mode; PORT_D12MuxType ePortD12Mode; PORT_D13MuxType ePortD13Mode; PORT_D15MuxType ePortD15Mode; PORT_D16MuxType ePortD16Mode; PORT_D17MuxType ePortD17Mode; PORT_D18MuxType ePortD18Mode; PORT_D19MuxType ePortD19Mode; PORT_D20MuxType ePortD20Mode; PORT_D21MuxType ePortD21Mode; PORT_D22MuxType ePortD22Mode; PORT_D23MuxType ePortD23Mode; PORT_D24MuxType ePortD24Mode; PORT_D25MuxType ePortD25Mode; PORT_D26MuxType ePortD26Mode; PORT_D27MuxType ePortD27Mode; PORT_D28MuxType ePortD28Mode; PORT_D29MuxType ePortD29Mode; PORT_D30MuxType ePortD30Mode; PORT_D31MuxType ePortD31Mode; PORT_E0MuxType ePortE0Mode; PORT_E1MuxType ePortE1Mode; PORT_E2MuxType ePortE2Mode; PORT_E3MuxType ePortE3Mode; PORT_E4MuxType ePortE4Mode; PORT_E5MuxType ePortE5Mode; PORT_E6MuxType ePortE6Mode; PORT_E7MuxType ePortE7Mode; PORT_E8MuxType ePortE8Mode; PORT_E9MuxType ePortE9Mode; PORT_E10MuxType ePortE10Mode; PORT_E11MuxType ePortE11Mode; PORT_E12MuxType ePortE12Mode; PORT_E13MuxType ePortE13Mode; PORT_E14MuxType ePortE14Mode; PORT_E15MuxType ePortE15Mode; PORT_E16MuxType ePortE16Mode; PORT_E17MuxType ePortE17Mode; PORT_E18MuxType ePortE18Mode; PORT_E19MuxType ePortE19Mode; PORT_E20MuxType ePortE20Mode; PORT_E21MuxType ePortE21Mode; PORT_E22MuxType ePortE22Mode; PORT_E23MuxType ePortE23Mode; PORT_E24MuxType ePortE24Mode; PORT_E25MuxType ePortE25Mode; PORT_E26MuxType ePortE26Mode; PORT_E27MuxType ePortE27Mode; PORT_E29MuxType ePortE29Mode; Port_PinModeType u32PortPinMode; } Port_PinMuxType; /** @brief Port interrupt configuration */ typedef enum { PORT_IRQ_DISABLE = 0U, PORT_IRQ_LOGIC_0 = 8U, PORT_IRQ_RISING = 9U, PORT_IRQ_FALLING = 10U, PORT_IRQ_BOTH_EDGE = 11U, PORT_IRQ_LOGIC_1 = 12U } PORT_IntConfigType; /** @brief Port DMA request configuration */ typedef enum { PORT_DMA_REQ_DISABLE = 0U, PORT_DMA_REQ_RISING = 1U, PORT_DMA_REQ_FALLING = 2U, PORT_DMA_REQ_BOTH_EDGE = 3U, } PORT_DMAReqType; /** @brief Port digital filter clock source */ typedef enum { PORT_FILTER_BUS_CLK = 0U, PORT_FILTER_AON32K_CLK, } PORT_DigitalFilterClkSrcType; /** @brief Port pull status */ typedef enum { PORT_PULL_DOWN = 0U, PORT_PULL_UP } PORT_PullStatusType; /********* Local inline function ************/ /** * @brief Configure pin * * @param pPort Port instance * @param u8Pin Pin number * @param u32PcrReg Pin PCR register value */ LOCAL_INLINE void PORT_HWA_ConfigPin(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32PcrReg) { pPort->PCR[u8Pin] = u32PcrReg; } /** * @brief Configure Pin Domain Write Protection * * @param pPort Port instance * @param u8Pin Pin number * @param u32DwpValue Bit field value:Domain Write Protection */ LOCAL_INLINE void PORT_HWA_SelPinRegWrtPermit(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32DwpValue) { uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); pPort->PCR[u8Pin] = (u32TempRegVal & (~ (uint32_t)PORT_PCR_DWP_MASK)) | PORT_PCR_DWP(u32DwpValue); } /** * @brief Configure Pin Domain Write Protection Lock * * @param pPort Port instance * @param u8Pin Pin number * @param bEnable Enable or Disable DWP Lock */ LOCAL_INLINE void PORT_HWA_ConfigPinDwpLock(PORT_Type *pPort, uint8_t u8Pin, bool bEnable) { uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); pPort->PCR[u8Pin] = (u32TempRegVal & (~ (uint32_t)PORT_PCR_DWPLK_MASK)) | PORT_PCR_DWPLK(bEnable); } /** * @brief Configure Pin Emergency Stop * * @param pPort Port instance * @param u8Pin Pin number * @param bEnable Enable or Disable Emergency Stop of this Pin */ LOCAL_INLINE void PORT_HWA_CfgPinEmgcyStop(PORT_Type *pPort, uint8_t u8Pin, bool bEnable) { uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); pPort->PCR[u8Pin] = (u32TempRegVal & (~ (uint32_t)PORT_PCR_ESTOP_MASK)) | PORT_PCR_ESTOP(bEnable); } /** * @brief Configure Global Domain Write Protection Lock * * @param pPort Port instance * @param u8Pin Pin number * @param bEnable Enable or Disable Global DWP Lock */ LOCAL_INLINE void PORT_HWA_CfgGlobalDwpLock(PORT_Type *pPort, bool bEnable) { uint32_t u32TempRegVal = (uint32_t)(pPort->GLDWP); pPort->GLDWP = (u32TempRegVal & (~ (uint32_t)PORT_GLDWP_DWPLK_MASK)) | PORT_GLDWP_DWPLK(bEnable); } /** * @brief Configure Global Domain Write Protection * * @param pPort Port instance * @param u8Pin Pin number * @param u32GlbDwpValue Bit field value:Global Domain Write Protection */ LOCAL_INLINE void PORT_HWA_CfgGlobalRegWrtPermit(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32GlbDwpValue) { uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); pPort->GLDWP = (u32TempRegVal & (~ (uint32_t)PORT_GLDWP_DWP_MASK)) | PORT_GLDWP_DWP(u32GlbDwpValue); } /** * @brief Read pin interrupt flag * * @param pPort Port instance * @param u8Pin Pin number * @return interrupt flag value */ LOCAL_INLINE bool PORT_HWA_ReadPinInterruptFlag(PORT_Type *pPort, uint8_t u8Pin) { return (bool)(pPort->PCR[u8Pin] & (uint32_t)PORT_PCR_ISF_MASK); } /** * @brief Set pin multiplexing * * @param pPort Port instance * @param u8Pin Pin number * @param Port_PinMuxType Pin MXU configuration value */ LOCAL_INLINE void PORT_HWA_SetPinMux(PORT_Type *pPort, uint8_t u8Pin, Port_PinMuxType u32PinMux) { uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_MUX_MASK) | PORT_PCR_MUX(u32PinMux.u32PortPinMode)); } /** * @brief Set pin interrupt mode * * @param pPort Port instance * @param u8Pin Pin number * @param u32PinIrqc Pin IRQC configuration value */ LOCAL_INLINE void PORT_HWA_SetPinInterruptMode(PORT_Type *pPort, uint8_t u8Pin, PORT_IntConfigType u32PinIrqc) { uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(u32PinIrqc)); } /** * @brief Set pin DMA request mode * * @param pPort Port instance * @param u8Pin Pin number * @param u32DMAReqMode Pin DMA request mode */ LOCAL_INLINE void PORT_HWA_SetPinDMAReqMode(PORT_Type *pPort, uint8_t u8Pin, PORT_DMAReqType u32DMAReqMode) { uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(u32DMAReqMode)); } /** * @brief Set pin pull enable * * @param pPort Port instance * @param u8Pin Pin number * @param u8PeValue Pin PE configuration value(1/0) */ LOCAL_INLINE void PORT_HWA_SetPinPullEnable(PORT_Type *pPort, uint8_t u8Pin, bool bPullEnable) { if (bPullEnable) { pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_PE_MASK; } else { pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_PE_MASK; } } /** * @brief Set pin pull mode * * @param pPort Port instance * @param u8Pin Pin number * @param u8PsValue Pin PS configuration value(1/0) */ LOCAL_INLINE void PORT_HWA_SetPinPullMode(PORT_Type *pPort, uint8_t u8Pin, PORT_PullStatusType u8PullSelect) { uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_PS_MASK) | PORT_PCR_PS(u8PullSelect)); } /** * @brief Set pin drive strength 0 * * @param pPort Port instance * @param u8Pin Pin number * @note only hs PAD use this bit */ LOCAL_INLINE void PORT_HWA_EnablePinDriveStrength0(PORT_Type *pPort, uint8_t u8Pin) { pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_DSE0_MASK; } /** * @brief Set pin drive strength 1 * * @param pPort Port instance * @param u8Pin Pin number * @note only UHS PAD use this bit */ LOCAL_INLINE void PORT_HWA_EnablePinDriveStrength1(PORT_Type *pPort, uint8_t u8Pin) { pPort->PCR[u8Pin] |= (uint32_t)(PORT_PCR_DSE1_MASK | PORT_PCR_DSE0_MASK); } /** * @brief Set pin passive filter enable * * @param pPort Port instance * @param u8Pin Pin number * @param u8PfeValue Pin PFE configuration value(1/0) */ LOCAL_INLINE void PORT_HWA_SetPinPassiveFilterEnable(PORT_Type *pPort, uint8_t u8Pin, bool bPfEable) { if (bPfEable) { pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_PFE_MASK; } else { pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_PFE_MASK; } } /** * @brief Configure port digital filter * * @param pPort Port instance * @param u32RegValue Enable bit,0-31 bit indicate pin 0-31 */ LOCAL_INLINE void PORT_HWA_ConfigDigitalFilter(PORT_Type *pPort, uint32_t u32RegValue) { pPort->DFER = u32RegValue; } /** * @brief Set port digital filter enable * * @param pPort Port instance * @param u8RegBit DFER register bit */ LOCAL_INLINE void PORT_HWA_SetDigitalFilterEnable(PORT_Type *pPort, uint8_t u8RegBit) { pPort->DFER |= (uint32_t)1 << u8RegBit; } /** * @brief Set port digital filter clock source * * @param pPort Port instance * @param eClkSrc Digital filter clock source */ LOCAL_INLINE void PORT_HWA_SetDigitalFilterClkSrc(PORT_Type *pPort, PORT_DigitalFilterClkSrcType eClkSrc) { pPort->DFCR |= PORT_DFCR_CS(eClkSrc); } /** * @brief Configure digital filter width * @param pPort Port instance * @param u32FilterWidth Digital filter length value,range:0-31 */ LOCAL_INLINE void PORT_HWA_ConfigDigitalFilterWidth(PORT_Type *pPort, uint32_t u32FilterWidth) { pPort->DFWR = PORT_DFWR_FILT(u32FilterWidth); } /** * @brief Clear pin interrupt mode * * @param pPort Port instance * @param u8Pin Pin number */ LOCAL_INLINE void PORT_HWA_ClearPinInterruptMode(PORT_Type *pPort, uint8_t u8Pin) { pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_IRQC_MASK; } /** * @brief Clear pin interrupt flag * * @param pPort Port instance * @param u8Pin Pin number */ LOCAL_INLINE void PORT_HWA_ClearPinInterruptFlag(PORT_Type *pPort, uint8_t u8Pin) { pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_ISF_MASK; } /** * @brief CLear port digital filter enable * * @param pPort Port instance */ LOCAL_INLINE void PORT_HWA_ClearDigitalFilterEnable(PORT_Type *pPort) { pPort->DFER = (uint32_t)0U; } /** * @brief Clear port digital filter enable for specific pin * * @param pPort Port instance * @param u8RegBit DFER register bit */ LOCAL_INLINE void PORT_HWA_ClearDigitalFilterPin(PORT_Type *pPort, uint8_t u8RegBit) { pPort->DFER &= (uint32_t)~((uint32_t)1 << u8RegBit); } /** * @brief Clear port digital filter clock source * * @param pPort Port instance */ LOCAL_INLINE void PORT_HWA_ClearDigitalFilterClkSrc(PORT_Type *pPort) { pPort->DFCR &= ~(uint32_t)PORT_DFCR_CS_MASK; } /** * @brief Clear port digital filter width * * @param pPort Port instance */ LOCAL_INLINE void PORT_HWA_ClearDigitalFilterWidth(PORT_Type *pPort) { pPort->DFWR &= ~(uint32_t)PORT_DFWR_FILT_MASK; } /** * @brief Write Global Pin Control Low Register( Write Regvalue to bits[15:0] of PCR0 ~ 15 ) * * @param pPort Port instance * @param u32Pin Port pin number * @param u32LowPcrRegValue Register value in bits[15:0] of PCR0 ~ 15 */ LOCAL_INLINE void PORT_HWA_WriteGPCLR(PORT_Type *pPort,uint32_t u32Pin,uint32_t u32LowPcrRegValue) { pPort->GPCLR = PORT_GPCLR_GPWE(u32Pin) | PORT_GPCLR_GPWD(u32LowPcrRegValue); } /** * @brief Write Global Pin Control High Register( Write Regvalue to bits[15:0] of PCR16 ~ 31 ) * * @param pPort Port instance * @param u32Pin Port pin number * @param u32LowPcrRegValue Register value in bits[15:0] of PCR16 ~ 31 */ LOCAL_INLINE void PORT_HWA_WriteGPCHR(PORT_Type *pPort,uint32_t u32Pin,uint32_t u32LowPcrRegValue) { pPort->GPCHR = (u32Pin & PORT_GPCHR_GPWE_MASK) | PORT_GPCHR_GPWD(u32LowPcrRegValue); } /** * @brief Write Global Interrupt Control Low Register( Write Regvalue to bits[31:16] of PCR0 ~ 15 ) * * @param pPort Port instance * @param u32Pin Port pin number * @param u32HighPcrRegValue Register value in bits[31:16] of PCR0 ~ 15 */ LOCAL_INLINE void PORT_HWA_WriteGICLR(PORT_Type *pPort,uint32_t u32Pin,uint32_t u32HighPcrRegValue) { pPort->GICLR = (u32HighPcrRegValue & PORT_GICLR_GIWD_MASK) | PORT_GICLR_GIWE(u32Pin); } /** * @brief Write Global Interrupt Control High Register( Write Regvalue to bits[31:16] of PCR16 ~ 31 ) * * @param pPort Port instance * @param u32Pin Port pin number * @param u32HighPcrRegValue Register value in bits[31:16] of PCR16 ~ 31 */ LOCAL_INLINE void PORT_HWA_WriteGICHR(PORT_Type *pPort,uint32_t u32Pin,uint32_t u32HighPcrRegValue) { pPort->GICHR = (u32HighPcrRegValue & PORT_GICHR_GIWD_MASK) & PORT_GICHR_GIWE(u32Pin); } #endif /* #ifndef _HWA_PORT_H_ */