From 5d050b4ec8fdd40e145274a96941e1ab14fd764c Mon Sep 17 00:00:00 2001 From: cfif Date: Wed, 29 Oct 2025 11:17:05 +0300 Subject: [PATCH] =?UTF-8?q?=D0=9E=D0=B1=D0=BD=D0=BE=D0=B2=D0=BB=D0=B5?= =?UTF-8?q?=D0=BD=D0=B8=D0=B5?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- DataNonVolatile.c | 8 +- DataNonVolatile.h | 7 +- HVAC_preDefine.h | 24 + Rs_Cal_Base.c | 1093 +++++++++++++++++++++++++++++++++++++++++++++ Rs_Cal_Base.h | 1088 ++++++++++++++++++++++++++++++++++++++++++++ Rs_Cal_Flash.c | 42 ++ Rs_Cal_Flash.h | 38 ++ common.h | 8 + rtwtypes.h | 8 + 9 files changed, 2311 insertions(+), 5 deletions(-) create mode 100644 HVAC_preDefine.h create mode 100644 Rs_Cal_Base.c create mode 100644 Rs_Cal_Base.h create mode 100644 Rs_Cal_Flash.c create mode 100644 Rs_Cal_Flash.h create mode 100644 common.h create mode 100644 rtwtypes.h diff --git a/DataNonVolatile.c b/DataNonVolatile.c index fcb0f30..4598030 100644 --- a/DataNonVolatile.c +++ b/DataNonVolatile.c @@ -5,10 +5,14 @@ #include "DataNonVolatatile_Private.h" -void DeviceDataNonVolatile_InitDefaults(tDeviceDataNonVolatile *env) { +void DeviceDataParam_InitDefaults(tDeviceDataNonVolatile *env) { DeviceStorageInitDeviceSettings(&env->device); env->version = DEVICE_DATA_NO_VOLATILE_VERSION; -} \ No newline at end of file +} + +void DeviceDataCalib_InitDefaults(uint8_t *env) { + +} diff --git a/DataNonVolatile.h b/DataNonVolatile.h index 55f1a20..ea960d7 100644 --- a/DataNonVolatile.h +++ b/DataNonVolatile.h @@ -7,6 +7,7 @@ #include #include "DataRuntime.h" +#include "HVAC_preDefine.h" #define DEVICE_DATA_NO_VOLATILE_VERSION 0x01 @@ -73,12 +74,12 @@ typedef struct { typedef struct { uint32_t version; - tDeviceSettings device; - } tDeviceDataNonVolatile; -void DeviceDataNonVolatile_InitDefaults(tDeviceDataNonVolatile *env); +void DeviceDataParam_InitDefaults(tDeviceDataNonVolatile *env); + +void DeviceDataCalib_InitDefaults(uint8_t *env); void DeviceDataNonVolatile_AddToVarTab( tDeviceDataNonVolatile *env, diff --git a/HVAC_preDefine.h b/HVAC_preDefine.h new file mode 100644 index 0000000..dff9726 --- /dev/null +++ b/HVAC_preDefine.h @@ -0,0 +1,24 @@ +// +// Created by cfif on 08.08.2025. +// + +#ifndef SIMULINK_HVAC_PREDEFINE_H +#define SIMULINK_HVAC_PREDEFINE_H + +#include +#include + +#define SECT_SRAM_CAL __attribute__((section (".caldata"))) +#define SECT_FLASH_CAL __attribute__((section (".caltext"))) +#define SECT_SRAM_NVM __attribute__((section (".nvmdata"))) +#define tU08 uint8_t +#define tU16 uint16_t +#define tS16 int16_t +#define tS08 int8_t + +#define M_MEMCOPY(dest, src) memcpy(dest, src, sizeof(dest)) + +#define ID_TRUE 1 +#define ID_FALSE 0 + +#endif //SIMULINK_HVAC_PREDEFINE_H diff --git a/Rs_Cal_Base.c b/Rs_Cal_Base.c new file mode 100644 index 0000000..b6a9c01 --- /dev/null +++ b/Rs_Cal_Base.c @@ -0,0 +1,1093 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_Base.c + * @brief No brief + * @remark Generated by Z:\���������\��������� ������\��\Rs_Cal_R20_ver14_250521.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +/****************************************************************************** + * INCLUDE FILES + *****************************************************************************/ +#include "HVAC_preDefine.h" +#include "Rs_Cal_Base.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/*PRQA S 0615 EOF #suppress : More than 511 block scope identifiers, from Calibration data table, No impact*/ +/*PRQA S 1514 EOF #suppress : In the same translation(used != defined), from Calibration data table, No impact*/ +/*PRQA S 3408 EOF #suppress : To manage Cal. data separately, from Calibration data table, No Impact*/ +/****************************************************************************** + * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +SECT_SRAM_CAL tU08 g_ucCalFromRelease = ID_FALSE; +SECT_SRAM_CAL tU08 g_aucCAL_FP_DATE[3] = { 0}; +SECT_SRAM_CAL tU08 g_aucCAL_VERSION[2] = { 0}; +SECT_SRAM_CAL tU08 g_ucCAL_VARIANT = 0; +/* ------------------------------------------Cal Version : End*/ +SECT_SRAM_CAL tU16 g_ausSET_TEMP_FULL[13] = { 0}; +SECT_SRAM_CAL tU16 g_ausSET_TEMP_HALF[7] = { 0}; +/* ------------------------------------------Set Temp : End*/ +SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FR_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MIN_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MAX_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLU_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRU_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RR_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MIN_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MAX_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RR_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV0[7] = { 0}; +/* ------------------------------------------Lv0 : End*/ +SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FR_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MIN_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MAX_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLU_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRU_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RR_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MIN_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MAX_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RR_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV1[7] = { 0}; +/* ------------------------------------------Lv1 : End*/ +SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FR_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MIN_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MAX_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLU_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRU_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RR_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MIN_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MAX_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RR_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV2[7] = { 0}; +/* ------------------------------------------Lv2 : End*/ +SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FR_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MIN_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MAX_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLU_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRU_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RR_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MIN_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MAX_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RR_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV3[7] = { 0}; +/* ------------------------------------------Lv3 : End*/ +SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FR_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MIN_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MAX_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLU_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRU_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RR_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MIN_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MAX_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RR_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV4[7] = { 0}; +/* ------------------------------------------Lv4 : End*/ +SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FR_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MIN_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MAX_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLU_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRU_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RR_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MIN_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MAX_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RR_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV5[7] = { 0}; +/* ------------------------------------------Lv5 : End*/ +SECT_SRAM_CAL tS16 g_assDUCT_TGT_DEF_VALVE_L[11] = { 0}; +SECT_SRAM_CAL tS16 g_assDUCT_TGT_DEF_VALVE_R[11] = { 0}; +/* ------------------------------------------DuctTgt Increase : End*/ +SECT_SRAM_CAL tS16 g_assAMB_LV_UP[5] = { 0}; +SECT_SRAM_CAL tS16 g_assAMB_LV_DN[5] = { 0}; +SECT_SRAM_CAL tS16 g_assAMB_LV_TG[6] = { 0}; +/* ------------------------------------------Ambient LEVEL : End*/ +SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV0[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV1[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV2[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV3[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV4[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV5[13] = { 0}; +SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV0[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV1[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV2[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV3[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV4[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV5[7] = { 0}; +/* ------------------------------------------Mode depend on SET for each level : End*/ +SECT_SRAM_CAL tS16 g_ssPREC_REC_ON_AMB = 0; +SECT_SRAM_CAL tS16 g_ssPREC_REC_OFF_AMB = 0; +SECT_SRAM_CAL tU08 g_aucPREC_VEH_SPD_OSA[13] = { 0}; +SECT_SRAM_CAL tS16 g_assPRE_AMB_RANGE_WINTER[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_OSA_WINTER[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_REC_WINTER[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausPREC_HUMIDITY_NOK[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausPREC_HUMIDITY_OK[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausPREC_ENTRY_RPM[3] = { 0}; +SECT_SRAM_CAL tU16 g_ausPREC_EXIT_RPM[3] = { 0}; +SECT_SRAM_CAL tU16 g_ausPREC_COMP_SPD_1[3] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_OSA_SUMMER_1[3] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_REC_SUMMER_1[3] = { 0}; +SECT_SRAM_CAL tS16 g_assPREC_EVA_DIFF_FB_TG_F[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_OSA_SUMMER_2[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_REC_SUMMER_2[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_EVA_DIFF[4] = { 0}; +SECT_SRAM_CAL tU08 g_ucPREC_OSA_SUMMER_3 = 0; +SECT_SRAM_CAL tU08 g_ucPREC_REC_SUMMER_3 = 0; +/* ------------------------------------------AutoRec : End*/ +SECT_SRAM_CAL tU16 g_ausFLOW_FR_VE2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_BIVALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_BI2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE_SUMMER[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_FO2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_FD2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_DE2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_TR2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_HI2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_BIVALVE_MANUAL[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_FO2VALVE[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT_2[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE_2[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT_3[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE_3[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT_MANUAL[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE_MANUAL[6] = { 0}; +/* ------------------------------------------Flow Control Valve: End*/ +SECT_SRAM_CAL tS16 g_assFLOW_BI_AMB_TGT[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI_VENT_PLUS[12] = { 0}; +SECT_SRAM_CAL tS16 g_assFLOW_BI_TEMP_TGT[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI_FOOT_PLUS[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI_VENT_VALVE_MAX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI_FOOT_VALVE_MAX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI_VENT_VALVE_MIN[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI_FOOT_VALVE_MIN[12] = { 0}; +/* ------------------------------------------Bi 2 level conditions: End*/ +SECT_SRAM_CAL tS16 g_assFLOW_B2I_AMB_TGT[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI2_VENT_PLUS[12] = { 0}; +SECT_SRAM_CAL tS16 g_assFLOW_BI2_TEMP_TGT[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI2_FOOT_PLUS[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI2_VENT_VALVE_MAX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI2_FOOT_VALVE_MAX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI2_VENT_VALVE_MIN[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI2_FOOT_VALVE_MIN[12] = { 0}; +/* ------------------------------------------AF level conditions: End*/ +SECT_SRAM_CAL tS16 g_assFLOW_AF_AMB_TGT[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AF_VENT_PLUS[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AF_BLR_AF_TGT[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AF_FOOT_PLUS[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AF_VENT_VALVE_MAX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AF_FOOT_VALVE_MAX[12] = { 0}; +/* ------------------------------------------AF level conditions: End*/ +SECT_SRAM_CAL tS16 g_assFLOW_AFSM_AMB_TGT[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_VENT_PLUS[12] = { 0}; +SECT_SRAM_CAL tS16 g_assFLOW_AFSM_TEMP_TGT[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_FOOT_PLUS[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_VENT_VALVE_MAX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_FOOT_VALVE_MAX[12] = { 0}; +/* ------------------------------------------AF_summer level conditions: End*/ +SECT_SRAM_CAL tU08 g_aucMODE_INDEX[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_DUCT_TGT[7] = { 0}; +SECT_SRAM_CAL tS16 g_assBLR_FOOT_IND[7] = { 0}; +SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_P1[11] = { 0}; +SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_P2[11] = { 0}; +SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_P3[11] = { 0}; +SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_M1[11] = { 0}; +SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_M2[11] = { 0}; +SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_M3[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_P1[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_P2[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_P3[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_M1[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_M2[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_M3[11] = { 0}; +/* ------------------------------------------Individual foot temperature: End*/ +SECT_SRAM_CAL tU08 g_aucREAR_FOOT_VALVE_AMB_LV2[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_FOOT_VALVE_AMB_LV3[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_FOOT_VALVE_AMB_LV4[13] = { 0}; +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ +SECT_SRAM_CAL tU16 g_ausFLOW_FR_VE2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_BIVALVE_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_BI2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_FO2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE_SUMMER_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_FD2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_DE2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_TR2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_HI2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_VE2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_FO2BLR_AF[8] = { 0}; +/* ------------------------------------------Flow Control AF: End*/ +SECT_SRAM_CAL tS08 g_ascAUTO_STEP_AF_F[5] = { 0}; +SECT_SRAM_CAL tS08 g_ascAUTO_STEP_AF_R[5] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_U_F_LV0_1[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_U_F_LV2_3[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_U_F_LV4_5[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_L_F_LV0_1[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_L_F_LV2_3[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_L_F_LV4_5[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_R_LV0_1[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_R_LV2_3[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_R_LV4_5[10] = { 0}; +/* ------------------------------------------5 AUTO mode: End*/ +SECT_SRAM_CAL tU16 g_ausVALVE_SPACE[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_SIDE_VENT[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_CENT_VENT[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_DRIVER_FOOT[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_RIGHT_PASS[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_V1_1_F[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_1_F_SIDE_VENT[10] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_2_F_CENT_VENT[10] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_3_F_DRIVER_FOOT[10] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_4_F_RIGHT_PASS[13] = { 0}; +SECT_SRAM_CAL tU16 g_ausVALVE_VEH_SPD[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_SIDE_VENT[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_SIDE_BI[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_SIDE_AFOOT[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_CNET_VENT[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_CENT_BI[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_CENT_AFOOT[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_FOOT_BI[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_FOOT_AFOOT[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_2FOOT[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_VEH_SPD_V1_3[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFRONT_SIDE_DRS_PERCENT[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFRONT_CENT_DRS_PERCENT[12] = { 0}; +/* ------------------------------------------Different blower speed FRONT MODE: End*/ +SECT_SRAM_CAL tU08 g_aucVALVE_S1_R_BIPILLAR[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_S1_R_CENT_VENT[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_S1_R_FOOT[5] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_PERC_R_BIPILLAR[10] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_PERC_R_CENT_VENT[10] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_PERC_R_FOOT[10] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_V1_1_R[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_1_R_BIPILLAR_MIN[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_2_R_CENT_VENT_MIN[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_3_R_FOOT_MIN[5] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_1_R_BIPILLAR_MAX[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_3_R_FOOTR_MAX[5] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_SIDE_DRS_PERCENT_VALVE[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_CENT_DRS_PERCENT_VALVE[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_SIDE_DRS_PERCENT_AF[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_CENT_DRS_PERCENT_AF[9] = { 0}; +/* ------------------------------------------Different blower speed REAR MODE: End*/ +SECT_SRAM_CAL tU16 g_ausMIN_PWM[2] = { 0}; +/* ------------------------------------------MinPWM: End*/ +SECT_SRAM_CAL tS16 g_assSTART_ENTER_COOLANT[6] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_ENTER_COOLANT_LV2[8] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_COOLANT_TO_STEP2[3] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_COOLANT_STEP1_BLR_F[6] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_COOLANT_STEP1_BLR_R[6] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_ENTER_INCAR[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_ENTER_SETTEMP[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_INCAR_FLT_UP[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_INCAR_FLT_DN[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_VALVE_IDX_STEP1[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_AUTODEMIST2_STEP2[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_ELEC_WINDOW[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_BLR_AF_STEP12_F[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_BLR_AF_STEP12_R[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_BLR_SPD_STEP2_F[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_BLR_SPD_STEP2_R[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_DUCT_TGT_STEP2_FX_U[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_DUCT_TGT_STEP2_FX_L[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_DUCT_TGT_STEP2_RX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_VALVE_CHANGE_SPD_F[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_VALVE_CHANGE_SPD_R[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_TIME_STEP1_TO_2[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_TIME_STEP2_TO_3[12] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_INCAR_STEP1_TO_2[12] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_INCAR_STEP2_TO_3[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_3WAY_OPEN[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_2WAY_OPEN[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_TXV_F[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_TXV_R[12] = { 0}; +/* ------------------------------------------Start control: End*/ +SECT_SRAM_CAL tS16 g_assFAILURE_AMB_TEMP[13] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_PRESSURE_LOW_HYS_UP[13] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_PRESSURE_LOW_HYS_DN[13] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_LOW_AMB_F[2] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_CUT_OFF_AMB_F[2] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_WINTER_TXV_DEWPOINT[2] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_CUT_OFF_AMB_R[2] = { 0}; +SECT_SRAM_CAL tS16 g_assEVA_TG_AMB_F[13] = { 0}; +SECT_SRAM_CAL tS16 g_assEVA_TG_AMB_R[13] = { 0}; +SECT_SRAM_CAL tU08 g_ucAC_EXTRA_RPM = 0; +SECT_SRAM_CAL tS16 g_assAC_EVA_LV_SHUT_OFF[2] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_PRESSURE_HYS_HI_ENG_ON[3] = { 0}; +SECT_SRAM_CAL tU16 g_usCMP_MAX_ENG_OFF = 0; +SECT_SRAM_CAL tU08 g_ucFAN_MAX_ENG_OFF = 0; +SECT_SRAM_CAL tS16 g_ssAC_WINTER_TXV_HYST = 0; +SECT_SRAM_CAL tU08 g_aucAC_PRESSURE_HYS_HI_ENG_OFF[2] = { 0}; +SECT_SRAM_CAL tU16 g_ausCMP_RPM_RESONANCE[6] = { 0}; +/* ------------------------------------------A/C Control Pressure : End*/ +SECT_SRAM_CAL tS16 g_assPRESSURE_TO_FAN_X[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucPRESSURE_TO_FAN_Y[7] = { 0}; +/* ------------------------------------------CoolingFan: End*/ +SECT_SRAM_CAL tS16 g_ssREST_BATT = 0; +SECT_SRAM_CAL tS16 g_ssRESTW_AMB = 0; +SECT_SRAM_CAL tS16 g_assRESTW_WATER[2] = { 0}; +SECT_SRAM_CAL tU16 g_usRESTW_READYEXPIRETIME = 0; +SECT_SRAM_CAL tU08 g_aucRESTW_MODE[2] = { 0}; +SECT_SRAM_CAL tU16 g_usRESTW_TIMEOUTTIME = 0; +SECT_SRAM_CAL tU08 g_ucRESTW_BLRSTEP = 0; +SECT_SRAM_CAL tS16 g_ssRESTS_AMB = 0; +SECT_SRAM_CAL tU08 g_uctRESTS_READYEXPIRETIME = 0; +SECT_SRAM_CAL tU08 g_aucRESTS_MODE[2] = { 0}; +SECT_SRAM_CAL tU16 g_usRESTS_TIMEOUTTIME = 0; +SECT_SRAM_CAL tU08 g_ucRESTS_BLRSTEP = 0; +/* ------------------------------------------Rest mode: End*/ +SECT_SRAM_CAL tU16 g_usFRESH_AIR_PURGE_ENTRY_TIME = 0; +SECT_SRAM_CAL tU16 g_ausFRESH_AIR_PURGE_CHANGE_TIME[7] = { 0}; +/* ------------------------------------------Purge Rec: End*/ +SECT_SRAM_CAL tS16 g_assMAX_DEF_U_DTG[10] = { 0}; +SECT_SRAM_CAL tU16 g_ausMAX_BLR_SPD[6] = { 0}; +/* ------------------------------------------MAX DEF: End*/ +SECT_SRAM_CAL tU08 g_aucAQS_REC_LV_CO[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucAQS_OSA_LV_CO[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucAQS_REC_LV_NOX[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucAQS_OSA_LV_NOX[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucAQS_REC_LV_NH3[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucAQS_OSA_LV_NH3[7] = { 0}; +SECT_SRAM_CAL tU08 g_ucAQS_REC_ON_TIME = 0; +SECT_SRAM_CAL tU08 g_aucAQS_REC_ON_WAIT[2] = { 0}; +/* ------------------------------------------Aqs: End*/ +SECT_SRAM_CAL tU16 g_usAUTODEMIST_LV2_BLR_PLUS = 0; +SECT_SRAM_CAL tU16 g_usAUTODEMIST_LV3_BLR_PLUS = 0; +SECT_SRAM_CAL tS16 g_assAUTODEMIST_OFFSET_AMB_TEMP[9] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTODEMIST_OFFSET_VENT_TEMP[9] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTODEMIST_STEP_UP[4] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTODEMIST_STEP_DN[4] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTODEMIST_WINTER[2] = { 0}; +/* ------------------------------------------Auto Demist: End*/ +SECT_SRAM_CAL tS16 g_ssAUTODEMIST_ELEC_AMB_ENTRY = 0; +SECT_SRAM_CAL tS16 g_assAUTODEMIST_ELEC_WINDSHELD_TEMP[2] = { 0}; +/* ------------------------------------------Electric AutoDemist: End*/ +SECT_SRAM_CAL tS16 g_ssAMBFILT_WATER = 0; +SECT_SRAM_CAL tU08 g_aucAMBFILT_H_CNT[2] = { 0}; +SECT_SRAM_CAL tS16 g_ssAMB_FAILSAFE = 0; +SECT_SRAM_CAL tS16 g_ssAMBKEEP_KAT = 0; +SECT_SRAM_CAL tS16 g_ssAMBKEEP_KAT_PLUS = 0; +SECT_SRAM_CAL tS16 g_ssAMBKEEP_WATER = 0; +SECT_SRAM_CAL tU08 g_aucAMBRATE_RISING[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucAMBRATE_FALLING[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucAMBRATE_RISING_DIFF[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucAMBRATE_FALLING_DIFF[8] = { 0}; +/* ------------------------------------------Ambient: End*/ +SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_F[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_F[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_DIFF_F[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_DIFF_F[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_R[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_R[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_DIFF_R[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_DIFF_R[8] = { 0}; +/* ------------------------------------------Incar: End*/ +SECT_SRAM_CAL tU16 g_ausSUNRATE_RISING[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausSUNRATE_FALLING[6] = { 0}; +/* ------------------------------------------Sun: End*/ +SECT_SRAM_CAL tU16 g_ausAMB_LV_CHANGE_UNIT[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucAMB_LV_CHANGE_SEC[6] = { 0}; +/* ------------------------------------------Level Chage: End*/ +SECT_SRAM_CAL tS16 g_ssTHREEWAY_WATER = 0; +SECT_SRAM_CAL tS16 g_assTHREEWAY_DUCT_TGT_R[2] = { 0}; +SECT_SRAM_CAL tU08 g_aucTHEREEWAY_EXPIRING[2] = { 0}; +/* ------------------------------------------Three way: End*/ +SECT_SRAM_CAL tS16 g_assTWOWAY_REAR_DUCTTGT_R[2] = { 0}; +SECT_SRAM_CAL tU08 g_aucTWOWAY_EXPIRING[2] = { 0}; +/* ------------------------------------------two-way: End*/ +SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_FL_CH0[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_FR_CH1[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_R_CH2[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_R_EX_CH2[4] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_FL_CH0[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_FR_CH1[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_R_CH2[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_R_EX_CH2[4] = { 0}; +/* ------------------------------------------Actuator Homing: End*/ +SECT_SRAM_CAL tS16 g_assHI_MODE_ENG_TMEP[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucHI_MODE_BLR_STEP_STS[6] = { 0}; +/* ------------------------------------------Hi Mode: End*/ +SECT_SRAM_CAL tU16 g_ausMinusAF_GlassPos_L[13] = { 0}; +SECT_SRAM_CAL tU16 g_ausMinusAF_GlassPos_R[13] = { 0}; +/* ------------------------------------------GlassPosition: End*/ +SECT_SRAM_CAL tS16 g_assFoot2_Lv3_Amb[6] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv4_Amb[6] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv5_Amb[6] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv3_DuctTgt_Plus[6] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv4_DuctTgt_Plus[6] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv5_DuctTgt_Plus[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFoot2_Lv1_FrontBlr_X[3] = { 0}; +SECT_SRAM_CAL tU16 g_ausFoot2_Lv1_Foot2Act_Y[3] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv2_Threshold_Diff[2] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv3_Threshold_Diff[2] = { 0}; +/* ------------------------------------------Foot2 Ctrl: End*/ +SECT_SRAM_CAL tU16 g_ausDbF_Side_Af_Bi[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Side_Af_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Side_Af_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Side_Bi_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Side_Bi_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Side_Bi2_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Cen_Af_Bi[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Cen_Af_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Cen_Af_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Cen_Bi_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Cen_Bi_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Cen_Bi2_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Foot_Af_Bi[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Foot_Af_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Foot_Af_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Foot_Bi_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Foot_Bi_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Foot_Bi2_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_AF_Af_Bi[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_AF_Af_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_AF_Af_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_AF_Bi_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_AF_Bi_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_AF_Bi2_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Af_Bi[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Af_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Af_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Bi_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Bi_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Bi2_Vent[9] = { 0}; +/* ------------------------------------------Different blower Front: End*/ +/*********************************************************Cal Table End*/ + +/****************************************************************************** + * LOCAL VARIABLES DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * LOCAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL FUNCTIONS + *****************************************************************************/ +/****************************************************************************** + * LOCAL FUNCTIONS + *****************************************************************************/ +/* End of Excel line : 1089 */ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/Rs_Cal_Base.h b/Rs_Cal_Base.h new file mode 100644 index 0000000..fb53ff6 --- /dev/null +++ b/Rs_Cal_Base.h @@ -0,0 +1,1088 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_Base.h + * @brief No brief + * @remark Generated by Z:\���������\��������� ������\��\Rs_Cal_R20_ver14_250521.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +#ifndef RS_CAL_BASE_H__ +#define RS_CAL_BASE_H__ + +/****************************************************************************** + * INCLUDE FILES +*****************************************************************************/ +#include "common.h" +#include "HVAC_preDefine.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/*PRQA S 0777 EOF #suppress : The specified number of significant characters, from Calibtaiton data table, No impact*/ +/*PRQA S 0779 EOF #suppress : The specified number of significant characters, from Calibtaiton data table, No impact*/ +/****************************************************************************** + * GLOBAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +extern SECT_SRAM_CAL tU08 g_ucCalFromRelease; +extern SECT_SRAM_CAL tU08 g_aucCAL_FP_DATE[3]; +extern SECT_SRAM_CAL tU08 g_aucCAL_VERSION[2]; +extern SECT_SRAM_CAL tU08 g_ucCAL_VARIANT; +/* ------------------------------------------Cal Version : End*/ +extern SECT_SRAM_CAL tU16 g_ausSET_TEMP_FULL[13]; +extern SECT_SRAM_CAL tU16 g_ausSET_TEMP_HALF[7]; +/* ------------------------------------------Set Temp : End*/ +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FR_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assVF_MIN_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_MAX_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLU_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRU_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RR_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assVR_MIN_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_MAX_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assTG_RL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assTG_RR_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV0[7]; +/* ------------------------------------------Lv0 : End*/ +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FR_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assVF_MIN_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_MAX_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLU_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRU_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RR_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assVR_MIN_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_MAX_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assTG_RL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assTG_RR_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV1[7]; +/* ------------------------------------------Lv1 : End*/ +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FR_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assVF_MIN_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_MAX_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLU_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRU_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RR_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assVR_MIN_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_MAX_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assTG_RL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assTG_RR_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV2[7]; +/* ------------------------------------------Lv2 : End*/ +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FR_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assVF_MIN_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_MAX_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLU_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRU_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RR_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assVR_MIN_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_MAX_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assTG_RL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assTG_RR_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV3[7]; +/* ------------------------------------------Lv3 : End*/ +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FR_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assVF_MIN_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_MAX_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLU_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRU_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RR_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assVR_MIN_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_MAX_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assTG_RL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assTG_RR_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV4[7]; +/* ------------------------------------------Lv4 : End*/ +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FR_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assVF_MIN_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_MAX_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLU_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRU_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RR_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assVR_MIN_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_MAX_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assTG_RL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assTG_RR_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV5[7]; +/* ------------------------------------------Lv5 : End*/ +extern SECT_SRAM_CAL tS16 g_assDUCT_TGT_DEF_VALVE_L[11]; +extern SECT_SRAM_CAL tS16 g_assDUCT_TGT_DEF_VALVE_R[11]; +/* ------------------------------------------DuctTgt Increase : End*/ +extern SECT_SRAM_CAL tS16 g_assAMB_LV_UP[5]; +extern SECT_SRAM_CAL tS16 g_assAMB_LV_DN[5]; +extern SECT_SRAM_CAL tS16 g_assAMB_LV_TG[6]; +/* ------------------------------------------Ambient LEVEL : End*/ +extern SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV0[13]; +extern SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV1[13]; +extern SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV2[13]; +extern SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV3[13]; +extern SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV4[13]; +extern SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV5[13]; +extern SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV0[7]; +extern SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV1[7]; +extern SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV2[7]; +extern SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV3[7]; +extern SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV4[7]; +extern SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV5[7]; +/* ------------------------------------------Mode depend on SET for each level : End*/ +extern SECT_SRAM_CAL tS16 g_ssPREC_REC_ON_AMB; +extern SECT_SRAM_CAL tS16 g_ssPREC_REC_OFF_AMB; +extern SECT_SRAM_CAL tU08 g_aucPREC_VEH_SPD_OSA[13]; +extern SECT_SRAM_CAL tS16 g_assPRE_AMB_RANGE_WINTER[7]; +extern SECT_SRAM_CAL tU08 g_aucPREC_OSA_WINTER[7]; +extern SECT_SRAM_CAL tU08 g_aucPREC_REC_WINTER[7]; +extern SECT_SRAM_CAL tU16 g_ausPREC_HUMIDITY_NOK[7]; +extern SECT_SRAM_CAL tU16 g_ausPREC_HUMIDITY_OK[7]; +extern SECT_SRAM_CAL tU16 g_ausPREC_ENTRY_RPM[3]; +extern SECT_SRAM_CAL tU16 g_ausPREC_EXIT_RPM[3]; +extern SECT_SRAM_CAL tU16 g_ausPREC_COMP_SPD_1[3]; +extern SECT_SRAM_CAL tU08 g_aucPREC_OSA_SUMMER_1[3]; +extern SECT_SRAM_CAL tU08 g_aucPREC_REC_SUMMER_1[3]; +extern SECT_SRAM_CAL tS16 g_assPREC_EVA_DIFF_FB_TG_F[7]; +extern SECT_SRAM_CAL tU08 g_aucPREC_OSA_SUMMER_2[7]; +extern SECT_SRAM_CAL tU08 g_aucPREC_REC_SUMMER_2[7]; +extern SECT_SRAM_CAL tU08 g_aucPREC_EVA_DIFF[4]; +extern SECT_SRAM_CAL tU08 g_ucPREC_OSA_SUMMER_3; +extern SECT_SRAM_CAL tU08 g_ucPREC_REC_SUMMER_3; +/* ------------------------------------------AutoRec : End*/ +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_VE2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_BIVALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_BI2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE_SUMMER[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_FO2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_FD2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_DE2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_TR2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_HI2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_BIVALVE_MANUAL[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_FO2VALVE[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT_2[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE_2[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT_3[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE_3[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT_MANUAL[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE_MANUAL[6]; +/* ------------------------------------------Flow Control Valve: End*/ +extern SECT_SRAM_CAL tS16 g_assFLOW_BI_AMB_TGT[6]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI_VENT_PLUS[12]; +extern SECT_SRAM_CAL tS16 g_assFLOW_BI_TEMP_TGT[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI_FOOT_PLUS[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI_VENT_VALVE_MAX[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI_FOOT_VALVE_MAX[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI_VENT_VALVE_MIN[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI_FOOT_VALVE_MIN[12]; +/* ------------------------------------------Bi 2 level conditions: End*/ +extern SECT_SRAM_CAL tS16 g_assFLOW_B2I_AMB_TGT[6]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI2_VENT_PLUS[12]; +extern SECT_SRAM_CAL tS16 g_assFLOW_BI2_TEMP_TGT[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI2_FOOT_PLUS[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI2_VENT_VALVE_MAX[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI2_FOOT_VALVE_MAX[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI2_VENT_VALVE_MIN[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI2_FOOT_VALVE_MIN[12]; +/* ------------------------------------------AF level conditions: End*/ +extern SECT_SRAM_CAL tS16 g_assFLOW_AF_AMB_TGT[6]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AF_VENT_PLUS[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AF_BLR_AF_TGT[6]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AF_FOOT_PLUS[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AF_VENT_VALVE_MAX[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AF_FOOT_VALVE_MAX[12]; +/* ------------------------------------------AF level conditions: End*/ +extern SECT_SRAM_CAL tS16 g_assFLOW_AFSM_AMB_TGT[6]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_VENT_PLUS[12]; +extern SECT_SRAM_CAL tS16 g_assFLOW_AFSM_TEMP_TGT[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_FOOT_PLUS[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_VENT_VALVE_MAX[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_FOOT_VALVE_MAX[12]; +/* ------------------------------------------AF_summer level conditions: End*/ +extern SECT_SRAM_CAL tU08 g_aucMODE_INDEX[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_DUCT_TGT[7]; +extern SECT_SRAM_CAL tS16 g_assBLR_FOOT_IND[7]; +extern SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_P1[11]; +extern SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_P2[11]; +extern SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_P3[11]; +extern SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_M1[11]; +extern SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_M2[11]; +extern SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_M3[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_P1[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_P2[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_P3[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_M1[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_M2[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_M3[11]; +/* ------------------------------------------Individual foot temperature: End*/ +extern SECT_SRAM_CAL tU08 g_aucREAR_FOOT_VALVE_AMB_LV2[13]; +extern SECT_SRAM_CAL tU08 g_aucREAR_FOOT_VALVE_AMB_LV3[13]; +extern SECT_SRAM_CAL tU08 g_aucREAR_FOOT_VALVE_AMB_LV4[13]; +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_VE2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_BIVALVE_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_BI2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_FO2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE_SUMMER_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_FD2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_DE2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_TR2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_HI2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_VE2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_FO2BLR_AF[8]; +/* ------------------------------------------Flow Control AF: End*/ +extern SECT_SRAM_CAL tS08 g_ascAUTO_STEP_AF_F[5]; +extern SECT_SRAM_CAL tS08 g_ascAUTO_STEP_AF_R[5]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_U_F_LV0_1[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_U_F_LV2_3[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_U_F_LV4_5[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_L_F_LV0_1[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_L_F_LV2_3[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_L_F_LV4_5[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_R_LV0_1[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_R_LV2_3[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_R_LV4_5[10]; +/* ------------------------------------------5 AUTO mode: End*/ +extern SECT_SRAM_CAL tU16 g_ausVALVE_SPACE[6]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_SIDE_VENT[9]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_CENT_VENT[9]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_DRIVER_FOOT[9]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_RIGHT_PASS[9]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_V1_1_F[7]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_1_F_SIDE_VENT[10]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_2_F_CENT_VENT[10]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_3_F_DRIVER_FOOT[10]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_4_F_RIGHT_PASS[13]; +extern SECT_SRAM_CAL tU16 g_ausVALVE_VEH_SPD[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_SIDE_VENT[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_SIDE_BI[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_SIDE_AFOOT[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_CNET_VENT[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_CENT_BI[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_CENT_AFOOT[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_FOOT_BI[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_FOOT_AFOOT[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_2FOOT[13]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_VEH_SPD_V1_3[12]; +extern SECT_SRAM_CAL tU08 g_aucFRONT_SIDE_DRS_PERCENT[12]; +extern SECT_SRAM_CAL tU08 g_aucFRONT_CENT_DRS_PERCENT[12]; +/* ------------------------------------------Different blower speed FRONT MODE: End*/ +extern SECT_SRAM_CAL tU08 g_aucVALVE_S1_R_BIPILLAR[8]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_S1_R_CENT_VENT[9]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_S1_R_FOOT[5]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_PERC_R_BIPILLAR[10]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_PERC_R_CENT_VENT[10]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_PERC_R_FOOT[10]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_V1_1_R[7]; +extern SECT_SRAM_CAL tU08 g_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO[7]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_1_R_BIPILLAR_MIN[8]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_2_R_CENT_VENT_MIN[9]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_3_R_FOOT_MIN[5]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_1_R_BIPILLAR_MAX[8]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX[9]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_3_R_FOOTR_MAX[5]; +extern SECT_SRAM_CAL tU08 g_aucREAR_SIDE_DRS_PERCENT_VALVE[9]; +extern SECT_SRAM_CAL tU08 g_aucREAR_CENT_DRS_PERCENT_VALVE[9]; +extern SECT_SRAM_CAL tU08 g_aucREAR_SIDE_DRS_PERCENT_AF[9]; +extern SECT_SRAM_CAL tU08 g_aucREAR_CENT_DRS_PERCENT_AF[9]; +/* ------------------------------------------Different blower speed REAR MODE: End*/ +extern SECT_SRAM_CAL tU16 g_ausMIN_PWM[2]; +/* ------------------------------------------MinPWM: End*/ +extern SECT_SRAM_CAL tS16 g_assSTART_ENTER_COOLANT[6]; +extern SECT_SRAM_CAL tS16 g_assSTART_ENTER_COOLANT_LV2[8]; +extern SECT_SRAM_CAL tS16 g_assSTART_COOLANT_TO_STEP2[3]; +extern SECT_SRAM_CAL tS16 g_assSTART_COOLANT_STEP1_BLR_F[6]; +extern SECT_SRAM_CAL tS16 g_assSTART_COOLANT_STEP1_BLR_R[6]; +extern SECT_SRAM_CAL tS16 g_assSTART_ENTER_INCAR[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_ENTER_SETTEMP[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_INCAR_FLT_UP[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_INCAR_FLT_DN[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_VALVE_IDX_STEP1[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_AUTODEMIST2_STEP2[6]; +extern SECT_SRAM_CAL tU08 g_aucSTART_ELEC_WINDOW[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_BLR_AF_STEP12_F[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_BLR_AF_STEP12_R[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_BLR_SPD_STEP2_F[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_BLR_SPD_STEP2_R[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_DUCT_TGT_STEP2_FX_U[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_DUCT_TGT_STEP2_FX_L[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_DUCT_TGT_STEP2_RX[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_VALVE_CHANGE_SPD_F[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_VALVE_CHANGE_SPD_R[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_TIME_STEP1_TO_2[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_TIME_STEP2_TO_3[12]; +extern SECT_SRAM_CAL tS16 g_assSTART_INCAR_STEP1_TO_2[12]; +extern SECT_SRAM_CAL tS16 g_assSTART_INCAR_STEP2_TO_3[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_3WAY_OPEN[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_2WAY_OPEN[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_TXV_F[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_TXV_R[12]; +/* ------------------------------------------Start control: End*/ +extern SECT_SRAM_CAL tS16 g_assFAILURE_AMB_TEMP[13]; +extern SECT_SRAM_CAL tS16 g_assAC_PRESSURE_LOW_HYS_UP[13]; +extern SECT_SRAM_CAL tS16 g_assAC_PRESSURE_LOW_HYS_DN[13]; +extern SECT_SRAM_CAL tS16 g_assAC_LOW_AMB_F[2]; +extern SECT_SRAM_CAL tS16 g_assAC_CUT_OFF_AMB_F[2]; +extern SECT_SRAM_CAL tS16 g_assAC_WINTER_TXV_DEWPOINT[2]; +extern SECT_SRAM_CAL tS16 g_assAC_CUT_OFF_AMB_R[2]; +extern SECT_SRAM_CAL tS16 g_assEVA_TG_AMB_F[13]; +extern SECT_SRAM_CAL tS16 g_assEVA_TG_AMB_R[13]; +extern SECT_SRAM_CAL tU08 g_ucAC_EXTRA_RPM; +extern SECT_SRAM_CAL tS16 g_assAC_EVA_LV_SHUT_OFF[2]; +extern SECT_SRAM_CAL tS16 g_assAC_PRESSURE_HYS_HI_ENG_ON[3]; +extern SECT_SRAM_CAL tU16 g_usCMP_MAX_ENG_OFF; +extern SECT_SRAM_CAL tU08 g_ucFAN_MAX_ENG_OFF; +extern SECT_SRAM_CAL tS16 g_ssAC_WINTER_TXV_HYST; +extern SECT_SRAM_CAL tU08 g_aucAC_PRESSURE_HYS_HI_ENG_OFF[2]; +extern SECT_SRAM_CAL tU16 g_ausCMP_RPM_RESONANCE[6]; +/* ------------------------------------------A/C Control Pressure : End*/ +extern SECT_SRAM_CAL tS16 g_assPRESSURE_TO_FAN_X[7]; +extern SECT_SRAM_CAL tU08 g_aucPRESSURE_TO_FAN_Y[7]; +/* ------------------------------------------CoolingFan: End*/ +extern SECT_SRAM_CAL tS16 g_ssREST_BATT; +extern SECT_SRAM_CAL tS16 g_ssRESTW_AMB; +extern SECT_SRAM_CAL tS16 g_assRESTW_WATER[2]; +extern SECT_SRAM_CAL tU16 g_usRESTW_READYEXPIRETIME; +extern SECT_SRAM_CAL tU08 g_aucRESTW_MODE[2]; +extern SECT_SRAM_CAL tU16 g_usRESTW_TIMEOUTTIME; +extern SECT_SRAM_CAL tU08 g_ucRESTW_BLRSTEP; +extern SECT_SRAM_CAL tS16 g_ssRESTS_AMB; +extern SECT_SRAM_CAL tU08 g_uctRESTS_READYEXPIRETIME; +extern SECT_SRAM_CAL tU08 g_aucRESTS_MODE[2]; +extern SECT_SRAM_CAL tU16 g_usRESTS_TIMEOUTTIME; +extern SECT_SRAM_CAL tU08 g_ucRESTS_BLRSTEP; +/* ------------------------------------------Rest mode: End*/ +extern SECT_SRAM_CAL tU16 g_usFRESH_AIR_PURGE_ENTRY_TIME; +extern SECT_SRAM_CAL tU16 g_ausFRESH_AIR_PURGE_CHANGE_TIME[7]; +/* ------------------------------------------Purge Rec: End*/ +extern SECT_SRAM_CAL tS16 g_assMAX_DEF_U_DTG[10]; +extern SECT_SRAM_CAL tU16 g_ausMAX_BLR_SPD[6]; +/* ------------------------------------------MAX DEF: End*/ +extern SECT_SRAM_CAL tU08 g_aucAQS_REC_LV_CO[8]; +extern SECT_SRAM_CAL tU08 g_aucAQS_OSA_LV_CO[7]; +extern SECT_SRAM_CAL tU08 g_aucAQS_REC_LV_NOX[8]; +extern SECT_SRAM_CAL tU08 g_aucAQS_OSA_LV_NOX[7]; +extern SECT_SRAM_CAL tU08 g_aucAQS_REC_LV_NH3[8]; +extern SECT_SRAM_CAL tU08 g_aucAQS_OSA_LV_NH3[7]; +extern SECT_SRAM_CAL tU08 g_ucAQS_REC_ON_TIME; +extern SECT_SRAM_CAL tU08 g_aucAQS_REC_ON_WAIT[2]; +/* ------------------------------------------Aqs: End*/ +extern SECT_SRAM_CAL tU16 g_usAUTODEMIST_LV2_BLR_PLUS; +extern SECT_SRAM_CAL tU16 g_usAUTODEMIST_LV3_BLR_PLUS; +extern SECT_SRAM_CAL tS16 g_assAUTODEMIST_OFFSET_AMB_TEMP[9]; +extern SECT_SRAM_CAL tS16 g_assAUTODEMIST_OFFSET_VENT_TEMP[9]; +extern SECT_SRAM_CAL tS16 g_assAUTODEMIST_STEP_UP[4]; +extern SECT_SRAM_CAL tS16 g_assAUTODEMIST_STEP_DN[4]; +extern SECT_SRAM_CAL tS16 g_assAUTODEMIST_WINTER[2]; +/* ------------------------------------------Auto Demist: End*/ +extern SECT_SRAM_CAL tS16 g_ssAUTODEMIST_ELEC_AMB_ENTRY; +extern SECT_SRAM_CAL tS16 g_assAUTODEMIST_ELEC_WINDSHELD_TEMP[2]; +/* ------------------------------------------Electric AutoDemist: End*/ +extern SECT_SRAM_CAL tS16 g_ssAMBFILT_WATER; +extern SECT_SRAM_CAL tU08 g_aucAMBFILT_H_CNT[2]; +extern SECT_SRAM_CAL tS16 g_ssAMB_FAILSAFE; +extern SECT_SRAM_CAL tS16 g_ssAMBKEEP_KAT; +extern SECT_SRAM_CAL tS16 g_ssAMBKEEP_KAT_PLUS; +extern SECT_SRAM_CAL tS16 g_ssAMBKEEP_WATER; +extern SECT_SRAM_CAL tU08 g_aucAMBRATE_RISING[6]; +extern SECT_SRAM_CAL tU08 g_aucAMBRATE_FALLING[6]; +extern SECT_SRAM_CAL tU08 g_aucAMBRATE_RISING_DIFF[8]; +extern SECT_SRAM_CAL tU08 g_aucAMBRATE_FALLING_DIFF[8]; +/* ------------------------------------------Ambient: End*/ +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_F[6]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_F[6]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_DIFF_F[8]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_DIFF_F[8]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_R[6]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_R[6]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_DIFF_R[8]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_DIFF_R[8]; +/* ------------------------------------------Incar: End*/ +extern SECT_SRAM_CAL tU16 g_ausSUNRATE_RISING[6]; +extern SECT_SRAM_CAL tU16 g_ausSUNRATE_FALLING[6]; +/* ------------------------------------------Sun: End*/ +extern SECT_SRAM_CAL tU16 g_ausAMB_LV_CHANGE_UNIT[6]; +extern SECT_SRAM_CAL tU08 g_aucAMB_LV_CHANGE_SEC[6]; +/* ------------------------------------------Level Chage: End*/ +extern SECT_SRAM_CAL tS16 g_ssTHREEWAY_WATER; +extern SECT_SRAM_CAL tS16 g_assTHREEWAY_DUCT_TGT_R[2]; +extern SECT_SRAM_CAL tU08 g_aucTHEREEWAY_EXPIRING[2]; +/* ------------------------------------------Three way: End*/ +extern SECT_SRAM_CAL tS16 g_assTWOWAY_REAR_DUCTTGT_R[2]; +extern SECT_SRAM_CAL tU08 g_aucTWOWAY_EXPIRING[2]; +/* ------------------------------------------two-way: End*/ +extern SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_FL_CH0[9]; +extern SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_FR_CH1[6]; +extern SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_R_CH2[9]; +extern SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_R_EX_CH2[4]; +extern SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_FL_CH0[9]; +extern SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_FR_CH1[6]; +extern SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_R_CH2[9]; +extern SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_R_EX_CH2[4]; +/* ------------------------------------------Actuator Homing: End*/ +extern SECT_SRAM_CAL tS16 g_assHI_MODE_ENG_TMEP[6]; +extern SECT_SRAM_CAL tU08 g_aucHI_MODE_BLR_STEP_STS[6]; +/* ------------------------------------------Hi Mode: End*/ +extern SECT_SRAM_CAL tU16 g_ausMinusAF_GlassPos_L[13]; +extern SECT_SRAM_CAL tU16 g_ausMinusAF_GlassPos_R[13]; +/* ------------------------------------------GlassPosition: End*/ +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv3_Amb[6]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv4_Amb[6]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv5_Amb[6]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv3_DuctTgt_Plus[6]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv4_DuctTgt_Plus[6]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv5_DuctTgt_Plus[6]; +extern SECT_SRAM_CAL tU16 g_ausFoot2_Lv1_FrontBlr_X[3]; +extern SECT_SRAM_CAL tU16 g_ausFoot2_Lv1_Foot2Act_Y[3]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv2_Threshold_Diff[2]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv3_Threshold_Diff[2]; +/* ------------------------------------------Foot2 Ctrl: End*/ +extern SECT_SRAM_CAL tU16 g_ausDbF_Side_Af_Bi[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Side_Af_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Side_Af_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Side_Bi_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Side_Bi_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Side_Bi2_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Cen_Af_Bi[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Cen_Af_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Cen_Af_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Cen_Bi_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Cen_Bi_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Cen_Bi2_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Foot_Af_Bi[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Foot_Af_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Foot_Af_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Foot_Bi_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Foot_Bi_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Foot_Bi2_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_AF_Af_Bi[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_AF_Af_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_AF_Af_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_AF_Bi_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_AF_Bi_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_AF_Bi2_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Af_Bi[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Af_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Af_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Bi_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Bi_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Bi2_Vent[9]; +/* ------------------------------------------Different blower Front: End*/ +/*********************************************************Cal Table End*/ + +/****************************************************************************** + * GLOBAL FUNCTIONS DECLARATIONS + *****************************************************************************/ + +/* End of Excel line : 1084 */ +#endif /*RS_CAL_BASE_H__*/ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/Rs_Cal_Flash.c b/Rs_Cal_Flash.c new file mode 100644 index 0000000..fb5ea72 --- /dev/null +++ b/Rs_Cal_Flash.c @@ -0,0 +1,42 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_1_SedanH.c + * @brief No brief + * @remark Generated by Z:\���������\��������� ������\��\Rs_Cal_R20_ver14_250521.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +/****************************************************************************** + * INCLUDE FILES + *****************************************************************************/ +#include "Rs_Cal_Flash.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/*PRQA S 0615 EOF #suppress : More than 511 block scope identifiers, from Calibration data table, No impact*/ +/*PRQA S 1514 EOF #suppress : In the same translation(used != defined), from Calibration data table, No impact*/ +/*PRQA S 3408 EOF #suppress : To manage Cal. data separately, from Calibration data table, No Impact*/ +/****************************************************************************** + * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ + +/****************************************************************************** + * LOCAL VARIABLES DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * LOCAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL FUNCTIONS + *****************************************************************************/ + +/****************************************************************************** + * LOCAL FUNCTIONS + *****************************************************************************/ +/* End of Excel line : 2153 */ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/Rs_Cal_Flash.h b/Rs_Cal_Flash.h new file mode 100644 index 0000000..275e4d7 --- /dev/null +++ b/Rs_Cal_Flash.h @@ -0,0 +1,38 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_1_SedanH.h + * @brief No brief + * @remark Generated by Z:\���������\��������� ������\��\Rs_Cal_R20_ver14_250521.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +#ifndef RS_CAL_1_SEDANH_H__ +#define RS_CAL_1_SEDANH_H__ + +/****************************************************************************** + * INCLUDE FILES +*****************************************************************************/ +#include "rtwtypes.h" +#include "HVAC_preDefine.h" +#include "common.h" +#include "Rs_Cal_Base.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ + +/****************************************************************************** + * GLOBAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +extern void Rs_Cal_1_SedanH(void); + +/* End of Excel line : 34 */ +#endif /*RS_CAL_1_SEDANH_H__*/ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/common.h b/common.h new file mode 100644 index 0000000..91ed46a --- /dev/null +++ b/common.h @@ -0,0 +1,8 @@ +// +// Created by cfif on 08.08.2025. +// + +#ifndef SIMULINK_COMMON_H +#define SIMULINK_COMMON_H + +#endif //SIMULINK_COMMON_H diff --git a/rtwtypes.h b/rtwtypes.h new file mode 100644 index 0000000..882dfce --- /dev/null +++ b/rtwtypes.h @@ -0,0 +1,8 @@ +// +// Created by cfif on 08.08.2025. +// + +#ifndef SIMULINK_RTWTYPES_H +#define SIMULINK_RTWTYPES_H + +#endif //SIMULINK_RTWTYPES_H