// // Created by cfif on 03.06.2024. // #include "CanPorts.h" #include "string.h" #include "fc7xxx_driver_port.h" #include "fc7xxx_driver_gpio.h" #include "candb.h" tCanPorts CAN_PORTS; typedef struct { uint32_t u32CanRAM[4]; } Can_RamType; #define size_aRxDataBuf 16 ALIGN(256) Can_RamType g_aRxDataBufCan0[size_aRxDataBuf]; // dma ring buffer size is 256 static void DMA_TransferCompleteCallback(void) { CanSerialPortFrameIrqRxProcessing(CAN_PORTS.Can0_IO.env, (uint32_t *) &g_aRxDataBufCan0[0]); } static void DMA_ErrorCallback(void) { while (1) { __asm("nop"); } } static void vCanPort_InitCAN0RxTxPin() { PORT_InitType tInitStruct = {0U}; GPIO_InitType tGpioInitStruct = {0}; // CAN0_STB // PortC 30: MUX = GPIO output tInitStruct.u32PortPins = PORT_PIN_30; tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; PORT_InitPins(PORT_C, &tInitStruct); tGpioInitStruct.u32GpioPins = PORT_PIN_30; tGpioInitStruct.ePinDirection = GPIO_OUT; tGpioInitStruct.ePinLevel = GPIO_LOW; GPIO_InitPins(GPIO_C, &tGpioInitStruct); // Port C2: MUX = ALT3, CAN0_RX tInitStruct.u32PortPins = PORT_PIN_2; tInitStruct.uPortPinMux.u32PortPinMode = PORTC_2_FLEXCAN0_RX; tInitStruct.bPullEn = FALSE; tInitStruct.ePullSel = PORT_PULL_UP; PORT_InitPins(PORT_C, &tInitStruct); tGpioInitStruct.u32GpioPins = PORT_PIN_2; tGpioInitStruct.ePinDirection = GPIO_IN; GPIO_InitPins((GPIO_InstanceType) PORT_C, &tGpioInitStruct); // Port C3: MUX = ALT3, CAN0_TX tInitStruct.u32PortPins = PORT_PIN_3; tInitStruct.uPortPinMux.u32PortPinMode = PORTC_3_FLEXCAN0_TX; PORT_InitPins(PORT_C, &tInitStruct); tGpioInitStruct.u32GpioPins = PORT_PIN_3; tGpioInitStruct.ePinDirection = GPIO_OUT; tGpioInitStruct.ePinLevel = GPIO_HIGH; GPIO_InitPins(GPIO_C, &tGpioInitStruct); } #define countIdCanSoftFilterCan0 31 const FilterTo_FLEXCAN_RxMbFilterType IdCanSoftFilterCan0[countIdCanSoftFilterCan0] = { {FLEXCAN_ID_STD, EMS_Veh_CANID, 0}, {FLEXCAN_ID_STD, BCM_Powertrain_CANID, 0}, {FLEXCAN_ID_STD, EMS_Veh_02_CANID, 0}, {FLEXCAN_ID_STD, BCM_EEM_CANID, 0}, {FLEXCAN_ID_STD, DMFR_Msg1_CANID, 0}, {FLEXCAN_ID_STD, DMFL_Msg1_CANID, 0}, {FLEXCAN_ID_STD, TM_Stat_CANID, 0}, {FLEXCAN_ID_STD, TM_CP_CANID, 0}, {FLEXCAN_ID_STD, HVC_CCU_Status_Msg_CANID, 0}, {FLEXCAN_ID_STD, BCM_VEH_STATE_CANID, 0}, {FLEXCAN_ID_STD, EMS_HVC_Req_Msg_CANID, 0}, {FLEXCAN_ID_STD, HVC_Err_Status_Msg_CANID, 0}, {FLEXCAN_ID_STD, BCM_CLIMATIC_DATA_CANID, 0}, {FLEXCAN_ID_STD, VCU_CCU_Req_CANID, 0}, {FLEXCAN_ID_STD, ESC_08_CANID, 0}, {FLEXCAN_ID_STD, SMFL_status_CANID, 0}, {FLEXCAN_ID_STD, SMFR_status_CANID, 0}, {FLEXCAN_ID_STD, SMRL_status_CANID, 0}, {FLEXCAN_ID_STD, SMRR_status_CANID, 0}, {FLEXCAN_ID_STD, SDM_Cmd_CANID, 0}, {FLEXCAN_ID_STD, VEH_VIN_CANID, 0}, {FLEXCAN_ID_STD, OCUFL_MSG_CANID, 0}, {FLEXCAN_ID_STD, OCUFR_MSG_CANID, 0}, {FLEXCAN_ID_STD, OCURL_MSG_CANID, 0}, {FLEXCAN_ID_STD, OCURR_MSG_CANID, 0}, {FLEXCAN_ID_STD, DW_STATE_CANID, 0}, {FLEXCAN_ID_STD, FIU_CCU1_CANID, 0}, {FLEXCAN_ID_STD, FIU_CCU2_CANID, 0}, {FLEXCAN_ID_STD, FIU_CCU3_CANID, 0}, {FLEXCAN_ID_STD, Diag_To_CCU_CANID, 1}, {FLEXCAN_ID_STD, Diag_Functional_CANID, 1}, }; #define countIdCanFilterFifoCan0 8 const FLEXCAN_RxMbFilterType IdCanFilterFifoCan0[countIdCanFilterFifoCan0] = { {FLEXCAN_ID_STD, 0x150, 0x7F8}, {FLEXCAN_ID_STD, 0x200, 0x7E0}, {FLEXCAN_ID_STD, 0x280, 0x7E0}, {FLEXCAN_ID_STD, 0x300, 0x700}, {FLEXCAN_ID_STD, 0x4D0, 0x7F0}, {FLEXCAN_ID_STD, 0x500, 0x700}, {FLEXCAN_ID_STD, Diag_To_CCU_CANID, 0xFFF}, {FLEXCAN_ID_STD, Diag_Functional_CANID, 0xFFF} }; /* uint32_t data[] = { 0x00000150, // 50 01 00 00 0x00000152, // 52 01 00 00 0x00000153, // 53 01 00 00 0x00000157, // 57 01 00 00 0x00000243, // 43 02 00 00 0x00000244, // 44 02 00 00 0x00000247, // 47 02 00 00 0x0000024C, // 4C 02 00 00 0x0000025A, // 5A 02 00 00 0x00000280, // 80 02 00 00 0x00000298, // 98 02 00 00 0x00000305, // 05 03 00 00 0x00000365, // 65 03 00 00 0x0000039D, // 9D 03 00 00 0x000003C1, // C1 03 00 00 0x000004D0, // D0 04 00 00 0x000004D1, // D1 04 00 00 0x000004D2, // D2 04 00 00 0x000004D3, // D3 04 00 00 0x0000050F, // 0F 05 00 00 0x0000051A, // 1A 05 00 00 0x00000521, // 21 05 00 00 0x00000522, // 22 05 00 00 0x00000523, // 23 05 00 00 0x00000524, // 24 05 00 00 0x00000589, // 89 05 00 00 0x000005A1, // A1 05 00 00 0x000005A2, // A2 05 00 00 0x000005A3 // A3 05 00 00 }; */ static void vCanPort_InitCan0() { vCanPort_InitCAN0RxTxPin(); /* uint32_t z[31]; uint32_t mask = 0; for (uint8_t i=0; i<29; ++i) { z[i] = IdCanSoftFilterCan0[i].u32RxCanId; mask |= z[i]; } */ vCanSerialPortFrameDMAInit( &CAN_PORTS.Can0, FLEXCAN0, 0, // CAN0 = 0 ... CAN3 = 3 FlexCAN0_IRQn, // // FlexCAN0_IRQn ... FlexCAN3_IRQn 0xFF, DMA_CHANNEL_1, DMA_REQ_FLEXCAN0, (uint8_t *) &g_aRxDataBufCan0[0], size_aRxDataBuf, IdCanSoftFilterCan0, countIdCanSoftFilterCan0, IdCanFilterFifoCan0, countIdCanFilterFifoCan0, DMA1_IRQn, 0xFF, DMA1_IRQn, FLEXCAN_BAUD_500K, FLEXCAN_ID_STD, 0x55, NULL, NULL, NULL, NULL, DMA_TransferCompleteCallback, DMA_ErrorCallback ); } void CanPorts_Init() { CAN_PORTS.Can0.reInit = false; vCanPort_InitCan0(); CAN_PORTS.Can0_IO = CanPortFrame_GetIo(&CAN_PORTS.Can0); } void CAN0_IRQHandler(void) { FLEXCAN_IRQHandler(0U); } void CAN1_IRQHandler(void) { FLEXCAN_IRQHandler(1U); } void CAN2_IRQHandler(void) { FLEXCAN_IRQHandler(2U); } void CAN3_IRQHandler(void) { FLEXCAN_IRQHandler(3U); }